projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'gpio-v4.6-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux...
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
52004014
FW		 126static bool __read_mostly vector_hashing = true;
127module_param(vector_hashing, bool, S_IRUGO);
128
893590c7 129static bool __read_mostly backwards_tsc_observed = false;
16a96021 130
18863bdd
AK		 131#define KVM_NR_SHARED_MSRS 16
132
133struct kvm_shared_msrs_global {
134 int nr;
2bf78fa7 135 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 136};
137
138struct kvm_shared_msrs {
139 struct user_return_notifier urn;
140 bool registered;
2bf78fa7
SY		 141 struct kvm_shared_msr_values {
142 u64 host;
143 u64 curr;
144 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 145};
146
147static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 148static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 149
417bc304 150struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 161 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 164 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 165 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 166 { "request_irq", VCPU_STAT(request_irq_exits) },
167 { "irq_exits", VCPU_STAT(irq_exits) },
168 { "host_state_reload", VCPU_STAT(host_state_reload) },
169 { "efer_reload", VCPU_STAT(efer_reload) },
170 { "fpu_reload", VCPU_STAT(fpu_reload) },
171 { "insn_emulation", VCPU_STAT(insn_emulation) },
172 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 173 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 174 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 175 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
176 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
177 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
178 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
179 { "mmu_flooded", VM_STAT(mmu_flooded) },
180 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 181 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 182 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 183 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 184 { "largepages", VM_STAT(lpages) },
417bc304
HB		 185 { NULL }
186};
187
2acf923e
DC		 188u64 __read_mostly host_xcr0;
189
b6785def 190static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 191
af585b92
GN		 192static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
193{
194 int i;
195 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
196 vcpu->arch.apf.gfns[i] = ~0;
197}
198
18863bdd
AK		 199static void kvm_on_user_return(struct user_return_notifier *urn)
200{
201 unsigned slot;
18863bdd
AK		 202 struct kvm_shared_msrs *locals
203 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 204 struct kvm_shared_msr_values *values;
18863bdd
AK		 205
206 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 207 values = &locals->values[slot];
208 if (values->host != values->curr) {
209 wrmsrl(shared_msrs_global.msrs[slot], values->host);
210 values->curr = values->host;
18863bdd
AK		 211 }
212 }
213 locals->registered = false;
214 user_return_notifier_unregister(urn);
215}
216
2bf78fa7 217static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 218{
18863bdd 219 u64 value;
013f6a5d
MT		 220 unsigned int cpu = smp_processor_id();
221 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 222
2bf78fa7
SY		 223 /* only read, and nobody should modify it at this time,
224 * so don't need lock */
225 if (slot >= shared_msrs_global.nr) {
226 printk(KERN_ERR "kvm: invalid MSR slot!");
227 return;
228 }
229 rdmsrl_safe(msr, &value);
230 smsr->values[slot].host = value;
231 smsr->values[slot].curr = value;
232}
233
234void kvm_define_shared_msr(unsigned slot, u32 msr)
235{
0123be42 236 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 237 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 238 if (slot >= shared_msrs_global.nr)
239 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 240}
241EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
242
243static void kvm_shared_msr_cpu_online(void)
244{
245 unsigned i;
18863bdd
AK		 246
247 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 248 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 249}
250
8b3c3104 251int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 252{
013f6a5d
MT		 253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 255 int err;
18863bdd 256
2bf78fa7 257 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 258 return 0;
2bf78fa7 259 smsr->values[slot].curr = value;
8b3c3104
AH		 260 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
261 if (err)
262 return 1;
263
18863bdd
AK		 264 if (!smsr->registered) {
265 smsr->urn.on_user_return = kvm_on_user_return;
266 user_return_notifier_register(&smsr->urn);
267 smsr->registered = true;
268 }
8b3c3104 269 return 0;
18863bdd
AK		 270}
271EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
272
13a34e06 273static void drop_user_return_notifiers(void)
3548bab5 274{
013f6a5d
MT		 275 unsigned int cpu = smp_processor_id();
276 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 277
278 if (smsr->registered)
279 kvm_on_user_return(&smsr->urn);
280}
281
6866b83e
CO		 282u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
283{
8a5a87d9 284 return vcpu->arch.apic_base;
6866b83e
CO		 285}
286EXPORT_SYMBOL_GPL(kvm_get_apic_base);
287
58cb628d
JK		 288int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
289{
290 u64 old_state = vcpu->arch.apic_base &
291 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
292 u64 new_state = msr_info->data &
293 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
294 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
295 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
296
297 if (!msr_info->host_initiated &&
298 ((msr_info->data & reserved_bits) != 0 ||
299 new_state == X2APIC_ENABLE ||
300 (new_state == MSR_IA32_APICBASE_ENABLE &&
301 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
302 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
303 old_state == 0)))
304 return 1;
305
306 kvm_lapic_set_base(vcpu, msr_info->data);
307 return 0;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_set_apic_base);
310
2605fc21 311asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 312{
313 /* Fault while not rebooting. We want the trace. */
314 BUG();
315}
316EXPORT_SYMBOL_GPL(kvm_spurious_fault);
317
3fd28fce
ED		 318#define EXCPT_BENIGN 0
319#define EXCPT_CONTRIBUTORY 1
320#define EXCPT_PF 2
321
322static int exception_class(int vector)
323{
324 switch (vector) {
325 case PF_VECTOR:
326 return EXCPT_PF;
327 case DE_VECTOR:
328 case TS_VECTOR:
329 case NP_VECTOR:
330 case SS_VECTOR:
331 case GP_VECTOR:
332 return EXCPT_CONTRIBUTORY;
333 default:
334 break;
335 }
336 return EXCPT_BENIGN;
337}
338
d6e8c854
NA		 339#define EXCPT_FAULT 0
340#define EXCPT_TRAP 1
341#define EXCPT_ABORT 2
342#define EXCPT_INTERRUPT 3
343
344static int exception_type(int vector)
345{
346 unsigned int mask;
347
348 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
349 return EXCPT_INTERRUPT;
350
351 mask = 1 << vector;
352
353 /* #DB is trap, as instruction watchpoints are handled elsewhere */
354 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
355 return EXCPT_TRAP;
356
357 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
358 return EXCPT_ABORT;
359
360 /* Reserved exceptions will result in fault */
361 return EXCPT_FAULT;
362}
363
3fd28fce 364static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 365 unsigned nr, bool has_error, u32 error_code,
366 bool reinject)
3fd28fce
ED		 367{
368 u32 prev_nr;
369 int class1, class2;
370
3842d135
AK		 371 kvm_make_request(KVM_REQ_EVENT, vcpu);
372
3fd28fce
ED		 373 if (!vcpu->arch.exception.pending) {
374 queue:
3ffb2468
NA		 375 if (has_error && !is_protmode(vcpu))
376 has_error = false;
3fd28fce
ED		 377 vcpu->arch.exception.pending = true;
378 vcpu->arch.exception.has_error_code = has_error;
379 vcpu->arch.exception.nr = nr;
380 vcpu->arch.exception.error_code = error_code;
3f0fd292 381 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 382 return;
383 }
384
385 /* to check exception */
386 prev_nr = vcpu->arch.exception.nr;
387 if (prev_nr == DF_VECTOR) {
388 /* triple fault -> shutdown */
a8eeb04a 389 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 390 return;
391 }
392 class1 = exception_class(prev_nr);
393 class2 = exception_class(nr);
394 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
395 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
396 /* generate double fault per SDM Table 5-5 */
397 vcpu->arch.exception.pending = true;
398 vcpu->arch.exception.has_error_code = true;
399 vcpu->arch.exception.nr = DF_VECTOR;
400 vcpu->arch.exception.error_code = 0;
401 } else
402 /* replace previous exception with a new one in a hope
403 that instruction re-execution will regenerate lost
404 exception */
405 goto queue;
406}
407
298101da
AK		 408void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
409{
ce7ddec4 410 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 411}
412EXPORT_SYMBOL_GPL(kvm_queue_exception);
413
ce7ddec4
JR		 414void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
415{
416 kvm_multiple_exception(vcpu, nr, false, 0, true);
417}
418EXPORT_SYMBOL_GPL(kvm_requeue_exception);
419
db8fcefa 420void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 421{
db8fcefa
AP		 422 if (err)
423 kvm_inject_gp(vcpu, 0);
424 else
425 kvm_x86_ops->skip_emulated_instruction(vcpu);
426}
427EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 428
6389ee94 429void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 430{
431 ++vcpu->stat.pf_guest;
6389ee94
AK		 432 vcpu->arch.cr2 = fault->address;
433 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 434}
27d6c865 435EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 436
ef54bcfe 437static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 438{
6389ee94
AK		 439 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
440 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 441 else
6389ee94 442 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 443
444 return fault->nested_page_fault;
d4f8cf66
JR		 445}
446
3419ffc8
SY		 447void kvm_inject_nmi(struct kvm_vcpu *vcpu)
448{
7460fb4a
AK		 449 atomic_inc(&vcpu->arch.nmi_queued);
450 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 451}
452EXPORT_SYMBOL_GPL(kvm_inject_nmi);
453
298101da
AK		 454void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
455{
ce7ddec4 456 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 457}
458EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
459
ce7ddec4
JR		 460void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
461{
462 kvm_multiple_exception(vcpu, nr, true, error_code, true);
463}
464EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
465
0a79b009
AK		 466/*
467 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
468 * a #GP and return false.
469 */
470bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 471{
0a79b009
AK		 472 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
473 return true;
474 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
475 return false;
298101da 476}
0a79b009 477EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 478
16f8a6f9
NA		 479bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
480{
481 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
482 return true;
483
484 kvm_queue_exception(vcpu, UD_VECTOR);
485 return false;
486}
487EXPORT_SYMBOL_GPL(kvm_require_dr);
488
ec92fe44
JR		 489/*
490 * This function will be used to read from the physical memory of the currently
54bf36aa 491 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 492 * can read from guest physical or from the guest's guest physical memory.
493 */
494int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
495 gfn_t ngfn, void *data, int offset, int len,
496 u32 access)
497{
54987b7a 498 struct x86_exception exception;
ec92fe44
JR		 499 gfn_t real_gfn;
500 gpa_t ngpa;
501
502 ngpa = gfn_to_gpa(ngfn);
54987b7a 503 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 504 if (real_gfn == UNMAPPED_GVA)
505 return -EFAULT;
506
507 real_gfn = gpa_to_gfn(real_gfn);
508
54bf36aa 509 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 510}
511EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
512
69b0049a 513static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 514 void *data, int offset, int len, u32 access)
515{
516 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
517 data, offset, len, access);
518}
519
a03490ed
CO		 520/*
521 * Load the pae pdptrs. Return true is they are all valid.
522 */
ff03a073 523int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 524{
525 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
526 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
527 int i;
528 int ret;
ff03a073 529 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 530
ff03a073
JR		 531 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
532 offset * sizeof(u64), sizeof(pdpte),
533 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 534 if (ret < 0) {
535 ret = 0;
536 goto out;
537 }
538 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 539 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 540 (pdpte[i] &
541 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 542 ret = 0;
543 goto out;
544 }
545 }
546 ret = 1;
547
ff03a073 548 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 549 __set_bit(VCPU_EXREG_PDPTR,
550 (unsigned long *)&vcpu->arch.regs_avail);
551 __set_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 553out:
a03490ed
CO		 554
555 return ret;
556}
cc4b6871 557EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 558
d835dfec
AK		 559static bool pdptrs_changed(struct kvm_vcpu *vcpu)
560{
ff03a073 561 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 562 bool changed = true;
3d06b8bf
JR		 563 int offset;
564 gfn_t gfn;
d835dfec
AK		 565 int r;
566
567 if (is_long_mode(vcpu) || !is_pae(vcpu))
568 return false;
569
6de4f3ad
AK		 570 if (!test_bit(VCPU_EXREG_PDPTR,
571 (unsigned long *)&vcpu->arch.regs_avail))
572 return true;
573
9f8fe504
AK		 574 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
575 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 576 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
577 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 578 if (r < 0)
579 goto out;
ff03a073 580 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 581out:
d835dfec
AK		 582
583 return changed;
584}
585
49a9b07e 586int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 587{
aad82703 588 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 589 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 590
f9a48e6a
AK		 591 cr0 |= X86_CR0_ET;
592
ab344828 593#ifdef CONFIG_X86_64
0f12244f
GN		 594 if (cr0 & 0xffffffff00000000UL)
595 return 1;
ab344828
GN		 596#endif
597
598 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
601 return 1;
a03490ed 602
0f12244f
GN		 603 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
604 return 1;
a03490ed
CO		 605
606 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
607#ifdef CONFIG_X86_64
f6801dff 608 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 609 int cs_db, cs_l;
610
0f12244f
GN		 611 if (!is_pae(vcpu))
612 return 1;
a03490ed 613 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 614 if (cs_l)
615 return 1;
a03490ed
CO		 616 } else
617#endif
ff03a073 618 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 619 kvm_read_cr3(vcpu)))
0f12244f 620 return 1;
a03490ed
CO		 621 }
622
ad756a16
MJ		 623 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
624 return 1;
625
a03490ed 626 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 627
d170c419 628 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 629 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 630 kvm_async_pf_hash_reset(vcpu);
631 }
e5f3f027 632
aad82703
SY		 633 if ((cr0 ^ old_cr0) & update_bits)
634 kvm_mmu_reset_context(vcpu);
b18d5431 635
879ae188
LE		 636 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
637 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
638 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 639 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
640
0f12244f
GN		 641 return 0;
642}
2d3ad1f4 643EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 644
2d3ad1f4 645void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 646{
49a9b07e 647 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 648}
2d3ad1f4 649EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 650
42bdf991
MT		 651static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
652{
653 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
654 !vcpu->guest_xcr0_loaded) {
655 /* kvm_set_xcr() also depends on this */
656 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
657 vcpu->guest_xcr0_loaded = 1;
658 }
659}
660
661static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
662{
663 if (vcpu->guest_xcr0_loaded) {
664 if (vcpu->arch.xcr0 != host_xcr0)
665 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
666 vcpu->guest_xcr0_loaded = 0;
667 }
668}
669
69b0049a 670static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 671{
56c103ec
LJ		 672 u64 xcr0 = xcr;
673 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 674 u64 valid_bits;
2acf923e
DC		 675
676 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
677 if (index != XCR_XFEATURE_ENABLED_MASK)
678 return 1;
d91cab78 679 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 680 return 1;
d91cab78 681 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 682 return 1;
46c34cb0
PB		 683
684 /*
685 * Do not allow the guest to set bits that we do not support
686 * saving. However, xcr0 bit 0 is always set, even if the
687 * emulated CPU does not support XSAVE (see fx_init).
688 */
d91cab78 689 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 690 if (xcr0 & ~valid_bits)
2acf923e 691 return 1;
46c34cb0 692
d91cab78
DH		 693 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
694 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 695 return 1;
696
d91cab78
DH		 697 if (xcr0 & XFEATURE_MASK_AVX512) {
698 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 699 return 1;
d91cab78 700 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 701 return 1;
702 }
2acf923e 703 vcpu->arch.xcr0 = xcr0;
56c103ec 704
d91cab78 705 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 706 kvm_update_cpuid(vcpu);
2acf923e
DC		 707 return 0;
708}
709
710int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
711{
764bcbc5
Z		 712 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
713 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 714 kvm_inject_gp(vcpu, 0);
715 return 1;
716 }
717 return 0;
718}
719EXPORT_SYMBOL_GPL(kvm_set_xcr);
720
a83b29c6 721int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 722{
fc78f519 723 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 724 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 725 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 726
0f12244f
GN		 727 if (cr4 & CR4_RESERVED_BITS)
728 return 1;
a03490ed 729
2acf923e
DC		 730 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
731 return 1;
732
c68b734f
YW		 733 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
734 return 1;
735
97ec8c06
FW		 736 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
737 return 1;
738
afcbf13f 739 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 740 return 1;
741
b9baba86
HH		 742 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
743 return 1;
744
a03490ed 745 if (is_long_mode(vcpu)) {
0f12244f
GN		 746 if (!(cr4 & X86_CR4_PAE))
747 return 1;
a2edf57f
AK		 748 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
749 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 750 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
751 kvm_read_cr3(vcpu)))
0f12244f
GN		 752 return 1;
753
ad756a16
MJ		 754 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
755 if (!guest_cpuid_has_pcid(vcpu))
756 return 1;
757
758 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
759 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
760 return 1;
761 }
762
5e1746d6 763 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 764 return 1;
a03490ed 765
ad756a16
MJ		 766 if (((cr4 ^ old_cr4) & pdptr_bits) ||
767 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 768 kvm_mmu_reset_context(vcpu);
0f12244f 769
b9baba86 770 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 771 kvm_update_cpuid(vcpu);
2acf923e 772
0f12244f
GN		 773 return 0;
774}
2d3ad1f4 775EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 776
2390218b 777int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 778{
ac146235 779#ifdef CONFIG_X86_64
9d88fca7 780 cr3 &= ~CR3_PCID_INVD;
ac146235 781#endif
9d88fca7 782
9f8fe504 783 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 784 kvm_mmu_sync_roots(vcpu);
77c3913b 785 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 786 return 0;
d835dfec
AK		 787 }
788
a03490ed 789 if (is_long_mode(vcpu)) {
d9f89b88
JK		 790 if (cr3 & CR3_L_MODE_RESERVED_BITS)
791 return 1;
792 } else if (is_pae(vcpu) && is_paging(vcpu) &&
793 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 794 return 1;
a03490ed 795
0f12244f 796 vcpu->arch.cr3 = cr3;
aff48baa 797 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 798 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 799 return 0;
800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 802
eea1cff9 803int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 804{
0f12244f
GN		 805 if (cr8 & CR8_RESERVED_BITS)
806 return 1;
35754c98 807 if (lapic_in_kernel(vcpu))
a03490ed
CO		 808 kvm_lapic_set_tpr(vcpu, cr8);
809 else
ad312c7c 810 vcpu->arch.cr8 = cr8;
0f12244f
GN		 811 return 0;
812}
2d3ad1f4 813EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 814
2d3ad1f4 815unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 816{
35754c98 817 if (lapic_in_kernel(vcpu))
a03490ed
CO		 818 return kvm_lapic_get_cr8(vcpu);
819 else
ad312c7c 820 return vcpu->arch.cr8;
a03490ed 821}
2d3ad1f4 822EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 823
ae561ede
NA		 824static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
825{
826 int i;
827
828 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
829 for (i = 0; i < KVM_NR_DB_REGS; i++)
830 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
831 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
832 }
833}
834
73aaf249
JK		 835static void kvm_update_dr6(struct kvm_vcpu *vcpu)
836{
837 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
838 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
839}
840
c8639010
JK		 841static void kvm_update_dr7(struct kvm_vcpu *vcpu)
842{
843 unsigned long dr7;
844
845 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
846 dr7 = vcpu->arch.guest_debug_dr7;
847 else
848 dr7 = vcpu->arch.dr7;
849 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 850 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
851 if (dr7 & DR7_BP_EN_MASK)
852 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 853}
854
6f43ed01
NA		 855static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
856{
857 u64 fixed = DR6_FIXED_1;
858
859 if (!guest_cpuid_has_rtm(vcpu))
860 fixed |= DR6_RTM;
861 return fixed;
862}
863
338dbc97 864static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 865{
866 switch (dr) {
867 case 0 ... 3:
868 vcpu->arch.db[dr] = val;
869 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
870 vcpu->arch.eff_db[dr] = val;
871 break;
872 case 4:
020df079
GN		 873 /* fall through */
874 case 6:
338dbc97
GN		 875 if (val & 0xffffffff00000000ULL)
876 return -1; /* #GP */
6f43ed01 877 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 878 kvm_update_dr6(vcpu);
020df079
GN		 879 break;
880 case 5:
020df079
GN		 881 /* fall through */
882 default: /* 7 */
338dbc97
GN		 883 if (val & 0xffffffff00000000ULL)
884 return -1; /* #GP */
020df079 885 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 886 kvm_update_dr7(vcpu);
020df079
GN		 887 break;
888 }
889
890 return 0;
891}
338dbc97
GN		 892
893int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
894{
16f8a6f9 895 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 896 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 897 return 1;
898 }
899 return 0;
338dbc97 900}
020df079
GN		 901EXPORT_SYMBOL_GPL(kvm_set_dr);
902
16f8a6f9 903int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 904{
905 switch (dr) {
906 case 0 ... 3:
907 *val = vcpu->arch.db[dr];
908 break;
909 case 4:
020df079
GN		 910 /* fall through */
911 case 6:
73aaf249
JK		 912 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
913 *val = vcpu->arch.dr6;
914 else
915 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 916 break;
917 case 5:
020df079
GN		 918 /* fall through */
919 default: /* 7 */
920 *val = vcpu->arch.dr7;
921 break;
922 }
338dbc97
GN		 923 return 0;
924}
020df079
GN		 925EXPORT_SYMBOL_GPL(kvm_get_dr);
926
022cd0e8
AK		 927bool kvm_rdpmc(struct kvm_vcpu *vcpu)
928{
929 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
930 u64 data;
931 int err;
932
c6702c9d 933 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 934 if (err)
935 return err;
936 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
937 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
938 return err;
939}
940EXPORT_SYMBOL_GPL(kvm_rdpmc);
941
043405e1
CO		 942/*
943 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
944 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
945 *
946 * This list is modified at module load time to reflect the
e3267cbb 947 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 948 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
949 * may depend on host virtualization features rather than host cpu features.
043405e1 950 */
e3267cbb 951
043405e1
CO		 952static u32 msrs_to_save[] = {
953 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 954 MSR_STAR,
043405e1
CO		 955#ifdef CONFIG_X86_64
956 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
957#endif
b3897a49 958 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 959 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 960};
961
962static unsigned num_msrs_to_save;
963
62ef68bb
PB		 964static u32 emulated_msrs[] = {
965 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
966 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
967 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
968 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 969 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
970 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 971 HV_X64_MSR_RESET,
11c4b1ca 972 HV_X64_MSR_VP_INDEX,
9eec50b8 973 HV_X64_MSR_VP_RUNTIME,
5c919412 974 HV_X64_MSR_SCONTROL,
1f4b34f8 975 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 976 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
977 MSR_KVM_PV_EOI_EN,
978
ba904635 979 MSR_IA32_TSC_ADJUST,
a3e06bbe 980 MSR_IA32_TSCDEADLINE,
043405e1 981 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 982 MSR_IA32_MCG_STATUS,
983 MSR_IA32_MCG_CTL,
64d60670 984 MSR_IA32_SMBASE,
043405e1
CO		 985};
986
62ef68bb
PB		 987static unsigned num_emulated_msrs;
988
384bb783 989bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 990{
b69e8cae 991 if (efer & efer_reserved_bits)
384bb783 992 return false;
15c4a640 993
1b2fd70c
AG		 994 if (efer & EFER_FFXSR) {
995 struct kvm_cpuid_entry2 *feat;
996
997 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 998 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 999 return false;
1b2fd70c
AG		 1000 }
1001
d8017474
AG		 1002 if (efer & EFER_SVME) {
1003 struct kvm_cpuid_entry2 *feat;
1004
1005 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1006 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1007 return false;
d8017474
AG		 1008 }
1009
384bb783
JK		 1010 return true;
1011}
1012EXPORT_SYMBOL_GPL(kvm_valid_efer);
1013
1014static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1015{
1016 u64 old_efer = vcpu->arch.efer;
1017
1018 if (!kvm_valid_efer(vcpu, efer))
1019 return 1;
1020
1021 if (is_paging(vcpu)
1022 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1023 return 1;
1024
15c4a640 1025 efer &= ~EFER_LMA;
f6801dff 1026 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1027
a3d204e2
SY		 1028 kvm_x86_ops->set_efer(vcpu, efer);
1029
aad82703
SY		 1030 /* Update reserved bits */
1031 if ((efer ^ old_efer) & EFER_NX)
1032 kvm_mmu_reset_context(vcpu);
1033
b69e8cae 1034 return 0;
15c4a640
CO		 1035}
1036
f2b4b7dd
JR		 1037void kvm_enable_efer_bits(u64 mask)
1038{
1039 efer_reserved_bits &= ~mask;
1040}
1041EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1042
15c4a640
CO		 1043/*
1044 * Writes msr value into into the appropriate "register".
1045 * Returns 0 on success, non-0 otherwise.
1046 * Assumes vcpu_load() was already called.
1047 */
8fe8ab46 1048int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1049{
854e8bb1
NA		 1050 switch (msr->index) {
1051 case MSR_FS_BASE:
1052 case MSR_GS_BASE:
1053 case MSR_KERNEL_GS_BASE:
1054 case MSR_CSTAR:
1055 case MSR_LSTAR:
1056 if (is_noncanonical_address(msr->data))
1057 return 1;
1058 break;
1059 case MSR_IA32_SYSENTER_EIP:
1060 case MSR_IA32_SYSENTER_ESP:
1061 /*
1062 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1063 * non-canonical address is written on Intel but not on
1064 * AMD (which ignores the top 32-bits, because it does
1065 * not implement 64-bit SYSENTER).
1066 *
1067 * 64-bit code should hence be able to write a non-canonical
1068 * value on AMD. Making the address canonical ensures that
1069 * vmentry does not fail on Intel after writing a non-canonical
1070 * value, and that something deterministic happens if the guest
1071 * invokes 64-bit SYSENTER.
1072 */
1073 msr->data = get_canonical(msr->data);
1074 }
8fe8ab46 1075 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1076}
854e8bb1 1077EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1078
313a3dc7
CO		 1079/*
1080 * Adapt set_msr() to msr_io()'s calling convention
1081 */
609e36d3
PB		 1082static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1083{
1084 struct msr_data msr;
1085 int r;
1086
1087 msr.index = index;
1088 msr.host_initiated = true;
1089 r = kvm_get_msr(vcpu, &msr);
1090 if (r)
1091 return r;
1092
1093 *data = msr.data;
1094 return 0;
1095}
1096
313a3dc7
CO		 1097static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1098{
8fe8ab46
WA		 1099 struct msr_data msr;
1100
1101 msr.data = *data;
1102 msr.index = index;
1103 msr.host_initiated = true;
1104 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1105}
1106
16e8d74d
MT		 1107#ifdef CONFIG_X86_64
1108struct pvclock_gtod_data {
1109 seqcount_t seq;
1110
1111 struct { /* extract of a clocksource struct */
1112 int vclock_mode;
1113 cycle_t cycle_last;
1114 cycle_t mask;
1115 u32 mult;
1116 u32 shift;
1117 } clock;
1118
cbcf2dd3
TG		 1119 u64 boot_ns;
1120 u64 nsec_base;
16e8d74d
MT		 1121};
1122
1123static struct pvclock_gtod_data pvclock_gtod_data;
1124
1125static void update_pvclock_gtod(struct timekeeper *tk)
1126{
1127 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1128 u64 boot_ns;
1129
876e7881 1130 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1131
1132 write_seqcount_begin(&vdata->seq);
1133
1134 /* copy pvclock gtod data */
876e7881
PZ		 1135 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1136 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1137 vdata->clock.mask = tk->tkr_mono.mask;
1138 vdata->clock.mult = tk->tkr_mono.mult;
1139 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1140
cbcf2dd3 1141 vdata->boot_ns = boot_ns;
876e7881 1142 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1143
1144 write_seqcount_end(&vdata->seq);
1145}
1146#endif
1147
bab5bb39
NK		 1148void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1149{
1150 /*
1151 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1152 * vcpu_enter_guest. This function is only called from
1153 * the physical CPU that is running vcpu.
1154 */
1155 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1156}
16e8d74d 1157
18068523
GOC		 1158static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1159{
9ed3c444
AK		 1160 int version;
1161 int r;
50d0a0f9 1162 struct pvclock_wall_clock wc;
923de3cf 1163 struct timespec boot;
18068523
GOC		 1164
1165 if (!wall_clock)
1166 return;
1167
9ed3c444
AK		 1168 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1169 if (r)
1170 return;
1171
1172 if (version & 1)
1173 ++version; /* first time write, random junk */
1174
1175 ++version;
18068523 1176
1dab1345
NK		 1177 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1178 return;
18068523 1179
50d0a0f9
GH		 1180 /*
1181 * The guest calculates current wall clock time by adding
34c238a1 1182 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1183 * wall clock specified here. guest system time equals host
1184 * system time for us, thus we must fill in host boot time here.
1185 */
923de3cf 1186 getboottime(&boot);
50d0a0f9 1187
4b648665
BR		 1188 if (kvm->arch.kvmclock_offset) {
1189 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1190 boot = timespec_sub(boot, ts);
1191 }
50d0a0f9
GH		 1192 wc.sec = boot.tv_sec;
1193 wc.nsec = boot.tv_nsec;
1194 wc.version = version;
18068523
GOC		 1195
1196 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1197
1198 version++;
1199 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1200}
1201
50d0a0f9
GH		 1202static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1203{
b51012de
PB		 1204 do_shl32_div32(dividend, divisor);
1205 return dividend;
50d0a0f9
GH		 1206}
1207
3ae13faa 1208static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1209 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1210{
5f4e3f88 1211 uint64_t scaled64;
50d0a0f9
GH		 1212 int32_t shift = 0;
1213 uint64_t tps64;
1214 uint32_t tps32;
1215
3ae13faa
PB		 1216 tps64 = base_hz;
1217 scaled64 = scaled_hz;
50933623 1218 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1219 tps64 >>= 1;
1220 shift--;
1221 }
1222
1223 tps32 = (uint32_t)tps64;
50933623
JK		 1224 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1225 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1226 scaled64 >>= 1;
1227 else
1228 tps32 <<= 1;
50d0a0f9
GH		 1229 shift++;
1230 }
1231
5f4e3f88
ZA		 1232 *pshift = shift;
1233 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1234
3ae13faa
PB		 1235 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1236 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1237}
1238
d828199e 1239#ifdef CONFIG_X86_64
16e8d74d 1240static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1241#endif
16e8d74d 1242
c8076604 1243static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1244static unsigned long max_tsc_khz;
c8076604 1245
cc578287 1246static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1247{
cc578287
ZA		 1248 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1249 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1250}
1251
cc578287 1252static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1253{
cc578287
ZA		 1254 u64 v = (u64)khz * (1000000 + ppm);
1255 do_div(v, 1000000);
1256 return v;
1e993611
JR		 1257}
1258
381d585c
HZ		 1259static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1260{
1261 u64 ratio;
1262
1263 /* Guest TSC same frequency as host TSC? */
1264 if (!scale) {
1265 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1266 return 0;
1267 }
1268
1269 /* TSC scaling supported? */
1270 if (!kvm_has_tsc_control) {
1271 if (user_tsc_khz > tsc_khz) {
1272 vcpu->arch.tsc_catchup = 1;
1273 vcpu->arch.tsc_always_catchup = 1;
1274 return 0;
1275 } else {
1276 WARN(1, "user requested TSC rate below hardware speed\n");
1277 return -1;
1278 }
1279 }
1280
1281 /* TSC scaling required - calculate ratio */
1282 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1283 user_tsc_khz, tsc_khz);
1284
1285 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1286 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1287 user_tsc_khz);
1288 return -1;
1289 }
1290
1291 vcpu->arch.tsc_scaling_ratio = ratio;
1292 return 0;
1293}
1294
4941b8cb 1295static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1296{
cc578287
ZA		 1297 u32 thresh_lo, thresh_hi;
1298 int use_scaling = 0;
217fc9cf 1299
03ba32ca 1300 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1301 if (user_tsc_khz == 0) {
ad721883
HZ		 1302 /* set tsc_scaling_ratio to a safe value */
1303 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1304 return -1;
ad721883 1305 }
03ba32ca 1306
c285545f 1307 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1308 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1309 &vcpu->arch.virtual_tsc_shift,
1310 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1311 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1312
1313 /*
1314 * Compute the variation in TSC rate which is acceptable
1315 * within the range of tolerance and decide if the
1316 * rate being applied is within that bounds of the hardware
1317 * rate. If so, no scaling or compensation need be done.
1318 */
1319 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1320 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1321 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1322 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1323 use_scaling = 1;
1324 }
4941b8cb 1325 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1326}
1327
1328static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1329{
e26101b1 1330 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1331 vcpu->arch.virtual_tsc_mult,
1332 vcpu->arch.virtual_tsc_shift);
e26101b1 1333 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1334 return tsc;
1335}
1336
69b0049a 1337static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1338{
1339#ifdef CONFIG_X86_64
1340 bool vcpus_matched;
b48aa97e
MT		 1341 struct kvm_arch *ka = &vcpu->kvm->arch;
1342 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1343
1344 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1345 atomic_read(&vcpu->kvm->online_vcpus));
1346
7f187922
MT		 1347 /*
1348 * Once the masterclock is enabled, always perform request in
1349 * order to update it.
1350 *
1351 * In order to enable masterclock, the host clocksource must be TSC
1352 * and the vcpus need to have matched TSCs. When that happens,
1353 * perform request to enable masterclock.
1354 */
1355 if (ka->use_master_clock ||
1356 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1357 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1358
1359 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1360 atomic_read(&vcpu->kvm->online_vcpus),
1361 ka->use_master_clock, gtod->clock.vclock_mode);
1362#endif
1363}
1364
ba904635
WA		 1365static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1366{
1367 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1368 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1369}
1370
35181e86
HZ		 1371/*
1372 * Multiply tsc by a fixed point number represented by ratio.
1373 *
1374 * The most significant 64-N bits (mult) of ratio represent the
1375 * integral part of the fixed point number; the remaining N bits
1376 * (frac) represent the fractional part, ie. ratio represents a fixed
1377 * point number (mult + frac * 2^(-N)).
1378 *
1379 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1380 */
1381static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1382{
1383 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1384}
1385
1386u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1387{
1388 u64 _tsc = tsc;
1389 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1390
1391 if (ratio != kvm_default_tsc_scaling_ratio)
1392 _tsc = __scale_tsc(ratio, tsc);
1393
1394 return _tsc;
1395}
1396EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1397
07c1419a
HZ		 1398static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1399{
1400 u64 tsc;
1401
1402 tsc = kvm_scale_tsc(vcpu, rdtsc());
1403
1404 return target_tsc - tsc;
1405}
1406
4ba76538
HZ		 1407u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1408{
1409 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1410}
1411EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1412
8fe8ab46 1413void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1414{
1415 struct kvm *kvm = vcpu->kvm;
f38e098f 1416 u64 offset, ns, elapsed;
99e3e30a 1417 unsigned long flags;
02626b6a 1418 s64 usdiff;
b48aa97e 1419 bool matched;
0d3da0d2 1420 bool already_matched;
8fe8ab46 1421 u64 data = msr->data;
99e3e30a 1422
038f8c11 1423 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1424 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1425 ns = get_kernel_ns();
f38e098f 1426 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1427
03ba32ca 1428 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1429 int faulted = 0;
1430
03ba32ca
MT		 1431 /* n.b - signed multiplication and division required */
1432 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1433#ifdef CONFIG_X86_64
03ba32ca 1434 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1435#else
03ba32ca 1436 /* do_div() only does unsigned */
8915aa27
MT		 1437 asm("1: idivl %[divisor]\n"
1438 "2: xor %%edx, %%edx\n"
1439 " movl $0, %[faulted]\n"
1440 "3:\n"
1441 ".section .fixup,\"ax\"\n"
1442 "4: movl $1, %[faulted]\n"
1443 " jmp 3b\n"
1444 ".previous\n"
1445
1446 _ASM_EXTABLE(1b, 4b)
1447
1448 : "=A"(usdiff), [faulted] "=r" (faulted)
1449 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1450
5d3cb0f6 1451#endif
03ba32ca
MT		 1452 do_div(elapsed, 1000);
1453 usdiff -= elapsed;
1454 if (usdiff < 0)
1455 usdiff = -usdiff;
8915aa27
MT		 1456
1457 /* idivl overflow => difference is larger than USEC_PER_SEC */
1458 if (faulted)
1459 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1460 } else
1461 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1462
1463 /*
5d3cb0f6
ZA		 1464 * Special case: TSC write with a small delta (1 second) of virtual
1465 * cycle time against real time is interpreted as an attempt to
1466 * synchronize the CPU.
1467 *
1468 * For a reliable TSC, we can match TSC offsets, and for an unstable
1469 * TSC, we add elapsed time in this computation. We could let the
1470 * compensation code attempt to catch up if we fall behind, but
1471 * it's better to try to match offsets from the beginning.
1472 */
02626b6a 1473 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1474 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1475 if (!check_tsc_unstable()) {
e26101b1 1476 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1477 pr_debug("kvm: matched tsc offset for %llu\n", data);
1478 } else {
857e4099 1479 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1480 data += delta;
07c1419a 1481 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1482 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1483 }
b48aa97e 1484 matched = true;
0d3da0d2 1485 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1486 } else {
1487 /*
1488 * We split periods of matched TSC writes into generations.
1489 * For each generation, we track the original measured
1490 * nanosecond time, offset, and write, so if TSCs are in
1491 * sync, we can match exact offset, and if not, we can match
4a969980 1492 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1493 *
1494 * These values are tracked in kvm->arch.cur_xxx variables.
1495 */
1496 kvm->arch.cur_tsc_generation++;
1497 kvm->arch.cur_tsc_nsec = ns;
1498 kvm->arch.cur_tsc_write = data;
1499 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1500 matched = false;
0d3da0d2 1501 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1502 kvm->arch.cur_tsc_generation, data);
f38e098f 1503 }
e26101b1
ZA		 1504
1505 /*
1506 * We also track th most recent recorded KHZ, write and time to
1507 * allow the matching interval to be extended at each write.
1508 */
f38e098f
ZA		 1509 kvm->arch.last_tsc_nsec = ns;
1510 kvm->arch.last_tsc_write = data;
5d3cb0f6 1511 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1512
b183aa58 1513 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1514
1515 /* Keep track of which generation this VCPU has synchronized to */
1516 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1517 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1518 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1519
ba904635
WA		 1520 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1521 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1522 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1523 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1524
1525 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1526 if (!matched) {
b48aa97e 1527 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1528 } else if (!already_matched) {
1529 kvm->arch.nr_vcpus_matched_tsc++;
1530 }
b48aa97e
MT		 1531
1532 kvm_track_tsc_matching(vcpu);
1533 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1534}
e26101b1 1535
99e3e30a
ZA		 1536EXPORT_SYMBOL_GPL(kvm_write_tsc);
1537
58ea6767
HZ		 1538static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1539 s64 adjustment)
1540{
1541 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1542}
1543
1544static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1545{
1546 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1547 WARN_ON(adjustment < 0);
1548 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1549 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1550}
1551
d828199e
MT		 1552#ifdef CONFIG_X86_64
1553
1554static cycle_t read_tsc(void)
1555{
03b9730b
AL		 1556 cycle_t ret = (cycle_t)rdtsc_ordered();
1557 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1558
1559 if (likely(ret >= last))
1560 return ret;
1561
1562 /*
1563 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1564 * predictable (it's just a function of time and the likely is
d828199e
MT		 1565 * very likely) and there's a data dependence, so force GCC
1566 * to generate a branch instead. I don't barrier() because
1567 * we don't actually need a barrier, and if this function
1568 * ever gets inlined it will generate worse code.
1569 */
1570 asm volatile ("");
1571 return last;
1572}
1573
1574static inline u64 vgettsc(cycle_t *cycle_now)
1575{
1576 long v;
1577 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1578
1579 *cycle_now = read_tsc();
1580
1581 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1582 return v * gtod->clock.mult;
1583}
1584
cbcf2dd3 1585static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1586{
cbcf2dd3 1587 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1588 unsigned long seq;
d828199e 1589 int mode;
cbcf2dd3 1590 u64 ns;
d828199e 1591
d828199e
MT		 1592 do {
1593 seq = read_seqcount_begin(&gtod->seq);
1594 mode = gtod->clock.vclock_mode;
cbcf2dd3 1595 ns = gtod->nsec_base;
d828199e
MT		 1596 ns += vgettsc(cycle_now);
1597 ns >>= gtod->clock.shift;
cbcf2dd3 1598 ns += gtod->boot_ns;
d828199e 1599 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1600 *t = ns;
d828199e
MT		 1601
1602 return mode;
1603}
1604
1605/* returns true if host is using tsc clocksource */
1606static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1607{
d828199e
MT		 1608 /* checked again under seqlock below */
1609 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1610 return false;
1611
cbcf2dd3 1612 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1613}
1614#endif
1615
1616/*
1617 *
b48aa97e
MT		 1618 * Assuming a stable TSC across physical CPUS, and a stable TSC
1619 * across virtual CPUs, the following condition is possible.
1620 * Each numbered line represents an event visible to both
d828199e
MT		 1621 * CPUs at the next numbered event.
1622 *
1623 * "timespecX" represents host monotonic time. "tscX" represents
1624 * RDTSC value.
1625 *
1626 * VCPU0 on CPU0 | VCPU1 on CPU1
1627 *
1628 * 1. read timespec0,tsc0
1629 * 2. | timespec1 = timespec0 + N
1630 * | tsc1 = tsc0 + M
1631 * 3. transition to guest | transition to guest
1632 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1633 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1634 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1635 *
1636 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1637 *
1638 * - ret0 < ret1
1639 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1640 * ...
1641 * - 0 < N - M => M < N
1642 *
1643 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1644 * always the case (the difference between two distinct xtime instances
1645 * might be smaller then the difference between corresponding TSC reads,
1646 * when updating guest vcpus pvclock areas).
1647 *
1648 * To avoid that problem, do not allow visibility of distinct
1649 * system_timestamp/tsc_timestamp values simultaneously: use a master
1650 * copy of host monotonic time values. Update that master copy
1651 * in lockstep.
1652 *
b48aa97e 1653 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1654 *
1655 */
1656
1657static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1658{
1659#ifdef CONFIG_X86_64
1660 struct kvm_arch *ka = &kvm->arch;
1661 int vclock_mode;
b48aa97e
MT		 1662 bool host_tsc_clocksource, vcpus_matched;
1663
1664 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1665 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1666
1667 /*
1668 * If the host uses TSC clock, then passthrough TSC as stable
1669 * to the guest.
1670 */
b48aa97e 1671 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1672 &ka->master_kernel_ns,
1673 &ka->master_cycle_now);
1674
16a96021 1675 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1676 && !backwards_tsc_observed
1677 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1678
d828199e
MT		 1679 if (ka->use_master_clock)
1680 atomic_set(&kvm_guest_has_master_clock, 1);
1681
1682 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1683 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1684 vcpus_matched);
d828199e
MT		 1685#endif
1686}
1687
2860c4b1
PB		 1688void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1689{
1690 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1691}
1692
2e762ff7
MT		 1693static void kvm_gen_update_masterclock(struct kvm *kvm)
1694{
1695#ifdef CONFIG_X86_64
1696 int i;
1697 struct kvm_vcpu *vcpu;
1698 struct kvm_arch *ka = &kvm->arch;
1699
1700 spin_lock(&ka->pvclock_gtod_sync_lock);
1701 kvm_make_mclock_inprogress_request(kvm);
1702 /* no guest entries from this point */
1703 pvclock_update_vm_gtod_copy(kvm);
1704
1705 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1706 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1707
1708 /* guest entries allowed */
1709 kvm_for_each_vcpu(i, vcpu, kvm)
1710 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1711
1712 spin_unlock(&ka->pvclock_gtod_sync_lock);
1713#endif
1714}
1715
34c238a1 1716static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1717{
78db6a50 1718 unsigned long flags, tgt_tsc_khz;
18068523 1719 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1720 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1721 s64 kernel_ns;
d828199e 1722 u64 tsc_timestamp, host_tsc;
0b79459b 1723 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1724 u8 pvclock_flags;
d828199e
MT		 1725 bool use_master_clock;
1726
1727 kernel_ns = 0;
1728 host_tsc = 0;
18068523 1729
d828199e
MT		 1730 /*
1731 * If the host uses TSC clock, then passthrough TSC as stable
1732 * to the guest.
1733 */
1734 spin_lock(&ka->pvclock_gtod_sync_lock);
1735 use_master_clock = ka->use_master_clock;
1736 if (use_master_clock) {
1737 host_tsc = ka->master_cycle_now;
1738 kernel_ns = ka->master_kernel_ns;
1739 }
1740 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1741
1742 /* Keep irq disabled to prevent changes to the clock */
1743 local_irq_save(flags);
78db6a50
PB		 1744 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1745 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1746 local_irq_restore(flags);
1747 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1748 return 1;
1749 }
d828199e 1750 if (!use_master_clock) {
4ea1636b 1751 host_tsc = rdtsc();
d828199e
MT		 1752 kernel_ns = get_kernel_ns();
1753 }
1754
4ba76538 1755 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1756
c285545f
ZA		 1757 /*
1758 * We may have to catch up the TSC to match elapsed wall clock
1759 * time for two reasons, even if kvmclock is used.
1760 * 1) CPU could have been running below the maximum TSC rate
1761 * 2) Broken TSC compensation resets the base at each VCPU
1762 * entry to avoid unknown leaps of TSC even when running
1763 * again on the same CPU. This may cause apparent elapsed
1764 * time to disappear, and the guest to stand still or run
1765 * very slowly.
1766 */
1767 if (vcpu->tsc_catchup) {
1768 u64 tsc = compute_guest_tsc(v, kernel_ns);
1769 if (tsc > tsc_timestamp) {
f1e2b260 1770 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1771 tsc_timestamp = tsc;
1772 }
50d0a0f9
GH		 1773 }
1774
18068523
GOC		 1775 local_irq_restore(flags);
1776
0b79459b 1777 if (!vcpu->pv_time_enabled)
c285545f 1778 return 0;
18068523 1779
78db6a50
PB		 1780 if (kvm_has_tsc_control)
1781 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1782
1783 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1784 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1785 &vcpu->hv_clock.tsc_shift,
1786 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1787 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1788 }
1789
1790 /* With all the info we got, fill in the values */
1d5f066e 1791 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1792 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1793 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1794
09a0c3f1
OH		 1795 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1796 &guest_hv_clock, sizeof(guest_hv_clock))))
1797 return 0;
1798
5dca0d91
RK		 1799 /* This VCPU is paused, but it's legal for a guest to read another
1800 * VCPU's kvmclock, so we really have to follow the specification where
1801 * it says that version is odd if data is being modified, and even after
1802 * it is consistent.
1803 *
1804 * Version field updates must be kept separate. This is because
1805 * kvm_write_guest_cached might use a "rep movs" instruction, and
1806 * writes within a string instruction are weakly ordered. So there
1807 * are three writes overall.
1808 *
1809 * As a small optimization, only write the version field in the first
1810 * and third write. The vcpu->pv_time cache is still valid, because the
1811 * version field is the first in the struct.
18068523 1812 */
5dca0d91
RK		 1813 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1814
1815 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1816 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1817 &vcpu->hv_clock,
1818 sizeof(vcpu->hv_clock.version));
1819
1820 smp_wmb();
78c0337a
MT		 1821
1822 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1823 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1824
1825 if (vcpu->pvclock_set_guest_stopped_request) {
1826 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1827 vcpu->pvclock_set_guest_stopped_request = false;
1828 }
1829
d828199e
MT		 1830 /* If the host uses TSC clocksource, then it is stable */
1831 if (use_master_clock)
1832 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1833
78c0337a
MT		 1834 vcpu->hv_clock.flags = pvclock_flags;
1835
ce1a5e60
DM		 1836 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1837
0b79459b
AH		 1838 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1839 &vcpu->hv_clock,
1840 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1841
1842 smp_wmb();
1843
1844 vcpu->hv_clock.version++;
1845 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1846 &vcpu->hv_clock,
1847 sizeof(vcpu->hv_clock.version));
8cfdc000 1848 return 0;
c8076604
GH		 1849}
1850
0061d53d
MT		 1851/*
1852 * kvmclock updates which are isolated to a given vcpu, such as
1853 * vcpu->cpu migration, should not allow system_timestamp from
1854 * the rest of the vcpus to remain static. Otherwise ntp frequency
1855 * correction applies to one vcpu's system_timestamp but not
1856 * the others.
1857 *
1858 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1859 * We need to rate-limit these requests though, as they can
1860 * considerably slow guests that have a large number of vcpus.
1861 * The time for a remote vcpu to update its kvmclock is bound
1862 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1863 */
1864
7e44e449
AJ		 1865#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1866
1867static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1868{
1869 int i;
7e44e449
AJ		 1870 struct delayed_work *dwork = to_delayed_work(work);
1871 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1872 kvmclock_update_work);
1873 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1874 struct kvm_vcpu *vcpu;
1875
1876 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1878 kvm_vcpu_kick(vcpu);
1879 }
1880}
1881
7e44e449
AJ		 1882static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1883{
1884 struct kvm *kvm = v->kvm;
1885
105b21bb 1886 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1887 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1888 KVMCLOCK_UPDATE_DELAY);
1889}
1890
332967a3
AJ		 1891#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1892
1893static void kvmclock_sync_fn(struct work_struct *work)
1894{
1895 struct delayed_work *dwork = to_delayed_work(work);
1896 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1897 kvmclock_sync_work);
1898 struct kvm *kvm = container_of(ka, struct kvm, arch);
1899
630994b3
MT		 1900 if (!kvmclock_periodic_sync)
1901 return;
1902
332967a3
AJ		 1903 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1904 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1905 KVMCLOCK_SYNC_PERIOD);
1906}
1907
890ca9ae 1908static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1909{
890ca9ae
HY		 1910 u64 mcg_cap = vcpu->arch.mcg_cap;
1911 unsigned bank_num = mcg_cap & 0xff;
1912
15c4a640 1913 switch (msr) {
15c4a640 1914 case MSR_IA32_MCG_STATUS:
890ca9ae 1915 vcpu->arch.mcg_status = data;
15c4a640 1916 break;
c7ac679c 1917 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1918 if (!(mcg_cap & MCG_CTL_P))
1919 return 1;
1920 if (data != 0 && data != ~(u64)0)
1921 return -1;
1922 vcpu->arch.mcg_ctl = data;
1923 break;
1924 default:
1925 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1926 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1927 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1928 /* only 0 or all 1s can be written to IA32_MCi_CTL
1929 * some Linux kernels though clear bit 10 in bank 4 to
1930 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1931 * this to avoid an uncatched #GP in the guest
1932 */
890ca9ae 1933 if ((offset & 0x3) == 0 &&
114be429 1934 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1935 return -1;
1936 vcpu->arch.mce_banks[offset] = data;
1937 break;
1938 }
1939 return 1;
1940 }
1941 return 0;
1942}
1943
ffde22ac
ES		 1944static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1945{
1946 struct kvm *kvm = vcpu->kvm;
1947 int lm = is_long_mode(vcpu);
1948 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1949 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1950 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1951 : kvm->arch.xen_hvm_config.blob_size_32;
1952 u32 page_num = data & ~PAGE_MASK;
1953 u64 page_addr = data & PAGE_MASK;
1954 u8 *page;
1955 int r;
1956
1957 r = -E2BIG;
1958 if (page_num >= blob_size)
1959 goto out;
1960 r = -ENOMEM;
ff5c2c03
SL		 1961 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1962 if (IS_ERR(page)) {
1963 r = PTR_ERR(page);
ffde22ac 1964 goto out;
ff5c2c03 1965 }
54bf36aa 1966 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1967 goto out_free;
1968 r = 0;
1969out_free:
1970 kfree(page);
1971out:
1972 return r;
1973}
1974
344d9588
GN		 1975static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1976{
1977 gpa_t gpa = data & ~0x3f;
1978
4a969980 1979 /* Bits 2:5 are reserved, Should be zero */
6adba527 1980 if (data & 0x3c)
344d9588
GN		 1981 return 1;
1982
1983 vcpu->arch.apf.msr_val = data;
1984
1985 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1986 kvm_clear_async_pf_completion_queue(vcpu);
1987 kvm_async_pf_hash_reset(vcpu);
1988 return 0;
1989 }
1990
8f964525
AH		 1991 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1992 sizeof(u32)))
344d9588
GN		 1993 return 1;
1994
6adba527 1995 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1996 kvm_async_pf_wakeup_all(vcpu);
1997 return 0;
1998}
1999
12f9a48f
GC		 2000static void kvmclock_reset(struct kvm_vcpu *vcpu)
2001{
0b79459b 2002 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2003}
2004
c9aaa895
GC		 2005static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2006{
2007 u64 delta;
2008
2009 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2010 return;
2011
2012 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2013 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2014 vcpu->arch.st.accum_steal = delta;
2015}
2016
2017static void record_steal_time(struct kvm_vcpu *vcpu)
2018{
7cae2bed
MT		 2019 accumulate_steal_time(vcpu);
2020
c9aaa895
GC		 2021 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2022 return;
2023
2024 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2025 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2026 return;
2027
2028 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2029 vcpu->arch.st.steal.version += 2;
2030 vcpu->arch.st.accum_steal = 0;
2031
2032 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2033 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2034}
2035
8fe8ab46 2036int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2037{
5753785f 2038 bool pr = false;
8fe8ab46
WA		 2039 u32 msr = msr_info->index;
2040 u64 data = msr_info->data;
5753785f 2041
15c4a640 2042 switch (msr) {
2e32b719
BP		 2043 case MSR_AMD64_NB_CFG:
2044 case MSR_IA32_UCODE_REV:
2045 case MSR_IA32_UCODE_WRITE:
2046 case MSR_VM_HSAVE_PA:
2047 case MSR_AMD64_PATCH_LOADER:
2048 case MSR_AMD64_BU_CFG2:
2049 break;
2050
15c4a640 2051 case MSR_EFER:
b69e8cae 2052 return set_efer(vcpu, data);
8f1589d9
AP		 2053 case MSR_K7_HWCR:
2054 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2055 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2056 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2057 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2058 if (data != 0) {
a737f256
CD		 2059 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2060 data);
8f1589d9
AP		 2061 return 1;
2062 }
15c4a640 2063 break;
f7c6d140
AP		 2064 case MSR_FAM10H_MMIO_CONF_BASE:
2065 if (data != 0) {
a737f256
CD		 2066 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2067 "0x%llx\n", data);
f7c6d140
AP		 2068 return 1;
2069 }
15c4a640 2070 break;
b5e2fec0
AG		 2071 case MSR_IA32_DEBUGCTLMSR:
2072 if (!data) {
2073 /* We support the non-activated case already */
2074 break;
2075 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2076 /* Values other than LBR and BTF are vendor-specific,
2077 thus reserved and should throw a #GP */
2078 return 1;
2079 }
a737f256
CD		 2080 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2081 __func__, data);
b5e2fec0 2082 break;
9ba075a6 2083 case 0x200 ... 0x2ff:
ff53604b 2084 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2085 case MSR_IA32_APICBASE:
58cb628d 2086 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2087 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2088 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2089 case MSR_IA32_TSCDEADLINE:
2090 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2091 break;
ba904635
WA		 2092 case MSR_IA32_TSC_ADJUST:
2093 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2094 if (!msr_info->host_initiated) {
d913b904 2095 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2096 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2097 }
2098 vcpu->arch.ia32_tsc_adjust_msr = data;
2099 }
2100 break;
15c4a640 2101 case MSR_IA32_MISC_ENABLE:
ad312c7c 2102 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2103 break;
64d60670
PB		 2104 case MSR_IA32_SMBASE:
2105 if (!msr_info->host_initiated)
2106 return 1;
2107 vcpu->arch.smbase = data;
2108 break;
11c6bffa 2109 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2110 case MSR_KVM_WALL_CLOCK:
2111 vcpu->kvm->arch.wall_clock = data;
2112 kvm_write_wall_clock(vcpu->kvm, data);
2113 break;
11c6bffa 2114 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2115 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2116 u64 gpa_offset;
54750f2c
MT		 2117 struct kvm_arch *ka = &vcpu->kvm->arch;
2118
12f9a48f 2119 kvmclock_reset(vcpu);
18068523 2120
54750f2c
MT		 2121 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2122 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2123
2124 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2125 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2126 &vcpu->requests);
2127
2128 ka->boot_vcpu_runs_old_kvmclock = tmp;
2129 }
2130
18068523 2131 vcpu->arch.time = data;
0061d53d 2132 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2133
2134 /* we verify if the enable bit is set... */
2135 if (!(data & 1))
2136 break;
2137
0b79459b 2138 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2139
0b79459b 2140 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2141 &vcpu->arch.pv_time, data & ~1ULL,
2142 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2143 vcpu->arch.pv_time_enabled = false;
2144 else
2145 vcpu->arch.pv_time_enabled = true;
32cad84f 2146
18068523
GOC		 2147 break;
2148 }
344d9588
GN		 2149 case MSR_KVM_ASYNC_PF_EN:
2150 if (kvm_pv_enable_async_pf(vcpu, data))
2151 return 1;
2152 break;
c9aaa895
GC		 2153 case MSR_KVM_STEAL_TIME:
2154
2155 if (unlikely(!sched_info_on()))
2156 return 1;
2157
2158 if (data & KVM_STEAL_RESERVED_MASK)
2159 return 1;
2160
2161 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2162 data & KVM_STEAL_VALID_BITS,
2163 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2164 return 1;
2165
2166 vcpu->arch.st.msr_val = data;
2167
2168 if (!(data & KVM_MSR_ENABLED))
2169 break;
2170
c9aaa895
GC		 2171 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2172
2173 break;
ae7a2a3f
MT		 2174 case MSR_KVM_PV_EOI_EN:
2175 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2176 return 1;
2177 break;
c9aaa895 2178
890ca9ae
HY		 2179 case MSR_IA32_MCG_CTL:
2180 case MSR_IA32_MCG_STATUS:
81760dcc 2181 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2182 return set_msr_mce(vcpu, msr, data);
71db6023 2183
6912ac32
WH		 2184 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2185 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2186 pr = true; /* fall through */
2187 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2188 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2189 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2190 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2191
2192 if (pr || data != 0)
a737f256
CD		 2193 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2194 "0x%x data 0x%llx\n", msr, data);
5753785f 2195 break;
84e0cefa
JS		 2196 case MSR_K7_CLK_CTL:
2197 /*
2198 * Ignore all writes to this no longer documented MSR.
2199 * Writes are only relevant for old K7 processors,
2200 * all pre-dating SVM, but a recommended workaround from
4a969980 2201 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2202 * affected processor models on the command line, hence
2203 * the need to ignore the workaround.
2204 */
2205 break;
55cd8e5a 2206 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2207 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2208 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2209 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2210 return kvm_hv_set_msr_common(vcpu, msr, data,
2211 msr_info->host_initiated);
91c9c3ed 2212 case MSR_IA32_BBL_CR_CTL3:
2213 /* Drop writes to this legacy MSR -- see rdmsr
2214 * counterpart for further detail.
2215 */
a737f256 2216 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2217 break;
2b036c6b
BO		 2218 case MSR_AMD64_OSVW_ID_LENGTH:
2219 if (!guest_cpuid_has_osvw(vcpu))
2220 return 1;
2221 vcpu->arch.osvw.length = data;
2222 break;
2223 case MSR_AMD64_OSVW_STATUS:
2224 if (!guest_cpuid_has_osvw(vcpu))
2225 return 1;
2226 vcpu->arch.osvw.status = data;
2227 break;
15c4a640 2228 default:
ffde22ac
ES		 2229 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2230 return xen_hvm_config(vcpu, data);
c6702c9d 2231 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2232 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2233 if (!ignore_msrs) {
a737f256
CD		 2234 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2235 msr, data);
ed85c068
AP		 2236 return 1;
2237 } else {
a737f256
CD		 2238 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2239 msr, data);
ed85c068
AP		 2240 break;
2241 }
15c4a640
CO		 2242 }
2243 return 0;
2244}
2245EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2246
2247
2248/*
2249 * Reads an msr value (of 'msr_index') into 'pdata'.
2250 * Returns 0 on success, non-0 otherwise.
2251 * Assumes vcpu_load() was already called.
2252 */
609e36d3 2253int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2254{
609e36d3 2255 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2256}
ff651cb6 2257EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2258
890ca9ae 2259static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2260{
2261 u64 data;
890ca9ae
HY		 2262 u64 mcg_cap = vcpu->arch.mcg_cap;
2263 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2264
2265 switch (msr) {
15c4a640
CO		 2266 case MSR_IA32_P5_MC_ADDR:
2267 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2268 data = 0;
2269 break;
15c4a640 2270 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2271 data = vcpu->arch.mcg_cap;
2272 break;
c7ac679c 2273 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2274 if (!(mcg_cap & MCG_CTL_P))
2275 return 1;
2276 data = vcpu->arch.mcg_ctl;
2277 break;
2278 case MSR_IA32_MCG_STATUS:
2279 data = vcpu->arch.mcg_status;
2280 break;
2281 default:
2282 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2283 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2284 u32 offset = msr - MSR_IA32_MC0_CTL;
2285 data = vcpu->arch.mce_banks[offset];
2286 break;
2287 }
2288 return 1;
2289 }
2290 *pdata = data;
2291 return 0;
2292}
2293
609e36d3 2294int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2295{
609e36d3 2296 switch (msr_info->index) {
890ca9ae 2297 case MSR_IA32_PLATFORM_ID:
15c4a640 2298 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2299 case MSR_IA32_DEBUGCTLMSR:
2300 case MSR_IA32_LASTBRANCHFROMIP:
2301 case MSR_IA32_LASTBRANCHTOIP:
2302 case MSR_IA32_LASTINTFROMIP:
2303 case MSR_IA32_LASTINTTOIP:
60af2ecd 2304 case MSR_K8_SYSCFG:
3afb1121
PB		 2305 case MSR_K8_TSEG_ADDR:
2306 case MSR_K8_TSEG_MASK:
60af2ecd 2307 case MSR_K7_HWCR:
61a6bd67 2308 case MSR_VM_HSAVE_PA:
1fdbd48c 2309 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2310 case MSR_AMD64_NB_CFG:
f7c6d140 2311 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2312 case MSR_AMD64_BU_CFG2:
609e36d3 2313 msr_info->data = 0;
15c4a640 2314 break;
6912ac32
WH		 2315 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2316 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2317 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2318 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2319 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2320 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2321 msr_info->data = 0;
5753785f 2322 break;
742bc670 2323 case MSR_IA32_UCODE_REV:
609e36d3 2324 msr_info->data = 0x100000000ULL;
742bc670 2325 break;
9ba075a6 2326 case MSR_MTRRcap:
9ba075a6 2327 case 0x200 ... 0x2ff:
ff53604b 2328 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2329 case 0xcd: /* fsb frequency */
609e36d3 2330 msr_info->data = 3;
15c4a640 2331 break;
7b914098
JS		 2332 /*
2333 * MSR_EBC_FREQUENCY_ID
2334 * Conservative value valid for even the basic CPU models.
2335 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2336 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2337 * and 266MHz for model 3, or 4. Set Core Clock
2338 * Frequency to System Bus Frequency Ratio to 1 (bits
2339 * 31:24) even though these are only valid for CPU
2340 * models > 2, however guests may end up dividing or
2341 * multiplying by zero otherwise.
2342 */
2343 case MSR_EBC_FREQUENCY_ID:
609e36d3 2344 msr_info->data = 1 << 24;
7b914098 2345 break;
15c4a640 2346 case MSR_IA32_APICBASE:
609e36d3 2347 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2348 break;
0105d1a5 2349 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2350 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2351 break;
a3e06bbe 2352 case MSR_IA32_TSCDEADLINE:
609e36d3 2353 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2354 break;
ba904635 2355 case MSR_IA32_TSC_ADJUST:
609e36d3 2356 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2357 break;
15c4a640 2358 case MSR_IA32_MISC_ENABLE:
609e36d3 2359 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2360 break;
64d60670
PB		 2361 case MSR_IA32_SMBASE:
2362 if (!msr_info->host_initiated)
2363 return 1;
2364 msr_info->data = vcpu->arch.smbase;
15c4a640 2365 break;
847f0ad8
AG		 2366 case MSR_IA32_PERF_STATUS:
2367 /* TSC increment by tick */
609e36d3 2368 msr_info->data = 1000ULL;
847f0ad8 2369 /* CPU multiplier */
b0996ae4 2370 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2371 break;
15c4a640 2372 case MSR_EFER:
609e36d3 2373 msr_info->data = vcpu->arch.efer;
15c4a640 2374 break;
18068523 2375 case MSR_KVM_WALL_CLOCK:
11c6bffa 2376 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2377 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2378 break;
2379 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2380 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2381 msr_info->data = vcpu->arch.time;
18068523 2382 break;
344d9588 2383 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2384 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2385 break;
c9aaa895 2386 case MSR_KVM_STEAL_TIME:
609e36d3 2387 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2388 break;
1d92128f 2389 case MSR_KVM_PV_EOI_EN:
609e36d3 2390 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2391 break;
890ca9ae
HY		 2392 case MSR_IA32_P5_MC_ADDR:
2393 case MSR_IA32_P5_MC_TYPE:
2394 case MSR_IA32_MCG_CAP:
2395 case MSR_IA32_MCG_CTL:
2396 case MSR_IA32_MCG_STATUS:
81760dcc 2397 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2398 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2399 case MSR_K7_CLK_CTL:
2400 /*
2401 * Provide expected ramp-up count for K7. All other
2402 * are set to zero, indicating minimum divisors for
2403 * every field.
2404 *
2405 * This prevents guest kernels on AMD host with CPU
2406 * type 6, model 8 and higher from exploding due to
2407 * the rdmsr failing.
2408 */
609e36d3 2409 msr_info->data = 0x20000000;
84e0cefa 2410 break;
55cd8e5a 2411 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2412 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2413 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2414 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2415 return kvm_hv_get_msr_common(vcpu,
2416 msr_info->index, &msr_info->data);
55cd8e5a 2417 break;
91c9c3ed 2418 case MSR_IA32_BBL_CR_CTL3:
2419 /* This legacy MSR exists but isn't fully documented in current
2420 * silicon. It is however accessed by winxp in very narrow
2421 * scenarios where it sets bit #19, itself documented as
2422 * a "reserved" bit. Best effort attempt to source coherent
2423 * read data here should the balance of the register be
2424 * interpreted by the guest:
2425 *
2426 * L2 cache control register 3: 64GB range, 256KB size,
2427 * enabled, latency 0x1, configured
2428 */
609e36d3 2429 msr_info->data = 0xbe702111;
91c9c3ed 2430 break;
2b036c6b
BO		 2431 case MSR_AMD64_OSVW_ID_LENGTH:
2432 if (!guest_cpuid_has_osvw(vcpu))
2433 return 1;
609e36d3 2434 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2435 break;
2436 case MSR_AMD64_OSVW_STATUS:
2437 if (!guest_cpuid_has_osvw(vcpu))
2438 return 1;
609e36d3 2439 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2440 break;
15c4a640 2441 default:
c6702c9d 2442 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2443 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2444 if (!ignore_msrs) {
609e36d3 2445 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2446 return 1;
2447 } else {
609e36d3
PB		 2448 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2449 msr_info->data = 0;
ed85c068
AP		 2450 }
2451 break;
15c4a640 2452 }
15c4a640
CO		 2453 return 0;
2454}
2455EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2456
313a3dc7
CO		 2457/*
2458 * Read or write a bunch of msrs. All parameters are kernel addresses.
2459 *
2460 * @return number of msrs set successfully.
2461 */
2462static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2463 struct kvm_msr_entry *entries,
2464 int (*do_msr)(struct kvm_vcpu *vcpu,
2465 unsigned index, u64 *data))
2466{
f656ce01 2467 int i, idx;
313a3dc7 2468
f656ce01 2469 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2470 for (i = 0; i < msrs->nmsrs; ++i)
2471 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2472 break;
f656ce01 2473 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2474
313a3dc7
CO		 2475 return i;
2476}
2477
2478/*
2479 * Read or write a bunch of msrs. Parameters are user addresses.
2480 *
2481 * @return number of msrs set successfully.
2482 */
2483static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2484 int (*do_msr)(struct kvm_vcpu *vcpu,
2485 unsigned index, u64 *data),
2486 int writeback)
2487{
2488 struct kvm_msrs msrs;
2489 struct kvm_msr_entry *entries;
2490 int r, n;
2491 unsigned size;
2492
2493 r = -EFAULT;
2494 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2495 goto out;
2496
2497 r = -E2BIG;
2498 if (msrs.nmsrs >= MAX_IO_MSRS)
2499 goto out;
2500
313a3dc7 2501 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2502 entries = memdup_user(user_msrs->entries, size);
2503 if (IS_ERR(entries)) {
2504 r = PTR_ERR(entries);
313a3dc7 2505 goto out;
ff5c2c03 2506 }
313a3dc7
CO		 2507
2508 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2509 if (r < 0)
2510 goto out_free;
2511
2512 r = -EFAULT;
2513 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2514 goto out_free;
2515
2516 r = n;
2517
2518out_free:
7a73c028 2519 kfree(entries);
313a3dc7
CO		 2520out:
2521 return r;
2522}
2523
784aa3d7 2524int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2525{
2526 int r;
2527
2528 switch (ext) {
2529 case KVM_CAP_IRQCHIP:
2530 case KVM_CAP_HLT:
2531 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2532 case KVM_CAP_SET_TSS_ADDR:
07716717 2533 case KVM_CAP_EXT_CPUID:
9c15bb1d 2534 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2535 case KVM_CAP_CLOCKSOURCE:
7837699f 2536 case KVM_CAP_PIT:
a28e4f5a 2537 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2538 case KVM_CAP_MP_STATE:
ed848624 2539 case KVM_CAP_SYNC_MMU:
a355c85c 2540 case KVM_CAP_USER_NMI:
52d939a0 2541 case KVM_CAP_REINJECT_CONTROL:
4925663a 2542 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2543 case KVM_CAP_IOEVENTFD:
f848a5a8 2544 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2545 case KVM_CAP_PIT2:
e9f42757 2546 case KVM_CAP_PIT_STATE2:
b927a3ce 2547 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2548 case KVM_CAP_XEN_HVM:
afbcf7ab 2549 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2550 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2551 case KVM_CAP_HYPERV:
10388a07 2552 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2553 case KVM_CAP_HYPERV_SPIN:
5c919412 2554 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2555 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2556 case KVM_CAP_DEBUGREGS:
d2be1651 2557 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2558 case KVM_CAP_XSAVE:
344d9588 2559 case KVM_CAP_ASYNC_PF:
92a1f12d 2560 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2561 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2562 case KVM_CAP_READONLY_MEM:
5f66b620 2563 case KVM_CAP_HYPERV_TIME:
100943c5 2564 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2565 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2566 case KVM_CAP_ENABLE_CAP_VM:
2567 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2568 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2569 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2570#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2571 case KVM_CAP_ASSIGN_DEV_IRQ:
2572 case KVM_CAP_PCI_2_3:
2573#endif
018d00d2
ZX		 2574 r = 1;
2575 break;
6d396b55
PB		 2576 case KVM_CAP_X86_SMM:
2577 /* SMBASE is usually relocated above 1M on modern chipsets,
2578 * and SMM handlers might indeed rely on 4G segment limits,
2579 * so do not report SMM to be available if real mode is
2580 * emulated via vm86 mode. Still, do not go to great lengths
2581 * to avoid userspace's usage of the feature, because it is a
2582 * fringe case that is not enabled except via specific settings
2583 * of the module parameters.
2584 */
2585 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2586 break;
542472b5
LV		 2587 case KVM_CAP_COALESCED_MMIO:
2588 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2589 break;
774ead3a
AK		 2590 case KVM_CAP_VAPIC:
2591 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2592 break;
f725230a 2593 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2594 r = KVM_SOFT_MAX_VCPUS;
2595 break;
2596 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2597 r = KVM_MAX_VCPUS;
2598 break;
a988b910 2599 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2600 r = KVM_USER_MEM_SLOTS;
a988b910 2601 break;
a68a6a72
MT		 2602 case KVM_CAP_PV_MMU: /* obsolete */
2603 r = 0;
2f333bcb 2604 break;
4cee4b72 2605#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2606 case KVM_CAP_IOMMU:
a1b60c1c 2607 r = iommu_present(&pci_bus_type);
62c476c7 2608 break;
4cee4b72 2609#endif
890ca9ae
HY		 2610 case KVM_CAP_MCE:
2611 r = KVM_MAX_MCE_BANKS;
2612 break;
2d5b5a66
SY		 2613 case KVM_CAP_XCRS:
2614 r = cpu_has_xsave;
2615 break;
92a1f12d
JR		 2616 case KVM_CAP_TSC_CONTROL:
2617 r = kvm_has_tsc_control;
2618 break;
018d00d2
ZX		 2619 default:
2620 r = 0;
2621 break;
2622 }
2623 return r;
2624
2625}
2626
043405e1
CO		 2627long kvm_arch_dev_ioctl(struct file *filp,
2628 unsigned int ioctl, unsigned long arg)
2629{
2630 void __user *argp = (void __user *)arg;
2631 long r;
2632
2633 switch (ioctl) {
2634 case KVM_GET_MSR_INDEX_LIST: {
2635 struct kvm_msr_list __user *user_msr_list = argp;
2636 struct kvm_msr_list msr_list;
2637 unsigned n;
2638
2639 r = -EFAULT;
2640 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2641 goto out;
2642 n = msr_list.nmsrs;
62ef68bb 2643 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2644 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2645 goto out;
2646 r = -E2BIG;
e125e7b6 2647 if (n < msr_list.nmsrs)
043405e1
CO		 2648 goto out;
2649 r = -EFAULT;
2650 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2651 num_msrs_to_save * sizeof(u32)))
2652 goto out;
e125e7b6 2653 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2654 &emulated_msrs,
62ef68bb 2655 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2656 goto out;
2657 r = 0;
2658 break;
2659 }
9c15bb1d
BP		 2660 case KVM_GET_SUPPORTED_CPUID:
2661 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2662 struct kvm_cpuid2 __user *cpuid_arg = argp;
2663 struct kvm_cpuid2 cpuid;
2664
2665 r = -EFAULT;
2666 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2667 goto out;
9c15bb1d
BP		 2668
2669 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2670 ioctl);
674eea0f
AK		 2671 if (r)
2672 goto out;
2673
2674 r = -EFAULT;
2675 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2676 goto out;
2677 r = 0;
2678 break;
2679 }
890ca9ae
HY		 2680 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2681 u64 mce_cap;
2682
2683 mce_cap = KVM_MCE_CAP_SUPPORTED;
2684 r = -EFAULT;
2685 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2686 goto out;
2687 r = 0;
2688 break;
2689 }
043405e1
CO		 2690 default:
2691 r = -EINVAL;
2692 }
2693out:
2694 return r;
2695}
2696
f5f48ee1
SY		 2697static void wbinvd_ipi(void *garbage)
2698{
2699 wbinvd();
2700}
2701
2702static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2703{
e0f0bbc5 2704 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2705}
2706
2860c4b1
PB		 2707static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2708{
2709 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2710}
2711
313a3dc7
CO		 2712void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2713{
f5f48ee1
SY		 2714 /* Address WBINVD may be executed by guest */
2715 if (need_emulate_wbinvd(vcpu)) {
2716 if (kvm_x86_ops->has_wbinvd_exit())
2717 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2718 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2719 smp_call_function_single(vcpu->cpu,
2720 wbinvd_ipi, NULL, 1);
2721 }
2722
313a3dc7 2723 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2724
0dd6a6ed
ZA		 2725 /* Apply any externally detected TSC adjustments (due to suspend) */
2726 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2727 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2728 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2729 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2730 }
8f6055cb 2731
48434c20 2732 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2733 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2734 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2735 if (tsc_delta < 0)
2736 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2737 if (check_tsc_unstable()) {
07c1419a 2738 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2739 vcpu->arch.last_guest_tsc);
2740 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2741 vcpu->arch.tsc_catchup = 1;
c285545f 2742 }
d98d07ca
MT		 2743 /*
2744 * On a host with synchronized TSC, there is no need to update
2745 * kvmclock on vcpu->cpu migration
2746 */
2747 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2748 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2749 if (vcpu->cpu != cpu)
2750 kvm_migrate_timers(vcpu);
e48672fa 2751 vcpu->cpu = cpu;
6b7d7e76 2752 }
c9aaa895 2753
c9aaa895 2754 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2755}
2756
2757void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2758{
02daab21 2759 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2760 kvm_put_guest_fpu(vcpu);
4ea1636b 2761 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2762}
2763
313a3dc7
CO		 2764static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2765 struct kvm_lapic_state *s)
2766{
d62caabb
AS		 2767 if (vcpu->arch.apicv_active)
2768 kvm_x86_ops->sync_pir_to_irr(vcpu);
2769
ad312c7c 2770 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2771
2772 return 0;
2773}
2774
2775static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2776 struct kvm_lapic_state *s)
2777{
64eb0620 2778 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2779 update_cr8_intercept(vcpu);
313a3dc7
CO		 2780
2781 return 0;
2782}
2783
127a457a
MG		 2784static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2785{
2786 return (!lapic_in_kernel(vcpu) ||
2787 kvm_apic_accept_pic_intr(vcpu));
2788}
2789
782d422b
MG		 2790/*
2791 * if userspace requested an interrupt window, check that the
2792 * interrupt window is open.
2793 *
2794 * No need to exit to userspace if we already have an interrupt queued.
2795 */
2796static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2797{
2798 return kvm_arch_interrupt_allowed(vcpu) &&
2799 !kvm_cpu_has_interrupt(vcpu) &&
2800 !kvm_event_needs_reinjection(vcpu) &&
2801 kvm_cpu_accept_dm_intr(vcpu);
2802}
2803
f77bc6a4
ZX		 2804static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2805 struct kvm_interrupt *irq)
2806{
02cdb50f 2807 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2808 return -EINVAL;
1c1a9ce9
SR		 2809
2810 if (!irqchip_in_kernel(vcpu->kvm)) {
2811 kvm_queue_interrupt(vcpu, irq->irq, false);
2812 kvm_make_request(KVM_REQ_EVENT, vcpu);
2813 return 0;
2814 }
2815
2816 /*
2817 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2818 * fail for in-kernel 8259.
2819 */
2820 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2821 return -ENXIO;
f77bc6a4 2822
1c1a9ce9
SR		 2823 if (vcpu->arch.pending_external_vector != -1)
2824 return -EEXIST;
f77bc6a4 2825
1c1a9ce9 2826 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2827 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2828 return 0;
2829}
2830
c4abb7c9
JK		 2831static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2832{
c4abb7c9 2833 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2834
2835 return 0;
2836}
2837
f077825a
PB		 2838static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2839{
64d60670
PB		 2840 kvm_make_request(KVM_REQ_SMI, vcpu);
2841
f077825a
PB		 2842 return 0;
2843}
2844
b209749f
AK		 2845static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2846 struct kvm_tpr_access_ctl *tac)
2847{
2848 if (tac->flags)
2849 return -EINVAL;
2850 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2851 return 0;
2852}
2853
890ca9ae
HY		 2854static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2855 u64 mcg_cap)
2856{
2857 int r;
2858 unsigned bank_num = mcg_cap & 0xff, bank;
2859
2860 r = -EINVAL;
a9e38c3e 2861 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2862 goto out;
2863 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2864 goto out;
2865 r = 0;
2866 vcpu->arch.mcg_cap = mcg_cap;
2867 /* Init IA32_MCG_CTL to all 1s */
2868 if (mcg_cap & MCG_CTL_P)
2869 vcpu->arch.mcg_ctl = ~(u64)0;
2870 /* Init IA32_MCi_CTL to all 1s */
2871 for (bank = 0; bank < bank_num; bank++)
2872 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2873out:
2874 return r;
2875}
2876
2877static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2878 struct kvm_x86_mce *mce)
2879{
2880 u64 mcg_cap = vcpu->arch.mcg_cap;
2881 unsigned bank_num = mcg_cap & 0xff;
2882 u64 *banks = vcpu->arch.mce_banks;
2883
2884 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2885 return -EINVAL;
2886 /*
2887 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2888 * reporting is disabled
2889 */
2890 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2891 vcpu->arch.mcg_ctl != ~(u64)0)
2892 return 0;
2893 banks += 4 * mce->bank;
2894 /*
2895 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2896 * reporting is disabled for the bank
2897 */
2898 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2899 return 0;
2900 if (mce->status & MCI_STATUS_UC) {
2901 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2902 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2903 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2904 return 0;
2905 }
2906 if (banks[1] & MCI_STATUS_VAL)
2907 mce->status |= MCI_STATUS_OVER;
2908 banks[2] = mce->addr;
2909 banks[3] = mce->misc;
2910 vcpu->arch.mcg_status = mce->mcg_status;
2911 banks[1] = mce->status;
2912 kvm_queue_exception(vcpu, MC_VECTOR);
2913 } else if (!(banks[1] & MCI_STATUS_VAL)
2914 || !(banks[1] & MCI_STATUS_UC)) {
2915 if (banks[1] & MCI_STATUS_VAL)
2916 mce->status |= MCI_STATUS_OVER;
2917 banks[2] = mce->addr;
2918 banks[3] = mce->misc;
2919 banks[1] = mce->status;
2920 } else
2921 banks[1] |= MCI_STATUS_OVER;
2922 return 0;
2923}
2924
3cfc3092
JK		 2925static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2926 struct kvm_vcpu_events *events)
2927{
7460fb4a 2928 process_nmi(vcpu);
03b82a30
JK		 2929 events->exception.injected =
2930 vcpu->arch.exception.pending &&
2931 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2932 events->exception.nr = vcpu->arch.exception.nr;
2933 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2934 events->exception.pad = 0;
3cfc3092
JK		 2935 events->exception.error_code = vcpu->arch.exception.error_code;
2936
03b82a30
JK		 2937 events->interrupt.injected =
2938 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2939 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2940 events->interrupt.soft = 0;
37ccdcbe 2941 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2942
2943 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2944 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2945 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2946 events->nmi.pad = 0;
3cfc3092 2947
66450a21 2948 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2949
f077825a
PB		 2950 events->smi.smm = is_smm(vcpu);
2951 events->smi.pending = vcpu->arch.smi_pending;
2952 events->smi.smm_inside_nmi =
2953 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2954 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2955
dab4b911 2956 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2957 | KVM_VCPUEVENT_VALID_SHADOW
2958 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2959 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2960}
2961
2962static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2963 struct kvm_vcpu_events *events)
2964{
dab4b911 2965 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2966 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2967 | KVM_VCPUEVENT_VALID_SHADOW
2968 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2969 return -EINVAL;
2970
7460fb4a 2971 process_nmi(vcpu);
3cfc3092
JK		 2972 vcpu->arch.exception.pending = events->exception.injected;
2973 vcpu->arch.exception.nr = events->exception.nr;
2974 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2975 vcpu->arch.exception.error_code = events->exception.error_code;
2976
2977 vcpu->arch.interrupt.pending = events->interrupt.injected;
2978 vcpu->arch.interrupt.nr = events->interrupt.nr;
2979 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2980 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2981 kvm_x86_ops->set_interrupt_shadow(vcpu,
2982 events->interrupt.shadow);
3cfc3092
JK		 2983
2984 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2985 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2986 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2987 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2988
66450a21 2989 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 2990 lapic_in_kernel(vcpu))
66450a21 2991 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2992
f077825a
PB		 2993 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2994 if (events->smi.smm)
2995 vcpu->arch.hflags |= HF_SMM_MASK;
2996 else
2997 vcpu->arch.hflags &= ~HF_SMM_MASK;
2998 vcpu->arch.smi_pending = events->smi.pending;
2999 if (events->smi.smm_inside_nmi)
3000 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3001 else
3002 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3003 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3004 if (events->smi.latched_init)
3005 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3006 else
3007 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3008 }
3009 }
3010
3842d135
AK		 3011 kvm_make_request(KVM_REQ_EVENT, vcpu);
3012
3cfc3092
JK		 3013 return 0;
3014}
3015
a1efbe77
JK		 3016static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3017 struct kvm_debugregs *dbgregs)
3018{
73aaf249
JK		 3019 unsigned long val;
3020
a1efbe77 3021 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3022 kvm_get_dr(vcpu, 6, &val);
73aaf249 3023 dbgregs->dr6 = val;
a1efbe77
JK		 3024 dbgregs->dr7 = vcpu->arch.dr7;
3025 dbgregs->flags = 0;
97e69aa6 3026 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3027}
3028
3029static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3030 struct kvm_debugregs *dbgregs)
3031{
3032 if (dbgregs->flags)
3033 return -EINVAL;
3034
a1efbe77 3035 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3036 kvm_update_dr0123(vcpu);
a1efbe77 3037 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3038 kvm_update_dr6(vcpu);
a1efbe77 3039 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3040 kvm_update_dr7(vcpu);
a1efbe77 3041
a1efbe77
JK		 3042 return 0;
3043}
3044
df1daba7
PB		 3045#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3046
3047static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3048{
c47ada30 3049 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3050 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3051 u64 valid;
3052
3053 /*
3054 * Copy legacy XSAVE area, to avoid complications with CPUID
3055 * leaves 0 and 1 in the loop below.
3056 */
3057 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3058
3059 /* Set XSTATE_BV */
3060 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3061
3062 /*
3063 * Copy each region from the possibly compacted offset to the
3064 * non-compacted offset.
3065 */
d91cab78 3066 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3067 while (valid) {
3068 u64 feature = valid & -valid;
3069 int index = fls64(feature) - 1;
3070 void *src = get_xsave_addr(xsave, feature);
3071
3072 if (src) {
3073 u32 size, offset, ecx, edx;
3074 cpuid_count(XSTATE_CPUID, index,
3075 &size, &offset, &ecx, &edx);
3076 memcpy(dest + offset, src, size);
3077 }
3078
3079 valid -= feature;
3080 }
3081}
3082
3083static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3084{
c47ada30 3085 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3086 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3087 u64 valid;
3088
3089 /*
3090 * Copy legacy XSAVE area, to avoid complications with CPUID
3091 * leaves 0 and 1 in the loop below.
3092 */
3093 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3094
3095 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3096 xsave->header.xfeatures = xstate_bv;
df1daba7 3097 if (cpu_has_xsaves)
3a54450b 3098 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3099
3100 /*
3101 * Copy each region from the non-compacted offset to the
3102 * possibly compacted offset.
3103 */
d91cab78 3104 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3105 while (valid) {
3106 u64 feature = valid & -valid;
3107 int index = fls64(feature) - 1;
3108 void *dest = get_xsave_addr(xsave, feature);
3109
3110 if (dest) {
3111 u32 size, offset, ecx, edx;
3112 cpuid_count(XSTATE_CPUID, index,
3113 &size, &offset, &ecx, &edx);
3114 memcpy(dest, src + offset, size);
ee4100da 3115 }
df1daba7
PB		 3116
3117 valid -= feature;
3118 }
3119}
3120
2d5b5a66
SY		 3121static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3122 struct kvm_xsave *guest_xsave)
3123{
4344ee98 3124 if (cpu_has_xsave) {
df1daba7
PB		 3125 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3126 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3127 } else {
2d5b5a66 3128 memcpy(guest_xsave->region,
7366ed77 3129 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3130 sizeof(struct fxregs_state));
2d5b5a66 3131 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3132 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3133 }
3134}
3135
3136static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3137 struct kvm_xsave *guest_xsave)
3138{
3139 u64 xstate_bv =
3140 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3141
d7876f1b
PB		 3142 if (cpu_has_xsave) {
3143 /*
3144 * Here we allow setting states that are not present in
3145 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3146 * with old userspace.
3147 */
4ff41732 3148 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3149 return -EINVAL;
df1daba7 3150 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3151 } else {
d91cab78 3152 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3153 return -EINVAL;
7366ed77 3154 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3155 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3156 }
3157 return 0;
3158}
3159
3160static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3161 struct kvm_xcrs *guest_xcrs)
3162{
3163 if (!cpu_has_xsave) {
3164 guest_xcrs->nr_xcrs = 0;
3165 return;
3166 }
3167
3168 guest_xcrs->nr_xcrs = 1;
3169 guest_xcrs->flags = 0;
3170 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3171 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3172}
3173
3174static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3175 struct kvm_xcrs *guest_xcrs)
3176{
3177 int i, r = 0;
3178
3179 if (!cpu_has_xsave)
3180 return -EINVAL;
3181
3182 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3183 return -EINVAL;
3184
3185 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3186 /* Only support XCR0 currently */
c67a04cb 3187 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3188 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3189 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3190 break;
3191 }
3192 if (r)
3193 r = -EINVAL;
3194 return r;
3195}
3196
1c0b28c2
EM		 3197/*
3198 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3199 * stopped by the hypervisor. This function will be called from the host only.
3200 * EINVAL is returned when the host attempts to set the flag for a guest that
3201 * does not support pv clocks.
3202 */
3203static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3204{
0b79459b 3205 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3206 return -EINVAL;
51d59c6b 3207 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3208 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3209 return 0;
3210}
3211
5c919412
AS		 3212static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3213 struct kvm_enable_cap *cap)
3214{
3215 if (cap->flags)
3216 return -EINVAL;
3217
3218 switch (cap->cap) {
3219 case KVM_CAP_HYPERV_SYNIC:
3220 return kvm_hv_activate_synic(vcpu);
3221 default:
3222 return -EINVAL;
3223 }
3224}
3225
313a3dc7
CO		 3226long kvm_arch_vcpu_ioctl(struct file *filp,
3227 unsigned int ioctl, unsigned long arg)
3228{
3229 struct kvm_vcpu *vcpu = filp->private_data;
3230 void __user *argp = (void __user *)arg;
3231 int r;
d1ac91d8
AK		 3232 union {
3233 struct kvm_lapic_state *lapic;
3234 struct kvm_xsave *xsave;
3235 struct kvm_xcrs *xcrs;
3236 void *buffer;
3237 } u;
3238
3239 u.buffer = NULL;
313a3dc7
CO		 3240 switch (ioctl) {
3241 case KVM_GET_LAPIC: {
2204ae3c 3242 r = -EINVAL;
bce87cce 3243 if (!lapic_in_kernel(vcpu))
2204ae3c 3244 goto out;
d1ac91d8 3245 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3246
b772ff36 3247 r = -ENOMEM;
d1ac91d8 3248 if (!u.lapic)
b772ff36 3249 goto out;
d1ac91d8 3250 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3251 if (r)
3252 goto out;
3253 r = -EFAULT;
d1ac91d8 3254 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3255 goto out;
3256 r = 0;
3257 break;
3258 }
3259 case KVM_SET_LAPIC: {
2204ae3c 3260 r = -EINVAL;
bce87cce 3261 if (!lapic_in_kernel(vcpu))
2204ae3c 3262 goto out;
ff5c2c03 3263 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3264 if (IS_ERR(u.lapic))
3265 return PTR_ERR(u.lapic);
ff5c2c03 3266
d1ac91d8 3267 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3268 break;
3269 }
f77bc6a4
ZX		 3270 case KVM_INTERRUPT: {
3271 struct kvm_interrupt irq;
3272
3273 r = -EFAULT;
3274 if (copy_from_user(&irq, argp, sizeof irq))
3275 goto out;
3276 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3277 break;
3278 }
c4abb7c9
JK		 3279 case KVM_NMI: {
3280 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3281 break;
3282 }
f077825a
PB		 3283 case KVM_SMI: {
3284 r = kvm_vcpu_ioctl_smi(vcpu);
3285 break;
3286 }
313a3dc7
CO		 3287 case KVM_SET_CPUID: {
3288 struct kvm_cpuid __user *cpuid_arg = argp;
3289 struct kvm_cpuid cpuid;
3290
3291 r = -EFAULT;
3292 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3293 goto out;
3294 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3295 break;
3296 }
07716717
DK		 3297 case KVM_SET_CPUID2: {
3298 struct kvm_cpuid2 __user *cpuid_arg = argp;
3299 struct kvm_cpuid2 cpuid;
3300
3301 r = -EFAULT;
3302 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3303 goto out;
3304 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3305 cpuid_arg->entries);
07716717
DK		 3306 break;
3307 }
3308 case KVM_GET_CPUID2: {
3309 struct kvm_cpuid2 __user *cpuid_arg = argp;
3310 struct kvm_cpuid2 cpuid;
3311
3312 r = -EFAULT;
3313 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3314 goto out;
3315 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3316 cpuid_arg->entries);
07716717
DK		 3317 if (r)
3318 goto out;
3319 r = -EFAULT;
3320 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3321 goto out;
3322 r = 0;
3323 break;
3324 }
313a3dc7 3325 case KVM_GET_MSRS:
609e36d3 3326 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3327 break;
3328 case KVM_SET_MSRS:
3329 r = msr_io(vcpu, argp, do_set_msr, 0);
3330 break;
b209749f
AK		 3331 case KVM_TPR_ACCESS_REPORTING: {
3332 struct kvm_tpr_access_ctl tac;
3333
3334 r = -EFAULT;
3335 if (copy_from_user(&tac, argp, sizeof tac))
3336 goto out;
3337 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3338 if (r)
3339 goto out;
3340 r = -EFAULT;
3341 if (copy_to_user(argp, &tac, sizeof tac))
3342 goto out;
3343 r = 0;
3344 break;
3345 };
b93463aa
AK		 3346 case KVM_SET_VAPIC_ADDR: {
3347 struct kvm_vapic_addr va;
3348
3349 r = -EINVAL;
35754c98 3350 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3351 goto out;
3352 r = -EFAULT;
3353 if (copy_from_user(&va, argp, sizeof va))
3354 goto out;
fda4e2e8 3355 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3356 break;
3357 }
890ca9ae
HY		 3358 case KVM_X86_SETUP_MCE: {
3359 u64 mcg_cap;
3360
3361 r = -EFAULT;
3362 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3363 goto out;
3364 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3365 break;
3366 }
3367 case KVM_X86_SET_MCE: {
3368 struct kvm_x86_mce mce;
3369
3370 r = -EFAULT;
3371 if (copy_from_user(&mce, argp, sizeof mce))
3372 goto out;
3373 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3374 break;
3375 }
3cfc3092
JK		 3376 case KVM_GET_VCPU_EVENTS: {
3377 struct kvm_vcpu_events events;
3378
3379 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3380
3381 r = -EFAULT;
3382 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3383 break;
3384 r = 0;
3385 break;
3386 }
3387 case KVM_SET_VCPU_EVENTS: {
3388 struct kvm_vcpu_events events;
3389
3390 r = -EFAULT;
3391 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3392 break;
3393
3394 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3395 break;
3396 }
a1efbe77
JK		 3397 case KVM_GET_DEBUGREGS: {
3398 struct kvm_debugregs dbgregs;
3399
3400 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3401
3402 r = -EFAULT;
3403 if (copy_to_user(argp, &dbgregs,
3404 sizeof(struct kvm_debugregs)))
3405 break;
3406 r = 0;
3407 break;
3408 }
3409 case KVM_SET_DEBUGREGS: {
3410 struct kvm_debugregs dbgregs;
3411
3412 r = -EFAULT;
3413 if (copy_from_user(&dbgregs, argp,
3414 sizeof(struct kvm_debugregs)))
3415 break;
3416
3417 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3418 break;
3419 }
2d5b5a66 3420 case KVM_GET_XSAVE: {
d1ac91d8 3421 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3422 r = -ENOMEM;
d1ac91d8 3423 if (!u.xsave)
2d5b5a66
SY		 3424 break;
3425
d1ac91d8 3426 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3427
3428 r = -EFAULT;
d1ac91d8 3429 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3430 break;
3431 r = 0;
3432 break;
3433 }
3434 case KVM_SET_XSAVE: {
ff5c2c03 3435 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3436 if (IS_ERR(u.xsave))
3437 return PTR_ERR(u.xsave);
2d5b5a66 3438
d1ac91d8 3439 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3440 break;
3441 }
3442 case KVM_GET_XCRS: {
d1ac91d8 3443 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3444 r = -ENOMEM;
d1ac91d8 3445 if (!u.xcrs)
2d5b5a66
SY		 3446 break;
3447
d1ac91d8 3448 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3449
3450 r = -EFAULT;
d1ac91d8 3451 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3452 sizeof(struct kvm_xcrs)))
3453 break;
3454 r = 0;
3455 break;
3456 }
3457 case KVM_SET_XCRS: {
ff5c2c03 3458 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3459 if (IS_ERR(u.xcrs))
3460 return PTR_ERR(u.xcrs);
2d5b5a66 3461
d1ac91d8 3462 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3463 break;
3464 }
92a1f12d
JR		 3465 case KVM_SET_TSC_KHZ: {
3466 u32 user_tsc_khz;
3467
3468 r = -EINVAL;
92a1f12d
JR		 3469 user_tsc_khz = (u32)arg;
3470
3471 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3472 goto out;
3473
cc578287
ZA		 3474 if (user_tsc_khz == 0)
3475 user_tsc_khz = tsc_khz;
3476
381d585c
HZ		 3477 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3478 r = 0;
92a1f12d 3479
92a1f12d
JR		 3480 goto out;
3481 }
3482 case KVM_GET_TSC_KHZ: {
cc578287 3483 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3484 goto out;
3485 }
1c0b28c2
EM		 3486 case KVM_KVMCLOCK_CTRL: {
3487 r = kvm_set_guest_paused(vcpu);
3488 goto out;
3489 }
5c919412
AS		 3490 case KVM_ENABLE_CAP: {
3491 struct kvm_enable_cap cap;
3492
3493 r = -EFAULT;
3494 if (copy_from_user(&cap, argp, sizeof(cap)))
3495 goto out;
3496 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3497 break;
3498 }
313a3dc7
CO		 3499 default:
3500 r = -EINVAL;
3501 }
3502out:
d1ac91d8 3503 kfree(u.buffer);
313a3dc7
CO		 3504 return r;
3505}
3506
5b1c1493
CO		 3507int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3508{
3509 return VM_FAULT_SIGBUS;
3510}
3511
1fe779f8
CO		 3512static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3513{
3514 int ret;
3515
3516 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3517 return -EINVAL;
1fe779f8
CO		 3518 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3519 return ret;
3520}
3521
b927a3ce
SY		 3522static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3523 u64 ident_addr)
3524{
3525 kvm->arch.ept_identity_map_addr = ident_addr;
3526 return 0;
3527}
3528
1fe779f8
CO		 3529static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3530 u32 kvm_nr_mmu_pages)
3531{
3532 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3533 return -EINVAL;
3534
79fac95e 3535 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3536
3537 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3538 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3539
79fac95e 3540 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3541 return 0;
3542}
3543
3544static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3545{
39de71ec 3546 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3547}
3548
1fe779f8
CO		 3549static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3550{
3551 int r;
3552
3553 r = 0;
3554 switch (chip->chip_id) {
3555 case KVM_IRQCHIP_PIC_MASTER:
3556 memcpy(&chip->chip.pic,
3557 &pic_irqchip(kvm)->pics[0],
3558 sizeof(struct kvm_pic_state));
3559 break;
3560 case KVM_IRQCHIP_PIC_SLAVE:
3561 memcpy(&chip->chip.pic,
3562 &pic_irqchip(kvm)->pics[1],
3563 sizeof(struct kvm_pic_state));
3564 break;
3565 case KVM_IRQCHIP_IOAPIC:
eba0226b 3566 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3567 break;
3568 default:
3569 r = -EINVAL;
3570 break;
3571 }
3572 return r;
3573}
3574
3575static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3576{
3577 int r;
3578
3579 r = 0;
3580 switch (chip->chip_id) {
3581 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3582 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3583 memcpy(&pic_irqchip(kvm)->pics[0],
3584 &chip->chip.pic,
3585 sizeof(struct kvm_pic_state));
f4f51050 3586 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3587 break;
3588 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3589 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3590 memcpy(&pic_irqchip(kvm)->pics[1],
3591 &chip->chip.pic,
3592 sizeof(struct kvm_pic_state));
f4f51050 3593 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3594 break;
3595 case KVM_IRQCHIP_IOAPIC:
eba0226b 3596 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3597 break;
3598 default:
3599 r = -EINVAL;
3600 break;
3601 }
3602 kvm_pic_update_irq(pic_irqchip(kvm));
3603 return r;
3604}
3605
e0f63cb9
SY		 3606static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3607{
34f3941c
RK		 3608 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3609
3610 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3611
3612 mutex_lock(&kps->lock);
3613 memcpy(ps, &kps->channels, sizeof(*ps));
3614 mutex_unlock(&kps->lock);
2da29bcc 3615 return 0;
e0f63cb9
SY		 3616}
3617
3618static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3619{
0185604c 3620 int i;
09edea72
RK		 3621 struct kvm_pit *pit = kvm->arch.vpit;
3622
3623 mutex_lock(&pit->pit_state.lock);
34f3941c 3624 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3625 for (i = 0; i < 3; i++)
09edea72
RK		 3626 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3627 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3628 return 0;
e9f42757
BK		 3629}
3630
3631static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3632{
e9f42757
BK		 3633 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3634 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3635 sizeof(ps->channels));
3636 ps->flags = kvm->arch.vpit->pit_state.flags;
3637 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3638 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3639 return 0;
e9f42757
BK		 3640}
3641
3642static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3643{
2da29bcc 3644 int start = 0;
0185604c 3645 int i;
e9f42757 3646 u32 prev_legacy, cur_legacy;
09edea72
RK		 3647 struct kvm_pit *pit = kvm->arch.vpit;
3648
3649 mutex_lock(&pit->pit_state.lock);
3650 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3651 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3652 if (!prev_legacy && cur_legacy)
3653 start = 1;
09edea72
RK		 3654 memcpy(&pit->pit_state.channels, &ps->channels,
3655 sizeof(pit->pit_state.channels));
3656 pit->pit_state.flags = ps->flags;
0185604c 3657 for (i = 0; i < 3; i++)
09edea72 3658 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3659 start && i == 0);
09edea72 3660 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3661 return 0;
e0f63cb9
SY		 3662}
3663
52d939a0
MT		 3664static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3665 struct kvm_reinject_control *control)
3666{
71474e2f
RK		 3667 struct kvm_pit *pit = kvm->arch.vpit;
3668
3669 if (!pit)
52d939a0 3670 return -ENXIO;
b39c90b6 3671
71474e2f
RK		 3672 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3673 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3674 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3675 */
3676 mutex_lock(&pit->pit_state.lock);
3677 kvm_pit_set_reinject(pit, control->pit_reinject);
3678 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3679
52d939a0
MT		 3680 return 0;
3681}
3682
95d4c16c 3683/**
60c34612
TY		 3684 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3685 * @kvm: kvm instance
3686 * @log: slot id and address to which we copy the log
95d4c16c 3687 *
e108ff2f
PB		 3688 * Steps 1-4 below provide general overview of dirty page logging. See
3689 * kvm_get_dirty_log_protect() function description for additional details.
3690 *
3691 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3692 * always flush the TLB (step 4) even if previous step failed and the dirty
3693 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3694 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3695 * writes will be marked dirty for next log read.
95d4c16c 3696 *
60c34612
TY		 3697 * 1. Take a snapshot of the bit and clear it if needed.
3698 * 2. Write protect the corresponding page.
e108ff2f
PB		 3699 * 3. Copy the snapshot to the userspace.
3700 * 4. Flush TLB's if needed.
5bb064dc 3701 */
60c34612 3702int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3703{
60c34612 3704 bool is_dirty = false;
e108ff2f 3705 int r;
5bb064dc 3706
79fac95e 3707 mutex_lock(&kvm->slots_lock);
5bb064dc 3708
88178fd4
KH		 3709 /*
3710 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3711 */
3712 if (kvm_x86_ops->flush_log_dirty)
3713 kvm_x86_ops->flush_log_dirty(kvm);
3714
e108ff2f 3715 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3716
3717 /*
3718 * All the TLBs can be flushed out of mmu lock, see the comments in
3719 * kvm_mmu_slot_remove_write_access().
3720 */
e108ff2f 3721 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3722 if (is_dirty)
3723 kvm_flush_remote_tlbs(kvm);
3724
79fac95e 3725 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3726 return r;
3727}
3728
aa2fbe6d
YZ		 3729int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3730 bool line_status)
23d43cf9
CD		 3731{
3732 if (!irqchip_in_kernel(kvm))
3733 return -ENXIO;
3734
3735 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3736 irq_event->irq, irq_event->level,
3737 line_status);
23d43cf9
CD		 3738 return 0;
3739}
3740
90de4a18
NA		 3741static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3742 struct kvm_enable_cap *cap)
3743{
3744 int r;
3745
3746 if (cap->flags)
3747 return -EINVAL;
3748
3749 switch (cap->cap) {
3750 case KVM_CAP_DISABLE_QUIRKS:
3751 kvm->arch.disabled_quirks = cap->args[0];
3752 r = 0;
3753 break;
49df6397
SR		 3754 case KVM_CAP_SPLIT_IRQCHIP: {
3755 mutex_lock(&kvm->lock);
b053b2ae
SR		 3756 r = -EINVAL;
3757 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3758 goto split_irqchip_unlock;
49df6397
SR		 3759 r = -EEXIST;
3760 if (irqchip_in_kernel(kvm))
3761 goto split_irqchip_unlock;
3762 if (atomic_read(&kvm->online_vcpus))
3763 goto split_irqchip_unlock;
3764 r = kvm_setup_empty_irq_routing(kvm);
3765 if (r)
3766 goto split_irqchip_unlock;
3767 /* Pairs with irqchip_in_kernel. */
3768 smp_wmb();
3769 kvm->arch.irqchip_split = true;
b053b2ae 3770 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3771 r = 0;
3772split_irqchip_unlock:
3773 mutex_unlock(&kvm->lock);
3774 break;
3775 }
90de4a18
NA		 3776 default:
3777 r = -EINVAL;
3778 break;
3779 }
3780 return r;
3781}
3782
1fe779f8
CO		 3783long kvm_arch_vm_ioctl(struct file *filp,
3784 unsigned int ioctl, unsigned long arg)
3785{
3786 struct kvm *kvm = filp->private_data;
3787 void __user *argp = (void __user *)arg;
367e1319 3788 int r = -ENOTTY;
f0d66275
DH		 3789 /*
3790 * This union makes it completely explicit to gcc-3.x
3791 * that these two variables' stack usage should be
3792 * combined, not added together.
3793 */
3794 union {
3795 struct kvm_pit_state ps;
e9f42757 3796 struct kvm_pit_state2 ps2;
c5ff41ce 3797 struct kvm_pit_config pit_config;
f0d66275 3798 } u;
1fe779f8
CO		 3799
3800 switch (ioctl) {
3801 case KVM_SET_TSS_ADDR:
3802 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3803 break;
b927a3ce
SY		 3804 case KVM_SET_IDENTITY_MAP_ADDR: {
3805 u64 ident_addr;
3806
3807 r = -EFAULT;
3808 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3809 goto out;
3810 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3811 break;
3812 }
1fe779f8
CO		 3813 case KVM_SET_NR_MMU_PAGES:
3814 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3815 break;
3816 case KVM_GET_NR_MMU_PAGES:
3817 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3818 break;
3ddea128
MT		 3819 case KVM_CREATE_IRQCHIP: {
3820 struct kvm_pic *vpic;
3821
3822 mutex_lock(&kvm->lock);
3823 r = -EEXIST;
3824 if (kvm->arch.vpic)
3825 goto create_irqchip_unlock;
3e515705
AK		 3826 r = -EINVAL;
3827 if (atomic_read(&kvm->online_vcpus))
3828 goto create_irqchip_unlock;
1fe779f8 3829 r = -ENOMEM;
3ddea128
MT		 3830 vpic = kvm_create_pic(kvm);
3831 if (vpic) {
1fe779f8
CO		 3832 r = kvm_ioapic_init(kvm);
3833 if (r) {
175504cd 3834 mutex_lock(&kvm->slots_lock);
71ba994c 3835 kvm_destroy_pic(vpic);
175504cd 3836 mutex_unlock(&kvm->slots_lock);
3ddea128 3837 goto create_irqchip_unlock;
1fe779f8
CO		 3838 }
3839 } else
3ddea128 3840 goto create_irqchip_unlock;
399ec807
AK		 3841 r = kvm_setup_default_irq_routing(kvm);
3842 if (r) {
175504cd 3843 mutex_lock(&kvm->slots_lock);
3ddea128 3844 mutex_lock(&kvm->irq_lock);
72bb2fcd 3845 kvm_ioapic_destroy(kvm);
71ba994c 3846 kvm_destroy_pic(vpic);
3ddea128 3847 mutex_unlock(&kvm->irq_lock);
175504cd 3848 mutex_unlock(&kvm->slots_lock);
71ba994c 3849 goto create_irqchip_unlock;
399ec807 3850 }
71ba994c
PB		 3851 /* Write kvm->irq_routing before kvm->arch.vpic. */
3852 smp_wmb();
3853 kvm->arch.vpic = vpic;
3ddea128
MT		 3854 create_irqchip_unlock:
3855 mutex_unlock(&kvm->lock);
1fe779f8 3856 break;
3ddea128 3857 }
7837699f 3858 case KVM_CREATE_PIT:
c5ff41ce
JK		 3859 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3860 goto create_pit;
3861 case KVM_CREATE_PIT2:
3862 r = -EFAULT;
3863 if (copy_from_user(&u.pit_config, argp,
3864 sizeof(struct kvm_pit_config)))
3865 goto out;
3866 create_pit:
79fac95e 3867 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3868 r = -EEXIST;
3869 if (kvm->arch.vpit)
3870 goto create_pit_unlock;
7837699f 3871 r = -ENOMEM;
c5ff41ce 3872 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3873 if (kvm->arch.vpit)
3874 r = 0;
269e05e4 3875 create_pit_unlock:
79fac95e 3876 mutex_unlock(&kvm->slots_lock);
7837699f 3877 break;
1fe779f8
CO		 3878 case KVM_GET_IRQCHIP: {
3879 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3880 struct kvm_irqchip *chip;
1fe779f8 3881
ff5c2c03
SL		 3882 chip = memdup_user(argp, sizeof(*chip));
3883 if (IS_ERR(chip)) {
3884 r = PTR_ERR(chip);
1fe779f8 3885 goto out;
ff5c2c03
SL		 3886 }
3887
1fe779f8 3888 r = -ENXIO;
49df6397 3889 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3890 goto get_irqchip_out;
3891 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3892 if (r)
f0d66275 3893 goto get_irqchip_out;
1fe779f8 3894 r = -EFAULT;
f0d66275
DH		 3895 if (copy_to_user(argp, chip, sizeof *chip))
3896 goto get_irqchip_out;
1fe779f8 3897 r = 0;
f0d66275
DH		 3898 get_irqchip_out:
3899 kfree(chip);
1fe779f8
CO		 3900 break;
3901 }
3902 case KVM_SET_IRQCHIP: {
3903 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3904 struct kvm_irqchip *chip;
1fe779f8 3905
ff5c2c03
SL		 3906 chip = memdup_user(argp, sizeof(*chip));
3907 if (IS_ERR(chip)) {
3908 r = PTR_ERR(chip);
1fe779f8 3909 goto out;
ff5c2c03
SL		 3910 }
3911
1fe779f8 3912 r = -ENXIO;
49df6397 3913 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3914 goto set_irqchip_out;
3915 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3916 if (r)
f0d66275 3917 goto set_irqchip_out;
1fe779f8 3918 r = 0;
f0d66275
DH		 3919 set_irqchip_out:
3920 kfree(chip);
1fe779f8
CO		 3921 break;
3922 }
e0f63cb9 3923 case KVM_GET_PIT: {
e0f63cb9 3924 r = -EFAULT;
f0d66275 3925 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3926 goto out;
3927 r = -ENXIO;
3928 if (!kvm->arch.vpit)
3929 goto out;
f0d66275 3930 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3931 if (r)
3932 goto out;
3933 r = -EFAULT;
f0d66275 3934 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3935 goto out;
3936 r = 0;
3937 break;
3938 }
3939 case KVM_SET_PIT: {
e0f63cb9 3940 r = -EFAULT;
f0d66275 3941 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3942 goto out;
3943 r = -ENXIO;
3944 if (!kvm->arch.vpit)
3945 goto out;
f0d66275 3946 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3947 break;
3948 }
e9f42757
BK		 3949 case KVM_GET_PIT2: {
3950 r = -ENXIO;
3951 if (!kvm->arch.vpit)
3952 goto out;
3953 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3954 if (r)
3955 goto out;
3956 r = -EFAULT;
3957 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3958 goto out;
3959 r = 0;
3960 break;
3961 }
3962 case KVM_SET_PIT2: {
3963 r = -EFAULT;
3964 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3965 goto out;
3966 r = -ENXIO;
3967 if (!kvm->arch.vpit)
3968 goto out;
3969 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3970 break;
3971 }
52d939a0
MT		 3972 case KVM_REINJECT_CONTROL: {
3973 struct kvm_reinject_control control;
3974 r = -EFAULT;
3975 if (copy_from_user(&control, argp, sizeof(control)))
3976 goto out;
3977 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3978 break;
3979 }
d71ba788
PB		 3980 case KVM_SET_BOOT_CPU_ID:
3981 r = 0;
3982 mutex_lock(&kvm->lock);
3983 if (atomic_read(&kvm->online_vcpus) != 0)
3984 r = -EBUSY;
3985 else
3986 kvm->arch.bsp_vcpu_id = arg;
3987 mutex_unlock(&kvm->lock);
3988 break;
ffde22ac
ES		 3989 case KVM_XEN_HVM_CONFIG: {
3990 r = -EFAULT;
3991 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3992 sizeof(struct kvm_xen_hvm_config)))
3993 goto out;
3994 r = -EINVAL;
3995 if (kvm->arch.xen_hvm_config.flags)
3996 goto out;
3997 r = 0;
3998 break;
3999 }
afbcf7ab 4000 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4001 struct kvm_clock_data user_ns;
4002 u64 now_ns;
4003 s64 delta;
4004
4005 r = -EFAULT;
4006 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4007 goto out;
4008
4009 r = -EINVAL;
4010 if (user_ns.flags)
4011 goto out;
4012
4013 r = 0;
395c6b0a 4014 local_irq_disable();
759379dd 4015 now_ns = get_kernel_ns();
afbcf7ab 4016 delta = user_ns.clock - now_ns;
395c6b0a 4017 local_irq_enable();
afbcf7ab 4018 kvm->arch.kvmclock_offset = delta;
2e762ff7 4019 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4020 break;
4021 }
4022 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4023 struct kvm_clock_data user_ns;
4024 u64 now_ns;
4025
395c6b0a 4026 local_irq_disable();
759379dd 4027 now_ns = get_kernel_ns();
afbcf7ab 4028 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4029 local_irq_enable();
afbcf7ab 4030 user_ns.flags = 0;
97e69aa6 4031 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4032
4033 r = -EFAULT;
4034 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4035 goto out;
4036 r = 0;
4037 break;
4038 }
90de4a18
NA		 4039 case KVM_ENABLE_CAP: {
4040 struct kvm_enable_cap cap;
afbcf7ab 4041
90de4a18
NA		 4042 r = -EFAULT;
4043 if (copy_from_user(&cap, argp, sizeof(cap)))
4044 goto out;
4045 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4046 break;
4047 }
1fe779f8 4048 default:
c274e03a 4049 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4050 }
4051out:
4052 return r;
4053}
4054
a16b043c 4055static void kvm_init_msr_list(void)
043405e1
CO		 4056{
4057 u32 dummy[2];
4058 unsigned i, j;
4059
62ef68bb 4060 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4061 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4062 continue;
93c4adc7
PB		 4063
4064 /*
4065 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4066 * to the guests in some cases.
93c4adc7
PB		 4067 */
4068 switch (msrs_to_save[i]) {
4069 case MSR_IA32_BNDCFGS:
4070 if (!kvm_x86_ops->mpx_supported())
4071 continue;
4072 break;
9dbe6cf9
PB		 4073 case MSR_TSC_AUX:
4074 if (!kvm_x86_ops->rdtscp_supported())
4075 continue;
4076 break;
93c4adc7
PB		 4077 default:
4078 break;
4079 }
4080
043405e1
CO		 4081 if (j < i)
4082 msrs_to_save[j] = msrs_to_save[i];
4083 j++;
4084 }
4085 num_msrs_to_save = j;
62ef68bb
PB		 4086
4087 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4088 switch (emulated_msrs[i]) {
6d396b55
PB		 4089 case MSR_IA32_SMBASE:
4090 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4091 continue;
4092 break;
62ef68bb
PB		 4093 default:
4094 break;
4095 }
4096
4097 if (j < i)
4098 emulated_msrs[j] = emulated_msrs[i];
4099 j++;
4100 }
4101 num_emulated_msrs = j;
043405e1
CO		 4102}
4103
bda9020e
MT		 4104static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4105 const void *v)
bbd9b64e 4106{
70252a10
AK		 4107 int handled = 0;
4108 int n;
4109
4110 do {
4111 n = min(len, 8);
bce87cce 4112 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4113 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4114 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4115 break;
4116 handled += n;
4117 addr += n;
4118 len -= n;
4119 v += n;
4120 } while (len);
bbd9b64e 4121
70252a10 4122 return handled;
bbd9b64e
CO		 4123}
4124
bda9020e 4125static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4126{
70252a10
AK		 4127 int handled = 0;
4128 int n;
4129
4130 do {
4131 n = min(len, 8);
bce87cce 4132 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4133 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4134 addr, n, v))
4135 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4136 break;
4137 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4138 handled += n;
4139 addr += n;
4140 len -= n;
4141 v += n;
4142 } while (len);
bbd9b64e 4143
70252a10 4144 return handled;
bbd9b64e
CO		 4145}
4146
2dafc6c2
GN		 4147static void kvm_set_segment(struct kvm_vcpu *vcpu,
4148 struct kvm_segment *var, int seg)
4149{
4150 kvm_x86_ops->set_segment(vcpu, var, seg);
4151}
4152
4153void kvm_get_segment(struct kvm_vcpu *vcpu,
4154 struct kvm_segment *var, int seg)
4155{
4156 kvm_x86_ops->get_segment(vcpu, var, seg);
4157}
4158
54987b7a
PB		 4159gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4160 struct x86_exception *exception)
02f59dc9
JR		 4161{
4162 gpa_t t_gpa;
02f59dc9
JR		 4163
4164 BUG_ON(!mmu_is_nested(vcpu));
4165
4166 /* NPT walks are always user-walks */
4167 access |= PFERR_USER_MASK;
54987b7a 4168 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4169
4170 return t_gpa;
4171}
4172
ab9ae313
AK		 4173gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4174 struct x86_exception *exception)
1871c602
GN		 4175{
4176 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4177 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4178}
4179
ab9ae313
AK		 4180 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4181 struct x86_exception *exception)
1871c602
GN		 4182{
4183 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4184 access |= PFERR_FETCH_MASK;
ab9ae313 4185 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4186}
4187
ab9ae313
AK		 4188gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4189 struct x86_exception *exception)
1871c602
GN		 4190{
4191 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4192 access |= PFERR_WRITE_MASK;
ab9ae313 4193 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4194}
4195
4196/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4197gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4198 struct x86_exception *exception)
1871c602 4199{
ab9ae313 4200 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4201}
4202
4203static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4204 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4205 struct x86_exception *exception)
bbd9b64e
CO		 4206{
4207 void *data = val;
10589a46 4208 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4209
4210 while (bytes) {
14dfe855 4211 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4212 exception);
bbd9b64e 4213 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4214 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4215 int ret;
4216
bcc55cba 4217 if (gpa == UNMAPPED_GVA)
ab9ae313 4218 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4219 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4220 offset, toread);
10589a46 4221 if (ret < 0) {
c3cd7ffa 4222 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4223 goto out;
4224 }
bbd9b64e 4225
77c2002e
IE		 4226 bytes -= toread;
4227 data += toread;
4228 addr += toread;
bbd9b64e 4229 }
10589a46 4230out:
10589a46 4231 return r;
bbd9b64e 4232}
77c2002e 4233
1871c602 4234/* used for instruction fetching */
0f65dd70
AK		 4235static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4236 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4237 struct x86_exception *exception)
1871c602 4238{
0f65dd70 4239 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4240 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4241 unsigned offset;
4242 int ret;
0f65dd70 4243
44583cba
PB		 4244 /* Inline kvm_read_guest_virt_helper for speed. */
4245 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4246 exception);
4247 if (unlikely(gpa == UNMAPPED_GVA))
4248 return X86EMUL_PROPAGATE_FAULT;
4249
4250 offset = addr & (PAGE_SIZE-1);
4251 if (WARN_ON(offset + bytes > PAGE_SIZE))
4252 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4253 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4254 offset, bytes);
44583cba
PB		 4255 if (unlikely(ret < 0))
4256 return X86EMUL_IO_NEEDED;
4257
4258 return X86EMUL_CONTINUE;
1871c602
GN		 4259}
4260
064aea77 4261int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4262 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4263 struct x86_exception *exception)
1871c602 4264{
0f65dd70 4265 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4266 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4267
1871c602 4268 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4269 exception);
1871c602 4270}
064aea77 4271EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4272
0f65dd70
AK		 4273static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4274 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4275 struct x86_exception *exception)
1871c602 4276{
0f65dd70 4277 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4278 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4279}
4280
7a036a6f
RK		 4281static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4282 unsigned long addr, void *val, unsigned int bytes)
4283{
4284 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4285 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4286
4287 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4288}
4289
6a4d7550 4290int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4291 gva_t addr, void *val,
2dafc6c2 4292 unsigned int bytes,
bcc55cba 4293 struct x86_exception *exception)
77c2002e 4294{
0f65dd70 4295 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4296 void *data = val;
4297 int r = X86EMUL_CONTINUE;
4298
4299 while (bytes) {
14dfe855
JR		 4300 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4301 PFERR_WRITE_MASK,
ab9ae313 4302 exception);
77c2002e
IE		 4303 unsigned offset = addr & (PAGE_SIZE-1);
4304 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4305 int ret;
4306
bcc55cba 4307 if (gpa == UNMAPPED_GVA)
ab9ae313 4308 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4309 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4310 if (ret < 0) {
c3cd7ffa 4311 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4312 goto out;
4313 }
4314
4315 bytes -= towrite;
4316 data += towrite;
4317 addr += towrite;
4318 }
4319out:
4320 return r;
4321}
6a4d7550 4322EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4323
af7cc7d1
XG		 4324static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4325 gpa_t *gpa, struct x86_exception *exception,
4326 bool write)
4327{
97d64b78
AK		 4328 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4329 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4330
be94f6b7
HH		 4331 /*
4332 * currently PKRU is only applied to ept enabled guest so
4333 * there is no pkey in EPT page table for L1 guest or EPT
4334 * shadow page table for L2 guest.
4335 */
97d64b78 4336 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4337 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4338 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4339 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4340 (gva & (PAGE_SIZE - 1));
4f022648 4341 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4342 return 1;
4343 }
4344
af7cc7d1
XG		 4345 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4346
4347 if (*gpa == UNMAPPED_GVA)
4348 return -1;
4349
4350 /* For APIC access vmexit */
4351 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4352 return 1;
4353
4f022648
XG		 4354 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4355 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4356 return 1;
4f022648 4357 }
bebb106a 4358
af7cc7d1
XG		 4359 return 0;
4360}
4361
3200f405 4362int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4363 const void *val, int bytes)
bbd9b64e
CO		 4364{
4365 int ret;
4366
54bf36aa 4367 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4368 if (ret < 0)
bbd9b64e 4369 return 0;
0eb05bf2 4370 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4371 return 1;
4372}
4373
77d197b2
XG		 4374struct read_write_emulator_ops {
4375 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4376 int bytes);
4377 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4378 void *val, int bytes);
4379 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4380 int bytes, void *val);
4381 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4382 void *val, int bytes);
4383 bool write;
4384};
4385
4386static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4387{
4388 if (vcpu->mmio_read_completed) {
77d197b2 4389 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4390 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4391 vcpu->mmio_read_completed = 0;
4392 return 1;
4393 }
4394
4395 return 0;
4396}
4397
4398static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4399 void *val, int bytes)
4400{
54bf36aa 4401 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4402}
4403
4404static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4405 void *val, int bytes)
4406{
4407 return emulator_write_phys(vcpu, gpa, val, bytes);
4408}
4409
4410static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4411{
4412 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4413 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4414}
4415
4416static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4417 void *val, int bytes)
4418{
4419 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4420 return X86EMUL_IO_NEEDED;
4421}
4422
4423static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4424 void *val, int bytes)
4425{
f78146b0
AK		 4426 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4427
87da7e66 4428 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4429 return X86EMUL_CONTINUE;
4430}
4431
0fbe9b0b 4432static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4433 .read_write_prepare = read_prepare,
4434 .read_write_emulate = read_emulate,
4435 .read_write_mmio = vcpu_mmio_read,
4436 .read_write_exit_mmio = read_exit_mmio,
4437};
4438
0fbe9b0b 4439static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4440 .read_write_emulate = write_emulate,
4441 .read_write_mmio = write_mmio,
4442 .read_write_exit_mmio = write_exit_mmio,
4443 .write = true,
4444};
4445
22388a3c
XG		 4446static int emulator_read_write_onepage(unsigned long addr, void *val,
4447 unsigned int bytes,
4448 struct x86_exception *exception,
4449 struct kvm_vcpu *vcpu,
0fbe9b0b 4450 const struct read_write_emulator_ops *ops)
bbd9b64e 4451{
af7cc7d1
XG		 4452 gpa_t gpa;
4453 int handled, ret;
22388a3c 4454 bool write = ops->write;
f78146b0 4455 struct kvm_mmio_fragment *frag;
10589a46 4456
22388a3c 4457 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4458
af7cc7d1 4459 if (ret < 0)
bbd9b64e 4460 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4461
4462 /* For APIC access vmexit */
af7cc7d1 4463 if (ret)
bbd9b64e
CO		 4464 goto mmio;
4465
22388a3c 4466 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4467 return X86EMUL_CONTINUE;
4468
4469mmio:
4470 /*
4471 * Is this MMIO handled locally?
4472 */
22388a3c 4473 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4474 if (handled == bytes)
bbd9b64e 4475 return X86EMUL_CONTINUE;
bbd9b64e 4476
70252a10
AK		 4477 gpa += handled;
4478 bytes -= handled;
4479 val += handled;
4480
87da7e66
XG		 4481 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4482 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4483 frag->gpa = gpa;
4484 frag->data = val;
4485 frag->len = bytes;
f78146b0 4486 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4487}
4488
52eb5a6d
XL		 4489static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4490 unsigned long addr,
22388a3c
XG		 4491 void *val, unsigned int bytes,
4492 struct x86_exception *exception,
0fbe9b0b 4493 const struct read_write_emulator_ops *ops)
bbd9b64e 4494{
0f65dd70 4495 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4496 gpa_t gpa;
4497 int rc;
4498
4499 if (ops->read_write_prepare &&
4500 ops->read_write_prepare(vcpu, val, bytes))
4501 return X86EMUL_CONTINUE;
4502
4503 vcpu->mmio_nr_fragments = 0;
0f65dd70 4504
bbd9b64e
CO		 4505 /* Crossing a page boundary? */
4506 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4507 int now;
bbd9b64e
CO		 4508
4509 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4510 rc = emulator_read_write_onepage(addr, val, now, exception,
4511 vcpu, ops);
4512
bbd9b64e
CO		 4513 if (rc != X86EMUL_CONTINUE)
4514 return rc;
4515 addr += now;
bac15531
NA		 4516 if (ctxt->mode != X86EMUL_MODE_PROT64)
4517 addr = (u32)addr;
bbd9b64e
CO		 4518 val += now;
4519 bytes -= now;
4520 }
22388a3c 4521
f78146b0
AK		 4522 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4523 vcpu, ops);
4524 if (rc != X86EMUL_CONTINUE)
4525 return rc;
4526
4527 if (!vcpu->mmio_nr_fragments)
4528 return rc;
4529
4530 gpa = vcpu->mmio_fragments[0].gpa;
4531
4532 vcpu->mmio_needed = 1;
4533 vcpu->mmio_cur_fragment = 0;
4534
87da7e66 4535 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4536 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4537 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4538 vcpu->run->mmio.phys_addr = gpa;
4539
4540 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4541}
4542
4543static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4544 unsigned long addr,
4545 void *val,
4546 unsigned int bytes,
4547 struct x86_exception *exception)
4548{
4549 return emulator_read_write(ctxt, addr, val, bytes,
4550 exception, &read_emultor);
4551}
4552
52eb5a6d 4553static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4554 unsigned long addr,
4555 const void *val,
4556 unsigned int bytes,
4557 struct x86_exception *exception)
4558{
4559 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4560 exception, &write_emultor);
bbd9b64e 4561}
bbd9b64e 4562
daea3e73
AK		 4563#define CMPXCHG_TYPE(t, ptr, old, new) \
4564 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4565
4566#ifdef CONFIG_X86_64
4567# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4568#else
4569# define CMPXCHG64(ptr, old, new) \
9749a6c0 4570 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4571#endif
4572
0f65dd70
AK		 4573static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4574 unsigned long addr,
bbd9b64e
CO		 4575 const void *old,
4576 const void *new,
4577 unsigned int bytes,
0f65dd70 4578 struct x86_exception *exception)
bbd9b64e 4579{
0f65dd70 4580 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4581 gpa_t gpa;
4582 struct page *page;
4583 char *kaddr;
4584 bool exchanged;
2bacc55c 4585
daea3e73
AK		 4586 /* guests cmpxchg8b have to be emulated atomically */
4587 if (bytes > 8 || (bytes & (bytes - 1)))
4588 goto emul_write;
10589a46 4589
daea3e73 4590 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4591
daea3e73
AK		 4592 if (gpa == UNMAPPED_GVA ||
4593 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4594 goto emul_write;
2bacc55c 4595
daea3e73
AK		 4596 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4597 goto emul_write;
72dc67a6 4598
54bf36aa 4599 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4600 if (is_error_page(page))
c19b8bd6 4601 goto emul_write;
72dc67a6 4602
8fd75e12 4603 kaddr = kmap_atomic(page);
daea3e73
AK		 4604 kaddr += offset_in_page(gpa);
4605 switch (bytes) {
4606 case 1:
4607 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4608 break;
4609 case 2:
4610 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4611 break;
4612 case 4:
4613 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4614 break;
4615 case 8:
4616 exchanged = CMPXCHG64(kaddr, old, new);
4617 break;
4618 default:
4619 BUG();
2bacc55c 4620 }
8fd75e12 4621 kunmap_atomic(kaddr);
daea3e73
AK		 4622 kvm_release_page_dirty(page);
4623
4624 if (!exchanged)
4625 return X86EMUL_CMPXCHG_FAILED;
4626
54bf36aa 4627 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4628 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4629
4630 return X86EMUL_CONTINUE;
4a5f48f6 4631
3200f405 4632emul_write:
daea3e73 4633 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4634
0f65dd70 4635 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4636}
4637
cf8f70bf
GN		 4638static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4639{
4640 /* TODO: String I/O for in kernel device */
4641 int r;
4642
4643 if (vcpu->arch.pio.in)
e32edf4f 4644 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4645 vcpu->arch.pio.size, pd);
4646 else
e32edf4f 4647 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4648 vcpu->arch.pio.port, vcpu->arch.pio.size,
4649 pd);
4650 return r;
4651}
4652
6f6fbe98
XG		 4653static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4654 unsigned short port, void *val,
4655 unsigned int count, bool in)
cf8f70bf 4656{
cf8f70bf 4657 vcpu->arch.pio.port = port;
6f6fbe98 4658 vcpu->arch.pio.in = in;
7972995b 4659 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4660 vcpu->arch.pio.size = size;
4661
4662 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4663 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4664 return 1;
4665 }
4666
4667 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4668 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4669 vcpu->run->io.size = size;
4670 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4671 vcpu->run->io.count = count;
4672 vcpu->run->io.port = port;
4673
4674 return 0;
4675}
4676
6f6fbe98
XG		 4677static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4678 int size, unsigned short port, void *val,
4679 unsigned int count)
cf8f70bf 4680{
ca1d4a9e 4681 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4682 int ret;
ca1d4a9e 4683
6f6fbe98
XG		 4684 if (vcpu->arch.pio.count)
4685 goto data_avail;
cf8f70bf 4686
6f6fbe98
XG		 4687 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4688 if (ret) {
4689data_avail:
4690 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4691 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4692 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4693 return 1;
4694 }
4695
cf8f70bf
GN		 4696 return 0;
4697}
4698
6f6fbe98
XG		 4699static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4700 int size, unsigned short port,
4701 const void *val, unsigned int count)
4702{
4703 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4704
4705 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4706 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4707 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4708}
4709
bbd9b64e
CO		 4710static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4711{
4712 return kvm_x86_ops->get_segment_base(vcpu, seg);
4713}
4714
3cb16fe7 4715static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4716{
3cb16fe7 4717 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4718}
4719
5cb56059 4720int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4721{
4722 if (!need_emulate_wbinvd(vcpu))
4723 return X86EMUL_CONTINUE;
4724
4725 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4726 int cpu = get_cpu();
4727
4728 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4729 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4730 wbinvd_ipi, NULL, 1);
2eec7343 4731 put_cpu();
f5f48ee1 4732 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4733 } else
4734 wbinvd();
f5f48ee1
SY		 4735 return X86EMUL_CONTINUE;
4736}
5cb56059
JS		 4737
4738int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4739{
4740 kvm_x86_ops->skip_emulated_instruction(vcpu);
4741 return kvm_emulate_wbinvd_noskip(vcpu);
4742}
f5f48ee1
SY		 4743EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4744
5cb56059
JS		 4745
4746
bcaf5cc5
AK		 4747static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4748{
5cb56059 4749 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4750}
4751
52eb5a6d
XL		 4752static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4753 unsigned long *dest)
bbd9b64e 4754{
16f8a6f9 4755 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4756}
4757
52eb5a6d
XL		 4758static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4759 unsigned long value)
bbd9b64e 4760{
338dbc97 4761
717746e3 4762 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4763}
4764
52a46617 4765static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4766{
52a46617 4767 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4768}
4769
717746e3 4770static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4771{
717746e3 4772 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4773 unsigned long value;
4774
4775 switch (cr) {
4776 case 0:
4777 value = kvm_read_cr0(vcpu);
4778 break;
4779 case 2:
4780 value = vcpu->arch.cr2;
4781 break;
4782 case 3:
9f8fe504 4783 value = kvm_read_cr3(vcpu);
52a46617
GN		 4784 break;
4785 case 4:
4786 value = kvm_read_cr4(vcpu);
4787 break;
4788 case 8:
4789 value = kvm_get_cr8(vcpu);
4790 break;
4791 default:
a737f256 4792 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4793 return 0;
4794 }
4795
4796 return value;
4797}
4798
717746e3 4799static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4800{
717746e3 4801 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4802 int res = 0;
4803
52a46617
GN		 4804 switch (cr) {
4805 case 0:
49a9b07e 4806 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4807 break;
4808 case 2:
4809 vcpu->arch.cr2 = val;
4810 break;
4811 case 3:
2390218b 4812 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4813 break;
4814 case 4:
a83b29c6 4815 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4816 break;
4817 case 8:
eea1cff9 4818 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4819 break;
4820 default:
a737f256 4821 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4822 res = -1;
52a46617 4823 }
0f12244f
GN		 4824
4825 return res;
52a46617
GN		 4826}
4827
717746e3 4828static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4829{
717746e3 4830 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4831}
4832
4bff1e86 4833static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4834{
4bff1e86 4835 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4836}
4837
4bff1e86 4838static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4839{
4bff1e86 4840 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4841}
4842
1ac9d0cf
AK		 4843static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4844{
4845 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4846}
4847
4848static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4849{
4850 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4851}
4852
4bff1e86
AK		 4853static unsigned long emulator_get_cached_segment_base(
4854 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4855{
4bff1e86 4856 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4857}
4858
1aa36616
AK		 4859static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4860 struct desc_struct *desc, u32 *base3,
4861 int seg)
2dafc6c2
GN		 4862{
4863 struct kvm_segment var;
4864
4bff1e86 4865 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4866 *selector = var.selector;
2dafc6c2 4867
378a8b09
GN		 4868 if (var.unusable) {
4869 memset(desc, 0, sizeof(*desc));
2dafc6c2 4870 return false;
378a8b09 4871 }
2dafc6c2
GN		 4872
4873 if (var.g)
4874 var.limit >>= 12;
4875 set_desc_limit(desc, var.limit);
4876 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4877#ifdef CONFIG_X86_64
4878 if (base3)
4879 *base3 = var.base >> 32;
4880#endif
2dafc6c2
GN		 4881 desc->type = var.type;
4882 desc->s = var.s;
4883 desc->dpl = var.dpl;
4884 desc->p = var.present;
4885 desc->avl = var.avl;
4886 desc->l = var.l;
4887 desc->d = var.db;
4888 desc->g = var.g;
4889
4890 return true;
4891}
4892
1aa36616
AK		 4893static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4894 struct desc_struct *desc, u32 base3,
4895 int seg)
2dafc6c2 4896{
4bff1e86 4897 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4898 struct kvm_segment var;
4899
1aa36616 4900 var.selector = selector;
2dafc6c2 4901 var.base = get_desc_base(desc);
5601d05b
GN		 4902#ifdef CONFIG_X86_64
4903 var.base |= ((u64)base3) << 32;
4904#endif
2dafc6c2
GN		 4905 var.limit = get_desc_limit(desc);
4906 if (desc->g)
4907 var.limit = (var.limit << 12) | 0xfff;
4908 var.type = desc->type;
2dafc6c2
GN		 4909 var.dpl = desc->dpl;
4910 var.db = desc->d;
4911 var.s = desc->s;
4912 var.l = desc->l;
4913 var.g = desc->g;
4914 var.avl = desc->avl;
4915 var.present = desc->p;
4916 var.unusable = !var.present;
4917 var.padding = 0;
4918
4919 kvm_set_segment(vcpu, &var, seg);
4920 return;
4921}
4922
717746e3
AK		 4923static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4924 u32 msr_index, u64 *pdata)
4925{
609e36d3
PB		 4926 struct msr_data msr;
4927 int r;
4928
4929 msr.index = msr_index;
4930 msr.host_initiated = false;
4931 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4932 if (r)
4933 return r;
4934
4935 *pdata = msr.data;
4936 return 0;
717746e3
AK		 4937}
4938
4939static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4940 u32 msr_index, u64 data)
4941{
8fe8ab46
WA		 4942 struct msr_data msr;
4943
4944 msr.data = data;
4945 msr.index = msr_index;
4946 msr.host_initiated = false;
4947 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4948}
4949
64d60670
PB		 4950static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4951{
4952 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4953
4954 return vcpu->arch.smbase;
4955}
4956
4957static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4958{
4959 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4960
4961 vcpu->arch.smbase = smbase;
4962}
4963
67f4d428
NA		 4964static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4965 u32 pmc)
4966{
c6702c9d 4967 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4968}
4969
222d21aa
AK		 4970static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4971 u32 pmc, u64 *pdata)
4972{
c6702c9d 4973 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4974}
4975
6c3287f7
AK		 4976static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4977{
4978 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4979}
4980
5037f6f3
AK		 4981static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4982{
4983 preempt_disable();
5197b808 4984 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4985 /*
4986 * CR0.TS may reference the host fpu state, not the guest fpu state,
4987 * so it may be clear at this point.
4988 */
4989 clts();
4990}
4991
4992static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4993{
4994 preempt_enable();
4995}
4996
2953538e 4997static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4998 struct x86_instruction_info *info,
c4f035c6
AK		 4999 enum x86_intercept_stage stage)
5000{
2953538e 5001 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5002}
5003
0017f93a 5004static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5005 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5006{
0017f93a 5007 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5008}
5009
dd856efa
AK		 5010static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5011{
5012 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5013}
5014
5015static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5016{
5017 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5018}
5019
801806d9
NA		 5020static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5021{
5022 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5023}
5024
0225fb50 5025static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5026 .read_gpr = emulator_read_gpr,
5027 .write_gpr = emulator_write_gpr,
1871c602 5028 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5029 .write_std = kvm_write_guest_virt_system,
7a036a6f 5030 .read_phys = kvm_read_guest_phys_system,
1871c602 5031 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5032 .read_emulated = emulator_read_emulated,
5033 .write_emulated = emulator_write_emulated,
5034 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5035 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5036 .pio_in_emulated = emulator_pio_in_emulated,
5037 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5038 .get_segment = emulator_get_segment,
5039 .set_segment = emulator_set_segment,
5951c442 5040 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5041 .get_gdt = emulator_get_gdt,
160ce1f1 5042 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5043 .set_gdt = emulator_set_gdt,
5044 .set_idt = emulator_set_idt,
52a46617
GN		 5045 .get_cr = emulator_get_cr,
5046 .set_cr = emulator_set_cr,
9c537244 5047 .cpl = emulator_get_cpl,
35aa5375
GN		 5048 .get_dr = emulator_get_dr,
5049 .set_dr = emulator_set_dr,
64d60670
PB		 5050 .get_smbase = emulator_get_smbase,
5051 .set_smbase = emulator_set_smbase,
717746e3
AK		 5052 .set_msr = emulator_set_msr,
5053 .get_msr = emulator_get_msr,
67f4d428 5054 .check_pmc = emulator_check_pmc,
222d21aa 5055 .read_pmc = emulator_read_pmc,
6c3287f7 5056 .halt = emulator_halt,
bcaf5cc5 5057 .wbinvd = emulator_wbinvd,
d6aa1000 5058 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5059 .get_fpu = emulator_get_fpu,
5060 .put_fpu = emulator_put_fpu,
c4f035c6 5061 .intercept = emulator_intercept,
bdb42f5a 5062 .get_cpuid = emulator_get_cpuid,
801806d9 5063 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5064};
5065
95cb2295
GN		 5066static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5067{
37ccdcbe 5068 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5069 /*
5070 * an sti; sti; sequence only disable interrupts for the first
5071 * instruction. So, if the last instruction, be it emulated or
5072 * not, left the system with the INT_STI flag enabled, it
5073 * means that the last instruction is an sti. We should not
5074 * leave the flag on in this case. The same goes for mov ss
5075 */
37ccdcbe
PB		 5076 if (int_shadow & mask)
5077 mask = 0;
6addfc42 5078 if (unlikely(int_shadow || mask)) {
95cb2295 5079 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5080 if (!mask)
5081 kvm_make_request(KVM_REQ_EVENT, vcpu);
5082 }
95cb2295
GN		 5083}
5084
ef54bcfe 5085static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5086{
5087 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5088 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5089 return kvm_propagate_fault(vcpu, &ctxt->exception);
5090
5091 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5092 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5093 ctxt->exception.error_code);
54b8486f 5094 else
da9cb575 5095 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5096 return false;
54b8486f
GN		 5097}
5098
8ec4722d
MG		 5099static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5100{
adf52235 5101 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5102 int cs_db, cs_l;
5103
8ec4722d
MG		 5104 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5105
adf52235
TY		 5106 ctxt->eflags = kvm_get_rflags(vcpu);
5107 ctxt->eip = kvm_rip_read(vcpu);
5108 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5109 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5110 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5111 cs_db ? X86EMUL_MODE_PROT32 :
5112 X86EMUL_MODE_PROT16;
a584539b 5113 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5114 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5115 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5116 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5117
dd856efa 5118 init_decode_cache(ctxt);
7ae441ea 5119 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5120}
5121
71f9833b 5122int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5123{
9d74191a 5124 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5125 int ret;
5126
5127 init_emulate_ctxt(vcpu);
5128
9dac77fa
AK		 5129 ctxt->op_bytes = 2;
5130 ctxt->ad_bytes = 2;
5131 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5132 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5133
5134 if (ret != X86EMUL_CONTINUE)
5135 return EMULATE_FAIL;
5136
9dac77fa 5137 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5138 kvm_rip_write(vcpu, ctxt->eip);
5139 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5140
5141 if (irq == NMI_VECTOR)
7460fb4a 5142 vcpu->arch.nmi_pending = 0;
63995653
MG		 5143 else
5144 vcpu->arch.interrupt.pending = false;
5145
5146 return EMULATE_DONE;
5147}
5148EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5149
6d77dbfc
GN		 5150static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5151{
fc3a9157
JR		 5152 int r = EMULATE_DONE;
5153
6d77dbfc
GN		 5154 ++vcpu->stat.insn_emulation_fail;
5155 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5156 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5157 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5158 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5159 vcpu->run->internal.ndata = 0;
5160 r = EMULATE_FAIL;
5161 }
6d77dbfc 5162 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5163
5164 return r;
6d77dbfc
GN		 5165}
5166
93c05d3e 5167static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5168 bool write_fault_to_shadow_pgtable,
5169 int emulation_type)
a6f177ef 5170{
95b3cf69 5171 gpa_t gpa = cr2;
ba049e93 5172 kvm_pfn_t pfn;
a6f177ef 5173
991eebf9
GN		 5174 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5175 return false;
5176
95b3cf69
XG		 5177 if (!vcpu->arch.mmu.direct_map) {
5178 /*
5179 * Write permission should be allowed since only
5180 * write access need to be emulated.
5181 */
5182 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5183
95b3cf69
XG		 5184 /*
5185 * If the mapping is invalid in guest, let cpu retry
5186 * it to generate fault.
5187 */
5188 if (gpa == UNMAPPED_GVA)
5189 return true;
5190 }
a6f177ef 5191
8e3d9d06
XG		 5192 /*
5193 * Do not retry the unhandleable instruction if it faults on the
5194 * readonly host memory, otherwise it will goto a infinite loop:
5195 * retry instruction -> write #PF -> emulation fail -> retry
5196 * instruction -> ...
5197 */
5198 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5199
5200 /*
5201 * If the instruction failed on the error pfn, it can not be fixed,
5202 * report the error to userspace.
5203 */
5204 if (is_error_noslot_pfn(pfn))
5205 return false;
5206
5207 kvm_release_pfn_clean(pfn);
5208
5209 /* The instructions are well-emulated on direct mmu. */
5210 if (vcpu->arch.mmu.direct_map) {
5211 unsigned int indirect_shadow_pages;
5212
5213 spin_lock(&vcpu->kvm->mmu_lock);
5214 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5215 spin_unlock(&vcpu->kvm->mmu_lock);
5216
5217 if (indirect_shadow_pages)
5218 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5219
a6f177ef 5220 return true;
8e3d9d06 5221 }
a6f177ef 5222
95b3cf69
XG		 5223 /*
5224 * if emulation was due to access to shadowed page table
5225 * and it failed try to unshadow page and re-enter the
5226 * guest to let CPU execute the instruction.
5227 */
5228 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5229
5230 /*
5231 * If the access faults on its page table, it can not
5232 * be fixed by unprotecting shadow page and it should
5233 * be reported to userspace.
5234 */
5235 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5236}
5237
1cb3f3ae
XG		 5238static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5239 unsigned long cr2, int emulation_type)
5240{
5241 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5242 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5243
5244 last_retry_eip = vcpu->arch.last_retry_eip;
5245 last_retry_addr = vcpu->arch.last_retry_addr;
5246
5247 /*
5248 * If the emulation is caused by #PF and it is non-page_table
5249 * writing instruction, it means the VM-EXIT is caused by shadow
5250 * page protected, we can zap the shadow page and retry this
5251 * instruction directly.
5252 *
5253 * Note: if the guest uses a non-page-table modifying instruction
5254 * on the PDE that points to the instruction, then we will unmap
5255 * the instruction and go to an infinite loop. So, we cache the
5256 * last retried eip and the last fault address, if we meet the eip
5257 * and the address again, we can break out of the potential infinite
5258 * loop.
5259 */
5260 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5261
5262 if (!(emulation_type & EMULTYPE_RETRY))
5263 return false;
5264
5265 if (x86_page_table_writing_insn(ctxt))
5266 return false;
5267
5268 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5269 return false;
5270
5271 vcpu->arch.last_retry_eip = ctxt->eip;
5272 vcpu->arch.last_retry_addr = cr2;
5273
5274 if (!vcpu->arch.mmu.direct_map)
5275 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5276
22368028 5277 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5278
5279 return true;
5280}
5281
716d51ab
GN		 5282static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5283static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5284
64d60670 5285static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5286{
64d60670 5287 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5288 /* This is a good place to trace that we are exiting SMM. */
5289 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5290
64d60670
PB		 5291 if (unlikely(vcpu->arch.smi_pending)) {
5292 kvm_make_request(KVM_REQ_SMI, vcpu);
5293 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5294 } else {
5295 /* Process a latched INIT, if any. */
5296 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5297 }
5298 }
699023e2
PB		 5299
5300 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5301}
5302
5303static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5304{
5305 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5306
a584539b 5307 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5308
5309 if (changed & HF_SMM_MASK)
5310 kvm_smm_changed(vcpu);
a584539b
PB		 5311}
5312
4a1e10d5
PB		 5313static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5314 unsigned long *db)
5315{
5316 u32 dr6 = 0;
5317 int i;
5318 u32 enable, rwlen;
5319
5320 enable = dr7;
5321 rwlen = dr7 >> 16;
5322 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5323 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5324 dr6 |= (1 << i);
5325 return dr6;
5326}
5327
6addfc42 5328static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5329{
5330 struct kvm_run *kvm_run = vcpu->run;
5331
5332 /*
6addfc42
PB		 5333 * rflags is the old, "raw" value of the flags. The new value has
5334 * not been saved yet.
663f4c61
PB		 5335 *
5336 * This is correct even for TF set by the guest, because "the
5337 * processor will not generate this exception after the instruction
5338 * that sets the TF flag".
5339 */
663f4c61
PB		 5340 if (unlikely(rflags & X86_EFLAGS_TF)) {
5341 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5342 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5343 DR6_RTM;
663f4c61
PB		 5344 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5345 kvm_run->debug.arch.exception = DB_VECTOR;
5346 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5347 *r = EMULATE_USER_EXIT;
5348 } else {
5349 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5350 /*
5351 * "Certain debug exceptions may clear bit 0-3. The
5352 * remaining contents of the DR6 register are never
5353 * cleared by the processor".
5354 */
5355 vcpu->arch.dr6 &= ~15;
6f43ed01 5356 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5357 kvm_queue_exception(vcpu, DB_VECTOR);
5358 }
5359 }
5360}
5361
4a1e10d5
PB		 5362static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5363{
4a1e10d5
PB		 5364 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5365 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5366 struct kvm_run *kvm_run = vcpu->run;
5367 unsigned long eip = kvm_get_linear_rip(vcpu);
5368 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5369 vcpu->arch.guest_debug_dr7,
5370 vcpu->arch.eff_db);
5371
5372 if (dr6 != 0) {
6f43ed01 5373 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5374 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5375 kvm_run->debug.arch.exception = DB_VECTOR;
5376 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5377 *r = EMULATE_USER_EXIT;
5378 return true;
5379 }
5380 }
5381
4161a569
NA		 5382 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5383 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5384 unsigned long eip = kvm_get_linear_rip(vcpu);
5385 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5386 vcpu->arch.dr7,
5387 vcpu->arch.db);
5388
5389 if (dr6 != 0) {
5390 vcpu->arch.dr6 &= ~15;
6f43ed01 5391 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5392 kvm_queue_exception(vcpu, DB_VECTOR);
5393 *r = EMULATE_DONE;
5394 return true;
5395 }
5396 }
5397
5398 return false;
5399}
5400
51d8b661
AP		 5401int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5402 unsigned long cr2,
dc25e89e
AP		 5403 int emulation_type,
5404 void *insn,
5405 int insn_len)
bbd9b64e 5406{
95cb2295 5407 int r;
9d74191a 5408 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5409 bool writeback = true;
93c05d3e 5410 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5411
93c05d3e
XG		 5412 /*
5413 * Clear write_fault_to_shadow_pgtable here to ensure it is
5414 * never reused.
5415 */
5416 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5417 kvm_clear_exception_queue(vcpu);
8d7d8102 5418
571008da 5419 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5420 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5421
5422 /*
5423 * We will reenter on the same instruction since
5424 * we do not set complete_userspace_io. This does not
5425 * handle watchpoints yet, those would be handled in
5426 * the emulate_ops.
5427 */
5428 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5429 return r;
5430
9d74191a
TY		 5431 ctxt->interruptibility = 0;
5432 ctxt->have_exception = false;
e0ad0b47 5433 ctxt->exception.vector = -1;
9d74191a 5434 ctxt->perm_ok = false;
bbd9b64e 5435
b51e974f 5436 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5437
9d74191a 5438 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5439
e46479f8 5440 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5441 ++vcpu->stat.insn_emulation;
1d2887e2 5442 if (r != EMULATION_OK) {
4005996e
AK		 5443 if (emulation_type & EMULTYPE_TRAP_UD)
5444 return EMULATE_FAIL;
991eebf9
GN		 5445 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5446 emulation_type))
bbd9b64e 5447 return EMULATE_DONE;
6d77dbfc
GN		 5448 if (emulation_type & EMULTYPE_SKIP)
5449 return EMULATE_FAIL;
5450 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5451 }
5452 }
5453
ba8afb6b 5454 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5455 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5456 if (ctxt->eflags & X86_EFLAGS_RF)
5457 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5458 return EMULATE_DONE;
5459 }
5460
1cb3f3ae
XG		 5461 if (retry_instruction(ctxt, cr2, emulation_type))
5462 return EMULATE_DONE;
5463
7ae441ea 5464 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5465 changes registers values during IO operation */
7ae441ea
GN		 5466 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5467 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5468 emulator_invalidate_register_cache(ctxt);
7ae441ea 5469 }
4d2179e1 5470
5cd21917 5471restart:
9d74191a 5472 r = x86_emulate_insn(ctxt);
bbd9b64e 5473
775fde86
JR		 5474 if (r == EMULATION_INTERCEPTED)
5475 return EMULATE_DONE;
5476
d2ddd1c4 5477 if (r == EMULATION_FAILED) {
991eebf9
GN		 5478 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5479 emulation_type))
c3cd7ffa
GN		 5480 return EMULATE_DONE;
5481
6d77dbfc 5482 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5483 }
5484
9d74191a 5485 if (ctxt->have_exception) {
d2ddd1c4 5486 r = EMULATE_DONE;
ef54bcfe
PB		 5487 if (inject_emulated_exception(vcpu))
5488 return r;
d2ddd1c4 5489 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5490 if (!vcpu->arch.pio.in) {
5491 /* FIXME: return into emulator if single-stepping. */
3457e419 5492 vcpu->arch.pio.count = 0;
0912c977 5493 } else {
7ae441ea 5494 writeback = false;
716d51ab
GN		 5495 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5496 }
ac0a48c3 5497 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5498 } else if (vcpu->mmio_needed) {
5499 if (!vcpu->mmio_is_write)
5500 writeback = false;
ac0a48c3 5501 r = EMULATE_USER_EXIT;
716d51ab 5502 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5503 } else if (r == EMULATION_RESTART)
5cd21917 5504 goto restart;
d2ddd1c4
GN		 5505 else
5506 r = EMULATE_DONE;
f850e2e6 5507
7ae441ea 5508 if (writeback) {
6addfc42 5509 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5510 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5511 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5512 if (vcpu->arch.hflags != ctxt->emul_flags)
5513 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5514 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5515 if (r == EMULATE_DONE)
6addfc42 5516 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5517 if (!ctxt->have_exception ||
5518 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5519 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5520
5521 /*
5522 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5523 * do nothing, and it will be requested again as soon as
5524 * the shadow expires. But we still need to check here,
5525 * because POPF has no interrupt shadow.
5526 */
5527 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5528 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5529 } else
5530 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5531
5532 return r;
de7d789a 5533}
51d8b661 5534EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5535
cf8f70bf 5536int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5537{
cf8f70bf 5538 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5539 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5540 size, port, &val, 1);
cf8f70bf 5541 /* do not return to emulator after return from userspace */
7972995b 5542 vcpu->arch.pio.count = 0;
de7d789a
CO		 5543 return ret;
5544}
cf8f70bf 5545EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5546
8cfdc000
ZA		 5547static void tsc_bad(void *info)
5548{
0a3aee0d 5549 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5550}
5551
5552static void tsc_khz_changed(void *data)
c8076604 5553{
8cfdc000
ZA		 5554 struct cpufreq_freqs *freq = data;
5555 unsigned long khz = 0;
5556
5557 if (data)
5558 khz = freq->new;
5559 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5560 khz = cpufreq_quick_get(raw_smp_processor_id());
5561 if (!khz)
5562 khz = tsc_khz;
0a3aee0d 5563 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5564}
5565
c8076604
GH		 5566static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5567 void *data)
5568{
5569 struct cpufreq_freqs *freq = data;
5570 struct kvm *kvm;
5571 struct kvm_vcpu *vcpu;
5572 int i, send_ipi = 0;
5573
8cfdc000
ZA		 5574 /*
5575 * We allow guests to temporarily run on slowing clocks,
5576 * provided we notify them after, or to run on accelerating
5577 * clocks, provided we notify them before. Thus time never
5578 * goes backwards.
5579 *
5580 * However, we have a problem. We can't atomically update
5581 * the frequency of a given CPU from this function; it is
5582 * merely a notifier, which can be called from any CPU.
5583 * Changing the TSC frequency at arbitrary points in time
5584 * requires a recomputation of local variables related to
5585 * the TSC for each VCPU. We must flag these local variables
5586 * to be updated and be sure the update takes place with the
5587 * new frequency before any guests proceed.
5588 *
5589 * Unfortunately, the combination of hotplug CPU and frequency
5590 * change creates an intractable locking scenario; the order
5591 * of when these callouts happen is undefined with respect to
5592 * CPU hotplug, and they can race with each other. As such,
5593 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5594 * undefined; you can actually have a CPU frequency change take
5595 * place in between the computation of X and the setting of the
5596 * variable. To protect against this problem, all updates of
5597 * the per_cpu tsc_khz variable are done in an interrupt
5598 * protected IPI, and all callers wishing to update the value
5599 * must wait for a synchronous IPI to complete (which is trivial
5600 * if the caller is on the CPU already). This establishes the
5601 * necessary total order on variable updates.
5602 *
5603 * Note that because a guest time update may take place
5604 * anytime after the setting of the VCPU's request bit, the
5605 * correct TSC value must be set before the request. However,
5606 * to ensure the update actually makes it to any guest which
5607 * starts running in hardware virtualization between the set
5608 * and the acquisition of the spinlock, we must also ping the
5609 * CPU after setting the request bit.
5610 *
5611 */
5612
c8076604
GH		 5613 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5614 return 0;
5615 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5616 return 0;
8cfdc000
ZA		 5617
5618 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5619
2f303b74 5620 spin_lock(&kvm_lock);
c8076604 5621 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5622 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5623 if (vcpu->cpu != freq->cpu)
5624 continue;
c285545f 5625 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5626 if (vcpu->cpu != smp_processor_id())
8cfdc000 5627 send_ipi = 1;
c8076604
GH		 5628 }
5629 }
2f303b74 5630 spin_unlock(&kvm_lock);
c8076604
GH		 5631
5632 if (freq->old < freq->new && send_ipi) {
5633 /*
5634 * We upscale the frequency. Must make the guest
5635 * doesn't see old kvmclock values while running with
5636 * the new frequency, otherwise we risk the guest sees
5637 * time go backwards.
5638 *
5639 * In case we update the frequency for another cpu
5640 * (which might be in guest context) send an interrupt
5641 * to kick the cpu out of guest context. Next time
5642 * guest context is entered kvmclock will be updated,
5643 * so the guest will not see stale values.
5644 */
8cfdc000 5645 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5646 }
5647 return 0;
5648}
5649
5650static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5651 .notifier_call = kvmclock_cpufreq_notifier
5652};
5653
5654static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5655 unsigned long action, void *hcpu)
5656{
5657 unsigned int cpu = (unsigned long)hcpu;
5658
5659 switch (action) {
5660 case CPU_ONLINE:
5661 case CPU_DOWN_FAILED:
5662 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5663 break;
5664 case CPU_DOWN_PREPARE:
5665 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5666 break;
5667 }
5668 return NOTIFY_OK;
5669}
5670
5671static struct notifier_block kvmclock_cpu_notifier_block = {
5672 .notifier_call = kvmclock_cpu_notifier,
5673 .priority = -INT_MAX
c8076604
GH		 5674};
5675
b820cc0c
ZA		 5676static void kvm_timer_init(void)
5677{
5678 int cpu;
5679
c285545f 5680 max_tsc_khz = tsc_khz;
460dd42e
SB		 5681
5682 cpu_notifier_register_begin();
b820cc0c 5683 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5684#ifdef CONFIG_CPU_FREQ
5685 struct cpufreq_policy policy;
5686 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5687 cpu = get_cpu();
5688 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5689 if (policy.cpuinfo.max_freq)
5690 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5691 put_cpu();
c285545f 5692#endif
b820cc0c
ZA		 5693 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5694 CPUFREQ_TRANSITION_NOTIFIER);
5695 }
c285545f 5696 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5697 for_each_online_cpu(cpu)
5698 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5699
5700 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5701 cpu_notifier_register_done();
5702
b820cc0c
ZA		 5703}
5704
ff9d07a0
ZY		 5705static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5706
f5132b01 5707int kvm_is_in_guest(void)
ff9d07a0 5708{
086c9855 5709 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5710}
5711
5712static int kvm_is_user_mode(void)
5713{
5714 int user_mode = 3;
dcf46b94 5715
086c9855
AS		 5716 if (__this_cpu_read(current_vcpu))
5717 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5718
ff9d07a0
ZY		 5719 return user_mode != 0;
5720}
5721
5722static unsigned long kvm_get_guest_ip(void)
5723{
5724 unsigned long ip = 0;
dcf46b94 5725
086c9855
AS		 5726 if (__this_cpu_read(current_vcpu))
5727 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5728
ff9d07a0
ZY		 5729 return ip;
5730}
5731
5732static struct perf_guest_info_callbacks kvm_guest_cbs = {
5733 .is_in_guest = kvm_is_in_guest,
5734 .is_user_mode = kvm_is_user_mode,
5735 .get_guest_ip = kvm_get_guest_ip,
5736};
5737
5738void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5739{
086c9855 5740 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5741}
5742EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5743
5744void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5745{
086c9855 5746 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5747}
5748EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5749
ce88decf
XG		 5750static void kvm_set_mmio_spte_mask(void)
5751{
5752 u64 mask;
5753 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5754
5755 /*
5756 * Set the reserved bits and the present bit of an paging-structure
5757 * entry to generate page fault with PFER.RSV = 1.
5758 */
885032b9 5759 /* Mask the reserved physical address bits. */
d1431483 5760 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5761
5762 /* Bit 62 is always reserved for 32bit host. */
5763 mask |= 0x3ull << 62;
5764
5765 /* Set the present bit. */
ce88decf
XG		 5766 mask |= 1ull;
5767
5768#ifdef CONFIG_X86_64
5769 /*
5770 * If reserved bit is not supported, clear the present bit to disable
5771 * mmio page fault.
5772 */
5773 if (maxphyaddr == 52)
5774 mask &= ~1ull;
5775#endif
5776
5777 kvm_mmu_set_mmio_spte_mask(mask);
5778}
5779
16e8d74d
MT		 5780#ifdef CONFIG_X86_64
5781static void pvclock_gtod_update_fn(struct work_struct *work)
5782{
d828199e
MT		 5783 struct kvm *kvm;
5784
5785 struct kvm_vcpu *vcpu;
5786 int i;
5787
2f303b74 5788 spin_lock(&kvm_lock);
d828199e
MT		 5789 list_for_each_entry(kvm, &vm_list, vm_list)
5790 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5791 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5792 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5793 spin_unlock(&kvm_lock);
16e8d74d
MT		 5794}
5795
5796static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5797
5798/*
5799 * Notification about pvclock gtod data update.
5800 */
5801static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5802 void *priv)
5803{
5804 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5805 struct timekeeper *tk = priv;
5806
5807 update_pvclock_gtod(tk);
5808
5809 /* disable master clock if host does not trust, or does not
5810 * use, TSC clocksource
5811 */
5812 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5813 atomic_read(&kvm_guest_has_master_clock) != 0)
5814 queue_work(system_long_wq, &pvclock_gtod_work);
5815
5816 return 0;
5817}
5818
5819static struct notifier_block pvclock_gtod_notifier = {
5820 .notifier_call = pvclock_gtod_notify,
5821};
5822#endif
5823
f8c16bba 5824int kvm_arch_init(void *opaque)
043405e1 5825{
b820cc0c 5826 int r;
6b61edf7 5827 struct kvm_x86_ops *ops = opaque;
f8c16bba 5828
f8c16bba
ZX		 5829 if (kvm_x86_ops) {
5830 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5831 r = -EEXIST;
5832 goto out;
f8c16bba
ZX		 5833 }
5834
5835 if (!ops->cpu_has_kvm_support()) {
5836 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5837 r = -EOPNOTSUPP;
5838 goto out;
f8c16bba
ZX		 5839 }
5840 if (ops->disabled_by_bios()) {
5841 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5842 r = -EOPNOTSUPP;
5843 goto out;
f8c16bba
ZX		 5844 }
5845
013f6a5d
MT		 5846 r = -ENOMEM;
5847 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5848 if (!shared_msrs) {
5849 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5850 goto out;
5851 }
5852
97db56ce
AK		 5853 r = kvm_mmu_module_init();
5854 if (r)
013f6a5d 5855 goto out_free_percpu;
97db56ce 5856
ce88decf 5857 kvm_set_mmio_spte_mask();
97db56ce 5858
f8c16bba 5859 kvm_x86_ops = ops;
920c8377 5860
7b52345e 5861 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5862 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5863
b820cc0c 5864 kvm_timer_init();
c8076604 5865
ff9d07a0
ZY		 5866 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5867
2acf923e
DC		 5868 if (cpu_has_xsave)
5869 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5870
c5cc421b 5871 kvm_lapic_init();
16e8d74d
MT		 5872#ifdef CONFIG_X86_64
5873 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5874#endif
5875
f8c16bba 5876 return 0;
56c6d28a 5877
013f6a5d
MT		 5878out_free_percpu:
5879 free_percpu(shared_msrs);
56c6d28a 5880out:
56c6d28a 5881 return r;
043405e1 5882}
8776e519 5883
f8c16bba
ZX		 5884void kvm_arch_exit(void)
5885{
ff9d07a0
ZY		 5886 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5887
888d256e
JK		 5888 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5889 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5890 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5891 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5892#ifdef CONFIG_X86_64
5893 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5894#endif
f8c16bba 5895 kvm_x86_ops = NULL;
56c6d28a 5896 kvm_mmu_module_exit();
013f6a5d 5897 free_percpu(shared_msrs);
56c6d28a 5898}
f8c16bba 5899
5cb56059 5900int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5901{
5902 ++vcpu->stat.halt_exits;
35754c98 5903 if (lapic_in_kernel(vcpu)) {
a4535290 5904 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5905 return 1;
5906 } else {
5907 vcpu->run->exit_reason = KVM_EXIT_HLT;
5908 return 0;
5909 }
5910}
5cb56059
JS		 5911EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5912
5913int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5914{
5915 kvm_x86_ops->skip_emulated_instruction(vcpu);
5916 return kvm_vcpu_halt(vcpu);
5917}
8776e519
HB		 5918EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5919
6aef266c
SV		 5920/*
5921 * kvm_pv_kick_cpu_op: Kick a vcpu.
5922 *
5923 * @apicid - apicid of vcpu to be kicked.
5924 */
5925static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5926{
24d2166b 5927 struct kvm_lapic_irq lapic_irq;
6aef266c 5928
24d2166b
R		 5929 lapic_irq.shorthand = 0;
5930 lapic_irq.dest_mode = 0;
5931 lapic_irq.dest_id = apicid;
93bbf0b8 5932 lapic_irq.msi_redir_hint = false;
6aef266c 5933
24d2166b 5934 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5935 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5936}
5937
d62caabb
AS		 5938void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5939{
5940 vcpu->arch.apicv_active = false;
5941 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5942}
5943
8776e519
HB		 5944int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5945{
5946 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5947 int op_64_bit, r = 1;
8776e519 5948
5cb56059
JS		 5949 kvm_x86_ops->skip_emulated_instruction(vcpu);
5950
55cd8e5a
GN		 5951 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5952 return kvm_hv_hypercall(vcpu);
5953
5fdbf976
MT		 5954 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5955 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5956 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5957 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5958 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5959
229456fc 5960 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5961
a449c7aa
NA		 5962 op_64_bit = is_64_bit_mode(vcpu);
5963 if (!op_64_bit) {
8776e519
HB		 5964 nr &= 0xFFFFFFFF;
5965 a0 &= 0xFFFFFFFF;
5966 a1 &= 0xFFFFFFFF;
5967 a2 &= 0xFFFFFFFF;
5968 a3 &= 0xFFFFFFFF;
5969 }
5970
07708c4a
JK		 5971 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5972 ret = -KVM_EPERM;
5973 goto out;
5974 }
5975
8776e519 5976 switch (nr) {
b93463aa
AK		 5977 case KVM_HC_VAPIC_POLL_IRQ:
5978 ret = 0;
5979 break;
6aef266c
SV		 5980 case KVM_HC_KICK_CPU:
5981 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5982 ret = 0;
5983 break;
8776e519
HB		 5984 default:
5985 ret = -KVM_ENOSYS;
5986 break;
5987 }
07708c4a 5988out:
a449c7aa
NA		 5989 if (!op_64_bit)
5990 ret = (u32)ret;
5fdbf976 5991 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5992 ++vcpu->stat.hypercalls;
2f333bcb 5993 return r;
8776e519
HB		 5994}
5995EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5996
b6785def 5997static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5998{
d6aa1000 5999 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6000 char instruction[3];
5fdbf976 6001 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6002
8776e519 6003 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6004
9d74191a 6005 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6006}
6007
851ba692 6008static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6009{
782d422b
MG		 6010 return vcpu->run->request_interrupt_window &&
6011 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6012}
6013
851ba692 6014static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6015{
851ba692
AK		 6016 struct kvm_run *kvm_run = vcpu->run;
6017
91586a3b 6018 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6019 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6020 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6021 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6022 kvm_run->ready_for_interrupt_injection =
6023 pic_in_kernel(vcpu->kvm) ||
782d422b 6024 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6025}
6026
95ba8273
GN		 6027static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6028{
6029 int max_irr, tpr;
6030
6031 if (!kvm_x86_ops->update_cr8_intercept)
6032 return;
6033
bce87cce 6034 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6035 return;
6036
d62caabb
AS		 6037 if (vcpu->arch.apicv_active)
6038 return;
6039
8db3baa2
GN		 6040 if (!vcpu->arch.apic->vapic_addr)
6041 max_irr = kvm_lapic_find_highest_irr(vcpu);
6042 else
6043 max_irr = -1;
95ba8273
GN		 6044
6045 if (max_irr != -1)
6046 max_irr >>= 4;
6047
6048 tpr = kvm_lapic_get_cr8(vcpu);
6049
6050 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6051}
6052
b6b8a145 6053static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6054{
b6b8a145
JK		 6055 int r;
6056
95ba8273 6057 /* try to reinject previous events if any */
b59bb7bd 6058 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6059 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6060 vcpu->arch.exception.has_error_code,
6061 vcpu->arch.exception.error_code);
d6e8c854
NA		 6062
6063 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6064 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6065 X86_EFLAGS_RF);
6066
6bdf0662
NA		 6067 if (vcpu->arch.exception.nr == DB_VECTOR &&
6068 (vcpu->arch.dr7 & DR7_GD)) {
6069 vcpu->arch.dr7 &= ~DR7_GD;
6070 kvm_update_dr7(vcpu);
6071 }
6072
b59bb7bd
GN		 6073 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6074 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6075 vcpu->arch.exception.error_code,
6076 vcpu->arch.exception.reinject);
b6b8a145 6077 return 0;
b59bb7bd
GN		 6078 }
6079
95ba8273
GN		 6080 if (vcpu->arch.nmi_injected) {
6081 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6082 return 0;
95ba8273
GN		 6083 }
6084
6085 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6086 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6087 return 0;
6088 }
6089
6090 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6091 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6092 if (r != 0)
6093 return r;
95ba8273
GN		 6094 }
6095
6096 /* try to inject new event if pending */
321c5658
YS		 6097 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6098 --vcpu->arch.nmi_pending;
6099 vcpu->arch.nmi_injected = true;
6100 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6101 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6102 /*
6103 * Because interrupts can be injected asynchronously, we are
6104 * calling check_nested_events again here to avoid a race condition.
6105 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6106 * proposal and current concerns. Perhaps we should be setting
6107 * KVM_REQ_EVENT only on certain events and not unconditionally?
6108 */
6109 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6110 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6111 if (r != 0)
6112 return r;
6113 }
95ba8273 6114 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6115 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6116 false);
6117 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6118 }
6119 }
b6b8a145 6120 return 0;
95ba8273
GN		 6121}
6122
7460fb4a
AK		 6123static void process_nmi(struct kvm_vcpu *vcpu)
6124{
6125 unsigned limit = 2;
6126
6127 /*
6128 * x86 is limited to one NMI running, and one NMI pending after it.
6129 * If an NMI is already in progress, limit further NMIs to just one.
6130 * Otherwise, allow two (and we'll inject the first one immediately).
6131 */
6132 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6133 limit = 1;
6134
6135 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6136 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6137 kvm_make_request(KVM_REQ_EVENT, vcpu);
6138}
6139
660a5d51
PB		 6140#define put_smstate(type, buf, offset, val) \
6141 *(type *)((buf) + (offset) - 0x7e00) = val
6142
6143static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6144{
6145 u32 flags = 0;
6146 flags |= seg->g << 23;
6147 flags |= seg->db << 22;
6148 flags |= seg->l << 21;
6149 flags |= seg->avl << 20;
6150 flags |= seg->present << 15;
6151 flags |= seg->dpl << 13;
6152 flags |= seg->s << 12;
6153 flags |= seg->type << 8;
6154 return flags;
6155}
6156
6157static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6158{
6159 struct kvm_segment seg;
6160 int offset;
6161
6162 kvm_get_segment(vcpu, &seg, n);
6163 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6164
6165 if (n < 3)
6166 offset = 0x7f84 + n * 12;
6167 else
6168 offset = 0x7f2c + (n - 3) * 12;
6169
6170 put_smstate(u32, buf, offset + 8, seg.base);
6171 put_smstate(u32, buf, offset + 4, seg.limit);
6172 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6173}
6174
efbb288a 6175#ifdef CONFIG_X86_64
660a5d51
PB		 6176static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6177{
6178 struct kvm_segment seg;
6179 int offset;
6180 u16 flags;
6181
6182 kvm_get_segment(vcpu, &seg, n);
6183 offset = 0x7e00 + n * 16;
6184
6185 flags = process_smi_get_segment_flags(&seg) >> 8;
6186 put_smstate(u16, buf, offset, seg.selector);
6187 put_smstate(u16, buf, offset + 2, flags);
6188 put_smstate(u32, buf, offset + 4, seg.limit);
6189 put_smstate(u64, buf, offset + 8, seg.base);
6190}
efbb288a 6191#endif
660a5d51
PB		 6192
6193static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6194{
6195 struct desc_ptr dt;
6196 struct kvm_segment seg;
6197 unsigned long val;
6198 int i;
6199
6200 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6201 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6202 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6203 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6204
6205 for (i = 0; i < 8; i++)
6206 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6207
6208 kvm_get_dr(vcpu, 6, &val);
6209 put_smstate(u32, buf, 0x7fcc, (u32)val);
6210 kvm_get_dr(vcpu, 7, &val);
6211 put_smstate(u32, buf, 0x7fc8, (u32)val);
6212
6213 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6214 put_smstate(u32, buf, 0x7fc4, seg.selector);
6215 put_smstate(u32, buf, 0x7f64, seg.base);
6216 put_smstate(u32, buf, 0x7f60, seg.limit);
6217 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6218
6219 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6220 put_smstate(u32, buf, 0x7fc0, seg.selector);
6221 put_smstate(u32, buf, 0x7f80, seg.base);
6222 put_smstate(u32, buf, 0x7f7c, seg.limit);
6223 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6224
6225 kvm_x86_ops->get_gdt(vcpu, &dt);
6226 put_smstate(u32, buf, 0x7f74, dt.address);
6227 put_smstate(u32, buf, 0x7f70, dt.size);
6228
6229 kvm_x86_ops->get_idt(vcpu, &dt);
6230 put_smstate(u32, buf, 0x7f58, dt.address);
6231 put_smstate(u32, buf, 0x7f54, dt.size);
6232
6233 for (i = 0; i < 6; i++)
6234 process_smi_save_seg_32(vcpu, buf, i);
6235
6236 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6237
6238 /* revision id */
6239 put_smstate(u32, buf, 0x7efc, 0x00020000);
6240 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6241}
6242
6243static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6244{
6245#ifdef CONFIG_X86_64
6246 struct desc_ptr dt;
6247 struct kvm_segment seg;
6248 unsigned long val;
6249 int i;
6250
6251 for (i = 0; i < 16; i++)
6252 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6253
6254 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6255 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6256
6257 kvm_get_dr(vcpu, 6, &val);
6258 put_smstate(u64, buf, 0x7f68, val);
6259 kvm_get_dr(vcpu, 7, &val);
6260 put_smstate(u64, buf, 0x7f60, val);
6261
6262 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6263 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6264 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6265
6266 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6267
6268 /* revision id */
6269 put_smstate(u32, buf, 0x7efc, 0x00020064);
6270
6271 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6272
6273 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6274 put_smstate(u16, buf, 0x7e90, seg.selector);
6275 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6276 put_smstate(u32, buf, 0x7e94, seg.limit);
6277 put_smstate(u64, buf, 0x7e98, seg.base);
6278
6279 kvm_x86_ops->get_idt(vcpu, &dt);
6280 put_smstate(u32, buf, 0x7e84, dt.size);
6281 put_smstate(u64, buf, 0x7e88, dt.address);
6282
6283 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6284 put_smstate(u16, buf, 0x7e70, seg.selector);
6285 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6286 put_smstate(u32, buf, 0x7e74, seg.limit);
6287 put_smstate(u64, buf, 0x7e78, seg.base);
6288
6289 kvm_x86_ops->get_gdt(vcpu, &dt);
6290 put_smstate(u32, buf, 0x7e64, dt.size);
6291 put_smstate(u64, buf, 0x7e68, dt.address);
6292
6293 for (i = 0; i < 6; i++)
6294 process_smi_save_seg_64(vcpu, buf, i);
6295#else
6296 WARN_ON_ONCE(1);
6297#endif
6298}
6299
64d60670
PB		 6300static void process_smi(struct kvm_vcpu *vcpu)
6301{
660a5d51 6302 struct kvm_segment cs, ds;
18c3626e 6303 struct desc_ptr dt;
660a5d51
PB		 6304 char buf[512];
6305 u32 cr0;
6306
64d60670
PB		 6307 if (is_smm(vcpu)) {
6308 vcpu->arch.smi_pending = true;
6309 return;
6310 }
6311
660a5d51
PB		 6312 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6313 vcpu->arch.hflags |= HF_SMM_MASK;
6314 memset(buf, 0, 512);
6315 if (guest_cpuid_has_longmode(vcpu))
6316 process_smi_save_state_64(vcpu, buf);
6317 else
6318 process_smi_save_state_32(vcpu, buf);
6319
54bf36aa 6320 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6321
6322 if (kvm_x86_ops->get_nmi_mask(vcpu))
6323 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6324 else
6325 kvm_x86_ops->set_nmi_mask(vcpu, true);
6326
6327 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6328 kvm_rip_write(vcpu, 0x8000);
6329
6330 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6331 kvm_x86_ops->set_cr0(vcpu, cr0);
6332 vcpu->arch.cr0 = cr0;
6333
6334 kvm_x86_ops->set_cr4(vcpu, 0);
6335
18c3626e
PB		 6336 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6337 dt.address = dt.size = 0;
6338 kvm_x86_ops->set_idt(vcpu, &dt);
6339
660a5d51
PB		 6340 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6341
6342 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6343 cs.base = vcpu->arch.smbase;
6344
6345 ds.selector = 0;
6346 ds.base = 0;
6347
6348 cs.limit = ds.limit = 0xffffffff;
6349 cs.type = ds.type = 0x3;
6350 cs.dpl = ds.dpl = 0;
6351 cs.db = ds.db = 0;
6352 cs.s = ds.s = 1;
6353 cs.l = ds.l = 0;
6354 cs.g = ds.g = 1;
6355 cs.avl = ds.avl = 0;
6356 cs.present = ds.present = 1;
6357 cs.unusable = ds.unusable = 0;
6358 cs.padding = ds.padding = 0;
6359
6360 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6361 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6362 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6363 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6364 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6365 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6366
6367 if (guest_cpuid_has_longmode(vcpu))
6368 kvm_x86_ops->set_efer(vcpu, 0);
6369
6370 kvm_update_cpuid(vcpu);
6371 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6372}
6373
2860c4b1
PB		 6374void kvm_make_scan_ioapic_request(struct kvm *kvm)
6375{
6376 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6377}
6378
3d81bc7e 6379static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6380{
5c919412
AS		 6381 u64 eoi_exit_bitmap[4];
6382
3d81bc7e
YZ		 6383 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6384 return;
c7c9c56c 6385
6308630b 6386 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6387
b053b2ae 6388 if (irqchip_split(vcpu->kvm))
6308630b 6389 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6390 else {
d62caabb
AS		 6391 if (vcpu->arch.apicv_active)
6392 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6393 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6394 }
5c919412
AS		 6395 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6396 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6397 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6398}
6399
a70656b6
RK		 6400static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6401{
6402 ++vcpu->stat.tlb_flush;
6403 kvm_x86_ops->tlb_flush(vcpu);
6404}
6405
4256f43f
TC		 6406void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6407{
c24ae0dc
TC		 6408 struct page *page = NULL;
6409
35754c98 6410 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6411 return;
6412
4256f43f
TC		 6413 if (!kvm_x86_ops->set_apic_access_page_addr)
6414 return;
6415
c24ae0dc 6416 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6417 if (is_error_page(page))
6418 return;
c24ae0dc
TC		 6419 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6420
6421 /*
6422 * Do not pin apic access page in memory, the MMU notifier
6423 * will call us again if it is migrated or swapped out.
6424 */
6425 put_page(page);
4256f43f
TC		 6426}
6427EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6428
fe71557a
TC		 6429void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6430 unsigned long address)
6431{
c24ae0dc
TC		 6432 /*
6433 * The physical address of apic access page is stored in the VMCS.
6434 * Update it when it becomes invalid.
6435 */
6436 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6437 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6438}
6439
9357d939 6440/*
362c698f 6441 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6442 * exiting to the userspace. Otherwise, the value will be returned to the
6443 * userspace.
6444 */
851ba692 6445static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6446{
6447 int r;
62a193ed
MG		 6448 bool req_int_win =
6449 dm_request_for_irq_injection(vcpu) &&
6450 kvm_cpu_accept_dm_intr(vcpu);
6451
730dca42 6452 bool req_immediate_exit = false;
b6c7a5dc 6453
3e007509 6454 if (vcpu->requests) {
a8eeb04a 6455 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6456 kvm_mmu_unload(vcpu);
a8eeb04a 6457 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6458 __kvm_migrate_timers(vcpu);
d828199e
MT		 6459 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6460 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6461 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6462 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6463 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6464 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6465 if (unlikely(r))
6466 goto out;
6467 }
a8eeb04a 6468 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6469 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6470 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6471 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6472 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6473 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6474 r = 0;
6475 goto out;
6476 }
a8eeb04a 6477 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6478 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6479 r = 0;
6480 goto out;
6481 }
a8eeb04a 6482 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6483 vcpu->fpu_active = 0;
6484 kvm_x86_ops->fpu_deactivate(vcpu);
6485 }
af585b92
GN		 6486 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6487 /* Page is swapped out. Do synthetic halt */
6488 vcpu->arch.apf.halted = true;
6489 r = 1;
6490 goto out;
6491 }
c9aaa895
GC		 6492 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6493 record_steal_time(vcpu);
64d60670
PB		 6494 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6495 process_smi(vcpu);
7460fb4a
AK		 6496 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6497 process_nmi(vcpu);
f5132b01 6498 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6499 kvm_pmu_handle_event(vcpu);
f5132b01 6500 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6501 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6502 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6503 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6504 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6505 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6506 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6507 vcpu->run->eoi.vector =
6508 vcpu->arch.pending_ioapic_eoi;
6509 r = 0;
6510 goto out;
6511 }
6512 }
3d81bc7e
YZ		 6513 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6514 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6515 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6516 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6517 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6518 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6519 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6520 r = 0;
6521 goto out;
6522 }
e516cebb
AS		 6523 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6524 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6525 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6526 r = 0;
6527 goto out;
6528 }
db397571
AS		 6529 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6530 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6531 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6532 r = 0;
6533 goto out;
6534 }
f3b138c5
AS		 6535
6536 /*
6537 * KVM_REQ_HV_STIMER has to be processed after
6538 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6539 * depend on the guest clock being up-to-date
6540 */
1f4b34f8
AS		 6541 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6542 kvm_hv_process_stimers(vcpu);
2f52d58c 6543 }
b93463aa 6544
bf9f6ac8
FW		 6545 /*
6546 * KVM_REQ_EVENT is not set when posted interrupts are set by
6547 * VT-d hardware, so we have to update RVI unconditionally.
6548 */
6549 if (kvm_lapic_enabled(vcpu)) {
6550 /*
6551 * Update architecture specific hints for APIC
6552 * virtual interrupt delivery.
6553 */
d62caabb 6554 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6555 kvm_x86_ops->hwapic_irr_update(vcpu,
6556 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6557 }
b93463aa 6558
b463a6f7 6559 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6560 kvm_apic_accept_events(vcpu);
6561 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6562 r = 1;
6563 goto out;
6564 }
6565
b6b8a145
JK		 6566 if (inject_pending_event(vcpu, req_int_win) != 0)
6567 req_immediate_exit = true;
b463a6f7 6568 /* enable NMI/IRQ window open exits if needed */
321c5658
YS		 6569 else {
6570 if (vcpu->arch.nmi_pending)
6571 kvm_x86_ops->enable_nmi_window(vcpu);
6572 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6573 kvm_x86_ops->enable_irq_window(vcpu);
6574 }
b463a6f7
AK		 6575
6576 if (kvm_lapic_enabled(vcpu)) {
6577 update_cr8_intercept(vcpu);
6578 kvm_lapic_sync_to_vapic(vcpu);
6579 }
6580 }
6581
d8368af8
AK		 6582 r = kvm_mmu_reload(vcpu);
6583 if (unlikely(r)) {
d905c069 6584 goto cancel_injection;
d8368af8
AK		 6585 }
6586
b6c7a5dc
HB		 6587 preempt_disable();
6588
6589 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6590 if (vcpu->fpu_active)
6591 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6592 vcpu->mode = IN_GUEST_MODE;
6593
01b71917
MT		 6594 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6595
0f127d12
LT		 6596 /*
6597 * We should set ->mode before check ->requests,
6598 * Please see the comment in kvm_make_all_cpus_request.
6599 * This also orders the write to mode from any reads
6600 * to the page tables done while the VCPU is running.
6601 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6602 */
01b71917 6603 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6604
d94e1dc9 6605 local_irq_disable();
32f88400 6606
6b7e2d09 6607 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6608 || need_resched() || signal_pending(current)) {
6b7e2d09 6609 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6610 smp_wmb();
6c142801
AK		 6611 local_irq_enable();
6612 preempt_enable();
01b71917 6613 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6614 r = 1;
d905c069 6615 goto cancel_injection;
6c142801
AK		 6616 }
6617
fc5b7f3b
DM		 6618 kvm_load_guest_xcr0(vcpu);
6619
d6185f20
NHE		 6620 if (req_immediate_exit)
6621 smp_send_reschedule(vcpu->cpu);
6622
8b89fe1f
PB		 6623 trace_kvm_entry(vcpu->vcpu_id);
6624 wait_lapic_expire(vcpu);
ccf73aaf 6625 __kvm_guest_enter();
b6c7a5dc 6626
42dbaa5a 6627 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6628 set_debugreg(0, 7);
6629 set_debugreg(vcpu->arch.eff_db[0], 0);
6630 set_debugreg(vcpu->arch.eff_db[1], 1);
6631 set_debugreg(vcpu->arch.eff_db[2], 2);
6632 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6633 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6634 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6635 }
b6c7a5dc 6636
851ba692 6637 kvm_x86_ops->run(vcpu);
b6c7a5dc 6638
c77fb5fe
PB		 6639 /*
6640 * Do this here before restoring debug registers on the host. And
6641 * since we do this before handling the vmexit, a DR access vmexit
6642 * can (a) read the correct value of the debug registers, (b) set
6643 * KVM_DEBUGREG_WONT_EXIT again.
6644 */
6645 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6646 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6647 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6648 kvm_update_dr0123(vcpu);
6649 kvm_update_dr6(vcpu);
6650 kvm_update_dr7(vcpu);
6651 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6652 }
6653
24f1e32c
FW		 6654 /*
6655 * If the guest has used debug registers, at least dr7
6656 * will be disabled while returning to the host.
6657 * If we don't have active breakpoints in the host, we don't
6658 * care about the messed up debug address registers. But if
6659 * we have some of them active, restore the old state.
6660 */
59d8eb53 6661 if (hw_breakpoint_active())
24f1e32c 6662 hw_breakpoint_restore();
42dbaa5a 6663
4ba76538 6664 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6665
6b7e2d09 6666 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6667 smp_wmb();
a547c6db 6668
fc5b7f3b
DM		 6669 kvm_put_guest_xcr0(vcpu);
6670
a547c6db
YZ		 6671 /* Interrupt is enabled by handle_external_intr() */
6672 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6673
6674 ++vcpu->stat.exits;
6675
6676 /*
6677 * We must have an instruction between local_irq_enable() and
6678 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6679 * the interrupt shadow. The stat.exits increment will do nicely.
6680 * But we need to prevent reordering, hence this barrier():
6681 */
6682 barrier();
6683
6684 kvm_guest_exit();
6685
6686 preempt_enable();
6687
f656ce01 6688 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6689
b6c7a5dc
HB		 6690 /*
6691 * Profile KVM exit RIPs:
6692 */
6693 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6694 unsigned long rip = kvm_rip_read(vcpu);
6695 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6696 }
6697
cc578287
ZA		 6698 if (unlikely(vcpu->arch.tsc_always_catchup))
6699 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6700
5cfb1d5a
MT		 6701 if (vcpu->arch.apic_attention)
6702 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6703
851ba692 6704 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6705 return r;
6706
6707cancel_injection:
6708 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6709 if (unlikely(vcpu->arch.apic_attention))
6710 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6711out:
6712 return r;
6713}
b6c7a5dc 6714
362c698f
PB		 6715static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6716{
bf9f6ac8
FW		 6717 if (!kvm_arch_vcpu_runnable(vcpu) &&
6718 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6719 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6720 kvm_vcpu_block(vcpu);
6721 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6722
6723 if (kvm_x86_ops->post_block)
6724 kvm_x86_ops->post_block(vcpu);
6725
9c8fd1ba
PB		 6726 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6727 return 1;
6728 }
362c698f
PB		 6729
6730 kvm_apic_accept_events(vcpu);
6731 switch(vcpu->arch.mp_state) {
6732 case KVM_MP_STATE_HALTED:
6733 vcpu->arch.pv.pv_unhalted = false;
6734 vcpu->arch.mp_state =
6735 KVM_MP_STATE_RUNNABLE;
6736 case KVM_MP_STATE_RUNNABLE:
6737 vcpu->arch.apf.halted = false;
6738 break;
6739 case KVM_MP_STATE_INIT_RECEIVED:
6740 break;
6741 default:
6742 return -EINTR;
6743 break;
6744 }
6745 return 1;
6746}
09cec754 6747
5d9bc648
PB		 6748static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6749{
6750 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6751 !vcpu->arch.apf.halted);
6752}
6753
362c698f 6754static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6755{
6756 int r;
f656ce01 6757 struct kvm *kvm = vcpu->kvm;
d7690175 6758
f656ce01 6759 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6760
362c698f 6761 for (;;) {
58f800d5 6762 if (kvm_vcpu_running(vcpu)) {
851ba692 6763 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6764 } else {
362c698f 6765 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6766 }
6767
09cec754
GN		 6768 if (r <= 0)
6769 break;
6770
6771 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6772 if (kvm_cpu_has_pending_timer(vcpu))
6773 kvm_inject_pending_timer_irqs(vcpu);
6774
782d422b
MG		 6775 if (dm_request_for_irq_injection(vcpu) &&
6776 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6777 r = 0;
6778 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6779 ++vcpu->stat.request_irq_exits;
362c698f 6780 break;
09cec754 6781 }
af585b92
GN		 6782
6783 kvm_check_async_pf_completion(vcpu);
6784
09cec754
GN		 6785 if (signal_pending(current)) {
6786 r = -EINTR;
851ba692 6787 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6788 ++vcpu->stat.signal_exits;
362c698f 6789 break;
09cec754
GN		 6790 }
6791 if (need_resched()) {
f656ce01 6792 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6793 cond_resched();
f656ce01 6794 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6795 }
b6c7a5dc
HB		 6796 }
6797
f656ce01 6798 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6799
6800 return r;
6801}
6802
716d51ab
GN		 6803static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6804{
6805 int r;
6806 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6807 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6808 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6809 if (r != EMULATE_DONE)
6810 return 0;
6811 return 1;
6812}
6813
6814static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6815{
6816 BUG_ON(!vcpu->arch.pio.count);
6817
6818 return complete_emulated_io(vcpu);
6819}
6820
f78146b0
AK		 6821/*
6822 * Implements the following, as a state machine:
6823 *
6824 * read:
6825 * for each fragment
87da7e66
XG		 6826 * for each mmio piece in the fragment
6827 * write gpa, len
6828 * exit
6829 * copy data
f78146b0
AK		 6830 * execute insn
6831 *
6832 * write:
6833 * for each fragment
87da7e66
XG		 6834 * for each mmio piece in the fragment
6835 * write gpa, len
6836 * copy data
6837 * exit
f78146b0 6838 */
716d51ab 6839static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6840{
6841 struct kvm_run *run = vcpu->run;
f78146b0 6842 struct kvm_mmio_fragment *frag;
87da7e66 6843 unsigned len;
5287f194 6844
716d51ab 6845 BUG_ON(!vcpu->mmio_needed);
5287f194 6846
716d51ab 6847 /* Complete previous fragment */
87da7e66
XG		 6848 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6849 len = min(8u, frag->len);
716d51ab 6850 if (!vcpu->mmio_is_write)
87da7e66
XG		 6851 memcpy(frag->data, run->mmio.data, len);
6852
6853 if (frag->len <= 8) {
6854 /* Switch to the next fragment. */
6855 frag++;
6856 vcpu->mmio_cur_fragment++;
6857 } else {
6858 /* Go forward to the next mmio piece. */
6859 frag->data += len;
6860 frag->gpa += len;
6861 frag->len -= len;
6862 }
6863
a08d3b3b 6864 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6865 vcpu->mmio_needed = 0;
0912c977
PB		 6866
6867 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6868 if (vcpu->mmio_is_write)
716d51ab
GN		 6869 return 1;
6870 vcpu->mmio_read_completed = 1;
6871 return complete_emulated_io(vcpu);
6872 }
87da7e66 6873
716d51ab
GN		 6874 run->exit_reason = KVM_EXIT_MMIO;
6875 run->mmio.phys_addr = frag->gpa;
6876 if (vcpu->mmio_is_write)
87da7e66
XG		 6877 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6878 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6879 run->mmio.is_write = vcpu->mmio_is_write;
6880 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6881 return 0;
5287f194
AK		 6882}
6883
716d51ab 6884
b6c7a5dc
HB		 6885int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6886{
c5bedc68 6887 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6888 int r;
6889 sigset_t sigsaved;
6890
c4d72e2d 6891 fpu__activate_curr(fpu);
e5c30142 6892
ac9f6dc0
AK		 6893 if (vcpu->sigset_active)
6894 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6895
a4535290 6896 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6897 kvm_vcpu_block(vcpu);
66450a21 6898 kvm_apic_accept_events(vcpu);
d7690175 6899 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6900 r = -EAGAIN;
6901 goto out;
b6c7a5dc
HB		 6902 }
6903
b6c7a5dc 6904 /* re-sync apic's tpr */
35754c98 6905 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6906 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6907 r = -EINVAL;
6908 goto out;
6909 }
6910 }
b6c7a5dc 6911
716d51ab
GN		 6912 if (unlikely(vcpu->arch.complete_userspace_io)) {
6913 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6914 vcpu->arch.complete_userspace_io = NULL;
6915 r = cui(vcpu);
6916 if (r <= 0)
6917 goto out;
6918 } else
6919 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6920
362c698f 6921 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6922
6923out:
f1d86e46 6924 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6925 if (vcpu->sigset_active)
6926 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6927
b6c7a5dc
HB		 6928 return r;
6929}
6930
6931int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6932{
7ae441ea
GN		 6933 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6934 /*
6935 * We are here if userspace calls get_regs() in the middle of
6936 * instruction emulation. Registers state needs to be copied
4a969980 6937 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6938 * that usually, but some bad designed PV devices (vmware
6939 * backdoor interface) need this to work
6940 */
dd856efa 6941 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6942 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6943 }
5fdbf976
MT		 6944 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6945 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6946 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6947 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6948 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6949 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6950 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6951 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6952#ifdef CONFIG_X86_64
5fdbf976
MT		 6953 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6954 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6955 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6956 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6957 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6958 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6959 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6960 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6961#endif
6962
5fdbf976 6963 regs->rip = kvm_rip_read(vcpu);
91586a3b 6964 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6965
b6c7a5dc
HB		 6966 return 0;
6967}
6968
6969int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6970{
7ae441ea
GN		 6971 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6972 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6973
5fdbf976
MT		 6974 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6975 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6976 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6977 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6978 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6979 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6980 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6981 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6982#ifdef CONFIG_X86_64
5fdbf976
MT		 6983 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6984 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6985 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6986 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6987 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6988 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6989 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6990 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6991#endif
6992
5fdbf976 6993 kvm_rip_write(vcpu, regs->rip);
91586a3b 6994 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6995
b4f14abd
JK		 6996 vcpu->arch.exception.pending = false;
6997
3842d135
AK		 6998 kvm_make_request(KVM_REQ_EVENT, vcpu);
6999
b6c7a5dc
HB		 7000 return 0;
7001}
7002
b6c7a5dc
HB		 7003void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7004{
7005 struct kvm_segment cs;
7006
3e6e0aab 7007 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7008 *db = cs.db;
7009 *l = cs.l;
7010}
7011EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7012
7013int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7014 struct kvm_sregs *sregs)
7015{
89a27f4d 7016 struct desc_ptr dt;
b6c7a5dc 7017
3e6e0aab
GT		 7018 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7019 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7020 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7021 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7022 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7023 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7024
3e6e0aab
GT		 7025 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7026 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7027
7028 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7029 sregs->idt.limit = dt.size;
7030 sregs->idt.base = dt.address;
b6c7a5dc 7031 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7032 sregs->gdt.limit = dt.size;
7033 sregs->gdt.base = dt.address;
b6c7a5dc 7034
4d4ec087 7035 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7036 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7037 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7038 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7039 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7040 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7041 sregs->apic_base = kvm_get_apic_base(vcpu);
7042
923c61bb 7043 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7044
36752c9b 7045 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7046 set_bit(vcpu->arch.interrupt.nr,
7047 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7048
b6c7a5dc
HB		 7049 return 0;
7050}
7051
62d9f0db
MT		 7052int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7053 struct kvm_mp_state *mp_state)
7054{
66450a21 7055 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7056 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7057 vcpu->arch.pv.pv_unhalted)
7058 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7059 else
7060 mp_state->mp_state = vcpu->arch.mp_state;
7061
62d9f0db
MT		 7062 return 0;
7063}
7064
7065int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7066 struct kvm_mp_state *mp_state)
7067{
bce87cce 7068 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7069 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7070 return -EINVAL;
7071
7072 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7073 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7074 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7075 } else
7076 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7077 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7078 return 0;
7079}
7080
7f3d35fd
KW		 7081int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7082 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7083{
9d74191a 7084 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7085 int ret;
e01c2426 7086
8ec4722d 7087 init_emulate_ctxt(vcpu);
c697518a 7088
7f3d35fd 7089 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7090 has_error_code, error_code);
c697518a 7091
c697518a 7092 if (ret)
19d04437 7093 return EMULATE_FAIL;
37817f29 7094
9d74191a
TY		 7095 kvm_rip_write(vcpu, ctxt->eip);
7096 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7097 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7098 return EMULATE_DONE;
37817f29
IE		 7099}
7100EXPORT_SYMBOL_GPL(kvm_task_switch);
7101
b6c7a5dc
HB		 7102int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7103 struct kvm_sregs *sregs)
7104{
58cb628d 7105 struct msr_data apic_base_msr;
b6c7a5dc 7106 int mmu_reset_needed = 0;
63f42e02 7107 int pending_vec, max_bits, idx;
89a27f4d 7108 struct desc_ptr dt;
b6c7a5dc 7109
6d1068b3
PM		 7110 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7111 return -EINVAL;
7112
89a27f4d
GN		 7113 dt.size = sregs->idt.limit;
7114 dt.address = sregs->idt.base;
b6c7a5dc 7115 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7116 dt.size = sregs->gdt.limit;
7117 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7118 kvm_x86_ops->set_gdt(vcpu, &dt);
7119
ad312c7c 7120 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7121 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7122 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7123 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7124
2d3ad1f4 7125 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7126
f6801dff 7127 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7128 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7129 apic_base_msr.data = sregs->apic_base;
7130 apic_base_msr.host_initiated = true;
7131 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7132
4d4ec087 7133 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7134 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7135 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7136
fc78f519 7137 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7138 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7139 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7140 kvm_update_cpuid(vcpu);
63f42e02
XG		 7141
7142 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7143 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7144 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7145 mmu_reset_needed = 1;
7146 }
63f42e02 7147 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7148
7149 if (mmu_reset_needed)
7150 kvm_mmu_reset_context(vcpu);
7151
a50abc3b 7152 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7153 pending_vec = find_first_bit(
7154 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7155 if (pending_vec < max_bits) {
66fd3f7f 7156 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7157 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7158 }
7159
3e6e0aab
GT		 7160 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7161 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7162 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7163 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7164 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7165 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7166
3e6e0aab
GT		 7167 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7168 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7169
5f0269f5
ME		 7170 update_cr8_intercept(vcpu);
7171
9c3e4aab 7172 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7173 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7174 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7175 !is_protmode(vcpu))
9c3e4aab
MT		 7176 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7177
3842d135
AK		 7178 kvm_make_request(KVM_REQ_EVENT, vcpu);
7179
b6c7a5dc
HB		 7180 return 0;
7181}
7182
d0bfb940
JK		 7183int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7184 struct kvm_guest_debug *dbg)
b6c7a5dc 7185{
355be0b9 7186 unsigned long rflags;
ae675ef0 7187 int i, r;
b6c7a5dc 7188
4f926bf2
JK		 7189 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7190 r = -EBUSY;
7191 if (vcpu->arch.exception.pending)
2122ff5e 7192 goto out;
4f926bf2
JK		 7193 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7194 kvm_queue_exception(vcpu, DB_VECTOR);
7195 else
7196 kvm_queue_exception(vcpu, BP_VECTOR);
7197 }
7198
91586a3b
JK		 7199 /*
7200 * Read rflags as long as potentially injected trace flags are still
7201 * filtered out.
7202 */
7203 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7204
7205 vcpu->guest_debug = dbg->control;
7206 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7207 vcpu->guest_debug = 0;
7208
7209 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7210 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7211 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7212 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7213 } else {
7214 for (i = 0; i < KVM_NR_DB_REGS; i++)
7215 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7216 }
c8639010 7217 kvm_update_dr7(vcpu);
ae675ef0 7218
f92653ee
JK		 7219 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7220 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7221 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7222
91586a3b
JK		 7223 /*
7224 * Trigger an rflags update that will inject or remove the trace
7225 * flags.
7226 */
7227 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7228
a96036b8 7229 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7230
4f926bf2 7231 r = 0;
d0bfb940 7232
2122ff5e 7233out:
b6c7a5dc
HB		 7234
7235 return r;
7236}
7237
8b006791
ZX		 7238/*
7239 * Translate a guest virtual address to a guest physical address.
7240 */
7241int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7242 struct kvm_translation *tr)
7243{
7244 unsigned long vaddr = tr->linear_address;
7245 gpa_t gpa;
f656ce01 7246 int idx;
8b006791 7247
f656ce01 7248 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7249 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7250 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7251 tr->physical_address = gpa;
7252 tr->valid = gpa != UNMAPPED_GVA;
7253 tr->writeable = 1;
7254 tr->usermode = 0;
8b006791
ZX		 7255
7256 return 0;
7257}
7258
d0752060
HB		 7259int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7260{
c47ada30 7261 struct fxregs_state *fxsave =
7366ed77 7262 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7263
d0752060
HB		 7264 memcpy(fpu->fpr, fxsave->st_space, 128);
7265 fpu->fcw = fxsave->cwd;
7266 fpu->fsw = fxsave->swd;
7267 fpu->ftwx = fxsave->twd;
7268 fpu->last_opcode = fxsave->fop;
7269 fpu->last_ip = fxsave->rip;
7270 fpu->last_dp = fxsave->rdp;
7271 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7272
d0752060
HB		 7273 return 0;
7274}
7275
7276int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7277{
c47ada30 7278 struct fxregs_state *fxsave =
7366ed77 7279 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7280
d0752060
HB		 7281 memcpy(fxsave->st_space, fpu->fpr, 128);
7282 fxsave->cwd = fpu->fcw;
7283 fxsave->swd = fpu->fsw;
7284 fxsave->twd = fpu->ftwx;
7285 fxsave->fop = fpu->last_opcode;
7286 fxsave->rip = fpu->last_ip;
7287 fxsave->rdp = fpu->last_dp;
7288 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7289
d0752060
HB		 7290 return 0;
7291}
7292
0ee6a517 7293static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7294{
bf935b0b 7295 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7296 if (cpu_has_xsaves)
7366ed77 7297 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7298 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7299
2acf923e
DC		 7300 /*
7301 * Ensure guest xcr0 is valid for loading
7302 */
d91cab78 7303 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7304
ad312c7c 7305 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7306}
d0752060
HB		 7307
7308void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7309{
2608d7a1 7310 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7311 return;
7312
2acf923e
DC		 7313 /*
7314 * Restore all possible states in the guest,
7315 * and assume host would use all available bits.
7316 * Guest xcr0 would be loaded later.
7317 */
d0752060 7318 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7319 __kernel_fpu_begin();
003e2e8b 7320 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7321 trace_kvm_fpu(1);
d0752060 7322}
d0752060
HB		 7323
7324void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7325{
653f52c3
RR		 7326 if (!vcpu->guest_fpu_loaded) {
7327 vcpu->fpu_counter = 0;
d0752060 7328 return;
653f52c3 7329 }
d0752060
HB		 7330
7331 vcpu->guest_fpu_loaded = 0;
4f836347 7332 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7333 __kernel_fpu_end();
f096ed85 7334 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7335 /*
7336 * If using eager FPU mode, or if the guest is a frequent user
7337 * of the FPU, just leave the FPU active for next time.
7338 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7339 * the FPU in bursts will revert to loading it on demand.
7340 */
5a5fbdc0 7341 if (!use_eager_fpu()) {
653f52c3
RR		 7342 if (++vcpu->fpu_counter < 5)
7343 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7344 }
0c04851c 7345 trace_kvm_fpu(0);
d0752060 7346}
e9b11c17
ZX		 7347
7348void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7349{
12f9a48f 7350 kvmclock_reset(vcpu);
7f1ea208 7351
f5f48ee1 7352 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7353 kvm_x86_ops->vcpu_free(vcpu);
7354}
7355
7356struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7357 unsigned int id)
7358{
c447e76b
LL		 7359 struct kvm_vcpu *vcpu;
7360
6755bae8
ZA		 7361 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7362 printk_once(KERN_WARNING
7363 "kvm: SMP vm created on host with unstable TSC; "
7364 "guest TSC will not be reliable\n");
c447e76b
LL		 7365
7366 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7367
c447e76b 7368 return vcpu;
26e5215f 7369}
e9b11c17 7370
26e5215f
AK		 7371int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7372{
7373 int r;
e9b11c17 7374
19efffa2 7375 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7376 r = vcpu_load(vcpu);
7377 if (r)
7378 return r;
d28bc9dd 7379 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7380 kvm_mmu_setup(vcpu);
e9b11c17 7381 vcpu_put(vcpu);
26e5215f 7382 return r;
e9b11c17
ZX		 7383}
7384
31928aa5 7385void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7386{
8fe8ab46 7387 struct msr_data msr;
332967a3 7388 struct kvm *kvm = vcpu->kvm;
42897d86 7389
31928aa5
DD		 7390 if (vcpu_load(vcpu))
7391 return;
8fe8ab46
WA		 7392 msr.data = 0x0;
7393 msr.index = MSR_IA32_TSC;
7394 msr.host_initiated = true;
7395 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7396 vcpu_put(vcpu);
7397
630994b3
MT		 7398 if (!kvmclock_periodic_sync)
7399 return;
7400
332967a3
AJ		 7401 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7402 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7403}
7404
d40ccc62 7405void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7406{
9fc77441 7407 int r;
344d9588
GN		 7408 vcpu->arch.apf.msr_val = 0;
7409
9fc77441
MT		 7410 r = vcpu_load(vcpu);
7411 BUG_ON(r);
e9b11c17
ZX		 7412 kvm_mmu_unload(vcpu);
7413 vcpu_put(vcpu);
7414
7415 kvm_x86_ops->vcpu_free(vcpu);
7416}
7417
d28bc9dd 7418void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7419{
e69fab5d
PB		 7420 vcpu->arch.hflags = 0;
7421
7460fb4a
AK		 7422 atomic_set(&vcpu->arch.nmi_queued, 0);
7423 vcpu->arch.nmi_pending = 0;
448fa4a9 7424 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7425 kvm_clear_interrupt_queue(vcpu);
7426 kvm_clear_exception_queue(vcpu);
448fa4a9 7427
42dbaa5a 7428 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7429 kvm_update_dr0123(vcpu);
6f43ed01 7430 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7431 kvm_update_dr6(vcpu);
42dbaa5a 7432 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7433 kvm_update_dr7(vcpu);
42dbaa5a 7434
1119022c
NA		 7435 vcpu->arch.cr2 = 0;
7436
3842d135 7437 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7438 vcpu->arch.apf.msr_val = 0;
c9aaa895 7439 vcpu->arch.st.msr_val = 0;
3842d135 7440
12f9a48f
GC		 7441 kvmclock_reset(vcpu);
7442
af585b92
GN		 7443 kvm_clear_async_pf_completion_queue(vcpu);
7444 kvm_async_pf_hash_reset(vcpu);
7445 vcpu->arch.apf.halted = false;
3842d135 7446
64d60670 7447 if (!init_event) {
d28bc9dd 7448 kvm_pmu_reset(vcpu);
64d60670
PB		 7449 vcpu->arch.smbase = 0x30000;
7450 }
f5132b01 7451
66f7b72e
JS		 7452 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7453 vcpu->arch.regs_avail = ~0;
7454 vcpu->arch.regs_dirty = ~0;
7455
d28bc9dd 7456 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7457}
7458
2b4a273b 7459void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7460{
7461 struct kvm_segment cs;
7462
7463 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7464 cs.selector = vector << 8;
7465 cs.base = vector << 12;
7466 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7467 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7468}
7469
13a34e06 7470int kvm_arch_hardware_enable(void)
e9b11c17 7471{
ca84d1a2
ZA		 7472 struct kvm *kvm;
7473 struct kvm_vcpu *vcpu;
7474 int i;
0dd6a6ed
ZA		 7475 int ret;
7476 u64 local_tsc;
7477 u64 max_tsc = 0;
7478 bool stable, backwards_tsc = false;
18863bdd
AK		 7479
7480 kvm_shared_msr_cpu_online();
13a34e06 7481 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7482 if (ret != 0)
7483 return ret;
7484
4ea1636b 7485 local_tsc = rdtsc();
0dd6a6ed
ZA		 7486 stable = !check_tsc_unstable();
7487 list_for_each_entry(kvm, &vm_list, vm_list) {
7488 kvm_for_each_vcpu(i, vcpu, kvm) {
7489 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7490 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7491 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7492 backwards_tsc = true;
7493 if (vcpu->arch.last_host_tsc > max_tsc)
7494 max_tsc = vcpu->arch.last_host_tsc;
7495 }
7496 }
7497 }
7498
7499 /*
7500 * Sometimes, even reliable TSCs go backwards. This happens on
7501 * platforms that reset TSC during suspend or hibernate actions, but
7502 * maintain synchronization. We must compensate. Fortunately, we can
7503 * detect that condition here, which happens early in CPU bringup,
7504 * before any KVM threads can be running. Unfortunately, we can't
7505 * bring the TSCs fully up to date with real time, as we aren't yet far
7506 * enough into CPU bringup that we know how much real time has actually
7507 * elapsed; our helper function, get_kernel_ns() will be using boot
7508 * variables that haven't been updated yet.
7509 *
7510 * So we simply find the maximum observed TSC above, then record the
7511 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7512 * the adjustment will be applied. Note that we accumulate
7513 * adjustments, in case multiple suspend cycles happen before some VCPU
7514 * gets a chance to run again. In the event that no KVM threads get a
7515 * chance to run, we will miss the entire elapsed period, as we'll have
7516 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7517 * loose cycle time. This isn't too big a deal, since the loss will be
7518 * uniform across all VCPUs (not to mention the scenario is extremely
7519 * unlikely). It is possible that a second hibernate recovery happens
7520 * much faster than a first, causing the observed TSC here to be
7521 * smaller; this would require additional padding adjustment, which is
7522 * why we set last_host_tsc to the local tsc observed here.
7523 *
7524 * N.B. - this code below runs only on platforms with reliable TSC,
7525 * as that is the only way backwards_tsc is set above. Also note
7526 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7527 * have the same delta_cyc adjustment applied if backwards_tsc
7528 * is detected. Note further, this adjustment is only done once,
7529 * as we reset last_host_tsc on all VCPUs to stop this from being
7530 * called multiple times (one for each physical CPU bringup).
7531 *
4a969980 7532 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7533 * will be compensated by the logic in vcpu_load, which sets the TSC to
7534 * catchup mode. This will catchup all VCPUs to real time, but cannot
7535 * guarantee that they stay in perfect synchronization.
7536 */
7537 if (backwards_tsc) {
7538 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7539 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7540 list_for_each_entry(kvm, &vm_list, vm_list) {
7541 kvm_for_each_vcpu(i, vcpu, kvm) {
7542 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7543 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7544 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7545 }
7546
7547 /*
7548 * We have to disable TSC offset matching.. if you were
7549 * booting a VM while issuing an S4 host suspend....
7550 * you may have some problem. Solving this issue is
7551 * left as an exercise to the reader.
7552 */
7553 kvm->arch.last_tsc_nsec = 0;
7554 kvm->arch.last_tsc_write = 0;
7555 }
7556
7557 }
7558 return 0;
e9b11c17
ZX		 7559}
7560
13a34e06 7561void kvm_arch_hardware_disable(void)
e9b11c17 7562{
13a34e06
RK		 7563 kvm_x86_ops->hardware_disable();
7564 drop_user_return_notifiers();
e9b11c17
ZX		 7565}
7566
7567int kvm_arch_hardware_setup(void)
7568{
9e9c3fe4
NA		 7569 int r;
7570
7571 r = kvm_x86_ops->hardware_setup();
7572 if (r != 0)
7573 return r;
7574
35181e86
HZ		 7575 if (kvm_has_tsc_control) {
7576 /*
7577 * Make sure the user can only configure tsc_khz values that
7578 * fit into a signed integer.
7579 * A min value is not calculated needed because it will always
7580 * be 1 on all machines.
7581 */
7582 u64 max = min(0x7fffffffULL,
7583 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7584 kvm_max_guest_tsc_khz = max;
7585
ad721883 7586 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7587 }
ad721883 7588
9e9c3fe4
NA		 7589 kvm_init_msr_list();
7590 return 0;
e9b11c17
ZX		 7591}
7592
7593void kvm_arch_hardware_unsetup(void)
7594{
7595 kvm_x86_ops->hardware_unsetup();
7596}
7597
7598void kvm_arch_check_processor_compat(void *rtn)
7599{
7600 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7601}
7602
7603bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7604{
7605 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7606}
7607EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7608
7609bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7610{
7611 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7612}
7613
3e515705
AK		 7614bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7615{
35754c98 7616 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7617}
7618
54e9818f 7619struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7620EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7621
e9b11c17
ZX		 7622int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7623{
7624 struct page *page;
7625 struct kvm *kvm;
7626 int r;
7627
7628 BUG_ON(vcpu->kvm == NULL);
7629 kvm = vcpu->kvm;
7630
d62caabb 7631 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7632 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7633 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7634 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7635 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7636 else
a4535290 7637 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7638
7639 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7640 if (!page) {
7641 r = -ENOMEM;
7642 goto fail;
7643 }
ad312c7c 7644 vcpu->arch.pio_data = page_address(page);
e9b11c17 7645
cc578287 7646 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7647
e9b11c17
ZX		 7648 r = kvm_mmu_create(vcpu);
7649 if (r < 0)
7650 goto fail_free_pio_data;
7651
7652 if (irqchip_in_kernel(kvm)) {
7653 r = kvm_create_lapic(vcpu);
7654 if (r < 0)
7655 goto fail_mmu_destroy;
54e9818f
GN		 7656 } else
7657 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7658
890ca9ae
HY		 7659 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7660 GFP_KERNEL);
7661 if (!vcpu->arch.mce_banks) {
7662 r = -ENOMEM;
443c39bc 7663 goto fail_free_lapic;
890ca9ae
HY		 7664 }
7665 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7666
f1797359
WY		 7667 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7668 r = -ENOMEM;
f5f48ee1 7669 goto fail_free_mce_banks;
f1797359 7670 }
f5f48ee1 7671
0ee6a517 7672 fx_init(vcpu);
66f7b72e 7673
ba904635 7674 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7675 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7676
7677 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7678 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7679
5a4f55cd
EK		 7680 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7681
74545705
RK		 7682 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7683
af585b92 7684 kvm_async_pf_hash_reset(vcpu);
f5132b01 7685 kvm_pmu_init(vcpu);
af585b92 7686
1c1a9ce9
SR		 7687 vcpu->arch.pending_external_vector = -1;
7688
5c919412
AS		 7689 kvm_hv_vcpu_init(vcpu);
7690
e9b11c17 7691 return 0;
0ee6a517 7692
f5f48ee1
SY		 7693fail_free_mce_banks:
7694 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7695fail_free_lapic:
7696 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7697fail_mmu_destroy:
7698 kvm_mmu_destroy(vcpu);
7699fail_free_pio_data:
ad312c7c 7700 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7701fail:
7702 return r;
7703}
7704
7705void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7706{
f656ce01
MT		 7707 int idx;
7708
1f4b34f8 7709 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7710 kvm_pmu_destroy(vcpu);
36cb93fd 7711 kfree(vcpu->arch.mce_banks);
e9b11c17 7712 kvm_free_lapic(vcpu);
f656ce01 7713 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7714 kvm_mmu_destroy(vcpu);
f656ce01 7715 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7716 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7717 if (!lapic_in_kernel(vcpu))
54e9818f 7718 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7719}
d19a9cd2 7720
e790d9ef
RK		 7721void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7722{
ae97a3b8 7723 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7724}
7725
e08b9637 7726int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7727{
e08b9637
CO		 7728 if (type)
7729 return -EINVAL;
7730
6ef768fa 7731 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7732 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7733 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7734 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7735 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7736
5550af4d
SY		 7737 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7738 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7739 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7740 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7741 &kvm->arch.irq_sources_bitmap);
5550af4d 7742
038f8c11 7743 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7744 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7745 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7746
7747 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7748
7e44e449 7749 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7750 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7751
0eb05bf2 7752 kvm_page_track_init(kvm);
13d268ca 7753 kvm_mmu_init_vm(kvm);
0eb05bf2 7754
d89f5eff 7755 return 0;
d19a9cd2
ZX		 7756}
7757
7758static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7759{
9fc77441
MT		 7760 int r;
7761 r = vcpu_load(vcpu);
7762 BUG_ON(r);
d19a9cd2
ZX		 7763 kvm_mmu_unload(vcpu);
7764 vcpu_put(vcpu);
7765}
7766
7767static void kvm_free_vcpus(struct kvm *kvm)
7768{
7769 unsigned int i;
988a2cae 7770 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7771
7772 /*
7773 * Unpin any mmu pages first.
7774 */
af585b92
GN		 7775 kvm_for_each_vcpu(i, vcpu, kvm) {
7776 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7777 kvm_unload_vcpu_mmu(vcpu);
af585b92 7778 }
988a2cae
GN		 7779 kvm_for_each_vcpu(i, vcpu, kvm)
7780 kvm_arch_vcpu_free(vcpu);
7781
7782 mutex_lock(&kvm->lock);
7783 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7784 kvm->vcpus[i] = NULL;
d19a9cd2 7785
988a2cae
GN		 7786 atomic_set(&kvm->online_vcpus, 0);
7787 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7788}
7789
ad8ba2cd
SY		 7790void kvm_arch_sync_events(struct kvm *kvm)
7791{
332967a3 7792 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7793 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7794 kvm_free_all_assigned_devices(kvm);
aea924f6 7795 kvm_free_pit(kvm);
ad8ba2cd
SY		 7796}
7797
1d8007bd 7798int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7799{
7800 int i, r;
25188b99 7801 unsigned long hva;
f0d648bd
PB		 7802 struct kvm_memslots *slots = kvm_memslots(kvm);
7803 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7804
7805 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7806 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7807 return -EINVAL;
9da0e4d5 7808
f0d648bd
PB		 7809 slot = id_to_memslot(slots, id);
7810 if (size) {
7811 if (WARN_ON(slot->npages))
7812 return -EEXIST;
7813
7814 /*
7815 * MAP_SHARED to prevent internal slot pages from being moved
7816 * by fork()/COW.
7817 */
7818 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7819 MAP_SHARED | MAP_ANONYMOUS, 0);
7820 if (IS_ERR((void *)hva))
7821 return PTR_ERR((void *)hva);
7822 } else {
7823 if (!slot->npages)
7824 return 0;
7825
7826 hva = 0;
7827 }
7828
7829 old = *slot;
9da0e4d5 7830 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7831 struct kvm_userspace_memory_region m;
9da0e4d5 7832
1d8007bd
PB		 7833 m.slot = id | (i << 16);
7834 m.flags = 0;
7835 m.guest_phys_addr = gpa;
f0d648bd 7836 m.userspace_addr = hva;
1d8007bd 7837 m.memory_size = size;
9da0e4d5
PB		 7838 r = __kvm_set_memory_region(kvm, &m);
7839 if (r < 0)
7840 return r;
7841 }
7842
f0d648bd
PB		 7843 if (!size) {
7844 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7845 WARN_ON(r < 0);
7846 }
7847
9da0e4d5
PB		 7848 return 0;
7849}
7850EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7851
1d8007bd 7852int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7853{
7854 int r;
7855
7856 mutex_lock(&kvm->slots_lock);
1d8007bd 7857 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7858 mutex_unlock(&kvm->slots_lock);
7859
7860 return r;
7861}
7862EXPORT_SYMBOL_GPL(x86_set_memory_region);
7863
d19a9cd2
ZX		 7864void kvm_arch_destroy_vm(struct kvm *kvm)
7865{
27469d29
AH		 7866 if (current->mm == kvm->mm) {
7867 /*
7868 * Free memory regions allocated on behalf of userspace,
7869 * unless the the memory map has changed due to process exit
7870 * or fd copying.
7871 */
1d8007bd
PB		 7872 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7873 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7874 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7875 }
6eb55818 7876 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7877 kfree(kvm->arch.vpic);
7878 kfree(kvm->arch.vioapic);
d19a9cd2 7879 kvm_free_vcpus(kvm);
1e08ec4a 7880 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7881 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7882}
0de10343 7883
5587027c 7884void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7885 struct kvm_memory_slot *dont)
7886{
7887 int i;
7888
d89cc617
TY		 7889 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7890 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7891 kvfree(free->arch.rmap[i]);
d89cc617 7892 free->arch.rmap[i] = NULL;
77d11309 7893 }
d89cc617
TY		 7894 if (i == 0)
7895 continue;
7896
7897 if (!dont || free->arch.lpage_info[i - 1] !=
7898 dont->arch.lpage_info[i - 1]) {
548ef284 7899 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7900 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7901 }
7902 }
21ebbeda
XG		 7903
7904 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7905}
7906
5587027c
AK		 7907int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7908 unsigned long npages)
db3fe4eb
TY		 7909{
7910 int i;
7911
d89cc617 7912 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7913 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7914 unsigned long ugfn;
7915 int lpages;
d89cc617 7916 int level = i + 1;
db3fe4eb
TY		 7917
7918 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7919 slot->base_gfn, level) + 1;
7920
d89cc617
TY		 7921 slot->arch.rmap[i] =
7922 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7923 if (!slot->arch.rmap[i])
77d11309 7924 goto out_free;
d89cc617
TY		 7925 if (i == 0)
7926 continue;
77d11309 7927
92f94f1e
XG		 7928 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7929 if (!linfo)
db3fe4eb
TY		 7930 goto out_free;
7931
92f94f1e
XG		 7932 slot->arch.lpage_info[i - 1] = linfo;
7933
db3fe4eb 7934 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7935 linfo[0].disallow_lpage = 1;
db3fe4eb 7936 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7937 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7938 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7939 /*
7940 * If the gfn and userspace address are not aligned wrt each
7941 * other, or if explicitly asked to, disable large page
7942 * support for this slot
7943 */
7944 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7945 !kvm_largepages_enabled()) {
7946 unsigned long j;
7947
7948 for (j = 0; j < lpages; ++j)
92f94f1e 7949 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7950 }
7951 }
7952
21ebbeda
XG		 7953 if (kvm_page_track_create_memslot(slot, npages))
7954 goto out_free;
7955
db3fe4eb
TY		 7956 return 0;
7957
7958out_free:
d89cc617 7959 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7960 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7961 slot->arch.rmap[i] = NULL;
7962 if (i == 0)
7963 continue;
7964
548ef284 7965 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7966 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7967 }
7968 return -ENOMEM;
7969}
7970
15f46015 7971void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7972{
e6dff7d1
TY		 7973 /*
7974 * memslots->generation has been incremented.
7975 * mmio generation may have reached its maximum value.
7976 */
54bf36aa 7977 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7978}
7979
f7784b8e
MT		 7980int kvm_arch_prepare_memory_region(struct kvm *kvm,
7981 struct kvm_memory_slot *memslot,
09170a49 7982 const struct kvm_userspace_memory_region *mem,
7b6195a9 7983 enum kvm_mr_change change)
0de10343 7984{
f7784b8e
MT		 7985 return 0;
7986}
7987
88178fd4
KH		 7988static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7989 struct kvm_memory_slot *new)
7990{
7991 /* Still write protect RO slot */
7992 if (new->flags & KVM_MEM_READONLY) {
7993 kvm_mmu_slot_remove_write_access(kvm, new);
7994 return;
7995 }
7996
7997 /*
7998 * Call kvm_x86_ops dirty logging hooks when they are valid.
7999 *
8000 * kvm_x86_ops->slot_disable_log_dirty is called when:
8001 *
8002 * - KVM_MR_CREATE with dirty logging is disabled
8003 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8004 *
8005 * The reason is, in case of PML, we need to set D-bit for any slots
8006 * with dirty logging disabled in order to eliminate unnecessary GPA
8007 * logging in PML buffer (and potential PML buffer full VMEXT). This
8008 * guarantees leaving PML enabled during guest's lifetime won't have
8009 * any additonal overhead from PML when guest is running with dirty
8010 * logging disabled for memory slots.
8011 *
8012 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8013 * to dirty logging mode.
8014 *
8015 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8016 *
8017 * In case of write protect:
8018 *
8019 * Write protect all pages for dirty logging.
8020 *
8021 * All the sptes including the large sptes which point to this
8022 * slot are set to readonly. We can not create any new large
8023 * spte on this slot until the end of the logging.
8024 *
8025 * See the comments in fast_page_fault().
8026 */
8027 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8028 if (kvm_x86_ops->slot_enable_log_dirty)
8029 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8030 else
8031 kvm_mmu_slot_remove_write_access(kvm, new);
8032 } else {
8033 if (kvm_x86_ops->slot_disable_log_dirty)
8034 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8035 }
8036}
8037
f7784b8e 8038void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8039 const struct kvm_userspace_memory_region *mem,
8482644a 8040 const struct kvm_memory_slot *old,
f36f3f28 8041 const struct kvm_memory_slot *new,
8482644a 8042 enum kvm_mr_change change)
f7784b8e 8043{
8482644a 8044 int nr_mmu_pages = 0;
f7784b8e 8045
48c0e4e9
XG		 8046 if (!kvm->arch.n_requested_mmu_pages)
8047 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8048
48c0e4e9 8049 if (nr_mmu_pages)
0de10343 8050 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8051
3ea3b7fa
WL		 8052 /*
8053 * Dirty logging tracks sptes in 4k granularity, meaning that large
8054 * sptes have to be split. If live migration is successful, the guest
8055 * in the source machine will be destroyed and large sptes will be
8056 * created in the destination. However, if the guest continues to run
8057 * in the source machine (for example if live migration fails), small
8058 * sptes will remain around and cause bad performance.
8059 *
8060 * Scan sptes if dirty logging has been stopped, dropping those
8061 * which can be collapsed into a single large-page spte. Later
8062 * page faults will create the large-page sptes.
8063 */
8064 if ((change != KVM_MR_DELETE) &&
8065 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8066 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8067 kvm_mmu_zap_collapsible_sptes(kvm, new);
8068
c972f3b1 8069 /*
88178fd4 8070 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8071 *
88178fd4
KH		 8072 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8073 * been zapped so no dirty logging staff is needed for old slot. For
8074 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8075 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8076 *
8077 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8078 */
88178fd4 8079 if (change != KVM_MR_DELETE)
f36f3f28 8080 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8081}
1d737c8a 8082
2df72e9b 8083void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8084{
6ca18b69 8085 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8086}
8087
2df72e9b
MT		 8088void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8089 struct kvm_memory_slot *slot)
8090{
6ca18b69 8091 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8092}
8093
5d9bc648
PB		 8094static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8095{
8096 if (!list_empty_careful(&vcpu->async_pf.done))
8097 return true;
8098
8099 if (kvm_apic_has_events(vcpu))
8100 return true;
8101
8102 if (vcpu->arch.pv.pv_unhalted)
8103 return true;
8104
8105 if (atomic_read(&vcpu->arch.nmi_queued))
8106 return true;
8107
73917739
PB		 8108 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8109 return true;
8110
5d9bc648
PB		 8111 if (kvm_arch_interrupt_allowed(vcpu) &&
8112 kvm_cpu_has_interrupt(vcpu))
8113 return true;
8114
1f4b34f8
AS		 8115 if (kvm_hv_has_stimer_pending(vcpu))
8116 return true;
8117
5d9bc648
PB		 8118 return false;
8119}
8120
1d737c8a
ZX		 8121int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8122{
b6b8a145
JK		 8123 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8124 kvm_x86_ops->check_nested_events(vcpu, false);
8125
5d9bc648 8126 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8127}
5736199a 8128
b6d33834 8129int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8130{
b6d33834 8131 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8132}
78646121
GN		 8133
8134int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8135{
8136 return kvm_x86_ops->interrupt_allowed(vcpu);
8137}
229456fc 8138
82b32774 8139unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8140{
82b32774
NA		 8141 if (is_64_bit_mode(vcpu))
8142 return kvm_rip_read(vcpu);
8143 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8144 kvm_rip_read(vcpu));
8145}
8146EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8147
82b32774
NA		 8148bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8149{
8150 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8151}
8152EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8153
94fe45da
JK		 8154unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8155{
8156 unsigned long rflags;
8157
8158 rflags = kvm_x86_ops->get_rflags(vcpu);
8159 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8160 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8161 return rflags;
8162}
8163EXPORT_SYMBOL_GPL(kvm_get_rflags);
8164
6addfc42 8165static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8166{
8167 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8168 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8169 rflags |= X86_EFLAGS_TF;
94fe45da 8170 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8171}
8172
8173void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8174{
8175 __kvm_set_rflags(vcpu, rflags);
3842d135 8176 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8177}
8178EXPORT_SYMBOL_GPL(kvm_set_rflags);
8179
56028d08
GN		 8180void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8181{
8182 int r;
8183
fb67e14f 8184 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8185 work->wakeup_all)
56028d08
GN		 8186 return;
8187
8188 r = kvm_mmu_reload(vcpu);
8189 if (unlikely(r))
8190 return;
8191
fb67e14f
XG		 8192 if (!vcpu->arch.mmu.direct_map &&
8193 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8194 return;
8195
56028d08
GN		 8196 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8197}
8198
af585b92
GN		 8199static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8200{
8201 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8202}
8203
8204static inline u32 kvm_async_pf_next_probe(u32 key)
8205{
8206 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8207}
8208
8209static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8210{
8211 u32 key = kvm_async_pf_hash_fn(gfn);
8212
8213 while (vcpu->arch.apf.gfns[key] != ~0)
8214 key = kvm_async_pf_next_probe(key);
8215
8216 vcpu->arch.apf.gfns[key] = gfn;
8217}
8218
8219static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8220{
8221 int i;
8222 u32 key = kvm_async_pf_hash_fn(gfn);
8223
8224 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8225 (vcpu->arch.apf.gfns[key] != gfn &&
8226 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8227 key = kvm_async_pf_next_probe(key);
8228
8229 return key;
8230}
8231
8232bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8233{
8234 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8235}
8236
8237static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8238{
8239 u32 i, j, k;
8240
8241 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8242 while (true) {
8243 vcpu->arch.apf.gfns[i] = ~0;
8244 do {
8245 j = kvm_async_pf_next_probe(j);
8246 if (vcpu->arch.apf.gfns[j] == ~0)
8247 return;
8248 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8249 /*
8250 * k lies cyclically in ]i,j]
8251 * | i.k.j |
8252 * |....j i.k.| or |.k..j i...|
8253 */
8254 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8255 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8256 i = j;
8257 }
8258}
8259
7c90705b
GN		 8260static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8261{
8262
8263 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8264 sizeof(val));
8265}
8266
af585b92
GN		 8267void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8268 struct kvm_async_pf *work)
8269{
6389ee94
AK		 8270 struct x86_exception fault;
8271
7c90705b 8272 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8273 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8274
8275 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8276 (vcpu->arch.apf.send_user_only &&
8277 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8278 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8279 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8280 fault.vector = PF_VECTOR;
8281 fault.error_code_valid = true;
8282 fault.error_code = 0;
8283 fault.nested_page_fault = false;
8284 fault.address = work->arch.token;
8285 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8286 }
af585b92
GN		 8287}
8288
8289void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8290 struct kvm_async_pf *work)
8291{
6389ee94
AK		 8292 struct x86_exception fault;
8293
7c90705b 8294 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8295 if (work->wakeup_all)
7c90705b
GN		 8296 work->arch.token = ~0; /* broadcast wakeup */
8297 else
8298 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8299
8300 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8301 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8302 fault.vector = PF_VECTOR;
8303 fault.error_code_valid = true;
8304 fault.error_code = 0;
8305 fault.nested_page_fault = false;
8306 fault.address = work->arch.token;
8307 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8308 }
e6d53e3b 8309 vcpu->arch.apf.halted = false;
a4fa1635 8310 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8311}
8312
8313bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8314{
8315 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8316 return true;
8317 else
8318 return !kvm_event_needs_reinjection(vcpu) &&
8319 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8320}
8321
5544eb9b
PB		 8322void kvm_arch_start_assignment(struct kvm *kvm)
8323{
8324 atomic_inc(&kvm->arch.assigned_device_count);
8325}
8326EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8327
8328void kvm_arch_end_assignment(struct kvm *kvm)
8329{
8330 atomic_dec(&kvm->arch.assigned_device_count);
8331}
8332EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8333
8334bool kvm_arch_has_assigned_device(struct kvm *kvm)
8335{
8336 return atomic_read(&kvm->arch.assigned_device_count);
8337}
8338EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8339
e0f0bbc5
AW		 8340void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8341{
8342 atomic_inc(&kvm->arch.noncoherent_dma_count);
8343}
8344EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8345
8346void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8347{
8348 atomic_dec(&kvm->arch.noncoherent_dma_count);
8349}
8350EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8351
8352bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8353{
8354 return atomic_read(&kvm->arch.noncoherent_dma_count);
8355}
8356EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8357
87276880
FW		 8358int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8359 struct irq_bypass_producer *prod)
8360{
8361 struct kvm_kernel_irqfd *irqfd =
8362 container_of(cons, struct kvm_kernel_irqfd, consumer);
8363
8364 if (kvm_x86_ops->update_pi_irte) {
8365 irqfd->producer = prod;
8366 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8367 prod->irq, irqfd->gsi, 1);
8368 }
8369
8370 return -EINVAL;
8371}
8372
8373void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8374 struct irq_bypass_producer *prod)
8375{
8376 int ret;
8377 struct kvm_kernel_irqfd *irqfd =
8378 container_of(cons, struct kvm_kernel_irqfd, consumer);
8379
8380 if (!kvm_x86_ops->update_pi_irte) {
8381 WARN_ON(irqfd->producer != NULL);
8382 return;
8383 }
8384
8385 WARN_ON(irqfd->producer != prod);
8386 irqfd->producer = NULL;
8387
8388 /*
8389 * When producer of consumer is unregistered, we change back to
8390 * remapped mode, so we can re-use the current implementation
8391 * when the irq is masked/disabed or the consumer side (KVM
8392 * int this case doesn't want to receive the interrupts.
8393 */
8394 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8395 if (ret)
8396 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8397 " fails: %d\n", irqfd->consumer.token, ret);
8398}
8399
8400int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8401 uint32_t guest_irq, bool set)
8402{
8403 if (!kvm_x86_ops->update_pi_irte)
8404 return -EINVAL;
8405
8406 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8407}
8408
52004014
FW		 8409bool kvm_vector_hashing_enabled(void)
8410{
8411 return vector_hashing;
8412}
8413EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8414
229456fc 8415EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8416EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8417EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8418EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8419EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8420EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8421EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8422EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8423EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8424EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8425EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8426EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8427EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8428EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8429EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8430EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8431EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
Linux kernel - Deliverables
This page took 1.933173 seconds and 5 git commands to generate.