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KVM: lapic: adjust preemption timer correctly when goes TSC backward
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
1767e931
PG		 39#include <linux/export.h>
40#include <linux/moduleparam.h>
0de10343 41#include <linux/mman.h>
2bacc55c 42#include <linux/highmem.h>
19de40a8 43#include <linux/iommu.h>
62c476c7 44#include <linux/intel-iommu.h>
c8076604 45#include <linux/cpufreq.h>
18863bdd 46#include <linux/user-return-notifier.h>
a983fb23 47#include <linux/srcu.h>
5a0e3ad6 48#include <linux/slab.h>
ff9d07a0 49#include <linux/perf_event.h>
7bee342a 50#include <linux/uaccess.h>
af585b92 51#include <linux/hash.h>
a1b60c1c 52#include <linux/pci.h>
16e8d74d
MT		 53#include <linux/timekeeper_internal.h>
54#include <linux/pvclock_gtod.h>
87276880
FW		 55#include <linux/kvm_irqfd.h>
56#include <linux/irqbypass.h>
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
043405e1 68
d1898b73
DH		 69#define CREATE_TRACE_POINTS
70#include "trace.h"
71
313a3dc7 72#define MAX_IO_MSRS 256
890ca9ae 73#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 74u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
75EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 76
0f65dd70
AK		 77#define emul_to_vcpu(ctxt) \
78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79
50a37eb4
JR		 80/* EFER defaults:
81 * - enable syscall per default because its emulated by KVM
82 * - enable LME and LMA per default on 64 bit KVM
83 */
84#ifdef CONFIG_X86_64
1260edbe
LJ		 85static
86u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 87#else
1260edbe 88static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 89#endif
313a3dc7 90
ba1389b7
AK		 91#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
92#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 93
c519265f
RK		 94#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 96
cb142eb7 97static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 98static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 99static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 100static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 101
893590c7 102struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 103EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 104
893590c7 105static bool __read_mostly ignore_msrs = 0;
476bc001 106module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 107
9ed96e87
MT		 108unsigned int min_timer_period_us = 500;
109module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
110
630994b3
MT		 111static bool __read_mostly kvmclock_periodic_sync = true;
112module_param(kvmclock_periodic_sync, bool, S_IRUGO);
113
893590c7 114bool __read_mostly kvm_has_tsc_control;
92a1f12d 115EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 116u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 117EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 118u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
119EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
120u64 __read_mostly kvm_max_tsc_scaling_ratio;
121EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 122u64 __read_mostly kvm_default_tsc_scaling_ratio;
123EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 124
cc578287 125/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 126static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 127module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
128
d0659d94 129/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 130unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 131module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
132
52004014
FW		 133static bool __read_mostly vector_hashing = true;
134module_param(vector_hashing, bool, S_IRUGO);
135
893590c7 136static bool __read_mostly backwards_tsc_observed = false;
16a96021 137
18863bdd
AK		 138#define KVM_NR_SHARED_MSRS 16
139
140struct kvm_shared_msrs_global {
141 int nr;
2bf78fa7 142 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 143};
144
145struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
2bf78fa7
SY		 148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 152};
153
154static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 155static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 156
417bc304 157struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 168 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 173 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 181 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 182 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 190 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 192 { "largepages", VM_STAT(lpages) },
417bc304
HB		 193 { NULL }
194};
195
2acf923e
DC		 196u64 __read_mostly host_xcr0;
197
b6785def 198static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 199
af585b92
GN		 200static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
201{
202 int i;
203 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
204 vcpu->arch.apf.gfns[i] = ~0;
205}
206
18863bdd
AK		 207static void kvm_on_user_return(struct user_return_notifier *urn)
208{
209 unsigned slot;
18863bdd
AK		 210 struct kvm_shared_msrs *locals
211 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 212 struct kvm_shared_msr_values *values;
18863bdd
AK		 213
214 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 215 values = &locals->values[slot];
216 if (values->host != values->curr) {
217 wrmsrl(shared_msrs_global.msrs[slot], values->host);
218 values->curr = values->host;
18863bdd
AK		 219 }
220 }
221 locals->registered = false;
222 user_return_notifier_unregister(urn);
223}
224
2bf78fa7 225static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 226{
18863bdd 227 u64 value;
013f6a5d
MT		 228 unsigned int cpu = smp_processor_id();
229 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 230
2bf78fa7
SY		 231 /* only read, and nobody should modify it at this time,
232 * so don't need lock */
233 if (slot >= shared_msrs_global.nr) {
234 printk(KERN_ERR "kvm: invalid MSR slot!");
235 return;
236 }
237 rdmsrl_safe(msr, &value);
238 smsr->values[slot].host = value;
239 smsr->values[slot].curr = value;
240}
241
242void kvm_define_shared_msr(unsigned slot, u32 msr)
243{
0123be42 244 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 245 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 246 if (slot >= shared_msrs_global.nr)
247 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 248}
249EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
250
251static void kvm_shared_msr_cpu_online(void)
252{
253 unsigned i;
18863bdd
AK		 254
255 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 256 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 257}
258
8b3c3104 259int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 260{
013f6a5d
MT		 261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 263 int err;
18863bdd 264
2bf78fa7 265 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 266 return 0;
2bf78fa7 267 smsr->values[slot].curr = value;
8b3c3104
AH		 268 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
269 if (err)
270 return 1;
271
18863bdd
AK		 272 if (!smsr->registered) {
273 smsr->urn.on_user_return = kvm_on_user_return;
274 user_return_notifier_register(&smsr->urn);
275 smsr->registered = true;
276 }
8b3c3104 277 return 0;
18863bdd
AK		 278}
279EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
280
13a34e06 281static void drop_user_return_notifiers(void)
3548bab5 282{
013f6a5d
MT		 283 unsigned int cpu = smp_processor_id();
284 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 285
286 if (smsr->registered)
287 kvm_on_user_return(&smsr->urn);
288}
289
6866b83e
CO		 290u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
291{
8a5a87d9 292 return vcpu->arch.apic_base;
6866b83e
CO		 293}
294EXPORT_SYMBOL_GPL(kvm_get_apic_base);
295
58cb628d
JK		 296int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
297{
298 u64 old_state = vcpu->arch.apic_base &
299 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
300 u64 new_state = msr_info->data &
301 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
302 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
303 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
304
305 if (!msr_info->host_initiated &&
306 ((msr_info->data & reserved_bits) != 0 ||
307 new_state == X2APIC_ENABLE ||
308 (new_state == MSR_IA32_APICBASE_ENABLE &&
309 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
310 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
311 old_state == 0)))
312 return 1;
313
314 kvm_lapic_set_base(vcpu, msr_info->data);
315 return 0;
6866b83e
CO		 316}
317EXPORT_SYMBOL_GPL(kvm_set_apic_base);
318
2605fc21 319asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 320{
321 /* Fault while not rebooting. We want the trace. */
322 BUG();
323}
324EXPORT_SYMBOL_GPL(kvm_spurious_fault);
325
3fd28fce
ED		 326#define EXCPT_BENIGN 0
327#define EXCPT_CONTRIBUTORY 1
328#define EXCPT_PF 2
329
330static int exception_class(int vector)
331{
332 switch (vector) {
333 case PF_VECTOR:
334 return EXCPT_PF;
335 case DE_VECTOR:
336 case TS_VECTOR:
337 case NP_VECTOR:
338 case SS_VECTOR:
339 case GP_VECTOR:
340 return EXCPT_CONTRIBUTORY;
341 default:
342 break;
343 }
344 return EXCPT_BENIGN;
345}
346
d6e8c854
NA		 347#define EXCPT_FAULT 0
348#define EXCPT_TRAP 1
349#define EXCPT_ABORT 2
350#define EXCPT_INTERRUPT 3
351
352static int exception_type(int vector)
353{
354 unsigned int mask;
355
356 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
357 return EXCPT_INTERRUPT;
358
359 mask = 1 << vector;
360
361 /* #DB is trap, as instruction watchpoints are handled elsewhere */
362 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
363 return EXCPT_TRAP;
364
365 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
366 return EXCPT_ABORT;
367
368 /* Reserved exceptions will result in fault */
369 return EXCPT_FAULT;
370}
371
3fd28fce 372static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 373 unsigned nr, bool has_error, u32 error_code,
374 bool reinject)
3fd28fce
ED		 375{
376 u32 prev_nr;
377 int class1, class2;
378
3842d135
AK		 379 kvm_make_request(KVM_REQ_EVENT, vcpu);
380
3fd28fce
ED		 381 if (!vcpu->arch.exception.pending) {
382 queue:
3ffb2468
NA		 383 if (has_error && !is_protmode(vcpu))
384 has_error = false;
3fd28fce
ED		 385 vcpu->arch.exception.pending = true;
386 vcpu->arch.exception.has_error_code = has_error;
387 vcpu->arch.exception.nr = nr;
388 vcpu->arch.exception.error_code = error_code;
3f0fd292 389 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 390 return;
391 }
392
393 /* to check exception */
394 prev_nr = vcpu->arch.exception.nr;
395 if (prev_nr == DF_VECTOR) {
396 /* triple fault -> shutdown */
a8eeb04a 397 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 398 return;
399 }
400 class1 = exception_class(prev_nr);
401 class2 = exception_class(nr);
402 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
403 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
404 /* generate double fault per SDM Table 5-5 */
405 vcpu->arch.exception.pending = true;
406 vcpu->arch.exception.has_error_code = true;
407 vcpu->arch.exception.nr = DF_VECTOR;
408 vcpu->arch.exception.error_code = 0;
409 } else
410 /* replace previous exception with a new one in a hope
411 that instruction re-execution will regenerate lost
412 exception */
413 goto queue;
414}
415
298101da
AK		 416void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
417{
ce7ddec4 418 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 419}
420EXPORT_SYMBOL_GPL(kvm_queue_exception);
421
ce7ddec4
JR		 422void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
423{
424 kvm_multiple_exception(vcpu, nr, false, 0, true);
425}
426EXPORT_SYMBOL_GPL(kvm_requeue_exception);
427
db8fcefa 428void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 429{
db8fcefa
AP		 430 if (err)
431 kvm_inject_gp(vcpu, 0);
432 else
433 kvm_x86_ops->skip_emulated_instruction(vcpu);
434}
435EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 436
6389ee94 437void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 438{
439 ++vcpu->stat.pf_guest;
6389ee94
AK		 440 vcpu->arch.cr2 = fault->address;
441 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 442}
27d6c865 443EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 444
ef54bcfe 445static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 446{
6389ee94
AK		 447 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
448 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 449 else
6389ee94 450 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 451
452 return fault->nested_page_fault;
d4f8cf66
JR		 453}
454
3419ffc8
SY		 455void kvm_inject_nmi(struct kvm_vcpu *vcpu)
456{
7460fb4a
AK		 457 atomic_inc(&vcpu->arch.nmi_queued);
458 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 459}
460EXPORT_SYMBOL_GPL(kvm_inject_nmi);
461
298101da
AK		 462void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
463{
ce7ddec4 464 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 465}
466EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
467
ce7ddec4
JR		 468void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
469{
470 kvm_multiple_exception(vcpu, nr, true, error_code, true);
471}
472EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
473
0a79b009
AK		 474/*
475 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
476 * a #GP and return false.
477 */
478bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 479{
0a79b009
AK		 480 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
481 return true;
482 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
483 return false;
298101da 484}
0a79b009 485EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 486
16f8a6f9
NA		 487bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
488{
489 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
490 return true;
491
492 kvm_queue_exception(vcpu, UD_VECTOR);
493 return false;
494}
495EXPORT_SYMBOL_GPL(kvm_require_dr);
496
ec92fe44
JR		 497/*
498 * This function will be used to read from the physical memory of the currently
54bf36aa 499 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 500 * can read from guest physical or from the guest's guest physical memory.
501 */
502int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
503 gfn_t ngfn, void *data, int offset, int len,
504 u32 access)
505{
54987b7a 506 struct x86_exception exception;
ec92fe44
JR		 507 gfn_t real_gfn;
508 gpa_t ngpa;
509
510 ngpa = gfn_to_gpa(ngfn);
54987b7a 511 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 512 if (real_gfn == UNMAPPED_GVA)
513 return -EFAULT;
514
515 real_gfn = gpa_to_gfn(real_gfn);
516
54bf36aa 517 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 518}
519EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
520
69b0049a 521static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 522 void *data, int offset, int len, u32 access)
523{
524 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
525 data, offset, len, access);
526}
527
a03490ed
CO		 528/*
529 * Load the pae pdptrs. Return true is they are all valid.
530 */
ff03a073 531int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 532{
533 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
534 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
535 int i;
536 int ret;
ff03a073 537 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 538
ff03a073
JR		 539 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
540 offset * sizeof(u64), sizeof(pdpte),
541 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 542 if (ret < 0) {
543 ret = 0;
544 goto out;
545 }
546 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 547 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 548 (pdpte[i] &
549 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 550 ret = 0;
551 goto out;
552 }
553 }
554 ret = 1;
555
ff03a073 556 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 557 __set_bit(VCPU_EXREG_PDPTR,
558 (unsigned long *)&vcpu->arch.regs_avail);
559 __set_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 561out:
a03490ed
CO		 562
563 return ret;
564}
cc4b6871 565EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 566
d835dfec
AK		 567static bool pdptrs_changed(struct kvm_vcpu *vcpu)
568{
ff03a073 569 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 570 bool changed = true;
3d06b8bf
JR		 571 int offset;
572 gfn_t gfn;
d835dfec
AK		 573 int r;
574
575 if (is_long_mode(vcpu) || !is_pae(vcpu))
576 return false;
577
6de4f3ad
AK		 578 if (!test_bit(VCPU_EXREG_PDPTR,
579 (unsigned long *)&vcpu->arch.regs_avail))
580 return true;
581
9f8fe504
AK		 582 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
583 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 584 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
585 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 586 if (r < 0)
587 goto out;
ff03a073 588 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 589out:
d835dfec
AK		 590
591 return changed;
592}
593
49a9b07e 594int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 595{
aad82703 596 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 597 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 598
f9a48e6a
AK		 599 cr0 |= X86_CR0_ET;
600
ab344828 601#ifdef CONFIG_X86_64
0f12244f
GN		 602 if (cr0 & 0xffffffff00000000UL)
603 return 1;
ab344828
GN		 604#endif
605
606 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 607
0f12244f
GN		 608 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
609 return 1;
a03490ed 610
0f12244f
GN		 611 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
612 return 1;
a03490ed
CO		 613
614 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
615#ifdef CONFIG_X86_64
f6801dff 616 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 617 int cs_db, cs_l;
618
0f12244f
GN		 619 if (!is_pae(vcpu))
620 return 1;
a03490ed 621 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 622 if (cs_l)
623 return 1;
a03490ed
CO		 624 } else
625#endif
ff03a073 626 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 627 kvm_read_cr3(vcpu)))
0f12244f 628 return 1;
a03490ed
CO		 629 }
630
ad756a16
MJ		 631 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
632 return 1;
633
a03490ed 634 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 635
d170c419 636 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 637 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 638 kvm_async_pf_hash_reset(vcpu);
639 }
e5f3f027 640
aad82703
SY		 641 if ((cr0 ^ old_cr0) & update_bits)
642 kvm_mmu_reset_context(vcpu);
b18d5431 643
879ae188
LE		 644 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
645 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
646 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 647 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
648
0f12244f
GN		 649 return 0;
650}
2d3ad1f4 651EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 652
2d3ad1f4 653void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 654{
49a9b07e 655 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 656}
2d3ad1f4 657EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 658
42bdf991
MT		 659static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
660{
661 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
662 !vcpu->guest_xcr0_loaded) {
663 /* kvm_set_xcr() also depends on this */
664 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
665 vcpu->guest_xcr0_loaded = 1;
666 }
667}
668
669static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
670{
671 if (vcpu->guest_xcr0_loaded) {
672 if (vcpu->arch.xcr0 != host_xcr0)
673 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
674 vcpu->guest_xcr0_loaded = 0;
675 }
676}
677
69b0049a 678static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 679{
56c103ec
LJ		 680 u64 xcr0 = xcr;
681 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 682 u64 valid_bits;
2acf923e
DC		 683
684 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
685 if (index != XCR_XFEATURE_ENABLED_MASK)
686 return 1;
d91cab78 687 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 688 return 1;
d91cab78 689 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 690 return 1;
46c34cb0
PB		 691
692 /*
693 * Do not allow the guest to set bits that we do not support
694 * saving. However, xcr0 bit 0 is always set, even if the
695 * emulated CPU does not support XSAVE (see fx_init).
696 */
d91cab78 697 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 698 if (xcr0 & ~valid_bits)
2acf923e 699 return 1;
46c34cb0 700
d91cab78
DH		 701 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
702 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 703 return 1;
704
d91cab78
DH		 705 if (xcr0 & XFEATURE_MASK_AVX512) {
706 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 707 return 1;
d91cab78 708 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 709 return 1;
710 }
2acf923e 711 vcpu->arch.xcr0 = xcr0;
56c103ec 712
d91cab78 713 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 714 kvm_update_cpuid(vcpu);
2acf923e
DC		 715 return 0;
716}
717
718int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
719{
764bcbc5
Z		 720 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
721 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 722 kvm_inject_gp(vcpu, 0);
723 return 1;
724 }
725 return 0;
726}
727EXPORT_SYMBOL_GPL(kvm_set_xcr);
728
a83b29c6 729int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 730{
fc78f519 731 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 732 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 733 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 734
0f12244f
GN		 735 if (cr4 & CR4_RESERVED_BITS)
736 return 1;
a03490ed 737
2acf923e
DC		 738 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
739 return 1;
740
c68b734f
YW		 741 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
742 return 1;
743
97ec8c06
FW		 744 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
745 return 1;
746
afcbf13f 747 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 748 return 1;
749
b9baba86
HH		 750 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
751 return 1;
752
a03490ed 753 if (is_long_mode(vcpu)) {
0f12244f
GN		 754 if (!(cr4 & X86_CR4_PAE))
755 return 1;
a2edf57f
AK		 756 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
757 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 758 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
759 kvm_read_cr3(vcpu)))
0f12244f
GN		 760 return 1;
761
ad756a16
MJ		 762 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
763 if (!guest_cpuid_has_pcid(vcpu))
764 return 1;
765
766 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
767 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
768 return 1;
769 }
770
5e1746d6 771 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 772 return 1;
a03490ed 773
ad756a16
MJ		 774 if (((cr4 ^ old_cr4) & pdptr_bits) ||
775 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 776 kvm_mmu_reset_context(vcpu);
0f12244f 777
b9baba86 778 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 779 kvm_update_cpuid(vcpu);
2acf923e 780
0f12244f
GN		 781 return 0;
782}
2d3ad1f4 783EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 784
2390218b 785int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 786{
ac146235 787#ifdef CONFIG_X86_64
9d88fca7 788 cr3 &= ~CR3_PCID_INVD;
ac146235 789#endif
9d88fca7 790
9f8fe504 791 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 792 kvm_mmu_sync_roots(vcpu);
77c3913b 793 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 794 return 0;
d835dfec
AK		 795 }
796
a03490ed 797 if (is_long_mode(vcpu)) {
d9f89b88
JK		 798 if (cr3 & CR3_L_MODE_RESERVED_BITS)
799 return 1;
800 } else if (is_pae(vcpu) && is_paging(vcpu) &&
801 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 802 return 1;
a03490ed 803
0f12244f 804 vcpu->arch.cr3 = cr3;
aff48baa 805 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 806 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 807 return 0;
808}
2d3ad1f4 809EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 810
eea1cff9 811int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 812{
0f12244f
GN		 813 if (cr8 & CR8_RESERVED_BITS)
814 return 1;
35754c98 815 if (lapic_in_kernel(vcpu))
a03490ed
CO		 816 kvm_lapic_set_tpr(vcpu, cr8);
817 else
ad312c7c 818 vcpu->arch.cr8 = cr8;
0f12244f
GN		 819 return 0;
820}
2d3ad1f4 821EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 822
2d3ad1f4 823unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 824{
35754c98 825 if (lapic_in_kernel(vcpu))
a03490ed
CO		 826 return kvm_lapic_get_cr8(vcpu);
827 else
ad312c7c 828 return vcpu->arch.cr8;
a03490ed 829}
2d3ad1f4 830EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 831
ae561ede
NA		 832static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
833{
834 int i;
835
836 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
837 for (i = 0; i < KVM_NR_DB_REGS; i++)
838 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
839 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
840 }
841}
842
73aaf249
JK		 843static void kvm_update_dr6(struct kvm_vcpu *vcpu)
844{
845 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
846 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
847}
848
c8639010
JK		 849static void kvm_update_dr7(struct kvm_vcpu *vcpu)
850{
851 unsigned long dr7;
852
853 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
854 dr7 = vcpu->arch.guest_debug_dr7;
855 else
856 dr7 = vcpu->arch.dr7;
857 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 858 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
859 if (dr7 & DR7_BP_EN_MASK)
860 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 861}
862
6f43ed01
NA		 863static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
864{
865 u64 fixed = DR6_FIXED_1;
866
867 if (!guest_cpuid_has_rtm(vcpu))
868 fixed |= DR6_RTM;
869 return fixed;
870}
871
338dbc97 872static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 873{
874 switch (dr) {
875 case 0 ... 3:
876 vcpu->arch.db[dr] = val;
877 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
878 vcpu->arch.eff_db[dr] = val;
879 break;
880 case 4:
020df079
GN		 881 /* fall through */
882 case 6:
338dbc97
GN		 883 if (val & 0xffffffff00000000ULL)
884 return -1; /* #GP */
6f43ed01 885 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 886 kvm_update_dr6(vcpu);
020df079
GN		 887 break;
888 case 5:
020df079
GN		 889 /* fall through */
890 default: /* 7 */
338dbc97
GN		 891 if (val & 0xffffffff00000000ULL)
892 return -1; /* #GP */
020df079 893 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 894 kvm_update_dr7(vcpu);
020df079
GN		 895 break;
896 }
897
898 return 0;
899}
338dbc97
GN		 900
901int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
902{
16f8a6f9 903 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 904 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 905 return 1;
906 }
907 return 0;
338dbc97 908}
020df079
GN		 909EXPORT_SYMBOL_GPL(kvm_set_dr);
910
16f8a6f9 911int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 912{
913 switch (dr) {
914 case 0 ... 3:
915 *val = vcpu->arch.db[dr];
916 break;
917 case 4:
020df079
GN		 918 /* fall through */
919 case 6:
73aaf249
JK		 920 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
921 *val = vcpu->arch.dr6;
922 else
923 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 924 break;
925 case 5:
020df079
GN		 926 /* fall through */
927 default: /* 7 */
928 *val = vcpu->arch.dr7;
929 break;
930 }
338dbc97
GN		 931 return 0;
932}
020df079
GN		 933EXPORT_SYMBOL_GPL(kvm_get_dr);
934
022cd0e8
AK		 935bool kvm_rdpmc(struct kvm_vcpu *vcpu)
936{
937 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
938 u64 data;
939 int err;
940
c6702c9d 941 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 942 if (err)
943 return err;
944 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
945 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
946 return err;
947}
948EXPORT_SYMBOL_GPL(kvm_rdpmc);
949
043405e1
CO		 950/*
951 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
952 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
953 *
954 * This list is modified at module load time to reflect the
e3267cbb 955 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 956 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
957 * may depend on host virtualization features rather than host cpu features.
043405e1 958 */
e3267cbb 959
043405e1
CO		 960static u32 msrs_to_save[] = {
961 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 962 MSR_STAR,
043405e1
CO		 963#ifdef CONFIG_X86_64
964 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
965#endif
b3897a49 966 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 967 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 968};
969
970static unsigned num_msrs_to_save;
971
62ef68bb
PB		 972static u32 emulated_msrs[] = {
973 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
974 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
975 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
976 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 977 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
978 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 979 HV_X64_MSR_RESET,
11c4b1ca 980 HV_X64_MSR_VP_INDEX,
9eec50b8 981 HV_X64_MSR_VP_RUNTIME,
5c919412 982 HV_X64_MSR_SCONTROL,
1f4b34f8 983 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 984 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
985 MSR_KVM_PV_EOI_EN,
986
ba904635 987 MSR_IA32_TSC_ADJUST,
a3e06bbe 988 MSR_IA32_TSCDEADLINE,
043405e1 989 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 990 MSR_IA32_MCG_STATUS,
991 MSR_IA32_MCG_CTL,
c45dcc71 992 MSR_IA32_MCG_EXT_CTL,
64d60670 993 MSR_IA32_SMBASE,
043405e1
CO		 994};
995
62ef68bb
PB		 996static unsigned num_emulated_msrs;
997
384bb783 998bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 999{
b69e8cae 1000 if (efer & efer_reserved_bits)
384bb783 1001 return false;
15c4a640 1002
1b2fd70c
AG		 1003 if (efer & EFER_FFXSR) {
1004 struct kvm_cpuid_entry2 *feat;
1005
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1007 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1008 return false;
1b2fd70c
AG		 1009 }
1010
d8017474
AG		 1011 if (efer & EFER_SVME) {
1012 struct kvm_cpuid_entry2 *feat;
1013
1014 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1015 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1016 return false;
d8017474
AG		 1017 }
1018
384bb783
JK		 1019 return true;
1020}
1021EXPORT_SYMBOL_GPL(kvm_valid_efer);
1022
1023static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1024{
1025 u64 old_efer = vcpu->arch.efer;
1026
1027 if (!kvm_valid_efer(vcpu, efer))
1028 return 1;
1029
1030 if (is_paging(vcpu)
1031 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1032 return 1;
1033
15c4a640 1034 efer &= ~EFER_LMA;
f6801dff 1035 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1036
a3d204e2
SY		 1037 kvm_x86_ops->set_efer(vcpu, efer);
1038
aad82703
SY		 1039 /* Update reserved bits */
1040 if ((efer ^ old_efer) & EFER_NX)
1041 kvm_mmu_reset_context(vcpu);
1042
b69e8cae 1043 return 0;
15c4a640
CO		 1044}
1045
f2b4b7dd
JR		 1046void kvm_enable_efer_bits(u64 mask)
1047{
1048 efer_reserved_bits &= ~mask;
1049}
1050EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1051
15c4a640
CO		 1052/*
1053 * Writes msr value into into the appropriate "register".
1054 * Returns 0 on success, non-0 otherwise.
1055 * Assumes vcpu_load() was already called.
1056 */
8fe8ab46 1057int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1058{
854e8bb1
NA		 1059 switch (msr->index) {
1060 case MSR_FS_BASE:
1061 case MSR_GS_BASE:
1062 case MSR_KERNEL_GS_BASE:
1063 case MSR_CSTAR:
1064 case MSR_LSTAR:
1065 if (is_noncanonical_address(msr->data))
1066 return 1;
1067 break;
1068 case MSR_IA32_SYSENTER_EIP:
1069 case MSR_IA32_SYSENTER_ESP:
1070 /*
1071 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1072 * non-canonical address is written on Intel but not on
1073 * AMD (which ignores the top 32-bits, because it does
1074 * not implement 64-bit SYSENTER).
1075 *
1076 * 64-bit code should hence be able to write a non-canonical
1077 * value on AMD. Making the address canonical ensures that
1078 * vmentry does not fail on Intel after writing a non-canonical
1079 * value, and that something deterministic happens if the guest
1080 * invokes 64-bit SYSENTER.
1081 */
1082 msr->data = get_canonical(msr->data);
1083 }
8fe8ab46 1084 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1085}
854e8bb1 1086EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1087
313a3dc7
CO		 1088/*
1089 * Adapt set_msr() to msr_io()'s calling convention
1090 */
609e36d3
PB		 1091static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1092{
1093 struct msr_data msr;
1094 int r;
1095
1096 msr.index = index;
1097 msr.host_initiated = true;
1098 r = kvm_get_msr(vcpu, &msr);
1099 if (r)
1100 return r;
1101
1102 *data = msr.data;
1103 return 0;
1104}
1105
313a3dc7
CO		 1106static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1107{
8fe8ab46
WA		 1108 struct msr_data msr;
1109
1110 msr.data = *data;
1111 msr.index = index;
1112 msr.host_initiated = true;
1113 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1114}
1115
16e8d74d
MT		 1116#ifdef CONFIG_X86_64
1117struct pvclock_gtod_data {
1118 seqcount_t seq;
1119
1120 struct { /* extract of a clocksource struct */
1121 int vclock_mode;
1122 cycle_t cycle_last;
1123 cycle_t mask;
1124 u32 mult;
1125 u32 shift;
1126 } clock;
1127
cbcf2dd3
TG		 1128 u64 boot_ns;
1129 u64 nsec_base;
16e8d74d
MT		 1130};
1131
1132static struct pvclock_gtod_data pvclock_gtod_data;
1133
1134static void update_pvclock_gtod(struct timekeeper *tk)
1135{
1136 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1137 u64 boot_ns;
1138
876e7881 1139 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1140
1141 write_seqcount_begin(&vdata->seq);
1142
1143 /* copy pvclock gtod data */
876e7881
PZ		 1144 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1145 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1146 vdata->clock.mask = tk->tkr_mono.mask;
1147 vdata->clock.mult = tk->tkr_mono.mult;
1148 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1149
cbcf2dd3 1150 vdata->boot_ns = boot_ns;
876e7881 1151 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1152
1153 write_seqcount_end(&vdata->seq);
1154}
1155#endif
1156
bab5bb39
NK		 1157void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1158{
1159 /*
1160 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1161 * vcpu_enter_guest. This function is only called from
1162 * the physical CPU that is running vcpu.
1163 */
1164 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1165}
16e8d74d 1166
18068523
GOC		 1167static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1168{
9ed3c444
AK		 1169 int version;
1170 int r;
50d0a0f9 1171 struct pvclock_wall_clock wc;
87aeb54f 1172 struct timespec64 boot;
18068523
GOC		 1173
1174 if (!wall_clock)
1175 return;
1176
9ed3c444
AK		 1177 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1178 if (r)
1179 return;
1180
1181 if (version & 1)
1182 ++version; /* first time write, random junk */
1183
1184 ++version;
18068523 1185
1dab1345
NK		 1186 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1187 return;
18068523 1188
50d0a0f9
GH		 1189 /*
1190 * The guest calculates current wall clock time by adding
34c238a1 1191 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1192 * wall clock specified here. guest system time equals host
1193 * system time for us, thus we must fill in host boot time here.
1194 */
87aeb54f 1195 getboottime64(&boot);
50d0a0f9 1196
4b648665 1197 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1198 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1199 boot = timespec64_sub(boot, ts);
4b648665 1200 }
87aeb54f 1201 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1202 wc.nsec = boot.tv_nsec;
1203 wc.version = version;
18068523
GOC		 1204
1205 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1206
1207 version++;
1208 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1209}
1210
50d0a0f9
GH		 1211static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1212{
b51012de
PB		 1213 do_shl32_div32(dividend, divisor);
1214 return dividend;
50d0a0f9
GH		 1215}
1216
3ae13faa 1217static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1218 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1219{
5f4e3f88 1220 uint64_t scaled64;
50d0a0f9
GH		 1221 int32_t shift = 0;
1222 uint64_t tps64;
1223 uint32_t tps32;
1224
3ae13faa
PB		 1225 tps64 = base_hz;
1226 scaled64 = scaled_hz;
50933623 1227 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1228 tps64 >>= 1;
1229 shift--;
1230 }
1231
1232 tps32 = (uint32_t)tps64;
50933623
JK		 1233 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1234 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1235 scaled64 >>= 1;
1236 else
1237 tps32 <<= 1;
50d0a0f9
GH		 1238 shift++;
1239 }
1240
5f4e3f88
ZA		 1241 *pshift = shift;
1242 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1243
3ae13faa
PB		 1244 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1245 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1246}
1247
d828199e 1248#ifdef CONFIG_X86_64
16e8d74d 1249static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1250#endif
16e8d74d 1251
c8076604 1252static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1253static unsigned long max_tsc_khz;
c8076604 1254
cc578287 1255static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1256{
cc578287
ZA		 1257 u64 v = (u64)khz * (1000000 + ppm);
1258 do_div(v, 1000000);
1259 return v;
1e993611
JR		 1260}
1261
381d585c
HZ		 1262static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1263{
1264 u64 ratio;
1265
1266 /* Guest TSC same frequency as host TSC? */
1267 if (!scale) {
1268 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1269 return 0;
1270 }
1271
1272 /* TSC scaling supported? */
1273 if (!kvm_has_tsc_control) {
1274 if (user_tsc_khz > tsc_khz) {
1275 vcpu->arch.tsc_catchup = 1;
1276 vcpu->arch.tsc_always_catchup = 1;
1277 return 0;
1278 } else {
1279 WARN(1, "user requested TSC rate below hardware speed\n");
1280 return -1;
1281 }
1282 }
1283
1284 /* TSC scaling required - calculate ratio */
1285 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1286 user_tsc_khz, tsc_khz);
1287
1288 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1289 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1290 user_tsc_khz);
1291 return -1;
1292 }
1293
1294 vcpu->arch.tsc_scaling_ratio = ratio;
1295 return 0;
1296}
1297
4941b8cb 1298static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1299{
cc578287
ZA		 1300 u32 thresh_lo, thresh_hi;
1301 int use_scaling = 0;
217fc9cf 1302
03ba32ca 1303 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1304 if (user_tsc_khz == 0) {
ad721883
HZ		 1305 /* set tsc_scaling_ratio to a safe value */
1306 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1307 return -1;
ad721883 1308 }
03ba32ca 1309
c285545f 1310 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1311 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1312 &vcpu->arch.virtual_tsc_shift,
1313 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1314 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1315
1316 /*
1317 * Compute the variation in TSC rate which is acceptable
1318 * within the range of tolerance and decide if the
1319 * rate being applied is within that bounds of the hardware
1320 * rate. If so, no scaling or compensation need be done.
1321 */
1322 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1323 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1324 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1325 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1326 use_scaling = 1;
1327 }
4941b8cb 1328 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1329}
1330
1331static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1332{
e26101b1 1333 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1334 vcpu->arch.virtual_tsc_mult,
1335 vcpu->arch.virtual_tsc_shift);
e26101b1 1336 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1337 return tsc;
1338}
1339
69b0049a 1340static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1341{
1342#ifdef CONFIG_X86_64
1343 bool vcpus_matched;
b48aa97e
MT		 1344 struct kvm_arch *ka = &vcpu->kvm->arch;
1345 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1346
1347 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1348 atomic_read(&vcpu->kvm->online_vcpus));
1349
7f187922
MT		 1350 /*
1351 * Once the masterclock is enabled, always perform request in
1352 * order to update it.
1353 *
1354 * In order to enable masterclock, the host clocksource must be TSC
1355 * and the vcpus need to have matched TSCs. When that happens,
1356 * perform request to enable masterclock.
1357 */
1358 if (ka->use_master_clock ||
1359 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1360 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1361
1362 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1363 atomic_read(&vcpu->kvm->online_vcpus),
1364 ka->use_master_clock, gtod->clock.vclock_mode);
1365#endif
1366}
1367
ba904635
WA		 1368static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1369{
1370 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1371 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1372}
1373
35181e86
HZ		 1374/*
1375 * Multiply tsc by a fixed point number represented by ratio.
1376 *
1377 * The most significant 64-N bits (mult) of ratio represent the
1378 * integral part of the fixed point number; the remaining N bits
1379 * (frac) represent the fractional part, ie. ratio represents a fixed
1380 * point number (mult + frac * 2^(-N)).
1381 *
1382 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1383 */
1384static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1385{
1386 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1387}
1388
1389u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1390{
1391 u64 _tsc = tsc;
1392 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1393
1394 if (ratio != kvm_default_tsc_scaling_ratio)
1395 _tsc = __scale_tsc(ratio, tsc);
1396
1397 return _tsc;
1398}
1399EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1400
07c1419a
HZ		 1401static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1402{
1403 u64 tsc;
1404
1405 tsc = kvm_scale_tsc(vcpu, rdtsc());
1406
1407 return target_tsc - tsc;
1408}
1409
4ba76538
HZ		 1410u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1411{
1412 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1413}
1414EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1415
8fe8ab46 1416void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1417{
1418 struct kvm *kvm = vcpu->kvm;
f38e098f 1419 u64 offset, ns, elapsed;
99e3e30a 1420 unsigned long flags;
02626b6a 1421 s64 usdiff;
b48aa97e 1422 bool matched;
0d3da0d2 1423 bool already_matched;
8fe8ab46 1424 u64 data = msr->data;
99e3e30a 1425
038f8c11 1426 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1427 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1428 ns = get_kernel_ns();
f38e098f 1429 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1430
03ba32ca 1431 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1432 int faulted = 0;
1433
03ba32ca
MT		 1434 /* n.b - signed multiplication and division required */
1435 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1436#ifdef CONFIG_X86_64
03ba32ca 1437 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1438#else
03ba32ca 1439 /* do_div() only does unsigned */
8915aa27
MT		 1440 asm("1: idivl %[divisor]\n"
1441 "2: xor %%edx, %%edx\n"
1442 " movl $0, %[faulted]\n"
1443 "3:\n"
1444 ".section .fixup,\"ax\"\n"
1445 "4: movl $1, %[faulted]\n"
1446 " jmp 3b\n"
1447 ".previous\n"
1448
1449 _ASM_EXTABLE(1b, 4b)
1450
1451 : "=A"(usdiff), [faulted] "=r" (faulted)
1452 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1453
5d3cb0f6 1454#endif
03ba32ca
MT		 1455 do_div(elapsed, 1000);
1456 usdiff -= elapsed;
1457 if (usdiff < 0)
1458 usdiff = -usdiff;
8915aa27
MT		 1459
1460 /* idivl overflow => difference is larger than USEC_PER_SEC */
1461 if (faulted)
1462 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1463 } else
1464 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1465
1466 /*
5d3cb0f6
ZA		 1467 * Special case: TSC write with a small delta (1 second) of virtual
1468 * cycle time against real time is interpreted as an attempt to
1469 * synchronize the CPU.
1470 *
1471 * For a reliable TSC, we can match TSC offsets, and for an unstable
1472 * TSC, we add elapsed time in this computation. We could let the
1473 * compensation code attempt to catch up if we fall behind, but
1474 * it's better to try to match offsets from the beginning.
1475 */
02626b6a 1476 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1477 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1478 if (!check_tsc_unstable()) {
e26101b1 1479 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1480 pr_debug("kvm: matched tsc offset for %llu\n", data);
1481 } else {
857e4099 1482 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1483 data += delta;
07c1419a 1484 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1485 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1486 }
b48aa97e 1487 matched = true;
0d3da0d2 1488 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1489 } else {
1490 /*
1491 * We split periods of matched TSC writes into generations.
1492 * For each generation, we track the original measured
1493 * nanosecond time, offset, and write, so if TSCs are in
1494 * sync, we can match exact offset, and if not, we can match
4a969980 1495 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1496 *
1497 * These values are tracked in kvm->arch.cur_xxx variables.
1498 */
1499 kvm->arch.cur_tsc_generation++;
1500 kvm->arch.cur_tsc_nsec = ns;
1501 kvm->arch.cur_tsc_write = data;
1502 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1503 matched = false;
0d3da0d2 1504 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1505 kvm->arch.cur_tsc_generation, data);
f38e098f 1506 }
e26101b1
ZA		 1507
1508 /*
1509 * We also track th most recent recorded KHZ, write and time to
1510 * allow the matching interval to be extended at each write.
1511 */
f38e098f
ZA		 1512 kvm->arch.last_tsc_nsec = ns;
1513 kvm->arch.last_tsc_write = data;
5d3cb0f6 1514 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1515
b183aa58 1516 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1517
1518 /* Keep track of which generation this VCPU has synchronized to */
1519 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1520 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1521 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1522
ba904635
WA		 1523 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1524 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1525 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1526 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1527
1528 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1529 if (!matched) {
b48aa97e 1530 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1531 } else if (!already_matched) {
1532 kvm->arch.nr_vcpus_matched_tsc++;
1533 }
b48aa97e
MT		 1534
1535 kvm_track_tsc_matching(vcpu);
1536 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1537}
e26101b1 1538
99e3e30a
ZA		 1539EXPORT_SYMBOL_GPL(kvm_write_tsc);
1540
58ea6767
HZ		 1541static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1542 s64 adjustment)
1543{
1544 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1545}
1546
1547static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1548{
1549 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1550 WARN_ON(adjustment < 0);
1551 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1552 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1553}
1554
d828199e
MT		 1555#ifdef CONFIG_X86_64
1556
1557static cycle_t read_tsc(void)
1558{
03b9730b
AL		 1559 cycle_t ret = (cycle_t)rdtsc_ordered();
1560 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1561
1562 if (likely(ret >= last))
1563 return ret;
1564
1565 /*
1566 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1567 * predictable (it's just a function of time and the likely is
d828199e
MT		 1568 * very likely) and there's a data dependence, so force GCC
1569 * to generate a branch instead. I don't barrier() because
1570 * we don't actually need a barrier, and if this function
1571 * ever gets inlined it will generate worse code.
1572 */
1573 asm volatile ("");
1574 return last;
1575}
1576
1577static inline u64 vgettsc(cycle_t *cycle_now)
1578{
1579 long v;
1580 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1581
1582 *cycle_now = read_tsc();
1583
1584 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1585 return v * gtod->clock.mult;
1586}
1587
cbcf2dd3 1588static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1589{
cbcf2dd3 1590 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1591 unsigned long seq;
d828199e 1592 int mode;
cbcf2dd3 1593 u64 ns;
d828199e 1594
d828199e
MT		 1595 do {
1596 seq = read_seqcount_begin(&gtod->seq);
1597 mode = gtod->clock.vclock_mode;
cbcf2dd3 1598 ns = gtod->nsec_base;
d828199e
MT		 1599 ns += vgettsc(cycle_now);
1600 ns >>= gtod->clock.shift;
cbcf2dd3 1601 ns += gtod->boot_ns;
d828199e 1602 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1603 *t = ns;
d828199e
MT		 1604
1605 return mode;
1606}
1607
1608/* returns true if host is using tsc clocksource */
1609static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1610{
d828199e
MT		 1611 /* checked again under seqlock below */
1612 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1613 return false;
1614
cbcf2dd3 1615 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1616}
1617#endif
1618
1619/*
1620 *
b48aa97e
MT		 1621 * Assuming a stable TSC across physical CPUS, and a stable TSC
1622 * across virtual CPUs, the following condition is possible.
1623 * Each numbered line represents an event visible to both
d828199e
MT		 1624 * CPUs at the next numbered event.
1625 *
1626 * "timespecX" represents host monotonic time. "tscX" represents
1627 * RDTSC value.
1628 *
1629 * VCPU0 on CPU0 | VCPU1 on CPU1
1630 *
1631 * 1. read timespec0,tsc0
1632 * 2. | timespec1 = timespec0 + N
1633 * | tsc1 = tsc0 + M
1634 * 3. transition to guest | transition to guest
1635 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1636 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1637 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1638 *
1639 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1640 *
1641 * - ret0 < ret1
1642 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1643 * ...
1644 * - 0 < N - M => M < N
1645 *
1646 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1647 * always the case (the difference between two distinct xtime instances
1648 * might be smaller then the difference between corresponding TSC reads,
1649 * when updating guest vcpus pvclock areas).
1650 *
1651 * To avoid that problem, do not allow visibility of distinct
1652 * system_timestamp/tsc_timestamp values simultaneously: use a master
1653 * copy of host monotonic time values. Update that master copy
1654 * in lockstep.
1655 *
b48aa97e 1656 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1657 *
1658 */
1659
1660static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1661{
1662#ifdef CONFIG_X86_64
1663 struct kvm_arch *ka = &kvm->arch;
1664 int vclock_mode;
b48aa97e
MT		 1665 bool host_tsc_clocksource, vcpus_matched;
1666
1667 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1668 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1669
1670 /*
1671 * If the host uses TSC clock, then passthrough TSC as stable
1672 * to the guest.
1673 */
b48aa97e 1674 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1675 &ka->master_kernel_ns,
1676 &ka->master_cycle_now);
1677
16a96021 1678 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1679 && !backwards_tsc_observed
1680 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1681
d828199e
MT		 1682 if (ka->use_master_clock)
1683 atomic_set(&kvm_guest_has_master_clock, 1);
1684
1685 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1686 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1687 vcpus_matched);
d828199e
MT		 1688#endif
1689}
1690
2860c4b1
PB		 1691void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1692{
1693 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1694}
1695
2e762ff7
MT		 1696static void kvm_gen_update_masterclock(struct kvm *kvm)
1697{
1698#ifdef CONFIG_X86_64
1699 int i;
1700 struct kvm_vcpu *vcpu;
1701 struct kvm_arch *ka = &kvm->arch;
1702
1703 spin_lock(&ka->pvclock_gtod_sync_lock);
1704 kvm_make_mclock_inprogress_request(kvm);
1705 /* no guest entries from this point */
1706 pvclock_update_vm_gtod_copy(kvm);
1707
1708 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1709 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1710
1711 /* guest entries allowed */
1712 kvm_for_each_vcpu(i, vcpu, kvm)
1713 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1714
1715 spin_unlock(&ka->pvclock_gtod_sync_lock);
1716#endif
1717}
1718
34c238a1 1719static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1720{
78db6a50 1721 unsigned long flags, tgt_tsc_khz;
18068523 1722 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1723 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1724 s64 kernel_ns;
d828199e 1725 u64 tsc_timestamp, host_tsc;
0b79459b 1726 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1727 u8 pvclock_flags;
d828199e
MT		 1728 bool use_master_clock;
1729
1730 kernel_ns = 0;
1731 host_tsc = 0;
18068523 1732
d828199e
MT		 1733 /*
1734 * If the host uses TSC clock, then passthrough TSC as stable
1735 * to the guest.
1736 */
1737 spin_lock(&ka->pvclock_gtod_sync_lock);
1738 use_master_clock = ka->use_master_clock;
1739 if (use_master_clock) {
1740 host_tsc = ka->master_cycle_now;
1741 kernel_ns = ka->master_kernel_ns;
1742 }
1743 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1744
1745 /* Keep irq disabled to prevent changes to the clock */
1746 local_irq_save(flags);
78db6a50
PB		 1747 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1748 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1749 local_irq_restore(flags);
1750 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1751 return 1;
1752 }
d828199e 1753 if (!use_master_clock) {
4ea1636b 1754 host_tsc = rdtsc();
d828199e
MT		 1755 kernel_ns = get_kernel_ns();
1756 }
1757
4ba76538 1758 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1759
c285545f
ZA		 1760 /*
1761 * We may have to catch up the TSC to match elapsed wall clock
1762 * time for two reasons, even if kvmclock is used.
1763 * 1) CPU could have been running below the maximum TSC rate
1764 * 2) Broken TSC compensation resets the base at each VCPU
1765 * entry to avoid unknown leaps of TSC even when running
1766 * again on the same CPU. This may cause apparent elapsed
1767 * time to disappear, and the guest to stand still or run
1768 * very slowly.
1769 */
1770 if (vcpu->tsc_catchup) {
1771 u64 tsc = compute_guest_tsc(v, kernel_ns);
1772 if (tsc > tsc_timestamp) {
f1e2b260 1773 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1774 tsc_timestamp = tsc;
1775 }
50d0a0f9
GH		 1776 }
1777
18068523
GOC		 1778 local_irq_restore(flags);
1779
0b79459b 1780 if (!vcpu->pv_time_enabled)
c285545f 1781 return 0;
18068523 1782
78db6a50
PB		 1783 if (kvm_has_tsc_control)
1784 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1785
1786 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1787 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1788 &vcpu->hv_clock.tsc_shift,
1789 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1790 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1791 }
1792
1793 /* With all the info we got, fill in the values */
1d5f066e 1794 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1795 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1796 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1797
09a0c3f1
OH		 1798 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1799 &guest_hv_clock, sizeof(guest_hv_clock))))
1800 return 0;
1801
5dca0d91
RK		 1802 /* This VCPU is paused, but it's legal for a guest to read another
1803 * VCPU's kvmclock, so we really have to follow the specification where
1804 * it says that version is odd if data is being modified, and even after
1805 * it is consistent.
1806 *
1807 * Version field updates must be kept separate. This is because
1808 * kvm_write_guest_cached might use a "rep movs" instruction, and
1809 * writes within a string instruction are weakly ordered. So there
1810 * are three writes overall.
1811 *
1812 * As a small optimization, only write the version field in the first
1813 * and third write. The vcpu->pv_time cache is still valid, because the
1814 * version field is the first in the struct.
18068523 1815 */
5dca0d91
RK		 1816 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1817
1818 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1819 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1820 &vcpu->hv_clock,
1821 sizeof(vcpu->hv_clock.version));
1822
1823 smp_wmb();
78c0337a
MT		 1824
1825 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1826 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1827
1828 if (vcpu->pvclock_set_guest_stopped_request) {
1829 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1830 vcpu->pvclock_set_guest_stopped_request = false;
1831 }
1832
d828199e
MT		 1833 /* If the host uses TSC clocksource, then it is stable */
1834 if (use_master_clock)
1835 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1836
78c0337a
MT		 1837 vcpu->hv_clock.flags = pvclock_flags;
1838
ce1a5e60
DM		 1839 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1840
0b79459b
AH		 1841 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1842 &vcpu->hv_clock,
1843 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1844
1845 smp_wmb();
1846
1847 vcpu->hv_clock.version++;
1848 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1849 &vcpu->hv_clock,
1850 sizeof(vcpu->hv_clock.version));
8cfdc000 1851 return 0;
c8076604
GH		 1852}
1853
0061d53d
MT		 1854/*
1855 * kvmclock updates which are isolated to a given vcpu, such as
1856 * vcpu->cpu migration, should not allow system_timestamp from
1857 * the rest of the vcpus to remain static. Otherwise ntp frequency
1858 * correction applies to one vcpu's system_timestamp but not
1859 * the others.
1860 *
1861 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1862 * We need to rate-limit these requests though, as they can
1863 * considerably slow guests that have a large number of vcpus.
1864 * The time for a remote vcpu to update its kvmclock is bound
1865 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1866 */
1867
7e44e449
AJ		 1868#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1869
1870static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1871{
1872 int i;
7e44e449
AJ		 1873 struct delayed_work *dwork = to_delayed_work(work);
1874 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1875 kvmclock_update_work);
1876 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1877 struct kvm_vcpu *vcpu;
1878
1879 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1880 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1881 kvm_vcpu_kick(vcpu);
1882 }
1883}
1884
7e44e449
AJ		 1885static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1886{
1887 struct kvm *kvm = v->kvm;
1888
105b21bb 1889 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1890 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1891 KVMCLOCK_UPDATE_DELAY);
1892}
1893
332967a3
AJ		 1894#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1895
1896static void kvmclock_sync_fn(struct work_struct *work)
1897{
1898 struct delayed_work *dwork = to_delayed_work(work);
1899 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1900 kvmclock_sync_work);
1901 struct kvm *kvm = container_of(ka, struct kvm, arch);
1902
630994b3
MT		 1903 if (!kvmclock_periodic_sync)
1904 return;
1905
332967a3
AJ		 1906 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1907 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1908 KVMCLOCK_SYNC_PERIOD);
1909}
1910
890ca9ae 1911static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1912{
890ca9ae
HY		 1913 u64 mcg_cap = vcpu->arch.mcg_cap;
1914 unsigned bank_num = mcg_cap & 0xff;
1915
15c4a640 1916 switch (msr) {
15c4a640 1917 case MSR_IA32_MCG_STATUS:
890ca9ae 1918 vcpu->arch.mcg_status = data;
15c4a640 1919 break;
c7ac679c 1920 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1921 if (!(mcg_cap & MCG_CTL_P))
1922 return 1;
1923 if (data != 0 && data != ~(u64)0)
1924 return -1;
1925 vcpu->arch.mcg_ctl = data;
1926 break;
1927 default:
1928 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1929 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1930 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1931 /* only 0 or all 1s can be written to IA32_MCi_CTL
1932 * some Linux kernels though clear bit 10 in bank 4 to
1933 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1934 * this to avoid an uncatched #GP in the guest
1935 */
890ca9ae 1936 if ((offset & 0x3) == 0 &&
114be429 1937 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1938 return -1;
1939 vcpu->arch.mce_banks[offset] = data;
1940 break;
1941 }
1942 return 1;
1943 }
1944 return 0;
1945}
1946
ffde22ac
ES		 1947static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1948{
1949 struct kvm *kvm = vcpu->kvm;
1950 int lm = is_long_mode(vcpu);
1951 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1952 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1953 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1954 : kvm->arch.xen_hvm_config.blob_size_32;
1955 u32 page_num = data & ~PAGE_MASK;
1956 u64 page_addr = data & PAGE_MASK;
1957 u8 *page;
1958 int r;
1959
1960 r = -E2BIG;
1961 if (page_num >= blob_size)
1962 goto out;
1963 r = -ENOMEM;
ff5c2c03
SL		 1964 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1965 if (IS_ERR(page)) {
1966 r = PTR_ERR(page);
ffde22ac 1967 goto out;
ff5c2c03 1968 }
54bf36aa 1969 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1970 goto out_free;
1971 r = 0;
1972out_free:
1973 kfree(page);
1974out:
1975 return r;
1976}
1977
344d9588
GN		 1978static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1979{
1980 gpa_t gpa = data & ~0x3f;
1981
4a969980 1982 /* Bits 2:5 are reserved, Should be zero */
6adba527 1983 if (data & 0x3c)
344d9588
GN		 1984 return 1;
1985
1986 vcpu->arch.apf.msr_val = data;
1987
1988 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1989 kvm_clear_async_pf_completion_queue(vcpu);
1990 kvm_async_pf_hash_reset(vcpu);
1991 return 0;
1992 }
1993
8f964525
AH		 1994 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1995 sizeof(u32)))
344d9588
GN		 1996 return 1;
1997
6adba527 1998 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1999 kvm_async_pf_wakeup_all(vcpu);
2000 return 0;
2001}
2002
12f9a48f
GC		 2003static void kvmclock_reset(struct kvm_vcpu *vcpu)
2004{
0b79459b 2005 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2006}
2007
c9aaa895
GC		 2008static void record_steal_time(struct kvm_vcpu *vcpu)
2009{
2010 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2011 return;
2012
2013 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2014 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2015 return;
2016
35f3fae1
WL		 2017 if (vcpu->arch.st.steal.version & 1)
2018 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2019
2020 vcpu->arch.st.steal.version += 1;
2021
2022 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2023 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2024
2025 smp_wmb();
2026
c54cdf14
LC		 2027 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2028 vcpu->arch.st.last_steal;
2029 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2030
2031 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2032 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2033
2034 smp_wmb();
2035
2036 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2037
2038 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2039 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2040}
2041
8fe8ab46 2042int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2043{
5753785f 2044 bool pr = false;
8fe8ab46
WA		 2045 u32 msr = msr_info->index;
2046 u64 data = msr_info->data;
5753785f 2047
15c4a640 2048 switch (msr) {
2e32b719
BP		 2049 case MSR_AMD64_NB_CFG:
2050 case MSR_IA32_UCODE_REV:
2051 case MSR_IA32_UCODE_WRITE:
2052 case MSR_VM_HSAVE_PA:
2053 case MSR_AMD64_PATCH_LOADER:
2054 case MSR_AMD64_BU_CFG2:
2055 break;
2056
15c4a640 2057 case MSR_EFER:
b69e8cae 2058 return set_efer(vcpu, data);
8f1589d9
AP		 2059 case MSR_K7_HWCR:
2060 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2061 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2062 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2063 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2064 if (data != 0) {
a737f256
CD		 2065 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2066 data);
8f1589d9
AP		 2067 return 1;
2068 }
15c4a640 2069 break;
f7c6d140
AP		 2070 case MSR_FAM10H_MMIO_CONF_BASE:
2071 if (data != 0) {
a737f256
CD		 2072 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2073 "0x%llx\n", data);
f7c6d140
AP		 2074 return 1;
2075 }
15c4a640 2076 break;
b5e2fec0
AG		 2077 case MSR_IA32_DEBUGCTLMSR:
2078 if (!data) {
2079 /* We support the non-activated case already */
2080 break;
2081 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2082 /* Values other than LBR and BTF are vendor-specific,
2083 thus reserved and should throw a #GP */
2084 return 1;
2085 }
a737f256
CD		 2086 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2087 __func__, data);
b5e2fec0 2088 break;
9ba075a6 2089 case 0x200 ... 0x2ff:
ff53604b 2090 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2091 case MSR_IA32_APICBASE:
58cb628d 2092 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2093 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2094 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2095 case MSR_IA32_TSCDEADLINE:
2096 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2097 break;
ba904635
WA		 2098 case MSR_IA32_TSC_ADJUST:
2099 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2100 if (!msr_info->host_initiated) {
d913b904 2101 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2102 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2103 }
2104 vcpu->arch.ia32_tsc_adjust_msr = data;
2105 }
2106 break;
15c4a640 2107 case MSR_IA32_MISC_ENABLE:
ad312c7c 2108 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2109 break;
64d60670
PB		 2110 case MSR_IA32_SMBASE:
2111 if (!msr_info->host_initiated)
2112 return 1;
2113 vcpu->arch.smbase = data;
2114 break;
11c6bffa 2115 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2116 case MSR_KVM_WALL_CLOCK:
2117 vcpu->kvm->arch.wall_clock = data;
2118 kvm_write_wall_clock(vcpu->kvm, data);
2119 break;
11c6bffa 2120 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2121 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2122 u64 gpa_offset;
54750f2c
MT		 2123 struct kvm_arch *ka = &vcpu->kvm->arch;
2124
12f9a48f 2125 kvmclock_reset(vcpu);
18068523 2126
54750f2c
MT		 2127 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2128 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2129
2130 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2131 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2132 &vcpu->requests);
2133
2134 ka->boot_vcpu_runs_old_kvmclock = tmp;
2135 }
2136
18068523 2137 vcpu->arch.time = data;
0061d53d 2138 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2139
2140 /* we verify if the enable bit is set... */
2141 if (!(data & 1))
2142 break;
2143
0b79459b 2144 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2145
0b79459b 2146 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2147 &vcpu->arch.pv_time, data & ~1ULL,
2148 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2149 vcpu->arch.pv_time_enabled = false;
2150 else
2151 vcpu->arch.pv_time_enabled = true;
32cad84f 2152
18068523
GOC		 2153 break;
2154 }
344d9588
GN		 2155 case MSR_KVM_ASYNC_PF_EN:
2156 if (kvm_pv_enable_async_pf(vcpu, data))
2157 return 1;
2158 break;
c9aaa895
GC		 2159 case MSR_KVM_STEAL_TIME:
2160
2161 if (unlikely(!sched_info_on()))
2162 return 1;
2163
2164 if (data & KVM_STEAL_RESERVED_MASK)
2165 return 1;
2166
2167 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2168 data & KVM_STEAL_VALID_BITS,
2169 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2170 return 1;
2171
2172 vcpu->arch.st.msr_val = data;
2173
2174 if (!(data & KVM_MSR_ENABLED))
2175 break;
2176
c9aaa895
GC		 2177 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2178
2179 break;
ae7a2a3f
MT		 2180 case MSR_KVM_PV_EOI_EN:
2181 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2182 return 1;
2183 break;
c9aaa895 2184
890ca9ae
HY		 2185 case MSR_IA32_MCG_CTL:
2186 case MSR_IA32_MCG_STATUS:
81760dcc 2187 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2188 return set_msr_mce(vcpu, msr, data);
71db6023 2189
6912ac32
WH		 2190 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2191 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2192 pr = true; /* fall through */
2193 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2194 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2195 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2196 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2197
2198 if (pr || data != 0)
a737f256
CD		 2199 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2200 "0x%x data 0x%llx\n", msr, data);
5753785f 2201 break;
84e0cefa
JS		 2202 case MSR_K7_CLK_CTL:
2203 /*
2204 * Ignore all writes to this no longer documented MSR.
2205 * Writes are only relevant for old K7 processors,
2206 * all pre-dating SVM, but a recommended workaround from
4a969980 2207 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2208 * affected processor models on the command line, hence
2209 * the need to ignore the workaround.
2210 */
2211 break;
55cd8e5a 2212 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2213 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2214 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2215 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2216 return kvm_hv_set_msr_common(vcpu, msr, data,
2217 msr_info->host_initiated);
91c9c3ed 2218 case MSR_IA32_BBL_CR_CTL3:
2219 /* Drop writes to this legacy MSR -- see rdmsr
2220 * counterpart for further detail.
2221 */
a737f256 2222 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2223 break;
2b036c6b
BO		 2224 case MSR_AMD64_OSVW_ID_LENGTH:
2225 if (!guest_cpuid_has_osvw(vcpu))
2226 return 1;
2227 vcpu->arch.osvw.length = data;
2228 break;
2229 case MSR_AMD64_OSVW_STATUS:
2230 if (!guest_cpuid_has_osvw(vcpu))
2231 return 1;
2232 vcpu->arch.osvw.status = data;
2233 break;
15c4a640 2234 default:
ffde22ac
ES		 2235 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2236 return xen_hvm_config(vcpu, data);
c6702c9d 2237 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2238 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2239 if (!ignore_msrs) {
a737f256
CD		 2240 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2241 msr, data);
ed85c068
AP		 2242 return 1;
2243 } else {
a737f256
CD		 2244 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2245 msr, data);
ed85c068
AP		 2246 break;
2247 }
15c4a640
CO		 2248 }
2249 return 0;
2250}
2251EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2252
2253
2254/*
2255 * Reads an msr value (of 'msr_index') into 'pdata'.
2256 * Returns 0 on success, non-0 otherwise.
2257 * Assumes vcpu_load() was already called.
2258 */
609e36d3 2259int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2260{
609e36d3 2261 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2262}
ff651cb6 2263EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2264
890ca9ae 2265static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2266{
2267 u64 data;
890ca9ae
HY		 2268 u64 mcg_cap = vcpu->arch.mcg_cap;
2269 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2270
2271 switch (msr) {
15c4a640
CO		 2272 case MSR_IA32_P5_MC_ADDR:
2273 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2274 data = 0;
2275 break;
15c4a640 2276 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2277 data = vcpu->arch.mcg_cap;
2278 break;
c7ac679c 2279 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2280 if (!(mcg_cap & MCG_CTL_P))
2281 return 1;
2282 data = vcpu->arch.mcg_ctl;
2283 break;
2284 case MSR_IA32_MCG_STATUS:
2285 data = vcpu->arch.mcg_status;
2286 break;
2287 default:
2288 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2289 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2290 u32 offset = msr - MSR_IA32_MC0_CTL;
2291 data = vcpu->arch.mce_banks[offset];
2292 break;
2293 }
2294 return 1;
2295 }
2296 *pdata = data;
2297 return 0;
2298}
2299
609e36d3 2300int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2301{
609e36d3 2302 switch (msr_info->index) {
890ca9ae 2303 case MSR_IA32_PLATFORM_ID:
15c4a640 2304 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2305 case MSR_IA32_DEBUGCTLMSR:
2306 case MSR_IA32_LASTBRANCHFROMIP:
2307 case MSR_IA32_LASTBRANCHTOIP:
2308 case MSR_IA32_LASTINTFROMIP:
2309 case MSR_IA32_LASTINTTOIP:
60af2ecd 2310 case MSR_K8_SYSCFG:
3afb1121
PB		 2311 case MSR_K8_TSEG_ADDR:
2312 case MSR_K8_TSEG_MASK:
60af2ecd 2313 case MSR_K7_HWCR:
61a6bd67 2314 case MSR_VM_HSAVE_PA:
1fdbd48c 2315 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2316 case MSR_AMD64_NB_CFG:
f7c6d140 2317 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2318 case MSR_AMD64_BU_CFG2:
0c2df2a1 2319 case MSR_IA32_PERF_CTL:
609e36d3 2320 msr_info->data = 0;
15c4a640 2321 break;
6912ac32
WH		 2322 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2323 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2324 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2325 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2326 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2327 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2328 msr_info->data = 0;
5753785f 2329 break;
742bc670 2330 case MSR_IA32_UCODE_REV:
609e36d3 2331 msr_info->data = 0x100000000ULL;
742bc670 2332 break;
9ba075a6 2333 case MSR_MTRRcap:
9ba075a6 2334 case 0x200 ... 0x2ff:
ff53604b 2335 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2336 case 0xcd: /* fsb frequency */
609e36d3 2337 msr_info->data = 3;
15c4a640 2338 break;
7b914098
JS		 2339 /*
2340 * MSR_EBC_FREQUENCY_ID
2341 * Conservative value valid for even the basic CPU models.
2342 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2343 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2344 * and 266MHz for model 3, or 4. Set Core Clock
2345 * Frequency to System Bus Frequency Ratio to 1 (bits
2346 * 31:24) even though these are only valid for CPU
2347 * models > 2, however guests may end up dividing or
2348 * multiplying by zero otherwise.
2349 */
2350 case MSR_EBC_FREQUENCY_ID:
609e36d3 2351 msr_info->data = 1 << 24;
7b914098 2352 break;
15c4a640 2353 case MSR_IA32_APICBASE:
609e36d3 2354 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2355 break;
0105d1a5 2356 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2357 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2358 break;
a3e06bbe 2359 case MSR_IA32_TSCDEADLINE:
609e36d3 2360 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2361 break;
ba904635 2362 case MSR_IA32_TSC_ADJUST:
609e36d3 2363 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2364 break;
15c4a640 2365 case MSR_IA32_MISC_ENABLE:
609e36d3 2366 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2367 break;
64d60670
PB		 2368 case MSR_IA32_SMBASE:
2369 if (!msr_info->host_initiated)
2370 return 1;
2371 msr_info->data = vcpu->arch.smbase;
15c4a640 2372 break;
847f0ad8
AG		 2373 case MSR_IA32_PERF_STATUS:
2374 /* TSC increment by tick */
609e36d3 2375 msr_info->data = 1000ULL;
847f0ad8 2376 /* CPU multiplier */
b0996ae4 2377 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2378 break;
15c4a640 2379 case MSR_EFER:
609e36d3 2380 msr_info->data = vcpu->arch.efer;
15c4a640 2381 break;
18068523 2382 case MSR_KVM_WALL_CLOCK:
11c6bffa 2383 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2384 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2385 break;
2386 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2387 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2388 msr_info->data = vcpu->arch.time;
18068523 2389 break;
344d9588 2390 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2391 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2392 break;
c9aaa895 2393 case MSR_KVM_STEAL_TIME:
609e36d3 2394 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2395 break;
1d92128f 2396 case MSR_KVM_PV_EOI_EN:
609e36d3 2397 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2398 break;
890ca9ae
HY		 2399 case MSR_IA32_P5_MC_ADDR:
2400 case MSR_IA32_P5_MC_TYPE:
2401 case MSR_IA32_MCG_CAP:
2402 case MSR_IA32_MCG_CTL:
2403 case MSR_IA32_MCG_STATUS:
81760dcc 2404 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2405 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2406 case MSR_K7_CLK_CTL:
2407 /*
2408 * Provide expected ramp-up count for K7. All other
2409 * are set to zero, indicating minimum divisors for
2410 * every field.
2411 *
2412 * This prevents guest kernels on AMD host with CPU
2413 * type 6, model 8 and higher from exploding due to
2414 * the rdmsr failing.
2415 */
609e36d3 2416 msr_info->data = 0x20000000;
84e0cefa 2417 break;
55cd8e5a 2418 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2419 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2420 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2421 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2422 return kvm_hv_get_msr_common(vcpu,
2423 msr_info->index, &msr_info->data);
55cd8e5a 2424 break;
91c9c3ed 2425 case MSR_IA32_BBL_CR_CTL3:
2426 /* This legacy MSR exists but isn't fully documented in current
2427 * silicon. It is however accessed by winxp in very narrow
2428 * scenarios where it sets bit #19, itself documented as
2429 * a "reserved" bit. Best effort attempt to source coherent
2430 * read data here should the balance of the register be
2431 * interpreted by the guest:
2432 *
2433 * L2 cache control register 3: 64GB range, 256KB size,
2434 * enabled, latency 0x1, configured
2435 */
609e36d3 2436 msr_info->data = 0xbe702111;
91c9c3ed 2437 break;
2b036c6b
BO		 2438 case MSR_AMD64_OSVW_ID_LENGTH:
2439 if (!guest_cpuid_has_osvw(vcpu))
2440 return 1;
609e36d3 2441 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2442 break;
2443 case MSR_AMD64_OSVW_STATUS:
2444 if (!guest_cpuid_has_osvw(vcpu))
2445 return 1;
609e36d3 2446 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2447 break;
15c4a640 2448 default:
c6702c9d 2449 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2450 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2451 if (!ignore_msrs) {
609e36d3 2452 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2453 return 1;
2454 } else {
609e36d3
PB		 2455 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2456 msr_info->data = 0;
ed85c068
AP		 2457 }
2458 break;
15c4a640 2459 }
15c4a640
CO		 2460 return 0;
2461}
2462EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2463
313a3dc7
CO		 2464/*
2465 * Read or write a bunch of msrs. All parameters are kernel addresses.
2466 *
2467 * @return number of msrs set successfully.
2468 */
2469static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2470 struct kvm_msr_entry *entries,
2471 int (*do_msr)(struct kvm_vcpu *vcpu,
2472 unsigned index, u64 *data))
2473{
f656ce01 2474 int i, idx;
313a3dc7 2475
f656ce01 2476 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2477 for (i = 0; i < msrs->nmsrs; ++i)
2478 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2479 break;
f656ce01 2480 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2481
313a3dc7
CO		 2482 return i;
2483}
2484
2485/*
2486 * Read or write a bunch of msrs. Parameters are user addresses.
2487 *
2488 * @return number of msrs set successfully.
2489 */
2490static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2491 int (*do_msr)(struct kvm_vcpu *vcpu,
2492 unsigned index, u64 *data),
2493 int writeback)
2494{
2495 struct kvm_msrs msrs;
2496 struct kvm_msr_entry *entries;
2497 int r, n;
2498 unsigned size;
2499
2500 r = -EFAULT;
2501 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2502 goto out;
2503
2504 r = -E2BIG;
2505 if (msrs.nmsrs >= MAX_IO_MSRS)
2506 goto out;
2507
313a3dc7 2508 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2509 entries = memdup_user(user_msrs->entries, size);
2510 if (IS_ERR(entries)) {
2511 r = PTR_ERR(entries);
313a3dc7 2512 goto out;
ff5c2c03 2513 }
313a3dc7
CO		 2514
2515 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2516 if (r < 0)
2517 goto out_free;
2518
2519 r = -EFAULT;
2520 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2521 goto out_free;
2522
2523 r = n;
2524
2525out_free:
7a73c028 2526 kfree(entries);
313a3dc7
CO		 2527out:
2528 return r;
2529}
2530
784aa3d7 2531int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2532{
2533 int r;
2534
2535 switch (ext) {
2536 case KVM_CAP_IRQCHIP:
2537 case KVM_CAP_HLT:
2538 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2539 case KVM_CAP_SET_TSS_ADDR:
07716717 2540 case KVM_CAP_EXT_CPUID:
9c15bb1d 2541 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2542 case KVM_CAP_CLOCKSOURCE:
7837699f 2543 case KVM_CAP_PIT:
a28e4f5a 2544 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2545 case KVM_CAP_MP_STATE:
ed848624 2546 case KVM_CAP_SYNC_MMU:
a355c85c 2547 case KVM_CAP_USER_NMI:
52d939a0 2548 case KVM_CAP_REINJECT_CONTROL:
4925663a 2549 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2550 case KVM_CAP_IOEVENTFD:
f848a5a8 2551 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2552 case KVM_CAP_PIT2:
e9f42757 2553 case KVM_CAP_PIT_STATE2:
b927a3ce 2554 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2555 case KVM_CAP_XEN_HVM:
afbcf7ab 2556 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2557 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2558 case KVM_CAP_HYPERV:
10388a07 2559 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2560 case KVM_CAP_HYPERV_SPIN:
5c919412 2561 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2562 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2563 case KVM_CAP_DEBUGREGS:
d2be1651 2564 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2565 case KVM_CAP_XSAVE:
344d9588 2566 case KVM_CAP_ASYNC_PF:
92a1f12d 2567 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2568 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2569 case KVM_CAP_READONLY_MEM:
5f66b620 2570 case KVM_CAP_HYPERV_TIME:
100943c5 2571 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2572 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2573 case KVM_CAP_ENABLE_CAP_VM:
2574 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2575 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2576 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2577#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2578 case KVM_CAP_ASSIGN_DEV_IRQ:
2579 case KVM_CAP_PCI_2_3:
2580#endif
018d00d2
ZX		 2581 r = 1;
2582 break;
6d396b55
PB		 2583 case KVM_CAP_X86_SMM:
2584 /* SMBASE is usually relocated above 1M on modern chipsets,
2585 * and SMM handlers might indeed rely on 4G segment limits,
2586 * so do not report SMM to be available if real mode is
2587 * emulated via vm86 mode. Still, do not go to great lengths
2588 * to avoid userspace's usage of the feature, because it is a
2589 * fringe case that is not enabled except via specific settings
2590 * of the module parameters.
2591 */
2592 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2593 break;
542472b5
LV		 2594 case KVM_CAP_COALESCED_MMIO:
2595 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2596 break;
774ead3a
AK		 2597 case KVM_CAP_VAPIC:
2598 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2599 break;
f725230a 2600 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2601 r = KVM_SOFT_MAX_VCPUS;
2602 break;
2603 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2604 r = KVM_MAX_VCPUS;
2605 break;
a988b910 2606 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2607 r = KVM_USER_MEM_SLOTS;
a988b910 2608 break;
a68a6a72
MT		 2609 case KVM_CAP_PV_MMU: /* obsolete */
2610 r = 0;
2f333bcb 2611 break;
4cee4b72 2612#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2613 case KVM_CAP_IOMMU:
a1b60c1c 2614 r = iommu_present(&pci_bus_type);
62c476c7 2615 break;
4cee4b72 2616#endif
890ca9ae
HY		 2617 case KVM_CAP_MCE:
2618 r = KVM_MAX_MCE_BANKS;
2619 break;
2d5b5a66 2620 case KVM_CAP_XCRS:
d366bf7e 2621 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2622 break;
92a1f12d
JR		 2623 case KVM_CAP_TSC_CONTROL:
2624 r = kvm_has_tsc_control;
2625 break;
37131313
RK		 2626 case KVM_CAP_X2APIC_API:
2627 r = KVM_X2APIC_API_VALID_FLAGS;
2628 break;
018d00d2
ZX		 2629 default:
2630 r = 0;
2631 break;
2632 }
2633 return r;
2634
2635}
2636
043405e1
CO		 2637long kvm_arch_dev_ioctl(struct file *filp,
2638 unsigned int ioctl, unsigned long arg)
2639{
2640 void __user *argp = (void __user *)arg;
2641 long r;
2642
2643 switch (ioctl) {
2644 case KVM_GET_MSR_INDEX_LIST: {
2645 struct kvm_msr_list __user *user_msr_list = argp;
2646 struct kvm_msr_list msr_list;
2647 unsigned n;
2648
2649 r = -EFAULT;
2650 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2651 goto out;
2652 n = msr_list.nmsrs;
62ef68bb 2653 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2654 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2655 goto out;
2656 r = -E2BIG;
e125e7b6 2657 if (n < msr_list.nmsrs)
043405e1
CO		 2658 goto out;
2659 r = -EFAULT;
2660 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2661 num_msrs_to_save * sizeof(u32)))
2662 goto out;
e125e7b6 2663 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2664 &emulated_msrs,
62ef68bb 2665 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2666 goto out;
2667 r = 0;
2668 break;
2669 }
9c15bb1d
BP		 2670 case KVM_GET_SUPPORTED_CPUID:
2671 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2672 struct kvm_cpuid2 __user *cpuid_arg = argp;
2673 struct kvm_cpuid2 cpuid;
2674
2675 r = -EFAULT;
2676 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2677 goto out;
9c15bb1d
BP		 2678
2679 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2680 ioctl);
674eea0f
AK		 2681 if (r)
2682 goto out;
2683
2684 r = -EFAULT;
2685 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2686 goto out;
2687 r = 0;
2688 break;
2689 }
890ca9ae 2690 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2691 r = -EFAULT;
c45dcc71
AR		 2692 if (copy_to_user(argp, &kvm_mce_cap_supported,
2693 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2694 goto out;
2695 r = 0;
2696 break;
2697 }
043405e1
CO		 2698 default:
2699 r = -EINVAL;
2700 }
2701out:
2702 return r;
2703}
2704
f5f48ee1
SY		 2705static void wbinvd_ipi(void *garbage)
2706{
2707 wbinvd();
2708}
2709
2710static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2711{
e0f0bbc5 2712 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2713}
2714
2860c4b1
PB		 2715static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2716{
2717 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2718}
2719
313a3dc7
CO		 2720void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2721{
f5f48ee1
SY		 2722 /* Address WBINVD may be executed by guest */
2723 if (need_emulate_wbinvd(vcpu)) {
2724 if (kvm_x86_ops->has_wbinvd_exit())
2725 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2726 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2727 smp_call_function_single(vcpu->cpu,
2728 wbinvd_ipi, NULL, 1);
2729 }
2730
313a3dc7 2731 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2732
0dd6a6ed
ZA		 2733 /* Apply any externally detected TSC adjustments (due to suspend) */
2734 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2735 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2736 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2737 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2738 }
8f6055cb 2739
48434c20 2740 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2741 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2742 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2743 if (tsc_delta < 0)
2744 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2745
c285545f 2746 if (check_tsc_unstable()) {
07c1419a 2747 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2748 vcpu->arch.last_guest_tsc);
2749 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2750 vcpu->arch.tsc_catchup = 1;
c285545f 2751 }
e12c8f36
WL		 2752 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2753 kvm_x86_ops->set_hv_timer(vcpu,
2754 kvm_get_lapic_tscdeadline_msr(vcpu)))
2755 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2756 /*
2757 * On a host with synchronized TSC, there is no need to update
2758 * kvmclock on vcpu->cpu migration
2759 */
2760 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2761 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2762 if (vcpu->cpu != cpu)
2763 kvm_migrate_timers(vcpu);
e48672fa 2764 vcpu->cpu = cpu;
6b7d7e76 2765 }
c9aaa895 2766
c9aaa895 2767 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2768}
2769
2770void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2771{
02daab21 2772 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2773 kvm_put_guest_fpu(vcpu);
4ea1636b 2774 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2775}
2776
313a3dc7
CO		 2777static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2778 struct kvm_lapic_state *s)
2779{
d62caabb
AS		 2780 if (vcpu->arch.apicv_active)
2781 kvm_x86_ops->sync_pir_to_irr(vcpu);
2782
a92e2543 2783 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2784}
2785
2786static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2787 struct kvm_lapic_state *s)
2788{
a92e2543
RK		 2789 int r;
2790
2791 r = kvm_apic_set_state(vcpu, s);
2792 if (r)
2793 return r;
cb142eb7 2794 update_cr8_intercept(vcpu);
313a3dc7
CO		 2795
2796 return 0;
2797}
2798
127a457a
MG		 2799static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2800{
2801 return (!lapic_in_kernel(vcpu) ||
2802 kvm_apic_accept_pic_intr(vcpu));
2803}
2804
782d422b
MG		 2805/*
2806 * if userspace requested an interrupt window, check that the
2807 * interrupt window is open.
2808 *
2809 * No need to exit to userspace if we already have an interrupt queued.
2810 */
2811static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2812{
2813 return kvm_arch_interrupt_allowed(vcpu) &&
2814 !kvm_cpu_has_interrupt(vcpu) &&
2815 !kvm_event_needs_reinjection(vcpu) &&
2816 kvm_cpu_accept_dm_intr(vcpu);
2817}
2818
f77bc6a4
ZX		 2819static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2820 struct kvm_interrupt *irq)
2821{
02cdb50f 2822 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2823 return -EINVAL;
1c1a9ce9
SR		 2824
2825 if (!irqchip_in_kernel(vcpu->kvm)) {
2826 kvm_queue_interrupt(vcpu, irq->irq, false);
2827 kvm_make_request(KVM_REQ_EVENT, vcpu);
2828 return 0;
2829 }
2830
2831 /*
2832 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2833 * fail for in-kernel 8259.
2834 */
2835 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2836 return -ENXIO;
f77bc6a4 2837
1c1a9ce9
SR		 2838 if (vcpu->arch.pending_external_vector != -1)
2839 return -EEXIST;
f77bc6a4 2840
1c1a9ce9 2841 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2842 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2843 return 0;
2844}
2845
c4abb7c9
JK		 2846static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2847{
c4abb7c9 2848 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2849
2850 return 0;
2851}
2852
f077825a
PB		 2853static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2854{
64d60670
PB		 2855 kvm_make_request(KVM_REQ_SMI, vcpu);
2856
f077825a
PB		 2857 return 0;
2858}
2859
b209749f
AK		 2860static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2861 struct kvm_tpr_access_ctl *tac)
2862{
2863 if (tac->flags)
2864 return -EINVAL;
2865 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2866 return 0;
2867}
2868
890ca9ae
HY		 2869static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2870 u64 mcg_cap)
2871{
2872 int r;
2873 unsigned bank_num = mcg_cap & 0xff, bank;
2874
2875 r = -EINVAL;
a9e38c3e 2876 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2877 goto out;
c45dcc71 2878 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 2879 goto out;
2880 r = 0;
2881 vcpu->arch.mcg_cap = mcg_cap;
2882 /* Init IA32_MCG_CTL to all 1s */
2883 if (mcg_cap & MCG_CTL_P)
2884 vcpu->arch.mcg_ctl = ~(u64)0;
2885 /* Init IA32_MCi_CTL to all 1s */
2886 for (bank = 0; bank < bank_num; bank++)
2887 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 2888
2889 if (kvm_x86_ops->setup_mce)
2890 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 2891out:
2892 return r;
2893}
2894
2895static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2896 struct kvm_x86_mce *mce)
2897{
2898 u64 mcg_cap = vcpu->arch.mcg_cap;
2899 unsigned bank_num = mcg_cap & 0xff;
2900 u64 *banks = vcpu->arch.mce_banks;
2901
2902 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2903 return -EINVAL;
2904 /*
2905 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2906 * reporting is disabled
2907 */
2908 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2909 vcpu->arch.mcg_ctl != ~(u64)0)
2910 return 0;
2911 banks += 4 * mce->bank;
2912 /*
2913 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2914 * reporting is disabled for the bank
2915 */
2916 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2917 return 0;
2918 if (mce->status & MCI_STATUS_UC) {
2919 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2920 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2921 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2922 return 0;
2923 }
2924 if (banks[1] & MCI_STATUS_VAL)
2925 mce->status |= MCI_STATUS_OVER;
2926 banks[2] = mce->addr;
2927 banks[3] = mce->misc;
2928 vcpu->arch.mcg_status = mce->mcg_status;
2929 banks[1] = mce->status;
2930 kvm_queue_exception(vcpu, MC_VECTOR);
2931 } else if (!(banks[1] & MCI_STATUS_VAL)
2932 || !(banks[1] & MCI_STATUS_UC)) {
2933 if (banks[1] & MCI_STATUS_VAL)
2934 mce->status |= MCI_STATUS_OVER;
2935 banks[2] = mce->addr;
2936 banks[3] = mce->misc;
2937 banks[1] = mce->status;
2938 } else
2939 banks[1] |= MCI_STATUS_OVER;
2940 return 0;
2941}
2942
3cfc3092
JK		 2943static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2944 struct kvm_vcpu_events *events)
2945{
7460fb4a 2946 process_nmi(vcpu);
03b82a30
JK		 2947 events->exception.injected =
2948 vcpu->arch.exception.pending &&
2949 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2950 events->exception.nr = vcpu->arch.exception.nr;
2951 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2952 events->exception.pad = 0;
3cfc3092
JK		 2953 events->exception.error_code = vcpu->arch.exception.error_code;
2954
03b82a30
JK		 2955 events->interrupt.injected =
2956 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2957 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2958 events->interrupt.soft = 0;
37ccdcbe 2959 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2960
2961 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2962 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2963 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2964 events->nmi.pad = 0;
3cfc3092 2965
66450a21 2966 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2967
f077825a
PB		 2968 events->smi.smm = is_smm(vcpu);
2969 events->smi.pending = vcpu->arch.smi_pending;
2970 events->smi.smm_inside_nmi =
2971 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2972 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2973
dab4b911 2974 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2975 | KVM_VCPUEVENT_VALID_SHADOW
2976 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2977 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2978}
2979
2980static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2981 struct kvm_vcpu_events *events)
2982{
dab4b911 2983 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2984 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2985 | KVM_VCPUEVENT_VALID_SHADOW
2986 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2987 return -EINVAL;
2988
78e546c8
PB		 2989 if (events->exception.injected &&
2990 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
2991 return -EINVAL;
2992
7460fb4a 2993 process_nmi(vcpu);
3cfc3092
JK		 2994 vcpu->arch.exception.pending = events->exception.injected;
2995 vcpu->arch.exception.nr = events->exception.nr;
2996 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2997 vcpu->arch.exception.error_code = events->exception.error_code;
2998
2999 vcpu->arch.interrupt.pending = events->interrupt.injected;
3000 vcpu->arch.interrupt.nr = events->interrupt.nr;
3001 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3002 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3003 kvm_x86_ops->set_interrupt_shadow(vcpu,
3004 events->interrupt.shadow);
3cfc3092
JK		 3005
3006 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3007 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3008 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3009 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3010
66450a21 3011 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3012 lapic_in_kernel(vcpu))
66450a21 3013 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3014
f077825a
PB		 3015 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3016 if (events->smi.smm)
3017 vcpu->arch.hflags |= HF_SMM_MASK;
3018 else
3019 vcpu->arch.hflags &= ~HF_SMM_MASK;
3020 vcpu->arch.smi_pending = events->smi.pending;
3021 if (events->smi.smm_inside_nmi)
3022 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3023 else
3024 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3025 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3026 if (events->smi.latched_init)
3027 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3028 else
3029 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3030 }
3031 }
3032
3842d135
AK		 3033 kvm_make_request(KVM_REQ_EVENT, vcpu);
3034
3cfc3092
JK		 3035 return 0;
3036}
3037
a1efbe77
JK		 3038static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3039 struct kvm_debugregs *dbgregs)
3040{
73aaf249
JK		 3041 unsigned long val;
3042
a1efbe77 3043 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3044 kvm_get_dr(vcpu, 6, &val);
73aaf249 3045 dbgregs->dr6 = val;
a1efbe77
JK		 3046 dbgregs->dr7 = vcpu->arch.dr7;
3047 dbgregs->flags = 0;
97e69aa6 3048 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3049}
3050
3051static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3052 struct kvm_debugregs *dbgregs)
3053{
3054 if (dbgregs->flags)
3055 return -EINVAL;
3056
d14bdb55
PB		 3057 if (dbgregs->dr6 & ~0xffffffffull)
3058 return -EINVAL;
3059 if (dbgregs->dr7 & ~0xffffffffull)
3060 return -EINVAL;
3061
a1efbe77 3062 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3063 kvm_update_dr0123(vcpu);
a1efbe77 3064 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3065 kvm_update_dr6(vcpu);
a1efbe77 3066 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3067 kvm_update_dr7(vcpu);
a1efbe77 3068
a1efbe77
JK		 3069 return 0;
3070}
3071
df1daba7
PB		 3072#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3073
3074static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3075{
c47ada30 3076 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3077 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3078 u64 valid;
3079
3080 /*
3081 * Copy legacy XSAVE area, to avoid complications with CPUID
3082 * leaves 0 and 1 in the loop below.
3083 */
3084 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3085
3086 /* Set XSTATE_BV */
3087 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3088
3089 /*
3090 * Copy each region from the possibly compacted offset to the
3091 * non-compacted offset.
3092 */
d91cab78 3093 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3094 while (valid) {
3095 u64 feature = valid & -valid;
3096 int index = fls64(feature) - 1;
3097 void *src = get_xsave_addr(xsave, feature);
3098
3099 if (src) {
3100 u32 size, offset, ecx, edx;
3101 cpuid_count(XSTATE_CPUID, index,
3102 &size, &offset, &ecx, &edx);
3103 memcpy(dest + offset, src, size);
3104 }
3105
3106 valid -= feature;
3107 }
3108}
3109
3110static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3111{
c47ada30 3112 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3113 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3114 u64 valid;
3115
3116 /*
3117 * Copy legacy XSAVE area, to avoid complications with CPUID
3118 * leaves 0 and 1 in the loop below.
3119 */
3120 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3121
3122 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3123 xsave->header.xfeatures = xstate_bv;
782511b0 3124 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3125 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3126
3127 /*
3128 * Copy each region from the non-compacted offset to the
3129 * possibly compacted offset.
3130 */
d91cab78 3131 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3132 while (valid) {
3133 u64 feature = valid & -valid;
3134 int index = fls64(feature) - 1;
3135 void *dest = get_xsave_addr(xsave, feature);
3136
3137 if (dest) {
3138 u32 size, offset, ecx, edx;
3139 cpuid_count(XSTATE_CPUID, index,
3140 &size, &offset, &ecx, &edx);
3141 memcpy(dest, src + offset, size);
ee4100da 3142 }
df1daba7
PB		 3143
3144 valid -= feature;
3145 }
3146}
3147
2d5b5a66
SY		 3148static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3149 struct kvm_xsave *guest_xsave)
3150{
d366bf7e 3151 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3152 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3153 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3154 } else {
2d5b5a66 3155 memcpy(guest_xsave->region,
7366ed77 3156 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3157 sizeof(struct fxregs_state));
2d5b5a66 3158 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3159 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3160 }
3161}
3162
3163static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3164 struct kvm_xsave *guest_xsave)
3165{
3166 u64 xstate_bv =
3167 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3168
d366bf7e 3169 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3170 /*
3171 * Here we allow setting states that are not present in
3172 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3173 * with old userspace.
3174 */
4ff41732 3175 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3176 return -EINVAL;
df1daba7 3177 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3178 } else {
d91cab78 3179 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3180 return -EINVAL;
7366ed77 3181 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3182 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3183 }
3184 return 0;
3185}
3186
3187static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3188 struct kvm_xcrs *guest_xcrs)
3189{
d366bf7e 3190 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3191 guest_xcrs->nr_xcrs = 0;
3192 return;
3193 }
3194
3195 guest_xcrs->nr_xcrs = 1;
3196 guest_xcrs->flags = 0;
3197 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3198 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3199}
3200
3201static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3202 struct kvm_xcrs *guest_xcrs)
3203{
3204 int i, r = 0;
3205
d366bf7e 3206 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3207 return -EINVAL;
3208
3209 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3210 return -EINVAL;
3211
3212 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3213 /* Only support XCR0 currently */
c67a04cb 3214 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3215 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3216 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3217 break;
3218 }
3219 if (r)
3220 r = -EINVAL;
3221 return r;
3222}
3223
1c0b28c2
EM		 3224/*
3225 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3226 * stopped by the hypervisor. This function will be called from the host only.
3227 * EINVAL is returned when the host attempts to set the flag for a guest that
3228 * does not support pv clocks.
3229 */
3230static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3231{
0b79459b 3232 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3233 return -EINVAL;
51d59c6b 3234 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3235 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3236 return 0;
3237}
3238
5c919412
AS		 3239static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3240 struct kvm_enable_cap *cap)
3241{
3242 if (cap->flags)
3243 return -EINVAL;
3244
3245 switch (cap->cap) {
3246 case KVM_CAP_HYPERV_SYNIC:
3247 return kvm_hv_activate_synic(vcpu);
3248 default:
3249 return -EINVAL;
3250 }
3251}
3252
313a3dc7
CO		 3253long kvm_arch_vcpu_ioctl(struct file *filp,
3254 unsigned int ioctl, unsigned long arg)
3255{
3256 struct kvm_vcpu *vcpu = filp->private_data;
3257 void __user *argp = (void __user *)arg;
3258 int r;
d1ac91d8
AK		 3259 union {
3260 struct kvm_lapic_state *lapic;
3261 struct kvm_xsave *xsave;
3262 struct kvm_xcrs *xcrs;
3263 void *buffer;
3264 } u;
3265
3266 u.buffer = NULL;
313a3dc7
CO		 3267 switch (ioctl) {
3268 case KVM_GET_LAPIC: {
2204ae3c 3269 r = -EINVAL;
bce87cce 3270 if (!lapic_in_kernel(vcpu))
2204ae3c 3271 goto out;
d1ac91d8 3272 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3273
b772ff36 3274 r = -ENOMEM;
d1ac91d8 3275 if (!u.lapic)
b772ff36 3276 goto out;
d1ac91d8 3277 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3278 if (r)
3279 goto out;
3280 r = -EFAULT;
d1ac91d8 3281 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3282 goto out;
3283 r = 0;
3284 break;
3285 }
3286 case KVM_SET_LAPIC: {
2204ae3c 3287 r = -EINVAL;
bce87cce 3288 if (!lapic_in_kernel(vcpu))
2204ae3c 3289 goto out;
ff5c2c03 3290 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3291 if (IS_ERR(u.lapic))
3292 return PTR_ERR(u.lapic);
ff5c2c03 3293
d1ac91d8 3294 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3295 break;
3296 }
f77bc6a4
ZX		 3297 case KVM_INTERRUPT: {
3298 struct kvm_interrupt irq;
3299
3300 r = -EFAULT;
3301 if (copy_from_user(&irq, argp, sizeof irq))
3302 goto out;
3303 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3304 break;
3305 }
c4abb7c9
JK		 3306 case KVM_NMI: {
3307 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3308 break;
3309 }
f077825a
PB		 3310 case KVM_SMI: {
3311 r = kvm_vcpu_ioctl_smi(vcpu);
3312 break;
3313 }
313a3dc7
CO		 3314 case KVM_SET_CPUID: {
3315 struct kvm_cpuid __user *cpuid_arg = argp;
3316 struct kvm_cpuid cpuid;
3317
3318 r = -EFAULT;
3319 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3320 goto out;
3321 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3322 break;
3323 }
07716717
DK		 3324 case KVM_SET_CPUID2: {
3325 struct kvm_cpuid2 __user *cpuid_arg = argp;
3326 struct kvm_cpuid2 cpuid;
3327
3328 r = -EFAULT;
3329 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3330 goto out;
3331 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3332 cpuid_arg->entries);
07716717
DK		 3333 break;
3334 }
3335 case KVM_GET_CPUID2: {
3336 struct kvm_cpuid2 __user *cpuid_arg = argp;
3337 struct kvm_cpuid2 cpuid;
3338
3339 r = -EFAULT;
3340 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3341 goto out;
3342 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3343 cpuid_arg->entries);
07716717
DK		 3344 if (r)
3345 goto out;
3346 r = -EFAULT;
3347 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3348 goto out;
3349 r = 0;
3350 break;
3351 }
313a3dc7 3352 case KVM_GET_MSRS:
609e36d3 3353 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3354 break;
3355 case KVM_SET_MSRS:
3356 r = msr_io(vcpu, argp, do_set_msr, 0);
3357 break;
b209749f
AK		 3358 case KVM_TPR_ACCESS_REPORTING: {
3359 struct kvm_tpr_access_ctl tac;
3360
3361 r = -EFAULT;
3362 if (copy_from_user(&tac, argp, sizeof tac))
3363 goto out;
3364 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3365 if (r)
3366 goto out;
3367 r = -EFAULT;
3368 if (copy_to_user(argp, &tac, sizeof tac))
3369 goto out;
3370 r = 0;
3371 break;
3372 };
b93463aa
AK		 3373 case KVM_SET_VAPIC_ADDR: {
3374 struct kvm_vapic_addr va;
3375
3376 r = -EINVAL;
35754c98 3377 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3378 goto out;
3379 r = -EFAULT;
3380 if (copy_from_user(&va, argp, sizeof va))
3381 goto out;
fda4e2e8 3382 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3383 break;
3384 }
890ca9ae
HY		 3385 case KVM_X86_SETUP_MCE: {
3386 u64 mcg_cap;
3387
3388 r = -EFAULT;
3389 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3390 goto out;
3391 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3392 break;
3393 }
3394 case KVM_X86_SET_MCE: {
3395 struct kvm_x86_mce mce;
3396
3397 r = -EFAULT;
3398 if (copy_from_user(&mce, argp, sizeof mce))
3399 goto out;
3400 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3401 break;
3402 }
3cfc3092
JK		 3403 case KVM_GET_VCPU_EVENTS: {
3404 struct kvm_vcpu_events events;
3405
3406 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3407
3408 r = -EFAULT;
3409 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3410 break;
3411 r = 0;
3412 break;
3413 }
3414 case KVM_SET_VCPU_EVENTS: {
3415 struct kvm_vcpu_events events;
3416
3417 r = -EFAULT;
3418 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3419 break;
3420
3421 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3422 break;
3423 }
a1efbe77
JK		 3424 case KVM_GET_DEBUGREGS: {
3425 struct kvm_debugregs dbgregs;
3426
3427 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3428
3429 r = -EFAULT;
3430 if (copy_to_user(argp, &dbgregs,
3431 sizeof(struct kvm_debugregs)))
3432 break;
3433 r = 0;
3434 break;
3435 }
3436 case KVM_SET_DEBUGREGS: {
3437 struct kvm_debugregs dbgregs;
3438
3439 r = -EFAULT;
3440 if (copy_from_user(&dbgregs, argp,
3441 sizeof(struct kvm_debugregs)))
3442 break;
3443
3444 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3445 break;
3446 }
2d5b5a66 3447 case KVM_GET_XSAVE: {
d1ac91d8 3448 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3449 r = -ENOMEM;
d1ac91d8 3450 if (!u.xsave)
2d5b5a66
SY		 3451 break;
3452
d1ac91d8 3453 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3454
3455 r = -EFAULT;
d1ac91d8 3456 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3457 break;
3458 r = 0;
3459 break;
3460 }
3461 case KVM_SET_XSAVE: {
ff5c2c03 3462 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3463 if (IS_ERR(u.xsave))
3464 return PTR_ERR(u.xsave);
2d5b5a66 3465
d1ac91d8 3466 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3467 break;
3468 }
3469 case KVM_GET_XCRS: {
d1ac91d8 3470 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3471 r = -ENOMEM;
d1ac91d8 3472 if (!u.xcrs)
2d5b5a66
SY		 3473 break;
3474
d1ac91d8 3475 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3476
3477 r = -EFAULT;
d1ac91d8 3478 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3479 sizeof(struct kvm_xcrs)))
3480 break;
3481 r = 0;
3482 break;
3483 }
3484 case KVM_SET_XCRS: {
ff5c2c03 3485 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3486 if (IS_ERR(u.xcrs))
3487 return PTR_ERR(u.xcrs);
2d5b5a66 3488
d1ac91d8 3489 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3490 break;
3491 }
92a1f12d
JR		 3492 case KVM_SET_TSC_KHZ: {
3493 u32 user_tsc_khz;
3494
3495 r = -EINVAL;
92a1f12d
JR		 3496 user_tsc_khz = (u32)arg;
3497
3498 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3499 goto out;
3500
cc578287
ZA		 3501 if (user_tsc_khz == 0)
3502 user_tsc_khz = tsc_khz;
3503
381d585c
HZ		 3504 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3505 r = 0;
92a1f12d 3506
92a1f12d
JR		 3507 goto out;
3508 }
3509 case KVM_GET_TSC_KHZ: {
cc578287 3510 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3511 goto out;
3512 }
1c0b28c2
EM		 3513 case KVM_KVMCLOCK_CTRL: {
3514 r = kvm_set_guest_paused(vcpu);
3515 goto out;
3516 }
5c919412
AS		 3517 case KVM_ENABLE_CAP: {
3518 struct kvm_enable_cap cap;
3519
3520 r = -EFAULT;
3521 if (copy_from_user(&cap, argp, sizeof(cap)))
3522 goto out;
3523 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3524 break;
3525 }
313a3dc7
CO		 3526 default:
3527 r = -EINVAL;
3528 }
3529out:
d1ac91d8 3530 kfree(u.buffer);
313a3dc7
CO		 3531 return r;
3532}
3533
5b1c1493
CO		 3534int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3535{
3536 return VM_FAULT_SIGBUS;
3537}
3538
1fe779f8
CO		 3539static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3540{
3541 int ret;
3542
3543 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3544 return -EINVAL;
1fe779f8
CO		 3545 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3546 return ret;
3547}
3548
b927a3ce
SY		 3549static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3550 u64 ident_addr)
3551{
3552 kvm->arch.ept_identity_map_addr = ident_addr;
3553 return 0;
3554}
3555
1fe779f8
CO		 3556static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3557 u32 kvm_nr_mmu_pages)
3558{
3559 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3560 return -EINVAL;
3561
79fac95e 3562 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3563
3564 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3565 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3566
79fac95e 3567 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3568 return 0;
3569}
3570
3571static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3572{
39de71ec 3573 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3574}
3575
1fe779f8
CO		 3576static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3577{
3578 int r;
3579
3580 r = 0;
3581 switch (chip->chip_id) {
3582 case KVM_IRQCHIP_PIC_MASTER:
3583 memcpy(&chip->chip.pic,
3584 &pic_irqchip(kvm)->pics[0],
3585 sizeof(struct kvm_pic_state));
3586 break;
3587 case KVM_IRQCHIP_PIC_SLAVE:
3588 memcpy(&chip->chip.pic,
3589 &pic_irqchip(kvm)->pics[1],
3590 sizeof(struct kvm_pic_state));
3591 break;
3592 case KVM_IRQCHIP_IOAPIC:
eba0226b 3593 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3594 break;
3595 default:
3596 r = -EINVAL;
3597 break;
3598 }
3599 return r;
3600}
3601
3602static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3603{
3604 int r;
3605
3606 r = 0;
3607 switch (chip->chip_id) {
3608 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3609 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3610 memcpy(&pic_irqchip(kvm)->pics[0],
3611 &chip->chip.pic,
3612 sizeof(struct kvm_pic_state));
f4f51050 3613 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3614 break;
3615 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3616 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3617 memcpy(&pic_irqchip(kvm)->pics[1],
3618 &chip->chip.pic,
3619 sizeof(struct kvm_pic_state));
f4f51050 3620 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3621 break;
3622 case KVM_IRQCHIP_IOAPIC:
eba0226b 3623 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3624 break;
3625 default:
3626 r = -EINVAL;
3627 break;
3628 }
3629 kvm_pic_update_irq(pic_irqchip(kvm));
3630 return r;
3631}
3632
e0f63cb9
SY		 3633static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3634{
34f3941c
RK		 3635 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3636
3637 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3638
3639 mutex_lock(&kps->lock);
3640 memcpy(ps, &kps->channels, sizeof(*ps));
3641 mutex_unlock(&kps->lock);
2da29bcc 3642 return 0;
e0f63cb9
SY		 3643}
3644
3645static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3646{
0185604c 3647 int i;
09edea72
RK		 3648 struct kvm_pit *pit = kvm->arch.vpit;
3649
3650 mutex_lock(&pit->pit_state.lock);
34f3941c 3651 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3652 for (i = 0; i < 3; i++)
09edea72
RK		 3653 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3654 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3655 return 0;
e9f42757
BK		 3656}
3657
3658static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3659{
e9f42757
BK		 3660 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3661 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3662 sizeof(ps->channels));
3663 ps->flags = kvm->arch.vpit->pit_state.flags;
3664 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3665 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3666 return 0;
e9f42757
BK		 3667}
3668
3669static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3670{
2da29bcc 3671 int start = 0;
0185604c 3672 int i;
e9f42757 3673 u32 prev_legacy, cur_legacy;
09edea72
RK		 3674 struct kvm_pit *pit = kvm->arch.vpit;
3675
3676 mutex_lock(&pit->pit_state.lock);
3677 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3678 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3679 if (!prev_legacy && cur_legacy)
3680 start = 1;
09edea72
RK		 3681 memcpy(&pit->pit_state.channels, &ps->channels,
3682 sizeof(pit->pit_state.channels));
3683 pit->pit_state.flags = ps->flags;
0185604c 3684 for (i = 0; i < 3; i++)
09edea72 3685 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3686 start && i == 0);
09edea72 3687 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3688 return 0;
e0f63cb9
SY		 3689}
3690
52d939a0
MT		 3691static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3692 struct kvm_reinject_control *control)
3693{
71474e2f
RK		 3694 struct kvm_pit *pit = kvm->arch.vpit;
3695
3696 if (!pit)
52d939a0 3697 return -ENXIO;
b39c90b6 3698
71474e2f
RK		 3699 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3700 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3701 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3702 */
3703 mutex_lock(&pit->pit_state.lock);
3704 kvm_pit_set_reinject(pit, control->pit_reinject);
3705 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3706
52d939a0
MT		 3707 return 0;
3708}
3709
95d4c16c 3710/**
60c34612
TY		 3711 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3712 * @kvm: kvm instance
3713 * @log: slot id and address to which we copy the log
95d4c16c 3714 *
e108ff2f
PB		 3715 * Steps 1-4 below provide general overview of dirty page logging. See
3716 * kvm_get_dirty_log_protect() function description for additional details.
3717 *
3718 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3719 * always flush the TLB (step 4) even if previous step failed and the dirty
3720 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3721 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3722 * writes will be marked dirty for next log read.
95d4c16c 3723 *
60c34612
TY		 3724 * 1. Take a snapshot of the bit and clear it if needed.
3725 * 2. Write protect the corresponding page.
e108ff2f
PB		 3726 * 3. Copy the snapshot to the userspace.
3727 * 4. Flush TLB's if needed.
5bb064dc 3728 */
60c34612 3729int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3730{
60c34612 3731 bool is_dirty = false;
e108ff2f 3732 int r;
5bb064dc 3733
79fac95e 3734 mutex_lock(&kvm->slots_lock);
5bb064dc 3735
88178fd4
KH		 3736 /*
3737 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3738 */
3739 if (kvm_x86_ops->flush_log_dirty)
3740 kvm_x86_ops->flush_log_dirty(kvm);
3741
e108ff2f 3742 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3743
3744 /*
3745 * All the TLBs can be flushed out of mmu lock, see the comments in
3746 * kvm_mmu_slot_remove_write_access().
3747 */
e108ff2f 3748 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3749 if (is_dirty)
3750 kvm_flush_remote_tlbs(kvm);
3751
79fac95e 3752 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3753 return r;
3754}
3755
aa2fbe6d
YZ		 3756int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3757 bool line_status)
23d43cf9
CD		 3758{
3759 if (!irqchip_in_kernel(kvm))
3760 return -ENXIO;
3761
3762 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3763 irq_event->irq, irq_event->level,
3764 line_status);
23d43cf9
CD		 3765 return 0;
3766}
3767
90de4a18
NA		 3768static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3769 struct kvm_enable_cap *cap)
3770{
3771 int r;
3772
3773 if (cap->flags)
3774 return -EINVAL;
3775
3776 switch (cap->cap) {
3777 case KVM_CAP_DISABLE_QUIRKS:
3778 kvm->arch.disabled_quirks = cap->args[0];
3779 r = 0;
3780 break;
49df6397
SR		 3781 case KVM_CAP_SPLIT_IRQCHIP: {
3782 mutex_lock(&kvm->lock);
b053b2ae
SR		 3783 r = -EINVAL;
3784 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3785 goto split_irqchip_unlock;
49df6397
SR		 3786 r = -EEXIST;
3787 if (irqchip_in_kernel(kvm))
3788 goto split_irqchip_unlock;
557abc40 3789 if (kvm->created_vcpus)
49df6397
SR		 3790 goto split_irqchip_unlock;
3791 r = kvm_setup_empty_irq_routing(kvm);
3792 if (r)
3793 goto split_irqchip_unlock;
3794 /* Pairs with irqchip_in_kernel. */
3795 smp_wmb();
3796 kvm->arch.irqchip_split = true;
b053b2ae 3797 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3798 r = 0;
3799split_irqchip_unlock:
3800 mutex_unlock(&kvm->lock);
3801 break;
3802 }
37131313
RK		 3803 case KVM_CAP_X2APIC_API:
3804 r = -EINVAL;
3805 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3806 break;
3807
3808 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3809 kvm->arch.x2apic_format = true;
c519265f
RK		 3810 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3811 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3812
3813 r = 0;
3814 break;
90de4a18
NA		 3815 default:
3816 r = -EINVAL;
3817 break;
3818 }
3819 return r;
3820}
3821
1fe779f8
CO		 3822long kvm_arch_vm_ioctl(struct file *filp,
3823 unsigned int ioctl, unsigned long arg)
3824{
3825 struct kvm *kvm = filp->private_data;
3826 void __user *argp = (void __user *)arg;
367e1319 3827 int r = -ENOTTY;
f0d66275
DH		 3828 /*
3829 * This union makes it completely explicit to gcc-3.x
3830 * that these two variables' stack usage should be
3831 * combined, not added together.
3832 */
3833 union {
3834 struct kvm_pit_state ps;
e9f42757 3835 struct kvm_pit_state2 ps2;
c5ff41ce 3836 struct kvm_pit_config pit_config;
f0d66275 3837 } u;
1fe779f8
CO		 3838
3839 switch (ioctl) {
3840 case KVM_SET_TSS_ADDR:
3841 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3842 break;
b927a3ce
SY		 3843 case KVM_SET_IDENTITY_MAP_ADDR: {
3844 u64 ident_addr;
3845
3846 r = -EFAULT;
3847 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3848 goto out;
3849 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3850 break;
3851 }
1fe779f8
CO		 3852 case KVM_SET_NR_MMU_PAGES:
3853 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3854 break;
3855 case KVM_GET_NR_MMU_PAGES:
3856 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3857 break;
3ddea128
MT		 3858 case KVM_CREATE_IRQCHIP: {
3859 struct kvm_pic *vpic;
3860
3861 mutex_lock(&kvm->lock);
3862 r = -EEXIST;
3863 if (kvm->arch.vpic)
3864 goto create_irqchip_unlock;
3e515705 3865 r = -EINVAL;
557abc40 3866 if (kvm->created_vcpus)
3e515705 3867 goto create_irqchip_unlock;
1fe779f8 3868 r = -ENOMEM;
3ddea128
MT		 3869 vpic = kvm_create_pic(kvm);
3870 if (vpic) {
1fe779f8
CO		 3871 r = kvm_ioapic_init(kvm);
3872 if (r) {
175504cd 3873 mutex_lock(&kvm->slots_lock);
71ba994c 3874 kvm_destroy_pic(vpic);
175504cd 3875 mutex_unlock(&kvm->slots_lock);
3ddea128 3876 goto create_irqchip_unlock;
1fe779f8
CO		 3877 }
3878 } else
3ddea128 3879 goto create_irqchip_unlock;
399ec807
AK		 3880 r = kvm_setup_default_irq_routing(kvm);
3881 if (r) {
175504cd 3882 mutex_lock(&kvm->slots_lock);
3ddea128 3883 mutex_lock(&kvm->irq_lock);
72bb2fcd 3884 kvm_ioapic_destroy(kvm);
71ba994c 3885 kvm_destroy_pic(vpic);
3ddea128 3886 mutex_unlock(&kvm->irq_lock);
175504cd 3887 mutex_unlock(&kvm->slots_lock);
71ba994c 3888 goto create_irqchip_unlock;
399ec807 3889 }
71ba994c
PB		 3890 /* Write kvm->irq_routing before kvm->arch.vpic. */
3891 smp_wmb();
3892 kvm->arch.vpic = vpic;
3ddea128
MT		 3893 create_irqchip_unlock:
3894 mutex_unlock(&kvm->lock);
1fe779f8 3895 break;
3ddea128 3896 }
7837699f 3897 case KVM_CREATE_PIT:
c5ff41ce
JK		 3898 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3899 goto create_pit;
3900 case KVM_CREATE_PIT2:
3901 r = -EFAULT;
3902 if (copy_from_user(&u.pit_config, argp,
3903 sizeof(struct kvm_pit_config)))
3904 goto out;
3905 create_pit:
250715a6 3906 mutex_lock(&kvm->lock);
269e05e4
AK		 3907 r = -EEXIST;
3908 if (kvm->arch.vpit)
3909 goto create_pit_unlock;
7837699f 3910 r = -ENOMEM;
c5ff41ce 3911 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3912 if (kvm->arch.vpit)
3913 r = 0;
269e05e4 3914 create_pit_unlock:
250715a6 3915 mutex_unlock(&kvm->lock);
7837699f 3916 break;
1fe779f8
CO		 3917 case KVM_GET_IRQCHIP: {
3918 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3919 struct kvm_irqchip *chip;
1fe779f8 3920
ff5c2c03
SL		 3921 chip = memdup_user(argp, sizeof(*chip));
3922 if (IS_ERR(chip)) {
3923 r = PTR_ERR(chip);
1fe779f8 3924 goto out;
ff5c2c03
SL		 3925 }
3926
1fe779f8 3927 r = -ENXIO;
49df6397 3928 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3929 goto get_irqchip_out;
3930 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3931 if (r)
f0d66275 3932 goto get_irqchip_out;
1fe779f8 3933 r = -EFAULT;
f0d66275
DH		 3934 if (copy_to_user(argp, chip, sizeof *chip))
3935 goto get_irqchip_out;
1fe779f8 3936 r = 0;
f0d66275
DH		 3937 get_irqchip_out:
3938 kfree(chip);
1fe779f8
CO		 3939 break;
3940 }
3941 case KVM_SET_IRQCHIP: {
3942 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3943 struct kvm_irqchip *chip;
1fe779f8 3944
ff5c2c03
SL		 3945 chip = memdup_user(argp, sizeof(*chip));
3946 if (IS_ERR(chip)) {
3947 r = PTR_ERR(chip);
1fe779f8 3948 goto out;
ff5c2c03
SL		 3949 }
3950
1fe779f8 3951 r = -ENXIO;
49df6397 3952 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3953 goto set_irqchip_out;
3954 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3955 if (r)
f0d66275 3956 goto set_irqchip_out;
1fe779f8 3957 r = 0;
f0d66275
DH		 3958 set_irqchip_out:
3959 kfree(chip);
1fe779f8
CO		 3960 break;
3961 }
e0f63cb9 3962 case KVM_GET_PIT: {
e0f63cb9 3963 r = -EFAULT;
f0d66275 3964 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3965 goto out;
3966 r = -ENXIO;
3967 if (!kvm->arch.vpit)
3968 goto out;
f0d66275 3969 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3970 if (r)
3971 goto out;
3972 r = -EFAULT;
f0d66275 3973 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3974 goto out;
3975 r = 0;
3976 break;
3977 }
3978 case KVM_SET_PIT: {
e0f63cb9 3979 r = -EFAULT;
f0d66275 3980 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3981 goto out;
3982 r = -ENXIO;
3983 if (!kvm->arch.vpit)
3984 goto out;
f0d66275 3985 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3986 break;
3987 }
e9f42757
BK		 3988 case KVM_GET_PIT2: {
3989 r = -ENXIO;
3990 if (!kvm->arch.vpit)
3991 goto out;
3992 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3993 if (r)
3994 goto out;
3995 r = -EFAULT;
3996 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3997 goto out;
3998 r = 0;
3999 break;
4000 }
4001 case KVM_SET_PIT2: {
4002 r = -EFAULT;
4003 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4004 goto out;
4005 r = -ENXIO;
4006 if (!kvm->arch.vpit)
4007 goto out;
4008 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4009 break;
4010 }
52d939a0
MT		 4011 case KVM_REINJECT_CONTROL: {
4012 struct kvm_reinject_control control;
4013 r = -EFAULT;
4014 if (copy_from_user(&control, argp, sizeof(control)))
4015 goto out;
4016 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4017 break;
4018 }
d71ba788
PB		 4019 case KVM_SET_BOOT_CPU_ID:
4020 r = 0;
4021 mutex_lock(&kvm->lock);
557abc40 4022 if (kvm->created_vcpus)
d71ba788
PB		 4023 r = -EBUSY;
4024 else
4025 kvm->arch.bsp_vcpu_id = arg;
4026 mutex_unlock(&kvm->lock);
4027 break;
ffde22ac
ES		 4028 case KVM_XEN_HVM_CONFIG: {
4029 r = -EFAULT;
4030 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4031 sizeof(struct kvm_xen_hvm_config)))
4032 goto out;
4033 r = -EINVAL;
4034 if (kvm->arch.xen_hvm_config.flags)
4035 goto out;
4036 r = 0;
4037 break;
4038 }
afbcf7ab 4039 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4040 struct kvm_clock_data user_ns;
4041 u64 now_ns;
4042 s64 delta;
4043
4044 r = -EFAULT;
4045 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4046 goto out;
4047
4048 r = -EINVAL;
4049 if (user_ns.flags)
4050 goto out;
4051
4052 r = 0;
395c6b0a 4053 local_irq_disable();
759379dd 4054 now_ns = get_kernel_ns();
afbcf7ab 4055 delta = user_ns.clock - now_ns;
395c6b0a 4056 local_irq_enable();
afbcf7ab 4057 kvm->arch.kvmclock_offset = delta;
2e762ff7 4058 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4059 break;
4060 }
4061 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4062 struct kvm_clock_data user_ns;
4063 u64 now_ns;
4064
395c6b0a 4065 local_irq_disable();
759379dd 4066 now_ns = get_kernel_ns();
afbcf7ab 4067 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4068 local_irq_enable();
afbcf7ab 4069 user_ns.flags = 0;
97e69aa6 4070 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4071
4072 r = -EFAULT;
4073 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4074 goto out;
4075 r = 0;
4076 break;
4077 }
90de4a18
NA		 4078 case KVM_ENABLE_CAP: {
4079 struct kvm_enable_cap cap;
afbcf7ab 4080
90de4a18
NA		 4081 r = -EFAULT;
4082 if (copy_from_user(&cap, argp, sizeof(cap)))
4083 goto out;
4084 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4085 break;
4086 }
1fe779f8 4087 default:
c274e03a 4088 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4089 }
4090out:
4091 return r;
4092}
4093
a16b043c 4094static void kvm_init_msr_list(void)
043405e1
CO		 4095{
4096 u32 dummy[2];
4097 unsigned i, j;
4098
62ef68bb 4099 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4100 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4101 continue;
93c4adc7
PB		 4102
4103 /*
4104 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4105 * to the guests in some cases.
93c4adc7
PB		 4106 */
4107 switch (msrs_to_save[i]) {
4108 case MSR_IA32_BNDCFGS:
4109 if (!kvm_x86_ops->mpx_supported())
4110 continue;
4111 break;
9dbe6cf9
PB		 4112 case MSR_TSC_AUX:
4113 if (!kvm_x86_ops->rdtscp_supported())
4114 continue;
4115 break;
93c4adc7
PB		 4116 default:
4117 break;
4118 }
4119
043405e1
CO		 4120 if (j < i)
4121 msrs_to_save[j] = msrs_to_save[i];
4122 j++;
4123 }
4124 num_msrs_to_save = j;
62ef68bb
PB		 4125
4126 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4127 switch (emulated_msrs[i]) {
6d396b55
PB		 4128 case MSR_IA32_SMBASE:
4129 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4130 continue;
4131 break;
62ef68bb
PB		 4132 default:
4133 break;
4134 }
4135
4136 if (j < i)
4137 emulated_msrs[j] = emulated_msrs[i];
4138 j++;
4139 }
4140 num_emulated_msrs = j;
043405e1
CO		 4141}
4142
bda9020e
MT		 4143static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4144 const void *v)
bbd9b64e 4145{
70252a10
AK		 4146 int handled = 0;
4147 int n;
4148
4149 do {
4150 n = min(len, 8);
bce87cce 4151 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4152 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4153 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4154 break;
4155 handled += n;
4156 addr += n;
4157 len -= n;
4158 v += n;
4159 } while (len);
bbd9b64e 4160
70252a10 4161 return handled;
bbd9b64e
CO		 4162}
4163
bda9020e 4164static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4165{
70252a10
AK		 4166 int handled = 0;
4167 int n;
4168
4169 do {
4170 n = min(len, 8);
bce87cce 4171 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4172 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4173 addr, n, v))
4174 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4175 break;
4176 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4177 handled += n;
4178 addr += n;
4179 len -= n;
4180 v += n;
4181 } while (len);
bbd9b64e 4182
70252a10 4183 return handled;
bbd9b64e
CO		 4184}
4185
2dafc6c2
GN		 4186static void kvm_set_segment(struct kvm_vcpu *vcpu,
4187 struct kvm_segment *var, int seg)
4188{
4189 kvm_x86_ops->set_segment(vcpu, var, seg);
4190}
4191
4192void kvm_get_segment(struct kvm_vcpu *vcpu,
4193 struct kvm_segment *var, int seg)
4194{
4195 kvm_x86_ops->get_segment(vcpu, var, seg);
4196}
4197
54987b7a
PB		 4198gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4199 struct x86_exception *exception)
02f59dc9
JR		 4200{
4201 gpa_t t_gpa;
02f59dc9
JR		 4202
4203 BUG_ON(!mmu_is_nested(vcpu));
4204
4205 /* NPT walks are always user-walks */
4206 access |= PFERR_USER_MASK;
54987b7a 4207 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4208
4209 return t_gpa;
4210}
4211
ab9ae313
AK		 4212gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4213 struct x86_exception *exception)
1871c602
GN		 4214{
4215 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4216 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4217}
4218
ab9ae313
AK		 4219 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4220 struct x86_exception *exception)
1871c602
GN		 4221{
4222 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4223 access |= PFERR_FETCH_MASK;
ab9ae313 4224 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4225}
4226
ab9ae313
AK		 4227gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4228 struct x86_exception *exception)
1871c602
GN		 4229{
4230 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4231 access |= PFERR_WRITE_MASK;
ab9ae313 4232 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4233}
4234
4235/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4236gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4237 struct x86_exception *exception)
1871c602 4238{
ab9ae313 4239 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4240}
4241
4242static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4243 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4244 struct x86_exception *exception)
bbd9b64e
CO		 4245{
4246 void *data = val;
10589a46 4247 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4248
4249 while (bytes) {
14dfe855 4250 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4251 exception);
bbd9b64e 4252 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4253 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4254 int ret;
4255
bcc55cba 4256 if (gpa == UNMAPPED_GVA)
ab9ae313 4257 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4258 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4259 offset, toread);
10589a46 4260 if (ret < 0) {
c3cd7ffa 4261 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4262 goto out;
4263 }
bbd9b64e 4264
77c2002e
IE		 4265 bytes -= toread;
4266 data += toread;
4267 addr += toread;
bbd9b64e 4268 }
10589a46 4269out:
10589a46 4270 return r;
bbd9b64e 4271}
77c2002e 4272
1871c602 4273/* used for instruction fetching */
0f65dd70
AK		 4274static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4275 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4276 struct x86_exception *exception)
1871c602 4277{
0f65dd70 4278 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4279 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4280 unsigned offset;
4281 int ret;
0f65dd70 4282
44583cba
PB		 4283 /* Inline kvm_read_guest_virt_helper for speed. */
4284 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4285 exception);
4286 if (unlikely(gpa == UNMAPPED_GVA))
4287 return X86EMUL_PROPAGATE_FAULT;
4288
4289 offset = addr & (PAGE_SIZE-1);
4290 if (WARN_ON(offset + bytes > PAGE_SIZE))
4291 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4292 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4293 offset, bytes);
44583cba
PB		 4294 if (unlikely(ret < 0))
4295 return X86EMUL_IO_NEEDED;
4296
4297 return X86EMUL_CONTINUE;
1871c602
GN		 4298}
4299
064aea77 4300int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4301 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4302 struct x86_exception *exception)
1871c602 4303{
0f65dd70 4304 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4305 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4306
1871c602 4307 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4308 exception);
1871c602 4309}
064aea77 4310EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4311
0f65dd70
AK		 4312static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4313 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4314 struct x86_exception *exception)
1871c602 4315{
0f65dd70 4316 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4317 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4318}
4319
7a036a6f
RK		 4320static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4321 unsigned long addr, void *val, unsigned int bytes)
4322{
4323 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4324 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4325
4326 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4327}
4328
6a4d7550 4329int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4330 gva_t addr, void *val,
2dafc6c2 4331 unsigned int bytes,
bcc55cba 4332 struct x86_exception *exception)
77c2002e 4333{
0f65dd70 4334 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4335 void *data = val;
4336 int r = X86EMUL_CONTINUE;
4337
4338 while (bytes) {
14dfe855
JR		 4339 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4340 PFERR_WRITE_MASK,
ab9ae313 4341 exception);
77c2002e
IE		 4342 unsigned offset = addr & (PAGE_SIZE-1);
4343 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4344 int ret;
4345
bcc55cba 4346 if (gpa == UNMAPPED_GVA)
ab9ae313 4347 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4348 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4349 if (ret < 0) {
c3cd7ffa 4350 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4351 goto out;
4352 }
4353
4354 bytes -= towrite;
4355 data += towrite;
4356 addr += towrite;
4357 }
4358out:
4359 return r;
4360}
6a4d7550 4361EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4362
af7cc7d1
XG		 4363static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4364 gpa_t *gpa, struct x86_exception *exception,
4365 bool write)
4366{
97d64b78
AK		 4367 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4368 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4369
be94f6b7
HH		 4370 /*
4371 * currently PKRU is only applied to ept enabled guest so
4372 * there is no pkey in EPT page table for L1 guest or EPT
4373 * shadow page table for L2 guest.
4374 */
97d64b78 4375 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4376 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4377 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4378 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4379 (gva & (PAGE_SIZE - 1));
4f022648 4380 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4381 return 1;
4382 }
4383
af7cc7d1
XG		 4384 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4385
4386 if (*gpa == UNMAPPED_GVA)
4387 return -1;
4388
4389 /* For APIC access vmexit */
4390 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4391 return 1;
4392
4f022648
XG		 4393 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4394 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4395 return 1;
4f022648 4396 }
bebb106a 4397
af7cc7d1
XG		 4398 return 0;
4399}
4400
3200f405 4401int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4402 const void *val, int bytes)
bbd9b64e
CO		 4403{
4404 int ret;
4405
54bf36aa 4406 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4407 if (ret < 0)
bbd9b64e 4408 return 0;
0eb05bf2 4409 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4410 return 1;
4411}
4412
77d197b2
XG		 4413struct read_write_emulator_ops {
4414 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4415 int bytes);
4416 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4417 void *val, int bytes);
4418 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4419 int bytes, void *val);
4420 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4421 void *val, int bytes);
4422 bool write;
4423};
4424
4425static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4426{
4427 if (vcpu->mmio_read_completed) {
77d197b2 4428 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4429 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4430 vcpu->mmio_read_completed = 0;
4431 return 1;
4432 }
4433
4434 return 0;
4435}
4436
4437static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4438 void *val, int bytes)
4439{
54bf36aa 4440 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4441}
4442
4443static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4444 void *val, int bytes)
4445{
4446 return emulator_write_phys(vcpu, gpa, val, bytes);
4447}
4448
4449static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4450{
4451 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4452 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4453}
4454
4455static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4456 void *val, int bytes)
4457{
4458 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4459 return X86EMUL_IO_NEEDED;
4460}
4461
4462static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4463 void *val, int bytes)
4464{
f78146b0
AK		 4465 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4466
87da7e66 4467 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4468 return X86EMUL_CONTINUE;
4469}
4470
0fbe9b0b 4471static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4472 .read_write_prepare = read_prepare,
4473 .read_write_emulate = read_emulate,
4474 .read_write_mmio = vcpu_mmio_read,
4475 .read_write_exit_mmio = read_exit_mmio,
4476};
4477
0fbe9b0b 4478static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4479 .read_write_emulate = write_emulate,
4480 .read_write_mmio = write_mmio,
4481 .read_write_exit_mmio = write_exit_mmio,
4482 .write = true,
4483};
4484
22388a3c
XG		 4485static int emulator_read_write_onepage(unsigned long addr, void *val,
4486 unsigned int bytes,
4487 struct x86_exception *exception,
4488 struct kvm_vcpu *vcpu,
0fbe9b0b 4489 const struct read_write_emulator_ops *ops)
bbd9b64e 4490{
af7cc7d1
XG		 4491 gpa_t gpa;
4492 int handled, ret;
22388a3c 4493 bool write = ops->write;
f78146b0 4494 struct kvm_mmio_fragment *frag;
10589a46 4495
22388a3c 4496 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4497
af7cc7d1 4498 if (ret < 0)
bbd9b64e 4499 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4500
4501 /* For APIC access vmexit */
af7cc7d1 4502 if (ret)
bbd9b64e
CO		 4503 goto mmio;
4504
22388a3c 4505 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4506 return X86EMUL_CONTINUE;
4507
4508mmio:
4509 /*
4510 * Is this MMIO handled locally?
4511 */
22388a3c 4512 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4513 if (handled == bytes)
bbd9b64e 4514 return X86EMUL_CONTINUE;
bbd9b64e 4515
70252a10
AK		 4516 gpa += handled;
4517 bytes -= handled;
4518 val += handled;
4519
87da7e66
XG		 4520 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4521 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4522 frag->gpa = gpa;
4523 frag->data = val;
4524 frag->len = bytes;
f78146b0 4525 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4526}
4527
52eb5a6d
XL		 4528static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4529 unsigned long addr,
22388a3c
XG		 4530 void *val, unsigned int bytes,
4531 struct x86_exception *exception,
0fbe9b0b 4532 const struct read_write_emulator_ops *ops)
bbd9b64e 4533{
0f65dd70 4534 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4535 gpa_t gpa;
4536 int rc;
4537
4538 if (ops->read_write_prepare &&
4539 ops->read_write_prepare(vcpu, val, bytes))
4540 return X86EMUL_CONTINUE;
4541
4542 vcpu->mmio_nr_fragments = 0;
0f65dd70 4543
bbd9b64e
CO		 4544 /* Crossing a page boundary? */
4545 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4546 int now;
bbd9b64e
CO		 4547
4548 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4549 rc = emulator_read_write_onepage(addr, val, now, exception,
4550 vcpu, ops);
4551
bbd9b64e
CO		 4552 if (rc != X86EMUL_CONTINUE)
4553 return rc;
4554 addr += now;
bac15531
NA		 4555 if (ctxt->mode != X86EMUL_MODE_PROT64)
4556 addr = (u32)addr;
bbd9b64e
CO		 4557 val += now;
4558 bytes -= now;
4559 }
22388a3c 4560
f78146b0
AK		 4561 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4562 vcpu, ops);
4563 if (rc != X86EMUL_CONTINUE)
4564 return rc;
4565
4566 if (!vcpu->mmio_nr_fragments)
4567 return rc;
4568
4569 gpa = vcpu->mmio_fragments[0].gpa;
4570
4571 vcpu->mmio_needed = 1;
4572 vcpu->mmio_cur_fragment = 0;
4573
87da7e66 4574 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4575 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4576 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4577 vcpu->run->mmio.phys_addr = gpa;
4578
4579 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4580}
4581
4582static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4583 unsigned long addr,
4584 void *val,
4585 unsigned int bytes,
4586 struct x86_exception *exception)
4587{
4588 return emulator_read_write(ctxt, addr, val, bytes,
4589 exception, &read_emultor);
4590}
4591
52eb5a6d 4592static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4593 unsigned long addr,
4594 const void *val,
4595 unsigned int bytes,
4596 struct x86_exception *exception)
4597{
4598 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4599 exception, &write_emultor);
bbd9b64e 4600}
bbd9b64e 4601
daea3e73
AK		 4602#define CMPXCHG_TYPE(t, ptr, old, new) \
4603 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4604
4605#ifdef CONFIG_X86_64
4606# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4607#else
4608# define CMPXCHG64(ptr, old, new) \
9749a6c0 4609 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4610#endif
4611
0f65dd70
AK		 4612static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4613 unsigned long addr,
bbd9b64e
CO		 4614 const void *old,
4615 const void *new,
4616 unsigned int bytes,
0f65dd70 4617 struct x86_exception *exception)
bbd9b64e 4618{
0f65dd70 4619 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4620 gpa_t gpa;
4621 struct page *page;
4622 char *kaddr;
4623 bool exchanged;
2bacc55c 4624
daea3e73
AK		 4625 /* guests cmpxchg8b have to be emulated atomically */
4626 if (bytes > 8 || (bytes & (bytes - 1)))
4627 goto emul_write;
10589a46 4628
daea3e73 4629 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4630
daea3e73
AK		 4631 if (gpa == UNMAPPED_GVA ||
4632 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4633 goto emul_write;
2bacc55c 4634
daea3e73
AK		 4635 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4636 goto emul_write;
72dc67a6 4637
54bf36aa 4638 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4639 if (is_error_page(page))
c19b8bd6 4640 goto emul_write;
72dc67a6 4641
8fd75e12 4642 kaddr = kmap_atomic(page);
daea3e73
AK		 4643 kaddr += offset_in_page(gpa);
4644 switch (bytes) {
4645 case 1:
4646 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4647 break;
4648 case 2:
4649 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4650 break;
4651 case 4:
4652 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4653 break;
4654 case 8:
4655 exchanged = CMPXCHG64(kaddr, old, new);
4656 break;
4657 default:
4658 BUG();
2bacc55c 4659 }
8fd75e12 4660 kunmap_atomic(kaddr);
daea3e73
AK		 4661 kvm_release_page_dirty(page);
4662
4663 if (!exchanged)
4664 return X86EMUL_CMPXCHG_FAILED;
4665
54bf36aa 4666 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4667 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4668
4669 return X86EMUL_CONTINUE;
4a5f48f6 4670
3200f405 4671emul_write:
daea3e73 4672 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4673
0f65dd70 4674 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4675}
4676
cf8f70bf
GN		 4677static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4678{
4679 /* TODO: String I/O for in kernel device */
4680 int r;
4681
4682 if (vcpu->arch.pio.in)
e32edf4f 4683 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4684 vcpu->arch.pio.size, pd);
4685 else
e32edf4f 4686 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4687 vcpu->arch.pio.port, vcpu->arch.pio.size,
4688 pd);
4689 return r;
4690}
4691
6f6fbe98
XG		 4692static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4693 unsigned short port, void *val,
4694 unsigned int count, bool in)
cf8f70bf 4695{
cf8f70bf 4696 vcpu->arch.pio.port = port;
6f6fbe98 4697 vcpu->arch.pio.in = in;
7972995b 4698 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4699 vcpu->arch.pio.size = size;
4700
4701 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4702 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4703 return 1;
4704 }
4705
4706 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4707 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4708 vcpu->run->io.size = size;
4709 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4710 vcpu->run->io.count = count;
4711 vcpu->run->io.port = port;
4712
4713 return 0;
4714}
4715
6f6fbe98
XG		 4716static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4717 int size, unsigned short port, void *val,
4718 unsigned int count)
cf8f70bf 4719{
ca1d4a9e 4720 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4721 int ret;
ca1d4a9e 4722
6f6fbe98
XG		 4723 if (vcpu->arch.pio.count)
4724 goto data_avail;
cf8f70bf 4725
6f6fbe98
XG		 4726 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4727 if (ret) {
4728data_avail:
4729 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4730 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4731 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4732 return 1;
4733 }
4734
cf8f70bf
GN		 4735 return 0;
4736}
4737
6f6fbe98
XG		 4738static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4739 int size, unsigned short port,
4740 const void *val, unsigned int count)
4741{
4742 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4743
4744 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4745 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4746 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4747}
4748
bbd9b64e
CO		 4749static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4750{
4751 return kvm_x86_ops->get_segment_base(vcpu, seg);
4752}
4753
3cb16fe7 4754static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4755{
3cb16fe7 4756 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4757}
4758
5cb56059 4759int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4760{
4761 if (!need_emulate_wbinvd(vcpu))
4762 return X86EMUL_CONTINUE;
4763
4764 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4765 int cpu = get_cpu();
4766
4767 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4768 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4769 wbinvd_ipi, NULL, 1);
2eec7343 4770 put_cpu();
f5f48ee1 4771 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4772 } else
4773 wbinvd();
f5f48ee1
SY		 4774 return X86EMUL_CONTINUE;
4775}
5cb56059
JS		 4776
4777int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4778{
4779 kvm_x86_ops->skip_emulated_instruction(vcpu);
4780 return kvm_emulate_wbinvd_noskip(vcpu);
4781}
f5f48ee1
SY		 4782EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4783
5cb56059
JS		 4784
4785
bcaf5cc5
AK		 4786static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4787{
5cb56059 4788 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4789}
4790
52eb5a6d
XL		 4791static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4792 unsigned long *dest)
bbd9b64e 4793{
16f8a6f9 4794 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4795}
4796
52eb5a6d
XL		 4797static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4798 unsigned long value)
bbd9b64e 4799{
338dbc97 4800
717746e3 4801 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4802}
4803
52a46617 4804static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4805{
52a46617 4806 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4807}
4808
717746e3 4809static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4810{
717746e3 4811 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4812 unsigned long value;
4813
4814 switch (cr) {
4815 case 0:
4816 value = kvm_read_cr0(vcpu);
4817 break;
4818 case 2:
4819 value = vcpu->arch.cr2;
4820 break;
4821 case 3:
9f8fe504 4822 value = kvm_read_cr3(vcpu);
52a46617
GN		 4823 break;
4824 case 4:
4825 value = kvm_read_cr4(vcpu);
4826 break;
4827 case 8:
4828 value = kvm_get_cr8(vcpu);
4829 break;
4830 default:
a737f256 4831 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4832 return 0;
4833 }
4834
4835 return value;
4836}
4837
717746e3 4838static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4839{
717746e3 4840 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4841 int res = 0;
4842
52a46617
GN		 4843 switch (cr) {
4844 case 0:
49a9b07e 4845 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4846 break;
4847 case 2:
4848 vcpu->arch.cr2 = val;
4849 break;
4850 case 3:
2390218b 4851 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4852 break;
4853 case 4:
a83b29c6 4854 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4855 break;
4856 case 8:
eea1cff9 4857 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4858 break;
4859 default:
a737f256 4860 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4861 res = -1;
52a46617 4862 }
0f12244f
GN		 4863
4864 return res;
52a46617
GN		 4865}
4866
717746e3 4867static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4868{
717746e3 4869 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4870}
4871
4bff1e86 4872static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4873{
4bff1e86 4874 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4875}
4876
4bff1e86 4877static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4878{
4bff1e86 4879 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4880}
4881
1ac9d0cf
AK		 4882static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4883{
4884 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4885}
4886
4887static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4888{
4889 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4890}
4891
4bff1e86
AK		 4892static unsigned long emulator_get_cached_segment_base(
4893 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4894{
4bff1e86 4895 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4896}
4897
1aa36616
AK		 4898static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4899 struct desc_struct *desc, u32 *base3,
4900 int seg)
2dafc6c2
GN		 4901{
4902 struct kvm_segment var;
4903
4bff1e86 4904 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4905 *selector = var.selector;
2dafc6c2 4906
378a8b09
GN		 4907 if (var.unusable) {
4908 memset(desc, 0, sizeof(*desc));
2dafc6c2 4909 return false;
378a8b09 4910 }
2dafc6c2
GN		 4911
4912 if (var.g)
4913 var.limit >>= 12;
4914 set_desc_limit(desc, var.limit);
4915 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4916#ifdef CONFIG_X86_64
4917 if (base3)
4918 *base3 = var.base >> 32;
4919#endif
2dafc6c2
GN		 4920 desc->type = var.type;
4921 desc->s = var.s;
4922 desc->dpl = var.dpl;
4923 desc->p = var.present;
4924 desc->avl = var.avl;
4925 desc->l = var.l;
4926 desc->d = var.db;
4927 desc->g = var.g;
4928
4929 return true;
4930}
4931
1aa36616
AK		 4932static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4933 struct desc_struct *desc, u32 base3,
4934 int seg)
2dafc6c2 4935{
4bff1e86 4936 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4937 struct kvm_segment var;
4938
1aa36616 4939 var.selector = selector;
2dafc6c2 4940 var.base = get_desc_base(desc);
5601d05b
GN		 4941#ifdef CONFIG_X86_64
4942 var.base |= ((u64)base3) << 32;
4943#endif
2dafc6c2
GN		 4944 var.limit = get_desc_limit(desc);
4945 if (desc->g)
4946 var.limit = (var.limit << 12) | 0xfff;
4947 var.type = desc->type;
2dafc6c2
GN		 4948 var.dpl = desc->dpl;
4949 var.db = desc->d;
4950 var.s = desc->s;
4951 var.l = desc->l;
4952 var.g = desc->g;
4953 var.avl = desc->avl;
4954 var.present = desc->p;
4955 var.unusable = !var.present;
4956 var.padding = 0;
4957
4958 kvm_set_segment(vcpu, &var, seg);
4959 return;
4960}
4961
717746e3
AK		 4962static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4963 u32 msr_index, u64 *pdata)
4964{
609e36d3
PB		 4965 struct msr_data msr;
4966 int r;
4967
4968 msr.index = msr_index;
4969 msr.host_initiated = false;
4970 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4971 if (r)
4972 return r;
4973
4974 *pdata = msr.data;
4975 return 0;
717746e3
AK		 4976}
4977
4978static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4979 u32 msr_index, u64 data)
4980{
8fe8ab46
WA		 4981 struct msr_data msr;
4982
4983 msr.data = data;
4984 msr.index = msr_index;
4985 msr.host_initiated = false;
4986 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4987}
4988
64d60670
PB		 4989static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4990{
4991 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4992
4993 return vcpu->arch.smbase;
4994}
4995
4996static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4997{
4998 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4999
5000 vcpu->arch.smbase = smbase;
5001}
5002
67f4d428
NA		 5003static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5004 u32 pmc)
5005{
c6702c9d 5006 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5007}
5008
222d21aa
AK		 5009static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5010 u32 pmc, u64 *pdata)
5011{
c6702c9d 5012 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5013}
5014
6c3287f7
AK		 5015static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5016{
5017 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5018}
5019
5037f6f3
AK		 5020static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5021{
5022 preempt_disable();
5197b808 5023 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5024 /*
5025 * CR0.TS may reference the host fpu state, not the guest fpu state,
5026 * so it may be clear at this point.
5027 */
5028 clts();
5029}
5030
5031static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5032{
5033 preempt_enable();
5034}
5035
2953538e 5036static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5037 struct x86_instruction_info *info,
c4f035c6
AK		 5038 enum x86_intercept_stage stage)
5039{
2953538e 5040 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5041}
5042
0017f93a 5043static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5044 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5045{
0017f93a 5046 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5047}
5048
dd856efa
AK		 5049static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5050{
5051 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5052}
5053
5054static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5055{
5056 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5057}
5058
801806d9
NA		 5059static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5060{
5061 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5062}
5063
0225fb50 5064static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5065 .read_gpr = emulator_read_gpr,
5066 .write_gpr = emulator_write_gpr,
1871c602 5067 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5068 .write_std = kvm_write_guest_virt_system,
7a036a6f 5069 .read_phys = kvm_read_guest_phys_system,
1871c602 5070 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5071 .read_emulated = emulator_read_emulated,
5072 .write_emulated = emulator_write_emulated,
5073 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5074 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5075 .pio_in_emulated = emulator_pio_in_emulated,
5076 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5077 .get_segment = emulator_get_segment,
5078 .set_segment = emulator_set_segment,
5951c442 5079 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5080 .get_gdt = emulator_get_gdt,
160ce1f1 5081 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5082 .set_gdt = emulator_set_gdt,
5083 .set_idt = emulator_set_idt,
52a46617
GN		 5084 .get_cr = emulator_get_cr,
5085 .set_cr = emulator_set_cr,
9c537244 5086 .cpl = emulator_get_cpl,
35aa5375
GN		 5087 .get_dr = emulator_get_dr,
5088 .set_dr = emulator_set_dr,
64d60670
PB		 5089 .get_smbase = emulator_get_smbase,
5090 .set_smbase = emulator_set_smbase,
717746e3
AK		 5091 .set_msr = emulator_set_msr,
5092 .get_msr = emulator_get_msr,
67f4d428 5093 .check_pmc = emulator_check_pmc,
222d21aa 5094 .read_pmc = emulator_read_pmc,
6c3287f7 5095 .halt = emulator_halt,
bcaf5cc5 5096 .wbinvd = emulator_wbinvd,
d6aa1000 5097 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5098 .get_fpu = emulator_get_fpu,
5099 .put_fpu = emulator_put_fpu,
c4f035c6 5100 .intercept = emulator_intercept,
bdb42f5a 5101 .get_cpuid = emulator_get_cpuid,
801806d9 5102 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5103};
5104
95cb2295
GN		 5105static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5106{
37ccdcbe 5107 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5108 /*
5109 * an sti; sti; sequence only disable interrupts for the first
5110 * instruction. So, if the last instruction, be it emulated or
5111 * not, left the system with the INT_STI flag enabled, it
5112 * means that the last instruction is an sti. We should not
5113 * leave the flag on in this case. The same goes for mov ss
5114 */
37ccdcbe
PB		 5115 if (int_shadow & mask)
5116 mask = 0;
6addfc42 5117 if (unlikely(int_shadow || mask)) {
95cb2295 5118 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5119 if (!mask)
5120 kvm_make_request(KVM_REQ_EVENT, vcpu);
5121 }
95cb2295
GN		 5122}
5123
ef54bcfe 5124static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5125{
5126 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5127 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5128 return kvm_propagate_fault(vcpu, &ctxt->exception);
5129
5130 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5131 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5132 ctxt->exception.error_code);
54b8486f 5133 else
da9cb575 5134 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5135 return false;
54b8486f
GN		 5136}
5137
8ec4722d
MG		 5138static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5139{
adf52235 5140 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5141 int cs_db, cs_l;
5142
8ec4722d
MG		 5143 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5144
adf52235
TY		 5145 ctxt->eflags = kvm_get_rflags(vcpu);
5146 ctxt->eip = kvm_rip_read(vcpu);
5147 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5148 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5149 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5150 cs_db ? X86EMUL_MODE_PROT32 :
5151 X86EMUL_MODE_PROT16;
a584539b 5152 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5153 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5154 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5155 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5156
dd856efa 5157 init_decode_cache(ctxt);
7ae441ea 5158 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5159}
5160
71f9833b 5161int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5162{
9d74191a 5163 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5164 int ret;
5165
5166 init_emulate_ctxt(vcpu);
5167
9dac77fa
AK		 5168 ctxt->op_bytes = 2;
5169 ctxt->ad_bytes = 2;
5170 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5171 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5172
5173 if (ret != X86EMUL_CONTINUE)
5174 return EMULATE_FAIL;
5175
9dac77fa 5176 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5177 kvm_rip_write(vcpu, ctxt->eip);
5178 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5179
5180 if (irq == NMI_VECTOR)
7460fb4a 5181 vcpu->arch.nmi_pending = 0;
63995653
MG		 5182 else
5183 vcpu->arch.interrupt.pending = false;
5184
5185 return EMULATE_DONE;
5186}
5187EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5188
6d77dbfc
GN		 5189static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5190{
fc3a9157
JR		 5191 int r = EMULATE_DONE;
5192
6d77dbfc
GN		 5193 ++vcpu->stat.insn_emulation_fail;
5194 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5195 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5196 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5197 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5198 vcpu->run->internal.ndata = 0;
5199 r = EMULATE_FAIL;
5200 }
6d77dbfc 5201 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5202
5203 return r;
6d77dbfc
GN		 5204}
5205
93c05d3e 5206static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5207 bool write_fault_to_shadow_pgtable,
5208 int emulation_type)
a6f177ef 5209{
95b3cf69 5210 gpa_t gpa = cr2;
ba049e93 5211 kvm_pfn_t pfn;
a6f177ef 5212
991eebf9
GN		 5213 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5214 return false;
5215
95b3cf69
XG		 5216 if (!vcpu->arch.mmu.direct_map) {
5217 /*
5218 * Write permission should be allowed since only
5219 * write access need to be emulated.
5220 */
5221 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5222
95b3cf69
XG		 5223 /*
5224 * If the mapping is invalid in guest, let cpu retry
5225 * it to generate fault.
5226 */
5227 if (gpa == UNMAPPED_GVA)
5228 return true;
5229 }
a6f177ef 5230
8e3d9d06
XG		 5231 /*
5232 * Do not retry the unhandleable instruction if it faults on the
5233 * readonly host memory, otherwise it will goto a infinite loop:
5234 * retry instruction -> write #PF -> emulation fail -> retry
5235 * instruction -> ...
5236 */
5237 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5238
5239 /*
5240 * If the instruction failed on the error pfn, it can not be fixed,
5241 * report the error to userspace.
5242 */
5243 if (is_error_noslot_pfn(pfn))
5244 return false;
5245
5246 kvm_release_pfn_clean(pfn);
5247
5248 /* The instructions are well-emulated on direct mmu. */
5249 if (vcpu->arch.mmu.direct_map) {
5250 unsigned int indirect_shadow_pages;
5251
5252 spin_lock(&vcpu->kvm->mmu_lock);
5253 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5254 spin_unlock(&vcpu->kvm->mmu_lock);
5255
5256 if (indirect_shadow_pages)
5257 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5258
a6f177ef 5259 return true;
8e3d9d06 5260 }
a6f177ef 5261
95b3cf69
XG		 5262 /*
5263 * if emulation was due to access to shadowed page table
5264 * and it failed try to unshadow page and re-enter the
5265 * guest to let CPU execute the instruction.
5266 */
5267 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5268
5269 /*
5270 * If the access faults on its page table, it can not
5271 * be fixed by unprotecting shadow page and it should
5272 * be reported to userspace.
5273 */
5274 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5275}
5276
1cb3f3ae
XG		 5277static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5278 unsigned long cr2, int emulation_type)
5279{
5280 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5281 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5282
5283 last_retry_eip = vcpu->arch.last_retry_eip;
5284 last_retry_addr = vcpu->arch.last_retry_addr;
5285
5286 /*
5287 * If the emulation is caused by #PF and it is non-page_table
5288 * writing instruction, it means the VM-EXIT is caused by shadow
5289 * page protected, we can zap the shadow page and retry this
5290 * instruction directly.
5291 *
5292 * Note: if the guest uses a non-page-table modifying instruction
5293 * on the PDE that points to the instruction, then we will unmap
5294 * the instruction and go to an infinite loop. So, we cache the
5295 * last retried eip and the last fault address, if we meet the eip
5296 * and the address again, we can break out of the potential infinite
5297 * loop.
5298 */
5299 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5300
5301 if (!(emulation_type & EMULTYPE_RETRY))
5302 return false;
5303
5304 if (x86_page_table_writing_insn(ctxt))
5305 return false;
5306
5307 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5308 return false;
5309
5310 vcpu->arch.last_retry_eip = ctxt->eip;
5311 vcpu->arch.last_retry_addr = cr2;
5312
5313 if (!vcpu->arch.mmu.direct_map)
5314 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5315
22368028 5316 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5317
5318 return true;
5319}
5320
716d51ab
GN		 5321static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5322static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5323
64d60670 5324static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5325{
64d60670 5326 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5327 /* This is a good place to trace that we are exiting SMM. */
5328 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5329
c43203ca
PB		 5330 /* Process a latched INIT or SMI, if any. */
5331 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5332 }
699023e2
PB		 5333
5334 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5335}
5336
5337static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5338{
5339 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5340
a584539b 5341 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5342
5343 if (changed & HF_SMM_MASK)
5344 kvm_smm_changed(vcpu);
a584539b
PB		 5345}
5346
4a1e10d5
PB		 5347static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5348 unsigned long *db)
5349{
5350 u32 dr6 = 0;
5351 int i;
5352 u32 enable, rwlen;
5353
5354 enable = dr7;
5355 rwlen = dr7 >> 16;
5356 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5357 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5358 dr6 |= (1 << i);
5359 return dr6;
5360}
5361
6addfc42 5362static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5363{
5364 struct kvm_run *kvm_run = vcpu->run;
5365
5366 /*
6addfc42
PB		 5367 * rflags is the old, "raw" value of the flags. The new value has
5368 * not been saved yet.
663f4c61
PB		 5369 *
5370 * This is correct even for TF set by the guest, because "the
5371 * processor will not generate this exception after the instruction
5372 * that sets the TF flag".
5373 */
663f4c61
PB		 5374 if (unlikely(rflags & X86_EFLAGS_TF)) {
5375 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5376 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5377 DR6_RTM;
663f4c61
PB		 5378 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5379 kvm_run->debug.arch.exception = DB_VECTOR;
5380 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5381 *r = EMULATE_USER_EXIT;
5382 } else {
5383 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5384 /*
5385 * "Certain debug exceptions may clear bit 0-3. The
5386 * remaining contents of the DR6 register are never
5387 * cleared by the processor".
5388 */
5389 vcpu->arch.dr6 &= ~15;
6f43ed01 5390 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5391 kvm_queue_exception(vcpu, DB_VECTOR);
5392 }
5393 }
5394}
5395
4a1e10d5
PB		 5396static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5397{
4a1e10d5
PB		 5398 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5399 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5400 struct kvm_run *kvm_run = vcpu->run;
5401 unsigned long eip = kvm_get_linear_rip(vcpu);
5402 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5403 vcpu->arch.guest_debug_dr7,
5404 vcpu->arch.eff_db);
5405
5406 if (dr6 != 0) {
6f43ed01 5407 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5408 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5409 kvm_run->debug.arch.exception = DB_VECTOR;
5410 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5411 *r = EMULATE_USER_EXIT;
5412 return true;
5413 }
5414 }
5415
4161a569
NA		 5416 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5417 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5418 unsigned long eip = kvm_get_linear_rip(vcpu);
5419 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5420 vcpu->arch.dr7,
5421 vcpu->arch.db);
5422
5423 if (dr6 != 0) {
5424 vcpu->arch.dr6 &= ~15;
6f43ed01 5425 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5426 kvm_queue_exception(vcpu, DB_VECTOR);
5427 *r = EMULATE_DONE;
5428 return true;
5429 }
5430 }
5431
5432 return false;
5433}
5434
51d8b661
AP		 5435int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5436 unsigned long cr2,
dc25e89e
AP		 5437 int emulation_type,
5438 void *insn,
5439 int insn_len)
bbd9b64e 5440{
95cb2295 5441 int r;
9d74191a 5442 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5443 bool writeback = true;
93c05d3e 5444 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5445
93c05d3e
XG		 5446 /*
5447 * Clear write_fault_to_shadow_pgtable here to ensure it is
5448 * never reused.
5449 */
5450 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5451 kvm_clear_exception_queue(vcpu);
8d7d8102 5452
571008da 5453 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5454 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5455
5456 /*
5457 * We will reenter on the same instruction since
5458 * we do not set complete_userspace_io. This does not
5459 * handle watchpoints yet, those would be handled in
5460 * the emulate_ops.
5461 */
5462 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5463 return r;
5464
9d74191a
TY		 5465 ctxt->interruptibility = 0;
5466 ctxt->have_exception = false;
e0ad0b47 5467 ctxt->exception.vector = -1;
9d74191a 5468 ctxt->perm_ok = false;
bbd9b64e 5469
b51e974f 5470 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5471
9d74191a 5472 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5473
e46479f8 5474 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5475 ++vcpu->stat.insn_emulation;
1d2887e2 5476 if (r != EMULATION_OK) {
4005996e
AK		 5477 if (emulation_type & EMULTYPE_TRAP_UD)
5478 return EMULATE_FAIL;
991eebf9
GN		 5479 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5480 emulation_type))
bbd9b64e 5481 return EMULATE_DONE;
6d77dbfc
GN		 5482 if (emulation_type & EMULTYPE_SKIP)
5483 return EMULATE_FAIL;
5484 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5485 }
5486 }
5487
ba8afb6b 5488 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5489 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5490 if (ctxt->eflags & X86_EFLAGS_RF)
5491 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5492 return EMULATE_DONE;
5493 }
5494
1cb3f3ae
XG		 5495 if (retry_instruction(ctxt, cr2, emulation_type))
5496 return EMULATE_DONE;
5497
7ae441ea 5498 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5499 changes registers values during IO operation */
7ae441ea
GN		 5500 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5501 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5502 emulator_invalidate_register_cache(ctxt);
7ae441ea 5503 }
4d2179e1 5504
5cd21917 5505restart:
9d74191a 5506 r = x86_emulate_insn(ctxt);
bbd9b64e 5507
775fde86
JR		 5508 if (r == EMULATION_INTERCEPTED)
5509 return EMULATE_DONE;
5510
d2ddd1c4 5511 if (r == EMULATION_FAILED) {
991eebf9
GN		 5512 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5513 emulation_type))
c3cd7ffa
GN		 5514 return EMULATE_DONE;
5515
6d77dbfc 5516 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5517 }
5518
9d74191a 5519 if (ctxt->have_exception) {
d2ddd1c4 5520 r = EMULATE_DONE;
ef54bcfe
PB		 5521 if (inject_emulated_exception(vcpu))
5522 return r;
d2ddd1c4 5523 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5524 if (!vcpu->arch.pio.in) {
5525 /* FIXME: return into emulator if single-stepping. */
3457e419 5526 vcpu->arch.pio.count = 0;
0912c977 5527 } else {
7ae441ea 5528 writeback = false;
716d51ab
GN		 5529 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5530 }
ac0a48c3 5531 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5532 } else if (vcpu->mmio_needed) {
5533 if (!vcpu->mmio_is_write)
5534 writeback = false;
ac0a48c3 5535 r = EMULATE_USER_EXIT;
716d51ab 5536 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5537 } else if (r == EMULATION_RESTART)
5cd21917 5538 goto restart;
d2ddd1c4
GN		 5539 else
5540 r = EMULATE_DONE;
f850e2e6 5541
7ae441ea 5542 if (writeback) {
6addfc42 5543 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5544 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5545 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5546 if (vcpu->arch.hflags != ctxt->emul_flags)
5547 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5548 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5549 if (r == EMULATE_DONE)
6addfc42 5550 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5551 if (!ctxt->have_exception ||
5552 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5553 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5554
5555 /*
5556 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5557 * do nothing, and it will be requested again as soon as
5558 * the shadow expires. But we still need to check here,
5559 * because POPF has no interrupt shadow.
5560 */
5561 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5562 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5563 } else
5564 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5565
5566 return r;
de7d789a 5567}
51d8b661 5568EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5569
cf8f70bf 5570int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5571{
cf8f70bf 5572 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5573 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5574 size, port, &val, 1);
cf8f70bf 5575 /* do not return to emulator after return from userspace */
7972995b 5576 vcpu->arch.pio.count = 0;
de7d789a
CO		 5577 return ret;
5578}
cf8f70bf 5579EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5580
251a5fd6 5581static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5582{
0a3aee0d 5583 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5584 return 0;
8cfdc000
ZA		 5585}
5586
5587static void tsc_khz_changed(void *data)
c8076604 5588{
8cfdc000
ZA		 5589 struct cpufreq_freqs *freq = data;
5590 unsigned long khz = 0;
5591
5592 if (data)
5593 khz = freq->new;
5594 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5595 khz = cpufreq_quick_get(raw_smp_processor_id());
5596 if (!khz)
5597 khz = tsc_khz;
0a3aee0d 5598 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5599}
5600
c8076604
GH		 5601static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5602 void *data)
5603{
5604 struct cpufreq_freqs *freq = data;
5605 struct kvm *kvm;
5606 struct kvm_vcpu *vcpu;
5607 int i, send_ipi = 0;
5608
8cfdc000
ZA		 5609 /*
5610 * We allow guests to temporarily run on slowing clocks,
5611 * provided we notify them after, or to run on accelerating
5612 * clocks, provided we notify them before. Thus time never
5613 * goes backwards.
5614 *
5615 * However, we have a problem. We can't atomically update
5616 * the frequency of a given CPU from this function; it is
5617 * merely a notifier, which can be called from any CPU.
5618 * Changing the TSC frequency at arbitrary points in time
5619 * requires a recomputation of local variables related to
5620 * the TSC for each VCPU. We must flag these local variables
5621 * to be updated and be sure the update takes place with the
5622 * new frequency before any guests proceed.
5623 *
5624 * Unfortunately, the combination of hotplug CPU and frequency
5625 * change creates an intractable locking scenario; the order
5626 * of when these callouts happen is undefined with respect to
5627 * CPU hotplug, and they can race with each other. As such,
5628 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5629 * undefined; you can actually have a CPU frequency change take
5630 * place in between the computation of X and the setting of the
5631 * variable. To protect against this problem, all updates of
5632 * the per_cpu tsc_khz variable are done in an interrupt
5633 * protected IPI, and all callers wishing to update the value
5634 * must wait for a synchronous IPI to complete (which is trivial
5635 * if the caller is on the CPU already). This establishes the
5636 * necessary total order on variable updates.
5637 *
5638 * Note that because a guest time update may take place
5639 * anytime after the setting of the VCPU's request bit, the
5640 * correct TSC value must be set before the request. However,
5641 * to ensure the update actually makes it to any guest which
5642 * starts running in hardware virtualization between the set
5643 * and the acquisition of the spinlock, we must also ping the
5644 * CPU after setting the request bit.
5645 *
5646 */
5647
c8076604
GH		 5648 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5649 return 0;
5650 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5651 return 0;
8cfdc000
ZA		 5652
5653 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5654
2f303b74 5655 spin_lock(&kvm_lock);
c8076604 5656 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5657 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5658 if (vcpu->cpu != freq->cpu)
5659 continue;
c285545f 5660 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5661 if (vcpu->cpu != smp_processor_id())
8cfdc000 5662 send_ipi = 1;
c8076604
GH		 5663 }
5664 }
2f303b74 5665 spin_unlock(&kvm_lock);
c8076604
GH		 5666
5667 if (freq->old < freq->new && send_ipi) {
5668 /*
5669 * We upscale the frequency. Must make the guest
5670 * doesn't see old kvmclock values while running with
5671 * the new frequency, otherwise we risk the guest sees
5672 * time go backwards.
5673 *
5674 * In case we update the frequency for another cpu
5675 * (which might be in guest context) send an interrupt
5676 * to kick the cpu out of guest context. Next time
5677 * guest context is entered kvmclock will be updated,
5678 * so the guest will not see stale values.
5679 */
8cfdc000 5680 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5681 }
5682 return 0;
5683}
5684
5685static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5686 .notifier_call = kvmclock_cpufreq_notifier
5687};
5688
251a5fd6 5689static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5690{
251a5fd6
SAS		 5691 tsc_khz_changed(NULL);
5692 return 0;
8cfdc000
ZA		 5693}
5694
b820cc0c
ZA		 5695static void kvm_timer_init(void)
5696{
5697 int cpu;
5698
c285545f 5699 max_tsc_khz = tsc_khz;
460dd42e 5700
b820cc0c 5701 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5702#ifdef CONFIG_CPU_FREQ
5703 struct cpufreq_policy policy;
5704 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5705 cpu = get_cpu();
5706 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5707 if (policy.cpuinfo.max_freq)
5708 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5709 put_cpu();
c285545f 5710#endif
b820cc0c
ZA		 5711 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5712 CPUFREQ_TRANSITION_NOTIFIER);
5713 }
c285545f 5714 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5715
251a5fd6
SAS		 5716 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "AP_X86_KVM_CLK_ONLINE",
5717 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5718}
5719
ff9d07a0
ZY		 5720static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5721
f5132b01 5722int kvm_is_in_guest(void)
ff9d07a0 5723{
086c9855 5724 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5725}
5726
5727static int kvm_is_user_mode(void)
5728{
5729 int user_mode = 3;
dcf46b94 5730
086c9855
AS		 5731 if (__this_cpu_read(current_vcpu))
5732 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5733
ff9d07a0
ZY		 5734 return user_mode != 0;
5735}
5736
5737static unsigned long kvm_get_guest_ip(void)
5738{
5739 unsigned long ip = 0;
dcf46b94 5740
086c9855
AS		 5741 if (__this_cpu_read(current_vcpu))
5742 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5743
ff9d07a0
ZY		 5744 return ip;
5745}
5746
5747static struct perf_guest_info_callbacks kvm_guest_cbs = {
5748 .is_in_guest = kvm_is_in_guest,
5749 .is_user_mode = kvm_is_user_mode,
5750 .get_guest_ip = kvm_get_guest_ip,
5751};
5752
5753void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5754{
086c9855 5755 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5756}
5757EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5758
5759void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5760{
086c9855 5761 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5762}
5763EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5764
ce88decf
XG		 5765static void kvm_set_mmio_spte_mask(void)
5766{
5767 u64 mask;
5768 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5769
5770 /*
5771 * Set the reserved bits and the present bit of an paging-structure
5772 * entry to generate page fault with PFER.RSV = 1.
5773 */
885032b9 5774 /* Mask the reserved physical address bits. */
d1431483 5775 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5776
5777 /* Bit 62 is always reserved for 32bit host. */
5778 mask |= 0x3ull << 62;
5779
5780 /* Set the present bit. */
ce88decf
XG		 5781 mask |= 1ull;
5782
5783#ifdef CONFIG_X86_64
5784 /*
5785 * If reserved bit is not supported, clear the present bit to disable
5786 * mmio page fault.
5787 */
5788 if (maxphyaddr == 52)
5789 mask &= ~1ull;
5790#endif
5791
5792 kvm_mmu_set_mmio_spte_mask(mask);
5793}
5794
16e8d74d
MT		 5795#ifdef CONFIG_X86_64
5796static void pvclock_gtod_update_fn(struct work_struct *work)
5797{
d828199e
MT		 5798 struct kvm *kvm;
5799
5800 struct kvm_vcpu *vcpu;
5801 int i;
5802
2f303b74 5803 spin_lock(&kvm_lock);
d828199e
MT		 5804 list_for_each_entry(kvm, &vm_list, vm_list)
5805 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5806 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5807 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5808 spin_unlock(&kvm_lock);
16e8d74d
MT		 5809}
5810
5811static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5812
5813/*
5814 * Notification about pvclock gtod data update.
5815 */
5816static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5817 void *priv)
5818{
5819 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5820 struct timekeeper *tk = priv;
5821
5822 update_pvclock_gtod(tk);
5823
5824 /* disable master clock if host does not trust, or does not
5825 * use, TSC clocksource
5826 */
5827 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5828 atomic_read(&kvm_guest_has_master_clock) != 0)
5829 queue_work(system_long_wq, &pvclock_gtod_work);
5830
5831 return 0;
5832}
5833
5834static struct notifier_block pvclock_gtod_notifier = {
5835 .notifier_call = pvclock_gtod_notify,
5836};
5837#endif
5838
f8c16bba 5839int kvm_arch_init(void *opaque)
043405e1 5840{
b820cc0c 5841 int r;
6b61edf7 5842 struct kvm_x86_ops *ops = opaque;
f8c16bba 5843
f8c16bba
ZX		 5844 if (kvm_x86_ops) {
5845 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5846 r = -EEXIST;
5847 goto out;
f8c16bba
ZX		 5848 }
5849
5850 if (!ops->cpu_has_kvm_support()) {
5851 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5852 r = -EOPNOTSUPP;
5853 goto out;
f8c16bba
ZX		 5854 }
5855 if (ops->disabled_by_bios()) {
5856 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5857 r = -EOPNOTSUPP;
5858 goto out;
f8c16bba
ZX		 5859 }
5860
013f6a5d
MT		 5861 r = -ENOMEM;
5862 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5863 if (!shared_msrs) {
5864 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5865 goto out;
5866 }
5867
97db56ce
AK		 5868 r = kvm_mmu_module_init();
5869 if (r)
013f6a5d 5870 goto out_free_percpu;
97db56ce 5871
ce88decf 5872 kvm_set_mmio_spte_mask();
97db56ce 5873
f8c16bba 5874 kvm_x86_ops = ops;
920c8377 5875
7b52345e 5876 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8
BD		 5877 PT_DIRTY_MASK, PT64_NX_MASK, 0,
5878 PT_PRESENT_MASK);
b820cc0c 5879 kvm_timer_init();
c8076604 5880
ff9d07a0
ZY		 5881 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5882
d366bf7e 5883 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 5884 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5885
c5cc421b 5886 kvm_lapic_init();
16e8d74d
MT		 5887#ifdef CONFIG_X86_64
5888 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5889#endif
5890
f8c16bba 5891 return 0;
56c6d28a 5892
013f6a5d
MT		 5893out_free_percpu:
5894 free_percpu(shared_msrs);
56c6d28a 5895out:
56c6d28a 5896 return r;
043405e1 5897}
8776e519 5898
f8c16bba
ZX		 5899void kvm_arch_exit(void)
5900{
ff9d07a0
ZY		 5901 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5902
888d256e
JK		 5903 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5904 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5905 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 5906 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 5907#ifdef CONFIG_X86_64
5908 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5909#endif
f8c16bba 5910 kvm_x86_ops = NULL;
56c6d28a 5911 kvm_mmu_module_exit();
013f6a5d 5912 free_percpu(shared_msrs);
56c6d28a 5913}
f8c16bba 5914
5cb56059 5915int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5916{
5917 ++vcpu->stat.halt_exits;
35754c98 5918 if (lapic_in_kernel(vcpu)) {
a4535290 5919 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5920 return 1;
5921 } else {
5922 vcpu->run->exit_reason = KVM_EXIT_HLT;
5923 return 0;
5924 }
5925}
5cb56059
JS		 5926EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5927
5928int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5929{
5930 kvm_x86_ops->skip_emulated_instruction(vcpu);
5931 return kvm_vcpu_halt(vcpu);
5932}
8776e519
HB		 5933EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5934
6aef266c
SV		 5935/*
5936 * kvm_pv_kick_cpu_op: Kick a vcpu.
5937 *
5938 * @apicid - apicid of vcpu to be kicked.
5939 */
5940static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5941{
24d2166b 5942 struct kvm_lapic_irq lapic_irq;
6aef266c 5943
24d2166b
R		 5944 lapic_irq.shorthand = 0;
5945 lapic_irq.dest_mode = 0;
5946 lapic_irq.dest_id = apicid;
93bbf0b8 5947 lapic_irq.msi_redir_hint = false;
6aef266c 5948
24d2166b 5949 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5950 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5951}
5952
d62caabb
AS		 5953void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5954{
5955 vcpu->arch.apicv_active = false;
5956 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5957}
5958
8776e519
HB		 5959int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5960{
5961 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5962 int op_64_bit, r = 1;
8776e519 5963
5cb56059
JS		 5964 kvm_x86_ops->skip_emulated_instruction(vcpu);
5965
55cd8e5a
GN		 5966 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5967 return kvm_hv_hypercall(vcpu);
5968
5fdbf976
MT		 5969 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5970 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5971 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5972 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5973 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5974
229456fc 5975 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5976
a449c7aa
NA		 5977 op_64_bit = is_64_bit_mode(vcpu);
5978 if (!op_64_bit) {
8776e519
HB		 5979 nr &= 0xFFFFFFFF;
5980 a0 &= 0xFFFFFFFF;
5981 a1 &= 0xFFFFFFFF;
5982 a2 &= 0xFFFFFFFF;
5983 a3 &= 0xFFFFFFFF;
5984 }
5985
07708c4a
JK		 5986 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5987 ret = -KVM_EPERM;
5988 goto out;
5989 }
5990
8776e519 5991 switch (nr) {
b93463aa
AK		 5992 case KVM_HC_VAPIC_POLL_IRQ:
5993 ret = 0;
5994 break;
6aef266c
SV		 5995 case KVM_HC_KICK_CPU:
5996 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5997 ret = 0;
5998 break;
8776e519
HB		 5999 default:
6000 ret = -KVM_ENOSYS;
6001 break;
6002 }
07708c4a 6003out:
a449c7aa
NA		 6004 if (!op_64_bit)
6005 ret = (u32)ret;
5fdbf976 6006 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6007 ++vcpu->stat.hypercalls;
2f333bcb 6008 return r;
8776e519
HB		 6009}
6010EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6011
b6785def 6012static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6013{
d6aa1000 6014 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6015 char instruction[3];
5fdbf976 6016 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6017
8776e519 6018 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6019
9d74191a 6020 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6021}
6022
851ba692 6023static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6024{
782d422b
MG		 6025 return vcpu->run->request_interrupt_window &&
6026 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6027}
6028
851ba692 6029static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6030{
851ba692
AK		 6031 struct kvm_run *kvm_run = vcpu->run;
6032
91586a3b 6033 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6034 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6035 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6036 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6037 kvm_run->ready_for_interrupt_injection =
6038 pic_in_kernel(vcpu->kvm) ||
782d422b 6039 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6040}
6041
95ba8273
GN		 6042static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6043{
6044 int max_irr, tpr;
6045
6046 if (!kvm_x86_ops->update_cr8_intercept)
6047 return;
6048
bce87cce 6049 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6050 return;
6051
d62caabb
AS		 6052 if (vcpu->arch.apicv_active)
6053 return;
6054
8db3baa2
GN		 6055 if (!vcpu->arch.apic->vapic_addr)
6056 max_irr = kvm_lapic_find_highest_irr(vcpu);
6057 else
6058 max_irr = -1;
95ba8273
GN		 6059
6060 if (max_irr != -1)
6061 max_irr >>= 4;
6062
6063 tpr = kvm_lapic_get_cr8(vcpu);
6064
6065 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6066}
6067
b6b8a145 6068static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6069{
b6b8a145
JK		 6070 int r;
6071
95ba8273 6072 /* try to reinject previous events if any */
b59bb7bd 6073 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6074 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6075 vcpu->arch.exception.has_error_code,
6076 vcpu->arch.exception.error_code);
d6e8c854
NA		 6077
6078 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6079 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6080 X86_EFLAGS_RF);
6081
6bdf0662
NA		 6082 if (vcpu->arch.exception.nr == DB_VECTOR &&
6083 (vcpu->arch.dr7 & DR7_GD)) {
6084 vcpu->arch.dr7 &= ~DR7_GD;
6085 kvm_update_dr7(vcpu);
6086 }
6087
b59bb7bd
GN		 6088 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6089 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6090 vcpu->arch.exception.error_code,
6091 vcpu->arch.exception.reinject);
b6b8a145 6092 return 0;
b59bb7bd
GN		 6093 }
6094
95ba8273
GN		 6095 if (vcpu->arch.nmi_injected) {
6096 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6097 return 0;
95ba8273
GN		 6098 }
6099
6100 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6101 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6102 return 0;
6103 }
6104
6105 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6106 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6107 if (r != 0)
6108 return r;
95ba8273
GN		 6109 }
6110
6111 /* try to inject new event if pending */
c43203ca
PB		 6112 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6113 vcpu->arch.smi_pending = false;
ee2cd4b7 6114 enter_smm(vcpu);
c43203ca 6115 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6116 --vcpu->arch.nmi_pending;
6117 vcpu->arch.nmi_injected = true;
6118 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6119 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6120 /*
6121 * Because interrupts can be injected asynchronously, we are
6122 * calling check_nested_events again here to avoid a race condition.
6123 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6124 * proposal and current concerns. Perhaps we should be setting
6125 * KVM_REQ_EVENT only on certain events and not unconditionally?
6126 */
6127 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6128 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6129 if (r != 0)
6130 return r;
6131 }
95ba8273 6132 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6133 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6134 false);
6135 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6136 }
6137 }
ee2cd4b7 6138
b6b8a145 6139 return 0;
95ba8273
GN		 6140}
6141
7460fb4a
AK		 6142static void process_nmi(struct kvm_vcpu *vcpu)
6143{
6144 unsigned limit = 2;
6145
6146 /*
6147 * x86 is limited to one NMI running, and one NMI pending after it.
6148 * If an NMI is already in progress, limit further NMIs to just one.
6149 * Otherwise, allow two (and we'll inject the first one immediately).
6150 */
6151 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6152 limit = 1;
6153
6154 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6155 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6156 kvm_make_request(KVM_REQ_EVENT, vcpu);
6157}
6158
660a5d51
PB		 6159#define put_smstate(type, buf, offset, val) \
6160 *(type *)((buf) + (offset) - 0x7e00) = val
6161
ee2cd4b7 6162static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6163{
6164 u32 flags = 0;
6165 flags |= seg->g << 23;
6166 flags |= seg->db << 22;
6167 flags |= seg->l << 21;
6168 flags |= seg->avl << 20;
6169 flags |= seg->present << 15;
6170 flags |= seg->dpl << 13;
6171 flags |= seg->s << 12;
6172 flags |= seg->type << 8;
6173 return flags;
6174}
6175
ee2cd4b7 6176static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6177{
6178 struct kvm_segment seg;
6179 int offset;
6180
6181 kvm_get_segment(vcpu, &seg, n);
6182 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6183
6184 if (n < 3)
6185 offset = 0x7f84 + n * 12;
6186 else
6187 offset = 0x7f2c + (n - 3) * 12;
6188
6189 put_smstate(u32, buf, offset + 8, seg.base);
6190 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6191 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6192}
6193
efbb288a 6194#ifdef CONFIG_X86_64
ee2cd4b7 6195static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6196{
6197 struct kvm_segment seg;
6198 int offset;
6199 u16 flags;
6200
6201 kvm_get_segment(vcpu, &seg, n);
6202 offset = 0x7e00 + n * 16;
6203
ee2cd4b7 6204 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6205 put_smstate(u16, buf, offset, seg.selector);
6206 put_smstate(u16, buf, offset + 2, flags);
6207 put_smstate(u32, buf, offset + 4, seg.limit);
6208 put_smstate(u64, buf, offset + 8, seg.base);
6209}
efbb288a 6210#endif
660a5d51 6211
ee2cd4b7 6212static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6213{
6214 struct desc_ptr dt;
6215 struct kvm_segment seg;
6216 unsigned long val;
6217 int i;
6218
6219 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6220 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6221 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6222 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6223
6224 for (i = 0; i < 8; i++)
6225 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6226
6227 kvm_get_dr(vcpu, 6, &val);
6228 put_smstate(u32, buf, 0x7fcc, (u32)val);
6229 kvm_get_dr(vcpu, 7, &val);
6230 put_smstate(u32, buf, 0x7fc8, (u32)val);
6231
6232 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6233 put_smstate(u32, buf, 0x7fc4, seg.selector);
6234 put_smstate(u32, buf, 0x7f64, seg.base);
6235 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6236 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6237
6238 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6239 put_smstate(u32, buf, 0x7fc0, seg.selector);
6240 put_smstate(u32, buf, 0x7f80, seg.base);
6241 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6242 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6243
6244 kvm_x86_ops->get_gdt(vcpu, &dt);
6245 put_smstate(u32, buf, 0x7f74, dt.address);
6246 put_smstate(u32, buf, 0x7f70, dt.size);
6247
6248 kvm_x86_ops->get_idt(vcpu, &dt);
6249 put_smstate(u32, buf, 0x7f58, dt.address);
6250 put_smstate(u32, buf, 0x7f54, dt.size);
6251
6252 for (i = 0; i < 6; i++)
ee2cd4b7 6253 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6254
6255 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6256
6257 /* revision id */
6258 put_smstate(u32, buf, 0x7efc, 0x00020000);
6259 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6260}
6261
ee2cd4b7 6262static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6263{
6264#ifdef CONFIG_X86_64
6265 struct desc_ptr dt;
6266 struct kvm_segment seg;
6267 unsigned long val;
6268 int i;
6269
6270 for (i = 0; i < 16; i++)
6271 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6272
6273 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6274 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6275
6276 kvm_get_dr(vcpu, 6, &val);
6277 put_smstate(u64, buf, 0x7f68, val);
6278 kvm_get_dr(vcpu, 7, &val);
6279 put_smstate(u64, buf, 0x7f60, val);
6280
6281 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6282 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6283 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6284
6285 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6286
6287 /* revision id */
6288 put_smstate(u32, buf, 0x7efc, 0x00020064);
6289
6290 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6291
6292 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6293 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6294 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6295 put_smstate(u32, buf, 0x7e94, seg.limit);
6296 put_smstate(u64, buf, 0x7e98, seg.base);
6297
6298 kvm_x86_ops->get_idt(vcpu, &dt);
6299 put_smstate(u32, buf, 0x7e84, dt.size);
6300 put_smstate(u64, buf, 0x7e88, dt.address);
6301
6302 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6303 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6304 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6305 put_smstate(u32, buf, 0x7e74, seg.limit);
6306 put_smstate(u64, buf, 0x7e78, seg.base);
6307
6308 kvm_x86_ops->get_gdt(vcpu, &dt);
6309 put_smstate(u32, buf, 0x7e64, dt.size);
6310 put_smstate(u64, buf, 0x7e68, dt.address);
6311
6312 for (i = 0; i < 6; i++)
ee2cd4b7 6313 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6314#else
6315 WARN_ON_ONCE(1);
6316#endif
6317}
6318
ee2cd4b7 6319static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6320{
660a5d51 6321 struct kvm_segment cs, ds;
18c3626e 6322 struct desc_ptr dt;
660a5d51
PB		 6323 char buf[512];
6324 u32 cr0;
6325
660a5d51
PB		 6326 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6327 vcpu->arch.hflags |= HF_SMM_MASK;
6328 memset(buf, 0, 512);
6329 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6330 enter_smm_save_state_64(vcpu, buf);
660a5d51 6331 else
ee2cd4b7 6332 enter_smm_save_state_32(vcpu, buf);
660a5d51 6333
54bf36aa 6334 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6335
6336 if (kvm_x86_ops->get_nmi_mask(vcpu))
6337 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6338 else
6339 kvm_x86_ops->set_nmi_mask(vcpu, true);
6340
6341 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6342 kvm_rip_write(vcpu, 0x8000);
6343
6344 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6345 kvm_x86_ops->set_cr0(vcpu, cr0);
6346 vcpu->arch.cr0 = cr0;
6347
6348 kvm_x86_ops->set_cr4(vcpu, 0);
6349
18c3626e
PB		 6350 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6351 dt.address = dt.size = 0;
6352 kvm_x86_ops->set_idt(vcpu, &dt);
6353
660a5d51
PB		 6354 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6355
6356 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6357 cs.base = vcpu->arch.smbase;
6358
6359 ds.selector = 0;
6360 ds.base = 0;
6361
6362 cs.limit = ds.limit = 0xffffffff;
6363 cs.type = ds.type = 0x3;
6364 cs.dpl = ds.dpl = 0;
6365 cs.db = ds.db = 0;
6366 cs.s = ds.s = 1;
6367 cs.l = ds.l = 0;
6368 cs.g = ds.g = 1;
6369 cs.avl = ds.avl = 0;
6370 cs.present = ds.present = 1;
6371 cs.unusable = ds.unusable = 0;
6372 cs.padding = ds.padding = 0;
6373
6374 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6375 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6376 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6377 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6378 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6379 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6380
6381 if (guest_cpuid_has_longmode(vcpu))
6382 kvm_x86_ops->set_efer(vcpu, 0);
6383
6384 kvm_update_cpuid(vcpu);
6385 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6386}
6387
ee2cd4b7 6388static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6389{
6390 vcpu->arch.smi_pending = true;
6391 kvm_make_request(KVM_REQ_EVENT, vcpu);
6392}
6393
2860c4b1
PB		 6394void kvm_make_scan_ioapic_request(struct kvm *kvm)
6395{
6396 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6397}
6398
3d81bc7e 6399static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6400{
5c919412
AS		 6401 u64 eoi_exit_bitmap[4];
6402
3d81bc7e
YZ		 6403 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6404 return;
c7c9c56c 6405
6308630b 6406 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6407
b053b2ae 6408 if (irqchip_split(vcpu->kvm))
6308630b 6409 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6410 else {
d62caabb
AS		 6411 if (vcpu->arch.apicv_active)
6412 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6413 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6414 }
5c919412
AS		 6415 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6416 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6417 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6418}
6419
a70656b6
RK		 6420static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6421{
6422 ++vcpu->stat.tlb_flush;
6423 kvm_x86_ops->tlb_flush(vcpu);
6424}
6425
4256f43f
TC		 6426void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6427{
c24ae0dc
TC		 6428 struct page *page = NULL;
6429
35754c98 6430 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6431 return;
6432
4256f43f
TC		 6433 if (!kvm_x86_ops->set_apic_access_page_addr)
6434 return;
6435
c24ae0dc 6436 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6437 if (is_error_page(page))
6438 return;
c24ae0dc
TC		 6439 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6440
6441 /*
6442 * Do not pin apic access page in memory, the MMU notifier
6443 * will call us again if it is migrated or swapped out.
6444 */
6445 put_page(page);
4256f43f
TC		 6446}
6447EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6448
fe71557a
TC		 6449void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6450 unsigned long address)
6451{
c24ae0dc
TC		 6452 /*
6453 * The physical address of apic access page is stored in the VMCS.
6454 * Update it when it becomes invalid.
6455 */
6456 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6457 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6458}
6459
9357d939 6460/*
362c698f 6461 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6462 * exiting to the userspace. Otherwise, the value will be returned to the
6463 * userspace.
6464 */
851ba692 6465static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6466{
6467 int r;
62a193ed
MG		 6468 bool req_int_win =
6469 dm_request_for_irq_injection(vcpu) &&
6470 kvm_cpu_accept_dm_intr(vcpu);
6471
730dca42 6472 bool req_immediate_exit = false;
b6c7a5dc 6473
3e007509 6474 if (vcpu->requests) {
a8eeb04a 6475 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6476 kvm_mmu_unload(vcpu);
a8eeb04a 6477 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6478 __kvm_migrate_timers(vcpu);
d828199e
MT		 6479 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6480 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6481 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6482 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6483 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6484 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6485 if (unlikely(r))
6486 goto out;
6487 }
a8eeb04a 6488 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6489 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6490 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6491 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6492 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6493 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6494 r = 0;
6495 goto out;
6496 }
a8eeb04a 6497 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6498 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6499 r = 0;
6500 goto out;
6501 }
a8eeb04a 6502 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6503 vcpu->fpu_active = 0;
6504 kvm_x86_ops->fpu_deactivate(vcpu);
6505 }
af585b92
GN		 6506 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6507 /* Page is swapped out. Do synthetic halt */
6508 vcpu->arch.apf.halted = true;
6509 r = 1;
6510 goto out;
6511 }
c9aaa895
GC		 6512 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6513 record_steal_time(vcpu);
64d60670
PB		 6514 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6515 process_smi(vcpu);
7460fb4a
AK		 6516 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6517 process_nmi(vcpu);
f5132b01 6518 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6519 kvm_pmu_handle_event(vcpu);
f5132b01 6520 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6521 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6522 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6523 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6524 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6525 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6526 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6527 vcpu->run->eoi.vector =
6528 vcpu->arch.pending_ioapic_eoi;
6529 r = 0;
6530 goto out;
6531 }
6532 }
3d81bc7e
YZ		 6533 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6534 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6535 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6536 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6537 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6538 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6539 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6540 r = 0;
6541 goto out;
6542 }
e516cebb
AS		 6543 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6544 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6545 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6546 r = 0;
6547 goto out;
6548 }
db397571
AS		 6549 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6550 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6551 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6552 r = 0;
6553 goto out;
6554 }
f3b138c5
AS		 6555
6556 /*
6557 * KVM_REQ_HV_STIMER has to be processed after
6558 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6559 * depend on the guest clock being up-to-date
6560 */
1f4b34f8
AS		 6561 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6562 kvm_hv_process_stimers(vcpu);
2f52d58c 6563 }
b93463aa 6564
bf9f6ac8
FW		 6565 /*
6566 * KVM_REQ_EVENT is not set when posted interrupts are set by
6567 * VT-d hardware, so we have to update RVI unconditionally.
6568 */
6569 if (kvm_lapic_enabled(vcpu)) {
6570 /*
6571 * Update architecture specific hints for APIC
6572 * virtual interrupt delivery.
6573 */
d62caabb 6574 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6575 kvm_x86_ops->hwapic_irr_update(vcpu,
6576 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6577 }
b93463aa 6578
b463a6f7 6579 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6580 kvm_apic_accept_events(vcpu);
6581 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6582 r = 1;
6583 goto out;
6584 }
6585
b6b8a145
JK		 6586 if (inject_pending_event(vcpu, req_int_win) != 0)
6587 req_immediate_exit = true;
321c5658 6588 else {
c43203ca
PB		 6589 /* Enable NMI/IRQ window open exits if needed.
6590 *
6591 * SMIs have two cases: 1) they can be nested, and
6592 * then there is nothing to do here because RSM will
6593 * cause a vmexit anyway; 2) or the SMI can be pending
6594 * because inject_pending_event has completed the
6595 * injection of an IRQ or NMI from the previous vmexit,
6596 * and then we request an immediate exit to inject the SMI.
6597 */
6598 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6599 req_immediate_exit = true;
321c5658
YS		 6600 if (vcpu->arch.nmi_pending)
6601 kvm_x86_ops->enable_nmi_window(vcpu);
6602 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6603 kvm_x86_ops->enable_irq_window(vcpu);
6604 }
b463a6f7
AK		 6605
6606 if (kvm_lapic_enabled(vcpu)) {
6607 update_cr8_intercept(vcpu);
6608 kvm_lapic_sync_to_vapic(vcpu);
6609 }
6610 }
6611
d8368af8
AK		 6612 r = kvm_mmu_reload(vcpu);
6613 if (unlikely(r)) {
d905c069 6614 goto cancel_injection;
d8368af8
AK		 6615 }
6616
b6c7a5dc
HB		 6617 preempt_disable();
6618
6619 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6620 if (vcpu->fpu_active)
6621 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6622 vcpu->mode = IN_GUEST_MODE;
6623
01b71917
MT		 6624 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6625
0f127d12
LT		 6626 /*
6627 * We should set ->mode before check ->requests,
6628 * Please see the comment in kvm_make_all_cpus_request.
6629 * This also orders the write to mode from any reads
6630 * to the page tables done while the VCPU is running.
6631 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6632 */
01b71917 6633 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6634
d94e1dc9 6635 local_irq_disable();
32f88400 6636
6b7e2d09 6637 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6638 || need_resched() || signal_pending(current)) {
6b7e2d09 6639 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6640 smp_wmb();
6c142801
AK		 6641 local_irq_enable();
6642 preempt_enable();
01b71917 6643 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6644 r = 1;
d905c069 6645 goto cancel_injection;
6c142801
AK		 6646 }
6647
fc5b7f3b
DM		 6648 kvm_load_guest_xcr0(vcpu);
6649
c43203ca
PB		 6650 if (req_immediate_exit) {
6651 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6652 smp_send_reschedule(vcpu->cpu);
c43203ca 6653 }
d6185f20 6654
8b89fe1f
PB		 6655 trace_kvm_entry(vcpu->vcpu_id);
6656 wait_lapic_expire(vcpu);
6edaa530 6657 guest_enter_irqoff();
b6c7a5dc 6658
42dbaa5a 6659 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6660 set_debugreg(0, 7);
6661 set_debugreg(vcpu->arch.eff_db[0], 0);
6662 set_debugreg(vcpu->arch.eff_db[1], 1);
6663 set_debugreg(vcpu->arch.eff_db[2], 2);
6664 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6665 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6666 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6667 }
b6c7a5dc 6668
851ba692 6669 kvm_x86_ops->run(vcpu);
b6c7a5dc 6670
c77fb5fe
PB		 6671 /*
6672 * Do this here before restoring debug registers on the host. And
6673 * since we do this before handling the vmexit, a DR access vmexit
6674 * can (a) read the correct value of the debug registers, (b) set
6675 * KVM_DEBUGREG_WONT_EXIT again.
6676 */
6677 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6678 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6679 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6680 kvm_update_dr0123(vcpu);
6681 kvm_update_dr6(vcpu);
6682 kvm_update_dr7(vcpu);
6683 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6684 }
6685
24f1e32c
FW		 6686 /*
6687 * If the guest has used debug registers, at least dr7
6688 * will be disabled while returning to the host.
6689 * If we don't have active breakpoints in the host, we don't
6690 * care about the messed up debug address registers. But if
6691 * we have some of them active, restore the old state.
6692 */
59d8eb53 6693 if (hw_breakpoint_active())
24f1e32c 6694 hw_breakpoint_restore();
42dbaa5a 6695
4ba76538 6696 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6697
6b7e2d09 6698 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6699 smp_wmb();
a547c6db 6700
fc5b7f3b
DM		 6701 kvm_put_guest_xcr0(vcpu);
6702
a547c6db
YZ		 6703 /* Interrupt is enabled by handle_external_intr() */
6704 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6705
6706 ++vcpu->stat.exits;
6707
f2485b3e 6708 guest_exit_irqoff();
b6c7a5dc 6709
f2485b3e 6710 local_irq_enable();
b6c7a5dc
HB		 6711 preempt_enable();
6712
f656ce01 6713 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6714
b6c7a5dc
HB		 6715 /*
6716 * Profile KVM exit RIPs:
6717 */
6718 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6719 unsigned long rip = kvm_rip_read(vcpu);
6720 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6721 }
6722
cc578287
ZA		 6723 if (unlikely(vcpu->arch.tsc_always_catchup))
6724 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6725
5cfb1d5a
MT		 6726 if (vcpu->arch.apic_attention)
6727 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6728
851ba692 6729 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6730 return r;
6731
6732cancel_injection:
6733 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6734 if (unlikely(vcpu->arch.apic_attention))
6735 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6736out:
6737 return r;
6738}
b6c7a5dc 6739
362c698f
PB		 6740static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6741{
bf9f6ac8
FW		 6742 if (!kvm_arch_vcpu_runnable(vcpu) &&
6743 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6744 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6745 kvm_vcpu_block(vcpu);
6746 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6747
6748 if (kvm_x86_ops->post_block)
6749 kvm_x86_ops->post_block(vcpu);
6750
9c8fd1ba
PB		 6751 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6752 return 1;
6753 }
362c698f
PB		 6754
6755 kvm_apic_accept_events(vcpu);
6756 switch(vcpu->arch.mp_state) {
6757 case KVM_MP_STATE_HALTED:
6758 vcpu->arch.pv.pv_unhalted = false;
6759 vcpu->arch.mp_state =
6760 KVM_MP_STATE_RUNNABLE;
6761 case KVM_MP_STATE_RUNNABLE:
6762 vcpu->arch.apf.halted = false;
6763 break;
6764 case KVM_MP_STATE_INIT_RECEIVED:
6765 break;
6766 default:
6767 return -EINTR;
6768 break;
6769 }
6770 return 1;
6771}
09cec754 6772
5d9bc648
PB		 6773static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6774{
6775 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6776 !vcpu->arch.apf.halted);
6777}
6778
362c698f 6779static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6780{
6781 int r;
f656ce01 6782 struct kvm *kvm = vcpu->kvm;
d7690175 6783
f656ce01 6784 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6785
362c698f 6786 for (;;) {
58f800d5 6787 if (kvm_vcpu_running(vcpu)) {
851ba692 6788 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6789 } else {
362c698f 6790 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6791 }
6792
09cec754
GN		 6793 if (r <= 0)
6794 break;
6795
6796 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6797 if (kvm_cpu_has_pending_timer(vcpu))
6798 kvm_inject_pending_timer_irqs(vcpu);
6799
782d422b
MG		 6800 if (dm_request_for_irq_injection(vcpu) &&
6801 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6802 r = 0;
6803 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6804 ++vcpu->stat.request_irq_exits;
362c698f 6805 break;
09cec754 6806 }
af585b92
GN		 6807
6808 kvm_check_async_pf_completion(vcpu);
6809
09cec754
GN		 6810 if (signal_pending(current)) {
6811 r = -EINTR;
851ba692 6812 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6813 ++vcpu->stat.signal_exits;
362c698f 6814 break;
09cec754
GN		 6815 }
6816 if (need_resched()) {
f656ce01 6817 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6818 cond_resched();
f656ce01 6819 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6820 }
b6c7a5dc
HB		 6821 }
6822
f656ce01 6823 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6824
6825 return r;
6826}
6827
716d51ab
GN		 6828static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6829{
6830 int r;
6831 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6832 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6833 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6834 if (r != EMULATE_DONE)
6835 return 0;
6836 return 1;
6837}
6838
6839static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6840{
6841 BUG_ON(!vcpu->arch.pio.count);
6842
6843 return complete_emulated_io(vcpu);
6844}
6845
f78146b0
AK		 6846/*
6847 * Implements the following, as a state machine:
6848 *
6849 * read:
6850 * for each fragment
87da7e66
XG		 6851 * for each mmio piece in the fragment
6852 * write gpa, len
6853 * exit
6854 * copy data
f78146b0
AK		 6855 * execute insn
6856 *
6857 * write:
6858 * for each fragment
87da7e66
XG		 6859 * for each mmio piece in the fragment
6860 * write gpa, len
6861 * copy data
6862 * exit
f78146b0 6863 */
716d51ab 6864static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6865{
6866 struct kvm_run *run = vcpu->run;
f78146b0 6867 struct kvm_mmio_fragment *frag;
87da7e66 6868 unsigned len;
5287f194 6869
716d51ab 6870 BUG_ON(!vcpu->mmio_needed);
5287f194 6871
716d51ab 6872 /* Complete previous fragment */
87da7e66
XG		 6873 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6874 len = min(8u, frag->len);
716d51ab 6875 if (!vcpu->mmio_is_write)
87da7e66
XG		 6876 memcpy(frag->data, run->mmio.data, len);
6877
6878 if (frag->len <= 8) {
6879 /* Switch to the next fragment. */
6880 frag++;
6881 vcpu->mmio_cur_fragment++;
6882 } else {
6883 /* Go forward to the next mmio piece. */
6884 frag->data += len;
6885 frag->gpa += len;
6886 frag->len -= len;
6887 }
6888
a08d3b3b 6889 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6890 vcpu->mmio_needed = 0;
0912c977
PB		 6891
6892 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6893 if (vcpu->mmio_is_write)
716d51ab
GN		 6894 return 1;
6895 vcpu->mmio_read_completed = 1;
6896 return complete_emulated_io(vcpu);
6897 }
87da7e66 6898
716d51ab
GN		 6899 run->exit_reason = KVM_EXIT_MMIO;
6900 run->mmio.phys_addr = frag->gpa;
6901 if (vcpu->mmio_is_write)
87da7e66
XG		 6902 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6903 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6904 run->mmio.is_write = vcpu->mmio_is_write;
6905 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6906 return 0;
5287f194
AK		 6907}
6908
716d51ab 6909
b6c7a5dc
HB		 6910int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6911{
c5bedc68 6912 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6913 int r;
6914 sigset_t sigsaved;
6915
c4d72e2d 6916 fpu__activate_curr(fpu);
e5c30142 6917
ac9f6dc0
AK		 6918 if (vcpu->sigset_active)
6919 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6920
a4535290 6921 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6922 kvm_vcpu_block(vcpu);
66450a21 6923 kvm_apic_accept_events(vcpu);
d7690175 6924 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6925 r = -EAGAIN;
6926 goto out;
b6c7a5dc
HB		 6927 }
6928
b6c7a5dc 6929 /* re-sync apic's tpr */
35754c98 6930 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6931 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6932 r = -EINVAL;
6933 goto out;
6934 }
6935 }
b6c7a5dc 6936
716d51ab
GN		 6937 if (unlikely(vcpu->arch.complete_userspace_io)) {
6938 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6939 vcpu->arch.complete_userspace_io = NULL;
6940 r = cui(vcpu);
6941 if (r <= 0)
6942 goto out;
6943 } else
6944 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6945
362c698f 6946 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6947
6948out:
f1d86e46 6949 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6950 if (vcpu->sigset_active)
6951 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6952
b6c7a5dc
HB		 6953 return r;
6954}
6955
6956int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6957{
7ae441ea
GN		 6958 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6959 /*
6960 * We are here if userspace calls get_regs() in the middle of
6961 * instruction emulation. Registers state needs to be copied
4a969980 6962 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6963 * that usually, but some bad designed PV devices (vmware
6964 * backdoor interface) need this to work
6965 */
dd856efa 6966 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6967 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6968 }
5fdbf976
MT		 6969 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6970 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6971 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6972 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6973 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6974 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6975 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6976 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6977#ifdef CONFIG_X86_64
5fdbf976
MT		 6978 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6979 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6980 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6981 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6982 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6983 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6984 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6985 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6986#endif
6987
5fdbf976 6988 regs->rip = kvm_rip_read(vcpu);
91586a3b 6989 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6990
b6c7a5dc
HB		 6991 return 0;
6992}
6993
6994int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6995{
7ae441ea
GN		 6996 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6997 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6998
5fdbf976
MT		 6999 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7000 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7001 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7002 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7003 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7004 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7005 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7006 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7007#ifdef CONFIG_X86_64
5fdbf976
MT		 7008 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7009 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7010 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7011 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7012 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7013 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7014 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7015 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7016#endif
7017
5fdbf976 7018 kvm_rip_write(vcpu, regs->rip);
91586a3b 7019 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7020
b4f14abd
JK		 7021 vcpu->arch.exception.pending = false;
7022
3842d135
AK		 7023 kvm_make_request(KVM_REQ_EVENT, vcpu);
7024
b6c7a5dc
HB		 7025 return 0;
7026}
7027
b6c7a5dc
HB		 7028void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7029{
7030 struct kvm_segment cs;
7031
3e6e0aab 7032 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7033 *db = cs.db;
7034 *l = cs.l;
7035}
7036EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7037
7038int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7039 struct kvm_sregs *sregs)
7040{
89a27f4d 7041 struct desc_ptr dt;
b6c7a5dc 7042
3e6e0aab
GT		 7043 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7044 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7045 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7046 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7047 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7048 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7049
3e6e0aab
GT		 7050 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7051 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7052
7053 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7054 sregs->idt.limit = dt.size;
7055 sregs->idt.base = dt.address;
b6c7a5dc 7056 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7057 sregs->gdt.limit = dt.size;
7058 sregs->gdt.base = dt.address;
b6c7a5dc 7059
4d4ec087 7060 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7061 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7062 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7063 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7064 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7065 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7066 sregs->apic_base = kvm_get_apic_base(vcpu);
7067
923c61bb 7068 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7069
36752c9b 7070 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7071 set_bit(vcpu->arch.interrupt.nr,
7072 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7073
b6c7a5dc
HB		 7074 return 0;
7075}
7076
62d9f0db
MT		 7077int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7078 struct kvm_mp_state *mp_state)
7079{
66450a21 7080 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7081 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7082 vcpu->arch.pv.pv_unhalted)
7083 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7084 else
7085 mp_state->mp_state = vcpu->arch.mp_state;
7086
62d9f0db
MT		 7087 return 0;
7088}
7089
7090int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7091 struct kvm_mp_state *mp_state)
7092{
bce87cce 7093 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7094 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7095 return -EINVAL;
7096
7097 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7098 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7099 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7100 } else
7101 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7102 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7103 return 0;
7104}
7105
7f3d35fd
KW		 7106int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7107 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7108{
9d74191a 7109 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7110 int ret;
e01c2426 7111
8ec4722d 7112 init_emulate_ctxt(vcpu);
c697518a 7113
7f3d35fd 7114 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7115 has_error_code, error_code);
c697518a 7116
c697518a 7117 if (ret)
19d04437 7118 return EMULATE_FAIL;
37817f29 7119
9d74191a
TY		 7120 kvm_rip_write(vcpu, ctxt->eip);
7121 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7122 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7123 return EMULATE_DONE;
37817f29
IE		 7124}
7125EXPORT_SYMBOL_GPL(kvm_task_switch);
7126
b6c7a5dc
HB		 7127int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7128 struct kvm_sregs *sregs)
7129{
58cb628d 7130 struct msr_data apic_base_msr;
b6c7a5dc 7131 int mmu_reset_needed = 0;
63f42e02 7132 int pending_vec, max_bits, idx;
89a27f4d 7133 struct desc_ptr dt;
b6c7a5dc 7134
6d1068b3
PM		 7135 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7136 return -EINVAL;
7137
89a27f4d
GN		 7138 dt.size = sregs->idt.limit;
7139 dt.address = sregs->idt.base;
b6c7a5dc 7140 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7141 dt.size = sregs->gdt.limit;
7142 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7143 kvm_x86_ops->set_gdt(vcpu, &dt);
7144
ad312c7c 7145 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7146 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7147 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7148 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7149
2d3ad1f4 7150 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7151
f6801dff 7152 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7153 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7154 apic_base_msr.data = sregs->apic_base;
7155 apic_base_msr.host_initiated = true;
7156 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7157
4d4ec087 7158 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7159 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7160 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7161
fc78f519 7162 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7163 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7164 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7165 kvm_update_cpuid(vcpu);
63f42e02
XG		 7166
7167 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7168 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7169 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7170 mmu_reset_needed = 1;
7171 }
63f42e02 7172 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7173
7174 if (mmu_reset_needed)
7175 kvm_mmu_reset_context(vcpu);
7176
a50abc3b 7177 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7178 pending_vec = find_first_bit(
7179 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7180 if (pending_vec < max_bits) {
66fd3f7f 7181 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7182 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7183 }
7184
3e6e0aab
GT		 7185 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7186 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7187 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7188 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7189 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7190 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7191
3e6e0aab
GT		 7192 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7193 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7194
5f0269f5
ME		 7195 update_cr8_intercept(vcpu);
7196
9c3e4aab 7197 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7198 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7199 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7200 !is_protmode(vcpu))
9c3e4aab
MT		 7201 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7202
3842d135
AK		 7203 kvm_make_request(KVM_REQ_EVENT, vcpu);
7204
b6c7a5dc
HB		 7205 return 0;
7206}
7207
d0bfb940
JK		 7208int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7209 struct kvm_guest_debug *dbg)
b6c7a5dc 7210{
355be0b9 7211 unsigned long rflags;
ae675ef0 7212 int i, r;
b6c7a5dc 7213
4f926bf2
JK		 7214 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7215 r = -EBUSY;
7216 if (vcpu->arch.exception.pending)
2122ff5e 7217 goto out;
4f926bf2
JK		 7218 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7219 kvm_queue_exception(vcpu, DB_VECTOR);
7220 else
7221 kvm_queue_exception(vcpu, BP_VECTOR);
7222 }
7223
91586a3b
JK		 7224 /*
7225 * Read rflags as long as potentially injected trace flags are still
7226 * filtered out.
7227 */
7228 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7229
7230 vcpu->guest_debug = dbg->control;
7231 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7232 vcpu->guest_debug = 0;
7233
7234 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7235 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7236 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7237 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7238 } else {
7239 for (i = 0; i < KVM_NR_DB_REGS; i++)
7240 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7241 }
c8639010 7242 kvm_update_dr7(vcpu);
ae675ef0 7243
f92653ee
JK		 7244 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7245 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7246 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7247
91586a3b
JK		 7248 /*
7249 * Trigger an rflags update that will inject or remove the trace
7250 * flags.
7251 */
7252 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7253
a96036b8 7254 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7255
4f926bf2 7256 r = 0;
d0bfb940 7257
2122ff5e 7258out:
b6c7a5dc
HB		 7259
7260 return r;
7261}
7262
8b006791
ZX		 7263/*
7264 * Translate a guest virtual address to a guest physical address.
7265 */
7266int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7267 struct kvm_translation *tr)
7268{
7269 unsigned long vaddr = tr->linear_address;
7270 gpa_t gpa;
f656ce01 7271 int idx;
8b006791 7272
f656ce01 7273 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7274 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7275 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7276 tr->physical_address = gpa;
7277 tr->valid = gpa != UNMAPPED_GVA;
7278 tr->writeable = 1;
7279 tr->usermode = 0;
8b006791
ZX		 7280
7281 return 0;
7282}
7283
d0752060
HB		 7284int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7285{
c47ada30 7286 struct fxregs_state *fxsave =
7366ed77 7287 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7288
d0752060
HB		 7289 memcpy(fpu->fpr, fxsave->st_space, 128);
7290 fpu->fcw = fxsave->cwd;
7291 fpu->fsw = fxsave->swd;
7292 fpu->ftwx = fxsave->twd;
7293 fpu->last_opcode = fxsave->fop;
7294 fpu->last_ip = fxsave->rip;
7295 fpu->last_dp = fxsave->rdp;
7296 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7297
d0752060
HB		 7298 return 0;
7299}
7300
7301int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7302{
c47ada30 7303 struct fxregs_state *fxsave =
7366ed77 7304 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7305
d0752060
HB		 7306 memcpy(fxsave->st_space, fpu->fpr, 128);
7307 fxsave->cwd = fpu->fcw;
7308 fxsave->swd = fpu->fsw;
7309 fxsave->twd = fpu->ftwx;
7310 fxsave->fop = fpu->last_opcode;
7311 fxsave->rip = fpu->last_ip;
7312 fxsave->rdp = fpu->last_dp;
7313 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7314
d0752060
HB		 7315 return 0;
7316}
7317
0ee6a517 7318static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7319{
bf935b0b 7320 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7321 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7322 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7323 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7324
2acf923e
DC		 7325 /*
7326 * Ensure guest xcr0 is valid for loading
7327 */
d91cab78 7328 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7329
ad312c7c 7330 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7331}
d0752060
HB		 7332
7333void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7334{
2608d7a1 7335 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7336 return;
7337
2acf923e
DC		 7338 /*
7339 * Restore all possible states in the guest,
7340 * and assume host would use all available bits.
7341 * Guest xcr0 would be loaded later.
7342 */
d0752060 7343 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7344 __kernel_fpu_begin();
003e2e8b 7345 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7346 trace_kvm_fpu(1);
d0752060 7347}
d0752060
HB		 7348
7349void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7350{
653f52c3
RR		 7351 if (!vcpu->guest_fpu_loaded) {
7352 vcpu->fpu_counter = 0;
d0752060 7353 return;
653f52c3 7354 }
d0752060
HB		 7355
7356 vcpu->guest_fpu_loaded = 0;
4f836347 7357 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7358 __kernel_fpu_end();
f096ed85 7359 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7360 /*
7361 * If using eager FPU mode, or if the guest is a frequent user
7362 * of the FPU, just leave the FPU active for next time.
7363 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7364 * the FPU in bursts will revert to loading it on demand.
7365 */
5a5fbdc0 7366 if (!use_eager_fpu()) {
653f52c3
RR		 7367 if (++vcpu->fpu_counter < 5)
7368 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7369 }
0c04851c 7370 trace_kvm_fpu(0);
d0752060 7371}
e9b11c17
ZX		 7372
7373void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7374{
12f9a48f 7375 kvmclock_reset(vcpu);
7f1ea208 7376
f5f48ee1 7377 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7378 kvm_x86_ops->vcpu_free(vcpu);
7379}
7380
7381struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7382 unsigned int id)
7383{
c447e76b
LL		 7384 struct kvm_vcpu *vcpu;
7385
6755bae8
ZA		 7386 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7387 printk_once(KERN_WARNING
7388 "kvm: SMP vm created on host with unstable TSC; "
7389 "guest TSC will not be reliable\n");
c447e76b
LL		 7390
7391 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7392
c447e76b 7393 return vcpu;
26e5215f 7394}
e9b11c17 7395
26e5215f
AK		 7396int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7397{
7398 int r;
e9b11c17 7399
19efffa2 7400 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7401 r = vcpu_load(vcpu);
7402 if (r)
7403 return r;
d28bc9dd 7404 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7405 kvm_mmu_setup(vcpu);
e9b11c17 7406 vcpu_put(vcpu);
26e5215f 7407 return r;
e9b11c17
ZX		 7408}
7409
31928aa5 7410void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7411{
8fe8ab46 7412 struct msr_data msr;
332967a3 7413 struct kvm *kvm = vcpu->kvm;
42897d86 7414
31928aa5
DD		 7415 if (vcpu_load(vcpu))
7416 return;
8fe8ab46
WA		 7417 msr.data = 0x0;
7418 msr.index = MSR_IA32_TSC;
7419 msr.host_initiated = true;
7420 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7421 vcpu_put(vcpu);
7422
630994b3
MT		 7423 if (!kvmclock_periodic_sync)
7424 return;
7425
332967a3
AJ		 7426 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7427 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7428}
7429
d40ccc62 7430void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7431{
9fc77441 7432 int r;
344d9588
GN		 7433 vcpu->arch.apf.msr_val = 0;
7434
9fc77441
MT		 7435 r = vcpu_load(vcpu);
7436 BUG_ON(r);
e9b11c17
ZX		 7437 kvm_mmu_unload(vcpu);
7438 vcpu_put(vcpu);
7439
7440 kvm_x86_ops->vcpu_free(vcpu);
7441}
7442
d28bc9dd 7443void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7444{
e69fab5d
PB		 7445 vcpu->arch.hflags = 0;
7446
c43203ca 7447 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7448 atomic_set(&vcpu->arch.nmi_queued, 0);
7449 vcpu->arch.nmi_pending = 0;
448fa4a9 7450 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7451 kvm_clear_interrupt_queue(vcpu);
7452 kvm_clear_exception_queue(vcpu);
448fa4a9 7453
42dbaa5a 7454 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7455 kvm_update_dr0123(vcpu);
6f43ed01 7456 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7457 kvm_update_dr6(vcpu);
42dbaa5a 7458 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7459 kvm_update_dr7(vcpu);
42dbaa5a 7460
1119022c
NA		 7461 vcpu->arch.cr2 = 0;
7462
3842d135 7463 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7464 vcpu->arch.apf.msr_val = 0;
c9aaa895 7465 vcpu->arch.st.msr_val = 0;
3842d135 7466
12f9a48f
GC		 7467 kvmclock_reset(vcpu);
7468
af585b92
GN		 7469 kvm_clear_async_pf_completion_queue(vcpu);
7470 kvm_async_pf_hash_reset(vcpu);
7471 vcpu->arch.apf.halted = false;
3842d135 7472
64d60670 7473 if (!init_event) {
d28bc9dd 7474 kvm_pmu_reset(vcpu);
64d60670
PB		 7475 vcpu->arch.smbase = 0x30000;
7476 }
f5132b01 7477
66f7b72e
JS		 7478 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7479 vcpu->arch.regs_avail = ~0;
7480 vcpu->arch.regs_dirty = ~0;
7481
d28bc9dd 7482 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7483}
7484
2b4a273b 7485void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7486{
7487 struct kvm_segment cs;
7488
7489 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7490 cs.selector = vector << 8;
7491 cs.base = vector << 12;
7492 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7493 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7494}
7495
13a34e06 7496int kvm_arch_hardware_enable(void)
e9b11c17 7497{
ca84d1a2
ZA		 7498 struct kvm *kvm;
7499 struct kvm_vcpu *vcpu;
7500 int i;
0dd6a6ed
ZA		 7501 int ret;
7502 u64 local_tsc;
7503 u64 max_tsc = 0;
7504 bool stable, backwards_tsc = false;
18863bdd
AK		 7505
7506 kvm_shared_msr_cpu_online();
13a34e06 7507 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7508 if (ret != 0)
7509 return ret;
7510
4ea1636b 7511 local_tsc = rdtsc();
0dd6a6ed
ZA		 7512 stable = !check_tsc_unstable();
7513 list_for_each_entry(kvm, &vm_list, vm_list) {
7514 kvm_for_each_vcpu(i, vcpu, kvm) {
7515 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7516 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7517 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7518 backwards_tsc = true;
7519 if (vcpu->arch.last_host_tsc > max_tsc)
7520 max_tsc = vcpu->arch.last_host_tsc;
7521 }
7522 }
7523 }
7524
7525 /*
7526 * Sometimes, even reliable TSCs go backwards. This happens on
7527 * platforms that reset TSC during suspend or hibernate actions, but
7528 * maintain synchronization. We must compensate. Fortunately, we can
7529 * detect that condition here, which happens early in CPU bringup,
7530 * before any KVM threads can be running. Unfortunately, we can't
7531 * bring the TSCs fully up to date with real time, as we aren't yet far
7532 * enough into CPU bringup that we know how much real time has actually
7533 * elapsed; our helper function, get_kernel_ns() will be using boot
7534 * variables that haven't been updated yet.
7535 *
7536 * So we simply find the maximum observed TSC above, then record the
7537 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7538 * the adjustment will be applied. Note that we accumulate
7539 * adjustments, in case multiple suspend cycles happen before some VCPU
7540 * gets a chance to run again. In the event that no KVM threads get a
7541 * chance to run, we will miss the entire elapsed period, as we'll have
7542 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7543 * loose cycle time. This isn't too big a deal, since the loss will be
7544 * uniform across all VCPUs (not to mention the scenario is extremely
7545 * unlikely). It is possible that a second hibernate recovery happens
7546 * much faster than a first, causing the observed TSC here to be
7547 * smaller; this would require additional padding adjustment, which is
7548 * why we set last_host_tsc to the local tsc observed here.
7549 *
7550 * N.B. - this code below runs only on platforms with reliable TSC,
7551 * as that is the only way backwards_tsc is set above. Also note
7552 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7553 * have the same delta_cyc adjustment applied if backwards_tsc
7554 * is detected. Note further, this adjustment is only done once,
7555 * as we reset last_host_tsc on all VCPUs to stop this from being
7556 * called multiple times (one for each physical CPU bringup).
7557 *
4a969980 7558 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7559 * will be compensated by the logic in vcpu_load, which sets the TSC to
7560 * catchup mode. This will catchup all VCPUs to real time, but cannot
7561 * guarantee that they stay in perfect synchronization.
7562 */
7563 if (backwards_tsc) {
7564 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7565 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7566 list_for_each_entry(kvm, &vm_list, vm_list) {
7567 kvm_for_each_vcpu(i, vcpu, kvm) {
7568 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7569 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7570 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7571 }
7572
7573 /*
7574 * We have to disable TSC offset matching.. if you were
7575 * booting a VM while issuing an S4 host suspend....
7576 * you may have some problem. Solving this issue is
7577 * left as an exercise to the reader.
7578 */
7579 kvm->arch.last_tsc_nsec = 0;
7580 kvm->arch.last_tsc_write = 0;
7581 }
7582
7583 }
7584 return 0;
e9b11c17
ZX		 7585}
7586
13a34e06 7587void kvm_arch_hardware_disable(void)
e9b11c17 7588{
13a34e06
RK		 7589 kvm_x86_ops->hardware_disable();
7590 drop_user_return_notifiers();
e9b11c17
ZX		 7591}
7592
7593int kvm_arch_hardware_setup(void)
7594{
9e9c3fe4
NA		 7595 int r;
7596
7597 r = kvm_x86_ops->hardware_setup();
7598 if (r != 0)
7599 return r;
7600
35181e86
HZ		 7601 if (kvm_has_tsc_control) {
7602 /*
7603 * Make sure the user can only configure tsc_khz values that
7604 * fit into a signed integer.
7605 * A min value is not calculated needed because it will always
7606 * be 1 on all machines.
7607 */
7608 u64 max = min(0x7fffffffULL,
7609 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7610 kvm_max_guest_tsc_khz = max;
7611
ad721883 7612 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7613 }
ad721883 7614
9e9c3fe4
NA		 7615 kvm_init_msr_list();
7616 return 0;
e9b11c17
ZX		 7617}
7618
7619void kvm_arch_hardware_unsetup(void)
7620{
7621 kvm_x86_ops->hardware_unsetup();
7622}
7623
7624void kvm_arch_check_processor_compat(void *rtn)
7625{
7626 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7627}
7628
7629bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7630{
7631 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7632}
7633EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7634
7635bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7636{
7637 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7638}
7639
54e9818f 7640struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7641EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7642
e9b11c17
ZX		 7643int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7644{
7645 struct page *page;
7646 struct kvm *kvm;
7647 int r;
7648
7649 BUG_ON(vcpu->kvm == NULL);
7650 kvm = vcpu->kvm;
7651
d62caabb 7652 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7653 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7654 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7655 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7656 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7657 else
a4535290 7658 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7659
7660 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7661 if (!page) {
7662 r = -ENOMEM;
7663 goto fail;
7664 }
ad312c7c 7665 vcpu->arch.pio_data = page_address(page);
e9b11c17 7666
cc578287 7667 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7668
e9b11c17
ZX		 7669 r = kvm_mmu_create(vcpu);
7670 if (r < 0)
7671 goto fail_free_pio_data;
7672
7673 if (irqchip_in_kernel(kvm)) {
7674 r = kvm_create_lapic(vcpu);
7675 if (r < 0)
7676 goto fail_mmu_destroy;
54e9818f
GN		 7677 } else
7678 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7679
890ca9ae
HY		 7680 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7681 GFP_KERNEL);
7682 if (!vcpu->arch.mce_banks) {
7683 r = -ENOMEM;
443c39bc 7684 goto fail_free_lapic;
890ca9ae
HY		 7685 }
7686 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7687
f1797359
WY		 7688 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7689 r = -ENOMEM;
f5f48ee1 7690 goto fail_free_mce_banks;
f1797359 7691 }
f5f48ee1 7692
0ee6a517 7693 fx_init(vcpu);
66f7b72e 7694
ba904635 7695 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7696 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7697
7698 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7699 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7700
5a4f55cd
EK		 7701 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7702
74545705
RK		 7703 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7704
af585b92 7705 kvm_async_pf_hash_reset(vcpu);
f5132b01 7706 kvm_pmu_init(vcpu);
af585b92 7707
1c1a9ce9
SR		 7708 vcpu->arch.pending_external_vector = -1;
7709
5c919412
AS		 7710 kvm_hv_vcpu_init(vcpu);
7711
e9b11c17 7712 return 0;
0ee6a517 7713
f5f48ee1
SY		 7714fail_free_mce_banks:
7715 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7716fail_free_lapic:
7717 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7718fail_mmu_destroy:
7719 kvm_mmu_destroy(vcpu);
7720fail_free_pio_data:
ad312c7c 7721 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7722fail:
7723 return r;
7724}
7725
7726void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7727{
f656ce01
MT		 7728 int idx;
7729
1f4b34f8 7730 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7731 kvm_pmu_destroy(vcpu);
36cb93fd 7732 kfree(vcpu->arch.mce_banks);
e9b11c17 7733 kvm_free_lapic(vcpu);
f656ce01 7734 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7735 kvm_mmu_destroy(vcpu);
f656ce01 7736 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7737 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7738 if (!lapic_in_kernel(vcpu))
54e9818f 7739 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7740}
d19a9cd2 7741
e790d9ef
RK		 7742void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7743{
ae97a3b8 7744 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7745}
7746
e08b9637 7747int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7748{
e08b9637
CO		 7749 if (type)
7750 return -EINVAL;
7751
6ef768fa 7752 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7753 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7754 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7755 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7756 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7757
5550af4d
SY		 7758 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7759 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7760 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7761 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7762 &kvm->arch.irq_sources_bitmap);
5550af4d 7763
038f8c11 7764 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7765 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7766 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7767
7768 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7769
7e44e449 7770 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7771 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7772
0eb05bf2 7773 kvm_page_track_init(kvm);
13d268ca 7774 kvm_mmu_init_vm(kvm);
0eb05bf2 7775
03543133
SS		 7776 if (kvm_x86_ops->vm_init)
7777 return kvm_x86_ops->vm_init(kvm);
7778
d89f5eff 7779 return 0;
d19a9cd2
ZX		 7780}
7781
7782static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7783{
9fc77441
MT		 7784 int r;
7785 r = vcpu_load(vcpu);
7786 BUG_ON(r);
d19a9cd2
ZX		 7787 kvm_mmu_unload(vcpu);
7788 vcpu_put(vcpu);
7789}
7790
7791static void kvm_free_vcpus(struct kvm *kvm)
7792{
7793 unsigned int i;
988a2cae 7794 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7795
7796 /*
7797 * Unpin any mmu pages first.
7798 */
af585b92
GN		 7799 kvm_for_each_vcpu(i, vcpu, kvm) {
7800 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7801 kvm_unload_vcpu_mmu(vcpu);
af585b92 7802 }
988a2cae
GN		 7803 kvm_for_each_vcpu(i, vcpu, kvm)
7804 kvm_arch_vcpu_free(vcpu);
7805
7806 mutex_lock(&kvm->lock);
7807 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7808 kvm->vcpus[i] = NULL;
d19a9cd2 7809
988a2cae
GN		 7810 atomic_set(&kvm->online_vcpus, 0);
7811 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7812}
7813
ad8ba2cd
SY		 7814void kvm_arch_sync_events(struct kvm *kvm)
7815{
332967a3 7816 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7817 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7818 kvm_free_all_assigned_devices(kvm);
aea924f6 7819 kvm_free_pit(kvm);
ad8ba2cd
SY		 7820}
7821
1d8007bd 7822int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7823{
7824 int i, r;
25188b99 7825 unsigned long hva;
f0d648bd
PB		 7826 struct kvm_memslots *slots = kvm_memslots(kvm);
7827 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7828
7829 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7830 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7831 return -EINVAL;
9da0e4d5 7832
f0d648bd
PB		 7833 slot = id_to_memslot(slots, id);
7834 if (size) {
b21629da 7835 if (slot->npages)
f0d648bd
PB		 7836 return -EEXIST;
7837
7838 /*
7839 * MAP_SHARED to prevent internal slot pages from being moved
7840 * by fork()/COW.
7841 */
7842 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7843 MAP_SHARED | MAP_ANONYMOUS, 0);
7844 if (IS_ERR((void *)hva))
7845 return PTR_ERR((void *)hva);
7846 } else {
7847 if (!slot->npages)
7848 return 0;
7849
7850 hva = 0;
7851 }
7852
7853 old = *slot;
9da0e4d5 7854 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7855 struct kvm_userspace_memory_region m;
9da0e4d5 7856
1d8007bd
PB		 7857 m.slot = id | (i << 16);
7858 m.flags = 0;
7859 m.guest_phys_addr = gpa;
f0d648bd 7860 m.userspace_addr = hva;
1d8007bd 7861 m.memory_size = size;
9da0e4d5
PB		 7862 r = __kvm_set_memory_region(kvm, &m);
7863 if (r < 0)
7864 return r;
7865 }
7866
f0d648bd
PB		 7867 if (!size) {
7868 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7869 WARN_ON(r < 0);
7870 }
7871
9da0e4d5
PB		 7872 return 0;
7873}
7874EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7875
1d8007bd 7876int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7877{
7878 int r;
7879
7880 mutex_lock(&kvm->slots_lock);
1d8007bd 7881 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7882 mutex_unlock(&kvm->slots_lock);
7883
7884 return r;
7885}
7886EXPORT_SYMBOL_GPL(x86_set_memory_region);
7887
d19a9cd2
ZX		 7888void kvm_arch_destroy_vm(struct kvm *kvm)
7889{
27469d29
AH		 7890 if (current->mm == kvm->mm) {
7891 /*
7892 * Free memory regions allocated on behalf of userspace,
7893 * unless the the memory map has changed due to process exit
7894 * or fd copying.
7895 */
1d8007bd
PB		 7896 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7897 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7898 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7899 }
03543133
SS		 7900 if (kvm_x86_ops->vm_destroy)
7901 kvm_x86_ops->vm_destroy(kvm);
6eb55818 7902 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7903 kfree(kvm->arch.vpic);
7904 kfree(kvm->arch.vioapic);
d19a9cd2 7905 kvm_free_vcpus(kvm);
af1bae54 7906 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7907 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7908}
0de10343 7909
5587027c 7910void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7911 struct kvm_memory_slot *dont)
7912{
7913 int i;
7914
d89cc617
TY		 7915 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7916 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7917 kvfree(free->arch.rmap[i]);
d89cc617 7918 free->arch.rmap[i] = NULL;
77d11309 7919 }
d89cc617
TY		 7920 if (i == 0)
7921 continue;
7922
7923 if (!dont || free->arch.lpage_info[i - 1] !=
7924 dont->arch.lpage_info[i - 1]) {
548ef284 7925 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7926 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7927 }
7928 }
21ebbeda
XG		 7929
7930 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7931}
7932
5587027c
AK		 7933int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7934 unsigned long npages)
db3fe4eb
TY		 7935{
7936 int i;
7937
d89cc617 7938 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7939 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7940 unsigned long ugfn;
7941 int lpages;
d89cc617 7942 int level = i + 1;
db3fe4eb
TY		 7943
7944 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7945 slot->base_gfn, level) + 1;
7946
d89cc617
TY		 7947 slot->arch.rmap[i] =
7948 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7949 if (!slot->arch.rmap[i])
77d11309 7950 goto out_free;
d89cc617
TY		 7951 if (i == 0)
7952 continue;
77d11309 7953
92f94f1e
XG		 7954 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7955 if (!linfo)
db3fe4eb
TY		 7956 goto out_free;
7957
92f94f1e
XG		 7958 slot->arch.lpage_info[i - 1] = linfo;
7959
db3fe4eb 7960 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7961 linfo[0].disallow_lpage = 1;
db3fe4eb 7962 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7963 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7964 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7965 /*
7966 * If the gfn and userspace address are not aligned wrt each
7967 * other, or if explicitly asked to, disable large page
7968 * support for this slot
7969 */
7970 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7971 !kvm_largepages_enabled()) {
7972 unsigned long j;
7973
7974 for (j = 0; j < lpages; ++j)
92f94f1e 7975 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7976 }
7977 }
7978
21ebbeda
XG		 7979 if (kvm_page_track_create_memslot(slot, npages))
7980 goto out_free;
7981
db3fe4eb
TY		 7982 return 0;
7983
7984out_free:
d89cc617 7985 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7986 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7987 slot->arch.rmap[i] = NULL;
7988 if (i == 0)
7989 continue;
7990
548ef284 7991 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7992 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7993 }
7994 return -ENOMEM;
7995}
7996
15f46015 7997void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7998{
e6dff7d1
TY		 7999 /*
8000 * memslots->generation has been incremented.
8001 * mmio generation may have reached its maximum value.
8002 */
54bf36aa 8003 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8004}
8005
f7784b8e
MT		 8006int kvm_arch_prepare_memory_region(struct kvm *kvm,
8007 struct kvm_memory_slot *memslot,
09170a49 8008 const struct kvm_userspace_memory_region *mem,
7b6195a9 8009 enum kvm_mr_change change)
0de10343 8010{
f7784b8e
MT		 8011 return 0;
8012}
8013
88178fd4
KH		 8014static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8015 struct kvm_memory_slot *new)
8016{
8017 /* Still write protect RO slot */
8018 if (new->flags & KVM_MEM_READONLY) {
8019 kvm_mmu_slot_remove_write_access(kvm, new);
8020 return;
8021 }
8022
8023 /*
8024 * Call kvm_x86_ops dirty logging hooks when they are valid.
8025 *
8026 * kvm_x86_ops->slot_disable_log_dirty is called when:
8027 *
8028 * - KVM_MR_CREATE with dirty logging is disabled
8029 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8030 *
8031 * The reason is, in case of PML, we need to set D-bit for any slots
8032 * with dirty logging disabled in order to eliminate unnecessary GPA
8033 * logging in PML buffer (and potential PML buffer full VMEXT). This
8034 * guarantees leaving PML enabled during guest's lifetime won't have
8035 * any additonal overhead from PML when guest is running with dirty
8036 * logging disabled for memory slots.
8037 *
8038 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8039 * to dirty logging mode.
8040 *
8041 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8042 *
8043 * In case of write protect:
8044 *
8045 * Write protect all pages for dirty logging.
8046 *
8047 * All the sptes including the large sptes which point to this
8048 * slot are set to readonly. We can not create any new large
8049 * spte on this slot until the end of the logging.
8050 *
8051 * See the comments in fast_page_fault().
8052 */
8053 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8054 if (kvm_x86_ops->slot_enable_log_dirty)
8055 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8056 else
8057 kvm_mmu_slot_remove_write_access(kvm, new);
8058 } else {
8059 if (kvm_x86_ops->slot_disable_log_dirty)
8060 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8061 }
8062}
8063
f7784b8e 8064void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8065 const struct kvm_userspace_memory_region *mem,
8482644a 8066 const struct kvm_memory_slot *old,
f36f3f28 8067 const struct kvm_memory_slot *new,
8482644a 8068 enum kvm_mr_change change)
f7784b8e 8069{
8482644a 8070 int nr_mmu_pages = 0;
f7784b8e 8071
48c0e4e9
XG		 8072 if (!kvm->arch.n_requested_mmu_pages)
8073 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8074
48c0e4e9 8075 if (nr_mmu_pages)
0de10343 8076 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8077
3ea3b7fa
WL		 8078 /*
8079 * Dirty logging tracks sptes in 4k granularity, meaning that large
8080 * sptes have to be split. If live migration is successful, the guest
8081 * in the source machine will be destroyed and large sptes will be
8082 * created in the destination. However, if the guest continues to run
8083 * in the source machine (for example if live migration fails), small
8084 * sptes will remain around and cause bad performance.
8085 *
8086 * Scan sptes if dirty logging has been stopped, dropping those
8087 * which can be collapsed into a single large-page spte. Later
8088 * page faults will create the large-page sptes.
8089 */
8090 if ((change != KVM_MR_DELETE) &&
8091 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8092 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8093 kvm_mmu_zap_collapsible_sptes(kvm, new);
8094
c972f3b1 8095 /*
88178fd4 8096 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8097 *
88178fd4
KH		 8098 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8099 * been zapped so no dirty logging staff is needed for old slot. For
8100 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8101 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8102 *
8103 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8104 */
88178fd4 8105 if (change != KVM_MR_DELETE)
f36f3f28 8106 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8107}
1d737c8a 8108
2df72e9b 8109void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8110{
6ca18b69 8111 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8112}
8113
2df72e9b
MT		 8114void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8115 struct kvm_memory_slot *slot)
8116{
6ca18b69 8117 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8118}
8119
5d9bc648
PB		 8120static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8121{
8122 if (!list_empty_careful(&vcpu->async_pf.done))
8123 return true;
8124
8125 if (kvm_apic_has_events(vcpu))
8126 return true;
8127
8128 if (vcpu->arch.pv.pv_unhalted)
8129 return true;
8130
8131 if (atomic_read(&vcpu->arch.nmi_queued))
8132 return true;
8133
73917739
PB		 8134 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8135 return true;
8136
5d9bc648
PB		 8137 if (kvm_arch_interrupt_allowed(vcpu) &&
8138 kvm_cpu_has_interrupt(vcpu))
8139 return true;
8140
1f4b34f8
AS		 8141 if (kvm_hv_has_stimer_pending(vcpu))
8142 return true;
8143
5d9bc648
PB		 8144 return false;
8145}
8146
1d737c8a
ZX		 8147int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8148{
b6b8a145
JK		 8149 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8150 kvm_x86_ops->check_nested_events(vcpu, false);
8151
5d9bc648 8152 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8153}
5736199a 8154
b6d33834 8155int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8156{
b6d33834 8157 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8158}
78646121
GN		 8159
8160int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8161{
8162 return kvm_x86_ops->interrupt_allowed(vcpu);
8163}
229456fc 8164
82b32774 8165unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8166{
82b32774
NA		 8167 if (is_64_bit_mode(vcpu))
8168 return kvm_rip_read(vcpu);
8169 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8170 kvm_rip_read(vcpu));
8171}
8172EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8173
82b32774
NA		 8174bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8175{
8176 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8177}
8178EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8179
94fe45da
JK		 8180unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8181{
8182 unsigned long rflags;
8183
8184 rflags = kvm_x86_ops->get_rflags(vcpu);
8185 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8186 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8187 return rflags;
8188}
8189EXPORT_SYMBOL_GPL(kvm_get_rflags);
8190
6addfc42 8191static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8192{
8193 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8194 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8195 rflags |= X86_EFLAGS_TF;
94fe45da 8196 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8197}
8198
8199void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8200{
8201 __kvm_set_rflags(vcpu, rflags);
3842d135 8202 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8203}
8204EXPORT_SYMBOL_GPL(kvm_set_rflags);
8205
56028d08
GN		 8206void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8207{
8208 int r;
8209
fb67e14f 8210 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8211 work->wakeup_all)
56028d08
GN		 8212 return;
8213
8214 r = kvm_mmu_reload(vcpu);
8215 if (unlikely(r))
8216 return;
8217
fb67e14f
XG		 8218 if (!vcpu->arch.mmu.direct_map &&
8219 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8220 return;
8221
56028d08
GN		 8222 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8223}
8224
af585b92
GN		 8225static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8226{
8227 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8228}
8229
8230static inline u32 kvm_async_pf_next_probe(u32 key)
8231{
8232 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8233}
8234
8235static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8236{
8237 u32 key = kvm_async_pf_hash_fn(gfn);
8238
8239 while (vcpu->arch.apf.gfns[key] != ~0)
8240 key = kvm_async_pf_next_probe(key);
8241
8242 vcpu->arch.apf.gfns[key] = gfn;
8243}
8244
8245static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8246{
8247 int i;
8248 u32 key = kvm_async_pf_hash_fn(gfn);
8249
8250 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8251 (vcpu->arch.apf.gfns[key] != gfn &&
8252 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8253 key = kvm_async_pf_next_probe(key);
8254
8255 return key;
8256}
8257
8258bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8259{
8260 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8261}
8262
8263static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8264{
8265 u32 i, j, k;
8266
8267 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8268 while (true) {
8269 vcpu->arch.apf.gfns[i] = ~0;
8270 do {
8271 j = kvm_async_pf_next_probe(j);
8272 if (vcpu->arch.apf.gfns[j] == ~0)
8273 return;
8274 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8275 /*
8276 * k lies cyclically in ]i,j]
8277 * | i.k.j |
8278 * |....j i.k.| or |.k..j i...|
8279 */
8280 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8281 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8282 i = j;
8283 }
8284}
8285
7c90705b
GN		 8286static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8287{
8288
8289 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8290 sizeof(val));
8291}
8292
af585b92
GN		 8293void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8294 struct kvm_async_pf *work)
8295{
6389ee94
AK		 8296 struct x86_exception fault;
8297
7c90705b 8298 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8299 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8300
8301 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8302 (vcpu->arch.apf.send_user_only &&
8303 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8304 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8305 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8306 fault.vector = PF_VECTOR;
8307 fault.error_code_valid = true;
8308 fault.error_code = 0;
8309 fault.nested_page_fault = false;
8310 fault.address = work->arch.token;
8311 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8312 }
af585b92
GN		 8313}
8314
8315void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8316 struct kvm_async_pf *work)
8317{
6389ee94
AK		 8318 struct x86_exception fault;
8319
7c90705b 8320 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8321 if (work->wakeup_all)
7c90705b
GN		 8322 work->arch.token = ~0; /* broadcast wakeup */
8323 else
8324 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8325
8326 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8327 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8328 fault.vector = PF_VECTOR;
8329 fault.error_code_valid = true;
8330 fault.error_code = 0;
8331 fault.nested_page_fault = false;
8332 fault.address = work->arch.token;
8333 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8334 }
e6d53e3b 8335 vcpu->arch.apf.halted = false;
a4fa1635 8336 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8337}
8338
8339bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8340{
8341 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8342 return true;
8343 else
8344 return !kvm_event_needs_reinjection(vcpu) &&
8345 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8346}
8347
5544eb9b
PB		 8348void kvm_arch_start_assignment(struct kvm *kvm)
8349{
8350 atomic_inc(&kvm->arch.assigned_device_count);
8351}
8352EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8353
8354void kvm_arch_end_assignment(struct kvm *kvm)
8355{
8356 atomic_dec(&kvm->arch.assigned_device_count);
8357}
8358EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8359
8360bool kvm_arch_has_assigned_device(struct kvm *kvm)
8361{
8362 return atomic_read(&kvm->arch.assigned_device_count);
8363}
8364EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8365
e0f0bbc5
AW		 8366void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8367{
8368 atomic_inc(&kvm->arch.noncoherent_dma_count);
8369}
8370EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8371
8372void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8373{
8374 atomic_dec(&kvm->arch.noncoherent_dma_count);
8375}
8376EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8377
8378bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8379{
8380 return atomic_read(&kvm->arch.noncoherent_dma_count);
8381}
8382EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8383
14717e20
AW		 8384bool kvm_arch_has_irq_bypass(void)
8385{
8386 return kvm_x86_ops->update_pi_irte != NULL;
8387}
8388
87276880
FW		 8389int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8390 struct irq_bypass_producer *prod)
8391{
8392 struct kvm_kernel_irqfd *irqfd =
8393 container_of(cons, struct kvm_kernel_irqfd, consumer);
8394
14717e20 8395 irqfd->producer = prod;
87276880 8396
14717e20
AW		 8397 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8398 prod->irq, irqfd->gsi, 1);
87276880
FW		 8399}
8400
8401void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8402 struct irq_bypass_producer *prod)
8403{
8404 int ret;
8405 struct kvm_kernel_irqfd *irqfd =
8406 container_of(cons, struct kvm_kernel_irqfd, consumer);
8407
87276880
FW		 8408 WARN_ON(irqfd->producer != prod);
8409 irqfd->producer = NULL;
8410
8411 /*
8412 * When producer of consumer is unregistered, we change back to
8413 * remapped mode, so we can re-use the current implementation
bb3541f1 8414 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8415 * int this case doesn't want to receive the interrupts.
8416 */
8417 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8418 if (ret)
8419 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8420 " fails: %d\n", irqfd->consumer.token, ret);
8421}
8422
8423int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8424 uint32_t guest_irq, bool set)
8425{
8426 if (!kvm_x86_ops->update_pi_irte)
8427 return -EINVAL;
8428
8429 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8430}
8431
52004014
FW		 8432bool kvm_vector_hashing_enabled(void)
8433{
8434 return vector_hashing;
8435}
8436EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8437
229456fc 8438EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8439EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8440EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8441EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8442EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8443EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8444EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8445EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8446EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8447EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8448EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8449EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8450EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8451EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8452EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8453EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8454EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8455EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8456EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux kernel - Deliverables
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