Commit | Line | Data |
---|---|---|
2e5d9c85 | 1 | /* |
2 | * Handle caching attributes in page tables (PAT) | |
3 | * | |
4 | * Authors: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> | |
5 | * Suresh B Siddha <suresh.b.siddha@intel.com> | |
6 | * | |
7 | * Loosely based on earlier PAT patchset from Eric Biederman and Andi Kleen. | |
8 | */ | |
9 | ||
ad2cde16 IM |
10 | #include <linux/seq_file.h> |
11 | #include <linux/bootmem.h> | |
12 | #include <linux/debugfs.h> | |
2e5d9c85 | 13 | #include <linux/kernel.h> |
92b9af9e | 14 | #include <linux/module.h> |
f25748e3 | 15 | #include <linux/pfn_t.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
ad2cde16 | 17 | #include <linux/mm.h> |
2e5d9c85 | 18 | #include <linux/fs.h> |
335ef896 | 19 | #include <linux/rbtree.h> |
2e5d9c85 | 20 | |
ad2cde16 | 21 | #include <asm/cacheflush.h> |
2e5d9c85 | 22 | #include <asm/processor.h> |
ad2cde16 | 23 | #include <asm/tlbflush.h> |
fd12a0d6 | 24 | #include <asm/x86_init.h> |
2e5d9c85 | 25 | #include <asm/pgtable.h> |
2e5d9c85 | 26 | #include <asm/fcntl.h> |
ad2cde16 | 27 | #include <asm/e820.h> |
2e5d9c85 | 28 | #include <asm/mtrr.h> |
ad2cde16 IM |
29 | #include <asm/page.h> |
30 | #include <asm/msr.h> | |
31 | #include <asm/pat.h> | |
e7f260a2 | 32 | #include <asm/io.h> |
2e5d9c85 | 33 | |
be5a0c12 | 34 | #include "pat_internal.h" |
bd809af1 | 35 | #include "mm_internal.h" |
be5a0c12 | 36 | |
9e76561f LR |
37 | #undef pr_fmt |
38 | #define pr_fmt(fmt) "" fmt | |
39 | ||
9dac6290 BP |
40 | static bool boot_cpu_done; |
41 | ||
cb32edf6 | 42 | static int __read_mostly __pat_enabled = IS_ENABLED(CONFIG_X86_PAT); |
2e5d9c85 | 43 | |
1ee4bd92 | 44 | static inline void pat_disable(const char *reason) |
2e5d9c85 | 45 | { |
cb32edf6 | 46 | __pat_enabled = 0; |
9e76561f | 47 | pr_info("x86/PAT: %s\n", reason); |
2e5d9c85 | 48 | } |
2e5d9c85 | 49 | |
be524fb9 | 50 | static int __init nopat(char *str) |
2e5d9c85 | 51 | { |
8d4a4300 | 52 | pat_disable("PAT support disabled."); |
2e5d9c85 | 53 | return 0; |
54 | } | |
8d4a4300 | 55 | early_param("nopat", nopat); |
cb32edf6 LR |
56 | |
57 | bool pat_enabled(void) | |
75a04811 | 58 | { |
cb32edf6 | 59 | return !!__pat_enabled; |
75a04811 | 60 | } |
fbe7193a | 61 | EXPORT_SYMBOL_GPL(pat_enabled); |
77b52b4c | 62 | |
be5a0c12 | 63 | int pat_debug_enable; |
ad2cde16 | 64 | |
77b52b4c VP |
65 | static int __init pat_debug_setup(char *str) |
66 | { | |
be5a0c12 | 67 | pat_debug_enable = 1; |
77b52b4c VP |
68 | return 0; |
69 | } | |
70 | __setup("debugpat", pat_debug_setup); | |
71 | ||
0dbcae88 TG |
72 | #ifdef CONFIG_X86_PAT |
73 | /* | |
35a5a104 TK |
74 | * X86 PAT uses page flags arch_1 and uncached together to keep track of |
75 | * memory type of pages that have backing page struct. | |
76 | * | |
77 | * X86 PAT supports 4 different memory types: | |
78 | * - _PAGE_CACHE_MODE_WB | |
79 | * - _PAGE_CACHE_MODE_WC | |
80 | * - _PAGE_CACHE_MODE_UC_MINUS | |
81 | * - _PAGE_CACHE_MODE_WT | |
82 | * | |
83 | * _PAGE_CACHE_MODE_WB is the default type. | |
0dbcae88 TG |
84 | */ |
85 | ||
35a5a104 | 86 | #define _PGMT_WB 0 |
0dbcae88 TG |
87 | #define _PGMT_WC (1UL << PG_arch_1) |
88 | #define _PGMT_UC_MINUS (1UL << PG_uncached) | |
35a5a104 | 89 | #define _PGMT_WT (1UL << PG_uncached | 1UL << PG_arch_1) |
0dbcae88 TG |
90 | #define _PGMT_MASK (1UL << PG_uncached | 1UL << PG_arch_1) |
91 | #define _PGMT_CLEAR_MASK (~_PGMT_MASK) | |
92 | ||
93 | static inline enum page_cache_mode get_page_memtype(struct page *pg) | |
94 | { | |
95 | unsigned long pg_flags = pg->flags & _PGMT_MASK; | |
96 | ||
35a5a104 TK |
97 | if (pg_flags == _PGMT_WB) |
98 | return _PAGE_CACHE_MODE_WB; | |
0dbcae88 TG |
99 | else if (pg_flags == _PGMT_WC) |
100 | return _PAGE_CACHE_MODE_WC; | |
101 | else if (pg_flags == _PGMT_UC_MINUS) | |
102 | return _PAGE_CACHE_MODE_UC_MINUS; | |
103 | else | |
35a5a104 | 104 | return _PAGE_CACHE_MODE_WT; |
0dbcae88 TG |
105 | } |
106 | ||
107 | static inline void set_page_memtype(struct page *pg, | |
108 | enum page_cache_mode memtype) | |
109 | { | |
110 | unsigned long memtype_flags; | |
111 | unsigned long old_flags; | |
112 | unsigned long new_flags; | |
113 | ||
114 | switch (memtype) { | |
115 | case _PAGE_CACHE_MODE_WC: | |
116 | memtype_flags = _PGMT_WC; | |
117 | break; | |
118 | case _PAGE_CACHE_MODE_UC_MINUS: | |
119 | memtype_flags = _PGMT_UC_MINUS; | |
120 | break; | |
35a5a104 TK |
121 | case _PAGE_CACHE_MODE_WT: |
122 | memtype_flags = _PGMT_WT; | |
0dbcae88 | 123 | break; |
35a5a104 | 124 | case _PAGE_CACHE_MODE_WB: |
0dbcae88 | 125 | default: |
35a5a104 | 126 | memtype_flags = _PGMT_WB; |
0dbcae88 TG |
127 | break; |
128 | } | |
129 | ||
130 | do { | |
131 | old_flags = pg->flags; | |
132 | new_flags = (old_flags & _PGMT_CLEAR_MASK) | memtype_flags; | |
133 | } while (cmpxchg(&pg->flags, old_flags, new_flags) != old_flags); | |
134 | } | |
135 | #else | |
136 | static inline enum page_cache_mode get_page_memtype(struct page *pg) | |
137 | { | |
138 | return -1; | |
139 | } | |
140 | static inline void set_page_memtype(struct page *pg, | |
141 | enum page_cache_mode memtype) | |
142 | { | |
143 | } | |
144 | #endif | |
145 | ||
2e5d9c85 | 146 | enum { |
147 | PAT_UC = 0, /* uncached */ | |
148 | PAT_WC = 1, /* Write combining */ | |
149 | PAT_WT = 4, /* Write Through */ | |
150 | PAT_WP = 5, /* Write Protected */ | |
151 | PAT_WB = 6, /* Write Back (default) */ | |
152 | PAT_UC_MINUS = 7, /* UC, but can be overriden by MTRR */ | |
153 | }; | |
154 | ||
bd809af1 JG |
155 | #define CM(c) (_PAGE_CACHE_MODE_ ## c) |
156 | ||
157 | static enum page_cache_mode pat_get_cache_mode(unsigned pat_val, char *msg) | |
158 | { | |
159 | enum page_cache_mode cache; | |
160 | char *cache_mode; | |
161 | ||
162 | switch (pat_val) { | |
163 | case PAT_UC: cache = CM(UC); cache_mode = "UC "; break; | |
164 | case PAT_WC: cache = CM(WC); cache_mode = "WC "; break; | |
165 | case PAT_WT: cache = CM(WT); cache_mode = "WT "; break; | |
166 | case PAT_WP: cache = CM(WP); cache_mode = "WP "; break; | |
167 | case PAT_WB: cache = CM(WB); cache_mode = "WB "; break; | |
168 | case PAT_UC_MINUS: cache = CM(UC_MINUS); cache_mode = "UC- "; break; | |
169 | default: cache = CM(WB); cache_mode = "WB "; break; | |
170 | } | |
171 | ||
172 | memcpy(msg, cache_mode, 4); | |
173 | ||
174 | return cache; | |
175 | } | |
176 | ||
177 | #undef CM | |
178 | ||
179 | /* | |
180 | * Update the cache mode to pgprot translation tables according to PAT | |
181 | * configuration. | |
182 | * Using lower indices is preferred, so we start with highest index. | |
183 | */ | |
9cd25aac | 184 | void pat_init_cache_modes(u64 pat) |
bd809af1 | 185 | { |
bd809af1 JG |
186 | enum page_cache_mode cache; |
187 | char pat_msg[33]; | |
9cd25aac | 188 | int i; |
bd809af1 | 189 | |
bd809af1 JG |
190 | pat_msg[32] = 0; |
191 | for (i = 7; i >= 0; i--) { | |
192 | cache = pat_get_cache_mode((pat >> (i * 8)) & 7, | |
193 | pat_msg + 4 * i); | |
194 | update_cache_mode_entry(i, cache); | |
195 | } | |
9e76561f | 196 | pr_info("x86/PAT: Configuration [0-7]: %s\n", pat_msg); |
bd809af1 JG |
197 | } |
198 | ||
cd7a4e93 | 199 | #define PAT(x, y) ((u64)PAT_ ## y << ((x)*8)) |
2e5d9c85 | 200 | |
9dac6290 | 201 | static void pat_bsp_init(u64 pat) |
2e5d9c85 | 202 | { |
9cd25aac BP |
203 | u64 tmp_pat; |
204 | ||
9dac6290 BP |
205 | if (!cpu_has_pat) { |
206 | pat_disable("PAT not supported by CPU."); | |
207 | return; | |
208 | } | |
2e5d9c85 | 209 | |
9cd25aac BP |
210 | if (!pat_enabled()) |
211 | goto done; | |
212 | ||
213 | rdmsrl(MSR_IA32_CR_PAT, tmp_pat); | |
214 | if (!tmp_pat) { | |
9dac6290 | 215 | pat_disable("PAT MSR is 0, disabled."); |
2e5d9c85 | 216 | return; |
9dac6290 BP |
217 | } |
218 | ||
219 | wrmsrl(MSR_IA32_CR_PAT, pat); | |
2e5d9c85 | 220 | |
9cd25aac BP |
221 | done: |
222 | pat_init_cache_modes(pat); | |
9dac6290 BP |
223 | } |
224 | ||
225 | static void pat_ap_init(u64 pat) | |
226 | { | |
9cd25aac BP |
227 | if (!pat_enabled()) |
228 | return; | |
229 | ||
75a04811 | 230 | if (!cpu_has_pat) { |
9dac6290 BP |
231 | /* |
232 | * If this happens we are on a secondary CPU, but switched to | |
233 | * PAT on the boot CPU. We have no way to undo PAT. | |
234 | */ | |
235 | panic("x86/PAT: PAT enabled, but not supported by secondary CPU\n"); | |
8d4a4300 | 236 | } |
2e5d9c85 | 237 | |
9dac6290 BP |
238 | wrmsrl(MSR_IA32_CR_PAT, pat); |
239 | } | |
240 | ||
241 | void pat_init(void) | |
242 | { | |
243 | u64 pat; | |
d79a40ca | 244 | struct cpuinfo_x86 *c = &boot_cpu_data; |
9dac6290 | 245 | |
9cd25aac BP |
246 | if (!pat_enabled()) { |
247 | /* | |
248 | * No PAT. Emulate the PAT table that corresponds to the two | |
249 | * cache bits, PWT (Write Through) and PCD (Cache Disable). This | |
250 | * setup is the same as the BIOS default setup when the system | |
251 | * has PAT but the "nopat" boot option has been specified. This | |
252 | * emulated PAT table is used when MSR_IA32_CR_PAT returns 0. | |
253 | * | |
d79a40ca | 254 | * PTE encoding: |
9cd25aac BP |
255 | * |
256 | * PCD | |
257 | * |PWT PAT | |
258 | * || slot | |
259 | * 00 0 WB : _PAGE_CACHE_MODE_WB | |
260 | * 01 1 WT : _PAGE_CACHE_MODE_WT | |
261 | * 10 2 UC-: _PAGE_CACHE_MODE_UC_MINUS | |
262 | * 11 3 UC : _PAGE_CACHE_MODE_UC | |
263 | * | |
264 | * NOTE: When WC or WP is used, it is redirected to UC- per | |
265 | * the default setup in __cachemode2pte_tbl[]. | |
266 | */ | |
267 | pat = PAT(0, WB) | PAT(1, WT) | PAT(2, UC_MINUS) | PAT(3, UC) | | |
268 | PAT(4, WB) | PAT(5, WT) | PAT(6, UC_MINUS) | PAT(7, UC); | |
d79a40ca TK |
269 | |
270 | } else if ((c->x86_vendor == X86_VENDOR_INTEL) && | |
271 | (((c->x86 == 0x6) && (c->x86_model <= 0xd)) || | |
272 | ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) { | |
9cd25aac | 273 | /* |
d79a40ca TK |
274 | * PAT support with the lower four entries. Intel Pentium 2, |
275 | * 3, M, and 4 are affected by PAT errata, which makes the | |
276 | * upper four entries unusable. To be on the safe side, we don't | |
277 | * use those. | |
278 | * | |
279 | * PTE encoding: | |
9cd25aac BP |
280 | * PAT |
281 | * |PCD | |
d79a40ca TK |
282 | * ||PWT PAT |
283 | * ||| slot | |
284 | * 000 0 WB : _PAGE_CACHE_MODE_WB | |
285 | * 001 1 WC : _PAGE_CACHE_MODE_WC | |
286 | * 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS | |
287 | * 011 3 UC : _PAGE_CACHE_MODE_UC | |
9cd25aac | 288 | * PAT bit unused |
d79a40ca TK |
289 | * |
290 | * NOTE: When WT or WP is used, it is redirected to UC- per | |
291 | * the default setup in __cachemode2pte_tbl[]. | |
9cd25aac BP |
292 | */ |
293 | pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) | | |
294 | PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC); | |
d79a40ca TK |
295 | } else { |
296 | /* | |
297 | * Full PAT support. We put WT in slot 7 to improve | |
298 | * robustness in the presence of errata that might cause | |
299 | * the high PAT bit to be ignored. This way, a buggy slot 7 | |
300 | * access will hit slot 3, and slot 3 is UC, so at worst | |
301 | * we lose performance without causing a correctness issue. | |
302 | * Pentium 4 erratum N46 is an example for such an erratum, | |
303 | * although we try not to use PAT at all on affected CPUs. | |
304 | * | |
305 | * PTE encoding: | |
306 | * PAT | |
307 | * |PCD | |
308 | * ||PWT PAT | |
309 | * ||| slot | |
310 | * 000 0 WB : _PAGE_CACHE_MODE_WB | |
311 | * 001 1 WC : _PAGE_CACHE_MODE_WC | |
312 | * 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS | |
313 | * 011 3 UC : _PAGE_CACHE_MODE_UC | |
314 | * 100 4 WB : Reserved | |
315 | * 101 5 WC : Reserved | |
316 | * 110 6 UC-: Reserved | |
317 | * 111 7 WT : _PAGE_CACHE_MODE_WT | |
318 | * | |
319 | * The reserved slots are unused, but mapped to their | |
320 | * corresponding types in the presence of PAT errata. | |
321 | */ | |
322 | pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) | | |
323 | PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, WT); | |
9cd25aac | 324 | } |
2e5d9c85 | 325 | |
9dac6290 BP |
326 | if (!boot_cpu_done) { |
327 | pat_bsp_init(pat); | |
328 | boot_cpu_done = true; | |
329 | } else { | |
330 | pat_ap_init(pat); | |
9d34cfdf | 331 | } |
2e5d9c85 | 332 | } |
333 | ||
334 | #undef PAT | |
335 | ||
9e41a49a | 336 | static DEFINE_SPINLOCK(memtype_lock); /* protects memtype accesses */ |
335ef896 | 337 | |
2e5d9c85 | 338 | /* |
339 | * Does intersection of PAT memory type and MTRR memory type and returns | |
340 | * the resulting memory type as PAT understands it. | |
341 | * (Type in pat and mtrr will not have same value) | |
342 | * The intersection is based on "Effective Memory Type" tables in IA-32 | |
343 | * SDM vol 3a | |
344 | */ | |
e00c8cc9 JG |
345 | static unsigned long pat_x_mtrr_type(u64 start, u64 end, |
346 | enum page_cache_mode req_type) | |
2e5d9c85 | 347 | { |
c26421d0 VP |
348 | /* |
349 | * Look for MTRR hint to get the effective type in case where PAT | |
350 | * request is for WB. | |
351 | */ | |
e00c8cc9 | 352 | if (req_type == _PAGE_CACHE_MODE_WB) { |
b73522e0 | 353 | u8 mtrr_type, uniform; |
dd0c7c49 | 354 | |
b73522e0 | 355 | mtrr_type = mtrr_type_lookup(start, end, &uniform); |
b6ff32d9 | 356 | if (mtrr_type != MTRR_TYPE_WRBACK) |
e00c8cc9 | 357 | return _PAGE_CACHE_MODE_UC_MINUS; |
b6ff32d9 | 358 | |
e00c8cc9 | 359 | return _PAGE_CACHE_MODE_WB; |
dd0c7c49 AH |
360 | } |
361 | ||
362 | return req_type; | |
2e5d9c85 | 363 | } |
364 | ||
fa83523f JD |
365 | struct pagerange_state { |
366 | unsigned long cur_pfn; | |
367 | int ram; | |
368 | int not_ram; | |
369 | }; | |
370 | ||
371 | static int | |
372 | pagerange_is_ram_callback(unsigned long initial_pfn, unsigned long total_nr_pages, void *arg) | |
373 | { | |
374 | struct pagerange_state *state = arg; | |
375 | ||
376 | state->not_ram |= initial_pfn > state->cur_pfn; | |
377 | state->ram |= total_nr_pages > 0; | |
378 | state->cur_pfn = initial_pfn + total_nr_pages; | |
379 | ||
380 | return state->ram && state->not_ram; | |
381 | } | |
382 | ||
3709c857 | 383 | static int pat_pagerange_is_ram(resource_size_t start, resource_size_t end) |
be03d9e8 | 384 | { |
fa83523f JD |
385 | int ret = 0; |
386 | unsigned long start_pfn = start >> PAGE_SHIFT; | |
387 | unsigned long end_pfn = (end + PAGE_SIZE - 1) >> PAGE_SHIFT; | |
388 | struct pagerange_state state = {start_pfn, 0, 0}; | |
389 | ||
390 | /* | |
391 | * For legacy reasons, physical address range in the legacy ISA | |
392 | * region is tracked as non-RAM. This will allow users of | |
393 | * /dev/mem to map portions of legacy ISA region, even when | |
394 | * some of those portions are listed(or not even listed) with | |
395 | * different e820 types(RAM/reserved/..) | |
396 | */ | |
397 | if (start_pfn < ISA_END_ADDRESS >> PAGE_SHIFT) | |
398 | start_pfn = ISA_END_ADDRESS >> PAGE_SHIFT; | |
399 | ||
400 | if (start_pfn < end_pfn) { | |
401 | ret = walk_system_ram_range(start_pfn, end_pfn - start_pfn, | |
402 | &state, pagerange_is_ram_callback); | |
be03d9e8 SS |
403 | } |
404 | ||
fa83523f | 405 | return (ret > 0) ? -1 : (state.ram ? 1 : 0); |
be03d9e8 SS |
406 | } |
407 | ||
9542ada8 | 408 | /* |
f5841740 | 409 | * For RAM pages, we use page flags to mark the pages with appropriate type. |
35a5a104 TK |
410 | * The page flags are limited to four types, WB (default), WC, WT and UC-. |
411 | * WP request fails with -EINVAL, and UC gets redirected to UC-. Setting | |
412 | * a new memory type is only allowed for a page mapped with the default WB | |
413 | * type. | |
0d69bdff TK |
414 | * |
415 | * Here we do two passes: | |
416 | * - Find the memtype of all the pages in the range, look for any conflicts. | |
417 | * - In case of no conflicts, set the new memtype for pages in the range. | |
9542ada8 | 418 | */ |
e00c8cc9 JG |
419 | static int reserve_ram_pages_type(u64 start, u64 end, |
420 | enum page_cache_mode req_type, | |
421 | enum page_cache_mode *new_type) | |
9542ada8 SS |
422 | { |
423 | struct page *page; | |
f5841740 VP |
424 | u64 pfn; |
425 | ||
35a5a104 | 426 | if (req_type == _PAGE_CACHE_MODE_WP) { |
0d69bdff TK |
427 | if (new_type) |
428 | *new_type = _PAGE_CACHE_MODE_UC_MINUS; | |
429 | return -EINVAL; | |
430 | } | |
431 | ||
e00c8cc9 | 432 | if (req_type == _PAGE_CACHE_MODE_UC) { |
f5841740 VP |
433 | /* We do not support strong UC */ |
434 | WARN_ON_ONCE(1); | |
e00c8cc9 | 435 | req_type = _PAGE_CACHE_MODE_UC_MINUS; |
f5841740 | 436 | } |
9542ada8 SS |
437 | |
438 | for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) { | |
e00c8cc9 | 439 | enum page_cache_mode type; |
9542ada8 | 440 | |
f5841740 VP |
441 | page = pfn_to_page(pfn); |
442 | type = get_page_memtype(page); | |
35a5a104 | 443 | if (type != _PAGE_CACHE_MODE_WB) { |
9e76561f | 444 | pr_info("x86/PAT: reserve_ram_pages_type failed [mem %#010Lx-%#010Lx], track 0x%x, req 0x%x\n", |
365811d6 | 445 | start, end - 1, type, req_type); |
f5841740 VP |
446 | if (new_type) |
447 | *new_type = type; | |
448 | ||
449 | return -EBUSY; | |
450 | } | |
9542ada8 | 451 | } |
9542ada8 | 452 | |
f5841740 VP |
453 | if (new_type) |
454 | *new_type = req_type; | |
455 | ||
456 | for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) { | |
9542ada8 | 457 | page = pfn_to_page(pfn); |
f5841740 | 458 | set_page_memtype(page, req_type); |
9542ada8 | 459 | } |
f5841740 | 460 | return 0; |
9542ada8 SS |
461 | } |
462 | ||
463 | static int free_ram_pages_type(u64 start, u64 end) | |
464 | { | |
465 | struct page *page; | |
f5841740 | 466 | u64 pfn; |
9542ada8 SS |
467 | |
468 | for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) { | |
469 | page = pfn_to_page(pfn); | |
35a5a104 | 470 | set_page_memtype(page, _PAGE_CACHE_MODE_WB); |
9542ada8 SS |
471 | } |
472 | return 0; | |
9542ada8 SS |
473 | } |
474 | ||
e7f260a2 | 475 | /* |
476 | * req_type typically has one of the: | |
e00c8cc9 JG |
477 | * - _PAGE_CACHE_MODE_WB |
478 | * - _PAGE_CACHE_MODE_WC | |
479 | * - _PAGE_CACHE_MODE_UC_MINUS | |
480 | * - _PAGE_CACHE_MODE_UC | |
0d69bdff | 481 | * - _PAGE_CACHE_MODE_WT |
e7f260a2 | 482 | * |
ac97991e AH |
483 | * If new_type is NULL, function will return an error if it cannot reserve the |
484 | * region with req_type. If new_type is non-NULL, function will return | |
485 | * available type in new_type in case of no error. In case of any error | |
e7f260a2 | 486 | * it will return a negative return value. |
487 | */ | |
e00c8cc9 JG |
488 | int reserve_memtype(u64 start, u64 end, enum page_cache_mode req_type, |
489 | enum page_cache_mode *new_type) | |
2e5d9c85 | 490 | { |
be5a0c12 | 491 | struct memtype *new; |
e00c8cc9 | 492 | enum page_cache_mode actual_type; |
9542ada8 | 493 | int is_range_ram; |
ad2cde16 | 494 | int err = 0; |
2e5d9c85 | 495 | |
ad2cde16 | 496 | BUG_ON(start >= end); /* end is exclusive */ |
69e26be9 | 497 | |
cb32edf6 | 498 | if (!pat_enabled()) { |
e7f260a2 | 499 | /* This is identical to page table setting without PAT */ |
7202fdb1 BP |
500 | if (new_type) |
501 | *new_type = req_type; | |
2e5d9c85 | 502 | return 0; |
503 | } | |
504 | ||
505 | /* Low ISA region is always mapped WB in page table. No need to track */ | |
8a271389 | 506 | if (x86_platform.is_untracked_pat_range(start, end)) { |
ac97991e | 507 | if (new_type) |
e00c8cc9 | 508 | *new_type = _PAGE_CACHE_MODE_WB; |
2e5d9c85 | 509 | return 0; |
510 | } | |
511 | ||
b6ff32d9 SS |
512 | /* |
513 | * Call mtrr_lookup to get the type hint. This is an | |
514 | * optimization for /dev/mem mmap'ers into WB memory (BIOS | |
515 | * tools and ACPI tools). Use WB request for WB memory and use | |
516 | * UC_MINUS otherwise. | |
517 | */ | |
e00c8cc9 | 518 | actual_type = pat_x_mtrr_type(start, end, req_type); |
2e5d9c85 | 519 | |
95971342 SS |
520 | if (new_type) |
521 | *new_type = actual_type; | |
522 | ||
be03d9e8 | 523 | is_range_ram = pat_pagerange_is_ram(start, end); |
f5841740 VP |
524 | if (is_range_ram == 1) { |
525 | ||
f5841740 | 526 | err = reserve_ram_pages_type(start, end, req_type, new_type); |
f5841740 VP |
527 | |
528 | return err; | |
529 | } else if (is_range_ram < 0) { | |
9542ada8 | 530 | return -EINVAL; |
f5841740 | 531 | } |
9542ada8 | 532 | |
6a4f3b52 | 533 | new = kzalloc(sizeof(struct memtype), GFP_KERNEL); |
ac97991e | 534 | if (!new) |
2e5d9c85 | 535 | return -ENOMEM; |
536 | ||
ad2cde16 IM |
537 | new->start = start; |
538 | new->end = end; | |
539 | new->type = actual_type; | |
2e5d9c85 | 540 | |
2e5d9c85 | 541 | spin_lock(&memtype_lock); |
542 | ||
9e41a49a | 543 | err = rbt_memtype_check_insert(new, new_type); |
2e5d9c85 | 544 | if (err) { |
9e76561f LR |
545 | pr_info("x86/PAT: reserve_memtype failed [mem %#010Lx-%#010Lx], track %s, req %s\n", |
546 | start, end - 1, | |
547 | cattr_name(new->type), cattr_name(req_type)); | |
ac97991e | 548 | kfree(new); |
2e5d9c85 | 549 | spin_unlock(&memtype_lock); |
ad2cde16 | 550 | |
2e5d9c85 | 551 | return err; |
552 | } | |
553 | ||
2e5d9c85 | 554 | spin_unlock(&memtype_lock); |
3e9c83b3 | 555 | |
365811d6 BH |
556 | dprintk("reserve_memtype added [mem %#010Lx-%#010Lx], track %s, req %s, ret %s\n", |
557 | start, end - 1, cattr_name(new->type), cattr_name(req_type), | |
3e9c83b3 AH |
558 | new_type ? cattr_name(*new_type) : "-"); |
559 | ||
2e5d9c85 | 560 | return err; |
561 | } | |
562 | ||
563 | int free_memtype(u64 start, u64 end) | |
564 | { | |
2e5d9c85 | 565 | int err = -EINVAL; |
9542ada8 | 566 | int is_range_ram; |
20413f27 | 567 | struct memtype *entry; |
2e5d9c85 | 568 | |
cb32edf6 | 569 | if (!pat_enabled()) |
2e5d9c85 | 570 | return 0; |
2e5d9c85 | 571 | |
572 | /* Low ISA region is always mapped WB. No need to track */ | |
8a271389 | 573 | if (x86_platform.is_untracked_pat_range(start, end)) |
2e5d9c85 | 574 | return 0; |
2e5d9c85 | 575 | |
be03d9e8 | 576 | is_range_ram = pat_pagerange_is_ram(start, end); |
f5841740 VP |
577 | if (is_range_ram == 1) { |
578 | ||
f5841740 | 579 | err = free_ram_pages_type(start, end); |
f5841740 VP |
580 | |
581 | return err; | |
582 | } else if (is_range_ram < 0) { | |
9542ada8 | 583 | return -EINVAL; |
f5841740 | 584 | } |
9542ada8 | 585 | |
2e5d9c85 | 586 | spin_lock(&memtype_lock); |
20413f27 | 587 | entry = rbt_memtype_erase(start, end); |
2e5d9c85 | 588 | spin_unlock(&memtype_lock); |
589 | ||
2039e6ac | 590 | if (IS_ERR(entry)) { |
9e76561f LR |
591 | pr_info("x86/PAT: %s:%d freeing invalid memtype [mem %#010Lx-%#010Lx]\n", |
592 | current->comm, current->pid, start, end - 1); | |
20413f27 | 593 | return -EINVAL; |
2e5d9c85 | 594 | } |
6997ab49 | 595 | |
20413f27 XF |
596 | kfree(entry); |
597 | ||
365811d6 | 598 | dprintk("free_memtype request [mem %#010Lx-%#010Lx]\n", start, end - 1); |
ad2cde16 | 599 | |
20413f27 | 600 | return 0; |
2e5d9c85 | 601 | } |
602 | ||
f0970c13 | 603 | |
637b86e7 VP |
604 | /** |
605 | * lookup_memtype - Looksup the memory type for a physical address | |
606 | * @paddr: physical address of which memory type needs to be looked up | |
607 | * | |
608 | * Only to be called when PAT is enabled | |
609 | * | |
2a374698 | 610 | * Returns _PAGE_CACHE_MODE_WB, _PAGE_CACHE_MODE_WC, _PAGE_CACHE_MODE_UC_MINUS |
35a5a104 | 611 | * or _PAGE_CACHE_MODE_WT. |
637b86e7 | 612 | */ |
2a374698 | 613 | static enum page_cache_mode lookup_memtype(u64 paddr) |
637b86e7 | 614 | { |
2a374698 | 615 | enum page_cache_mode rettype = _PAGE_CACHE_MODE_WB; |
637b86e7 VP |
616 | struct memtype *entry; |
617 | ||
8a271389 | 618 | if (x86_platform.is_untracked_pat_range(paddr, paddr + PAGE_SIZE)) |
637b86e7 VP |
619 | return rettype; |
620 | ||
621 | if (pat_pagerange_is_ram(paddr, paddr + PAGE_SIZE)) { | |
622 | struct page *page; | |
637b86e7 | 623 | |
35a5a104 TK |
624 | page = pfn_to_page(paddr >> PAGE_SHIFT); |
625 | return get_page_memtype(page); | |
637b86e7 VP |
626 | } |
627 | ||
628 | spin_lock(&memtype_lock); | |
629 | ||
9e41a49a | 630 | entry = rbt_memtype_lookup(paddr); |
637b86e7 VP |
631 | if (entry != NULL) |
632 | rettype = entry->type; | |
633 | else | |
2a374698 | 634 | rettype = _PAGE_CACHE_MODE_UC_MINUS; |
637b86e7 VP |
635 | |
636 | spin_unlock(&memtype_lock); | |
637 | return rettype; | |
638 | } | |
639 | ||
9fd126bc VP |
640 | /** |
641 | * io_reserve_memtype - Request a memory type mapping for a region of memory | |
642 | * @start: start (physical address) of the region | |
643 | * @end: end (physical address) of the region | |
644 | * @type: A pointer to memtype, with requested type. On success, requested | |
645 | * or any other compatible type that was available for the region is returned | |
646 | * | |
647 | * On success, returns 0 | |
648 | * On failure, returns non-zero | |
649 | */ | |
650 | int io_reserve_memtype(resource_size_t start, resource_size_t end, | |
49a3b3cb | 651 | enum page_cache_mode *type) |
9fd126bc | 652 | { |
b855192c | 653 | resource_size_t size = end - start; |
49a3b3cb JG |
654 | enum page_cache_mode req_type = *type; |
655 | enum page_cache_mode new_type; | |
9fd126bc VP |
656 | int ret; |
657 | ||
b855192c | 658 | WARN_ON_ONCE(iomem_map_sanity_check(start, size)); |
9fd126bc VP |
659 | |
660 | ret = reserve_memtype(start, end, req_type, &new_type); | |
661 | if (ret) | |
662 | goto out_err; | |
663 | ||
b855192c | 664 | if (!is_new_memtype_allowed(start, size, req_type, new_type)) |
9fd126bc VP |
665 | goto out_free; |
666 | ||
b855192c | 667 | if (kernel_map_sync_memtype(start, size, new_type) < 0) |
9fd126bc VP |
668 | goto out_free; |
669 | ||
670 | *type = new_type; | |
671 | return 0; | |
672 | ||
673 | out_free: | |
674 | free_memtype(start, end); | |
675 | ret = -EBUSY; | |
676 | out_err: | |
677 | return ret; | |
678 | } | |
679 | ||
680 | /** | |
681 | * io_free_memtype - Release a memory type mapping for a region of memory | |
682 | * @start: start (physical address) of the region | |
683 | * @end: end (physical address) of the region | |
684 | */ | |
685 | void io_free_memtype(resource_size_t start, resource_size_t end) | |
686 | { | |
687 | free_memtype(start, end); | |
688 | } | |
689 | ||
f0970c13 | 690 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, |
691 | unsigned long size, pgprot_t vma_prot) | |
692 | { | |
693 | return vma_prot; | |
694 | } | |
695 | ||
d092633b | 696 | #ifdef CONFIG_STRICT_DEVMEM |
1f40a8bf | 697 | /* This check is done in drivers/char/mem.c in case of STRICT_DEVMEM */ |
0124cecf VP |
698 | static inline int range_is_allowed(unsigned long pfn, unsigned long size) |
699 | { | |
700 | return 1; | |
701 | } | |
702 | #else | |
9e41bff2 | 703 | /* This check is needed to avoid cache aliasing when PAT is enabled */ |
0124cecf VP |
704 | static inline int range_is_allowed(unsigned long pfn, unsigned long size) |
705 | { | |
706 | u64 from = ((u64)pfn) << PAGE_SHIFT; | |
707 | u64 to = from + size; | |
708 | u64 cursor = from; | |
709 | ||
cb32edf6 | 710 | if (!pat_enabled()) |
9e41bff2 RT |
711 | return 1; |
712 | ||
0124cecf VP |
713 | while (cursor < to) { |
714 | if (!devmem_is_allowed(pfn)) { | |
9e76561f LR |
715 | pr_info("x86/PAT: Program %s tried to access /dev/mem between [mem %#010Lx-%#010Lx], PAT prevents it\n", |
716 | current->comm, from, to - 1); | |
0124cecf VP |
717 | return 0; |
718 | } | |
719 | cursor += PAGE_SIZE; | |
720 | pfn++; | |
721 | } | |
722 | return 1; | |
723 | } | |
d092633b | 724 | #endif /* CONFIG_STRICT_DEVMEM */ |
0124cecf | 725 | |
f0970c13 | 726 | int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, |
727 | unsigned long size, pgprot_t *vma_prot) | |
728 | { | |
e00c8cc9 | 729 | enum page_cache_mode pcm = _PAGE_CACHE_MODE_WB; |
f0970c13 | 730 | |
0124cecf VP |
731 | if (!range_is_allowed(pfn, size)) |
732 | return 0; | |
733 | ||
6b2f3d1f | 734 | if (file->f_flags & O_DSYNC) |
e00c8cc9 | 735 | pcm = _PAGE_CACHE_MODE_UC_MINUS; |
f0970c13 | 736 | |
737 | #ifdef CONFIG_X86_32 | |
738 | /* | |
739 | * On the PPro and successors, the MTRRs are used to set | |
740 | * memory types for physical addresses outside main memory, | |
741 | * so blindly setting UC or PWT on those pages is wrong. | |
742 | * For Pentiums and earlier, the surround logic should disable | |
743 | * caching for the high addresses through the KEN pin, but | |
744 | * we maintain the tradition of paranoia in this code. | |
745 | */ | |
cb32edf6 | 746 | if (!pat_enabled() && |
cd7a4e93 AH |
747 | !(boot_cpu_has(X86_FEATURE_MTRR) || |
748 | boot_cpu_has(X86_FEATURE_K6_MTRR) || | |
749 | boot_cpu_has(X86_FEATURE_CYRIX_ARR) || | |
750 | boot_cpu_has(X86_FEATURE_CENTAUR_MCR)) && | |
751 | (pfn << PAGE_SHIFT) >= __pa(high_memory)) { | |
e00c8cc9 | 752 | pcm = _PAGE_CACHE_MODE_UC; |
f0970c13 | 753 | } |
754 | #endif | |
755 | ||
e7f260a2 | 756 | *vma_prot = __pgprot((pgprot_val(*vma_prot) & ~_PAGE_CACHE_MASK) | |
e00c8cc9 | 757 | cachemode2protval(pcm)); |
f0970c13 | 758 | return 1; |
759 | } | |
e7f260a2 | 760 | |
7880f746 VP |
761 | /* |
762 | * Change the memory type for the physial address range in kernel identity | |
763 | * mapping space if that range is a part of identity map. | |
764 | */ | |
b14097bd JG |
765 | int kernel_map_sync_memtype(u64 base, unsigned long size, |
766 | enum page_cache_mode pcm) | |
7880f746 VP |
767 | { |
768 | unsigned long id_sz; | |
769 | ||
a25b9316 | 770 | if (base > __pa(high_memory-1)) |
7880f746 VP |
771 | return 0; |
772 | ||
60f583d5 DH |
773 | /* |
774 | * some areas in the middle of the kernel identity range | |
775 | * are not mapped, like the PCI space. | |
776 | */ | |
777 | if (!page_is_ram(base >> PAGE_SHIFT)) | |
778 | return 0; | |
779 | ||
a25b9316 | 780 | id_sz = (__pa(high_memory-1) <= base + size) ? |
7880f746 VP |
781 | __pa(high_memory) - base : |
782 | size; | |
783 | ||
b14097bd | 784 | if (ioremap_change_attr((unsigned long)__va(base), id_sz, pcm) < 0) { |
9e76561f | 785 | pr_info("x86/PAT: %s:%d ioremap_change_attr failed %s for [mem %#010Lx-%#010Lx]\n", |
7880f746 | 786 | current->comm, current->pid, |
e00c8cc9 | 787 | cattr_name(pcm), |
365811d6 | 788 | base, (unsigned long long)(base + size-1)); |
7880f746 VP |
789 | return -EINVAL; |
790 | } | |
791 | return 0; | |
792 | } | |
793 | ||
5899329b | 794 | /* |
795 | * Internal interface to reserve a range of physical memory with prot. | |
796 | * Reserved non RAM regions only and after successful reserve_memtype, | |
797 | * this func also keeps identity mapping (if any) in sync with this new prot. | |
798 | */ | |
cdecff68 | 799 | static int reserve_pfn_range(u64 paddr, unsigned long size, pgprot_t *vma_prot, |
800 | int strict_prot) | |
5899329b | 801 | { |
802 | int is_ram = 0; | |
7880f746 | 803 | int ret; |
e00c8cc9 JG |
804 | enum page_cache_mode want_pcm = pgprot2cachemode(*vma_prot); |
805 | enum page_cache_mode pcm = want_pcm; | |
5899329b | 806 | |
be03d9e8 | 807 | is_ram = pat_pagerange_is_ram(paddr, paddr + size); |
5899329b | 808 | |
be03d9e8 | 809 | /* |
d886c73c VP |
810 | * reserve_pfn_range() for RAM pages. We do not refcount to keep |
811 | * track of number of mappings of RAM pages. We can assert that | |
812 | * the type requested matches the type of first page in the range. | |
be03d9e8 | 813 | */ |
d886c73c | 814 | if (is_ram) { |
cb32edf6 | 815 | if (!pat_enabled()) |
d886c73c VP |
816 | return 0; |
817 | ||
e00c8cc9 JG |
818 | pcm = lookup_memtype(paddr); |
819 | if (want_pcm != pcm) { | |
9e76561f | 820 | pr_warn("x86/PAT: %s:%d map pfn RAM range req %s for [mem %#010Lx-%#010Lx], got %s\n", |
d886c73c | 821 | current->comm, current->pid, |
e00c8cc9 | 822 | cattr_name(want_pcm), |
d886c73c | 823 | (unsigned long long)paddr, |
365811d6 | 824 | (unsigned long long)(paddr + size - 1), |
e00c8cc9 | 825 | cattr_name(pcm)); |
d886c73c | 826 | *vma_prot = __pgprot((pgprot_val(*vma_prot) & |
e00c8cc9 JG |
827 | (~_PAGE_CACHE_MASK)) | |
828 | cachemode2protval(pcm)); | |
d886c73c | 829 | } |
4bb9c5c0 | 830 | return 0; |
d886c73c | 831 | } |
5899329b | 832 | |
e00c8cc9 | 833 | ret = reserve_memtype(paddr, paddr + size, want_pcm, &pcm); |
5899329b | 834 | if (ret) |
835 | return ret; | |
836 | ||
e00c8cc9 | 837 | if (pcm != want_pcm) { |
1adcaafe | 838 | if (strict_prot || |
e00c8cc9 | 839 | !is_new_memtype_allowed(paddr, size, want_pcm, pcm)) { |
cdecff68 | 840 | free_memtype(paddr, paddr + size); |
9e76561f LR |
841 | pr_err("x86/PAT: %s:%d map pfn expected mapping type %s for [mem %#010Lx-%#010Lx], got %s\n", |
842 | current->comm, current->pid, | |
843 | cattr_name(want_pcm), | |
844 | (unsigned long long)paddr, | |
845 | (unsigned long long)(paddr + size - 1), | |
846 | cattr_name(pcm)); | |
cdecff68 | 847 | return -EINVAL; |
848 | } | |
849 | /* | |
850 | * We allow returning different type than the one requested in | |
851 | * non strict case. | |
852 | */ | |
853 | *vma_prot = __pgprot((pgprot_val(*vma_prot) & | |
854 | (~_PAGE_CACHE_MASK)) | | |
e00c8cc9 | 855 | cachemode2protval(pcm)); |
5899329b | 856 | } |
857 | ||
e00c8cc9 | 858 | if (kernel_map_sync_memtype(paddr, size, pcm) < 0) { |
5899329b | 859 | free_memtype(paddr, paddr + size); |
5899329b | 860 | return -EINVAL; |
861 | } | |
862 | return 0; | |
863 | } | |
864 | ||
865 | /* | |
866 | * Internal interface to free a range of physical memory. | |
867 | * Frees non RAM regions only. | |
868 | */ | |
869 | static void free_pfn_range(u64 paddr, unsigned long size) | |
870 | { | |
871 | int is_ram; | |
872 | ||
be03d9e8 | 873 | is_ram = pat_pagerange_is_ram(paddr, paddr + size); |
5899329b | 874 | if (is_ram == 0) |
875 | free_memtype(paddr, paddr + size); | |
876 | } | |
877 | ||
878 | /* | |
5180da41 | 879 | * track_pfn_copy is called when vma that is covering the pfnmap gets |
5899329b | 880 | * copied through copy_page_range(). |
881 | * | |
882 | * If the vma has a linear pfn mapping for the entire range, we get the prot | |
883 | * from pte and reserve the entire vma range with single reserve_pfn_range call. | |
5899329b | 884 | */ |
5180da41 | 885 | int track_pfn_copy(struct vm_area_struct *vma) |
5899329b | 886 | { |
c1c15b65 | 887 | resource_size_t paddr; |
982d789a | 888 | unsigned long prot; |
4b065046 | 889 | unsigned long vma_size = vma->vm_end - vma->vm_start; |
cdecff68 | 890 | pgprot_t pgprot; |
5899329b | 891 | |
b3b9c293 | 892 | if (vma->vm_flags & VM_PAT) { |
5899329b | 893 | /* |
982d789a | 894 | * reserve the whole chunk covered by vma. We need the |
895 | * starting address and protection from pte. | |
5899329b | 896 | */ |
4b065046 | 897 | if (follow_phys(vma, vma->vm_start, 0, &prot, &paddr)) { |
5899329b | 898 | WARN_ON_ONCE(1); |
982d789a | 899 | return -EINVAL; |
5899329b | 900 | } |
cdecff68 | 901 | pgprot = __pgprot(prot); |
902 | return reserve_pfn_range(paddr, vma_size, &pgprot, 1); | |
5899329b | 903 | } |
904 | ||
5899329b | 905 | return 0; |
5899329b | 906 | } |
907 | ||
908 | /* | |
5899329b | 909 | * prot is passed in as a parameter for the new mapping. If the vma has a |
910 | * linear pfn mapping for the entire range reserve the entire vma range with | |
911 | * single reserve_pfn_range call. | |
5899329b | 912 | */ |
5180da41 | 913 | int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, |
b3b9c293 | 914 | unsigned long pfn, unsigned long addr, unsigned long size) |
5899329b | 915 | { |
b1a86e15 | 916 | resource_size_t paddr = (resource_size_t)pfn << PAGE_SHIFT; |
2a374698 | 917 | enum page_cache_mode pcm; |
5899329b | 918 | |
b1a86e15 | 919 | /* reserve the whole chunk starting from paddr */ |
b3b9c293 KK |
920 | if (addr == vma->vm_start && size == (vma->vm_end - vma->vm_start)) { |
921 | int ret; | |
922 | ||
923 | ret = reserve_pfn_range(paddr, size, prot, 0); | |
924 | if (!ret) | |
925 | vma->vm_flags |= VM_PAT; | |
926 | return ret; | |
927 | } | |
5899329b | 928 | |
cb32edf6 | 929 | if (!pat_enabled()) |
10876376 VP |
930 | return 0; |
931 | ||
5180da41 SS |
932 | /* |
933 | * For anything smaller than the vma size we set prot based on the | |
934 | * lookup. | |
935 | */ | |
2a374698 | 936 | pcm = lookup_memtype(paddr); |
5180da41 SS |
937 | |
938 | /* Check memtype for the remaining pages */ | |
939 | while (size > PAGE_SIZE) { | |
940 | size -= PAGE_SIZE; | |
941 | paddr += PAGE_SIZE; | |
2a374698 | 942 | if (pcm != lookup_memtype(paddr)) |
5180da41 SS |
943 | return -EINVAL; |
944 | } | |
945 | ||
dd7b6847 | 946 | *prot = __pgprot((pgprot_val(*prot) & (~_PAGE_CACHE_MASK)) | |
2a374698 | 947 | cachemode2protval(pcm)); |
5180da41 SS |
948 | |
949 | return 0; | |
950 | } | |
951 | ||
952 | int track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, | |
f25748e3 | 953 | pfn_t pfn) |
5180da41 | 954 | { |
2a374698 | 955 | enum page_cache_mode pcm; |
5180da41 | 956 | |
cb32edf6 | 957 | if (!pat_enabled()) |
5180da41 SS |
958 | return 0; |
959 | ||
960 | /* Set prot based on lookup */ | |
f25748e3 | 961 | pcm = lookup_memtype(pfn_t_to_phys(pfn)); |
dd7b6847 | 962 | *prot = __pgprot((pgprot_val(*prot) & (~_PAGE_CACHE_MASK)) | |
2a374698 | 963 | cachemode2protval(pcm)); |
10876376 | 964 | |
5899329b | 965 | return 0; |
5899329b | 966 | } |
967 | ||
968 | /* | |
5180da41 | 969 | * untrack_pfn is called while unmapping a pfnmap for a region. |
5899329b | 970 | * untrack can be called for a specific region indicated by pfn and size or |
b1a86e15 | 971 | * can be for the entire vma (in which case pfn, size are zero). |
5899329b | 972 | */ |
5180da41 SS |
973 | void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, |
974 | unsigned long size) | |
5899329b | 975 | { |
c1c15b65 | 976 | resource_size_t paddr; |
b1a86e15 | 977 | unsigned long prot; |
5899329b | 978 | |
b3b9c293 | 979 | if (!(vma->vm_flags & VM_PAT)) |
5899329b | 980 | return; |
b1a86e15 SS |
981 | |
982 | /* free the chunk starting from pfn or the whole chunk */ | |
983 | paddr = (resource_size_t)pfn << PAGE_SHIFT; | |
984 | if (!paddr && !size) { | |
985 | if (follow_phys(vma, vma->vm_start, 0, &prot, &paddr)) { | |
986 | WARN_ON_ONCE(1); | |
987 | return; | |
988 | } | |
989 | ||
990 | size = vma->vm_end - vma->vm_start; | |
5899329b | 991 | } |
b1a86e15 | 992 | free_pfn_range(paddr, size); |
b3b9c293 | 993 | vma->vm_flags &= ~VM_PAT; |
5899329b | 994 | } |
995 | ||
d9fe4fab TK |
996 | /* |
997 | * untrack_pfn_moved is called, while mremapping a pfnmap for a new region, | |
998 | * with the old vma after its pfnmap page table has been removed. The new | |
999 | * vma has a new pfnmap to the same pfn & cache type with VM_PAT set. | |
1000 | */ | |
1001 | void untrack_pfn_moved(struct vm_area_struct *vma) | |
1002 | { | |
1003 | vma->vm_flags &= ~VM_PAT; | |
1004 | } | |
1005 | ||
2520bd31 | 1006 | pgprot_t pgprot_writecombine(pgprot_t prot) |
1007 | { | |
7202fdb1 | 1008 | return __pgprot(pgprot_val(prot) | |
e00c8cc9 | 1009 | cachemode2protval(_PAGE_CACHE_MODE_WC)); |
2520bd31 | 1010 | } |
92b9af9e | 1011 | EXPORT_SYMBOL_GPL(pgprot_writecombine); |
2520bd31 | 1012 | |
d1b4bfbf TK |
1013 | pgprot_t pgprot_writethrough(pgprot_t prot) |
1014 | { | |
1015 | return __pgprot(pgprot_val(prot) | | |
1016 | cachemode2protval(_PAGE_CACHE_MODE_WT)); | |
1017 | } | |
1018 | EXPORT_SYMBOL_GPL(pgprot_writethrough); | |
1019 | ||
012f09e7 | 1020 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_X86_PAT) |
fec0962e | 1021 | |
fec0962e | 1022 | static struct memtype *memtype_get_idx(loff_t pos) |
1023 | { | |
be5a0c12 | 1024 | struct memtype *print_entry; |
1025 | int ret; | |
fec0962e | 1026 | |
be5a0c12 | 1027 | print_entry = kzalloc(sizeof(struct memtype), GFP_KERNEL); |
fec0962e | 1028 | if (!print_entry) |
1029 | return NULL; | |
1030 | ||
1031 | spin_lock(&memtype_lock); | |
9e41a49a | 1032 | ret = rbt_memtype_copy_nth_element(print_entry, pos); |
fec0962e | 1033 | spin_unlock(&memtype_lock); |
ad2cde16 | 1034 | |
be5a0c12 | 1035 | if (!ret) { |
1036 | return print_entry; | |
1037 | } else { | |
1038 | kfree(print_entry); | |
1039 | return NULL; | |
1040 | } | |
fec0962e | 1041 | } |
1042 | ||
1043 | static void *memtype_seq_start(struct seq_file *seq, loff_t *pos) | |
1044 | { | |
1045 | if (*pos == 0) { | |
1046 | ++*pos; | |
3736708f | 1047 | seq_puts(seq, "PAT memtype list:\n"); |
fec0962e | 1048 | } |
1049 | ||
1050 | return memtype_get_idx(*pos); | |
1051 | } | |
1052 | ||
1053 | static void *memtype_seq_next(struct seq_file *seq, void *v, loff_t *pos) | |
1054 | { | |
1055 | ++*pos; | |
1056 | return memtype_get_idx(*pos); | |
1057 | } | |
1058 | ||
1059 | static void memtype_seq_stop(struct seq_file *seq, void *v) | |
1060 | { | |
1061 | } | |
1062 | ||
1063 | static int memtype_seq_show(struct seq_file *seq, void *v) | |
1064 | { | |
1065 | struct memtype *print_entry = (struct memtype *)v; | |
1066 | ||
1067 | seq_printf(seq, "%s @ 0x%Lx-0x%Lx\n", cattr_name(print_entry->type), | |
1068 | print_entry->start, print_entry->end); | |
1069 | kfree(print_entry); | |
ad2cde16 | 1070 | |
fec0962e | 1071 | return 0; |
1072 | } | |
1073 | ||
d535e431 | 1074 | static const struct seq_operations memtype_seq_ops = { |
fec0962e | 1075 | .start = memtype_seq_start, |
1076 | .next = memtype_seq_next, | |
1077 | .stop = memtype_seq_stop, | |
1078 | .show = memtype_seq_show, | |
1079 | }; | |
1080 | ||
1081 | static int memtype_seq_open(struct inode *inode, struct file *file) | |
1082 | { | |
1083 | return seq_open(file, &memtype_seq_ops); | |
1084 | } | |
1085 | ||
1086 | static const struct file_operations memtype_fops = { | |
1087 | .open = memtype_seq_open, | |
1088 | .read = seq_read, | |
1089 | .llseek = seq_lseek, | |
1090 | .release = seq_release, | |
1091 | }; | |
1092 | ||
1093 | static int __init pat_memtype_list_init(void) | |
1094 | { | |
cb32edf6 | 1095 | if (pat_enabled()) { |
dd4377b0 XF |
1096 | debugfs_create_file("pat_memtype_list", S_IRUSR, |
1097 | arch_debugfs_dir, NULL, &memtype_fops); | |
1098 | } | |
fec0962e | 1099 | return 0; |
1100 | } | |
1101 | ||
1102 | late_initcall(pat_memtype_list_init); | |
1103 | ||
012f09e7 | 1104 | #endif /* CONFIG_DEBUG_FS && CONFIG_X86_PAT */ |