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x86: constify PCI raw ops structures
[deliverable/linux.git] / arch / x86 / pci / direct.c
CommitLineData
1da177e4
LT		 1/*
2 * direct.c - Low-level direct PCI config space access
3 */
4
5#include <linux/pci.h>
6#include <linux/init.h>
ec0f08ee 7#include <linux/dmi.h>
82487711 8#include <asm/pci_x86.h>
1da177e4
LT		 9
10/*
831d9918
RR		 11 * Functions for accessing PCI base (first 256 bytes) and extended
12 * (4096 bytes per PCI function) configuration space with type 1
13 * accesses.
1da177e4
LT		 14 */
15
16#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
831d9918
RR		 17 (0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \
18 | (devfn << 8) | (reg & 0xFC))
1da177e4 19
b6ce068a 20static int pci_conf1_read(unsigned int seg, unsigned int bus,
1da177e4
LT		 21 unsigned int devfn, int reg, int len, u32 *value)
22{
23 unsigned long flags;
24
db34a363 25 if (seg || (bus > 255) || (devfn > 255) || (reg > 4095)) {
49c93e84 26 *value = -1;
1da177e4 27 return -EINVAL;
49c93e84 28 }
1da177e4 29
d19f61f0 30 raw_spin_lock_irqsave(&pci_config_lock, flags);
1da177e4
LT		 31
32 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
33
34 switch (len) {
35 case 1:
36 *value = inb(0xCFC + (reg & 3));
37 break;
38 case 2:
39 *value = inw(0xCFC + (reg & 2));
40 break;
41 case 4:
42 *value = inl(0xCFC);
43 break;
44 }
45
d19f61f0 46 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
1da177e4
LT		 47
48 return 0;
49}
50
b6ce068a 51static int pci_conf1_write(unsigned int seg, unsigned int bus,
1da177e4
LT		 52 unsigned int devfn, int reg, int len, u32 value)
53{
54 unsigned long flags;
55
db34a363 56 if (seg || (bus > 255) || (devfn > 255) || (reg > 4095))
1da177e4
LT		 57 return -EINVAL;
58
d19f61f0 59 raw_spin_lock_irqsave(&pci_config_lock, flags);
1da177e4
LT		 60
61 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
62
63 switch (len) {
64 case 1:
65 outb((u8)value, 0xCFC + (reg & 3));
66 break;
67 case 2:
68 outw((u16)value, 0xCFC + (reg & 2));
69 break;
70 case 4:
71 outl((u32)value, 0xCFC);
72 break;
73 }
74
d19f61f0 75 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
1da177e4
LT		 76
77 return 0;
78}
79
80#undef PCI_CONF1_ADDRESS
81
72da0b07 82const struct pci_raw_ops pci_direct_conf1 = {
1da177e4
LT		 83 .read = pci_conf1_read,
84 .write = pci_conf1_write,
85};
86
87
88/*
89 * Functions for accessing PCI configuration space with type 2 accesses
90 */
91
92#define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg)
93
94static int pci_conf2_read(unsigned int seg, unsigned int bus,
95 unsigned int devfn, int reg, int len, u32 *value)
96{
97 unsigned long flags;
98 int dev, fn;
99
db34a363 100 WARN_ON(seg);
ecc16ba9
AK		 101 if ((bus > 255) || (devfn > 255) || (reg > 255)) {
102 *value = -1;
1da177e4 103 return -EINVAL;
ecc16ba9 104 }
1da177e4
LT		 105
106 dev = PCI_SLOT(devfn);
107 fn = PCI_FUNC(devfn);
108
109 if (dev & 0x10)
110 return PCIBIOS_DEVICE_NOT_FOUND;
111
d19f61f0 112 raw_spin_lock_irqsave(&pci_config_lock, flags);
1da177e4
LT		 113
114 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
115 outb((u8)bus, 0xCFA);
116
117 switch (len) {
118 case 1:
119 *value = inb(PCI_CONF2_ADDRESS(dev, reg));
120 break;
121 case 2:
122 *value = inw(PCI_CONF2_ADDRESS(dev, reg));
123 break;
124 case 4:
125 *value = inl(PCI_CONF2_ADDRESS(dev, reg));
126 break;
127 }
128
129 outb(0, 0xCF8);
130
d19f61f0 131 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
1da177e4
LT		 132
133 return 0;
134}
135
136static int pci_conf2_write(unsigned int seg, unsigned int bus,
137 unsigned int devfn, int reg, int len, u32 value)
138{
139 unsigned long flags;
140 int dev, fn;
141
db34a363 142 WARN_ON(seg);
1da177e4
LT		 143 if ((bus > 255) || (devfn > 255) || (reg > 255))
144 return -EINVAL;
145
146 dev = PCI_SLOT(devfn);
147 fn = PCI_FUNC(devfn);
148
149 if (dev & 0x10)
150 return PCIBIOS_DEVICE_NOT_FOUND;
151
d19f61f0 152 raw_spin_lock_irqsave(&pci_config_lock, flags);
1da177e4
LT		 153
154 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
155 outb((u8)bus, 0xCFA);
156
157 switch (len) {
158 case 1:
159 outb((u8)value, PCI_CONF2_ADDRESS(dev, reg));
160 break;
161 case 2:
162 outw((u16)value, PCI_CONF2_ADDRESS(dev, reg));
163 break;
164 case 4:
165 outl((u32)value, PCI_CONF2_ADDRESS(dev, reg));
166 break;
167 }
168
169 outb(0, 0xCF8);
170
d19f61f0 171 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
1da177e4
LT		 172
173 return 0;
174}
175
176#undef PCI_CONF2_ADDRESS
177
72da0b07 178static const struct pci_raw_ops pci_direct_conf2 = {
1da177e4
LT		 179 .read = pci_conf2_read,
180 .write = pci_conf2_write,
181};
182
183
184/*
185 * Before we decide to use direct hardware access mechanisms, we try to do some
186 * trivial checks to ensure it at least _seems_ to be working -- we just test
187 * whether bus 00 contains a host bridge (this is similar to checking
188 * techniques used in XFree86, but ours should be more reliable since we
189 * attempt to make use of direct access hints provided by the PCI BIOS).
190 *
191 * This should be close to trivial, but it isn't, because there are buggy
192 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
193 */
72da0b07 194static int __init pci_sanity_check(const struct pci_raw_ops *o)
1da177e4
LT		 195{
196 u32 x = 0;
3e5cd1f2 197 int year, devfn;
1da177e4
LT		 198
199 if (pci_probe & PCI_NO_CHECKS)
200 return 1;
ec0f08ee
AK		 201 /* Assume Type 1 works for newer systems.
202 This handles machines that don't have anything on PCI Bus 0. */
3e5cd1f2
TH		 203 dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL);
204 if (year >= 2001)
ec0f08ee 205 return 1;
1da177e4
LT		 206
207 for (devfn = 0; devfn < 0x100; devfn++) {
208 if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x))
209 continue;
210 if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)
211 return 1;
212
213 if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x))
214 continue;
215 if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)
216 return 1;
217 }
218