[deliverable/linux.git] / arch / x86 / platform / intel-mid / pwr.c

/*
 * Intel MID Power Management Unit (PWRMU) device driver
 *
 * Copyright (C) 2016, Intel Corporation
 *
 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * Intel MID Power Management Unit device driver handles the South Complex PCI
 * devices such as GPDMA, SPI, I2C, PWM, and so on. By default PCI core
 * modifies bits in PMCSR register in the PCI configuration space. This is not
 * enough on some SoCs like Intel Tangier. In such case PCI core sets a new
 * power state of the device in question through a PM hook registered in struct
 * pci_platform_pm_ops (see drivers/pci/pci-mid.c).
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/mutex.h>
#include <linux/pci.h>

#include <asm/intel-mid.h>

/* Registers */
#define PM_STS			0x00
#define PM_CMD			0x04
#define PM_ICS			0x08
#define PM_WKC(x)		(0x10 + (x) * 4)
#define PM_WKS(x)		(0x18 + (x) * 4)
#define PM_SSC(x)		(0x20 + (x) * 4)
#define PM_SSS(x)		(0x30 + (x) * 4)

/* Bits in PM_STS */
#define PM_STS_BUSY		(1 << 8)

/* Bits in PM_CMD */
#define PM_CMD_CMD(x)		((x) << 0)
#define PM_CMD_IOC		(1 << 8)
#define PM_CMD_CM_NOP		(0 << 9)
#define PM_CMD_CM_IMMEDIATE	(1 << 9)
#define PM_CMD_CM_DELAY		(2 << 9)
#define PM_CMD_CM_TRIGGER	(3 << 9)
#define PM_CMD_D3cold		(1 << 21)

/* List of commands */
#define CMD_SET_CFG		0x01

/* Bits in PM_ICS */
#define PM_ICS_INT_STATUS(x)	((x) & 0xff)
#define PM_ICS_IE		(1 << 8)
#define PM_ICS_IP		(1 << 9)
#define PM_ICS_SW_INT_STS	(1 << 10)

/* List of interrupts */
#define INT_INVALID		0
#define INT_CMD_COMPLETE	1
#define INT_CMD_ERR		2
#define INT_WAKE_EVENT		3
#define INT_LSS_POWER_ERR	4
#define INT_S0iX_MSG_ERR	5
#define INT_NO_C6		6
#define INT_TRIGGER_ERR		7
#define INT_INACTIVITY		8

/* South Complex devices */
#define LSS_MAX_SHARED_DEVS	4
#define LSS_MAX_DEVS		64

#define LSS_WS_BITS		1	/* wake state width */
#define LSS_PWS_BITS		2	/* power state width */

/* Supported device IDs */
#define PCI_DEVICE_ID_PENWELL	0x0828
#define PCI_DEVICE_ID_TANGIER	0x11a1

struct mid_pwr_dev {
	struct pci_dev *pdev;
	pci_power_t state;
};

struct mid_pwr {
	struct device *dev;
	void __iomem *regs;
	int irq;
	bool available;

	struct mutex lock;
	struct mid_pwr_dev lss[LSS_MAX_DEVS][LSS_MAX_SHARED_DEVS];
};

static struct mid_pwr *midpwr;

static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg)
{
	return readl(pwr->regs + PM_SSS(reg));
}

static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value)
{
	writel(value, pwr->regs + PM_SSC(reg));
}

static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value)
{
	writel(value, pwr->regs + PM_WKC(reg));
}

static void mid_pwr_interrupt_disable(struct mid_pwr *pwr)
{
	writel(~PM_ICS_IE, pwr->regs + PM_ICS);
}

static bool mid_pwr_is_busy(struct mid_pwr *pwr)
{
	return !!(readl(pwr->regs + PM_STS) & PM_STS_BUSY);
}

/* Wait 500ms that the latest PWRMU command finished */
static int mid_pwr_wait(struct mid_pwr *pwr)
{
	unsigned int count = 500000;
	bool busy;

	do {
		busy = mid_pwr_is_busy(pwr);
		if (!busy)
			return 0;
		udelay(1);
	} while (--count);

	return -EBUSY;
}

static int mid_pwr_wait_for_cmd(struct mid_pwr *pwr, u8 cmd)
{
	writel(PM_CMD_CMD(cmd) | PM_CMD_CM_IMMEDIATE, pwr->regs + PM_CMD);
	return mid_pwr_wait(pwr);
}

static int __update_power_state(struct mid_pwr *pwr, int reg, int bit, int new)
{
	int curstate;
	u32 power;
	int ret;

	/* Check if the device is already in desired state */
	power = mid_pwr_get_state(pwr, reg);
	curstate = (power >> bit) & 3;
	if (curstate == new)
		return 0;

	/* Update the power state */
	mid_pwr_set_state(pwr, reg, (power & ~(3 << bit)) | (new << bit));

	/* Send command to SCU */
	ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
	if (ret)
		return ret;

	/* Check if the device is already in desired state */
	power = mid_pwr_get_state(pwr, reg);
	curstate = (power >> bit) & 3;
	if (curstate != new)
		return -EAGAIN;

	return 0;
}

static pci_power_t __find_weakest_power_state(struct mid_pwr_dev *lss,
					      struct pci_dev *pdev,
					      pci_power_t state)
{
	pci_power_t weakest = PCI_D3hot;
	unsigned int j;

	/* Find device in cache or first free cell */
	for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
		if (lss[j].pdev == pdev || !lss[j].pdev)
			break;
	}

	/* Store the desired state in cache */
	if (j < LSS_MAX_SHARED_DEVS) {
		lss[j].pdev = pdev;
		lss[j].state = state;
	} else {
		dev_WARN(&pdev->dev, "No room for device in PWRMU LSS cache\n");
		weakest = state;
	}

	/* Find the power state we may use */
	for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
		if (lss[j].state < weakest)
			weakest = lss[j].state;
	}

	return weakest;
}

static int __set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
			     pci_power_t state, int id, int reg, int bit)
{
	const char *name;
	int ret;

	state = __find_weakest_power_state(pwr->lss[id], pdev, state);
	name = pci_power_name(state);

	ret = __update_power_state(pwr, reg, bit, (__force int)state);
	if (ret) {
		dev_warn(&pdev->dev, "Can't set power state %s: %d\n", name, ret);
		return ret;
	}

	dev_vdbg(&pdev->dev, "Set power state %s\n", name);
	return 0;
}

static int mid_pwr_set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
				   pci_power_t state)
{
	int id, reg, bit;
	int ret;

	id = intel_mid_pwr_get_lss_id(pdev);
	if (id < 0)
		return id;

	reg = (id * LSS_PWS_BITS) / 32;
	bit = (id * LSS_PWS_BITS) % 32;

	/* We support states between PCI_D0 and PCI_D3hot */
	if (state < PCI_D0)
		state = PCI_D0;
	if (state > PCI_D3hot)
		state = PCI_D3hot;

	mutex_lock(&pwr->lock);
	ret = __set_power_state(pwr, pdev, state, id, reg, bit);
	mutex_unlock(&pwr->lock);
	return ret;
}

int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
{
	struct mid_pwr *pwr = midpwr;
	int ret = 0;

	might_sleep();

	if (pwr && pwr->available)
		ret = mid_pwr_set_power_state(pwr, pdev, state);
	dev_vdbg(&pdev->dev, "set_power_state() returns %d\n", ret);

	return 0;
}
EXPORT_SYMBOL_GPL(intel_mid_pci_set_power_state);

int intel_mid_pwr_get_lss_id(struct pci_dev *pdev)
{
	int vndr;
	u8 id;

	/*
	 * Mapping to PWRMU index is kept in the Logical SubSystem ID byte of
	 * Vendor capability.
	 */
	vndr = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
	if (!vndr)
		return -EINVAL;

	/* Read the Logical SubSystem ID byte */
	pci_read_config_byte(pdev, vndr + INTEL_MID_PWR_LSS_OFFSET, &id);
	if (!(id & INTEL_MID_PWR_LSS_TYPE))
		return -ENODEV;

	id &= ~INTEL_MID_PWR_LSS_TYPE;
	if (id >= LSS_MAX_DEVS)
		return -ERANGE;

	return id;
}

static irqreturn_t mid_pwr_irq_handler(int irq, void *dev_id)
{
	struct mid_pwr *pwr = dev_id;
	u32 ics;

	ics = readl(pwr->regs + PM_ICS);
	if (!(ics & PM_ICS_IP))
		return IRQ_NONE;

	writel(ics | PM_ICS_IP, pwr->regs + PM_ICS);

	dev_warn(pwr->dev, "Unexpected IRQ: %#x\n", PM_ICS_INT_STATUS(ics));
	return IRQ_HANDLED;
}

struct mid_pwr_device_info {
	int (*set_initial_state)(struct mid_pwr *pwr);
};

static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	struct mid_pwr_device_info *info = (void *)id->driver_data;
	struct device *dev = &pdev->dev;
	struct mid_pwr *pwr;
	int ret;

	ret = pcim_enable_device(pdev);
	if (ret < 0) {
		dev_err(&pdev->dev, "error: could not enable device\n");
		return ret;
	}

	ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
	if (ret) {
		dev_err(&pdev->dev, "I/O memory remapping failed\n");
		return ret;
	}

	pwr = devm_kzalloc(dev, sizeof(*pwr), GFP_KERNEL);
	if (!pwr)
		return -ENOMEM;

	pwr->dev = dev;
	pwr->regs = pcim_iomap_table(pdev)[0];
	pwr->irq = pdev->irq;

	mutex_init(&pwr->lock);

	/* Disable interrupts */
	mid_pwr_interrupt_disable(pwr);

	if (info && info->set_initial_state) {
		ret = info->set_initial_state(pwr);
		if (ret)
			dev_warn(dev, "Can't set initial state: %d\n", ret);
	}

	ret = devm_request_irq(dev, pdev->irq, mid_pwr_irq_handler,
			       IRQF_NO_SUSPEND, pci_name(pdev), pwr);
	if (ret)
		return ret;

	pwr->available = true;
	midpwr = pwr;

	pci_set_drvdata(pdev, pwr);
	return 0;
}

static int mid_set_initial_state(struct mid_pwr *pwr)
{
	unsigned int i, j;
	int ret;

	/*
	 * Enable wake events.
	 *
	 * PWRMU supports up to 32 sources for wake up the system. Ungate them
	 * all here.
	 */
	mid_pwr_set_wake(pwr, 0, 0xffffffff);
	mid_pwr_set_wake(pwr, 1, 0xffffffff);

	/*
	 * Power off South Complex devices.
	 *
	 * There is a map (see a note below) of 64 devices with 2 bits per each
	 * on 32-bit HW registers. The following calls set all devices to one
	 * known initial state, i.e. PCI_D3hot. This is done in conjunction
	 * with PMCSR setting in arch/x86/pci/intel_mid_pci.c.
	 *
	 * NOTE: The actual device mapping is provided by a platform at run
	 * time using vendor capability of PCI configuration space.
	 */
	mid_pwr_set_state(pwr, 0, 0xffffffff);
	mid_pwr_set_state(pwr, 1, 0xffffffff);
	mid_pwr_set_state(pwr, 2, 0xffffffff);
	mid_pwr_set_state(pwr, 3, 0xffffffff);

	/* Send command to SCU */
	ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
	if (ret)
		return ret;

	for (i = 0; i < LSS_MAX_DEVS; i++) {
		for (j = 0; j < LSS_MAX_SHARED_DEVS; j++)
			pwr->lss[i][j].state = PCI_D3hot;
	}

	return 0;
}

static const struct mid_pwr_device_info mid_info = {
	.set_initial_state = mid_set_initial_state,
};

static const struct pci_device_id mid_pwr_pci_ids[] = {
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
	{}
};

static struct pci_driver mid_pwr_pci_driver = {
	.name		= "intel_mid_pwr",
	.probe		= mid_pwr_probe,
	.id_table	= mid_pwr_pci_ids,
};

builtin_pci_driver(mid_pwr_pci_driver);
Commit	Line	Data
5823d089 AS	1	/*
	2	* Intel MID Power Management Unit (PWRMU) device driver
	3	*
	4	* Copyright (C) 2016, Intel Corporation
	5	*
	6	* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2, as published by the Free Software Foundation.
	11	*
	12	* Intel MID Power Management Unit device driver handles the South Complex PCI
	13	* devices such as GPDMA, SPI, I2C, PWM, and so on. By default PCI core
	14	* modifies bits in PMCSR register in the PCI configuration space. This is not
	15	* enough on some SoCs like Intel Tangier. In such case PCI core sets a new
	16	* power state of the device in question through a PM hook registered in struct
	17	* pci_platform_pm_ops (see drivers/pci/pci-mid.c).
	18	*/
	19
	20	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	21
	22	#include <linux/delay.h>
	23	#include <linux/errno.h>
5823d089 AS	24	#include <linux/interrupt.h>
5823d089 AS	25	#include <linux/kernel.h>
cc3ae7b0	26	#include <linux/export.h>
5823d089 AS	27	#include <linux/mutex.h>
	28	#include <linux/pci.h>
	29
	30	#include <asm/intel-mid.h>
	31
	32	/* Registers */
	33	#define PM_STS 0x00
	34	#define PM_CMD 0x04
	35	#define PM_ICS 0x08
	36	#define PM_WKC(x) (0x10 + (x) * 4)
	37	#define PM_WKS(x) (0x18 + (x) * 4)
	38	#define PM_SSC(x) (0x20 + (x) * 4)
	39	#define PM_SSS(x) (0x30 + (x) * 4)
	40
	41	/* Bits in PM_STS */
	42	#define PM_STS_BUSY (1 << 8)
	43
	44	/* Bits in PM_CMD */
	45	#define PM_CMD_CMD(x) ((x) << 0)
	46	#define PM_CMD_IOC (1 << 8)
70b5b18f AS	47	#define PM_CMD_CM_NOP (0 << 9)
	48	#define PM_CMD_CM_IMMEDIATE (1 << 9)
	49	#define PM_CMD_CM_DELAY (2 << 9)
	50	#define PM_CMD_CM_TRIGGER (3 << 9)
5823d089 AS	51	#define PM_CMD_D3cold (1 << 21)
	52
	53	/* List of commands */
	54	#define CMD_SET_CFG 0x01
	55
	56	/* Bits in PM_ICS */
	57	#define PM_ICS_INT_STATUS(x) ((x) & 0xff)
	58	#define PM_ICS_IE (1 << 8)
	59	#define PM_ICS_IP (1 << 9)
	60	#define PM_ICS_SW_INT_STS (1 << 10)
	61
	62	/* List of interrupts */
	63	#define INT_INVALID 0
	64	#define INT_CMD_COMPLETE 1
	65	#define INT_CMD_ERR 2
	66	#define INT_WAKE_EVENT 3
	67	#define INT_LSS_POWER_ERR 4
	68	#define INT_S0iX_MSG_ERR 5
	69	#define INT_NO_C6 6
	70	#define INT_TRIGGER_ERR 7
	71	#define INT_INACTIVITY 8
	72
	73	/* South Complex devices */
	74	#define LSS_MAX_SHARED_DEVS 4
	75	#define LSS_MAX_DEVS 64
	76
	77	#define LSS_WS_BITS 1 /* wake state width */
	78	#define LSS_PWS_BITS 2 /* power state width */
	79
	80	/* Supported device IDs */
ca22312d	81	#define PCI_DEVICE_ID_PENWELL 0x0828
5823d089 AS	82	#define PCI_DEVICE_ID_TANGIER 0x11a1
	83
	84	struct mid_pwr_dev {
	85	struct pci_dev *pdev;
	86	pci_power_t state;
	87	};
	88
	89	struct mid_pwr {
	90	struct device *dev;
	91	void __iomem *regs;
	92	int irq;
	93	bool available;
	94
	95	struct mutex lock;
	96	struct mid_pwr_dev lss[LSS_MAX_DEVS][LSS_MAX_SHARED_DEVS];
	97	};
	98
	99	static struct mid_pwr *midpwr;
	100
	101	static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg)
	102	{
	103	return readl(pwr->regs + PM_SSS(reg));
	104	}
	105
	106	static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value)
	107	{
	108	writel(value, pwr->regs + PM_SSC(reg));
	109	}
	110
	111	static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value)
	112	{
	113	writel(value, pwr->regs + PM_WKC(reg));
	114	}
	115
	116	static void mid_pwr_interrupt_disable(struct mid_pwr *pwr)
	117	{
	118	writel(~PM_ICS_IE, pwr->regs + PM_ICS);
	119	}
	120
	121	static bool mid_pwr_is_busy(struct mid_pwr *pwr)
	122	{
	123	return !!(readl(pwr->regs + PM_STS) & PM_STS_BUSY);
	124	}
	125
	126	/* Wait 500ms that the latest PWRMU command finished */
	127	static int mid_pwr_wait(struct mid_pwr *pwr)
	128	{
	129	unsigned int count = 500000;
	130	bool busy;
	131
	132	do {
	133	busy = mid_pwr_is_busy(pwr);
	134	if (!busy)
	135	return 0;
	136	udelay(1);
	137	} while (--count);
	138
	139	return -EBUSY;
	140	}
	141
	142	static int mid_pwr_wait_for_cmd(struct mid_pwr *pwr, u8 cmd)
	143	{
70b5b18f	144	writel(PM_CMD_CMD(cmd) \| PM_CMD_CM_IMMEDIATE, pwr->regs + PM_CMD);
5823d089 AS	145	return mid_pwr_wait(pwr);
	146	}
	147
	148	static int __update_power_state(struct mid_pwr *pwr, int reg, int bit, int new)
	149	{
	150	int curstate;
	151	u32 power;
	152	int ret;
	153
	154	/* Check if the device is already in desired state */
	155	power = mid_pwr_get_state(pwr, reg);
	156	curstate = (power >> bit) & 3;
	157	if (curstate == new)
	158	return 0;
	159
	160	/* Update the power state */
	161	mid_pwr_set_state(pwr, reg, (power & ~(3 << bit)) \| (new << bit));
	162
	163	/* Send command to SCU */
	164	ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
	165	if (ret)
	166	return ret;
	167
	168	/* Check if the device is already in desired state */
	169	power = mid_pwr_get_state(pwr, reg);
	170	curstate = (power >> bit) & 3;
	171	if (curstate != new)
	172	return -EAGAIN;
	173
	174	return 0;
	175	}
	176
	177	static pci_power_t __find_weakest_power_state(struct mid_pwr_dev *lss,
	178	struct pci_dev *pdev,
	179	pci_power_t state)
	180	{
	181	pci_power_t weakest = PCI_D3hot;
	182	unsigned int j;
	183
	184	/* Find device in cache or first free cell */
	185	for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
	186	if (lss[j].pdev == pdev \|\| !lss[j].pdev)
	187	break;
	188	}
	189
	190	/* Store the desired state in cache */
	191	if (j < LSS_MAX_SHARED_DEVS) {
	192	lss[j].pdev = pdev;
	193	lss[j].state = state;
	194	} else {
	195	dev_WARN(&pdev->dev, "No room for device in PWRMU LSS cache\n");
	196	weakest = state;
	197	}
	198
	199	/* Find the power state we may use */
	200	for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
	201	if (lss[j].state < weakest)
	202	weakest = lss[j].state;
	203	}
	204
	205	return weakest;
	206	}
	207
	208	static int __set_power_state(struct mid_pwr pwr, struct pci_dev pdev,
209	pci_power_t state, int id, int reg, int bit)
210	{
211	const char *name;
212	int ret;
213
214	state = __find_weakest_power_state(pwr->lss[id], pdev, state);
215	name = pci_power_name(state);
216
217	ret = __update_power_state(pwr, reg, bit, (__force int)state);
218	if (ret) {
219	dev_warn(&pdev->dev, "Can't set power state %s: %d\n", name, ret);
220	return ret;
221	}
222
223	dev_vdbg(&pdev->dev, "Set power state %s\n", name);
224	return 0;
225	}
226
227	static int mid_pwr_set_power_state(struct mid_pwr pwr, struct pci_dev pdev,
228	pci_power_t state)
229	{
230	int id, reg, bit;
231	int ret;
232
233	id = intel_mid_pwr_get_lss_id(pdev);
234	if (id < 0)
235	return id;
236
237	reg = (id * LSS_PWS_BITS) / 32;
238	bit = (id * LSS_PWS_BITS) % 32;
239
240	/* We support states between PCI_D0 and PCI_D3hot */
241	if (state < PCI_D0)
242	state = PCI_D0;
243	if (state > PCI_D3hot)
244	state = PCI_D3hot;
245
246	mutex_lock(&pwr->lock);
247	ret = __set_power_state(pwr, pdev, state, id, reg, bit);
248	mutex_unlock(&pwr->lock);
249	return ret;
250	}
251
252	int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
253	{
254	struct mid_pwr *pwr = midpwr;
255	int ret = 0;
256
257	might_sleep();
258
259	if (pwr && pwr->available)
260	ret = mid_pwr_set_power_state(pwr, pdev, state);
261	dev_vdbg(&pdev->dev, "set_power_state() returns %d\n", ret);
262
263	return 0;
264	}
265	EXPORT_SYMBOL_GPL(intel_mid_pci_set_power_state);
266
267	int intel_mid_pwr_get_lss_id(struct pci_dev *pdev)
268	{
269	int vndr;
270	u8 id;
271
272	/*
273	* Mapping to PWRMU index is kept in the Logical SubSystem ID byte of
274	* Vendor capability.
275	*/
276	vndr = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
277	if (!vndr)
278	return -EINVAL;
279
280	/* Read the Logical SubSystem ID byte */
281	pci_read_config_byte(pdev, vndr + INTEL_MID_PWR_LSS_OFFSET, &id);
282	if (!(id & INTEL_MID_PWR_LSS_TYPE))
283	return -ENODEV;
284
285	id &= ~INTEL_MID_PWR_LSS_TYPE;
286	if (id >= LSS_MAX_DEVS)
287	return -ERANGE;
288
289	return id;
290	}
291
292	static irqreturn_t mid_pwr_irq_handler(int irq, void *dev_id)
293	{
294	struct mid_pwr *pwr = dev_id;
295	u32 ics;
296
297	ics = readl(pwr->regs + PM_ICS);
298	if (!(ics & PM_ICS_IP))
299	return IRQ_NONE;
300
301	writel(ics \| PM_ICS_IP, pwr->regs + PM_ICS);
302
303	dev_warn(pwr->dev, "Unexpected IRQ: %#x\n", PM_ICS_INT_STATUS(ics));
304	return IRQ_HANDLED;
305	}
306
307	struct mid_pwr_device_info {
308	int (set_initial_state)(struct mid_pwr pwr);
309	};
310
311	static int mid_pwr_probe(struct pci_dev pdev, const struct pci_device_id id)
312	{
313	struct mid_pwr_device_info info = (void )id->driver_data;
314	struct device *dev = &pdev->dev;
315	struct mid_pwr *pwr;
316	int ret;
317
318	ret = pcim_enable_device(pdev);
319	if (ret < 0) {
320	dev_err(&pdev->dev, "error: could not enable device\n");
321	return ret;
322	}
323
324	ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
325	if (ret) {
326	dev_err(&pdev->dev, "I/O memory remapping failed\n");
327	return ret;
328	}
329
330	pwr = devm_kzalloc(dev, sizeof(*pwr), GFP_KERNEL);
331	if (!pwr)
332	return -ENOMEM;
333
334	pwr->dev = dev;
335	pwr->regs = pcim_iomap_table(pdev)[0];
336	pwr->irq = pdev->irq;
337
338	mutex_init(&pwr->lock);
339
340	/* Disable interrupts */
341	mid_pwr_interrupt_disable(pwr);
342
343	if (info && info->set_initial_state) {
344	ret = info->set_initial_state(pwr);
345	if (ret)
346	dev_warn(dev, "Can't set initial state: %d\n", ret);
347	}
348
349	ret = devm_request_irq(dev, pdev->irq, mid_pwr_irq_handler,
350	IRQF_NO_SUSPEND, pci_name(pdev), pwr);
351	if (ret)
352	return ret;
353
354	pwr->available = true;
355	midpwr = pwr;
356
357	pci_set_drvdata(pdev, pwr);
358	return 0;
359	}
360
ca22312d	361	static int mid_set_initial_state(struct mid_pwr *pwr)
5823d089 AS	362	{
	363	unsigned int i, j;
	364	int ret;
	365
	366	/*
	367	* Enable wake events.
	368	*
	369	* PWRMU supports up to 32 sources for wake up the system. Ungate them
	370	* all here.
	371	*/
	372	mid_pwr_set_wake(pwr, 0, 0xffffffff);
	373	mid_pwr_set_wake(pwr, 1, 0xffffffff);
	374
	375	/*
	376	* Power off South Complex devices.
	377	*
	378	* There is a map (see a note below) of 64 devices with 2 bits per each
	379	* on 32-bit HW registers. The following calls set all devices to one
	380	* known initial state, i.e. PCI_D3hot. This is done in conjunction
	381	* with PMCSR setting in arch/x86/pci/intel_mid_pci.c.
	382	*
	383	* NOTE: The actual device mapping is provided by a platform at run
	384	* time using vendor capability of PCI configuration space.
	385	*/
	386	mid_pwr_set_state(pwr, 0, 0xffffffff);
	387	mid_pwr_set_state(pwr, 1, 0xffffffff);
	388	mid_pwr_set_state(pwr, 2, 0xffffffff);
	389	mid_pwr_set_state(pwr, 3, 0xffffffff);
	390
	391	/* Send command to SCU */
	392	ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
	393	if (ret)
	394	return ret;
	395
	396	for (i = 0; i < LSS_MAX_DEVS; i++) {
	397	for (j = 0; j < LSS_MAX_SHARED_DEVS; j++)
	398	pwr->lss[i][j].state = PCI_D3hot;
	399	}
	400
	401	return 0;
	402	}
	403
ca22312d AS	404	static const struct mid_pwr_device_info mid_info = {
ca22312d AS	405	.set_initial_state = mid_set_initial_state,
5823d089 AS	406	};
	407
	408	static const struct pci_device_id mid_pwr_pci_ids[] = {
ca22312d AS	409	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
ca22312d AS	410	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
5823d089 AS	411	{}
5823d089 AS	412	};
5823d089 AS	413
	414	static struct pci_driver mid_pwr_pci_driver = {
	415	.name = "intel_mid_pwr",
	416	.probe = mid_pwr_probe,
	417	.id_table = mid_pwr_pci_ids,
	418	};
	419
	420	builtin_pci_driver(mid_pwr_pci_driver);