Commit | Line | Data |
---|---|---|
1812924b CW |
1 | /* |
2 | * SGI UltraViolet TLB flush routines. | |
3 | * | |
f073cc8f | 4 | * (c) 2008-2011 Cliff Wickman <cpw@sgi.com>, SGI. |
1812924b CW |
5 | * |
6 | * This code is released under the GNU General Public License version 2 or | |
7 | * later. | |
8 | */ | |
aef8f5b8 | 9 | #include <linux/seq_file.h> |
1812924b | 10 | #include <linux/proc_fs.h> |
e8e5e8a8 | 11 | #include <linux/debugfs.h> |
1812924b | 12 | #include <linux/kernel.h> |
5a0e3ad6 | 13 | #include <linux/slab.h> |
ca444564 | 14 | #include <linux/delay.h> |
1812924b | 15 | |
1812924b | 16 | #include <asm/mmu_context.h> |
bdbcdd48 | 17 | #include <asm/uv/uv.h> |
1812924b | 18 | #include <asm/uv/uv_mmrs.h> |
b4c286e6 | 19 | #include <asm/uv/uv_hub.h> |
1812924b | 20 | #include <asm/uv/uv_bau.h> |
7b6aa335 | 21 | #include <asm/apic.h> |
b4c286e6 | 22 | #include <asm/idle.h> |
b194b120 | 23 | #include <asm/tsc.h> |
99dd8713 | 24 | #include <asm/irq_vectors.h> |
b8f7fb13 | 25 | #include <asm/timer.h> |
1812924b | 26 | |
12a6611f CW |
27 | /* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */ |
28 | static int timeout_base_ns[] = { | |
29 | 20, | |
30 | 160, | |
31 | 1280, | |
32 | 10240, | |
33 | 81920, | |
34 | 655360, | |
35 | 5242880, | |
36 | 167772160 | |
37 | }; | |
f073cc8f | 38 | |
12a6611f | 39 | static int timeout_us; |
e8e5e8a8 | 40 | static int nobau; |
50fb55ac CW |
41 | static int baudisabled; |
42 | static spinlock_t disable_lock; | |
43 | static cycles_t congested_cycles; | |
12a6611f | 44 | |
e8e5e8a8 | 45 | /* tunables: */ |
f073cc8f CW |
46 | static int max_concurr = MAX_BAU_CONCURRENT; |
47 | static int max_concurr_const = MAX_BAU_CONCURRENT; | |
48 | static int plugged_delay = PLUGGED_DELAY; | |
49 | static int plugsb4reset = PLUGSB4RESET; | |
50 | static int timeoutsb4reset = TIMEOUTSB4RESET; | |
51 | static int ipi_reset_limit = IPI_RESET_LIMIT; | |
52 | static int complete_threshold = COMPLETE_THRESHOLD; | |
53 | static int congested_respns_us = CONGESTED_RESPONSE_US; | |
54 | static int congested_reps = CONGESTED_REPS; | |
55 | static int congested_period = CONGESTED_PERIOD; | |
56 | ||
57 | static struct tunables tunables[] = { | |
58 | {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */ | |
59 | {&plugged_delay, PLUGGED_DELAY}, | |
60 | {&plugsb4reset, PLUGSB4RESET}, | |
61 | {&timeoutsb4reset, TIMEOUTSB4RESET}, | |
62 | {&ipi_reset_limit, IPI_RESET_LIMIT}, | |
63 | {&complete_threshold, COMPLETE_THRESHOLD}, | |
64 | {&congested_respns_us, CONGESTED_RESPONSE_US}, | |
65 | {&congested_reps, CONGESTED_REPS}, | |
66 | {&congested_period, CONGESTED_PERIOD} | |
67 | }; | |
68 | ||
e8e5e8a8 CW |
69 | static struct dentry *tunables_dir; |
70 | static struct dentry *tunables_file; | |
b4c286e6 | 71 | |
f073cc8f CW |
72 | /* these correspond to the statistics printed by ptc_seq_show() */ |
73 | static char *stat_description[] = { | |
74 | "sent: number of shootdown messages sent", | |
75 | "stime: time spent sending messages", | |
76 | "numuvhubs: number of hubs targeted with shootdown", | |
77 | "numuvhubs16: number times 16 or more hubs targeted", | |
78 | "numuvhubs8: number times 8 or more hubs targeted", | |
79 | "numuvhubs4: number times 4 or more hubs targeted", | |
80 | "numuvhubs2: number times 2 or more hubs targeted", | |
81 | "numuvhubs1: number times 1 hub targeted", | |
82 | "numcpus: number of cpus targeted with shootdown", | |
83 | "dto: number of destination timeouts", | |
84 | "retries: destination timeout retries sent", | |
85 | "rok: : destination timeouts successfully retried", | |
86 | "resetp: ipi-style resource resets for plugs", | |
87 | "resett: ipi-style resource resets for timeouts", | |
88 | "giveup: fall-backs to ipi-style shootdowns", | |
89 | "sto: number of source timeouts", | |
90 | "bz: number of stay-busy's", | |
91 | "throt: number times spun in throttle", | |
92 | "swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE", | |
93 | "recv: shootdown messages received", | |
94 | "rtime: time spent processing messages", | |
95 | "all: shootdown all-tlb messages", | |
96 | "one: shootdown one-tlb messages", | |
97 | "mult: interrupts that found multiple messages", | |
98 | "none: interrupts that found no messages", | |
99 | "retry: number of retry messages processed", | |
100 | "canc: number messages canceled by retries", | |
101 | "nocan: number retries that found nothing to cancel", | |
102 | "reset: number of ipi-style reset requests processed", | |
103 | "rcan: number messages canceled by reset requests", | |
104 | "disable: number times use of the BAU was disabled", | |
105 | "enable: number times use of the BAU was re-enabled" | |
106 | }; | |
107 | ||
108 | static int __init | |
109 | setup_nobau(char *arg) | |
b8f7fb13 CW |
110 | { |
111 | nobau = 1; | |
112 | return 0; | |
113 | } | |
114 | early_param("nobau", setup_nobau); | |
b4c286e6 | 115 | |
b8f7fb13 | 116 | /* base pnode in this partition */ |
f073cc8f | 117 | static int uv_base_pnode __read_mostly; |
1812924b | 118 | |
dc163a41 IM |
119 | static DEFINE_PER_CPU(struct ptc_stats, ptcstats); |
120 | static DEFINE_PER_CPU(struct bau_control, bau_control); | |
b8f7fb13 CW |
121 | static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask); |
122 | ||
9674f35b | 123 | /* |
b8f7fb13 CW |
124 | * Determine the first node on a uvhub. 'Nodes' are used for kernel |
125 | * memory allocation. | |
9674f35b | 126 | */ |
b8f7fb13 | 127 | static int __init uvhub_to_first_node(int uvhub) |
9674f35b CW |
128 | { |
129 | int node, b; | |
130 | ||
131 | for_each_online_node(node) { | |
132 | b = uv_node_to_blade_id(node); | |
b8f7fb13 | 133 | if (uvhub == b) |
9674f35b CW |
134 | return node; |
135 | } | |
b8f7fb13 | 136 | return -1; |
9674f35b CW |
137 | } |
138 | ||
139 | /* | |
b8f7fb13 | 140 | * Determine the apicid of the first cpu on a uvhub. |
9674f35b | 141 | */ |
b8f7fb13 | 142 | static int __init uvhub_to_first_apicid(int uvhub) |
9674f35b CW |
143 | { |
144 | int cpu; | |
145 | ||
146 | for_each_present_cpu(cpu) | |
b8f7fb13 | 147 | if (uvhub == uv_cpu_to_blade_id(cpu)) |
9674f35b CW |
148 | return per_cpu(x86_cpu_to_apicid, cpu); |
149 | return -1; | |
150 | } | |
151 | ||
1812924b CW |
152 | /* |
153 | * Free a software acknowledge hardware resource by clearing its Pending | |
154 | * bit. This will return a reply to the sender. | |
155 | * If the message has timed out, a reply has already been sent by the | |
156 | * hardware but the resource has not been released. In that case our | |
157 | * clear of the Timeout bit (as well) will free the resource. No reply will | |
158 | * be sent (the hardware will only do one reply per message). | |
159 | */ | |
f073cc8f | 160 | static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp) |
1812924b | 161 | { |
b194b120 | 162 | unsigned long dw; |
f073cc8f | 163 | struct bau_pq_entry *msg; |
1812924b | 164 | |
b8f7fb13 CW |
165 | msg = mdp->msg; |
166 | if (!msg->canceled) { | |
f073cc8f CW |
167 | dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec; |
168 | write_mmr_sw_ack(dw); | |
b8f7fb13 | 169 | } |
1812924b | 170 | msg->replied_to = 1; |
f073cc8f | 171 | msg->swack_vec = 0; |
1812924b CW |
172 | } |
173 | ||
174 | /* | |
b8f7fb13 | 175 | * Process the receipt of a RETRY message |
1812924b | 176 | */ |
f073cc8f CW |
177 | static void bau_process_retry_msg(struct msg_desc *mdp, |
178 | struct bau_control *bcp) | |
1812924b | 179 | { |
b8f7fb13 CW |
180 | int i; |
181 | int cancel_count = 0; | |
b8f7fb13 CW |
182 | unsigned long msg_res; |
183 | unsigned long mmr = 0; | |
f073cc8f CW |
184 | struct bau_pq_entry *msg = mdp->msg; |
185 | struct bau_pq_entry *msg2; | |
186 | struct ptc_stats *stat = bcp->statp; | |
1812924b | 187 | |
b8f7fb13 CW |
188 | stat->d_retries++; |
189 | /* | |
190 | * cancel any message from msg+1 to the retry itself | |
191 | */ | |
192 | for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) { | |
f073cc8f CW |
193 | if (msg2 > mdp->queue_last) |
194 | msg2 = mdp->queue_first; | |
b8f7fb13 CW |
195 | if (msg2 == msg) |
196 | break; | |
197 | ||
f073cc8f | 198 | /* same conditions for cancellation as do_reset */ |
b8f7fb13 | 199 | if ((msg2->replied_to == 0) && (msg2->canceled == 0) && |
f073cc8f CW |
200 | (msg2->swack_vec) && ((msg2->swack_vec & |
201 | msg->swack_vec) == 0) && | |
b8f7fb13 CW |
202 | (msg2->sending_cpu == msg->sending_cpu) && |
203 | (msg2->msg_type != MSG_NOOP)) { | |
f073cc8f CW |
204 | mmr = read_mmr_sw_ack(); |
205 | msg_res = msg2->swack_vec; | |
b8f7fb13 CW |
206 | /* |
207 | * This is a message retry; clear the resources held | |
208 | * by the previous message only if they timed out. | |
209 | * If it has not timed out we have an unexpected | |
210 | * situation to report. | |
211 | */ | |
39847e7f | 212 | if (mmr & (msg_res << UV_SW_ACK_NPENDING)) { |
f073cc8f | 213 | unsigned long mr; |
b8f7fb13 CW |
214 | /* |
215 | * is the resource timed out? | |
216 | * make everyone ignore the cancelled message. | |
217 | */ | |
218 | msg2->canceled = 1; | |
219 | stat->d_canceled++; | |
220 | cancel_count++; | |
f073cc8f CW |
221 | mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res; |
222 | write_mmr_sw_ack(mr); | |
39847e7f | 223 | } |
b8f7fb13 CW |
224 | } |
225 | } | |
226 | if (!cancel_count) | |
227 | stat->d_nocanceled++; | |
228 | } | |
1812924b | 229 | |
b8f7fb13 CW |
230 | /* |
231 | * Do all the things a cpu should do for a TLB shootdown message. | |
232 | * Other cpu's may come here at the same time for this message. | |
233 | */ | |
f073cc8f CW |
234 | static void bau_process_message(struct msg_desc *mdp, |
235 | struct bau_control *bcp) | |
b8f7fb13 | 236 | { |
b8f7fb13 | 237 | short socket_ack_count = 0; |
f073cc8f CW |
238 | short *sp; |
239 | struct atomic_short *asp; | |
240 | struct ptc_stats *stat = bcp->statp; | |
241 | struct bau_pq_entry *msg = mdp->msg; | |
b8f7fb13 | 242 | struct bau_control *smaster = bcp->socket_master; |
1812924b | 243 | |
b8f7fb13 CW |
244 | /* |
245 | * This must be a normal message, or retry of a normal message | |
246 | */ | |
1812924b CW |
247 | if (msg->address == TLB_FLUSH_ALL) { |
248 | local_flush_tlb(); | |
b8f7fb13 | 249 | stat->d_alltlb++; |
1812924b CW |
250 | } else { |
251 | __flush_tlb_one(msg->address); | |
b8f7fb13 | 252 | stat->d_onetlb++; |
1812924b | 253 | } |
b8f7fb13 CW |
254 | stat->d_requestee++; |
255 | ||
256 | /* | |
257 | * One cpu on each uvhub has the additional job on a RETRY | |
258 | * of releasing the resource held by the message that is | |
259 | * being retried. That message is identified by sending | |
260 | * cpu number. | |
261 | */ | |
262 | if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master) | |
f073cc8f | 263 | bau_process_retry_msg(mdp, bcp); |
1812924b | 264 | |
b8f7fb13 | 265 | /* |
f073cc8f | 266 | * This is a swack message, so we have to reply to it. |
b8f7fb13 CW |
267 | * Count each responding cpu on the socket. This avoids |
268 | * pinging the count's cache line back and forth between | |
269 | * the sockets. | |
270 | */ | |
f073cc8f CW |
271 | sp = &smaster->socket_acknowledge_count[mdp->msg_slot]; |
272 | asp = (struct atomic_short *)sp; | |
273 | socket_ack_count = atom_asr(1, asp); | |
b8f7fb13 | 274 | if (socket_ack_count == bcp->cpus_in_socket) { |
f073cc8f | 275 | int msg_ack_count; |
b8f7fb13 CW |
276 | /* |
277 | * Both sockets dump their completed count total into | |
278 | * the message's count. | |
279 | */ | |
280 | smaster->socket_acknowledge_count[mdp->msg_slot] = 0; | |
f073cc8f CW |
281 | asp = (struct atomic_short *)&msg->acknowledge_count; |
282 | msg_ack_count = atom_asr(socket_ack_count, asp); | |
b8f7fb13 CW |
283 | |
284 | if (msg_ack_count == bcp->cpus_in_uvhub) { | |
285 | /* | |
286 | * All cpus in uvhub saw it; reply | |
287 | */ | |
f073cc8f | 288 | reply_to_message(mdp, bcp); |
b8f7fb13 CW |
289 | } |
290 | } | |
1812924b | 291 | |
b8f7fb13 | 292 | return; |
1812924b CW |
293 | } |
294 | ||
295 | /* | |
485f07d3 | 296 | * Determine the first cpu on a pnode. |
b8f7fb13 | 297 | */ |
485f07d3 | 298 | static int pnode_to_first_cpu(int pnode, struct bau_control *smaster) |
b8f7fb13 CW |
299 | { |
300 | int cpu; | |
485f07d3 | 301 | struct hub_and_pnode *hpp; |
302 | ||
303 | for_each_present_cpu(cpu) { | |
304 | hpp = &smaster->thp[cpu]; | |
305 | if (pnode == hpp->pnode) | |
b8f7fb13 | 306 | return cpu; |
485f07d3 | 307 | } |
b8f7fb13 CW |
308 | return -1; |
309 | } | |
310 | ||
311 | /* | |
312 | * Last resort when we get a large number of destination timeouts is | |
313 | * to clear resources held by a given cpu. | |
314 | * Do this with IPI so that all messages in the BAU message queue | |
f073cc8f | 315 | * can be identified by their nonzero swack_vec field. |
1812924b | 316 | * |
b8f7fb13 CW |
317 | * This is entered for a single cpu on the uvhub. |
318 | * The sender want's this uvhub to free a specific message's | |
f073cc8f | 319 | * swack resources. |
1812924b | 320 | */ |
f073cc8f | 321 | static void do_reset(void *ptr) |
1812924b | 322 | { |
b4c286e6 | 323 | int i; |
f073cc8f CW |
324 | struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id()); |
325 | struct reset_args *rap = (struct reset_args *)ptr; | |
326 | struct bau_pq_entry *msg; | |
327 | struct ptc_stats *stat = bcp->statp; | |
1812924b | 328 | |
b8f7fb13 | 329 | stat->d_resets++; |
b8f7fb13 CW |
330 | /* |
331 | * We're looking for the given sender, and | |
f073cc8f | 332 | * will free its swack resource. |
b8f7fb13 CW |
333 | * If all cpu's finally responded after the timeout, its |
334 | * message 'replied_to' was set. | |
335 | */ | |
f073cc8f CW |
336 | for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) { |
337 | unsigned long msg_res; | |
338 | /* do_reset: same conditions for cancellation as | |
339 | bau_process_retry_msg() */ | |
b8f7fb13 CW |
340 | if ((msg->replied_to == 0) && |
341 | (msg->canceled == 0) && | |
342 | (msg->sending_cpu == rap->sender) && | |
f073cc8f | 343 | (msg->swack_vec) && |
b8f7fb13 | 344 | (msg->msg_type != MSG_NOOP)) { |
f073cc8f CW |
345 | unsigned long mmr; |
346 | unsigned long mr; | |
b8f7fb13 CW |
347 | /* |
348 | * make everyone else ignore this message | |
349 | */ | |
350 | msg->canceled = 1; | |
b8f7fb13 CW |
351 | /* |
352 | * only reset the resource if it is still pending | |
353 | */ | |
f073cc8f CW |
354 | mmr = read_mmr_sw_ack(); |
355 | msg_res = msg->swack_vec; | |
356 | mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res; | |
b8f7fb13 CW |
357 | if (mmr & msg_res) { |
358 | stat->d_rcanceled++; | |
f073cc8f | 359 | write_mmr_sw_ack(mr); |
dc163a41 | 360 | } |
dc163a41 IM |
361 | } |
362 | } | |
b8f7fb13 | 363 | return; |
dc163a41 IM |
364 | } |
365 | ||
366 | /* | |
b8f7fb13 CW |
367 | * Use IPI to get all target uvhubs to release resources held by |
368 | * a given sending cpu number. | |
dc163a41 | 369 | */ |
a456eaab | 370 | static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp) |
dc163a41 | 371 | { |
485f07d3 | 372 | int pnode; |
373 | int apnode; | |
f073cc8f | 374 | int maskbits; |
485f07d3 | 375 | int sender = bcp->cpu; |
442d3924 | 376 | cpumask_t *mask = bcp->uvhub_master->cpumask; |
485f07d3 | 377 | struct bau_control *smaster = bcp->socket_master; |
b8f7fb13 | 378 | struct reset_args reset_args; |
dc163a41 | 379 | |
b8f7fb13 | 380 | reset_args.sender = sender; |
442d3924 | 381 | cpus_clear(*mask); |
b8f7fb13 | 382 | /* find a single cpu for each uvhub in this distribution mask */ |
a456eaab | 383 | maskbits = sizeof(struct pnmask) * BITSPERBYTE; |
485f07d3 | 384 | /* each bit is a pnode relative to the partition base pnode */ |
385 | for (pnode = 0; pnode < maskbits; pnode++) { | |
f073cc8f | 386 | int cpu; |
485f07d3 | 387 | if (!bau_uvhub_isset(pnode, distribution)) |
b194b120 | 388 | continue; |
485f07d3 | 389 | apnode = pnode + bcp->partition_base_pnode; |
390 | cpu = pnode_to_first_cpu(apnode, smaster); | |
442d3924 | 391 | cpu_set(cpu, *mask); |
1812924b | 392 | } |
f073cc8f CW |
393 | |
394 | /* IPI all cpus; preemption is already disabled */ | |
442d3924 | 395 | smp_call_function_many(mask, do_reset, (void *)&reset_args, 1); |
b8f7fb13 CW |
396 | return; |
397 | } | |
398 | ||
f073cc8f | 399 | static inline unsigned long cycles_2_us(unsigned long long cyc) |
b8f7fb13 CW |
400 | { |
401 | unsigned long long ns; | |
402 | unsigned long us; | |
f073cc8f CW |
403 | int cpu = smp_processor_id(); |
404 | ||
405 | ns = (cyc * per_cpu(cyc2ns, cpu)) >> CYC2NS_SCALE_FACTOR; | |
b8f7fb13 CW |
406 | us = ns / 1000; |
407 | return us; | |
1812924b CW |
408 | } |
409 | ||
b194b120 | 410 | /* |
b8f7fb13 CW |
411 | * wait for all cpus on this hub to finish their sends and go quiet |
412 | * leaves uvhub_quiesce set so that no new broadcasts are started by | |
413 | * bau_flush_send_and_wait() | |
414 | */ | |
f073cc8f | 415 | static inline void quiesce_local_uvhub(struct bau_control *hmaster) |
b8f7fb13 | 416 | { |
f073cc8f | 417 | atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce); |
b8f7fb13 CW |
418 | } |
419 | ||
420 | /* | |
421 | * mark this quiet-requestor as done | |
422 | */ | |
f073cc8f | 423 | static inline void end_uvhub_quiesce(struct bau_control *hmaster) |
b8f7fb13 | 424 | { |
f073cc8f CW |
425 | atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce); |
426 | } | |
427 | ||
428 | static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift) | |
429 | { | |
430 | unsigned long descriptor_status; | |
431 | ||
432 | descriptor_status = uv_read_local_mmr(mmr_offset); | |
433 | descriptor_status >>= right_shift; | |
434 | descriptor_status &= UV_ACT_STATUS_MASK; | |
435 | return descriptor_status; | |
b8f7fb13 CW |
436 | } |
437 | ||
438 | /* | |
439 | * Wait for completion of a broadcast software ack message | |
440 | * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP | |
b194b120 | 441 | */ |
2a919596 | 442 | static int uv1_wait_completion(struct bau_desc *bau_desc, |
f073cc8f CW |
443 | unsigned long mmr_offset, int right_shift, |
444 | struct bau_control *bcp, long try) | |
b194b120 | 445 | { |
b194b120 | 446 | unsigned long descriptor_status; |
f073cc8f | 447 | cycles_t ttm; |
712157aa | 448 | struct ptc_stats *stat = bcp->statp; |
b194b120 | 449 | |
f073cc8f | 450 | descriptor_status = uv1_read_status(mmr_offset, right_shift); |
b8f7fb13 | 451 | /* spin on the status MMR, waiting for it to go idle */ |
f073cc8f | 452 | while ((descriptor_status != DS_IDLE)) { |
b194b120 | 453 | /* |
2a919596 JS |
454 | * Our software ack messages may be blocked because |
455 | * there are no swack resources available. As long | |
456 | * as none of them has timed out hardware will NACK | |
457 | * our message and its state will stay IDLE. | |
b194b120 | 458 | */ |
f073cc8f | 459 | if (descriptor_status == DS_SOURCE_TIMEOUT) { |
b8f7fb13 CW |
460 | stat->s_stimeout++; |
461 | return FLUSH_GIVEUP; | |
f073cc8f | 462 | } else if (descriptor_status == DS_DESTINATION_TIMEOUT) { |
2a919596 | 463 | stat->s_dtimeout++; |
f073cc8f | 464 | ttm = get_cycles(); |
2a919596 JS |
465 | |
466 | /* | |
467 | * Our retries may be blocked by all destination | |
468 | * swack resources being consumed, and a timeout | |
469 | * pending. In that case hardware returns the | |
470 | * ERROR that looks like a destination timeout. | |
471 | */ | |
f073cc8f | 472 | if (cycles_2_us(ttm - bcp->send_message) < timeout_us) { |
2a919596 JS |
473 | bcp->conseccompletes = 0; |
474 | return FLUSH_RETRY_PLUGGED; | |
475 | } | |
476 | ||
477 | bcp->conseccompletes = 0; | |
478 | return FLUSH_RETRY_TIMEOUT; | |
479 | } else { | |
480 | /* | |
481 | * descriptor_status is still BUSY | |
482 | */ | |
483 | cpu_relax(); | |
484 | } | |
f073cc8f | 485 | descriptor_status = uv1_read_status(mmr_offset, right_shift); |
2a919596 JS |
486 | } |
487 | bcp->conseccompletes++; | |
488 | return FLUSH_COMPLETE; | |
489 | } | |
490 | ||
f073cc8f CW |
491 | /* |
492 | * UV2 has an extra bit of status in the ACTIVATION_STATUS_2 register. | |
493 | */ | |
494 | static unsigned long uv2_read_status(unsigned long offset, int rshft, int cpu) | |
2a919596 JS |
495 | { |
496 | unsigned long descriptor_status; | |
497 | unsigned long descriptor_status2; | |
f073cc8f CW |
498 | |
499 | descriptor_status = ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK); | |
500 | descriptor_status2 = (read_mmr_uv2_status() >> cpu) & 0x1UL; | |
501 | descriptor_status = (descriptor_status << 1) | descriptor_status2; | |
502 | return descriptor_status; | |
503 | } | |
504 | ||
505 | static int uv2_wait_completion(struct bau_desc *bau_desc, | |
506 | unsigned long mmr_offset, int right_shift, | |
507 | struct bau_control *bcp, long try) | |
508 | { | |
509 | unsigned long descriptor_stat; | |
510 | cycles_t ttm; | |
511 | int cpu = bcp->uvhub_cpu; | |
2a919596 JS |
512 | struct ptc_stats *stat = bcp->statp; |
513 | ||
f073cc8f CW |
514 | descriptor_stat = uv2_read_status(mmr_offset, right_shift, cpu); |
515 | ||
2a919596 | 516 | /* spin on the status MMR, waiting for it to go idle */ |
f073cc8f | 517 | while (descriptor_stat != UV2H_DESC_IDLE) { |
2a919596 JS |
518 | /* |
519 | * Our software ack messages may be blocked because | |
520 | * there are no swack resources available. As long | |
521 | * as none of them has timed out hardware will NACK | |
522 | * our message and its state will stay IDLE. | |
523 | */ | |
f073cc8f CW |
524 | if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT) || |
525 | (descriptor_stat == UV2H_DESC_DEST_STRONG_NACK) || | |
526 | (descriptor_stat == UV2H_DESC_DEST_PUT_ERR)) { | |
2a919596 JS |
527 | stat->s_stimeout++; |
528 | return FLUSH_GIVEUP; | |
f073cc8f | 529 | } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) { |
b8f7fb13 | 530 | stat->s_dtimeout++; |
f073cc8f | 531 | ttm = get_cycles(); |
b8f7fb13 CW |
532 | /* |
533 | * Our retries may be blocked by all destination | |
534 | * swack resources being consumed, and a timeout | |
535 | * pending. In that case hardware returns the | |
536 | * ERROR that looks like a destination timeout. | |
537 | */ | |
f073cc8f | 538 | if (cycles_2_us(ttm - bcp->send_message) < timeout_us) { |
b8f7fb13 CW |
539 | bcp->conseccompletes = 0; |
540 | return FLUSH_RETRY_PLUGGED; | |
541 | } | |
b8f7fb13 CW |
542 | bcp->conseccompletes = 0; |
543 | return FLUSH_RETRY_TIMEOUT; | |
544 | } else { | |
545 | /* | |
f073cc8f | 546 | * descriptor_stat is still BUSY |
b8f7fb13 CW |
547 | */ |
548 | cpu_relax(); | |
b194b120 | 549 | } |
f073cc8f | 550 | descriptor_stat = uv2_read_status(mmr_offset, right_shift, cpu); |
b194b120 | 551 | } |
b8f7fb13 | 552 | bcp->conseccompletes++; |
b194b120 CW |
553 | return FLUSH_COMPLETE; |
554 | } | |
555 | ||
f073cc8f CW |
556 | /* |
557 | * There are 2 status registers; each and array[32] of 2 bits. Set up for | |
558 | * which register to read and position in that register based on cpu in | |
559 | * current hub. | |
560 | */ | |
561 | static int wait_completion(struct bau_desc *bau_desc, | |
562 | struct bau_control *bcp, long try) | |
2a919596 | 563 | { |
f073cc8f CW |
564 | int right_shift; |
565 | unsigned long mmr_offset; | |
566 | int cpu = bcp->uvhub_cpu; | |
567 | ||
568 | if (cpu < UV_CPUS_PER_AS) { | |
569 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; | |
570 | right_shift = cpu * UV_ACT_STATUS_SIZE; | |
571 | } else { | |
572 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1; | |
573 | right_shift = ((cpu - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE); | |
574 | } | |
575 | ||
2a919596 JS |
576 | if (is_uv1_hub()) |
577 | return uv1_wait_completion(bau_desc, mmr_offset, right_shift, | |
f073cc8f | 578 | bcp, try); |
2a919596 JS |
579 | else |
580 | return uv2_wait_completion(bau_desc, mmr_offset, right_shift, | |
f073cc8f | 581 | bcp, try); |
2a919596 JS |
582 | } |
583 | ||
f073cc8f | 584 | static inline cycles_t sec_2_cycles(unsigned long sec) |
b8f7fb13 CW |
585 | { |
586 | unsigned long ns; | |
587 | cycles_t cyc; | |
588 | ||
589 | ns = sec * 1000000000; | |
590 | cyc = (ns << CYC2NS_SCALE_FACTOR)/(per_cpu(cyc2ns, smp_processor_id())); | |
591 | return cyc; | |
592 | } | |
593 | ||
594 | /* | |
f073cc8f | 595 | * Our retries are blocked by all destination sw ack resources being |
f6d8a566 CW |
596 | * in use, and a timeout is pending. In that case hardware immediately |
597 | * returns the ERROR that looks like a destination timeout. | |
598 | */ | |
f073cc8f CW |
599 | static void destination_plugged(struct bau_desc *bau_desc, |
600 | struct bau_control *bcp, | |
f6d8a566 CW |
601 | struct bau_control *hmaster, struct ptc_stats *stat) |
602 | { | |
603 | udelay(bcp->plugged_delay); | |
604 | bcp->plugged_tries++; | |
f073cc8f | 605 | |
f6d8a566 CW |
606 | if (bcp->plugged_tries >= bcp->plugsb4reset) { |
607 | bcp->plugged_tries = 0; | |
f073cc8f | 608 | |
f6d8a566 | 609 | quiesce_local_uvhub(hmaster); |
f073cc8f | 610 | |
f6d8a566 | 611 | spin_lock(&hmaster->queue_lock); |
485f07d3 | 612 | reset_with_ipi(&bau_desc->distribution, bcp); |
f6d8a566 | 613 | spin_unlock(&hmaster->queue_lock); |
f073cc8f | 614 | |
f6d8a566 | 615 | end_uvhub_quiesce(hmaster); |
f073cc8f | 616 | |
f6d8a566 CW |
617 | bcp->ipi_attempts++; |
618 | stat->s_resets_plug++; | |
619 | } | |
620 | } | |
621 | ||
f073cc8f CW |
622 | static void destination_timeout(struct bau_desc *bau_desc, |
623 | struct bau_control *bcp, struct bau_control *hmaster, | |
624 | struct ptc_stats *stat) | |
f6d8a566 | 625 | { |
f073cc8f | 626 | hmaster->max_concurr = 1; |
f6d8a566 CW |
627 | bcp->timeout_tries++; |
628 | if (bcp->timeout_tries >= bcp->timeoutsb4reset) { | |
629 | bcp->timeout_tries = 0; | |
f073cc8f | 630 | |
f6d8a566 | 631 | quiesce_local_uvhub(hmaster); |
f073cc8f | 632 | |
f6d8a566 | 633 | spin_lock(&hmaster->queue_lock); |
485f07d3 | 634 | reset_with_ipi(&bau_desc->distribution, bcp); |
f6d8a566 | 635 | spin_unlock(&hmaster->queue_lock); |
f073cc8f | 636 | |
f6d8a566 | 637 | end_uvhub_quiesce(hmaster); |
f073cc8f | 638 | |
f6d8a566 CW |
639 | bcp->ipi_attempts++; |
640 | stat->s_resets_timeout++; | |
641 | } | |
642 | } | |
643 | ||
50fb55ac CW |
644 | /* |
645 | * Completions are taking a very long time due to a congested numalink | |
646 | * network. | |
647 | */ | |
f073cc8f CW |
648 | static void disable_for_congestion(struct bau_control *bcp, |
649 | struct ptc_stats *stat) | |
50fb55ac | 650 | { |
50fb55ac CW |
651 | /* let only one cpu do this disabling */ |
652 | spin_lock(&disable_lock); | |
f073cc8f | 653 | |
50fb55ac CW |
654 | if (!baudisabled && bcp->period_requests && |
655 | ((bcp->period_time / bcp->period_requests) > congested_cycles)) { | |
f073cc8f CW |
656 | int tcpu; |
657 | struct bau_control *tbcp; | |
50fb55ac CW |
658 | /* it becomes this cpu's job to turn on the use of the |
659 | BAU again */ | |
660 | baudisabled = 1; | |
661 | bcp->set_bau_off = 1; | |
f073cc8f CW |
662 | bcp->set_bau_on_time = get_cycles(); |
663 | bcp->set_bau_on_time += sec_2_cycles(bcp->cong_period); | |
50fb55ac CW |
664 | stat->s_bau_disabled++; |
665 | for_each_present_cpu(tcpu) { | |
666 | tbcp = &per_cpu(bau_control, tcpu); | |
f073cc8f | 667 | tbcp->baudisabled = 1; |
50fb55ac CW |
668 | } |
669 | } | |
f073cc8f | 670 | |
50fb55ac CW |
671 | spin_unlock(&disable_lock); |
672 | } | |
673 | ||
f073cc8f CW |
674 | static void count_max_concurr(int stat, struct bau_control *bcp, |
675 | struct bau_control *hmaster) | |
676 | { | |
677 | bcp->plugged_tries = 0; | |
678 | bcp->timeout_tries = 0; | |
679 | if (stat != FLUSH_COMPLETE) | |
680 | return; | |
681 | if (bcp->conseccompletes <= bcp->complete_threshold) | |
682 | return; | |
683 | if (hmaster->max_concurr >= hmaster->max_concurr_const) | |
684 | return; | |
685 | hmaster->max_concurr++; | |
686 | } | |
687 | ||
688 | static void record_send_stats(cycles_t time1, cycles_t time2, | |
689 | struct bau_control *bcp, struct ptc_stats *stat, | |
690 | int completion_status, int try) | |
691 | { | |
692 | cycles_t elapsed; | |
693 | ||
694 | if (time2 > time1) { | |
695 | elapsed = time2 - time1; | |
696 | stat->s_time += elapsed; | |
697 | ||
698 | if ((completion_status == FLUSH_COMPLETE) && (try == 1)) { | |
699 | bcp->period_requests++; | |
700 | bcp->period_time += elapsed; | |
701 | if ((elapsed > congested_cycles) && | |
702 | (bcp->period_requests > bcp->cong_reps)) | |
703 | disable_for_congestion(bcp, stat); | |
704 | } | |
705 | } else | |
706 | stat->s_requestor--; | |
707 | ||
708 | if (completion_status == FLUSH_COMPLETE && try > 1) | |
709 | stat->s_retriesok++; | |
710 | else if (completion_status == FLUSH_GIVEUP) | |
711 | stat->s_giveup++; | |
712 | } | |
713 | ||
714 | /* | |
715 | * Because of a uv1 hardware bug only a limited number of concurrent | |
716 | * requests can be made. | |
717 | */ | |
718 | static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat) | |
719 | { | |
720 | spinlock_t *lock = &hmaster->uvhub_lock; | |
721 | atomic_t *v; | |
722 | ||
723 | v = &hmaster->active_descriptor_count; | |
724 | if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) { | |
725 | stat->s_throttles++; | |
726 | do { | |
727 | cpu_relax(); | |
728 | } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)); | |
729 | } | |
730 | } | |
731 | ||
732 | /* | |
733 | * Handle the completion status of a message send. | |
734 | */ | |
735 | static void handle_cmplt(int completion_status, struct bau_desc *bau_desc, | |
736 | struct bau_control *bcp, struct bau_control *hmaster, | |
737 | struct ptc_stats *stat) | |
738 | { | |
739 | if (completion_status == FLUSH_RETRY_PLUGGED) | |
740 | destination_plugged(bau_desc, bcp, hmaster, stat); | |
741 | else if (completion_status == FLUSH_RETRY_TIMEOUT) | |
742 | destination_timeout(bau_desc, bcp, hmaster, stat); | |
743 | } | |
744 | ||
745 | /* | |
b8f7fb13 | 746 | * Send a broadcast and wait for it to complete. |
b194b120 | 747 | * |
f6d8a566 | 748 | * The flush_mask contains the cpus the broadcast is to be sent to including |
b8f7fb13 | 749 | * cpus that are on the local uvhub. |
b194b120 | 750 | * |
450a007e CW |
751 | * Returns 0 if all flushing represented in the mask was done. |
752 | * Returns 1 if it gives up entirely and the original cpu mask is to be | |
753 | * returned to the kernel. | |
b194b120 | 754 | */ |
450a007e | 755 | int uv_flush_send_and_wait(struct bau_desc *bau_desc, |
f073cc8f | 756 | struct cpumask *flush_mask, struct bau_control *bcp) |
b194b120 | 757 | { |
b8f7fb13 | 758 | int seq_number = 0; |
f073cc8f | 759 | int completion_stat = 0; |
b8f7fb13 | 760 | long try = 0; |
b4c286e6 | 761 | unsigned long index; |
b194b120 CW |
762 | cycles_t time1; |
763 | cycles_t time2; | |
712157aa | 764 | struct ptc_stats *stat = bcp->statp; |
b8f7fb13 CW |
765 | struct bau_control *hmaster = bcp->uvhub_master; |
766 | ||
f073cc8f CW |
767 | if (is_uv1_hub()) |
768 | uv1_throttle(hmaster, stat); | |
769 | ||
b8f7fb13 CW |
770 | while (hmaster->uvhub_quiesce) |
771 | cpu_relax(); | |
b194b120 | 772 | |
b194b120 CW |
773 | time1 = get_cycles(); |
774 | do { | |
b8f7fb13 | 775 | if (try == 0) { |
7fba1bcd | 776 | bau_desc->header.msg_type = MSG_REGULAR; |
b8f7fb13 CW |
777 | seq_number = bcp->message_number++; |
778 | } else { | |
b8f7fb13 CW |
779 | bau_desc->header.msg_type = MSG_RETRY; |
780 | stat->s_retry_messages++; | |
781 | } | |
f073cc8f | 782 | |
b8f7fb13 | 783 | bau_desc->header.sequence = seq_number; |
f073cc8f | 784 | index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu; |
b8f7fb13 | 785 | bcp->send_message = get_cycles(); |
f073cc8f CW |
786 | |
787 | write_mmr_activation(index); | |
788 | ||
b8f7fb13 | 789 | try++; |
f073cc8f CW |
790 | completion_stat = wait_completion(bau_desc, bcp, try); |
791 | ||
792 | handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat); | |
b8f7fb13 | 793 | |
e8e5e8a8 | 794 | if (bcp->ipi_attempts >= bcp->ipi_reset_limit) { |
b8f7fb13 | 795 | bcp->ipi_attempts = 0; |
f073cc8f | 796 | completion_stat = FLUSH_GIVEUP; |
b8f7fb13 CW |
797 | break; |
798 | } | |
799 | cpu_relax(); | |
f073cc8f CW |
800 | } while ((completion_stat == FLUSH_RETRY_PLUGGED) || |
801 | (completion_stat == FLUSH_RETRY_TIMEOUT)); | |
802 | ||
b194b120 | 803 | time2 = get_cycles(); |
f073cc8f CW |
804 | |
805 | count_max_concurr(completion_stat, bcp, hmaster); | |
806 | ||
b8f7fb13 CW |
807 | while (hmaster->uvhub_quiesce) |
808 | cpu_relax(); | |
f073cc8f | 809 | |
b8f7fb13 | 810 | atomic_dec(&hmaster->active_descriptor_count); |
f073cc8f CW |
811 | |
812 | record_send_stats(time1, time2, bcp, stat, completion_stat, try); | |
813 | ||
814 | if (completion_stat == FLUSH_GIVEUP) | |
815 | return 1; | |
816 | return 0; | |
817 | } | |
818 | ||
819 | /* | |
820 | * The BAU is disabled. When the disabled time period has expired, the cpu | |
821 | * that disabled it must re-enable it. | |
822 | * Return 0 if it is re-enabled for all cpus. | |
823 | */ | |
824 | static int check_enable(struct bau_control *bcp, struct ptc_stats *stat) | |
825 | { | |
826 | int tcpu; | |
827 | struct bau_control *tbcp; | |
828 | ||
829 | if (bcp->set_bau_off) { | |
830 | if (get_cycles() >= bcp->set_bau_on_time) { | |
831 | stat->s_bau_reenabled++; | |
832 | baudisabled = 0; | |
833 | for_each_present_cpu(tcpu) { | |
834 | tbcp = &per_cpu(bau_control, tcpu); | |
835 | tbcp->baudisabled = 0; | |
836 | tbcp->period_requests = 0; | |
837 | tbcp->period_time = 0; | |
50fb55ac | 838 | } |
f073cc8f | 839 | return 0; |
50fb55ac | 840 | } |
f073cc8f CW |
841 | } |
842 | return -1; | |
843 | } | |
844 | ||
845 | static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs, | |
846 | int remotes, struct bau_desc *bau_desc) | |
847 | { | |
848 | stat->s_requestor++; | |
849 | stat->s_ntargcpu += remotes + locals; | |
850 | stat->s_ntargremotes += remotes; | |
851 | stat->s_ntarglocals += locals; | |
852 | ||
853 | /* uvhub statistics */ | |
854 | hubs = bau_uvhub_weight(&bau_desc->distribution); | |
855 | if (locals) { | |
856 | stat->s_ntarglocaluvhub++; | |
857 | stat->s_ntargremoteuvhub += (hubs - 1); | |
e8e5e8a8 | 858 | } else |
f073cc8f CW |
859 | stat->s_ntargremoteuvhub += hubs; |
860 | ||
861 | stat->s_ntarguvhub += hubs; | |
862 | ||
863 | if (hubs >= 16) | |
864 | stat->s_ntarguvhub16++; | |
865 | else if (hubs >= 8) | |
866 | stat->s_ntarguvhub8++; | |
867 | else if (hubs >= 4) | |
868 | stat->s_ntarguvhub4++; | |
869 | else if (hubs >= 2) | |
870 | stat->s_ntarguvhub2++; | |
871 | else | |
872 | stat->s_ntarguvhub1++; | |
873 | } | |
874 | ||
875 | /* | |
876 | * Translate a cpu mask to the uvhub distribution mask in the BAU | |
877 | * activation descriptor. | |
878 | */ | |
879 | static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp, | |
880 | struct bau_desc *bau_desc, int *localsp, int *remotesp) | |
881 | { | |
882 | int cpu; | |
883 | int pnode; | |
884 | int cnt = 0; | |
885 | struct hub_and_pnode *hpp; | |
886 | ||
887 | for_each_cpu(cpu, flush_mask) { | |
888 | /* | |
889 | * The distribution vector is a bit map of pnodes, relative | |
890 | * to the partition base pnode (and the partition base nasid | |
891 | * in the header). | |
892 | * Translate cpu to pnode and hub using a local memory array. | |
893 | */ | |
894 | hpp = &bcp->socket_master->thp[cpu]; | |
895 | pnode = hpp->pnode - bcp->partition_base_pnode; | |
896 | bau_uvhub_set(pnode, &bau_desc->distribution); | |
897 | cnt++; | |
898 | if (hpp->uvhub == bcp->uvhub) | |
899 | (*localsp)++; | |
900 | else | |
901 | (*remotesp)++; | |
b194b120 | 902 | } |
f073cc8f CW |
903 | if (!cnt) |
904 | return 1; | |
450a007e | 905 | return 0; |
b194b120 CW |
906 | } |
907 | ||
f073cc8f CW |
908 | /* |
909 | * globally purge translation cache of a virtual address or all TLB's | |
bdbcdd48 | 910 | * @cpumask: mask of all cpu's in which the address is to be removed |
1812924b CW |
911 | * @mm: mm_struct containing virtual address range |
912 | * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu) | |
bdbcdd48 | 913 | * @cpu: the current cpu |
1812924b CW |
914 | * |
915 | * This is the entry point for initiating any UV global TLB shootdown. | |
916 | * | |
917 | * Purges the translation caches of all specified processors of the given | |
918 | * virtual address, or purges all TLB's on specified processors. | |
919 | * | |
bdbcdd48 TH |
920 | * The caller has derived the cpumask from the mm_struct. This function |
921 | * is called only if there are bits set in the mask. (e.g. flush_tlb_page()) | |
1812924b | 922 | * |
b8f7fb13 CW |
923 | * The cpumask is converted into a uvhubmask of the uvhubs containing |
924 | * those cpus. | |
b194b120 | 925 | * |
bdbcdd48 TH |
926 | * Note that this function should be called with preemption disabled. |
927 | * | |
928 | * Returns NULL if all remote flushing was done. | |
929 | * Returns pointer to cpumask if some remote flushing remains to be | |
930 | * done. The returned pointer is valid till preemption is re-enabled. | |
1812924b | 931 | */ |
bdbcdd48 | 932 | const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, |
f073cc8f CW |
933 | struct mm_struct *mm, unsigned long va, |
934 | unsigned int cpu) | |
1812924b | 935 | { |
b194b120 | 936 | int locals = 0; |
450a007e CW |
937 | int remotes = 0; |
938 | int hubs = 0; | |
dc163a41 | 939 | struct bau_desc *bau_desc; |
b8f7fb13 CW |
940 | struct cpumask *flush_mask; |
941 | struct ptc_stats *stat; | |
942 | struct bau_control *bcp; | |
bdbcdd48 | 943 | |
e8e5e8a8 | 944 | /* kernel was booted 'nobau' */ |
b8f7fb13 CW |
945 | if (nobau) |
946 | return cpumask; | |
bdbcdd48 | 947 | |
b8f7fb13 | 948 | bcp = &per_cpu(bau_control, cpu); |
712157aa | 949 | stat = bcp->statp; |
50fb55ac CW |
950 | |
951 | /* bau was disabled due to slow response */ | |
952 | if (bcp->baudisabled) { | |
f073cc8f CW |
953 | if (check_enable(bcp, stat)) |
954 | return cpumask; | |
50fb55ac | 955 | } |
e8e5e8a8 | 956 | |
b8f7fb13 CW |
957 | /* |
958 | * Each sending cpu has a per-cpu mask which it fills from the caller's | |
450a007e CW |
959 | * cpu mask. All cpus are converted to uvhubs and copied to the |
960 | * activation descriptor. | |
b8f7fb13 CW |
961 | */ |
962 | flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu); | |
450a007e | 963 | /* don't actually do a shootdown of the local cpu */ |
b8f7fb13 | 964 | cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu)); |
f073cc8f | 965 | |
b8f7fb13 | 966 | if (cpu_isset(cpu, *cpumask)) |
450a007e | 967 | stat->s_ntargself++; |
1812924b | 968 | |
b8f7fb13 | 969 | bau_desc = bcp->descriptor_base; |
f073cc8f | 970 | bau_desc += ITEMS_PER_DESC * bcp->uvhub_cpu; |
b8f7fb13 | 971 | bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE); |
f073cc8f | 972 | if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes)) |
450a007e | 973 | return NULL; |
450a007e | 974 | |
f073cc8f | 975 | record_send_statistics(stat, locals, hubs, remotes, bau_desc); |
1812924b CW |
976 | |
977 | bau_desc->payload.address = va; | |
bdbcdd48 | 978 | bau_desc->payload.sending_cpu = cpu; |
b8f7fb13 | 979 | /* |
450a007e CW |
980 | * uv_flush_send_and_wait returns 0 if all cpu's were messaged, |
981 | * or 1 if it gave up and the original cpumask should be returned. | |
b8f7fb13 | 982 | */ |
450a007e CW |
983 | if (!uv_flush_send_and_wait(bau_desc, flush_mask, bcp)) |
984 | return NULL; | |
985 | else | |
986 | return cpumask; | |
1812924b CW |
987 | } |
988 | ||
989 | /* | |
990 | * The BAU message interrupt comes here. (registered by set_intr_gate) | |
991 | * See entry_64.S | |
992 | * | |
993 | * We received a broadcast assist message. | |
994 | * | |
b8f7fb13 | 995 | * Interrupts are disabled; this interrupt could represent |
1812924b CW |
996 | * the receipt of several messages. |
997 | * | |
b8f7fb13 CW |
998 | * All cores/threads on this hub get this interrupt. |
999 | * The last one to see it does the software ack. | |
1812924b | 1000 | * (the resource will not be freed until noninterruptable cpus see this |
b8f7fb13 | 1001 | * interrupt; hardware may timeout the s/w ack and reply ERROR) |
1812924b | 1002 | */ |
b194b120 | 1003 | void uv_bau_message_interrupt(struct pt_regs *regs) |
1812924b | 1004 | { |
1812924b | 1005 | int count = 0; |
b8f7fb13 | 1006 | cycles_t time_start; |
f073cc8f | 1007 | struct bau_pq_entry *msg; |
b8f7fb13 CW |
1008 | struct bau_control *bcp; |
1009 | struct ptc_stats *stat; | |
1010 | struct msg_desc msgdesc; | |
1011 | ||
1012 | time_start = get_cycles(); | |
f073cc8f | 1013 | |
b8f7fb13 | 1014 | bcp = &per_cpu(bau_control, smp_processor_id()); |
712157aa | 1015 | stat = bcp->statp; |
f073cc8f CW |
1016 | |
1017 | msgdesc.queue_first = bcp->queue_first; | |
1018 | msgdesc.queue_last = bcp->queue_last; | |
1019 | ||
b8f7fb13 | 1020 | msg = bcp->bau_msg_head; |
f073cc8f | 1021 | while (msg->swack_vec) { |
1812924b | 1022 | count++; |
f073cc8f CW |
1023 | |
1024 | msgdesc.msg_slot = msg - msgdesc.queue_first; | |
1025 | msgdesc.swack_slot = ffs(msg->swack_vec) - 1; | |
b8f7fb13 | 1026 | msgdesc.msg = msg; |
f073cc8f CW |
1027 | bau_process_message(&msgdesc, bcp); |
1028 | ||
1812924b | 1029 | msg++; |
f073cc8f CW |
1030 | if (msg > msgdesc.queue_last) |
1031 | msg = msgdesc.queue_first; | |
b8f7fb13 | 1032 | bcp->bau_msg_head = msg; |
1812924b | 1033 | } |
b8f7fb13 | 1034 | stat->d_time += (get_cycles() - time_start); |
1812924b | 1035 | if (!count) |
b8f7fb13 | 1036 | stat->d_nomsg++; |
1812924b | 1037 | else if (count > 1) |
b8f7fb13 | 1038 | stat->d_multmsg++; |
f073cc8f | 1039 | |
b8f7fb13 | 1040 | ack_APIC_irq(); |
1812924b CW |
1041 | } |
1042 | ||
c4c4688f | 1043 | /* |
f073cc8f | 1044 | * Each target uvhub (i.e. a uvhub that has cpu's) needs to have |
c4c4688f CW |
1045 | * shootdown message timeouts enabled. The timeout does not cause |
1046 | * an interrupt, but causes an error message to be returned to | |
1047 | * the sender. | |
1048 | */ | |
f073cc8f | 1049 | static void __init enable_timeouts(void) |
1812924b | 1050 | { |
b8f7fb13 CW |
1051 | int uvhub; |
1052 | int nuvhubs; | |
1812924b | 1053 | int pnode; |
c4c4688f | 1054 | unsigned long mmr_image; |
1812924b | 1055 | |
b8f7fb13 | 1056 | nuvhubs = uv_num_possible_blades(); |
1812924b | 1057 | |
b8f7fb13 CW |
1058 | for (uvhub = 0; uvhub < nuvhubs; uvhub++) { |
1059 | if (!uv_blade_nr_possible_cpus(uvhub)) | |
1812924b | 1060 | continue; |
c4c4688f | 1061 | |
b8f7fb13 | 1062 | pnode = uv_blade_to_pnode(uvhub); |
f073cc8f | 1063 | mmr_image = read_mmr_misc_control(pnode); |
c4c4688f CW |
1064 | /* |
1065 | * Set the timeout period and then lock it in, in three | |
1066 | * steps; captures and locks in the period. | |
1067 | * | |
1068 | * To program the period, the SOFT_ACK_MODE must be off. | |
1069 | */ | |
f073cc8f CW |
1070 | mmr_image &= ~(1L << SOFTACK_MSHIFT); |
1071 | write_mmr_misc_control(pnode, mmr_image); | |
c4c4688f CW |
1072 | /* |
1073 | * Set the 4-bit period. | |
1074 | */ | |
f073cc8f CW |
1075 | mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT); |
1076 | mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT); | |
1077 | write_mmr_misc_control(pnode, mmr_image); | |
c4c4688f | 1078 | /* |
2a919596 | 1079 | * UV1: |
c4c4688f CW |
1080 | * Subsequent reversals of the timebase bit (3) cause an |
1081 | * immediate timeout of one or all INTD resources as | |
1082 | * indicated in bits 2:0 (7 causes all of them to timeout). | |
1083 | */ | |
f073cc8f | 1084 | mmr_image |= (1L << SOFTACK_MSHIFT); |
2a919596 | 1085 | if (is_uv2_hub()) { |
f073cc8f CW |
1086 | mmr_image |= (1L << UV2_LEG_SHFT); |
1087 | mmr_image |= (1L << UV2_EXT_SHFT); | |
2a919596 | 1088 | } |
f073cc8f | 1089 | write_mmr_misc_control(pnode, mmr_image); |
1812924b | 1090 | } |
1812924b CW |
1091 | } |
1092 | ||
f073cc8f | 1093 | static void *ptc_seq_start(struct seq_file *file, loff_t *offset) |
1812924b CW |
1094 | { |
1095 | if (*offset < num_possible_cpus()) | |
1096 | return offset; | |
1097 | return NULL; | |
1098 | } | |
1099 | ||
f073cc8f | 1100 | static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset) |
1812924b CW |
1101 | { |
1102 | (*offset)++; | |
1103 | if (*offset < num_possible_cpus()) | |
1104 | return offset; | |
1105 | return NULL; | |
1106 | } | |
1107 | ||
f073cc8f | 1108 | static void ptc_seq_stop(struct seq_file *file, void *data) |
1812924b CW |
1109 | { |
1110 | } | |
1111 | ||
f073cc8f | 1112 | static inline unsigned long long usec_2_cycles(unsigned long microsec) |
b8f7fb13 CW |
1113 | { |
1114 | unsigned long ns; | |
1115 | unsigned long long cyc; | |
1116 | ||
12a6611f | 1117 | ns = microsec * 1000; |
b8f7fb13 CW |
1118 | cyc = (ns << CYC2NS_SCALE_FACTOR)/(per_cpu(cyc2ns, smp_processor_id())); |
1119 | return cyc; | |
1120 | } | |
1121 | ||
1812924b | 1122 | /* |
f073cc8f | 1123 | * Display the statistics thru /proc/sgi_uv/ptc_statistics |
b8f7fb13 | 1124 | * 'data' points to the cpu number |
f073cc8f | 1125 | * Note: see the descriptions in stat_description[]. |
1812924b | 1126 | */ |
f073cc8f | 1127 | static int ptc_seq_show(struct seq_file *file, void *data) |
1812924b CW |
1128 | { |
1129 | struct ptc_stats *stat; | |
1130 | int cpu; | |
1131 | ||
1132 | cpu = *(loff_t *)data; | |
1812924b CW |
1133 | if (!cpu) { |
1134 | seq_printf(file, | |
450a007e CW |
1135 | "# cpu sent stime self locals remotes ncpus localhub "); |
1136 | seq_printf(file, | |
1137 | "remotehub numuvhubs numuvhubs16 numuvhubs8 "); | |
1812924b | 1138 | seq_printf(file, |
f073cc8f | 1139 | "numuvhubs4 numuvhubs2 numuvhubs1 dto retries rok "); |
b8f7fb13 | 1140 | seq_printf(file, |
f073cc8f | 1141 | "resetp resett giveup sto bz throt swack recv rtime "); |
b8f7fb13 | 1142 | seq_printf(file, |
f073cc8f | 1143 | "all one mult none retry canc nocan reset rcan "); |
50fb55ac CW |
1144 | seq_printf(file, |
1145 | "disable enable\n"); | |
1812924b CW |
1146 | } |
1147 | if (cpu < num_possible_cpus() && cpu_online(cpu)) { | |
1148 | stat = &per_cpu(ptcstats, cpu); | |
b8f7fb13 CW |
1149 | /* source side statistics */ |
1150 | seq_printf(file, | |
1151 | "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", | |
1152 | cpu, stat->s_requestor, cycles_2_us(stat->s_time), | |
450a007e CW |
1153 | stat->s_ntargself, stat->s_ntarglocals, |
1154 | stat->s_ntargremotes, stat->s_ntargcpu, | |
1155 | stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub, | |
1156 | stat->s_ntarguvhub, stat->s_ntarguvhub16); | |
1157 | seq_printf(file, "%ld %ld %ld %ld %ld ", | |
b8f7fb13 CW |
1158 | stat->s_ntarguvhub8, stat->s_ntarguvhub4, |
1159 | stat->s_ntarguvhub2, stat->s_ntarguvhub1, | |
450a007e | 1160 | stat->s_dtimeout); |
b8f7fb13 CW |
1161 | seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ", |
1162 | stat->s_retry_messages, stat->s_retriesok, | |
1163 | stat->s_resets_plug, stat->s_resets_timeout, | |
1164 | stat->s_giveup, stat->s_stimeout, | |
1165 | stat->s_busy, stat->s_throttles); | |
e8e5e8a8 | 1166 | |
b8f7fb13 CW |
1167 | /* destination side statistics */ |
1168 | seq_printf(file, | |
50fb55ac | 1169 | "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", |
f073cc8f | 1170 | read_gmmr_sw_ack(uv_cpu_to_pnode(cpu)), |
b8f7fb13 CW |
1171 | stat->d_requestee, cycles_2_us(stat->d_time), |
1172 | stat->d_alltlb, stat->d_onetlb, stat->d_multmsg, | |
1173 | stat->d_nomsg, stat->d_retries, stat->d_canceled, | |
1174 | stat->d_nocanceled, stat->d_resets, | |
1175 | stat->d_rcanceled); | |
50fb55ac CW |
1176 | seq_printf(file, "%ld %ld\n", |
1177 | stat->s_bau_disabled, stat->s_bau_reenabled); | |
1812924b | 1178 | } |
1812924b CW |
1179 | return 0; |
1180 | } | |
1181 | ||
e8e5e8a8 CW |
1182 | /* |
1183 | * Display the tunables thru debugfs | |
1184 | */ | |
1185 | static ssize_t tunables_read(struct file *file, char __user *userbuf, | |
f073cc8f | 1186 | size_t count, loff_t *ppos) |
e8e5e8a8 | 1187 | { |
b365a85c | 1188 | char *buf; |
e8e5e8a8 CW |
1189 | int ret; |
1190 | ||
b365a85c | 1191 | buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d\n", |
f073cc8f | 1192 | "max_concur plugged_delay plugsb4reset", |
e8e5e8a8 CW |
1193 | "timeoutsb4reset ipi_reset_limit complete_threshold", |
1194 | "congested_response_us congested_reps congested_period", | |
f073cc8f | 1195 | max_concurr, plugged_delay, plugsb4reset, |
e8e5e8a8 | 1196 | timeoutsb4reset, ipi_reset_limit, complete_threshold, |
f073cc8f | 1197 | congested_respns_us, congested_reps, congested_period); |
e8e5e8a8 | 1198 | |
b365a85c DC |
1199 | if (!buf) |
1200 | return -ENOMEM; | |
1201 | ||
1202 | ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); | |
1203 | kfree(buf); | |
1204 | return ret; | |
e8e5e8a8 CW |
1205 | } |
1206 | ||
1812924b | 1207 | /* |
f073cc8f CW |
1208 | * handle a write to /proc/sgi_uv/ptc_statistics |
1209 | * -1: reset the statistics | |
1812924b | 1210 | * 0: display meaning of the statistics |
1812924b | 1211 | */ |
f073cc8f CW |
1212 | static ssize_t ptc_proc_write(struct file *file, const char __user *user, |
1213 | size_t count, loff_t *data) | |
1812924b | 1214 | { |
b8f7fb13 | 1215 | int cpu; |
f073cc8f CW |
1216 | int i; |
1217 | int elements; | |
b8f7fb13 | 1218 | long input_arg; |
1812924b | 1219 | char optstr[64]; |
b8f7fb13 | 1220 | struct ptc_stats *stat; |
1812924b | 1221 | |
e7eb8726 | 1222 | if (count == 0 || count > sizeof(optstr)) |
cef53278 | 1223 | return -EINVAL; |
1812924b CW |
1224 | if (copy_from_user(optstr, user, count)) |
1225 | return -EFAULT; | |
1226 | optstr[count - 1] = '\0'; | |
f073cc8f | 1227 | |
b8f7fb13 | 1228 | if (strict_strtol(optstr, 10, &input_arg) < 0) { |
1812924b CW |
1229 | printk(KERN_DEBUG "%s is invalid\n", optstr); |
1230 | return -EINVAL; | |
1231 | } | |
1232 | ||
b8f7fb13 | 1233 | if (input_arg == 0) { |
f073cc8f | 1234 | elements = sizeof(stat_description)/sizeof(*stat_description); |
1812924b | 1235 | printk(KERN_DEBUG "# cpu: cpu number\n"); |
b8f7fb13 | 1236 | printk(KERN_DEBUG "Sender statistics:\n"); |
f073cc8f CW |
1237 | for (i = 0; i < elements; i++) |
1238 | printk(KERN_DEBUG "%s\n", stat_description[i]); | |
b8f7fb13 CW |
1239 | } else if (input_arg == -1) { |
1240 | for_each_present_cpu(cpu) { | |
1241 | stat = &per_cpu(ptcstats, cpu); | |
1242 | memset(stat, 0, sizeof(struct ptc_stats)); | |
1243 | } | |
e8e5e8a8 CW |
1244 | } |
1245 | ||
1246 | return count; | |
1247 | } | |
1248 | ||
1249 | static int local_atoi(const char *name) | |
1250 | { | |
1251 | int val = 0; | |
1252 | ||
1253 | for (;; name++) { | |
1254 | switch (*name) { | |
1255 | case '0' ... '9': | |
1256 | val = 10*val+(*name-'0'); | |
1257 | break; | |
1258 | default: | |
1259 | return val; | |
b8f7fb13 | 1260 | } |
1812924b | 1261 | } |
e8e5e8a8 CW |
1262 | } |
1263 | ||
1264 | /* | |
f073cc8f CW |
1265 | * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables. |
1266 | * Zero values reset them to defaults. | |
e8e5e8a8 | 1267 | */ |
f073cc8f CW |
1268 | static int parse_tunables_write(struct bau_control *bcp, char *instr, |
1269 | int count) | |
e8e5e8a8 | 1270 | { |
e8e5e8a8 CW |
1271 | char *p; |
1272 | char *q; | |
f073cc8f CW |
1273 | int cnt = 0; |
1274 | int val; | |
1275 | int e = sizeof(tunables) / sizeof(*tunables); | |
e8e5e8a8 | 1276 | |
e8e5e8a8 CW |
1277 | p = instr + strspn(instr, WHITESPACE); |
1278 | q = p; | |
1279 | for (; *p; p = q + strspn(q, WHITESPACE)) { | |
1280 | q = p + strcspn(p, WHITESPACE); | |
1281 | cnt++; | |
1282 | if (q == p) | |
1283 | break; | |
1284 | } | |
f073cc8f CW |
1285 | if (cnt != e) { |
1286 | printk(KERN_INFO "bau tunable error: should be %d values\n", e); | |
e8e5e8a8 CW |
1287 | return -EINVAL; |
1288 | } | |
1289 | ||
1290 | p = instr + strspn(instr, WHITESPACE); | |
1291 | q = p; | |
1292 | for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) { | |
1293 | q = p + strcspn(p, WHITESPACE); | |
1294 | val = local_atoi(p); | |
1295 | switch (cnt) { | |
1296 | case 0: | |
1297 | if (val == 0) { | |
f073cc8f CW |
1298 | max_concurr = MAX_BAU_CONCURRENT; |
1299 | max_concurr_const = MAX_BAU_CONCURRENT; | |
e8e5e8a8 CW |
1300 | continue; |
1301 | } | |
e8e5e8a8 CW |
1302 | if (val < 1 || val > bcp->cpus_in_uvhub) { |
1303 | printk(KERN_DEBUG | |
1304 | "Error: BAU max concurrent %d is invalid\n", | |
1305 | val); | |
1306 | return -EINVAL; | |
1307 | } | |
f073cc8f CW |
1308 | max_concurr = val; |
1309 | max_concurr_const = val; | |
e8e5e8a8 | 1310 | continue; |
f073cc8f | 1311 | default: |
e8e5e8a8 | 1312 | if (val == 0) |
f073cc8f | 1313 | *tunables[cnt].tunp = tunables[cnt].deflt; |
e8e5e8a8 | 1314 | else |
f073cc8f | 1315 | *tunables[cnt].tunp = val; |
e8e5e8a8 CW |
1316 | continue; |
1317 | } | |
1318 | if (q == p) | |
1319 | break; | |
1320 | } | |
f073cc8f CW |
1321 | return 0; |
1322 | } | |
1323 | ||
1324 | /* | |
1325 | * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables) | |
1326 | */ | |
1327 | static ssize_t tunables_write(struct file *file, const char __user *user, | |
1328 | size_t count, loff_t *data) | |
1329 | { | |
1330 | int cpu; | |
1331 | int ret; | |
1332 | char instr[100]; | |
1333 | struct bau_control *bcp; | |
1334 | ||
1335 | if (count == 0 || count > sizeof(instr)-1) | |
1336 | return -EINVAL; | |
1337 | if (copy_from_user(instr, user, count)) | |
1338 | return -EFAULT; | |
1339 | ||
1340 | instr[count] = '\0'; | |
1341 | ||
00b30cf0 | 1342 | cpu = get_cpu(); |
1343 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f | 1344 | ret = parse_tunables_write(bcp, instr, count); |
00b30cf0 | 1345 | put_cpu(); |
f073cc8f CW |
1346 | if (ret) |
1347 | return ret; | |
1348 | ||
e8e5e8a8 CW |
1349 | for_each_present_cpu(cpu) { |
1350 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f CW |
1351 | bcp->max_concurr = max_concurr; |
1352 | bcp->max_concurr_const = max_concurr; | |
1353 | bcp->plugged_delay = plugged_delay; | |
1354 | bcp->plugsb4reset = plugsb4reset; | |
1355 | bcp->timeoutsb4reset = timeoutsb4reset; | |
1356 | bcp->ipi_reset_limit = ipi_reset_limit; | |
1357 | bcp->complete_threshold = complete_threshold; | |
1358 | bcp->cong_response_us = congested_respns_us; | |
1359 | bcp->cong_reps = congested_reps; | |
1360 | bcp->cong_period = congested_period; | |
e8e5e8a8 | 1361 | } |
1812924b CW |
1362 | return count; |
1363 | } | |
1364 | ||
1365 | static const struct seq_operations uv_ptc_seq_ops = { | |
f073cc8f CW |
1366 | .start = ptc_seq_start, |
1367 | .next = ptc_seq_next, | |
1368 | .stop = ptc_seq_stop, | |
1369 | .show = ptc_seq_show | |
1812924b CW |
1370 | }; |
1371 | ||
f073cc8f | 1372 | static int ptc_proc_open(struct inode *inode, struct file *file) |
1812924b CW |
1373 | { |
1374 | return seq_open(file, &uv_ptc_seq_ops); | |
1375 | } | |
1376 | ||
e8e5e8a8 CW |
1377 | static int tunables_open(struct inode *inode, struct file *file) |
1378 | { | |
1379 | return 0; | |
1380 | } | |
1381 | ||
1812924b | 1382 | static const struct file_operations proc_uv_ptc_operations = { |
f073cc8f | 1383 | .open = ptc_proc_open, |
b194b120 | 1384 | .read = seq_read, |
f073cc8f | 1385 | .write = ptc_proc_write, |
b194b120 CW |
1386 | .llseek = seq_lseek, |
1387 | .release = seq_release, | |
1812924b CW |
1388 | }; |
1389 | ||
e8e5e8a8 CW |
1390 | static const struct file_operations tunables_fops = { |
1391 | .open = tunables_open, | |
1392 | .read = tunables_read, | |
1393 | .write = tunables_write, | |
6038f373 | 1394 | .llseek = default_llseek, |
e8e5e8a8 CW |
1395 | }; |
1396 | ||
b194b120 | 1397 | static int __init uv_ptc_init(void) |
1812924b | 1398 | { |
b194b120 | 1399 | struct proc_dir_entry *proc_uv_ptc; |
1812924b CW |
1400 | |
1401 | if (!is_uv_system()) | |
1402 | return 0; | |
1403 | ||
10f02d11 AD |
1404 | proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL, |
1405 | &proc_uv_ptc_operations); | |
1812924b CW |
1406 | if (!proc_uv_ptc) { |
1407 | printk(KERN_ERR "unable to create %s proc entry\n", | |
1408 | UV_PTC_BASENAME); | |
1409 | return -EINVAL; | |
1410 | } | |
e8e5e8a8 CW |
1411 | |
1412 | tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL); | |
1413 | if (!tunables_dir) { | |
1414 | printk(KERN_ERR "unable to create debugfs directory %s\n", | |
1415 | UV_BAU_TUNABLES_DIR); | |
1416 | return -EINVAL; | |
1417 | } | |
1418 | tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600, | |
f073cc8f | 1419 | tunables_dir, NULL, &tunables_fops); |
e8e5e8a8 CW |
1420 | if (!tunables_file) { |
1421 | printk(KERN_ERR "unable to create debugfs file %s\n", | |
1422 | UV_BAU_TUNABLES_FILE); | |
1423 | return -EINVAL; | |
1424 | } | |
1812924b CW |
1425 | return 0; |
1426 | } | |
1427 | ||
1812924b | 1428 | /* |
77ed23f8 | 1429 | * Initialize the sending side's sending buffers. |
1812924b | 1430 | */ |
f073cc8f | 1431 | static void activation_descriptor_init(int node, int pnode, int base_pnode) |
1812924b CW |
1432 | { |
1433 | int i; | |
b8f7fb13 | 1434 | int cpu; |
6a469e46 | 1435 | unsigned long gpa; |
1812924b | 1436 | unsigned long m; |
b194b120 | 1437 | unsigned long n; |
f073cc8f | 1438 | size_t dsize; |
b8f7fb13 CW |
1439 | struct bau_desc *bau_desc; |
1440 | struct bau_desc *bd2; | |
1441 | struct bau_control *bcp; | |
b194b120 | 1442 | |
0e2595cd | 1443 | /* |
f073cc8f CW |
1444 | * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC) |
1445 | * per cpu; and one per cpu on the uvhub (ADP_SZ) | |
0e2595cd | 1446 | */ |
f073cc8f CW |
1447 | dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC; |
1448 | bau_desc = kmalloc_node(dsize, GFP_KERNEL, node); | |
b8f7fb13 | 1449 | BUG_ON(!bau_desc); |
b4c286e6 | 1450 | |
6a469e46 JS |
1451 | gpa = uv_gpa(bau_desc); |
1452 | n = uv_gpa_to_gnode(gpa); | |
1453 | m = uv_gpa_to_offset(gpa); | |
b4c286e6 | 1454 | |
77ed23f8 | 1455 | /* the 14-bit pnode */ |
f073cc8f | 1456 | write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m)); |
0e2595cd | 1457 | /* |
f073cc8f | 1458 | * Initializing all 8 (ITEMS_PER_DESC) descriptors for each |
0e2595cd | 1459 | * cpu even though we only use the first one; one descriptor can |
b8f7fb13 | 1460 | * describe a broadcast to 256 uv hubs. |
0e2595cd | 1461 | */ |
f073cc8f | 1462 | for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) { |
b8f7fb13 | 1463 | memset(bd2, 0, sizeof(struct bau_desc)); |
f073cc8f | 1464 | bd2->header.swack_flag = 1; |
94ca8e48 | 1465 | /* |
77ed23f8 CW |
1466 | * The base_dest_nasid set in the message header is the nasid |
1467 | * of the first uvhub in the partition. The bit map will | |
1468 | * indicate destination pnode numbers relative to that base. | |
1469 | * They may not be consecutive if nasid striding is being used. | |
94ca8e48 | 1470 | */ |
f073cc8f CW |
1471 | bd2->header.base_dest_nasid = UV_PNODE_TO_NASID(base_pnode); |
1472 | bd2->header.dest_subnodeid = UV_LB_SUBNODEID; | |
1473 | bd2->header.command = UV_NET_ENDPOINT_INTD; | |
1474 | bd2->header.int_both = 1; | |
b194b120 CW |
1475 | /* |
1476 | * all others need to be set to zero: | |
1477 | * fairness chaining multilevel count replied_to | |
1478 | */ | |
1479 | } | |
b8f7fb13 CW |
1480 | for_each_present_cpu(cpu) { |
1481 | if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu))) | |
1482 | continue; | |
1483 | bcp = &per_cpu(bau_control, cpu); | |
1484 | bcp->descriptor_base = bau_desc; | |
1485 | } | |
b194b120 CW |
1486 | } |
1487 | ||
1488 | /* | |
1489 | * initialize the destination side's receiving buffers | |
b8f7fb13 CW |
1490 | * entered for each uvhub in the partition |
1491 | * - node is first node (kernel memory notion) on the uvhub | |
1492 | * - pnode is the uvhub's physical identifier | |
b194b120 | 1493 | */ |
f073cc8f | 1494 | static void pq_init(int node, int pnode) |
b194b120 | 1495 | { |
b8f7fb13 | 1496 | int cpu; |
f073cc8f | 1497 | size_t plsize; |
b4c286e6 | 1498 | char *cp; |
f073cc8f CW |
1499 | void *vp; |
1500 | unsigned long pn; | |
1501 | unsigned long first; | |
1502 | unsigned long pn_first; | |
1503 | unsigned long last; | |
1504 | struct bau_pq_entry *pqp; | |
b8f7fb13 | 1505 | struct bau_control *bcp; |
1812924b | 1506 | |
f073cc8f CW |
1507 | plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry); |
1508 | vp = kmalloc_node(plsize, GFP_KERNEL, node); | |
1509 | pqp = (struct bau_pq_entry *)vp; | |
dc163a41 | 1510 | BUG_ON(!pqp); |
b4c286e6 | 1511 | |
b194b120 | 1512 | cp = (char *)pqp + 31; |
f073cc8f | 1513 | pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5); |
b8f7fb13 CW |
1514 | |
1515 | for_each_present_cpu(cpu) { | |
1516 | if (pnode != uv_cpu_to_pnode(cpu)) | |
1517 | continue; | |
1518 | /* for every cpu on this pnode: */ | |
1519 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f CW |
1520 | bcp->queue_first = pqp; |
1521 | bcp->bau_msg_head = pqp; | |
1522 | bcp->queue_last = pqp + (DEST_Q_SIZE - 1); | |
b8f7fb13 | 1523 | } |
4ea3c51d | 1524 | /* |
6a469e46 | 1525 | * need the gnode of where the memory was really allocated |
4ea3c51d | 1526 | */ |
6a469e46 | 1527 | pn = uv_gpa_to_gnode(uv_gpa(pqp)); |
f073cc8f CW |
1528 | first = uv_physnodeaddr(pqp); |
1529 | pn_first = ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) | first; | |
1530 | last = uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1)); | |
1531 | write_mmr_payload_first(pnode, pn_first); | |
1532 | write_mmr_payload_tail(pnode, first); | |
1533 | write_mmr_payload_last(pnode, last); | |
1534 | ||
b8f7fb13 | 1535 | /* in effect, all msg_type's are set to MSG_NOOP */ |
f073cc8f | 1536 | memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE); |
b194b120 | 1537 | } |
1812924b | 1538 | |
b194b120 | 1539 | /* |
b8f7fb13 | 1540 | * Initialization of each UV hub's structures |
b194b120 | 1541 | */ |
f073cc8f | 1542 | static void __init init_uvhub(int uvhub, int vector, int base_pnode) |
b194b120 | 1543 | { |
9674f35b | 1544 | int node; |
b194b120 | 1545 | int pnode; |
b194b120 | 1546 | unsigned long apicid; |
b8f7fb13 CW |
1547 | |
1548 | node = uvhub_to_first_node(uvhub); | |
1549 | pnode = uv_blade_to_pnode(uvhub); | |
f073cc8f CW |
1550 | |
1551 | activation_descriptor_init(node, pnode, base_pnode); | |
1552 | ||
1553 | pq_init(node, pnode); | |
b194b120 | 1554 | /* |
77ed23f8 CW |
1555 | * The below initialization can't be in firmware because the |
1556 | * messaging IRQ will be determined by the OS. | |
b194b120 | 1557 | */ |
8191c9f6 | 1558 | apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits; |
f073cc8f | 1559 | write_mmr_data_config(pnode, ((apicid << 32) | vector)); |
b8f7fb13 CW |
1560 | } |
1561 | ||
12a6611f CW |
1562 | /* |
1563 | * We will set BAU_MISC_CONTROL with a timeout period. | |
1564 | * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT. | |
f073cc8f | 1565 | * So the destination timeout period has to be calculated from them. |
12a6611f | 1566 | */ |
f073cc8f | 1567 | static int calculate_destination_timeout(void) |
12a6611f CW |
1568 | { |
1569 | unsigned long mmr_image; | |
1570 | int mult1; | |
1571 | int mult2; | |
1572 | int index; | |
1573 | int base; | |
1574 | int ret; | |
1575 | unsigned long ts_ns; | |
1576 | ||
2a919596 | 1577 | if (is_uv1_hub()) { |
f073cc8f | 1578 | mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK; |
2a919596 JS |
1579 | mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL); |
1580 | index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK; | |
1581 | mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT); | |
1582 | mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK; | |
1583 | base = timeout_base_ns[index]; | |
1584 | ts_ns = base * mult1 * mult2; | |
1585 | ret = ts_ns / 1000; | |
1586 | } else { | |
1587 | /* 4 bits 0/1 for 10/80us, 3 bits of multiplier */ | |
1588 | mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL); | |
1589 | mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT; | |
f073cc8f | 1590 | if (mmr_image & (1L << UV2_ACK_UNITS_SHFT)) |
2a919596 JS |
1591 | mult1 = 80; |
1592 | else | |
1593 | mult1 = 10; | |
1594 | base = mmr_image & UV2_ACK_MASK; | |
1595 | ret = mult1 * base; | |
1596 | } | |
12a6611f CW |
1597 | return ret; |
1598 | } | |
1599 | ||
f073cc8f CW |
1600 | static void __init init_per_cpu_tunables(void) |
1601 | { | |
1602 | int cpu; | |
1603 | struct bau_control *bcp; | |
1604 | ||
1605 | for_each_present_cpu(cpu) { | |
1606 | bcp = &per_cpu(bau_control, cpu); | |
1607 | bcp->baudisabled = 0; | |
1608 | bcp->statp = &per_cpu(ptcstats, cpu); | |
1609 | /* time interval to catch a hardware stay-busy bug */ | |
1610 | bcp->timeout_interval = usec_2_cycles(2*timeout_us); | |
1611 | bcp->max_concurr = max_concurr; | |
1612 | bcp->max_concurr_const = max_concurr; | |
1613 | bcp->plugged_delay = plugged_delay; | |
1614 | bcp->plugsb4reset = plugsb4reset; | |
1615 | bcp->timeoutsb4reset = timeoutsb4reset; | |
1616 | bcp->ipi_reset_limit = ipi_reset_limit; | |
1617 | bcp->complete_threshold = complete_threshold; | |
1618 | bcp->cong_response_us = congested_respns_us; | |
1619 | bcp->cong_reps = congested_reps; | |
1620 | bcp->cong_period = congested_period; | |
1621 | } | |
1622 | } | |
1623 | ||
b8f7fb13 | 1624 | /* |
f073cc8f | 1625 | * Scan all cpus to collect blade and socket summaries. |
b8f7fb13 | 1626 | */ |
f073cc8f CW |
1627 | static int __init get_cpu_topology(int base_pnode, |
1628 | struct uvhub_desc *uvhub_descs, | |
1629 | unsigned char *uvhub_mask) | |
b8f7fb13 | 1630 | { |
b8f7fb13 CW |
1631 | int cpu; |
1632 | int pnode; | |
1633 | int uvhub; | |
f073cc8f | 1634 | int socket; |
b8f7fb13 CW |
1635 | struct bau_control *bcp; |
1636 | struct uvhub_desc *bdp; | |
1637 | struct socket_desc *sdp; | |
b8f7fb13 | 1638 | |
b8f7fb13 CW |
1639 | for_each_present_cpu(cpu) { |
1640 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f | 1641 | |
b8f7fb13 | 1642 | memset(bcp, 0, sizeof(struct bau_control)); |
f073cc8f | 1643 | |
b8f7fb13 | 1644 | pnode = uv_cpu_hub_info(cpu)->pnode; |
f073cc8f | 1645 | if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) { |
77ed23f8 CW |
1646 | printk(KERN_EMERG |
1647 | "cpu %d pnode %d-%d beyond %d; BAU disabled\n", | |
f073cc8f | 1648 | cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE); |
77ed23f8 CW |
1649 | return 1; |
1650 | } | |
f073cc8f | 1651 | |
77ed23f8 | 1652 | bcp->osnode = cpu_to_node(cpu); |
f073cc8f CW |
1653 | bcp->partition_base_pnode = base_pnode; |
1654 | ||
b8f7fb13 | 1655 | uvhub = uv_cpu_hub_info(cpu)->numa_blade_id; |
c4026cfd | 1656 | *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8)); |
b8f7fb13 | 1657 | bdp = &uvhub_descs[uvhub]; |
f073cc8f | 1658 | |
b8f7fb13 CW |
1659 | bdp->num_cpus++; |
1660 | bdp->uvhub = uvhub; | |
1661 | bdp->pnode = pnode; | |
f073cc8f | 1662 | |
a8328ee5 CW |
1663 | /* kludge: 'assuming' one node per socket, and assuming that |
1664 | disabling a socket just leaves a gap in node numbers */ | |
77ed23f8 | 1665 | socket = bcp->osnode & 1; |
a8328ee5 | 1666 | bdp->socket_mask |= (1 << socket); |
b8f7fb13 CW |
1667 | sdp = &bdp->socket[socket]; |
1668 | sdp->cpu_number[sdp->num_cpus] = cpu; | |
1669 | sdp->num_cpus++; | |
cfa60917 | 1670 | if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) { |
f073cc8f CW |
1671 | printk(KERN_EMERG "%d cpus per socket invalid\n", |
1672 | sdp->num_cpus); | |
cfa60917 CW |
1673 | return 1; |
1674 | } | |
b8f7fb13 | 1675 | } |
f073cc8f CW |
1676 | return 0; |
1677 | } | |
1678 | ||
1679 | /* | |
1680 | * Each socket is to get a local array of pnodes/hubs. | |
1681 | */ | |
1682 | static void make_per_cpu_thp(struct bau_control *smaster) | |
1683 | { | |
1684 | int cpu; | |
1685 | size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus(); | |
1686 | ||
1687 | smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode); | |
1688 | memset(smaster->thp, 0, hpsz); | |
1689 | for_each_present_cpu(cpu) { | |
1690 | smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode; | |
1691 | smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id; | |
1692 | } | |
1693 | } | |
1694 | ||
442d3924 | 1695 | /* |
1696 | * Each uvhub is to get a local cpumask. | |
1697 | */ | |
1698 | static void make_per_hub_cpumask(struct bau_control *hmaster) | |
1699 | { | |
1700 | int sz = sizeof(cpumask_t); | |
1701 | ||
1702 | hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode); | |
1703 | } | |
1704 | ||
f073cc8f CW |
1705 | /* |
1706 | * Initialize all the per_cpu information for the cpu's on a given socket, | |
1707 | * given what has been gathered into the socket_desc struct. | |
1708 | * And reports the chosen hub and socket masters back to the caller. | |
1709 | */ | |
1710 | static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp, | |
1711 | struct bau_control **smasterp, | |
1712 | struct bau_control **hmasterp) | |
1713 | { | |
1714 | int i; | |
1715 | int cpu; | |
1716 | struct bau_control *bcp; | |
1717 | ||
1718 | for (i = 0; i < sdp->num_cpus; i++) { | |
1719 | cpu = sdp->cpu_number[i]; | |
1720 | bcp = &per_cpu(bau_control, cpu); | |
1721 | bcp->cpu = cpu; | |
1722 | if (i == 0) { | |
1723 | *smasterp = bcp; | |
1724 | if (!(*hmasterp)) | |
1725 | *hmasterp = bcp; | |
1726 | } | |
1727 | bcp->cpus_in_uvhub = bdp->num_cpus; | |
1728 | bcp->cpus_in_socket = sdp->num_cpus; | |
1729 | bcp->socket_master = *smasterp; | |
1730 | bcp->uvhub = bdp->uvhub; | |
1731 | bcp->uvhub_master = *hmasterp; | |
1732 | bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id; | |
1733 | if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) { | |
1734 | printk(KERN_EMERG "%d cpus per uvhub invalid\n", | |
1735 | bcp->uvhub_cpu); | |
1736 | return 1; | |
1737 | } | |
1738 | } | |
1739 | return 0; | |
1740 | } | |
1741 | ||
1742 | /* | |
1743 | * Summarize the blade and socket topology into the per_cpu structures. | |
1744 | */ | |
1745 | static int __init summarize_uvhub_sockets(int nuvhubs, | |
1746 | struct uvhub_desc *uvhub_descs, | |
1747 | unsigned char *uvhub_mask) | |
1748 | { | |
1749 | int socket; | |
1750 | int uvhub; | |
1751 | unsigned short socket_mask; | |
1752 | ||
c4026cfd | 1753 | for (uvhub = 0; uvhub < nuvhubs; uvhub++) { |
f073cc8f CW |
1754 | struct uvhub_desc *bdp; |
1755 | struct bau_control *smaster = NULL; | |
1756 | struct bau_control *hmaster = NULL; | |
1757 | ||
c4026cfd CW |
1758 | if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8)))) |
1759 | continue; | |
f073cc8f | 1760 | |
b8f7fb13 | 1761 | bdp = &uvhub_descs[uvhub]; |
a8328ee5 CW |
1762 | socket_mask = bdp->socket_mask; |
1763 | socket = 0; | |
1764 | while (socket_mask) { | |
f073cc8f CW |
1765 | struct socket_desc *sdp; |
1766 | if ((socket_mask & 1)) { | |
1767 | sdp = &bdp->socket[socket]; | |
1768 | if (scan_sock(sdp, bdp, &smaster, &hmaster)) | |
cfa60917 | 1769 | return 1; |
9c9153db | 1770 | make_per_cpu_thp(smaster); |
b8f7fb13 CW |
1771 | } |
1772 | socket++; | |
a8328ee5 | 1773 | socket_mask = (socket_mask >> 1); |
b8f7fb13 | 1774 | } |
442d3924 | 1775 | make_per_hub_cpumask(hmaster); |
b8f7fb13 | 1776 | } |
f073cc8f CW |
1777 | return 0; |
1778 | } | |
1779 | ||
1780 | /* | |
1781 | * initialize the bau_control structure for each cpu | |
1782 | */ | |
1783 | static int __init init_per_cpu(int nuvhubs, int base_part_pnode) | |
1784 | { | |
1785 | unsigned char *uvhub_mask; | |
1786 | void *vp; | |
1787 | struct uvhub_desc *uvhub_descs; | |
1788 | ||
1789 | timeout_us = calculate_destination_timeout(); | |
1790 | ||
1791 | vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL); | |
1792 | uvhub_descs = (struct uvhub_desc *)vp; | |
1793 | memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc)); | |
1794 | uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL); | |
1795 | ||
1796 | if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask)) | |
bbd270e6 | 1797 | goto fail; |
f073cc8f CW |
1798 | |
1799 | if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask)) | |
bbd270e6 | 1800 | goto fail; |
f073cc8f | 1801 | |
b8f7fb13 | 1802 | kfree(uvhub_descs); |
c4026cfd | 1803 | kfree(uvhub_mask); |
f073cc8f | 1804 | init_per_cpu_tunables(); |
cfa60917 | 1805 | return 0; |
bbd270e6 | 1806 | |
1807 | fail: | |
1808 | kfree(uvhub_descs); | |
1809 | kfree(uvhub_mask); | |
1810 | return 1; | |
b194b120 CW |
1811 | } |
1812 | ||
1813 | /* | |
1814 | * Initialization of BAU-related structures | |
1815 | */ | |
1816 | static int __init uv_bau_init(void) | |
1817 | { | |
b8f7fb13 CW |
1818 | int uvhub; |
1819 | int pnode; | |
1820 | int nuvhubs; | |
2c74d666 | 1821 | int cur_cpu; |
f073cc8f | 1822 | int cpus; |
b8f7fb13 | 1823 | int vector; |
f073cc8f | 1824 | cpumask_var_t *mask; |
b194b120 CW |
1825 | |
1826 | if (!is_uv_system()) | |
1827 | return 0; | |
1812924b | 1828 | |
b8f7fb13 CW |
1829 | if (nobau) |
1830 | return 0; | |
1831 | ||
f073cc8f CW |
1832 | for_each_possible_cpu(cur_cpu) { |
1833 | mask = &per_cpu(uv_flush_tlb_mask, cur_cpu); | |
1834 | zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu)); | |
1835 | } | |
76ba0ecd | 1836 | |
b8f7fb13 | 1837 | nuvhubs = uv_num_possible_blades(); |
50fb55ac | 1838 | spin_lock_init(&disable_lock); |
f073cc8f | 1839 | congested_cycles = usec_2_cycles(congested_respns_us); |
9674f35b | 1840 | |
f073cc8f | 1841 | uv_base_pnode = 0x7fffffff; |
77ed23f8 | 1842 | for (uvhub = 0; uvhub < nuvhubs; uvhub++) { |
f073cc8f CW |
1843 | cpus = uv_blade_nr_possible_cpus(uvhub); |
1844 | if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode)) | |
1845 | uv_base_pnode = uv_blade_to_pnode(uvhub); | |
77ed23f8 CW |
1846 | } |
1847 | ||
f073cc8f | 1848 | if (init_per_cpu(nuvhubs, uv_base_pnode)) { |
77ed23f8 CW |
1849 | nobau = 1; |
1850 | return 0; | |
1851 | } | |
b8f7fb13 CW |
1852 | |
1853 | vector = UV_BAU_MESSAGE; | |
1854 | for_each_possible_blade(uvhub) | |
1855 | if (uv_blade_nr_possible_cpus(uvhub)) | |
f073cc8f | 1856 | init_uvhub(uvhub, vector, uv_base_pnode); |
b8f7fb13 | 1857 | |
f073cc8f | 1858 | enable_timeouts(); |
b8f7fb13 CW |
1859 | alloc_intr_gate(vector, uv_bau_message_intr1); |
1860 | ||
1861 | for_each_possible_blade(uvhub) { | |
93a7ca0c | 1862 | if (uv_blade_nr_possible_cpus(uvhub)) { |
f073cc8f CW |
1863 | unsigned long val; |
1864 | unsigned long mmr; | |
93a7ca0c CW |
1865 | pnode = uv_blade_to_pnode(uvhub); |
1866 | /* INIT the bau */ | |
f073cc8f CW |
1867 | val = 1L << 63; |
1868 | write_gmmr_activation(pnode, val); | |
93a7ca0c | 1869 | mmr = 1; /* should be 1 to broadcast to both sockets */ |
f073cc8f | 1870 | write_mmr_data_broadcast(pnode, mmr); |
93a7ca0c | 1871 | } |
b8f7fb13 | 1872 | } |
b4c286e6 | 1873 | |
1812924b CW |
1874 | return 0; |
1875 | } | |
b8f7fb13 | 1876 | core_initcall(uv_bau_init); |
e8e5e8a8 | 1877 | fs_initcall(uv_ptc_init); |