[deliverable/linux.git] / arch / xtensa / include / asm / initialize_mmu.h

/*
 * arch/xtensa/include/asm/initialize_mmu.h
 *
 * Initializes MMU:
 *
 *      For the new V3 MMU we remap the TLB from virtual == physical
 *      to the standard Linux mapping used in earlier MMU's.
 *
 *      The the MMU we also support a new configuration register that
 *      specifies how the S32C1I instruction operates with the cache
 *      controller.
 *
 * This file is subject to the terms and conditions of the GNU General
 * Public License.  See the file "COPYING" in the main directory of
 * this archive for more details.
 *
 * Copyright (C) 2008 - 2012 Tensilica, Inc.
 *
 *   Marc Gauthier <marc@tensilica.com>
 *   Pete Delaney <piet@tensilica.com>
 */

#ifndef _XTENSA_INITIALIZE_MMU_H
#define _XTENSA_INITIALIZE_MMU_H

#include <asm/pgtable.h>
#include <asm/vectors.h>

#if XCHAL_HAVE_PTP_MMU
#define CA_BYPASS	(_PAGE_CA_BYPASS | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
#define CA_WRITEBACK	(_PAGE_CA_WB     | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
#else
#define CA_WRITEBACK	(0x4)
#endif

#ifndef XCHAL_SPANNING_WAY
#define XCHAL_SPANNING_WAY 0
#endif

#ifdef __ASSEMBLY__

#define XTENSA_HWVERSION_RC_2009_0 230000

	.macro	initialize_mmu

#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
/*
 * We Have Atomic Operation Control (ATOMCTL) Register; Initialize it.
 * For details see Documentation/xtensa/atomctl.txt
 */
#if XCHAL_DCACHE_IS_COHERENT
	movi	a3, 0x25	/* For SMP/MX -- internal for writeback,
				 * RCW otherwise
				 */
#else
	movi	a3, 0x29	/* non-MX -- Most cores use Std Memory
				 * Controlers which usually can't use RCW
				 */
#endif
	wsr	a3, atomctl
#endif  /* XCHAL_HAVE_S32C1I &&
	 * (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
	 */

#if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
/*
 * Have MMU v3
 */

#if !XCHAL_HAVE_VECBASE
# error "MMU v3 requires reloc vectors"
#endif

	movi	a1, 0
	_call0	1f
	_j	2f

	.align	4
1:	movi	a2, 0x10000000

#if CONFIG_KERNEL_LOAD_ADDRESS < 0x40000000ul
#define TEMP_MAPPING_VADDR 0x40000000
#else
#define TEMP_MAPPING_VADDR 0x00000000
#endif

	/* Step 1: invalidate mapping at 0x40000000..0x5FFFFFFF. */

	movi	a2, TEMP_MAPPING_VADDR | XCHAL_SPANNING_WAY
	idtlb	a2
	iitlb	a2
	isync

	/* Step 2: map 0x40000000..0x47FFFFFF to paddr containing this code
	 * and jump to the new mapping.
	 */

	srli	a3, a0, 27
	slli	a3, a3, 27
	addi	a3, a3, CA_BYPASS
	addi	a7, a2, 5 - XCHAL_SPANNING_WAY
	wdtlb	a3, a7
	witlb	a3, a7
	isync

	slli	a4, a0, 5
	srli	a4, a4, 5
	addi	a5, a2, -XCHAL_SPANNING_WAY
	add	a4, a4, a5
	jx	a4

	/* Step 3: unmap everything other than current area.
	 *	   Start at 0x60000000, wrap around, and end with 0x20000000
	 */
2:	movi	a4, 0x20000000
	add	a5, a2, a4
3:	idtlb	a5
	iitlb	a5
	add	a5, a5, a4
	bne	a5, a2, 3b

	/* Step 4: Setup MMU with the requested static mappings. */

	movi	a6, 0x01000000
	wsr	a6, ITLBCFG
	wsr	a6, DTLBCFG
	isync

	movi	a5, XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_TLB_WAY
	movi	a4, XCHAL_KSEG_PADDR + CA_WRITEBACK
	wdtlb	a4, a5
	witlb	a4, a5

	movi	a5, XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_TLB_WAY
	movi	a4, XCHAL_KSEG_PADDR + CA_BYPASS
	wdtlb	a4, a5
	witlb	a4, a5

#ifdef CONFIG_XTENSA_KSEG_512M
	movi	a5, XCHAL_KSEG_CACHED_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY
	movi	a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_WRITEBACK
	wdtlb	a4, a5
	witlb	a4, a5

	movi	a5, XCHAL_KSEG_BYPASS_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY
	movi	a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_BYPASS
	wdtlb	a4, a5
	witlb	a4, a5
#endif

	movi	a5, XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_TLB_WAY
	movi	a4, XCHAL_KIO_DEFAULT_PADDR + CA_WRITEBACK
	wdtlb	a4, a5
	witlb	a4, a5

	movi	a5, XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_TLB_WAY
	movi	a4, XCHAL_KIO_DEFAULT_PADDR + CA_BYPASS
	wdtlb	a4, a5
	witlb	a4, a5

	isync

	/* Jump to self, using final mappings. */
	movi	a4, 1f
	jx	a4

1:
	/* Step 5: remove temporary mapping. */
	idtlb	a7
	iitlb	a7
	isync

	movi	a0, 0
	wsr	a0, ptevaddr
	rsync

#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
	  XCHAL_HAVE_SPANNING_WAY */

#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS && \
		(XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE)
	/* Enable data and instruction cache in the DEFAULT_MEMORY region
	 * if the processor has DTLB and ITLB.
	 */

	movi	a5, PLATFORM_DEFAULT_MEM_START | XCHAL_SPANNING_WAY
	movi	a6, ~_PAGE_ATTRIB_MASK
	movi	a7, CA_WRITEBACK
	movi	a8, 0x20000000
	movi	a9, PLATFORM_DEFAULT_MEM_SIZE
	j	2f
1:
	sub	a9, a9, a8
2:
#if XCHAL_DCACHE_SIZE
	rdtlb1	a3, a5
	and	a3, a3, a6
	or	a3, a3, a7
	wdtlb	a3, a5
#endif
#if XCHAL_ICACHE_SIZE
	ritlb1	a4, a5
	and	a4, a4, a6
	or	a4, a4, a7
	witlb	a4, a5
#endif
	add	a5, a5, a8
	bltu	a8, a9, 1b

#endif

	.endm

#endif /*__ASSEMBLY__*/

#endif /* _XTENSA_INITIALIZE_MMU_H */
Commit	Line	Data
c622b29d MF	1	/*
	2	* arch/xtensa/include/asm/initialize_mmu.h
	3	*
	4	* Initializes MMU:
	5	*
	6	* For the new V3 MMU we remap the TLB from virtual == physical
	7	* to the standard Linux mapping used in earlier MMU's.
	8	*
	9	* The the MMU we also support a new configuration register that
	10	* specifies how the S32C1I instruction operates with the cache
	11	* controller.
	12	*
	13	* This file is subject to the terms and conditions of the GNU General
	14	* Public License. See the file "COPYING" in the main directory of
	15	* this archive for more details.
	16	*
	17	* Copyright (C) 2008 - 2012 Tensilica, Inc.
	18	*
	19	* Marc Gauthier <marc@tensilica.com>
	20	* Pete Delaney <piet@tensilica.com>
	21	*/
	22
	23	#ifndef _XTENSA_INITIALIZE_MMU_H
	24	#define _XTENSA_INITIALIZE_MMU_H
	25
e85e335f MF	26	#include <asm/pgtable.h>
	27	#include <asm/vectors.h>
	28
2eabc180	29	#if XCHAL_HAVE_PTP_MMU
6cb97111 BS	30	#define CA_BYPASS (_PAGE_CA_BYPASS \| _PAGE_HW_WRITE \| _PAGE_HW_EXEC)
6cb97111 BS	31	#define CA_WRITEBACK (_PAGE_CA_WB \| _PAGE_HW_WRITE \| _PAGE_HW_EXEC)
2eabc180 MF	32	#else
	33	#define CA_WRITEBACK (0x4)
	34	#endif
	35
	36	#ifndef XCHAL_SPANNING_WAY
	37	#define XCHAL_SPANNING_WAY 0
	38	#endif
6cb97111	39
c622b29d MF	40	#ifdef __ASSEMBLY__
	41
	42	#define XTENSA_HWVERSION_RC_2009_0 230000
	43
	44	.macro initialize_mmu
	45
	46	#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
	47	/*
	48	* We Have Atomic Operation Control (ATOMCTL) Register; Initialize it.
	49	* For details see Documentation/xtensa/atomctl.txt
	50	*/
	51	#if XCHAL_DCACHE_IS_COHERENT
	52	movi a3, 0x25 /* For SMP/MX -- internal for writeback,
	53	* RCW otherwise
	54	*/
	55	#else
	56	movi a3, 0x29 /* non-MX -- Most cores use Std Memory
	57	* Controlers which usually can't use RCW
	58	*/
	59	#endif
	60	wsr a3, atomctl
	61	#endif /* XCHAL_HAVE_S32C1I &&
	62	* (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
	63	*/
	64
e85e335f MF	65	#if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
	66	/*
	67	* Have MMU v3
	68	*/
	69
	70	#if !XCHAL_HAVE_VECBASE
	71	# error "MMU v3 requires reloc vectors"
	72	#endif
	73
	74	movi a1, 0
	75	_call0 1f
	76	_j 2f
	77
	78	.align 4
	79	1: movi a2, 0x10000000
a9f2fc62 MF	80
	81	#if CONFIG_KERNEL_LOAD_ADDRESS < 0x40000000ul
	82	#define TEMP_MAPPING_VADDR 0x40000000
	83	#else
	84	#define TEMP_MAPPING_VADDR 0x00000000
	85	#endif
e85e335f MF	86
	87	/* Step 1: invalidate mapping at 0x40000000..0x5FFFFFFF. */
	88
a9f2fc62	89	movi a2, TEMP_MAPPING_VADDR \| XCHAL_SPANNING_WAY
e85e335f MF	90	idtlb a2
	91	iitlb a2
	92	isync
	93
	94	/* Step 2: map 0x40000000..0x47FFFFFF to paddr containing this code
	95	* and jump to the new mapping.
	96	*/
e85e335f MF	97
	98	srli a3, a0, 27
	99	slli a3, a3, 27
	100	addi a3, a3, CA_BYPASS
a9f2fc62	101	addi a7, a2, 5 - XCHAL_SPANNING_WAY
e85e335f MF	102	wdtlb a3, a7
	103	witlb a3, a7
	104	isync
	105
	106	slli a4, a0, 5
	107	srli a4, a4, 5
a9f2fc62	108	addi a5, a2, -XCHAL_SPANNING_WAY
e85e335f MF	109	add a4, a4, a5
	110	jx a4
	111
	112	/* Step 3: unmap everything other than current area.
	113	* Start at 0x60000000, wrap around, and end with 0x20000000
	114	*/
	115	2: movi a4, 0x20000000
	116	add a5, a2, a4
	117	3: idtlb a5
	118	iitlb a5
	119	add a5, a5, a4
	120	bne a5, a2, 3b
	121
d39af902 MF	122	/* Step 4: Setup MMU with the requested static mappings. */
d39af902 MF	123
e85e335f MF	124	movi a6, 0x01000000
	125	wsr a6, ITLBCFG
	126	wsr a6, DTLBCFG
	127	isync
	128
d39af902 MF	129	movi a5, XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_TLB_WAY
	130	movi a4, XCHAL_KSEG_PADDR + CA_WRITEBACK
	131	wdtlb a4, a5
	132	witlb a4, a5
	133
	134	movi a5, XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_TLB_WAY
	135	movi a4, XCHAL_KSEG_PADDR + CA_BYPASS
e85e335f MF	136	wdtlb a4, a5
	137	witlb a4, a5
	138
d39af902 MF	139	#ifdef CONFIG_XTENSA_KSEG_512M
	140	movi a5, XCHAL_KSEG_CACHED_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY
	141	movi a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_WRITEBACK
e85e335f MF	142	wdtlb a4, a5
	143	witlb a4, a5
	144
d39af902 MF	145	movi a5, XCHAL_KSEG_BYPASS_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY
	146	movi a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_BYPASS
	147	wdtlb a4, a5
	148	witlb a4, a5
	149	#endif
	150
a9f2fc62	151	movi a5, XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_TLB_WAY
6cb97111	152	movi a4, XCHAL_KIO_DEFAULT_PADDR + CA_WRITEBACK
e85e335f MF	153	wdtlb a4, a5
	154	witlb a4, a5
	155
a9f2fc62	156	movi a5, XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_TLB_WAY
6cb97111	157	movi a4, XCHAL_KIO_DEFAULT_PADDR + CA_BYPASS
e85e335f MF	158	wdtlb a4, a5
	159	witlb a4, a5
	160
	161	isync
	162
a9f2fc62	163	/* Jump to self, using final mappings. */
e85e335f MF	164	movi a4, 1f
	165	jx a4
	166
	167	1:
e85e335f MF	168	/* Step 5: remove temporary mapping. */
	169	idtlb a7
	170	iitlb a7
	171	isync
	172
	173	movi a0, 0
	174	wsr a0, ptevaddr
	175	rsync
	176
	177	#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
	178	XCHAL_HAVE_SPANNING_WAY */
	179
01618bde MF	180	#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS && \
01618bde MF	181	(XCHAL_DCACHE_SIZE \|\| XCHAL_ICACHE_SIZE)
2eabc180 MF	182	/* Enable data and instruction cache in the DEFAULT_MEMORY region
	183	* if the processor has DTLB and ITLB.
	184	*/
	185
	186	movi a5, PLATFORM_DEFAULT_MEM_START \| XCHAL_SPANNING_WAY
	187	movi a6, ~_PAGE_ATTRIB_MASK
	188	movi a7, CA_WRITEBACK
	189	movi a8, 0x20000000
	190	movi a9, PLATFORM_DEFAULT_MEM_SIZE
	191	j 2f
	192	1:
	193	sub a9, a9, a8
	194	2:
01618bde	195	#if XCHAL_DCACHE_SIZE
2eabc180	196	rdtlb1 a3, a5
2eabc180	197	and a3, a3, a6
2eabc180	198	or a3, a3, a7
2eabc180	199	wdtlb a3, a5
01618bde MF	200	#endif
	201	#if XCHAL_ICACHE_SIZE
	202	ritlb1 a4, a5
	203	and a4, a4, a6
	204	or a4, a4, a7
2eabc180	205	witlb a4, a5
01618bde	206	#endif
2eabc180 MF	207	add a5, a5, a8
	208	bltu a8, a9, 1b
	209
	210	#endif
	211
c622b29d MF	212	.endm
	213
	214	#endif /__ASSEMBLY__/
	215
	216	#endif /* _XTENSA_INITIALIZE_MMU_H */