x86: Correct EVEX vector load/store optimization
[deliverable/binutils-gdb.git] / bfd / cpu-sh.c
CommitLineData
ef230218 1/* BFD library support routines for the Renesas / SuperH SH architecture.
82704155 2 Copyright (C) 1993-2019 Free Software Foundation, Inc.
252b5132
RH
3 Hacked by Steve Chamberlain of Cygnus Support.
4
5177500f 5 This file is part of BFD, the Binary File Descriptor library.
252b5132 6
5177500f
NC
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
cd123cb7 9 the Free Software Foundation; either version 3 of the License, or
5177500f 10 (at your option) any later version.
252b5132 11
5177500f
NC
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
252b5132 16
5177500f
NC
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
cd123cb7
NC
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
252b5132 21
252b5132 22#include "sysdep.h"
3db64b00 23#include "bfd.h"
252b5132 24#include "libbfd.h"
f6f9408f 25#include "../opcodes/sh-opc.h"
252b5132 26
07d6d2b8
AM
27#define SH_NEXT arch_info_struct + 0
28#define SH2_NEXT arch_info_struct + 1
29#define SH2E_NEXT arch_info_struct + 2
30#define SH_DSP_NEXT arch_info_struct + 3
31#define SH3_NEXT arch_info_struct + 4
32#define SH3_NOMMU_NEXT arch_info_struct + 5
33#define SH3_DSP_NEXT arch_info_struct + 6
34#define SH3E_NEXT arch_info_struct + 7
35#define SH4_NEXT arch_info_struct + 8
36#define SH4A_NEXT arch_info_struct + 9
37#define SH4AL_DSP_NEXT arch_info_struct + 10
38#define SH4_NOFPU_NEXT arch_info_struct + 11
39#define SH4_NOMMU_NOFPU_NEXT arch_info_struct + 12
40#define SH4A_NOFPU_NEXT arch_info_struct + 13
41#define SH2A_NEXT arch_info_struct + 14
42#define SH2A_NOFPU_NEXT arch_info_struct + 15
e38bc3b5 43#define SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT arch_info_struct + 16
07d6d2b8
AM
44#define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17
45#define SH2A_OR_SH4_NEXT arch_info_struct + 18
211dc24b 46#define SH2A_OR_SH3E_NEXT NULL
252b5132 47
71f6b586 48static const bfd_arch_info_type arch_info_struct[] =
252b5132 49{
d4845d57 50 {
e38bc3b5
NC
51 32, /* 32 bits in a word. */
52 32, /* 32 bits in an address. */
53 8, /* 8 bits in a byte. */
d4845d57
JR
54 bfd_arch_sh,
55 bfd_mach_sh2,
e38bc3b5
NC
56 "sh", /* Architecture name. */
57 "sh2", /* Machine name. */
d4845d57 58 1,
e38bc3b5 59 FALSE, /* Not the default. */
d4845d57 60 bfd_default_compatible,
a44d7f9c 61 bfd_default_scan,
b7761f11 62 bfd_arch_default_fill,
d4845d57
JR
63 SH2_NEXT
64 },
5177500f 65 {
e38bc3b5
NC
66 32, /* 32 bits in a word. */
67 32, /* 32 bits in an address. */
68 8, /* 8 bits in a byte. */
5177500f
NC
69 bfd_arch_sh,
70 bfd_mach_sh2e,
e38bc3b5
NC
71 "sh", /* Architecture name. */
72 "sh2e", /* Machine name. */
5177500f 73 1,
e38bc3b5 74 FALSE, /* Not the default. */
5177500f
NC
75 bfd_default_compatible,
76 bfd_default_scan,
b7761f11 77 bfd_arch_default_fill,
5177500f
NC
78 SH2E_NEXT
79 },
d4845d57 80 {
e38bc3b5
NC
81 32, /* 32 bits in a word. */
82 32, /* 32 bits in an address. */
83 8, /* 8 bits in a byte. */
d4845d57
JR
84 bfd_arch_sh,
85 bfd_mach_sh_dsp,
e38bc3b5
NC
86 "sh", /* Architecture name. */
87 "sh-dsp", /* Machine name. */
d4845d57 88 1,
e38bc3b5 89 FALSE, /* Not the default. */
d4845d57 90 bfd_default_compatible,
a44d7f9c 91 bfd_default_scan,
b7761f11 92 bfd_arch_default_fill,
d4845d57
JR
93 SH_DSP_NEXT
94 },
252b5132 95 {
e38bc3b5
NC
96 32, /* 32 bits in a word. */
97 32, /* 32 bits in an address. */
98 8, /* 8 bits in a byte. */
252b5132
RH
99 bfd_arch_sh,
100 bfd_mach_sh3,
e38bc3b5
NC
101 "sh", /* Architecture name. */
102 "sh3", /* Machine name. */
252b5132 103 1,
e38bc3b5 104 FALSE, /* Not the default. */
252b5132 105 bfd_default_compatible,
a44d7f9c 106 bfd_default_scan,
b7761f11 107 bfd_arch_default_fill,
252b5132
RH
108 SH3_NEXT
109 },
f6f9408f 110 {
e38bc3b5
NC
111 32, /* 32 bits in a word. */
112 32, /* 32 bits in an address. */
113 8, /* 8 bits in a byte. */
f6f9408f
JR
114 bfd_arch_sh,
115 bfd_mach_sh3_nommu,
e38bc3b5
NC
116 "sh", /* Architecture name. */
117 "sh3-nommu", /* Machine name. */
f6f9408f 118 1,
e38bc3b5 119 FALSE, /* Not the default. */
f6f9408f
JR
120 bfd_default_compatible,
121 bfd_default_scan,
b7761f11 122 bfd_arch_default_fill,
f6f9408f
JR
123 SH3_NOMMU_NEXT
124 },
d4845d57 125 {
e38bc3b5
NC
126 32, /* 32 bits in a word. */
127 32, /* 32 bits in an address. */
128 8, /* 8 bits in a byte. */
d4845d57
JR
129 bfd_arch_sh,
130 bfd_mach_sh3_dsp,
e38bc3b5
NC
131 "sh", /* Architecture name. */
132 "sh3-dsp", /* Machine name. */
d4845d57 133 1,
e38bc3b5 134 FALSE, /* Not the default. */
d4845d57 135 bfd_default_compatible,
a44d7f9c 136 bfd_default_scan,
b7761f11 137 bfd_arch_default_fill,
d4845d57
JR
138 SH3_DSP_NEXT
139 },
252b5132 140 {
e38bc3b5
NC
141 32, /* 32 bits in a word. */
142 32, /* 32 bits in an address. */
143 8, /* 8 bits in a byte. */
252b5132
RH
144 bfd_arch_sh,
145 bfd_mach_sh3e,
e38bc3b5
NC
146 "sh", /* Architecture name. */
147 "sh3e", /* Machine name. */
252b5132 148 1,
e38bc3b5 149 FALSE, /* Not the default. */
252b5132 150 bfd_default_compatible,
a44d7f9c 151 bfd_default_scan,
b7761f11 152 bfd_arch_default_fill,
252b5132
RH
153 SH3E_NEXT
154 },
d4845d57 155 {
e38bc3b5
NC
156 32, /* 32 bits in a word. */
157 32, /* 32 bits in an address. */
158 8, /* 8 bits in a byte. */
d4845d57
JR
159 bfd_arch_sh,
160 bfd_mach_sh4,
e38bc3b5
NC
161 "sh", /* Architecture name. */
162 "sh4", /* Machine name. */
d4845d57 163 1,
e38bc3b5 164 FALSE, /* Not the default. */
d4845d57 165 bfd_default_compatible,
a44d7f9c 166 bfd_default_scan,
b7761f11 167 bfd_arch_default_fill,
d4845d57
JR
168 SH4_NEXT
169 },
af9ba621 170 {
e38bc3b5
NC
171 32, /* 32 bits in a word. */
172 32, /* 32 bits in an address. */
173 8, /* 8 bits in a byte. */
af9ba621
CV
174 bfd_arch_sh,
175 bfd_mach_sh4a,
e38bc3b5
NC
176 "sh", /* Architecture name. */
177 "sh4a", /* Machine name. */
af9ba621 178 1,
e38bc3b5 179 FALSE, /* Not the default. */
af9ba621
CV
180 bfd_default_compatible,
181 bfd_default_scan,
b7761f11 182 bfd_arch_default_fill,
af9ba621
CV
183 SH4A_NEXT
184 },
185 {
e38bc3b5
NC
186 32, /* 32 bits in a word. */
187 32, /* 32 bits in an address. */
188 8, /* 8 bits in a byte. */
af9ba621
CV
189 bfd_arch_sh,
190 bfd_mach_sh4al_dsp,
e38bc3b5
NC
191 "sh", /* Architecture name. */
192 "sh4al-dsp", /* Machine name. */
af9ba621 193 1,
e38bc3b5 194 FALSE, /* Not the default. */
af9ba621
CV
195 bfd_default_compatible,
196 bfd_default_scan,
b7761f11 197 bfd_arch_default_fill,
af9ba621
CV
198 SH4AL_DSP_NEXT
199 },
200 {
e38bc3b5
NC
201 32, /* 32 bits in a word. */
202 32, /* 32 bits in an address. */
203 8, /* 8 bits in a byte. */
af9ba621
CV
204 bfd_arch_sh,
205 bfd_mach_sh4_nofpu,
e38bc3b5
NC
206 "sh", /* Architecture name. */
207 "sh4-nofpu", /* Machine name. */
af9ba621 208 1,
e38bc3b5 209 FALSE, /* Not the default. */
af9ba621
CV
210 bfd_default_compatible,
211 bfd_default_scan,
b7761f11 212 bfd_arch_default_fill,
af9ba621
CV
213 SH4_NOFPU_NEXT
214 },
ae51a426 215 {
e38bc3b5
NC
216 32, /* 32 bits in a word. */
217 32, /* 32 bits in an address. */
218 8, /* 8 bits in a byte. */
ae51a426
JR
219 bfd_arch_sh,
220 bfd_mach_sh4_nommu_nofpu,
e38bc3b5
NC
221 "sh", /* Architecture name. */
222 "sh4-nommu-nofpu", /* Machine name. */
ae51a426 223 1,
e38bc3b5 224 FALSE, /* Not the default. */
ae51a426
JR
225 bfd_default_compatible,
226 bfd_default_scan,
b7761f11 227 bfd_arch_default_fill,
ae51a426
JR
228 SH4_NOMMU_NOFPU_NEXT
229 },
af9ba621 230 {
e38bc3b5
NC
231 32, /* 32 bits in a word. */
232 32, /* 32 bits in an address. */
233 8, /* 8 bits in a byte. */
af9ba621
CV
234 bfd_arch_sh,
235 bfd_mach_sh4a_nofpu,
e38bc3b5
NC
236 "sh", /* Architecture name. */
237 "sh4a-nofpu", /* Machine name. */
af9ba621 238 1,
e38bc3b5 239 FALSE, /* Not the default. */
af9ba621
CV
240 bfd_default_compatible,
241 bfd_default_scan,
b7761f11 242 bfd_arch_default_fill,
af9ba621
CV
243 SH4A_NOFPU_NEXT
244 },
1d70c7fb
AO
245 {
246 32, /* 32 bits in a word. */
247 32, /* 32 bits in an address. */
248 8, /* 8 bits in a byte. */
249 bfd_arch_sh,
250 bfd_mach_sh2a,
e38bc3b5
NC
251 "sh", /* Architecture name. */
252 "sh2a", /* Machine name. */
1d70c7fb
AO
253 1,
254 FALSE, /* Not the default. */
255 bfd_default_compatible,
256 bfd_default_scan,
b7761f11 257 bfd_arch_default_fill,
1d70c7fb
AO
258 SH2A_NEXT
259 },
260 {
261 32, /* 32 bits in a word. */
262 32, /* 32 bits in an address. */
263 8, /* 8 bits in a byte. */
264 bfd_arch_sh,
265 bfd_mach_sh2a_nofpu,
e38bc3b5
NC
266 "sh", /* Architecture name. */
267 "sh2a-nofpu", /* Machine name. */
1d70c7fb
AO
268 1,
269 FALSE, /* Not the default. */
270 bfd_default_compatible,
271 bfd_default_scan,
b7761f11 272 bfd_arch_default_fill,
1d70c7fb
AO
273 SH2A_NOFPU_NEXT
274 },
fbca6ad9 275 {
e38bc3b5
NC
276 32, /* 32 bits in a word. */
277 32, /* 32 bits in an address. */
278 8, /* 8 bits in a byte. */
279 bfd_arch_sh,
280 bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu,
281 "sh", /* Architecture name. */
282 "sh2a-nofpu-or-sh4-nommu-nofpu", /* Machine name. */
283 1,
284 FALSE, /* Not the default. */
285 bfd_default_compatible,
286 bfd_default_scan,
b7761f11 287 bfd_arch_default_fill,
e38bc3b5
NC
288 SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT
289 },
290 {
291 32, /* 32 bits in a word. */
292 32, /* 32 bits in an address. */
293 8, /* 8 bits in a byte. */
294 bfd_arch_sh,
295 bfd_mach_sh2a_nofpu_or_sh3_nommu,
296 "sh", /* Architecture name. . */
297 "sh2a-nofpu-or-sh3-nommu", /* Machine name. */
298 1,
299 FALSE, /* Not the default. */
300 bfd_default_compatible,
301 bfd_default_scan,
b7761f11 302 bfd_arch_default_fill,
e38bc3b5
NC
303 SH2A_NOFPU_OR_SH3_NOMMU_NEXT
304 },
305 {
306 32, /* 32 bits in a word. */
307 32, /* 32 bits in an address. */
308 8, /* 8 bits in a byte. */
309 bfd_arch_sh,
310 bfd_mach_sh2a_or_sh4,
311 "sh", /* Architecture name. */
312 "sh2a-or-sh4", /* Machine name. */
313 1,
314 FALSE, /* Not the default. */
315 bfd_default_compatible,
316 bfd_default_scan,
b7761f11 317 bfd_arch_default_fill,
e38bc3b5
NC
318 SH2A_OR_SH4_NEXT
319 },
320 {
321 32, /* 32 bits in a word. */
322 32, /* 32 bits in an address. */
323 8, /* 8 bits in a byte. */
324 bfd_arch_sh,
325 bfd_mach_sh2a_or_sh3e,
326 "sh", /* Architecture name. */
327 "sh2a-or-sh3e", /* Machine name. */
328 1,
329 FALSE, /* Not the default. */
330 bfd_default_compatible,
331 bfd_default_scan,
b7761f11 332 bfd_arch_default_fill,
e38bc3b5
NC
333 SH2A_OR_SH3E_NEXT
334 },
252b5132
RH
335};
336
337const bfd_arch_info_type bfd_sh_arch =
338{
e38bc3b5
NC
339 32, /* 32 bits in a word. */
340 32, /* 32 bits in an address. */
341 8, /* 8 bits in a byte. */
252b5132
RH
342 bfd_arch_sh,
343 bfd_mach_sh,
e38bc3b5
NC
344 "sh", /* Architecture name. */
345 "sh", /* Machine name. */
252b5132 346 1,
e38bc3b5 347 TRUE, /* The default machine. */
252b5132 348 bfd_default_compatible,
a44d7f9c 349 bfd_default_scan,
b7761f11 350 bfd_arch_default_fill,
252b5132
RH
351 SH_NEXT
352};
f6f9408f
JR
353
354
355/* This table defines the mappings from the BFD internal numbering
356 system to the opcodes internal flags system.
357 It is used by the functions defined below.
358 The prototypes for these SH specific functions are found in
359 sh-opc.h . */
360
361static struct { unsigned long bfd_mach, arch, arch_up; } bfd_to_arch_table[] =
362{
07d6d2b8
AM
363 { bfd_mach_sh, arch_sh1, arch_sh_up },
364 { bfd_mach_sh2, arch_sh2, arch_sh2_up },
365 { bfd_mach_sh2e, arch_sh2e, arch_sh2e_up },
366 { bfd_mach_sh_dsp, arch_sh_dsp, arch_sh_dsp_up },
367 { bfd_mach_sh2a, arch_sh2a, arch_sh2a_up },
368 { bfd_mach_sh2a_nofpu, arch_sh2a_nofpu, arch_sh2a_nofpu_up },
369
370 { bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, arch_sh2a_nofpu_or_sh4_nommu_nofpu, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up },
371 { bfd_mach_sh2a_nofpu_or_sh3_nommu, arch_sh2a_nofpu_or_sh3_nommu, arch_sh2a_nofpu_or_sh3_nommu_up },
372 { bfd_mach_sh2a_or_sh4, arch_sh2a_or_sh4, arch_sh2a_or_sh4_up },
e38bc3b5 373 { bfd_mach_sh2a_or_sh3e, arch_sh2a_or_sh3e, arch_sh2a_or_sh3e_up },
68ffbac6 374
07d6d2b8
AM
375 { bfd_mach_sh3, arch_sh3, arch_sh3_up },
376 { bfd_mach_sh3_nommu, arch_sh3_nommu, arch_sh3_nommu_up },
377 { bfd_mach_sh3_dsp, arch_sh3_dsp, arch_sh3_dsp_up },
378 { bfd_mach_sh3e, arch_sh3e, arch_sh3e_up },
379 { bfd_mach_sh4, arch_sh4, arch_sh4_up },
380 { bfd_mach_sh4a, arch_sh4a, arch_sh4a_up },
381 { bfd_mach_sh4al_dsp, arch_sh4al_dsp, arch_sh4al_dsp_up },
382 { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
f6f9408f 383 { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
07d6d2b8
AM
384 { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
385 { 0, 0, 0 } /* Terminator. */
f6f9408f
JR
386};
387
388
389/* Convert a BFD mach number into the right opcodes arch flags
390 using the table above. */
391
392unsigned int
393sh_get_arch_from_bfd_mach (unsigned long mach)
394{
395 int i = 0;
e38bc3b5 396
f6f9408f
JR
397 while (bfd_to_arch_table[i].bfd_mach != 0)
398 if (bfd_to_arch_table[i].bfd_mach == mach)
399 return bfd_to_arch_table[i].arch;
400 else
401 i++;
402
e38bc3b5 403 /* Machine not found. */
f6f9408f
JR
404 BFD_FAIL();
405
406 return SH_ARCH_UNKNOWN_ARCH;
407}
408
409
410/* Convert a BFD mach number into a set of opcodes arch flags
411 describing all the compatible architectures (i.e. arch_up)
412 using the table above. */
413
414unsigned int
415sh_get_arch_up_from_bfd_mach (unsigned long mach)
416{
417 int i = 0;
e38bc3b5 418
f6f9408f
JR
419 while (bfd_to_arch_table[i].bfd_mach != 0)
420 if (bfd_to_arch_table[i].bfd_mach == mach)
421 return bfd_to_arch_table[i].arch_up;
422 else
423 i++;
424
e38bc3b5 425 /* Machine not found. */
f6f9408f
JR
426 BFD_FAIL();
427
428 return SH_ARCH_UNKNOWN_ARCH;
429}
430
431
432/* Convert an arbitary arch_set - not necessarily corresponding
433 directly to anything in the table above - to the most generic
434 architecture which supports all the required features, and
435 return the corresponding BFD mach. */
436
437unsigned long
438sh_get_bfd_mach_from_arch_set (unsigned int arch_set)
439{
440 unsigned long result = 0;
441 unsigned int best = ~arch_set;
442 unsigned int co_mask = ~0;
443 int i = 0;
444
445 /* If arch_set permits variants with no coprocessor then do not allow
446 the other irrelevant co-processor bits to influence the choice:
447 e.g. if dsp is disallowed by arch_set, then the algorithm would
448 prefer fpu variants over nofpu variants because they also disallow
449 dsp - even though the nofpu would be the most correct choice.
450 This assumes that EVERY fpu/dsp variant has a no-coprocessor
451 counter-part, or their non-fpu/dsp instructions do not have the
452 no co-processor bit set. */
453 if (arch_set & arch_sh_no_co)
454 co_mask = ~(arch_sh_sp_fpu | arch_sh_dp_fpu | arch_sh_has_dsp);
455
456 while (bfd_to_arch_table[i].bfd_mach != 0)
457 {
458 unsigned int try = bfd_to_arch_table[i].arch_up & co_mask;
459
460 /* Conceptually: Find the architecture with the least number
461 of extra features or, if they have the same number, then
462 the greatest number of required features. Disregard
07d6d2b8 463 architectures where the required features alone do
f6f9408f
JR
464 not describe a valid architecture. */
465 if (((try & ~arch_set) < (best & ~arch_set)
466 || ((try & ~arch_set) == (best & ~arch_set)
467 && (~try & arch_set) < (~best & arch_set)))
468 && SH_MERGE_ARCH_SET_VALID (try, arch_set))
469 {
470 result = bfd_to_arch_table[i].bfd_mach;
471 best = try;
472 }
473
474 i++;
475 }
476
477 /* This might happen if a new variant is added to sh-opc.h
478 but no corresponding entry is added to the table above. */
479 BFD_ASSERT (result != 0);
480
481 return result;
482}
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