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Slightly improve logic of some operations on stap-probe.c
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
82704155 2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
7f266840 31
00a97672
RS		 32/* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34#define RELOC_SECTION(HTAB, NAME) \
35 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
36
37/* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39#define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
43
44/* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46#define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
50
51/* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53#define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
57
f3185997 58#define elf_info_to_howto NULL
07d6d2b8 59#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 60
61#define ARM_ELF_ABI_VERSION 0
62#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
63
79f08007
YZ		 64/* The Adjusted Place, as defined by AAELF. */
65#define Pa(X) ((X) & 0xfffffffc)
66
3e6b1042
DJ		 67static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
68 struct bfd_link_info *link_info,
69 asection *sec,
70 bfd_byte *contents);
71
7f266840
DJ		 72/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
73 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
74 in that slot. */
75
c19d1205 76static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 77{
8029a119 78 /* No relocation. */
7f266840
DJ		 79 HOWTO (R_ARM_NONE, /* type */
80 0, /* rightshift */
6346d5ca 81 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 82 0, /* bitsize */
83 FALSE, /* pc_relative */
84 0, /* bitpos */
85 complain_overflow_dont,/* complain_on_overflow */
86 bfd_elf_generic_reloc, /* special_function */
87 "R_ARM_NONE", /* name */
88 FALSE, /* partial_inplace */
89 0, /* src_mask */
90 0, /* dst_mask */
91 FALSE), /* pcrel_offset */
92
93 HOWTO (R_ARM_PC24, /* type */
94 2, /* rightshift */
95 2, /* size (0 = byte, 1 = short, 2 = long) */
96 24, /* bitsize */
97 TRUE, /* pc_relative */
98 0, /* bitpos */
99 complain_overflow_signed,/* complain_on_overflow */
100 bfd_elf_generic_reloc, /* special_function */
101 "R_ARM_PC24", /* name */
102 FALSE, /* partial_inplace */
103 0x00ffffff, /* src_mask */
104 0x00ffffff, /* dst_mask */
105 TRUE), /* pcrel_offset */
106
107 /* 32 bit absolute */
108 HOWTO (R_ARM_ABS32, /* type */
109 0, /* rightshift */
110 2, /* size (0 = byte, 1 = short, 2 = long) */
111 32, /* bitsize */
112 FALSE, /* pc_relative */
113 0, /* bitpos */
114 complain_overflow_bitfield,/* complain_on_overflow */
115 bfd_elf_generic_reloc, /* special_function */
116 "R_ARM_ABS32", /* name */
117 FALSE, /* partial_inplace */
118 0xffffffff, /* src_mask */
119 0xffffffff, /* dst_mask */
120 FALSE), /* pcrel_offset */
121
122 /* standard 32bit pc-relative reloc */
123 HOWTO (R_ARM_REL32, /* type */
124 0, /* rightshift */
125 2, /* size (0 = byte, 1 = short, 2 = long) */
126 32, /* bitsize */
127 TRUE, /* pc_relative */
128 0, /* bitpos */
129 complain_overflow_bitfield,/* complain_on_overflow */
130 bfd_elf_generic_reloc, /* special_function */
131 "R_ARM_REL32", /* name */
132 FALSE, /* partial_inplace */
133 0xffffffff, /* src_mask */
134 0xffffffff, /* dst_mask */
135 TRUE), /* pcrel_offset */
136
c19d1205 137 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 138 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 139 0, /* rightshift */
140 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 141 32, /* bitsize */
142 TRUE, /* pc_relative */
7f266840 143 0, /* bitpos */
4962c51a 144 complain_overflow_dont,/* complain_on_overflow */
7f266840 145 bfd_elf_generic_reloc, /* special_function */
4962c51a 146 "R_ARM_LDR_PC_G0", /* name */
7f266840 147 FALSE, /* partial_inplace */
4962c51a
MS		 148 0xffffffff, /* src_mask */
149 0xffffffff, /* dst_mask */
150 TRUE), /* pcrel_offset */
7f266840
DJ		 151
152 /* 16 bit absolute */
153 HOWTO (R_ARM_ABS16, /* type */
154 0, /* rightshift */
155 1, /* size (0 = byte, 1 = short, 2 = long) */
156 16, /* bitsize */
157 FALSE, /* pc_relative */
158 0, /* bitpos */
159 complain_overflow_bitfield,/* complain_on_overflow */
160 bfd_elf_generic_reloc, /* special_function */
161 "R_ARM_ABS16", /* name */
162 FALSE, /* partial_inplace */
163 0x0000ffff, /* src_mask */
164 0x0000ffff, /* dst_mask */
165 FALSE), /* pcrel_offset */
166
167 /* 12 bit absolute */
168 HOWTO (R_ARM_ABS12, /* type */
169 0, /* rightshift */
170 2, /* size (0 = byte, 1 = short, 2 = long) */
171 12, /* bitsize */
172 FALSE, /* pc_relative */
173 0, /* bitpos */
174 complain_overflow_bitfield,/* complain_on_overflow */
175 bfd_elf_generic_reloc, /* special_function */
176 "R_ARM_ABS12", /* name */
177 FALSE, /* partial_inplace */
00a97672
RS		 178 0x00000fff, /* src_mask */
179 0x00000fff, /* dst_mask */
7f266840
DJ		 180 FALSE), /* pcrel_offset */
181
182 HOWTO (R_ARM_THM_ABS5, /* type */
183 6, /* rightshift */
184 1, /* size (0 = byte, 1 = short, 2 = long) */
185 5, /* bitsize */
186 FALSE, /* pc_relative */
187 0, /* bitpos */
188 complain_overflow_bitfield,/* complain_on_overflow */
189 bfd_elf_generic_reloc, /* special_function */
190 "R_ARM_THM_ABS5", /* name */
191 FALSE, /* partial_inplace */
192 0x000007e0, /* src_mask */
193 0x000007e0, /* dst_mask */
194 FALSE), /* pcrel_offset */
195
196 /* 8 bit absolute */
197 HOWTO (R_ARM_ABS8, /* type */
198 0, /* rightshift */
199 0, /* size (0 = byte, 1 = short, 2 = long) */
200 8, /* bitsize */
201 FALSE, /* pc_relative */
202 0, /* bitpos */
203 complain_overflow_bitfield,/* complain_on_overflow */
204 bfd_elf_generic_reloc, /* special_function */
205 "R_ARM_ABS8", /* name */
206 FALSE, /* partial_inplace */
207 0x000000ff, /* src_mask */
208 0x000000ff, /* dst_mask */
209 FALSE), /* pcrel_offset */
210
211 HOWTO (R_ARM_SBREL32, /* type */
212 0, /* rightshift */
213 2, /* size (0 = byte, 1 = short, 2 = long) */
214 32, /* bitsize */
215 FALSE, /* pc_relative */
216 0, /* bitpos */
217 complain_overflow_dont,/* complain_on_overflow */
218 bfd_elf_generic_reloc, /* special_function */
219 "R_ARM_SBREL32", /* name */
220 FALSE, /* partial_inplace */
221 0xffffffff, /* src_mask */
222 0xffffffff, /* dst_mask */
223 FALSE), /* pcrel_offset */
224
c19d1205 225 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 226 1, /* rightshift */
227 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 228 24, /* bitsize */
7f266840
DJ		 229 TRUE, /* pc_relative */
230 0, /* bitpos */
231 complain_overflow_signed,/* complain_on_overflow */
232 bfd_elf_generic_reloc, /* special_function */
c19d1205 233 "R_ARM_THM_CALL", /* name */
7f266840 234 FALSE, /* partial_inplace */
7f6ab9f8
AM		 235 0x07ff2fff, /* src_mask */
236 0x07ff2fff, /* dst_mask */
7f266840
DJ		 237 TRUE), /* pcrel_offset */
238
07d6d2b8 239 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 240 1, /* rightshift */
241 1, /* size (0 = byte, 1 = short, 2 = long) */
242 8, /* bitsize */
243 TRUE, /* pc_relative */
244 0, /* bitpos */
245 complain_overflow_signed,/* complain_on_overflow */
246 bfd_elf_generic_reloc, /* special_function */
247 "R_ARM_THM_PC8", /* name */
248 FALSE, /* partial_inplace */
249 0x000000ff, /* src_mask */
250 0x000000ff, /* dst_mask */
251 TRUE), /* pcrel_offset */
252
c19d1205 253 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 254 1, /* rightshift */
255 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 256 32, /* bitsize */
257 FALSE, /* pc_relative */
7f266840
DJ		 258 0, /* bitpos */
259 complain_overflow_signed,/* complain_on_overflow */
260 bfd_elf_generic_reloc, /* special_function */
c19d1205 261 "R_ARM_BREL_ADJ", /* name */
7f266840 262 FALSE, /* partial_inplace */
c19d1205
ZW		 263 0xffffffff, /* src_mask */
264 0xffffffff, /* dst_mask */
265 FALSE), /* pcrel_offset */
7f266840 266
0855e32b 267 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 268 0, /* rightshift */
0855e32b
NS		 269 2, /* size (0 = byte, 1 = short, 2 = long) */
270 32, /* bitsize */
7f266840
DJ		 271 FALSE, /* pc_relative */
272 0, /* bitpos */
0855e32b 273 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 274 bfd_elf_generic_reloc, /* special_function */
0855e32b 275 "R_ARM_TLS_DESC", /* name */
7f266840 276 FALSE, /* partial_inplace */
0855e32b
NS		 277 0xffffffff, /* src_mask */
278 0xffffffff, /* dst_mask */
7f266840
DJ		 279 FALSE), /* pcrel_offset */
280
281 HOWTO (R_ARM_THM_SWI8, /* type */
282 0, /* rightshift */
283 0, /* size (0 = byte, 1 = short, 2 = long) */
284 0, /* bitsize */
285 FALSE, /* pc_relative */
286 0, /* bitpos */
287 complain_overflow_signed,/* complain_on_overflow */
288 bfd_elf_generic_reloc, /* special_function */
289 "R_ARM_SWI8", /* name */
290 FALSE, /* partial_inplace */
291 0x00000000, /* src_mask */
292 0x00000000, /* dst_mask */
293 FALSE), /* pcrel_offset */
294
295 /* BLX instruction for the ARM. */
296 HOWTO (R_ARM_XPC25, /* type */
297 2, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 299 24, /* bitsize */
7f266840
DJ		 300 TRUE, /* pc_relative */
301 0, /* bitpos */
302 complain_overflow_signed,/* complain_on_overflow */
303 bfd_elf_generic_reloc, /* special_function */
304 "R_ARM_XPC25", /* name */
305 FALSE, /* partial_inplace */
306 0x00ffffff, /* src_mask */
307 0x00ffffff, /* dst_mask */
308 TRUE), /* pcrel_offset */
309
310 /* BLX instruction for the Thumb. */
311 HOWTO (R_ARM_THM_XPC22, /* type */
312 2, /* rightshift */
313 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 314 24, /* bitsize */
7f266840
DJ		 315 TRUE, /* pc_relative */
316 0, /* bitpos */
317 complain_overflow_signed,/* complain_on_overflow */
318 bfd_elf_generic_reloc, /* special_function */
319 "R_ARM_THM_XPC22", /* name */
320 FALSE, /* partial_inplace */
7f6ab9f8
AM		 321 0x07ff2fff, /* src_mask */
322 0x07ff2fff, /* dst_mask */
7f266840
DJ		 323 TRUE), /* pcrel_offset */
324
ba93b8ac 325 /* Dynamic TLS relocations. */
7f266840 326
ba93b8ac 327 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 328 0, /* rightshift */
329 2, /* size (0 = byte, 1 = short, 2 = long) */
330 32, /* bitsize */
331 FALSE, /* pc_relative */
332 0, /* bitpos */
99059e56
RM		 333 complain_overflow_bitfield,/* complain_on_overflow */
334 bfd_elf_generic_reloc, /* special_function */
335 "R_ARM_TLS_DTPMOD32", /* name */
336 TRUE, /* partial_inplace */
337 0xffffffff, /* src_mask */
338 0xffffffff, /* dst_mask */
07d6d2b8 339 FALSE), /* pcrel_offset */
7f266840 340
ba93b8ac 341 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 342 0, /* rightshift */
343 2, /* size (0 = byte, 1 = short, 2 = long) */
344 32, /* bitsize */
345 FALSE, /* pc_relative */
346 0, /* bitpos */
99059e56
RM		 347 complain_overflow_bitfield,/* complain_on_overflow */
348 bfd_elf_generic_reloc, /* special_function */
349 "R_ARM_TLS_DTPOFF32", /* name */
350 TRUE, /* partial_inplace */
351 0xffffffff, /* src_mask */
352 0xffffffff, /* dst_mask */
07d6d2b8 353 FALSE), /* pcrel_offset */
7f266840 354
ba93b8ac 355 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 356 0, /* rightshift */
357 2, /* size (0 = byte, 1 = short, 2 = long) */
358 32, /* bitsize */
359 FALSE, /* pc_relative */
360 0, /* bitpos */
99059e56
RM		 361 complain_overflow_bitfield,/* complain_on_overflow */
362 bfd_elf_generic_reloc, /* special_function */
363 "R_ARM_TLS_TPOFF32", /* name */
364 TRUE, /* partial_inplace */
365 0xffffffff, /* src_mask */
366 0xffffffff, /* dst_mask */
07d6d2b8 367 FALSE), /* pcrel_offset */
7f266840
DJ		 368
369 /* Relocs used in ARM Linux */
370
371 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 372 0, /* rightshift */
373 2, /* size (0 = byte, 1 = short, 2 = long) */
374 32, /* bitsize */
375 FALSE, /* pc_relative */
376 0, /* bitpos */
99059e56
RM		 377 complain_overflow_bitfield,/* complain_on_overflow */
378 bfd_elf_generic_reloc, /* special_function */
379 "R_ARM_COPY", /* name */
380 TRUE, /* partial_inplace */
381 0xffffffff, /* src_mask */
382 0xffffffff, /* dst_mask */
07d6d2b8 383 FALSE), /* pcrel_offset */
7f266840
DJ		 384
385 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 386 0, /* rightshift */
387 2, /* size (0 = byte, 1 = short, 2 = long) */
388 32, /* bitsize */
389 FALSE, /* pc_relative */
390 0, /* bitpos */
99059e56
RM		 391 complain_overflow_bitfield,/* complain_on_overflow */
392 bfd_elf_generic_reloc, /* special_function */
393 "R_ARM_GLOB_DAT", /* name */
394 TRUE, /* partial_inplace */
395 0xffffffff, /* src_mask */
396 0xffffffff, /* dst_mask */
07d6d2b8 397 FALSE), /* pcrel_offset */
7f266840
DJ		 398
399 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 400 0, /* rightshift */
401 2, /* size (0 = byte, 1 = short, 2 = long) */
402 32, /* bitsize */
403 FALSE, /* pc_relative */
404 0, /* bitpos */
99059e56
RM		 405 complain_overflow_bitfield,/* complain_on_overflow */
406 bfd_elf_generic_reloc, /* special_function */
407 "R_ARM_JUMP_SLOT", /* name */
408 TRUE, /* partial_inplace */
409 0xffffffff, /* src_mask */
410 0xffffffff, /* dst_mask */
07d6d2b8 411 FALSE), /* pcrel_offset */
7f266840
DJ		 412
413 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 414 0, /* rightshift */
415 2, /* size (0 = byte, 1 = short, 2 = long) */
416 32, /* bitsize */
417 FALSE, /* pc_relative */
418 0, /* bitpos */
99059e56
RM		 419 complain_overflow_bitfield,/* complain_on_overflow */
420 bfd_elf_generic_reloc, /* special_function */
421 "R_ARM_RELATIVE", /* name */
422 TRUE, /* partial_inplace */
423 0xffffffff, /* src_mask */
424 0xffffffff, /* dst_mask */
07d6d2b8 425 FALSE), /* pcrel_offset */
7f266840 426
c19d1205 427 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 428 0, /* rightshift */
429 2, /* size (0 = byte, 1 = short, 2 = long) */
430 32, /* bitsize */
431 FALSE, /* pc_relative */
432 0, /* bitpos */
99059e56
RM		 433 complain_overflow_bitfield,/* complain_on_overflow */
434 bfd_elf_generic_reloc, /* special_function */
435 "R_ARM_GOTOFF32", /* name */
436 TRUE, /* partial_inplace */
437 0xffffffff, /* src_mask */
438 0xffffffff, /* dst_mask */
07d6d2b8 439 FALSE), /* pcrel_offset */
7f266840
DJ		 440
441 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 442 0, /* rightshift */
443 2, /* size (0 = byte, 1 = short, 2 = long) */
444 32, /* bitsize */
99059e56 445 TRUE, /* pc_relative */
07d6d2b8 446 0, /* bitpos */
99059e56
RM		 447 complain_overflow_bitfield,/* complain_on_overflow */
448 bfd_elf_generic_reloc, /* special_function */
449 "R_ARM_GOTPC", /* name */
450 TRUE, /* partial_inplace */
451 0xffffffff, /* src_mask */
452 0xffffffff, /* dst_mask */
453 TRUE), /* pcrel_offset */
7f266840
DJ		 454
455 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 456 0, /* rightshift */
457 2, /* size (0 = byte, 1 = short, 2 = long) */
458 32, /* bitsize */
99059e56 459 FALSE, /* pc_relative */
07d6d2b8 460 0, /* bitpos */
99059e56
RM		 461 complain_overflow_bitfield,/* complain_on_overflow */
462 bfd_elf_generic_reloc, /* special_function */
463 "R_ARM_GOT32", /* name */
464 TRUE, /* partial_inplace */
465 0xffffffff, /* src_mask */
466 0xffffffff, /* dst_mask */
467 FALSE), /* pcrel_offset */
7f266840
DJ		 468
469 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 470 2, /* rightshift */
471 2, /* size (0 = byte, 1 = short, 2 = long) */
472 24, /* bitsize */
99059e56 473 TRUE, /* pc_relative */
07d6d2b8 474 0, /* bitpos */
99059e56
RM		 475 complain_overflow_bitfield,/* complain_on_overflow */
476 bfd_elf_generic_reloc, /* special_function */
477 "R_ARM_PLT32", /* name */
478 FALSE, /* partial_inplace */
479 0x00ffffff, /* src_mask */
480 0x00ffffff, /* dst_mask */
481 TRUE), /* pcrel_offset */
7f266840
DJ		 482
483 HOWTO (R_ARM_CALL, /* type */
484 2, /* rightshift */
485 2, /* size (0 = byte, 1 = short, 2 = long) */
486 24, /* bitsize */
487 TRUE, /* pc_relative */
488 0, /* bitpos */
489 complain_overflow_signed,/* complain_on_overflow */
490 bfd_elf_generic_reloc, /* special_function */
491 "R_ARM_CALL", /* name */
492 FALSE, /* partial_inplace */
493 0x00ffffff, /* src_mask */
494 0x00ffffff, /* dst_mask */
495 TRUE), /* pcrel_offset */
496
497 HOWTO (R_ARM_JUMP24, /* type */
498 2, /* rightshift */
499 2, /* size (0 = byte, 1 = short, 2 = long) */
500 24, /* bitsize */
501 TRUE, /* pc_relative */
502 0, /* bitpos */
503 complain_overflow_signed,/* complain_on_overflow */
504 bfd_elf_generic_reloc, /* special_function */
505 "R_ARM_JUMP24", /* name */
506 FALSE, /* partial_inplace */
507 0x00ffffff, /* src_mask */
508 0x00ffffff, /* dst_mask */
509 TRUE), /* pcrel_offset */
510
c19d1205
ZW		 511 HOWTO (R_ARM_THM_JUMP24, /* type */
512 1, /* rightshift */
513 2, /* size (0 = byte, 1 = short, 2 = long) */
514 24, /* bitsize */
515 TRUE, /* pc_relative */
7f266840 516 0, /* bitpos */
c19d1205 517 complain_overflow_signed,/* complain_on_overflow */
7f266840 518 bfd_elf_generic_reloc, /* special_function */
c19d1205 519 "R_ARM_THM_JUMP24", /* name */
7f266840 520 FALSE, /* partial_inplace */
c19d1205
ZW		 521 0x07ff2fff, /* src_mask */
522 0x07ff2fff, /* dst_mask */
523 TRUE), /* pcrel_offset */
7f266840 524
c19d1205 525 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 526 0, /* rightshift */
c19d1205
ZW		 527 2, /* size (0 = byte, 1 = short, 2 = long) */
528 32, /* bitsize */
7f266840
DJ		 529 FALSE, /* pc_relative */
530 0, /* bitpos */
531 complain_overflow_dont,/* complain_on_overflow */
532 bfd_elf_generic_reloc, /* special_function */
c19d1205 533 "R_ARM_BASE_ABS", /* name */
7f266840 534 FALSE, /* partial_inplace */
c19d1205
ZW		 535 0xffffffff, /* src_mask */
536 0xffffffff, /* dst_mask */
7f266840
DJ		 537 FALSE), /* pcrel_offset */
538
539 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
540 0, /* rightshift */
541 2, /* size (0 = byte, 1 = short, 2 = long) */
542 12, /* bitsize */
543 TRUE, /* pc_relative */
544 0, /* bitpos */
545 complain_overflow_dont,/* complain_on_overflow */
546 bfd_elf_generic_reloc, /* special_function */
547 "R_ARM_ALU_PCREL_7_0", /* name */
548 FALSE, /* partial_inplace */
549 0x00000fff, /* src_mask */
550 0x00000fff, /* dst_mask */
551 TRUE), /* pcrel_offset */
552
553 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
554 0, /* rightshift */
555 2, /* size (0 = byte, 1 = short, 2 = long) */
556 12, /* bitsize */
557 TRUE, /* pc_relative */
558 8, /* bitpos */
559 complain_overflow_dont,/* complain_on_overflow */
560 bfd_elf_generic_reloc, /* special_function */
561 "R_ARM_ALU_PCREL_15_8",/* name */
562 FALSE, /* partial_inplace */
563 0x00000fff, /* src_mask */
564 0x00000fff, /* dst_mask */
565 TRUE), /* pcrel_offset */
566
567 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
568 0, /* rightshift */
569 2, /* size (0 = byte, 1 = short, 2 = long) */
570 12, /* bitsize */
571 TRUE, /* pc_relative */
572 16, /* bitpos */
573 complain_overflow_dont,/* complain_on_overflow */
574 bfd_elf_generic_reloc, /* special_function */
575 "R_ARM_ALU_PCREL_23_15",/* name */
576 FALSE, /* partial_inplace */
577 0x00000fff, /* src_mask */
578 0x00000fff, /* dst_mask */
579 TRUE), /* pcrel_offset */
580
581 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
582 0, /* rightshift */
583 2, /* size (0 = byte, 1 = short, 2 = long) */
584 12, /* bitsize */
585 FALSE, /* pc_relative */
586 0, /* bitpos */
587 complain_overflow_dont,/* complain_on_overflow */
588 bfd_elf_generic_reloc, /* special_function */
589 "R_ARM_LDR_SBREL_11_0",/* name */
590 FALSE, /* partial_inplace */
591 0x00000fff, /* src_mask */
592 0x00000fff, /* dst_mask */
593 FALSE), /* pcrel_offset */
594
595 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
596 0, /* rightshift */
597 2, /* size (0 = byte, 1 = short, 2 = long) */
598 8, /* bitsize */
599 FALSE, /* pc_relative */
600 12, /* bitpos */
601 complain_overflow_dont,/* complain_on_overflow */
602 bfd_elf_generic_reloc, /* special_function */
603 "R_ARM_ALU_SBREL_19_12",/* name */
604 FALSE, /* partial_inplace */
605 0x000ff000, /* src_mask */
606 0x000ff000, /* dst_mask */
607 FALSE), /* pcrel_offset */
608
609 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
610 0, /* rightshift */
611 2, /* size (0 = byte, 1 = short, 2 = long) */
612 8, /* bitsize */
613 FALSE, /* pc_relative */
614 20, /* bitpos */
615 complain_overflow_dont,/* complain_on_overflow */
616 bfd_elf_generic_reloc, /* special_function */
617 "R_ARM_ALU_SBREL_27_20",/* name */
618 FALSE, /* partial_inplace */
619 0x0ff00000, /* src_mask */
620 0x0ff00000, /* dst_mask */
621 FALSE), /* pcrel_offset */
622
623 HOWTO (R_ARM_TARGET1, /* type */
624 0, /* rightshift */
625 2, /* size (0 = byte, 1 = short, 2 = long) */
626 32, /* bitsize */
627 FALSE, /* pc_relative */
628 0, /* bitpos */
629 complain_overflow_dont,/* complain_on_overflow */
630 bfd_elf_generic_reloc, /* special_function */
631 "R_ARM_TARGET1", /* name */
632 FALSE, /* partial_inplace */
633 0xffffffff, /* src_mask */
634 0xffffffff, /* dst_mask */
635 FALSE), /* pcrel_offset */
636
637 HOWTO (R_ARM_ROSEGREL32, /* type */
638 0, /* rightshift */
639 2, /* size (0 = byte, 1 = short, 2 = long) */
640 32, /* bitsize */
641 FALSE, /* pc_relative */
642 0, /* bitpos */
643 complain_overflow_dont,/* complain_on_overflow */
644 bfd_elf_generic_reloc, /* special_function */
645 "R_ARM_ROSEGREL32", /* name */
646 FALSE, /* partial_inplace */
647 0xffffffff, /* src_mask */
648 0xffffffff, /* dst_mask */
649 FALSE), /* pcrel_offset */
650
651 HOWTO (R_ARM_V4BX, /* type */
652 0, /* rightshift */
653 2, /* size (0 = byte, 1 = short, 2 = long) */
654 32, /* bitsize */
655 FALSE, /* pc_relative */
656 0, /* bitpos */
657 complain_overflow_dont,/* complain_on_overflow */
658 bfd_elf_generic_reloc, /* special_function */
659 "R_ARM_V4BX", /* name */
660 FALSE, /* partial_inplace */
661 0xffffffff, /* src_mask */
662 0xffffffff, /* dst_mask */
663 FALSE), /* pcrel_offset */
664
665 HOWTO (R_ARM_TARGET2, /* type */
666 0, /* rightshift */
667 2, /* size (0 = byte, 1 = short, 2 = long) */
668 32, /* bitsize */
669 FALSE, /* pc_relative */
670 0, /* bitpos */
671 complain_overflow_signed,/* complain_on_overflow */
672 bfd_elf_generic_reloc, /* special_function */
673 "R_ARM_TARGET2", /* name */
674 FALSE, /* partial_inplace */
675 0xffffffff, /* src_mask */
676 0xffffffff, /* dst_mask */
677 TRUE), /* pcrel_offset */
678
679 HOWTO (R_ARM_PREL31, /* type */
680 0, /* rightshift */
681 2, /* size (0 = byte, 1 = short, 2 = long) */
682 31, /* bitsize */
683 TRUE, /* pc_relative */
684 0, /* bitpos */
685 complain_overflow_signed,/* complain_on_overflow */
686 bfd_elf_generic_reloc, /* special_function */
687 "R_ARM_PREL31", /* name */
688 FALSE, /* partial_inplace */
689 0x7fffffff, /* src_mask */
690 0x7fffffff, /* dst_mask */
691 TRUE), /* pcrel_offset */
c19d1205
ZW		 692
693 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
694 0, /* rightshift */
695 2, /* size (0 = byte, 1 = short, 2 = long) */
696 16, /* bitsize */
697 FALSE, /* pc_relative */
698 0, /* bitpos */
699 complain_overflow_dont,/* complain_on_overflow */
700 bfd_elf_generic_reloc, /* special_function */
701 "R_ARM_MOVW_ABS_NC", /* name */
702 FALSE, /* partial_inplace */
39623e12
PB		 703 0x000f0fff, /* src_mask */
704 0x000f0fff, /* dst_mask */
c19d1205
ZW		 705 FALSE), /* pcrel_offset */
706
707 HOWTO (R_ARM_MOVT_ABS, /* type */
708 0, /* rightshift */
709 2, /* size (0 = byte, 1 = short, 2 = long) */
710 16, /* bitsize */
711 FALSE, /* pc_relative */
712 0, /* bitpos */
713 complain_overflow_bitfield,/* complain_on_overflow */
714 bfd_elf_generic_reloc, /* special_function */
715 "R_ARM_MOVT_ABS", /* name */
716 FALSE, /* partial_inplace */
39623e12
PB		 717 0x000f0fff, /* src_mask */
718 0x000f0fff, /* dst_mask */
c19d1205
ZW		 719 FALSE), /* pcrel_offset */
720
721 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
722 0, /* rightshift */
723 2, /* size (0 = byte, 1 = short, 2 = long) */
724 16, /* bitsize */
725 TRUE, /* pc_relative */
726 0, /* bitpos */
727 complain_overflow_dont,/* complain_on_overflow */
728 bfd_elf_generic_reloc, /* special_function */
729 "R_ARM_MOVW_PREL_NC", /* name */
730 FALSE, /* partial_inplace */
39623e12
PB		 731 0x000f0fff, /* src_mask */
732 0x000f0fff, /* dst_mask */
c19d1205
ZW		 733 TRUE), /* pcrel_offset */
734
735 HOWTO (R_ARM_MOVT_PREL, /* type */
736 0, /* rightshift */
737 2, /* size (0 = byte, 1 = short, 2 = long) */
738 16, /* bitsize */
739 TRUE, /* pc_relative */
740 0, /* bitpos */
741 complain_overflow_bitfield,/* complain_on_overflow */
742 bfd_elf_generic_reloc, /* special_function */
743 "R_ARM_MOVT_PREL", /* name */
744 FALSE, /* partial_inplace */
39623e12
PB		 745 0x000f0fff, /* src_mask */
746 0x000f0fff, /* dst_mask */
c19d1205
ZW		 747 TRUE), /* pcrel_offset */
748
749 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
750 0, /* rightshift */
751 2, /* size (0 = byte, 1 = short, 2 = long) */
752 16, /* bitsize */
753 FALSE, /* pc_relative */
754 0, /* bitpos */
755 complain_overflow_dont,/* complain_on_overflow */
756 bfd_elf_generic_reloc, /* special_function */
757 "R_ARM_THM_MOVW_ABS_NC",/* name */
758 FALSE, /* partial_inplace */
759 0x040f70ff, /* src_mask */
760 0x040f70ff, /* dst_mask */
761 FALSE), /* pcrel_offset */
762
763 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
764 0, /* rightshift */
765 2, /* size (0 = byte, 1 = short, 2 = long) */
766 16, /* bitsize */
767 FALSE, /* pc_relative */
768 0, /* bitpos */
769 complain_overflow_bitfield,/* complain_on_overflow */
770 bfd_elf_generic_reloc, /* special_function */
771 "R_ARM_THM_MOVT_ABS", /* name */
772 FALSE, /* partial_inplace */
773 0x040f70ff, /* src_mask */
774 0x040f70ff, /* dst_mask */
775 FALSE), /* pcrel_offset */
776
777 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
778 0, /* rightshift */
779 2, /* size (0 = byte, 1 = short, 2 = long) */
780 16, /* bitsize */
781 TRUE, /* pc_relative */
782 0, /* bitpos */
783 complain_overflow_dont,/* complain_on_overflow */
784 bfd_elf_generic_reloc, /* special_function */
785 "R_ARM_THM_MOVW_PREL_NC",/* name */
786 FALSE, /* partial_inplace */
787 0x040f70ff, /* src_mask */
788 0x040f70ff, /* dst_mask */
789 TRUE), /* pcrel_offset */
790
791 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
792 0, /* rightshift */
793 2, /* size (0 = byte, 1 = short, 2 = long) */
794 16, /* bitsize */
795 TRUE, /* pc_relative */
796 0, /* bitpos */
797 complain_overflow_bitfield,/* complain_on_overflow */
798 bfd_elf_generic_reloc, /* special_function */
799 "R_ARM_THM_MOVT_PREL", /* name */
800 FALSE, /* partial_inplace */
801 0x040f70ff, /* src_mask */
802 0x040f70ff, /* dst_mask */
803 TRUE), /* pcrel_offset */
804
805 HOWTO (R_ARM_THM_JUMP19, /* type */
806 1, /* rightshift */
807 2, /* size (0 = byte, 1 = short, 2 = long) */
808 19, /* bitsize */
809 TRUE, /* pc_relative */
810 0, /* bitpos */
811 complain_overflow_signed,/* complain_on_overflow */
812 bfd_elf_generic_reloc, /* special_function */
813 "R_ARM_THM_JUMP19", /* name */
814 FALSE, /* partial_inplace */
815 0x043f2fff, /* src_mask */
816 0x043f2fff, /* dst_mask */
817 TRUE), /* pcrel_offset */
818
819 HOWTO (R_ARM_THM_JUMP6, /* type */
820 1, /* rightshift */
821 1, /* size (0 = byte, 1 = short, 2 = long) */
822 6, /* bitsize */
823 TRUE, /* pc_relative */
824 0, /* bitpos */
825 complain_overflow_unsigned,/* complain_on_overflow */
826 bfd_elf_generic_reloc, /* special_function */
827 "R_ARM_THM_JUMP6", /* name */
828 FALSE, /* partial_inplace */
829 0x02f8, /* src_mask */
830 0x02f8, /* dst_mask */
831 TRUE), /* pcrel_offset */
832
833 /* These are declared as 13-bit signed relocations because we can
834 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
835 versa. */
836 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
837 0, /* rightshift */
838 2, /* size (0 = byte, 1 = short, 2 = long) */
839 13, /* bitsize */
840 TRUE, /* pc_relative */
841 0, /* bitpos */
2cab6cc3 842 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 843 bfd_elf_generic_reloc, /* special_function */
844 "R_ARM_THM_ALU_PREL_11_0",/* name */
845 FALSE, /* partial_inplace */
2cab6cc3
MS		 846 0xffffffff, /* src_mask */
847 0xffffffff, /* dst_mask */
c19d1205
ZW		 848 TRUE), /* pcrel_offset */
849
850 HOWTO (R_ARM_THM_PC12, /* type */
851 0, /* rightshift */
852 2, /* size (0 = byte, 1 = short, 2 = long) */
853 13, /* bitsize */
854 TRUE, /* pc_relative */
855 0, /* bitpos */
2cab6cc3 856 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 857 bfd_elf_generic_reloc, /* special_function */
858 "R_ARM_THM_PC12", /* name */
859 FALSE, /* partial_inplace */
2cab6cc3
MS		 860 0xffffffff, /* src_mask */
861 0xffffffff, /* dst_mask */
c19d1205
ZW		 862 TRUE), /* pcrel_offset */
863
864 HOWTO (R_ARM_ABS32_NOI, /* type */
865 0, /* rightshift */
866 2, /* size (0 = byte, 1 = short, 2 = long) */
867 32, /* bitsize */
868 FALSE, /* pc_relative */
869 0, /* bitpos */
870 complain_overflow_dont,/* complain_on_overflow */
871 bfd_elf_generic_reloc, /* special_function */
872 "R_ARM_ABS32_NOI", /* name */
873 FALSE, /* partial_inplace */
874 0xffffffff, /* src_mask */
875 0xffffffff, /* dst_mask */
876 FALSE), /* pcrel_offset */
877
878 HOWTO (R_ARM_REL32_NOI, /* type */
879 0, /* rightshift */
880 2, /* size (0 = byte, 1 = short, 2 = long) */
881 32, /* bitsize */
882 TRUE, /* pc_relative */
883 0, /* bitpos */
884 complain_overflow_dont,/* complain_on_overflow */
885 bfd_elf_generic_reloc, /* special_function */
886 "R_ARM_REL32_NOI", /* name */
887 FALSE, /* partial_inplace */
888 0xffffffff, /* src_mask */
889 0xffffffff, /* dst_mask */
890 FALSE), /* pcrel_offset */
7f266840 891
4962c51a
MS		 892 /* Group relocations. */
893
894 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
895 0, /* rightshift */
896 2, /* size (0 = byte, 1 = short, 2 = long) */
897 32, /* bitsize */
898 TRUE, /* pc_relative */
899 0, /* bitpos */
900 complain_overflow_dont,/* complain_on_overflow */
901 bfd_elf_generic_reloc, /* special_function */
902 "R_ARM_ALU_PC_G0_NC", /* name */
903 FALSE, /* partial_inplace */
904 0xffffffff, /* src_mask */
905 0xffffffff, /* dst_mask */
906 TRUE), /* pcrel_offset */
907
07d6d2b8 908 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 909 0, /* rightshift */
910 2, /* size (0 = byte, 1 = short, 2 = long) */
911 32, /* bitsize */
912 TRUE, /* pc_relative */
913 0, /* bitpos */
914 complain_overflow_dont,/* complain_on_overflow */
915 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 916 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 917 FALSE, /* partial_inplace */
918 0xffffffff, /* src_mask */
919 0xffffffff, /* dst_mask */
920 TRUE), /* pcrel_offset */
921
922 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
923 0, /* rightshift */
924 2, /* size (0 = byte, 1 = short, 2 = long) */
925 32, /* bitsize */
926 TRUE, /* pc_relative */
927 0, /* bitpos */
928 complain_overflow_dont,/* complain_on_overflow */
929 bfd_elf_generic_reloc, /* special_function */
930 "R_ARM_ALU_PC_G1_NC", /* name */
931 FALSE, /* partial_inplace */
932 0xffffffff, /* src_mask */
933 0xffffffff, /* dst_mask */
934 TRUE), /* pcrel_offset */
935
07d6d2b8 936 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 937 0, /* rightshift */
938 2, /* size (0 = byte, 1 = short, 2 = long) */
939 32, /* bitsize */
940 TRUE, /* pc_relative */
941 0, /* bitpos */
942 complain_overflow_dont,/* complain_on_overflow */
943 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 944 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 945 FALSE, /* partial_inplace */
946 0xffffffff, /* src_mask */
947 0xffffffff, /* dst_mask */
948 TRUE), /* pcrel_offset */
949
07d6d2b8 950 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 951 0, /* rightshift */
952 2, /* size (0 = byte, 1 = short, 2 = long) */
953 32, /* bitsize */
954 TRUE, /* pc_relative */
955 0, /* bitpos */
956 complain_overflow_dont,/* complain_on_overflow */
957 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 958 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 959 FALSE, /* partial_inplace */
960 0xffffffff, /* src_mask */
961 0xffffffff, /* dst_mask */
962 TRUE), /* pcrel_offset */
963
07d6d2b8 964 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 965 0, /* rightshift */
966 2, /* size (0 = byte, 1 = short, 2 = long) */
967 32, /* bitsize */
968 TRUE, /* pc_relative */
969 0, /* bitpos */
970 complain_overflow_dont,/* complain_on_overflow */
971 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 972 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 973 FALSE, /* partial_inplace */
974 0xffffffff, /* src_mask */
975 0xffffffff, /* dst_mask */
976 TRUE), /* pcrel_offset */
977
07d6d2b8 978 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 979 0, /* rightshift */
980 2, /* size (0 = byte, 1 = short, 2 = long) */
981 32, /* bitsize */
982 TRUE, /* pc_relative */
983 0, /* bitpos */
984 complain_overflow_dont,/* complain_on_overflow */
985 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 986 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 987 FALSE, /* partial_inplace */
988 0xffffffff, /* src_mask */
989 0xffffffff, /* dst_mask */
990 TRUE), /* pcrel_offset */
991
07d6d2b8 992 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 993 0, /* rightshift */
994 2, /* size (0 = byte, 1 = short, 2 = long) */
995 32, /* bitsize */
996 TRUE, /* pc_relative */
997 0, /* bitpos */
998 complain_overflow_dont,/* complain_on_overflow */
999 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1000 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1001 FALSE, /* partial_inplace */
1002 0xffffffff, /* src_mask */
1003 0xffffffff, /* dst_mask */
1004 TRUE), /* pcrel_offset */
1005
07d6d2b8 1006 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1007 0, /* rightshift */
1008 2, /* size (0 = byte, 1 = short, 2 = long) */
1009 32, /* bitsize */
1010 TRUE, /* pc_relative */
1011 0, /* bitpos */
1012 complain_overflow_dont,/* complain_on_overflow */
1013 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1014 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1015 FALSE, /* partial_inplace */
1016 0xffffffff, /* src_mask */
1017 0xffffffff, /* dst_mask */
1018 TRUE), /* pcrel_offset */
1019
07d6d2b8 1020 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1021 0, /* rightshift */
1022 2, /* size (0 = byte, 1 = short, 2 = long) */
1023 32, /* bitsize */
1024 TRUE, /* pc_relative */
1025 0, /* bitpos */
1026 complain_overflow_dont,/* complain_on_overflow */
1027 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1028 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1029 FALSE, /* partial_inplace */
1030 0xffffffff, /* src_mask */
1031 0xffffffff, /* dst_mask */
1032 TRUE), /* pcrel_offset */
1033
07d6d2b8 1034 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1035 0, /* rightshift */
1036 2, /* size (0 = byte, 1 = short, 2 = long) */
1037 32, /* bitsize */
1038 TRUE, /* pc_relative */
1039 0, /* bitpos */
1040 complain_overflow_dont,/* complain_on_overflow */
1041 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1042 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1043 FALSE, /* partial_inplace */
1044 0xffffffff, /* src_mask */
1045 0xffffffff, /* dst_mask */
1046 TRUE), /* pcrel_offset */
1047
07d6d2b8 1048 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1049 0, /* rightshift */
1050 2, /* size (0 = byte, 1 = short, 2 = long) */
1051 32, /* bitsize */
1052 TRUE, /* pc_relative */
1053 0, /* bitpos */
1054 complain_overflow_dont,/* complain_on_overflow */
1055 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1056 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1057 FALSE, /* partial_inplace */
1058 0xffffffff, /* src_mask */
1059 0xffffffff, /* dst_mask */
1060 TRUE), /* pcrel_offset */
1061
07d6d2b8 1062 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1063 0, /* rightshift */
1064 2, /* size (0 = byte, 1 = short, 2 = long) */
1065 32, /* bitsize */
1066 TRUE, /* pc_relative */
1067 0, /* bitpos */
1068 complain_overflow_dont,/* complain_on_overflow */
1069 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1070 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1071 FALSE, /* partial_inplace */
1072 0xffffffff, /* src_mask */
1073 0xffffffff, /* dst_mask */
1074 TRUE), /* pcrel_offset */
1075
07d6d2b8 1076 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1077 0, /* rightshift */
1078 2, /* size (0 = byte, 1 = short, 2 = long) */
1079 32, /* bitsize */
1080 TRUE, /* pc_relative */
1081 0, /* bitpos */
1082 complain_overflow_dont,/* complain_on_overflow */
1083 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1084 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1085 FALSE, /* partial_inplace */
1086 0xffffffff, /* src_mask */
1087 0xffffffff, /* dst_mask */
1088 TRUE), /* pcrel_offset */
1089
07d6d2b8 1090 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1091 0, /* rightshift */
1092 2, /* size (0 = byte, 1 = short, 2 = long) */
1093 32, /* bitsize */
1094 TRUE, /* pc_relative */
1095 0, /* bitpos */
1096 complain_overflow_dont,/* complain_on_overflow */
1097 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1098 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1099 FALSE, /* partial_inplace */
1100 0xffffffff, /* src_mask */
1101 0xffffffff, /* dst_mask */
1102 TRUE), /* pcrel_offset */
1103
07d6d2b8 1104 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1105 0, /* rightshift */
1106 2, /* size (0 = byte, 1 = short, 2 = long) */
1107 32, /* bitsize */
1108 TRUE, /* pc_relative */
1109 0, /* bitpos */
1110 complain_overflow_dont,/* complain_on_overflow */
1111 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1112 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1113 FALSE, /* partial_inplace */
1114 0xffffffff, /* src_mask */
1115 0xffffffff, /* dst_mask */
1116 TRUE), /* pcrel_offset */
1117
07d6d2b8 1118 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1119 0, /* rightshift */
1120 2, /* size (0 = byte, 1 = short, 2 = long) */
1121 32, /* bitsize */
1122 TRUE, /* pc_relative */
1123 0, /* bitpos */
1124 complain_overflow_dont,/* complain_on_overflow */
1125 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1126 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1127 FALSE, /* partial_inplace */
1128 0xffffffff, /* src_mask */
1129 0xffffffff, /* dst_mask */
1130 TRUE), /* pcrel_offset */
1131
07d6d2b8 1132 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1133 0, /* rightshift */
1134 2, /* size (0 = byte, 1 = short, 2 = long) */
1135 32, /* bitsize */
1136 TRUE, /* pc_relative */
1137 0, /* bitpos */
1138 complain_overflow_dont,/* complain_on_overflow */
1139 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1140 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1141 FALSE, /* partial_inplace */
1142 0xffffffff, /* src_mask */
1143 0xffffffff, /* dst_mask */
1144 TRUE), /* pcrel_offset */
1145
07d6d2b8 1146 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1147 0, /* rightshift */
1148 2, /* size (0 = byte, 1 = short, 2 = long) */
1149 32, /* bitsize */
1150 TRUE, /* pc_relative */
1151 0, /* bitpos */
1152 complain_overflow_dont,/* complain_on_overflow */
1153 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1154 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1155 FALSE, /* partial_inplace */
1156 0xffffffff, /* src_mask */
1157 0xffffffff, /* dst_mask */
1158 TRUE), /* pcrel_offset */
1159
07d6d2b8 1160 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1161 0, /* rightshift */
1162 2, /* size (0 = byte, 1 = short, 2 = long) */
1163 32, /* bitsize */
1164 TRUE, /* pc_relative */
1165 0, /* bitpos */
1166 complain_overflow_dont,/* complain_on_overflow */
1167 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1168 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1169 FALSE, /* partial_inplace */
1170 0xffffffff, /* src_mask */
1171 0xffffffff, /* dst_mask */
1172 TRUE), /* pcrel_offset */
1173
07d6d2b8 1174 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1175 0, /* rightshift */
1176 2, /* size (0 = byte, 1 = short, 2 = long) */
1177 32, /* bitsize */
1178 TRUE, /* pc_relative */
1179 0, /* bitpos */
1180 complain_overflow_dont,/* complain_on_overflow */
1181 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1182 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1183 FALSE, /* partial_inplace */
1184 0xffffffff, /* src_mask */
1185 0xffffffff, /* dst_mask */
1186 TRUE), /* pcrel_offset */
1187
07d6d2b8 1188 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1189 0, /* rightshift */
1190 2, /* size (0 = byte, 1 = short, 2 = long) */
1191 32, /* bitsize */
1192 TRUE, /* pc_relative */
1193 0, /* bitpos */
1194 complain_overflow_dont,/* complain_on_overflow */
1195 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1196 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1197 FALSE, /* partial_inplace */
1198 0xffffffff, /* src_mask */
1199 0xffffffff, /* dst_mask */
1200 TRUE), /* pcrel_offset */
1201
07d6d2b8 1202 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1203 0, /* rightshift */
1204 2, /* size (0 = byte, 1 = short, 2 = long) */
1205 32, /* bitsize */
1206 TRUE, /* pc_relative */
1207 0, /* bitpos */
1208 complain_overflow_dont,/* complain_on_overflow */
1209 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1210 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1211 FALSE, /* partial_inplace */
1212 0xffffffff, /* src_mask */
1213 0xffffffff, /* dst_mask */
1214 TRUE), /* pcrel_offset */
1215
07d6d2b8 1216 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1217 0, /* rightshift */
1218 2, /* size (0 = byte, 1 = short, 2 = long) */
1219 32, /* bitsize */
1220 TRUE, /* pc_relative */
1221 0, /* bitpos */
1222 complain_overflow_dont,/* complain_on_overflow */
1223 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1224 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1225 FALSE, /* partial_inplace */
1226 0xffffffff, /* src_mask */
1227 0xffffffff, /* dst_mask */
1228 TRUE), /* pcrel_offset */
1229
07d6d2b8 1230 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1231 0, /* rightshift */
1232 2, /* size (0 = byte, 1 = short, 2 = long) */
1233 32, /* bitsize */
1234 TRUE, /* pc_relative */
1235 0, /* bitpos */
1236 complain_overflow_dont,/* complain_on_overflow */
1237 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1238 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1239 FALSE, /* partial_inplace */
1240 0xffffffff, /* src_mask */
1241 0xffffffff, /* dst_mask */
1242 TRUE), /* pcrel_offset */
1243
07d6d2b8 1244 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1245 0, /* rightshift */
1246 2, /* size (0 = byte, 1 = short, 2 = long) */
1247 32, /* bitsize */
1248 TRUE, /* pc_relative */
1249 0, /* bitpos */
1250 complain_overflow_dont,/* complain_on_overflow */
1251 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1252 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1253 FALSE, /* partial_inplace */
1254 0xffffffff, /* src_mask */
1255 0xffffffff, /* dst_mask */
1256 TRUE), /* pcrel_offset */
1257
07d6d2b8 1258 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1259 0, /* rightshift */
1260 2, /* size (0 = byte, 1 = short, 2 = long) */
1261 32, /* bitsize */
1262 TRUE, /* pc_relative */
1263 0, /* bitpos */
1264 complain_overflow_dont,/* complain_on_overflow */
1265 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1266 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1267 FALSE, /* partial_inplace */
1268 0xffffffff, /* src_mask */
1269 0xffffffff, /* dst_mask */
1270 TRUE), /* pcrel_offset */
1271
1272 /* End of group relocations. */
c19d1205 1273
c19d1205
ZW		 1274 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1275 0, /* rightshift */
1276 2, /* size (0 = byte, 1 = short, 2 = long) */
1277 16, /* bitsize */
1278 FALSE, /* pc_relative */
1279 0, /* bitpos */
1280 complain_overflow_dont,/* complain_on_overflow */
1281 bfd_elf_generic_reloc, /* special_function */
1282 "R_ARM_MOVW_BREL_NC", /* name */
1283 FALSE, /* partial_inplace */
1284 0x0000ffff, /* src_mask */
1285 0x0000ffff, /* dst_mask */
1286 FALSE), /* pcrel_offset */
1287
1288 HOWTO (R_ARM_MOVT_BREL, /* type */
1289 0, /* rightshift */
1290 2, /* size (0 = byte, 1 = short, 2 = long) */
1291 16, /* bitsize */
1292 FALSE, /* pc_relative */
1293 0, /* bitpos */
1294 complain_overflow_bitfield,/* complain_on_overflow */
1295 bfd_elf_generic_reloc, /* special_function */
1296 "R_ARM_MOVT_BREL", /* name */
1297 FALSE, /* partial_inplace */
1298 0x0000ffff, /* src_mask */
1299 0x0000ffff, /* dst_mask */
1300 FALSE), /* pcrel_offset */
1301
1302 HOWTO (R_ARM_MOVW_BREL, /* type */
1303 0, /* rightshift */
1304 2, /* size (0 = byte, 1 = short, 2 = long) */
1305 16, /* bitsize */
1306 FALSE, /* pc_relative */
1307 0, /* bitpos */
1308 complain_overflow_dont,/* complain_on_overflow */
1309 bfd_elf_generic_reloc, /* special_function */
1310 "R_ARM_MOVW_BREL", /* name */
1311 FALSE, /* partial_inplace */
1312 0x0000ffff, /* src_mask */
1313 0x0000ffff, /* dst_mask */
1314 FALSE), /* pcrel_offset */
1315
1316 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1317 0, /* rightshift */
1318 2, /* size (0 = byte, 1 = short, 2 = long) */
1319 16, /* bitsize */
1320 FALSE, /* pc_relative */
1321 0, /* bitpos */
1322 complain_overflow_dont,/* complain_on_overflow */
1323 bfd_elf_generic_reloc, /* special_function */
1324 "R_ARM_THM_MOVW_BREL_NC",/* name */
1325 FALSE, /* partial_inplace */
1326 0x040f70ff, /* src_mask */
1327 0x040f70ff, /* dst_mask */
1328 FALSE), /* pcrel_offset */
1329
1330 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1331 0, /* rightshift */
1332 2, /* size (0 = byte, 1 = short, 2 = long) */
1333 16, /* bitsize */
1334 FALSE, /* pc_relative */
1335 0, /* bitpos */
1336 complain_overflow_bitfield,/* complain_on_overflow */
1337 bfd_elf_generic_reloc, /* special_function */
1338 "R_ARM_THM_MOVT_BREL", /* name */
1339 FALSE, /* partial_inplace */
1340 0x040f70ff, /* src_mask */
1341 0x040f70ff, /* dst_mask */
1342 FALSE), /* pcrel_offset */
1343
1344 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1345 0, /* rightshift */
1346 2, /* size (0 = byte, 1 = short, 2 = long) */
1347 16, /* bitsize */
1348 FALSE, /* pc_relative */
1349 0, /* bitpos */
1350 complain_overflow_dont,/* complain_on_overflow */
1351 bfd_elf_generic_reloc, /* special_function */
1352 "R_ARM_THM_MOVW_BREL", /* name */
1353 FALSE, /* partial_inplace */
1354 0x040f70ff, /* src_mask */
1355 0x040f70ff, /* dst_mask */
1356 FALSE), /* pcrel_offset */
1357
0855e32b
NS		 1358 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1359 0, /* rightshift */
1360 2, /* size (0 = byte, 1 = short, 2 = long) */
1361 32, /* bitsize */
1362 FALSE, /* pc_relative */
1363 0, /* bitpos */
1364 complain_overflow_bitfield,/* complain_on_overflow */
1365 NULL, /* special_function */
1366 "R_ARM_TLS_GOTDESC", /* name */
1367 TRUE, /* partial_inplace */
1368 0xffffffff, /* src_mask */
1369 0xffffffff, /* dst_mask */
1370 FALSE), /* pcrel_offset */
1371
1372 HOWTO (R_ARM_TLS_CALL, /* type */
1373 0, /* rightshift */
1374 2, /* size (0 = byte, 1 = short, 2 = long) */
1375 24, /* bitsize */
1376 FALSE, /* pc_relative */
1377 0, /* bitpos */
1378 complain_overflow_dont,/* complain_on_overflow */
1379 bfd_elf_generic_reloc, /* special_function */
1380 "R_ARM_TLS_CALL", /* name */
1381 FALSE, /* partial_inplace */
1382 0x00ffffff, /* src_mask */
1383 0x00ffffff, /* dst_mask */
1384 FALSE), /* pcrel_offset */
1385
1386 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1387 0, /* rightshift */
1388 2, /* size (0 = byte, 1 = short, 2 = long) */
1389 0, /* bitsize */
1390 FALSE, /* pc_relative */
1391 0, /* bitpos */
1392 complain_overflow_bitfield,/* complain_on_overflow */
1393 bfd_elf_generic_reloc, /* special_function */
1394 "R_ARM_TLS_DESCSEQ", /* name */
1395 FALSE, /* partial_inplace */
1396 0x00000000, /* src_mask */
1397 0x00000000, /* dst_mask */
1398 FALSE), /* pcrel_offset */
1399
1400 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1401 0, /* rightshift */
1402 2, /* size (0 = byte, 1 = short, 2 = long) */
1403 24, /* bitsize */
1404 FALSE, /* pc_relative */
1405 0, /* bitpos */
1406 complain_overflow_dont,/* complain_on_overflow */
1407 bfd_elf_generic_reloc, /* special_function */
1408 "R_ARM_THM_TLS_CALL", /* name */
1409 FALSE, /* partial_inplace */
1410 0x07ff07ff, /* src_mask */
1411 0x07ff07ff, /* dst_mask */
1412 FALSE), /* pcrel_offset */
c19d1205
ZW		 1413
1414 HOWTO (R_ARM_PLT32_ABS, /* type */
1415 0, /* rightshift */
1416 2, /* size (0 = byte, 1 = short, 2 = long) */
1417 32, /* bitsize */
1418 FALSE, /* pc_relative */
1419 0, /* bitpos */
1420 complain_overflow_dont,/* complain_on_overflow */
1421 bfd_elf_generic_reloc, /* special_function */
1422 "R_ARM_PLT32_ABS", /* name */
1423 FALSE, /* partial_inplace */
1424 0xffffffff, /* src_mask */
1425 0xffffffff, /* dst_mask */
1426 FALSE), /* pcrel_offset */
1427
1428 HOWTO (R_ARM_GOT_ABS, /* type */
1429 0, /* rightshift */
1430 2, /* size (0 = byte, 1 = short, 2 = long) */
1431 32, /* bitsize */
1432 FALSE, /* pc_relative */
1433 0, /* bitpos */
1434 complain_overflow_dont,/* complain_on_overflow */
1435 bfd_elf_generic_reloc, /* special_function */
1436 "R_ARM_GOT_ABS", /* name */
1437 FALSE, /* partial_inplace */
1438 0xffffffff, /* src_mask */
1439 0xffffffff, /* dst_mask */
1440 FALSE), /* pcrel_offset */
1441
1442 HOWTO (R_ARM_GOT_PREL, /* type */
1443 0, /* rightshift */
1444 2, /* size (0 = byte, 1 = short, 2 = long) */
1445 32, /* bitsize */
1446 TRUE, /* pc_relative */
1447 0, /* bitpos */
1448 complain_overflow_dont, /* complain_on_overflow */
1449 bfd_elf_generic_reloc, /* special_function */
1450 "R_ARM_GOT_PREL", /* name */
1451 FALSE, /* partial_inplace */
1452 0xffffffff, /* src_mask */
1453 0xffffffff, /* dst_mask */
1454 TRUE), /* pcrel_offset */
1455
1456 HOWTO (R_ARM_GOT_BREL12, /* type */
1457 0, /* rightshift */
1458 2, /* size (0 = byte, 1 = short, 2 = long) */
1459 12, /* bitsize */
1460 FALSE, /* pc_relative */
1461 0, /* bitpos */
1462 complain_overflow_bitfield,/* complain_on_overflow */
1463 bfd_elf_generic_reloc, /* special_function */
1464 "R_ARM_GOT_BREL12", /* name */
1465 FALSE, /* partial_inplace */
1466 0x00000fff, /* src_mask */
1467 0x00000fff, /* dst_mask */
1468 FALSE), /* pcrel_offset */
1469
1470 HOWTO (R_ARM_GOTOFF12, /* type */
1471 0, /* rightshift */
1472 2, /* size (0 = byte, 1 = short, 2 = long) */
1473 12, /* bitsize */
1474 FALSE, /* pc_relative */
1475 0, /* bitpos */
1476 complain_overflow_bitfield,/* complain_on_overflow */
1477 bfd_elf_generic_reloc, /* special_function */
1478 "R_ARM_GOTOFF12", /* name */
1479 FALSE, /* partial_inplace */
1480 0x00000fff, /* src_mask */
1481 0x00000fff, /* dst_mask */
1482 FALSE), /* pcrel_offset */
1483
07d6d2b8 1484 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1485
1486 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1487 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1488 0, /* rightshift */
1489 2, /* size (0 = byte, 1 = short, 2 = long) */
1490 0, /* bitsize */
1491 FALSE, /* pc_relative */
1492 0, /* bitpos */
99059e56 1493 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1494 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1495 "R_ARM_GNU_VTENTRY", /* name */
1496 FALSE, /* partial_inplace */
1497 0, /* src_mask */
1498 0, /* dst_mask */
1499 FALSE), /* pcrel_offset */
c19d1205
ZW		 1500
1501 /* GNU extension to record C++ vtable hierarchy */
1502 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1503 0, /* rightshift */
1504 2, /* size (0 = byte, 1 = short, 2 = long) */
1505 0, /* bitsize */
1506 FALSE, /* pc_relative */
1507 0, /* bitpos */
99059e56 1508 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1509 NULL, /* special_function */
99059e56 1510 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1511 FALSE, /* partial_inplace */
1512 0, /* src_mask */
1513 0, /* dst_mask */
1514 FALSE), /* pcrel_offset */
c19d1205
ZW		 1515
1516 HOWTO (R_ARM_THM_JUMP11, /* type */
1517 1, /* rightshift */
1518 1, /* size (0 = byte, 1 = short, 2 = long) */
1519 11, /* bitsize */
1520 TRUE, /* pc_relative */
1521 0, /* bitpos */
1522 complain_overflow_signed, /* complain_on_overflow */
1523 bfd_elf_generic_reloc, /* special_function */
1524 "R_ARM_THM_JUMP11", /* name */
1525 FALSE, /* partial_inplace */
1526 0x000007ff, /* src_mask */
1527 0x000007ff, /* dst_mask */
1528 TRUE), /* pcrel_offset */
1529
1530 HOWTO (R_ARM_THM_JUMP8, /* type */
1531 1, /* rightshift */
1532 1, /* size (0 = byte, 1 = short, 2 = long) */
1533 8, /* bitsize */
1534 TRUE, /* pc_relative */
1535 0, /* bitpos */
1536 complain_overflow_signed, /* complain_on_overflow */
1537 bfd_elf_generic_reloc, /* special_function */
1538 "R_ARM_THM_JUMP8", /* name */
1539 FALSE, /* partial_inplace */
1540 0x000000ff, /* src_mask */
1541 0x000000ff, /* dst_mask */
1542 TRUE), /* pcrel_offset */
ba93b8ac 1543
c19d1205
ZW		 1544 /* TLS relocations */
1545 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1546 0, /* rightshift */
1547 2, /* size (0 = byte, 1 = short, 2 = long) */
1548 32, /* bitsize */
1549 FALSE, /* pc_relative */
1550 0, /* bitpos */
99059e56
RM		 1551 complain_overflow_bitfield,/* complain_on_overflow */
1552 NULL, /* special_function */
1553 "R_ARM_TLS_GD32", /* name */
1554 TRUE, /* partial_inplace */
1555 0xffffffff, /* src_mask */
1556 0xffffffff, /* dst_mask */
07d6d2b8 1557 FALSE), /* pcrel_offset */
ba93b8ac 1558
ba93b8ac 1559 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1560 0, /* rightshift */
1561 2, /* size (0 = byte, 1 = short, 2 = long) */
1562 32, /* bitsize */
1563 FALSE, /* pc_relative */
1564 0, /* bitpos */
99059e56
RM		 1565 complain_overflow_bitfield,/* complain_on_overflow */
1566 bfd_elf_generic_reloc, /* special_function */
1567 "R_ARM_TLS_LDM32", /* name */
1568 TRUE, /* partial_inplace */
1569 0xffffffff, /* src_mask */
1570 0xffffffff, /* dst_mask */
07d6d2b8 1571 FALSE), /* pcrel_offset */
ba93b8ac 1572
c19d1205 1573 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1574 0, /* rightshift */
1575 2, /* size (0 = byte, 1 = short, 2 = long) */
1576 32, /* bitsize */
1577 FALSE, /* pc_relative */
1578 0, /* bitpos */
99059e56
RM		 1579 complain_overflow_bitfield,/* complain_on_overflow */
1580 bfd_elf_generic_reloc, /* special_function */
1581 "R_ARM_TLS_LDO32", /* name */
1582 TRUE, /* partial_inplace */
1583 0xffffffff, /* src_mask */
1584 0xffffffff, /* dst_mask */
07d6d2b8 1585 FALSE), /* pcrel_offset */
ba93b8ac 1586
ba93b8ac 1587 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1588 0, /* rightshift */
1589 2, /* size (0 = byte, 1 = short, 2 = long) */
1590 32, /* bitsize */
1591 FALSE, /* pc_relative */
1592 0, /* bitpos */
99059e56
RM		 1593 complain_overflow_bitfield,/* complain_on_overflow */
1594 NULL, /* special_function */
1595 "R_ARM_TLS_IE32", /* name */
1596 TRUE, /* partial_inplace */
1597 0xffffffff, /* src_mask */
1598 0xffffffff, /* dst_mask */
07d6d2b8 1599 FALSE), /* pcrel_offset */
7f266840 1600
c19d1205 1601 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1602 0, /* rightshift */
1603 2, /* size (0 = byte, 1 = short, 2 = long) */
1604 32, /* bitsize */
1605 FALSE, /* pc_relative */
1606 0, /* bitpos */
99059e56 1607 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1608 NULL, /* special_function */
99059e56
RM		 1609 "R_ARM_TLS_LE32", /* name */
1610 TRUE, /* partial_inplace */
1611 0xffffffff, /* src_mask */
1612 0xffffffff, /* dst_mask */
07d6d2b8 1613 FALSE), /* pcrel_offset */
7f266840 1614
c19d1205
ZW		 1615 HOWTO (R_ARM_TLS_LDO12, /* type */
1616 0, /* rightshift */
1617 2, /* size (0 = byte, 1 = short, 2 = long) */
1618 12, /* bitsize */
1619 FALSE, /* pc_relative */
7f266840 1620 0, /* bitpos */
c19d1205 1621 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1622 bfd_elf_generic_reloc, /* special_function */
c19d1205 1623 "R_ARM_TLS_LDO12", /* name */
7f266840 1624 FALSE, /* partial_inplace */
c19d1205
ZW		 1625 0x00000fff, /* src_mask */
1626 0x00000fff, /* dst_mask */
1627 FALSE), /* pcrel_offset */
7f266840 1628
c19d1205
ZW		 1629 HOWTO (R_ARM_TLS_LE12, /* type */
1630 0, /* rightshift */
1631 2, /* size (0 = byte, 1 = short, 2 = long) */
1632 12, /* bitsize */
1633 FALSE, /* pc_relative */
7f266840 1634 0, /* bitpos */
c19d1205 1635 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1636 bfd_elf_generic_reloc, /* special_function */
c19d1205 1637 "R_ARM_TLS_LE12", /* name */
7f266840 1638 FALSE, /* partial_inplace */
c19d1205
ZW		 1639 0x00000fff, /* src_mask */
1640 0x00000fff, /* dst_mask */
1641 FALSE), /* pcrel_offset */
7f266840 1642
c19d1205 1643 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1644 0, /* rightshift */
1645 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1646 12, /* bitsize */
1647 FALSE, /* pc_relative */
7f266840 1648 0, /* bitpos */
c19d1205 1649 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1650 bfd_elf_generic_reloc, /* special_function */
c19d1205 1651 "R_ARM_TLS_IE12GP", /* name */
7f266840 1652 FALSE, /* partial_inplace */
c19d1205
ZW		 1653 0x00000fff, /* src_mask */
1654 0x00000fff, /* dst_mask */
1655 FALSE), /* pcrel_offset */
0855e32b 1656
34e77a92 1657 /* 112-127 private relocations. */
0855e32b
NS		 1658 EMPTY_HOWTO (112),
1659 EMPTY_HOWTO (113),
1660 EMPTY_HOWTO (114),
1661 EMPTY_HOWTO (115),
1662 EMPTY_HOWTO (116),
1663 EMPTY_HOWTO (117),
1664 EMPTY_HOWTO (118),
1665 EMPTY_HOWTO (119),
1666 EMPTY_HOWTO (120),
1667 EMPTY_HOWTO (121),
1668 EMPTY_HOWTO (122),
1669 EMPTY_HOWTO (123),
1670 EMPTY_HOWTO (124),
1671 EMPTY_HOWTO (125),
1672 EMPTY_HOWTO (126),
1673 EMPTY_HOWTO (127),
34e77a92
RS		 1674
1675 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1676 EMPTY_HOWTO (128),
1677
1678 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1679 0, /* rightshift */
1680 1, /* size (0 = byte, 1 = short, 2 = long) */
1681 0, /* bitsize */
1682 FALSE, /* pc_relative */
1683 0, /* bitpos */
1684 complain_overflow_bitfield,/* complain_on_overflow */
1685 bfd_elf_generic_reloc, /* special_function */
1686 "R_ARM_THM_TLS_DESCSEQ",/* name */
1687 FALSE, /* partial_inplace */
1688 0x00000000, /* src_mask */
1689 0x00000000, /* dst_mask */
1690 FALSE), /* pcrel_offset */
72d98d16
MG		 1691 EMPTY_HOWTO (130),
1692 EMPTY_HOWTO (131),
1693 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1694 0, /* rightshift. */
1695 1, /* size (0 = byte, 1 = short, 2 = long). */
1696 16, /* bitsize. */
1697 FALSE, /* pc_relative. */
1698 0, /* bitpos. */
1699 complain_overflow_bitfield,/* complain_on_overflow. */
1700 bfd_elf_generic_reloc, /* special_function. */
1701 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1702 FALSE, /* partial_inplace. */
1703 0x00000000, /* src_mask. */
1704 0x00000000, /* dst_mask. */
1705 FALSE), /* pcrel_offset. */
1706 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1707 0, /* rightshift. */
1708 1, /* size (0 = byte, 1 = short, 2 = long). */
1709 16, /* bitsize. */
1710 FALSE, /* pc_relative. */
1711 0, /* bitpos. */
1712 complain_overflow_bitfield,/* complain_on_overflow. */
1713 bfd_elf_generic_reloc, /* special_function. */
1714 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1715 FALSE, /* partial_inplace. */
1716 0x00000000, /* src_mask. */
1717 0x00000000, /* dst_mask. */
1718 FALSE), /* pcrel_offset. */
1719 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1720 0, /* rightshift. */
1721 1, /* size (0 = byte, 1 = short, 2 = long). */
1722 16, /* bitsize. */
1723 FALSE, /* pc_relative. */
1724 0, /* bitpos. */
1725 complain_overflow_bitfield,/* complain_on_overflow. */
1726 bfd_elf_generic_reloc, /* special_function. */
1727 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1728 FALSE, /* partial_inplace. */
1729 0x00000000, /* src_mask. */
1730 0x00000000, /* dst_mask. */
1731 FALSE), /* pcrel_offset. */
1732 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1733 0, /* rightshift. */
1734 1, /* size (0 = byte, 1 = short, 2 = long). */
1735 16, /* bitsize. */
1736 FALSE, /* pc_relative. */
1737 0, /* bitpos. */
1738 complain_overflow_bitfield,/* complain_on_overflow. */
1739 bfd_elf_generic_reloc, /* special_function. */
1740 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1741 FALSE, /* partial_inplace. */
1742 0x00000000, /* src_mask. */
1743 0x00000000, /* dst_mask. */
1744 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1745 /* Relocations for Armv8.1-M Mainline. */
1746 HOWTO (R_ARM_THM_BF16, /* type. */
1747 0, /* rightshift. */
1748 1, /* size (0 = byte, 1 = short, 2 = long). */
1749 16, /* bitsize. */
1750 TRUE, /* pc_relative. */
1751 0, /* bitpos. */
1752 complain_overflow_dont,/* do not complain_on_overflow. */
1753 bfd_elf_generic_reloc, /* special_function. */
1754 "R_ARM_THM_BF16", /* name. */
1755 FALSE, /* partial_inplace. */
1756 0x001f0ffe, /* src_mask. */
1757 0x001f0ffe, /* dst_mask. */
1758 TRUE), /* pcrel_offset. */
1889da70
AV		 1759 HOWTO (R_ARM_THM_BF12, /* type. */
1760 0, /* rightshift. */
1761 1, /* size (0 = byte, 1 = short, 2 = long). */
1762 12, /* bitsize. */
1763 TRUE, /* pc_relative. */
1764 0, /* bitpos. */
1765 complain_overflow_dont,/* do not complain_on_overflow. */
1766 bfd_elf_generic_reloc, /* special_function. */
1767 "R_ARM_THM_BF12", /* name. */
1768 FALSE, /* partial_inplace. */
1769 0x00010ffe, /* src_mask. */
1770 0x00010ffe, /* dst_mask. */
1771 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1772 HOWTO (R_ARM_THM_BF18, /* type. */
1773 0, /* rightshift. */
1774 1, /* size (0 = byte, 1 = short, 2 = long). */
1775 18, /* bitsize. */
1776 TRUE, /* pc_relative. */
1777 0, /* bitpos. */
1778 complain_overflow_dont,/* do not complain_on_overflow. */
1779 bfd_elf_generic_reloc, /* special_function. */
1780 "R_ARM_THM_BF18", /* name. */
1781 FALSE, /* partial_inplace. */
1782 0x007f0ffe, /* src_mask. */
1783 0x007f0ffe, /* dst_mask. */
1784 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1785};
1786
34e77a92 1787/* 160 onwards: */
5c5a4843 1788static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1789{
1790 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1791 0, /* rightshift */
1792 2, /* size (0 = byte, 1 = short, 2 = long) */
1793 32, /* bitsize */
1794 FALSE, /* pc_relative */
1795 0, /* bitpos */
99059e56
RM		 1796 complain_overflow_bitfield,/* complain_on_overflow */
1797 bfd_elf_generic_reloc, /* special_function */
1798 "R_ARM_IRELATIVE", /* name */
1799 TRUE, /* partial_inplace */
1800 0xffffffff, /* src_mask */
1801 0xffffffff, /* dst_mask */
188fd7ae
CL		 1802 FALSE), /* pcrel_offset */
1803 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1804 0, /* rightshift */
1805 2, /* size (0 = byte, 1 = short, 2 = long) */
1806 32, /* bitsize */
1807 FALSE, /* pc_relative */
1808 0, /* bitpos */
1809 complain_overflow_bitfield,/* complain_on_overflow */
1810 bfd_elf_generic_reloc, /* special_function */
1811 "R_ARM_GOTFUNCDESC", /* name */
1812 FALSE, /* partial_inplace */
1813 0, /* src_mask */
1814 0xffffffff, /* dst_mask */
1815 FALSE), /* pcrel_offset */
1816 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1817 0, /* rightshift */
1818 2, /* size (0 = byte, 1 = short, 2 = long) */
1819 32, /* bitsize */
1820 FALSE, /* pc_relative */
1821 0, /* bitpos */
1822 complain_overflow_bitfield,/* complain_on_overflow */
1823 bfd_elf_generic_reloc, /* special_function */
1824 "R_ARM_GOTOFFFUNCDESC",/* name */
1825 FALSE, /* partial_inplace */
1826 0, /* src_mask */
1827 0xffffffff, /* dst_mask */
1828 FALSE), /* pcrel_offset */
1829 HOWTO (R_ARM_FUNCDESC, /* type */
1830 0, /* rightshift */
1831 2, /* size (0 = byte, 1 = short, 2 = long) */
1832 32, /* bitsize */
1833 FALSE, /* pc_relative */
1834 0, /* bitpos */
1835 complain_overflow_bitfield,/* complain_on_overflow */
1836 bfd_elf_generic_reloc, /* special_function */
1837 "R_ARM_FUNCDESC", /* name */
1838 FALSE, /* partial_inplace */
1839 0, /* src_mask */
1840 0xffffffff, /* dst_mask */
1841 FALSE), /* pcrel_offset */
1842 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1843 0, /* rightshift */
1844 2, /* size (0 = byte, 1 = short, 2 = long) */
1845 64, /* bitsize */
1846 FALSE, /* pc_relative */
1847 0, /* bitpos */
1848 complain_overflow_bitfield,/* complain_on_overflow */
1849 bfd_elf_generic_reloc, /* special_function */
1850 "R_ARM_FUNCDESC_VALUE",/* name */
1851 FALSE, /* partial_inplace */
1852 0, /* src_mask */
1853 0xffffffff, /* dst_mask */
1854 FALSE), /* pcrel_offset */
5c5a4843
CL		 1855 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1856 0, /* rightshift */
1857 2, /* size (0 = byte, 1 = short, 2 = long) */
1858 32, /* bitsize */
1859 FALSE, /* pc_relative */
1860 0, /* bitpos */
1861 complain_overflow_bitfield,/* complain_on_overflow */
1862 bfd_elf_generic_reloc, /* special_function */
1863 "R_ARM_TLS_GD32_FDPIC",/* name */
1864 FALSE, /* partial_inplace */
1865 0, /* src_mask */
1866 0xffffffff, /* dst_mask */
1867 FALSE), /* pcrel_offset */
1868 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1869 0, /* rightshift */
1870 2, /* size (0 = byte, 1 = short, 2 = long) */
1871 32, /* bitsize */
1872 FALSE, /* pc_relative */
1873 0, /* bitpos */
1874 complain_overflow_bitfield,/* complain_on_overflow */
1875 bfd_elf_generic_reloc, /* special_function */
1876 "R_ARM_TLS_LDM32_FDPIC",/* name */
1877 FALSE, /* partial_inplace */
1878 0, /* src_mask */
1879 0xffffffff, /* dst_mask */
1880 FALSE), /* pcrel_offset */
1881 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1882 0, /* rightshift */
1883 2, /* size (0 = byte, 1 = short, 2 = long) */
1884 32, /* bitsize */
1885 FALSE, /* pc_relative */
1886 0, /* bitpos */
1887 complain_overflow_bitfield,/* complain_on_overflow */
1888 bfd_elf_generic_reloc, /* special_function */
1889 "R_ARM_TLS_IE32_FDPIC",/* name */
1890 FALSE, /* partial_inplace */
1891 0, /* src_mask */
1892 0xffffffff, /* dst_mask */
1893 FALSE), /* pcrel_offset */
34e77a92 1894};
c19d1205 1895
34e77a92
RS		 1896/* 249-255 extended, currently unused, relocations: */
1897static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1898{
1899 HOWTO (R_ARM_RREL32, /* type */
1900 0, /* rightshift */
1901 0, /* size (0 = byte, 1 = short, 2 = long) */
1902 0, /* bitsize */
1903 FALSE, /* pc_relative */
1904 0, /* bitpos */
1905 complain_overflow_dont,/* complain_on_overflow */
1906 bfd_elf_generic_reloc, /* special_function */
1907 "R_ARM_RREL32", /* name */
1908 FALSE, /* partial_inplace */
1909 0, /* src_mask */
1910 0, /* dst_mask */
1911 FALSE), /* pcrel_offset */
1912
1913 HOWTO (R_ARM_RABS32, /* type */
1914 0, /* rightshift */
1915 0, /* size (0 = byte, 1 = short, 2 = long) */
1916 0, /* bitsize */
1917 FALSE, /* pc_relative */
1918 0, /* bitpos */
1919 complain_overflow_dont,/* complain_on_overflow */
1920 bfd_elf_generic_reloc, /* special_function */
1921 "R_ARM_RABS32", /* name */
1922 FALSE, /* partial_inplace */
1923 0, /* src_mask */
1924 0, /* dst_mask */
1925 FALSE), /* pcrel_offset */
1926
1927 HOWTO (R_ARM_RPC24, /* type */
1928 0, /* rightshift */
1929 0, /* size (0 = byte, 1 = short, 2 = long) */
1930 0, /* bitsize */
1931 FALSE, /* pc_relative */
1932 0, /* bitpos */
1933 complain_overflow_dont,/* complain_on_overflow */
1934 bfd_elf_generic_reloc, /* special_function */
1935 "R_ARM_RPC24", /* name */
1936 FALSE, /* partial_inplace */
1937 0, /* src_mask */
1938 0, /* dst_mask */
1939 FALSE), /* pcrel_offset */
1940
1941 HOWTO (R_ARM_RBASE, /* type */
1942 0, /* rightshift */
1943 0, /* size (0 = byte, 1 = short, 2 = long) */
1944 0, /* bitsize */
1945 FALSE, /* pc_relative */
1946 0, /* bitpos */
1947 complain_overflow_dont,/* complain_on_overflow */
1948 bfd_elf_generic_reloc, /* special_function */
1949 "R_ARM_RBASE", /* name */
1950 FALSE, /* partial_inplace */
1951 0, /* src_mask */
1952 0, /* dst_mask */
1953 FALSE) /* pcrel_offset */
1954};
1955
1956static reloc_howto_type *
1957elf32_arm_howto_from_type (unsigned int r_type)
1958{
906e58ca 1959 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1960 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1961
188fd7ae
CL		 1962 if (r_type >= R_ARM_IRELATIVE
1963 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1964 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1965
c19d1205 1966 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1967 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1968 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1969
c19d1205 1970 return NULL;
7f266840
DJ		 1971}
1972
f3185997
NC		 1973static bfd_boolean
1974elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1975 Elf_Internal_Rela * elf_reloc)
1976{
1977 unsigned int r_type;
1978
1979 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1980 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1981 {
1982 /* xgettext:c-format */
1983 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1984 abfd, r_type);
1985 bfd_set_error (bfd_error_bad_value);
1986 return FALSE;
1987 }
1988 return TRUE;
7f266840
DJ		 1989}
1990
1991struct elf32_arm_reloc_map
1992 {
1993 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1994 unsigned char elf_reloc_val;
7f266840
DJ		 1995 };
1996
1997/* All entries in this list must also be present in elf32_arm_howto_table. */
1998static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1999 {
07d6d2b8 2000 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2001 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2002 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2003 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2004 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2005 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2006 {BFD_RELOC_32, R_ARM_ABS32},
2007 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2008 {BFD_RELOC_8, R_ARM_ABS8},
2009 {BFD_RELOC_16, R_ARM_ABS16},
2010 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2011 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2012 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2013 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2014 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2018 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2019 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2020 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2021 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2022 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2023 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2024 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2025 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2026 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2027 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2028 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2029 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2030 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2031 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2032 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2033 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2034 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2035 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2038 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2039 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2040 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2041 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2042 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2043 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2044 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2045 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2046 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2047 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2048 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2049 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2050 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2051 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2052 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2053 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2054 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2055 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2056 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2057 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2058 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2059 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2060 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2061 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2062 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2064 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2065 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2066 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2068 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2069 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2070 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2071 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2072 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2073 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2074 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2075 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2076 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2077 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2078 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2079 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2080 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2082 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2083 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2084 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2085 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2086 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2087 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2088 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2089 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2090 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2091 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2092 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2093 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2094 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2097 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2098 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2100 };
2101
2102static reloc_howto_type *
f1c71a59
ZW		 2103elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2104 bfd_reloc_code_real_type code)
7f266840
DJ		 2105{
2106 unsigned int i;
8029a119 2107
906e58ca 2108 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2109 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2110 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2111
c19d1205 2112 return NULL;
7f266840
DJ		 2113}
2114
157090f7
AM		 2115static reloc_howto_type *
2116elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2117 const char *r_name)
2118{
2119 unsigned int i;
2120
906e58ca 2121 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2122 if (elf32_arm_howto_table_1[i].name != NULL
2123 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2124 return &elf32_arm_howto_table_1[i];
2125
906e58ca 2126 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2127 if (elf32_arm_howto_table_2[i].name != NULL
2128 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2129 return &elf32_arm_howto_table_2[i];
2130
34e77a92
RS		 2131 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2132 if (elf32_arm_howto_table_3[i].name != NULL
2133 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2134 return &elf32_arm_howto_table_3[i];
2135
157090f7
AM		 2136 return NULL;
2137}
2138
906e58ca
NC		 2139/* Support for core dump NOTE sections. */
2140
7f266840 2141static bfd_boolean
f1c71a59 2142elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2143{
2144 int offset;
2145 size_t size;
2146
2147 switch (note->descsz)
2148 {
2149 default:
2150 return FALSE;
2151
8029a119 2152 case 148: /* Linux/ARM 32-bit. */
7f266840 2153 /* pr_cursig */
228e534f 2154 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2155
2156 /* pr_pid */
228e534f 2157 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2158
2159 /* pr_reg */
2160 offset = 72;
2161 size = 72;
2162
2163 break;
2164 }
2165
2166 /* Make a ".reg/999" section. */
2167 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2168 size, note->descpos + offset);
2169}
2170
2171static bfd_boolean
f1c71a59 2172elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2173{
2174 switch (note->descsz)
2175 {
2176 default:
2177 return FALSE;
2178
8029a119 2179 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2180 elf_tdata (abfd)->core->pid
4395ee08 2181 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2182 elf_tdata (abfd)->core->program
7f266840 2183 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2184 elf_tdata (abfd)->core->command
7f266840
DJ		 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2186 }
2187
2188 /* Note that for some reason, a spurious space is tacked
2189 onto the end of the args in some (at least one anyway)
2190 implementations, so strip it off if it exists. */
7f266840 2191 {
228e534f 2192 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2193 int n = strlen (command);
2194
2195 if (0 < n && command[n - 1] == ' ')
2196 command[n - 1] = '\0';
2197 }
2198
2199 return TRUE;
2200}
2201
1f20dca5
UW		 2202static char *
2203elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2204 int note_type, ...)
2205{
2206 switch (note_type)
2207 {
2208 default:
2209 return NULL;
2210
2211 case NT_PRPSINFO:
2212 {
602f1657 2213 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2214 va_list ap;
2215
2216 va_start (ap, note_type);
2217 memset (data, 0, sizeof (data));
2218 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2219#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2220 DIAGNOSTIC_PUSH;
be3e27bb 2221 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2222 -Wstringop-truncation:
2223 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2224 */
95da9854
L		 2225 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2226#endif
1f20dca5 2227 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2228#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2229 DIAGNOSTIC_POP;
fe75810f 2230#endif
1f20dca5
UW		 2231 va_end (ap);
2232
2233 return elfcore_write_note (abfd, buf, bufsiz,
2234 "CORE", note_type, data, sizeof (data));
2235 }
2236
2237 case NT_PRSTATUS:
2238 {
2239 char data[148];
2240 va_list ap;
2241 long pid;
2242 int cursig;
2243 const void *greg;
2244
2245 va_start (ap, note_type);
2246 memset (data, 0, sizeof (data));
2247 pid = va_arg (ap, long);
2248 bfd_put_32 (abfd, pid, data + 24);
2249 cursig = va_arg (ap, int);
2250 bfd_put_16 (abfd, cursig, data + 12);
2251 greg = va_arg (ap, const void *);
2252 memcpy (data + 72, greg, 72);
2253 va_end (ap);
2254
2255 return elfcore_write_note (abfd, buf, bufsiz,
2256 "CORE", note_type, data, sizeof (data));
2257 }
2258 }
2259}
2260
07d6d2b8
AM		 2261#define TARGET_LITTLE_SYM arm_elf32_le_vec
2262#define TARGET_LITTLE_NAME "elf32-littlearm"
2263#define TARGET_BIG_SYM arm_elf32_be_vec
2264#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2265
2266#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2267#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2268#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2269
252b5132
RH		 2270typedef unsigned long int insn32;
2271typedef unsigned short int insn16;
2272
3a4a14e9
PB		 2273/* In lieu of proper flags, assume all EABIv4 or later objects are
2274 interworkable. */
57e8b36a 2275#define INTERWORK_FLAG(abfd) \
3a4a14e9 2276 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2277 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2278 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2279
252b5132
RH		 2280/* The linker script knows the section names for placement.
2281 The entry_names are used to do simple name mangling on the stubs.
2282 Given a function name, and its type, the stub can be found. The
9b485d32 2283 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2284#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2285#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2286
2287#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2288#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2289
c7b8f16e
JB		 2290#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2291#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2292
a504d23a
LA		 2293#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2294#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2295
845b51d6
PB		 2296#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2297#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2298
7413f23f
DJ		 2299#define STUB_ENTRY_NAME "__%s_veneer"
2300
4ba2ef8f
TP		 2301#define CMSE_PREFIX "__acle_se_"
2302
252b5132
RH		 2303/* The name of the dynamic interpreter. This is put in the .interp
2304 section. */
2305#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2306
cb10292c
CL		 2307/* FDPIC default stack size. */
2308#define DEFAULT_STACK_SIZE 0x8000
2309
0855e32b 2310static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2311{
2312 0xe08e0000, /* add r0, lr, r0 */
2313 0xe5901004, /* ldr r1, [r0,#4] */
2314 0xe12fff11, /* bx r1 */
2315};
0855e32b
NS		 2316
2317static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2318{
2319 0xe52d2004, /* push {r2} */
2320 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2321 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2322 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2323 0xe081100f, /* 2: add r1, pc */
2324 0xe12fff12, /* bx r2 */
2325 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2326 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2327 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2328};
0855e32b 2329
7801f98f
CL		 2330/* ARM FDPIC PLT entry. */
2331/* The last 5 words contain PLT lazy fragment code and data. */
2332static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2333 {
2334 0xe59fc008, /* ldr r12, .L1 */
2335 0xe08cc009, /* add r12, r12, r9 */
2336 0xe59c9004, /* ldr r9, [r12, #4] */
2337 0xe59cf000, /* ldr pc, [r12] */
2338 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2339 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2340 0xe51fc00c, /* ldr r12, [pc, #-12] */
2341 0xe92d1000, /* push {r12} */
2342 0xe599c004, /* ldr r12, [r9, #4] */
2343 0xe599f000, /* ldr pc, [r9] */
2344 };
2345
59029f57
CL		 2346/* Thumb FDPIC PLT entry. */
2347/* The last 5 words contain PLT lazy fragment code and data. */
2348static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2349 {
2350 0xc00cf8df, /* ldr.w r12, .L1 */
2351 0x0c09eb0c, /* add.w r12, r12, r9 */
2352 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2353 0xf000f8dc, /* ldr.w pc, [r12] */
2354 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2355 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2356 0xc008f85f, /* ldr.w r12, .L2 */
2357 0xcd04f84d, /* push {r12} */
2358 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2359 0xf000f8d9, /* ldr.w pc, [r9] */
2360 };
2361
5e681ec4
PB		 2362#ifdef FOUR_WORD_PLT
2363
252b5132
RH		 2364/* The first entry in a procedure linkage table looks like
2365 this. It is set up so that any shared library function that is
59f2c4e7 2366 called before the relocation has been set up calls the dynamic
9b485d32 2367 linker first. */
e5a52504 2368static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2369{
2370 0xe52de004, /* str lr, [sp, #-4]! */
2371 0xe59fe010, /* ldr lr, [pc, #16] */
2372 0xe08fe00e, /* add lr, pc, lr */
2373 0xe5bef008, /* ldr pc, [lr, #8]! */
2374};
5e681ec4
PB		 2375
2376/* Subsequent entries in a procedure linkage table look like
2377 this. */
e5a52504 2378static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2379{
2380 0xe28fc600, /* add ip, pc, #NN */
2381 0xe28cca00, /* add ip, ip, #NN */
2382 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2383 0x00000000, /* unused */
2384};
5e681ec4 2385
eed94f8f 2386#else /* not FOUR_WORD_PLT */
5e681ec4 2387
5e681ec4
PB		 2388/* The first entry in a procedure linkage table looks like
2389 this. It is set up so that any shared library function that is
2390 called before the relocation has been set up calls the dynamic
2391 linker first. */
e5a52504 2392static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2393{
07d6d2b8
AM		 2394 0xe52de004, /* str lr, [sp, #-4]! */
2395 0xe59fe004, /* ldr lr, [pc, #4] */
2396 0xe08fe00e, /* add lr, pc, lr */
2397 0xe5bef008, /* ldr pc, [lr, #8]! */
2398 0x00000000, /* &GOT[0] - . */
b38cadfb 2399};
252b5132 2400
1db37fe6
YG		 2401/* By default subsequent entries in a procedure linkage table look like
2402 this. Offsets that don't fit into 28 bits will cause link error. */
2403static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2404{
2405 0xe28fc600, /* add ip, pc, #0xNN00000 */
2406 0xe28cca00, /* add ip, ip, #0xNN000 */
2407 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2408};
5e681ec4 2409
1db37fe6
YG		 2410/* When explicitly asked, we'll use this "long" entry format
2411 which can cope with arbitrary displacements. */
2412static const bfd_vma elf32_arm_plt_entry_long [] =
2413{
07d6d2b8
AM		 2414 0xe28fc200, /* add ip, pc, #0xN0000000 */
2415 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2416 0xe28cca00, /* add ip, ip, #0xNN000 */
2417 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2418};
2419
2420static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2421
eed94f8f
NC		 2422#endif /* not FOUR_WORD_PLT */
2423
2424/* The first entry in a procedure linkage table looks like this.
2425 It is set up so that any shared library function that is called before the
2426 relocation has been set up calls the dynamic linker first. */
2427static const bfd_vma elf32_thumb2_plt0_entry [] =
2428{
2429 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2430 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2431 0xf8dfb500, /* push {lr} */
2432 0x44fee008, /* ldr.w lr, [pc, #8] */
2433 /* add lr, pc */
eed94f8f 2434 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2435 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2436};
2437
2438/* Subsequent entries in a procedure linkage table for thumb only target
2439 look like this. */
2440static const bfd_vma elf32_thumb2_plt_entry [] =
2441{
2442 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2443 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2444 0x0c00f240, /* movw ip, #0xNNNN */
2445 0x0c00f2c0, /* movt ip, #0xNNNN */
2446 0xf8dc44fc, /* add ip, pc */
2447 0xbf00f000 /* ldr.w pc, [ip] */
2448 /* nop */
eed94f8f 2449};
252b5132 2450
00a97672
RS		 2451/* The format of the first entry in the procedure linkage table
2452 for a VxWorks executable. */
2453static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2454{
07d6d2b8
AM		 2455 0xe52dc008, /* str ip,[sp,#-8]! */
2456 0xe59fc000, /* ldr ip,[pc] */
2457 0xe59cf008, /* ldr pc,[ip,#8] */
2458 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2459};
00a97672
RS		 2460
2461/* The format of subsequent entries in a VxWorks executable. */
2462static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2463{
07d6d2b8
AM		 2464 0xe59fc000, /* ldr ip,[pc] */
2465 0xe59cf000, /* ldr pc,[ip] */
2466 0x00000000, /* .long @got */
2467 0xe59fc000, /* ldr ip,[pc] */
2468 0xea000000, /* b _PLT */
2469 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2470};
00a97672
RS		 2471
2472/* The format of entries in a VxWorks shared library. */
2473static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2474{
07d6d2b8
AM		 2475 0xe59fc000, /* ldr ip,[pc] */
2476 0xe79cf009, /* ldr pc,[ip,r9] */
2477 0x00000000, /* .long @got */
2478 0xe59fc000, /* ldr ip,[pc] */
2479 0xe599f008, /* ldr pc,[r9,#8] */
2480 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2481};
00a97672 2482
b7693d02
DJ		 2483/* An initial stub used if the PLT entry is referenced from Thumb code. */
2484#define PLT_THUMB_STUB_SIZE 4
2485static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2486{
2487 0x4778, /* bx pc */
2488 0x46c0 /* nop */
2489};
b7693d02 2490
e5a52504
MM		 2491/* The entries in a PLT when using a DLL-based target with multiple
2492 address spaces. */
906e58ca 2493static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2494{
07d6d2b8
AM		 2495 0xe51ff004, /* ldr pc, [pc, #-4] */
2496 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2497};
2498
2499/* The first entry in a procedure linkage table looks like
2500 this. It is set up so that any shared library function that is
2501 called before the relocation has been set up calls the dynamic
2502 linker first. */
2503static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2504{
2505 /* First bundle: */
2506 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2507 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2508 0xe08cc00f, /* add ip, ip, pc */
2509 0xe52dc008, /* str ip, [sp, #-8]! */
2510 /* Second bundle: */
edccdf7c
RM		 2511 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2512 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2513 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2514 0xe12fff1c, /* bx ip */
b38cadfb 2515 /* Third bundle: */
edccdf7c
RM		 2516 0xe320f000, /* nop */
2517 0xe320f000, /* nop */
2518 0xe320f000, /* nop */
b38cadfb
NC		 2519 /* .Lplt_tail: */
2520 0xe50dc004, /* str ip, [sp, #-4] */
2521 /* Fourth bundle: */
edccdf7c
RM		 2522 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2523 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2524 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2525 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2526};
2527#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2528
2529/* Subsequent entries in a procedure linkage table look like this. */
2530static const bfd_vma elf32_arm_nacl_plt_entry [] =
2531{
2532 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2533 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2534 0xe08cc00f, /* add ip, ip, pc */
2535 0xea000000, /* b .Lplt_tail */
2536};
e5a52504 2537
906e58ca
NC		 2538#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2539#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2540#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2541#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2542#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2543#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2544#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2545#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2546
461a49ca 2547enum stub_insn_type
b38cadfb
NC		 2548{
2549 THUMB16_TYPE = 1,
2550 THUMB32_TYPE,
2551 ARM_TYPE,
2552 DATA_TYPE
2553};
461a49ca 2554
48229727
JB		 2555#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2556/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2557 is inserted in arm_build_one_stub(). */
2558#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2559#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2560#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2561#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2562#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2563#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2564#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2565#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2566
2567typedef struct
2568{
07d6d2b8 2569 bfd_vma data;
b38cadfb 2570 enum stub_insn_type type;
07d6d2b8
AM		 2571 unsigned int r_type;
2572 int reloc_addend;
461a49ca
DJ		 2573} insn_sequence;
2574
fea2b4d6
CL		 2575/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2576 to reach the stub if necessary. */
461a49ca 2577static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2578{
07d6d2b8 2579 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2580 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2581};
906e58ca 2582
fea2b4d6
CL		 2583/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2584 available. */
461a49ca 2585static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2586{
07d6d2b8
AM		 2587 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2588 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2589 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2590};
906e58ca 2591
d3626fb0 2592/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2593static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2594{
07d6d2b8
AM		 2595 THUMB16_INSN (0xb401), /* push {r0} */
2596 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2597 THUMB16_INSN (0x4684), /* mov ip, r0 */
2598 THUMB16_INSN (0xbc01), /* pop {r0} */
2599 THUMB16_INSN (0x4760), /* bx ip */
2600 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2601 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2602};
906e58ca 2603
80c135e5
TP		 2604/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2605static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2606{
07d6d2b8 2607 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2608 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2609};
2610
d5a67c02
AV		 2611/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2612 M-profile architectures. */
2613static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2614{
2615 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2616 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2617 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2618};
2619
d3626fb0
CL		 2620/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2621 allowed. */
2622static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2623{
07d6d2b8
AM		 2624 THUMB16_INSN (0x4778), /* bx pc */
2625 THUMB16_INSN (0x46c0), /* nop */
2626 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2627 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2628 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2629};
d3626fb0 2630
fea2b4d6
CL		 2631/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2632 available. */
461a49ca 2633static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2634{
07d6d2b8
AM		 2635 THUMB16_INSN (0x4778), /* bx pc */
2636 THUMB16_INSN (0x46c0), /* nop */
2637 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2638 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2639};
906e58ca 2640
fea2b4d6
CL		 2641/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2642 one, when the destination is close enough. */
461a49ca 2643static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2644{
07d6d2b8
AM		 2645 THUMB16_INSN (0x4778), /* bx pc */
2646 THUMB16_INSN (0x46c0), /* nop */
b38cadfb
NC		 2647 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2648};
c820be07 2649
cf3eccff 2650/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2651 blx to reach the stub if necessary. */
cf3eccff 2652static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2653{
07d6d2b8
AM		 2654 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2655 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2656 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2657};
906e58ca 2658
cf3eccff
DJ		 2659/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2660 blx to reach the stub if necessary. We can not add into pc;
2661 it is not guaranteed to mode switch (different in ARMv6 and
2662 ARMv7). */
2663static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2666 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2667 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2668 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2669};
cf3eccff 2670
ebe24dd4
CL		 2671/* V4T ARM -> ARM long branch stub, PIC. */
2672static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2673{
07d6d2b8
AM		 2674 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2675 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2676 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2677 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2678};
ebe24dd4
CL		 2679
2680/* V4T Thumb -> ARM long branch stub, PIC. */
2681static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2682{
07d6d2b8
AM		 2683 THUMB16_INSN (0x4778), /* bx pc */
2684 THUMB16_INSN (0x46c0), /* nop */
2685 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2686 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2687 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2688};
ebe24dd4 2689
d3626fb0
CL		 2690/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2691 architectures. */
ebe24dd4 2692static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2693{
07d6d2b8
AM		 2694 THUMB16_INSN (0xb401), /* push {r0} */
2695 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2696 THUMB16_INSN (0x46fc), /* mov ip, pc */
2697 THUMB16_INSN (0x4484), /* add ip, r0 */
2698 THUMB16_INSN (0xbc01), /* pop {r0} */
2699 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2700 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2701};
ebe24dd4 2702
d3626fb0
CL		 2703/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2704 allowed. */
2705static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2706{
07d6d2b8
AM		 2707 THUMB16_INSN (0x4778), /* bx pc */
2708 THUMB16_INSN (0x46c0), /* nop */
2709 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2710 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2711 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2712 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2713};
d3626fb0 2714
0855e32b
NS		 2715/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2716 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2717static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2718{
07d6d2b8
AM		 2719 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2720 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2721 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2722};
2723
2724/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2725 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2726static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2727{
07d6d2b8
AM		 2728 THUMB16_INSN (0x4778), /* bx pc */
2729 THUMB16_INSN (0x46c0), /* nop */
2730 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2731 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2732 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2733};
2734
7a89b94e
NC		 2735/* NaCl ARM -> ARM long branch stub. */
2736static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2737{
2738 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2739 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2740 ARM_INSN (0xe12fff1c), /* bx ip */
2741 ARM_INSN (0xe320f000), /* nop */
2742 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2743 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2744 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2745 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2746};
2747
2748/* NaCl ARM -> ARM long branch stub, PIC. */
2749static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2750{
2751 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2752 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2753 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2754 ARM_INSN (0xe12fff1c), /* bx ip */
2755 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2756 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2757 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2758 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2759};
2760
4ba2ef8f
TP		 2761/* Stub used for transition to secure state (aka SG veneer). */
2762static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2763{
2764 THUMB32_INSN (0xe97fe97f), /* sg. */
2765 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2766};
2767
7a89b94e 2768
48229727
JB		 2769/* Cortex-A8 erratum-workaround stubs. */
2770
2771/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2772 can't use a conditional branch to reach this stub). */
2773
2774static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2775{
07d6d2b8 2776 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2777 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2778 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2779};
48229727
JB		 2780
2781/* Stub used for b.w and bl.w instructions. */
2782
2783static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2784{
2785 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2786};
48229727
JB		 2787
2788static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2789{
2790 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2791};
48229727
JB		 2792
2793/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2794 instruction (which switches to ARM mode) to point to this stub. Jump to the
2795 real destination using an ARM-mode branch. */
2796
2797static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2798{
2799 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2800};
48229727 2801
9553db3c
NC		 2802/* For each section group there can be a specially created linker section
2803 to hold the stubs for that group. The name of the stub section is based
2804 upon the name of another section within that group with the suffix below
2805 applied.
2806
2807 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2808 create what appeared to be a linker stub section when it actually
2809 contained user code/data. For example, consider this fragment:
b38cadfb 2810
9553db3c
NC		 2811 const char * stubborn_problems[] = { "np" };
2812
2813 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2814 section called:
2815
2816 .data.rel.local.stubborn_problems
2817
2818 This then causes problems in arm32_arm_build_stubs() as it triggers:
2819
2820 // Ignore non-stub sections.
2821 if (!strstr (stub_sec->name, STUB_SUFFIX))
2822 continue;
2823
2824 And so the section would be ignored instead of being processed. Hence
2825 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2826 C identifier. */
2827#define STUB_SUFFIX ".__stub"
906e58ca 2828
738a79f6
CL		 2829/* One entry per long/short branch stub defined above. */
2830#define DEF_STUBS \
2831 DEF_STUB(long_branch_any_any) \
2832 DEF_STUB(long_branch_v4t_arm_thumb) \
2833 DEF_STUB(long_branch_thumb_only) \
2834 DEF_STUB(long_branch_v4t_thumb_thumb) \
2835 DEF_STUB(long_branch_v4t_thumb_arm) \
2836 DEF_STUB(short_branch_v4t_thumb_arm) \
2837 DEF_STUB(long_branch_any_arm_pic) \
2838 DEF_STUB(long_branch_any_thumb_pic) \
2839 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2840 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2841 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2842 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2843 DEF_STUB(long_branch_any_tls_pic) \
2844 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2845 DEF_STUB(long_branch_arm_nacl) \
2846 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2847 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2848 DEF_STUB(a8_veneer_b_cond) \
2849 DEF_STUB(a8_veneer_b) \
2850 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2851 DEF_STUB(a8_veneer_blx) \
2852 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2853 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2854
2855#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2856enum elf32_arm_stub_type
2857{
906e58ca 2858 arm_stub_none,
738a79f6 2859 DEF_STUBS
4f4faa4d 2860 max_stub_type
738a79f6
CL		 2861};
2862#undef DEF_STUB
2863
8d9d9490
TP		 2864/* Note the first a8_veneer type. */
2865const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2866
738a79f6
CL		 2867typedef struct
2868{
d3ce72d0 2869 const insn_sequence* template_sequence;
738a79f6
CL		 2870 int template_size;
2871} stub_def;
2872
2873#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2874static const stub_def stub_definitions[] =
2875{
738a79f6
CL		 2876 {NULL, 0},
2877 DEF_STUBS
906e58ca
NC		 2878};
2879
2880struct elf32_arm_stub_hash_entry
2881{
2882 /* Base hash table entry structure. */
2883 struct bfd_hash_entry root;
2884
2885 /* The stub section. */
2886 asection *stub_sec;
2887
2888 /* Offset within stub_sec of the beginning of this stub. */
2889 bfd_vma stub_offset;
2890
2891 /* Given the symbol's value and its section we can determine its final
2892 value when building the stubs (so the stub knows where to jump). */
2893 bfd_vma target_value;
2894 asection *target_section;
2895
8d9d9490
TP		 2896 /* Same as above but for the source of the branch to the stub. Used for
2897 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2898 such, source section does not need to be recorded since Cortex-A8 erratum
2899 workaround stubs are only generated when both source and target are in the
2900 same section. */
2901 bfd_vma source_value;
48229727
JB		 2902
2903 /* The instruction which caused this stub to be generated (only valid for
2904 Cortex-A8 erratum workaround stubs at present). */
2905 unsigned long orig_insn;
2906
461a49ca 2907 /* The stub type. */
906e58ca 2908 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2909 /* Its encoding size in bytes. */
2910 int stub_size;
2911 /* Its template. */
2912 const insn_sequence *stub_template;
2913 /* The size of the template (number of entries). */
2914 int stub_template_size;
906e58ca
NC		 2915
2916 /* The symbol table entry, if any, that this was derived from. */
2917 struct elf32_arm_link_hash_entry *h;
2918
35fc36a8
RS		 2919 /* Type of branch. */
2920 enum arm_st_branch_type branch_type;
906e58ca
NC		 2921
2922 /* Where this stub is being called from, or, in the case of combined
2923 stub sections, the first input section in the group. */
2924 asection *id_sec;
7413f23f
DJ		 2925
2926 /* The name for the local symbol at the start of this stub. The
2927 stub name in the hash table has to be unique; this does not, so
2928 it can be friendlier. */
2929 char *output_name;
906e58ca
NC		 2930};
2931
e489d0ae
PB		 2932/* Used to build a map of a section. This is required for mixed-endian
2933 code/data. */
2934
2935typedef struct elf32_elf_section_map
2936{
2937 bfd_vma vma;
2938 char type;
2939}
2940elf32_arm_section_map;
2941
c7b8f16e
JB		 2942/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2943
2944typedef enum
2945{
2946 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2947 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2948 VFP11_ERRATUM_ARM_VENEER,
2949 VFP11_ERRATUM_THUMB_VENEER
2950}
2951elf32_vfp11_erratum_type;
2952
2953typedef struct elf32_vfp11_erratum_list
2954{
2955 struct elf32_vfp11_erratum_list *next;
2956 bfd_vma vma;
2957 union
2958 {
2959 struct
2960 {
2961 struct elf32_vfp11_erratum_list *veneer;
2962 unsigned int vfp_insn;
2963 } b;
2964 struct
2965 {
2966 struct elf32_vfp11_erratum_list *branch;
2967 unsigned int id;
2968 } v;
2969 } u;
2970 elf32_vfp11_erratum_type type;
2971}
2972elf32_vfp11_erratum_list;
2973
a504d23a
LA		 2974/* Information about a STM32L4XX erratum veneer, or a branch to such a
2975 veneer. */
2976typedef enum
2977{
2978 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2979 STM32L4XX_ERRATUM_VENEER
2980}
2981elf32_stm32l4xx_erratum_type;
2982
2983typedef struct elf32_stm32l4xx_erratum_list
2984{
2985 struct elf32_stm32l4xx_erratum_list *next;
2986 bfd_vma vma;
2987 union
2988 {
2989 struct
2990 {
2991 struct elf32_stm32l4xx_erratum_list *veneer;
2992 unsigned int insn;
2993 } b;
2994 struct
2995 {
2996 struct elf32_stm32l4xx_erratum_list *branch;
2997 unsigned int id;
2998 } v;
2999 } u;
3000 elf32_stm32l4xx_erratum_type type;
3001}
3002elf32_stm32l4xx_erratum_list;
3003
2468f9c9
PB		 3004typedef enum
3005{
3006 DELETE_EXIDX_ENTRY,
3007 INSERT_EXIDX_CANTUNWIND_AT_END
3008}
3009arm_unwind_edit_type;
3010
3011/* A (sorted) list of edits to apply to an unwind table. */
3012typedef struct arm_unwind_table_edit
3013{
3014 arm_unwind_edit_type type;
3015 /* Note: we sometimes want to insert an unwind entry corresponding to a
3016 section different from the one we're currently writing out, so record the
3017 (text) section this edit relates to here. */
3018 asection *linked_section;
3019 unsigned int index;
3020 struct arm_unwind_table_edit *next;
3021}
3022arm_unwind_table_edit;
3023
8e3de13a 3024typedef struct _arm_elf_section_data
e489d0ae 3025{
2468f9c9 3026 /* Information about mapping symbols. */
e489d0ae 3027 struct bfd_elf_section_data elf;
8e3de13a 3028 unsigned int mapcount;
c7b8f16e 3029 unsigned int mapsize;
e489d0ae 3030 elf32_arm_section_map *map;
2468f9c9 3031 /* Information about CPU errata. */
c7b8f16e
JB		 3032 unsigned int erratumcount;
3033 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3034 unsigned int stm32l4xx_erratumcount;
3035 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3036 unsigned int additional_reloc_count;
2468f9c9
PB		 3037 /* Information about unwind tables. */
3038 union
3039 {
3040 /* Unwind info attached to a text section. */
3041 struct
3042 {
3043 asection *arm_exidx_sec;
3044 } text;
3045
3046 /* Unwind info attached to an .ARM.exidx section. */
3047 struct
3048 {
3049 arm_unwind_table_edit *unwind_edit_list;
3050 arm_unwind_table_edit *unwind_edit_tail;
3051 } exidx;
3052 } u;
8e3de13a
NC		 3053}
3054_arm_elf_section_data;
e489d0ae
PB		 3055
3056#define elf32_arm_section_data(sec) \
8e3de13a 3057 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3058
48229727
JB		 3059/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3060 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3061 so may be created multiple times: we use an array of these entries whilst
3062 relaxing which we can refresh easily, then create stubs for each potentially
3063 erratum-triggering instruction once we've settled on a solution. */
3064
b38cadfb
NC		 3065struct a8_erratum_fix
3066{
48229727
JB		 3067 bfd *input_bfd;
3068 asection *section;
3069 bfd_vma offset;
8d9d9490 3070 bfd_vma target_offset;
48229727
JB		 3071 unsigned long orig_insn;
3072 char *stub_name;
3073 enum elf32_arm_stub_type stub_type;
35fc36a8 3074 enum arm_st_branch_type branch_type;
48229727
JB		 3075};
3076
3077/* A table of relocs applied to branches which might trigger Cortex-A8
3078 erratum. */
3079
b38cadfb
NC		 3080struct a8_erratum_reloc
3081{
48229727
JB		 3082 bfd_vma from;
3083 bfd_vma destination;
92750f34
DJ		 3084 struct elf32_arm_link_hash_entry *hash;
3085 const char *sym_name;
48229727 3086 unsigned int r_type;
35fc36a8 3087 enum arm_st_branch_type branch_type;
48229727
JB		 3088 bfd_boolean non_a8_stub;
3089};
3090
ba93b8ac
DJ		 3091/* The size of the thread control block. */
3092#define TCB_SIZE 8
3093
34e77a92
RS		 3094/* ARM-specific information about a PLT entry, over and above the usual
3095 gotplt_union. */
b38cadfb
NC		 3096struct arm_plt_info
3097{
34e77a92
RS		 3098 /* We reference count Thumb references to a PLT entry separately,
3099 so that we can emit the Thumb trampoline only if needed. */
3100 bfd_signed_vma thumb_refcount;
3101
3102 /* Some references from Thumb code may be eliminated by BL->BLX
3103 conversion, so record them separately. */
3104 bfd_signed_vma maybe_thumb_refcount;
3105
3106 /* How many of the recorded PLT accesses were from non-call relocations.
3107 This information is useful when deciding whether anything takes the
3108 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3109 non-call references to the function should resolve directly to the
3110 real runtime target. */
3111 unsigned int noncall_refcount;
3112
3113 /* Since PLT entries have variable size if the Thumb prologue is
3114 used, we need to record the index into .got.plt instead of
3115 recomputing it from the PLT offset. */
3116 bfd_signed_vma got_offset;
3117};
3118
3119/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3120struct arm_local_iplt_info
3121{
34e77a92
RS		 3122 /* The information that is usually found in the generic ELF part of
3123 the hash table entry. */
3124 union gotplt_union root;
3125
3126 /* The information that is usually found in the ARM-specific part of
3127 the hash table entry. */
3128 struct arm_plt_info arm;
3129
3130 /* A list of all potential dynamic relocations against this symbol. */
3131 struct elf_dyn_relocs *dyn_relocs;
3132};
3133
e8b09b87
CL		 3134/* Structure to handle FDPIC support for local functions. */
3135struct fdpic_local {
3136 unsigned int funcdesc_cnt;
3137 unsigned int gotofffuncdesc_cnt;
3138 int funcdesc_offset;
3139};
3140
0ffa91dd 3141struct elf_arm_obj_tdata
ba93b8ac
DJ		 3142{
3143 struct elf_obj_tdata root;
3144
3145 /* tls_type for each local got entry. */
3146 char *local_got_tls_type;
ee065d83 3147
0855e32b
NS		 3148 /* GOTPLT entries for TLS descriptors. */
3149 bfd_vma *local_tlsdesc_gotent;
3150
34e77a92
RS		 3151 /* Information for local symbols that need entries in .iplt. */
3152 struct arm_local_iplt_info **local_iplt;
3153
bf21ed78
MS		 3154 /* Zero to warn when linking objects with incompatible enum sizes. */
3155 int no_enum_size_warning;
a9dc9481
JM		 3156
3157 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3158 int no_wchar_size_warning;
e8b09b87
CL		 3159
3160 /* Maintains FDPIC counters and funcdesc info. */
3161 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3162};
3163
0ffa91dd
NC		 3164#define elf_arm_tdata(bfd) \
3165 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3166
0ffa91dd
NC		 3167#define elf32_arm_local_got_tls_type(bfd) \
3168 (elf_arm_tdata (bfd)->local_got_tls_type)
3169
0855e32b
NS		 3170#define elf32_arm_local_tlsdesc_gotent(bfd) \
3171 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3172
34e77a92
RS		 3173#define elf32_arm_local_iplt(bfd) \
3174 (elf_arm_tdata (bfd)->local_iplt)
3175
e8b09b87
CL		 3176#define elf32_arm_local_fdpic_cnts(bfd) \
3177 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3178
0ffa91dd
NC		 3179#define is_arm_elf(bfd) \
3180 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3181 && elf_tdata (bfd) != NULL \
4dfe6ac6 3182 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3183
3184static bfd_boolean
3185elf32_arm_mkobject (bfd *abfd)
3186{
0ffa91dd 3187 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3188 ARM_ELF_DATA);
ba93b8ac
DJ		 3189}
3190
ba93b8ac
DJ		 3191#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3192
e8b09b87
CL		 3193/* Structure to handle FDPIC support for extern functions. */
3194struct fdpic_global {
3195 unsigned int gotofffuncdesc_cnt;
3196 unsigned int gotfuncdesc_cnt;
3197 unsigned int funcdesc_cnt;
3198 int funcdesc_offset;
3199 int gotfuncdesc_offset;
3200};
3201
ba96a88f 3202/* Arm ELF linker hash entry. */
252b5132 3203struct elf32_arm_link_hash_entry
b38cadfb
NC		 3204{
3205 struct elf_link_hash_entry root;
252b5132 3206
b38cadfb
NC		 3207 /* Track dynamic relocs copied for this symbol. */
3208 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3209
b38cadfb
NC		 3210 /* ARM-specific PLT information. */
3211 struct arm_plt_info plt;
ba93b8ac
DJ		 3212
3213#define GOT_UNKNOWN 0
3214#define GOT_NORMAL 1
3215#define GOT_TLS_GD 2
3216#define GOT_TLS_IE 4
0855e32b
NS		 3217#define GOT_TLS_GDESC 8
3218#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3219 unsigned int tls_type : 8;
34e77a92 3220
b38cadfb
NC		 3221 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3222 unsigned int is_iplt : 1;
34e77a92 3223
b38cadfb 3224 unsigned int unused : 23;
a4fd1a8e 3225
b38cadfb
NC		 3226 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3227 starting at the end of the jump table. */
3228 bfd_vma tlsdesc_got;
0855e32b 3229
b38cadfb
NC		 3230 /* The symbol marking the real symbol location for exported thumb
3231 symbols with Arm stubs. */
3232 struct elf_link_hash_entry *export_glue;
906e58ca 3233
b38cadfb 3234 /* A pointer to the most recently used stub hash entry against this
8029a119 3235 symbol. */
b38cadfb 3236 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3237
3238 /* Counter for FDPIC relocations against this symbol. */
3239 struct fdpic_global fdpic_cnts;
b38cadfb 3240};
252b5132 3241
252b5132 3242/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3243#define elf32_arm_link_hash_traverse(table, func, info) \
3244 (elf_link_hash_traverse \
3245 (&(table)->root, \
b7693d02 3246 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3247 (info)))
3248
3249/* Get the ARM elf linker hash table from a link_info structure. */
3250#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3251 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3252 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3253
906e58ca
NC		 3254#define arm_stub_hash_lookup(table, string, create, copy) \
3255 ((struct elf32_arm_stub_hash_entry *) \
3256 bfd_hash_lookup ((table), (string), (create), (copy)))
3257
21d799b5
NC		 3258/* Array to keep track of which stub sections have been created, and
3259 information on stub grouping. */
3260struct map_stub
3261{
3262 /* This is the section to which stubs in the group will be
3263 attached. */
3264 asection *link_sec;
3265 /* The stub section. */
3266 asection *stub_sec;
3267};
3268
0855e32b
NS		 3269#define elf32_arm_compute_jump_table_size(htab) \
3270 ((htab)->next_tls_desc_index * 4)
3271
9b485d32 3272/* ARM ELF linker hash table. */
252b5132 3273struct elf32_arm_link_hash_table
906e58ca
NC		 3274{
3275 /* The main hash table. */
3276 struct elf_link_hash_table root;
252b5132 3277
906e58ca
NC		 3278 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3279 bfd_size_type thumb_glue_size;
252b5132 3280
906e58ca
NC		 3281 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3282 bfd_size_type arm_glue_size;
252b5132 3283
906e58ca
NC		 3284 /* The size in bytes of section containing the ARMv4 BX veneers. */
3285 bfd_size_type bx_glue_size;
845b51d6 3286
906e58ca
NC		 3287 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3288 veneer has been populated. */
3289 bfd_vma bx_glue_offset[15];
845b51d6 3290
906e58ca
NC		 3291 /* The size in bytes of the section containing glue for VFP11 erratum
3292 veneers. */
3293 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3294
a504d23a
LA		 3295 /* The size in bytes of the section containing glue for STM32L4XX erratum
3296 veneers. */
3297 bfd_size_type stm32l4xx_erratum_glue_size;
3298
48229727
JB		 3299 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3300 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3301 elf32_arm_write_section(). */
3302 struct a8_erratum_fix *a8_erratum_fixes;
3303 unsigned int num_a8_erratum_fixes;
3304
906e58ca
NC		 3305 /* An arbitrary input BFD chosen to hold the glue sections. */
3306 bfd * bfd_of_glue_owner;
ba96a88f 3307
906e58ca
NC		 3308 /* Nonzero to output a BE8 image. */
3309 int byteswap_code;
e489d0ae 3310
906e58ca
NC		 3311 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3312 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3313 int target1_is_rel;
9c504268 3314
906e58ca
NC		 3315 /* The relocation to use for R_ARM_TARGET2 relocations. */
3316 int target2_reloc;
eb043451 3317
906e58ca
NC		 3318 /* 0 = Ignore R_ARM_V4BX.
3319 1 = Convert BX to MOV PC.
3320 2 = Generate v4 interworing stubs. */
3321 int fix_v4bx;
319850b4 3322
48229727
JB		 3323 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3324 int fix_cortex_a8;
3325
2de70689
MGD		 3326 /* Whether we should fix the ARM1176 BLX immediate issue. */
3327 int fix_arm1176;
3328
906e58ca
NC		 3329 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3330 int use_blx;
33bfe774 3331
906e58ca
NC		 3332 /* What sort of code sequences we should look for which may trigger the
3333 VFP11 denorm erratum. */
3334 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3335
906e58ca
NC		 3336 /* Global counter for the number of fixes we have emitted. */
3337 int num_vfp11_fixes;
c7b8f16e 3338
a504d23a
LA		 3339 /* What sort of code sequences we should look for which may trigger the
3340 STM32L4XX erratum. */
3341 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3342
3343 /* Global counter for the number of fixes we have emitted. */
3344 int num_stm32l4xx_fixes;
3345
906e58ca
NC		 3346 /* Nonzero to force PIC branch veneers. */
3347 int pic_veneer;
27e55c4d 3348
906e58ca
NC		 3349 /* The number of bytes in the initial entry in the PLT. */
3350 bfd_size_type plt_header_size;
e5a52504 3351
906e58ca
NC		 3352 /* The number of bytes in the subsequent PLT etries. */
3353 bfd_size_type plt_entry_size;
e5a52504 3354
906e58ca
NC		 3355 /* True if the target system is VxWorks. */
3356 int vxworks_p;
00a97672 3357
906e58ca
NC		 3358 /* True if the target system is Symbian OS. */
3359 int symbian_p;
e5a52504 3360
b38cadfb
NC		 3361 /* True if the target system is Native Client. */
3362 int nacl_p;
3363
906e58ca 3364 /* True if the target uses REL relocations. */
f3185997 3365 bfd_boolean use_rel;
4e7fd91e 3366
54ddd295
TP		 3367 /* Nonzero if import library must be a secure gateway import library
3368 as per ARMv8-M Security Extensions. */
3369 int cmse_implib;
3370
0955507f
TP		 3371 /* The import library whose symbols' address must remain stable in
3372 the import library generated. */
3373 bfd *in_implib_bfd;
3374
0855e32b
NS		 3375 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3376 bfd_vma next_tls_desc_index;
3377
3378 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3379 bfd_vma num_tls_desc;
3380
906e58ca
NC		 3381 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3382 asection *srelplt2;
00a97672 3383
0855e32b
NS		 3384 /* The offset into splt of the PLT entry for the TLS descriptor
3385 resolver. Special values are 0, if not necessary (or not found
3386 to be necessary yet), and -1 if needed but not determined
3387 yet. */
3388 bfd_vma dt_tlsdesc_plt;
3389
3390 /* The offset into sgot of the GOT entry used by the PLT entry
3391 above. */
b38cadfb 3392 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3393
3394 /* Offset in .plt section of tls_arm_trampoline. */
3395 bfd_vma tls_trampoline;
3396
5c5a4843 3397 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3398 union
3399 {
3400 bfd_signed_vma refcount;
3401 bfd_vma offset;
3402 } tls_ldm_got;
b7693d02 3403
87d72d41
AM		 3404 /* Small local sym cache. */
3405 struct sym_cache sym_cache;
906e58ca
NC		 3406
3407 /* For convenience in allocate_dynrelocs. */
3408 bfd * obfd;
3409
0855e32b
NS		 3410 /* The amount of space used by the reserved portion of the sgotplt
3411 section, plus whatever space is used by the jump slots. */
3412 bfd_vma sgotplt_jump_table_size;
3413
906e58ca
NC		 3414 /* The stub hash table. */
3415 struct bfd_hash_table stub_hash_table;
3416
3417 /* Linker stub bfd. */
3418 bfd *stub_bfd;
3419
3420 /* Linker call-backs. */
6bde4c52
TP		 3421 asection * (*add_stub_section) (const char *, asection *, asection *,
3422 unsigned int);
906e58ca
NC		 3423 void (*layout_sections_again) (void);
3424
3425 /* Array to keep track of which stub sections have been created, and
3426 information on stub grouping. */
21d799b5 3427 struct map_stub *stub_group;
906e58ca 3428
4ba2ef8f
TP		 3429 /* Input stub section holding secure gateway veneers. */
3430 asection *cmse_stub_sec;
3431
0955507f
TP		 3432 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3433 start to be allocated. */
3434 bfd_vma new_cmse_stub_offset;
3435
fe33d2fa 3436 /* Number of elements in stub_group. */
7292b3ac 3437 unsigned int top_id;
fe33d2fa 3438
906e58ca
NC		 3439 /* Assorted information used by elf32_arm_size_stubs. */
3440 unsigned int bfd_count;
7292b3ac 3441 unsigned int top_index;
906e58ca 3442 asection **input_list;
617a5ada
CL		 3443
3444 /* True if the target system uses FDPIC. */
3445 int fdpic_p;
e8b09b87
CL		 3446
3447 /* Fixup section. Used for FDPIC. */
3448 asection *srofixup;
906e58ca 3449};
252b5132 3450
e8b09b87
CL		 3451/* Add an FDPIC read-only fixup. */
3452static void
3453arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3454{
3455 bfd_vma fixup_offset;
3456
3457 fixup_offset = srofixup->reloc_count++ * 4;
3458 BFD_ASSERT (fixup_offset < srofixup->size);
3459 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3460}
3461
a504d23a
LA		 3462static inline int
3463ctz (unsigned int mask)
3464{
3465#if GCC_VERSION >= 3004
3466 return __builtin_ctz (mask);
3467#else
3468 unsigned int i;
3469
3470 for (i = 0; i < 8 * sizeof (mask); i++)
3471 {
3472 if (mask & 0x1)
3473 break;
3474 mask = (mask >> 1);
3475 }
3476 return i;
3477#endif
3478}
3479
3480static inline int
b25e998d 3481elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3482{
3483#if GCC_VERSION >= 3004
3484 return __builtin_popcount (mask);
3485#else
b25e998d
CG		 3486 unsigned int i;
3487 int sum = 0;
a504d23a
LA		 3488
3489 for (i = 0; i < 8 * sizeof (mask); i++)
3490 {
3491 if (mask & 0x1)
3492 sum++;
3493 mask = (mask >> 1);
3494 }
3495 return sum;
3496#endif
3497}
3498
e8b09b87
CL		 3499static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3500 asection *sreloc, Elf_Internal_Rela *rel);
3501
3502static void
3503arm_elf_fill_funcdesc(bfd *output_bfd,
3504 struct bfd_link_info *info,
3505 int *funcdesc_offset,
3506 int dynindx,
3507 int offset,
3508 bfd_vma addr,
3509 bfd_vma dynreloc_value,
3510 bfd_vma seg)
3511{
3512 if ((*funcdesc_offset & 1) == 0)
3513 {
3514 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3515 asection *sgot = globals->root.sgot;
3516
3517 if (bfd_link_pic(info))
3518 {
3519 asection *srelgot = globals->root.srelgot;
3520 Elf_Internal_Rela outrel;
3521
3522 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3523 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3524 outrel.r_addend = 0;
3525
3526 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3527 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3528 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3529 }
3530 else
3531 {
3532 struct elf_link_hash_entry *hgot = globals->root.hgot;
3533 bfd_vma got_value = hgot->root.u.def.value
3534 + hgot->root.u.def.section->output_section->vma
3535 + hgot->root.u.def.section->output_offset;
3536
3537 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3538 sgot->output_section->vma + sgot->output_offset
3539 + offset);
3540 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3541 sgot->output_section->vma + sgot->output_offset
3542 + offset + 4);
3543 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3544 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3545 }
3546 *funcdesc_offset |= 1;
3547 }
3548}
3549
780a67af
NC		 3550/* Create an entry in an ARM ELF linker hash table. */
3551
3552static struct bfd_hash_entry *
57e8b36a 3553elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3554 struct bfd_hash_table * table,
3555 const char * string)
780a67af
NC		 3556{
3557 struct elf32_arm_link_hash_entry * ret =
3558 (struct elf32_arm_link_hash_entry *) entry;
3559
3560 /* Allocate the structure if it has not already been allocated by a
3561 subclass. */
906e58ca 3562 if (ret == NULL)
21d799b5 3563 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3564 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3565 if (ret == NULL)
780a67af
NC		 3566 return (struct bfd_hash_entry *) ret;
3567
3568 /* Call the allocation method of the superclass. */
3569 ret = ((struct elf32_arm_link_hash_entry *)
3570 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3571 table, string));
57e8b36a 3572 if (ret != NULL)
b7693d02 3573 {
0bdcacaf 3574 ret->dyn_relocs = NULL;
ba93b8ac 3575 ret->tls_type = GOT_UNKNOWN;
0855e32b 3576 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3577 ret->plt.thumb_refcount = 0;
3578 ret->plt.maybe_thumb_refcount = 0;
3579 ret->plt.noncall_refcount = 0;
3580 ret->plt.got_offset = -1;
3581 ret->is_iplt = FALSE;
a4fd1a8e 3582 ret->export_glue = NULL;
906e58ca
NC		 3583
3584 ret->stub_cache = NULL;
e8b09b87
CL		 3585
3586 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3587 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3588 ret->fdpic_cnts.funcdesc_cnt = 0;
3589 ret->fdpic_cnts.funcdesc_offset = -1;
3590 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3591 }
780a67af
NC		 3592
3593 return (struct bfd_hash_entry *) ret;
3594}
3595
34e77a92
RS		 3596/* Ensure that we have allocated bookkeeping structures for ABFD's local
3597 symbols. */
3598
3599static bfd_boolean
3600elf32_arm_allocate_local_sym_info (bfd *abfd)
3601{
3602 if (elf_local_got_refcounts (abfd) == NULL)
3603 {
3604 bfd_size_type num_syms;
3605 bfd_size_type size;
3606 char *data;
3607
3608 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3609 size = num_syms * (sizeof (bfd_signed_vma)
3610 + sizeof (struct arm_local_iplt_info *)
3611 + sizeof (bfd_vma)
e8b09b87
CL		 3612 + sizeof (char)
3613 + sizeof (struct fdpic_local));
34e77a92
RS		 3614 data = bfd_zalloc (abfd, size);
3615 if (data == NULL)
3616 return FALSE;
3617
e8b09b87
CL		 3618 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3619 data += num_syms * sizeof (struct fdpic_local);
3620
34e77a92
RS		 3621 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3622 data += num_syms * sizeof (bfd_signed_vma);
3623
3624 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3625 data += num_syms * sizeof (struct arm_local_iplt_info *);
3626
3627 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3628 data += num_syms * sizeof (bfd_vma);
3629
3630 elf32_arm_local_got_tls_type (abfd) = data;
3631 }
3632 return TRUE;
3633}
3634
3635/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3636 to input bfd ABFD. Create the information if it doesn't already exist.
3637 Return null if an allocation fails. */
3638
3639static struct arm_local_iplt_info *
3640elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3641{
3642 struct arm_local_iplt_info **ptr;
3643
3644 if (!elf32_arm_allocate_local_sym_info (abfd))
3645 return NULL;
3646
3647 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3648 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3649 if (*ptr == NULL)
3650 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3651 return *ptr;
3652}
3653
3654/* Try to obtain PLT information for the symbol with index R_SYMNDX
3655 in ABFD's symbol table. If the symbol is global, H points to its
3656 hash table entry, otherwise H is null.
3657
3658 Return true if the symbol does have PLT information. When returning
3659 true, point *ROOT_PLT at the target-independent reference count/offset
3660 union and *ARM_PLT at the ARM-specific information. */
3661
3662static bfd_boolean
4ba2ef8f
TP		 3663elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3664 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3665 unsigned long r_symndx, union gotplt_union **root_plt,
3666 struct arm_plt_info **arm_plt)
3667{
3668 struct arm_local_iplt_info *local_iplt;
3669
4ba2ef8f
TP		 3670 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3671 return FALSE;
3672
34e77a92
RS		 3673 if (h != NULL)
3674 {
3675 *root_plt = &h->root.plt;
3676 *arm_plt = &h->plt;
3677 return TRUE;
3678 }
3679
3680 if (elf32_arm_local_iplt (abfd) == NULL)
3681 return FALSE;
3682
3683 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3684 if (local_iplt == NULL)
3685 return FALSE;
3686
3687 *root_plt = &local_iplt->root;
3688 *arm_plt = &local_iplt->arm;
3689 return TRUE;
3690}
3691
59029f57
CL		 3692static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3693
34e77a92
RS		 3694/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3695 before it. */
3696
3697static bfd_boolean
3698elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3699 struct arm_plt_info *arm_plt)
3700{
3701 struct elf32_arm_link_hash_table *htab;
3702
3703 htab = elf32_arm_hash_table (info);
59029f57
CL		 3704
3705 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3706 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3707}
3708
3709/* Return a pointer to the head of the dynamic reloc list that should
3710 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3711 ABFD's symbol table. Return null if an error occurs. */
3712
3713static struct elf_dyn_relocs **
3714elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3715 Elf_Internal_Sym *isym)
3716{
3717 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3718 {
3719 struct arm_local_iplt_info *local_iplt;
3720
3721 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3722 if (local_iplt == NULL)
3723 return NULL;
3724 return &local_iplt->dyn_relocs;
3725 }
3726 else
3727 {
3728 /* Track dynamic relocs needed for local syms too.
3729 We really need local syms available to do this
3730 easily. Oh well. */
3731 asection *s;
3732 void *vpp;
3733
3734 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3735 if (s == NULL)
3736 abort ();
3737
3738 vpp = &elf_section_data (s)->local_dynrel;
3739 return (struct elf_dyn_relocs **) vpp;
3740 }
3741}
3742
906e58ca
NC		 3743/* Initialize an entry in the stub hash table. */
3744
3745static struct bfd_hash_entry *
3746stub_hash_newfunc (struct bfd_hash_entry *entry,
3747 struct bfd_hash_table *table,
3748 const char *string)
3749{
3750 /* Allocate the structure if it has not already been allocated by a
3751 subclass. */
3752 if (entry == NULL)
3753 {
21d799b5 3754 entry = (struct bfd_hash_entry *)
99059e56 3755 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3756 if (entry == NULL)
3757 return entry;
3758 }
3759
3760 /* Call the allocation method of the superclass. */
3761 entry = bfd_hash_newfunc (entry, table, string);
3762 if (entry != NULL)
3763 {
3764 struct elf32_arm_stub_hash_entry *eh;
3765
3766 /* Initialize the local fields. */
3767 eh = (struct elf32_arm_stub_hash_entry *) entry;
3768 eh->stub_sec = NULL;
0955507f 3769 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3770 eh->source_value = 0;
906e58ca
NC		 3771 eh->target_value = 0;
3772 eh->target_section = NULL;
cedfb179 3773 eh->orig_insn = 0;
906e58ca 3774 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3775 eh->stub_size = 0;
3776 eh->stub_template = NULL;
0955507f 3777 eh->stub_template_size = -1;
906e58ca
NC		 3778 eh->h = NULL;
3779 eh->id_sec = NULL;
d8d2f433 3780 eh->output_name = NULL;
906e58ca
NC		 3781 }
3782
3783 return entry;
3784}
3785
00a97672 3786/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3787 shortcuts to them in our hash table. */
3788
3789static bfd_boolean
57e8b36a 3790create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3791{
3792 struct elf32_arm_link_hash_table *htab;
3793
e5a52504 3794 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3795 if (htab == NULL)
3796 return FALSE;
3797
e5a52504
MM		 3798 /* BPABI objects never have a GOT, or associated sections. */
3799 if (htab->symbian_p)
3800 return TRUE;
3801
5e681ec4
PB		 3802 if (! _bfd_elf_create_got_section (dynobj, info))
3803 return FALSE;
3804
e8b09b87
CL		 3805 /* Also create .rofixup. */
3806 if (htab->fdpic_p)
3807 {
3808 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3809 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3810 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
3811 if (htab->srofixup == NULL || ! bfd_set_section_alignment (dynobj, htab->srofixup, 2))
3812 return FALSE;
3813 }
3814
5e681ec4
PB		 3815 return TRUE;
3816}
3817
34e77a92
RS		 3818/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3819
3820static bfd_boolean
3821create_ifunc_sections (struct bfd_link_info *info)
3822{
3823 struct elf32_arm_link_hash_table *htab;
3824 const struct elf_backend_data *bed;
3825 bfd *dynobj;
3826 asection *s;
3827 flagword flags;
b38cadfb 3828
34e77a92
RS		 3829 htab = elf32_arm_hash_table (info);
3830 dynobj = htab->root.dynobj;
3831 bed = get_elf_backend_data (dynobj);
3832 flags = bed->dynamic_sec_flags;
3833
3834 if (htab->root.iplt == NULL)
3835 {
3d4d4302
AM		 3836 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3837 flags | SEC_READONLY | SEC_CODE);
34e77a92 3838 if (s == NULL
a0f49396 3839 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3840 return FALSE;
3841 htab->root.iplt = s;
3842 }
3843
3844 if (htab->root.irelplt == NULL)
3845 {
3d4d4302
AM		 3846 s = bfd_make_section_anyway_with_flags (dynobj,
3847 RELOC_SECTION (htab, ".iplt"),
3848 flags | SEC_READONLY);
34e77a92 3849 if (s == NULL
a0f49396 3850 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3851 return FALSE;
3852 htab->root.irelplt = s;
3853 }
3854
3855 if (htab->root.igotplt == NULL)
3856 {
3d4d4302 3857 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3858 if (s == NULL
3859 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3860 return FALSE;
3861 htab->root.igotplt = s;
3862 }
3863 return TRUE;
3864}
3865
eed94f8f
NC		 3866/* Determine if we're dealing with a Thumb only architecture. */
3867
3868static bfd_boolean
3869using_thumb_only (struct elf32_arm_link_hash_table *globals)
3870{
2fd158eb
TP		 3871 int arch;
3872 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3873 Tag_CPU_arch_profile);
eed94f8f 3874
2fd158eb
TP		 3875 if (profile)
3876 return profile == 'M';
eed94f8f 3877
2fd158eb 3878 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3879
60a019a0 3880 /* Force return logic to be reviewed for each new architecture. */
031254f2 3881 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3882
2fd158eb
TP		 3883 if (arch == TAG_CPU_ARCH_V6_M
3884 || arch == TAG_CPU_ARCH_V6S_M
3885 || arch == TAG_CPU_ARCH_V7E_M
3886 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3887 || arch == TAG_CPU_ARCH_V8M_MAIN
3888 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3889 return TRUE;
eed94f8f 3890
2fd158eb 3891 return FALSE;
eed94f8f
NC		 3892}
3893
3894/* Determine if we're dealing with a Thumb-2 object. */
3895
3896static bfd_boolean
3897using_thumb2 (struct elf32_arm_link_hash_table *globals)
3898{
60a019a0
TP		 3899 int arch;
3900 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3901 Tag_THUMB_ISA_use);
3902
3903 if (thumb_isa)
3904 return thumb_isa == 2;
3905
3906 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3907
3908 /* Force return logic to be reviewed for each new architecture. */
031254f2 3909 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3910
3911 return (arch == TAG_CPU_ARCH_V6T2
3912 || arch == TAG_CPU_ARCH_V7
3913 || arch == TAG_CPU_ARCH_V7E_M
3914 || arch == TAG_CPU_ARCH_V8
bff0500d 3915 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3916 || arch == TAG_CPU_ARCH_V8M_MAIN
3917 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3918}
3919
5e866f5a
TP		 3920/* Determine whether Thumb-2 BL instruction is available. */
3921
3922static bfd_boolean
3923using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3924{
3925 int arch =
3926 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3927
3928 /* Force return logic to be reviewed for each new architecture. */
031254f2 3929 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3930
3931 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3932 return (arch == TAG_CPU_ARCH_V6T2
3933 || arch >= TAG_CPU_ARCH_V7);
3934}
3935
00a97672
RS		 3936/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3937 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3938 hash table. */
3939
3940static bfd_boolean
57e8b36a 3941elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3942{
3943 struct elf32_arm_link_hash_table *htab;
3944
3945 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3946 if (htab == NULL)
3947 return FALSE;
3948
362d30a1 3949 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3950 return FALSE;
3951
3952 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3953 return FALSE;
3954
00a97672
RS		 3955 if (htab->vxworks_p)
3956 {
3957 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3958 return FALSE;
3959
0e1862bb 3960 if (bfd_link_pic (info))
00a97672
RS		 3961 {
3962 htab->plt_header_size = 0;
3963 htab->plt_entry_size
3964 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3965 }
3966 else
3967 {
3968 htab->plt_header_size
3969 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3970 htab->plt_entry_size
3971 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3972 }
aebf9be7
NC		 3973
3974 if (elf_elfheader (dynobj))
3975 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3976 }
eed94f8f
NC		 3977 else
3978 {
3979 /* PR ld/16017
3980 Test for thumb only architectures. Note - we cannot just call
3981 using_thumb_only() as the attributes in the output bfd have not been
3982 initialised at this point, so instead we use the input bfd. */
3983 bfd * saved_obfd = htab->obfd;
3984
3985 htab->obfd = dynobj;
3986 if (using_thumb_only (htab))
3987 {
3988 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3989 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3990 }
3991 htab->obfd = saved_obfd;
3992 }
5e681ec4 3993
7801f98f
CL		 3994 if (htab->fdpic_p) {
3995 htab->plt_header_size = 0;
3996 if (info->flags & DF_BIND_NOW)
3997 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
3998 else
3999 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
4000 }
4001
362d30a1
RS		 4002 if (!htab->root.splt
4003 || !htab->root.srelplt
9d19e4fd
AM		 4004 || !htab->root.sdynbss
4005 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 4006 abort ();
4007
4008 return TRUE;
4009}
4010
906e58ca
NC		 4011/* Copy the extra info we tack onto an elf_link_hash_entry. */
4012
4013static void
4014elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4015 struct elf_link_hash_entry *dir,
4016 struct elf_link_hash_entry *ind)
4017{
4018 struct elf32_arm_link_hash_entry *edir, *eind;
4019
4020 edir = (struct elf32_arm_link_hash_entry *) dir;
4021 eind = (struct elf32_arm_link_hash_entry *) ind;
4022
0bdcacaf 4023 if (eind->dyn_relocs != NULL)
906e58ca 4024 {
0bdcacaf 4025 if (edir->dyn_relocs != NULL)
906e58ca 4026 {
0bdcacaf
RS		 4027 struct elf_dyn_relocs **pp;
4028 struct elf_dyn_relocs *p;
906e58ca
NC		 4029
4030 /* Add reloc counts against the indirect sym to the direct sym
4031 list. Merge any entries against the same section. */
0bdcacaf 4032 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 4033 {
0bdcacaf 4034 struct elf_dyn_relocs *q;
906e58ca 4035
0bdcacaf
RS		 4036 for (q = edir->dyn_relocs; q != NULL; q = q->next)
4037 if (q->sec == p->sec)
906e58ca
NC		 4038 {
4039 q->pc_count += p->pc_count;
4040 q->count += p->count;
4041 *pp = p->next;
4042 break;
4043 }
4044 if (q == NULL)
4045 pp = &p->next;
4046 }
0bdcacaf 4047 *pp = edir->dyn_relocs;
906e58ca
NC		 4048 }
4049
0bdcacaf
RS		 4050 edir->dyn_relocs = eind->dyn_relocs;
4051 eind->dyn_relocs = NULL;
906e58ca
NC		 4052 }
4053
4054 if (ind->root.type == bfd_link_hash_indirect)
4055 {
4056 /* Copy over PLT info. */
34e77a92
RS		 4057 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4058 eind->plt.thumb_refcount = 0;
4059 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4060 eind->plt.maybe_thumb_refcount = 0;
4061 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4062 eind->plt.noncall_refcount = 0;
4063
e8b09b87
CL		 4064 /* Copy FDPIC counters. */
4065 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4066 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4067 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4068
34e77a92
RS		 4069 /* We should only allocate a function to .iplt once the final
4070 symbol information is known. */
4071 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4072
4073 if (dir->got.refcount <= 0)
4074 {
4075 edir->tls_type = eind->tls_type;
4076 eind->tls_type = GOT_UNKNOWN;
4077 }
4078 }
4079
4080 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4081}
4082
68faa637
AM		 4083/* Destroy an ARM elf linker hash table. */
4084
4085static void
d495ab0d 4086elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4087{
4088 struct elf32_arm_link_hash_table *ret
d495ab0d 4089 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4090
4091 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4092 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4093}
4094
906e58ca
NC		 4095/* Create an ARM elf linker hash table. */
4096
4097static struct bfd_link_hash_table *
4098elf32_arm_link_hash_table_create (bfd *abfd)
4099{
4100 struct elf32_arm_link_hash_table *ret;
4101 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4102
7bf52ea2 4103 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4104 if (ret == NULL)
4105 return NULL;
4106
4107 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4108 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4109 sizeof (struct elf32_arm_link_hash_entry),
4110 ARM_ELF_DATA))
906e58ca
NC		 4111 {
4112 free (ret);
4113 return NULL;
4114 }
4115
906e58ca 4116 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4117 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4118#ifdef FOUR_WORD_PLT
4119 ret->plt_header_size = 16;
4120 ret->plt_entry_size = 16;
4121#else
4122 ret->plt_header_size = 20;
1db37fe6 4123 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4124#endif
f3185997 4125 ret->use_rel = TRUE;
906e58ca 4126 ret->obfd = abfd;
617a5ada 4127 ret->fdpic_p = 0;
906e58ca
NC		 4128
4129 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4130 sizeof (struct elf32_arm_stub_hash_entry)))
4131 {
d495ab0d 4132 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4133 return NULL;
4134 }
d495ab0d 4135 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4136
4137 return &ret->root.root;
4138}
4139
cd1dac3d
DG		 4140/* Determine what kind of NOPs are available. */
4141
4142static bfd_boolean
4143arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4144{
4145 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4146 Tag_CPU_arch);
cd1dac3d 4147
60a019a0 4148 /* Force return logic to be reviewed for each new architecture. */
031254f2 4149 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4150
4151 return (arch == TAG_CPU_ARCH_V6T2
4152 || arch == TAG_CPU_ARCH_V6K
4153 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4154 || arch == TAG_CPU_ARCH_V8
4155 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4156}
4157
f4ac8484
DJ		 4158static bfd_boolean
4159arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4160{
4161 switch (stub_type)
4162 {
fea2b4d6 4163 case arm_stub_long_branch_thumb_only:
80c135e5 4164 case arm_stub_long_branch_thumb2_only:
d5a67c02 4165 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4166 case arm_stub_long_branch_v4t_thumb_arm:
4167 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4168 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4169 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4170 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4171 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4172 return TRUE;
4173 case arm_stub_none:
4174 BFD_FAIL ();
4175 return FALSE;
4176 break;
4177 default:
4178 return FALSE;
4179 }
4180}
4181
906e58ca
NC		 4182/* Determine the type of stub needed, if any, for a call. */
4183
4184static enum elf32_arm_stub_type
4185arm_type_of_stub (struct bfd_link_info *info,
4186 asection *input_sec,
4187 const Elf_Internal_Rela *rel,
34e77a92 4188 unsigned char st_type,
35fc36a8 4189 enum arm_st_branch_type *actual_branch_type,
906e58ca 4190 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4191 bfd_vma destination,
4192 asection *sym_sec,
4193 bfd *input_bfd,
4194 const char *name)
906e58ca
NC		 4195{
4196 bfd_vma location;
4197 bfd_signed_vma branch_offset;
4198 unsigned int r_type;
4199 struct elf32_arm_link_hash_table * globals;
5e866f5a 4200 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4201 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4202 int use_plt = 0;
35fc36a8 4203 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4204 union gotplt_union *root_plt;
4205 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4206 int arch;
4207 int thumb2_movw;
906e58ca 4208
35fc36a8 4209 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4210 return stub_type;
4211
906e58ca 4212 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4213 if (globals == NULL)
4214 return stub_type;
906e58ca
NC		 4215
4216 thumb_only = using_thumb_only (globals);
906e58ca 4217 thumb2 = using_thumb2 (globals);
5e866f5a 4218 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4219
d5a67c02
AV		 4220 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4221
4222 /* True for architectures that implement the thumb2 movw instruction. */
4223 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4224
906e58ca
NC		 4225 /* Determine where the call point is. */
4226 location = (input_sec->output_offset
4227 + input_sec->output_section->vma
4228 + rel->r_offset);
4229
906e58ca
NC		 4230 r_type = ELF32_R_TYPE (rel->r_info);
4231
39f21624
NC		 4232 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4233 are considering a function call relocation. */
c5423981 4234 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4235 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4236 && branch_type == ST_BRANCH_TO_ARM)
4237 branch_type = ST_BRANCH_TO_THUMB;
4238
34e77a92
RS		 4239 /* For TLS call relocs, it is the caller's responsibility to provide
4240 the address of the appropriate trampoline. */
4241 if (r_type != R_ARM_TLS_CALL
4242 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4243 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4244 ELF32_R_SYM (rel->r_info), &root_plt,
4245 &arm_plt)
34e77a92 4246 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4247 {
34e77a92 4248 asection *splt;
fe33d2fa 4249
34e77a92
RS		 4250 if (hash == NULL || hash->is_iplt)
4251 splt = globals->root.iplt;
4252 else
4253 splt = globals->root.splt;
4254 if (splt != NULL)
b38cadfb 4255 {
34e77a92
RS		 4256 use_plt = 1;
4257
4258 /* Note when dealing with PLT entries: the main PLT stub is in
4259 ARM mode, so if the branch is in Thumb mode, another
4260 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4261 PLT stub. If a long branch stub is needed, we'll add a
4262 Thumb->Arm one and branch directly to the ARM PLT entry.
4263 Here, we have to check if a pre-PLT Thumb->ARM stub
4264 is needed and if it will be close enough. */
34e77a92
RS		 4265
4266 destination = (splt->output_section->vma
4267 + splt->output_offset
4268 + root_plt->offset);
4269 st_type = STT_FUNC;
2df2751d
CL		 4270
4271 /* Thumb branch/call to PLT: it can become a branch to ARM
4272 or to Thumb. We must perform the same checks and
4273 corrections as in elf32_arm_final_link_relocate. */
4274 if ((r_type == R_ARM_THM_CALL)
4275 || (r_type == R_ARM_THM_JUMP24))
4276 {
4277 if (globals->use_blx
4278 && r_type == R_ARM_THM_CALL
4279 && !thumb_only)
4280 {
4281 /* If the Thumb BLX instruction is available, convert
4282 the BL to a BLX instruction to call the ARM-mode
4283 PLT entry. */
4284 branch_type = ST_BRANCH_TO_ARM;
4285 }
4286 else
4287 {
4288 if (!thumb_only)
4289 /* Target the Thumb stub before the ARM PLT entry. */
4290 destination -= PLT_THUMB_STUB_SIZE;
4291 branch_type = ST_BRANCH_TO_THUMB;
4292 }
4293 }
4294 else
4295 {
4296 branch_type = ST_BRANCH_TO_ARM;
4297 }
34e77a92 4298 }
5fa9e92f 4299 }
34e77a92
RS		 4300 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4301 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4302
fe33d2fa
CL		 4303 branch_offset = (bfd_signed_vma)(destination - location);
4304
0855e32b 4305 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4306 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4307 {
5fa9e92f
CL		 4308 /* Handle cases where:
4309 - this call goes too far (different Thumb/Thumb2 max
99059e56 4310 distance)
155d87d7 4311 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4312 Thumb->Arm branch (not bl). A stub is needed in this case,
4313 but only if this call is not through a PLT entry. Indeed,
695344c0 4314 PLT stubs handle mode switching already. */
5e866f5a 4315 if ((!thumb2_bl
906e58ca
NC		 4316 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4317 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4318 || (thumb2_bl
906e58ca
NC		 4319 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4320 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4321 || (thumb2
4322 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4323 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4324 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4325 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4326 && (((r_type == R_ARM_THM_CALL
4327 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4328 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4329 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4330 && !use_plt))
906e58ca 4331 {
2df2751d
CL		 4332 /* If we need to insert a Thumb-Thumb long branch stub to a
4333 PLT, use one that branches directly to the ARM PLT
4334 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4335 stub, undo this now. */
695344c0
NC		 4336 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4337 {
4338 branch_type = ST_BRANCH_TO_ARM;
4339 branch_offset += PLT_THUMB_STUB_SIZE;
4340 }
2df2751d 4341
35fc36a8 4342 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4343 {
4344 /* Thumb to thumb. */
4345 if (!thumb_only)
4346 {
d5a67c02 4347 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4348 _bfd_error_handler
871b3ab2 4349 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4350 " section with SHF_ARM_PURECODE section"
4351 " attribute is only supported for M-profile"
90b6238f 4352 " targets that implement the movw instruction"),
10463f39 4353 input_bfd, input_sec);
d5a67c02 4354
0e1862bb 4355 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4356 /* PIC stubs. */
155d87d7 4357 ? ((globals->use_blx
9553db3c 4358 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4359 /* V5T and above. Stub starts with ARM code, so
4360 we must be able to switch mode before
4361 reaching it, which is only possible for 'bl'
4362 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4363 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4364 /* On V4T, use Thumb code only. */
d3626fb0 4365 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4366
4367 /* non-PIC stubs. */
155d87d7 4368 : ((globals->use_blx
9553db3c 4369 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4370 /* V5T and above. */
4371 ? arm_stub_long_branch_any_any
4372 /* V4T. */
d3626fb0 4373 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4374 }
4375 else
4376 {
d5a67c02
AV		 4377 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4378 stub_type = arm_stub_long_branch_thumb2_only_pure;
4379 else
4380 {
4381 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4382 _bfd_error_handler
871b3ab2 4383 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4384 " section with SHF_ARM_PURECODE section"
4385 " attribute is only supported for M-profile"
90b6238f 4386 " targets that implement the movw instruction"),
10463f39 4387 input_bfd, input_sec);
d5a67c02
AV		 4388
4389 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4390 /* PIC stub. */
4391 ? arm_stub_long_branch_thumb_only_pic
4392 /* non-PIC stub. */
4393 : (thumb2 ? arm_stub_long_branch_thumb2_only
4394 : arm_stub_long_branch_thumb_only);
4395 }
906e58ca
NC		 4396 }
4397 }
4398 else
4399 {
d5a67c02 4400 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4401 _bfd_error_handler
871b3ab2 4402 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4403 " section with SHF_ARM_PURECODE section"
4404 " attribute is only supported" " for M-profile"
90b6238f 4405 " targets that implement the movw instruction"),
10463f39 4406 input_bfd, input_sec);
d5a67c02 4407
906e58ca 4408 /* Thumb to arm. */
c820be07
NC		 4409 if (sym_sec != NULL
4410 && sym_sec->owner != NULL
4411 && !INTERWORK_FLAG (sym_sec->owner))
4412 {
4eca0228 4413 _bfd_error_handler
90b6238f
AM		 4414 (_("%pB(%s): warning: interworking not enabled;"
4415 " first occurrence: %pB: %s call to %s"),
4416 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4417 }
4418
0855e32b 4419 stub_type =
0e1862bb 4420 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4421 /* PIC stubs. */
0855e32b 4422 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4423 /* TLS PIC stubs. */
0855e32b
NS		 4424 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4425 : arm_stub_long_branch_v4t_thumb_tls_pic)
4426 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4427 /* V5T PIC and above. */
4428 ? arm_stub_long_branch_any_arm_pic
4429 /* V4T PIC stub. */
4430 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4431
4432 /* non-PIC stubs. */
0855e32b 4433 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4434 /* V5T and above. */
4435 ? arm_stub_long_branch_any_any
4436 /* V4T. */
4437 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4438
4439 /* Handle v4t short branches. */
fea2b4d6 4440 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4441 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4442 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4443 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4444 }
4445 }
4446 }
fe33d2fa
CL		 4447 else if (r_type == R_ARM_CALL
4448 || r_type == R_ARM_JUMP24
0855e32b
NS		 4449 || r_type == R_ARM_PLT32
4450 || r_type == R_ARM_TLS_CALL)
906e58ca 4451 {
d5a67c02 4452 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4453 _bfd_error_handler
871b3ab2 4454 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4455 " section with SHF_ARM_PURECODE section"
4456 " attribute is only supported for M-profile"
90b6238f 4457 " targets that implement the movw instruction"),
10463f39 4458 input_bfd, input_sec);
35fc36a8 4459 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4460 {
4461 /* Arm to thumb. */
c820be07
NC		 4462
4463 if (sym_sec != NULL
4464 && sym_sec->owner != NULL
4465 && !INTERWORK_FLAG (sym_sec->owner))
4466 {
4eca0228 4467 _bfd_error_handler
90b6238f
AM		 4468 (_("%pB(%s): warning: interworking not enabled;"
4469 " first occurrence: %pB: %s call to %s"),
4470 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4471 }
4472
4473 /* We have an extra 2-bytes reach because of
4474 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4475 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4476 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4477 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4478 || (r_type == R_ARM_JUMP24)
4479 || (r_type == R_ARM_PLT32))
906e58ca 4480 {
0e1862bb 4481 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4482 /* PIC stubs. */
ebe24dd4
CL		 4483 ? ((globals->use_blx)
4484 /* V5T and above. */
4485 ? arm_stub_long_branch_any_thumb_pic
4486 /* V4T stub. */
4487 : arm_stub_long_branch_v4t_arm_thumb_pic)
4488
c2b4a39d
CL		 4489 /* non-PIC stubs. */
4490 : ((globals->use_blx)
4491 /* V5T and above. */
4492 ? arm_stub_long_branch_any_any
4493 /* V4T. */
4494 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4495 }
4496 }
4497 else
4498 {
4499 /* Arm to arm. */
4500 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4501 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4502 {
0855e32b 4503 stub_type =
0e1862bb 4504 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4505 /* PIC stubs. */
0855e32b 4506 ? (r_type == R_ARM_TLS_CALL
6a631e86 4507 /* TLS PIC Stub. */
0855e32b 4508 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4509 : (globals->nacl_p
4510 ? arm_stub_long_branch_arm_nacl_pic
4511 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4512 /* non-PIC stubs. */
7a89b94e
NC		 4513 : (globals->nacl_p
4514 ? arm_stub_long_branch_arm_nacl
4515 : arm_stub_long_branch_any_any);
906e58ca
NC		 4516 }
4517 }
4518 }
4519
fe33d2fa
CL		 4520 /* If a stub is needed, record the actual destination type. */
4521 if (stub_type != arm_stub_none)
35fc36a8 4522 *actual_branch_type = branch_type;
fe33d2fa 4523
906e58ca
NC		 4524 return stub_type;
4525}
4526
4527/* Build a name for an entry in the stub hash table. */
4528
4529static char *
4530elf32_arm_stub_name (const asection *input_section,
4531 const asection *sym_sec,
4532 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4533 const Elf_Internal_Rela *rel,
4534 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4535{
4536 char *stub_name;
4537 bfd_size_type len;
4538
4539 if (hash)
4540 {
fe33d2fa 4541 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4542 stub_name = (char *) bfd_malloc (len);
906e58ca 4543 if (stub_name != NULL)
fe33d2fa 4544 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4545 input_section->id & 0xffffffff,
4546 hash->root.root.root.string,
fe33d2fa
CL		 4547 (int) rel->r_addend & 0xffffffff,
4548 (int) stub_type);
906e58ca
NC		 4549 }
4550 else
4551 {
fe33d2fa 4552 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4553 stub_name = (char *) bfd_malloc (len);
906e58ca 4554 if (stub_name != NULL)
fe33d2fa 4555 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4556 input_section->id & 0xffffffff,
4557 sym_sec->id & 0xffffffff,
0855e32b
NS		 4558 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4559 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4560 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4561 (int) rel->r_addend & 0xffffffff,
4562 (int) stub_type);
906e58ca
NC		 4563 }
4564
4565 return stub_name;
4566}
4567
4568/* Look up an entry in the stub hash. Stub entries are cached because
4569 creating the stub name takes a bit of time. */
4570
4571static struct elf32_arm_stub_hash_entry *
4572elf32_arm_get_stub_entry (const asection *input_section,
4573 const asection *sym_sec,
4574 struct elf_link_hash_entry *hash,
4575 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4576 struct elf32_arm_link_hash_table *htab,
4577 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4578{
4579 struct elf32_arm_stub_hash_entry *stub_entry;
4580 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4581 const asection *id_sec;
4582
4583 if ((input_section->flags & SEC_CODE) == 0)
4584 return NULL;
4585
4586 /* If this input section is part of a group of sections sharing one
4587 stub section, then use the id of the first section in the group.
4588 Stub names need to include a section id, as there may well be
4589 more than one stub used to reach say, printf, and we need to
4590 distinguish between them. */
c2abbbeb 4591 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4592 id_sec = htab->stub_group[input_section->id].link_sec;
4593
4594 if (h != NULL && h->stub_cache != NULL
4595 && h->stub_cache->h == h
fe33d2fa
CL		 4596 && h->stub_cache->id_sec == id_sec
4597 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4598 {
4599 stub_entry = h->stub_cache;
4600 }
4601 else
4602 {
4603 char *stub_name;
4604
fe33d2fa 4605 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4606 if (stub_name == NULL)
4607 return NULL;
4608
4609 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4610 stub_name, FALSE, FALSE);
4611 if (h != NULL)
4612 h->stub_cache = stub_entry;
4613
4614 free (stub_name);
4615 }
4616
4617 return stub_entry;
4618}
4619
daa4adae
TP		 4620/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4621 section. */
4622
4623static bfd_boolean
4624arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4625{
4626 if (stub_type >= max_stub_type)
4627 abort (); /* Should be unreachable. */
4628
4ba2ef8f
TP		 4629 switch (stub_type)
4630 {
4631 case arm_stub_cmse_branch_thumb_only:
4632 return TRUE;
4633
4634 default:
4635 return FALSE;
4636 }
4637
4638 abort (); /* Should be unreachable. */
daa4adae
TP		 4639}
4640
4641/* Required alignment (as a power of 2) for the dedicated section holding
4642 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4643 with input sections. */
4644
4645static int
4646arm_dedicated_stub_output_section_required_alignment
4647 (enum elf32_arm_stub_type stub_type)
4648{
4649 if (stub_type >= max_stub_type)
4650 abort (); /* Should be unreachable. */
4651
4ba2ef8f
TP		 4652 switch (stub_type)
4653 {
4654 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4655 boundary. */
4656 case arm_stub_cmse_branch_thumb_only:
4657 return 5;
4658
4659 default:
4660 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4661 return 0;
4662 }
4663
4664 abort (); /* Should be unreachable. */
daa4adae
TP		 4665}
4666
4667/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4668 NULL if veneers of this type are interspersed with input sections. */
4669
4670static const char *
4671arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4672{
4673 if (stub_type >= max_stub_type)
4674 abort (); /* Should be unreachable. */
4675
4ba2ef8f
TP		 4676 switch (stub_type)
4677 {
4678 case arm_stub_cmse_branch_thumb_only:
4679 return ".gnu.sgstubs";
4680
4681 default:
4682 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4683 return NULL;
4684 }
4685
4686 abort (); /* Should be unreachable. */
daa4adae
TP		 4687}
4688
4689/* If veneers of type STUB_TYPE should go in a dedicated output section,
4690 returns the address of the hash table field in HTAB holding a pointer to the
4691 corresponding input section. Otherwise, returns NULL. */
4692
4693static asection **
4ba2ef8f
TP		 4694arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4695 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4696{
4697 if (stub_type >= max_stub_type)
4698 abort (); /* Should be unreachable. */
4699
4ba2ef8f
TP		 4700 switch (stub_type)
4701 {
4702 case arm_stub_cmse_branch_thumb_only:
4703 return &htab->cmse_stub_sec;
4704
4705 default:
4706 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4707 return NULL;
4708 }
4709
4710 abort (); /* Should be unreachable. */
daa4adae
TP		 4711}
4712
4713/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4714 is the section that branch into veneer and can be NULL if stub should go in
4715 a dedicated output section. Returns a pointer to the stub section, and the
4716 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4717 LINK_SEC_P may be NULL. */
906e58ca 4718
48229727
JB		 4719static asection *
4720elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4721 struct elf32_arm_link_hash_table *htab,
4722 enum elf32_arm_stub_type stub_type)
906e58ca 4723{
daa4adae
TP		 4724 asection *link_sec, *out_sec, **stub_sec_p;
4725 const char *stub_sec_prefix;
4726 bfd_boolean dedicated_output_section =
4727 arm_dedicated_stub_output_section_required (stub_type);
4728 int align;
906e58ca 4729
daa4adae 4730 if (dedicated_output_section)
906e58ca 4731 {
daa4adae
TP		 4732 bfd *output_bfd = htab->obfd;
4733 const char *out_sec_name =
4734 arm_dedicated_stub_output_section_name (stub_type);
4735 link_sec = NULL;
4736 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4737 stub_sec_prefix = out_sec_name;
4738 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4739 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4740 if (out_sec == NULL)
906e58ca 4741 {
90b6238f 4742 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4743 "section %s"), out_sec_name);
daa4adae 4744 return NULL;
906e58ca 4745 }
daa4adae
TP		 4746 }
4747 else
4748 {
c2abbbeb 4749 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4750 link_sec = htab->stub_group[section->id].link_sec;
4751 BFD_ASSERT (link_sec != NULL);
4752 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4753 if (*stub_sec_p == NULL)
4754 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4755 stub_sec_prefix = link_sec->name;
4756 out_sec = link_sec->output_section;
4757 align = htab->nacl_p ? 4 : 3;
906e58ca 4758 }
b38cadfb 4759
daa4adae
TP		 4760 if (*stub_sec_p == NULL)
4761 {
4762 size_t namelen;
4763 bfd_size_type len;
4764 char *s_name;
4765
4766 namelen = strlen (stub_sec_prefix);
4767 len = namelen + sizeof (STUB_SUFFIX);
4768 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4769 if (s_name == NULL)
4770 return NULL;
4771
4772 memcpy (s_name, stub_sec_prefix, namelen);
4773 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4774 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4775 align);
4776 if (*stub_sec_p == NULL)
4777 return NULL;
4778
4779 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4780 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4781 | SEC_KEEP;
4782 }
4783
4784 if (!dedicated_output_section)
4785 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4786
48229727
JB		 4787 if (link_sec_p)
4788 *link_sec_p = link_sec;
b38cadfb 4789
daa4adae 4790 return *stub_sec_p;
48229727
JB		 4791}
4792
4793/* Add a new stub entry to the stub hash. Not all fields of the new
4794 stub entry are initialised. */
4795
4796static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4797elf32_arm_add_stub (const char *stub_name, asection *section,
4798 struct elf32_arm_link_hash_table *htab,
4799 enum elf32_arm_stub_type stub_type)
48229727
JB		 4800{
4801 asection *link_sec;
4802 asection *stub_sec;
4803 struct elf32_arm_stub_hash_entry *stub_entry;
4804
daa4adae
TP		 4805 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4806 stub_type);
48229727
JB		 4807 if (stub_sec == NULL)
4808 return NULL;
906e58ca
NC		 4809
4810 /* Enter this entry into the linker stub hash table. */
4811 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4812 TRUE, FALSE);
4813 if (stub_entry == NULL)
4814 {
6bde4c52
TP		 4815 if (section == NULL)
4816 section = stub_sec;
871b3ab2 4817 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4818 section->owner, stub_name);
906e58ca
NC		 4819 return NULL;
4820 }
4821
4822 stub_entry->stub_sec = stub_sec;
0955507f 4823 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4824 stub_entry->id_sec = link_sec;
4825
906e58ca
NC		 4826 return stub_entry;
4827}
4828
4829/* Store an Arm insn into an output section not processed by
4830 elf32_arm_write_section. */
4831
4832static void
8029a119
NC		 4833put_arm_insn (struct elf32_arm_link_hash_table * htab,
4834 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4835{
4836 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4837 bfd_putl32 (val, ptr);
4838 else
4839 bfd_putb32 (val, ptr);
4840}
4841
4842/* Store a 16-bit Thumb insn into an output section not processed by
4843 elf32_arm_write_section. */
4844
4845static void
8029a119
NC		 4846put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4847 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4848{
4849 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4850 bfd_putl16 (val, ptr);
4851 else
4852 bfd_putb16 (val, ptr);
4853}
4854
a504d23a
LA		 4855/* Store a Thumb2 insn into an output section not processed by
4856 elf32_arm_write_section. */
4857
4858static void
4859put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4860 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4861{
4862 /* T2 instructions are 16-bit streamed. */
4863 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4864 {
4865 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4866 bfd_putl16 ((val & 0xffff), ptr + 2);
4867 }
4868 else
4869 {
4870 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4871 bfd_putb16 ((val & 0xffff), ptr + 2);
4872 }
4873}
4874
0855e32b
NS		 4875/* If it's possible to change R_TYPE to a more efficient access
4876 model, return the new reloc type. */
4877
4878static unsigned
b38cadfb 4879elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4880 struct elf_link_hash_entry *h)
4881{
4882 int is_local = (h == NULL);
4883
0e1862bb
L		 4884 if (bfd_link_pic (info)
4885 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4886 return r_type;
4887
b38cadfb 4888 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4889 switch (r_type)
4890 {
4891 case R_ARM_TLS_GOTDESC:
4892 case R_ARM_TLS_CALL:
4893 case R_ARM_THM_TLS_CALL:
4894 case R_ARM_TLS_DESCSEQ:
4895 case R_ARM_THM_TLS_DESCSEQ:
4896 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4897 }
4898
4899 return r_type;
4900}
4901
48229727
JB		 4902static bfd_reloc_status_type elf32_arm_final_link_relocate
4903 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4904 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4905 const char *, unsigned char, enum arm_st_branch_type,
4906 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4907
4563a860
JB		 4908static unsigned int
4909arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4910{
4911 switch (stub_type)
4912 {
4913 case arm_stub_a8_veneer_b_cond:
4914 case arm_stub_a8_veneer_b:
4915 case arm_stub_a8_veneer_bl:
4916 return 2;
4917
4918 case arm_stub_long_branch_any_any:
4919 case arm_stub_long_branch_v4t_arm_thumb:
4920 case arm_stub_long_branch_thumb_only:
80c135e5 4921 case arm_stub_long_branch_thumb2_only:
d5a67c02 4922 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4923 case arm_stub_long_branch_v4t_thumb_thumb:
4924 case arm_stub_long_branch_v4t_thumb_arm:
4925 case arm_stub_short_branch_v4t_thumb_arm:
4926 case arm_stub_long_branch_any_arm_pic:
4927 case arm_stub_long_branch_any_thumb_pic:
4928 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4929 case arm_stub_long_branch_v4t_arm_thumb_pic:
4930 case arm_stub_long_branch_v4t_thumb_arm_pic:
4931 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4932 case arm_stub_long_branch_any_tls_pic:
4933 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4934 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4935 case arm_stub_a8_veneer_blx:
4936 return 4;
b38cadfb 4937
7a89b94e
NC		 4938 case arm_stub_long_branch_arm_nacl:
4939 case arm_stub_long_branch_arm_nacl_pic:
4940 return 16;
4941
4563a860
JB		 4942 default:
4943 abort (); /* Should be unreachable. */
4944 }
4945}
4946
4f4faa4d
TP		 4947/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4948 veneering (TRUE) or have their own symbol (FALSE). */
4949
4950static bfd_boolean
4951arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4952{
4953 if (stub_type >= max_stub_type)
4954 abort (); /* Should be unreachable. */
4955
4ba2ef8f
TP		 4956 switch (stub_type)
4957 {
4958 case arm_stub_cmse_branch_thumb_only:
4959 return TRUE;
4960
4961 default:
4962 return FALSE;
4963 }
4964
4965 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4966}
4967
d7c5bd02
TP		 4968/* Returns the padding needed for the dedicated section used stubs of type
4969 STUB_TYPE. */
4970
4971static int
4972arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4973{
4974 if (stub_type >= max_stub_type)
4975 abort (); /* Should be unreachable. */
4976
4ba2ef8f
TP		 4977 switch (stub_type)
4978 {
4979 case arm_stub_cmse_branch_thumb_only:
4980 return 32;
4981
4982 default:
4983 return 0;
4984 }
4985
4986 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4987}
4988
0955507f
TP		 4989/* If veneers of type STUB_TYPE should go in a dedicated output section,
4990 returns the address of the hash table field in HTAB holding the offset at
4991 which new veneers should be layed out in the stub section. */
4992
4993static bfd_vma*
4994arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4995 enum elf32_arm_stub_type stub_type)
4996{
4997 switch (stub_type)
4998 {
4999 case arm_stub_cmse_branch_thumb_only:
5000 return &htab->new_cmse_stub_offset;
5001
5002 default:
5003 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
5004 return NULL;
5005 }
5006}
5007
906e58ca
NC		 5008static bfd_boolean
5009arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5010 void * in_arg)
5011{
7a89b94e 5012#define MAXRELOCS 3
0955507f 5013 bfd_boolean removed_sg_veneer;
906e58ca 5014 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5015 struct elf32_arm_link_hash_table *globals;
906e58ca 5016 struct bfd_link_info *info;
906e58ca
NC		 5017 asection *stub_sec;
5018 bfd *stub_bfd;
906e58ca
NC		 5019 bfd_byte *loc;
5020 bfd_vma sym_value;
5021 int template_size;
5022 int size;
d3ce72d0 5023 const insn_sequence *template_sequence;
906e58ca 5024 int i;
48229727
JB		 5025 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5026 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5027 int nrelocs = 0;
0955507f 5028 int just_allocated = 0;
906e58ca
NC		 5029
5030 /* Massage our args to the form they really have. */
5031 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5032 info = (struct bfd_link_info *) in_arg;
5033
5034 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5035 if (globals == NULL)
5036 return FALSE;
906e58ca 5037
906e58ca
NC		 5038 stub_sec = stub_entry->stub_sec;
5039
4dfe6ac6 5040 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5041 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5042 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5043 return TRUE;
fe33d2fa 5044
0955507f
TP		 5045 /* Assign a slot at the end of section if none assigned yet. */
5046 if (stub_entry->stub_offset == (bfd_vma) -1)
5047 {
5048 stub_entry->stub_offset = stub_sec->size;
5049 just_allocated = 1;
5050 }
906e58ca
NC		 5051 loc = stub_sec->contents + stub_entry->stub_offset;
5052
5053 stub_bfd = stub_sec->owner;
5054
906e58ca
NC		 5055 /* This is the address of the stub destination. */
5056 sym_value = (stub_entry->target_value
5057 + stub_entry->target_section->output_offset
5058 + stub_entry->target_section->output_section->vma);
5059
d3ce72d0 5060 template_sequence = stub_entry->stub_template;
461a49ca 5061 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5062
5063 size = 0;
461a49ca 5064 for (i = 0; i < template_size; i++)
906e58ca 5065 {
d3ce72d0 5066 switch (template_sequence[i].type)
461a49ca
DJ		 5067 {
5068 case THUMB16_TYPE:
48229727 5069 {
d3ce72d0
NC		 5070 bfd_vma data = (bfd_vma) template_sequence[i].data;
5071 if (template_sequence[i].reloc_addend != 0)
48229727 5072 {
99059e56
RM		 5073 /* We've borrowed the reloc_addend field to mean we should
5074 insert a condition code into this (Thumb-1 branch)
5075 instruction. See THUMB16_BCOND_INSN. */
5076 BFD_ASSERT ((data & 0xff00) == 0xd000);
5077 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5078 }
fe33d2fa 5079 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5080 size += 2;
5081 }
461a49ca 5082 break;
906e58ca 5083
48229727 5084 case THUMB32_TYPE:
fe33d2fa
CL		 5085 bfd_put_16 (stub_bfd,
5086 (template_sequence[i].data >> 16) & 0xffff,
5087 loc + size);
5088 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5089 loc + size + 2);
99059e56
RM		 5090 if (template_sequence[i].r_type != R_ARM_NONE)
5091 {
5092 stub_reloc_idx[nrelocs] = i;
5093 stub_reloc_offset[nrelocs++] = size;
5094 }
5095 size += 4;
5096 break;
48229727 5097
461a49ca 5098 case ARM_TYPE:
fe33d2fa
CL		 5099 bfd_put_32 (stub_bfd, template_sequence[i].data,
5100 loc + size);
461a49ca
DJ		 5101 /* Handle cases where the target is encoded within the
5102 instruction. */
d3ce72d0 5103 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5104 {
48229727
JB		 5105 stub_reloc_idx[nrelocs] = i;
5106 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5107 }
5108 size += 4;
5109 break;
5110
5111 case DATA_TYPE:
d3ce72d0 5112 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5113 stub_reloc_idx[nrelocs] = i;
5114 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5115 size += 4;
5116 break;
5117
5118 default:
5119 BFD_FAIL ();
5120 return FALSE;
5121 }
906e58ca 5122 }
461a49ca 5123
0955507f
TP		 5124 if (just_allocated)
5125 stub_sec->size += size;
906e58ca 5126
461a49ca
DJ		 5127 /* Stub size has already been computed in arm_size_one_stub. Check
5128 consistency. */
5129 BFD_ASSERT (size == stub_entry->stub_size);
5130
906e58ca 5131 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5132 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5133 sym_value |= 1;
5134
0955507f
TP		 5135 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5136 to relocate in each stub. */
5137 removed_sg_veneer =
5138 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5139 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5140
48229727 5141 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5142 {
5143 Elf_Internal_Rela rel;
5144 bfd_boolean unresolved_reloc;
5145 char *error_message;
5146 bfd_vma points_to =
5147 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5148
5149 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5150 rel.r_info = ELF32_R_INFO (0,
5151 template_sequence[stub_reloc_idx[i]].r_type);
5152 rel.r_addend = 0;
5153
5154 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5155 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5156 template should refer back to the instruction after the original
5157 branch. We use target_section as Cortex-A8 erratum workaround stubs
5158 are only generated when both source and target are in the same
5159 section. */
5160 points_to = stub_entry->target_section->output_section->vma
5161 + stub_entry->target_section->output_offset
5162 + stub_entry->source_value;
5163
5164 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5165 (template_sequence[stub_reloc_idx[i]].r_type),
5166 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5167 points_to, info, stub_entry->target_section, "", STT_FUNC,
5168 stub_entry->branch_type,
5169 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5170 &error_message);
5171 }
906e58ca
NC		 5172
5173 return TRUE;
48229727 5174#undef MAXRELOCS
906e58ca
NC		 5175}
5176
48229727
JB		 5177/* Calculate the template, template size and instruction size for a stub.
5178 Return value is the instruction size. */
906e58ca 5179
48229727
JB		 5180static unsigned int
5181find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5182 const insn_sequence **stub_template,
5183 int *stub_template_size)
906e58ca 5184{
d3ce72d0 5185 const insn_sequence *template_sequence = NULL;
48229727
JB		 5186 int template_size = 0, i;
5187 unsigned int size;
906e58ca 5188
d3ce72d0 5189 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5190 if (stub_template)
5191 *stub_template = template_sequence;
5192
48229727 5193 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5194 if (stub_template_size)
5195 *stub_template_size = template_size;
906e58ca
NC		 5196
5197 size = 0;
461a49ca
DJ		 5198 for (i = 0; i < template_size; i++)
5199 {
d3ce72d0 5200 switch (template_sequence[i].type)
461a49ca
DJ		 5201 {
5202 case THUMB16_TYPE:
5203 size += 2;
5204 break;
5205
5206 case ARM_TYPE:
48229727 5207 case THUMB32_TYPE:
461a49ca
DJ		 5208 case DATA_TYPE:
5209 size += 4;
5210 break;
5211
5212 default:
5213 BFD_FAIL ();
2a229407 5214 return 0;
461a49ca
DJ		 5215 }
5216 }
5217
48229727
JB		 5218 return size;
5219}
5220
5221/* As above, but don't actually build the stub. Just bump offset so
5222 we know stub section sizes. */
5223
5224static bfd_boolean
5225arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5226 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5227{
5228 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5229 const insn_sequence *template_sequence;
48229727
JB		 5230 int template_size, size;
5231
5232 /* Massage our args to the form they really have. */
5233 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5234
5235 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5236 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5237
d3ce72d0 5238 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5239 &template_size);
5240
0955507f
TP		 5241 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5242 if (stub_entry->stub_template_size)
5243 {
5244 stub_entry->stub_size = size;
5245 stub_entry->stub_template = template_sequence;
5246 stub_entry->stub_template_size = template_size;
5247 }
5248
5249 /* Already accounted for. */
5250 if (stub_entry->stub_offset != (bfd_vma) -1)
5251 return TRUE;
461a49ca 5252
906e58ca
NC		 5253 size = (size + 7) & ~7;
5254 stub_entry->stub_sec->size += size;
461a49ca 5255
906e58ca
NC		 5256 return TRUE;
5257}
5258
5259/* External entry points for sizing and building linker stubs. */
5260
5261/* Set up various things so that we can make a list of input sections
5262 for each output section included in the link. Returns -1 on error,
5263 0 when no stubs will be needed, and 1 on success. */
5264
5265int
5266elf32_arm_setup_section_lists (bfd *output_bfd,
5267 struct bfd_link_info *info)
5268{
5269 bfd *input_bfd;
5270 unsigned int bfd_count;
7292b3ac 5271 unsigned int top_id, top_index;
906e58ca
NC		 5272 asection *section;
5273 asection **input_list, **list;
5274 bfd_size_type amt;
5275 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5276
4dfe6ac6
NC		 5277 if (htab == NULL)
5278 return 0;
906e58ca
NC		 5279 if (! is_elf_hash_table (htab))
5280 return 0;
5281
5282 /* Count the number of input BFDs and find the top input section id. */
5283 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5284 input_bfd != NULL;
c72f2fb2 5285 input_bfd = input_bfd->link.next)
906e58ca
NC		 5286 {
5287 bfd_count += 1;
5288 for (section = input_bfd->sections;
5289 section != NULL;
5290 section = section->next)
5291 {
5292 if (top_id < section->id)
5293 top_id = section->id;
5294 }
5295 }
5296 htab->bfd_count = bfd_count;
5297
5298 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5299 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5300 if (htab->stub_group == NULL)
5301 return -1;
fe33d2fa 5302 htab->top_id = top_id;
906e58ca
NC		 5303
5304 /* We can't use output_bfd->section_count here to find the top output
5305 section index as some sections may have been removed, and
5306 _bfd_strip_section_from_output doesn't renumber the indices. */
5307 for (section = output_bfd->sections, top_index = 0;
5308 section != NULL;
5309 section = section->next)
5310 {
5311 if (top_index < section->index)
5312 top_index = section->index;
5313 }
5314
5315 htab->top_index = top_index;
5316 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5317 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5318 htab->input_list = input_list;
5319 if (input_list == NULL)
5320 return -1;
5321
5322 /* For sections we aren't interested in, mark their entries with a
5323 value we can check later. */
5324 list = input_list + top_index;
5325 do
5326 *list = bfd_abs_section_ptr;
5327 while (list-- != input_list);
5328
5329 for (section = output_bfd->sections;
5330 section != NULL;
5331 section = section->next)
5332 {
5333 if ((section->flags & SEC_CODE) != 0)
5334 input_list[section->index] = NULL;
5335 }
5336
5337 return 1;
5338}
5339
5340/* The linker repeatedly calls this function for each input section,
5341 in the order that input sections are linked into output sections.
5342 Build lists of input sections to determine groupings between which
5343 we may insert linker stubs. */
5344
5345void
5346elf32_arm_next_input_section (struct bfd_link_info *info,
5347 asection *isec)
5348{
5349 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5350
4dfe6ac6
NC		 5351 if (htab == NULL)
5352 return;
5353
906e58ca
NC		 5354 if (isec->output_section->index <= htab->top_index)
5355 {
5356 asection **list = htab->input_list + isec->output_section->index;
5357
a7470592 5358 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5359 {
5360 /* Steal the link_sec pointer for our list. */
5361#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5362 /* This happens to make the list in reverse order,
07d72278 5363 which we reverse later. */
906e58ca
NC		 5364 PREV_SEC (isec) = *list;
5365 *list = isec;
5366 }
5367 }
5368}
5369
5370/* See whether we can group stub sections together. Grouping stub
5371 sections may result in fewer stubs. More importantly, we need to
07d72278 5372 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5373 .fini output sections respectively, because glibc splits the
5374 _init and _fini functions into multiple parts. Putting a stub in
5375 the middle of a function is not a good idea. */
5376
5377static void
5378group_sections (struct elf32_arm_link_hash_table *htab,
5379 bfd_size_type stub_group_size,
07d72278 5380 bfd_boolean stubs_always_after_branch)
906e58ca 5381{
07d72278 5382 asection **list = htab->input_list;
906e58ca
NC		 5383
5384 do
5385 {
5386 asection *tail = *list;
07d72278 5387 asection *head;
906e58ca
NC		 5388
5389 if (tail == bfd_abs_section_ptr)
5390 continue;
5391
07d72278
DJ		 5392 /* Reverse the list: we must avoid placing stubs at the
5393 beginning of the section because the beginning of the text
5394 section may be required for an interrupt vector in bare metal
5395 code. */
5396#define NEXT_SEC PREV_SEC
e780aef2
CL		 5397 head = NULL;
5398 while (tail != NULL)
99059e56
RM		 5399 {
5400 /* Pop from tail. */
5401 asection *item = tail;
5402 tail = PREV_SEC (item);
e780aef2 5403
99059e56
RM		 5404 /* Push on head. */
5405 NEXT_SEC (item) = head;
5406 head = item;
5407 }
07d72278
DJ		 5408
5409 while (head != NULL)
906e58ca
NC		 5410 {
5411 asection *curr;
07d72278 5412 asection *next;
e780aef2
CL		 5413 bfd_vma stub_group_start = head->output_offset;
5414 bfd_vma end_of_next;
906e58ca 5415
07d72278 5416 curr = head;
e780aef2 5417 while (NEXT_SEC (curr) != NULL)
8cd931b7 5418 {
e780aef2
CL		 5419 next = NEXT_SEC (curr);
5420 end_of_next = next->output_offset + next->size;
5421 if (end_of_next - stub_group_start >= stub_group_size)
5422 /* End of NEXT is too far from start, so stop. */
8cd931b7 5423 break;
e780aef2
CL		 5424 /* Add NEXT to the group. */
5425 curr = next;
8cd931b7 5426 }
906e58ca 5427
07d72278 5428 /* OK, the size from the start to the start of CURR is less
906e58ca 5429 than stub_group_size and thus can be handled by one stub
07d72278 5430 section. (Or the head section is itself larger than
906e58ca
NC		 5431 stub_group_size, in which case we may be toast.)
5432 We should really be keeping track of the total size of
5433 stubs added here, as stubs contribute to the final output
7fb9f789 5434 section size. */
906e58ca
NC		 5435 do
5436 {
07d72278 5437 next = NEXT_SEC (head);
906e58ca 5438 /* Set up this stub group. */
07d72278 5439 htab->stub_group[head->id].link_sec = curr;
906e58ca 5440 }
07d72278 5441 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5442
5443 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5444 bytes after the stub section can be handled by it too. */
5445 if (!stubs_always_after_branch)
906e58ca 5446 {
e780aef2
CL		 5447 stub_group_start = curr->output_offset + curr->size;
5448
8cd931b7 5449 while (next != NULL)
906e58ca 5450 {
e780aef2
CL		 5451 end_of_next = next->output_offset + next->size;
5452 if (end_of_next - stub_group_start >= stub_group_size)
5453 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5454 break;
e780aef2 5455 /* Add NEXT to the stub group. */
07d72278
DJ		 5456 head = next;
5457 next = NEXT_SEC (head);
5458 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5459 }
5460 }
07d72278 5461 head = next;
906e58ca
NC		 5462 }
5463 }
07d72278 5464 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5465
5466 free (htab->input_list);
5467#undef PREV_SEC
07d72278 5468#undef NEXT_SEC
906e58ca
NC		 5469}
5470
48229727
JB		 5471/* Comparison function for sorting/searching relocations relating to Cortex-A8
5472 erratum fix. */
5473
5474static int
5475a8_reloc_compare (const void *a, const void *b)
5476{
21d799b5
NC		 5477 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5478 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5479
5480 if (ra->from < rb->from)
5481 return -1;
5482 else if (ra->from > rb->from)
5483 return 1;
5484 else
5485 return 0;
5486}
5487
5488static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5489 const char *, char **);
5490
5491/* Helper function to scan code for sequences which might trigger the Cortex-A8
5492 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5493 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5494 otherwise. */
5495
81694485
NC		 5496static bfd_boolean
5497cortex_a8_erratum_scan (bfd *input_bfd,
5498 struct bfd_link_info *info,
48229727
JB		 5499 struct a8_erratum_fix **a8_fixes_p,
5500 unsigned int *num_a8_fixes_p,
5501 unsigned int *a8_fix_table_size_p,
5502 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5503 unsigned int num_a8_relocs,
5504 unsigned prev_num_a8_fixes,
5505 bfd_boolean *stub_changed_p)
48229727
JB		 5506{
5507 asection *section;
5508 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5509 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5510 unsigned int num_a8_fixes = *num_a8_fixes_p;
5511 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5512
4dfe6ac6
NC		 5513 if (htab == NULL)
5514 return FALSE;
5515
48229727
JB		 5516 for (section = input_bfd->sections;
5517 section != NULL;
5518 section = section->next)
5519 {
5520 bfd_byte *contents = NULL;
5521 struct _arm_elf_section_data *sec_data;
5522 unsigned int span;
5523 bfd_vma base_vma;
5524
5525 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5526 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5527 || (section->flags & SEC_EXCLUDE) != 0
5528 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5529 || (section->output_section == bfd_abs_section_ptr))
5530 continue;
48229727
JB		 5531
5532 base_vma = section->output_section->vma + section->output_offset;
5533
5534 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5535 contents = elf_section_data (section)->this_hdr.contents;
48229727 5536 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5537 return TRUE;
48229727
JB		 5538
5539 sec_data = elf32_arm_section_data (section);
5540
5541 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5542 {
5543 unsigned int span_start = sec_data->map[span].vma;
5544 unsigned int span_end = (span == sec_data->mapcount - 1)
5545 ? section->size : sec_data->map[span + 1].vma;
5546 unsigned int i;
5547 char span_type = sec_data->map[span].type;
5548 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5549
5550 if (span_type != 't')
5551 continue;
5552
5553 /* Span is entirely within a single 4KB region: skip scanning. */
5554 if (((base_vma + span_start) & ~0xfff)
48229727 5555 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5556 continue;
5557
5558 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5559
5560 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5561 * The branch target is in the same 4KB region as the
5562 first half of the branch.
5563 * The instruction before the branch is a 32-bit
5564 length non-branch instruction. */
5565 for (i = span_start; i < span_end;)
5566 {
5567 unsigned int insn = bfd_getl16 (&contents[i]);
5568 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5569 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5570
99059e56
RM		 5571 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5572 insn_32bit = TRUE;
48229727
JB		 5573
5574 if (insn_32bit)
99059e56
RM		 5575 {
5576 /* Load the rest of the insn (in manual-friendly order). */
5577 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5578
5579 /* Encoding T4: B<c>.W. */
5580 is_b = (insn & 0xf800d000) == 0xf0009000;
5581 /* Encoding T1: BL<c>.W. */
5582 is_bl = (insn & 0xf800d000) == 0xf000d000;
5583 /* Encoding T2: BLX<c>.W. */
5584 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5585 /* Encoding T3: B<c>.W (not permitted in IT block). */
5586 is_bcc = (insn & 0xf800d000) == 0xf0008000
5587 && (insn & 0x07f00000) != 0x03800000;
5588 }
5589
5590 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5591
99059e56 5592 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5593 && insn_32bit
5594 && is_32bit_branch
5595 && last_was_32bit
5596 && ! last_was_branch)
99059e56
RM		 5597 {
5598 bfd_signed_vma offset = 0;
5599 bfd_boolean force_target_arm = FALSE;
48229727 5600 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5601 bfd_vma target;
5602 enum elf32_arm_stub_type stub_type = arm_stub_none;
5603 struct a8_erratum_reloc key, *found;
5604 bfd_boolean use_plt = FALSE;
48229727 5605
99059e56
RM		 5606 key.from = base_vma + i;
5607 found = (struct a8_erratum_reloc *)
5608 bsearch (&key, a8_relocs, num_a8_relocs,
5609 sizeof (struct a8_erratum_reloc),
5610 &a8_reloc_compare);
48229727
JB		 5611
5612 if (found)
5613 {
5614 char *error_message = NULL;
5615 struct elf_link_hash_entry *entry;
5616
5617 /* We don't care about the error returned from this
99059e56 5618 function, only if there is glue or not. */
48229727
JB		 5619 entry = find_thumb_glue (info, found->sym_name,
5620 &error_message);
5621
5622 if (entry)
5623 found->non_a8_stub = TRUE;
5624
92750f34 5625 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5626 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5627 && found->hash->root.plt.offset != (bfd_vma) -1)
5628 use_plt = TRUE;
5629
5630 if (found->r_type == R_ARM_THM_CALL)
5631 {
35fc36a8
RS		 5632 if (found->branch_type == ST_BRANCH_TO_ARM
5633 || use_plt)
92750f34
DJ		 5634 force_target_arm = TRUE;
5635 else
5636 force_target_thumb = TRUE;
5637 }
48229727
JB		 5638 }
5639
99059e56 5640 /* Check if we have an offending branch instruction. */
48229727
JB		 5641
5642 if (found && found->non_a8_stub)
5643 /* We've already made a stub for this instruction, e.g.
5644 it's a long branch or a Thumb->ARM stub. Assume that
5645 stub will suffice to work around the A8 erratum (see
5646 setting of always_after_branch above). */
5647 ;
99059e56
RM		 5648 else if (is_bcc)
5649 {
5650 offset = (insn & 0x7ff) << 1;
5651 offset |= (insn & 0x3f0000) >> 4;
5652 offset |= (insn & 0x2000) ? 0x40000 : 0;
5653 offset |= (insn & 0x800) ? 0x80000 : 0;
5654 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5655 if (offset & 0x100000)
5656 offset |= ~ ((bfd_signed_vma) 0xfffff);
5657 stub_type = arm_stub_a8_veneer_b_cond;
5658 }
5659 else if (is_b || is_bl || is_blx)
5660 {
5661 int s = (insn & 0x4000000) != 0;
5662 int j1 = (insn & 0x2000) != 0;
5663 int j2 = (insn & 0x800) != 0;
5664 int i1 = !(j1 ^ s);
5665 int i2 = !(j2 ^ s);
5666
5667 offset = (insn & 0x7ff) << 1;
5668 offset |= (insn & 0x3ff0000) >> 4;
5669 offset |= i2 << 22;
5670 offset |= i1 << 23;
5671 offset |= s << 24;
5672 if (offset & 0x1000000)
5673 offset |= ~ ((bfd_signed_vma) 0xffffff);
5674
5675 if (is_blx)
5676 offset &= ~ ((bfd_signed_vma) 3);
5677
5678 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5679 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5680 }
5681
5682 if (stub_type != arm_stub_none)
5683 {
5684 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5685
5686 /* The original instruction is a BL, but the target is
99059e56 5687 an ARM instruction. If we were not making a stub,
48229727
JB		 5688 the BL would have been converted to a BLX. Use the
5689 BLX stub instead in that case. */
5690 if (htab->use_blx && force_target_arm
5691 && stub_type == arm_stub_a8_veneer_bl)
5692 {
5693 stub_type = arm_stub_a8_veneer_blx;
5694 is_blx = TRUE;
5695 is_bl = FALSE;
5696 }
5697 /* Conversely, if the original instruction was
5698 BLX but the target is Thumb mode, use the BL
5699 stub. */
5700 else if (force_target_thumb
5701 && stub_type == arm_stub_a8_veneer_blx)
5702 {
5703 stub_type = arm_stub_a8_veneer_bl;
5704 is_blx = FALSE;
5705 is_bl = TRUE;
5706 }
5707
99059e56
RM		 5708 if (is_blx)
5709 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5710
99059e56
RM		 5711 /* If we found a relocation, use the proper destination,
5712 not the offset in the (unrelocated) instruction.
48229727
JB		 5713 Note this is always done if we switched the stub type
5714 above. */
99059e56
RM		 5715 if (found)
5716 offset =
81694485 5717 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5718
99059e56
RM		 5719 /* If the stub will use a Thumb-mode branch to a
5720 PLT target, redirect it to the preceding Thumb
5721 entry point. */
5722 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5723 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5724
99059e56 5725 target = pc_for_insn + offset;
48229727 5726
99059e56
RM		 5727 /* The BLX stub is ARM-mode code. Adjust the offset to
5728 take the different PC value (+8 instead of +4) into
48229727 5729 account. */
99059e56
RM		 5730 if (stub_type == arm_stub_a8_veneer_blx)
5731 offset += 4;
5732
5733 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5734 {
5735 char *stub_name = NULL;
5736
5737 if (num_a8_fixes == a8_fix_table_size)
5738 {
5739 a8_fix_table_size *= 2;
5740 a8_fixes = (struct a8_erratum_fix *)
5741 bfd_realloc (a8_fixes,
5742 sizeof (struct a8_erratum_fix)
5743 * a8_fix_table_size);
5744 }
48229727 5745
eb7c4339
NS		 5746 if (num_a8_fixes < prev_num_a8_fixes)
5747 {
5748 /* If we're doing a subsequent scan,
5749 check if we've found the same fix as
5750 before, and try and reuse the stub
5751 name. */
5752 stub_name = a8_fixes[num_a8_fixes].stub_name;
5753 if ((a8_fixes[num_a8_fixes].section != section)
5754 || (a8_fixes[num_a8_fixes].offset != i))
5755 {
5756 free (stub_name);
5757 stub_name = NULL;
5758 *stub_changed_p = TRUE;
5759 }
5760 }
5761
5762 if (!stub_name)
5763 {
21d799b5 5764 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5765 if (stub_name != NULL)
5766 sprintf (stub_name, "%x:%x", section->id, i);
5767 }
48229727 5768
99059e56
RM		 5769 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5770 a8_fixes[num_a8_fixes].section = section;
5771 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5772 a8_fixes[num_a8_fixes].target_offset =
5773 target - base_vma;
99059e56
RM		 5774 a8_fixes[num_a8_fixes].orig_insn = insn;
5775 a8_fixes[num_a8_fixes].stub_name = stub_name;
5776 a8_fixes[num_a8_fixes].stub_type = stub_type;
5777 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5778 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5779
99059e56
RM		 5780 num_a8_fixes++;
5781 }
5782 }
5783 }
48229727 5784
99059e56
RM		 5785 i += insn_32bit ? 4 : 2;
5786 last_was_32bit = insn_32bit;
48229727 5787 last_was_branch = is_32bit_branch;
99059e56
RM		 5788 }
5789 }
48229727
JB		 5790
5791 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5792 free (contents);
48229727 5793 }
fe33d2fa 5794
48229727
JB		 5795 *a8_fixes_p = a8_fixes;
5796 *num_a8_fixes_p = num_a8_fixes;
5797 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5798
81694485 5799 return FALSE;
48229727
JB		 5800}
5801
b715f643
TP		 5802/* Create or update a stub entry depending on whether the stub can already be
5803 found in HTAB. The stub is identified by:
5804 - its type STUB_TYPE
5805 - its source branch (note that several can share the same stub) whose
5806 section and relocation (if any) are given by SECTION and IRELA
5807 respectively
5808 - its target symbol whose input section, hash, name, value and branch type
5809 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5810 respectively
5811
5812 If found, the value of the stub's target symbol is updated from SYM_VALUE
5813 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5814 TRUE and the stub entry is initialized.
5815
0955507f
TP		 5816 Returns the stub that was created or updated, or NULL if an error
5817 occurred. */
b715f643 5818
0955507f 5819static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5820elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5821 enum elf32_arm_stub_type stub_type, asection *section,
5822 Elf_Internal_Rela *irela, asection *sym_sec,
5823 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5824 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5825 bfd_boolean *new_stub)
5826{
5827 const asection *id_sec;
5828 char *stub_name;
5829 struct elf32_arm_stub_hash_entry *stub_entry;
5830 unsigned int r_type;
4f4faa4d 5831 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5832
5833 BFD_ASSERT (stub_type != arm_stub_none);
5834 *new_stub = FALSE;
5835
4f4faa4d
TP		 5836 if (sym_claimed)
5837 stub_name = sym_name;
5838 else
5839 {
5840 BFD_ASSERT (irela);
5841 BFD_ASSERT (section);
c2abbbeb 5842 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5843
4f4faa4d
TP		 5844 /* Support for grouping stub sections. */
5845 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5846
4f4faa4d
TP		 5847 /* Get the name of this stub. */
5848 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5849 stub_type);
5850 if (!stub_name)
0955507f 5851 return NULL;
4f4faa4d 5852 }
b715f643
TP		 5853
5854 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5855 FALSE);
5856 /* The proper stub has already been created, just update its value. */
5857 if (stub_entry != NULL)
5858 {
4f4faa4d
TP		 5859 if (!sym_claimed)
5860 free (stub_name);
b715f643 5861 stub_entry->target_value = sym_value;
0955507f 5862 return stub_entry;
b715f643
TP		 5863 }
5864
daa4adae 5865 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5866 if (stub_entry == NULL)
5867 {
4f4faa4d
TP		 5868 if (!sym_claimed)
5869 free (stub_name);
0955507f 5870 return NULL;
b715f643
TP		 5871 }
5872
5873 stub_entry->target_value = sym_value;
5874 stub_entry->target_section = sym_sec;
5875 stub_entry->stub_type = stub_type;
5876 stub_entry->h = hash;
5877 stub_entry->branch_type = branch_type;
5878
4f4faa4d
TP		 5879 if (sym_claimed)
5880 stub_entry->output_name = sym_name;
5881 else
b715f643 5882 {
4f4faa4d
TP		 5883 if (sym_name == NULL)
5884 sym_name = "unnamed";
5885 stub_entry->output_name = (char *)
5886 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5887 + strlen (sym_name));
5888 if (stub_entry->output_name == NULL)
5889 {
5890 free (stub_name);
0955507f 5891 return NULL;
4f4faa4d 5892 }
b715f643 5893
4f4faa4d
TP		 5894 /* For historical reasons, use the existing names for ARM-to-Thumb and
5895 Thumb-to-ARM stubs. */
5896 r_type = ELF32_R_TYPE (irela->r_info);
5897 if ((r_type == (unsigned int) R_ARM_THM_CALL
5898 || r_type == (unsigned int) R_ARM_THM_JUMP24
5899 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5900 && branch_type == ST_BRANCH_TO_ARM)
5901 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5902 else if ((r_type == (unsigned int) R_ARM_CALL
5903 || r_type == (unsigned int) R_ARM_JUMP24)
5904 && branch_type == ST_BRANCH_TO_THUMB)
5905 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5906 else
5907 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5908 }
b715f643
TP		 5909
5910 *new_stub = TRUE;
0955507f 5911 return stub_entry;
b715f643
TP		 5912}
5913
4ba2ef8f
TP		 5914/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5915 gateway veneer to transition from non secure to secure state and create them
5916 accordingly.
5917
5918 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5919 defines the conditions that govern Secure Gateway veneer creation for a
5920 given symbol <SYM> as follows:
5921 - it has function type
5922 - it has non local binding
5923 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5924 same type, binding and value as <SYM> (called normal symbol).
5925 An entry function can handle secure state transition itself in which case
5926 its special symbol would have a different value from the normal symbol.
5927
5928 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5929 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5930 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5931 created.
4ba2ef8f 5932
0955507f 5933 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5934
5935static bfd_boolean
5936cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5937 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5938 int *cmse_stub_created)
4ba2ef8f
TP		 5939{
5940 const struct elf_backend_data *bed;
5941 Elf_Internal_Shdr *symtab_hdr;
5942 unsigned i, j, sym_count, ext_start;
5943 Elf_Internal_Sym *cmse_sym, *local_syms;
5944 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5945 enum arm_st_branch_type branch_type;
5946 char *sym_name, *lsym_name;
5947 bfd_vma sym_value;
5948 asection *section;
0955507f
TP		 5949 struct elf32_arm_stub_hash_entry *stub_entry;
5950 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5951
5952 bed = get_elf_backend_data (input_bfd);
5953 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5954 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5955 ext_start = symtab_hdr->sh_info;
5956 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5957 && out_attr[Tag_CPU_arch_profile].i == 'M');
5958
5959 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5960 if (local_syms == NULL)
5961 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5962 symtab_hdr->sh_info, 0, NULL, NULL,
5963 NULL);
5964 if (symtab_hdr->sh_info && local_syms == NULL)
5965 return FALSE;
5966
5967 /* Scan symbols. */
5968 for (i = 0; i < sym_count; i++)
5969 {
5970 cmse_invalid = FALSE;
5971
5972 if (i < ext_start)
5973 {
5974 cmse_sym = &local_syms[i];
5975 /* Not a special symbol. */
5976 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5977 continue;
5978 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5979 symtab_hdr->sh_link,
5980 cmse_sym->st_name);
5981 /* Special symbol with local binding. */
5982 cmse_invalid = TRUE;
5983 }
5984 else
5985 {
5986 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5987 sym_name = (char *) cmse_hash->root.root.root.string;
5988
5989 /* Not a special symbol. */
5990 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5991 continue;
5992
5993 /* Special symbol has incorrect binding or type. */
5994 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5995 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5996 || cmse_hash->root.type != STT_FUNC)
5997 cmse_invalid = TRUE;
5998 }
5999
6000 if (!is_v8m)
6001 {
90b6238f
AM		 6002 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
6003 "ARMv8-M architecture or later"),
4eca0228 6004 input_bfd, sym_name);
4ba2ef8f
TP		 6005 is_v8m = TRUE; /* Avoid multiple warning. */
6006 ret = FALSE;
6007 }
6008
6009 if (cmse_invalid)
6010 {
90b6238f
AM		 6011 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6012 " a global or weak function symbol"),
4eca0228 6013 input_bfd, sym_name);
4ba2ef8f
TP		 6014 ret = FALSE;
6015 if (i < ext_start)
6016 continue;
6017 }
6018
6019 sym_name += strlen (CMSE_PREFIX);
6020 hash = (struct elf32_arm_link_hash_entry *)
6021 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6022
6023 /* No associated normal symbol or it is neither global nor weak. */
6024 if (!hash
6025 || (hash->root.root.type != bfd_link_hash_defined
6026 && hash->root.root.type != bfd_link_hash_defweak)
6027 || hash->root.type != STT_FUNC)
6028 {
6029 /* Initialize here to avoid warning about use of possibly
6030 uninitialized variable. */
6031 j = 0;
6032
6033 if (!hash)
6034 {
6035 /* Searching for a normal symbol with local binding. */
6036 for (; j < ext_start; j++)
6037 {
6038 lsym_name =
6039 bfd_elf_string_from_elf_section (input_bfd,
6040 symtab_hdr->sh_link,
6041 local_syms[j].st_name);
6042 if (!strcmp (sym_name, lsym_name))
6043 break;
6044 }
6045 }
6046
6047 if (hash || j < ext_start)
6048 {
4eca0228 6049 _bfd_error_handler
90b6238f
AM		 6050 (_("%pB: invalid standard symbol `%s'; it must be "
6051 "a global or weak function symbol"),
6052 input_bfd, sym_name);
4ba2ef8f
TP		 6053 }
6054 else
4eca0228 6055 _bfd_error_handler
90b6238f 6056 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6057 ret = FALSE;
6058 if (!hash)
6059 continue;
6060 }
6061
6062 sym_value = hash->root.root.u.def.value;
6063 section = hash->root.root.u.def.section;
6064
6065 if (cmse_hash->root.root.u.def.section != section)
6066 {
4eca0228 6067 _bfd_error_handler
90b6238f 6068 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6069 input_bfd, sym_name);
6070 ret = FALSE;
6071 }
6072 if (cmse_hash->root.root.u.def.value != sym_value)
6073 continue; /* Ignore: could be an entry function starting with SG. */
6074
6075 /* If this section is a link-once section that will be discarded, then
6076 don't create any stubs. */
6077 if (section->output_section == NULL)
6078 {
4eca0228 6079 _bfd_error_handler
90b6238f 6080 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6081 continue;
6082 }
6083
6084 if (hash->root.size == 0)
6085 {
4eca0228 6086 _bfd_error_handler
90b6238f 6087 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6088 ret = FALSE;
6089 }
6090
6091 if (!ret)
6092 continue;
6093 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6094 stub_entry
4ba2ef8f
TP		 6095 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6096 NULL, NULL, section, hash, sym_name,
6097 sym_value, branch_type, &new_stub);
6098
0955507f 6099 if (stub_entry == NULL)
4ba2ef8f
TP		 6100 ret = FALSE;
6101 else
6102 {
6103 BFD_ASSERT (new_stub);
0955507f 6104 (*cmse_stub_created)++;
4ba2ef8f
TP		 6105 }
6106 }
6107
6108 if (!symtab_hdr->contents)
6109 free (local_syms);
6110 return ret;
6111}
6112
0955507f
TP		 6113/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6114 code entry function, ie can be called from non secure code without using a
6115 veneer. */
6116
6117static bfd_boolean
6118cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6119{
42484486 6120 bfd_byte contents[4];
0955507f
TP		 6121 uint32_t first_insn;
6122 asection *section;
6123 file_ptr offset;
6124 bfd *abfd;
6125
6126 /* Defined symbol of function type. */
6127 if (hash->root.root.type != bfd_link_hash_defined
6128 && hash->root.root.type != bfd_link_hash_defweak)
6129 return FALSE;
6130 if (hash->root.type != STT_FUNC)
6131 return FALSE;
6132
6133 /* Read first instruction. */
6134 section = hash->root.root.u.def.section;
6135 abfd = section->owner;
6136 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6137 if (!bfd_get_section_contents (abfd, section, contents, offset,
6138 sizeof (contents)))
0955507f
TP		 6139 return FALSE;
6140
42484486
TP		 6141 first_insn = bfd_get_32 (abfd, contents);
6142
6143 /* Starts by SG instruction. */
0955507f
TP		 6144 return first_insn == 0xe97fe97f;
6145}
6146
6147/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6148 secure gateway veneers (ie. the veneers was not in the input import library)
6149 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6150
6151static bfd_boolean
6152arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6153{
6154 struct elf32_arm_stub_hash_entry *stub_entry;
6155 struct bfd_link_info *info;
6156
6157 /* Massage our args to the form they really have. */
6158 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6159 info = (struct bfd_link_info *) gen_info;
6160
6161 if (info->out_implib_bfd)
6162 return TRUE;
6163
6164 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6165 return TRUE;
6166
6167 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6168 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6169
6170 return TRUE;
6171}
6172
6173/* Set offset of each secure gateway veneers so that its address remain
6174 identical to the one in the input import library referred by
6175 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6176 (present in input import library but absent from the executable being
6177 linked) or if new veneers appeared and there is no output import library
6178 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6179 number of secure gateway veneers found in the input import library.
6180
6181 The function returns whether an error occurred. If no error occurred,
6182 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6183 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6184 veneer observed set for new veneers to be layed out after. */
6185
6186static bfd_boolean
6187set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6188 struct elf32_arm_link_hash_table *htab,
6189 int *cmse_stub_created)
6190{
6191 long symsize;
6192 char *sym_name;
6193 flagword flags;
6194 long i, symcount;
6195 bfd *in_implib_bfd;
6196 asection *stub_out_sec;
6197 bfd_boolean ret = TRUE;
6198 Elf_Internal_Sym *intsym;
6199 const char *out_sec_name;
6200 bfd_size_type cmse_stub_size;
6201 asymbol **sympp = NULL, *sym;
6202 struct elf32_arm_link_hash_entry *hash;
6203 const insn_sequence *cmse_stub_template;
6204 struct elf32_arm_stub_hash_entry *stub_entry;
6205 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6206 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6207 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6208
6209 /* No input secure gateway import library. */
6210 if (!htab->in_implib_bfd)
6211 return TRUE;
6212
6213 in_implib_bfd = htab->in_implib_bfd;
6214 if (!htab->cmse_implib)
6215 {
871b3ab2 6216 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6217 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6218 return FALSE;
6219 }
6220
6221 /* Get symbol table size. */
6222 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6223 if (symsize < 0)
6224 return FALSE;
6225
6226 /* Read in the input secure gateway import library's symbol table. */
6227 sympp = (asymbol **) xmalloc (symsize);
6228 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6229 if (symcount < 0)
6230 {
6231 ret = FALSE;
6232 goto free_sym_buf;
6233 }
6234
6235 htab->new_cmse_stub_offset = 0;
6236 cmse_stub_size =
6237 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6238 &cmse_stub_template,
6239 &cmse_stub_template_size);
6240 out_sec_name =
6241 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6242 stub_out_sec =
6243 bfd_get_section_by_name (htab->obfd, out_sec_name);
6244 if (stub_out_sec != NULL)
6245 cmse_stub_sec_vma = stub_out_sec->vma;
6246
6247 /* Set addresses of veneers mentionned in input secure gateway import
6248 library's symbol table. */
6249 for (i = 0; i < symcount; i++)
6250 {
6251 sym = sympp[i];
6252 flags = sym->flags;
6253 sym_name = (char *) bfd_asymbol_name (sym);
6254 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6255
6256 if (sym->section != bfd_abs_section_ptr
6257 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6258 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6259 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6260 != ST_BRANCH_TO_THUMB))
6261 {
90b6238f
AM		 6262 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6263 "symbol should be absolute, global and "
6264 "refer to Thumb functions"),
4eca0228 6265 in_implib_bfd, sym_name);
0955507f
TP		 6266 ret = FALSE;
6267 continue;
6268 }
6269
6270 veneer_value = bfd_asymbol_value (sym);
6271 stub_offset = veneer_value - cmse_stub_sec_vma;
6272 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6273 FALSE, FALSE);
6274 hash = (struct elf32_arm_link_hash_entry *)
6275 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6276
6277 /* Stub entry should have been created by cmse_scan or the symbol be of
6278 a secure function callable from non secure code. */
6279 if (!stub_entry && !hash)
6280 {
6281 bfd_boolean new_stub;
6282
4eca0228 6283 _bfd_error_handler
90b6238f 6284 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6285 hash = (struct elf32_arm_link_hash_entry *)
6286 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6287 stub_entry
6288 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6289 NULL, NULL, bfd_abs_section_ptr, hash,
6290 sym_name, veneer_value,
6291 ST_BRANCH_TO_THUMB, &new_stub);
6292 if (stub_entry == NULL)
6293 ret = FALSE;
6294 else
6295 {
6296 BFD_ASSERT (new_stub);
6297 new_cmse_stubs_created++;
6298 (*cmse_stub_created)++;
6299 }
6300 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6301 stub_entry->stub_offset = stub_offset;
6302 }
6303 /* Symbol found is not callable from non secure code. */
6304 else if (!stub_entry)
6305 {
6306 if (!cmse_entry_fct_p (hash))
6307 {
90b6238f 6308 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6309 sym_name);
0955507f
TP		 6310 ret = FALSE;
6311 }
6312 continue;
6313 }
6314 else
6315 {
6316 /* Only stubs for SG veneers should have been created. */
6317 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6318
6319 /* Check visibility hasn't changed. */
6320 if (!!(flags & BSF_GLOBAL)
6321 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6322 _bfd_error_handler
90b6238f 6323 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6324 sym_name);
6325
6326 stub_entry->stub_offset = stub_offset;
6327 }
6328
6329 /* Size should match that of a SG veneer. */
6330 if (intsym->st_size != cmse_stub_size)
6331 {
90b6238f 6332 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6333 in_implib_bfd, sym_name);
0955507f
TP		 6334 ret = FALSE;
6335 }
6336
6337 /* Previous veneer address is before current SG veneer section. */
6338 if (veneer_value < cmse_stub_sec_vma)
6339 {
6340 /* Avoid offset underflow. */
6341 if (stub_entry)
6342 stub_entry->stub_offset = 0;
6343 stub_offset = 0;
6344 ret = FALSE;
6345 }
6346
6347 /* Complain if stub offset not a multiple of stub size. */
6348 if (stub_offset % cmse_stub_size)
6349 {
4eca0228 6350 _bfd_error_handler
90b6238f
AM		 6351 (_("offset of veneer for entry function `%s' not a multiple of "
6352 "its size"), sym_name);
0955507f
TP		 6353 ret = FALSE;
6354 }
6355
6356 if (!ret)
6357 continue;
6358
6359 new_cmse_stubs_created--;
6360 if (veneer_value < cmse_stub_array_start)
6361 cmse_stub_array_start = veneer_value;
6362 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6363 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6364 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6365 }
6366
6367 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6368 {
6369 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6370 _bfd_error_handler
0955507f
TP		 6371 (_("new entry function(s) introduced but no output import library "
6372 "specified:"));
6373 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6374 }
6375
6376 if (cmse_stub_array_start != cmse_stub_sec_vma)
6377 {
4eca0228 6378 _bfd_error_handler
90b6238f 6379 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6380 out_sec_name);
6381 ret = FALSE;
6382 }
6383
6384free_sym_buf:
6385 free (sympp);
6386 return ret;
6387}
6388
906e58ca
NC		 6389/* Determine and set the size of the stub section for a final link.
6390
6391 The basic idea here is to examine all the relocations looking for
6392 PC-relative calls to a target that is unreachable with a "bl"
6393 instruction. */
6394
6395bfd_boolean
6396elf32_arm_size_stubs (bfd *output_bfd,
6397 bfd *stub_bfd,
6398 struct bfd_link_info *info,
6399 bfd_signed_vma group_size,
7a89b94e 6400 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6401 asection *,
7a89b94e 6402 unsigned int),
906e58ca
NC		 6403 void (*layout_sections_again) (void))
6404{
0955507f 6405 bfd_boolean ret = TRUE;
4ba2ef8f 6406 obj_attribute *out_attr;
0955507f 6407 int cmse_stub_created = 0;
906e58ca 6408 bfd_size_type stub_group_size;
4ba2ef8f 6409 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6410 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6411 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6412 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6413 struct a8_erratum_reloc *a8_relocs = NULL;
6414 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6415
4dfe6ac6
NC		 6416 if (htab == NULL)
6417 return FALSE;
6418
48229727
JB		 6419 if (htab->fix_cortex_a8)
6420 {
21d799b5 6421 a8_fixes = (struct a8_erratum_fix *)
99059e56 6422 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6423 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6424 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6425 }
906e58ca
NC		 6426
6427 /* Propagate mach to stub bfd, because it may not have been
6428 finalized when we created stub_bfd. */
6429 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6430 bfd_get_mach (output_bfd));
6431
6432 /* Stash our params away. */
6433 htab->stub_bfd = stub_bfd;
6434 htab->add_stub_section = add_stub_section;
6435 htab->layout_sections_again = layout_sections_again;
07d72278 6436 stubs_always_after_branch = group_size < 0;
48229727 6437
4ba2ef8f
TP		 6438 out_attr = elf_known_obj_attributes_proc (output_bfd);
6439 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6440
48229727
JB		 6441 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6442 as the first half of a 32-bit branch straddling two 4K pages. This is a
6443 crude way of enforcing that. */
6444 if (htab->fix_cortex_a8)
6445 stubs_always_after_branch = 1;
6446
906e58ca
NC		 6447 if (group_size < 0)
6448 stub_group_size = -group_size;
6449 else
6450 stub_group_size = group_size;
6451
6452 if (stub_group_size == 1)
6453 {
6454 /* Default values. */
6455 /* Thumb branch range is +-4MB has to be used as the default
6456 maximum size (a given section can contain both ARM and Thumb
6457 code, so the worst case has to be taken into account).
6458
6459 This value is 24K less than that, which allows for 2025
6460 12-byte stubs. If we exceed that, then we will fail to link.
6461 The user will have to relink with an explicit group size
6462 option. */
6463 stub_group_size = 4170000;
6464 }
6465
07d72278 6466 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6467
3ae046cc
NS		 6468 /* If we're applying the cortex A8 fix, we need to determine the
6469 program header size now, because we cannot change it later --
6470 that could alter section placements. Notice the A8 erratum fix
6471 ends up requiring the section addresses to remain unchanged
6472 modulo the page size. That's something we cannot represent
6473 inside BFD, and we don't want to force the section alignment to
6474 be the page size. */
6475 if (htab->fix_cortex_a8)
6476 (*htab->layout_sections_again) ();
6477
906e58ca
NC		 6478 while (1)
6479 {
6480 bfd *input_bfd;
6481 unsigned int bfd_indx;
6482 asection *stub_sec;
d7c5bd02 6483 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6484 bfd_boolean stub_changed = FALSE;
6485 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6486
48229727 6487 num_a8_fixes = 0;
906e58ca
NC		 6488 for (input_bfd = info->input_bfds, bfd_indx = 0;
6489 input_bfd != NULL;
c72f2fb2 6490 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6491 {
6492 Elf_Internal_Shdr *symtab_hdr;
6493 asection *section;
6494 Elf_Internal_Sym *local_syms = NULL;
6495
8c246a60
AM		 6496 if (!is_arm_elf (input_bfd)
6497 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0)
99059e56 6498 continue;
adbcc655 6499
48229727
JB		 6500 num_a8_relocs = 0;
6501
906e58ca
NC		 6502 /* We'll need the symbol table in a second. */
6503 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6504 if (symtab_hdr->sh_info == 0)
6505 continue;
6506
4ba2ef8f
TP		 6507 /* Limit scan of symbols to object file whose profile is
6508 Microcontroller to not hinder performance in the general case. */
6509 if (m_profile && first_veneer_scan)
6510 {
6511 struct elf_link_hash_entry **sym_hashes;
6512
6513 sym_hashes = elf_sym_hashes (input_bfd);
6514 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6515 &cmse_stub_created))
4ba2ef8f 6516 goto error_ret_free_local;
0955507f
TP		 6517
6518 if (cmse_stub_created != 0)
6519 stub_changed = TRUE;
4ba2ef8f
TP		 6520 }
6521
906e58ca
NC		 6522 /* Walk over each section attached to the input bfd. */
6523 for (section = input_bfd->sections;
6524 section != NULL;
6525 section = section->next)
6526 {
6527 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6528
6529 /* If there aren't any relocs, then there's nothing more
6530 to do. */
6531 if ((section->flags & SEC_RELOC) == 0
6532 || section->reloc_count == 0
6533 || (section->flags & SEC_CODE) == 0)
6534 continue;
6535
6536 /* If this section is a link-once section that will be
6537 discarded, then don't create any stubs. */
6538 if (section->output_section == NULL
6539 || section->output_section->owner != output_bfd)
6540 continue;
6541
6542 /* Get the relocs. */
6543 internal_relocs
6544 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6545 NULL, info->keep_memory);
6546 if (internal_relocs == NULL)
6547 goto error_ret_free_local;
6548
6549 /* Now examine each relocation. */
6550 irela = internal_relocs;
6551 irelaend = irela + section->reloc_count;
6552 for (; irela < irelaend; irela++)
6553 {
6554 unsigned int r_type, r_indx;
906e58ca
NC		 6555 asection *sym_sec;
6556 bfd_vma sym_value;
6557 bfd_vma destination;
6558 struct elf32_arm_link_hash_entry *hash;
7413f23f 6559 const char *sym_name;
34e77a92 6560 unsigned char st_type;
35fc36a8 6561 enum arm_st_branch_type branch_type;
48229727 6562 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6563
6564 r_type = ELF32_R_TYPE (irela->r_info);
6565 r_indx = ELF32_R_SYM (irela->r_info);
6566
6567 if (r_type >= (unsigned int) R_ARM_max)
6568 {
6569 bfd_set_error (bfd_error_bad_value);
6570 error_ret_free_internal:
6571 if (elf_section_data (section)->relocs == NULL)
6572 free (internal_relocs);
15dd01b1
TP		 6573 /* Fall through. */
6574 error_ret_free_local:
6575 if (local_syms != NULL
6576 && (symtab_hdr->contents
6577 != (unsigned char *) local_syms))
6578 free (local_syms);
6579 return FALSE;
906e58ca 6580 }
b38cadfb 6581
0855e32b
NS		 6582 hash = NULL;
6583 if (r_indx >= symtab_hdr->sh_info)
6584 hash = elf32_arm_hash_entry
6585 (elf_sym_hashes (input_bfd)
6586 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6587
0855e32b
NS		 6588 /* Only look for stubs on branch instructions, or
6589 non-relaxed TLSCALL */
906e58ca 6590 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6591 && (r_type != (unsigned int) R_ARM_THM_CALL)
6592 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6593 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6594 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6595 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6596 && (r_type != (unsigned int) R_ARM_PLT32)
6597 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6598 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6599 && r_type == elf32_arm_tls_transition
6600 (info, r_type, &hash->root)
6601 && ((hash ? hash->tls_type
6602 : (elf32_arm_local_got_tls_type
6603 (input_bfd)[r_indx]))
6604 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6605 continue;
6606
6607 /* Now determine the call target, its name, value,
6608 section. */
6609 sym_sec = NULL;
6610 sym_value = 0;
6611 destination = 0;
7413f23f 6612 sym_name = NULL;
b38cadfb 6613
0855e32b
NS		 6614 if (r_type == (unsigned int) R_ARM_TLS_CALL
6615 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6616 {
6617 /* A non-relaxed TLS call. The target is the
6618 plt-resident trampoline and nothing to do
6619 with the symbol. */
6620 BFD_ASSERT (htab->tls_trampoline > 0);
6621 sym_sec = htab->root.splt;
6622 sym_value = htab->tls_trampoline;
6623 hash = 0;
34e77a92 6624 st_type = STT_FUNC;
35fc36a8 6625 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6626 }
6627 else if (!hash)
906e58ca
NC		 6628 {
6629 /* It's a local symbol. */
6630 Elf_Internal_Sym *sym;
906e58ca
NC		 6631
6632 if (local_syms == NULL)
6633 {
6634 local_syms
6635 = (Elf_Internal_Sym *) symtab_hdr->contents;
6636 if (local_syms == NULL)
6637 local_syms
6638 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6639 symtab_hdr->sh_info, 0,
6640 NULL, NULL, NULL);
6641 if (local_syms == NULL)
6642 goto error_ret_free_internal;
6643 }
6644
6645 sym = local_syms + r_indx;
f6d250ce
TS		 6646 if (sym->st_shndx == SHN_UNDEF)
6647 sym_sec = bfd_und_section_ptr;
6648 else if (sym->st_shndx == SHN_ABS)
6649 sym_sec = bfd_abs_section_ptr;
6650 else if (sym->st_shndx == SHN_COMMON)
6651 sym_sec = bfd_com_section_ptr;
6652 else
6653 sym_sec =
6654 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6655
ffcb4889
NS		 6656 if (!sym_sec)
6657 /* This is an undefined symbol. It can never
6a631e86 6658 be resolved. */
ffcb4889 6659 continue;
fe33d2fa 6660
906e58ca
NC		 6661 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6662 sym_value = sym->st_value;
6663 destination = (sym_value + irela->r_addend
6664 + sym_sec->output_offset
6665 + sym_sec->output_section->vma);
34e77a92 6666 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6667 branch_type =
6668 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6669 sym_name
6670 = bfd_elf_string_from_elf_section (input_bfd,
6671 symtab_hdr->sh_link,
6672 sym->st_name);
906e58ca
NC		 6673 }
6674 else
6675 {
6676 /* It's an external symbol. */
906e58ca
NC		 6677 while (hash->root.root.type == bfd_link_hash_indirect
6678 || hash->root.root.type == bfd_link_hash_warning)
6679 hash = ((struct elf32_arm_link_hash_entry *)
6680 hash->root.root.u.i.link);
6681
6682 if (hash->root.root.type == bfd_link_hash_defined
6683 || hash->root.root.type == bfd_link_hash_defweak)
6684 {
6685 sym_sec = hash->root.root.u.def.section;
6686 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6687
6688 struct elf32_arm_link_hash_table *globals =
6689 elf32_arm_hash_table (info);
6690
6691 /* For a destination in a shared library,
6692 use the PLT stub as target address to
6693 decide whether a branch stub is
6694 needed. */
4dfe6ac6 6695 if (globals != NULL
362d30a1 6696 && globals->root.splt != NULL
4dfe6ac6 6697 && hash != NULL
022f8312
CL		 6698 && hash->root.plt.offset != (bfd_vma) -1)
6699 {
362d30a1 6700 sym_sec = globals->root.splt;
022f8312
CL		 6701 sym_value = hash->root.plt.offset;
6702 if (sym_sec->output_section != NULL)
6703 destination = (sym_value
6704 + sym_sec->output_offset
6705 + sym_sec->output_section->vma);
6706 }
6707 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6708 destination = (sym_value + irela->r_addend
6709 + sym_sec->output_offset
6710 + sym_sec->output_section->vma);
6711 }
69c5861e
CL		 6712 else if ((hash->root.root.type == bfd_link_hash_undefined)
6713 || (hash->root.root.type == bfd_link_hash_undefweak))
6714 {
6715 /* For a shared library, use the PLT stub as
6716 target address to decide whether a long
6717 branch stub is needed.
6718 For absolute code, they cannot be handled. */
6719 struct elf32_arm_link_hash_table *globals =
6720 elf32_arm_hash_table (info);
6721
4dfe6ac6 6722 if (globals != NULL
362d30a1 6723 && globals->root.splt != NULL
4dfe6ac6 6724 && hash != NULL
69c5861e
CL		 6725 && hash->root.plt.offset != (bfd_vma) -1)
6726 {
362d30a1 6727 sym_sec = globals->root.splt;
69c5861e
CL		 6728 sym_value = hash->root.plt.offset;
6729 if (sym_sec->output_section != NULL)
6730 destination = (sym_value
6731 + sym_sec->output_offset
6732 + sym_sec->output_section->vma);
6733 }
6734 else
6735 continue;
6736 }
906e58ca
NC		 6737 else
6738 {
6739 bfd_set_error (bfd_error_bad_value);
6740 goto error_ret_free_internal;
6741 }
34e77a92 6742 st_type = hash->root.type;
39d911fc
TP		 6743 branch_type =
6744 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6745 sym_name = hash->root.root.root.string;
906e58ca
NC		 6746 }
6747
48229727 6748 do
7413f23f 6749 {
b715f643 6750 bfd_boolean new_stub;
0955507f 6751 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6752
48229727
JB		 6753 /* Determine what (if any) linker stub is needed. */
6754 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6755 st_type, &branch_type,
6756 hash, destination, sym_sec,
48229727
JB		 6757 input_bfd, sym_name);
6758 if (stub_type == arm_stub_none)
6759 break;
6760
48229727
JB		 6761 /* We've either created a stub for this reloc already,
6762 or we are about to. */
0955507f 6763 stub_entry =
b715f643
TP		 6764 elf32_arm_create_stub (htab, stub_type, section, irela,
6765 sym_sec, hash,
6766 (char *) sym_name, sym_value,
6767 branch_type, &new_stub);
7413f23f 6768
0955507f 6769 created_stub = stub_entry != NULL;
b715f643
TP		 6770 if (!created_stub)
6771 goto error_ret_free_internal;
6772 else if (!new_stub)
6773 break;
99059e56 6774 else
b715f643 6775 stub_changed = TRUE;
99059e56
RM		 6776 }
6777 while (0);
6778
6779 /* Look for relocations which might trigger Cortex-A8
6780 erratum. */
6781 if (htab->fix_cortex_a8
6782 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6783 || r_type == (unsigned int) R_ARM_THM_JUMP19
6784 || r_type == (unsigned int) R_ARM_THM_CALL
6785 || r_type == (unsigned int) R_ARM_THM_XPC22))
6786 {
6787 bfd_vma from = section->output_section->vma
6788 + section->output_offset
6789 + irela->r_offset;
6790
6791 if ((from & 0xfff) == 0xffe)
6792 {
6793 /* Found a candidate. Note we haven't checked the
6794 destination is within 4K here: if we do so (and
6795 don't create an entry in a8_relocs) we can't tell
6796 that a branch should have been relocated when
6797 scanning later. */
6798 if (num_a8_relocs == a8_reloc_table_size)
6799 {
6800 a8_reloc_table_size *= 2;
6801 a8_relocs = (struct a8_erratum_reloc *)
6802 bfd_realloc (a8_relocs,
6803 sizeof (struct a8_erratum_reloc)
6804 * a8_reloc_table_size);
6805 }
6806
6807 a8_relocs[num_a8_relocs].from = from;
6808 a8_relocs[num_a8_relocs].destination = destination;
6809 a8_relocs[num_a8_relocs].r_type = r_type;
6810 a8_relocs[num_a8_relocs].branch_type = branch_type;
6811 a8_relocs[num_a8_relocs].sym_name = sym_name;
6812 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6813 a8_relocs[num_a8_relocs].hash = hash;
6814
6815 num_a8_relocs++;
6816 }
6817 }
906e58ca
NC		 6818 }
6819
99059e56
RM		 6820 /* We're done with the internal relocs, free them. */
6821 if (elf_section_data (section)->relocs == NULL)
6822 free (internal_relocs);
6823 }
48229727 6824
99059e56 6825 if (htab->fix_cortex_a8)
48229727 6826 {
99059e56
RM		 6827 /* Sort relocs which might apply to Cortex-A8 erratum. */
6828 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6829 sizeof (struct a8_erratum_reloc),
99059e56 6830 &a8_reloc_compare);
48229727 6831
99059e56
RM		 6832 /* Scan for branches which might trigger Cortex-A8 erratum. */
6833 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6834 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6835 a8_relocs, num_a8_relocs,
6836 prev_num_a8_fixes, &stub_changed)
6837 != 0)
48229727 6838 goto error_ret_free_local;
5e681ec4 6839 }
7f991970
AM		 6840
6841 if (local_syms != NULL
6842 && symtab_hdr->contents != (unsigned char *) local_syms)
6843 {
6844 if (!info->keep_memory)
6845 free (local_syms);
6846 else
6847 symtab_hdr->contents = (unsigned char *) local_syms;
6848 }
5e681ec4
PB		 6849 }
6850
0955507f
TP		 6851 if (first_veneer_scan
6852 && !set_cmse_veneer_addr_from_implib (info, htab,
6853 &cmse_stub_created))
6854 ret = FALSE;
6855
eb7c4339 6856 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6857 stub_changed = TRUE;
48229727 6858
906e58ca
NC		 6859 if (!stub_changed)
6860 break;
5e681ec4 6861
906e58ca
NC		 6862 /* OK, we've added some stubs. Find out the new size of the
6863 stub sections. */
6864 for (stub_sec = htab->stub_bfd->sections;
6865 stub_sec != NULL;
6866 stub_sec = stub_sec->next)
3e6b1042
DJ		 6867 {
6868 /* Ignore non-stub sections. */
6869 if (!strstr (stub_sec->name, STUB_SUFFIX))
6870 continue;
6871
6872 stub_sec->size = 0;
6873 }
b34b2d70 6874
0955507f
TP		 6875 /* Add new SG veneers after those already in the input import
6876 library. */
6877 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6878 stub_type++)
6879 {
6880 bfd_vma *start_offset_p;
6881 asection **stub_sec_p;
6882
6883 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6884 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6885 if (start_offset_p == NULL)
6886 continue;
6887
6888 BFD_ASSERT (stub_sec_p != NULL);
6889 if (*stub_sec_p != NULL)
6890 (*stub_sec_p)->size = *start_offset_p;
6891 }
6892
d7c5bd02 6893 /* Compute stub section size, considering padding. */
906e58ca 6894 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6895 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6896 stub_type++)
6897 {
6898 int size, padding;
6899 asection **stub_sec_p;
6900
6901 padding = arm_dedicated_stub_section_padding (stub_type);
6902 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6903 /* Skip if no stub input section or no stub section padding
6904 required. */
6905 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6906 continue;
6907 /* Stub section padding required but no dedicated section. */
6908 BFD_ASSERT (stub_sec_p);
6909
6910 size = (*stub_sec_p)->size;
6911 size = (size + padding - 1) & ~(padding - 1);
6912 (*stub_sec_p)->size = size;
6913 }
906e58ca 6914
48229727
JB		 6915 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6916 if (htab->fix_cortex_a8)
99059e56
RM		 6917 for (i = 0; i < num_a8_fixes; i++)
6918 {
48229727 6919 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6920 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6921
6922 if (stub_sec == NULL)
7f991970 6923 return FALSE;
48229727 6924
99059e56
RM		 6925 stub_sec->size
6926 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6927 NULL);
6928 }
48229727
JB		 6929
6930
906e58ca
NC		 6931 /* Ask the linker to do its stuff. */
6932 (*htab->layout_sections_again) ();
4ba2ef8f 6933 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6934 }
6935
48229727
JB		 6936 /* Add stubs for Cortex-A8 erratum fixes now. */
6937 if (htab->fix_cortex_a8)
6938 {
6939 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6940 {
6941 struct elf32_arm_stub_hash_entry *stub_entry;
6942 char *stub_name = a8_fixes[i].stub_name;
6943 asection *section = a8_fixes[i].section;
6944 unsigned int section_id = a8_fixes[i].section->id;
6945 asection *link_sec = htab->stub_group[section_id].link_sec;
6946 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6947 const insn_sequence *template_sequence;
6948 int template_size, size = 0;
6949
6950 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6951 TRUE, FALSE);
6952 if (stub_entry == NULL)
6953 {
871b3ab2 6954 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6955 section->owner, stub_name);
99059e56
RM		 6956 return FALSE;
6957 }
6958
6959 stub_entry->stub_sec = stub_sec;
0955507f 6960 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6961 stub_entry->id_sec = link_sec;
6962 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6963 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6964 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6965 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6966 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6967 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6968
99059e56
RM		 6969 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6970 &template_sequence,
6971 &template_size);
48229727 6972
99059e56
RM		 6973 stub_entry->stub_size = size;
6974 stub_entry->stub_template = template_sequence;
6975 stub_entry->stub_template_size = template_size;
6976 }
48229727
JB		 6977
6978 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6979 elf32_arm_write_section(). */
48229727
JB		 6980 htab->a8_erratum_fixes = a8_fixes;
6981 htab->num_a8_erratum_fixes = num_a8_fixes;
6982 }
6983 else
6984 {
6985 htab->a8_erratum_fixes = NULL;
6986 htab->num_a8_erratum_fixes = 0;
6987 }
0955507f 6988 return ret;
5e681ec4
PB		 6989}
6990
906e58ca
NC		 6991/* Build all the stubs associated with the current output file. The
6992 stubs are kept in a hash table attached to the main linker hash
6993 table. We also set up the .plt entries for statically linked PIC
6994 functions here. This function is called via arm_elf_finish in the
6995 linker. */
252b5132 6996
906e58ca
NC		 6997bfd_boolean
6998elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6999{
906e58ca
NC		 7000 asection *stub_sec;
7001 struct bfd_hash_table *table;
0955507f 7002 enum elf32_arm_stub_type stub_type;
906e58ca 7003 struct elf32_arm_link_hash_table *htab;
252b5132 7004
906e58ca 7005 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 7006 if (htab == NULL)
7007 return FALSE;
252b5132 7008
906e58ca
NC		 7009 for (stub_sec = htab->stub_bfd->sections;
7010 stub_sec != NULL;
7011 stub_sec = stub_sec->next)
252b5132 7012 {
906e58ca
NC		 7013 bfd_size_type size;
7014
8029a119 7015 /* Ignore non-stub sections. */
906e58ca
NC		 7016 if (!strstr (stub_sec->name, STUB_SUFFIX))
7017 continue;
7018
d7c5bd02 7019 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7020 must at least be done for stub section requiring padding and for SG
7021 veneers to ensure that a non secure code branching to a removed SG
7022 veneer causes an error. */
906e58ca 7023 size = stub_sec->size;
21d799b5 7024 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7025 if (stub_sec->contents == NULL && size != 0)
7026 return FALSE;
0955507f 7027
906e58ca 7028 stub_sec->size = 0;
252b5132
RH		 7029 }
7030
0955507f
TP		 7031 /* Add new SG veneers after those already in the input import library. */
7032 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7033 {
7034 bfd_vma *start_offset_p;
7035 asection **stub_sec_p;
7036
7037 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7038 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7039 if (start_offset_p == NULL)
7040 continue;
7041
7042 BFD_ASSERT (stub_sec_p != NULL);
7043 if (*stub_sec_p != NULL)
7044 (*stub_sec_p)->size = *start_offset_p;
7045 }
7046
906e58ca
NC		 7047 /* Build the stubs as directed by the stub hash table. */
7048 table = &htab->stub_hash_table;
7049 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7050 if (htab->fix_cortex_a8)
7051 {
7052 /* Place the cortex a8 stubs last. */
7053 htab->fix_cortex_a8 = -1;
7054 bfd_hash_traverse (table, arm_build_one_stub, info);
7055 }
252b5132 7056
906e58ca 7057 return TRUE;
252b5132
RH		 7058}
7059
9b485d32
NC		 7060/* Locate the Thumb encoded calling stub for NAME. */
7061
252b5132 7062static struct elf_link_hash_entry *
57e8b36a
NC		 7063find_thumb_glue (struct bfd_link_info *link_info,
7064 const char *name,
f2a9dd69 7065 char **error_message)
252b5132
RH		 7066{
7067 char *tmp_name;
7068 struct elf_link_hash_entry *hash;
7069 struct elf32_arm_link_hash_table *hash_table;
7070
7071 /* We need a pointer to the armelf specific hash table. */
7072 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7073 if (hash_table == NULL)
7074 return NULL;
252b5132 7075
21d799b5 7076 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7077 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7078
7079 BFD_ASSERT (tmp_name);
7080
7081 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7082
7083 hash = elf_link_hash_lookup
b34976b6 7084 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7085
b1657152 7086 if (hash == NULL
90b6238f
AM		 7087 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7088 "Thumb", tmp_name, name) == -1)
b1657152 7089 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7090
7091 free (tmp_name);
7092
7093 return hash;
7094}
7095
9b485d32
NC		 7096/* Locate the ARM encoded calling stub for NAME. */
7097
252b5132 7098static struct elf_link_hash_entry *
57e8b36a
NC		 7099find_arm_glue (struct bfd_link_info *link_info,
7100 const char *name,
f2a9dd69 7101 char **error_message)
252b5132
RH		 7102{
7103 char *tmp_name;
7104 struct elf_link_hash_entry *myh;
7105 struct elf32_arm_link_hash_table *hash_table;
7106
7107 /* We need a pointer to the elfarm specific hash table. */
7108 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7109 if (hash_table == NULL)
7110 return NULL;
252b5132 7111
21d799b5 7112 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7113 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7114
7115 BFD_ASSERT (tmp_name);
7116
7117 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7118
7119 myh = elf_link_hash_lookup
b34976b6 7120 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7121
b1657152 7122 if (myh == NULL
90b6238f
AM		 7123 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7124 "ARM", tmp_name, name) == -1)
b1657152 7125 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7126
7127 free (tmp_name);
7128
7129 return myh;
7130}
7131
8f6277f5 7132/* ARM->Thumb glue (static images):
252b5132
RH		 7133
7134 .arm
7135 __func_from_arm:
7136 ldr r12, __func_addr
7137 bx r12
7138 __func_addr:
906e58ca 7139 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7140
26079076
PB		 7141 (v5t static images)
7142 .arm
7143 __func_from_arm:
7144 ldr pc, __func_addr
7145 __func_addr:
906e58ca 7146 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7147
8f6277f5
PB		 7148 (relocatable images)
7149 .arm
7150 __func_from_arm:
7151 ldr r12, __func_offset
7152 add r12, r12, pc
7153 bx r12
7154 __func_offset:
8029a119 7155 .word func - . */
8f6277f5
PB		 7156
7157#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7158static const insn32 a2t1_ldr_insn = 0xe59fc000;
7159static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7160static const insn32 a2t3_func_addr_insn = 0x00000001;
7161
26079076
PB		 7162#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7163static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7164static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7165
8f6277f5
PB		 7166#define ARM2THUMB_PIC_GLUE_SIZE 16
7167static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7168static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7169static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7170
07d6d2b8 7171/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7172
07d6d2b8
AM		 7173 .thumb .thumb
7174 .align 2 .align 2
7175 __func_from_thumb: __func_from_thumb:
7176 bx pc push {r6, lr}
7177 nop ldr r6, __func_addr
7178 .arm mov lr, pc
7179 b func bx r6
99059e56
RM		 7180 .arm
7181 ;; back_to_thumb
7182 ldmia r13! {r6, lr}
7183 bx lr
7184 __func_addr:
07d6d2b8 7185 .word func */
252b5132
RH		 7186
7187#define THUMB2ARM_GLUE_SIZE 8
7188static const insn16 t2a1_bx_pc_insn = 0x4778;
7189static const insn16 t2a2_noop_insn = 0x46c0;
7190static const insn32 t2a3_b_insn = 0xea000000;
7191
c7b8f16e 7192#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7193#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7194#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7195
845b51d6
PB		 7196#define ARM_BX_VENEER_SIZE 12
7197static const insn32 armbx1_tst_insn = 0xe3100001;
7198static const insn32 armbx2_moveq_insn = 0x01a0f000;
7199static const insn32 armbx3_bx_insn = 0xe12fff10;
7200
7e392df6 7201#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7202static void
7203arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7204{
7205 asection * s;
8029a119 7206 bfd_byte * contents;
252b5132 7207
8029a119 7208 if (size == 0)
3e6b1042
DJ		 7209 {
7210 /* Do not include empty glue sections in the output. */
7211 if (abfd != NULL)
7212 {
3d4d4302 7213 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7214 if (s != NULL)
7215 s->flags |= SEC_EXCLUDE;
7216 }
7217 return;
7218 }
252b5132 7219
8029a119 7220 BFD_ASSERT (abfd != NULL);
252b5132 7221
3d4d4302 7222 s = bfd_get_linker_section (abfd, name);
8029a119 7223 BFD_ASSERT (s != NULL);
252b5132 7224
21d799b5 7225 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 7226
8029a119
NC		 7227 BFD_ASSERT (s->size == size);
7228 s->contents = contents;
7229}
906e58ca 7230
8029a119
NC		 7231bfd_boolean
7232bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7233{
7234 struct elf32_arm_link_hash_table * globals;
906e58ca 7235
8029a119
NC		 7236 globals = elf32_arm_hash_table (info);
7237 BFD_ASSERT (globals != NULL);
906e58ca 7238
8029a119
NC		 7239 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7240 globals->arm_glue_size,
7241 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7242
8029a119
NC		 7243 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7244 globals->thumb_glue_size,
7245 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7246
8029a119
NC		 7247 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7248 globals->vfp11_erratum_glue_size,
7249 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7250
a504d23a
LA		 7251 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7252 globals->stm32l4xx_erratum_glue_size,
7253 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7254
8029a119
NC		 7255 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7256 globals->bx_glue_size,
845b51d6
PB		 7257 ARM_BX_GLUE_SECTION_NAME);
7258
b34976b6 7259 return TRUE;
252b5132
RH		 7260}
7261
a4fd1a8e 7262/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7263 returns the symbol identifying the stub. */
7264
a4fd1a8e 7265static struct elf_link_hash_entry *
57e8b36a
NC		 7266record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7267 struct elf_link_hash_entry * h)
252b5132
RH		 7268{
7269 const char * name = h->root.root.string;
63b0f745 7270 asection * s;
252b5132
RH		 7271 char * tmp_name;
7272 struct elf_link_hash_entry * myh;
14a793b2 7273 struct bfd_link_hash_entry * bh;
252b5132 7274 struct elf32_arm_link_hash_table * globals;
dc810e39 7275 bfd_vma val;
2f475487 7276 bfd_size_type size;
252b5132
RH		 7277
7278 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7279 BFD_ASSERT (globals != NULL);
7280 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7281
3d4d4302 7282 s = bfd_get_linker_section
252b5132
RH		 7283 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7284
252b5132
RH		 7285 BFD_ASSERT (s != NULL);
7286
21d799b5 7287 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7288 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7289
7290 BFD_ASSERT (tmp_name);
7291
7292 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7293
7294 myh = elf_link_hash_lookup
b34976b6 7295 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7296
7297 if (myh != NULL)
7298 {
9b485d32 7299 /* We've already seen this guy. */
252b5132 7300 free (tmp_name);
a4fd1a8e 7301 return myh;
252b5132
RH		 7302 }
7303
57e8b36a
NC		 7304 /* The only trick here is using hash_table->arm_glue_size as the value.
7305 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7306 putting it. The +1 on the value marks that the stub has not been
7307 output yet - not that it is a Thumb function. */
14a793b2 7308 bh = NULL;
dc810e39
AM		 7309 val = globals->arm_glue_size + 1;
7310 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7311 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7312 NULL, TRUE, FALSE, &bh);
252b5132 7313
b7693d02
DJ		 7314 myh = (struct elf_link_hash_entry *) bh;
7315 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7316 myh->forced_local = 1;
7317
252b5132
RH		 7318 free (tmp_name);
7319
0e1862bb
L		 7320 if (bfd_link_pic (link_info)
7321 || globals->root.is_relocatable_executable
27e55c4d 7322 || globals->pic_veneer)
2f475487 7323 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7324 else if (globals->use_blx)
7325 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7326 else
2f475487
AM		 7327 size = ARM2THUMB_STATIC_GLUE_SIZE;
7328
7329 s->size += size;
7330 globals->arm_glue_size += size;
252b5132 7331
a4fd1a8e 7332 return myh;
252b5132
RH		 7333}
7334
845b51d6
PB		 7335/* Allocate space for ARMv4 BX veneers. */
7336
7337static void
7338record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7339{
7340 asection * s;
7341 struct elf32_arm_link_hash_table *globals;
7342 char *tmp_name;
7343 struct elf_link_hash_entry *myh;
7344 struct bfd_link_hash_entry *bh;
7345 bfd_vma val;
7346
7347 /* BX PC does not need a veneer. */
7348 if (reg == 15)
7349 return;
7350
7351 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7352 BFD_ASSERT (globals != NULL);
7353 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7354
7355 /* Check if this veneer has already been allocated. */
7356 if (globals->bx_glue_offset[reg])
7357 return;
7358
3d4d4302 7359 s = bfd_get_linker_section
845b51d6
PB		 7360 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7361
7362 BFD_ASSERT (s != NULL);
7363
7364 /* Add symbol for veneer. */
21d799b5
NC		 7365 tmp_name = (char *)
7366 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7367
845b51d6 7368 BFD_ASSERT (tmp_name);
906e58ca 7369
845b51d6 7370 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7371
845b51d6
PB		 7372 myh = elf_link_hash_lookup
7373 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7374
845b51d6 7375 BFD_ASSERT (myh == NULL);
906e58ca 7376
845b51d6
PB		 7377 bh = NULL;
7378 val = globals->bx_glue_size;
7379 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7380 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7381 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7382
7383 myh = (struct elf_link_hash_entry *) bh;
7384 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7385 myh->forced_local = 1;
7386
7387 s->size += ARM_BX_VENEER_SIZE;
7388 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7389 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7390}
7391
7392
c7b8f16e
JB		 7393/* Add an entry to the code/data map for section SEC. */
7394
7395static void
7396elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7397{
7398 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7399 unsigned int newidx;
906e58ca 7400
c7b8f16e
JB		 7401 if (sec_data->map == NULL)
7402 {
21d799b5 7403 sec_data->map = (elf32_arm_section_map *)
99059e56 7404 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7405 sec_data->mapcount = 0;
7406 sec_data->mapsize = 1;
7407 }
906e58ca 7408
c7b8f16e 7409 newidx = sec_data->mapcount++;
906e58ca 7410
c7b8f16e
JB		 7411 if (sec_data->mapcount > sec_data->mapsize)
7412 {
7413 sec_data->mapsize *= 2;
21d799b5 7414 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7415 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7416 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7417 }
7418
7419 if (sec_data->map)
7420 {
7421 sec_data->map[newidx].vma = vma;
7422 sec_data->map[newidx].type = type;
c7b8f16e 7423 }
c7b8f16e
JB		 7424}
7425
7426
7427/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7428 veneers are handled for now. */
7429
7430static bfd_vma
7431record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7432 elf32_vfp11_erratum_list *branch,
7433 bfd *branch_bfd,
7434 asection *branch_sec,
7435 unsigned int offset)
c7b8f16e
JB		 7436{
7437 asection *s;
7438 struct elf32_arm_link_hash_table *hash_table;
7439 char *tmp_name;
7440 struct elf_link_hash_entry *myh;
7441 struct bfd_link_hash_entry *bh;
7442 bfd_vma val;
7443 struct _arm_elf_section_data *sec_data;
c7b8f16e 7444 elf32_vfp11_erratum_list *newerr;
906e58ca 7445
c7b8f16e 7446 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7447 BFD_ASSERT (hash_table != NULL);
7448 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7449
3d4d4302 7450 s = bfd_get_linker_section
c7b8f16e 7451 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7452
c7b8f16e 7453 sec_data = elf32_arm_section_data (s);
906e58ca 7454
c7b8f16e 7455 BFD_ASSERT (s != NULL);
906e58ca 7456
21d799b5 7457 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7458 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7459
c7b8f16e 7460 BFD_ASSERT (tmp_name);
906e58ca 7461
c7b8f16e
JB		 7462 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7463 hash_table->num_vfp11_fixes);
906e58ca 7464
c7b8f16e
JB		 7465 myh = elf_link_hash_lookup
7466 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7467
c7b8f16e 7468 BFD_ASSERT (myh == NULL);
906e58ca 7469
c7b8f16e
JB		 7470 bh = NULL;
7471 val = hash_table->vfp11_erratum_glue_size;
7472 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7473 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7474 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7475
7476 myh = (struct elf_link_hash_entry *) bh;
7477 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7478 myh->forced_local = 1;
7479
7480 /* Link veneer back to calling location. */
c7e2358a 7481 sec_data->erratumcount += 1;
21d799b5
NC		 7482 newerr = (elf32_vfp11_erratum_list *)
7483 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7484
c7b8f16e
JB		 7485 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7486 newerr->vma = -1;
7487 newerr->u.v.branch = branch;
7488 newerr->u.v.id = hash_table->num_vfp11_fixes;
7489 branch->u.b.veneer = newerr;
7490
7491 newerr->next = sec_data->erratumlist;
7492 sec_data->erratumlist = newerr;
7493
7494 /* A symbol for the return from the veneer. */
7495 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7496 hash_table->num_vfp11_fixes);
7497
7498 myh = elf_link_hash_lookup
7499 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7500
c7b8f16e
JB		 7501 if (myh != NULL)
7502 abort ();
7503
7504 bh = NULL;
7505 val = offset + 4;
7506 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7507 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7508
c7b8f16e
JB		 7509 myh = (struct elf_link_hash_entry *) bh;
7510 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7511 myh->forced_local = 1;
7512
7513 free (tmp_name);
906e58ca 7514
c7b8f16e
JB		 7515 /* Generate a mapping symbol for the veneer section, and explicitly add an
7516 entry for that symbol to the code/data map for the section. */
7517 if (hash_table->vfp11_erratum_glue_size == 0)
7518 {
7519 bh = NULL;
7520 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7521 ever requires this erratum fix. */
c7b8f16e
JB		 7522 _bfd_generic_link_add_one_symbol (link_info,
7523 hash_table->bfd_of_glue_owner, "$a",
7524 BSF_LOCAL, s, 0, NULL,
99059e56 7525 TRUE, FALSE, &bh);
c7b8f16e
JB		 7526
7527 myh = (struct elf_link_hash_entry *) bh;
7528 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7529 myh->forced_local = 1;
906e58ca 7530
c7b8f16e 7531 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7532 BFDs. We must make a note of this generated mapping symbol
7533 ourselves so that code byteswapping works properly in
7534 elf32_arm_write_section. */
c7b8f16e
JB		 7535 elf32_arm_section_map_add (s, 'a', 0);
7536 }
906e58ca 7537
c7b8f16e
JB		 7538 s->size += VFP11_ERRATUM_VENEER_SIZE;
7539 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7540 hash_table->num_vfp11_fixes++;
906e58ca 7541
c7b8f16e
JB		 7542 /* The offset of the veneer. */
7543 return val;
7544}
7545
a504d23a
LA		 7546/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7547 veneers need to be handled because used only in Cortex-M. */
7548
7549static bfd_vma
7550record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7551 elf32_stm32l4xx_erratum_list *branch,
7552 bfd *branch_bfd,
7553 asection *branch_sec,
7554 unsigned int offset,
7555 bfd_size_type veneer_size)
7556{
7557 asection *s;
7558 struct elf32_arm_link_hash_table *hash_table;
7559 char *tmp_name;
7560 struct elf_link_hash_entry *myh;
7561 struct bfd_link_hash_entry *bh;
7562 bfd_vma val;
7563 struct _arm_elf_section_data *sec_data;
7564 elf32_stm32l4xx_erratum_list *newerr;
7565
7566 hash_table = elf32_arm_hash_table (link_info);
7567 BFD_ASSERT (hash_table != NULL);
7568 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7569
7570 s = bfd_get_linker_section
7571 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7572
7573 BFD_ASSERT (s != NULL);
7574
7575 sec_data = elf32_arm_section_data (s);
7576
7577 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7578 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7579
7580 BFD_ASSERT (tmp_name);
7581
7582 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7583 hash_table->num_stm32l4xx_fixes);
7584
7585 myh = elf_link_hash_lookup
7586 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7587
7588 BFD_ASSERT (myh == NULL);
7589
7590 bh = NULL;
7591 val = hash_table->stm32l4xx_erratum_glue_size;
7592 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7593 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7594 NULL, TRUE, FALSE, &bh);
7595
7596 myh = (struct elf_link_hash_entry *) bh;
7597 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7598 myh->forced_local = 1;
7599
7600 /* Link veneer back to calling location. */
7601 sec_data->stm32l4xx_erratumcount += 1;
7602 newerr = (elf32_stm32l4xx_erratum_list *)
7603 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7604
7605 newerr->type = STM32L4XX_ERRATUM_VENEER;
7606 newerr->vma = -1;
7607 newerr->u.v.branch = branch;
7608 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7609 branch->u.b.veneer = newerr;
7610
7611 newerr->next = sec_data->stm32l4xx_erratumlist;
7612 sec_data->stm32l4xx_erratumlist = newerr;
7613
7614 /* A symbol for the return from the veneer. */
7615 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7616 hash_table->num_stm32l4xx_fixes);
7617
7618 myh = elf_link_hash_lookup
7619 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7620
7621 if (myh != NULL)
7622 abort ();
7623
7624 bh = NULL;
7625 val = offset + 4;
7626 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7627 branch_sec, val, NULL, TRUE, FALSE, &bh);
7628
7629 myh = (struct elf_link_hash_entry *) bh;
7630 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7631 myh->forced_local = 1;
7632
7633 free (tmp_name);
7634
7635 /* Generate a mapping symbol for the veneer section, and explicitly add an
7636 entry for that symbol to the code/data map for the section. */
7637 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7638 {
7639 bh = NULL;
7640 /* Creates a THUMB symbol since there is no other choice. */
7641 _bfd_generic_link_add_one_symbol (link_info,
7642 hash_table->bfd_of_glue_owner, "$t",
7643 BSF_LOCAL, s, 0, NULL,
7644 TRUE, FALSE, &bh);
7645
7646 myh = (struct elf_link_hash_entry *) bh;
7647 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7648 myh->forced_local = 1;
7649
7650 /* The elf32_arm_init_maps function only cares about symbols from input
7651 BFDs. We must make a note of this generated mapping symbol
7652 ourselves so that code byteswapping works properly in
7653 elf32_arm_write_section. */
7654 elf32_arm_section_map_add (s, 't', 0);
7655 }
7656
7657 s->size += veneer_size;
7658 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7659 hash_table->num_stm32l4xx_fixes++;
7660
7661 /* The offset of the veneer. */
7662 return val;
7663}
7664
8029a119 7665#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7666 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7667 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7668
7669/* Create a fake section for use by the ARM backend of the linker. */
7670
7671static bfd_boolean
7672arm_make_glue_section (bfd * abfd, const char * name)
7673{
7674 asection * sec;
7675
3d4d4302 7676 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7677 if (sec != NULL)
7678 /* Already made. */
7679 return TRUE;
7680
3d4d4302 7681 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7682
7683 if (sec == NULL
7684 || !bfd_set_section_alignment (abfd, sec, 2))
7685 return FALSE;
7686
7687 /* Set the gc mark to prevent the section from being removed by garbage
7688 collection, despite the fact that no relocs refer to this section. */
7689 sec->gc_mark = 1;
7690
7691 return TRUE;
7692}
7693
1db37fe6
YG		 7694/* Set size of .plt entries. This function is called from the
7695 linker scripts in ld/emultempl/{armelf}.em. */
7696
7697void
7698bfd_elf32_arm_use_long_plt (void)
7699{
7700 elf32_arm_use_long_plt_entry = TRUE;
7701}
7702
8afb0e02
NC		 7703/* Add the glue sections to ABFD. This function is called from the
7704 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7705
b34976b6 7706bfd_boolean
57e8b36a
NC		 7707bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7708 struct bfd_link_info *info)
252b5132 7709{
a504d23a
LA		 7710 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7711 bfd_boolean dostm32l4xx = globals
7712 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7713 bfd_boolean addglue;
7714
8afb0e02
NC		 7715 /* If we are only performing a partial
7716 link do not bother adding the glue. */
0e1862bb 7717 if (bfd_link_relocatable (info))
b34976b6 7718 return TRUE;
252b5132 7719
a504d23a 7720 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7721 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7722 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7723 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7724
7725 if (!dostm32l4xx)
7726 return addglue;
7727
7728 return addglue
7729 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7730}
7731
daa4adae
TP		 7732/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7733 ensures they are not marked for deletion by
7734 strip_excluded_output_sections () when veneers are going to be created
7735 later. Not doing so would trigger assert on empty section size in
7736 lang_size_sections_1 (). */
7737
7738void
7739bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7740{
7741 enum elf32_arm_stub_type stub_type;
7742
7743 /* If we are only performing a partial
7744 link do not bother adding the glue. */
7745 if (bfd_link_relocatable (info))
7746 return;
7747
7748 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7749 {
7750 asection *out_sec;
7751 const char *out_sec_name;
7752
7753 if (!arm_dedicated_stub_output_section_required (stub_type))
7754 continue;
7755
7756 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7757 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7758 if (out_sec != NULL)
7759 out_sec->flags |= SEC_KEEP;
7760 }
7761}
7762
8afb0e02
NC		 7763/* Select a BFD to be used to hold the sections used by the glue code.
7764 This function is called from the linker scripts in ld/emultempl/
8029a119 7765 {armelf/pe}.em. */
8afb0e02 7766
b34976b6 7767bfd_boolean
57e8b36a 7768bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7769{
7770 struct elf32_arm_link_hash_table *globals;
7771
7772 /* If we are only performing a partial link
7773 do not bother getting a bfd to hold the glue. */
0e1862bb 7774 if (bfd_link_relocatable (info))
b34976b6 7775 return TRUE;
8afb0e02 7776
b7693d02
DJ		 7777 /* Make sure we don't attach the glue sections to a dynamic object. */
7778 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7779
8afb0e02 7780 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7781 BFD_ASSERT (globals != NULL);
7782
7783 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7784 return TRUE;
8afb0e02 7785
252b5132
RH		 7786 /* Save the bfd for later use. */
7787 globals->bfd_of_glue_owner = abfd;
cedb70c5 7788
b34976b6 7789 return TRUE;
252b5132
RH		 7790}
7791
906e58ca
NC		 7792static void
7793check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7794{
2de70689
MGD		 7795 int cpu_arch;
7796
b38cadfb 7797 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7798 Tag_CPU_arch);
7799
7800 if (globals->fix_arm1176)
7801 {
7802 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7803 globals->use_blx = 1;
7804 }
7805 else
7806 {
7807 if (cpu_arch > TAG_CPU_ARCH_V4T)
7808 globals->use_blx = 1;
7809 }
39b41c9c
PB		 7810}
7811
b34976b6 7812bfd_boolean
57e8b36a 7813bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7814 struct bfd_link_info *link_info)
252b5132
RH		 7815{
7816 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7817 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7818 Elf_Internal_Rela *irel, *irelend;
7819 bfd_byte *contents = NULL;
252b5132
RH		 7820
7821 asection *sec;
7822 struct elf32_arm_link_hash_table *globals;
7823
7824 /* If we are only performing a partial link do not bother
7825 to construct any glue. */
0e1862bb 7826 if (bfd_link_relocatable (link_info))
b34976b6 7827 return TRUE;
252b5132 7828
39ce1a6a
NC		 7829 /* Here we have a bfd that is to be included on the link. We have a
7830 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7831 globals = elf32_arm_hash_table (link_info);
252b5132 7832 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7833
7834 check_use_blx (globals);
252b5132 7835
d504ffc8 7836 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7837 {
90b6238f 7838 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7839 abfd);
e489d0ae
PB		 7840 return FALSE;
7841 }
f21f3fe0 7842
39ce1a6a
NC		 7843 /* PR 5398: If we have not decided to include any loadable sections in
7844 the output then we will not have a glue owner bfd. This is OK, it
7845 just means that there is nothing else for us to do here. */
7846 if (globals->bfd_of_glue_owner == NULL)
7847 return TRUE;
7848
252b5132
RH		 7849 /* Rummage around all the relocs and map the glue vectors. */
7850 sec = abfd->sections;
7851
7852 if (sec == NULL)
b34976b6 7853 return TRUE;
252b5132
RH		 7854
7855 for (; sec != NULL; sec = sec->next)
7856 {
7857 if (sec->reloc_count == 0)
7858 continue;
7859
2f475487
AM		 7860 if ((sec->flags & SEC_EXCLUDE) != 0)
7861 continue;
7862
0ffa91dd 7863 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7864
9b485d32 7865 /* Load the relocs. */
6cdc0ccc 7866 internal_relocs
906e58ca 7867 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7868
6cdc0ccc
AM		 7869 if (internal_relocs == NULL)
7870 goto error_return;
252b5132 7871
6cdc0ccc
AM		 7872 irelend = internal_relocs + sec->reloc_count;
7873 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7874 {
7875 long r_type;
7876 unsigned long r_index;
252b5132
RH		 7877
7878 struct elf_link_hash_entry *h;
7879
7880 r_type = ELF32_R_TYPE (irel->r_info);
7881 r_index = ELF32_R_SYM (irel->r_info);
7882
9b485d32 7883 /* These are the only relocation types we care about. */
ba96a88f 7884 if ( r_type != R_ARM_PC24
845b51d6 7885 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7886 continue;
7887
7888 /* Get the section contents if we haven't done so already. */
7889 if (contents == NULL)
7890 {
7891 /* Get cached copy if it exists. */
7892 if (elf_section_data (sec)->this_hdr.contents != NULL)
7893 contents = elf_section_data (sec)->this_hdr.contents;
7894 else
7895 {
7896 /* Go get them off disk. */
57e8b36a 7897 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7898 goto error_return;
7899 }
7900 }
7901
845b51d6
PB		 7902 if (r_type == R_ARM_V4BX)
7903 {
7904 int reg;
7905
7906 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7907 record_arm_bx_glue (link_info, reg);
7908 continue;
7909 }
7910
a7c10850 7911 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7912 h = NULL;
7913
9b485d32 7914 /* We don't care about local symbols. */
252b5132
RH		 7915 if (r_index < symtab_hdr->sh_info)
7916 continue;
7917
9b485d32 7918 /* This is an external symbol. */
252b5132
RH		 7919 r_index -= symtab_hdr->sh_info;
7920 h = (struct elf_link_hash_entry *)
7921 elf_sym_hashes (abfd)[r_index];
7922
7923 /* If the relocation is against a static symbol it must be within
7924 the current section and so cannot be a cross ARM/Thumb relocation. */
7925 if (h == NULL)
7926 continue;
7927
d504ffc8
DJ		 7928 /* If the call will go through a PLT entry then we do not need
7929 glue. */
362d30a1 7930 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7931 continue;
7932
252b5132
RH		 7933 switch (r_type)
7934 {
7935 case R_ARM_PC24:
7936 /* This one is a call from arm code. We need to look up
99059e56
RM		 7937 the target of the call. If it is a thumb target, we
7938 insert glue. */
39d911fc
TP		 7939 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7940 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7941 record_arm_to_thumb_glue (link_info, h);
7942 break;
7943
252b5132 7944 default:
c6596c5e 7945 abort ();
252b5132
RH		 7946 }
7947 }
6cdc0ccc
AM		 7948
7949 if (contents != NULL
7950 && elf_section_data (sec)->this_hdr.contents != contents)
7951 free (contents);
7952 contents = NULL;
7953
7954 if (internal_relocs != NULL
7955 && elf_section_data (sec)->relocs != internal_relocs)
7956 free (internal_relocs);
7957 internal_relocs = NULL;
252b5132
RH		 7958 }
7959
b34976b6 7960 return TRUE;
9a5aca8c 7961
252b5132 7962error_return:
6cdc0ccc
AM		 7963 if (contents != NULL
7964 && elf_section_data (sec)->this_hdr.contents != contents)
7965 free (contents);
7966 if (internal_relocs != NULL
7967 && elf_section_data (sec)->relocs != internal_relocs)
7968 free (internal_relocs);
9a5aca8c 7969
b34976b6 7970 return FALSE;
252b5132 7971}
7e392df6 7972#endif
252b5132 7973
eb043451 7974
c7b8f16e
JB		 7975/* Initialise maps of ARM/Thumb/data for input BFDs. */
7976
7977void
7978bfd_elf32_arm_init_maps (bfd *abfd)
7979{
7980 Elf_Internal_Sym *isymbuf;
7981 Elf_Internal_Shdr *hdr;
7982 unsigned int i, localsyms;
7983
af1f4419
NC		 7984 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7985 if (! is_arm_elf (abfd))
7986 return;
7987
c7b8f16e
JB		 7988 if ((abfd->flags & DYNAMIC) != 0)
7989 return;
7990
0ffa91dd 7991 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7992 localsyms = hdr->sh_info;
7993
7994 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7995 should contain the number of local symbols, which should come before any
7996 global symbols. Mapping symbols are always local. */
7997 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7998 NULL);
7999
8000 /* No internal symbols read? Skip this BFD. */
8001 if (isymbuf == NULL)
8002 return;
8003
8004 for (i = 0; i < localsyms; i++)
8005 {
8006 Elf_Internal_Sym *isym = &isymbuf[i];
8007 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
8008 const char *name;
906e58ca 8009
c7b8f16e 8010 if (sec != NULL
99059e56
RM		 8011 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8012 {
8013 name = bfd_elf_string_from_elf_section (abfd,
8014 hdr->sh_link, isym->st_name);
906e58ca 8015
99059e56 8016 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8017 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8018 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8019 }
c7b8f16e
JB		 8020 }
8021}
8022
8023
48229727
JB		 8024/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8025 say what they wanted. */
8026
8027void
8028bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8029{
8030 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8031 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8032
4dfe6ac6
NC		 8033 if (globals == NULL)
8034 return;
8035
48229727
JB		 8036 if (globals->fix_cortex_a8 == -1)
8037 {
8038 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8039 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8040 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8041 || out_attr[Tag_CPU_arch_profile].i == 0))
8042 globals->fix_cortex_a8 = 1;
8043 else
8044 globals->fix_cortex_a8 = 0;
8045 }
8046}
8047
8048
c7b8f16e
JB		 8049void
8050bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8051{
8052 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8053 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8054
4dfe6ac6
NC		 8055 if (globals == NULL)
8056 return;
c7b8f16e
JB		 8057 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8058 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8059 {
8060 switch (globals->vfp11_fix)
99059e56
RM		 8061 {
8062 case BFD_ARM_VFP11_FIX_DEFAULT:
8063 case BFD_ARM_VFP11_FIX_NONE:
8064 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8065 break;
8066
8067 default:
8068 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8069 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8070 "workaround is not necessary for target architecture"), obfd);
8071 }
c7b8f16e
JB		 8072 }
8073 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8074 /* For earlier architectures, we might need the workaround, but do not
8075 enable it by default. If users is running with broken hardware, they
8076 must enable the erratum fix explicitly. */
8077 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8078}
8079
a504d23a
LA		 8080void
8081bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8082{
8083 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8084 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8085
8086 if (globals == NULL)
8087 return;
8088
8089 /* We assume only Cortex-M4 may require the fix. */
8090 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8091 || out_attr[Tag_CPU_arch_profile].i != 'M')
8092 {
8093 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8094 /* Give a warning, but do as the user requests anyway. */
4eca0228 8095 _bfd_error_handler
871b3ab2 8096 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8097 "workaround is not necessary for target architecture"), obfd);
8098 }
8099}
c7b8f16e 8100
906e58ca
NC		 8101enum bfd_arm_vfp11_pipe
8102{
c7b8f16e
JB		 8103 VFP11_FMAC,
8104 VFP11_LS,
8105 VFP11_DS,
8106 VFP11_BAD
8107};
8108
8109/* Return a VFP register number. This is encoded as RX:X for single-precision
8110 registers, or X:RX for double-precision registers, where RX is the group of
8111 four bits in the instruction encoding and X is the single extension bit.
8112 RX and X fields are specified using their lowest (starting) bit. The return
8113 value is:
8114
8115 0...31: single-precision registers s0...s31
8116 32...63: double-precision registers d0...d31.
906e58ca 8117
c7b8f16e
JB		 8118 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8119 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8120
c7b8f16e
JB		 8121static unsigned int
8122bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8123 unsigned int x)
c7b8f16e
JB		 8124{
8125 if (is_double)
8126 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8127 else
8128 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8129}
8130
8131/* Set bits in *WMASK according to a register number REG as encoded by
8132 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8133
8134static void
8135bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8136{
8137 if (reg < 32)
8138 *wmask |= 1 << reg;
8139 else if (reg < 48)
8140 *wmask |= 3 << ((reg - 32) * 2);
8141}
8142
8143/* Return TRUE if WMASK overwrites anything in REGS. */
8144
8145static bfd_boolean
8146bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8147{
8148 int i;
906e58ca 8149
c7b8f16e
JB		 8150 for (i = 0; i < numregs; i++)
8151 {
8152 unsigned int reg = regs[i];
8153
8154 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8155 return TRUE;
906e58ca 8156
c7b8f16e
JB		 8157 reg -= 32;
8158
8159 if (reg >= 16)
99059e56 8160 continue;
906e58ca 8161
c7b8f16e 8162 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8163 return TRUE;
c7b8f16e 8164 }
906e58ca 8165
c7b8f16e
JB		 8166 return FALSE;
8167}
8168
8169/* In this function, we're interested in two things: finding input registers
8170 for VFP data-processing instructions, and finding the set of registers which
8171 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8172 hold the written set, so FLDM etc. are easy to deal with (we're only
8173 interested in 32 SP registers or 16 dp registers, due to the VFP version
8174 implemented by the chip in question). DP registers are marked by setting
8175 both SP registers in the write mask). */
8176
8177static enum bfd_arm_vfp11_pipe
8178bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8179 int *numregs)
c7b8f16e 8180{
91d6fa6a 8181 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8182 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8183
8184 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8185 {
8186 unsigned int pqrs;
8187 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8188 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8189
8190 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8191 | ((insn & 0x00300000) >> 19)
8192 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8193
8194 switch (pqrs)
99059e56
RM		 8195 {
8196 case 0: /* fmac[sd]. */
8197 case 1: /* fnmac[sd]. */
8198 case 2: /* fmsc[sd]. */
8199 case 3: /* fnmsc[sd]. */
8200 vpipe = VFP11_FMAC;
8201 bfd_arm_vfp11_write_mask (destmask, fd);
8202 regs[0] = fd;
8203 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8204 regs[2] = fm;
8205 *numregs = 3;
8206 break;
8207
8208 case 4: /* fmul[sd]. */
8209 case 5: /* fnmul[sd]. */
8210 case 6: /* fadd[sd]. */
8211 case 7: /* fsub[sd]. */
8212 vpipe = VFP11_FMAC;
8213 goto vfp_binop;
8214
8215 case 8: /* fdiv[sd]. */
8216 vpipe = VFP11_DS;
8217 vfp_binop:
8218 bfd_arm_vfp11_write_mask (destmask, fd);
8219 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8220 regs[1] = fm;
8221 *numregs = 2;
8222 break;
8223
8224 case 15: /* extended opcode. */
8225 {
8226 unsigned int extn = ((insn >> 15) & 0x1e)
8227 | ((insn >> 7) & 1);
8228
8229 switch (extn)
8230 {
8231 case 0: /* fcpy[sd]. */
8232 case 1: /* fabs[sd]. */
8233 case 2: /* fneg[sd]. */
8234 case 8: /* fcmp[sd]. */
8235 case 9: /* fcmpe[sd]. */
8236 case 10: /* fcmpz[sd]. */
8237 case 11: /* fcmpez[sd]. */
8238 case 16: /* fuito[sd]. */
8239 case 17: /* fsito[sd]. */
8240 case 24: /* ftoui[sd]. */
8241 case 25: /* ftouiz[sd]. */
8242 case 26: /* ftosi[sd]. */
8243 case 27: /* ftosiz[sd]. */
8244 /* These instructions will not bounce due to underflow. */
8245 *numregs = 0;
8246 vpipe = VFP11_FMAC;
8247 break;
8248
8249 case 3: /* fsqrt[sd]. */
8250 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8251 registers to cause the erratum in previous instructions. */
8252 bfd_arm_vfp11_write_mask (destmask, fd);
8253 vpipe = VFP11_DS;
8254 break;
8255
8256 case 15: /* fcvt{ds,sd}. */
8257 {
8258 int rnum = 0;
8259
8260 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8261
8262 /* Only FCVTSD can underflow. */
99059e56
RM		 8263 if ((insn & 0x100) != 0)
8264 regs[rnum++] = fm;
c7b8f16e 8265
99059e56 8266 *numregs = rnum;
c7b8f16e 8267
99059e56
RM		 8268 vpipe = VFP11_FMAC;
8269 }
8270 break;
c7b8f16e 8271
99059e56
RM		 8272 default:
8273 return VFP11_BAD;
8274 }
8275 }
8276 break;
c7b8f16e 8277
99059e56
RM		 8278 default:
8279 return VFP11_BAD;
8280 }
c7b8f16e
JB		 8281 }
8282 /* Two-register transfer. */
8283 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8284 {
8285 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8286
c7b8f16e
JB		 8287 if ((insn & 0x100000) == 0)
8288 {
99059e56
RM		 8289 if (is_double)
8290 bfd_arm_vfp11_write_mask (destmask, fm);
8291 else
8292 {
8293 bfd_arm_vfp11_write_mask (destmask, fm);
8294 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8295 }
c7b8f16e
JB		 8296 }
8297
91d6fa6a 8298 vpipe = VFP11_LS;
c7b8f16e
JB		 8299 }
8300 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8301 {
8302 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8303 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8304
c7b8f16e 8305 switch (puw)
99059e56
RM		 8306 {
8307 case 0: /* Two-reg transfer. We should catch these above. */
8308 abort ();
906e58ca 8309
99059e56
RM		 8310 case 2: /* fldm[sdx]. */
8311 case 3:
8312 case 5:
8313 {
8314 unsigned int i, offset = insn & 0xff;
c7b8f16e 8315
99059e56
RM		 8316 if (is_double)
8317 offset >>= 1;
c7b8f16e 8318
99059e56
RM		 8319 for (i = fd; i < fd + offset; i++)
8320 bfd_arm_vfp11_write_mask (destmask, i);
8321 }
8322 break;
906e58ca 8323
99059e56
RM		 8324 case 4: /* fld[sd]. */
8325 case 6:
8326 bfd_arm_vfp11_write_mask (destmask, fd);
8327 break;
906e58ca 8328
99059e56
RM		 8329 default:
8330 return VFP11_BAD;
8331 }
c7b8f16e 8332
91d6fa6a 8333 vpipe = VFP11_LS;
c7b8f16e
JB		 8334 }
8335 /* Single-register transfer. Note L==0. */
8336 else if ((insn & 0x0f100e10) == 0x0e000a10)
8337 {
8338 unsigned int opcode = (insn >> 21) & 7;
8339 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8340
8341 switch (opcode)
99059e56
RM		 8342 {
8343 case 0: /* fmsr/fmdlr. */
8344 case 1: /* fmdhr. */
8345 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8346 destination register. I don't know if this is exactly right,
8347 but it is the conservative choice. */
8348 bfd_arm_vfp11_write_mask (destmask, fn);
8349 break;
8350
8351 case 7: /* fmxr. */
8352 break;
8353 }
c7b8f16e 8354
91d6fa6a 8355 vpipe = VFP11_LS;
c7b8f16e
JB		 8356 }
8357
91d6fa6a 8358 return vpipe;
c7b8f16e
JB		 8359}
8360
8361
8362static int elf32_arm_compare_mapping (const void * a, const void * b);
8363
8364
8365/* Look for potentially-troublesome code sequences which might trigger the
8366 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8367 (available from ARM) for details of the erratum. A short version is
8368 described in ld.texinfo. */
8369
8370bfd_boolean
8371bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8372{
8373 asection *sec;
8374 bfd_byte *contents = NULL;
8375 int state = 0;
8376 int regs[3], numregs = 0;
8377 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8378 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8379
4dfe6ac6
NC		 8380 if (globals == NULL)
8381 return FALSE;
8382
c7b8f16e
JB		 8383 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8384 The states transition as follows:
906e58ca 8385
c7b8f16e 8386 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8387 A VFP FMAC-pipeline instruction has been seen. Fill
8388 regs[0]..regs[numregs-1] with its input operands. Remember this
8389 instruction in 'first_fmac'.
c7b8f16e
JB		 8390
8391 1 -> 2
99059e56
RM		 8392 Any instruction, except for a VFP instruction which overwrites
8393 regs[*].
906e58ca 8394
c7b8f16e
JB		 8395 1 -> 3 [ -> 0 ] or
8396 2 -> 3 [ -> 0 ]
99059e56
RM		 8397 A VFP instruction has been seen which overwrites any of regs[*].
8398 We must make a veneer! Reset state to 0 before examining next
8399 instruction.
906e58ca 8400
c7b8f16e 8401 2 -> 0
99059e56
RM		 8402 If we fail to match anything in state 2, reset to state 0 and reset
8403 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8404
8405 If the VFP11 vector mode is in use, there must be at least two unrelated
8406 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8407 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8408
8409 /* If we are only performing a partial link do not bother
8410 to construct any glue. */
0e1862bb 8411 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8412 return TRUE;
8413
0ffa91dd
NC		 8414 /* Skip if this bfd does not correspond to an ELF image. */
8415 if (! is_arm_elf (abfd))
8416 return TRUE;
906e58ca 8417
c7b8f16e
JB		 8418 /* We should have chosen a fix type by the time we get here. */
8419 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8420
8421 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8422 return TRUE;
2e6030b9 8423
33a7ffc2
JM		 8424 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8425 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8426 return TRUE;
8427
c7b8f16e
JB		 8428 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8429 {
8430 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8431 struct _arm_elf_section_data *sec_data;
8432
8433 /* If we don't have executable progbits, we're not interested in this
99059e56 8434 section. Also skip if section is to be excluded. */
c7b8f16e 8435 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8436 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8437 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8438 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8439 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8440 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8441 continue;
c7b8f16e
JB		 8442
8443 sec_data = elf32_arm_section_data (sec);
906e58ca 8444
c7b8f16e 8445 if (sec_data->mapcount == 0)
99059e56 8446 continue;
906e58ca 8447
c7b8f16e
JB		 8448 if (elf_section_data (sec)->this_hdr.contents != NULL)
8449 contents = elf_section_data (sec)->this_hdr.contents;
8450 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8451 goto error_return;
8452
8453 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8454 elf32_arm_compare_mapping);
8455
8456 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8457 {
8458 unsigned int span_start = sec_data->map[span].vma;
8459 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8460 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8461 char span_type = sec_data->map[span].type;
8462
8463 /* FIXME: Only ARM mode is supported at present. We may need to
8464 support Thumb-2 mode also at some point. */
8465 if (span_type != 'a')
8466 continue;
8467
8468 for (i = span_start; i < span_end;)
8469 {
8470 unsigned int next_i = i + 4;
8471 unsigned int insn = bfd_big_endian (abfd)
8472 ? (contents[i] << 24)
8473 | (contents[i + 1] << 16)
8474 | (contents[i + 2] << 8)
8475 | contents[i + 3]
8476 : (contents[i + 3] << 24)
8477 | (contents[i + 2] << 16)
8478 | (contents[i + 1] << 8)
8479 | contents[i];
8480 unsigned int writemask = 0;
8481 enum bfd_arm_vfp11_pipe vpipe;
8482
8483 switch (state)
8484 {
8485 case 0:
8486 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8487 &numregs);
8488 /* I'm assuming the VFP11 erratum can trigger with denorm
8489 operands on either the FMAC or the DS pipeline. This might
8490 lead to slightly overenthusiastic veneer insertion. */
8491 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8492 {
8493 state = use_vector ? 1 : 2;
8494 first_fmac = i;
8495 veneer_of_insn = insn;
8496 }
8497 break;
8498
8499 case 1:
8500 {
8501 int other_regs[3], other_numregs;
8502 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8503 other_regs,
99059e56
RM		 8504 &other_numregs);
8505 if (vpipe != VFP11_BAD
8506 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8507 numregs))
99059e56
RM		 8508 state = 3;
8509 else
8510 state = 2;
8511 }
8512 break;
8513
8514 case 2:
8515 {
8516 int other_regs[3], other_numregs;
8517 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8518 other_regs,
99059e56
RM		 8519 &other_numregs);
8520 if (vpipe != VFP11_BAD
8521 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8522 numregs))
99059e56
RM		 8523 state = 3;
8524 else
8525 {
8526 state = 0;
8527 next_i = first_fmac + 4;
8528 }
8529 }
8530 break;
8531
8532 case 3:
8533 abort (); /* Should be unreachable. */
8534 }
8535
8536 if (state == 3)
8537 {
8538 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8539 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8540
8541 elf32_arm_section_data (sec)->erratumcount += 1;
8542
8543 newerr->u.b.vfp_insn = veneer_of_insn;
8544
8545 switch (span_type)
8546 {
8547 case 'a':
8548 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8549 break;
8550
8551 default:
8552 abort ();
8553 }
8554
8555 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8556 first_fmac);
8557
99059e56 8558 newerr->vma = -1;
c7b8f16e 8559
99059e56
RM		 8560 newerr->next = sec_data->erratumlist;
8561 sec_data->erratumlist = newerr;
c7b8f16e 8562
99059e56
RM		 8563 state = 0;
8564 }
c7b8f16e 8565
99059e56
RM		 8566 i = next_i;
8567 }
8568 }
906e58ca 8569
c7b8f16e 8570 if (contents != NULL
99059e56
RM		 8571 && elf_section_data (sec)->this_hdr.contents != contents)
8572 free (contents);
c7b8f16e
JB		 8573 contents = NULL;
8574 }
8575
8576 return TRUE;
8577
8578error_return:
8579 if (contents != NULL
8580 && elf_section_data (sec)->this_hdr.contents != contents)
8581 free (contents);
906e58ca 8582
c7b8f16e
JB		 8583 return FALSE;
8584}
8585
8586/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8587 after sections have been laid out, using specially-named symbols. */
8588
8589void
8590bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8591 struct bfd_link_info *link_info)
8592{
8593 asection *sec;
8594 struct elf32_arm_link_hash_table *globals;
8595 char *tmp_name;
906e58ca 8596
0e1862bb 8597 if (bfd_link_relocatable (link_info))
c7b8f16e 8598 return;
2e6030b9
MS		 8599
8600 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8601 if (! is_arm_elf (abfd))
2e6030b9
MS		 8602 return;
8603
c7b8f16e 8604 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8605 if (globals == NULL)
8606 return;
906e58ca 8607
21d799b5 8608 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8609 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8610
8611 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8612 {
8613 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8614 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8615
c7b8f16e 8616 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8617 {
8618 struct elf_link_hash_entry *myh;
8619 bfd_vma vma;
8620
8621 switch (errnode->type)
8622 {
8623 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8624 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8625 /* Find veneer symbol. */
8626 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8627 errnode->u.b.veneer->u.v.id);
8628
99059e56
RM		 8629 myh = elf_link_hash_lookup
8630 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8631
a504d23a 8632 if (myh == NULL)
90b6238f
AM		 8633 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8634 abfd, "VFP11", tmp_name);
a504d23a
LA		 8635
8636 vma = myh->root.u.def.section->output_section->vma
8637 + myh->root.u.def.section->output_offset
8638 + myh->root.u.def.value;
8639
8640 errnode->u.b.veneer->vma = vma;
8641 break;
8642
8643 case VFP11_ERRATUM_ARM_VENEER:
8644 case VFP11_ERRATUM_THUMB_VENEER:
8645 /* Find return location. */
8646 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8647 errnode->u.v.id);
8648
8649 myh = elf_link_hash_lookup
8650 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8651
8652 if (myh == NULL)
90b6238f
AM		 8653 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8654 abfd, "VFP11", tmp_name);
a504d23a
LA		 8655
8656 vma = myh->root.u.def.section->output_section->vma
8657 + myh->root.u.def.section->output_offset
8658 + myh->root.u.def.value;
8659
8660 errnode->u.v.branch->vma = vma;
8661 break;
8662
8663 default:
8664 abort ();
8665 }
8666 }
8667 }
8668
8669 free (tmp_name);
8670}
8671
8672/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8673 return locations after sections have been laid out, using
8674 specially-named symbols. */
8675
8676void
8677bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8678 struct bfd_link_info *link_info)
8679{
8680 asection *sec;
8681 struct elf32_arm_link_hash_table *globals;
8682 char *tmp_name;
8683
8684 if (bfd_link_relocatable (link_info))
8685 return;
8686
8687 /* Skip if this bfd does not correspond to an ELF image. */
8688 if (! is_arm_elf (abfd))
8689 return;
8690
8691 globals = elf32_arm_hash_table (link_info);
8692 if (globals == NULL)
8693 return;
8694
8695 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8696 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8697
8698 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8699 {
8700 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8701 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8702
8703 for (; errnode != NULL; errnode = errnode->next)
8704 {
8705 struct elf_link_hash_entry *myh;
8706 bfd_vma vma;
8707
8708 switch (errnode->type)
8709 {
8710 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8711 /* Find veneer symbol. */
8712 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8713 errnode->u.b.veneer->u.v.id);
8714
8715 myh = elf_link_hash_lookup
8716 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8717
8718 if (myh == NULL)
90b6238f
AM		 8719 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8720 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8721
8722 vma = myh->root.u.def.section->output_section->vma
8723 + myh->root.u.def.section->output_offset
8724 + myh->root.u.def.value;
8725
8726 errnode->u.b.veneer->vma = vma;
8727 break;
8728
8729 case STM32L4XX_ERRATUM_VENEER:
8730 /* Find return location. */
8731 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8732 errnode->u.v.id);
8733
8734 myh = elf_link_hash_lookup
8735 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8736
8737 if (myh == NULL)
90b6238f
AM		 8738 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8739 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8740
8741 vma = myh->root.u.def.section->output_section->vma
8742 + myh->root.u.def.section->output_offset
8743 + myh->root.u.def.value;
8744
8745 errnode->u.v.branch->vma = vma;
8746 break;
8747
8748 default:
8749 abort ();
8750 }
8751 }
8752 }
8753
8754 free (tmp_name);
8755}
8756
8757static inline bfd_boolean
8758is_thumb2_ldmia (const insn32 insn)
8759{
8760 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8761 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8762 return (insn & 0xffd02000) == 0xe8900000;
8763}
8764
8765static inline bfd_boolean
8766is_thumb2_ldmdb (const insn32 insn)
8767{
8768 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8769 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8770 return (insn & 0xffd02000) == 0xe9100000;
8771}
8772
8773static inline bfd_boolean
8774is_thumb2_vldm (const insn32 insn)
8775{
8776 /* A6.5 Extension register load or store instruction
8777 A7.7.229
9239bbd3
CM		 8778 We look for SP 32-bit and DP 64-bit registers.
8779 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8780 <list> is consecutive 64-bit registers
8781 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8782 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8783 <list> is consecutive 32-bit registers
8784 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8785 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8786 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8787 return
9239bbd3
CM		 8788 (((insn & 0xfe100f00) == 0xec100b00) ||
8789 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8790 && /* (IA without !). */
8791 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8792 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8793 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8794 /* (DB with !). */
8795 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8796}
8797
8798/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8799 VLDM opcode and:
8800 - computes the number and the mode of memory accesses
8801 - decides if the replacement should be done:
8802 . replaces only if > 8-word accesses
8803 . or (testing purposes only) replaces all accesses. */
8804
8805static bfd_boolean
8806stm32l4xx_need_create_replacing_stub (const insn32 insn,
8807 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8808{
9239bbd3 8809 int nb_words = 0;
a504d23a
LA		 8810
8811 /* The field encoding the register list is the same for both LDMIA
8812 and LDMDB encodings. */
8813 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8814 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8815 else if (is_thumb2_vldm (insn))
9239bbd3 8816 nb_words = (insn & 0xff);
a504d23a
LA		 8817
8818 /* DEFAULT mode accounts for the real bug condition situation,
8819 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8820 return
9239bbd3 8821 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8822 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8823}
8824
8825/* Look for potentially-troublesome code sequences which might trigger
8826 the STM STM32L4XX erratum. */
8827
8828bfd_boolean
8829bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8830 struct bfd_link_info *link_info)
8831{
8832 asection *sec;
8833 bfd_byte *contents = NULL;
8834 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8835
8836 if (globals == NULL)
8837 return FALSE;
8838
8839 /* If we are only performing a partial link do not bother
8840 to construct any glue. */
8841 if (bfd_link_relocatable (link_info))
8842 return TRUE;
8843
8844 /* Skip if this bfd does not correspond to an ELF image. */
8845 if (! is_arm_elf (abfd))
8846 return TRUE;
8847
8848 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8849 return TRUE;
8850
8851 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8852 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8853 return TRUE;
8854
8855 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8856 {
8857 unsigned int i, span;
8858 struct _arm_elf_section_data *sec_data;
8859
8860 /* If we don't have executable progbits, we're not interested in this
8861 section. Also skip if section is to be excluded. */
8862 if (elf_section_type (sec) != SHT_PROGBITS
8863 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8864 || (sec->flags & SEC_EXCLUDE) != 0
8865 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8866 || sec->output_section == bfd_abs_section_ptr
8867 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8868 continue;
8869
8870 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8871
a504d23a
LA		 8872 if (sec_data->mapcount == 0)
8873 continue;
c7b8f16e 8874
a504d23a
LA		 8875 if (elf_section_data (sec)->this_hdr.contents != NULL)
8876 contents = elf_section_data (sec)->this_hdr.contents;
8877 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8878 goto error_return;
c7b8f16e 8879
a504d23a
LA		 8880 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8881 elf32_arm_compare_mapping);
c7b8f16e 8882
a504d23a
LA		 8883 for (span = 0; span < sec_data->mapcount; span++)
8884 {
8885 unsigned int span_start = sec_data->map[span].vma;
8886 unsigned int span_end = (span == sec_data->mapcount - 1)
8887 ? sec->size : sec_data->map[span + 1].vma;
8888 char span_type = sec_data->map[span].type;
8889 int itblock_current_pos = 0;
c7b8f16e 8890
a504d23a
LA		 8891 /* Only Thumb2 mode need be supported with this CM4 specific
8892 code, we should not encounter any arm mode eg span_type
8893 != 'a'. */
8894 if (span_type != 't')
8895 continue;
c7b8f16e 8896
a504d23a
LA		 8897 for (i = span_start; i < span_end;)
8898 {
8899 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8900 bfd_boolean insn_32bit = FALSE;
8901 bfd_boolean is_ldm = FALSE;
8902 bfd_boolean is_vldm = FALSE;
8903 bfd_boolean is_not_last_in_it_block = FALSE;
8904
8905 /* The first 16-bits of all 32-bit thumb2 instructions start
8906 with opcode[15..13]=0b111 and the encoded op1 can be anything
8907 except opcode[12..11]!=0b00.
8908 See 32-bit Thumb instruction encoding. */
8909 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8910 insn_32bit = TRUE;
c7b8f16e 8911
a504d23a
LA		 8912 /* Compute the predicate that tells if the instruction
8913 is concerned by the IT block
8914 - Creates an error if there is a ldm that is not
8915 last in the IT block thus cannot be replaced
8916 - Otherwise we can create a branch at the end of the
8917 IT block, it will be controlled naturally by IT
8918 with the proper pseudo-predicate
8919 - So the only interesting predicate is the one that
8920 tells that we are not on the last item of an IT
8921 block. */
8922 if (itblock_current_pos != 0)
8923 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8924
a504d23a
LA		 8925 if (insn_32bit)
8926 {
8927 /* Load the rest of the insn (in manual-friendly order). */
8928 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8929 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8930 is_vldm = is_thumb2_vldm (insn);
8931
8932 /* Veneers are created for (v)ldm depending on
8933 option flags and memory accesses conditions; but
8934 if the instruction is not the last instruction of
8935 an IT block, we cannot create a jump there, so we
8936 bail out. */
5025eb7c
AO		 8937 if ((is_ldm || is_vldm)
8938 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8939 (insn, globals->stm32l4xx_fix))
8940 {
8941 if (is_not_last_in_it_block)
8942 {
4eca0228 8943 _bfd_error_handler
695344c0 8944 /* xgettext:c-format */
871b3ab2 8945 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8946 " in non-last IT block instruction:"
8947 " STM32L4XX veneer cannot be generated; "
8948 "use gcc option -mrestrict-it to generate"
8949 " only one instruction per IT block"),
d42c267e 8950 abfd, sec, i);
a504d23a
LA		 8951 }
8952 else
8953 {
8954 elf32_stm32l4xx_erratum_list *newerr =
8955 (elf32_stm32l4xx_erratum_list *)
8956 bfd_zmalloc
8957 (sizeof (elf32_stm32l4xx_erratum_list));
8958
8959 elf32_arm_section_data (sec)
8960 ->stm32l4xx_erratumcount += 1;
8961 newerr->u.b.insn = insn;
8962 /* We create only thumb branches. */
8963 newerr->type =
8964 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8965 record_stm32l4xx_erratum_veneer
8966 (link_info, newerr, abfd, sec,
8967 i,
8968 is_ldm ?
8969 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8970 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8971 newerr->vma = -1;
8972 newerr->next = sec_data->stm32l4xx_erratumlist;
8973 sec_data->stm32l4xx_erratumlist = newerr;
8974 }
8975 }
8976 }
8977 else
8978 {
8979 /* A7.7.37 IT p208
8980 IT blocks are only encoded in T1
8981 Encoding T1: IT{x{y{z}}} <firstcond>
8982 1 0 1 1 - 1 1 1 1 - firstcond - mask
8983 if mask = '0000' then see 'related encodings'
8984 We don't deal with UNPREDICTABLE, just ignore these.
8985 There can be no nested IT blocks so an IT block
8986 is naturally a new one for which it is worth
8987 computing its size. */
5025eb7c
AO		 8988 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8989 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8990 /* If we have a new IT block we compute its size. */
8991 if (is_newitblock)
8992 {
8993 /* Compute the number of instructions controlled
8994 by the IT block, it will be used to decide
8995 whether we are inside an IT block or not. */
8996 unsigned int mask = insn & 0x000f;
8997 itblock_current_pos = 4 - ctz (mask);
8998 }
8999 }
9000
9001 i += insn_32bit ? 4 : 2;
99059e56
RM		 9002 }
9003 }
a504d23a
LA		 9004
9005 if (contents != NULL
9006 && elf_section_data (sec)->this_hdr.contents != contents)
9007 free (contents);
9008 contents = NULL;
c7b8f16e 9009 }
906e58ca 9010
a504d23a
LA		 9011 return TRUE;
9012
9013error_return:
9014 if (contents != NULL
9015 && elf_section_data (sec)->this_hdr.contents != contents)
9016 free (contents);
c7b8f16e 9017
a504d23a
LA		 9018 return FALSE;
9019}
c7b8f16e 9020
eb043451
PB		 9021/* Set target relocation values needed during linking. */
9022
9023void
68c39892 9024bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9025 struct bfd_link_info *link_info,
68c39892 9026 struct elf32_arm_params *params)
eb043451
PB		 9027{
9028 struct elf32_arm_link_hash_table *globals;
9029
9030 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9031 if (globals == NULL)
9032 return;
eb043451 9033
68c39892 9034 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9035 if (globals->fdpic_p)
9036 globals->target2_reloc = R_ARM_GOT32;
9037 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9038 globals->target2_reloc = R_ARM_REL32;
68c39892 9039 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9040 globals->target2_reloc = R_ARM_ABS32;
68c39892 9041 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9042 globals->target2_reloc = R_ARM_GOT_PREL;
9043 else
9044 {
90b6238f 9045 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9046 params->target2_type);
eb043451 9047 }
68c39892
TP		 9048 globals->fix_v4bx = params->fix_v4bx;
9049 globals->use_blx |= params->use_blx;
9050 globals->vfp11_fix = params->vfp11_denorm_fix;
9051 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9052 if (globals->fdpic_p)
9053 globals->pic_veneer = 1;
9054 else
9055 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9056 globals->fix_cortex_a8 = params->fix_cortex_a8;
9057 globals->fix_arm1176 = params->fix_arm1176;
9058 globals->cmse_implib = params->cmse_implib;
9059 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9060
0ffa91dd 9061 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9062 elf_arm_tdata (output_bfd)->no_enum_size_warning
9063 = params->no_enum_size_warning;
9064 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9065 = params->no_wchar_size_warning;
eb043451 9066}
eb043451 9067
12a0a0fd 9068/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9069
12a0a0fd
PB		 9070static void
9071insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9072{
9073 bfd_vma upper;
9074 bfd_vma lower;
9075 int reloc_sign;
9076
9077 BFD_ASSERT ((offset & 1) == 0);
9078
9079 upper = bfd_get_16 (abfd, insn);
9080 lower = bfd_get_16 (abfd, insn + 2);
9081 reloc_sign = (offset < 0) ? 1 : 0;
9082 upper = (upper & ~(bfd_vma) 0x7ff)
9083 | ((offset >> 12) & 0x3ff)
9084 | (reloc_sign << 10);
906e58ca 9085 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9086 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9087 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9088 | ((offset >> 1) & 0x7ff);
9089 bfd_put_16 (abfd, upper, insn);
9090 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9091}
9092
9b485d32
NC		 9093/* Thumb code calling an ARM function. */
9094
252b5132 9095static int
57e8b36a 9096elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9097 const char * name,
9098 bfd * input_bfd,
9099 bfd * output_bfd,
9100 asection * input_section,
9101 bfd_byte * hit_data,
9102 asection * sym_sec,
9103 bfd_vma offset,
9104 bfd_signed_vma addend,
9105 bfd_vma val,
f2a9dd69 9106 char **error_message)
252b5132 9107{
bcbdc74c 9108 asection * s = 0;
dc810e39 9109 bfd_vma my_offset;
252b5132 9110 long int ret_offset;
bcbdc74c
NC		 9111 struct elf_link_hash_entry * myh;
9112 struct elf32_arm_link_hash_table * globals;
252b5132 9113
f2a9dd69 9114 myh = find_thumb_glue (info, name, error_message);
252b5132 9115 if (myh == NULL)
b34976b6 9116 return FALSE;
252b5132
RH		 9117
9118 globals = elf32_arm_hash_table (info);
252b5132
RH		 9119 BFD_ASSERT (globals != NULL);
9120 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9121
9122 my_offset = myh->root.u.def.value;
9123
3d4d4302
AM		 9124 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9125 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9126
9127 BFD_ASSERT (s != NULL);
9128 BFD_ASSERT (s->contents != NULL);
9129 BFD_ASSERT (s->output_section != NULL);
9130
9131 if ((my_offset & 0x01) == 0x01)
9132 {
9133 if (sym_sec != NULL
9134 && sym_sec->owner != NULL
9135 && !INTERWORK_FLAG (sym_sec->owner))
9136 {
4eca0228 9137 _bfd_error_handler
90b6238f
AM		 9138 (_("%pB(%s): warning: interworking not enabled;"
9139 " first occurrence: %pB: %s call to %s"),
9140 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9141
b34976b6 9142 return FALSE;
252b5132
RH		 9143 }
9144
9145 --my_offset;
9146 myh->root.u.def.value = my_offset;
9147
52ab56c2
PB		 9148 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9149 s->contents + my_offset);
252b5132 9150
52ab56c2
PB		 9151 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9152 s->contents + my_offset + 2);
252b5132
RH		 9153
9154 ret_offset =
9b485d32
NC		 9155 /* Address of destination of the stub. */
9156 ((bfd_signed_vma) val)
252b5132 9157 - ((bfd_signed_vma)
57e8b36a
NC		 9158 /* Offset from the start of the current section
9159 to the start of the stubs. */
9b485d32
NC		 9160 (s->output_offset
9161 /* Offset of the start of this stub from the start of the stubs. */
9162 + my_offset
9163 /* Address of the start of the current section. */
9164 + s->output_section->vma)
9165 /* The branch instruction is 4 bytes into the stub. */
9166 + 4
9167 /* ARM branches work from the pc of the instruction + 8. */
9168 + 8);
252b5132 9169
52ab56c2
PB		 9170 put_arm_insn (globals, output_bfd,
9171 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9172 s->contents + my_offset + 4);
252b5132
RH		 9173 }
9174
9175 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9176
427bfd90
NC		 9177 /* Now go back and fix up the original BL insn to point to here. */
9178 ret_offset =
9179 /* Address of where the stub is located. */
9180 (s->output_section->vma + s->output_offset + my_offset)
9181 /* Address of where the BL is located. */
57e8b36a
NC		 9182 - (input_section->output_section->vma + input_section->output_offset
9183 + offset)
427bfd90
NC		 9184 /* Addend in the relocation. */
9185 - addend
9186 /* Biassing for PC-relative addressing. */
9187 - 8;
252b5132 9188
12a0a0fd 9189 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9190
b34976b6 9191 return TRUE;
252b5132
RH		 9192}
9193
a4fd1a8e 9194/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9195
a4fd1a8e
PB		 9196static struct elf_link_hash_entry *
9197elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9198 const char * name,
9199 bfd * input_bfd,
9200 bfd * output_bfd,
9201 asection * sym_sec,
9202 bfd_vma val,
9203 asection * s,
9204 char ** error_message)
252b5132 9205{
dc810e39 9206 bfd_vma my_offset;
252b5132 9207 long int ret_offset;
bcbdc74c
NC		 9208 struct elf_link_hash_entry * myh;
9209 struct elf32_arm_link_hash_table * globals;
252b5132 9210
f2a9dd69 9211 myh = find_arm_glue (info, name, error_message);
252b5132 9212 if (myh == NULL)
a4fd1a8e 9213 return NULL;
252b5132
RH		 9214
9215 globals = elf32_arm_hash_table (info);
252b5132
RH		 9216 BFD_ASSERT (globals != NULL);
9217 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9218
9219 my_offset = myh->root.u.def.value;
252b5132
RH		 9220
9221 if ((my_offset & 0x01) == 0x01)
9222 {
9223 if (sym_sec != NULL
9224 && sym_sec->owner != NULL
9225 && !INTERWORK_FLAG (sym_sec->owner))
9226 {
4eca0228 9227 _bfd_error_handler
90b6238f
AM		 9228 (_("%pB(%s): warning: interworking not enabled;"
9229 " first occurrence: %pB: %s call to %s"),
9230 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9231 }
9b485d32 9232
252b5132
RH		 9233 --my_offset;
9234 myh->root.u.def.value = my_offset;
9235
0e1862bb
L		 9236 if (bfd_link_pic (info)
9237 || globals->root.is_relocatable_executable
27e55c4d 9238 || globals->pic_veneer)
8f6277f5
PB		 9239 {
9240 /* For relocatable objects we can't use absolute addresses,
9241 so construct the address from a relative offset. */
9242 /* TODO: If the offset is small it's probably worth
9243 constructing the address with adds. */
52ab56c2
PB		 9244 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9245 s->contents + my_offset);
9246 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9247 s->contents + my_offset + 4);
9248 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9249 s->contents + my_offset + 8);
8f6277f5
PB		 9250 /* Adjust the offset by 4 for the position of the add,
9251 and 8 for the pipeline offset. */
9252 ret_offset = (val - (s->output_offset
9253 + s->output_section->vma
9254 + my_offset + 12))
9255 | 1;
9256 bfd_put_32 (output_bfd, ret_offset,
9257 s->contents + my_offset + 12);
9258 }
26079076
PB		 9259 else if (globals->use_blx)
9260 {
9261 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9262 s->contents + my_offset);
9263
9264 /* It's a thumb address. Add the low order bit. */
9265 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9266 s->contents + my_offset + 4);
9267 }
8f6277f5
PB		 9268 else
9269 {
52ab56c2
PB		 9270 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9271 s->contents + my_offset);
252b5132 9272
52ab56c2
PB		 9273 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9274 s->contents + my_offset + 4);
252b5132 9275
8f6277f5
PB		 9276 /* It's a thumb address. Add the low order bit. */
9277 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9278 s->contents + my_offset + 8);
8029a119
NC		 9279
9280 my_offset += 12;
8f6277f5 9281 }
252b5132
RH		 9282 }
9283
9284 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9285
a4fd1a8e
PB		 9286 return myh;
9287}
9288
9289/* Arm code calling a Thumb function. */
9290
9291static int
9292elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9293 const char * name,
9294 bfd * input_bfd,
9295 bfd * output_bfd,
9296 asection * input_section,
9297 bfd_byte * hit_data,
9298 asection * sym_sec,
9299 bfd_vma offset,
9300 bfd_signed_vma addend,
9301 bfd_vma val,
f2a9dd69 9302 char **error_message)
a4fd1a8e
PB		 9303{
9304 unsigned long int tmp;
9305 bfd_vma my_offset;
9306 asection * s;
9307 long int ret_offset;
9308 struct elf_link_hash_entry * myh;
9309 struct elf32_arm_link_hash_table * globals;
9310
9311 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9312 BFD_ASSERT (globals != NULL);
9313 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9314
3d4d4302
AM		 9315 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9316 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9317 BFD_ASSERT (s != NULL);
9318 BFD_ASSERT (s->contents != NULL);
9319 BFD_ASSERT (s->output_section != NULL);
9320
9321 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9322 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9323 if (!myh)
9324 return FALSE;
9325
9326 my_offset = myh->root.u.def.value;
252b5132
RH		 9327 tmp = bfd_get_32 (input_bfd, hit_data);
9328 tmp = tmp & 0xFF000000;
9329
9b485d32 9330 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9331 ret_offset = (s->output_offset
9332 + my_offset
9333 + s->output_section->vma
9334 - (input_section->output_offset
9335 + input_section->output_section->vma
9336 + offset + addend)
9337 - 8);
9a5aca8c 9338
252b5132
RH		 9339 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9340
dc810e39 9341 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9342
b34976b6 9343 return TRUE;
252b5132
RH		 9344}
9345
a4fd1a8e
PB		 9346/* Populate Arm stub for an exported Thumb function. */
9347
9348static bfd_boolean
9349elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9350{
9351 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9352 asection * s;
9353 struct elf_link_hash_entry * myh;
9354 struct elf32_arm_link_hash_entry *eh;
9355 struct elf32_arm_link_hash_table * globals;
9356 asection *sec;
9357 bfd_vma val;
f2a9dd69 9358 char *error_message;
a4fd1a8e 9359
906e58ca 9360 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9361 /* Allocate stubs for exported Thumb functions on v4t. */
9362 if (eh->export_glue == NULL)
9363 return TRUE;
9364
9365 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9366 BFD_ASSERT (globals != NULL);
9367 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9368
3d4d4302
AM		 9369 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9370 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9371 BFD_ASSERT (s != NULL);
9372 BFD_ASSERT (s->contents != NULL);
9373 BFD_ASSERT (s->output_section != NULL);
9374
9375 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9376
9377 BFD_ASSERT (sec->output_section != NULL);
9378
a4fd1a8e
PB		 9379 val = eh->export_glue->root.u.def.value + sec->output_offset
9380 + sec->output_section->vma;
8029a119 9381
a4fd1a8e
PB		 9382 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9383 h->root.u.def.section->owner,
f2a9dd69
DJ		 9384 globals->obfd, sec, val, s,
9385 &error_message);
a4fd1a8e
PB		 9386 BFD_ASSERT (myh);
9387 return TRUE;
9388}
9389
845b51d6
PB		 9390/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9391
9392static bfd_vma
9393elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9394{
9395 bfd_byte *p;
9396 bfd_vma glue_addr;
9397 asection *s;
9398 struct elf32_arm_link_hash_table *globals;
9399
9400 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9401 BFD_ASSERT (globals != NULL);
9402 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9403
3d4d4302
AM		 9404 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9405 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9406 BFD_ASSERT (s != NULL);
9407 BFD_ASSERT (s->contents != NULL);
9408 BFD_ASSERT (s->output_section != NULL);
9409
9410 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9411
9412 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9413
9414 if ((globals->bx_glue_offset[reg] & 1) == 0)
9415 {
9416 p = s->contents + glue_addr;
9417 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9418 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9419 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9420 globals->bx_glue_offset[reg] |= 1;
9421 }
9422
9423 return glue_addr + s->output_section->vma + s->output_offset;
9424}
9425
a4fd1a8e
PB		 9426/* Generate Arm stubs for exported Thumb symbols. */
9427static void
906e58ca 9428elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9429 struct bfd_link_info *link_info)
9430{
9431 struct elf32_arm_link_hash_table * globals;
9432
8029a119
NC		 9433 if (link_info == NULL)
9434 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9435 return;
9436
9437 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9438 if (globals == NULL)
9439 return;
9440
84c08195
PB		 9441 /* If blx is available then exported Thumb symbols are OK and there is
9442 nothing to do. */
a4fd1a8e
PB		 9443 if (globals->use_blx)
9444 return;
9445
9446 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9447 link_info);
9448}
9449
47beaa6a
RS		 9450/* Reserve space for COUNT dynamic relocations in relocation selection
9451 SRELOC. */
9452
9453static void
9454elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9455 bfd_size_type count)
9456{
9457 struct elf32_arm_link_hash_table *htab;
9458
9459 htab = elf32_arm_hash_table (info);
9460 BFD_ASSERT (htab->root.dynamic_sections_created);
9461 if (sreloc == NULL)
9462 abort ();
9463 sreloc->size += RELOC_SIZE (htab) * count;
9464}
9465
34e77a92
RS		 9466/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9467 dynamic, the relocations should go in SRELOC, otherwise they should
9468 go in the special .rel.iplt section. */
9469
9470static void
9471elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9472 bfd_size_type count)
9473{
9474 struct elf32_arm_link_hash_table *htab;
9475
9476 htab = elf32_arm_hash_table (info);
9477 if (!htab->root.dynamic_sections_created)
9478 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9479 else
9480 {
9481 BFD_ASSERT (sreloc != NULL);
9482 sreloc->size += RELOC_SIZE (htab) * count;
9483 }
9484}
9485
47beaa6a
RS		 9486/* Add relocation REL to the end of relocation section SRELOC. */
9487
9488static void
9489elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9490 asection *sreloc, Elf_Internal_Rela *rel)
9491{
9492 bfd_byte *loc;
9493 struct elf32_arm_link_hash_table *htab;
9494
9495 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9496 if (!htab->root.dynamic_sections_created
9497 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9498 sreloc = htab->root.irelplt;
47beaa6a
RS		 9499 if (sreloc == NULL)
9500 abort ();
9501 loc = sreloc->contents;
9502 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9503 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9504 abort ();
9505 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9506}
9507
34e77a92
RS		 9508/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9509 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9510 to .plt. */
9511
9512static void
9513elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9514 bfd_boolean is_iplt_entry,
9515 union gotplt_union *root_plt,
9516 struct arm_plt_info *arm_plt)
9517{
9518 struct elf32_arm_link_hash_table *htab;
9519 asection *splt;
9520 asection *sgotplt;
9521
9522 htab = elf32_arm_hash_table (info);
9523
9524 if (is_iplt_entry)
9525 {
9526 splt = htab->root.iplt;
9527 sgotplt = htab->root.igotplt;
9528
99059e56
RM		 9529 /* NaCl uses a special first entry in .iplt too. */
9530 if (htab->nacl_p && splt->size == 0)
9531 splt->size += htab->plt_header_size;
9532
34e77a92
RS		 9533 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9534 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9535 }
9536 else
9537 {
9538 splt = htab->root.splt;
9539 sgotplt = htab->root.sgotplt;
9540
7801f98f
CL		 9541 if (htab->fdpic_p)
9542 {
9543 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9544 /* For lazy binding, relocations will be put into .rel.plt, in
9545 .rel.got otherwise. */
9546 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9547 if (info->flags & DF_BIND_NOW)
9548 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9549 else
9550 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9551 }
9552 else
9553 {
9554 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9555 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9556 }
34e77a92
RS		 9557
9558 /* If this is the first .plt entry, make room for the special
9559 first entry. */
9560 if (splt->size == 0)
9561 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9562
9563 htab->next_tls_desc_index++;
34e77a92
RS		 9564 }
9565
9566 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9567 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9568 splt->size += PLT_THUMB_STUB_SIZE;
9569 root_plt->offset = splt->size;
9570 splt->size += htab->plt_entry_size;
9571
9572 if (!htab->symbian_p)
9573 {
9574 /* We also need to make an entry in the .got.plt section, which
9575 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9576 if (is_iplt_entry)
9577 arm_plt->got_offset = sgotplt->size;
9578 else
9579 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9580 if (htab->fdpic_p)
9581 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9582 sgotplt->size += 8;
7801f98f
CL		 9583 else
9584 sgotplt->size += 4;
34e77a92
RS		 9585 }
9586}
9587
b38cadfb
NC		 9588static bfd_vma
9589arm_movw_immediate (bfd_vma value)
9590{
9591 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9592}
9593
9594static bfd_vma
9595arm_movt_immediate (bfd_vma value)
9596{
9597 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9598}
9599
34e77a92
RS		 9600/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9601 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9602 Otherwise, DYNINDX is the index of the symbol in the dynamic
9603 symbol table and SYM_VALUE is undefined.
9604
9605 ROOT_PLT points to the offset of the PLT entry from the start of its
9606 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9607 bookkeeping information.
34e77a92 9608
57460bcf
NC		 9609 Returns FALSE if there was a problem. */
9610
9611static bfd_boolean
34e77a92
RS		 9612elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9613 union gotplt_union *root_plt,
9614 struct arm_plt_info *arm_plt,
9615 int dynindx, bfd_vma sym_value)
9616{
9617 struct elf32_arm_link_hash_table *htab;
9618 asection *sgot;
9619 asection *splt;
9620 asection *srel;
9621 bfd_byte *loc;
9622 bfd_vma plt_index;
9623 Elf_Internal_Rela rel;
9624 bfd_vma plt_header_size;
9625 bfd_vma got_header_size;
9626
9627 htab = elf32_arm_hash_table (info);
9628
9629 /* Pick the appropriate sections and sizes. */
9630 if (dynindx == -1)
9631 {
9632 splt = htab->root.iplt;
9633 sgot = htab->root.igotplt;
9634 srel = htab->root.irelplt;
9635
9636 /* There are no reserved entries in .igot.plt, and no special
9637 first entry in .iplt. */
9638 got_header_size = 0;
9639 plt_header_size = 0;
9640 }
9641 else
9642 {
9643 splt = htab->root.splt;
9644 sgot = htab->root.sgotplt;
9645 srel = htab->root.srelplt;
9646
9647 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9648 plt_header_size = htab->plt_header_size;
9649 }
9650 BFD_ASSERT (splt != NULL && srel != NULL);
9651
9652 /* Fill in the entry in the procedure linkage table. */
9653 if (htab->symbian_p)
9654 {
9655 BFD_ASSERT (dynindx >= 0);
9656 put_arm_insn (htab, output_bfd,
9657 elf32_arm_symbian_plt_entry[0],
9658 splt->contents + root_plt->offset);
9659 bfd_put_32 (output_bfd,
9660 elf32_arm_symbian_plt_entry[1],
9661 splt->contents + root_plt->offset + 4);
9662
9663 /* Fill in the entry in the .rel.plt section. */
9664 rel.r_offset = (splt->output_section->vma
9665 + splt->output_offset
9666 + root_plt->offset + 4);
9667 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9668
9669 /* Get the index in the procedure linkage table which
9670 corresponds to this symbol. This is the index of this symbol
9671 in all the symbols for which we are making plt entries. The
9672 first entry in the procedure linkage table is reserved. */
9673 plt_index = ((root_plt->offset - plt_header_size)
9674 / htab->plt_entry_size);
9675 }
9676 else
9677 {
9678 bfd_vma got_offset, got_address, plt_address;
9679 bfd_vma got_displacement, initial_got_entry;
9680 bfd_byte * ptr;
9681
9682 BFD_ASSERT (sgot != NULL);
9683
9684 /* Get the offset into the .(i)got.plt table of the entry that
9685 corresponds to this function. */
9686 got_offset = (arm_plt->got_offset & -2);
9687
9688 /* Get the index in the procedure linkage table which
9689 corresponds to this symbol. This is the index of this symbol
9690 in all the symbols for which we are making plt entries.
9691 After the reserved .got.plt entries, all symbols appear in
9692 the same order as in .plt. */
7801f98f 9693 if (htab->fdpic_p)
4b24dd1a
AM		 9694 /* Function descriptor takes 8 bytes. */
9695 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9696 else
4b24dd1a 9697 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9698
9699 /* Calculate the address of the GOT entry. */
9700 got_address = (sgot->output_section->vma
9701 + sgot->output_offset
9702 + got_offset);
9703
9704 /* ...and the address of the PLT entry. */
9705 plt_address = (splt->output_section->vma
9706 + splt->output_offset
9707 + root_plt->offset);
9708
9709 ptr = splt->contents + root_plt->offset;
0e1862bb 9710 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9711 {
9712 unsigned int i;
9713 bfd_vma val;
9714
9715 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9716 {
9717 val = elf32_arm_vxworks_shared_plt_entry[i];
9718 if (i == 2)
9719 val |= got_address - sgot->output_section->vma;
9720 if (i == 5)
9721 val |= plt_index * RELOC_SIZE (htab);
9722 if (i == 2 || i == 5)
9723 bfd_put_32 (output_bfd, val, ptr);
9724 else
9725 put_arm_insn (htab, output_bfd, val, ptr);
9726 }
9727 }
9728 else if (htab->vxworks_p)
9729 {
9730 unsigned int i;
9731 bfd_vma val;
9732
9733 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9734 {
9735 val = elf32_arm_vxworks_exec_plt_entry[i];
9736 if (i == 2)
9737 val |= got_address;
9738 if (i == 4)
9739 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9740 if (i == 5)
9741 val |= plt_index * RELOC_SIZE (htab);
9742 if (i == 2 || i == 5)
9743 bfd_put_32 (output_bfd, val, ptr);
9744 else
9745 put_arm_insn (htab, output_bfd, val, ptr);
9746 }
9747
9748 loc = (htab->srelplt2->contents
9749 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9750
9751 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9752 referencing the GOT for this PLT entry. */
9753 rel.r_offset = plt_address + 8;
9754 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9755 rel.r_addend = got_offset;
9756 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9757 loc += RELOC_SIZE (htab);
9758
9759 /* Create the R_ARM_ABS32 relocation referencing the
9760 beginning of the PLT for this GOT entry. */
9761 rel.r_offset = got_address;
9762 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9763 rel.r_addend = 0;
9764 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9765 }
b38cadfb
NC		 9766 else if (htab->nacl_p)
9767 {
9768 /* Calculate the displacement between the PLT slot and the
9769 common tail that's part of the special initial PLT slot. */
6034aab8 9770 int32_t tail_displacement
b38cadfb
NC		 9771 = ((splt->output_section->vma + splt->output_offset
9772 + ARM_NACL_PLT_TAIL_OFFSET)
9773 - (plt_address + htab->plt_entry_size + 4));
9774 BFD_ASSERT ((tail_displacement & 3) == 0);
9775 tail_displacement >>= 2;
9776
9777 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9778 || (-tail_displacement & 0xff000000) == 0);
9779
9780 /* Calculate the displacement between the PLT slot and the entry
9781 in the GOT. The offset accounts for the value produced by
9782 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9783 got_displacement = (got_address
99059e56 9784 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9785
9786 /* NaCl does not support interworking at all. */
9787 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9788
9789 put_arm_insn (htab, output_bfd,
9790 elf32_arm_nacl_plt_entry[0]
9791 | arm_movw_immediate (got_displacement),
9792 ptr + 0);
9793 put_arm_insn (htab, output_bfd,
9794 elf32_arm_nacl_plt_entry[1]
9795 | arm_movt_immediate (got_displacement),
9796 ptr + 4);
9797 put_arm_insn (htab, output_bfd,
9798 elf32_arm_nacl_plt_entry[2],
9799 ptr + 8);
9800 put_arm_insn (htab, output_bfd,
9801 elf32_arm_nacl_plt_entry[3]
9802 | (tail_displacement & 0x00ffffff),
9803 ptr + 12);
9804 }
7801f98f
CL		 9805 else if (htab->fdpic_p)
9806 {
59029f57
CL		 9807 const bfd_vma *plt_entry = using_thumb_only(htab)
9808 ? elf32_arm_fdpic_thumb_plt_entry
9809 : elf32_arm_fdpic_plt_entry;
9810
7801f98f
CL		 9811 /* Fill-up Thumb stub if needed. */
9812 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9813 {
9814 put_thumb_insn (htab, output_bfd,
9815 elf32_arm_plt_thumb_stub[0], ptr - 4);
9816 put_thumb_insn (htab, output_bfd,
9817 elf32_arm_plt_thumb_stub[1], ptr - 2);
9818 }
59029f57
CL		 9819 /* As we are using 32 bit instructions even for the Thumb
9820 version, we have to use 'put_arm_insn' instead of
9821 'put_thumb_insn'. */
9822 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9823 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9824 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9825 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9826 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9827
9828 if (!(info->flags & DF_BIND_NOW))
9829 {
9830 /* funcdesc_value_reloc_offset. */
9831 bfd_put_32 (output_bfd,
9832 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9833 ptr + 20);
59029f57
CL		 9834 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9835 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9836 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9837 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9838 }
9839 }
57460bcf
NC		 9840 else if (using_thumb_only (htab))
9841 {
eed94f8f 9842 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9843 if (!using_thumb2 (htab))
eed94f8f
NC		 9844 {
9845 /* FIXME: We ought to be able to generate thumb-1 PLT
9846 instructions... */
90b6238f 9847 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9848 output_bfd);
9849 return FALSE;
9850 }
57460bcf 9851
eed94f8f
NC		 9852 /* Calculate the displacement between the PLT slot and the entry in
9853 the GOT. The 12-byte offset accounts for the value produced by
9854 adding to pc in the 3rd instruction of the PLT stub. */
9855 got_displacement = got_address - (plt_address + 12);
9856
9857 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9858 instead of 'put_thumb_insn'. */
9859 put_arm_insn (htab, output_bfd,
9860 elf32_thumb2_plt_entry[0]
9861 | ((got_displacement & 0x000000ff) << 16)
9862 | ((got_displacement & 0x00000700) << 20)
9863 | ((got_displacement & 0x00000800) >> 1)
9864 | ((got_displacement & 0x0000f000) >> 12),
9865 ptr + 0);
9866 put_arm_insn (htab, output_bfd,
9867 elf32_thumb2_plt_entry[1]
9868 | ((got_displacement & 0x00ff0000) )
9869 | ((got_displacement & 0x07000000) << 4)
9870 | ((got_displacement & 0x08000000) >> 17)
9871 | ((got_displacement & 0xf0000000) >> 28),
9872 ptr + 4);
9873 put_arm_insn (htab, output_bfd,
9874 elf32_thumb2_plt_entry[2],
9875 ptr + 8);
9876 put_arm_insn (htab, output_bfd,
9877 elf32_thumb2_plt_entry[3],
9878 ptr + 12);
57460bcf 9879 }
34e77a92
RS		 9880 else
9881 {
9882 /* Calculate the displacement between the PLT slot and the
9883 entry in the GOT. The eight-byte offset accounts for the
9884 value produced by adding to pc in the first instruction
9885 of the PLT stub. */
9886 got_displacement = got_address - (plt_address + 8);
9887
34e77a92
RS		 9888 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9889 {
9890 put_thumb_insn (htab, output_bfd,
9891 elf32_arm_plt_thumb_stub[0], ptr - 4);
9892 put_thumb_insn (htab, output_bfd,
9893 elf32_arm_plt_thumb_stub[1], ptr - 2);
9894 }
9895
1db37fe6
YG		 9896 if (!elf32_arm_use_long_plt_entry)
9897 {
9898 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9899
9900 put_arm_insn (htab, output_bfd,
9901 elf32_arm_plt_entry_short[0]
9902 | ((got_displacement & 0x0ff00000) >> 20),
9903 ptr + 0);
9904 put_arm_insn (htab, output_bfd,
9905 elf32_arm_plt_entry_short[1]
9906 | ((got_displacement & 0x000ff000) >> 12),
9907 ptr+ 4);
9908 put_arm_insn (htab, output_bfd,
9909 elf32_arm_plt_entry_short[2]
9910 | (got_displacement & 0x00000fff),
9911 ptr + 8);
34e77a92 9912#ifdef FOUR_WORD_PLT
1db37fe6 9913 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9914#endif
1db37fe6
YG		 9915 }
9916 else
9917 {
9918 put_arm_insn (htab, output_bfd,
9919 elf32_arm_plt_entry_long[0]
9920 | ((got_displacement & 0xf0000000) >> 28),
9921 ptr + 0);
9922 put_arm_insn (htab, output_bfd,
9923 elf32_arm_plt_entry_long[1]
9924 | ((got_displacement & 0x0ff00000) >> 20),
9925 ptr + 4);
9926 put_arm_insn (htab, output_bfd,
9927 elf32_arm_plt_entry_long[2]
9928 | ((got_displacement & 0x000ff000) >> 12),
9929 ptr+ 8);
9930 put_arm_insn (htab, output_bfd,
9931 elf32_arm_plt_entry_long[3]
9932 | (got_displacement & 0x00000fff),
9933 ptr + 12);
9934 }
34e77a92
RS		 9935 }
9936
9937 /* Fill in the entry in the .rel(a).(i)plt section. */
9938 rel.r_offset = got_address;
9939 rel.r_addend = 0;
9940 if (dynindx == -1)
9941 {
9942 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9943 The dynamic linker or static executable then calls SYM_VALUE
9944 to determine the correct run-time value of the .igot.plt entry. */
9945 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9946 initial_got_entry = sym_value;
9947 }
9948 else
9949 {
7801f98f
CL		 9950 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9951 used by PLT entry. */
9952 if (htab->fdpic_p)
9953 {
9954 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9955 initial_got_entry = 0;
9956 }
9957 else
9958 {
9959 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9960 initial_got_entry = (splt->output_section->vma
9961 + splt->output_offset);
9962 }
34e77a92
RS		 9963 }
9964
9965 /* Fill in the entry in the global offset table. */
9966 bfd_put_32 (output_bfd, initial_got_entry,
9967 sgot->contents + got_offset);
7801f98f
CL		 9968
9969 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9970 {
9971 /* Setup initial funcdesc value. */
9972 /* FIXME: we don't support lazy binding because there is a
9973 race condition between both words getting written and
9974 some other thread attempting to read them. The ARM
9975 architecture does not have an atomic 64 bit load/store
9976 instruction that could be used to prevent it; it is
9977 recommended that threaded FDPIC applications run with the
9978 LD_BIND_NOW environment variable set. */
9979 bfd_put_32(output_bfd, plt_address + 0x18,
9980 sgot->contents + got_offset);
9981 bfd_put_32(output_bfd, -1 /*TODO*/,
9982 sgot->contents + got_offset + 4);
9983 }
34e77a92
RS		 9984 }
9985
aba8c3de
WN		 9986 if (dynindx == -1)
9987 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9988 else
9989 {
7801f98f
CL		 9990 if (htab->fdpic_p)
9991 {
9992 /* For FDPIC we put PLT relocationss into .rel.got when not
9993 lazy binding otherwise we put them in .rel.plt. For now,
9994 we don't support lazy binding so put it in .rel.got. */
9995 if (info->flags & DF_BIND_NOW)
9996 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
9997 else
9998 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
9999 }
10000 else
10001 {
10002 loc = srel->contents + plt_index * RELOC_SIZE (htab);
10003 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
10004 }
aba8c3de 10005 }
57460bcf
NC		 10006
10007 return TRUE;
34e77a92
RS		 10008}
10009
eb043451
PB		 10010/* Some relocations map to different relocations depending on the
10011 target. Return the real relocation. */
8029a119 10012
eb043451
PB		 10013static int
10014arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10015 int r_type)
10016{
10017 switch (r_type)
10018 {
10019 case R_ARM_TARGET1:
10020 if (globals->target1_is_rel)
10021 return R_ARM_REL32;
10022 else
10023 return R_ARM_ABS32;
10024
10025 case R_ARM_TARGET2:
10026 return globals->target2_reloc;
10027
10028 default:
10029 return r_type;
10030 }
10031}
eb043451 10032
ba93b8ac
DJ		 10033/* Return the base VMA address which should be subtracted from real addresses
10034 when resolving @dtpoff relocation.
10035 This is PT_TLS segment p_vaddr. */
10036
10037static bfd_vma
10038dtpoff_base (struct bfd_link_info *info)
10039{
10040 /* If tls_sec is NULL, we should have signalled an error already. */
10041 if (elf_hash_table (info)->tls_sec == NULL)
10042 return 0;
10043 return elf_hash_table (info)->tls_sec->vma;
10044}
10045
10046/* Return the relocation value for @tpoff relocation
10047 if STT_TLS virtual address is ADDRESS. */
10048
10049static bfd_vma
10050tpoff (struct bfd_link_info *info, bfd_vma address)
10051{
10052 struct elf_link_hash_table *htab = elf_hash_table (info);
10053 bfd_vma base;
10054
10055 /* If tls_sec is NULL, we should have signalled an error already. */
10056 if (htab->tls_sec == NULL)
10057 return 0;
10058 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10059 return address - htab->tls_sec->vma + base;
10060}
10061
00a97672
RS		 10062/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10063 VALUE is the relocation value. */
10064
10065static bfd_reloc_status_type
10066elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10067{
10068 if (value > 0xfff)
10069 return bfd_reloc_overflow;
10070
10071 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10072 bfd_put_32 (abfd, value, data);
10073 return bfd_reloc_ok;
10074}
10075
0855e32b
NS		 10076/* Handle TLS relaxations. Relaxing is possible for symbols that use
10077 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10078 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10079
10080 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10081 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10082 case of error.
10083
10084 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10085 the pre-relaxed code. It would be nice if the relocs were updated
10086 to match the optimization. */
0855e32b 10087
b38cadfb 10088static bfd_reloc_status_type
0855e32b 10089elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10090 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10091 Elf_Internal_Rela *rel, unsigned long is_local)
10092{
10093 unsigned long insn;
b38cadfb 10094
0855e32b
NS		 10095 switch (ELF32_R_TYPE (rel->r_info))
10096 {
10097 default:
10098 return bfd_reloc_notsupported;
b38cadfb 10099
0855e32b
NS		 10100 case R_ARM_TLS_GOTDESC:
10101 if (is_local)
10102 insn = 0;
10103 else
10104 {
10105 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10106 if (insn & 1)
10107 insn -= 5; /* THUMB */
10108 else
10109 insn -= 8; /* ARM */
10110 }
10111 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10112 return bfd_reloc_continue;
10113
10114 case R_ARM_THM_TLS_DESCSEQ:
10115 /* Thumb insn. */
10116 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10117 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10118 {
10119 if (is_local)
10120 /* nop */
10121 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10122 }
10123 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10124 {
10125 if (is_local)
10126 /* nop */
10127 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10128 else
10129 /* ldr rx,[ry] */
10130 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10131 }
10132 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10133 {
10134 if (is_local)
10135 /* nop */
10136 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10137 else
10138 /* mov r0, rx */
10139 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10140 contents + rel->r_offset);
10141 }
10142 else
10143 {
10144 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10145 /* It's a 32 bit instruction, fetch the rest of it for
10146 error generation. */
10147 insn = (insn << 16)
10148 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10149 _bfd_error_handler
695344c0 10150 /* xgettext:c-format */
2dcf00ce 10151 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10152 "unexpected %s instruction '%#lx' in TLS trampoline"),
10153 input_bfd, input_sec, (uint64_t) rel->r_offset,
10154 "Thumb", insn);
0855e32b
NS		 10155 return bfd_reloc_notsupported;
10156 }
10157 break;
b38cadfb 10158
0855e32b
NS		 10159 case R_ARM_TLS_DESCSEQ:
10160 /* arm insn. */
10161 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10162 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10163 {
10164 if (is_local)
10165 /* mov rx, ry */
10166 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10167 contents + rel->r_offset);
10168 }
10169 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10170 {
10171 if (is_local)
10172 /* nop */
10173 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10174 else
10175 /* ldr rx,[ry] */
10176 bfd_put_32 (input_bfd, insn & 0xfffff000,
10177 contents + rel->r_offset);
10178 }
10179 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10180 {
10181 if (is_local)
10182 /* nop */
10183 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10184 else
10185 /* mov r0, rx */
10186 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10187 contents + rel->r_offset);
10188 }
10189 else
10190 {
4eca0228 10191 _bfd_error_handler
695344c0 10192 /* xgettext:c-format */
2dcf00ce 10193 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10194 "unexpected %s instruction '%#lx' in TLS trampoline"),
10195 input_bfd, input_sec, (uint64_t) rel->r_offset,
10196 "ARM", insn);
0855e32b
NS		 10197 return bfd_reloc_notsupported;
10198 }
10199 break;
10200
10201 case R_ARM_TLS_CALL:
10202 /* GD->IE relaxation, turn the instruction into 'nop' or
10203 'ldr r0, [pc,r0]' */
10204 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10205 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10206 break;
b38cadfb 10207
0855e32b 10208 case R_ARM_THM_TLS_CALL:
6a631e86 10209 /* GD->IE relaxation. */
0855e32b
NS		 10210 if (!is_local)
10211 /* add r0,pc; ldr r0, [r0] */
10212 insn = 0x44786800;
60a019a0 10213 else if (using_thumb2 (globals))
0855e32b
NS		 10214 /* nop.w */
10215 insn = 0xf3af8000;
10216 else
10217 /* nop; nop */
10218 insn = 0xbf00bf00;
b38cadfb 10219
0855e32b
NS		 10220 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10221 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10222 break;
10223 }
10224 return bfd_reloc_ok;
10225}
10226
4962c51a
MS		 10227/* For a given value of n, calculate the value of G_n as required to
10228 deal with group relocations. We return it in the form of an
10229 encoded constant-and-rotation, together with the final residual. If n is
10230 specified as less than zero, then final_residual is filled with the
10231 input value and no further action is performed. */
10232
10233static bfd_vma
10234calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10235{
10236 int current_n;
10237 bfd_vma g_n;
10238 bfd_vma encoded_g_n = 0;
10239 bfd_vma residual = value; /* Also known as Y_n. */
10240
10241 for (current_n = 0; current_n <= n; current_n++)
10242 {
10243 int shift;
10244
10245 /* Calculate which part of the value to mask. */
10246 if (residual == 0)
99059e56 10247 shift = 0;
4962c51a 10248 else
99059e56
RM		 10249 {
10250 int msb;
10251
10252 /* Determine the most significant bit in the residual and
10253 align the resulting value to a 2-bit boundary. */
10254 for (msb = 30; msb >= 0; msb -= 2)
10255 if (residual & (3 << msb))
10256 break;
10257
10258 /* The desired shift is now (msb - 6), or zero, whichever
10259 is the greater. */
10260 shift = msb - 6;
10261 if (shift < 0)
10262 shift = 0;
10263 }
4962c51a
MS		 10264
10265 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10266 g_n = residual & (0xff << shift);
10267 encoded_g_n = (g_n >> shift)
99059e56 10268 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10269
10270 /* Calculate the residual for the next time around. */
10271 residual &= ~g_n;
10272 }
10273
10274 *final_residual = residual;
10275
10276 return encoded_g_n;
10277}
10278
10279/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10280 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10281
4962c51a 10282static int
906e58ca 10283identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10284{
10285 int opcode = insn & 0x1e00000;
10286
10287 if (opcode == 1 << 23) /* ADD */
10288 return 1;
10289
10290 if (opcode == 1 << 22) /* SUB */
10291 return -1;
10292
10293 return 0;
10294}
10295
e5d6e09e
AV		 10296/* Helper function to compute the Addend for Armv8.1-M Mainline relocations. */
10297static bfd_vma
10298get_value_helper (bfd_vma plt_offset,
10299 asection *splt,
10300 asection *input_section,
10301 asection *sym_sec,
10302 struct elf_link_hash_entry * h,
10303 struct bfd_link_info *info,
10304 bfd *input_bfd,
10305 Elf_Internal_Rela *rel,
10306 const char *sym_name,
10307 unsigned char st_type,
10308 struct elf32_arm_link_hash_table *globals,
10309 bfd_boolean *unresolved_reloc_p)
10310{
10311 bfd_vma value = 0;
10312 enum arm_st_branch_type branch_type;
10313 enum elf32_arm_stub_type stub_type = arm_stub_none;
10314 struct elf32_arm_stub_hash_entry *stub_entry;
10315 struct elf32_arm_link_hash_entry *hash
10316 = (struct elf32_arm_link_hash_entry *)h;
10317
10318
10319 if (plt_offset != (bfd_vma) -1)
10320 {
10321 value = (splt->output_section->vma
10322 + splt->output_offset
10323 + plt_offset);
10324 value -= PLT_THUMB_STUB_SIZE;
10325 *unresolved_reloc_p = FALSE;
10326 }
10327
10328 stub_type = arm_type_of_stub (info, input_section, rel,
10329 st_type, &branch_type,
10330 hash, value, sym_sec,
10331 input_bfd, sym_name);
10332
10333 if (stub_type != arm_stub_none)
10334 {
10335 stub_entry = elf32_arm_get_stub_entry (input_section,
10336 sym_sec, h,
10337 rel, globals,
10338 stub_type);
10339 if (stub_entry != NULL)
10340 {
10341 value = (stub_entry->stub_offset
10342 + stub_entry->stub_sec->output_offset
10343 + stub_entry->stub_sec->output_section->vma);
10344 }
10345 }
10346 return value;
10347}
10348
252b5132 10349/* Perform a relocation as part of a final link. */
9b485d32 10350
252b5132 10351static bfd_reloc_status_type
07d6d2b8
AM		 10352elf32_arm_final_link_relocate (reloc_howto_type * howto,
10353 bfd * input_bfd,
10354 bfd * output_bfd,
10355 asection * input_section,
10356 bfd_byte * contents,
10357 Elf_Internal_Rela * rel,
10358 bfd_vma value,
10359 struct bfd_link_info * info,
10360 asection * sym_sec,
10361 const char * sym_name,
10362 unsigned char st_type,
10363 enum arm_st_branch_type branch_type,
0945cdfd 10364 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10365 bfd_boolean * unresolved_reloc_p,
10366 char ** error_message)
10367{
10368 unsigned long r_type = howto->type;
10369 unsigned long r_symndx;
10370 bfd_byte * hit_data = contents + rel->r_offset;
10371 bfd_vma * local_got_offsets;
10372 bfd_vma * local_tlsdesc_gotents;
10373 asection * sgot;
10374 asection * splt;
10375 asection * sreloc = NULL;
10376 asection * srelgot;
10377 bfd_vma addend;
10378 bfd_signed_vma signed_addend;
10379 unsigned char dynreloc_st_type;
10380 bfd_vma dynreloc_value;
ba96a88f 10381 struct elf32_arm_link_hash_table * globals;
34e77a92 10382 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10383 union gotplt_union *root_plt;
10384 struct arm_plt_info *arm_plt;
10385 bfd_vma plt_offset;
10386 bfd_vma gotplt_offset;
10387 bfd_boolean has_iplt_entry;
10388 bfd_boolean resolved_to_zero;
f21f3fe0 10389
9c504268 10390 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10391 if (globals == NULL)
10392 return bfd_reloc_notsupported;
9c504268 10393
0ffa91dd 10394 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10395 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10396
10397 /* Some relocation types map to different relocations depending on the
9c504268 10398 target. We pick the right one here. */
eb043451 10399 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10400
10401 /* It is possible to have linker relaxations on some TLS access
10402 models. Update our information here. */
10403 r_type = elf32_arm_tls_transition (info, r_type, h);
10404
eb043451
PB		 10405 if (r_type != howto->type)
10406 howto = elf32_arm_howto_from_type (r_type);
9c504268 10407
34e77a92 10408 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10409 sgot = globals->root.sgot;
252b5132 10410 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10411 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10412
34e77a92
RS		 10413 if (globals->root.dynamic_sections_created)
10414 srelgot = globals->root.srelgot;
10415 else
10416 srelgot = NULL;
10417
252b5132
RH		 10418 r_symndx = ELF32_R_SYM (rel->r_info);
10419
4e7fd91e 10420 if (globals->use_rel)
ba96a88f 10421 {
4e7fd91e
PB		 10422 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10423
10424 if (addend & ((howto->src_mask + 1) >> 1))
10425 {
10426 signed_addend = -1;
10427 signed_addend &= ~ howto->src_mask;
10428 signed_addend |= addend;
10429 }
10430 else
10431 signed_addend = addend;
ba96a88f
NC		 10432 }
10433 else
4e7fd91e 10434 addend = signed_addend = rel->r_addend;
f21f3fe0 10435
39f21624
NC		 10436 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10437 are resolving a function call relocation. */
10438 if (using_thumb_only (globals)
10439 && (r_type == R_ARM_THM_CALL
10440 || r_type == R_ARM_THM_JUMP24)
10441 && branch_type == ST_BRANCH_TO_ARM)
10442 branch_type = ST_BRANCH_TO_THUMB;
10443
34e77a92
RS		 10444 /* Record the symbol information that should be used in dynamic
10445 relocations. */
10446 dynreloc_st_type = st_type;
10447 dynreloc_value = value;
10448 if (branch_type == ST_BRANCH_TO_THUMB)
10449 dynreloc_value |= 1;
10450
10451 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10452 VALUE appropriately for relocations that we resolve at link time. */
10453 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10454 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10455 &arm_plt)
34e77a92
RS		 10456 && root_plt->offset != (bfd_vma) -1)
10457 {
10458 plt_offset = root_plt->offset;
10459 gotplt_offset = arm_plt->got_offset;
10460
10461 if (h == NULL || eh->is_iplt)
10462 {
10463 has_iplt_entry = TRUE;
10464 splt = globals->root.iplt;
10465
10466 /* Populate .iplt entries here, because not all of them will
10467 be seen by finish_dynamic_symbol. The lower bit is set if
10468 we have already populated the entry. */
10469 if (plt_offset & 1)
10470 plt_offset--;
10471 else
10472 {
57460bcf
NC		 10473 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10474 -1, dynreloc_value))
10475 root_plt->offset |= 1;
10476 else
10477 return bfd_reloc_notsupported;
34e77a92
RS		 10478 }
10479
10480 /* Static relocations always resolve to the .iplt entry. */
10481 st_type = STT_FUNC;
10482 value = (splt->output_section->vma
10483 + splt->output_offset
10484 + plt_offset);
10485 branch_type = ST_BRANCH_TO_ARM;
10486
10487 /* If there are non-call relocations that resolve to the .iplt
10488 entry, then all dynamic ones must too. */
10489 if (arm_plt->noncall_refcount != 0)
10490 {
10491 dynreloc_st_type = st_type;
10492 dynreloc_value = value;
10493 }
10494 }
10495 else
10496 /* We populate the .plt entry in finish_dynamic_symbol. */
10497 splt = globals->root.splt;
10498 }
10499 else
10500 {
10501 splt = NULL;
10502 plt_offset = (bfd_vma) -1;
10503 gotplt_offset = (bfd_vma) -1;
10504 }
10505
95b03e4a
L		 10506 resolved_to_zero = (h != NULL
10507 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10508
252b5132
RH		 10509 switch (r_type)
10510 {
10511 case R_ARM_NONE:
28a094c2
DJ		 10512 /* We don't need to find a value for this symbol. It's just a
10513 marker. */
10514 *unresolved_reloc_p = FALSE;
252b5132
RH		 10515 return bfd_reloc_ok;
10516
00a97672
RS		 10517 case R_ARM_ABS12:
10518 if (!globals->vxworks_p)
10519 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10520 /* Fall through. */
00a97672 10521
252b5132
RH		 10522 case R_ARM_PC24:
10523 case R_ARM_ABS32:
bb224fc3 10524 case R_ARM_ABS32_NOI:
252b5132 10525 case R_ARM_REL32:
bb224fc3 10526 case R_ARM_REL32_NOI:
5b5bb741
PB		 10527 case R_ARM_CALL:
10528 case R_ARM_JUMP24:
dfc5f959 10529 case R_ARM_XPC25:
eb043451 10530 case R_ARM_PREL31:
7359ea65 10531 case R_ARM_PLT32:
7359ea65
DJ		 10532 /* Handle relocations which should use the PLT entry. ABS32/REL32
10533 will use the symbol's value, which may point to a PLT entry, but we
10534 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10535 branches in this object should go to it, except if the PLT is too
10536 far away, in which case a long branch stub should be inserted. */
bb224fc3 10537 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10538 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10539 && r_type != R_ARM_CALL
10540 && r_type != R_ARM_JUMP24
10541 && r_type != R_ARM_PLT32)
34e77a92 10542 && plt_offset != (bfd_vma) -1)
7359ea65 10543 {
34e77a92
RS		 10544 /* If we've created a .plt section, and assigned a PLT entry
10545 to this function, it must either be a STT_GNU_IFUNC reference
10546 or not be known to bind locally. In other cases, we should
10547 have cleared the PLT entry by now. */
10548 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10549
10550 value = (splt->output_section->vma
10551 + splt->output_offset
34e77a92 10552 + plt_offset);
0945cdfd 10553 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10554 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10555 contents, rel->r_offset, value,
00a97672 10556 rel->r_addend);
7359ea65
DJ		 10557 }
10558
67687978
PB		 10559 /* When generating a shared object or relocatable executable, these
10560 relocations are copied into the output file to be resolved at
10561 run time. */
0e1862bb 10562 if ((bfd_link_pic (info)
e8b09b87
CL		 10563 || globals->root.is_relocatable_executable
10564 || globals->fdpic_p)
7359ea65 10565 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10566 && !(globals->vxworks_p
3348747a
NS		 10567 && strcmp (input_section->output_section->name,
10568 ".tls_vars") == 0)
bb224fc3 10569 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10570 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10571 && !(input_bfd == globals->stub_bfd
10572 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10573 && (h == NULL
95b03e4a
L		 10574 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10575 && !resolved_to_zero)
7359ea65
DJ		 10576 || h->root.type != bfd_link_hash_undefweak)
10577 && r_type != R_ARM_PC24
5b5bb741
PB		 10578 && r_type != R_ARM_CALL
10579 && r_type != R_ARM_JUMP24
ee06dc07 10580 && r_type != R_ARM_PREL31
7359ea65 10581 && r_type != R_ARM_PLT32)
252b5132 10582 {
947216bf 10583 Elf_Internal_Rela outrel;
b34976b6 10584 bfd_boolean skip, relocate;
e8b09b87 10585 int isrofixup = 0;
f21f3fe0 10586
52db4ec2
JW		 10587 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10588 && !h->def_regular)
10589 {
10590 char *v = _("shared object");
10591
0e1862bb 10592 if (bfd_link_executable (info))
52db4ec2
JW		 10593 v = _("PIE executable");
10594
4eca0228 10595 _bfd_error_handler
871b3ab2 10596 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10597 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10598 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10599 return bfd_reloc_notsupported;
10600 }
10601
0945cdfd
DJ		 10602 *unresolved_reloc_p = FALSE;
10603
34e77a92 10604 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10605 {
83bac4b0
NC		 10606 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10607 ! globals->use_rel);
f21f3fe0 10608
83bac4b0 10609 if (sreloc == NULL)
252b5132 10610 return bfd_reloc_notsupported;
252b5132 10611 }
f21f3fe0 10612
b34976b6
AM		 10613 skip = FALSE;
10614 relocate = FALSE;
f21f3fe0 10615
00a97672 10616 outrel.r_addend = addend;
c629eae0
JJ		 10617 outrel.r_offset =
10618 _bfd_elf_section_offset (output_bfd, info, input_section,
10619 rel->r_offset);
10620 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10621 skip = TRUE;
0bb2d96a 10622 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10623 skip = TRUE, relocate = TRUE;
252b5132
RH		 10624 outrel.r_offset += (input_section->output_section->vma
10625 + input_section->output_offset);
f21f3fe0 10626
252b5132 10627 if (skip)
0bb2d96a 10628 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10629 else if (h != NULL
10630 && h->dynindx != -1
0e1862bb 10631 && (!bfd_link_pic (info)
1dcb9720
JW		 10632 || !(bfd_link_pie (info)
10633 || SYMBOLIC_BIND (info, h))
f5385ebf 10634 || !h->def_regular))
5e681ec4 10635 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10636 else
10637 {
a16385dc
MM		 10638 int symbol;
10639
5e681ec4 10640 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10641 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10642 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10643 if (globals->symbian_p)
6366ff1e 10644 {
74541ad4
AM		 10645 asection *osec;
10646
6366ff1e
MM		 10647 /* On Symbian OS, the data segment and text segement
10648 can be relocated independently. Therefore, we
10649 must indicate the segment to which this
10650 relocation is relative. The BPABI allows us to
10651 use any symbol in the right segment; we just use
10652 the section symbol as it is convenient. (We
10653 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10654 will not appear in the dynamic symbol table.)
10655
10656 Note that the dynamic linker ignores the section
10657 symbol value, so we don't subtract osec->vma
10658 from the emitted reloc addend. */
10dbd1f3 10659 if (sym_sec)
74541ad4 10660 osec = sym_sec->output_section;
10dbd1f3 10661 else
74541ad4
AM		 10662 osec = input_section->output_section;
10663 symbol = elf_section_data (osec)->dynindx;
10664 if (symbol == 0)
10665 {
10666 struct elf_link_hash_table *htab = elf_hash_table (info);
10667
10668 if ((osec->flags & SEC_READONLY) == 0
10669 && htab->data_index_section != NULL)
10670 osec = htab->data_index_section;
10671 else
10672 osec = htab->text_index_section;
10673 symbol = elf_section_data (osec)->dynindx;
10674 }
6366ff1e
MM		 10675 BFD_ASSERT (symbol != 0);
10676 }
a16385dc
MM		 10677 else
10678 /* On SVR4-ish systems, the dynamic loader cannot
10679 relocate the text and data segments independently,
10680 so the symbol does not matter. */
10681 symbol = 0;
34e77a92
RS		 10682 if (dynreloc_st_type == STT_GNU_IFUNC)
10683 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10684 to the .iplt entry. Instead, every non-call reference
10685 must use an R_ARM_IRELATIVE relocation to obtain the
10686 correct run-time address. */
10687 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10688 else if (globals->fdpic_p && !bfd_link_pic(info))
10689 isrofixup = 1;
34e77a92
RS		 10690 else
10691 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10692 if (globals->use_rel)
10693 relocate = TRUE;
10694 else
34e77a92 10695 outrel.r_addend += dynreloc_value;
252b5132 10696 }
f21f3fe0 10697
e8b09b87
CL		 10698 if (isrofixup)
10699 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10700 else
10701 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10702
f21f3fe0 10703 /* If this reloc is against an external symbol, we do not want to
252b5132 10704 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10705 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10706 if (! relocate)
10707 return bfd_reloc_ok;
9a5aca8c 10708
f21f3fe0 10709 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10710 contents, rel->r_offset,
10711 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10712 }
10713 else switch (r_type)
10714 {
00a97672
RS		 10715 case R_ARM_ABS12:
10716 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10717
dfc5f959 10718 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10719 case R_ARM_CALL:
10720 case R_ARM_JUMP24:
8029a119 10721 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10722 case R_ARM_PLT32:
906e58ca 10723 {
906e58ca
NC		 10724 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10725
dfc5f959 10726 if (r_type == R_ARM_XPC25)
252b5132 10727 {
dfc5f959
NC		 10728 /* Check for Arm calling Arm function. */
10729 /* FIXME: Should we translate the instruction into a BL
10730 instruction instead ? */
35fc36a8 10731 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10732 _bfd_error_handler
90b6238f
AM		 10733 (_("\%pB: warning: %s BLX instruction targets"
10734 " %s function '%s'"),
10735 input_bfd, "ARM",
10736 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10737 }
155d87d7 10738 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10739 {
10740 /* Check for Arm calling Thumb function. */
35fc36a8 10741 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10742 {
f2a9dd69
DJ		 10743 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10744 output_bfd, input_section,
10745 hit_data, sym_sec, rel->r_offset,
10746 signed_addend, value,
10747 error_message))
10748 return bfd_reloc_ok;
10749 else
10750 return bfd_reloc_dangerous;
dfc5f959 10751 }
252b5132 10752 }
ba96a88f 10753
906e58ca 10754 /* Check if a stub has to be inserted because the
8029a119 10755 destination is too far or we are changing mode. */
155d87d7
CL		 10756 if ( r_type == R_ARM_CALL
10757 || r_type == R_ARM_JUMP24
10758 || r_type == R_ARM_PLT32)
906e58ca 10759 {
fe33d2fa
CL		 10760 enum elf32_arm_stub_type stub_type = arm_stub_none;
10761 struct elf32_arm_link_hash_entry *hash;
10762
10763 hash = (struct elf32_arm_link_hash_entry *) h;
10764 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10765 st_type, &branch_type,
10766 hash, value, sym_sec,
fe33d2fa 10767 input_bfd, sym_name);
5fa9e92f 10768
fe33d2fa 10769 if (stub_type != arm_stub_none)
906e58ca
NC		 10770 {
10771 /* The target is out of reach, so redirect the
10772 branch to the local stub for this function. */
906e58ca
NC		 10773 stub_entry = elf32_arm_get_stub_entry (input_section,
10774 sym_sec, h,
fe33d2fa
CL		 10775 rel, globals,
10776 stub_type);
9cd3e4e5
NC		 10777 {
10778 if (stub_entry != NULL)
10779 value = (stub_entry->stub_offset
10780 + stub_entry->stub_sec->output_offset
10781 + stub_entry->stub_sec->output_section->vma);
10782
10783 if (plt_offset != (bfd_vma) -1)
10784 *unresolved_reloc_p = FALSE;
10785 }
906e58ca 10786 }
fe33d2fa
CL		 10787 else
10788 {
10789 /* If the call goes through a PLT entry, make sure to
10790 check distance to the right destination address. */
34e77a92 10791 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10792 {
10793 value = (splt->output_section->vma
10794 + splt->output_offset
34e77a92 10795 + plt_offset);
fe33d2fa
CL		 10796 *unresolved_reloc_p = FALSE;
10797 /* The PLT entry is in ARM mode, regardless of the
10798 target function. */
35fc36a8 10799 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10800 }
10801 }
906e58ca
NC		 10802 }
10803
dea514f5
PB		 10804 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10805 where:
10806 S is the address of the symbol in the relocation.
10807 P is address of the instruction being relocated.
10808 A is the addend (extracted from the instruction) in bytes.
10809
10810 S is held in 'value'.
10811 P is the base address of the section containing the
10812 instruction plus the offset of the reloc into that
10813 section, ie:
10814 (input_section->output_section->vma +
10815 input_section->output_offset +
10816 rel->r_offset).
10817 A is the addend, converted into bytes, ie:
10818 (signed_addend * 4)
10819
10820 Note: None of these operations have knowledge of the pipeline
10821 size of the processor, thus it is up to the assembler to
10822 encode this information into the addend. */
10823 value -= (input_section->output_section->vma
10824 + input_section->output_offset);
10825 value -= rel->r_offset;
4e7fd91e
PB		 10826 if (globals->use_rel)
10827 value += (signed_addend << howto->size);
10828 else
10829 /* RELA addends do not have to be adjusted by howto->size. */
10830 value += signed_addend;
23080146 10831
dcb5e6e6
NC		 10832 signed_addend = value;
10833 signed_addend >>= howto->rightshift;
9a5aca8c 10834
5ab79981 10835 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10836 the next instruction unless a PLT entry will be created.
77b4f08f 10837 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10838 The jump to the next instruction is optimized as a NOP depending
10839 on the architecture. */
ffcb4889 10840 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10841 && plt_offset == (bfd_vma) -1)
77b4f08f 10842 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10843 {
cd1dac3d
DG		 10844 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10845
10846 if (arch_has_arm_nop (globals))
10847 value |= 0x0320f000;
10848 else
10849 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10850 }
10851 else
59f2c4e7 10852 {
9b485d32 10853 /* Perform a signed range check. */
dcb5e6e6 10854 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10855 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10856 return bfd_reloc_overflow;
9a5aca8c 10857
5ab79981 10858 addend = (value & 2);
39b41c9c 10859
5ab79981
PB		 10860 value = (signed_addend & howto->dst_mask)
10861 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10862
5ab79981
PB		 10863 if (r_type == R_ARM_CALL)
10864 {
155d87d7 10865 /* Set the H bit in the BLX instruction. */
35fc36a8 10866 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10867 {
10868 if (addend)
10869 value |= (1 << 24);
10870 else
10871 value &= ~(bfd_vma)(1 << 24);
10872 }
10873
5ab79981 10874 /* Select the correct instruction (BL or BLX). */
906e58ca 10875 /* Only if we are not handling a BL to a stub. In this
8029a119 10876 case, mode switching is performed by the stub. */
35fc36a8 10877 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10878 value |= (1 << 28);
63e1a0fc 10879 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10880 {
10881 value &= ~(bfd_vma)(1 << 28);
10882 value |= (1 << 24);
10883 }
39b41c9c
PB		 10884 }
10885 }
906e58ca 10886 }
252b5132 10887 break;
f21f3fe0 10888
252b5132
RH		 10889 case R_ARM_ABS32:
10890 value += addend;
35fc36a8 10891 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10892 value |= 1;
10893 break;
f21f3fe0 10894
bb224fc3
MS		 10895 case R_ARM_ABS32_NOI:
10896 value += addend;
10897 break;
10898
252b5132 10899 case R_ARM_REL32:
a8bc6c78 10900 value += addend;
35fc36a8 10901 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10902 value |= 1;
252b5132 10903 value -= (input_section->output_section->vma
62efb346 10904 + input_section->output_offset + rel->r_offset);
252b5132 10905 break;
eb043451 10906
bb224fc3
MS		 10907 case R_ARM_REL32_NOI:
10908 value += addend;
10909 value -= (input_section->output_section->vma
10910 + input_section->output_offset + rel->r_offset);
10911 break;
10912
eb043451
PB		 10913 case R_ARM_PREL31:
10914 value -= (input_section->output_section->vma
10915 + input_section->output_offset + rel->r_offset);
10916 value += signed_addend;
10917 if (! h || h->root.type != bfd_link_hash_undefweak)
10918 {
8029a119 10919 /* Check for overflow. */
eb043451
PB		 10920 if ((value ^ (value >> 1)) & (1 << 30))
10921 return bfd_reloc_overflow;
10922 }
10923 value &= 0x7fffffff;
10924 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10925 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10926 value |= 1;
10927 break;
252b5132 10928 }
f21f3fe0 10929
252b5132
RH		 10930 bfd_put_32 (input_bfd, value, hit_data);
10931 return bfd_reloc_ok;
10932
10933 case R_ARM_ABS8:
fd0fd00c
MJ		 10934 /* PR 16202: Refectch the addend using the correct size. */
10935 if (globals->use_rel)
10936 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10937 value += addend;
4e67d4ca
DG		 10938
10939 /* There is no way to tell whether the user intended to use a signed or
10940 unsigned addend. When checking for overflow we accept either,
10941 as specified by the AAELF. */
10942 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10943 return bfd_reloc_overflow;
10944
10945 bfd_put_8 (input_bfd, value, hit_data);
10946 return bfd_reloc_ok;
10947
10948 case R_ARM_ABS16:
fd0fd00c
MJ		 10949 /* PR 16202: Refectch the addend using the correct size. */
10950 if (globals->use_rel)
10951 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10952 value += addend;
10953
4e67d4ca
DG		 10954 /* See comment for R_ARM_ABS8. */
10955 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10956 return bfd_reloc_overflow;
10957
10958 bfd_put_16 (input_bfd, value, hit_data);
10959 return bfd_reloc_ok;
10960
252b5132 10961 case R_ARM_THM_ABS5:
9b485d32 10962 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10963 if (globals->use_rel)
10964 {
10965 /* Need to refetch addend. */
10966 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10967 /* ??? Need to determine shift amount from operand size. */
10968 addend >>= howto->rightshift;
10969 }
252b5132
RH		 10970 value += addend;
10971
10972 /* ??? Isn't value unsigned? */
10973 if ((long) value > 0x1f || (long) value < -0x10)
10974 return bfd_reloc_overflow;
10975
10976 /* ??? Value needs to be properly shifted into place first. */
10977 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10978 bfd_put_16 (input_bfd, value, hit_data);
10979 return bfd_reloc_ok;
10980
2cab6cc3
MS		 10981 case R_ARM_THM_ALU_PREL_11_0:
10982 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10983 {
10984 bfd_vma insn;
10985 bfd_signed_vma relocation;
10986
10987 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10988 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10989
99059e56
RM		 10990 if (globals->use_rel)
10991 {
10992 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10993 | ((insn & (1 << 26)) >> 15);
10994 if (insn & 0xf00000)
10995 signed_addend = -signed_addend;
10996 }
2cab6cc3
MS		 10997
10998 relocation = value + signed_addend;
79f08007 10999 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11000 + input_section->output_offset
11001 + rel->r_offset);
2cab6cc3 11002
8c65b54f
CS		 11003 /* PR 21523: Use an absolute value. The user of this reloc will
11004 have already selected an ADD or SUB insn appropriately. */
453f8e1e 11005 value = llabs (relocation);
2cab6cc3 11006
99059e56
RM		 11007 if (value >= 0x1000)
11008 return bfd_reloc_overflow;
2cab6cc3 11009
e645cf40
AG		 11010 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
11011 if (branch_type == ST_BRANCH_TO_THUMB)
11012 value |= 1;
11013
2cab6cc3 11014 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 11015 | ((value & 0x700) << 4)
11016 | ((value & 0x800) << 15);
11017 if (relocation < 0)
11018 insn |= 0xa00000;
2cab6cc3
MS		 11019
11020 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11021 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11022
99059e56 11023 return bfd_reloc_ok;
2cab6cc3
MS		 11024 }
11025
e1ec24c6
NC		 11026 case R_ARM_THM_PC8:
11027 /* PR 10073: This reloc is not generated by the GNU toolchain,
11028 but it is supported for compatibility with third party libraries
11029 generated by other compilers, specifically the ARM/IAR. */
11030 {
11031 bfd_vma insn;
11032 bfd_signed_vma relocation;
11033
11034 insn = bfd_get_16 (input_bfd, hit_data);
11035
99059e56 11036 if (globals->use_rel)
79f08007 11037 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 11038
11039 relocation = value + addend;
79f08007 11040 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11041 + input_section->output_offset
11042 + rel->r_offset);
e1ec24c6 11043
b6518b38 11044 value = relocation;
e1ec24c6
NC		 11045
11046 /* We do not check for overflow of this reloc. Although strictly
11047 speaking this is incorrect, it appears to be necessary in order
11048 to work with IAR generated relocs. Since GCC and GAS do not
11049 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11050 a problem for them. */
11051 value &= 0x3fc;
11052
11053 insn = (insn & 0xff00) | (value >> 2);
11054
11055 bfd_put_16 (input_bfd, insn, hit_data);
11056
99059e56 11057 return bfd_reloc_ok;
e1ec24c6
NC		 11058 }
11059
2cab6cc3
MS		 11060 case R_ARM_THM_PC12:
11061 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11062 {
11063 bfd_vma insn;
11064 bfd_signed_vma relocation;
11065
11066 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11067 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11068
99059e56
RM		 11069 if (globals->use_rel)
11070 {
11071 signed_addend = insn & 0xfff;
11072 if (!(insn & (1 << 23)))
11073 signed_addend = -signed_addend;
11074 }
2cab6cc3
MS		 11075
11076 relocation = value + signed_addend;
79f08007 11077 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11078 + input_section->output_offset
11079 + rel->r_offset);
2cab6cc3 11080
b6518b38 11081 value = relocation;
2cab6cc3 11082
99059e56
RM		 11083 if (value >= 0x1000)
11084 return bfd_reloc_overflow;
2cab6cc3
MS		 11085
11086 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11087 if (relocation >= 0)
11088 insn |= (1 << 23);
2cab6cc3
MS		 11089
11090 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11091 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11092
99059e56 11093 return bfd_reloc_ok;
2cab6cc3
MS		 11094 }
11095
dfc5f959 11096 case R_ARM_THM_XPC22:
c19d1205 11097 case R_ARM_THM_CALL:
bd97cb95 11098 case R_ARM_THM_JUMP24:
dfc5f959 11099 /* Thumb BL (branch long instruction). */
252b5132 11100 {
b34976b6 11101 bfd_vma relocation;
99059e56 11102 bfd_vma reloc_sign;
b34976b6
AM		 11103 bfd_boolean overflow = FALSE;
11104 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11105 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11106 bfd_signed_vma reloc_signed_max;
11107 bfd_signed_vma reloc_signed_min;
b34976b6 11108 bfd_vma check;
252b5132 11109 bfd_signed_vma signed_check;
e95de063 11110 int bitsize;
cd1dac3d 11111 const int thumb2 = using_thumb2 (globals);
5e866f5a 11112 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11113
5ab79981 11114 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11115 the next instruction unless a PLT entry will be created.
11116 The jump to the next instruction is optimized as a NOP.W for
11117 Thumb-2 enabled architectures. */
19540007 11118 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11119 && plt_offset == (bfd_vma) -1)
5ab79981 11120 {
60a019a0 11121 if (thumb2)
cd1dac3d
DG		 11122 {
11123 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11124 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11125 }
11126 else
11127 {
11128 bfd_put_16 (input_bfd, 0xe000, hit_data);
11129 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11130 }
5ab79981
PB		 11131 return bfd_reloc_ok;
11132 }
11133
e95de063 11134 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11135 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11136 if (globals->use_rel)
11137 {
99059e56
RM		 11138 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11139 bfd_vma upper = upper_insn & 0x3ff;
11140 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11141 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11142 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11143 bfd_vma i1 = j1 ^ s ? 0 : 1;
11144 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11145
99059e56
RM		 11146 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11147 /* Sign extend. */
11148 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11149
4e7fd91e
PB		 11150 signed_addend = addend;
11151 }
cb1afa5c 11152
dfc5f959
NC		 11153 if (r_type == R_ARM_THM_XPC22)
11154 {
11155 /* Check for Thumb to Thumb call. */
11156 /* FIXME: Should we translate the instruction into a BL
11157 instruction instead ? */
35fc36a8 11158 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11159 _bfd_error_handler
90b6238f
AM		 11160 (_("%pB: warning: %s BLX instruction targets"
11161 " %s function '%s'"),
11162 input_bfd, "Thumb",
11163 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11164 }
11165 else
252b5132 11166 {
dfc5f959
NC		 11167 /* If it is not a call to Thumb, assume call to Arm.
11168 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11169 function call at all, but rather a long jump. Calls through
11170 the PLT do not require stubs. */
34e77a92 11171 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11172 {
bd97cb95 11173 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11174 {
11175 /* Convert BL to BLX. */
11176 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11177 }
155d87d7
CL		 11178 else if (( r_type != R_ARM_THM_CALL)
11179 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11180 {
11181 if (elf32_thumb_to_arm_stub
11182 (info, sym_name, input_bfd, output_bfd, input_section,
11183 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11184 error_message))
11185 return bfd_reloc_ok;
11186 else
11187 return bfd_reloc_dangerous;
11188 }
da5938a2 11189 }
35fc36a8
RS		 11190 else if (branch_type == ST_BRANCH_TO_THUMB
11191 && globals->use_blx
bd97cb95 11192 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11193 {
11194 /* Make sure this is a BL. */
11195 lower_insn |= 0x1800;
11196 }
252b5132 11197 }
f21f3fe0 11198
fe33d2fa 11199 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11200 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11201 {
11202 /* Check if a stub has to be inserted because the destination
8029a119 11203 is too far. */
fe33d2fa
CL		 11204 struct elf32_arm_stub_hash_entry *stub_entry;
11205 struct elf32_arm_link_hash_entry *hash;
11206
11207 hash = (struct elf32_arm_link_hash_entry *) h;
11208
11209 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11210 st_type, &branch_type,
11211 hash, value, sym_sec,
fe33d2fa
CL		 11212 input_bfd, sym_name);
11213
11214 if (stub_type != arm_stub_none)
906e58ca
NC		 11215 {
11216 /* The target is out of reach or we are changing modes, so
11217 redirect the branch to the local stub for this
11218 function. */
11219 stub_entry = elf32_arm_get_stub_entry (input_section,
11220 sym_sec, h,
fe33d2fa
CL		 11221 rel, globals,
11222 stub_type);
906e58ca 11223 if (stub_entry != NULL)
9cd3e4e5
NC		 11224 {
11225 value = (stub_entry->stub_offset
11226 + stub_entry->stub_sec->output_offset
11227 + stub_entry->stub_sec->output_section->vma);
11228
11229 if (plt_offset != (bfd_vma) -1)
11230 *unresolved_reloc_p = FALSE;
11231 }
906e58ca 11232
f4ac8484 11233 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11234 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11235 {
11236 if ((stub_entry
11237 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11238 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11239 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11240 }
906e58ca
NC		 11241 }
11242 }
11243
fe33d2fa 11244 /* Handle calls via the PLT. */
34e77a92 11245 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11246 {
11247 value = (splt->output_section->vma
11248 + splt->output_offset
34e77a92 11249 + plt_offset);
fe33d2fa 11250
eed94f8f
NC		 11251 if (globals->use_blx
11252 && r_type == R_ARM_THM_CALL
11253 && ! using_thumb_only (globals))
fe33d2fa
CL		 11254 {
11255 /* If the Thumb BLX instruction is available, convert
11256 the BL to a BLX instruction to call the ARM-mode
11257 PLT entry. */
11258 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11259 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11260 }
11261 else
11262 {
eed94f8f
NC		 11263 if (! using_thumb_only (globals))
11264 /* Target the Thumb stub before the ARM PLT entry. */
11265 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11266 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11267 }
11268 *unresolved_reloc_p = FALSE;
11269 }
11270
ba96a88f 11271 relocation = value + signed_addend;
f21f3fe0 11272
252b5132 11273 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11274 + input_section->output_offset
11275 + rel->r_offset);
9a5aca8c 11276
252b5132
RH		 11277 check = relocation >> howto->rightshift;
11278
11279 /* If this is a signed value, the rightshift just dropped
11280 leading 1 bits (assuming twos complement). */
11281 if ((bfd_signed_vma) relocation >= 0)
11282 signed_check = check;
11283 else
11284 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11285
e95de063
MS		 11286 /* Calculate the permissable maximum and minimum values for
11287 this relocation according to whether we're relocating for
11288 Thumb-2 or not. */
11289 bitsize = howto->bitsize;
5e866f5a 11290 if (!thumb2_bl)
e95de063 11291 bitsize -= 2;
f6ebfac0 11292 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11293 reloc_signed_min = ~reloc_signed_max;
11294
252b5132 11295 /* Assumes two's complement. */
ba96a88f 11296 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11297 overflow = TRUE;
252b5132 11298
bd97cb95 11299 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11300 /* For a BLX instruction, make sure that the relocation is rounded up
11301 to a word boundary. This follows the semantics of the instruction
11302 which specifies that bit 1 of the target address will come from bit
11303 1 of the base address. */
11304 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11305
e95de063
MS		 11306 /* Put RELOCATION back into the insn. Assumes two's complement.
11307 We use the Thumb-2 encoding, which is safe even if dealing with
11308 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11309 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11310 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11311 | ((relocation >> 12) & 0x3ff)
11312 | (reloc_sign << 10);
906e58ca 11313 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11314 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11315 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11316 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11317
252b5132
RH		 11318 /* Put the relocated value back in the object file: */
11319 bfd_put_16 (input_bfd, upper_insn, hit_data);
11320 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11321
11322 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11323 }
11324 break;
11325
c19d1205
ZW		 11326 case R_ARM_THM_JUMP19:
11327 /* Thumb32 conditional branch instruction. */
11328 {
11329 bfd_vma relocation;
11330 bfd_boolean overflow = FALSE;
11331 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11332 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11333 bfd_signed_vma reloc_signed_max = 0xffffe;
11334 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11335 bfd_signed_vma signed_check;
07d6d2b8 11336 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11337 struct elf32_arm_stub_hash_entry *stub_entry;
11338 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11339
11340 /* Need to refetch the addend, reconstruct the top three bits,
11341 and squish the two 11 bit pieces together. */
11342 if (globals->use_rel)
11343 {
11344 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11345 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11346 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11347 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11348 bfd_vma lower = (lower_insn & 0x07ff);
11349
a00a1f35
MS		 11350 upper |= J1 << 6;
11351 upper |= J2 << 7;
11352 upper |= (!S) << 8;
c19d1205
ZW		 11353 upper -= 0x0100; /* Sign extend. */
11354
11355 addend = (upper << 12) | (lower << 1);
11356 signed_addend = addend;
11357 }
11358
bd97cb95 11359 /* Handle calls via the PLT. */
34e77a92 11360 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11361 {
11362 value = (splt->output_section->vma
11363 + splt->output_offset
34e77a92 11364 + plt_offset);
bd97cb95
DJ		 11365 /* Target the Thumb stub before the ARM PLT entry. */
11366 value -= PLT_THUMB_STUB_SIZE;
11367 *unresolved_reloc_p = FALSE;
11368 }
11369
c5423981
TG		 11370 hash = (struct elf32_arm_link_hash_entry *)h;
11371
11372 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11373 st_type, &branch_type,
11374 hash, value, sym_sec,
11375 input_bfd, sym_name);
c5423981
TG		 11376 if (stub_type != arm_stub_none)
11377 {
11378 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11379 sym_sec, h,
11380 rel, globals,
11381 stub_type);
c5423981
TG		 11382 if (stub_entry != NULL)
11383 {
07d6d2b8
AM		 11384 value = (stub_entry->stub_offset
11385 + stub_entry->stub_sec->output_offset
11386 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11387 }
11388 }
c19d1205 11389
99059e56 11390 relocation = value + signed_addend;
c19d1205
ZW		 11391 relocation -= (input_section->output_section->vma
11392 + input_section->output_offset
11393 + rel->r_offset);
a00a1f35 11394 signed_check = (bfd_signed_vma) relocation;
c19d1205 11395
c19d1205
ZW		 11396 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11397 overflow = TRUE;
11398
11399 /* Put RELOCATION back into the insn. */
11400 {
11401 bfd_vma S = (relocation & 0x00100000) >> 20;
11402 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11403 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11404 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11405 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11406
a00a1f35 11407 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11408 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11409 }
11410
11411 /* Put the relocated value back in the object file: */
11412 bfd_put_16 (input_bfd, upper_insn, hit_data);
11413 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11414
11415 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11416 }
11417
11418 case R_ARM_THM_JUMP11:
11419 case R_ARM_THM_JUMP8:
11420 case R_ARM_THM_JUMP6:
51c5503b
NC		 11421 /* Thumb B (branch) instruction). */
11422 {
6cf9e9fe 11423 bfd_signed_vma relocation;
51c5503b
NC		 11424 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11425 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11426 bfd_signed_vma signed_check;
11427
c19d1205
ZW		 11428 /* CZB cannot jump backward. */
11429 if (r_type == R_ARM_THM_JUMP6)
11430 reloc_signed_min = 0;
11431
4e7fd91e 11432 if (globals->use_rel)
6cf9e9fe 11433 {
4e7fd91e
PB		 11434 /* Need to refetch addend. */
11435 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11436 if (addend & ((howto->src_mask + 1) >> 1))
11437 {
11438 signed_addend = -1;
11439 signed_addend &= ~ howto->src_mask;
11440 signed_addend |= addend;
11441 }
11442 else
11443 signed_addend = addend;
11444 /* The value in the insn has been right shifted. We need to
11445 undo this, so that we can perform the address calculation
11446 in terms of bytes. */
11447 signed_addend <<= howto->rightshift;
6cf9e9fe 11448 }
6cf9e9fe 11449 relocation = value + signed_addend;
51c5503b
NC		 11450
11451 relocation -= (input_section->output_section->vma
11452 + input_section->output_offset
11453 + rel->r_offset);
11454
6cf9e9fe
NC		 11455 relocation >>= howto->rightshift;
11456 signed_check = relocation;
c19d1205
ZW		 11457
11458 if (r_type == R_ARM_THM_JUMP6)
11459 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11460 else
11461 relocation &= howto->dst_mask;
51c5503b 11462 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11463
51c5503b
NC		 11464 bfd_put_16 (input_bfd, relocation, hit_data);
11465
11466 /* Assumes two's complement. */
11467 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11468 return bfd_reloc_overflow;
11469
11470 return bfd_reloc_ok;
11471 }
cedb70c5 11472
8375c36b
PB		 11473 case R_ARM_ALU_PCREL7_0:
11474 case R_ARM_ALU_PCREL15_8:
11475 case R_ARM_ALU_PCREL23_15:
11476 {
11477 bfd_vma insn;
11478 bfd_vma relocation;
11479
11480 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11481 if (globals->use_rel)
11482 {
11483 /* Extract the addend. */
11484 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11485 signed_addend = addend;
11486 }
8375c36b
PB		 11487 relocation = value + signed_addend;
11488
11489 relocation -= (input_section->output_section->vma
11490 + input_section->output_offset
11491 + rel->r_offset);
11492 insn = (insn & ~0xfff)
11493 | ((howto->bitpos << 7) & 0xf00)
11494 | ((relocation >> howto->bitpos) & 0xff);
11495 bfd_put_32 (input_bfd, value, hit_data);
11496 }
11497 return bfd_reloc_ok;
11498
252b5132
RH		 11499 case R_ARM_GNU_VTINHERIT:
11500 case R_ARM_GNU_VTENTRY:
11501 return bfd_reloc_ok;
11502
c19d1205 11503 case R_ARM_GOTOFF32:
252b5132 11504 /* Relocation is relative to the start of the
99059e56 11505 global offset table. */
252b5132
RH		 11506
11507 BFD_ASSERT (sgot != NULL);
11508 if (sgot == NULL)
99059e56 11509 return bfd_reloc_notsupported;
9a5aca8c 11510
cedb70c5 11511 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11512 address by one, so that attempts to call the function pointer will
11513 correctly interpret it as Thumb code. */
35fc36a8 11514 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11515 value += 1;
11516
252b5132 11517 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11518 calculation. We always want the start of .got. If we
11519 define _GLOBAL_OFFSET_TABLE in a different way, as is
11520 permitted by the ABI, we might have to change this
11521 calculation. */
252b5132 11522 value -= sgot->output_section->vma;
f21f3fe0 11523 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11524 contents, rel->r_offset, value,
00a97672 11525 rel->r_addend);
252b5132
RH		 11526
11527 case R_ARM_GOTPC:
a7c10850 11528 /* Use global offset table as symbol value. */
252b5132 11529 BFD_ASSERT (sgot != NULL);
f21f3fe0 11530
252b5132 11531 if (sgot == NULL)
99059e56 11532 return bfd_reloc_notsupported;
252b5132 11533
0945cdfd 11534 *unresolved_reloc_p = FALSE;
252b5132 11535 value = sgot->output_section->vma;
f21f3fe0 11536 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11537 contents, rel->r_offset, value,
00a97672 11538 rel->r_addend);
f21f3fe0 11539
252b5132 11540 case R_ARM_GOT32:
eb043451 11541 case R_ARM_GOT_PREL:
252b5132 11542 /* Relocation is to the entry for this symbol in the
99059e56 11543 global offset table. */
252b5132
RH		 11544 if (sgot == NULL)
11545 return bfd_reloc_notsupported;
f21f3fe0 11546
34e77a92
RS		 11547 if (dynreloc_st_type == STT_GNU_IFUNC
11548 && plt_offset != (bfd_vma) -1
11549 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11550 {
11551 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11552 symbol, and the relocation resolves directly to the runtime
11553 target rather than to the .iplt entry. This means that any
11554 .got entry would be the same value as the .igot.plt entry,
11555 so there's no point creating both. */
11556 sgot = globals->root.igotplt;
11557 value = sgot->output_offset + gotplt_offset;
11558 }
11559 else if (h != NULL)
252b5132
RH		 11560 {
11561 bfd_vma off;
f21f3fe0 11562
252b5132
RH		 11563 off = h->got.offset;
11564 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11565 if ((off & 1) != 0)
252b5132 11566 {
b436d854
RS		 11567 /* We have already processsed one GOT relocation against
11568 this symbol. */
11569 off &= ~1;
11570 if (globals->root.dynamic_sections_created
11571 && !SYMBOL_REFERENCES_LOCAL (info, h))
11572 *unresolved_reloc_p = FALSE;
11573 }
11574 else
11575 {
11576 Elf_Internal_Rela outrel;
e8b09b87 11577 int isrofixup = 0;
b436d854 11578
e8b09b87
CL		 11579 if (((h->dynindx != -1) || globals->fdpic_p)
11580 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11581 {
11582 /* If the symbol doesn't resolve locally in a static
11583 object, we have an undefined reference. If the
11584 symbol doesn't resolve locally in a dynamic object,
11585 it should be resolved by the dynamic linker. */
11586 if (globals->root.dynamic_sections_created)
11587 {
11588 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11589 *unresolved_reloc_p = FALSE;
11590 }
11591 else
11592 outrel.r_info = 0;
11593 outrel.r_addend = 0;
11594 }
252b5132
RH		 11595 else
11596 {
34e77a92 11597 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11598 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11599 else if (bfd_link_pic (info)
11600 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11601 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11602 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11603 else
2376f038
EB		 11604 {
11605 outrel.r_info = 0;
11606 if (globals->fdpic_p)
11607 isrofixup = 1;
11608 }
34e77a92 11609 outrel.r_addend = dynreloc_value;
b436d854 11610 }
ee29b9fb 11611
b436d854
RS		 11612 /* The GOT entry is initialized to zero by default.
11613 See if we should install a different value. */
11614 if (outrel.r_addend != 0
2376f038 11615 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11616 {
11617 bfd_put_32 (output_bfd, outrel.r_addend,
11618 sgot->contents + off);
11619 outrel.r_addend = 0;
252b5132 11620 }
f21f3fe0 11621
2376f038
EB		 11622 if (isrofixup)
11623 arm_elf_add_rofixup (output_bfd,
11624 elf32_arm_hash_table(info)->srofixup,
11625 sgot->output_section->vma
11626 + sgot->output_offset + off);
11627
11628 else if (outrel.r_info != 0)
b436d854
RS		 11629 {
11630 outrel.r_offset = (sgot->output_section->vma
11631 + sgot->output_offset
11632 + off);
11633 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11634 }
2376f038 11635
b436d854
RS		 11636 h->got.offset |= 1;
11637 }
252b5132
RH		 11638 value = sgot->output_offset + off;
11639 }
11640 else
11641 {
11642 bfd_vma off;
f21f3fe0 11643
5025eb7c
AO		 11644 BFD_ASSERT (local_got_offsets != NULL
11645 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11646
252b5132 11647 off = local_got_offsets[r_symndx];
f21f3fe0 11648
252b5132
RH		 11649 /* The offset must always be a multiple of 4. We use the
11650 least significant bit to record whether we have already
9b485d32 11651 generated the necessary reloc. */
252b5132
RH		 11652 if ((off & 1) != 0)
11653 off &= ~1;
11654 else
11655 {
2376f038
EB		 11656 Elf_Internal_Rela outrel;
11657 int isrofixup = 0;
f21f3fe0 11658
2376f038
EB		 11659 if (dynreloc_st_type == STT_GNU_IFUNC)
11660 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11661 else if (bfd_link_pic (info))
11662 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11663 else
252b5132 11664 {
2376f038
EB		 11665 outrel.r_info = 0;
11666 if (globals->fdpic_p)
11667 isrofixup = 1;
11668 }
11669
11670 /* The GOT entry is initialized to zero by default.
11671 See if we should install a different value. */
11672 if (globals->use_rel || outrel.r_info == 0)
11673 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11674
11675 if (isrofixup)
11676 arm_elf_add_rofixup (output_bfd,
11677 globals->srofixup,
11678 sgot->output_section->vma
11679 + sgot->output_offset + off);
f21f3fe0 11680
2376f038
EB		 11681 else if (outrel.r_info != 0)
11682 {
34e77a92 11683 outrel.r_addend = addend + dynreloc_value;
252b5132 11684 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11685 + sgot->output_offset
252b5132 11686 + off);
47beaa6a 11687 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11688 }
f21f3fe0 11689
252b5132
RH		 11690 local_got_offsets[r_symndx] |= 1;
11691 }
f21f3fe0 11692
252b5132
RH		 11693 value = sgot->output_offset + off;
11694 }
eb043451
PB		 11695 if (r_type != R_ARM_GOT32)
11696 value += sgot->output_section->vma;
9a5aca8c 11697
f21f3fe0 11698 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11699 contents, rel->r_offset, value,
00a97672 11700 rel->r_addend);
f21f3fe0 11701
ba93b8ac
DJ		 11702 case R_ARM_TLS_LDO32:
11703 value = value - dtpoff_base (info);
11704
11705 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11706 contents, rel->r_offset, value,
11707 rel->r_addend);
ba93b8ac
DJ		 11708
11709 case R_ARM_TLS_LDM32:
5c5a4843 11710 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11711 {
11712 bfd_vma off;
11713
362d30a1 11714 if (sgot == NULL)
ba93b8ac
DJ		 11715 abort ();
11716
11717 off = globals->tls_ldm_got.offset;
11718
11719 if ((off & 1) != 0)
11720 off &= ~1;
11721 else
11722 {
11723 /* If we don't know the module number, create a relocation
11724 for it. */
0e1862bb 11725 if (bfd_link_pic (info))
ba93b8ac
DJ		 11726 {
11727 Elf_Internal_Rela outrel;
ba93b8ac 11728
362d30a1 11729 if (srelgot == NULL)
ba93b8ac
DJ		 11730 abort ();
11731
00a97672 11732 outrel.r_addend = 0;
362d30a1
RS		 11733 outrel.r_offset = (sgot->output_section->vma
11734 + sgot->output_offset + off);
ba93b8ac
DJ		 11735 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11736
00a97672
RS		 11737 if (globals->use_rel)
11738 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11739 sgot->contents + off);
ba93b8ac 11740
47beaa6a 11741 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11742 }
11743 else
362d30a1 11744 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11745
11746 globals->tls_ldm_got.offset |= 1;
11747 }
11748
5c5a4843 11749 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11750 {
11751 bfd_put_32(output_bfd,
11752 globals->root.sgot->output_offset + off,
11753 contents + rel->r_offset);
11754
11755 return bfd_reloc_ok;
11756 }
11757 else
11758 {
11759 value = sgot->output_section->vma + sgot->output_offset + off
11760 - (input_section->output_section->vma
11761 + input_section->output_offset + rel->r_offset);
ba93b8ac 11762
e8b09b87
CL		 11763 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11764 contents, rel->r_offset, value,
11765 rel->r_addend);
11766 }
ba93b8ac
DJ		 11767 }
11768
0855e32b
NS		 11769 case R_ARM_TLS_CALL:
11770 case R_ARM_THM_TLS_CALL:
ba93b8ac 11771 case R_ARM_TLS_GD32:
5c5a4843 11772 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11773 case R_ARM_TLS_IE32:
5c5a4843 11774 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11775 case R_ARM_TLS_GOTDESC:
11776 case R_ARM_TLS_DESCSEQ:
11777 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11778 {
0855e32b
NS		 11779 bfd_vma off, offplt;
11780 int indx = 0;
ba93b8ac
DJ		 11781 char tls_type;
11782
0855e32b 11783 BFD_ASSERT (sgot != NULL);
ba93b8ac 11784
ba93b8ac
DJ		 11785 if (h != NULL)
11786 {
11787 bfd_boolean dyn;
11788 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11789 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11790 bfd_link_pic (info),
11791 h)
11792 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11793 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11794 {
11795 *unresolved_reloc_p = FALSE;
11796 indx = h->dynindx;
11797 }
11798 off = h->got.offset;
0855e32b 11799 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11800 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11801 }
11802 else
11803 {
0855e32b 11804 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11805 off = local_got_offsets[r_symndx];
0855e32b 11806 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11807 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11808 }
11809
0855e32b 11810 /* Linker relaxations happens from one of the
b38cadfb 11811 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11812 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11813 tls_type = GOT_TLS_IE;
0855e32b
NS		 11814
11815 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11816
11817 if ((off & 1) != 0)
11818 off &= ~1;
11819 else
11820 {
11821 bfd_boolean need_relocs = FALSE;
11822 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11823 int cur_off = off;
11824
11825 /* The GOT entries have not been initialized yet. Do it
11826 now, and emit any relocations. If both an IE GOT and a
11827 GD GOT are necessary, we emit the GD first. */
11828
0e1862bb 11829 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11830 && (h == NULL
95b03e4a
L		 11831 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11832 && !resolved_to_zero)
ba93b8ac
DJ		 11833 || h->root.type != bfd_link_hash_undefweak))
11834 {
11835 need_relocs = TRUE;
0855e32b 11836 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11837 }
11838
0855e32b
NS		 11839 if (tls_type & GOT_TLS_GDESC)
11840 {
47beaa6a
RS		 11841 bfd_byte *loc;
11842
0855e32b
NS		 11843 /* We should have relaxed, unless this is an undefined
11844 weak symbol. */
11845 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11846 || bfd_link_pic (info));
0855e32b 11847 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11848 <= globals->root.sgotplt->size);
0855e32b
NS		 11849
11850 outrel.r_addend = 0;
11851 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11852 + globals->root.sgotplt->output_offset
11853 + offplt
11854 + globals->sgotplt_jump_table_size);
b38cadfb 11855
0855e32b
NS		 11856 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11857 sreloc = globals->root.srelplt;
11858 loc = sreloc->contents;
11859 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11860 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11861 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11862
11863 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11864
11865 /* For globals, the first word in the relocation gets
11866 the relocation index and the top bit set, or zero,
11867 if we're binding now. For locals, it gets the
11868 symbol's offset in the tls section. */
99059e56 11869 bfd_put_32 (output_bfd,
0855e32b
NS		 11870 !h ? value - elf_hash_table (info)->tls_sec->vma
11871 : info->flags & DF_BIND_NOW ? 0
11872 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11873 globals->root.sgotplt->contents + offplt
11874 + globals->sgotplt_jump_table_size);
11875
0855e32b 11876 /* Second word in the relocation is always zero. */
99059e56 11877 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11878 globals->root.sgotplt->contents + offplt
11879 + globals->sgotplt_jump_table_size + 4);
0855e32b 11880 }
ba93b8ac
DJ		 11881 if (tls_type & GOT_TLS_GD)
11882 {
11883 if (need_relocs)
11884 {
00a97672 11885 outrel.r_addend = 0;
362d30a1
RS		 11886 outrel.r_offset = (sgot->output_section->vma
11887 + sgot->output_offset
00a97672 11888 + cur_off);
ba93b8ac 11889 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11890
00a97672
RS		 11891 if (globals->use_rel)
11892 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11893 sgot->contents + cur_off);
00a97672 11894
47beaa6a 11895 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11896
11897 if (indx == 0)
11898 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11899 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11900 else
11901 {
00a97672 11902 outrel.r_addend = 0;
ba93b8ac
DJ		 11903 outrel.r_info = ELF32_R_INFO (indx,
11904 R_ARM_TLS_DTPOFF32);
11905 outrel.r_offset += 4;
00a97672
RS		 11906
11907 if (globals->use_rel)
11908 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11909 sgot->contents + cur_off + 4);
00a97672 11910
47beaa6a
RS		 11911 elf32_arm_add_dynreloc (output_bfd, info,
11912 srelgot, &outrel);
ba93b8ac
DJ		 11913 }
11914 }
11915 else
11916 {
11917 /* If we are not emitting relocations for a
11918 general dynamic reference, then we must be in a
11919 static link or an executable link with the
11920 symbol binding locally. Mark it as belonging
11921 to module 1, the executable. */
11922 bfd_put_32 (output_bfd, 1,
362d30a1 11923 sgot->contents + cur_off);
ba93b8ac 11924 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11925 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11926 }
11927
11928 cur_off += 8;
11929 }
11930
11931 if (tls_type & GOT_TLS_IE)
11932 {
11933 if (need_relocs)
11934 {
00a97672
RS		 11935 if (indx == 0)
11936 outrel.r_addend = value - dtpoff_base (info);
11937 else
11938 outrel.r_addend = 0;
362d30a1
RS		 11939 outrel.r_offset = (sgot->output_section->vma
11940 + sgot->output_offset
ba93b8ac
DJ		 11941 + cur_off);
11942 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11943
00a97672
RS		 11944 if (globals->use_rel)
11945 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11946 sgot->contents + cur_off);
ba93b8ac 11947
47beaa6a 11948 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11949 }
11950 else
11951 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11952 sgot->contents + cur_off);
ba93b8ac
DJ		 11953 cur_off += 4;
11954 }
11955
11956 if (h != NULL)
11957 h->got.offset |= 1;
11958 else
11959 local_got_offsets[r_symndx] |= 1;
11960 }
11961
5c5a4843 11962 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11963 off += 8;
0855e32b
NS		 11964 else if (tls_type & GOT_TLS_GDESC)
11965 off = offplt;
11966
11967 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11968 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11969 {
11970 bfd_signed_vma offset;
12352d3f
PB		 11971 /* TLS stubs are arm mode. The original symbol is a
11972 data object, so branch_type is bogus. */
11973 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11974 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11975 = arm_type_of_stub (info, input_section, rel,
11976 st_type, &branch_type,
0855e32b
NS		 11977 (struct elf32_arm_link_hash_entry *)h,
11978 globals->tls_trampoline, globals->root.splt,
11979 input_bfd, sym_name);
11980
11981 if (stub_type != arm_stub_none)
11982 {
11983 struct elf32_arm_stub_hash_entry *stub_entry
11984 = elf32_arm_get_stub_entry
11985 (input_section, globals->root.splt, 0, rel,
11986 globals, stub_type);
11987 offset = (stub_entry->stub_offset
11988 + stub_entry->stub_sec->output_offset
11989 + stub_entry->stub_sec->output_section->vma);
11990 }
11991 else
11992 offset = (globals->root.splt->output_section->vma
11993 + globals->root.splt->output_offset
11994 + globals->tls_trampoline);
11995
11996 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11997 {
11998 unsigned long inst;
b38cadfb
NC		 11999
12000 offset -= (input_section->output_section->vma
12001 + input_section->output_offset
12002 + rel->r_offset + 8);
0855e32b
NS		 12003
12004 inst = offset >> 2;
12005 inst &= 0x00ffffff;
12006 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
12007 }
12008 else
12009 {
12010 /* Thumb blx encodes the offset in a complicated
12011 fashion. */
12012 unsigned upper_insn, lower_insn;
12013 unsigned neg;
12014
b38cadfb
NC		 12015 offset -= (input_section->output_section->vma
12016 + input_section->output_offset
0855e32b 12017 + rel->r_offset + 4);
b38cadfb 12018
12352d3f
PB		 12019 if (stub_type != arm_stub_none
12020 && arm_stub_is_thumb (stub_type))
12021 {
12022 lower_insn = 0xd000;
12023 }
12024 else
12025 {
12026 lower_insn = 0xc000;
6a631e86 12027 /* Round up the offset to a word boundary. */
12352d3f
PB		 12028 offset = (offset + 2) & ~2;
12029 }
12030
0855e32b
NS		 12031 neg = offset < 0;
12032 upper_insn = (0xf000
12033 | ((offset >> 12) & 0x3ff)
12034 | (neg << 10));
12352d3f 12035 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 12036 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 12037 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 12038 bfd_put_16 (input_bfd, upper_insn, hit_data);
12039 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12040 return bfd_reloc_ok;
12041 }
12042 }
12043 /* These relocations needs special care, as besides the fact
12044 they point somewhere in .gotplt, the addend must be
12045 adjusted accordingly depending on the type of instruction
6a631e86 12046 we refer to. */
0855e32b
NS		 12047 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
12048 {
12049 unsigned long data, insn;
12050 unsigned thumb;
b38cadfb 12051
0855e32b
NS		 12052 data = bfd_get_32 (input_bfd, hit_data);
12053 thumb = data & 1;
12054 data &= ~1u;
b38cadfb 12055
0855e32b
NS		 12056 if (thumb)
12057 {
12058 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
12059 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
12060 insn = (insn << 16)
12061 | bfd_get_16 (input_bfd,
12062 contents + rel->r_offset - data + 2);
12063 if ((insn & 0xf800c000) == 0xf000c000)
12064 /* bl/blx */
12065 value = -6;
12066 else if ((insn & 0xffffff00) == 0x4400)
12067 /* add */
12068 value = -5;
12069 else
12070 {
4eca0228 12071 _bfd_error_handler
695344c0 12072 /* xgettext:c-format */
2dcf00ce 12073 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12074 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12075 "referenced by TLS_GOTDESC"),
12076 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12077 "Thumb", insn);
0855e32b
NS		 12078 return bfd_reloc_notsupported;
12079 }
12080 }
12081 else
12082 {
12083 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12084
12085 switch (insn >> 24)
12086 {
12087 case 0xeb: /* bl */
12088 case 0xfa: /* blx */
12089 value = -4;
12090 break;
12091
12092 case 0xe0: /* add */
12093 value = -8;
12094 break;
b38cadfb 12095
0855e32b 12096 default:
4eca0228 12097 _bfd_error_handler
695344c0 12098 /* xgettext:c-format */
2dcf00ce 12099 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12100 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12101 "referenced by TLS_GOTDESC"),
12102 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12103 "ARM", insn);
0855e32b
NS		 12104 return bfd_reloc_notsupported;
12105 }
12106 }
b38cadfb 12107
0855e32b
NS		 12108 value += ((globals->root.sgotplt->output_section->vma
12109 + globals->root.sgotplt->output_offset + off)
12110 - (input_section->output_section->vma
12111 + input_section->output_offset
12112 + rel->r_offset)
12113 + globals->sgotplt_jump_table_size);
12114 }
12115 else
12116 value = ((globals->root.sgot->output_section->vma
12117 + globals->root.sgot->output_offset + off)
12118 - (input_section->output_section->vma
12119 + input_section->output_offset + rel->r_offset));
ba93b8ac 12120
5c5a4843
CL		 12121 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12122 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12123 {
12124 /* For FDPIC relocations, resolve to the offset of the GOT
12125 entry from the start of GOT. */
12126 bfd_put_32(output_bfd,
12127 globals->root.sgot->output_offset + off,
12128 contents + rel->r_offset);
12129
12130 return bfd_reloc_ok;
12131 }
12132 else
12133 {
12134 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12135 contents, rel->r_offset, value,
12136 rel->r_addend);
12137 }
ba93b8ac
DJ		 12138 }
12139
12140 case R_ARM_TLS_LE32:
3cbc1e5e 12141 if (bfd_link_dll (info))
ba93b8ac 12142 {
4eca0228 12143 _bfd_error_handler
695344c0 12144 /* xgettext:c-format */
2dcf00ce
AM		 12145 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12146 "in shared object"),
12147 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12148 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12149 }
12150 else
12151 value = tpoff (info, value);
906e58ca 12152
ba93b8ac 12153 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12154 contents, rel->r_offset, value,
12155 rel->r_addend);
ba93b8ac 12156
319850b4
JB		 12157 case R_ARM_V4BX:
12158 if (globals->fix_v4bx)
845b51d6
PB		 12159 {
12160 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12161
845b51d6
PB		 12162 /* Ensure that we have a BX instruction. */
12163 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12164
845b51d6
PB		 12165 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12166 {
12167 /* Branch to veneer. */
12168 bfd_vma glue_addr;
12169 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12170 glue_addr -= input_section->output_section->vma
12171 + input_section->output_offset
12172 + rel->r_offset + 8;
12173 insn = (insn & 0xf0000000) | 0x0a000000
12174 | ((glue_addr >> 2) & 0x00ffffff);
12175 }
12176 else
12177 {
12178 /* Preserve Rm (lowest four bits) and the condition code
12179 (highest four bits). Other bits encode MOV PC,Rm. */
12180 insn = (insn & 0xf000000f) | 0x01a0f000;
12181 }
319850b4 12182
845b51d6
PB		 12183 bfd_put_32 (input_bfd, insn, hit_data);
12184 }
319850b4
JB		 12185 return bfd_reloc_ok;
12186
b6895b4f
PB		 12187 case R_ARM_MOVW_ABS_NC:
12188 case R_ARM_MOVT_ABS:
12189 case R_ARM_MOVW_PREL_NC:
12190 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12191 /* Until we properly support segment-base-relative addressing then
12192 we assume the segment base to be zero, as for the group relocations.
12193 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12194 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12195 case R_ARM_MOVW_BREL_NC:
12196 case R_ARM_MOVW_BREL:
12197 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12198 {
12199 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12200
12201 if (globals->use_rel)
12202 {
12203 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12204 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12205 }
92f5d02b 12206
b6895b4f 12207 value += signed_addend;
b6895b4f
PB		 12208
12209 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12210 value -= (input_section->output_section->vma
12211 + input_section->output_offset + rel->r_offset);
12212
92f5d02b 12213 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12214 return bfd_reloc_overflow;
92f5d02b 12215
35fc36a8 12216 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12217 value |= 1;
12218
12219 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12220 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12221 value >>= 16;
12222
12223 insn &= 0xfff0f000;
12224 insn |= value & 0xfff;
12225 insn |= (value & 0xf000) << 4;
12226 bfd_put_32 (input_bfd, insn, hit_data);
12227 }
12228 return bfd_reloc_ok;
12229
12230 case R_ARM_THM_MOVW_ABS_NC:
12231 case R_ARM_THM_MOVT_ABS:
12232 case R_ARM_THM_MOVW_PREL_NC:
12233 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12234 /* Until we properly support segment-base-relative addressing then
12235 we assume the segment base to be zero, as for the above relocations.
12236 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12237 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12238 as R_ARM_THM_MOVT_ABS. */
12239 case R_ARM_THM_MOVW_BREL_NC:
12240 case R_ARM_THM_MOVW_BREL:
12241 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12242 {
12243 bfd_vma insn;
906e58ca 12244
b6895b4f
PB		 12245 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12246 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12247
12248 if (globals->use_rel)
12249 {
12250 addend = ((insn >> 4) & 0xf000)
12251 | ((insn >> 15) & 0x0800)
12252 | ((insn >> 4) & 0x0700)
07d6d2b8 12253 | (insn & 0x00ff);
39623e12 12254 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12255 }
92f5d02b 12256
b6895b4f 12257 value += signed_addend;
b6895b4f
PB		 12258
12259 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12260 value -= (input_section->output_section->vma
12261 + input_section->output_offset + rel->r_offset);
12262
92f5d02b 12263 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12264 return bfd_reloc_overflow;
92f5d02b 12265
35fc36a8 12266 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12267 value |= 1;
12268
12269 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12270 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12271 value >>= 16;
12272
12273 insn &= 0xfbf08f00;
12274 insn |= (value & 0xf000) << 4;
12275 insn |= (value & 0x0800) << 15;
12276 insn |= (value & 0x0700) << 4;
12277 insn |= (value & 0x00ff);
12278
12279 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12280 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12281 }
12282 return bfd_reloc_ok;
12283
4962c51a
MS		 12284 case R_ARM_ALU_PC_G0_NC:
12285 case R_ARM_ALU_PC_G1_NC:
12286 case R_ARM_ALU_PC_G0:
12287 case R_ARM_ALU_PC_G1:
12288 case R_ARM_ALU_PC_G2:
12289 case R_ARM_ALU_SB_G0_NC:
12290 case R_ARM_ALU_SB_G1_NC:
12291 case R_ARM_ALU_SB_G0:
12292 case R_ARM_ALU_SB_G1:
12293 case R_ARM_ALU_SB_G2:
12294 {
12295 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12296 bfd_vma pc = input_section->output_section->vma
4962c51a 12297 + input_section->output_offset + rel->r_offset;
31a91d61 12298 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12299 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12300 bfd_vma residual;
12301 bfd_vma g_n;
4962c51a 12302 bfd_signed_vma signed_value;
99059e56
RM		 12303 int group = 0;
12304
12305 /* Determine which group of bits to select. */
12306 switch (r_type)
12307 {
12308 case R_ARM_ALU_PC_G0_NC:
12309 case R_ARM_ALU_PC_G0:
12310 case R_ARM_ALU_SB_G0_NC:
12311 case R_ARM_ALU_SB_G0:
12312 group = 0;
12313 break;
12314
12315 case R_ARM_ALU_PC_G1_NC:
12316 case R_ARM_ALU_PC_G1:
12317 case R_ARM_ALU_SB_G1_NC:
12318 case R_ARM_ALU_SB_G1:
12319 group = 1;
12320 break;
12321
12322 case R_ARM_ALU_PC_G2:
12323 case R_ARM_ALU_SB_G2:
12324 group = 2;
12325 break;
12326
12327 default:
12328 abort ();
12329 }
12330
12331 /* If REL, extract the addend from the insn. If RELA, it will
12332 have already been fetched for us. */
4962c51a 12333 if (globals->use_rel)
99059e56
RM		 12334 {
12335 int negative;
12336 bfd_vma constant = insn & 0xff;
12337 bfd_vma rotation = (insn & 0xf00) >> 8;
12338
12339 if (rotation == 0)
12340 signed_addend = constant;
12341 else
12342 {
12343 /* Compensate for the fact that in the instruction, the
12344 rotation is stored in multiples of 2 bits. */
12345 rotation *= 2;
12346
12347 /* Rotate "constant" right by "rotation" bits. */
12348 signed_addend = (constant >> rotation) |
12349 (constant << (8 * sizeof (bfd_vma) - rotation));
12350 }
12351
12352 /* Determine if the instruction is an ADD or a SUB.
12353 (For REL, this determines the sign of the addend.) */
12354 negative = identify_add_or_sub (insn);
12355 if (negative == 0)
12356 {
4eca0228 12357 _bfd_error_handler
695344c0 12358 /* xgettext:c-format */
90b6238f 12359 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12360 "are allowed for ALU group relocations"),
12361 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12362 return bfd_reloc_overflow;
12363 }
12364
12365 signed_addend *= negative;
12366 }
4962c51a
MS		 12367
12368 /* Compute the value (X) to go in the place. */
99059e56
RM		 12369 if (r_type == R_ARM_ALU_PC_G0_NC
12370 || r_type == R_ARM_ALU_PC_G1_NC
12371 || r_type == R_ARM_ALU_PC_G0
12372 || r_type == R_ARM_ALU_PC_G1
12373 || r_type == R_ARM_ALU_PC_G2)
12374 /* PC relative. */
12375 signed_value = value - pc + signed_addend;
12376 else
12377 /* Section base relative. */
12378 signed_value = value - sb + signed_addend;
12379
12380 /* If the target symbol is a Thumb function, then set the
12381 Thumb bit in the address. */
35fc36a8 12382 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12383 signed_value |= 1;
12384
99059e56
RM		 12385 /* Calculate the value of the relevant G_n, in encoded
12386 constant-with-rotation format. */
b6518b38
NC		 12387 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12388 group, &residual);
99059e56
RM		 12389
12390 /* Check for overflow if required. */
12391 if ((r_type == R_ARM_ALU_PC_G0
12392 || r_type == R_ARM_ALU_PC_G1
12393 || r_type == R_ARM_ALU_PC_G2
12394 || r_type == R_ARM_ALU_SB_G0
12395 || r_type == R_ARM_ALU_SB_G1
12396 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12397 {
4eca0228 12398 _bfd_error_handler
695344c0 12399 /* xgettext:c-format */
90b6238f 12400 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12401 "splitting %#" PRIx64 " for group relocation %s"),
12402 input_bfd, input_section, (uint64_t) rel->r_offset,
12403 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12404 howto->name);
99059e56
RM		 12405 return bfd_reloc_overflow;
12406 }
12407
12408 /* Mask out the value and the ADD/SUB part of the opcode; take care
12409 not to destroy the S bit. */
12410 insn &= 0xff1ff000;
12411
12412 /* Set the opcode according to whether the value to go in the
12413 place is negative. */
12414 if (signed_value < 0)
12415 insn |= 1 << 22;
12416 else
12417 insn |= 1 << 23;
12418
12419 /* Encode the offset. */
12420 insn |= g_n;
4962c51a
MS		 12421
12422 bfd_put_32 (input_bfd, insn, hit_data);
12423 }
12424 return bfd_reloc_ok;
12425
12426 case R_ARM_LDR_PC_G0:
12427 case R_ARM_LDR_PC_G1:
12428 case R_ARM_LDR_PC_G2:
12429 case R_ARM_LDR_SB_G0:
12430 case R_ARM_LDR_SB_G1:
12431 case R_ARM_LDR_SB_G2:
12432 {
12433 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12434 bfd_vma pc = input_section->output_section->vma
4962c51a 12435 + input_section->output_offset + rel->r_offset;
31a91d61 12436 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12437 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12438 bfd_vma residual;
4962c51a 12439 bfd_signed_vma signed_value;
99059e56
RM		 12440 int group = 0;
12441
12442 /* Determine which groups of bits to calculate. */
12443 switch (r_type)
12444 {
12445 case R_ARM_LDR_PC_G0:
12446 case R_ARM_LDR_SB_G0:
12447 group = 0;
12448 break;
12449
12450 case R_ARM_LDR_PC_G1:
12451 case R_ARM_LDR_SB_G1:
12452 group = 1;
12453 break;
12454
12455 case R_ARM_LDR_PC_G2:
12456 case R_ARM_LDR_SB_G2:
12457 group = 2;
12458 break;
12459
12460 default:
12461 abort ();
12462 }
12463
12464 /* If REL, extract the addend from the insn. If RELA, it will
12465 have already been fetched for us. */
4962c51a 12466 if (globals->use_rel)
99059e56
RM		 12467 {
12468 int negative = (insn & (1 << 23)) ? 1 : -1;
12469 signed_addend = negative * (insn & 0xfff);
12470 }
4962c51a
MS		 12471
12472 /* Compute the value (X) to go in the place. */
99059e56
RM		 12473 if (r_type == R_ARM_LDR_PC_G0
12474 || r_type == R_ARM_LDR_PC_G1
12475 || r_type == R_ARM_LDR_PC_G2)
12476 /* PC relative. */
12477 signed_value = value - pc + signed_addend;
12478 else
12479 /* Section base relative. */
12480 signed_value = value - sb + signed_addend;
12481
12482 /* Calculate the value of the relevant G_{n-1} to obtain
12483 the residual at that stage. */
b6518b38
NC		 12484 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12485 group - 1, &residual);
99059e56
RM		 12486
12487 /* Check for overflow. */
12488 if (residual >= 0x1000)
12489 {
4eca0228 12490 _bfd_error_handler
695344c0 12491 /* xgettext:c-format */
90b6238f 12492 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12493 "splitting %#" PRIx64 " for group relocation %s"),
12494 input_bfd, input_section, (uint64_t) rel->r_offset,
12495 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12496 howto->name);
99059e56
RM		 12497 return bfd_reloc_overflow;
12498 }
12499
12500 /* Mask out the value and U bit. */
12501 insn &= 0xff7ff000;
12502
12503 /* Set the U bit if the value to go in the place is non-negative. */
12504 if (signed_value >= 0)
12505 insn |= 1 << 23;
12506
12507 /* Encode the offset. */
12508 insn |= residual;
4962c51a
MS		 12509
12510 bfd_put_32 (input_bfd, insn, hit_data);
12511 }
12512 return bfd_reloc_ok;
12513
12514 case R_ARM_LDRS_PC_G0:
12515 case R_ARM_LDRS_PC_G1:
12516 case R_ARM_LDRS_PC_G2:
12517 case R_ARM_LDRS_SB_G0:
12518 case R_ARM_LDRS_SB_G1:
12519 case R_ARM_LDRS_SB_G2:
12520 {
12521 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12522 bfd_vma pc = input_section->output_section->vma
4962c51a 12523 + input_section->output_offset + rel->r_offset;
31a91d61 12524 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12525 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12526 bfd_vma residual;
4962c51a 12527 bfd_signed_vma signed_value;
99059e56
RM		 12528 int group = 0;
12529
12530 /* Determine which groups of bits to calculate. */
12531 switch (r_type)
12532 {
12533 case R_ARM_LDRS_PC_G0:
12534 case R_ARM_LDRS_SB_G0:
12535 group = 0;
12536 break;
12537
12538 case R_ARM_LDRS_PC_G1:
12539 case R_ARM_LDRS_SB_G1:
12540 group = 1;
12541 break;
12542
12543 case R_ARM_LDRS_PC_G2:
12544 case R_ARM_LDRS_SB_G2:
12545 group = 2;
12546 break;
12547
12548 default:
12549 abort ();
12550 }
12551
12552 /* If REL, extract the addend from the insn. If RELA, it will
12553 have already been fetched for us. */
4962c51a 12554 if (globals->use_rel)
99059e56
RM		 12555 {
12556 int negative = (insn & (1 << 23)) ? 1 : -1;
12557 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12558 }
4962c51a
MS		 12559
12560 /* Compute the value (X) to go in the place. */
99059e56
RM		 12561 if (r_type == R_ARM_LDRS_PC_G0
12562 || r_type == R_ARM_LDRS_PC_G1
12563 || r_type == R_ARM_LDRS_PC_G2)
12564 /* PC relative. */
12565 signed_value = value - pc + signed_addend;
12566 else
12567 /* Section base relative. */
12568 signed_value = value - sb + signed_addend;
12569
12570 /* Calculate the value of the relevant G_{n-1} to obtain
12571 the residual at that stage. */
b6518b38
NC		 12572 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12573 group - 1, &residual);
99059e56
RM		 12574
12575 /* Check for overflow. */
12576 if (residual >= 0x100)
12577 {
4eca0228 12578 _bfd_error_handler
695344c0 12579 /* xgettext:c-format */
90b6238f 12580 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12581 "splitting %#" PRIx64 " for group relocation %s"),
12582 input_bfd, input_section, (uint64_t) rel->r_offset,
12583 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12584 howto->name);
99059e56
RM		 12585 return bfd_reloc_overflow;
12586 }
12587
12588 /* Mask out the value and U bit. */
12589 insn &= 0xff7ff0f0;
12590
12591 /* Set the U bit if the value to go in the place is non-negative. */
12592 if (signed_value >= 0)
12593 insn |= 1 << 23;
12594
12595 /* Encode the offset. */
12596 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12597
12598 bfd_put_32 (input_bfd, insn, hit_data);
12599 }
12600 return bfd_reloc_ok;
12601
12602 case R_ARM_LDC_PC_G0:
12603 case R_ARM_LDC_PC_G1:
12604 case R_ARM_LDC_PC_G2:
12605 case R_ARM_LDC_SB_G0:
12606 case R_ARM_LDC_SB_G1:
12607 case R_ARM_LDC_SB_G2:
12608 {
12609 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12610 bfd_vma pc = input_section->output_section->vma
4962c51a 12611 + input_section->output_offset + rel->r_offset;
31a91d61 12612 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12613 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12614 bfd_vma residual;
4962c51a 12615 bfd_signed_vma signed_value;
99059e56
RM		 12616 int group = 0;
12617
12618 /* Determine which groups of bits to calculate. */
12619 switch (r_type)
12620 {
12621 case R_ARM_LDC_PC_G0:
12622 case R_ARM_LDC_SB_G0:
12623 group = 0;
12624 break;
12625
12626 case R_ARM_LDC_PC_G1:
12627 case R_ARM_LDC_SB_G1:
12628 group = 1;
12629 break;
12630
12631 case R_ARM_LDC_PC_G2:
12632 case R_ARM_LDC_SB_G2:
12633 group = 2;
12634 break;
12635
12636 default:
12637 abort ();
12638 }
12639
12640 /* If REL, extract the addend from the insn. If RELA, it will
12641 have already been fetched for us. */
4962c51a 12642 if (globals->use_rel)
99059e56
RM		 12643 {
12644 int negative = (insn & (1 << 23)) ? 1 : -1;
12645 signed_addend = negative * ((insn & 0xff) << 2);
12646 }
4962c51a
MS		 12647
12648 /* Compute the value (X) to go in the place. */
99059e56
RM		 12649 if (r_type == R_ARM_LDC_PC_G0
12650 || r_type == R_ARM_LDC_PC_G1
12651 || r_type == R_ARM_LDC_PC_G2)
12652 /* PC relative. */
12653 signed_value = value - pc + signed_addend;
12654 else
12655 /* Section base relative. */
12656 signed_value = value - sb + signed_addend;
12657
12658 /* Calculate the value of the relevant G_{n-1} to obtain
12659 the residual at that stage. */
b6518b38
NC		 12660 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12661 group - 1, &residual);
99059e56
RM		 12662
12663 /* Check for overflow. (The absolute value to go in the place must be
12664 divisible by four and, after having been divided by four, must
12665 fit in eight bits.) */
12666 if ((residual & 0x3) != 0 || residual >= 0x400)
12667 {
4eca0228 12668 _bfd_error_handler
695344c0 12669 /* xgettext:c-format */
90b6238f 12670 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12671 "splitting %#" PRIx64 " for group relocation %s"),
12672 input_bfd, input_section, (uint64_t) rel->r_offset,
12673 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12674 howto->name);
99059e56
RM		 12675 return bfd_reloc_overflow;
12676 }
12677
12678 /* Mask out the value and U bit. */
12679 insn &= 0xff7fff00;
12680
12681 /* Set the U bit if the value to go in the place is non-negative. */
12682 if (signed_value >= 0)
12683 insn |= 1 << 23;
12684
12685 /* Encode the offset. */
12686 insn |= residual >> 2;
4962c51a
MS		 12687
12688 bfd_put_32 (input_bfd, insn, hit_data);
12689 }
12690 return bfd_reloc_ok;
12691
72d98d16
MG		 12692 case R_ARM_THM_ALU_ABS_G0_NC:
12693 case R_ARM_THM_ALU_ABS_G1_NC:
12694 case R_ARM_THM_ALU_ABS_G2_NC:
12695 case R_ARM_THM_ALU_ABS_G3_NC:
12696 {
12697 const int shift_array[4] = {0, 8, 16, 24};
12698 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12699 bfd_vma addr = value;
12700 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12701
12702 /* Compute address. */
12703 if (globals->use_rel)
12704 signed_addend = insn & 0xff;
12705 addr += signed_addend;
12706 if (branch_type == ST_BRANCH_TO_THUMB)
12707 addr |= 1;
12708 /* Clean imm8 insn. */
12709 insn &= 0xff00;
12710 /* And update with correct part of address. */
12711 insn |= (addr >> shift) & 0xff;
12712 /* Update insn. */
12713 bfd_put_16 (input_bfd, insn, hit_data);
12714 }
12715
12716 *unresolved_reloc_p = FALSE;
12717 return bfd_reloc_ok;
12718
e8b09b87
CL		 12719 case R_ARM_GOTOFFFUNCDESC:
12720 {
4b24dd1a 12721 if (h == NULL)
e8b09b87
CL		 12722 {
12723 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12724 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12725 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12726 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12727 bfd_vma seg = -1;
12728
12729 if (bfd_link_pic(info) && dynindx == 0)
12730 abort();
12731
12732 /* Resolve relocation. */
12733 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12734 , contents + rel->r_offset);
12735 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12736 not done yet. */
12737 arm_elf_fill_funcdesc(output_bfd, info,
12738 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12739 dynindx, offset, addr, dynreloc_value, seg);
12740 }
12741 else
12742 {
12743 int dynindx;
12744 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12745 bfd_vma addr;
12746 bfd_vma seg = -1;
12747
12748 /* For static binaries, sym_sec can be null. */
12749 if (sym_sec)
12750 {
12751 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12752 addr = dynreloc_value - sym_sec->output_section->vma;
12753 }
12754 else
12755 {
12756 dynindx = 0;
12757 addr = 0;
12758 }
12759
12760 if (bfd_link_pic(info) && dynindx == 0)
12761 abort();
12762
12763 /* This case cannot occur since funcdesc is allocated by
12764 the dynamic loader so we cannot resolve the relocation. */
12765 if (h->dynindx != -1)
12766 abort();
12767
12768 /* Resolve relocation. */
12769 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12770 contents + rel->r_offset);
12771 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12772 arm_elf_fill_funcdesc(output_bfd, info,
12773 &eh->fdpic_cnts.funcdesc_offset,
12774 dynindx, offset, addr, dynreloc_value, seg);
12775 }
12776 }
12777 *unresolved_reloc_p = FALSE;
12778 return bfd_reloc_ok;
12779
12780 case R_ARM_GOTFUNCDESC:
12781 {
4b24dd1a 12782 if (h != NULL)
e8b09b87
CL		 12783 {
12784 Elf_Internal_Rela outrel;
12785
12786 /* Resolve relocation. */
12787 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12788 + sgot->output_offset),
12789 contents + rel->r_offset);
12790 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12791 if(h->dynindx == -1)
12792 {
12793 int dynindx;
12794 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12795 bfd_vma addr;
12796 bfd_vma seg = -1;
12797
12798 /* For static binaries sym_sec can be null. */
12799 if (sym_sec)
12800 {
12801 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12802 addr = dynreloc_value - sym_sec->output_section->vma;
12803 }
12804 else
12805 {
12806 dynindx = 0;
12807 addr = 0;
12808 }
12809
12810 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12811 arm_elf_fill_funcdesc(output_bfd, info,
12812 &eh->fdpic_cnts.funcdesc_offset,
12813 dynindx, offset, addr, dynreloc_value, seg);
12814 }
12815
12816 /* Add a dynamic relocation on GOT entry if not already done. */
12817 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12818 {
12819 if (h->dynindx == -1)
12820 {
12821 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12822 if (h->root.type == bfd_link_hash_undefweak)
12823 bfd_put_32(output_bfd, 0, sgot->contents
12824 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12825 else
12826 bfd_put_32(output_bfd, sgot->output_section->vma
12827 + sgot->output_offset
12828 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12829 sgot->contents
12830 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12831 }
12832 else
12833 {
12834 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12835 }
12836 outrel.r_offset = sgot->output_section->vma
12837 + sgot->output_offset
12838 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12839 outrel.r_addend = 0;
12840 if (h->dynindx == -1 && !bfd_link_pic(info))
12841 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12842 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12843 else
4b24dd1a
AM		 12844 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12845 outrel.r_offset);
e8b09b87
CL		 12846 else
12847 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12848 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12849 }
12850 }
12851 else
12852 {
12853 /* Such relocation on static function should not have been
12854 emitted by the compiler. */
12855 abort();
12856 }
12857 }
12858 *unresolved_reloc_p = FALSE;
12859 return bfd_reloc_ok;
12860
12861 case R_ARM_FUNCDESC:
12862 {
4b24dd1a 12863 if (h == NULL)
e8b09b87
CL		 12864 {
12865 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12866 Elf_Internal_Rela outrel;
12867 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12868 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12869 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12870 bfd_vma seg = -1;
12871
12872 if (bfd_link_pic(info) && dynindx == 0)
12873 abort();
12874
12875 /* Replace static FUNCDESC relocation with a
12876 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12877 executable. */
12878 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12879 outrel.r_offset = input_section->output_section->vma
12880 + input_section->output_offset + rel->r_offset;
12881 outrel.r_addend = 0;
12882 if (bfd_link_pic(info))
12883 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12884 else
12885 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12886
12887 bfd_put_32 (input_bfd, sgot->output_section->vma
12888 + sgot->output_offset + offset, hit_data);
12889
12890 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12891 arm_elf_fill_funcdesc(output_bfd, info,
12892 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12893 dynindx, offset, addr, dynreloc_value, seg);
12894 }
12895 else
12896 {
12897 if (h->dynindx == -1)
12898 {
12899 int dynindx;
12900 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12901 bfd_vma addr;
12902 bfd_vma seg = -1;
12903 Elf_Internal_Rela outrel;
12904
12905 /* For static binaries sym_sec can be null. */
12906 if (sym_sec)
12907 {
12908 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12909 addr = dynreloc_value - sym_sec->output_section->vma;
12910 }
12911 else
12912 {
12913 dynindx = 0;
12914 addr = 0;
12915 }
12916
12917 if (bfd_link_pic(info) && dynindx == 0)
12918 abort();
12919
12920 /* Replace static FUNCDESC relocation with a
12921 R_ARM_RELATIVE dynamic relocation. */
12922 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12923 outrel.r_offset = input_section->output_section->vma
12924 + input_section->output_offset + rel->r_offset;
12925 outrel.r_addend = 0;
12926 if (bfd_link_pic(info))
12927 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12928 else
12929 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12930
12931 bfd_put_32 (input_bfd, sgot->output_section->vma
12932 + sgot->output_offset + offset, hit_data);
12933
12934 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12935 arm_elf_fill_funcdesc(output_bfd, info,
12936 &eh->fdpic_cnts.funcdesc_offset,
12937 dynindx, offset, addr, dynreloc_value, seg);
12938 }
12939 else
12940 {
12941 Elf_Internal_Rela outrel;
12942
12943 /* Add a dynamic relocation. */
12944 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12945 outrel.r_offset = input_section->output_section->vma
12946 + input_section->output_offset + rel->r_offset;
12947 outrel.r_addend = 0;
12948 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12949 }
12950 }
12951 }
12952 *unresolved_reloc_p = FALSE;
12953 return bfd_reloc_ok;
12954
e5d6e09e
AV		 12955 case R_ARM_THM_BF16:
12956 {
12957 bfd_vma relocation;
12958 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12959 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12960
12961 if (globals->use_rel)
12962 {
12963 bfd_vma immA = (upper_insn & 0x001f);
12964 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12965 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12966 addend = (immA << 12);
12967 addend |= (immB << 2);
12968 addend |= (immC << 1);
12969 addend |= 1;
12970 /* Sign extend. */
12971 addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
12972 }
12973
12974 value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
12975 info, input_bfd, rel, sym_name, st_type,
12976 globals, unresolved_reloc_p);
12977
12978 relocation = value + addend;
12979 relocation -= (input_section->output_section->vma
12980 + input_section->output_offset
12981 + rel->r_offset);
12982
12983 /* Put RELOCATION back into the insn. */
12984 {
12985 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12986 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12987 bfd_vma immC = (relocation & 0x00000002) >> 1;
12988
12989 upper_insn = (upper_insn & 0xffe0) | immA;
12990 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12991 }
12992
12993 /* Put the relocated value back in the object file: */
12994 bfd_put_16 (input_bfd, upper_insn, hit_data);
12995 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12996
12997 return bfd_reloc_ok;
12998 }
12999
1889da70
AV		 13000 case R_ARM_THM_BF12:
13001 {
13002 bfd_vma relocation;
13003 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
13004 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
13005
13006 if (globals->use_rel)
13007 {
13008 bfd_vma immA = (upper_insn & 0x0001);
13009 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
13010 bfd_vma immC = (lower_insn & 0x0800) >> 11;
13011 addend = (immA << 12);
13012 addend |= (immB << 2);
13013 addend |= (immC << 1);
13014 addend |= 1;
13015 /* Sign extend. */
13016 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
13017 }
13018
13019 value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
13020 info, input_bfd, rel, sym_name, st_type,
13021 globals, unresolved_reloc_p);
13022
13023 relocation = value + addend;
13024 relocation -= (input_section->output_section->vma
13025 + input_section->output_offset
13026 + rel->r_offset);
13027
13028 /* Put RELOCATION back into the insn. */
13029 {
13030 bfd_vma immA = (relocation & 0x00001000) >> 12;
13031 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13032 bfd_vma immC = (relocation & 0x00000002) >> 1;
13033
13034 upper_insn = (upper_insn & 0xfffe) | immA;
13035 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13036 }
13037
13038 /* Put the relocated value back in the object file: */
13039 bfd_put_16 (input_bfd, upper_insn, hit_data);
13040 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13041
13042 return bfd_reloc_ok;
13043 }
13044
1caf72a5
AV		 13045 case R_ARM_THM_BF18:
13046 {
13047 bfd_vma relocation;
13048 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
13049 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
13050
13051 if (globals->use_rel)
13052 {
13053 bfd_vma immA = (upper_insn & 0x007f);
13054 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
13055 bfd_vma immC = (lower_insn & 0x0800) >> 11;
13056 addend = (immA << 12);
13057 addend |= (immB << 2);
13058 addend |= (immC << 1);
13059 addend |= 1;
13060 /* Sign extend. */
13061 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
13062 }
13063
13064 value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
13065 info, input_bfd, rel, sym_name, st_type,
13066 globals, unresolved_reloc_p);
13067
13068 relocation = value + addend;
13069 relocation -= (input_section->output_section->vma
13070 + input_section->output_offset
13071 + rel->r_offset);
13072
13073 /* Put RELOCATION back into the insn. */
13074 {
13075 bfd_vma immA = (relocation & 0x0007f000) >> 12;
13076 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13077 bfd_vma immC = (relocation & 0x00000002) >> 1;
13078
13079 upper_insn = (upper_insn & 0xff80) | immA;
13080 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13081 }
13082
13083 /* Put the relocated value back in the object file: */
13084 bfd_put_16 (input_bfd, upper_insn, hit_data);
13085 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13086
13087 return bfd_reloc_ok;
13088 }
13089
252b5132
RH		 13090 default:
13091 return bfd_reloc_notsupported;
13092 }
13093}
13094
98c1d4aa
NC		 13095/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13096static void
07d6d2b8
AM		 13097arm_add_to_rel (bfd * abfd,
13098 bfd_byte * address,
57e8b36a 13099 reloc_howto_type * howto,
07d6d2b8 13100 bfd_signed_vma increment)
98c1d4aa 13101{
98c1d4aa
NC		 13102 bfd_signed_vma addend;
13103
bd97cb95
DJ		 13104 if (howto->type == R_ARM_THM_CALL
13105 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13106 {
9a5aca8c
AM		 13107 int upper_insn, lower_insn;
13108 int upper, lower;
98c1d4aa 13109
9a5aca8c
AM		 13110 upper_insn = bfd_get_16 (abfd, address);
13111 lower_insn = bfd_get_16 (abfd, address + 2);
13112 upper = upper_insn & 0x7ff;
13113 lower = lower_insn & 0x7ff;
13114
13115 addend = (upper << 12) | (lower << 1);
ddda4409 13116 addend += increment;
9a5aca8c 13117 addend >>= 1;
98c1d4aa 13118
9a5aca8c
AM		 13119 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13120 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13121
dc810e39
AM		 13122 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13123 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13124 }
13125 else
13126 {
07d6d2b8 13127 bfd_vma contents;
9a5aca8c
AM		 13128
13129 contents = bfd_get_32 (abfd, address);
13130
13131 /* Get the (signed) value from the instruction. */
13132 addend = contents & howto->src_mask;
13133 if (addend & ((howto->src_mask + 1) >> 1))
13134 {
13135 bfd_signed_vma mask;
13136
13137 mask = -1;
13138 mask &= ~ howto->src_mask;
13139 addend |= mask;
13140 }
13141
13142 /* Add in the increment, (which is a byte value). */
13143 switch (howto->type)
13144 {
13145 default:
13146 addend += increment;
13147 break;
13148
13149 case R_ARM_PC24:
c6596c5e 13150 case R_ARM_PLT32:
5b5bb741
PB		 13151 case R_ARM_CALL:
13152 case R_ARM_JUMP24:
9a5aca8c 13153 addend <<= howto->size;
dc810e39 13154 addend += increment;
9a5aca8c
AM		 13155
13156 /* Should we check for overflow here ? */
13157
13158 /* Drop any undesired bits. */
13159 addend >>= howto->rightshift;
13160 break;
13161 }
13162
13163 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13164
13165 bfd_put_32 (abfd, contents, address);
ddda4409 13166 }
98c1d4aa 13167}
252b5132 13168
ba93b8ac
DJ		 13169#define IS_ARM_TLS_RELOC(R_TYPE) \
13170 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13171 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13172 || (R_TYPE) == R_ARM_TLS_LDO32 \
13173 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13174 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13175 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13176 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13177 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13178 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13179 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13180 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13181 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13182
13183/* Specific set of relocations for the gnu tls dialect. */
13184#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13185 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13186 || (R_TYPE) == R_ARM_TLS_CALL \
13187 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13188 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13189 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13190
252b5132 13191/* Relocate an ARM ELF section. */
906e58ca 13192
b34976b6 13193static bfd_boolean
07d6d2b8 13194elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13195 struct bfd_link_info * info,
07d6d2b8
AM		 13196 bfd * input_bfd,
13197 asection * input_section,
13198 bfd_byte * contents,
13199 Elf_Internal_Rela * relocs,
13200 Elf_Internal_Sym * local_syms,
13201 asection ** local_sections)
252b5132 13202{
b34976b6
AM		 13203 Elf_Internal_Shdr *symtab_hdr;
13204 struct elf_link_hash_entry **sym_hashes;
13205 Elf_Internal_Rela *rel;
13206 Elf_Internal_Rela *relend;
13207 const char *name;
b32d3aa2 13208 struct elf32_arm_link_hash_table * globals;
252b5132 13209
4e7fd91e 13210 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13211 if (globals == NULL)
13212 return FALSE;
b491616a 13213
0ffa91dd 13214 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13215 sym_hashes = elf_sym_hashes (input_bfd);
13216
13217 rel = relocs;
13218 relend = relocs + input_section->reloc_count;
13219 for (; rel < relend; rel++)
13220 {
07d6d2b8
AM		 13221 int r_type;
13222 reloc_howto_type * howto;
13223 unsigned long r_symndx;
13224 Elf_Internal_Sym * sym;
13225 asection * sec;
252b5132 13226 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13227 bfd_vma relocation;
13228 bfd_reloc_status_type r;
13229 arelent bfd_reloc;
13230 char sym_type;
13231 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13232 char *error_message = NULL;
f21f3fe0 13233
252b5132 13234 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13235 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13236 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13237
ba96a88f 13238 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13239 || r_type == R_ARM_GNU_VTINHERIT)
13240 continue;
252b5132 13241
47aeb64c
NC		 13242 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13243
13244 if (howto == NULL)
13245 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13246
252b5132
RH		 13247 h = NULL;
13248 sym = NULL;
13249 sec = NULL;
9b485d32 13250
252b5132
RH		 13251 if (r_symndx < symtab_hdr->sh_info)
13252 {
13253 sym = local_syms + r_symndx;
ba93b8ac 13254 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13255 sec = local_sections[r_symndx];
ffcb4889
NS		 13256
13257 /* An object file might have a reference to a local
13258 undefined symbol. This is a daft object file, but we
13259 should at least do something about it. V4BX & NONE
13260 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13261 allowed to use the undefined symbol, so allow those.
13262 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13263 if (r_type != R_ARM_V4BX
13264 && r_type != R_ARM_NONE
77b4f08f 13265 && r_symndx != STN_UNDEF
ffcb4889
NS		 13266 && bfd_is_und_section (sec)
13267 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13268 (*info->callbacks->undefined_symbol)
13269 (info, bfd_elf_string_from_elf_section
13270 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13271 input_bfd, input_section,
13272 rel->r_offset, TRUE);
b38cadfb 13273
4e7fd91e 13274 if (globals->use_rel)
f8df10f4 13275 {
4e7fd91e
PB		 13276 relocation = (sec->output_section->vma
13277 + sec->output_offset
13278 + sym->st_value);
0e1862bb 13279 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13280 && (sec->flags & SEC_MERGE)
13281 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13282 {
4e7fd91e
PB		 13283 asection *msec;
13284 bfd_vma addend, value;
13285
39623e12 13286 switch (r_type)
4e7fd91e 13287 {
39623e12
PB		 13288 case R_ARM_MOVW_ABS_NC:
13289 case R_ARM_MOVT_ABS:
13290 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13291 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13292 addend = (addend ^ 0x8000) - 0x8000;
13293 break;
f8df10f4 13294
39623e12
PB		 13295 case R_ARM_THM_MOVW_ABS_NC:
13296 case R_ARM_THM_MOVT_ABS:
13297 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13298 << 16;
13299 value |= bfd_get_16 (input_bfd,
13300 contents + rel->r_offset + 2);
13301 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13302 | ((value & 0x04000000) >> 15);
13303 addend = (addend ^ 0x8000) - 0x8000;
13304 break;
f8df10f4 13305
39623e12
PB		 13306 default:
13307 if (howto->rightshift
13308 || (howto->src_mask & (howto->src_mask + 1)))
13309 {
4eca0228 13310 _bfd_error_handler
695344c0 13311 /* xgettext:c-format */
2dcf00ce
AM		 13312 (_("%pB(%pA+%#" PRIx64 "): "
13313 "%s relocation against SEC_MERGE section"),
39623e12 13314 input_bfd, input_section,
2dcf00ce 13315 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13316 return FALSE;
13317 }
13318
13319 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13320
13321 /* Get the (signed) value from the instruction. */
13322 addend = value & howto->src_mask;
13323 if (addend & ((howto->src_mask + 1) >> 1))
13324 {
13325 bfd_signed_vma mask;
13326
13327 mask = -1;
13328 mask &= ~ howto->src_mask;
13329 addend |= mask;
13330 }
13331 break;
4e7fd91e 13332 }
39623e12 13333
4e7fd91e
PB		 13334 msec = sec;
13335 addend =
13336 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13337 - relocation;
13338 addend += msec->output_section->vma + msec->output_offset;
39623e12 13339
cc643b88 13340 /* Cases here must match those in the preceding
39623e12
PB		 13341 switch statement. */
13342 switch (r_type)
13343 {
13344 case R_ARM_MOVW_ABS_NC:
13345 case R_ARM_MOVT_ABS:
13346 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13347 | (addend & 0xfff);
13348 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13349 break;
13350
13351 case R_ARM_THM_MOVW_ABS_NC:
13352 case R_ARM_THM_MOVT_ABS:
13353 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13354 | (addend & 0xff) | ((addend & 0x0800) << 15);
13355 bfd_put_16 (input_bfd, value >> 16,
13356 contents + rel->r_offset);
13357 bfd_put_16 (input_bfd, value,
13358 contents + rel->r_offset + 2);
13359 break;
13360
13361 default:
13362 value = (value & ~ howto->dst_mask)
13363 | (addend & howto->dst_mask);
13364 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13365 break;
13366 }
f8df10f4 13367 }
f8df10f4 13368 }
4e7fd91e
PB		 13369 else
13370 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13371 }
13372 else
13373 {
62d887d4 13374 bfd_boolean warned, ignored;
560e09e9 13375
b2a8e766
AM		 13376 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13377 r_symndx, symtab_hdr, sym_hashes,
13378 h, sec, relocation,
62d887d4 13379 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13380
13381 sym_type = h->type;
252b5132
RH		 13382 }
13383
dbaa2011 13384 if (sec != NULL && discarded_section (sec))
e4067dbb 13385 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13386 rel, 1, relend, howto, 0, contents);
ab96bf03 13387
0e1862bb 13388 if (bfd_link_relocatable (info))
ab96bf03
AM		 13389 {
13390 /* This is a relocatable link. We don't have to change
13391 anything, unless the reloc is against a section symbol,
13392 in which case we have to adjust according to where the
13393 section symbol winds up in the output section. */
13394 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13395 {
13396 if (globals->use_rel)
13397 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13398 howto, (bfd_signed_vma) sec->output_offset);
13399 else
13400 rel->r_addend += sec->output_offset;
13401 }
13402 continue;
13403 }
13404
252b5132
RH		 13405 if (h != NULL)
13406 name = h->root.root.string;
13407 else
13408 {
13409 name = (bfd_elf_string_from_elf_section
13410 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13411 if (name == NULL || *name == '\0')
13412 name = bfd_section_name (input_bfd, sec);
13413 }
f21f3fe0 13414
cf35638d 13415 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13416 && r_type != R_ARM_NONE
13417 && (h == NULL
13418 || h->root.type == bfd_link_hash_defined
13419 || h->root.type == bfd_link_hash_defweak)
13420 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13421 {
4eca0228 13422 _bfd_error_handler
ba93b8ac 13423 ((sym_type == STT_TLS
695344c0 13424 /* xgettext:c-format */
2dcf00ce 13425 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13426 /* xgettext:c-format */
2dcf00ce 13427 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13428 input_bfd,
13429 input_section,
2dcf00ce 13430 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13431 howto->name,
13432 name);
13433 }
13434
0855e32b 13435 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13436 done, i.e., the relaxation produced the final output we want,
13437 and we won't let anybody mess with it. Also, we have to do
13438 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13439 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13440 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13441 || (IS_ARM_TLS_GNU_RELOC (r_type)
13442 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13443 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13444 & GOT_TLS_GDESC)))
13445 {
13446 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13447 contents, rel, h == NULL);
13448 /* This may have been marked unresolved because it came from
13449 a shared library. But we've just dealt with that. */
13450 unresolved_reloc = 0;
13451 }
13452 else
13453 r = bfd_reloc_continue;
b38cadfb 13454
39d911fc
TP		 13455 if (r == bfd_reloc_continue)
13456 {
13457 unsigned char branch_type =
13458 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13459 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13460
13461 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13462 input_section, contents, rel,
13463 relocation, info, sec, name,
13464 sym_type, branch_type, h,
13465 &unresolved_reloc,
13466 &error_message);
13467 }
0945cdfd
DJ		 13468
13469 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13470 because such sections are not SEC_ALLOC and thus ld.so will
13471 not process them. */
13472 if (unresolved_reloc
99059e56
RM		 13473 && !((input_section->flags & SEC_DEBUGGING) != 0
13474 && h->def_dynamic)
1d5316ab
AM		 13475 && _bfd_elf_section_offset (output_bfd, info, input_section,
13476 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13477 {
4eca0228 13478 _bfd_error_handler
695344c0 13479 /* xgettext:c-format */
2dcf00ce
AM		 13480 (_("%pB(%pA+%#" PRIx64 "): "
13481 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13482 input_bfd,
13483 input_section,
2dcf00ce 13484 (uint64_t) rel->r_offset,
843fe662
L		 13485 howto->name,
13486 h->root.root.string);
0945cdfd
DJ		 13487 return FALSE;
13488 }
252b5132
RH		 13489
13490 if (r != bfd_reloc_ok)
13491 {
252b5132
RH		 13492 switch (r)
13493 {
13494 case bfd_reloc_overflow:
cf919dfd
PB		 13495 /* If the overflowing reloc was to an undefined symbol,
13496 we have already printed one error message and there
13497 is no point complaining again. */
1a72702b
AM		 13498 if (!h || h->root.type != bfd_link_hash_undefined)
13499 (*info->callbacks->reloc_overflow)
13500 (info, (h ? &h->root : NULL), name, howto->name,
13501 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13502 break;
13503
13504 case bfd_reloc_undefined:
1a72702b
AM		 13505 (*info->callbacks->undefined_symbol)
13506 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13507 break;
13508
13509 case bfd_reloc_outofrange:
f2a9dd69 13510 error_message = _("out of range");
252b5132
RH		 13511 goto common_error;
13512
13513 case bfd_reloc_notsupported:
f2a9dd69 13514 error_message = _("unsupported relocation");
252b5132
RH		 13515 goto common_error;
13516
13517 case bfd_reloc_dangerous:
f2a9dd69 13518 /* error_message should already be set. */
252b5132
RH		 13519 goto common_error;
13520
13521 default:
f2a9dd69 13522 error_message = _("unknown error");
8029a119 13523 /* Fall through. */
252b5132
RH		 13524
13525 common_error:
f2a9dd69 13526 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13527 (*info->callbacks->reloc_dangerous)
13528 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13529 break;
13530 }
13531 }
13532 }
13533
b34976b6 13534 return TRUE;
252b5132
RH		 13535}
13536
91d6fa6a 13537/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13538 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13539 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13540 maintaining that condition). */
13541
13542static void
13543add_unwind_table_edit (arm_unwind_table_edit **head,
13544 arm_unwind_table_edit **tail,
13545 arm_unwind_edit_type type,
13546 asection *linked_section,
91d6fa6a 13547 unsigned int tindex)
2468f9c9 13548{
21d799b5
NC		 13549 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13550 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13551
2468f9c9
PB		 13552 new_edit->type = type;
13553 new_edit->linked_section = linked_section;
91d6fa6a 13554 new_edit->index = tindex;
b38cadfb 13555
91d6fa6a 13556 if (tindex > 0)
2468f9c9
PB		 13557 {
13558 new_edit->next = NULL;
13559
13560 if (*tail)
13561 (*tail)->next = new_edit;
13562
13563 (*tail) = new_edit;
13564
13565 if (!*head)
13566 (*head) = new_edit;
13567 }
13568 else
13569 {
13570 new_edit->next = *head;
13571
13572 if (!*tail)
13573 *tail = new_edit;
13574
13575 *head = new_edit;
13576 }
13577}
13578
13579static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13580
13581/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13582static void
13583adjust_exidx_size(asection *exidx_sec, int adjust)
13584{
13585 asection *out_sec;
13586
13587 if (!exidx_sec->rawsize)
13588 exidx_sec->rawsize = exidx_sec->size;
13589
13590 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
13591 out_sec = exidx_sec->output_section;
13592 /* Adjust size of output section. */
13593 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
13594}
13595
13596/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13597static void
13598insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13599{
13600 struct _arm_elf_section_data *exidx_arm_data;
13601
13602 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13603 add_unwind_table_edit (
13604 &exidx_arm_data->u.exidx.unwind_edit_list,
13605 &exidx_arm_data->u.exidx.unwind_edit_tail,
13606 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13607
491d01d3
YU		 13608 exidx_arm_data->additional_reloc_count++;
13609
2468f9c9
PB		 13610 adjust_exidx_size(exidx_sec, 8);
13611}
13612
13613/* Scan .ARM.exidx tables, and create a list describing edits which should be
13614 made to those tables, such that:
b38cadfb 13615
2468f9c9
PB		 13616 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13617 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13618 codes which have been inlined into the index).
2468f9c9 13619
85fdf906
AH		 13620 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13621
2468f9c9 13622 The edits are applied when the tables are written
b38cadfb 13623 (in elf32_arm_write_section). */
2468f9c9
PB		 13624
13625bfd_boolean
13626elf32_arm_fix_exidx_coverage (asection **text_section_order,
13627 unsigned int num_text_sections,
85fdf906
AH		 13628 struct bfd_link_info *info,
13629 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13630{
13631 bfd *inp;
13632 unsigned int last_second_word = 0, i;
13633 asection *last_exidx_sec = NULL;
13634 asection *last_text_sec = NULL;
13635 int last_unwind_type = -1;
13636
13637 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13638 text sections. */
c72f2fb2 13639 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13640 {
13641 asection *sec;
b38cadfb 13642
2468f9c9 13643 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13644 {
2468f9c9
PB		 13645 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13646 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13647
dec9d5df 13648 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13649 continue;
b38cadfb 13650
2468f9c9
PB		 13651 if (elf_sec->linked_to)
13652 {
13653 Elf_Internal_Shdr *linked_hdr
99059e56 13654 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13655 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13656 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13657
13658 if (linked_sec_arm_data == NULL)
99059e56 13659 continue;
2468f9c9
PB		 13660
13661 /* Link this .ARM.exidx section back from the text section it
99059e56 13662 describes. */
2468f9c9
PB		 13663 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13664 }
13665 }
13666 }
13667
13668 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13669 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13670 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13671
13672 for (i = 0; i < num_text_sections; i++)
13673 {
13674 asection *sec = text_section_order[i];
13675 asection *exidx_sec;
13676 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13677 struct _arm_elf_section_data *exidx_arm_data;
13678 bfd_byte *contents = NULL;
13679 int deleted_exidx_bytes = 0;
13680 bfd_vma j;
13681 arm_unwind_table_edit *unwind_edit_head = NULL;
13682 arm_unwind_table_edit *unwind_edit_tail = NULL;
13683 Elf_Internal_Shdr *hdr;
13684 bfd *ibfd;
13685
13686 if (arm_data == NULL)
99059e56 13687 continue;
2468f9c9
PB		 13688
13689 exidx_sec = arm_data->u.text.arm_exidx_sec;
13690 if (exidx_sec == NULL)
13691 {
13692 /* Section has no unwind data. */
13693 if (last_unwind_type == 0 || !last_exidx_sec)
13694 continue;
13695
13696 /* Ignore zero sized sections. */
13697 if (sec->size == 0)
13698 continue;
13699
13700 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13701 last_unwind_type = 0;
13702 continue;
13703 }
13704
22a8f80e
PB		 13705 /* Skip /DISCARD/ sections. */
13706 if (bfd_is_abs_section (exidx_sec->output_section))
13707 continue;
13708
2468f9c9
PB		 13709 hdr = &elf_section_data (exidx_sec)->this_hdr;
13710 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13711 continue;
b38cadfb 13712
2468f9c9
PB		 13713 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13714 if (exidx_arm_data == NULL)
99059e56 13715 continue;
b38cadfb 13716
2468f9c9 13717 ibfd = exidx_sec->owner;
b38cadfb 13718
2468f9c9
PB		 13719 if (hdr->contents != NULL)
13720 contents = hdr->contents;
13721 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13722 /* An error? */
13723 continue;
13724
ac06903d
YU		 13725 if (last_unwind_type > 0)
13726 {
13727 unsigned int first_word = bfd_get_32 (ibfd, contents);
13728 /* Add cantunwind if first unwind item does not match section
13729 start. */
13730 if (first_word != sec->vma)
13731 {
13732 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13733 last_unwind_type = 0;
13734 }
13735 }
13736
2468f9c9
PB		 13737 for (j = 0; j < hdr->sh_size; j += 8)
13738 {
13739 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13740 int unwind_type;
13741 int elide = 0;
13742
13743 /* An EXIDX_CANTUNWIND entry. */
13744 if (second_word == 1)
13745 {
13746 if (last_unwind_type == 0)
13747 elide = 1;
13748 unwind_type = 0;
13749 }
13750 /* Inlined unwinding data. Merge if equal to previous. */
13751 else if ((second_word & 0x80000000) != 0)
13752 {
85fdf906
AH		 13753 if (merge_exidx_entries
13754 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13755 elide = 1;
13756 unwind_type = 1;
13757 last_second_word = second_word;
13758 }
13759 /* Normal table entry. In theory we could merge these too,
13760 but duplicate entries are likely to be much less common. */
13761 else
13762 unwind_type = 2;
13763
491d01d3 13764 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13765 {
13766 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13767 DELETE_EXIDX_ENTRY, NULL, j / 8);
13768
13769 deleted_exidx_bytes += 8;
13770 }
13771
13772 last_unwind_type = unwind_type;
13773 }
13774
13775 /* Free contents if we allocated it ourselves. */
13776 if (contents != hdr->contents)
99059e56 13777 free (contents);
2468f9c9
PB		 13778
13779 /* Record edits to be applied later (in elf32_arm_write_section). */
13780 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13781 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13782
2468f9c9
PB		 13783 if (deleted_exidx_bytes > 0)
13784 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13785
13786 last_exidx_sec = exidx_sec;
13787 last_text_sec = sec;
13788 }
13789
13790 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13791 if (!bfd_link_relocatable (info) && last_exidx_sec
13792 && last_unwind_type != 0)
2468f9c9
PB		 13793 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13794
13795 return TRUE;
13796}
13797
3e6b1042
DJ		 13798static bfd_boolean
13799elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13800 bfd *ibfd, const char *name)
13801{
13802 asection *sec, *osec;
13803
3d4d4302 13804 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13805 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13806 return TRUE;
13807
13808 osec = sec->output_section;
13809 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13810 return TRUE;
13811
13812 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13813 sec->output_offset, sec->size))
13814 return FALSE;
13815
13816 return TRUE;
13817}
13818
13819static bfd_boolean
13820elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13821{
13822 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13823 asection *sec, *osec;
3e6b1042 13824
4dfe6ac6
NC		 13825 if (globals == NULL)
13826 return FALSE;
13827
3e6b1042
DJ		 13828 /* Invoke the regular ELF backend linker to do all the work. */
13829 if (!bfd_elf_final_link (abfd, info))
13830 return FALSE;
13831
fe33d2fa
CL		 13832 /* Process stub sections (eg BE8 encoding, ...). */
13833 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13834 unsigned int i;
cdb21a0a
NS		 13835 for (i=0; i<htab->top_id; i++)
13836 {
13837 sec = htab->stub_group[i].stub_sec;
13838 /* Only process it once, in its link_sec slot. */
13839 if (sec && i == htab->stub_group[i].link_sec->id)
13840 {
13841 osec = sec->output_section;
13842 elf32_arm_write_section (abfd, info, sec, sec->contents);
13843 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13844 sec->output_offset, sec->size))
13845 return FALSE;
13846 }
fe33d2fa 13847 }
fe33d2fa 13848
3e6b1042
DJ		 13849 /* Write out any glue sections now that we have created all the
13850 stubs. */
13851 if (globals->bfd_of_glue_owner != NULL)
13852 {
13853 if (! elf32_arm_output_glue_section (info, abfd,
13854 globals->bfd_of_glue_owner,
13855 ARM2THUMB_GLUE_SECTION_NAME))
13856 return FALSE;
13857
13858 if (! elf32_arm_output_glue_section (info, abfd,
13859 globals->bfd_of_glue_owner,
13860 THUMB2ARM_GLUE_SECTION_NAME))
13861 return FALSE;
13862
13863 if (! elf32_arm_output_glue_section (info, abfd,
13864 globals->bfd_of_glue_owner,
13865 VFP11_ERRATUM_VENEER_SECTION_NAME))
13866 return FALSE;
13867
a504d23a
LA		 13868 if (! elf32_arm_output_glue_section (info, abfd,
13869 globals->bfd_of_glue_owner,
13870 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13871 return FALSE;
13872
3e6b1042
DJ		 13873 if (! elf32_arm_output_glue_section (info, abfd,
13874 globals->bfd_of_glue_owner,
13875 ARM_BX_GLUE_SECTION_NAME))
13876 return FALSE;
13877 }
13878
13879 return TRUE;
13880}
13881
5968a7b8
NC		 13882/* Return a best guess for the machine number based on the attributes. */
13883
13884static unsigned int
13885bfd_arm_get_mach_from_attributes (bfd * abfd)
13886{
13887 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13888
13889 switch (arch)
13890 {
c0c468d5 13891 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13892 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13893 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13894 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13895
13896 case TAG_CPU_ARCH_V5TE:
13897 {
13898 char * name;
13899
13900 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13901 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13902
13903 if (name)
13904 {
13905 if (strcmp (name, "IWMMXT2") == 0)
13906 return bfd_mach_arm_iWMMXt2;
13907
13908 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13909 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13910
13911 if (strcmp (name, "XSCALE") == 0)
13912 {
13913 int wmmx;
13914
13915 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13916 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13917 switch (wmmx)
13918 {
13919 case 1: return bfd_mach_arm_iWMMXt;
13920 case 2: return bfd_mach_arm_iWMMXt2;
13921 default: return bfd_mach_arm_XScale;
13922 }
13923 }
5968a7b8
NC		 13924 }
13925
13926 return bfd_mach_arm_5TE;
13927 }
13928
c0c468d5
TP		 13929 case TAG_CPU_ARCH_V5TEJ:
13930 return bfd_mach_arm_5TEJ;
13931 case TAG_CPU_ARCH_V6:
13932 return bfd_mach_arm_6;
13933 case TAG_CPU_ARCH_V6KZ:
13934 return bfd_mach_arm_6KZ;
13935 case TAG_CPU_ARCH_V6T2:
13936 return bfd_mach_arm_6T2;
13937 case TAG_CPU_ARCH_V6K:
13938 return bfd_mach_arm_6K;
13939 case TAG_CPU_ARCH_V7:
13940 return bfd_mach_arm_7;
13941 case TAG_CPU_ARCH_V6_M:
13942 return bfd_mach_arm_6M;
13943 case TAG_CPU_ARCH_V6S_M:
13944 return bfd_mach_arm_6SM;
13945 case TAG_CPU_ARCH_V7E_M:
13946 return bfd_mach_arm_7EM;
13947 case TAG_CPU_ARCH_V8:
13948 return bfd_mach_arm_8;
13949 case TAG_CPU_ARCH_V8R:
13950 return bfd_mach_arm_8R;
13951 case TAG_CPU_ARCH_V8M_BASE:
13952 return bfd_mach_arm_8M_BASE;
13953 case TAG_CPU_ARCH_V8M_MAIN:
13954 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13955 case TAG_CPU_ARCH_V8_1M_MAIN:
13956 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13957
5968a7b8 13958 default:
c0c468d5
TP		 13959 /* Force entry to be added for any new known Tag_CPU_arch value. */
13960 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13961
13962 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13963 return bfd_mach_arm_unknown;
13964 }
13965}
13966
c178919b
NC		 13967/* Set the right machine number. */
13968
13969static bfd_boolean
57e8b36a 13970elf32_arm_object_p (bfd *abfd)
c178919b 13971{
5a6c6817 13972 unsigned int mach;
57e8b36a 13973
5a6c6817 13974 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13975
5968a7b8
NC		 13976 if (mach == bfd_mach_arm_unknown)
13977 {
13978 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13979 mach = bfd_mach_arm_ep9312;
13980 else
13981 mach = bfd_arm_get_mach_from_attributes (abfd);
13982 }
c178919b 13983
5968a7b8 13984 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13985 return TRUE;
13986}
13987
fc830a83 13988/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13989
b34976b6 13990static bfd_boolean
57e8b36a 13991elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13992{
13993 if (elf_flags_init (abfd)
13994 && elf_elfheader (abfd)->e_flags != flags)
13995 {
fc830a83
NC		 13996 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13997 {
fd2ec330 13998 if (flags & EF_ARM_INTERWORK)
4eca0228 13999 _bfd_error_handler
90b6238f 14000 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 14001 abfd);
fc830a83 14002 else
d003868e 14003 _bfd_error_handler
90b6238f 14004 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 14005 abfd);
fc830a83 14006 }
252b5132
RH		 14007 }
14008 else
14009 {
14010 elf_elfheader (abfd)->e_flags = flags;
b34976b6 14011 elf_flags_init (abfd) = TRUE;
252b5132
RH		 14012 }
14013
b34976b6 14014 return TRUE;
252b5132
RH		 14015}
14016
fc830a83 14017/* Copy backend specific data from one object module to another. */
9b485d32 14018
b34976b6 14019static bfd_boolean
57e8b36a 14020elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 14021{
14022 flagword in_flags;
14023 flagword out_flags;
14024
0ffa91dd 14025 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 14026 return TRUE;
252b5132 14027
fc830a83 14028 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 14029 out_flags = elf_elfheader (obfd)->e_flags;
14030
fc830a83
NC		 14031 if (elf_flags_init (obfd)
14032 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
14033 && in_flags != out_flags)
252b5132 14034 {
252b5132 14035 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 14036 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 14037 return FALSE;
252b5132
RH		 14038
14039 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 14040 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 14041 return FALSE;
252b5132
RH		 14042
14043 /* If the src and dest have different interworking flags
99059e56 14044 then turn off the interworking bit. */
fd2ec330 14045 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 14046 {
fd2ec330 14047 if (out_flags & EF_ARM_INTERWORK)
d003868e 14048 _bfd_error_handler
90b6238f 14049 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 14050 obfd, ibfd);
252b5132 14051
fd2ec330 14052 in_flags &= ~EF_ARM_INTERWORK;
252b5132 14053 }
1006ba19
PB		 14054
14055 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 14056 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
14057 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 14058 }
14059
14060 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 14061 elf_flags_init (obfd) = TRUE;
252b5132 14062
e2349352 14063 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 14064}
14065
14066/* Values for Tag_ABI_PCS_R9_use. */
14067enum
14068{
14069 AEABI_R9_V6,
14070 AEABI_R9_SB,
14071 AEABI_R9_TLS,
14072 AEABI_R9_unused
14073};
14074
14075/* Values for Tag_ABI_PCS_RW_data. */
14076enum
14077{
14078 AEABI_PCS_RW_data_absolute,
14079 AEABI_PCS_RW_data_PCrel,
14080 AEABI_PCS_RW_data_SBrel,
14081 AEABI_PCS_RW_data_unused
14082};
14083
14084/* Values for Tag_ABI_enum_size. */
14085enum
14086{
14087 AEABI_enum_unused,
14088 AEABI_enum_short,
14089 AEABI_enum_wide,
14090 AEABI_enum_forced_wide
14091};
14092
104d59d1
JM		 14093/* Determine whether an object attribute tag takes an integer, a
14094 string or both. */
906e58ca 14095
104d59d1
JM		 14096static int
14097elf32_arm_obj_attrs_arg_type (int tag)
14098{
14099 if (tag == Tag_compatibility)
3483fe2e 14100 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14101 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14102 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14103 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14104 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14105 else if (tag < 32)
3483fe2e 14106 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14107 else
3483fe2e 14108 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14109}
14110
5aa6ff7c
AS		 14111/* The ABI defines that Tag_conformance should be emitted first, and that
14112 Tag_nodefaults should be second (if either is defined). This sets those
14113 two positions, and bumps up the position of all the remaining tags to
14114 compensate. */
14115static int
14116elf32_arm_obj_attrs_order (int num)
14117{
3de4a297 14118 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14119 return Tag_conformance;
3de4a297 14120 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14121 return Tag_nodefaults;
14122 if ((num - 2) < Tag_nodefaults)
14123 return num - 2;
14124 if ((num - 1) < Tag_conformance)
14125 return num - 1;
14126 return num;
14127}
14128
e8b36cd1
JM		 14129/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14130static bfd_boolean
14131elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14132{
14133 if ((tag & 127) < 64)
14134 {
14135 _bfd_error_handler
90b6238f 14136 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14137 abfd, tag);
14138 bfd_set_error (bfd_error_bad_value);
14139 return FALSE;
14140 }
14141 else
14142 {
14143 _bfd_error_handler
90b6238f 14144 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14145 abfd, tag);
14146 return TRUE;
14147 }
14148}
14149
91e22acd
AS		 14150/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14151 Returns -1 if no architecture could be read. */
14152
14153static int
14154get_secondary_compatible_arch (bfd *abfd)
14155{
14156 obj_attribute *attr =
14157 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14158
14159 /* Note: the tag and its argument below are uleb128 values, though
14160 currently-defined values fit in one byte for each. */
14161 if (attr->s
14162 && attr->s[0] == Tag_CPU_arch
14163 && (attr->s[1] & 128) != 128
14164 && attr->s[2] == 0)
14165 return attr->s[1];
14166
14167 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14168 return -1;
14169}
14170
14171/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14172 The tag is removed if ARCH is -1. */
14173
8e79c3df 14174static void
91e22acd 14175set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14176{
91e22acd
AS		 14177 obj_attribute *attr =
14178 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14179
91e22acd
AS		 14180 if (arch == -1)
14181 {
14182 attr->s = NULL;
14183 return;
8e79c3df 14184 }
91e22acd
AS		 14185
14186 /* Note: the tag and its argument below are uleb128 values, though
14187 currently-defined values fit in one byte for each. */
14188 if (!attr->s)
21d799b5 14189 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14190 attr->s[0] = Tag_CPU_arch;
14191 attr->s[1] = arch;
14192 attr->s[2] = '\0';
8e79c3df
CM		 14193}
14194
91e22acd
AS		 14195/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14196 into account. */
14197
14198static int
14199tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14200 int newtag, int secondary_compat)
8e79c3df 14201{
91e22acd
AS		 14202#define T(X) TAG_CPU_ARCH_##X
14203 int tagl, tagh, result;
14204 const int v6t2[] =
14205 {
14206 T(V6T2), /* PRE_V4. */
14207 T(V6T2), /* V4. */
14208 T(V6T2), /* V4T. */
14209 T(V6T2), /* V5T. */
14210 T(V6T2), /* V5TE. */
14211 T(V6T2), /* V5TEJ. */
14212 T(V6T2), /* V6. */
14213 T(V7), /* V6KZ. */
14214 T(V6T2) /* V6T2. */
14215 };
14216 const int v6k[] =
14217 {
14218 T(V6K), /* PRE_V4. */
14219 T(V6K), /* V4. */
14220 T(V6K), /* V4T. */
14221 T(V6K), /* V5T. */
14222 T(V6K), /* V5TE. */
14223 T(V6K), /* V5TEJ. */
14224 T(V6K), /* V6. */
14225 T(V6KZ), /* V6KZ. */
14226 T(V7), /* V6T2. */
14227 T(V6K) /* V6K. */
14228 };
14229 const int v7[] =
14230 {
14231 T(V7), /* PRE_V4. */
14232 T(V7), /* V4. */
14233 T(V7), /* V4T. */
14234 T(V7), /* V5T. */
14235 T(V7), /* V5TE. */
14236 T(V7), /* V5TEJ. */
14237 T(V7), /* V6. */
14238 T(V7), /* V6KZ. */
14239 T(V7), /* V6T2. */
14240 T(V7), /* V6K. */
14241 T(V7) /* V7. */
14242 };
14243 const int v6_m[] =
14244 {
07d6d2b8
AM		 14245 -1, /* PRE_V4. */
14246 -1, /* V4. */
91e22acd
AS		 14247 T(V6K), /* V4T. */
14248 T(V6K), /* V5T. */
14249 T(V6K), /* V5TE. */
14250 T(V6K), /* V5TEJ. */
14251 T(V6K), /* V6. */
14252 T(V6KZ), /* V6KZ. */
14253 T(V7), /* V6T2. */
14254 T(V6K), /* V6K. */
14255 T(V7), /* V7. */
14256 T(V6_M) /* V6_M. */
14257 };
14258 const int v6s_m[] =
14259 {
07d6d2b8
AM		 14260 -1, /* PRE_V4. */
14261 -1, /* V4. */
91e22acd
AS		 14262 T(V6K), /* V4T. */
14263 T(V6K), /* V5T. */
14264 T(V6K), /* V5TE. */
14265 T(V6K), /* V5TEJ. */
14266 T(V6K), /* V6. */
14267 T(V6KZ), /* V6KZ. */
14268 T(V7), /* V6T2. */
14269 T(V6K), /* V6K. */
14270 T(V7), /* V7. */
14271 T(V6S_M), /* V6_M. */
14272 T(V6S_M) /* V6S_M. */
14273 };
9e3c6df6
PB		 14274 const int v7e_m[] =
14275 {
07d6d2b8
AM		 14276 -1, /* PRE_V4. */
14277 -1, /* V4. */
9e3c6df6
PB		 14278 T(V7E_M), /* V4T. */
14279 T(V7E_M), /* V5T. */
14280 T(V7E_M), /* V5TE. */
14281 T(V7E_M), /* V5TEJ. */
14282 T(V7E_M), /* V6. */
14283 T(V7E_M), /* V6KZ. */
14284 T(V7E_M), /* V6T2. */
14285 T(V7E_M), /* V6K. */
14286 T(V7E_M), /* V7. */
14287 T(V7E_M), /* V6_M. */
14288 T(V7E_M), /* V6S_M. */
14289 T(V7E_M) /* V7E_M. */
14290 };
bca38921
MGD		 14291 const int v8[] =
14292 {
14293 T(V8), /* PRE_V4. */
14294 T(V8), /* V4. */
14295 T(V8), /* V4T. */
14296 T(V8), /* V5T. */
14297 T(V8), /* V5TE. */
14298 T(V8), /* V5TEJ. */
14299 T(V8), /* V6. */
14300 T(V8), /* V6KZ. */
14301 T(V8), /* V6T2. */
14302 T(V8), /* V6K. */
14303 T(V8), /* V7. */
14304 T(V8), /* V6_M. */
14305 T(V8), /* V6S_M. */
14306 T(V8), /* V7E_M. */
14307 T(V8) /* V8. */
14308 };
bff0500d
TP		 14309 const int v8r[] =
14310 {
14311 T(V8R), /* PRE_V4. */
14312 T(V8R), /* V4. */
14313 T(V8R), /* V4T. */
14314 T(V8R), /* V5T. */
14315 T(V8R), /* V5TE. */
14316 T(V8R), /* V5TEJ. */
14317 T(V8R), /* V6. */
14318 T(V8R), /* V6KZ. */
14319 T(V8R), /* V6T2. */
14320 T(V8R), /* V6K. */
14321 T(V8R), /* V7. */
14322 T(V8R), /* V6_M. */
14323 T(V8R), /* V6S_M. */
14324 T(V8R), /* V7E_M. */
14325 T(V8), /* V8. */
14326 T(V8R), /* V8R. */
14327 };
2fd158eb
TP		 14328 const int v8m_baseline[] =
14329 {
14330 -1, /* PRE_V4. */
14331 -1, /* V4. */
14332 -1, /* V4T. */
14333 -1, /* V5T. */
14334 -1, /* V5TE. */
14335 -1, /* V5TEJ. */
14336 -1, /* V6. */
14337 -1, /* V6KZ. */
14338 -1, /* V6T2. */
14339 -1, /* V6K. */
14340 -1, /* V7. */
14341 T(V8M_BASE), /* V6_M. */
14342 T(V8M_BASE), /* V6S_M. */
14343 -1, /* V7E_M. */
14344 -1, /* V8. */
bff0500d 14345 -1, /* V8R. */
2fd158eb
TP		 14346 T(V8M_BASE) /* V8-M BASELINE. */
14347 };
14348 const int v8m_mainline[] =
14349 {
14350 -1, /* PRE_V4. */
14351 -1, /* V4. */
14352 -1, /* V4T. */
14353 -1, /* V5T. */
14354 -1, /* V5TE. */
14355 -1, /* V5TEJ. */
14356 -1, /* V6. */
14357 -1, /* V6KZ. */
14358 -1, /* V6T2. */
14359 -1, /* V6K. */
14360 T(V8M_MAIN), /* V7. */
14361 T(V8M_MAIN), /* V6_M. */
14362 T(V8M_MAIN), /* V6S_M. */
14363 T(V8M_MAIN), /* V7E_M. */
14364 -1, /* V8. */
bff0500d 14365 -1, /* V8R. */
2fd158eb
TP		 14366 T(V8M_MAIN), /* V8-M BASELINE. */
14367 T(V8M_MAIN) /* V8-M MAINLINE. */
14368 };
031254f2
AV		 14369 const int v8_1m_mainline[] =
14370 {
14371 -1, /* PRE_V4. */
14372 -1, /* V4. */
14373 -1, /* V4T. */
14374 -1, /* V5T. */
14375 -1, /* V5TE. */
14376 -1, /* V5TEJ. */
14377 -1, /* V6. */
14378 -1, /* V6KZ. */
14379 -1, /* V6T2. */
14380 -1, /* V6K. */
14381 T(V8_1M_MAIN), /* V7. */
14382 T(V8_1M_MAIN), /* V6_M. */
14383 T(V8_1M_MAIN), /* V6S_M. */
14384 T(V8_1M_MAIN), /* V7E_M. */
14385 -1, /* V8. */
14386 -1, /* V8R. */
14387 T(V8_1M_MAIN), /* V8-M BASELINE. */
14388 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14389 -1, /* Unused (18). */
14390 -1, /* Unused (19). */
14391 -1, /* Unused (20). */
14392 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14393 };
91e22acd
AS		 14394 const int v4t_plus_v6_m[] =
14395 {
14396 -1, /* PRE_V4. */
14397 -1, /* V4. */
14398 T(V4T), /* V4T. */
14399 T(V5T), /* V5T. */
14400 T(V5TE), /* V5TE. */
14401 T(V5TEJ), /* V5TEJ. */
14402 T(V6), /* V6. */
14403 T(V6KZ), /* V6KZ. */
14404 T(V6T2), /* V6T2. */
14405 T(V6K), /* V6K. */
14406 T(V7), /* V7. */
14407 T(V6_M), /* V6_M. */
14408 T(V6S_M), /* V6S_M. */
9e3c6df6 14409 T(V7E_M), /* V7E_M. */
bca38921 14410 T(V8), /* V8. */
bff0500d 14411 -1, /* V8R. */
2fd158eb
TP		 14412 T(V8M_BASE), /* V8-M BASELINE. */
14413 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14414 -1, /* Unused (18). */
14415 -1, /* Unused (19). */
14416 -1, /* Unused (20). */
14417 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14418 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14419 };
14420 const int *comb[] =
14421 {
14422 v6t2,
14423 v6k,
14424 v7,
14425 v6_m,
14426 v6s_m,
9e3c6df6 14427 v7e_m,
bca38921 14428 v8,
bff0500d 14429 v8r,
2fd158eb
TP		 14430 v8m_baseline,
14431 v8m_mainline,
031254f2
AV		 14432 NULL,
14433 NULL,
14434 NULL,
14435 v8_1m_mainline,
91e22acd
AS		 14436 /* Pseudo-architecture. */
14437 v4t_plus_v6_m
14438 };
14439
14440 /* Check we've not got a higher architecture than we know about. */
14441
9e3c6df6 14442 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14443 {
90b6238f 14444 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14445 return -1;
14446 }
14447
14448 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14449
14450 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14451 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14452 oldtag = T(V4T_PLUS_V6_M);
14453
14454 /* And override the new tag if we have a Tag_also_compatible_with on the
14455 input. */
14456
14457 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14458 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14459 newtag = T(V4T_PLUS_V6_M);
14460
14461 tagl = (oldtag < newtag) ? oldtag : newtag;
14462 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14463
14464 /* Architectures before V6KZ add features monotonically. */
14465 if (tagh <= TAG_CPU_ARCH_V6KZ)
14466 return result;
14467
4ed7ed8d 14468 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14469
14470 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14471 as the canonical version. */
14472 if (result == T(V4T_PLUS_V6_M))
14473 {
14474 result = T(V4T);
14475 *secondary_compat_out = T(V6_M);
14476 }
14477 else
14478 *secondary_compat_out = -1;
14479
14480 if (result == -1)
14481 {
90b6238f 14482 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14483 ibfd, oldtag, newtag);
14484 return -1;
14485 }
14486
14487 return result;
14488#undef T
8e79c3df
CM		 14489}
14490
ac56ee8f
MGD		 14491/* Query attributes object to see if integer divide instructions may be
14492 present in an object. */
14493static bfd_boolean
14494elf32_arm_attributes_accept_div (const obj_attribute *attr)
14495{
14496 int arch = attr[Tag_CPU_arch].i;
14497 int profile = attr[Tag_CPU_arch_profile].i;
14498
14499 switch (attr[Tag_DIV_use].i)
14500 {
14501 case 0:
14502 /* Integer divide allowed if instruction contained in archetecture. */
14503 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14504 return TRUE;
14505 else if (arch >= TAG_CPU_ARCH_V7E_M)
14506 return TRUE;
14507 else
14508 return FALSE;
14509
14510 case 1:
14511 /* Integer divide explicitly prohibited. */
14512 return FALSE;
14513
14514 default:
14515 /* Unrecognised case - treat as allowing divide everywhere. */
14516 case 2:
14517 /* Integer divide allowed in ARM state. */
14518 return TRUE;
14519 }
14520}
14521
14522/* Query attributes object to see if integer divide instructions are
14523 forbidden to be in the object. This is not the inverse of
14524 elf32_arm_attributes_accept_div. */
14525static bfd_boolean
14526elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14527{
14528 return attr[Tag_DIV_use].i == 1;
14529}
14530
ee065d83
PB		 14531/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14532 are conflicting attributes. */
906e58ca 14533
ee065d83 14534static bfd_boolean
50e03d47 14535elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14536{
50e03d47 14537 bfd *obfd = info->output_bfd;
104d59d1
JM		 14538 obj_attribute *in_attr;
14539 obj_attribute *out_attr;
ee065d83
PB		 14540 /* Some tags have 0 = don't care, 1 = strong requirement,
14541 2 = weak requirement. */
91e22acd 14542 static const int order_021[3] = {0, 2, 1};
ee065d83 14543 int i;
91e22acd 14544 bfd_boolean result = TRUE;
9274e9de 14545 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14546
3e6b1042
DJ		 14547 /* Skip the linker stubs file. This preserves previous behavior
14548 of accepting unknown attributes in the first input file - but
14549 is that a bug? */
14550 if (ibfd->flags & BFD_LINKER_CREATED)
14551 return TRUE;
14552
9274e9de
TG		 14553 /* Skip any input that hasn't attribute section.
14554 This enables to link object files without attribute section with
14555 any others. */
14556 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14557 return TRUE;
14558
104d59d1 14559 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14560 {
14561 /* This is the first object. Copy the attributes. */
104d59d1 14562 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14563
cd21e546
MGD		 14564 out_attr = elf_known_obj_attributes_proc (obfd);
14565
004ae526
PB		 14566 /* Use the Tag_null value to indicate the attributes have been
14567 initialized. */
cd21e546 14568 out_attr[0].i = 1;
004ae526 14569
cd21e546
MGD		 14570 /* We do not output objects with Tag_MPextension_use_legacy - we move
14571 the attribute's value to Tag_MPextension_use. */
14572 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14573 {
14574 if (out_attr[Tag_MPextension_use].i != 0
14575 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14576 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14577 {
14578 _bfd_error_handler
871b3ab2 14579 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14580 "Tag_MPextension_use attributes"), ibfd);
14581 result = FALSE;
14582 }
14583
14584 out_attr[Tag_MPextension_use] =
14585 out_attr[Tag_MPextension_use_legacy];
14586 out_attr[Tag_MPextension_use_legacy].type = 0;
14587 out_attr[Tag_MPextension_use_legacy].i = 0;
14588 }
14589
14590 return result;
ee065d83
PB		 14591 }
14592
104d59d1
JM		 14593 in_attr = elf_known_obj_attributes_proc (ibfd);
14594 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14595 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14596 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14597 {
5c294fee
TG		 14598 /* Ignore mismatches if the object doesn't use floating point or is
14599 floating point ABI independent. */
14600 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14601 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14602 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14603 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14604 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14605 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14606 {
14607 _bfd_error_handler
871b3ab2 14608 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14609 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14610 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14611 result = FALSE;
ee065d83
PB		 14612 }
14613 }
14614
3de4a297 14615 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14616 {
14617 /* Merge this attribute with existing attributes. */
14618 switch (i)
14619 {
14620 case Tag_CPU_raw_name:
14621 case Tag_CPU_name:
6a631e86 14622 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14623 break;
14624
14625 case Tag_ABI_optimization_goals:
14626 case Tag_ABI_FP_optimization_goals:
14627 /* Use the first value seen. */
14628 break;
14629
14630 case Tag_CPU_arch:
91e22acd
AS		 14631 {
14632 int secondary_compat = -1, secondary_compat_out = -1;
14633 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14634 int arch_attr;
14635 static const char *name_table[] =
14636 {
91e22acd
AS		 14637 /* These aren't real CPU names, but we can't guess
14638 that from the architecture version alone. */
14639 "Pre v4",
14640 "ARM v4",
14641 "ARM v4T",
14642 "ARM v5T",
14643 "ARM v5TE",
14644 "ARM v5TEJ",
14645 "ARM v6",
14646 "ARM v6KZ",
14647 "ARM v6T2",
14648 "ARM v6K",
14649 "ARM v7",
14650 "ARM v6-M",
bca38921 14651 "ARM v6S-M",
2fd158eb
TP		 14652 "ARM v8",
14653 "",
14654 "ARM v8-M.baseline",
14655 "ARM v8-M.mainline",
91e22acd
AS		 14656 };
14657
14658 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14659 secondary_compat = get_secondary_compatible_arch (ibfd);
14660 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14661 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14662 &secondary_compat_out,
14663 in_attr[i].i,
14664 secondary_compat);
14665
14666 /* Return with error if failed to merge. */
14667 if (arch_attr == -1)
14668 return FALSE;
14669
14670 out_attr[i].i = arch_attr;
14671
91e22acd
AS		 14672 set_secondary_compatible_arch (obfd, secondary_compat_out);
14673
14674 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14675 if (out_attr[i].i == saved_out_attr)
14676 ; /* Leave the names alone. */
14677 else if (out_attr[i].i == in_attr[i].i)
14678 {
14679 /* The output architecture has been changed to match the
14680 input architecture. Use the input names. */
14681 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14682 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14683 : NULL;
14684 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14685 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14686 : NULL;
14687 }
14688 else
14689 {
14690 out_attr[Tag_CPU_name].s = NULL;
14691 out_attr[Tag_CPU_raw_name].s = NULL;
14692 }
14693
14694 /* If we still don't have a value for Tag_CPU_name,
14695 make one up now. Tag_CPU_raw_name remains blank. */
14696 if (out_attr[Tag_CPU_name].s == NULL
14697 && out_attr[i].i < ARRAY_SIZE (name_table))
14698 out_attr[Tag_CPU_name].s =
14699 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14700 }
14701 break;
14702
ee065d83
PB		 14703 case Tag_ARM_ISA_use:
14704 case Tag_THUMB_ISA_use:
ee065d83 14705 case Tag_WMMX_arch:
91e22acd
AS		 14706 case Tag_Advanced_SIMD_arch:
14707 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14708 case Tag_ABI_FP_rounding:
ee065d83
PB		 14709 case Tag_ABI_FP_exceptions:
14710 case Tag_ABI_FP_user_exceptions:
14711 case Tag_ABI_FP_number_model:
75375b3e 14712 case Tag_FP_HP_extension:
91e22acd
AS		 14713 case Tag_CPU_unaligned_access:
14714 case Tag_T2EE_use:
91e22acd 14715 case Tag_MPextension_use:
a7ad558c 14716 case Tag_MVE_arch:
ee065d83
PB		 14717 /* Use the largest value specified. */
14718 if (in_attr[i].i > out_attr[i].i)
14719 out_attr[i].i = in_attr[i].i;
14720 break;
14721
75375b3e 14722 case Tag_ABI_align_preserved:
91e22acd
AS		 14723 case Tag_ABI_PCS_RO_data:
14724 /* Use the smallest value specified. */
14725 if (in_attr[i].i < out_attr[i].i)
14726 out_attr[i].i = in_attr[i].i;
14727 break;
14728
75375b3e 14729 case Tag_ABI_align_needed:
91e22acd 14730 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14731 && (in_attr[Tag_ABI_align_preserved].i == 0
14732 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14733 {
91e22acd
AS		 14734 /* This error message should be enabled once all non-conformant
14735 binaries in the toolchain have had the attributes set
14736 properly.
ee065d83 14737 _bfd_error_handler
871b3ab2 14738 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14739 obfd, ibfd);
14740 result = FALSE; */
ee065d83 14741 }
91e22acd
AS		 14742 /* Fall through. */
14743 case Tag_ABI_FP_denormal:
14744 case Tag_ABI_PCS_GOT_use:
14745 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14746 value if greater than 2 (for future-proofing). */
14747 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14748 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14749 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14750 out_attr[i].i = in_attr[i].i;
14751 break;
91e22acd 14752
75375b3e
MGD		 14753 case Tag_Virtualization_use:
14754 /* The virtualization tag effectively stores two bits of
14755 information: the intended use of TrustZone (in bit 0), and the
14756 intended use of Virtualization (in bit 1). */
14757 if (out_attr[i].i == 0)
14758 out_attr[i].i = in_attr[i].i;
14759 else if (in_attr[i].i != 0
14760 && in_attr[i].i != out_attr[i].i)
14761 {
14762 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14763 out_attr[i].i = 3;
14764 else
14765 {
14766 _bfd_error_handler
871b3ab2
AM		 14767 (_("error: %pB: unable to merge virtualization attributes "
14768 "with %pB"),
75375b3e
MGD		 14769 obfd, ibfd);
14770 result = FALSE;
14771 }
14772 }
14773 break;
91e22acd
AS		 14774
14775 case Tag_CPU_arch_profile:
14776 if (out_attr[i].i != in_attr[i].i)
14777 {
14778 /* 0 will merge with anything.
14779 'A' and 'S' merge to 'A'.
14780 'R' and 'S' merge to 'R'.
99059e56 14781 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14782 if (out_attr[i].i == 0
14783 || (out_attr[i].i == 'S'
14784 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14785 out_attr[i].i = in_attr[i].i;
14786 else if (in_attr[i].i == 0
14787 || (in_attr[i].i == 'S'
14788 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14789 ; /* Do nothing. */
91e22acd
AS		 14790 else
14791 {
14792 _bfd_error_handler
90b6238f 14793 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14794 ibfd,
14795 in_attr[i].i ? in_attr[i].i : '0',
14796 out_attr[i].i ? out_attr[i].i : '0');
14797 result = FALSE;
14798 }
14799 }
14800 break;
15afaa63
TP		 14801
14802 case Tag_DSP_extension:
14803 /* No need to change output value if any of:
14804 - pre (<=) ARMv5T input architecture (do not have DSP)
14805 - M input profile not ARMv7E-M and do not have DSP. */
14806 if (in_attr[Tag_CPU_arch].i <= 3
14807 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14808 && in_attr[Tag_CPU_arch].i != 13
14809 && in_attr[i].i == 0))
14810 ; /* Do nothing. */
14811 /* Output value should be 0 if DSP part of architecture, ie.
14812 - post (>=) ARMv5te architecture output
14813 - A, R or S profile output or ARMv7E-M output architecture. */
14814 else if (out_attr[Tag_CPU_arch].i >= 4
14815 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14816 || out_attr[Tag_CPU_arch_profile].i == 'R'
14817 || out_attr[Tag_CPU_arch_profile].i == 'S'
14818 || out_attr[Tag_CPU_arch].i == 13))
14819 out_attr[i].i = 0;
14820 /* Otherwise, DSP instructions are added and not part of output
14821 architecture. */
14822 else
14823 out_attr[i].i = 1;
14824 break;
14825
75375b3e 14826 case Tag_FP_arch:
62f3b8c8 14827 {
4547cb56
NC		 14828 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14829 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14830 when it's 0. It might mean absence of FP hardware if
99654aaf 14831 Tag_FP_arch is zero. */
4547cb56 14832
a715796b 14833#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14834 static const struct
14835 {
14836 int ver;
14837 int regs;
bca38921 14838 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14839 {
14840 {0, 0},
14841 {1, 16},
14842 {2, 16},
14843 {3, 32},
14844 {3, 16},
14845 {4, 32},
bca38921 14846 {4, 16},
a715796b
TG		 14847 {8, 32},
14848 {8, 16}
62f3b8c8
PB		 14849 };
14850 int ver;
14851 int regs;
14852 int newval;
14853
4547cb56
NC		 14854 /* If the output has no requirement about FP hardware,
14855 follow the requirement of the input. */
14856 if (out_attr[i].i == 0)
14857 {
4ec192e6
RE		 14858 /* This assert is still reasonable, we shouldn't
14859 produce the suspicious build attribute
14860 combination (See below for in_attr). */
4547cb56
NC		 14861 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14862 out_attr[i].i = in_attr[i].i;
14863 out_attr[Tag_ABI_HardFP_use].i
14864 = in_attr[Tag_ABI_HardFP_use].i;
14865 break;
14866 }
14867 /* If the input has no requirement about FP hardware, do
14868 nothing. */
14869 else if (in_attr[i].i == 0)
14870 {
4ec192e6
RE		 14871 /* We used to assert that Tag_ABI_HardFP_use was
14872 zero here, but we should never assert when
14873 consuming an object file that has suspicious
14874 build attributes. The single precision variant
14875 of 'no FP architecture' is still 'no FP
14876 architecture', so we just ignore the tag in this
14877 case. */
4547cb56
NC		 14878 break;
14879 }
14880
14881 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14882 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14883
14884 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14885 do nothing. */
14886 if (in_attr[Tag_ABI_HardFP_use].i == 0
14887 && out_attr[Tag_ABI_HardFP_use].i == 0)
14888 ;
14889 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14890 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14891 else if (in_attr[Tag_ABI_HardFP_use].i
14892 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14893 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14894
14895 /* Now we can handle Tag_FP_arch. */
14896
bca38921
MGD		 14897 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14898 pick the biggest. */
14899 if (in_attr[i].i >= VFP_VERSION_COUNT
14900 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14901 {
14902 out_attr[i] = in_attr[i];
14903 break;
14904 }
14905 /* The output uses the superset of input features
14906 (ISA version) and registers. */
14907 ver = vfp_versions[in_attr[i].i].ver;
14908 if (ver < vfp_versions[out_attr[i].i].ver)
14909 ver = vfp_versions[out_attr[i].i].ver;
14910 regs = vfp_versions[in_attr[i].i].regs;
14911 if (regs < vfp_versions[out_attr[i].i].regs)
14912 regs = vfp_versions[out_attr[i].i].regs;
14913 /* This assumes all possible supersets are also a valid
99059e56 14914 options. */
bca38921 14915 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14916 {
14917 if (regs == vfp_versions[newval].regs
14918 && ver == vfp_versions[newval].ver)
14919 break;
14920 }
14921 out_attr[i].i = newval;
14922 }
b1cc4aeb 14923 break;
ee065d83
PB		 14924 case Tag_PCS_config:
14925 if (out_attr[i].i == 0)
14926 out_attr[i].i = in_attr[i].i;
b6009aca 14927 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14928 {
14929 /* It's sometimes ok to mix different configs, so this is only
99059e56 14930 a warning. */
ee065d83 14931 _bfd_error_handler
90b6238f 14932 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14933 }
14934 break;
14935 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14936 if (in_attr[i].i != out_attr[i].i
14937 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14938 && in_attr[i].i != AEABI_R9_unused)
14939 {
14940 _bfd_error_handler
90b6238f 14941 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14942 result = FALSE;
ee065d83
PB		 14943 }
14944 if (out_attr[i].i == AEABI_R9_unused)
14945 out_attr[i].i = in_attr[i].i;
14946 break;
14947 case Tag_ABI_PCS_RW_data:
14948 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14949 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14950 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14951 {
14952 _bfd_error_handler
871b3ab2 14953 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14954 ibfd);
91e22acd 14955 result = FALSE;
ee065d83
PB		 14956 }
14957 /* Use the smallest value specified. */
14958 if (in_attr[i].i < out_attr[i].i)
14959 out_attr[i].i = in_attr[i].i;
14960 break;
ee065d83 14961 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14962 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14963 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14964 {
14965 _bfd_error_handler
871b3ab2 14966 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14967 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14968 }
a9dc9481 14969 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14970 out_attr[i].i = in_attr[i].i;
14971 break;
ee065d83
PB		 14972 case Tag_ABI_enum_size:
14973 if (in_attr[i].i != AEABI_enum_unused)
14974 {
14975 if (out_attr[i].i == AEABI_enum_unused
14976 || out_attr[i].i == AEABI_enum_forced_wide)
14977 {
14978 /* The existing object is compatible with anything.
14979 Use whatever requirements the new object has. */
14980 out_attr[i].i = in_attr[i].i;
14981 }
14982 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14983 && out_attr[i].i != in_attr[i].i
0ffa91dd 14984 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14985 {
91e22acd 14986 static const char *aeabi_enum_names[] =
bf21ed78 14987 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14988 const char *in_name =
14989 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14990 ? aeabi_enum_names[in_attr[i].i]
14991 : "<unknown>";
14992 const char *out_name =
14993 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14994 ? aeabi_enum_names[out_attr[i].i]
14995 : "<unknown>";
ee065d83 14996 _bfd_error_handler
871b3ab2 14997 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14998 ibfd, in_name, out_name);
ee065d83
PB		 14999 }
15000 }
15001 break;
15002 case Tag_ABI_VFP_args:
15003 /* Aready done. */
15004 break;
15005 case Tag_ABI_WMMX_args:
15006 if (in_attr[i].i != out_attr[i].i)
15007 {
15008 _bfd_error_handler
871b3ab2 15009 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 15010 ibfd, obfd);
91e22acd 15011 result = FALSE;
ee065d83
PB		 15012 }
15013 break;
7b86a9fa
AS		 15014 case Tag_compatibility:
15015 /* Merged in target-independent code. */
15016 break;
91e22acd 15017 case Tag_ABI_HardFP_use:
4547cb56 15018 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 15019 break;
15020 case Tag_ABI_FP_16bit_format:
15021 if (in_attr[i].i != 0 && out_attr[i].i != 0)
15022 {
15023 if (in_attr[i].i != out_attr[i].i)
15024 {
15025 _bfd_error_handler
871b3ab2 15026 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 15027 ibfd, obfd);
15028 result = FALSE;
15029 }
15030 }
15031 if (in_attr[i].i != 0)
15032 out_attr[i].i = in_attr[i].i;
15033 break;
7b86a9fa 15034
cd21e546 15035 case Tag_DIV_use:
ac56ee8f
MGD		 15036 /* A value of zero on input means that the divide instruction may
15037 be used if available in the base architecture as specified via
15038 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15039 the user did not want divide instructions. A value of 2
15040 explicitly means that divide instructions were allowed in ARM
15041 and Thumb state. */
15042 if (in_attr[i].i == out_attr[i].i)
15043 /* Do nothing. */ ;
15044 else if (elf32_arm_attributes_forbid_div (in_attr)
15045 && !elf32_arm_attributes_accept_div (out_attr))
15046 out_attr[i].i = 1;
15047 else if (elf32_arm_attributes_forbid_div (out_attr)
15048 && elf32_arm_attributes_accept_div (in_attr))
15049 out_attr[i].i = in_attr[i].i;
15050 else if (in_attr[i].i == 2)
15051 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 15052 break;
15053
15054 case Tag_MPextension_use_legacy:
15055 /* We don't output objects with Tag_MPextension_use_legacy - we
15056 move the value to Tag_MPextension_use. */
15057 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
15058 {
15059 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
15060 {
15061 _bfd_error_handler
871b3ab2 15062 (_("%pB has both the current and legacy "
b38cadfb 15063 "Tag_MPextension_use attributes"),
cd21e546
MGD		 15064 ibfd);
15065 result = FALSE;
15066 }
15067 }
15068
15069 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15070 out_attr[Tag_MPextension_use] = in_attr[i];
15071
15072 break;
15073
91e22acd 15074 case Tag_nodefaults:
2d0bb761
AS		 15075 /* This tag is set if it exists, but the value is unused (and is
15076 typically zero). We don't actually need to do anything here -
15077 the merge happens automatically when the type flags are merged
15078 below. */
91e22acd
AS		 15079 break;
15080 case Tag_also_compatible_with:
15081 /* Already done in Tag_CPU_arch. */
15082 break;
15083 case Tag_conformance:
15084 /* Keep the attribute if it matches. Throw it away otherwise.
15085 No attribute means no claim to conform. */
15086 if (!in_attr[i].s || !out_attr[i].s
15087 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15088 out_attr[i].s = NULL;
15089 break;
3cfad14c 15090
91e22acd 15091 default:
e8b36cd1
JM		 15092 result
15093 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15094 }
15095
15096 /* If out_attr was copied from in_attr then it won't have a type yet. */
15097 if (in_attr[i].type && !out_attr[i].type)
15098 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15099 }
15100
104d59d1 15101 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15102 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15103 return FALSE;
ee065d83 15104
104d59d1 15105 /* Check for any attributes not known on ARM. */
e8b36cd1 15106 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15107
91e22acd 15108 return result;
252b5132
RH		 15109}
15110
3a4a14e9
PB		 15111
15112/* Return TRUE if the two EABI versions are incompatible. */
15113
15114static bfd_boolean
15115elf32_arm_versions_compatible (unsigned iver, unsigned over)
15116{
15117 /* v4 and v5 are the same spec before and after it was released,
15118 so allow mixing them. */
15119 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15120 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15121 return TRUE;
15122
15123 return (iver == over);
15124}
15125
252b5132
RH		 15126/* Merge backend specific data from an object file to the output
15127 object file when linking. */
9b485d32 15128
b34976b6 15129static bfd_boolean
50e03d47 15130elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15131
9b485d32
NC		 15132/* Display the flags field. */
15133
b34976b6 15134static bfd_boolean
57e8b36a 15135elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15136{
fc830a83
NC		 15137 FILE * file = (FILE *) ptr;
15138 unsigned long flags;
252b5132
RH		 15139
15140 BFD_ASSERT (abfd != NULL && ptr != NULL);
15141
15142 /* Print normal ELF private data. */
15143 _bfd_elf_print_private_bfd_data (abfd, ptr);
15144
fc830a83 15145 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15146 /* Ignore init flag - it may not be set, despite the flags field
15147 containing valid data. */
252b5132 15148
9b485d32 15149 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15150
fc830a83
NC		 15151 switch (EF_ARM_EABI_VERSION (flags))
15152 {
15153 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15154 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15155 official ARM ELF extended ABI. Hence they are only decoded if
15156 the EABI version is not set. */
fd2ec330 15157 if (flags & EF_ARM_INTERWORK)
9b485d32 15158 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15159
fd2ec330 15160 if (flags & EF_ARM_APCS_26)
6c571f00 15161 fprintf (file, " [APCS-26]");
fc830a83 15162 else
6c571f00 15163 fprintf (file, " [APCS-32]");
9a5aca8c 15164
96a846ea
RE		 15165 if (flags & EF_ARM_VFP_FLOAT)
15166 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15167 else if (flags & EF_ARM_MAVERICK_FLOAT)
15168 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15169 else
15170 fprintf (file, _(" [FPA float format]"));
15171
fd2ec330 15172 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15173 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15174
fd2ec330 15175 if (flags & EF_ARM_PIC)
9b485d32 15176 fprintf (file, _(" [position independent]"));
fc830a83 15177
fd2ec330 15178 if (flags & EF_ARM_NEW_ABI)
9b485d32 15179 fprintf (file, _(" [new ABI]"));
9a5aca8c 15180
fd2ec330 15181 if (flags & EF_ARM_OLD_ABI)
9b485d32 15182 fprintf (file, _(" [old ABI]"));
9a5aca8c 15183
fd2ec330 15184 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15185 fprintf (file, _(" [software FP]"));
9a5aca8c 15186
96a846ea
RE		 15187 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15188 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15189 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15190 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15191 break;
9a5aca8c 15192
fc830a83 15193 case EF_ARM_EABI_VER1:
9b485d32 15194 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15195
fc830a83 15196 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15197 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15198 else
9b485d32 15199 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15200
fc830a83
NC		 15201 flags &= ~ EF_ARM_SYMSARESORTED;
15202 break;
9a5aca8c 15203
fd2ec330
PB		 15204 case EF_ARM_EABI_VER2:
15205 fprintf (file, _(" [Version2 EABI]"));
15206
15207 if (flags & EF_ARM_SYMSARESORTED)
15208 fprintf (file, _(" [sorted symbol table]"));
15209 else
15210 fprintf (file, _(" [unsorted symbol table]"));
15211
15212 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15213 fprintf (file, _(" [dynamic symbols use segment index]"));
15214
15215 if (flags & EF_ARM_MAPSYMSFIRST)
15216 fprintf (file, _(" [mapping symbols precede others]"));
15217
99e4ae17 15218 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15219 | EF_ARM_MAPSYMSFIRST);
15220 break;
15221
d507cf36
PB		 15222 case EF_ARM_EABI_VER3:
15223 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15224 break;
15225
15226 case EF_ARM_EABI_VER4:
15227 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15228 goto eabi;
d507cf36 15229
3a4a14e9
PB		 15230 case EF_ARM_EABI_VER5:
15231 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15232
15233 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15234 fprintf (file, _(" [soft-float ABI]"));
15235
15236 if (flags & EF_ARM_ABI_FLOAT_HARD)
15237 fprintf (file, _(" [hard-float ABI]"));
15238
15239 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15240
3a4a14e9 15241 eabi:
d507cf36
PB		 15242 if (flags & EF_ARM_BE8)
15243 fprintf (file, _(" [BE8]"));
15244
15245 if (flags & EF_ARM_LE8)
15246 fprintf (file, _(" [LE8]"));
15247
15248 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15249 break;
15250
fc830a83 15251 default:
9b485d32 15252 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15253 break;
15254 }
252b5132 15255
fc830a83 15256 flags &= ~ EF_ARM_EABIMASK;
252b5132 15257
fc830a83 15258 if (flags & EF_ARM_RELEXEC)
9b485d32 15259 fprintf (file, _(" [relocatable executable]"));
252b5132 15260
18a20338
CL		 15261 if (flags & EF_ARM_PIC)
15262 fprintf (file, _(" [position independent]"));
15263
15264 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15265 fprintf (file, _(" [FDPIC ABI supplement]"));
15266
15267 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15268
15269 if (flags)
9b485d32 15270 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15271
252b5132
RH		 15272 fputc ('\n', file);
15273
b34976b6 15274 return TRUE;
252b5132
RH		 15275}
15276
15277static int
57e8b36a 15278elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15279{
2f0ca46a
NC		 15280 switch (ELF_ST_TYPE (elf_sym->st_info))
15281 {
15282 case STT_ARM_TFUNC:
15283 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15284
2f0ca46a
NC		 15285 case STT_ARM_16BIT:
15286 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15287 This allows us to distinguish between data used by Thumb instructions
15288 and non-data (which is probably code) inside Thumb regions of an
15289 executable. */
1a0eb693 15290 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15291 return ELF_ST_TYPE (elf_sym->st_info);
15292 break;
9a5aca8c 15293
ce855c42
NC		 15294 default:
15295 break;
2f0ca46a
NC		 15296 }
15297
15298 return type;
252b5132 15299}
f21f3fe0 15300
252b5132 15301static asection *
07adf181
AM		 15302elf32_arm_gc_mark_hook (asection *sec,
15303 struct bfd_link_info *info,
15304 Elf_Internal_Rela *rel,
15305 struct elf_link_hash_entry *h,
15306 Elf_Internal_Sym *sym)
252b5132
RH		 15307{
15308 if (h != NULL)
07adf181 15309 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15310 {
15311 case R_ARM_GNU_VTINHERIT:
15312 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15313 return NULL;
15314 }
9ad5cbcf 15315
07adf181 15316 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15317}
15318
780a67af
NC		 15319/* Look through the relocs for a section during the first phase. */
15320
b34976b6 15321static bfd_boolean
57e8b36a
NC		 15322elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15323 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15324{
b34976b6
AM		 15325 Elf_Internal_Shdr *symtab_hdr;
15326 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15327 const Elf_Internal_Rela *rel;
15328 const Elf_Internal_Rela *rel_end;
15329 bfd *dynobj;
5e681ec4 15330 asection *sreloc;
5e681ec4 15331 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15332 bfd_boolean call_reloc_p;
15333 bfd_boolean may_become_dynamic_p;
15334 bfd_boolean may_need_local_target_p;
ce98a316 15335 unsigned long nsyms;
9a5aca8c 15336
0e1862bb 15337 if (bfd_link_relocatable (info))
b34976b6 15338 return TRUE;
9a5aca8c 15339
0ffa91dd
NC		 15340 BFD_ASSERT (is_arm_elf (abfd));
15341
5e681ec4 15342 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15343 if (htab == NULL)
15344 return FALSE;
15345
5e681ec4 15346 sreloc = NULL;
9a5aca8c 15347
67687978
PB		 15348 /* Create dynamic sections for relocatable executables so that we can
15349 copy relocations. */
15350 if (htab->root.is_relocatable_executable
15351 && ! htab->root.dynamic_sections_created)
15352 {
15353 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15354 return FALSE;
15355 }
15356
cbc704f3
RS		 15357 if (htab->root.dynobj == NULL)
15358 htab->root.dynobj = abfd;
34e77a92
RS		 15359 if (!create_ifunc_sections (info))
15360 return FALSE;
cbc704f3
RS		 15361
15362 dynobj = htab->root.dynobj;
15363
0ffa91dd 15364 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15365 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15366 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15367
252b5132
RH		 15368 rel_end = relocs + sec->reloc_count;
15369 for (rel = relocs; rel < rel_end; rel++)
15370 {
34e77a92 15371 Elf_Internal_Sym *isym;
252b5132 15372 struct elf_link_hash_entry *h;
b7693d02 15373 struct elf32_arm_link_hash_entry *eh;
d42c267e 15374 unsigned int r_symndx;
eb043451 15375 int r_type;
9a5aca8c 15376
252b5132 15377 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15378 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15379 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15380
ce98a316
NC		 15381 if (r_symndx >= nsyms
15382 /* PR 9934: It is possible to have relocations that do not
15383 refer to symbols, thus it is also possible to have an
15384 object file containing relocations but no symbol table. */
cf35638d 15385 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15386 {
871b3ab2 15387 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15388 r_symndx);
ba93b8ac
DJ		 15389 return FALSE;
15390 }
15391
34e77a92
RS		 15392 h = NULL;
15393 isym = NULL;
15394 if (nsyms > 0)
973a3492 15395 {
34e77a92
RS		 15396 if (r_symndx < symtab_hdr->sh_info)
15397 {
15398 /* A local symbol. */
15399 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15400 abfd, r_symndx);
15401 if (isym == NULL)
15402 return FALSE;
15403 }
15404 else
15405 {
15406 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15407 while (h->root.type == bfd_link_hash_indirect
15408 || h->root.type == bfd_link_hash_warning)
15409 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15410 }
973a3492 15411 }
9a5aca8c 15412
b7693d02
DJ		 15413 eh = (struct elf32_arm_link_hash_entry *) h;
15414
f6e32f6d
RS		 15415 call_reloc_p = FALSE;
15416 may_become_dynamic_p = FALSE;
15417 may_need_local_target_p = FALSE;
15418
0855e32b
NS		 15419 /* Could be done earlier, if h were already available. */
15420 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15421 switch (r_type)
99059e56 15422 {
e8b09b87
CL		 15423 case R_ARM_GOTOFFFUNCDESC:
15424 {
15425 if (h == NULL)
15426 {
15427 if (!elf32_arm_allocate_local_sym_info (abfd))
15428 return FALSE;
15429 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15430 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15431 }
15432 else
15433 {
15434 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15435 }
15436 }
15437 break;
15438
15439 case R_ARM_GOTFUNCDESC:
15440 {
15441 if (h == NULL)
15442 {
15443 /* Such a relocation is not supposed to be generated
15444 by gcc on a static function. */
15445 /* Anyway if needed it could be handled. */
15446 abort();
15447 }
15448 else
15449 {
15450 eh->fdpic_cnts.gotfuncdesc_cnt++;
15451 }
15452 }
15453 break;
15454
15455 case R_ARM_FUNCDESC:
15456 {
15457 if (h == NULL)
15458 {
15459 if (!elf32_arm_allocate_local_sym_info (abfd))
15460 return FALSE;
15461 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15462 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15463 }
15464 else
15465 {
15466 eh->fdpic_cnts.funcdesc_cnt++;
15467 }
15468 }
15469 break;
15470
5e681ec4 15471 case R_ARM_GOT32:
eb043451 15472 case R_ARM_GOT_PREL:
ba93b8ac 15473 case R_ARM_TLS_GD32:
5c5a4843 15474 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15475 case R_ARM_TLS_IE32:
5c5a4843 15476 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15477 case R_ARM_TLS_GOTDESC:
15478 case R_ARM_TLS_DESCSEQ:
15479 case R_ARM_THM_TLS_DESCSEQ:
15480 case R_ARM_TLS_CALL:
15481 case R_ARM_THM_TLS_CALL:
5e681ec4 15482 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15483 {
15484 int tls_type, old_tls_type;
5e681ec4 15485
ba93b8ac
DJ		 15486 switch (r_type)
15487 {
15488 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15489 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15490
ba93b8ac 15491 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15492 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15493
0855e32b
NS		 15494 case R_ARM_TLS_GOTDESC:
15495 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15496 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15497 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15498
ba93b8ac
DJ		 15499 default: tls_type = GOT_NORMAL; break;
15500 }
252b5132 15501
0e1862bb 15502 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15503 info->flags |= DF_STATIC_TLS;
15504
ba93b8ac
DJ		 15505 if (h != NULL)
15506 {
15507 h->got.refcount++;
15508 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15509 }
15510 else
15511 {
ba93b8ac 15512 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15513 if (!elf32_arm_allocate_local_sym_info (abfd))
15514 return FALSE;
15515 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15516 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15517 }
15518
0855e32b 15519 /* If a variable is accessed with both tls methods, two
99059e56 15520 slots may be created. */
0855e32b
NS		 15521 if (GOT_TLS_GD_ANY_P (old_tls_type)
15522 && GOT_TLS_GD_ANY_P (tls_type))
15523 tls_type |= old_tls_type;
15524
15525 /* We will already have issued an error message if there
15526 is a TLS/non-TLS mismatch, based on the symbol
15527 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15528 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15529 && tls_type != GOT_NORMAL)
15530 tls_type |= old_tls_type;
15531
0855e32b 15532 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15533 method, we're able to relax. Turn off the GDESC flag,
15534 without messing up with any other kind of tls types
6a631e86 15535 that may be involved. */
0855e32b
NS		 15536 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15537 tls_type &= ~GOT_TLS_GDESC;
15538
ba93b8ac
DJ		 15539 if (old_tls_type != tls_type)
15540 {
15541 if (h != NULL)
15542 elf32_arm_hash_entry (h)->tls_type = tls_type;
15543 else
15544 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15545 }
15546 }
8029a119 15547 /* Fall through. */
ba93b8ac
DJ		 15548
15549 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15550 case R_ARM_TLS_LDM32_FDPIC:
15551 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15552 htab->tls_ldm_got.refcount++;
8029a119 15553 /* Fall through. */
252b5132 15554
c19d1205 15555 case R_ARM_GOTOFF32:
5e681ec4 15556 case R_ARM_GOTPC:
cbc704f3
RS		 15557 if (htab->root.sgot == NULL
15558 && !create_got_section (htab->root.dynobj, info))
15559 return FALSE;
252b5132
RH		 15560 break;
15561
252b5132 15562 case R_ARM_PC24:
7359ea65 15563 case R_ARM_PLT32:
5b5bb741
PB		 15564 case R_ARM_CALL:
15565 case R_ARM_JUMP24:
eb043451 15566 case R_ARM_PREL31:
c19d1205 15567 case R_ARM_THM_CALL:
bd97cb95
DJ		 15568 case R_ARM_THM_JUMP24:
15569 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15570 call_reloc_p = TRUE;
15571 may_need_local_target_p = TRUE;
15572 break;
15573
15574 case R_ARM_ABS12:
15575 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15576 ldr __GOTT_INDEX__ offsets. */
15577 if (!htab->vxworks_p)
15578 {
15579 may_need_local_target_p = TRUE;
15580 break;
15581 }
aebf9be7 15582 else goto jump_over;
9eaff861 15583
f6e32f6d 15584 /* Fall through. */
39623e12 15585
96c23d59
JM		 15586 case R_ARM_MOVW_ABS_NC:
15587 case R_ARM_MOVT_ABS:
15588 case R_ARM_THM_MOVW_ABS_NC:
15589 case R_ARM_THM_MOVT_ABS:
0e1862bb 15590 if (bfd_link_pic (info))
96c23d59 15591 {
4eca0228 15592 _bfd_error_handler
871b3ab2 15593 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15594 abfd, elf32_arm_howto_table_1[r_type].name,
15595 (h) ? h->root.root.string : "a local symbol");
15596 bfd_set_error (bfd_error_bad_value);
15597 return FALSE;
15598 }
15599
15600 /* Fall through. */
39623e12
PB		 15601 case R_ARM_ABS32:
15602 case R_ARM_ABS32_NOI:
aebf9be7 15603 jump_over:
0e1862bb 15604 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15605 {
15606 h->pointer_equality_needed = 1;
15607 }
15608 /* Fall through. */
39623e12
PB		 15609 case R_ARM_REL32:
15610 case R_ARM_REL32_NOI:
b6895b4f
PB		 15611 case R_ARM_MOVW_PREL_NC:
15612 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15613 case R_ARM_THM_MOVW_PREL_NC:
15614 case R_ARM_THM_MOVT_PREL:
39623e12 15615
b7693d02 15616 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15617 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15618 || htab->fdpic_p)
34e77a92
RS		 15619 && (sec->flags & SEC_ALLOC) != 0)
15620 {
15621 if (h == NULL
469a3493 15622 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15623 {
15624 /* In shared libraries and relocatable executables,
15625 we treat local relative references as calls;
15626 see the related SYMBOL_CALLS_LOCAL code in
15627 allocate_dynrelocs. */
15628 call_reloc_p = TRUE;
15629 may_need_local_target_p = TRUE;
15630 }
15631 else
15632 /* We are creating a shared library or relocatable
15633 executable, and this is a reloc against a global symbol,
15634 or a non-PC-relative reloc against a local symbol.
15635 We may need to copy the reloc into the output. */
15636 may_become_dynamic_p = TRUE;
15637 }
f6e32f6d
RS		 15638 else
15639 may_need_local_target_p = TRUE;
252b5132
RH		 15640 break;
15641
99059e56
RM		 15642 /* This relocation describes the C++ object vtable hierarchy.
15643 Reconstruct it for later use during GC. */
15644 case R_ARM_GNU_VTINHERIT:
15645 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15646 return FALSE;
15647 break;
15648
15649 /* This relocation describes which C++ vtable entries are actually
15650 used. Record for later use during GC. */
15651 case R_ARM_GNU_VTENTRY:
a0ea3a14 15652 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15653 return FALSE;
15654 break;
15655 }
f6e32f6d
RS		 15656
15657 if (h != NULL)
15658 {
15659 if (call_reloc_p)
15660 /* We may need a .plt entry if the function this reloc
15661 refers to is in a different object, regardless of the
15662 symbol's type. We can't tell for sure yet, because
15663 something later might force the symbol local. */
15664 h->needs_plt = 1;
15665 else if (may_need_local_target_p)
15666 /* If this reloc is in a read-only section, we might
15667 need a copy reloc. We can't check reliably at this
15668 stage whether the section is read-only, as input
15669 sections have not yet been mapped to output sections.
15670 Tentatively set the flag for now, and correct in
15671 adjust_dynamic_symbol. */
15672 h->non_got_ref = 1;
15673 }
15674
34e77a92
RS		 15675 if (may_need_local_target_p
15676 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15677 {
34e77a92
RS		 15678 union gotplt_union *root_plt;
15679 struct arm_plt_info *arm_plt;
15680 struct arm_local_iplt_info *local_iplt;
15681
15682 if (h != NULL)
15683 {
15684 root_plt = &h->plt;
15685 arm_plt = &eh->plt;
15686 }
15687 else
15688 {
15689 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15690 if (local_iplt == NULL)
15691 return FALSE;
15692 root_plt = &local_iplt->root;
15693 arm_plt = &local_iplt->arm;
15694 }
15695
f6e32f6d
RS		 15696 /* If the symbol is a function that doesn't bind locally,
15697 this relocation will need a PLT entry. */
a8c887dd
NC		 15698 if (root_plt->refcount != -1)
15699 root_plt->refcount += 1;
34e77a92
RS		 15700
15701 if (!call_reloc_p)
15702 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15703
15704 /* It's too early to use htab->use_blx here, so we have to
15705 record possible blx references separately from
15706 relocs that definitely need a thumb stub. */
15707
15708 if (r_type == R_ARM_THM_CALL)
34e77a92 15709 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15710
15711 if (r_type == R_ARM_THM_JUMP24
15712 || r_type == R_ARM_THM_JUMP19)
34e77a92 15713 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15714 }
15715
15716 if (may_become_dynamic_p)
15717 {
15718 struct elf_dyn_relocs *p, **head;
15719
15720 /* Create a reloc section in dynobj. */
15721 if (sreloc == NULL)
15722 {
15723 sreloc = _bfd_elf_make_dynamic_reloc_section
15724 (sec, dynobj, 2, abfd, ! htab->use_rel);
15725
15726 if (sreloc == NULL)
15727 return FALSE;
15728
15729 /* BPABI objects never have dynamic relocations mapped. */
15730 if (htab->symbian_p)
15731 {
15732 flagword flags;
15733
15734 flags = bfd_get_section_flags (dynobj, sreloc);
15735 flags &= ~(SEC_LOAD | SEC_ALLOC);
15736 bfd_set_section_flags (dynobj, sreloc, flags);
15737 }
15738 }
15739
15740 /* If this is a global symbol, count the number of
15741 relocations we need for this symbol. */
15742 if (h != NULL)
15743 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15744 else
15745 {
34e77a92
RS		 15746 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15747 if (head == NULL)
f6e32f6d 15748 return FALSE;
f6e32f6d
RS		 15749 }
15750
15751 p = *head;
15752 if (p == NULL || p->sec != sec)
15753 {
15754 bfd_size_type amt = sizeof *p;
15755
15756 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15757 if (p == NULL)
15758 return FALSE;
15759 p->next = *head;
15760 *head = p;
15761 p->sec = sec;
15762 p->count = 0;
15763 p->pc_count = 0;
15764 }
15765
469a3493 15766 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15767 p->pc_count += 1;
15768 p->count += 1;
e8b09b87
CL		 15769 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15770 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15771 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15772 that will become rofixup. */
15773 /* This is due to the fact that we suppose all will become rofixup. */
15774 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15775 _bfd_error_handler
15776 (_("FDPIC does not yet support %s relocation"
15777 " to become dynamic for executable"),
15778 elf32_arm_howto_table_1[r_type].name);
15779 abort();
15780 }
f6e32f6d 15781 }
252b5132 15782 }
f21f3fe0 15783
b34976b6 15784 return TRUE;
252b5132
RH		 15785}
15786
9eaff861
AO		 15787static void
15788elf32_arm_update_relocs (asection *o,
15789 struct bfd_elf_section_reloc_data *reldata)
15790{
15791 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15792 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15793 const struct elf_backend_data *bed;
15794 _arm_elf_section_data *eado;
15795 struct bfd_link_order *p;
15796 bfd_byte *erela_head, *erela;
15797 Elf_Internal_Rela *irela_head, *irela;
15798 Elf_Internal_Shdr *rel_hdr;
15799 bfd *abfd;
15800 unsigned int count;
15801
15802 eado = get_arm_elf_section_data (o);
15803
15804 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15805 return;
15806
15807 abfd = o->owner;
15808 bed = get_elf_backend_data (abfd);
15809 rel_hdr = reldata->hdr;
15810
15811 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15812 {
15813 swap_in = bed->s->swap_reloc_in;
15814 swap_out = bed->s->swap_reloc_out;
15815 }
15816 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15817 {
15818 swap_in = bed->s->swap_reloca_in;
15819 swap_out = bed->s->swap_reloca_out;
15820 }
15821 else
15822 abort ();
15823
15824 erela_head = rel_hdr->contents;
15825 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15826 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15827
15828 erela = erela_head;
15829 irela = irela_head;
15830 count = 0;
15831
15832 for (p = o->map_head.link_order; p; p = p->next)
15833 {
15834 if (p->type == bfd_section_reloc_link_order
15835 || p->type == bfd_symbol_reloc_link_order)
15836 {
15837 (*swap_in) (abfd, erela, irela);
15838 erela += rel_hdr->sh_entsize;
15839 irela++;
15840 count++;
15841 }
15842 else if (p->type == bfd_indirect_link_order)
15843 {
15844 struct bfd_elf_section_reloc_data *input_reldata;
15845 arm_unwind_table_edit *edit_list, *edit_tail;
15846 _arm_elf_section_data *eadi;
15847 bfd_size_type j;
15848 bfd_vma offset;
15849 asection *i;
15850
15851 i = p->u.indirect.section;
15852
15853 eadi = get_arm_elf_section_data (i);
15854 edit_list = eadi->u.exidx.unwind_edit_list;
15855 edit_tail = eadi->u.exidx.unwind_edit_tail;
15856 offset = o->vma + i->output_offset;
15857
15858 if (eadi->elf.rel.hdr &&
15859 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15860 input_reldata = &eadi->elf.rel;
15861 else if (eadi->elf.rela.hdr &&
15862 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15863 input_reldata = &eadi->elf.rela;
15864 else
15865 abort ();
15866
15867 if (edit_list)
15868 {
15869 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15870 {
15871 arm_unwind_table_edit *edit_node, *edit_next;
15872 bfd_vma bias;
c48182bf 15873 bfd_vma reloc_index;
9eaff861
AO		 15874
15875 (*swap_in) (abfd, erela, irela);
c48182bf 15876 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15877
15878 bias = 0;
15879 edit_node = edit_list;
15880 for (edit_next = edit_list;
c48182bf 15881 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15882 edit_next = edit_node->next)
15883 {
15884 bias++;
15885 edit_node = edit_next;
15886 }
15887
15888 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15889 || edit_node->index != reloc_index)
9eaff861
AO		 15890 {
15891 irela->r_offset -= bias * 8;
15892 irela++;
15893 count++;
15894 }
15895
15896 erela += rel_hdr->sh_entsize;
15897 }
15898
15899 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15900 {
15901 /* New relocation entity. */
15902 asection *text_sec = edit_tail->linked_section;
15903 asection *text_out = text_sec->output_section;
15904 bfd_vma exidx_offset = offset + i->size - 8;
15905
15906 irela->r_addend = 0;
15907 irela->r_offset = exidx_offset;
15908 irela->r_info = ELF32_R_INFO
15909 (text_out->target_index, R_ARM_PREL31);
15910 irela++;
15911 count++;
15912 }
15913 }
15914 else
15915 {
15916 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15917 {
15918 (*swap_in) (abfd, erela, irela);
15919 erela += rel_hdr->sh_entsize;
15920 irela++;
15921 }
15922
15923 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15924 }
15925 }
15926 }
15927
15928 reldata->count = count;
15929 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15930
15931 erela = erela_head;
15932 irela = irela_head;
15933 while (count > 0)
15934 {
15935 (*swap_out) (abfd, irela, erela);
15936 erela += rel_hdr->sh_entsize;
15937 irela++;
15938 count--;
15939 }
15940
15941 free (irela_head);
15942
15943 /* Hashes are no longer valid. */
15944 free (reldata->hashes);
15945 reldata->hashes = NULL;
15946}
15947
6a5bb875 15948/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15949 required if the corresponding code section is marked. Similarly, ARMv8-M
15950 secure entry functions can only be referenced by SG veneers which are
15951 created after the GC process. They need to be marked in case they reside in
15952 their own section (as would be the case if code was compiled with
15953 -ffunction-sections). */
6a5bb875
PB		 15954
15955static bfd_boolean
906e58ca
NC		 15956elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15957 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15958{
15959 bfd *sub;
15960 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15961 asection *cmse_sec;
15962 obj_attribute *out_attr;
15963 Elf_Internal_Shdr *symtab_hdr;
15964 unsigned i, sym_count, ext_start;
15965 const struct elf_backend_data *bed;
15966 struct elf_link_hash_entry **sym_hashes;
15967 struct elf32_arm_link_hash_entry *cmse_hash;
15968 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15969
7f6ab9f8
AM		 15970 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15971
4ba2ef8f
TP		 15972 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15973 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15974 && out_attr[Tag_CPU_arch_profile].i == 'M';
15975
6a5bb875
PB		 15976 /* Marking EH data may cause additional code sections to be marked,
15977 requiring multiple passes. */
15978 again = TRUE;
15979 while (again)
15980 {
15981 again = FALSE;
c72f2fb2 15982 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15983 {
15984 asection *o;
15985
0ffa91dd 15986 if (! is_arm_elf (sub))
6a5bb875
PB		 15987 continue;
15988
15989 elf_shdrp = elf_elfsections (sub);
15990 for (o = sub->sections; o != NULL; o = o->next)
15991 {
15992 Elf_Internal_Shdr *hdr;
0ffa91dd 15993
6a5bb875 15994 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15995 if (hdr->sh_type == SHT_ARM_EXIDX
15996 && hdr->sh_link
15997 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15998 && !o->gc_mark
15999 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
16000 {
16001 again = TRUE;
16002 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
16003 return FALSE;
16004 }
16005 }
4ba2ef8f
TP		 16006
16007 /* Mark section holding ARMv8-M secure entry functions. We mark all
16008 of them so no need for a second browsing. */
16009 if (is_v8m && first_bfd_browse)
16010 {
16011 sym_hashes = elf_sym_hashes (sub);
16012 bed = get_elf_backend_data (sub);
16013 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
16014 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
16015 ext_start = symtab_hdr->sh_info;
16016
16017 /* Scan symbols. */
16018 for (i = ext_start; i < sym_count; i++)
16019 {
16020 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
16021
16022 /* Assume it is a special symbol. If not, cmse_scan will
16023 warn about it and user can do something about it. */
16024 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
16025 {
16026 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 16027 if (!cmse_sec->gc_mark
16028 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 16029 return FALSE;
16030 }
16031 }
16032 }
6a5bb875 16033 }
4ba2ef8f 16034 first_bfd_browse = FALSE;
6a5bb875
PB		 16035 }
16036
16037 return TRUE;
16038}
16039
3c9458e9
NC		 16040/* Treat mapping symbols as special target symbols. */
16041
16042static bfd_boolean
16043elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
16044{
b0796911
PB		 16045 return bfd_is_arm_special_symbol_name (sym->name,
16046 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 16047}
16048
0367ecfb
NC		 16049/* This is a copy of elf_find_function() from elf.c except that
16050 ARM mapping symbols are ignored when looking for function names
16051 and STT_ARM_TFUNC is considered to a function type. */
252b5132 16052
0367ecfb 16053static bfd_boolean
07d6d2b8 16054arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 16055 asymbol ** symbols,
fb167eb2 16056 asection * section,
07d6d2b8 16057 bfd_vma offset,
0367ecfb
NC		 16058 const char ** filename_ptr,
16059 const char ** functionname_ptr)
16060{
16061 const char * filename = NULL;
16062 asymbol * func = NULL;
16063 bfd_vma low_func = 0;
16064 asymbol ** p;
252b5132
RH		 16065
16066 for (p = symbols; *p != NULL; p++)
16067 {
16068 elf_symbol_type *q;
16069
16070 q = (elf_symbol_type *) *p;
16071
252b5132
RH		 16072 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
16073 {
16074 default:
16075 break;
16076 case STT_FILE:
16077 filename = bfd_asymbol_name (&q->symbol);
16078 break;
252b5132
RH		 16079 case STT_FUNC:
16080 case STT_ARM_TFUNC:
9d2da7ca 16081 case STT_NOTYPE:
b0796911 16082 /* Skip mapping symbols. */
0367ecfb 16083 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 16084 && bfd_is_arm_special_symbol_name (q->symbol.name,
16085 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 16086 continue;
16087 /* Fall through. */
6b40fcba 16088 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 16089 && q->symbol.value >= low_func
16090 && q->symbol.value <= offset)
16091 {
16092 func = (asymbol *) q;
16093 low_func = q->symbol.value;
16094 }
16095 break;
16096 }
16097 }
16098
16099 if (func == NULL)
b34976b6 16100 return FALSE;
252b5132 16101
0367ecfb
NC		 16102 if (filename_ptr)
16103 *filename_ptr = filename;
16104 if (functionname_ptr)
16105 *functionname_ptr = bfd_asymbol_name (func);
16106
16107 return TRUE;
906e58ca 16108}
0367ecfb
NC		 16109
16110
16111/* Find the nearest line to a particular section and offset, for error
16112 reporting. This code is a duplicate of the code in elf.c, except
16113 that it uses arm_elf_find_function. */
16114
16115static bfd_boolean
07d6d2b8
AM		 16116elf32_arm_find_nearest_line (bfd * abfd,
16117 asymbol ** symbols,
16118 asection * section,
16119 bfd_vma offset,
0367ecfb
NC		 16120 const char ** filename_ptr,
16121 const char ** functionname_ptr,
fb167eb2
AM		 16122 unsigned int * line_ptr,
16123 unsigned int * discriminator_ptr)
0367ecfb
NC		 16124{
16125 bfd_boolean found = FALSE;
16126
fb167eb2 16127 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 16128 filename_ptr, functionname_ptr,
fb167eb2
AM		 16129 line_ptr, discriminator_ptr,
16130 dwarf_debug_sections, 0,
0367ecfb
NC		 16131 & elf_tdata (abfd)->dwarf2_find_line_info))
16132 {
16133 if (!*functionname_ptr)
fb167eb2 16134 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16135 *filename_ptr ? NULL : filename_ptr,
16136 functionname_ptr);
f21f3fe0 16137
0367ecfb
NC		 16138 return TRUE;
16139 }
16140
fb167eb2
AM		 16141 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
16142 uses DWARF1. */
16143
0367ecfb
NC		 16144 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
16145 & found, filename_ptr,
16146 functionname_ptr, line_ptr,
16147 & elf_tdata (abfd)->line_info))
16148 return FALSE;
16149
16150 if (found && (*functionname_ptr || *line_ptr))
16151 return TRUE;
16152
16153 if (symbols == NULL)
16154 return FALSE;
16155
fb167eb2 16156 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16157 filename_ptr, functionname_ptr))
16158 return FALSE;
16159
16160 *line_ptr = 0;
b34976b6 16161 return TRUE;
252b5132
RH		 16162}
16163
4ab527b0 16164static bfd_boolean
07d6d2b8 16165elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16166 const char ** filename_ptr,
16167 const char ** functionname_ptr,
16168 unsigned int * line_ptr)
16169{
16170 bfd_boolean found;
16171 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16172 functionname_ptr, line_ptr,
16173 & elf_tdata (abfd)->dwarf2_find_line_info);
16174 return found;
16175}
16176
63c1f59d
AM		 16177/* Find dynamic relocs for H that apply to read-only sections. */
16178
16179static asection *
16180readonly_dynrelocs (struct elf_link_hash_entry *h)
16181{
16182 struct elf_dyn_relocs *p;
16183
16184 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
16185 {
16186 asection *s = p->sec->output_section;
16187
16188 if (s != NULL && (s->flags & SEC_READONLY) != 0)
16189 return p->sec;
16190 }
16191 return NULL;
16192}
16193
252b5132
RH		 16194/* Adjust a symbol defined by a dynamic object and referenced by a
16195 regular object. The current definition is in some section of the
16196 dynamic object, but we're not including those sections. We have to
16197 change the definition to something the rest of the link can
16198 understand. */
16199
b34976b6 16200static bfd_boolean
57e8b36a
NC		 16201elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16202 struct elf_link_hash_entry * h)
252b5132
RH		 16203{
16204 bfd * dynobj;
5474d94f 16205 asection *s, *srel;
b7693d02 16206 struct elf32_arm_link_hash_entry * eh;
67687978 16207 struct elf32_arm_link_hash_table *globals;
252b5132 16208
67687978 16209 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16210 if (globals == NULL)
16211 return FALSE;
16212
252b5132
RH		 16213 dynobj = elf_hash_table (info)->dynobj;
16214
16215 /* Make sure we know what is going on here. */
16216 BFD_ASSERT (dynobj != NULL
f5385ebf 16217 && (h->needs_plt
34e77a92 16218 || h->type == STT_GNU_IFUNC
60d67dc8 16219 || h->is_weakalias
f5385ebf
AM		 16220 || (h->def_dynamic
16221 && h->ref_regular
16222 && !h->def_regular)));
252b5132 16223
b7693d02
DJ		 16224 eh = (struct elf32_arm_link_hash_entry *) h;
16225
252b5132
RH		 16226 /* If this is a function, put it in the procedure linkage table. We
16227 will fill in the contents of the procedure linkage table later,
16228 when we know the address of the .got section. */
34e77a92 16229 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16230 {
34e77a92
RS		 16231 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16232 symbol binds locally. */
5e681ec4 16233 if (h->plt.refcount <= 0
34e77a92
RS		 16234 || (h->type != STT_GNU_IFUNC
16235 && (SYMBOL_CALLS_LOCAL (info, h)
16236 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16237 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16238 {
16239 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16240 file, but the symbol was never referred to by a dynamic
16241 object, or if all references were garbage collected. In
16242 such a case, we don't actually need to build a procedure
16243 linkage table, and we can just do a PC24 reloc instead. */
16244 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16245 eh->plt.thumb_refcount = 0;
16246 eh->plt.maybe_thumb_refcount = 0;
16247 eh->plt.noncall_refcount = 0;
f5385ebf 16248 h->needs_plt = 0;
252b5132
RH		 16249 }
16250
b34976b6 16251 return TRUE;
252b5132 16252 }
5e681ec4 16253 else
b7693d02
DJ		 16254 {
16255 /* It's possible that we incorrectly decided a .plt reloc was
16256 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16257 in check_relocs. We can't decide accurately between function
16258 and non-function syms in check-relocs; Objects loaded later in
16259 the link may change h->type. So fix it now. */
16260 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16261 eh->plt.thumb_refcount = 0;
16262 eh->plt.maybe_thumb_refcount = 0;
16263 eh->plt.noncall_refcount = 0;
b7693d02 16264 }
252b5132
RH		 16265
16266 /* If this is a weak symbol, and there is a real definition, the
16267 processor independent code will have arranged for us to see the
16268 real definition first, and we can just use the same value. */
60d67dc8 16269 if (h->is_weakalias)
252b5132 16270 {
60d67dc8
AM		 16271 struct elf_link_hash_entry *def = weakdef (h);
16272 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16273 h->root.u.def.section = def->root.u.def.section;
16274 h->root.u.def.value = def->root.u.def.value;
b34976b6 16275 return TRUE;
252b5132
RH		 16276 }
16277
ba93b8ac
DJ		 16278 /* If there are no non-GOT references, we do not need a copy
16279 relocation. */
16280 if (!h->non_got_ref)
16281 return TRUE;
16282
252b5132
RH		 16283 /* This is a reference to a symbol defined by a dynamic object which
16284 is not a function. */
16285
16286 /* If we are creating a shared library, we must presume that the
16287 only references to the symbol are via the global offset table.
16288 For such cases we need not do anything here; the relocations will
67687978
PB		 16289 be handled correctly by relocate_section. Relocatable executables
16290 can reference data in shared objects directly, so we don't need to
16291 do anything here. */
0e1862bb 16292 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16293 return TRUE;
252b5132
RH		 16294
16295 /* We must allocate the symbol in our .dynbss section, which will
16296 become part of the .bss section of the executable. There will be
16297 an entry for this symbol in the .dynsym section. The dynamic
16298 object will contain position independent code, so all references
16299 from the dynamic object to this symbol will go through the global
16300 offset table. The dynamic linker will use the .dynsym entry to
16301 determine the address it must put in the global offset table, so
16302 both the dynamic object and the regular object will refer to the
16303 same memory location for the variable. */
5522f910
NC		 16304 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16305 linker to copy the initial value out of the dynamic object and into
16306 the runtime process image. We need to remember the offset into the
00a97672 16307 .rel(a).bss section we are going to use. */
5474d94f
AM		 16308 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16309 {
16310 s = globals->root.sdynrelro;
16311 srel = globals->root.sreldynrelro;
16312 }
16313 else
16314 {
16315 s = globals->root.sdynbss;
16316 srel = globals->root.srelbss;
16317 }
5522f910
NC		 16318 if (info->nocopyreloc == 0
16319 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16320 && h->size != 0)
252b5132 16321 {
47beaa6a 16322 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16323 h->needs_copy = 1;
252b5132
RH		 16324 }
16325
6cabe1ea 16326 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16327}
16328
5e681ec4
PB		 16329/* Allocate space in .plt, .got and associated reloc sections for
16330 dynamic relocs. */
16331
16332static bfd_boolean
47beaa6a 16333allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16334{
16335 struct bfd_link_info *info;
16336 struct elf32_arm_link_hash_table *htab;
16337 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16338 struct elf_dyn_relocs *p;
5e681ec4
PB		 16339
16340 if (h->root.type == bfd_link_hash_indirect)
16341 return TRUE;
16342
e6a6bb22
AM		 16343 eh = (struct elf32_arm_link_hash_entry *) h;
16344
5e681ec4
PB		 16345 info = (struct bfd_link_info *) inf;
16346 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16347 if (htab == NULL)
16348 return FALSE;
5e681ec4 16349
34e77a92 16350 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16351 && h->plt.refcount > 0)
16352 {
16353 /* Make sure this symbol is output as a dynamic symbol.
16354 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16355 if (h->dynindx == -1 && !h->forced_local
16356 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16357 {
c152c796 16358 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16359 return FALSE;
16360 }
16361
34e77a92
RS		 16362 /* If the call in the PLT entry binds locally, the associated
16363 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16364 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16365 than the .plt section. */
16366 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16367 {
16368 eh->is_iplt = 1;
16369 if (eh->plt.noncall_refcount == 0
16370 && SYMBOL_REFERENCES_LOCAL (info, h))
16371 /* All non-call references can be resolved directly.
16372 This means that they can (and in some cases, must)
16373 resolve directly to the run-time target, rather than
16374 to the PLT. That in turns means that any .got entry
16375 would be equal to the .igot.plt entry, so there's
16376 no point having both. */
16377 h->got.refcount = 0;
16378 }
16379
0e1862bb 16380 if (bfd_link_pic (info)
34e77a92 16381 || eh->is_iplt
7359ea65 16382 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16383 {
34e77a92 16384 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16385
5e681ec4
PB		 16386 /* If this symbol is not defined in a regular file, and we are
16387 not generating a shared library, then set the symbol to this
16388 location in the .plt. This is required to make function
16389 pointers compare as equal between the normal executable and
16390 the shared library. */
0e1862bb 16391 if (! bfd_link_pic (info)
f5385ebf 16392 && !h->def_regular)
5e681ec4 16393 {
34e77a92 16394 h->root.u.def.section = htab->root.splt;
5e681ec4 16395 h->root.u.def.value = h->plt.offset;
5e681ec4 16396
67d74e43
DJ		 16397 /* Make sure the function is not marked as Thumb, in case
16398 it is the target of an ABS32 relocation, which will
16399 point to the PLT entry. */
39d911fc 16400 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16401 }
022f8312 16402
00a97672
RS		 16403 /* VxWorks executables have a second set of relocations for
16404 each PLT entry. They go in a separate relocation section,
16405 which is processed by the kernel loader. */
0e1862bb 16406 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16407 {
16408 /* There is a relocation for the initial PLT entry:
16409 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16410 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16411 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16412
16413 /* There are two extra relocations for each subsequent
16414 PLT entry: an R_ARM_32 relocation for the GOT entry,
16415 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16416 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16417 }
5e681ec4
PB		 16418 }
16419 else
16420 {
16421 h->plt.offset = (bfd_vma) -1;
f5385ebf 16422 h->needs_plt = 0;
5e681ec4
PB		 16423 }
16424 }
16425 else
16426 {
16427 h->plt.offset = (bfd_vma) -1;
f5385ebf 16428 h->needs_plt = 0;
5e681ec4
PB		 16429 }
16430
0855e32b
NS		 16431 eh = (struct elf32_arm_link_hash_entry *) h;
16432 eh->tlsdesc_got = (bfd_vma) -1;
16433
5e681ec4
PB		 16434 if (h->got.refcount > 0)
16435 {
16436 asection *s;
16437 bfd_boolean dyn;
ba93b8ac
DJ		 16438 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16439 int indx;
5e681ec4
PB		 16440
16441 /* Make sure this symbol is output as a dynamic symbol.
16442 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16443 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16444 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16445 {
c152c796 16446 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16447 return FALSE;
16448 }
16449
e5a52504
MM		 16450 if (!htab->symbian_p)
16451 {
362d30a1 16452 s = htab->root.sgot;
e5a52504 16453 h->got.offset = s->size;
ba93b8ac
DJ		 16454
16455 if (tls_type == GOT_UNKNOWN)
16456 abort ();
16457
16458 if (tls_type == GOT_NORMAL)
16459 /* Non-TLS symbols need one GOT slot. */
16460 s->size += 4;
16461 else
16462 {
99059e56
RM		 16463 if (tls_type & GOT_TLS_GDESC)
16464 {
0855e32b 16465 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16466 eh->tlsdesc_got
0855e32b
NS		 16467 = (htab->root.sgotplt->size
16468 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16469 htab->root.sgotplt->size += 8;
16470 h->got.offset = (bfd_vma) -2;
34e77a92 16471 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16472 reloc in the middle of .got.plt. */
99059e56
RM		 16473 htab->num_tls_desc++;
16474 }
0855e32b 16475
ba93b8ac 16476 if (tls_type & GOT_TLS_GD)
0855e32b 16477 {
5c5a4843
CL		 16478 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16479 consecutive GOT slots. If the symbol is both GD
16480 and GDESC, got.offset may have been
16481 overwritten. */
0855e32b
NS		 16482 h->got.offset = s->size;
16483 s->size += 8;
16484 }
16485
ba93b8ac 16486 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16487 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16488 slot. */
ba93b8ac
DJ		 16489 s->size += 4;
16490 }
16491
e5a52504 16492 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16493
16494 indx = 0;
0e1862bb
L		 16495 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16496 bfd_link_pic (info),
16497 h)
16498 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16499 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16500 indx = h->dynindx;
16501
16502 if (tls_type != GOT_NORMAL
0e1862bb 16503 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 16504 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16505 || h->root.type != bfd_link_hash_undefweak))
16506 {
16507 if (tls_type & GOT_TLS_IE)
47beaa6a 16508 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16509
16510 if (tls_type & GOT_TLS_GD)
47beaa6a 16511 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16512
b38cadfb 16513 if (tls_type & GOT_TLS_GDESC)
0855e32b 16514 {
47beaa6a 16515 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16516 /* GDESC needs a trampoline to jump to. */
16517 htab->tls_trampoline = -1;
16518 }
16519
16520 /* Only GD needs it. GDESC just emits one relocation per
16521 2 entries. */
b38cadfb 16522 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16523 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16524 }
e8b09b87
CL		 16525 else if (((indx != -1) || htab->fdpic_p)
16526 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16527 {
16528 if (htab->root.dynamic_sections_created)
16529 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16530 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16531 }
34e77a92
RS		 16532 else if (h->type == STT_GNU_IFUNC
16533 && eh->plt.noncall_refcount == 0)
16534 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16535 they all resolve dynamically instead. Reserve room for the
16536 GOT entry's R_ARM_IRELATIVE relocation. */
16537 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 16538 else if (bfd_link_pic (info)
16539 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16540 || h->root.type != bfd_link_hash_undefweak))
b436d854 16541 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16542 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16543 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16544 /* Reserve room for rofixup for FDPIC executable. */
16545 /* TLS relocs do not need space since they are completely
16546 resolved. */
16547 htab->srofixup->size += 4;
e5a52504 16548 }
5e681ec4
PB		 16549 }
16550 else
16551 h->got.offset = (bfd_vma) -1;
16552
e8b09b87
CL		 16553 /* FDPIC support. */
16554 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16555 {
16556 /* Symbol musn't be exported. */
16557 if (h->dynindx != -1)
16558 abort();
16559
16560 /* We only allocate one function descriptor with its associated relocation. */
16561 if (eh->fdpic_cnts.funcdesc_offset == -1)
16562 {
16563 asection *s = htab->root.sgot;
16564
16565 eh->fdpic_cnts.funcdesc_offset = s->size;
16566 s->size += 8;
16567 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16568 if (bfd_link_pic(info))
16569 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16570 else
16571 htab->srofixup->size += 8;
16572 }
16573 }
16574
16575 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16576 {
16577 asection *s = htab->root.sgot;
16578
16579 if (htab->root.dynamic_sections_created && h->dynindx == -1
16580 && !h->forced_local)
16581 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16582 return FALSE;
16583
16584 if (h->dynindx == -1)
16585 {
16586 /* We only allocate one function descriptor with its associated relocation. q */
16587 if (eh->fdpic_cnts.funcdesc_offset == -1)
16588 {
16589
16590 eh->fdpic_cnts.funcdesc_offset = s->size;
16591 s->size += 8;
16592 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16593 if (bfd_link_pic(info))
16594 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16595 else
16596 htab->srofixup->size += 8;
16597 }
16598 }
16599
16600 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16601 R_ARM_RELATIVE/rofixup relocation on it. */
16602 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16603 s->size += 4;
16604 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16605 htab->srofixup->size += 4;
e8b09b87 16606 else
4b24dd1a 16607 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16608 }
16609
16610 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16611 {
16612 if (htab->root.dynamic_sections_created && h->dynindx == -1
16613 && !h->forced_local)
16614 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16615 return FALSE;
16616
16617 if (h->dynindx == -1)
16618 {
16619 /* We only allocate one function descriptor with its associated relocation. */
16620 if (eh->fdpic_cnts.funcdesc_offset == -1)
16621 {
16622 asection *s = htab->root.sgot;
16623
16624 eh->fdpic_cnts.funcdesc_offset = s->size;
16625 s->size += 8;
16626 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16627 if (bfd_link_pic(info))
16628 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16629 else
16630 htab->srofixup->size += 8;
16631 }
16632 }
16633 if (h->dynindx == -1 && !bfd_link_pic(info))
16634 {
16635 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16636 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16637 }
16638 else
16639 {
16640 /* Will need one dynamic reloc per reference. will be either
16641 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16642 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16643 eh->fdpic_cnts.funcdesc_cnt);
16644 }
16645 }
16646
a4fd1a8e
PB		 16647 /* Allocate stubs for exported Thumb functions on v4t. */
16648 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16649 && h->def_regular
39d911fc 16650 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16651 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16652 {
16653 struct elf_link_hash_entry * th;
16654 struct bfd_link_hash_entry * bh;
16655 struct elf_link_hash_entry * myh;
16656 char name[1024];
16657 asection *s;
16658 bh = NULL;
16659 /* Create a new symbol to regist the real location of the function. */
16660 s = h->root.u.def.section;
906e58ca 16661 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16662 _bfd_generic_link_add_one_symbol (info, s->owner,
16663 name, BSF_GLOBAL, s,
16664 h->root.u.def.value,
16665 NULL, TRUE, FALSE, &bh);
16666
16667 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16668 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16669 myh->forced_local = 1;
39d911fc 16670 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16671 eh->export_glue = myh;
16672 th = record_arm_to_thumb_glue (info, h);
16673 /* Point the symbol at the stub. */
16674 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16675 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16676 h->root.u.def.section = th->root.u.def.section;
16677 h->root.u.def.value = th->root.u.def.value & ~1;
16678 }
16679
0bdcacaf 16680 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16681 return TRUE;
16682
16683 /* In the shared -Bsymbolic case, discard space allocated for
16684 dynamic pc-relative relocs against symbols which turn out to be
16685 defined in regular objects. For the normal shared case, discard
16686 space for pc-relative relocs that have become local due to symbol
16687 visibility changes. */
16688
e8b09b87 16689 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16690 {
469a3493
RM		 16691 /* Relocs that use pc_count are PC-relative forms, which will appear
16692 on something like ".long foo - ." or "movw REG, foo - .". We want
16693 calls to protected symbols to resolve directly to the function
16694 rather than going via the plt. If people want function pointer
16695 comparisons to work as expected then they should avoid writing
16696 assembly like ".long foo - .". */
ba93b8ac
DJ		 16697 if (SYMBOL_CALLS_LOCAL (info, h))
16698 {
0bdcacaf 16699 struct elf_dyn_relocs **pp;
ba93b8ac 16700
0bdcacaf 16701 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16702 {
16703 p->count -= p->pc_count;
16704 p->pc_count = 0;
16705 if (p->count == 0)
16706 *pp = p->next;
16707 else
16708 pp = &p->next;
16709 }
16710 }
16711
4dfe6ac6 16712 if (htab->vxworks_p)
3348747a 16713 {
0bdcacaf 16714 struct elf_dyn_relocs **pp;
3348747a 16715
0bdcacaf 16716 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16717 {
0bdcacaf 16718 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16719 *pp = p->next;
16720 else
16721 pp = &p->next;
16722 }
16723 }
16724
ba93b8ac 16725 /* Also discard relocs on undefined weak syms with non-default
99059e56 16726 visibility. */
0bdcacaf 16727 if (eh->dyn_relocs != NULL
5e681ec4 16728 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16729 {
95b03e4a
L		 16730 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16731 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16732 eh->dyn_relocs = NULL;
22d606e9
AM		 16733
16734 /* Make sure undefined weak symbols are output as a dynamic
16735 symbol in PIEs. */
e8b09b87 16736 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16737 && !h->forced_local)
16738 {
16739 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16740 return FALSE;
16741 }
16742 }
16743
67687978
PB		 16744 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16745 && h->root.type == bfd_link_hash_new)
16746 {
16747 /* Output absolute symbols so that we can create relocations
16748 against them. For normal symbols we output a relocation
16749 against the section that contains them. */
16750 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16751 return FALSE;
16752 }
16753
5e681ec4
PB		 16754 }
16755 else
16756 {
16757 /* For the non-shared case, discard space for relocs against
16758 symbols which turn out to need copy relocs or are not
16759 dynamic. */
16760
f5385ebf
AM		 16761 if (!h->non_got_ref
16762 && ((h->def_dynamic
16763 && !h->def_regular)
5e681ec4
PB		 16764 || (htab->root.dynamic_sections_created
16765 && (h->root.type == bfd_link_hash_undefweak
16766 || h->root.type == bfd_link_hash_undefined))))
16767 {
16768 /* Make sure this symbol is output as a dynamic symbol.
16769 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16770 if (h->dynindx == -1 && !h->forced_local
16771 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16772 {
c152c796 16773 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16774 return FALSE;
16775 }
16776
16777 /* If that succeeded, we know we'll be keeping all the
16778 relocs. */
16779 if (h->dynindx != -1)
16780 goto keep;
16781 }
16782
0bdcacaf 16783 eh->dyn_relocs = NULL;
5e681ec4
PB		 16784
16785 keep: ;
16786 }
16787
16788 /* Finally, allocate space. */
0bdcacaf 16789 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16790 {
0bdcacaf 16791 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16792
34e77a92
RS		 16793 if (h->type == STT_GNU_IFUNC
16794 && eh->plt.noncall_refcount == 0
16795 && SYMBOL_REFERENCES_LOCAL (info, h))
16796 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16797 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16798 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16799 else if (htab->fdpic_p && !bfd_link_pic(info))
16800 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16801 else
16802 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16803 }
16804
16805 return TRUE;
16806}
16807
63c1f59d
AM		 16808/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16809 read-only sections. */
08d1f311
DJ		 16810
16811static bfd_boolean
63c1f59d 16812maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16813{
63c1f59d 16814 asection *sec;
08d1f311 16815
63c1f59d
AM		 16816 if (h->root.type == bfd_link_hash_indirect)
16817 return TRUE;
08d1f311 16818
63c1f59d
AM		 16819 sec = readonly_dynrelocs (h);
16820 if (sec != NULL)
16821 {
16822 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16823
63c1f59d
AM		 16824 info->flags |= DF_TEXTREL;
16825 info->callbacks->minfo
c1c8c1ef 16826 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16827 sec->owner, h->root.root.string, sec);
08d1f311 16828
63c1f59d
AM		 16829 /* Not an error, just cut short the traversal. */
16830 return FALSE;
08d1f311 16831 }
cb10292c 16832
08d1f311
DJ		 16833 return TRUE;
16834}
16835
d504ffc8
DJ		 16836void
16837bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16838 int byteswap_code)
16839{
16840 struct elf32_arm_link_hash_table *globals;
16841
16842 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16843 if (globals == NULL)
16844 return;
16845
d504ffc8
DJ		 16846 globals->byteswap_code = byteswap_code;
16847}
16848
252b5132
RH		 16849/* Set the sizes of the dynamic sections. */
16850
b34976b6 16851static bfd_boolean
57e8b36a
NC		 16852elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16853 struct bfd_link_info * info)
252b5132
RH		 16854{
16855 bfd * dynobj;
16856 asection * s;
b34976b6
AM		 16857 bfd_boolean plt;
16858 bfd_boolean relocs;
5e681ec4
PB		 16859 bfd *ibfd;
16860 struct elf32_arm_link_hash_table *htab;
252b5132 16861
5e681ec4 16862 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16863 if (htab == NULL)
16864 return FALSE;
16865
252b5132
RH		 16866 dynobj = elf_hash_table (info)->dynobj;
16867 BFD_ASSERT (dynobj != NULL);
39b41c9c 16868 check_use_blx (htab);
252b5132
RH		 16869
16870 if (elf_hash_table (info)->dynamic_sections_created)
16871 {
16872 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16873 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16874 {
3d4d4302 16875 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16876 BFD_ASSERT (s != NULL);
eea6121a 16877 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16878 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16879 }
16880 }
5e681ec4
PB		 16881
16882 /* Set up .got offsets for local syms, and space for local dynamic
16883 relocs. */
c72f2fb2 16884 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16885 {
5e681ec4
PB		 16886 bfd_signed_vma *local_got;
16887 bfd_signed_vma *end_local_got;
34e77a92 16888 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16889 char *local_tls_type;
0855e32b 16890 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16891 bfd_size_type locsymcount;
16892 Elf_Internal_Shdr *symtab_hdr;
16893 asection *srel;
4dfe6ac6 16894 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16895 unsigned int symndx;
e8b09b87 16896 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16897
0ffa91dd 16898 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16899 continue;
16900
16901 for (s = ibfd->sections; s != NULL; s = s->next)
16902 {
0bdcacaf 16903 struct elf_dyn_relocs *p;
5e681ec4 16904
0bdcacaf 16905 for (p = (struct elf_dyn_relocs *)
99059e56 16906 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16907 {
0bdcacaf
RS		 16908 if (!bfd_is_abs_section (p->sec)
16909 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16910 {
16911 /* Input section has been discarded, either because
16912 it is a copy of a linkonce section or due to
16913 linker script /DISCARD/, so we'll be discarding
16914 the relocs too. */
16915 }
3348747a 16916 else if (is_vxworks
0bdcacaf 16917 && strcmp (p->sec->output_section->name,
3348747a
NS		 16918 ".tls_vars") == 0)
16919 {
16920 /* Relocations in vxworks .tls_vars sections are
16921 handled specially by the loader. */
16922 }
5e681ec4
PB		 16923 else if (p->count != 0)
16924 {
0bdcacaf 16925 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16926 if (htab->fdpic_p && !bfd_link_pic(info))
16927 htab->srofixup->size += 4 * p->count;
16928 else
16929 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16930 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16931 info->flags |= DF_TEXTREL;
16932 }
16933 }
16934 }
16935
16936 local_got = elf_local_got_refcounts (ibfd);
16937 if (!local_got)
16938 continue;
16939
0ffa91dd 16940 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16941 locsymcount = symtab_hdr->sh_info;
16942 end_local_got = local_got + locsymcount;
34e77a92 16943 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16944 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16945 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16946 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16947 symndx = 0;
362d30a1
RS		 16948 s = htab->root.sgot;
16949 srel = htab->root.srelgot;
0855e32b 16950 for (; local_got < end_local_got;
34e77a92 16951 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16952 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16953 {
0855e32b 16954 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16955 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16956
16957 /* FDPIC support. */
16958 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16959 {
16960 if (local_fdpic_cnts->funcdesc_offset == -1)
16961 {
16962 local_fdpic_cnts->funcdesc_offset = s->size;
16963 s->size += 8;
16964
16965 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16966 if (bfd_link_pic(info))
16967 elf32_arm_allocate_dynrelocs (info, srel, 1);
16968 else
16969 htab->srofixup->size += 8;
16970 }
16971 }
16972
16973 if (local_fdpic_cnts->funcdesc_cnt > 0)
16974 {
16975 if (local_fdpic_cnts->funcdesc_offset == -1)
16976 {
16977 local_fdpic_cnts->funcdesc_offset = s->size;
16978 s->size += 8;
16979
16980 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16981 if (bfd_link_pic(info))
16982 elf32_arm_allocate_dynrelocs (info, srel, 1);
16983 else
16984 htab->srofixup->size += 8;
16985 }
16986
16987 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16988 if (bfd_link_pic(info))
16989 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16990 else
16991 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16992 }
16993
34e77a92
RS		 16994 if (local_iplt != NULL)
16995 {
16996 struct elf_dyn_relocs *p;
16997
16998 if (local_iplt->root.refcount > 0)
16999 {
17000 elf32_arm_allocate_plt_entry (info, TRUE,
17001 &local_iplt->root,
17002 &local_iplt->arm);
17003 if (local_iplt->arm.noncall_refcount == 0)
17004 /* All references to the PLT are calls, so all
17005 non-call references can resolve directly to the
17006 run-time target. This means that the .got entry
17007 would be the same as the .igot.plt entry, so there's
17008 no point creating both. */
17009 *local_got = 0;
17010 }
17011 else
17012 {
17013 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
17014 local_iplt->root.offset = (bfd_vma) -1;
17015 }
17016
17017 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
17018 {
17019 asection *psrel;
17020
17021 psrel = elf_section_data (p->sec)->sreloc;
17022 if (local_iplt->arm.noncall_refcount == 0)
17023 elf32_arm_allocate_irelocs (info, psrel, p->count);
17024 else
17025 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
17026 }
17027 }
5e681ec4
PB		 17028 if (*local_got > 0)
17029 {
34e77a92
RS		 17030 Elf_Internal_Sym *isym;
17031
eea6121a 17032 *local_got = s->size;
ba93b8ac
DJ		 17033 if (*local_tls_type & GOT_TLS_GD)
17034 /* TLS_GD relocs need an 8-byte structure in the GOT. */
17035 s->size += 8;
0855e32b
NS		 17036 if (*local_tls_type & GOT_TLS_GDESC)
17037 {
17038 *local_tlsdesc_gotent = htab->root.sgotplt->size
17039 - elf32_arm_compute_jump_table_size (htab);
17040 htab->root.sgotplt->size += 8;
17041 *local_got = (bfd_vma) -2;
34e77a92 17042 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 17043 reloc in the middle of .got.plt. */
99059e56 17044 htab->num_tls_desc++;
0855e32b 17045 }
ba93b8ac
DJ		 17046 if (*local_tls_type & GOT_TLS_IE)
17047 s->size += 4;
ba93b8ac 17048
0855e32b
NS		 17049 if (*local_tls_type & GOT_NORMAL)
17050 {
17051 /* If the symbol is both GD and GDESC, *local_got
17052 may have been overwritten. */
17053 *local_got = s->size;
17054 s->size += 4;
17055 }
17056
34e77a92
RS		 17057 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
17058 if (isym == NULL)
17059 return FALSE;
17060
17061 /* If all references to an STT_GNU_IFUNC PLT are calls,
17062 then all non-call references, including this GOT entry,
17063 resolve directly to the run-time target. */
17064 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
17065 && (local_iplt == NULL
17066 || local_iplt->arm.noncall_refcount == 0))
17067 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 17068 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 17069 {
e8b09b87 17070 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 17071 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 17072 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
17073 htab->srofixup->size += 4;
99059e56 17074
e8b09b87
CL		 17075 if ((bfd_link_pic (info) || htab->fdpic_p)
17076 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 17077 {
17078 elf32_arm_allocate_dynrelocs (info,
17079 htab->root.srelplt, 1);
17080 htab->tls_trampoline = -1;
17081 }
0855e32b 17082 }
5e681ec4
PB		 17083 }
17084 else
17085 *local_got = (bfd_vma) -1;
17086 }
252b5132
RH		 17087 }
17088
ba93b8ac
DJ		 17089 if (htab->tls_ldm_got.refcount > 0)
17090 {
17091 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 17092 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 17093 htab->tls_ldm_got.offset = htab->root.sgot->size;
17094 htab->root.sgot->size += 8;
0e1862bb 17095 if (bfd_link_pic (info))
47beaa6a 17096 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 17097 }
17098 else
17099 htab->tls_ldm_got.offset = -1;
17100
e8b09b87
CL		 17101 /* At the very end of the .rofixup section is a pointer to the GOT,
17102 reserve space for it. */
17103 if (htab->fdpic_p && htab->srofixup != NULL)
17104 htab->srofixup->size += 4;
17105
5e681ec4
PB		 17106 /* Allocate global sym .plt and .got entries, and space for global
17107 sym dynamic relocs. */
47beaa6a 17108 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 17109
d504ffc8 17110 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 17111 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 17112 {
0ffa91dd 17113 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 17114 continue;
17115
c7b8f16e
JB		 17116 /* Initialise mapping tables for code/data. */
17117 bfd_elf32_arm_init_maps (ibfd);
906e58ca 17118
c7b8f16e 17119 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 17120 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
17121 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 17122 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 17123 }
d504ffc8 17124
3e6b1042
DJ		 17125 /* Allocate space for the glue sections now that we've sized them. */
17126 bfd_elf32_arm_allocate_interworking_sections (info);
17127
0855e32b
NS		 17128 /* For every jump slot reserved in the sgotplt, reloc_count is
17129 incremented. However, when we reserve space for TLS descriptors,
17130 it's not incremented, so in order to compute the space reserved
17131 for them, it suffices to multiply the reloc count by the jump
17132 slot size. */
17133 if (htab->root.srelplt)
17134 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
17135
17136 if (htab->tls_trampoline)
17137 {
17138 if (htab->root.splt->size == 0)
17139 htab->root.splt->size += htab->plt_header_size;
b38cadfb 17140
0855e32b
NS		 17141 htab->tls_trampoline = htab->root.splt->size;
17142 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 17143
0855e32b 17144 /* If we're not using lazy TLS relocations, don't generate the
99059e56 17145 PLT and GOT entries they require. */
0855e32b
NS		 17146 if (!(info->flags & DF_BIND_NOW))
17147 {
17148 htab->dt_tlsdesc_got = htab->root.sgot->size;
17149 htab->root.sgot->size += 4;
17150
17151 htab->dt_tlsdesc_plt = htab->root.splt->size;
17152 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
17153 }
17154 }
17155
252b5132
RH		 17156 /* The check_relocs and adjust_dynamic_symbol entry points have
17157 determined the sizes of the various dynamic sections. Allocate
17158 memory for them. */
b34976b6
AM		 17159 plt = FALSE;
17160 relocs = FALSE;
252b5132
RH		 17161 for (s = dynobj->sections; s != NULL; s = s->next)
17162 {
17163 const char * name;
252b5132
RH		 17164
17165 if ((s->flags & SEC_LINKER_CREATED) == 0)
17166 continue;
17167
17168 /* It's OK to base decisions on the section name, because none
17169 of the dynobj section names depend upon the input files. */
17170 name = bfd_get_section_name (dynobj, s);
17171
34e77a92 17172 if (s == htab->root.splt)
252b5132 17173 {
c456f082
AM		 17174 /* Remember whether there is a PLT. */
17175 plt = s->size != 0;
252b5132 17176 }
0112cd26 17177 else if (CONST_STRNEQ (name, ".rel"))
252b5132 17178 {
c456f082 17179 if (s->size != 0)
252b5132 17180 {
252b5132 17181 /* Remember whether there are any reloc sections other
00a97672 17182 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17183 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17184 relocs = TRUE;
252b5132
RH		 17185
17186 /* We use the reloc_count field as a counter if we need
17187 to copy relocs into the output file. */
17188 s->reloc_count = 0;
17189 }
17190 }
34e77a92
RS		 17191 else if (s != htab->root.sgot
17192 && s != htab->root.sgotplt
17193 && s != htab->root.iplt
17194 && s != htab->root.igotplt
5474d94f 17195 && s != htab->root.sdynbss
e8b09b87
CL		 17196 && s != htab->root.sdynrelro
17197 && s != htab->srofixup)
252b5132
RH		 17198 {
17199 /* It's not one of our sections, so don't allocate space. */
17200 continue;
17201 }
17202
c456f082 17203 if (s->size == 0)
252b5132 17204 {
c456f082 17205 /* If we don't need this section, strip it from the
00a97672
RS		 17206 output file. This is mostly to handle .rel(a).bss and
17207 .rel(a).plt. We must create both sections in
c456f082
AM		 17208 create_dynamic_sections, because they must be created
17209 before the linker maps input sections to output
17210 sections. The linker does that before
17211 adjust_dynamic_symbol is called, and it is that
17212 function which decides whether anything needs to go
17213 into these sections. */
8423293d 17214 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17215 continue;
17216 }
17217
c456f082
AM		 17218 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17219 continue;
17220
252b5132 17221 /* Allocate memory for the section contents. */
21d799b5 17222 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17223 if (s->contents == NULL)
b34976b6 17224 return FALSE;
252b5132
RH		 17225 }
17226
17227 if (elf_hash_table (info)->dynamic_sections_created)
17228 {
17229 /* Add some entries to the .dynamic section. We fill in the
17230 values later, in elf32_arm_finish_dynamic_sections, but we
17231 must add the entries now so that we get the correct size for
17232 the .dynamic section. The DT_DEBUG entry is filled in by the
17233 dynamic linker and used by the debugger. */
dc810e39 17234#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17235 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17236
0e1862bb 17237 if (bfd_link_executable (info))
252b5132 17238 {
dc810e39 17239 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17240 return FALSE;
252b5132
RH		 17241 }
17242
17243 if (plt)
17244 {
dc810e39
AM		 17245 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17246 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17247 || !add_dynamic_entry (DT_PLTREL,
17248 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17249 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17250 return FALSE;
0855e32b 17251
5025eb7c
AO		 17252 if (htab->dt_tlsdesc_plt
17253 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17254 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17255 return FALSE;
252b5132
RH		 17256 }
17257
17258 if (relocs)
17259 {
00a97672
RS		 17260 if (htab->use_rel)
17261 {
17262 if (!add_dynamic_entry (DT_REL, 0)
17263 || !add_dynamic_entry (DT_RELSZ, 0)
17264 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17265 return FALSE;
17266 }
17267 else
17268 {
17269 if (!add_dynamic_entry (DT_RELA, 0)
17270 || !add_dynamic_entry (DT_RELASZ, 0)
17271 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17272 return FALSE;
17273 }
252b5132
RH		 17274 }
17275
08d1f311
DJ		 17276 /* If any dynamic relocs apply to a read-only section,
17277 then we need a DT_TEXTREL entry. */
17278 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17279 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17280
99e4ae17 17281 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17282 {
dc810e39 17283 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17284 return FALSE;
252b5132 17285 }
7a2b07ff
NS		 17286 if (htab->vxworks_p
17287 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17288 return FALSE;
252b5132 17289 }
8532796c 17290#undef add_dynamic_entry
252b5132 17291
b34976b6 17292 return TRUE;
252b5132
RH		 17293}
17294
0855e32b
NS		 17295/* Size sections even though they're not dynamic. We use it to setup
17296 _TLS_MODULE_BASE_, if needed. */
17297
17298static bfd_boolean
17299elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17300 struct bfd_link_info *info)
0855e32b
NS		 17301{
17302 asection *tls_sec;
cb10292c
CL		 17303 struct elf32_arm_link_hash_table *htab;
17304
17305 htab = elf32_arm_hash_table (info);
0855e32b 17306
0e1862bb 17307 if (bfd_link_relocatable (info))
0855e32b
NS		 17308 return TRUE;
17309
17310 tls_sec = elf_hash_table (info)->tls_sec;
17311
17312 if (tls_sec)
17313 {
17314 struct elf_link_hash_entry *tlsbase;
17315
17316 tlsbase = elf_link_hash_lookup
17317 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17318
17319 if (tlsbase)
99059e56
RM		 17320 {
17321 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17322 const struct elf_backend_data *bed
99059e56 17323 = get_elf_backend_data (output_bfd);
0855e32b 17324
99059e56 17325 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17326 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17327 tls_sec, 0, NULL, FALSE,
17328 bed->collect, &bh)))
17329 return FALSE;
b38cadfb 17330
99059e56
RM		 17331 tlsbase->type = STT_TLS;
17332 tlsbase = (struct elf_link_hash_entry *)bh;
17333 tlsbase->def_regular = 1;
17334 tlsbase->other = STV_HIDDEN;
17335 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17336 }
17337 }
cb10292c
CL		 17338
17339 if (htab->fdpic_p && !bfd_link_relocatable (info)
17340 && !bfd_elf_stack_segment_size (output_bfd, info,
17341 "__stacksize", DEFAULT_STACK_SIZE))
17342 return FALSE;
17343
0855e32b
NS		 17344 return TRUE;
17345}
17346
252b5132
RH		 17347/* Finish up dynamic symbol handling. We set the contents of various
17348 dynamic sections here. */
17349
b34976b6 17350static bfd_boolean
906e58ca
NC		 17351elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17352 struct bfd_link_info * info,
17353 struct elf_link_hash_entry * h,
17354 Elf_Internal_Sym * sym)
252b5132 17355{
e5a52504 17356 struct elf32_arm_link_hash_table *htab;
b7693d02 17357 struct elf32_arm_link_hash_entry *eh;
252b5132 17358
e5a52504 17359 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17360 if (htab == NULL)
17361 return FALSE;
17362
b7693d02 17363 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17364
17365 if (h->plt.offset != (bfd_vma) -1)
17366 {
34e77a92 17367 if (!eh->is_iplt)
e5a52504 17368 {
34e77a92 17369 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17370 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17371 h->dynindx, 0))
17372 return FALSE;
e5a52504 17373 }
57e8b36a 17374
f5385ebf 17375 if (!h->def_regular)
252b5132
RH		 17376 {
17377 /* Mark the symbol as undefined, rather than as defined in
3a635617 17378 the .plt section. */
252b5132 17379 sym->st_shndx = SHN_UNDEF;
3a635617 17380 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17381 Otherwise, the PLT entry would provide a definition for
17382 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17383 and so the symbol would never be NULL. Leave the value if
17384 there were any relocations where pointer equality matters
17385 (this is a clue for the dynamic linker, to make function
17386 pointer comparisons work between an application and shared
17387 library). */
97323ad1 17388 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17389 sym->st_value = 0;
252b5132 17390 }
34e77a92
RS		 17391 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17392 {
17393 /* At least one non-call relocation references this .iplt entry,
17394 so the .iplt entry is the function's canonical address. */
17395 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17396 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17397 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17398 (output_bfd, htab->root.iplt->output_section));
17399 sym->st_value = (h->plt.offset
17400 + htab->root.iplt->output_section->vma
17401 + htab->root.iplt->output_offset);
17402 }
252b5132
RH		 17403 }
17404
f5385ebf 17405 if (h->needs_copy)
252b5132
RH		 17406 {
17407 asection * s;
947216bf 17408 Elf_Internal_Rela rel;
252b5132
RH		 17409
17410 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17411 BFD_ASSERT (h->dynindx != -1
17412 && (h->root.type == bfd_link_hash_defined
17413 || h->root.type == bfd_link_hash_defweak));
17414
00a97672 17415 rel.r_addend = 0;
252b5132
RH		 17416 rel.r_offset = (h->root.u.def.value
17417 + h->root.u.def.section->output_section->vma
17418 + h->root.u.def.section->output_offset);
17419 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17420 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17421 s = htab->root.sreldynrelro;
17422 else
17423 s = htab->root.srelbss;
47beaa6a 17424 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17425 }
17426
00a97672 17427 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17428 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17429 it is relative to the ".got" section. */
9637f6ef 17430 if (h == htab->root.hdynamic
fac7bd64 17431 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17432 sym->st_shndx = SHN_ABS;
17433
b34976b6 17434 return TRUE;
252b5132
RH		 17435}
17436
0855e32b
NS		 17437static void
17438arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17439 void *contents,
17440 const unsigned long *template, unsigned count)
17441{
17442 unsigned ix;
b38cadfb 17443
0855e32b
NS		 17444 for (ix = 0; ix != count; ix++)
17445 {
17446 unsigned long insn = template[ix];
17447
17448 /* Emit mov pc,rx if bx is not permitted. */
17449 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17450 insn = (insn & 0xf000000f) | 0x01a0f000;
17451 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17452 }
17453}
17454
99059e56
RM		 17455/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17456 other variants, NaCl needs this entry in a static executable's
17457 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17458 zero. For .iplt really only the last bundle is useful, and .iplt
17459 could have a shorter first entry, with each individual PLT entry's
17460 relative branch calculated differently so it targets the last
17461 bundle instead of the instruction before it (labelled .Lplt_tail
17462 above). But it's simpler to keep the size and layout of PLT0
17463 consistent with the dynamic case, at the cost of some dead code at
17464 the start of .iplt and the one dead store to the stack at the start
17465 of .Lplt_tail. */
17466static void
17467arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17468 asection *plt, bfd_vma got_displacement)
17469{
17470 unsigned int i;
17471
17472 put_arm_insn (htab, output_bfd,
17473 elf32_arm_nacl_plt0_entry[0]
17474 | arm_movw_immediate (got_displacement),
17475 plt->contents + 0);
17476 put_arm_insn (htab, output_bfd,
17477 elf32_arm_nacl_plt0_entry[1]
17478 | arm_movt_immediate (got_displacement),
17479 plt->contents + 4);
17480
17481 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17482 put_arm_insn (htab, output_bfd,
17483 elf32_arm_nacl_plt0_entry[i],
17484 plt->contents + (i * 4));
17485}
17486
252b5132
RH		 17487/* Finish up the dynamic sections. */
17488
b34976b6 17489static bfd_boolean
57e8b36a 17490elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17491{
17492 bfd * dynobj;
17493 asection * sgot;
17494 asection * sdyn;
4dfe6ac6
NC		 17495 struct elf32_arm_link_hash_table *htab;
17496
17497 htab = elf32_arm_hash_table (info);
17498 if (htab == NULL)
17499 return FALSE;
252b5132
RH		 17500
17501 dynobj = elf_hash_table (info)->dynobj;
17502
362d30a1 17503 sgot = htab->root.sgotplt;
894891db
NC		 17504 /* A broken linker script might have discarded the dynamic sections.
17505 Catch this here so that we do not seg-fault later on. */
17506 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17507 return FALSE;
3d4d4302 17508 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17509
17510 if (elf_hash_table (info)->dynamic_sections_created)
17511 {
17512 asection *splt;
17513 Elf32_External_Dyn *dyncon, *dynconend;
17514
362d30a1 17515 splt = htab->root.splt;
24a1ba0f 17516 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17517 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17518
17519 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17520 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17521
252b5132
RH		 17522 for (; dyncon < dynconend; dyncon++)
17523 {
17524 Elf_Internal_Dyn dyn;
17525 const char * name;
17526 asection * s;
17527
17528 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17529
17530 switch (dyn.d_tag)
17531 {
229fcec5
MM		 17532 unsigned int type;
17533
252b5132 17534 default:
7a2b07ff
NS		 17535 if (htab->vxworks_p
17536 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17537 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17538 break;
17539
229fcec5
MM		 17540 case DT_HASH:
17541 name = ".hash";
17542 goto get_vma_if_bpabi;
17543 case DT_STRTAB:
17544 name = ".dynstr";
17545 goto get_vma_if_bpabi;
17546 case DT_SYMTAB:
17547 name = ".dynsym";
17548 goto get_vma_if_bpabi;
c0042f5d
MM		 17549 case DT_VERSYM:
17550 name = ".gnu.version";
17551 goto get_vma_if_bpabi;
17552 case DT_VERDEF:
17553 name = ".gnu.version_d";
17554 goto get_vma_if_bpabi;
17555 case DT_VERNEED:
17556 name = ".gnu.version_r";
17557 goto get_vma_if_bpabi;
17558
252b5132 17559 case DT_PLTGOT:
4ade44b7 17560 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17561 goto get_vma;
17562 case DT_JMPREL:
00a97672 17563 name = RELOC_SECTION (htab, ".plt");
252b5132 17564 get_vma:
4ade44b7 17565 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17566 if (s == NULL)
17567 {
4eca0228 17568 _bfd_error_handler
4ade44b7 17569 (_("could not find section %s"), name);
05456594
NC		 17570 bfd_set_error (bfd_error_invalid_operation);
17571 return FALSE;
17572 }
229fcec5 17573 if (!htab->symbian_p)
4ade44b7 17574 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17575 else
17576 /* In the BPABI, tags in the PT_DYNAMIC section point
17577 at the file offset, not the memory address, for the
17578 convenience of the post linker. */
4ade44b7 17579 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17580 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17581 break;
17582
229fcec5
MM		 17583 get_vma_if_bpabi:
17584 if (htab->symbian_p)
17585 goto get_vma;
17586 break;
17587
252b5132 17588 case DT_PLTRELSZ:
362d30a1 17589 s = htab->root.srelplt;
252b5132 17590 BFD_ASSERT (s != NULL);
eea6121a 17591 dyn.d_un.d_val = s->size;
252b5132
RH		 17592 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17593 break;
906e58ca 17594
252b5132 17595 case DT_RELSZ:
00a97672 17596 case DT_RELASZ:
229fcec5
MM		 17597 case DT_REL:
17598 case DT_RELA:
229fcec5
MM		 17599 /* In the BPABI, the DT_REL tag must point at the file
17600 offset, not the VMA, of the first relocation
17601 section. So, we use code similar to that in
17602 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17603 relocation section, since relocation sections are
17604 never allocated under the BPABI. PLT relocs are also
17605 included. */
229fcec5
MM		 17606 if (htab->symbian_p)
17607 {
17608 unsigned int i;
17609 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17610 ? SHT_REL : SHT_RELA);
17611 dyn.d_un.d_val = 0;
17612 for (i = 1; i < elf_numsections (output_bfd); i++)
17613 {
906e58ca 17614 Elf_Internal_Shdr *hdr
229fcec5
MM		 17615 = elf_elfsections (output_bfd)[i];
17616 if (hdr->sh_type == type)
17617 {
906e58ca 17618 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17619 || dyn.d_tag == DT_RELASZ)
17620 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17621 else if ((ufile_ptr) hdr->sh_offset
17622 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17623 dyn.d_un.d_val = hdr->sh_offset;
17624 }
17625 }
17626 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17627 }
252b5132 17628 break;
88f7bcd5 17629
0855e32b 17630 case DT_TLSDESC_PLT:
99059e56 17631 s = htab->root.splt;
0855e32b
NS		 17632 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17633 + htab->dt_tlsdesc_plt);
17634 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17635 break;
17636
17637 case DT_TLSDESC_GOT:
99059e56 17638 s = htab->root.sgot;
0855e32b 17639 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17640 + htab->dt_tlsdesc_got);
0855e32b
NS		 17641 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17642 break;
17643
88f7bcd5
NC		 17644 /* Set the bottom bit of DT_INIT/FINI if the
17645 corresponding function is Thumb. */
17646 case DT_INIT:
17647 name = info->init_function;
17648 goto get_sym;
17649 case DT_FINI:
17650 name = info->fini_function;
17651 get_sym:
17652 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17653 then there is nothing to adjust. */
88f7bcd5
NC		 17654 if (dyn.d_un.d_val != 0)
17655 {
17656 struct elf_link_hash_entry * eh;
17657
17658 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17659 FALSE, FALSE, TRUE);
39d911fc
TP		 17660 if (eh != NULL
17661 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17662 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17663 {
17664 dyn.d_un.d_val |= 1;
b34976b6 17665 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17666 }
17667 }
17668 break;
252b5132
RH		 17669 }
17670 }
17671
24a1ba0f 17672 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17673 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17674 {
00a97672
RS		 17675 const bfd_vma *plt0_entry;
17676 bfd_vma got_address, plt_address, got_displacement;
17677
17678 /* Calculate the addresses of the GOT and PLT. */
17679 got_address = sgot->output_section->vma + sgot->output_offset;
17680 plt_address = splt->output_section->vma + splt->output_offset;
17681
17682 if (htab->vxworks_p)
17683 {
17684 /* The VxWorks GOT is relocated by the dynamic linker.
17685 Therefore, we must emit relocations rather than simply
17686 computing the values now. */
17687 Elf_Internal_Rela rel;
17688
17689 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17690 put_arm_insn (htab, output_bfd, plt0_entry[0],
17691 splt->contents + 0);
17692 put_arm_insn (htab, output_bfd, plt0_entry[1],
17693 splt->contents + 4);
17694 put_arm_insn (htab, output_bfd, plt0_entry[2],
17695 splt->contents + 8);
00a97672
RS		 17696 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17697
8029a119 17698 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17699 rel.r_offset = plt_address + 12;
17700 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17701 rel.r_addend = 0;
17702 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17703 htab->srelplt2->contents);
17704 }
b38cadfb 17705 else if (htab->nacl_p)
99059e56
RM		 17706 arm_nacl_put_plt0 (htab, output_bfd, splt,
17707 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17708 else if (using_thumb_only (htab))
17709 {
17710 got_displacement = got_address - (plt_address + 12);
17711
17712 plt0_entry = elf32_thumb2_plt0_entry;
17713 put_arm_insn (htab, output_bfd, plt0_entry[0],
17714 splt->contents + 0);
17715 put_arm_insn (htab, output_bfd, plt0_entry[1],
17716 splt->contents + 4);
17717 put_arm_insn (htab, output_bfd, plt0_entry[2],
17718 splt->contents + 8);
17719
17720 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17721 }
00a97672
RS		 17722 else
17723 {
17724 got_displacement = got_address - (plt_address + 16);
17725
17726 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17727 put_arm_insn (htab, output_bfd, plt0_entry[0],
17728 splt->contents + 0);
17729 put_arm_insn (htab, output_bfd, plt0_entry[1],
17730 splt->contents + 4);
17731 put_arm_insn (htab, output_bfd, plt0_entry[2],
17732 splt->contents + 8);
17733 put_arm_insn (htab, output_bfd, plt0_entry[3],
17734 splt->contents + 12);
5e681ec4 17735
5e681ec4 17736#ifdef FOUR_WORD_PLT
00a97672
RS		 17737 /* The displacement value goes in the otherwise-unused
17738 last word of the second entry. */
17739 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17740#else
00a97672 17741 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17742#endif
00a97672 17743 }
f7a74f8c 17744 }
252b5132
RH		 17745
17746 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17747 really seem like the right value. */
74541ad4
AM		 17748 if (splt->output_section->owner == output_bfd)
17749 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17750
0855e32b
NS		 17751 if (htab->dt_tlsdesc_plt)
17752 {
17753 bfd_vma got_address
17754 = sgot->output_section->vma + sgot->output_offset;
17755 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17756 + htab->root.sgot->output_offset);
17757 bfd_vma plt_address
17758 = splt->output_section->vma + splt->output_offset;
17759
b38cadfb 17760 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17761 splt->contents + htab->dt_tlsdesc_plt,
17762 dl_tlsdesc_lazy_trampoline, 6);
17763
17764 bfd_put_32 (output_bfd,
17765 gotplt_address + htab->dt_tlsdesc_got
17766 - (plt_address + htab->dt_tlsdesc_plt)
17767 - dl_tlsdesc_lazy_trampoline[6],
17768 splt->contents + htab->dt_tlsdesc_plt + 24);
17769 bfd_put_32 (output_bfd,
17770 got_address - (plt_address + htab->dt_tlsdesc_plt)
17771 - dl_tlsdesc_lazy_trampoline[7],
17772 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17773 }
17774
17775 if (htab->tls_trampoline)
17776 {
b38cadfb 17777 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17778 splt->contents + htab->tls_trampoline,
17779 tls_trampoline, 3);
17780#ifdef FOUR_WORD_PLT
17781 bfd_put_32 (output_bfd, 0x00000000,
17782 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17783#endif
0855e32b
NS		 17784 }
17785
0e1862bb
L		 17786 if (htab->vxworks_p
17787 && !bfd_link_pic (info)
17788 && htab->root.splt->size > 0)
00a97672
RS		 17789 {
17790 /* Correct the .rel(a).plt.unloaded relocations. They will have
17791 incorrect symbol indexes. */
17792 int num_plts;
eed62c48 17793 unsigned char *p;
00a97672 17794
362d30a1 17795 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17796 / htab->plt_entry_size);
17797 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17798
17799 for (; num_plts; num_plts--)
17800 {
17801 Elf_Internal_Rela rel;
17802
17803 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17804 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17805 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17806 p += RELOC_SIZE (htab);
17807
17808 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17809 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17810 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17811 p += RELOC_SIZE (htab);
17812 }
17813 }
252b5132
RH		 17814 }
17815
99059e56
RM		 17816 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17817 /* NaCl uses a special first entry in .iplt too. */
17818 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17819
252b5132 17820 /* Fill in the first three entries in the global offset table. */
229fcec5 17821 if (sgot)
252b5132 17822 {
229fcec5
MM		 17823 if (sgot->size > 0)
17824 {
17825 if (sdyn == NULL)
17826 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17827 else
17828 bfd_put_32 (output_bfd,
17829 sdyn->output_section->vma + sdyn->output_offset,
17830 sgot->contents);
17831 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17832 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17833 }
252b5132 17834
229fcec5
MM		 17835 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17836 }
252b5132 17837
e8b09b87
CL		 17838 /* At the very end of the .rofixup section is a pointer to the GOT. */
17839 if (htab->fdpic_p && htab->srofixup != NULL)
17840 {
17841 struct elf_link_hash_entry *hgot = htab->root.hgot;
17842
17843 bfd_vma got_value = hgot->root.u.def.value
17844 + hgot->root.u.def.section->output_section->vma
17845 + hgot->root.u.def.section->output_offset;
17846
17847 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17848
17849 /* Make sure we allocated and generated the same number of fixups. */
17850 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17851 }
17852
b34976b6 17853 return TRUE;
252b5132
RH		 17854}
17855
ba96a88f 17856static void
57e8b36a 17857elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 17858{
9b485d32 17859 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17860 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17861 struct elf_segment_map *m;
ba96a88f
NC		 17862
17863 i_ehdrp = elf_elfheader (abfd);
17864
94a3258f
PB		 17865 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17866 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
17867 else
7394f108 17868 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 17869 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17870
93204d3a
PB		 17871 if (link_info)
17872 {
17873 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17874 if (globals != NULL && globals->byteswap_code)
93204d3a 17875 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17876
17877 if (globals->fdpic_p)
17878 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17879 }
3bfcb652
NC		 17880
17881 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17882 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17883 {
17884 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17885 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17886 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17887 else
17888 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17889 }
ac4c9b04
MG		 17890
17891 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17892 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17893 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17894 {
17895 unsigned int j;
17896
17897 if (m->count == 0)
17898 continue;
17899 for (j = 0; j < m->count; j++)
17900 {
f0728ee3 17901 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17902 break;
17903 }
17904 if (j == m->count)
17905 {
17906 m->p_flags = PF_X;
17907 m->p_flags_valid = 1;
17908 }
17909 }
ba96a88f
NC		 17910}
17911
99e4ae17 17912static enum elf_reloc_type_class
7e612e98
AM		 17913elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17914 const asection *rel_sec ATTRIBUTE_UNUSED,
17915 const Elf_Internal_Rela *rela)
99e4ae17 17916{
f51e552e 17917 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17918 {
17919 case R_ARM_RELATIVE:
17920 return reloc_class_relative;
17921 case R_ARM_JUMP_SLOT:
17922 return reloc_class_plt;
17923 case R_ARM_COPY:
17924 return reloc_class_copy;
109575d7
JW		 17925 case R_ARM_IRELATIVE:
17926 return reloc_class_ifunc;
99e4ae17
AJ		 17927 default:
17928 return reloc_class_normal;
17929 }
17930}
17931
e489d0ae 17932static void
57e8b36a 17933elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 17934{
5a6c6817 17935 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17936}
17937
40a18ebd
NC		 17938/* Return TRUE if this is an unwinding table entry. */
17939
17940static bfd_boolean
17941is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17942{
0112cd26
NC		 17943 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17944 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17945}
17946
17947
17948/* Set the type and flags for an ARM section. We do this by
17949 the section name, which is a hack, but ought to work. */
17950
17951static bfd_boolean
17952elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17953{
17954 const char * name;
17955
17956 name = bfd_get_section_name (abfd, sec);
17957
17958 if (is_arm_elf_unwind_section_name (abfd, name))
17959 {
17960 hdr->sh_type = SHT_ARM_EXIDX;
17961 hdr->sh_flags |= SHF_LINK_ORDER;
17962 }
ac4c9b04 17963
f0728ee3
AV		 17964 if (sec->flags & SEC_ELF_PURECODE)
17965 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17966
40a18ebd
NC		 17967 return TRUE;
17968}
17969
6dc132d9
L		 17970/* Handle an ARM specific section when reading an object file. This is
17971 called when bfd_section_from_shdr finds a section with an unknown
17972 type. */
40a18ebd
NC		 17973
17974static bfd_boolean
17975elf32_arm_section_from_shdr (bfd *abfd,
17976 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17977 const char *name,
17978 int shindex)
40a18ebd
NC		 17979{
17980 /* There ought to be a place to keep ELF backend specific flags, but
17981 at the moment there isn't one. We just keep track of the
17982 sections by their name, instead. Fortunately, the ABI gives
17983 names for all the ARM specific sections, so we will probably get
17984 away with this. */
17985 switch (hdr->sh_type)
17986 {
17987 case SHT_ARM_EXIDX:
0951f019
RE		 17988 case SHT_ARM_PREEMPTMAP:
17989 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17990 break;
17991
17992 default:
17993 return FALSE;
17994 }
17995
6dc132d9 17996 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17997 return FALSE;
17998
17999 return TRUE;
18000}
e489d0ae 18001
44444f50
NC		 18002static _arm_elf_section_data *
18003get_arm_elf_section_data (asection * sec)
18004{
47b2e99c
JZ		 18005 if (sec && sec->owner && is_arm_elf (sec->owner))
18006 return elf32_arm_section_data (sec);
44444f50
NC		 18007 else
18008 return NULL;
8e3de13a
NC		 18009}
18010
4e617b1e
PB		 18011typedef struct
18012{
57402f1e 18013 void *flaginfo;
4e617b1e 18014 struct bfd_link_info *info;
91a5743d
PB		 18015 asection *sec;
18016 int sec_shndx;
6e0b88f1
AM		 18017 int (*func) (void *, const char *, Elf_Internal_Sym *,
18018 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 18019} output_arch_syminfo;
18020
18021enum map_symbol_type
18022{
18023 ARM_MAP_ARM,
18024 ARM_MAP_THUMB,
18025 ARM_MAP_DATA
18026};
18027
18028
7413f23f 18029/* Output a single mapping symbol. */
4e617b1e
PB		 18030
18031static bfd_boolean
7413f23f
DJ		 18032elf32_arm_output_map_sym (output_arch_syminfo *osi,
18033 enum map_symbol_type type,
18034 bfd_vma offset)
4e617b1e
PB		 18035{
18036 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 18037 Elf_Internal_Sym sym;
18038
91a5743d
PB		 18039 sym.st_value = osi->sec->output_section->vma
18040 + osi->sec->output_offset
18041 + offset;
4e617b1e
PB		 18042 sym.st_size = 0;
18043 sym.st_other = 0;
18044 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 18045 sym.st_shndx = osi->sec_shndx;
35fc36a8 18046 sym.st_target_internal = 0;
fe33d2fa 18047 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 18048 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 18049}
18050
34e77a92
RS		 18051/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
18052 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 18053
18054static bfd_boolean
34e77a92
RS		 18055elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
18056 bfd_boolean is_iplt_entry_p,
18057 union gotplt_union *root_plt,
18058 struct arm_plt_info *arm_plt)
4e617b1e 18059{
4e617b1e 18060 struct elf32_arm_link_hash_table *htab;
34e77a92 18061 bfd_vma addr, plt_header_size;
4e617b1e 18062
34e77a92 18063 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 18064 return TRUE;
18065
4dfe6ac6
NC		 18066 htab = elf32_arm_hash_table (osi->info);
18067 if (htab == NULL)
18068 return FALSE;
18069
34e77a92
RS		 18070 if (is_iplt_entry_p)
18071 {
18072 osi->sec = htab->root.iplt;
18073 plt_header_size = 0;
18074 }
18075 else
18076 {
18077 osi->sec = htab->root.splt;
18078 plt_header_size = htab->plt_header_size;
18079 }
18080 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
18081 (osi->info->output_bfd, osi->sec->output_section));
18082
18083 addr = root_plt->offset & -2;
4e617b1e
PB		 18084 if (htab->symbian_p)
18085 {
7413f23f 18086 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18087 return FALSE;
7413f23f 18088 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 18089 return FALSE;
18090 }
18091 else if (htab->vxworks_p)
18092 {
7413f23f 18093 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18094 return FALSE;
7413f23f 18095 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 18096 return FALSE;
7413f23f 18097 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 18098 return FALSE;
7413f23f 18099 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 18100 return FALSE;
18101 }
b38cadfb
NC		 18102 else if (htab->nacl_p)
18103 {
18104 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
18105 return FALSE;
18106 }
7801f98f
CL		 18107 else if (htab->fdpic_p)
18108 {
59029f57
CL		 18109 enum map_symbol_type type = using_thumb_only(htab)
18110 ? ARM_MAP_THUMB
18111 : ARM_MAP_ARM;
18112
7801f98f 18113 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 18114 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
18115 return FALSE;
59029f57 18116 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 18117 return FALSE;
7801f98f 18118 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 18119 return FALSE;
7801f98f 18120 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 18121 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
18122 return FALSE;
7801f98f 18123 }
eed94f8f
NC		 18124 else if (using_thumb_only (htab))
18125 {
18126 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
18127 return FALSE;
6a631e86 18128 }
4e617b1e
PB		 18129 else
18130 {
34e77a92 18131 bfd_boolean thumb_stub_p;
bd97cb95 18132
34e77a92
RS		 18133 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
18134 if (thumb_stub_p)
4e617b1e 18135 {
7413f23f 18136 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 18137 return FALSE;
18138 }
18139#ifdef FOUR_WORD_PLT
7413f23f 18140 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18141 return FALSE;
7413f23f 18142 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 18143 return FALSE;
18144#else
906e58ca 18145 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 18146 so only need to output a mapping symbol for the first PLT entry and
18147 entries with thumb thunks. */
34e77a92 18148 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 18149 {
7413f23f 18150 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 18151 return FALSE;
18152 }
18153#endif
18154 }
18155
18156 return TRUE;
18157}
18158
34e77a92
RS		 18159/* Output mapping symbols for PLT entries associated with H. */
18160
18161static bfd_boolean
18162elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
18163{
18164 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
18165 struct elf32_arm_link_hash_entry *eh;
18166
18167 if (h->root.type == bfd_link_hash_indirect)
18168 return TRUE;
18169
18170 if (h->root.type == bfd_link_hash_warning)
18171 /* When warning symbols are created, they **replace** the "real"
18172 entry in the hash table, thus we never get to see the real
18173 symbol in a hash traversal. So look at it now. */
18174 h = (struct elf_link_hash_entry *) h->root.u.i.link;
18175
18176 eh = (struct elf32_arm_link_hash_entry *) h;
18177 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
18178 &h->plt, &eh->plt);
18179}
18180
4f4faa4d
TP		 18181/* Bind a veneered symbol to its veneer identified by its hash entry
18182 STUB_ENTRY. The veneered location thus loose its symbol. */
18183
18184static void
18185arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
18186{
18187 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
18188
18189 BFD_ASSERT (hash);
18190 hash->root.root.u.def.section = stub_entry->stub_sec;
18191 hash->root.root.u.def.value = stub_entry->stub_offset;
18192 hash->root.size = stub_entry->stub_size;
18193}
18194
7413f23f
DJ		 18195/* Output a single local symbol for a generated stub. */
18196
18197static bfd_boolean
18198elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18199 bfd_vma offset, bfd_vma size)
18200{
7413f23f
DJ		 18201 Elf_Internal_Sym sym;
18202
7413f23f
DJ		 18203 sym.st_value = osi->sec->output_section->vma
18204 + osi->sec->output_offset
18205 + offset;
18206 sym.st_size = size;
18207 sym.st_other = 0;
18208 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18209 sym.st_shndx = osi->sec_shndx;
35fc36a8 18210 sym.st_target_internal = 0;
57402f1e 18211 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 18212}
4e617b1e 18213
da5938a2 18214static bfd_boolean
8029a119
NC		 18215arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18216 void * in_arg)
da5938a2
NC		 18217{
18218 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 18219 asection *stub_sec;
18220 bfd_vma addr;
7413f23f 18221 char *stub_name;
9a008db3 18222 output_arch_syminfo *osi;
d3ce72d0 18223 const insn_sequence *template_sequence;
461a49ca
DJ		 18224 enum stub_insn_type prev_type;
18225 int size;
18226 int i;
18227 enum map_symbol_type sym_type;
da5938a2
NC		 18228
18229 /* Massage our args to the form they really have. */
18230 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 18231 osi = (output_arch_syminfo *) in_arg;
da5938a2 18232
da5938a2
NC		 18233 stub_sec = stub_entry->stub_sec;
18234
18235 /* Ensure this stub is attached to the current section being
7413f23f 18236 processed. */
da5938a2
NC		 18237 if (stub_sec != osi->sec)
18238 return TRUE;
18239
7413f23f 18240 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18241 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18242
18243 if (arm_stub_sym_claimed (stub_entry->stub_type))
18244 arm_stub_claim_sym (stub_entry);
18245 else
7413f23f 18246 {
4f4faa4d
TP		 18247 stub_name = stub_entry->output_name;
18248 switch (template_sequence[0].type)
18249 {
18250 case ARM_TYPE:
18251 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18252 stub_entry->stub_size))
18253 return FALSE;
18254 break;
18255 case THUMB16_TYPE:
18256 case THUMB32_TYPE:
18257 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18258 stub_entry->stub_size))
18259 return FALSE;
18260 break;
18261 default:
18262 BFD_FAIL ();
18263 return 0;
18264 }
7413f23f 18265 }
da5938a2 18266
461a49ca
DJ		 18267 prev_type = DATA_TYPE;
18268 size = 0;
18269 for (i = 0; i < stub_entry->stub_template_size; i++)
18270 {
d3ce72d0 18271 switch (template_sequence[i].type)
461a49ca
DJ		 18272 {
18273 case ARM_TYPE:
18274 sym_type = ARM_MAP_ARM;
18275 break;
18276
18277 case THUMB16_TYPE:
48229727 18278 case THUMB32_TYPE:
461a49ca
DJ		 18279 sym_type = ARM_MAP_THUMB;
18280 break;
18281
18282 case DATA_TYPE:
18283 sym_type = ARM_MAP_DATA;
18284 break;
18285
18286 default:
18287 BFD_FAIL ();
4e31c731 18288 return FALSE;
461a49ca
DJ		 18289 }
18290
d3ce72d0 18291 if (template_sequence[i].type != prev_type)
461a49ca 18292 {
d3ce72d0 18293 prev_type = template_sequence[i].type;
461a49ca
DJ		 18294 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18295 return FALSE;
18296 }
18297
d3ce72d0 18298 switch (template_sequence[i].type)
461a49ca
DJ		 18299 {
18300 case ARM_TYPE:
48229727 18301 case THUMB32_TYPE:
461a49ca
DJ		 18302 size += 4;
18303 break;
18304
18305 case THUMB16_TYPE:
18306 size += 2;
18307 break;
18308
18309 case DATA_TYPE:
18310 size += 4;
18311 break;
18312
18313 default:
18314 BFD_FAIL ();
4e31c731 18315 return FALSE;
461a49ca
DJ		 18316 }
18317 }
18318
da5938a2
NC		 18319 return TRUE;
18320}
18321
33811162
DG		 18322/* Output mapping symbols for linker generated sections,
18323 and for those data-only sections that do not have a
18324 $d. */
4e617b1e
PB		 18325
18326static bfd_boolean
18327elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18328 struct bfd_link_info *info,
57402f1e 18329 void *flaginfo,
6e0b88f1
AM		 18330 int (*func) (void *, const char *,
18331 Elf_Internal_Sym *,
18332 asection *,
18333 struct elf_link_hash_entry *))
4e617b1e
PB		 18334{
18335 output_arch_syminfo osi;
18336 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18337 bfd_vma offset;
18338 bfd_size_type size;
33811162 18339 bfd *input_bfd;
4e617b1e
PB		 18340
18341 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18342 if (htab == NULL)
18343 return FALSE;
18344
906e58ca 18345 check_use_blx (htab);
91a5743d 18346
57402f1e 18347 osi.flaginfo = flaginfo;
4e617b1e
PB		 18348 osi.info = info;
18349 osi.func = func;
906e58ca 18350
33811162
DG		 18351 /* Add a $d mapping symbol to data-only sections that
18352 don't have any mapping symbol. This may result in (harmless) redundant
18353 mapping symbols. */
18354 for (input_bfd = info->input_bfds;
18355 input_bfd != NULL;
c72f2fb2 18356 input_bfd = input_bfd->link.next)
33811162
DG		 18357 {
18358 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18359 for (osi.sec = input_bfd->sections;
18360 osi.sec != NULL;
18361 osi.sec = osi.sec->next)
18362 {
18363 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18364 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18365 != 0)
33811162
DG		 18366 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18367 == SEC_HAS_CONTENTS
18368 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18369 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18370 && osi.sec->size > 0
18371 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18372 {
18373 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18374 (output_bfd, osi.sec->output_section);
18375 if (osi.sec_shndx != (int)SHN_BAD)
18376 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18377 }
18378 }
18379 }
18380
91a5743d
PB		 18381 /* ARM->Thumb glue. */
18382 if (htab->arm_glue_size > 0)
18383 {
3d4d4302
AM		 18384 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18385 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18386
18387 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18388 (output_bfd, osi.sec->output_section);
0e1862bb 18389 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18390 || htab->pic_veneer)
18391 size = ARM2THUMB_PIC_GLUE_SIZE;
18392 else if (htab->use_blx)
18393 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18394 else
18395 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18396
91a5743d
PB		 18397 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18398 {
7413f23f
DJ		 18399 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18400 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18401 }
18402 }
18403
18404 /* Thumb->ARM glue. */
18405 if (htab->thumb_glue_size > 0)
18406 {
3d4d4302
AM		 18407 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18408 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18409
18410 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18411 (output_bfd, osi.sec->output_section);
18412 size = THUMB2ARM_GLUE_SIZE;
18413
18414 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18415 {
7413f23f
DJ		 18416 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18417 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18418 }
18419 }
18420
845b51d6
PB		 18421 /* ARMv4 BX veneers. */
18422 if (htab->bx_glue_size > 0)
18423 {
3d4d4302
AM		 18424 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18425 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18426
18427 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18428 (output_bfd, osi.sec->output_section);
18429
7413f23f 18430 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18431 }
18432
8029a119
NC		 18433 /* Long calls stubs. */
18434 if (htab->stub_bfd && htab->stub_bfd->sections)
18435 {
da5938a2 18436 asection* stub_sec;
8029a119 18437
da5938a2
NC		 18438 for (stub_sec = htab->stub_bfd->sections;
18439 stub_sec != NULL;
8029a119
NC		 18440 stub_sec = stub_sec->next)
18441 {
18442 /* Ignore non-stub sections. */
18443 if (!strstr (stub_sec->name, STUB_SUFFIX))
18444 continue;
da5938a2 18445
8029a119 18446 osi.sec = stub_sec;
da5938a2 18447
8029a119
NC		 18448 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18449 (output_bfd, osi.sec->output_section);
da5938a2 18450
8029a119
NC		 18451 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18452 }
18453 }
da5938a2 18454
91a5743d 18455 /* Finally, output mapping symbols for the PLT. */
34e77a92 18456 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18457 {
34e77a92
RS		 18458 osi.sec = htab->root.splt;
18459 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18460 (output_bfd, osi.sec->output_section));
18461
18462 /* Output mapping symbols for the plt header. SymbianOS does not have a
18463 plt header. */
18464 if (htab->vxworks_p)
18465 {
18466 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18467 if (!bfd_link_pic (info))
34e77a92
RS		 18468 {
18469 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18470 return FALSE;
18471 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18472 return FALSE;
18473 }
18474 }
b38cadfb
NC		 18475 else if (htab->nacl_p)
18476 {
18477 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18478 return FALSE;
18479 }
59029f57 18480 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18481 {
18482 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18483 return FALSE;
18484 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18485 return FALSE;
18486 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18487 return FALSE;
18488 }
e8b09b87 18489 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18490 {
7413f23f 18491 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18492 return FALSE;
34e77a92
RS		 18493#ifndef FOUR_WORD_PLT
18494 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18495 return FALSE;
34e77a92 18496#endif
4e617b1e
PB		 18497 }
18498 }
99059e56
RM		 18499 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18500 {
18501 /* NaCl uses a special first entry in .iplt too. */
18502 osi.sec = htab->root.iplt;
18503 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18504 (output_bfd, osi.sec->output_section));
18505 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18506 return FALSE;
18507 }
34e77a92
RS		 18508 if ((htab->root.splt && htab->root.splt->size > 0)
18509 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18510 {
34e77a92
RS		 18511 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18512 for (input_bfd = info->input_bfds;
18513 input_bfd != NULL;
c72f2fb2 18514 input_bfd = input_bfd->link.next)
34e77a92
RS		 18515 {
18516 struct arm_local_iplt_info **local_iplt;
18517 unsigned int i, num_syms;
4e617b1e 18518
34e77a92
RS		 18519 local_iplt = elf32_arm_local_iplt (input_bfd);
18520 if (local_iplt != NULL)
18521 {
18522 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18523 for (i = 0; i < num_syms; i++)
18524 if (local_iplt[i] != NULL
18525 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18526 &local_iplt[i]->root,
18527 &local_iplt[i]->arm))
18528 return FALSE;
18529 }
18530 }
18531 }
0855e32b
NS		 18532 if (htab->dt_tlsdesc_plt != 0)
18533 {
18534 /* Mapping symbols for the lazy tls trampoline. */
18535 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18536 return FALSE;
b38cadfb 18537
0855e32b
NS		 18538 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18539 htab->dt_tlsdesc_plt + 24))
18540 return FALSE;
18541 }
18542 if (htab->tls_trampoline != 0)
18543 {
18544 /* Mapping symbols for the tls trampoline. */
18545 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18546 return FALSE;
18547#ifdef FOUR_WORD_PLT
18548 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18549 htab->tls_trampoline + 12))
18550 return FALSE;
b38cadfb 18551#endif
0855e32b 18552 }
b38cadfb 18553
4e617b1e
PB		 18554 return TRUE;
18555}
18556
54ddd295
TP		 18557/* Filter normal symbols of CMSE entry functions of ABFD to include in
18558 the import library. All SYMCOUNT symbols of ABFD can be examined
18559 from their pointers in SYMS. Pointers of symbols to keep should be
18560 stored continuously at the beginning of that array.
18561
18562 Returns the number of symbols to keep. */
18563
18564static unsigned int
18565elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18566 struct bfd_link_info *info,
18567 asymbol **syms, long symcount)
18568{
18569 size_t maxnamelen;
18570 char *cmse_name;
18571 long src_count, dst_count = 0;
18572 struct elf32_arm_link_hash_table *htab;
18573
18574 htab = elf32_arm_hash_table (info);
18575 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18576 symcount = 0;
18577
18578 maxnamelen = 128;
18579 cmse_name = (char *) bfd_malloc (maxnamelen);
18580 for (src_count = 0; src_count < symcount; src_count++)
18581 {
18582 struct elf32_arm_link_hash_entry *cmse_hash;
18583 asymbol *sym;
18584 flagword flags;
18585 char *name;
18586 size_t namelen;
18587
18588 sym = syms[src_count];
18589 flags = sym->flags;
18590 name = (char *) bfd_asymbol_name (sym);
18591
18592 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18593 continue;
18594 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18595 continue;
18596
18597 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18598 if (namelen > maxnamelen)
18599 {
18600 cmse_name = (char *)
18601 bfd_realloc (cmse_name, namelen);
18602 maxnamelen = namelen;
18603 }
18604 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18605 cmse_hash = (struct elf32_arm_link_hash_entry *)
18606 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18607
18608 if (!cmse_hash
18609 || (cmse_hash->root.root.type != bfd_link_hash_defined
18610 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18611 || cmse_hash->root.type != STT_FUNC)
18612 continue;
18613
18614 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
18615 continue;
18616
18617 syms[dst_count++] = sym;
18618 }
18619 free (cmse_name);
18620
18621 syms[dst_count] = NULL;
18622
18623 return dst_count;
18624}
18625
18626/* Filter symbols of ABFD to include in the import library. All
18627 SYMCOUNT symbols of ABFD can be examined from their pointers in
18628 SYMS. Pointers of symbols to keep should be stored continuously at
18629 the beginning of that array.
18630
18631 Returns the number of symbols to keep. */
18632
18633static unsigned int
18634elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18635 struct bfd_link_info *info,
18636 asymbol **syms, long symcount)
18637{
18638 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18639
046734ff
TP		 18640 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18641 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18642 library to be a relocatable object file. */
18643 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18644 if (globals->cmse_implib)
18645 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18646 else
18647 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18648}
18649
e489d0ae
PB		 18650/* Allocate target specific section data. */
18651
18652static bfd_boolean
18653elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18654{
f592407e
AM		 18655 if (!sec->used_by_bfd)
18656 {
18657 _arm_elf_section_data *sdata;
18658 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18659
21d799b5 18660 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18661 if (sdata == NULL)
18662 return FALSE;
18663 sec->used_by_bfd = sdata;
18664 }
e489d0ae
PB		 18665
18666 return _bfd_elf_new_section_hook (abfd, sec);
18667}
18668
18669
18670/* Used to order a list of mapping symbols by address. */
18671
18672static int
18673elf32_arm_compare_mapping (const void * a, const void * b)
18674{
7f6a71ff
JM		 18675 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18676 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18677
18678 if (amap->vma > bmap->vma)
18679 return 1;
18680 else if (amap->vma < bmap->vma)
18681 return -1;
18682 else if (amap->type > bmap->type)
18683 /* Ensure results do not depend on the host qsort for objects with
18684 multiple mapping symbols at the same address by sorting on type
18685 after vma. */
18686 return 1;
18687 else if (amap->type < bmap->type)
18688 return -1;
18689 else
18690 return 0;
e489d0ae
PB		 18691}
18692
2468f9c9
PB		 18693/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18694
18695static unsigned long
18696offset_prel31 (unsigned long addr, bfd_vma offset)
18697{
18698 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18699}
18700
18701/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18702 relocations. */
18703
18704static void
18705copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18706{
18707 unsigned long first_word = bfd_get_32 (output_bfd, from);
18708 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18709
2468f9c9
PB		 18710 /* High bit of first word is supposed to be zero. */
18711 if ((first_word & 0x80000000ul) == 0)
18712 first_word = offset_prel31 (first_word, offset);
b38cadfb 18713
2468f9c9
PB		 18714 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18715 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18716 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18717 second_word = offset_prel31 (second_word, offset);
b38cadfb 18718
2468f9c9
PB		 18719 bfd_put_32 (output_bfd, first_word, to);
18720 bfd_put_32 (output_bfd, second_word, to + 4);
18721}
e489d0ae 18722
48229727
JB		 18723/* Data for make_branch_to_a8_stub(). */
18724
b38cadfb
NC		 18725struct a8_branch_to_stub_data
18726{
48229727
JB		 18727 asection *writing_section;
18728 bfd_byte *contents;
18729};
18730
18731
18732/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18733 places for a particular section. */
18734
18735static bfd_boolean
18736make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18737 void *in_arg)
48229727
JB		 18738{
18739 struct elf32_arm_stub_hash_entry *stub_entry;
18740 struct a8_branch_to_stub_data *data;
18741 bfd_byte *contents;
18742 unsigned long branch_insn;
18743 bfd_vma veneered_insn_loc, veneer_entry_loc;
18744 bfd_signed_vma branch_offset;
18745 bfd *abfd;
8d9d9490 18746 unsigned int loc;
48229727
JB		 18747
18748 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18749 data = (struct a8_branch_to_stub_data *) in_arg;
18750
18751 if (stub_entry->target_section != data->writing_section
4563a860 18752 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18753 return TRUE;
18754
18755 contents = data->contents;
18756
8d9d9490
TP		 18757 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18758 generated when both source and target are in the same section. */
48229727
JB		 18759 veneered_insn_loc = stub_entry->target_section->output_section->vma
18760 + stub_entry->target_section->output_offset
8d9d9490 18761 + stub_entry->source_value;
48229727
JB		 18762
18763 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18764 + stub_entry->stub_sec->output_offset
18765 + stub_entry->stub_offset;
18766
18767 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18768 veneered_insn_loc &= ~3u;
18769
18770 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18771
18772 abfd = stub_entry->target_section->owner;
8d9d9490 18773 loc = stub_entry->source_value;
48229727
JB		 18774
18775 /* We attempt to avoid this condition by setting stubs_always_after_branch
18776 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18777 This check is just to be on the safe side... */
18778 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18779 {
871b3ab2 18780 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18781 "allocated in unsafe location"), abfd);
48229727
JB		 18782 return FALSE;
18783 }
18784
18785 switch (stub_entry->stub_type)
18786 {
18787 case arm_stub_a8_veneer_b:
18788 case arm_stub_a8_veneer_b_cond:
18789 branch_insn = 0xf0009000;
18790 goto jump24;
18791
18792 case arm_stub_a8_veneer_blx:
18793 branch_insn = 0xf000e800;
18794 goto jump24;
18795
18796 case arm_stub_a8_veneer_bl:
18797 {
18798 unsigned int i1, j1, i2, j2, s;
18799
18800 branch_insn = 0xf000d000;
18801
18802 jump24:
18803 if (branch_offset < -16777216 || branch_offset > 16777214)
18804 {
18805 /* There's not much we can do apart from complain if this
18806 happens. */
871b3ab2 18807 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18808 "of range (input file too large)"), abfd);
48229727
JB		 18809 return FALSE;
18810 }
18811
18812 /* i1 = not(j1 eor s), so:
18813 not i1 = j1 eor s
18814 j1 = (not i1) eor s. */
18815
18816 branch_insn |= (branch_offset >> 1) & 0x7ff;
18817 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18818 i2 = (branch_offset >> 22) & 1;
18819 i1 = (branch_offset >> 23) & 1;
18820 s = (branch_offset >> 24) & 1;
18821 j1 = (!i1) ^ s;
18822 j2 = (!i2) ^ s;
18823 branch_insn |= j2 << 11;
18824 branch_insn |= j1 << 13;
18825 branch_insn |= s << 26;
18826 }
18827 break;
18828
18829 default:
18830 BFD_FAIL ();
18831 return FALSE;
18832 }
18833
8d9d9490
TP		 18834 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18835 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18836
18837 return TRUE;
18838}
18839
a504d23a
LA		 18840/* Beginning of stm32l4xx work-around. */
18841
18842/* Functions encoding instructions necessary for the emission of the
18843 fix-stm32l4xx-629360.
18844 Encoding is extracted from the
18845 ARM (C) Architecture Reference Manual
18846 ARMv7-A and ARMv7-R edition
18847 ARM DDI 0406C.b (ID072512). */
18848
18849static inline bfd_vma
82188b29 18850create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18851{
18852 /* A8.8.18 B (A8-334)
18853 B target_address (Encoding T4). */
18854 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18855 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18856 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18857
a504d23a
LA		 18858 int s = ((branch_offset & 0x1000000) >> 24);
18859 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18860 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18861
18862 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18863 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18864
18865 bfd_vma patched_inst = 0xf0009000
18866 | s << 26 /* S. */
18867 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18868 | j1 << 13 /* J1. */
18869 | j2 << 11 /* J2. */
18870 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18871
18872 return patched_inst;
18873}
18874
18875static inline bfd_vma
18876create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18877{
18878 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18879 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18880 bfd_vma patched_inst = 0xe8900000
18881 | (/*W=*/wback << 21)
18882 | (base_reg << 16)
18883 | (reg_mask & 0x0000ffff);
18884
18885 return patched_inst;
18886}
18887
18888static inline bfd_vma
18889create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18890{
18891 /* A8.8.60 LDMDB/LDMEA (A8-402)
18892 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18893 bfd_vma patched_inst = 0xe9100000
18894 | (/*W=*/wback << 21)
18895 | (base_reg << 16)
18896 | (reg_mask & 0x0000ffff);
18897
18898 return patched_inst;
18899}
18900
18901static inline bfd_vma
18902create_instruction_mov (int target_reg, int source_reg)
18903{
18904 /* A8.8.103 MOV (register) (A8-486)
18905 MOV Rd, Rm (Encoding T1). */
18906 bfd_vma patched_inst = 0x4600
18907 | (target_reg & 0x7)
18908 | ((target_reg & 0x8) >> 3) << 7
18909 | (source_reg << 3);
18910
18911 return patched_inst;
18912}
18913
18914static inline bfd_vma
18915create_instruction_sub (int target_reg, int source_reg, int value)
18916{
18917 /* A8.8.221 SUB (immediate) (A8-708)
18918 SUB Rd, Rn, #value (Encoding T3). */
18919 bfd_vma patched_inst = 0xf1a00000
18920 | (target_reg << 8)
18921 | (source_reg << 16)
18922 | (/*S=*/0 << 20)
18923 | ((value & 0x800) >> 11) << 26
18924 | ((value & 0x700) >> 8) << 12
18925 | (value & 0x0ff);
18926
18927 return patched_inst;
18928}
18929
18930static inline bfd_vma
9239bbd3 18931create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18932 int first_reg)
18933{
18934 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18935 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18936 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18937 | (/*W=*/wback << 21)
18938 | (base_reg << 16)
9239bbd3
CM		 18939 | (num_words & 0x000000ff)
18940 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18941 | (first_reg & 0x00000001) << 22;
18942
18943 return patched_inst;
18944}
18945
18946static inline bfd_vma
9239bbd3
CM		 18947create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18948 int first_reg)
a504d23a
LA		 18949{
18950 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18951 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18952 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18953 | (base_reg << 16)
9239bbd3
CM		 18954 | (num_words & 0x000000ff)
18955 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18956 | (first_reg & 0x00000001) << 22;
18957
18958 return patched_inst;
18959}
18960
18961static inline bfd_vma
18962create_instruction_udf_w (int value)
18963{
18964 /* A8.8.247 UDF (A8-758)
18965 Undefined (Encoding T2). */
18966 bfd_vma patched_inst = 0xf7f0a000
18967 | (value & 0x00000fff)
18968 | (value & 0x000f0000) << 16;
18969
18970 return patched_inst;
18971}
18972
18973static inline bfd_vma
18974create_instruction_udf (int value)
18975{
18976 /* A8.8.247 UDF (A8-758)
18977 Undefined (Encoding T1). */
18978 bfd_vma patched_inst = 0xde00
18979 | (value & 0xff);
18980
18981 return patched_inst;
18982}
18983
18984/* Functions writing an instruction in memory, returning the next
18985 memory position to write to. */
18986
18987static inline bfd_byte *
18988push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18989 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18990{
18991 put_thumb2_insn (htab, output_bfd, insn, pt);
18992 return pt + 4;
18993}
18994
18995static inline bfd_byte *
18996push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18997 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18998{
18999 put_thumb_insn (htab, output_bfd, insn, pt);
19000 return pt + 2;
19001}
19002
19003/* Function filling up a region in memory with T1 and T2 UDFs taking
19004 care of alignment. */
19005
19006static bfd_byte *
19007stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 19008 bfd * output_bfd,
19009 const bfd_byte * const base_stub_contents,
19010 bfd_byte * const from_stub_contents,
19011 const bfd_byte * const end_stub_contents)
a504d23a
LA		 19012{
19013 bfd_byte *current_stub_contents = from_stub_contents;
19014
19015 /* Fill the remaining of the stub with deterministic contents : UDF
19016 instructions.
19017 Check if realignment is needed on modulo 4 frontier using T1, to
19018 further use T2. */
19019 if ((current_stub_contents < end_stub_contents)
19020 && !((current_stub_contents - base_stub_contents) % 2)
19021 && ((current_stub_contents - base_stub_contents) % 4))
19022 current_stub_contents =
19023 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19024 create_instruction_udf (0));
19025
19026 for (; current_stub_contents < end_stub_contents;)
19027 current_stub_contents =
19028 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19029 create_instruction_udf_w (0));
19030
19031 return current_stub_contents;
19032}
19033
19034/* Functions writing the stream of instructions equivalent to the
19035 derived sequence for ldmia, ldmdb, vldm respectively. */
19036
19037static void
19038stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
19039 bfd * output_bfd,
19040 const insn32 initial_insn,
19041 const bfd_byte *const initial_insn_addr,
19042 bfd_byte *const base_stub_contents)
19043{
19044 int wback = (initial_insn & 0x00200000) >> 21;
19045 int ri, rn = (initial_insn & 0x000F0000) >> 16;
19046 int insn_all_registers = initial_insn & 0x0000ffff;
19047 int insn_low_registers, insn_high_registers;
19048 int usable_register_mask;
b25e998d 19049 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19050 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19051 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
19052 bfd_byte *current_stub_contents = base_stub_contents;
19053
19054 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
19055
19056 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19057 smaller than 8 registers load sequences that do not cause the
19058 hardware issue. */
19059 if (nb_registers <= 8)
19060 {
19061 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19062 current_stub_contents =
19063 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19064 initial_insn);
19065
19066 /* B initial_insn_addr+4. */
19067 if (!restore_pc)
19068 current_stub_contents =
19069 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19070 create_instruction_branch_absolute
82188b29 19071 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19072
19073 /* Fill the remaining of the stub with deterministic contents. */
19074 current_stub_contents =
19075 stm32l4xx_fill_stub_udf (htab, output_bfd,
19076 base_stub_contents, current_stub_contents,
19077 base_stub_contents +
19078 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19079
19080 return;
19081 }
19082
19083 /* - reg_list[13] == 0. */
19084 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
19085
19086 /* - reg_list[14] & reg_list[15] != 1. */
19087 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19088
19089 /* - if (wback==1) reg_list[rn] == 0. */
19090 BFD_ASSERT (!wback || !restore_rn);
19091
19092 /* - nb_registers > 8. */
b25e998d 19093 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19094
19095 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19096
19097 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
19098 - One with the 7 lowest registers (register mask 0x007F)
19099 This LDM will finally contain between 2 and 7 registers
19100 - One with the 7 highest registers (register mask 0xDF80)
19101 This ldm will finally contain between 2 and 7 registers. */
19102 insn_low_registers = insn_all_registers & 0x007F;
19103 insn_high_registers = insn_all_registers & 0xDF80;
19104
19105 /* A spare register may be needed during this veneer to temporarily
19106 handle the base register. This register will be restored with the
19107 last LDM operation.
19108 The usable register may be any general purpose register (that
19109 excludes PC, SP, LR : register mask is 0x1FFF). */
19110 usable_register_mask = 0x1FFF;
19111
19112 /* Generate the stub function. */
19113 if (wback)
19114 {
19115 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
19116 current_stub_contents =
19117 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19118 create_instruction_ldmia
19119 (rn, /*wback=*/1, insn_low_registers));
19120
19121 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19122 current_stub_contents =
19123 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19124 create_instruction_ldmia
19125 (rn, /*wback=*/1, insn_high_registers));
19126 if (!restore_pc)
19127 {
19128 /* B initial_insn_addr+4. */
19129 current_stub_contents =
19130 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19131 create_instruction_branch_absolute
82188b29 19132 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19133 }
19134 }
19135 else /* if (!wback). */
19136 {
19137 ri = rn;
19138
19139 /* If Rn is not part of the high-register-list, move it there. */
19140 if (!(insn_high_registers & (1 << rn)))
19141 {
19142 /* Choose a Ri in the high-register-list that will be restored. */
19143 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19144
19145 /* MOV Ri, Rn. */
19146 current_stub_contents =
19147 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19148 create_instruction_mov (ri, rn));
19149 }
19150
19151 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19152 current_stub_contents =
19153 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19154 create_instruction_ldmia
19155 (ri, /*wback=*/1, insn_low_registers));
19156
19157 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19158 current_stub_contents =
19159 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19160 create_instruction_ldmia
19161 (ri, /*wback=*/0, insn_high_registers));
19162
19163 if (!restore_pc)
19164 {
19165 /* B initial_insn_addr+4. */
19166 current_stub_contents =
19167 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19168 create_instruction_branch_absolute
82188b29 19169 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19170 }
19171 }
19172
19173 /* Fill the remaining of the stub with deterministic contents. */
19174 current_stub_contents =
19175 stm32l4xx_fill_stub_udf (htab, output_bfd,
19176 base_stub_contents, current_stub_contents,
19177 base_stub_contents +
19178 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19179}
19180
19181static void
19182stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19183 bfd * output_bfd,
19184 const insn32 initial_insn,
19185 const bfd_byte *const initial_insn_addr,
19186 bfd_byte *const base_stub_contents)
19187{
19188 int wback = (initial_insn & 0x00200000) >> 21;
19189 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19190 int insn_all_registers = initial_insn & 0x0000ffff;
19191 int insn_low_registers, insn_high_registers;
19192 int usable_register_mask;
19193 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19194 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 19195 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19196 bfd_byte *current_stub_contents = base_stub_contents;
19197
19198 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19199
19200 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19201 smaller than 8 registers load sequences that do not cause the
19202 hardware issue. */
19203 if (nb_registers <= 8)
19204 {
19205 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19206 current_stub_contents =
19207 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19208 initial_insn);
19209
19210 /* B initial_insn_addr+4. */
19211 current_stub_contents =
19212 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19213 create_instruction_branch_absolute
82188b29 19214 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19215
19216 /* Fill the remaining of the stub with deterministic contents. */
19217 current_stub_contents =
19218 stm32l4xx_fill_stub_udf (htab, output_bfd,
19219 base_stub_contents, current_stub_contents,
19220 base_stub_contents +
19221 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19222
19223 return;
19224 }
19225
19226 /* - reg_list[13] == 0. */
19227 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19228
19229 /* - reg_list[14] & reg_list[15] != 1. */
19230 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19231
19232 /* - if (wback==1) reg_list[rn] == 0. */
19233 BFD_ASSERT (!wback || !restore_rn);
19234
19235 /* - nb_registers > 8. */
b25e998d 19236 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19237
19238 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19239
19240 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19241 - One with the 7 lowest registers (register mask 0x007F)
19242 This LDM will finally contain between 2 and 7 registers
19243 - One with the 7 highest registers (register mask 0xDF80)
19244 This ldm will finally contain between 2 and 7 registers. */
19245 insn_low_registers = insn_all_registers & 0x007F;
19246 insn_high_registers = insn_all_registers & 0xDF80;
19247
19248 /* A spare register may be needed during this veneer to temporarily
19249 handle the base register. This register will be restored with
19250 the last LDM operation.
19251 The usable register may be any general purpose register (that excludes
19252 PC, SP, LR : register mask is 0x1FFF). */
19253 usable_register_mask = 0x1FFF;
19254
19255 /* Generate the stub function. */
19256 if (!wback && !restore_pc && !restore_rn)
19257 {
19258 /* Choose a Ri in the low-register-list that will be restored. */
19259 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19260
19261 /* MOV Ri, Rn. */
19262 current_stub_contents =
19263 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19264 create_instruction_mov (ri, rn));
19265
19266 /* LDMDB Ri!, {R-high-register-list}. */
19267 current_stub_contents =
19268 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19269 create_instruction_ldmdb
19270 (ri, /*wback=*/1, insn_high_registers));
19271
19272 /* LDMDB Ri, {R-low-register-list}. */
19273 current_stub_contents =
19274 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19275 create_instruction_ldmdb
19276 (ri, /*wback=*/0, insn_low_registers));
19277
19278 /* B initial_insn_addr+4. */
19279 current_stub_contents =
19280 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19281 create_instruction_branch_absolute
82188b29 19282 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19283 }
19284 else if (wback && !restore_pc && !restore_rn)
19285 {
19286 /* LDMDB Rn!, {R-high-register-list}. */
19287 current_stub_contents =
19288 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19289 create_instruction_ldmdb
19290 (rn, /*wback=*/1, insn_high_registers));
19291
19292 /* LDMDB Rn!, {R-low-register-list}. */
19293 current_stub_contents =
19294 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19295 create_instruction_ldmdb
19296 (rn, /*wback=*/1, insn_low_registers));
19297
19298 /* B initial_insn_addr+4. */
19299 current_stub_contents =
19300 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19301 create_instruction_branch_absolute
82188b29 19302 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19303 }
19304 else if (!wback && restore_pc && !restore_rn)
19305 {
19306 /* Choose a Ri in the high-register-list that will be restored. */
19307 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19308
19309 /* SUB Ri, Rn, #(4*nb_registers). */
19310 current_stub_contents =
19311 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19312 create_instruction_sub (ri, rn, (4 * nb_registers)));
19313
19314 /* LDMIA Ri!, {R-low-register-list}. */
19315 current_stub_contents =
19316 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19317 create_instruction_ldmia
19318 (ri, /*wback=*/1, insn_low_registers));
19319
19320 /* LDMIA Ri, {R-high-register-list}. */
19321 current_stub_contents =
19322 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19323 create_instruction_ldmia
19324 (ri, /*wback=*/0, insn_high_registers));
19325 }
19326 else if (wback && restore_pc && !restore_rn)
19327 {
19328 /* Choose a Ri in the high-register-list that will be restored. */
19329 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19330
19331 /* SUB Rn, Rn, #(4*nb_registers) */
19332 current_stub_contents =
19333 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19334 create_instruction_sub (rn, rn, (4 * nb_registers)));
19335
19336 /* MOV Ri, Rn. */
19337 current_stub_contents =
19338 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19339 create_instruction_mov (ri, rn));
19340
19341 /* LDMIA Ri!, {R-low-register-list}. */
19342 current_stub_contents =
19343 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19344 create_instruction_ldmia
19345 (ri, /*wback=*/1, insn_low_registers));
19346
19347 /* LDMIA Ri, {R-high-register-list}. */
19348 current_stub_contents =
19349 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19350 create_instruction_ldmia
19351 (ri, /*wback=*/0, insn_high_registers));
19352 }
19353 else if (!wback && !restore_pc && restore_rn)
19354 {
19355 ri = rn;
19356 if (!(insn_low_registers & (1 << rn)))
19357 {
19358 /* Choose a Ri in the low-register-list that will be restored. */
19359 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19360
19361 /* MOV Ri, Rn. */
19362 current_stub_contents =
19363 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19364 create_instruction_mov (ri, rn));
19365 }
19366
19367 /* LDMDB Ri!, {R-high-register-list}. */
19368 current_stub_contents =
19369 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19370 create_instruction_ldmdb
19371 (ri, /*wback=*/1, insn_high_registers));
19372
19373 /* LDMDB Ri, {R-low-register-list}. */
19374 current_stub_contents =
19375 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19376 create_instruction_ldmdb
19377 (ri, /*wback=*/0, insn_low_registers));
19378
19379 /* B initial_insn_addr+4. */
19380 current_stub_contents =
19381 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19382 create_instruction_branch_absolute
82188b29 19383 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19384 }
19385 else if (!wback && restore_pc && restore_rn)
19386 {
19387 ri = rn;
19388 if (!(insn_high_registers & (1 << rn)))
19389 {
19390 /* Choose a Ri in the high-register-list that will be restored. */
19391 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19392 }
19393
19394 /* SUB Ri, Rn, #(4*nb_registers). */
19395 current_stub_contents =
19396 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19397 create_instruction_sub (ri, rn, (4 * nb_registers)));
19398
19399 /* LDMIA Ri!, {R-low-register-list}. */
19400 current_stub_contents =
19401 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19402 create_instruction_ldmia
19403 (ri, /*wback=*/1, insn_low_registers));
19404
19405 /* LDMIA Ri, {R-high-register-list}. */
19406 current_stub_contents =
19407 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19408 create_instruction_ldmia
19409 (ri, /*wback=*/0, insn_high_registers));
19410 }
19411 else if (wback && restore_rn)
19412 {
19413 /* The assembler should not have accepted to encode this. */
19414 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19415 "undefined behavior.\n");
19416 }
19417
19418 /* Fill the remaining of the stub with deterministic contents. */
19419 current_stub_contents =
19420 stm32l4xx_fill_stub_udf (htab, output_bfd,
19421 base_stub_contents, current_stub_contents,
19422 base_stub_contents +
19423 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19424
19425}
19426
19427static void
19428stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19429 bfd * output_bfd,
19430 const insn32 initial_insn,
19431 const bfd_byte *const initial_insn_addr,
19432 bfd_byte *const base_stub_contents)
19433{
9239bbd3 19434 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 19435 bfd_byte *current_stub_contents = base_stub_contents;
19436
19437 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19438
19439 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19440 smaller than 8 words load sequences that do not cause the
a504d23a 19441 hardware issue. */
9239bbd3 19442 if (num_words <= 8)
a504d23a
LA		 19443 {
19444 /* Untouched instruction. */
19445 current_stub_contents =
19446 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19447 initial_insn);
19448
19449 /* B initial_insn_addr+4. */
19450 current_stub_contents =
19451 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19452 create_instruction_branch_absolute
82188b29 19453 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19454 }
19455 else
19456 {
9eaff861 19457 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19458 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19459 bfd_boolean is_ia_nobang = /* (IA without !). */
19460 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19461 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19462 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19463 bfd_boolean is_db_bang = /* (DB with !). */
19464 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19465 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19466 /* d = UInt (Vd:D);. */
9239bbd3 19467 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19468 | (((unsigned int)initial_insn << 9) >> 31);
19469
9239bbd3
CM		 19470 /* Compute the number of 8-words chunks needed to split. */
19471 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19472 int chunk;
19473
19474 /* The test coverage has been done assuming the following
19475 hypothesis that exactly one of the previous is_ predicates is
19476 true. */
9239bbd3
CM		 19477 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19478 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19479
9239bbd3 19480 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19481 cases, then we emit the adjustments:
19482
19483 vldm rx, {...}
19484 -> vldm rx!, {8_words_or_less} for each needed 8_word
19485 -> sub rx, rx, #size (list)
19486
19487 vldm rx!, {...}
19488 -> vldm rx!, {8_words_or_less} for each needed 8_word
19489 This also handles vpop instruction (when rx is sp)
19490
19491 vldmd rx!, {...}
19492 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19493 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19494 {
9239bbd3
CM		 19495 bfd_vma new_insn = 0;
19496
a504d23a
LA		 19497 if (is_ia_nobang || is_ia_bang)
19498 {
9239bbd3
CM		 19499 new_insn = create_instruction_vldmia
19500 (base_reg,
19501 is_dp,
19502 /*wback= . */1,
19503 chunks - (chunk + 1) ?
19504 8 : num_words - chunk * 8,
19505 first_reg + chunk * 8);
a504d23a
LA		 19506 }
19507 else if (is_db_bang)
19508 {
9239bbd3
CM		 19509 new_insn = create_instruction_vldmdb
19510 (base_reg,
19511 is_dp,
19512 chunks - (chunk + 1) ?
19513 8 : num_words - chunk * 8,
19514 first_reg + chunk * 8);
a504d23a 19515 }
9239bbd3
CM		 19516
19517 if (new_insn)
19518 current_stub_contents =
19519 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19520 new_insn);
a504d23a
LA		 19521 }
19522
19523 /* Only this case requires the base register compensation
19524 subtract. */
19525 if (is_ia_nobang)
19526 {
19527 current_stub_contents =
19528 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19529 create_instruction_sub
9239bbd3 19530 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19531 }
19532
19533 /* B initial_insn_addr+4. */
19534 current_stub_contents =
19535 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19536 create_instruction_branch_absolute
82188b29 19537 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19538 }
19539
19540 /* Fill the remaining of the stub with deterministic contents. */
19541 current_stub_contents =
19542 stm32l4xx_fill_stub_udf (htab, output_bfd,
19543 base_stub_contents, current_stub_contents,
19544 base_stub_contents +
19545 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19546}
19547
19548static void
19549stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19550 bfd * output_bfd,
19551 const insn32 wrong_insn,
19552 const bfd_byte *const wrong_insn_addr,
19553 bfd_byte *const stub_contents)
19554{
19555 if (is_thumb2_ldmia (wrong_insn))
19556 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19557 wrong_insn, wrong_insn_addr,
19558 stub_contents);
19559 else if (is_thumb2_ldmdb (wrong_insn))
19560 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19561 wrong_insn, wrong_insn_addr,
19562 stub_contents);
19563 else if (is_thumb2_vldm (wrong_insn))
19564 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19565 wrong_insn, wrong_insn_addr,
19566 stub_contents);
19567}
19568
19569/* End of stm32l4xx work-around. */
19570
19571
e489d0ae
PB		 19572/* Do code byteswapping. Return FALSE afterwards so that the section is
19573 written out as normal. */
19574
19575static bfd_boolean
c7b8f16e 19576elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19577 struct bfd_link_info *link_info,
19578 asection *sec,
e489d0ae
PB		 19579 bfd_byte *contents)
19580{
48229727 19581 unsigned int mapcount, errcount;
8e3de13a 19582 _arm_elf_section_data *arm_data;
c7b8f16e 19583 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19584 elf32_arm_section_map *map;
c7b8f16e 19585 elf32_vfp11_erratum_list *errnode;
a504d23a 19586 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19587 bfd_vma ptr;
19588 bfd_vma end;
c7b8f16e 19589 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19590 bfd_byte tmp;
48229727 19591 unsigned int i;
57e8b36a 19592
4dfe6ac6
NC		 19593 if (globals == NULL)
19594 return FALSE;
19595
8e3de13a
NC		 19596 /* If this section has not been allocated an _arm_elf_section_data
19597 structure then we cannot record anything. */
19598 arm_data = get_arm_elf_section_data (sec);
19599 if (arm_data == NULL)
19600 return FALSE;
19601
19602 mapcount = arm_data->mapcount;
19603 map = arm_data->map;
c7b8f16e
JB		 19604 errcount = arm_data->erratumcount;
19605
19606 if (errcount != 0)
19607 {
19608 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19609
19610 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19611 errnode = errnode->next)
19612 {
19613 bfd_vma target = errnode->vma - offset;
19614
19615 switch (errnode->type)
19616 {
19617 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19618 {
19619 bfd_vma branch_to_veneer;
19620 /* Original condition code of instruction, plus bit mask for
19621 ARM B instruction. */
19622 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19623 | 0x0a000000;
c7b8f16e
JB		 19624
19625 /* The instruction is before the label. */
91d6fa6a 19626 target -= 4;
c7b8f16e
JB		 19627
19628 /* Above offset included in -4 below. */
19629 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19630 - errnode->vma - 4;
c7b8f16e
JB		 19631
19632 if ((signed) branch_to_veneer < -(1 << 25)
19633 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19634 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19635 "range"), output_bfd);
c7b8f16e 19636
99059e56
RM		 19637 insn |= (branch_to_veneer >> 2) & 0xffffff;
19638 contents[endianflip ^ target] = insn & 0xff;
19639 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19640 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19641 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19642 }
19643 break;
c7b8f16e
JB		 19644
19645 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19646 {
19647 bfd_vma branch_from_veneer;
19648 unsigned int insn;
c7b8f16e 19649
99059e56
RM		 19650 /* Take size of veneer into account. */
19651 branch_from_veneer = errnode->u.v.branch->vma
19652 - errnode->vma - 12;
c7b8f16e
JB		 19653
19654 if ((signed) branch_from_veneer < -(1 << 25)
19655 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19656 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19657 "range"), output_bfd);
c7b8f16e 19658
99059e56
RM		 19659 /* Original instruction. */
19660 insn = errnode->u.v.branch->u.b.vfp_insn;
19661 contents[endianflip ^ target] = insn & 0xff;
19662 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19663 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19664 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19665
19666 /* Branch back to insn after original insn. */
19667 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19668 contents[endianflip ^ (target + 4)] = insn & 0xff;
19669 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19670 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19671 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19672 }
19673 break;
c7b8f16e 19674
99059e56
RM		 19675 default:
19676 abort ();
19677 }
19678 }
c7b8f16e 19679 }
e489d0ae 19680
a504d23a
LA		 19681 if (arm_data->stm32l4xx_erratumcount != 0)
19682 {
19683 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19684 stm32l4xx_errnode != 0;
19685 stm32l4xx_errnode = stm32l4xx_errnode->next)
19686 {
19687 bfd_vma target = stm32l4xx_errnode->vma - offset;
19688
19689 switch (stm32l4xx_errnode->type)
19690 {
19691 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19692 {
19693 unsigned int insn;
19694 bfd_vma branch_to_veneer =
19695 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19696
19697 if ((signed) branch_to_veneer < -(1 << 24)
19698 || (signed) branch_to_veneer >= (1 << 24))
19699 {
19700 bfd_vma out_of_range =
19701 ((signed) branch_to_veneer < -(1 << 24)) ?
19702 - branch_to_veneer - (1 << 24) :
19703 ((signed) branch_to_veneer >= (1 << 24)) ?
19704 branch_to_veneer - (1 << 24) : 0;
19705
4eca0228 19706 _bfd_error_handler
2dcf00ce 19707 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19708 "cannot create STM32L4XX veneer; "
19709 "jump out of range by %" PRId64 " bytes; "
19710 "cannot encode branch instruction"),
a504d23a 19711 output_bfd,
2dcf00ce
AM		 19712 (uint64_t) (stm32l4xx_errnode->vma - 4),
19713 (int64_t) out_of_range);
a504d23a
LA		 19714 continue;
19715 }
19716
19717 insn = create_instruction_branch_absolute
82188b29 19718 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19719
a2699ef2
AM		 19720 /* The instruction is before the label. */
19721 target -= 4;
19722
a504d23a
LA		 19723 put_thumb2_insn (globals, output_bfd,
19724 (bfd_vma) insn, contents + target);
19725 }
19726 break;
19727
19728 case STM32L4XX_ERRATUM_VENEER:
19729 {
82188b29
NC		 19730 bfd_byte * veneer;
19731 bfd_byte * veneer_r;
a504d23a
LA		 19732 unsigned int insn;
19733
82188b29
NC		 19734 veneer = contents + target;
19735 veneer_r = veneer
19736 + stm32l4xx_errnode->u.b.veneer->vma
19737 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19738
19739 if ((signed) (veneer_r - veneer -
19740 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19741 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19742 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19743 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19744 || (signed) (veneer_r - veneer) >= (1 << 24))
19745 {
90b6238f
AM		 19746 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19747 "veneer"), output_bfd);
a504d23a
LA		 19748 continue;
19749 }
19750
19751 /* Original instruction. */
19752 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19753
19754 stm32l4xx_create_replacing_stub
19755 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19756 }
19757 break;
19758
19759 default:
19760 abort ();
19761 }
19762 }
19763 }
19764
2468f9c9
PB		 19765 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19766 {
19767 arm_unwind_table_edit *edit_node
99059e56 19768 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19769 /* Now, sec->size is the size of the section we will write. The original
99059e56 19770 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19771 markers) was sec->rawsize. (This isn't the case if we perform no
19772 edits, then rawsize will be zero and we should use size). */
21d799b5 19773 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19774 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19775 unsigned int in_index, out_index;
19776 bfd_vma add_to_offsets = 0;
19777
19778 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19779 {
2468f9c9
PB		 19780 if (edit_node)
19781 {
19782 unsigned int edit_index = edit_node->index;
b38cadfb 19783
2468f9c9 19784 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19785 {
2468f9c9
PB		 19786 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19787 contents + in_index * 8, add_to_offsets);
19788 out_index++;
19789 in_index++;
19790 }
19791 else if (in_index == edit_index
19792 || (in_index * 8 >= input_size
19793 && edit_index == UINT_MAX))
99059e56 19794 {
2468f9c9
PB		 19795 switch (edit_node->type)
19796 {
19797 case DELETE_EXIDX_ENTRY:
19798 in_index++;
19799 add_to_offsets += 8;
19800 break;
b38cadfb 19801
2468f9c9
PB		 19802 case INSERT_EXIDX_CANTUNWIND_AT_END:
19803 {
99059e56 19804 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19805 bfd_vma text_offset = text_sec->output_section->vma
19806 + text_sec->output_offset
19807 + text_sec->size;
19808 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19809 unsigned long prel31_offset;
2468f9c9
PB		 19810
19811 /* Note: this is meant to be equivalent to an
19812 R_ARM_PREL31 relocation. These synthetic
19813 EXIDX_CANTUNWIND markers are not relocated by the
19814 usual BFD method. */
19815 prel31_offset = (text_offset - exidx_offset)
19816 & 0x7ffffffful;
491d01d3
YU		 19817 if (bfd_link_relocatable (link_info))
19818 {
19819 /* Here relocation for new EXIDX_CANTUNWIND is
19820 created, so there is no need to
19821 adjust offset by hand. */
19822 prel31_offset = text_sec->output_offset
19823 + text_sec->size;
491d01d3 19824 }
2468f9c9
PB		 19825
19826 /* First address we can't unwind. */
19827 bfd_put_32 (output_bfd, prel31_offset,
19828 &edited_contents[out_index * 8]);
19829
19830 /* Code for EXIDX_CANTUNWIND. */
19831 bfd_put_32 (output_bfd, 0x1,
19832 &edited_contents[out_index * 8 + 4]);
19833
19834 out_index++;
19835 add_to_offsets -= 8;
19836 }
19837 break;
19838 }
b38cadfb 19839
2468f9c9
PB		 19840 edit_node = edit_node->next;
19841 }
19842 }
19843 else
19844 {
19845 /* No more edits, copy remaining entries verbatim. */
19846 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19847 contents + in_index * 8, add_to_offsets);
19848 out_index++;
19849 in_index++;
19850 }
19851 }
19852
19853 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19854 bfd_set_section_contents (output_bfd, sec->output_section,
19855 edited_contents,
19856 (file_ptr) sec->output_offset, sec->size);
19857
19858 return TRUE;
19859 }
19860
48229727
JB		 19861 /* Fix code to point to Cortex-A8 erratum stubs. */
19862 if (globals->fix_cortex_a8)
19863 {
19864 struct a8_branch_to_stub_data data;
19865
19866 data.writing_section = sec;
19867 data.contents = contents;
19868
a504d23a
LA		 19869 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19870 & data);
48229727
JB		 19871 }
19872
e489d0ae
PB		 19873 if (mapcount == 0)
19874 return FALSE;
19875
c7b8f16e 19876 if (globals->byteswap_code)
e489d0ae 19877 {
c7b8f16e 19878 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19879
c7b8f16e
JB		 19880 ptr = map[0].vma;
19881 for (i = 0; i < mapcount; i++)
99059e56
RM		 19882 {
19883 if (i == mapcount - 1)
c7b8f16e 19884 end = sec->size;
99059e56
RM		 19885 else
19886 end = map[i + 1].vma;
e489d0ae 19887
99059e56 19888 switch (map[i].type)
e489d0ae 19889 {
c7b8f16e
JB		 19890 case 'a':
19891 /* Byte swap code words. */
19892 while (ptr + 3 < end)
99059e56
RM		 19893 {
19894 tmp = contents[ptr];
19895 contents[ptr] = contents[ptr + 3];
19896 contents[ptr + 3] = tmp;
19897 tmp = contents[ptr + 1];
19898 contents[ptr + 1] = contents[ptr + 2];
19899 contents[ptr + 2] = tmp;
19900 ptr += 4;
19901 }
c7b8f16e 19902 break;
e489d0ae 19903
c7b8f16e
JB		 19904 case 't':
19905 /* Byte swap code halfwords. */
19906 while (ptr + 1 < end)
99059e56
RM		 19907 {
19908 tmp = contents[ptr];
19909 contents[ptr] = contents[ptr + 1];
19910 contents[ptr + 1] = tmp;
19911 ptr += 2;
19912 }
c7b8f16e
JB		 19913 break;
19914
19915 case 'd':
19916 /* Leave data alone. */
19917 break;
19918 }
99059e56
RM		 19919 ptr = end;
19920 }
e489d0ae 19921 }
8e3de13a 19922
93204d3a 19923 free (map);
47b2e99c 19924 arm_data->mapcount = -1;
c7b8f16e 19925 arm_data->mapsize = 0;
8e3de13a 19926 arm_data->map = NULL;
8e3de13a 19927
e489d0ae
PB		 19928 return FALSE;
19929}
19930
0beaef2b
PB		 19931/* Mangle thumb function symbols as we read them in. */
19932
8384fb8f 19933static bfd_boolean
0beaef2b
PB		 19934elf32_arm_swap_symbol_in (bfd * abfd,
19935 const void *psrc,
19936 const void *pshn,
19937 Elf_Internal_Sym *dst)
19938{
4ba2ef8f
TP		 19939 Elf_Internal_Shdr *symtab_hdr;
19940 const char *name = NULL;
19941
8384fb8f
AM		 19942 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19943 return FALSE;
39d911fc 19944 dst->st_target_internal = 0;
0beaef2b
PB		 19945
19946 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19947 the address. */
63e1a0fc
PB		 19948 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19949 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19950 {
63e1a0fc
PB		 19951 if (dst->st_value & 1)
19952 {
19953 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19954 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19955 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19956 }
19957 else
39d911fc 19958 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19959 }
19960 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19961 {
19962 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19963 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19964 }
35fc36a8 19965 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19966 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19967 else
39d911fc 19968 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19969
4ba2ef8f
TP		 19970 /* Mark CMSE special symbols. */
19971 symtab_hdr = & elf_symtab_hdr (abfd);
19972 if (symtab_hdr->sh_size)
19973 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
19974 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
19975 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
19976
8384fb8f 19977 return TRUE;
0beaef2b
PB		 19978}
19979
19980
19981/* Mangle thumb function symbols as we write them out. */
19982
19983static void
19984elf32_arm_swap_symbol_out (bfd *abfd,
19985 const Elf_Internal_Sym *src,
19986 void *cdst,
19987 void *shndx)
19988{
19989 Elf_Internal_Sym newsym;
19990
19991 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19992 of the address set, as per the new EABI. We do this unconditionally
19993 because objcopy does not set the elf header flags until after
19994 it writes out the symbol table. */
39d911fc 19995 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19996 {
19997 newsym = *src;
34e77a92
RS		 19998 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19999 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 20000 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 20001 {
20002 /* Do this only for defined symbols. At link type, the static
20003 linker will simulate the work of dynamic linker of resolving
20004 symbols and will carry over the thumbness of found symbols to
20005 the output symbol table. It's not clear how it happens, but
20006 the thumbness of undefined symbols can well be different at
20007 runtime, and writing '1' for them will be confusing for users
20008 and possibly for dynamic linker itself.
20009 */
20010 newsym.st_value |= 1;
20011 }
906e58ca 20012
0beaef2b
PB		 20013 src = &newsym;
20014 }
20015 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
20016}
20017
b294bdf8
MM		 20018/* Add the PT_ARM_EXIDX program header. */
20019
20020static bfd_boolean
906e58ca 20021elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 20022 struct bfd_link_info *info ATTRIBUTE_UNUSED)
20023{
20024 struct elf_segment_map *m;
20025 asection *sec;
20026
20027 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20028 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20029 {
20030 /* If there is already a PT_ARM_EXIDX header, then we do not
20031 want to add another one. This situation arises when running
20032 "strip"; the input binary already has the header. */
12bd6957 20033 m = elf_seg_map (abfd);
b294bdf8
MM		 20034 while (m && m->p_type != PT_ARM_EXIDX)
20035 m = m->next;
20036 if (!m)
20037 {
21d799b5 20038 m = (struct elf_segment_map *)
99059e56 20039 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 20040 if (m == NULL)
20041 return FALSE;
20042 m->p_type = PT_ARM_EXIDX;
20043 m->count = 1;
20044 m->sections[0] = sec;
20045
12bd6957
AM		 20046 m->next = elf_seg_map (abfd);
20047 elf_seg_map (abfd) = m;
b294bdf8
MM		 20048 }
20049 }
20050
20051 return TRUE;
20052}
20053
20054/* We may add a PT_ARM_EXIDX program header. */
20055
20056static int
a6b96beb
AM		 20057elf32_arm_additional_program_headers (bfd *abfd,
20058 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 20059{
20060 asection *sec;
20061
20062 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20063 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20064 return 1;
20065 else
20066 return 0;
20067}
20068
34e77a92
RS		 20069/* Hook called by the linker routine which adds symbols from an object
20070 file. */
20071
20072static bfd_boolean
20073elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
20074 Elf_Internal_Sym *sym, const char **namep,
20075 flagword *flagsp, asection **secp, bfd_vma *valp)
20076{
c792917c
NC		 20077 if (elf32_arm_hash_table (info) == NULL)
20078 return FALSE;
20079
34e77a92
RS		 20080 if (elf32_arm_hash_table (info)->vxworks_p
20081 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
20082 flagsp, secp, valp))
20083 return FALSE;
20084
20085 return TRUE;
20086}
20087
0beaef2b 20088/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 20089const struct elf_size_info elf32_arm_size_info =
20090{
0beaef2b
PB		 20091 sizeof (Elf32_External_Ehdr),
20092 sizeof (Elf32_External_Phdr),
20093 sizeof (Elf32_External_Shdr),
20094 sizeof (Elf32_External_Rel),
20095 sizeof (Elf32_External_Rela),
20096 sizeof (Elf32_External_Sym),
20097 sizeof (Elf32_External_Dyn),
20098 sizeof (Elf_External_Note),
20099 4,
20100 1,
20101 32, 2,
20102 ELFCLASS32, EV_CURRENT,
20103 bfd_elf32_write_out_phdrs,
20104 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 20105 bfd_elf32_checksum_contents,
0beaef2b
PB		 20106 bfd_elf32_write_relocs,
20107 elf32_arm_swap_symbol_in,
20108 elf32_arm_swap_symbol_out,
20109 bfd_elf32_slurp_reloc_table,
20110 bfd_elf32_slurp_symbol_table,
20111 bfd_elf32_swap_dyn_in,
20112 bfd_elf32_swap_dyn_out,
20113 bfd_elf32_swap_reloc_in,
20114 bfd_elf32_swap_reloc_out,
20115 bfd_elf32_swap_reloca_in,
20116 bfd_elf32_swap_reloca_out
20117};
20118
685e70ae
VK		 20119static bfd_vma
20120read_code32 (const bfd *abfd, const bfd_byte *addr)
20121{
20122 /* V7 BE8 code is always little endian. */
20123 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20124 return bfd_getl32 (addr);
20125
20126 return bfd_get_32 (abfd, addr);
20127}
20128
20129static bfd_vma
20130read_code16 (const bfd *abfd, const bfd_byte *addr)
20131{
20132 /* V7 BE8 code is always little endian. */
20133 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20134 return bfd_getl16 (addr);
20135
20136 return bfd_get_16 (abfd, addr);
20137}
20138
6a631e86
YG		 20139/* Return size of plt0 entry starting at ADDR
20140 or (bfd_vma) -1 if size can not be determined. */
20141
20142static bfd_vma
20143elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
20144{
20145 bfd_vma first_word;
20146 bfd_vma plt0_size;
20147
685e70ae 20148 first_word = read_code32 (abfd, addr);
6a631e86
YG		 20149
20150 if (first_word == elf32_arm_plt0_entry[0])
20151 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
20152 else if (first_word == elf32_thumb2_plt0_entry[0])
20153 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
20154 else
20155 /* We don't yet handle this PLT format. */
20156 return (bfd_vma) -1;
20157
20158 return plt0_size;
20159}
20160
20161/* Return size of plt entry starting at offset OFFSET
20162 of plt section located at address START
20163 or (bfd_vma) -1 if size can not be determined. */
20164
20165static bfd_vma
20166elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
20167{
20168 bfd_vma first_insn;
20169 bfd_vma plt_size = 0;
20170 const bfd_byte *addr = start + offset;
20171
20172 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 20173 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 20174 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
20175
20176 /* Respect Thumb stub if necessary. */
685e70ae 20177 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 20178 {
20179 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
20180 }
20181
20182 /* Strip immediate from first add. */
685e70ae 20183 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 20184
20185#ifdef FOUR_WORD_PLT
20186 if (first_insn == elf32_arm_plt_entry[0])
20187 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20188#else
20189 if (first_insn == elf32_arm_plt_entry_long[0])
20190 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20191 else if (first_insn == elf32_arm_plt_entry_short[0])
20192 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20193#endif
20194 else
20195 /* We don't yet handle this PLT format. */
20196 return (bfd_vma) -1;
20197
20198 return plt_size;
20199}
20200
20201/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20202
20203static long
20204elf32_arm_get_synthetic_symtab (bfd *abfd,
20205 long symcount ATTRIBUTE_UNUSED,
20206 asymbol **syms ATTRIBUTE_UNUSED,
20207 long dynsymcount,
20208 asymbol **dynsyms,
20209 asymbol **ret)
20210{
20211 asection *relplt;
20212 asymbol *s;
20213 arelent *p;
20214 long count, i, n;
20215 size_t size;
20216 Elf_Internal_Shdr *hdr;
20217 char *names;
20218 asection *plt;
20219 bfd_vma offset;
20220 bfd_byte *data;
20221
20222 *ret = NULL;
20223
20224 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20225 return 0;
20226
20227 if (dynsymcount <= 0)
20228 return 0;
20229
20230 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20231 if (relplt == NULL)
20232 return 0;
20233
20234 hdr = &elf_section_data (relplt)->this_hdr;
20235 if (hdr->sh_link != elf_dynsymtab (abfd)
20236 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20237 return 0;
20238
20239 plt = bfd_get_section_by_name (abfd, ".plt");
20240 if (plt == NULL)
20241 return 0;
20242
20243 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20244 return -1;
20245
20246 data = plt->contents;
20247 if (data == NULL)
20248 {
20249 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20250 return -1;
20251 bfd_cache_section_contents((asection *) plt, data);
20252 }
20253
20254 count = relplt->size / hdr->sh_entsize;
20255 size = count * sizeof (asymbol);
20256 p = relplt->relocation;
20257 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20258 {
20259 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20260 if (p->addend != 0)
20261 size += sizeof ("+0x") - 1 + 8;
20262 }
20263
20264 s = *ret = (asymbol *) bfd_malloc (size);
20265 if (s == NULL)
20266 return -1;
20267
20268 offset = elf32_arm_plt0_size (abfd, data);
20269 if (offset == (bfd_vma) -1)
20270 return -1;
20271
20272 names = (char *) (s + count);
20273 p = relplt->relocation;
20274 n = 0;
20275 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20276 {
20277 size_t len;
20278
20279 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20280 if (plt_size == (bfd_vma) -1)
20281 break;
20282
20283 *s = **p->sym_ptr_ptr;
20284 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20285 we are defining a symbol, ensure one of them is set. */
20286 if ((s->flags & BSF_LOCAL) == 0)
20287 s->flags |= BSF_GLOBAL;
20288 s->flags |= BSF_SYNTHETIC;
20289 s->section = plt;
20290 s->value = offset;
20291 s->name = names;
20292 s->udata.p = NULL;
20293 len = strlen ((*p->sym_ptr_ptr)->name);
20294 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20295 names += len;
20296 if (p->addend != 0)
20297 {
20298 char buf[30], *a;
20299
20300 memcpy (names, "+0x", sizeof ("+0x") - 1);
20301 names += sizeof ("+0x") - 1;
20302 bfd_sprintf_vma (abfd, buf, p->addend);
20303 for (a = buf; *a == '0'; ++a)
20304 ;
20305 len = strlen (a);
20306 memcpy (names, a, len);
20307 names += len;
20308 }
20309 memcpy (names, "@plt", sizeof ("@plt"));
20310 names += sizeof ("@plt");
20311 ++s, ++n;
20312 offset += plt_size;
20313 }
20314
20315 return n;
20316}
20317
ac4c9b04
MG		 20318static bfd_boolean
20319elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
20320{
f0728ee3
AV		 20321 if (hdr->sh_flags & SHF_ARM_PURECODE)
20322 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20323 return TRUE;
20324}
20325
20326static flagword
20327elf32_arm_lookup_section_flags (char *flag_name)
20328{
f0728ee3
AV		 20329 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20330 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20331
20332 return SEC_NO_FLAGS;
20333}
20334
491d01d3
YU		 20335static unsigned int
20336elf32_arm_count_additional_relocs (asection *sec)
20337{
20338 struct _arm_elf_section_data *arm_data;
20339 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20340
6342be70 20341 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20342}
20343
5522f910 20344/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20345 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20346 FALSE otherwise. ISECTION is the best guess matching section from the
20347 input bfd IBFD, but it might be NULL. */
20348
20349static bfd_boolean
20350elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20351 bfd *obfd ATTRIBUTE_UNUSED,
20352 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20353 Elf_Internal_Shdr *osection)
20354{
20355 switch (osection->sh_type)
20356 {
20357 case SHT_ARM_EXIDX:
20358 {
20359 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20360 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20361 unsigned i = 0;
20362
20363 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20364 osection->sh_info = 0;
20365
20366 /* The sh_link field must be set to the text section associated with
20367 this index section. Unfortunately the ARM EHABI does not specify
20368 exactly how to determine this association. Our caller does try
20369 to match up OSECTION with its corresponding input section however
20370 so that is a good first guess. */
20371 if (isection != NULL
20372 && osection->bfd_section != NULL
20373 && isection->bfd_section != NULL
20374 && isection->bfd_section->output_section != NULL
20375 && isection->bfd_section->output_section == osection->bfd_section
20376 && iheaders != NULL
20377 && isection->sh_link > 0
20378 && isection->sh_link < elf_numsections (ibfd)
20379 && iheaders[isection->sh_link]->bfd_section != NULL
20380 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20381 )
20382 {
20383 for (i = elf_numsections (obfd); i-- > 0;)
20384 if (oheaders[i]->bfd_section
20385 == iheaders[isection->sh_link]->bfd_section->output_section)
20386 break;
20387 }
9eaff861 20388
5522f910
NC		 20389 if (i == 0)
20390 {
20391 /* Failing that we have to find a matching section ourselves. If
20392 we had the output section name available we could compare that
20393 with input section names. Unfortunately we don't. So instead
20394 we use a simple heuristic and look for the nearest executable
20395 section before this one. */
20396 for (i = elf_numsections (obfd); i-- > 0;)
20397 if (oheaders[i] == osection)
20398 break;
20399 if (i == 0)
20400 break;
20401
20402 while (i-- > 0)
20403 if (oheaders[i]->sh_type == SHT_PROGBITS
20404 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20405 == (SHF_ALLOC | SHF_EXECINSTR))
20406 break;
20407 }
20408
20409 if (i)
20410 {
20411 osection->sh_link = i;
20412 /* If the text section was part of a group
20413 then the index section should be too. */
20414 if (oheaders[i]->sh_flags & SHF_GROUP)
20415 osection->sh_flags |= SHF_GROUP;
20416 return TRUE;
20417 }
20418 }
20419 break;
20420
20421 case SHT_ARM_PREEMPTMAP:
20422 osection->sh_flags = SHF_ALLOC;
20423 break;
20424
20425 case SHT_ARM_ATTRIBUTES:
20426 case SHT_ARM_DEBUGOVERLAY:
20427 case SHT_ARM_OVERLAYSECTION:
20428 default:
20429 break;
20430 }
20431
20432 return FALSE;
20433}
20434
d691934d
NC		 20435/* Returns TRUE if NAME is an ARM mapping symbol.
20436 Traditionally the symbols $a, $d and $t have been used.
20437 The ARM ELF standard also defines $x (for A64 code). It also allows a
20438 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20439 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20440 not support them here. $t.x indicates the start of ThumbEE instructions. */
20441
20442static bfd_boolean
20443is_arm_mapping_symbol (const char * name)
20444{
20445 return name != NULL /* Paranoia. */
20446 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20447 the mapping symbols could have acquired a prefix.
20448 We do not support this here, since such symbols no
20449 longer conform to the ARM ELF ABI. */
20450 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20451 && (name[2] == 0 || name[2] == '.');
20452 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20453 any characters that follow the period are legal characters for the body
20454 of a symbol's name. For now we just assume that this is the case. */
20455}
20456
fca2a38f
NC		 20457/* Make sure that mapping symbols in object files are not removed via the
20458 "strip --strip-unneeded" tool. These symbols are needed in order to
20459 correctly generate interworking veneers, and for byte swapping code
20460 regions. Once an object file has been linked, it is safe to remove the
20461 symbols as they will no longer be needed. */
20462
20463static void
20464elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20465{
20466 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20467 && sym->section != bfd_abs_section_ptr
d691934d 20468 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20469 sym->flags |= BSF_KEEP;
20470}
20471
5522f910
NC		 20472#undef elf_backend_copy_special_section_fields
20473#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20474
252b5132 20475#define ELF_ARCH bfd_arch_arm
ae95ffa6 20476#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20477#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20478#ifdef __QNXTARGET__
20479#define ELF_MAXPAGESIZE 0x1000
20480#else
7572ca89 20481#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20482#endif
b1342370 20483#define ELF_MINPAGESIZE 0x1000
24718e3b 20484#define ELF_COMMONPAGESIZE 0x1000
252b5132 20485
07d6d2b8 20486#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20487
99e4ae17
AJ		 20488#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20489#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20490#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20491#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20492#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20493#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20494#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 20495#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20496#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20497#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20498#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20499#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20500#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20501
07d6d2b8
AM		 20502#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20503#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20504#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20505#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20506#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20507#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20508#define elf_backend_write_section elf32_arm_write_section
252b5132 20509#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20510#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20511#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20512#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20513#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20514#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20515#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 20516#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 20517#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20518#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20519#define elf_backend_fake_sections elf32_arm_fake_sections
20520#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20521#define elf_backend_final_write_processing elf32_arm_final_write_processing
20522#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20523#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20524#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20525#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20526#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20527#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20528#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20529#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20530#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20531#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20532
20533#define elf_backend_can_refcount 1
20534#define elf_backend_can_gc_sections 1
20535#define elf_backend_plt_readonly 1
20536#define elf_backend_want_got_plt 1
20537#define elf_backend_want_plt_sym 0
5474d94f 20538#define elf_backend_want_dynrelro 1
906e58ca
NC		 20539#define elf_backend_may_use_rel_p 1
20540#define elf_backend_may_use_rela_p 0
4e7fd91e 20541#define elf_backend_default_use_rela_p 0
64f52338 20542#define elf_backend_dtrel_excludes_plt 1
252b5132 20543
04f7c78d 20544#define elf_backend_got_header_size 12
b68a20d6 20545#define elf_backend_extern_protected_data 1
04f7c78d 20546
07d6d2b8 20547#undef elf_backend_obj_attrs_vendor
906e58ca 20548#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20549#undef elf_backend_obj_attrs_section
906e58ca 20550#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20551#undef elf_backend_obj_attrs_arg_type
906e58ca 20552#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20553#undef elf_backend_obj_attrs_section_type
104d59d1 20554#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20555#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20556#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20557
07d6d2b8 20558#undef elf_backend_section_flags
ac4c9b04 20559#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20560#undef elf_backend_lookup_section_flags_hook
20561#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20562
a2f63b2e
MR		 20563#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20564
252b5132 20565#include "elf32-target.h"
7f266840 20566
b38cadfb
NC		 20567/* Native Client targets. */
20568
20569#undef TARGET_LITTLE_SYM
6d00b590 20570#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20571#undef TARGET_LITTLE_NAME
20572#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20573#undef TARGET_BIG_SYM
6d00b590 20574#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20575#undef TARGET_BIG_NAME
20576#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20577
20578/* Like elf32_arm_link_hash_table_create -- but overrides
20579 appropriately for NaCl. */
20580
20581static struct bfd_link_hash_table *
20582elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20583{
20584 struct bfd_link_hash_table *ret;
20585
20586 ret = elf32_arm_link_hash_table_create (abfd);
20587 if (ret)
20588 {
20589 struct elf32_arm_link_hash_table *htab
20590 = (struct elf32_arm_link_hash_table *) ret;
20591
20592 htab->nacl_p = 1;
20593
20594 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20595 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20596 }
20597 return ret;
20598}
20599
20600/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20601 really need to use elf32_arm_modify_segment_map. But we do it
20602 anyway just to reduce gratuitous differences with the stock ARM backend. */
20603
20604static bfd_boolean
20605elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20606{
20607 return (elf32_arm_modify_segment_map (abfd, info)
20608 && nacl_modify_segment_map (abfd, info));
20609}
20610
887badb3
RM		 20611static void
20612elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
20613{
20614 elf32_arm_final_write_processing (abfd, linker);
20615 nacl_final_write_processing (abfd, linker);
20616}
20617
6a631e86
YG		 20618static bfd_vma
20619elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20620 const arelent *rel ATTRIBUTE_UNUSED)
20621{
20622 return plt->vma
20623 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20624 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20625}
887badb3 20626
b38cadfb 20627#undef elf32_bed
6a631e86 20628#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20629#undef bfd_elf32_bfd_link_hash_table_create
20630#define bfd_elf32_bfd_link_hash_table_create \
20631 elf32_arm_nacl_link_hash_table_create
20632#undef elf_backend_plt_alignment
6a631e86 20633#define elf_backend_plt_alignment 4
b38cadfb
NC		 20634#undef elf_backend_modify_segment_map
20635#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20636#undef elf_backend_modify_program_headers
20637#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 20638#undef elf_backend_final_write_processing
20639#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20640#undef bfd_elf32_get_synthetic_symtab
20641#undef elf_backend_plt_sym_val
20642#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20643#undef elf_backend_copy_special_section_fields
b38cadfb 20644
887badb3
RM		 20645#undef ELF_MINPAGESIZE
20646#undef ELF_COMMONPAGESIZE
20647
b38cadfb
NC		 20648
20649#include "elf32-target.h"
20650
20651/* Reset to defaults. */
20652#undef elf_backend_plt_alignment
20653#undef elf_backend_modify_segment_map
20654#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20655#undef elf_backend_modify_program_headers
887badb3
RM		 20656#undef elf_backend_final_write_processing
20657#define elf_backend_final_write_processing elf32_arm_final_write_processing
20658#undef ELF_MINPAGESIZE
20659#define ELF_MINPAGESIZE 0x1000
20660#undef ELF_COMMONPAGESIZE
20661#define ELF_COMMONPAGESIZE 0x1000
20662
b38cadfb 20663
617a5ada
CL		 20664/* FDPIC Targets. */
20665
20666#undef TARGET_LITTLE_SYM
20667#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20668#undef TARGET_LITTLE_NAME
20669#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20670#undef TARGET_BIG_SYM
20671#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20672#undef TARGET_BIG_NAME
20673#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20674#undef elf_match_priority
20675#define elf_match_priority 128
18a20338
CL		 20676#undef ELF_OSABI
20677#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20678
20679/* Like elf32_arm_link_hash_table_create -- but overrides
20680 appropriately for FDPIC. */
20681
20682static struct bfd_link_hash_table *
20683elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20684{
20685 struct bfd_link_hash_table *ret;
20686
20687 ret = elf32_arm_link_hash_table_create (abfd);
20688 if (ret)
20689 {
20690 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20691
20692 htab->fdpic_p = 1;
20693 }
20694 return ret;
20695}
20696
e8b09b87
CL		 20697/* We need dynamic symbols for every section, since segments can
20698 relocate independently. */
20699static bfd_boolean
20700elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20701 struct bfd_link_info *info
20702 ATTRIBUTE_UNUSED,
20703 asection *p ATTRIBUTE_UNUSED)
20704{
20705 switch (elf_section_data (p)->this_hdr.sh_type)
20706 {
20707 case SHT_PROGBITS:
20708 case SHT_NOBITS:
20709 /* If sh_type is yet undecided, assume it could be
20710 SHT_PROGBITS/SHT_NOBITS. */
20711 case SHT_NULL:
20712 return FALSE;
20713
20714 /* There shouldn't be section relative relocations
20715 against any other section. */
20716 default:
20717 return TRUE;
20718 }
20719}
20720
617a5ada
CL		 20721#undef elf32_bed
20722#define elf32_bed elf32_arm_fdpic_bed
20723
20724#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20725#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20726
e8b09b87
CL		 20727#undef elf_backend_omit_section_dynsym
20728#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20729
617a5ada 20730#include "elf32-target.h"
e8b09b87 20731
617a5ada 20732#undef elf_match_priority
18a20338 20733#undef ELF_OSABI
e8b09b87 20734#undef elf_backend_omit_section_dynsym
617a5ada 20735
906e58ca 20736/* VxWorks Targets. */
4e7fd91e 20737
07d6d2b8
AM		 20738#undef TARGET_LITTLE_SYM
20739#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20740#undef TARGET_LITTLE_NAME
20741#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20742#undef TARGET_BIG_SYM
20743#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20744#undef TARGET_BIG_NAME
20745#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20746
20747/* Like elf32_arm_link_hash_table_create -- but overrides
20748 appropriately for VxWorks. */
906e58ca 20749
4e7fd91e
PB		 20750static struct bfd_link_hash_table *
20751elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20752{
20753 struct bfd_link_hash_table *ret;
20754
20755 ret = elf32_arm_link_hash_table_create (abfd);
20756 if (ret)
20757 {
20758 struct elf32_arm_link_hash_table *htab
00a97672 20759 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20760 htab->use_rel = 0;
00a97672 20761 htab->vxworks_p = 1;
4e7fd91e
PB		 20762 }
20763 return ret;
906e58ca 20764}
4e7fd91e 20765
00a97672
RS		 20766static void
20767elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
20768{
20769 elf32_arm_final_write_processing (abfd, linker);
20770 elf_vxworks_final_write_processing (abfd, linker);
20771}
20772
906e58ca 20773#undef elf32_bed
4e7fd91e
PB		 20774#define elf32_bed elf32_arm_vxworks_bed
20775
906e58ca
NC		 20776#undef bfd_elf32_bfd_link_hash_table_create
20777#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20778#undef elf_backend_final_write_processing
20779#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20780#undef elf_backend_emit_relocs
9eaff861 20781#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20782
906e58ca 20783#undef elf_backend_may_use_rel_p
00a97672 20784#define elf_backend_may_use_rel_p 0
906e58ca 20785#undef elf_backend_may_use_rela_p
00a97672 20786#define elf_backend_may_use_rela_p 1
906e58ca 20787#undef elf_backend_default_use_rela_p
00a97672 20788#define elf_backend_default_use_rela_p 1
906e58ca 20789#undef elf_backend_want_plt_sym
00a97672 20790#define elf_backend_want_plt_sym 1
906e58ca 20791#undef ELF_MAXPAGESIZE
00a97672 20792#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20793
20794#include "elf32-target.h"
20795
20796
21d799b5
NC		 20797/* Merge backend specific data from an object file to the output
20798 object file when linking. */
20799
20800static bfd_boolean
50e03d47 20801elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20802{
50e03d47 20803 bfd *obfd = info->output_bfd;
21d799b5
NC		 20804 flagword out_flags;
20805 flagword in_flags;
20806 bfd_boolean flags_compatible = TRUE;
20807 asection *sec;
20808
cc643b88 20809 /* Check if we have the same endianness. */
50e03d47 20810 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20811 return FALSE;
20812
20813 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20814 return TRUE;
20815
50e03d47 20816 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20817 return FALSE;
20818
20819 /* The input BFD must have had its flags initialised. */
20820 /* The following seems bogus to me -- The flags are initialized in
20821 the assembler but I don't think an elf_flags_init field is
20822 written into the object. */
20823 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20824
20825 in_flags = elf_elfheader (ibfd)->e_flags;
20826 out_flags = elf_elfheader (obfd)->e_flags;
20827
20828 /* In theory there is no reason why we couldn't handle this. However
20829 in practice it isn't even close to working and there is no real
20830 reason to want it. */
20831 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20832 && !(ibfd->flags & DYNAMIC)
20833 && (in_flags & EF_ARM_BE8))
20834 {
871b3ab2 20835 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20836 ibfd);
20837 return FALSE;
20838 }
20839
20840 if (!elf_flags_init (obfd))
20841 {
20842 /* If the input is the default architecture and had the default
20843 flags then do not bother setting the flags for the output
20844 architecture, instead allow future merges to do this. If no
20845 future merges ever set these flags then they will retain their
99059e56
RM		 20846 uninitialised values, which surprise surprise, correspond
20847 to the default values. */
21d799b5
NC		 20848 if (bfd_get_arch_info (ibfd)->the_default
20849 && elf_elfheader (ibfd)->e_flags == 0)
20850 return TRUE;
20851
20852 elf_flags_init (obfd) = TRUE;
20853 elf_elfheader (obfd)->e_flags = in_flags;
20854
20855 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20856 && bfd_get_arch_info (obfd)->the_default)
20857 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20858
20859 return TRUE;
20860 }
20861
20862 /* Determine what should happen if the input ARM architecture
20863 does not match the output ARM architecture. */
20864 if (! bfd_arm_merge_machines (ibfd, obfd))
20865 return FALSE;
20866
20867 /* Identical flags must be compatible. */
20868 if (in_flags == out_flags)
20869 return TRUE;
20870
20871 /* Check to see if the input BFD actually contains any sections. If
20872 not, its flags may not have been initialised either, but it
20873 cannot actually cause any incompatiblity. Do not short-circuit
20874 dynamic objects; their section list may be emptied by
20875 elf_link_add_object_symbols.
20876
20877 Also check to see if there are no code sections in the input.
20878 In this case there is no need to check for code specific flags.
20879 XXX - do we need to worry about floating-point format compatability
20880 in data sections ? */
20881 if (!(ibfd->flags & DYNAMIC))
20882 {
20883 bfd_boolean null_input_bfd = TRUE;
20884 bfd_boolean only_data_sections = TRUE;
20885
20886 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20887 {
20888 /* Ignore synthetic glue sections. */
20889 if (strcmp (sec->name, ".glue_7")
20890 && strcmp (sec->name, ".glue_7t"))
20891 {
20892 if ((bfd_get_section_flags (ibfd, sec)
20893 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20894 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20895 only_data_sections = FALSE;
21d799b5
NC		 20896
20897 null_input_bfd = FALSE;
20898 break;
20899 }
20900 }
20901
20902 if (null_input_bfd || only_data_sections)
20903 return TRUE;
20904 }
20905
20906 /* Complain about various flag mismatches. */
20907 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20908 EF_ARM_EABI_VERSION (out_flags)))
20909 {
20910 _bfd_error_handler
90b6238f 20911 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20912 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20913 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20914 return FALSE;
20915 }
20916
20917 /* Not sure what needs to be checked for EABI versions >= 1. */
20918 /* VxWorks libraries do not use these flags. */
20919 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20920 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20921 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20922 {
20923 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20924 {
20925 _bfd_error_handler
871b3ab2 20926 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20927 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20928 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20929 flags_compatible = FALSE;
20930 }
20931
20932 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20933 {
20934 if (in_flags & EF_ARM_APCS_FLOAT)
20935 _bfd_error_handler
871b3ab2 20936 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20937 ibfd, obfd);
20938 else
20939 _bfd_error_handler
871b3ab2 20940 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20941 ibfd, obfd);
20942
20943 flags_compatible = FALSE;
20944 }
20945
20946 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20947 {
20948 if (in_flags & EF_ARM_VFP_FLOAT)
20949 _bfd_error_handler
90b6238f
AM		 20950 (_("error: %pB uses %s instructions, whereas %pB does not"),
20951 ibfd, "VFP", obfd);
21d799b5
NC		 20952 else
20953 _bfd_error_handler
90b6238f
AM		 20954 (_("error: %pB uses %s instructions, whereas %pB does not"),
20955 ibfd, "FPA", obfd);
21d799b5
NC		 20956
20957 flags_compatible = FALSE;
20958 }
20959
20960 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20961 {
20962 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20963 _bfd_error_handler
90b6238f
AM		 20964 (_("error: %pB uses %s instructions, whereas %pB does not"),
20965 ibfd, "Maverick", obfd);
21d799b5
NC		 20966 else
20967 _bfd_error_handler
90b6238f
AM		 20968 (_("error: %pB does not use %s instructions, whereas %pB does"),
20969 ibfd, "Maverick", obfd);
21d799b5
NC		 20970
20971 flags_compatible = FALSE;
20972 }
20973
20974#ifdef EF_ARM_SOFT_FLOAT
20975 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20976 {
20977 /* We can allow interworking between code that is VFP format
20978 layout, and uses either soft float or integer regs for
20979 passing floating point arguments and results. We already
20980 know that the APCS_FLOAT flags match; similarly for VFP
20981 flags. */
20982 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20983 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20984 {
20985 if (in_flags & EF_ARM_SOFT_FLOAT)
20986 _bfd_error_handler
871b3ab2 20987 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20988 ibfd, obfd);
20989 else
20990 _bfd_error_handler
871b3ab2 20991 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20992 ibfd, obfd);
20993
20994 flags_compatible = FALSE;
20995 }
20996 }
20997#endif
20998
20999 /* Interworking mismatch is only a warning. */
21000 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
21001 {
21002 if (in_flags & EF_ARM_INTERWORK)
21003 {
21004 _bfd_error_handler
90b6238f 21005 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 21006 ibfd, obfd);
21007 }
21008 else
21009 {
21010 _bfd_error_handler
90b6238f 21011 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 21012 ibfd, obfd);
21013 }
21014 }
21015 }
21016
21017 return flags_compatible;
21018}
21019
21020
906e58ca 21021/* Symbian OS Targets. */
7f266840 21022
07d6d2b8
AM		 21023#undef TARGET_LITTLE_SYM
21024#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
21025#undef TARGET_LITTLE_NAME
21026#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
21027#undef TARGET_BIG_SYM
21028#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
21029#undef TARGET_BIG_NAME
21030#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 21031
21032/* Like elf32_arm_link_hash_table_create -- but overrides
21033 appropriately for Symbian OS. */
906e58ca 21034
7f266840
DJ		 21035static struct bfd_link_hash_table *
21036elf32_arm_symbian_link_hash_table_create (bfd *abfd)
21037{
21038 struct bfd_link_hash_table *ret;
21039
21040 ret = elf32_arm_link_hash_table_create (abfd);
21041 if (ret)
21042 {
21043 struct elf32_arm_link_hash_table *htab
21044 = (struct elf32_arm_link_hash_table *)ret;
21045 /* There is no PLT header for Symbian OS. */
21046 htab->plt_header_size = 0;
95720a86
DJ		 21047 /* The PLT entries are each one instruction and one word. */
21048 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 21049 htab->symbian_p = 1;
33bfe774
JB		 21050 /* Symbian uses armv5t or above, so use_blx is always true. */
21051 htab->use_blx = 1;
67687978 21052 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 21053 }
21054 return ret;
906e58ca 21055}
7f266840 21056
b35d266b 21057static const struct bfd_elf_special_section
551b43fd 21058elf32_arm_symbian_special_sections[] =
7f266840 21059{
5cd3778d
MM		 21060 /* In a BPABI executable, the dynamic linking sections do not go in
21061 the loadable read-only segment. The post-linker may wish to
21062 refer to these sections, but they are not part of the final
21063 program image. */
07d6d2b8
AM		 21064 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
21065 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
21066 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
21067 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
21068 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 21069 /* These sections do not need to be writable as the SymbianOS
21070 postlinker will arrange things so that no dynamic relocation is
21071 required. */
07d6d2b8
AM		 21072 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
21073 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 21074 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 21075 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 21076};
21077
c3c76620 21078static void
906e58ca 21079elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 21080 struct bfd_link_info *link_info)
c3c76620
MM		 21081{
21082 /* BPABI objects are never loaded directly by an OS kernel; they are
21083 processed by a postlinker first, into an OS-specific format. If
21084 the D_PAGED bit is set on the file, BFD will align segments on
21085 page boundaries, so that an OS can directly map the file. With
21086 BPABI objects, that just results in wasted space. In addition,
21087 because we clear the D_PAGED bit, map_sections_to_segments will
21088 recognize that the program headers should not be mapped into any
21089 loadable segment. */
21090 abfd->flags &= ~D_PAGED;
906e58ca 21091 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 21092}
7f266840
DJ		 21093
21094static bfd_boolean
906e58ca 21095elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 21096 struct bfd_link_info *info)
7f266840
DJ		 21097{
21098 struct elf_segment_map *m;
21099 asection *dynsec;
21100
7f266840
DJ		 21101 /* BPABI shared libraries and executables should have a PT_DYNAMIC
21102 segment. However, because the .dynamic section is not marked
21103 with SEC_LOAD, the generic ELF code will not create such a
21104 segment. */
21105 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
21106 if (dynsec)
21107 {
12bd6957 21108 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 21109 if (m->p_type == PT_DYNAMIC)
21110 break;
21111
21112 if (m == NULL)
21113 {
21114 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 21115 m->next = elf_seg_map (abfd);
21116 elf_seg_map (abfd) = m;
8ded5a0f 21117 }
7f266840
DJ		 21118 }
21119
b294bdf8
MM		 21120 /* Also call the generic arm routine. */
21121 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 21122}
21123
95720a86
DJ		 21124/* Return address for Ith PLT stub in section PLT, for relocation REL
21125 or (bfd_vma) -1 if it should not be included. */
21126
21127static bfd_vma
21128elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
21129 const arelent *rel ATTRIBUTE_UNUSED)
21130{
21131 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
21132}
21133
8029a119 21134#undef elf32_bed
7f266840
DJ		 21135#define elf32_bed elf32_arm_symbian_bed
21136
21137/* The dynamic sections are not allocated on SymbianOS; the postlinker
21138 will process them and then discard them. */
906e58ca 21139#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 21140#define ELF_DYNAMIC_SEC_FLAGS \
21141 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
21142
9eaff861 21143#undef elf_backend_emit_relocs
c3c76620 21144
906e58ca
NC		 21145#undef bfd_elf32_bfd_link_hash_table_create
21146#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
21147#undef elf_backend_special_sections
07d6d2b8 21148#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 21149#undef elf_backend_begin_write_processing
21150#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
21151#undef elf_backend_final_write_processing
21152#define elf_backend_final_write_processing elf32_arm_final_write_processing
21153
21154#undef elf_backend_modify_segment_map
7f266840
DJ		 21155#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
21156
21157/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 21158#undef elf_backend_got_header_size
7f266840
DJ		 21159#define elf_backend_got_header_size 0
21160
21161/* Similarly, there is no .got.plt section. */
906e58ca 21162#undef elf_backend_want_got_plt
7f266840
DJ		 21163#define elf_backend_want_got_plt 0
21164
906e58ca 21165#undef elf_backend_plt_sym_val
95720a86
DJ		 21166#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21167
906e58ca 21168#undef elf_backend_may_use_rel_p
00a97672 21169#define elf_backend_may_use_rel_p 1
906e58ca 21170#undef elf_backend_may_use_rela_p
00a97672 21171#define elf_backend_may_use_rela_p 0
906e58ca 21172#undef elf_backend_default_use_rela_p
00a97672 21173#define elf_backend_default_use_rela_p 0
906e58ca 21174#undef elf_backend_want_plt_sym
00a97672 21175#define elf_backend_want_plt_sym 0
64f52338
AM		 21176#undef elf_backend_dtrel_excludes_plt
21177#define elf_backend_dtrel_excludes_plt 0
906e58ca 21178#undef ELF_MAXPAGESIZE
00a97672 21179#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 21180
7f266840 21181#include "elf32-target.h"
GDB Binutils - Deliverables
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