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gdb/riscv: Remove CSR feature file
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
b3adc24a 2 Copyright (C) 1998-2020 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
f37164d7
AM		 31#include "elf32-arm.h"
32#include "cpu-arm.h"
7f266840 33
00a97672
RS		 34/* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36#define RELOC_SECTION(HTAB, NAME) \
37 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
38
39/* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41#define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
45
46/* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48#define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
52
53/* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55#define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
59
f3185997 60#define elf_info_to_howto NULL
07d6d2b8 61#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 62
63#define ARM_ELF_ABI_VERSION 0
64#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65
79f08007
YZ		 66/* The Adjusted Place, as defined by AAELF. */
67#define Pa(X) ((X) & 0xfffffffc)
68
3e6b1042
DJ		 69static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
70 struct bfd_link_info *link_info,
71 asection *sec,
72 bfd_byte *contents);
73
7f266840
DJ		 74/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
77
c19d1205 78static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 79{
8029a119 80 /* No relocation. */
7f266840
DJ		 81 HOWTO (R_ARM_NONE, /* type */
82 0, /* rightshift */
6346d5ca 83 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 84 0, /* bitsize */
85 FALSE, /* pc_relative */
86 0, /* bitpos */
87 complain_overflow_dont,/* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_ARM_NONE", /* name */
90 FALSE, /* partial_inplace */
91 0, /* src_mask */
92 0, /* dst_mask */
93 FALSE), /* pcrel_offset */
94
95 HOWTO (R_ARM_PC24, /* type */
96 2, /* rightshift */
97 2, /* size (0 = byte, 1 = short, 2 = long) */
98 24, /* bitsize */
99 TRUE, /* pc_relative */
100 0, /* bitpos */
101 complain_overflow_signed,/* complain_on_overflow */
102 bfd_elf_generic_reloc, /* special_function */
103 "R_ARM_PC24", /* name */
104 FALSE, /* partial_inplace */
105 0x00ffffff, /* src_mask */
106 0x00ffffff, /* dst_mask */
107 TRUE), /* pcrel_offset */
108
109 /* 32 bit absolute */
110 HOWTO (R_ARM_ABS32, /* type */
111 0, /* rightshift */
112 2, /* size (0 = byte, 1 = short, 2 = long) */
113 32, /* bitsize */
114 FALSE, /* pc_relative */
115 0, /* bitpos */
116 complain_overflow_bitfield,/* complain_on_overflow */
117 bfd_elf_generic_reloc, /* special_function */
118 "R_ARM_ABS32", /* name */
119 FALSE, /* partial_inplace */
120 0xffffffff, /* src_mask */
121 0xffffffff, /* dst_mask */
122 FALSE), /* pcrel_offset */
123
124 /* standard 32bit pc-relative reloc */
125 HOWTO (R_ARM_REL32, /* type */
126 0, /* rightshift */
127 2, /* size (0 = byte, 1 = short, 2 = long) */
128 32, /* bitsize */
129 TRUE, /* pc_relative */
130 0, /* bitpos */
131 complain_overflow_bitfield,/* complain_on_overflow */
132 bfd_elf_generic_reloc, /* special_function */
133 "R_ARM_REL32", /* name */
134 FALSE, /* partial_inplace */
135 0xffffffff, /* src_mask */
136 0xffffffff, /* dst_mask */
137 TRUE), /* pcrel_offset */
138
c19d1205 139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 140 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 141 0, /* rightshift */
142 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 143 32, /* bitsize */
144 TRUE, /* pc_relative */
7f266840 145 0, /* bitpos */
4962c51a 146 complain_overflow_dont,/* complain_on_overflow */
7f266840 147 bfd_elf_generic_reloc, /* special_function */
4962c51a 148 "R_ARM_LDR_PC_G0", /* name */
7f266840 149 FALSE, /* partial_inplace */
4962c51a
MS		 150 0xffffffff, /* src_mask */
151 0xffffffff, /* dst_mask */
152 TRUE), /* pcrel_offset */
7f266840
DJ		 153
154 /* 16 bit absolute */
155 HOWTO (R_ARM_ABS16, /* type */
156 0, /* rightshift */
157 1, /* size (0 = byte, 1 = short, 2 = long) */
158 16, /* bitsize */
159 FALSE, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield,/* complain_on_overflow */
162 bfd_elf_generic_reloc, /* special_function */
163 "R_ARM_ABS16", /* name */
164 FALSE, /* partial_inplace */
165 0x0000ffff, /* src_mask */
166 0x0000ffff, /* dst_mask */
167 FALSE), /* pcrel_offset */
168
169 /* 12 bit absolute */
170 HOWTO (R_ARM_ABS12, /* type */
171 0, /* rightshift */
172 2, /* size (0 = byte, 1 = short, 2 = long) */
173 12, /* bitsize */
174 FALSE, /* pc_relative */
175 0, /* bitpos */
176 complain_overflow_bitfield,/* complain_on_overflow */
177 bfd_elf_generic_reloc, /* special_function */
178 "R_ARM_ABS12", /* name */
179 FALSE, /* partial_inplace */
00a97672
RS		 180 0x00000fff, /* src_mask */
181 0x00000fff, /* dst_mask */
7f266840
DJ		 182 FALSE), /* pcrel_offset */
183
184 HOWTO (R_ARM_THM_ABS5, /* type */
185 6, /* rightshift */
186 1, /* size (0 = byte, 1 = short, 2 = long) */
187 5, /* bitsize */
188 FALSE, /* pc_relative */
189 0, /* bitpos */
190 complain_overflow_bitfield,/* complain_on_overflow */
191 bfd_elf_generic_reloc, /* special_function */
192 "R_ARM_THM_ABS5", /* name */
193 FALSE, /* partial_inplace */
194 0x000007e0, /* src_mask */
195 0x000007e0, /* dst_mask */
196 FALSE), /* pcrel_offset */
197
198 /* 8 bit absolute */
199 HOWTO (R_ARM_ABS8, /* type */
200 0, /* rightshift */
201 0, /* size (0 = byte, 1 = short, 2 = long) */
202 8, /* bitsize */
203 FALSE, /* pc_relative */
204 0, /* bitpos */
205 complain_overflow_bitfield,/* complain_on_overflow */
206 bfd_elf_generic_reloc, /* special_function */
207 "R_ARM_ABS8", /* name */
208 FALSE, /* partial_inplace */
209 0x000000ff, /* src_mask */
210 0x000000ff, /* dst_mask */
211 FALSE), /* pcrel_offset */
212
213 HOWTO (R_ARM_SBREL32, /* type */
214 0, /* rightshift */
215 2, /* size (0 = byte, 1 = short, 2 = long) */
216 32, /* bitsize */
217 FALSE, /* pc_relative */
218 0, /* bitpos */
219 complain_overflow_dont,/* complain_on_overflow */
220 bfd_elf_generic_reloc, /* special_function */
221 "R_ARM_SBREL32", /* name */
222 FALSE, /* partial_inplace */
223 0xffffffff, /* src_mask */
224 0xffffffff, /* dst_mask */
225 FALSE), /* pcrel_offset */
226
c19d1205 227 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 228 1, /* rightshift */
229 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 230 24, /* bitsize */
7f266840
DJ		 231 TRUE, /* pc_relative */
232 0, /* bitpos */
233 complain_overflow_signed,/* complain_on_overflow */
234 bfd_elf_generic_reloc, /* special_function */
c19d1205 235 "R_ARM_THM_CALL", /* name */
7f266840 236 FALSE, /* partial_inplace */
7f6ab9f8
AM		 237 0x07ff2fff, /* src_mask */
238 0x07ff2fff, /* dst_mask */
7f266840
DJ		 239 TRUE), /* pcrel_offset */
240
07d6d2b8 241 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 242 1, /* rightshift */
243 1, /* size (0 = byte, 1 = short, 2 = long) */
244 8, /* bitsize */
245 TRUE, /* pc_relative */
246 0, /* bitpos */
247 complain_overflow_signed,/* complain_on_overflow */
248 bfd_elf_generic_reloc, /* special_function */
249 "R_ARM_THM_PC8", /* name */
250 FALSE, /* partial_inplace */
251 0x000000ff, /* src_mask */
252 0x000000ff, /* dst_mask */
253 TRUE), /* pcrel_offset */
254
c19d1205 255 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 256 1, /* rightshift */
257 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 258 32, /* bitsize */
259 FALSE, /* pc_relative */
7f266840
DJ		 260 0, /* bitpos */
261 complain_overflow_signed,/* complain_on_overflow */
262 bfd_elf_generic_reloc, /* special_function */
c19d1205 263 "R_ARM_BREL_ADJ", /* name */
7f266840 264 FALSE, /* partial_inplace */
c19d1205
ZW		 265 0xffffffff, /* src_mask */
266 0xffffffff, /* dst_mask */
267 FALSE), /* pcrel_offset */
7f266840 268
0855e32b 269 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 270 0, /* rightshift */
0855e32b
NS		 271 2, /* size (0 = byte, 1 = short, 2 = long) */
272 32, /* bitsize */
7f266840
DJ		 273 FALSE, /* pc_relative */
274 0, /* bitpos */
0855e32b 275 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 276 bfd_elf_generic_reloc, /* special_function */
0855e32b 277 "R_ARM_TLS_DESC", /* name */
7f266840 278 FALSE, /* partial_inplace */
0855e32b
NS		 279 0xffffffff, /* src_mask */
280 0xffffffff, /* dst_mask */
7f266840
DJ		 281 FALSE), /* pcrel_offset */
282
283 HOWTO (R_ARM_THM_SWI8, /* type */
284 0, /* rightshift */
285 0, /* size (0 = byte, 1 = short, 2 = long) */
286 0, /* bitsize */
287 FALSE, /* pc_relative */
288 0, /* bitpos */
289 complain_overflow_signed,/* complain_on_overflow */
290 bfd_elf_generic_reloc, /* special_function */
291 "R_ARM_SWI8", /* name */
292 FALSE, /* partial_inplace */
293 0x00000000, /* src_mask */
294 0x00000000, /* dst_mask */
295 FALSE), /* pcrel_offset */
296
297 /* BLX instruction for the ARM. */
298 HOWTO (R_ARM_XPC25, /* type */
299 2, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 301 24, /* bitsize */
7f266840
DJ		 302 TRUE, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_signed,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_ARM_XPC25", /* name */
307 FALSE, /* partial_inplace */
308 0x00ffffff, /* src_mask */
309 0x00ffffff, /* dst_mask */
310 TRUE), /* pcrel_offset */
311
312 /* BLX instruction for the Thumb. */
313 HOWTO (R_ARM_THM_XPC22, /* type */
314 2, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 316 24, /* bitsize */
7f266840
DJ		 317 TRUE, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_signed,/* complain_on_overflow */
320 bfd_elf_generic_reloc, /* special_function */
321 "R_ARM_THM_XPC22", /* name */
322 FALSE, /* partial_inplace */
7f6ab9f8
AM		 323 0x07ff2fff, /* src_mask */
324 0x07ff2fff, /* dst_mask */
7f266840
DJ		 325 TRUE), /* pcrel_offset */
326
ba93b8ac 327 /* Dynamic TLS relocations. */
7f266840 328
ba93b8ac 329 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 330 0, /* rightshift */
331 2, /* size (0 = byte, 1 = short, 2 = long) */
332 32, /* bitsize */
333 FALSE, /* pc_relative */
334 0, /* bitpos */
99059e56
RM		 335 complain_overflow_bitfield,/* complain_on_overflow */
336 bfd_elf_generic_reloc, /* special_function */
337 "R_ARM_TLS_DTPMOD32", /* name */
338 TRUE, /* partial_inplace */
339 0xffffffff, /* src_mask */
340 0xffffffff, /* dst_mask */
07d6d2b8 341 FALSE), /* pcrel_offset */
7f266840 342
ba93b8ac 343 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 344 0, /* rightshift */
345 2, /* size (0 = byte, 1 = short, 2 = long) */
346 32, /* bitsize */
347 FALSE, /* pc_relative */
348 0, /* bitpos */
99059e56
RM		 349 complain_overflow_bitfield,/* complain_on_overflow */
350 bfd_elf_generic_reloc, /* special_function */
351 "R_ARM_TLS_DTPOFF32", /* name */
352 TRUE, /* partial_inplace */
353 0xffffffff, /* src_mask */
354 0xffffffff, /* dst_mask */
07d6d2b8 355 FALSE), /* pcrel_offset */
7f266840 356
ba93b8ac 357 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 358 0, /* rightshift */
359 2, /* size (0 = byte, 1 = short, 2 = long) */
360 32, /* bitsize */
361 FALSE, /* pc_relative */
362 0, /* bitpos */
99059e56
RM		 363 complain_overflow_bitfield,/* complain_on_overflow */
364 bfd_elf_generic_reloc, /* special_function */
365 "R_ARM_TLS_TPOFF32", /* name */
366 TRUE, /* partial_inplace */
367 0xffffffff, /* src_mask */
368 0xffffffff, /* dst_mask */
07d6d2b8 369 FALSE), /* pcrel_offset */
7f266840
DJ		 370
371 /* Relocs used in ARM Linux */
372
373 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 374 0, /* rightshift */
375 2, /* size (0 = byte, 1 = short, 2 = long) */
376 32, /* bitsize */
377 FALSE, /* pc_relative */
378 0, /* bitpos */
99059e56
RM		 379 complain_overflow_bitfield,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_ARM_COPY", /* name */
382 TRUE, /* partial_inplace */
383 0xffffffff, /* src_mask */
384 0xffffffff, /* dst_mask */
07d6d2b8 385 FALSE), /* pcrel_offset */
7f266840
DJ		 386
387 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 388 0, /* rightshift */
389 2, /* size (0 = byte, 1 = short, 2 = long) */
390 32, /* bitsize */
391 FALSE, /* pc_relative */
392 0, /* bitpos */
99059e56
RM		 393 complain_overflow_bitfield,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_ARM_GLOB_DAT", /* name */
396 TRUE, /* partial_inplace */
397 0xffffffff, /* src_mask */
398 0xffffffff, /* dst_mask */
07d6d2b8 399 FALSE), /* pcrel_offset */
7f266840
DJ		 400
401 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 402 0, /* rightshift */
403 2, /* size (0 = byte, 1 = short, 2 = long) */
404 32, /* bitsize */
405 FALSE, /* pc_relative */
406 0, /* bitpos */
99059e56
RM		 407 complain_overflow_bitfield,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_ARM_JUMP_SLOT", /* name */
410 TRUE, /* partial_inplace */
411 0xffffffff, /* src_mask */
412 0xffffffff, /* dst_mask */
07d6d2b8 413 FALSE), /* pcrel_offset */
7f266840
DJ		 414
415 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 416 0, /* rightshift */
417 2, /* size (0 = byte, 1 = short, 2 = long) */
418 32, /* bitsize */
419 FALSE, /* pc_relative */
420 0, /* bitpos */
99059e56
RM		 421 complain_overflow_bitfield,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_ARM_RELATIVE", /* name */
424 TRUE, /* partial_inplace */
425 0xffffffff, /* src_mask */
426 0xffffffff, /* dst_mask */
07d6d2b8 427 FALSE), /* pcrel_offset */
7f266840 428
c19d1205 429 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 430 0, /* rightshift */
431 2, /* size (0 = byte, 1 = short, 2 = long) */
432 32, /* bitsize */
433 FALSE, /* pc_relative */
434 0, /* bitpos */
99059e56
RM		 435 complain_overflow_bitfield,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_ARM_GOTOFF32", /* name */
438 TRUE, /* partial_inplace */
439 0xffffffff, /* src_mask */
440 0xffffffff, /* dst_mask */
07d6d2b8 441 FALSE), /* pcrel_offset */
7f266840
DJ		 442
443 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 444 0, /* rightshift */
445 2, /* size (0 = byte, 1 = short, 2 = long) */
446 32, /* bitsize */
99059e56 447 TRUE, /* pc_relative */
07d6d2b8 448 0, /* bitpos */
99059e56
RM		 449 complain_overflow_bitfield,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_ARM_GOTPC", /* name */
452 TRUE, /* partial_inplace */
453 0xffffffff, /* src_mask */
454 0xffffffff, /* dst_mask */
455 TRUE), /* pcrel_offset */
7f266840
DJ		 456
457 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 458 0, /* rightshift */
459 2, /* size (0 = byte, 1 = short, 2 = long) */
460 32, /* bitsize */
99059e56 461 FALSE, /* pc_relative */
07d6d2b8 462 0, /* bitpos */
99059e56
RM		 463 complain_overflow_bitfield,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_ARM_GOT32", /* name */
466 TRUE, /* partial_inplace */
467 0xffffffff, /* src_mask */
468 0xffffffff, /* dst_mask */
469 FALSE), /* pcrel_offset */
7f266840
DJ		 470
471 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 472 2, /* rightshift */
473 2, /* size (0 = byte, 1 = short, 2 = long) */
474 24, /* bitsize */
99059e56 475 TRUE, /* pc_relative */
07d6d2b8 476 0, /* bitpos */
99059e56
RM		 477 complain_overflow_bitfield,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_ARM_PLT32", /* name */
480 FALSE, /* partial_inplace */
481 0x00ffffff, /* src_mask */
482 0x00ffffff, /* dst_mask */
483 TRUE), /* pcrel_offset */
7f266840
DJ		 484
485 HOWTO (R_ARM_CALL, /* type */
486 2, /* rightshift */
487 2, /* size (0 = byte, 1 = short, 2 = long) */
488 24, /* bitsize */
489 TRUE, /* pc_relative */
490 0, /* bitpos */
491 complain_overflow_signed,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_ARM_CALL", /* name */
494 FALSE, /* partial_inplace */
495 0x00ffffff, /* src_mask */
496 0x00ffffff, /* dst_mask */
497 TRUE), /* pcrel_offset */
498
499 HOWTO (R_ARM_JUMP24, /* type */
500 2, /* rightshift */
501 2, /* size (0 = byte, 1 = short, 2 = long) */
502 24, /* bitsize */
503 TRUE, /* pc_relative */
504 0, /* bitpos */
505 complain_overflow_signed,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_ARM_JUMP24", /* name */
508 FALSE, /* partial_inplace */
509 0x00ffffff, /* src_mask */
510 0x00ffffff, /* dst_mask */
511 TRUE), /* pcrel_offset */
512
c19d1205
ZW		 513 HOWTO (R_ARM_THM_JUMP24, /* type */
514 1, /* rightshift */
515 2, /* size (0 = byte, 1 = short, 2 = long) */
516 24, /* bitsize */
517 TRUE, /* pc_relative */
7f266840 518 0, /* bitpos */
c19d1205 519 complain_overflow_signed,/* complain_on_overflow */
7f266840 520 bfd_elf_generic_reloc, /* special_function */
c19d1205 521 "R_ARM_THM_JUMP24", /* name */
7f266840 522 FALSE, /* partial_inplace */
c19d1205
ZW		 523 0x07ff2fff, /* src_mask */
524 0x07ff2fff, /* dst_mask */
525 TRUE), /* pcrel_offset */
7f266840 526
c19d1205 527 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 528 0, /* rightshift */
c19d1205
ZW		 529 2, /* size (0 = byte, 1 = short, 2 = long) */
530 32, /* bitsize */
7f266840
DJ		 531 FALSE, /* pc_relative */
532 0, /* bitpos */
533 complain_overflow_dont,/* complain_on_overflow */
534 bfd_elf_generic_reloc, /* special_function */
c19d1205 535 "R_ARM_BASE_ABS", /* name */
7f266840 536 FALSE, /* partial_inplace */
c19d1205
ZW		 537 0xffffffff, /* src_mask */
538 0xffffffff, /* dst_mask */
7f266840
DJ		 539 FALSE), /* pcrel_offset */
540
541 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
542 0, /* rightshift */
543 2, /* size (0 = byte, 1 = short, 2 = long) */
544 12, /* bitsize */
545 TRUE, /* pc_relative */
546 0, /* bitpos */
547 complain_overflow_dont,/* complain_on_overflow */
548 bfd_elf_generic_reloc, /* special_function */
549 "R_ARM_ALU_PCREL_7_0", /* name */
550 FALSE, /* partial_inplace */
551 0x00000fff, /* src_mask */
552 0x00000fff, /* dst_mask */
553 TRUE), /* pcrel_offset */
554
555 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
556 0, /* rightshift */
557 2, /* size (0 = byte, 1 = short, 2 = long) */
558 12, /* bitsize */
559 TRUE, /* pc_relative */
560 8, /* bitpos */
561 complain_overflow_dont,/* complain_on_overflow */
562 bfd_elf_generic_reloc, /* special_function */
563 "R_ARM_ALU_PCREL_15_8",/* name */
564 FALSE, /* partial_inplace */
565 0x00000fff, /* src_mask */
566 0x00000fff, /* dst_mask */
567 TRUE), /* pcrel_offset */
568
569 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
570 0, /* rightshift */
571 2, /* size (0 = byte, 1 = short, 2 = long) */
572 12, /* bitsize */
573 TRUE, /* pc_relative */
574 16, /* bitpos */
575 complain_overflow_dont,/* complain_on_overflow */
576 bfd_elf_generic_reloc, /* special_function */
577 "R_ARM_ALU_PCREL_23_15",/* name */
578 FALSE, /* partial_inplace */
579 0x00000fff, /* src_mask */
580 0x00000fff, /* dst_mask */
581 TRUE), /* pcrel_offset */
582
583 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
584 0, /* rightshift */
585 2, /* size (0 = byte, 1 = short, 2 = long) */
586 12, /* bitsize */
587 FALSE, /* pc_relative */
588 0, /* bitpos */
589 complain_overflow_dont,/* complain_on_overflow */
590 bfd_elf_generic_reloc, /* special_function */
591 "R_ARM_LDR_SBREL_11_0",/* name */
592 FALSE, /* partial_inplace */
593 0x00000fff, /* src_mask */
594 0x00000fff, /* dst_mask */
595 FALSE), /* pcrel_offset */
596
597 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
598 0, /* rightshift */
599 2, /* size (0 = byte, 1 = short, 2 = long) */
600 8, /* bitsize */
601 FALSE, /* pc_relative */
602 12, /* bitpos */
603 complain_overflow_dont,/* complain_on_overflow */
604 bfd_elf_generic_reloc, /* special_function */
605 "R_ARM_ALU_SBREL_19_12",/* name */
606 FALSE, /* partial_inplace */
607 0x000ff000, /* src_mask */
608 0x000ff000, /* dst_mask */
609 FALSE), /* pcrel_offset */
610
611 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
612 0, /* rightshift */
613 2, /* size (0 = byte, 1 = short, 2 = long) */
614 8, /* bitsize */
615 FALSE, /* pc_relative */
616 20, /* bitpos */
617 complain_overflow_dont,/* complain_on_overflow */
618 bfd_elf_generic_reloc, /* special_function */
619 "R_ARM_ALU_SBREL_27_20",/* name */
620 FALSE, /* partial_inplace */
621 0x0ff00000, /* src_mask */
622 0x0ff00000, /* dst_mask */
623 FALSE), /* pcrel_offset */
624
625 HOWTO (R_ARM_TARGET1, /* type */
626 0, /* rightshift */
627 2, /* size (0 = byte, 1 = short, 2 = long) */
628 32, /* bitsize */
629 FALSE, /* pc_relative */
630 0, /* bitpos */
631 complain_overflow_dont,/* complain_on_overflow */
632 bfd_elf_generic_reloc, /* special_function */
633 "R_ARM_TARGET1", /* name */
634 FALSE, /* partial_inplace */
635 0xffffffff, /* src_mask */
636 0xffffffff, /* dst_mask */
637 FALSE), /* pcrel_offset */
638
639 HOWTO (R_ARM_ROSEGREL32, /* type */
640 0, /* rightshift */
641 2, /* size (0 = byte, 1 = short, 2 = long) */
642 32, /* bitsize */
643 FALSE, /* pc_relative */
644 0, /* bitpos */
645 complain_overflow_dont,/* complain_on_overflow */
646 bfd_elf_generic_reloc, /* special_function */
647 "R_ARM_ROSEGREL32", /* name */
648 FALSE, /* partial_inplace */
649 0xffffffff, /* src_mask */
650 0xffffffff, /* dst_mask */
651 FALSE), /* pcrel_offset */
652
653 HOWTO (R_ARM_V4BX, /* type */
654 0, /* rightshift */
655 2, /* size (0 = byte, 1 = short, 2 = long) */
656 32, /* bitsize */
657 FALSE, /* pc_relative */
658 0, /* bitpos */
659 complain_overflow_dont,/* complain_on_overflow */
660 bfd_elf_generic_reloc, /* special_function */
661 "R_ARM_V4BX", /* name */
662 FALSE, /* partial_inplace */
663 0xffffffff, /* src_mask */
664 0xffffffff, /* dst_mask */
665 FALSE), /* pcrel_offset */
666
667 HOWTO (R_ARM_TARGET2, /* type */
668 0, /* rightshift */
669 2, /* size (0 = byte, 1 = short, 2 = long) */
670 32, /* bitsize */
671 FALSE, /* pc_relative */
672 0, /* bitpos */
673 complain_overflow_signed,/* complain_on_overflow */
674 bfd_elf_generic_reloc, /* special_function */
675 "R_ARM_TARGET2", /* name */
676 FALSE, /* partial_inplace */
677 0xffffffff, /* src_mask */
678 0xffffffff, /* dst_mask */
679 TRUE), /* pcrel_offset */
680
681 HOWTO (R_ARM_PREL31, /* type */
682 0, /* rightshift */
683 2, /* size (0 = byte, 1 = short, 2 = long) */
684 31, /* bitsize */
685 TRUE, /* pc_relative */
686 0, /* bitpos */
687 complain_overflow_signed,/* complain_on_overflow */
688 bfd_elf_generic_reloc, /* special_function */
689 "R_ARM_PREL31", /* name */
690 FALSE, /* partial_inplace */
691 0x7fffffff, /* src_mask */
692 0x7fffffff, /* dst_mask */
693 TRUE), /* pcrel_offset */
c19d1205
ZW		 694
695 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
696 0, /* rightshift */
697 2, /* size (0 = byte, 1 = short, 2 = long) */
698 16, /* bitsize */
699 FALSE, /* pc_relative */
700 0, /* bitpos */
701 complain_overflow_dont,/* complain_on_overflow */
702 bfd_elf_generic_reloc, /* special_function */
703 "R_ARM_MOVW_ABS_NC", /* name */
704 FALSE, /* partial_inplace */
39623e12
PB		 705 0x000f0fff, /* src_mask */
706 0x000f0fff, /* dst_mask */
c19d1205
ZW		 707 FALSE), /* pcrel_offset */
708
709 HOWTO (R_ARM_MOVT_ABS, /* type */
710 0, /* rightshift */
711 2, /* size (0 = byte, 1 = short, 2 = long) */
712 16, /* bitsize */
713 FALSE, /* pc_relative */
714 0, /* bitpos */
715 complain_overflow_bitfield,/* complain_on_overflow */
716 bfd_elf_generic_reloc, /* special_function */
717 "R_ARM_MOVT_ABS", /* name */
718 FALSE, /* partial_inplace */
39623e12
PB		 719 0x000f0fff, /* src_mask */
720 0x000f0fff, /* dst_mask */
c19d1205
ZW		 721 FALSE), /* pcrel_offset */
722
723 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
724 0, /* rightshift */
725 2, /* size (0 = byte, 1 = short, 2 = long) */
726 16, /* bitsize */
727 TRUE, /* pc_relative */
728 0, /* bitpos */
729 complain_overflow_dont,/* complain_on_overflow */
730 bfd_elf_generic_reloc, /* special_function */
731 "R_ARM_MOVW_PREL_NC", /* name */
732 FALSE, /* partial_inplace */
39623e12
PB		 733 0x000f0fff, /* src_mask */
734 0x000f0fff, /* dst_mask */
c19d1205
ZW		 735 TRUE), /* pcrel_offset */
736
737 HOWTO (R_ARM_MOVT_PREL, /* type */
738 0, /* rightshift */
739 2, /* size (0 = byte, 1 = short, 2 = long) */
740 16, /* bitsize */
741 TRUE, /* pc_relative */
742 0, /* bitpos */
743 complain_overflow_bitfield,/* complain_on_overflow */
744 bfd_elf_generic_reloc, /* special_function */
745 "R_ARM_MOVT_PREL", /* name */
746 FALSE, /* partial_inplace */
39623e12
PB		 747 0x000f0fff, /* src_mask */
748 0x000f0fff, /* dst_mask */
c19d1205
ZW		 749 TRUE), /* pcrel_offset */
750
751 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
752 0, /* rightshift */
753 2, /* size (0 = byte, 1 = short, 2 = long) */
754 16, /* bitsize */
755 FALSE, /* pc_relative */
756 0, /* bitpos */
757 complain_overflow_dont,/* complain_on_overflow */
758 bfd_elf_generic_reloc, /* special_function */
759 "R_ARM_THM_MOVW_ABS_NC",/* name */
760 FALSE, /* partial_inplace */
761 0x040f70ff, /* src_mask */
762 0x040f70ff, /* dst_mask */
763 FALSE), /* pcrel_offset */
764
765 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
766 0, /* rightshift */
767 2, /* size (0 = byte, 1 = short, 2 = long) */
768 16, /* bitsize */
769 FALSE, /* pc_relative */
770 0, /* bitpos */
771 complain_overflow_bitfield,/* complain_on_overflow */
772 bfd_elf_generic_reloc, /* special_function */
773 "R_ARM_THM_MOVT_ABS", /* name */
774 FALSE, /* partial_inplace */
775 0x040f70ff, /* src_mask */
776 0x040f70ff, /* dst_mask */
777 FALSE), /* pcrel_offset */
778
779 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
780 0, /* rightshift */
781 2, /* size (0 = byte, 1 = short, 2 = long) */
782 16, /* bitsize */
783 TRUE, /* pc_relative */
784 0, /* bitpos */
785 complain_overflow_dont,/* complain_on_overflow */
786 bfd_elf_generic_reloc, /* special_function */
787 "R_ARM_THM_MOVW_PREL_NC",/* name */
788 FALSE, /* partial_inplace */
789 0x040f70ff, /* src_mask */
790 0x040f70ff, /* dst_mask */
791 TRUE), /* pcrel_offset */
792
793 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
794 0, /* rightshift */
795 2, /* size (0 = byte, 1 = short, 2 = long) */
796 16, /* bitsize */
797 TRUE, /* pc_relative */
798 0, /* bitpos */
799 complain_overflow_bitfield,/* complain_on_overflow */
800 bfd_elf_generic_reloc, /* special_function */
801 "R_ARM_THM_MOVT_PREL", /* name */
802 FALSE, /* partial_inplace */
803 0x040f70ff, /* src_mask */
804 0x040f70ff, /* dst_mask */
805 TRUE), /* pcrel_offset */
806
807 HOWTO (R_ARM_THM_JUMP19, /* type */
808 1, /* rightshift */
809 2, /* size (0 = byte, 1 = short, 2 = long) */
810 19, /* bitsize */
811 TRUE, /* pc_relative */
812 0, /* bitpos */
813 complain_overflow_signed,/* complain_on_overflow */
814 bfd_elf_generic_reloc, /* special_function */
815 "R_ARM_THM_JUMP19", /* name */
816 FALSE, /* partial_inplace */
817 0x043f2fff, /* src_mask */
818 0x043f2fff, /* dst_mask */
819 TRUE), /* pcrel_offset */
820
821 HOWTO (R_ARM_THM_JUMP6, /* type */
822 1, /* rightshift */
823 1, /* size (0 = byte, 1 = short, 2 = long) */
824 6, /* bitsize */
825 TRUE, /* pc_relative */
826 0, /* bitpos */
827 complain_overflow_unsigned,/* complain_on_overflow */
828 bfd_elf_generic_reloc, /* special_function */
829 "R_ARM_THM_JUMP6", /* name */
830 FALSE, /* partial_inplace */
831 0x02f8, /* src_mask */
832 0x02f8, /* dst_mask */
833 TRUE), /* pcrel_offset */
834
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
838 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
839 0, /* rightshift */
840 2, /* size (0 = byte, 1 = short, 2 = long) */
841 13, /* bitsize */
842 TRUE, /* pc_relative */
843 0, /* bitpos */
2cab6cc3 844 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 845 bfd_elf_generic_reloc, /* special_function */
846 "R_ARM_THM_ALU_PREL_11_0",/* name */
847 FALSE, /* partial_inplace */
2cab6cc3
MS		 848 0xffffffff, /* src_mask */
849 0xffffffff, /* dst_mask */
c19d1205
ZW		 850 TRUE), /* pcrel_offset */
851
852 HOWTO (R_ARM_THM_PC12, /* type */
853 0, /* rightshift */
854 2, /* size (0 = byte, 1 = short, 2 = long) */
855 13, /* bitsize */
856 TRUE, /* pc_relative */
857 0, /* bitpos */
2cab6cc3 858 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 859 bfd_elf_generic_reloc, /* special_function */
860 "R_ARM_THM_PC12", /* name */
861 FALSE, /* partial_inplace */
2cab6cc3
MS		 862 0xffffffff, /* src_mask */
863 0xffffffff, /* dst_mask */
c19d1205
ZW		 864 TRUE), /* pcrel_offset */
865
866 HOWTO (R_ARM_ABS32_NOI, /* type */
867 0, /* rightshift */
868 2, /* size (0 = byte, 1 = short, 2 = long) */
869 32, /* bitsize */
870 FALSE, /* pc_relative */
871 0, /* bitpos */
872 complain_overflow_dont,/* complain_on_overflow */
873 bfd_elf_generic_reloc, /* special_function */
874 "R_ARM_ABS32_NOI", /* name */
875 FALSE, /* partial_inplace */
876 0xffffffff, /* src_mask */
877 0xffffffff, /* dst_mask */
878 FALSE), /* pcrel_offset */
879
880 HOWTO (R_ARM_REL32_NOI, /* type */
881 0, /* rightshift */
882 2, /* size (0 = byte, 1 = short, 2 = long) */
883 32, /* bitsize */
884 TRUE, /* pc_relative */
885 0, /* bitpos */
886 complain_overflow_dont,/* complain_on_overflow */
887 bfd_elf_generic_reloc, /* special_function */
888 "R_ARM_REL32_NOI", /* name */
889 FALSE, /* partial_inplace */
890 0xffffffff, /* src_mask */
891 0xffffffff, /* dst_mask */
892 FALSE), /* pcrel_offset */
7f266840 893
4962c51a
MS		 894 /* Group relocations. */
895
896 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
897 0, /* rightshift */
898 2, /* size (0 = byte, 1 = short, 2 = long) */
899 32, /* bitsize */
900 TRUE, /* pc_relative */
901 0, /* bitpos */
902 complain_overflow_dont,/* complain_on_overflow */
903 bfd_elf_generic_reloc, /* special_function */
904 "R_ARM_ALU_PC_G0_NC", /* name */
905 FALSE, /* partial_inplace */
906 0xffffffff, /* src_mask */
907 0xffffffff, /* dst_mask */
908 TRUE), /* pcrel_offset */
909
07d6d2b8 910 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 911 0, /* rightshift */
912 2, /* size (0 = byte, 1 = short, 2 = long) */
913 32, /* bitsize */
914 TRUE, /* pc_relative */
915 0, /* bitpos */
916 complain_overflow_dont,/* complain_on_overflow */
917 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 918 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 919 FALSE, /* partial_inplace */
920 0xffffffff, /* src_mask */
921 0xffffffff, /* dst_mask */
922 TRUE), /* pcrel_offset */
923
924 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
925 0, /* rightshift */
926 2, /* size (0 = byte, 1 = short, 2 = long) */
927 32, /* bitsize */
928 TRUE, /* pc_relative */
929 0, /* bitpos */
930 complain_overflow_dont,/* complain_on_overflow */
931 bfd_elf_generic_reloc, /* special_function */
932 "R_ARM_ALU_PC_G1_NC", /* name */
933 FALSE, /* partial_inplace */
934 0xffffffff, /* src_mask */
935 0xffffffff, /* dst_mask */
936 TRUE), /* pcrel_offset */
937
07d6d2b8 938 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 939 0, /* rightshift */
940 2, /* size (0 = byte, 1 = short, 2 = long) */
941 32, /* bitsize */
942 TRUE, /* pc_relative */
943 0, /* bitpos */
944 complain_overflow_dont,/* complain_on_overflow */
945 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 946 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 947 FALSE, /* partial_inplace */
948 0xffffffff, /* src_mask */
949 0xffffffff, /* dst_mask */
950 TRUE), /* pcrel_offset */
951
07d6d2b8 952 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 953 0, /* rightshift */
954 2, /* size (0 = byte, 1 = short, 2 = long) */
955 32, /* bitsize */
956 TRUE, /* pc_relative */
957 0, /* bitpos */
958 complain_overflow_dont,/* complain_on_overflow */
959 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 960 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 961 FALSE, /* partial_inplace */
962 0xffffffff, /* src_mask */
963 0xffffffff, /* dst_mask */
964 TRUE), /* pcrel_offset */
965
07d6d2b8 966 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 967 0, /* rightshift */
968 2, /* size (0 = byte, 1 = short, 2 = long) */
969 32, /* bitsize */
970 TRUE, /* pc_relative */
971 0, /* bitpos */
972 complain_overflow_dont,/* complain_on_overflow */
973 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 974 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 975 FALSE, /* partial_inplace */
976 0xffffffff, /* src_mask */
977 0xffffffff, /* dst_mask */
978 TRUE), /* pcrel_offset */
979
07d6d2b8 980 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 981 0, /* rightshift */
982 2, /* size (0 = byte, 1 = short, 2 = long) */
983 32, /* bitsize */
984 TRUE, /* pc_relative */
985 0, /* bitpos */
986 complain_overflow_dont,/* complain_on_overflow */
987 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 988 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 989 FALSE, /* partial_inplace */
990 0xffffffff, /* src_mask */
991 0xffffffff, /* dst_mask */
992 TRUE), /* pcrel_offset */
993
07d6d2b8 994 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 995 0, /* rightshift */
996 2, /* size (0 = byte, 1 = short, 2 = long) */
997 32, /* bitsize */
998 TRUE, /* pc_relative */
999 0, /* bitpos */
1000 complain_overflow_dont,/* complain_on_overflow */
1001 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1002 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1003 FALSE, /* partial_inplace */
1004 0xffffffff, /* src_mask */
1005 0xffffffff, /* dst_mask */
1006 TRUE), /* pcrel_offset */
1007
07d6d2b8 1008 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1009 0, /* rightshift */
1010 2, /* size (0 = byte, 1 = short, 2 = long) */
1011 32, /* bitsize */
1012 TRUE, /* pc_relative */
1013 0, /* bitpos */
1014 complain_overflow_dont,/* complain_on_overflow */
1015 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1016 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1017 FALSE, /* partial_inplace */
1018 0xffffffff, /* src_mask */
1019 0xffffffff, /* dst_mask */
1020 TRUE), /* pcrel_offset */
1021
07d6d2b8 1022 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1023 0, /* rightshift */
1024 2, /* size (0 = byte, 1 = short, 2 = long) */
1025 32, /* bitsize */
1026 TRUE, /* pc_relative */
1027 0, /* bitpos */
1028 complain_overflow_dont,/* complain_on_overflow */
1029 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1030 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1031 FALSE, /* partial_inplace */
1032 0xffffffff, /* src_mask */
1033 0xffffffff, /* dst_mask */
1034 TRUE), /* pcrel_offset */
1035
07d6d2b8 1036 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1037 0, /* rightshift */
1038 2, /* size (0 = byte, 1 = short, 2 = long) */
1039 32, /* bitsize */
1040 TRUE, /* pc_relative */
1041 0, /* bitpos */
1042 complain_overflow_dont,/* complain_on_overflow */
1043 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1044 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1045 FALSE, /* partial_inplace */
1046 0xffffffff, /* src_mask */
1047 0xffffffff, /* dst_mask */
1048 TRUE), /* pcrel_offset */
1049
07d6d2b8 1050 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1051 0, /* rightshift */
1052 2, /* size (0 = byte, 1 = short, 2 = long) */
1053 32, /* bitsize */
1054 TRUE, /* pc_relative */
1055 0, /* bitpos */
1056 complain_overflow_dont,/* complain_on_overflow */
1057 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1058 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1059 FALSE, /* partial_inplace */
1060 0xffffffff, /* src_mask */
1061 0xffffffff, /* dst_mask */
1062 TRUE), /* pcrel_offset */
1063
07d6d2b8 1064 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1065 0, /* rightshift */
1066 2, /* size (0 = byte, 1 = short, 2 = long) */
1067 32, /* bitsize */
1068 TRUE, /* pc_relative */
1069 0, /* bitpos */
1070 complain_overflow_dont,/* complain_on_overflow */
1071 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1072 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1073 FALSE, /* partial_inplace */
1074 0xffffffff, /* src_mask */
1075 0xffffffff, /* dst_mask */
1076 TRUE), /* pcrel_offset */
1077
07d6d2b8 1078 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1079 0, /* rightshift */
1080 2, /* size (0 = byte, 1 = short, 2 = long) */
1081 32, /* bitsize */
1082 TRUE, /* pc_relative */
1083 0, /* bitpos */
1084 complain_overflow_dont,/* complain_on_overflow */
1085 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1086 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1087 FALSE, /* partial_inplace */
1088 0xffffffff, /* src_mask */
1089 0xffffffff, /* dst_mask */
1090 TRUE), /* pcrel_offset */
1091
07d6d2b8 1092 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1093 0, /* rightshift */
1094 2, /* size (0 = byte, 1 = short, 2 = long) */
1095 32, /* bitsize */
1096 TRUE, /* pc_relative */
1097 0, /* bitpos */
1098 complain_overflow_dont,/* complain_on_overflow */
1099 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1100 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1101 FALSE, /* partial_inplace */
1102 0xffffffff, /* src_mask */
1103 0xffffffff, /* dst_mask */
1104 TRUE), /* pcrel_offset */
1105
07d6d2b8 1106 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1107 0, /* rightshift */
1108 2, /* size (0 = byte, 1 = short, 2 = long) */
1109 32, /* bitsize */
1110 TRUE, /* pc_relative */
1111 0, /* bitpos */
1112 complain_overflow_dont,/* complain_on_overflow */
1113 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1114 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1115 FALSE, /* partial_inplace */
1116 0xffffffff, /* src_mask */
1117 0xffffffff, /* dst_mask */
1118 TRUE), /* pcrel_offset */
1119
07d6d2b8 1120 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1121 0, /* rightshift */
1122 2, /* size (0 = byte, 1 = short, 2 = long) */
1123 32, /* bitsize */
1124 TRUE, /* pc_relative */
1125 0, /* bitpos */
1126 complain_overflow_dont,/* complain_on_overflow */
1127 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1128 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1129 FALSE, /* partial_inplace */
1130 0xffffffff, /* src_mask */
1131 0xffffffff, /* dst_mask */
1132 TRUE), /* pcrel_offset */
1133
07d6d2b8 1134 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1135 0, /* rightshift */
1136 2, /* size (0 = byte, 1 = short, 2 = long) */
1137 32, /* bitsize */
1138 TRUE, /* pc_relative */
1139 0, /* bitpos */
1140 complain_overflow_dont,/* complain_on_overflow */
1141 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1142 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1143 FALSE, /* partial_inplace */
1144 0xffffffff, /* src_mask */
1145 0xffffffff, /* dst_mask */
1146 TRUE), /* pcrel_offset */
1147
07d6d2b8 1148 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1149 0, /* rightshift */
1150 2, /* size (0 = byte, 1 = short, 2 = long) */
1151 32, /* bitsize */
1152 TRUE, /* pc_relative */
1153 0, /* bitpos */
1154 complain_overflow_dont,/* complain_on_overflow */
1155 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1156 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1157 FALSE, /* partial_inplace */
1158 0xffffffff, /* src_mask */
1159 0xffffffff, /* dst_mask */
1160 TRUE), /* pcrel_offset */
1161
07d6d2b8 1162 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1163 0, /* rightshift */
1164 2, /* size (0 = byte, 1 = short, 2 = long) */
1165 32, /* bitsize */
1166 TRUE, /* pc_relative */
1167 0, /* bitpos */
1168 complain_overflow_dont,/* complain_on_overflow */
1169 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1170 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1171 FALSE, /* partial_inplace */
1172 0xffffffff, /* src_mask */
1173 0xffffffff, /* dst_mask */
1174 TRUE), /* pcrel_offset */
1175
07d6d2b8 1176 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1177 0, /* rightshift */
1178 2, /* size (0 = byte, 1 = short, 2 = long) */
1179 32, /* bitsize */
1180 TRUE, /* pc_relative */
1181 0, /* bitpos */
1182 complain_overflow_dont,/* complain_on_overflow */
1183 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1184 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1185 FALSE, /* partial_inplace */
1186 0xffffffff, /* src_mask */
1187 0xffffffff, /* dst_mask */
1188 TRUE), /* pcrel_offset */
1189
07d6d2b8 1190 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1191 0, /* rightshift */
1192 2, /* size (0 = byte, 1 = short, 2 = long) */
1193 32, /* bitsize */
1194 TRUE, /* pc_relative */
1195 0, /* bitpos */
1196 complain_overflow_dont,/* complain_on_overflow */
1197 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1198 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1199 FALSE, /* partial_inplace */
1200 0xffffffff, /* src_mask */
1201 0xffffffff, /* dst_mask */
1202 TRUE), /* pcrel_offset */
1203
07d6d2b8 1204 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1205 0, /* rightshift */
1206 2, /* size (0 = byte, 1 = short, 2 = long) */
1207 32, /* bitsize */
1208 TRUE, /* pc_relative */
1209 0, /* bitpos */
1210 complain_overflow_dont,/* complain_on_overflow */
1211 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1212 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1213 FALSE, /* partial_inplace */
1214 0xffffffff, /* src_mask */
1215 0xffffffff, /* dst_mask */
1216 TRUE), /* pcrel_offset */
1217
07d6d2b8 1218 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1219 0, /* rightshift */
1220 2, /* size (0 = byte, 1 = short, 2 = long) */
1221 32, /* bitsize */
1222 TRUE, /* pc_relative */
1223 0, /* bitpos */
1224 complain_overflow_dont,/* complain_on_overflow */
1225 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1226 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1227 FALSE, /* partial_inplace */
1228 0xffffffff, /* src_mask */
1229 0xffffffff, /* dst_mask */
1230 TRUE), /* pcrel_offset */
1231
07d6d2b8 1232 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1233 0, /* rightshift */
1234 2, /* size (0 = byte, 1 = short, 2 = long) */
1235 32, /* bitsize */
1236 TRUE, /* pc_relative */
1237 0, /* bitpos */
1238 complain_overflow_dont,/* complain_on_overflow */
1239 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1240 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1241 FALSE, /* partial_inplace */
1242 0xffffffff, /* src_mask */
1243 0xffffffff, /* dst_mask */
1244 TRUE), /* pcrel_offset */
1245
07d6d2b8 1246 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1247 0, /* rightshift */
1248 2, /* size (0 = byte, 1 = short, 2 = long) */
1249 32, /* bitsize */
1250 TRUE, /* pc_relative */
1251 0, /* bitpos */
1252 complain_overflow_dont,/* complain_on_overflow */
1253 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1254 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1255 FALSE, /* partial_inplace */
1256 0xffffffff, /* src_mask */
1257 0xffffffff, /* dst_mask */
1258 TRUE), /* pcrel_offset */
1259
07d6d2b8 1260 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1261 0, /* rightshift */
1262 2, /* size (0 = byte, 1 = short, 2 = long) */
1263 32, /* bitsize */
1264 TRUE, /* pc_relative */
1265 0, /* bitpos */
1266 complain_overflow_dont,/* complain_on_overflow */
1267 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1268 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1269 FALSE, /* partial_inplace */
1270 0xffffffff, /* src_mask */
1271 0xffffffff, /* dst_mask */
1272 TRUE), /* pcrel_offset */
1273
1274 /* End of group relocations. */
c19d1205 1275
c19d1205
ZW		 1276 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1277 0, /* rightshift */
1278 2, /* size (0 = byte, 1 = short, 2 = long) */
1279 16, /* bitsize */
1280 FALSE, /* pc_relative */
1281 0, /* bitpos */
1282 complain_overflow_dont,/* complain_on_overflow */
1283 bfd_elf_generic_reloc, /* special_function */
1284 "R_ARM_MOVW_BREL_NC", /* name */
1285 FALSE, /* partial_inplace */
1286 0x0000ffff, /* src_mask */
1287 0x0000ffff, /* dst_mask */
1288 FALSE), /* pcrel_offset */
1289
1290 HOWTO (R_ARM_MOVT_BREL, /* type */
1291 0, /* rightshift */
1292 2, /* size (0 = byte, 1 = short, 2 = long) */
1293 16, /* bitsize */
1294 FALSE, /* pc_relative */
1295 0, /* bitpos */
1296 complain_overflow_bitfield,/* complain_on_overflow */
1297 bfd_elf_generic_reloc, /* special_function */
1298 "R_ARM_MOVT_BREL", /* name */
1299 FALSE, /* partial_inplace */
1300 0x0000ffff, /* src_mask */
1301 0x0000ffff, /* dst_mask */
1302 FALSE), /* pcrel_offset */
1303
1304 HOWTO (R_ARM_MOVW_BREL, /* type */
1305 0, /* rightshift */
1306 2, /* size (0 = byte, 1 = short, 2 = long) */
1307 16, /* bitsize */
1308 FALSE, /* pc_relative */
1309 0, /* bitpos */
1310 complain_overflow_dont,/* complain_on_overflow */
1311 bfd_elf_generic_reloc, /* special_function */
1312 "R_ARM_MOVW_BREL", /* name */
1313 FALSE, /* partial_inplace */
1314 0x0000ffff, /* src_mask */
1315 0x0000ffff, /* dst_mask */
1316 FALSE), /* pcrel_offset */
1317
1318 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1319 0, /* rightshift */
1320 2, /* size (0 = byte, 1 = short, 2 = long) */
1321 16, /* bitsize */
1322 FALSE, /* pc_relative */
1323 0, /* bitpos */
1324 complain_overflow_dont,/* complain_on_overflow */
1325 bfd_elf_generic_reloc, /* special_function */
1326 "R_ARM_THM_MOVW_BREL_NC",/* name */
1327 FALSE, /* partial_inplace */
1328 0x040f70ff, /* src_mask */
1329 0x040f70ff, /* dst_mask */
1330 FALSE), /* pcrel_offset */
1331
1332 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1333 0, /* rightshift */
1334 2, /* size (0 = byte, 1 = short, 2 = long) */
1335 16, /* bitsize */
1336 FALSE, /* pc_relative */
1337 0, /* bitpos */
1338 complain_overflow_bitfield,/* complain_on_overflow */
1339 bfd_elf_generic_reloc, /* special_function */
1340 "R_ARM_THM_MOVT_BREL", /* name */
1341 FALSE, /* partial_inplace */
1342 0x040f70ff, /* src_mask */
1343 0x040f70ff, /* dst_mask */
1344 FALSE), /* pcrel_offset */
1345
1346 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1347 0, /* rightshift */
1348 2, /* size (0 = byte, 1 = short, 2 = long) */
1349 16, /* bitsize */
1350 FALSE, /* pc_relative */
1351 0, /* bitpos */
1352 complain_overflow_dont,/* complain_on_overflow */
1353 bfd_elf_generic_reloc, /* special_function */
1354 "R_ARM_THM_MOVW_BREL", /* name */
1355 FALSE, /* partial_inplace */
1356 0x040f70ff, /* src_mask */
1357 0x040f70ff, /* dst_mask */
1358 FALSE), /* pcrel_offset */
1359
0855e32b
NS		 1360 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1361 0, /* rightshift */
1362 2, /* size (0 = byte, 1 = short, 2 = long) */
1363 32, /* bitsize */
1364 FALSE, /* pc_relative */
1365 0, /* bitpos */
1366 complain_overflow_bitfield,/* complain_on_overflow */
1367 NULL, /* special_function */
1368 "R_ARM_TLS_GOTDESC", /* name */
1369 TRUE, /* partial_inplace */
1370 0xffffffff, /* src_mask */
1371 0xffffffff, /* dst_mask */
1372 FALSE), /* pcrel_offset */
1373
1374 HOWTO (R_ARM_TLS_CALL, /* type */
1375 0, /* rightshift */
1376 2, /* size (0 = byte, 1 = short, 2 = long) */
1377 24, /* bitsize */
1378 FALSE, /* pc_relative */
1379 0, /* bitpos */
1380 complain_overflow_dont,/* complain_on_overflow */
1381 bfd_elf_generic_reloc, /* special_function */
1382 "R_ARM_TLS_CALL", /* name */
1383 FALSE, /* partial_inplace */
1384 0x00ffffff, /* src_mask */
1385 0x00ffffff, /* dst_mask */
1386 FALSE), /* pcrel_offset */
1387
1388 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1389 0, /* rightshift */
1390 2, /* size (0 = byte, 1 = short, 2 = long) */
1391 0, /* bitsize */
1392 FALSE, /* pc_relative */
1393 0, /* bitpos */
1394 complain_overflow_bitfield,/* complain_on_overflow */
1395 bfd_elf_generic_reloc, /* special_function */
1396 "R_ARM_TLS_DESCSEQ", /* name */
1397 FALSE, /* partial_inplace */
1398 0x00000000, /* src_mask */
1399 0x00000000, /* dst_mask */
1400 FALSE), /* pcrel_offset */
1401
1402 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1403 0, /* rightshift */
1404 2, /* size (0 = byte, 1 = short, 2 = long) */
1405 24, /* bitsize */
1406 FALSE, /* pc_relative */
1407 0, /* bitpos */
1408 complain_overflow_dont,/* complain_on_overflow */
1409 bfd_elf_generic_reloc, /* special_function */
1410 "R_ARM_THM_TLS_CALL", /* name */
1411 FALSE, /* partial_inplace */
1412 0x07ff07ff, /* src_mask */
1413 0x07ff07ff, /* dst_mask */
1414 FALSE), /* pcrel_offset */
c19d1205
ZW		 1415
1416 HOWTO (R_ARM_PLT32_ABS, /* type */
1417 0, /* rightshift */
1418 2, /* size (0 = byte, 1 = short, 2 = long) */
1419 32, /* bitsize */
1420 FALSE, /* pc_relative */
1421 0, /* bitpos */
1422 complain_overflow_dont,/* complain_on_overflow */
1423 bfd_elf_generic_reloc, /* special_function */
1424 "R_ARM_PLT32_ABS", /* name */
1425 FALSE, /* partial_inplace */
1426 0xffffffff, /* src_mask */
1427 0xffffffff, /* dst_mask */
1428 FALSE), /* pcrel_offset */
1429
1430 HOWTO (R_ARM_GOT_ABS, /* type */
1431 0, /* rightshift */
1432 2, /* size (0 = byte, 1 = short, 2 = long) */
1433 32, /* bitsize */
1434 FALSE, /* pc_relative */
1435 0, /* bitpos */
1436 complain_overflow_dont,/* complain_on_overflow */
1437 bfd_elf_generic_reloc, /* special_function */
1438 "R_ARM_GOT_ABS", /* name */
1439 FALSE, /* partial_inplace */
1440 0xffffffff, /* src_mask */
1441 0xffffffff, /* dst_mask */
1442 FALSE), /* pcrel_offset */
1443
1444 HOWTO (R_ARM_GOT_PREL, /* type */
1445 0, /* rightshift */
1446 2, /* size (0 = byte, 1 = short, 2 = long) */
1447 32, /* bitsize */
1448 TRUE, /* pc_relative */
1449 0, /* bitpos */
1450 complain_overflow_dont, /* complain_on_overflow */
1451 bfd_elf_generic_reloc, /* special_function */
1452 "R_ARM_GOT_PREL", /* name */
1453 FALSE, /* partial_inplace */
1454 0xffffffff, /* src_mask */
1455 0xffffffff, /* dst_mask */
1456 TRUE), /* pcrel_offset */
1457
1458 HOWTO (R_ARM_GOT_BREL12, /* type */
1459 0, /* rightshift */
1460 2, /* size (0 = byte, 1 = short, 2 = long) */
1461 12, /* bitsize */
1462 FALSE, /* pc_relative */
1463 0, /* bitpos */
1464 complain_overflow_bitfield,/* complain_on_overflow */
1465 bfd_elf_generic_reloc, /* special_function */
1466 "R_ARM_GOT_BREL12", /* name */
1467 FALSE, /* partial_inplace */
1468 0x00000fff, /* src_mask */
1469 0x00000fff, /* dst_mask */
1470 FALSE), /* pcrel_offset */
1471
1472 HOWTO (R_ARM_GOTOFF12, /* type */
1473 0, /* rightshift */
1474 2, /* size (0 = byte, 1 = short, 2 = long) */
1475 12, /* bitsize */
1476 FALSE, /* pc_relative */
1477 0, /* bitpos */
1478 complain_overflow_bitfield,/* complain_on_overflow */
1479 bfd_elf_generic_reloc, /* special_function */
1480 "R_ARM_GOTOFF12", /* name */
1481 FALSE, /* partial_inplace */
1482 0x00000fff, /* src_mask */
1483 0x00000fff, /* dst_mask */
1484 FALSE), /* pcrel_offset */
1485
07d6d2b8 1486 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1487
1488 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1489 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1490 0, /* rightshift */
1491 2, /* size (0 = byte, 1 = short, 2 = long) */
1492 0, /* bitsize */
1493 FALSE, /* pc_relative */
1494 0, /* bitpos */
99059e56 1495 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1496 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1497 "R_ARM_GNU_VTENTRY", /* name */
1498 FALSE, /* partial_inplace */
1499 0, /* src_mask */
1500 0, /* dst_mask */
1501 FALSE), /* pcrel_offset */
c19d1205
ZW		 1502
1503 /* GNU extension to record C++ vtable hierarchy */
1504 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1505 0, /* rightshift */
1506 2, /* size (0 = byte, 1 = short, 2 = long) */
1507 0, /* bitsize */
1508 FALSE, /* pc_relative */
1509 0, /* bitpos */
99059e56 1510 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1511 NULL, /* special_function */
99059e56 1512 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1513 FALSE, /* partial_inplace */
1514 0, /* src_mask */
1515 0, /* dst_mask */
1516 FALSE), /* pcrel_offset */
c19d1205
ZW		 1517
1518 HOWTO (R_ARM_THM_JUMP11, /* type */
1519 1, /* rightshift */
1520 1, /* size (0 = byte, 1 = short, 2 = long) */
1521 11, /* bitsize */
1522 TRUE, /* pc_relative */
1523 0, /* bitpos */
1524 complain_overflow_signed, /* complain_on_overflow */
1525 bfd_elf_generic_reloc, /* special_function */
1526 "R_ARM_THM_JUMP11", /* name */
1527 FALSE, /* partial_inplace */
1528 0x000007ff, /* src_mask */
1529 0x000007ff, /* dst_mask */
1530 TRUE), /* pcrel_offset */
1531
1532 HOWTO (R_ARM_THM_JUMP8, /* type */
1533 1, /* rightshift */
1534 1, /* size (0 = byte, 1 = short, 2 = long) */
1535 8, /* bitsize */
1536 TRUE, /* pc_relative */
1537 0, /* bitpos */
1538 complain_overflow_signed, /* complain_on_overflow */
1539 bfd_elf_generic_reloc, /* special_function */
1540 "R_ARM_THM_JUMP8", /* name */
1541 FALSE, /* partial_inplace */
1542 0x000000ff, /* src_mask */
1543 0x000000ff, /* dst_mask */
1544 TRUE), /* pcrel_offset */
ba93b8ac 1545
c19d1205
ZW		 1546 /* TLS relocations */
1547 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1548 0, /* rightshift */
1549 2, /* size (0 = byte, 1 = short, 2 = long) */
1550 32, /* bitsize */
1551 FALSE, /* pc_relative */
1552 0, /* bitpos */
99059e56
RM		 1553 complain_overflow_bitfield,/* complain_on_overflow */
1554 NULL, /* special_function */
1555 "R_ARM_TLS_GD32", /* name */
1556 TRUE, /* partial_inplace */
1557 0xffffffff, /* src_mask */
1558 0xffffffff, /* dst_mask */
07d6d2b8 1559 FALSE), /* pcrel_offset */
ba93b8ac 1560
ba93b8ac 1561 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1562 0, /* rightshift */
1563 2, /* size (0 = byte, 1 = short, 2 = long) */
1564 32, /* bitsize */
1565 FALSE, /* pc_relative */
1566 0, /* bitpos */
99059e56
RM		 1567 complain_overflow_bitfield,/* complain_on_overflow */
1568 bfd_elf_generic_reloc, /* special_function */
1569 "R_ARM_TLS_LDM32", /* name */
1570 TRUE, /* partial_inplace */
1571 0xffffffff, /* src_mask */
1572 0xffffffff, /* dst_mask */
07d6d2b8 1573 FALSE), /* pcrel_offset */
ba93b8ac 1574
c19d1205 1575 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1576 0, /* rightshift */
1577 2, /* size (0 = byte, 1 = short, 2 = long) */
1578 32, /* bitsize */
1579 FALSE, /* pc_relative */
1580 0, /* bitpos */
99059e56
RM		 1581 complain_overflow_bitfield,/* complain_on_overflow */
1582 bfd_elf_generic_reloc, /* special_function */
1583 "R_ARM_TLS_LDO32", /* name */
1584 TRUE, /* partial_inplace */
1585 0xffffffff, /* src_mask */
1586 0xffffffff, /* dst_mask */
07d6d2b8 1587 FALSE), /* pcrel_offset */
ba93b8ac 1588
ba93b8ac 1589 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1590 0, /* rightshift */
1591 2, /* size (0 = byte, 1 = short, 2 = long) */
1592 32, /* bitsize */
1593 FALSE, /* pc_relative */
1594 0, /* bitpos */
99059e56
RM		 1595 complain_overflow_bitfield,/* complain_on_overflow */
1596 NULL, /* special_function */
1597 "R_ARM_TLS_IE32", /* name */
1598 TRUE, /* partial_inplace */
1599 0xffffffff, /* src_mask */
1600 0xffffffff, /* dst_mask */
07d6d2b8 1601 FALSE), /* pcrel_offset */
7f266840 1602
c19d1205 1603 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1604 0, /* rightshift */
1605 2, /* size (0 = byte, 1 = short, 2 = long) */
1606 32, /* bitsize */
1607 FALSE, /* pc_relative */
1608 0, /* bitpos */
99059e56 1609 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1610 NULL, /* special_function */
99059e56
RM		 1611 "R_ARM_TLS_LE32", /* name */
1612 TRUE, /* partial_inplace */
1613 0xffffffff, /* src_mask */
1614 0xffffffff, /* dst_mask */
07d6d2b8 1615 FALSE), /* pcrel_offset */
7f266840 1616
c19d1205
ZW		 1617 HOWTO (R_ARM_TLS_LDO12, /* type */
1618 0, /* rightshift */
1619 2, /* size (0 = byte, 1 = short, 2 = long) */
1620 12, /* bitsize */
1621 FALSE, /* pc_relative */
7f266840 1622 0, /* bitpos */
c19d1205 1623 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1624 bfd_elf_generic_reloc, /* special_function */
c19d1205 1625 "R_ARM_TLS_LDO12", /* name */
7f266840 1626 FALSE, /* partial_inplace */
c19d1205
ZW		 1627 0x00000fff, /* src_mask */
1628 0x00000fff, /* dst_mask */
1629 FALSE), /* pcrel_offset */
7f266840 1630
c19d1205
ZW		 1631 HOWTO (R_ARM_TLS_LE12, /* type */
1632 0, /* rightshift */
1633 2, /* size (0 = byte, 1 = short, 2 = long) */
1634 12, /* bitsize */
1635 FALSE, /* pc_relative */
7f266840 1636 0, /* bitpos */
c19d1205 1637 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1638 bfd_elf_generic_reloc, /* special_function */
c19d1205 1639 "R_ARM_TLS_LE12", /* name */
7f266840 1640 FALSE, /* partial_inplace */
c19d1205
ZW		 1641 0x00000fff, /* src_mask */
1642 0x00000fff, /* dst_mask */
1643 FALSE), /* pcrel_offset */
7f266840 1644
c19d1205 1645 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1646 0, /* rightshift */
1647 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1648 12, /* bitsize */
1649 FALSE, /* pc_relative */
7f266840 1650 0, /* bitpos */
c19d1205 1651 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1652 bfd_elf_generic_reloc, /* special_function */
c19d1205 1653 "R_ARM_TLS_IE12GP", /* name */
7f266840 1654 FALSE, /* partial_inplace */
c19d1205
ZW		 1655 0x00000fff, /* src_mask */
1656 0x00000fff, /* dst_mask */
1657 FALSE), /* pcrel_offset */
0855e32b 1658
34e77a92 1659 /* 112-127 private relocations. */
0855e32b
NS		 1660 EMPTY_HOWTO (112),
1661 EMPTY_HOWTO (113),
1662 EMPTY_HOWTO (114),
1663 EMPTY_HOWTO (115),
1664 EMPTY_HOWTO (116),
1665 EMPTY_HOWTO (117),
1666 EMPTY_HOWTO (118),
1667 EMPTY_HOWTO (119),
1668 EMPTY_HOWTO (120),
1669 EMPTY_HOWTO (121),
1670 EMPTY_HOWTO (122),
1671 EMPTY_HOWTO (123),
1672 EMPTY_HOWTO (124),
1673 EMPTY_HOWTO (125),
1674 EMPTY_HOWTO (126),
1675 EMPTY_HOWTO (127),
34e77a92
RS		 1676
1677 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1678 EMPTY_HOWTO (128),
1679
1680 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1681 0, /* rightshift */
1682 1, /* size (0 = byte, 1 = short, 2 = long) */
1683 0, /* bitsize */
1684 FALSE, /* pc_relative */
1685 0, /* bitpos */
1686 complain_overflow_bitfield,/* complain_on_overflow */
1687 bfd_elf_generic_reloc, /* special_function */
1688 "R_ARM_THM_TLS_DESCSEQ",/* name */
1689 FALSE, /* partial_inplace */
1690 0x00000000, /* src_mask */
1691 0x00000000, /* dst_mask */
1692 FALSE), /* pcrel_offset */
72d98d16
MG		 1693 EMPTY_HOWTO (130),
1694 EMPTY_HOWTO (131),
1695 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1696 0, /* rightshift. */
1697 1, /* size (0 = byte, 1 = short, 2 = long). */
1698 16, /* bitsize. */
1699 FALSE, /* pc_relative. */
1700 0, /* bitpos. */
1701 complain_overflow_bitfield,/* complain_on_overflow. */
1702 bfd_elf_generic_reloc, /* special_function. */
1703 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1704 FALSE, /* partial_inplace. */
1705 0x00000000, /* src_mask. */
1706 0x00000000, /* dst_mask. */
1707 FALSE), /* pcrel_offset. */
1708 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1709 0, /* rightshift. */
1710 1, /* size (0 = byte, 1 = short, 2 = long). */
1711 16, /* bitsize. */
1712 FALSE, /* pc_relative. */
1713 0, /* bitpos. */
1714 complain_overflow_bitfield,/* complain_on_overflow. */
1715 bfd_elf_generic_reloc, /* special_function. */
1716 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1717 FALSE, /* partial_inplace. */
1718 0x00000000, /* src_mask. */
1719 0x00000000, /* dst_mask. */
1720 FALSE), /* pcrel_offset. */
1721 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1722 0, /* rightshift. */
1723 1, /* size (0 = byte, 1 = short, 2 = long). */
1724 16, /* bitsize. */
1725 FALSE, /* pc_relative. */
1726 0, /* bitpos. */
1727 complain_overflow_bitfield,/* complain_on_overflow. */
1728 bfd_elf_generic_reloc, /* special_function. */
1729 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1730 FALSE, /* partial_inplace. */
1731 0x00000000, /* src_mask. */
1732 0x00000000, /* dst_mask. */
1733 FALSE), /* pcrel_offset. */
1734 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1735 0, /* rightshift. */
1736 1, /* size (0 = byte, 1 = short, 2 = long). */
1737 16, /* bitsize. */
1738 FALSE, /* pc_relative. */
1739 0, /* bitpos. */
1740 complain_overflow_bitfield,/* complain_on_overflow. */
1741 bfd_elf_generic_reloc, /* special_function. */
1742 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1743 FALSE, /* partial_inplace. */
1744 0x00000000, /* src_mask. */
1745 0x00000000, /* dst_mask. */
1746 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1747 /* Relocations for Armv8.1-M Mainline. */
1748 HOWTO (R_ARM_THM_BF16, /* type. */
1749 0, /* rightshift. */
1750 1, /* size (0 = byte, 1 = short, 2 = long). */
1751 16, /* bitsize. */
1752 TRUE, /* pc_relative. */
1753 0, /* bitpos. */
1754 complain_overflow_dont,/* do not complain_on_overflow. */
1755 bfd_elf_generic_reloc, /* special_function. */
1756 "R_ARM_THM_BF16", /* name. */
1757 FALSE, /* partial_inplace. */
1758 0x001f0ffe, /* src_mask. */
1759 0x001f0ffe, /* dst_mask. */
1760 TRUE), /* pcrel_offset. */
1889da70
AV		 1761 HOWTO (R_ARM_THM_BF12, /* type. */
1762 0, /* rightshift. */
1763 1, /* size (0 = byte, 1 = short, 2 = long). */
1764 12, /* bitsize. */
1765 TRUE, /* pc_relative. */
1766 0, /* bitpos. */
1767 complain_overflow_dont,/* do not complain_on_overflow. */
1768 bfd_elf_generic_reloc, /* special_function. */
1769 "R_ARM_THM_BF12", /* name. */
1770 FALSE, /* partial_inplace. */
1771 0x00010ffe, /* src_mask. */
1772 0x00010ffe, /* dst_mask. */
1773 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1774 HOWTO (R_ARM_THM_BF18, /* type. */
1775 0, /* rightshift. */
1776 1, /* size (0 = byte, 1 = short, 2 = long). */
1777 18, /* bitsize. */
1778 TRUE, /* pc_relative. */
1779 0, /* bitpos. */
1780 complain_overflow_dont,/* do not complain_on_overflow. */
1781 bfd_elf_generic_reloc, /* special_function. */
1782 "R_ARM_THM_BF18", /* name. */
1783 FALSE, /* partial_inplace. */
1784 0x007f0ffe, /* src_mask. */
1785 0x007f0ffe, /* dst_mask. */
1786 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1787};
1788
34e77a92 1789/* 160 onwards: */
5c5a4843 1790static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1791{
1792 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1793 0, /* rightshift */
1794 2, /* size (0 = byte, 1 = short, 2 = long) */
1795 32, /* bitsize */
1796 FALSE, /* pc_relative */
1797 0, /* bitpos */
99059e56
RM		 1798 complain_overflow_bitfield,/* complain_on_overflow */
1799 bfd_elf_generic_reloc, /* special_function */
1800 "R_ARM_IRELATIVE", /* name */
1801 TRUE, /* partial_inplace */
1802 0xffffffff, /* src_mask */
1803 0xffffffff, /* dst_mask */
188fd7ae
CL		 1804 FALSE), /* pcrel_offset */
1805 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1806 0, /* rightshift */
1807 2, /* size (0 = byte, 1 = short, 2 = long) */
1808 32, /* bitsize */
1809 FALSE, /* pc_relative */
1810 0, /* bitpos */
1811 complain_overflow_bitfield,/* complain_on_overflow */
1812 bfd_elf_generic_reloc, /* special_function */
1813 "R_ARM_GOTFUNCDESC", /* name */
1814 FALSE, /* partial_inplace */
1815 0, /* src_mask */
1816 0xffffffff, /* dst_mask */
1817 FALSE), /* pcrel_offset */
1818 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1819 0, /* rightshift */
1820 2, /* size (0 = byte, 1 = short, 2 = long) */
1821 32, /* bitsize */
1822 FALSE, /* pc_relative */
1823 0, /* bitpos */
1824 complain_overflow_bitfield,/* complain_on_overflow */
1825 bfd_elf_generic_reloc, /* special_function */
1826 "R_ARM_GOTOFFFUNCDESC",/* name */
1827 FALSE, /* partial_inplace */
1828 0, /* src_mask */
1829 0xffffffff, /* dst_mask */
1830 FALSE), /* pcrel_offset */
1831 HOWTO (R_ARM_FUNCDESC, /* type */
1832 0, /* rightshift */
1833 2, /* size (0 = byte, 1 = short, 2 = long) */
1834 32, /* bitsize */
1835 FALSE, /* pc_relative */
1836 0, /* bitpos */
1837 complain_overflow_bitfield,/* complain_on_overflow */
1838 bfd_elf_generic_reloc, /* special_function */
1839 "R_ARM_FUNCDESC", /* name */
1840 FALSE, /* partial_inplace */
1841 0, /* src_mask */
1842 0xffffffff, /* dst_mask */
1843 FALSE), /* pcrel_offset */
1844 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1845 0, /* rightshift */
1846 2, /* size (0 = byte, 1 = short, 2 = long) */
1847 64, /* bitsize */
1848 FALSE, /* pc_relative */
1849 0, /* bitpos */
1850 complain_overflow_bitfield,/* complain_on_overflow */
1851 bfd_elf_generic_reloc, /* special_function */
1852 "R_ARM_FUNCDESC_VALUE",/* name */
1853 FALSE, /* partial_inplace */
1854 0, /* src_mask */
1855 0xffffffff, /* dst_mask */
1856 FALSE), /* pcrel_offset */
5c5a4843
CL		 1857 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1858 0, /* rightshift */
1859 2, /* size (0 = byte, 1 = short, 2 = long) */
1860 32, /* bitsize */
1861 FALSE, /* pc_relative */
1862 0, /* bitpos */
1863 complain_overflow_bitfield,/* complain_on_overflow */
1864 bfd_elf_generic_reloc, /* special_function */
1865 "R_ARM_TLS_GD32_FDPIC",/* name */
1866 FALSE, /* partial_inplace */
1867 0, /* src_mask */
1868 0xffffffff, /* dst_mask */
1869 FALSE), /* pcrel_offset */
1870 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1871 0, /* rightshift */
1872 2, /* size (0 = byte, 1 = short, 2 = long) */
1873 32, /* bitsize */
1874 FALSE, /* pc_relative */
1875 0, /* bitpos */
1876 complain_overflow_bitfield,/* complain_on_overflow */
1877 bfd_elf_generic_reloc, /* special_function */
1878 "R_ARM_TLS_LDM32_FDPIC",/* name */
1879 FALSE, /* partial_inplace */
1880 0, /* src_mask */
1881 0xffffffff, /* dst_mask */
1882 FALSE), /* pcrel_offset */
1883 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1884 0, /* rightshift */
1885 2, /* size (0 = byte, 1 = short, 2 = long) */
1886 32, /* bitsize */
1887 FALSE, /* pc_relative */
1888 0, /* bitpos */
1889 complain_overflow_bitfield,/* complain_on_overflow */
1890 bfd_elf_generic_reloc, /* special_function */
1891 "R_ARM_TLS_IE32_FDPIC",/* name */
1892 FALSE, /* partial_inplace */
1893 0, /* src_mask */
1894 0xffffffff, /* dst_mask */
1895 FALSE), /* pcrel_offset */
34e77a92 1896};
c19d1205 1897
34e77a92
RS		 1898/* 249-255 extended, currently unused, relocations: */
1899static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1900{
1901 HOWTO (R_ARM_RREL32, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RREL32", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RABS32, /* type */
1916 0, /* rightshift */
1917 0, /* size (0 = byte, 1 = short, 2 = long) */
1918 0, /* bitsize */
1919 FALSE, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RABS32", /* name */
1924 FALSE, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 FALSE), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RPC24, /* type */
1930 0, /* rightshift */
1931 0, /* size (0 = byte, 1 = short, 2 = long) */
1932 0, /* bitsize */
1933 FALSE, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RPC24", /* name */
1938 FALSE, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 FALSE), /* pcrel_offset */
1942
1943 HOWTO (R_ARM_RBASE, /* type */
1944 0, /* rightshift */
1945 0, /* size (0 = byte, 1 = short, 2 = long) */
1946 0, /* bitsize */
1947 FALSE, /* pc_relative */
1948 0, /* bitpos */
1949 complain_overflow_dont,/* complain_on_overflow */
1950 bfd_elf_generic_reloc, /* special_function */
1951 "R_ARM_RBASE", /* name */
1952 FALSE, /* partial_inplace */
1953 0, /* src_mask */
1954 0, /* dst_mask */
1955 FALSE) /* pcrel_offset */
1956};
1957
1958static reloc_howto_type *
1959elf32_arm_howto_from_type (unsigned int r_type)
1960{
906e58ca 1961 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1962 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1963
188fd7ae
CL		 1964 if (r_type >= R_ARM_IRELATIVE
1965 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1966 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1967
c19d1205 1968 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1969 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1970 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1971
c19d1205 1972 return NULL;
7f266840
DJ		 1973}
1974
f3185997
NC		 1975static bfd_boolean
1976elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1977 Elf_Internal_Rela * elf_reloc)
1978{
1979 unsigned int r_type;
1980
1981 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1982 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1983 {
1984 /* xgettext:c-format */
1985 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1986 abfd, r_type);
1987 bfd_set_error (bfd_error_bad_value);
1988 return FALSE;
1989 }
1990 return TRUE;
7f266840
DJ		 1991}
1992
1993struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1996 unsigned char elf_reloc_val;
7f266840
DJ		 1997 };
1998
1999/* All entries in this list must also be present in elf32_arm_howto_table. */
2000static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
2001 {
07d6d2b8 2002 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2003 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2004 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2005 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2006 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2007 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2008 {BFD_RELOC_32, R_ARM_ABS32},
2009 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2010 {BFD_RELOC_8, R_ARM_ABS8},
2011 {BFD_RELOC_16, R_ARM_ABS16},
2012 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2013 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2014 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2018 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2019 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2020 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2021 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2022 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2023 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2024 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2025 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2026 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2027 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2028 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2029 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2030 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2031 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2032 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2033 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2034 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2035 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2038 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2039 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2040 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2041 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2042 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2043 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2044 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2045 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2046 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2047 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2048 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2049 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2050 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2051 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2052 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2053 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2054 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2055 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2056 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2057 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2058 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2059 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2060 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2061 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2062 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2064 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2065 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2066 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2068 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2069 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2070 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2071 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2072 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2073 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2074 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2075 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2076 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2077 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2078 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2079 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2080 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2082 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2083 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2084 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2085 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2086 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2087 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2088 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2089 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2090 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2091 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2092 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2093 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2094 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2097 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2098 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2100 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2101 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2102 };
2103
2104static reloc_howto_type *
f1c71a59
ZW		 2105elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2106 bfd_reloc_code_real_type code)
7f266840
DJ		 2107{
2108 unsigned int i;
8029a119 2109
906e58ca 2110 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2111 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2112 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2113
c19d1205 2114 return NULL;
7f266840
DJ		 2115}
2116
157090f7
AM		 2117static reloc_howto_type *
2118elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2119 const char *r_name)
2120{
2121 unsigned int i;
2122
906e58ca 2123 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2124 if (elf32_arm_howto_table_1[i].name != NULL
2125 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2126 return &elf32_arm_howto_table_1[i];
2127
906e58ca 2128 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2129 if (elf32_arm_howto_table_2[i].name != NULL
2130 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2131 return &elf32_arm_howto_table_2[i];
2132
34e77a92
RS		 2133 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2134 if (elf32_arm_howto_table_3[i].name != NULL
2135 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2136 return &elf32_arm_howto_table_3[i];
2137
157090f7
AM		 2138 return NULL;
2139}
2140
906e58ca
NC		 2141/* Support for core dump NOTE sections. */
2142
7f266840 2143static bfd_boolean
f1c71a59 2144elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2145{
2146 int offset;
2147 size_t size;
2148
2149 switch (note->descsz)
2150 {
2151 default:
2152 return FALSE;
2153
8029a119 2154 case 148: /* Linux/ARM 32-bit. */
7f266840 2155 /* pr_cursig */
228e534f 2156 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2157
2158 /* pr_pid */
228e534f 2159 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2160
2161 /* pr_reg */
2162 offset = 72;
2163 size = 72;
2164
2165 break;
2166 }
2167
2168 /* Make a ".reg/999" section. */
2169 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2170 size, note->descpos + offset);
2171}
2172
2173static bfd_boolean
f1c71a59 2174elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2175{
2176 switch (note->descsz)
2177 {
2178 default:
2179 return FALSE;
2180
8029a119 2181 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2182 elf_tdata (abfd)->core->pid
4395ee08 2183 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2184 elf_tdata (abfd)->core->program
7f266840 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2186 elf_tdata (abfd)->core->command
7f266840
DJ		 2187 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2188 }
2189
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
7f266840 2193 {
228e534f 2194 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2195 int n = strlen (command);
2196
2197 if (0 < n && command[n - 1] == ' ')
2198 command[n - 1] = '\0';
2199 }
2200
2201 return TRUE;
2202}
2203
1f20dca5
UW		 2204static char *
2205elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2206 int note_type, ...)
2207{
2208 switch (note_type)
2209 {
2210 default:
2211 return NULL;
2212
2213 case NT_PRPSINFO:
2214 {
602f1657 2215 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2216 va_list ap;
2217
2218 va_start (ap, note_type);
2219 memset (data, 0, sizeof (data));
2220 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2221#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2222 DIAGNOSTIC_PUSH;
be3e27bb 2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
95da9854
L		 2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228#endif
1f20dca5 2229 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2230#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2231 DIAGNOSTIC_POP;
fe75810f 2232#endif
1f20dca5
UW		 2233 va_end (ap);
2234
2235 return elfcore_write_note (abfd, buf, bufsiz,
2236 "CORE", note_type, data, sizeof (data));
2237 }
2238
2239 case NT_PRSTATUS:
2240 {
2241 char data[148];
2242 va_list ap;
2243 long pid;
2244 int cursig;
2245 const void *greg;
2246
2247 va_start (ap, note_type);
2248 memset (data, 0, sizeof (data));
2249 pid = va_arg (ap, long);
2250 bfd_put_32 (abfd, pid, data + 24);
2251 cursig = va_arg (ap, int);
2252 bfd_put_16 (abfd, cursig, data + 12);
2253 greg = va_arg (ap, const void *);
2254 memcpy (data + 72, greg, 72);
2255 va_end (ap);
2256
2257 return elfcore_write_note (abfd, buf, bufsiz,
2258 "CORE", note_type, data, sizeof (data));
2259 }
2260 }
2261}
2262
07d6d2b8
AM		 2263#define TARGET_LITTLE_SYM arm_elf32_le_vec
2264#define TARGET_LITTLE_NAME "elf32-littlearm"
2265#define TARGET_BIG_SYM arm_elf32_be_vec
2266#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2267
2268#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2270#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2271
252b5132
RH		 2272typedef unsigned long int insn32;
2273typedef unsigned short int insn16;
2274
3a4a14e9
PB		 2275/* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
57e8b36a 2277#define INTERWORK_FLAG(abfd) \
3a4a14e9 2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2281
252b5132
RH		 2282/* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
9b485d32 2285 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2286#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2287#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2288
2289#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2290#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2291
c7b8f16e
JB		 2292#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2293#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2294
a504d23a
LA		 2295#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2296#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2297
845b51d6
PB		 2298#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2299#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2300
7413f23f
DJ		 2301#define STUB_ENTRY_NAME "__%s_veneer"
2302
4ba2ef8f
TP		 2303#define CMSE_PREFIX "__acle_se_"
2304
4d83e8d9
CL		 2305#define CMSE_STUB_NAME ".gnu.sgstubs"
2306
252b5132
RH		 2307/* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2309#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2310
cb10292c
CL		 2311/* FDPIC default stack size. */
2312#define DEFAULT_STACK_SIZE 0x8000
2313
0855e32b 2314static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2315{
2316 0xe08e0000, /* add r0, lr, r0 */
2317 0xe5901004, /* ldr r1, [r0,#4] */
2318 0xe12fff11, /* bx r1 */
2319};
0855e32b
NS		 2320
2321static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2322{
2323 0xe52d2004, /* push {r2} */
2324 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2325 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2326 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2327 0xe081100f, /* 2: add r1, pc */
2328 0xe12fff12, /* bx r2 */
2329 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2330 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2331 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2332};
0855e32b 2333
b4e87f2c
TC		 2334/* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2338
7801f98f
CL		 2339/* ARM FDPIC PLT entry. */
2340/* The last 5 words contain PLT lazy fragment code and data. */
2341static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2342 {
2343 0xe59fc008, /* ldr r12, .L1 */
2344 0xe08cc009, /* add r12, r12, r9 */
2345 0xe59c9004, /* ldr r9, [r12, #4] */
2346 0xe59cf000, /* ldr pc, [r12] */
2347 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2348 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2349 0xe51fc00c, /* ldr r12, [pc, #-12] */
2350 0xe92d1000, /* push {r12} */
2351 0xe599c004, /* ldr r12, [r9, #4] */
2352 0xe599f000, /* ldr pc, [r9] */
2353 };
2354
59029f57
CL		 2355/* Thumb FDPIC PLT entry. */
2356/* The last 5 words contain PLT lazy fragment code and data. */
2357static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2358 {
2359 0xc00cf8df, /* ldr.w r12, .L1 */
2360 0x0c09eb0c, /* add.w r12, r12, r9 */
2361 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2362 0xf000f8dc, /* ldr.w pc, [r12] */
2363 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2364 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2365 0xc008f85f, /* ldr.w r12, .L2 */
2366 0xcd04f84d, /* push {r12} */
2367 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2368 0xf000f8d9, /* ldr.w pc, [r9] */
2369 };
2370
5e681ec4
PB		 2371#ifdef FOUR_WORD_PLT
2372
252b5132
RH		 2373/* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
59f2c4e7 2375 called before the relocation has been set up calls the dynamic
9b485d32 2376 linker first. */
e5a52504 2377static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2378{
2379 0xe52de004, /* str lr, [sp, #-4]! */
2380 0xe59fe010, /* ldr lr, [pc, #16] */
2381 0xe08fe00e, /* add lr, pc, lr */
2382 0xe5bef008, /* ldr pc, [lr, #8]! */
2383};
5e681ec4
PB		 2384
2385/* Subsequent entries in a procedure linkage table look like
2386 this. */
e5a52504 2387static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2388{
2389 0xe28fc600, /* add ip, pc, #NN */
2390 0xe28cca00, /* add ip, ip, #NN */
2391 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2392 0x00000000, /* unused */
2393};
5e681ec4 2394
eed94f8f 2395#else /* not FOUR_WORD_PLT */
5e681ec4 2396
5e681ec4
PB		 2397/* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
e5a52504 2401static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2402{
07d6d2b8
AM		 2403 0xe52de004, /* str lr, [sp, #-4]! */
2404 0xe59fe004, /* ldr lr, [pc, #4] */
2405 0xe08fe00e, /* add lr, pc, lr */
2406 0xe5bef008, /* ldr pc, [lr, #8]! */
2407 0x00000000, /* &GOT[0] - . */
b38cadfb 2408};
252b5132 2409
1db37fe6
YG		 2410/* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2412static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2413{
2414 0xe28fc600, /* add ip, pc, #0xNN00000 */
2415 0xe28cca00, /* add ip, ip, #0xNN000 */
2416 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2417};
5e681ec4 2418
1db37fe6
YG		 2419/* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2421static const bfd_vma elf32_arm_plt_entry_long [] =
2422{
07d6d2b8
AM		 2423 0xe28fc200, /* add ip, pc, #0xN0000000 */
2424 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2425 0xe28cca00, /* add ip, ip, #0xNN000 */
2426 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2427};
2428
2429static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2430
eed94f8f
NC		 2431#endif /* not FOUR_WORD_PLT */
2432
2433/* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2436static const bfd_vma elf32_thumb2_plt0_entry [] =
2437{
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2440 0xf8dfb500, /* push {lr} */
2441 0x44fee008, /* ldr.w lr, [pc, #8] */
2442 /* add lr, pc */
eed94f8f 2443 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2444 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2445};
2446
2447/* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2449static const bfd_vma elf32_thumb2_plt_entry [] =
2450{
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2453 0x0c00f240, /* movw ip, #0xNNNN */
2454 0x0c00f2c0, /* movt ip, #0xNNNN */
2455 0xf8dc44fc, /* add ip, pc */
15ccbdd7
TC		 2456 0xe7fcf000 /* ldr.w pc, [ip] */
2457 /* b .-4 */
eed94f8f 2458};
252b5132 2459
00a97672
RS		 2460/* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2462static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2463{
07d6d2b8
AM		 2464 0xe52dc008, /* str ip,[sp,#-8]! */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe59cf008, /* ldr pc,[ip,#8] */
2467 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2468};
00a97672
RS		 2469
2470/* The format of subsequent entries in a VxWorks executable. */
2471static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2472{
07d6d2b8
AM		 2473 0xe59fc000, /* ldr ip,[pc] */
2474 0xe59cf000, /* ldr pc,[ip] */
2475 0x00000000, /* .long @got */
2476 0xe59fc000, /* ldr ip,[pc] */
2477 0xea000000, /* b _PLT */
2478 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2479};
00a97672
RS		 2480
2481/* The format of entries in a VxWorks shared library. */
2482static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2483{
07d6d2b8
AM		 2484 0xe59fc000, /* ldr ip,[pc] */
2485 0xe79cf009, /* ldr pc,[ip,r9] */
2486 0x00000000, /* .long @got */
2487 0xe59fc000, /* ldr ip,[pc] */
2488 0xe599f008, /* ldr pc,[r9,#8] */
2489 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2490};
00a97672 2491
b7693d02
DJ		 2492/* An initial stub used if the PLT entry is referenced from Thumb code. */
2493#define PLT_THUMB_STUB_SIZE 4
2494static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2495{
2496 0x4778, /* bx pc */
b4e87f2c 2497 0xe7fd /* b .-2 */
b38cadfb 2498};
b7693d02 2499
e5a52504
MM		 2500/* The entries in a PLT when using a DLL-based target with multiple
2501 address spaces. */
906e58ca 2502static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2503{
07d6d2b8
AM		 2504 0xe51ff004, /* ldr pc, [pc, #-4] */
2505 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2506};
2507
2508/* The first entry in a procedure linkage table looks like
2509 this. It is set up so that any shared library function that is
2510 called before the relocation has been set up calls the dynamic
2511 linker first. */
2512static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2513{
2514 /* First bundle: */
2515 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2516 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2517 0xe08cc00f, /* add ip, ip, pc */
2518 0xe52dc008, /* str ip, [sp, #-8]! */
2519 /* Second bundle: */
edccdf7c
RM		 2520 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2521 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2522 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2523 0xe12fff1c, /* bx ip */
b38cadfb 2524 /* Third bundle: */
edccdf7c
RM		 2525 0xe320f000, /* nop */
2526 0xe320f000, /* nop */
2527 0xe320f000, /* nop */
b38cadfb
NC		 2528 /* .Lplt_tail: */
2529 0xe50dc004, /* str ip, [sp, #-4] */
2530 /* Fourth bundle: */
edccdf7c
RM		 2531 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2532 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2533 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2534 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2535};
2536#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2537
2538/* Subsequent entries in a procedure linkage table look like this. */
2539static const bfd_vma elf32_arm_nacl_plt_entry [] =
2540{
2541 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2542 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2543 0xe08cc00f, /* add ip, ip, pc */
2544 0xea000000, /* b .Lplt_tail */
2545};
e5a52504 2546
906e58ca
NC		 2547#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2548#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2549#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2550#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2551#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2552#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2553#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2554#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2555
461a49ca 2556enum stub_insn_type
b38cadfb
NC		 2557{
2558 THUMB16_TYPE = 1,
2559 THUMB32_TYPE,
2560 ARM_TYPE,
2561 DATA_TYPE
2562};
461a49ca 2563
48229727
JB		 2564#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2565/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2566 is inserted in arm_build_one_stub(). */
2567#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2568#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2569#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2570#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2571#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2572#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2573#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2574#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2575
2576typedef struct
2577{
07d6d2b8 2578 bfd_vma data;
b38cadfb 2579 enum stub_insn_type type;
07d6d2b8
AM		 2580 unsigned int r_type;
2581 int reloc_addend;
461a49ca
DJ		 2582} insn_sequence;
2583
b4e87f2c
TC		 2584/* See note [Thumb nop sequence] when adding a veneer. */
2585
fea2b4d6
CL		 2586/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2587 to reach the stub if necessary. */
461a49ca 2588static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2589{
07d6d2b8 2590 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2591 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2592};
906e58ca 2593
fea2b4d6
CL		 2594/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2595 available. */
461a49ca 2596static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2597{
07d6d2b8
AM		 2598 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2599 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2600 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2601};
906e58ca 2602
d3626fb0 2603/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2604static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2605{
07d6d2b8
AM		 2606 THUMB16_INSN (0xb401), /* push {r0} */
2607 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2608 THUMB16_INSN (0x4684), /* mov ip, r0 */
2609 THUMB16_INSN (0xbc01), /* pop {r0} */
2610 THUMB16_INSN (0x4760), /* bx ip */
2611 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2612 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2613};
906e58ca 2614
80c135e5
TP		 2615/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2616static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2617{
07d6d2b8 2618 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2619 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2620};
2621
d5a67c02
AV		 2622/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2623 M-profile architectures. */
2624static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2625{
2626 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2627 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2628 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2629};
2630
d3626fb0
CL		 2631/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2632 allowed. */
2633static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2634{
07d6d2b8 2635 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2636 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2637 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2638 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2639 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2640};
d3626fb0 2641
fea2b4d6
CL		 2642/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2643 available. */
461a49ca 2644static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2645{
07d6d2b8 2646 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2647 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2648 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2649 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2650};
906e58ca 2651
fea2b4d6
CL		 2652/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2653 one, when the destination is close enough. */
461a49ca 2654static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2655{
07d6d2b8 2656 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2657 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2658 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2659};
c820be07 2660
cf3eccff 2661/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2662 blx to reach the stub if necessary. */
cf3eccff 2663static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2666 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2667 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2668};
906e58ca 2669
cf3eccff
DJ		 2670/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2671 blx to reach the stub if necessary. We can not add into pc;
2672 it is not guaranteed to mode switch (different in ARMv6 and
2673 ARMv7). */
2674static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2677 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2678 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2679 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2680};
cf3eccff 2681
ebe24dd4
CL		 2682/* V4T ARM -> ARM long branch stub, PIC. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2684{
07d6d2b8
AM		 2685 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2686 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2687 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2688 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2689};
ebe24dd4
CL		 2690
2691/* V4T Thumb -> ARM long branch stub, PIC. */
2692static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2693{
07d6d2b8 2694 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2695 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2696 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2697 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2698 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2699};
ebe24dd4 2700
d3626fb0
CL		 2701/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2702 architectures. */
ebe24dd4 2703static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2704{
07d6d2b8
AM		 2705 THUMB16_INSN (0xb401), /* push {r0} */
2706 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2707 THUMB16_INSN (0x46fc), /* mov ip, pc */
2708 THUMB16_INSN (0x4484), /* add ip, r0 */
2709 THUMB16_INSN (0xbc01), /* pop {r0} */
2710 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2711 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2712};
ebe24dd4 2713
d3626fb0
CL		 2714/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2715 allowed. */
2716static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2717{
07d6d2b8 2718 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2719 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2720 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2721 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2722 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2723 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2724};
d3626fb0 2725
0855e32b
NS		 2726/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2727 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2728static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2729{
07d6d2b8
AM		 2730 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2731 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2732 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2733};
2734
2735/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2736 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2737static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2738{
07d6d2b8 2739 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2740 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2741 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2742 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2743 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2744};
2745
7a89b94e
NC		 2746/* NaCl ARM -> ARM long branch stub. */
2747static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2748{
2749 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2750 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2751 ARM_INSN (0xe12fff1c), /* bx ip */
2752 ARM_INSN (0xe320f000), /* nop */
2753 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2754 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2755 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2756 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2757};
2758
2759/* NaCl ARM -> ARM long branch stub, PIC. */
2760static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2761{
2762 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2763 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2764 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2765 ARM_INSN (0xe12fff1c), /* bx ip */
2766 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2767 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2768 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2769 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2770};
2771
4ba2ef8f
TP		 2772/* Stub used for transition to secure state (aka SG veneer). */
2773static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2774{
2775 THUMB32_INSN (0xe97fe97f), /* sg. */
2776 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2777};
2778
7a89b94e 2779
48229727
JB		 2780/* Cortex-A8 erratum-workaround stubs. */
2781
2782/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2783 can't use a conditional branch to reach this stub). */
2784
2785static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2786{
07d6d2b8 2787 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2788 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2789 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2790};
48229727
JB		 2791
2792/* Stub used for b.w and bl.w instructions. */
2793
2794static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2795{
2796 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2797};
48229727
JB		 2798
2799static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2800{
2801 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2802};
48229727
JB		 2803
2804/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2805 instruction (which switches to ARM mode) to point to this stub. Jump to the
2806 real destination using an ARM-mode branch. */
2807
2808static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2809{
2810 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2811};
48229727 2812
9553db3c
NC		 2813/* For each section group there can be a specially created linker section
2814 to hold the stubs for that group. The name of the stub section is based
2815 upon the name of another section within that group with the suffix below
2816 applied.
2817
2818 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2819 create what appeared to be a linker stub section when it actually
2820 contained user code/data. For example, consider this fragment:
b38cadfb 2821
9553db3c
NC		 2822 const char * stubborn_problems[] = { "np" };
2823
2824 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2825 section called:
2826
2827 .data.rel.local.stubborn_problems
2828
2829 This then causes problems in arm32_arm_build_stubs() as it triggers:
2830
2831 // Ignore non-stub sections.
2832 if (!strstr (stub_sec->name, STUB_SUFFIX))
2833 continue;
2834
2835 And so the section would be ignored instead of being processed. Hence
2836 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2837 C identifier. */
2838#define STUB_SUFFIX ".__stub"
906e58ca 2839
738a79f6
CL		 2840/* One entry per long/short branch stub defined above. */
2841#define DEF_STUBS \
2842 DEF_STUB(long_branch_any_any) \
2843 DEF_STUB(long_branch_v4t_arm_thumb) \
2844 DEF_STUB(long_branch_thumb_only) \
2845 DEF_STUB(long_branch_v4t_thumb_thumb) \
2846 DEF_STUB(long_branch_v4t_thumb_arm) \
2847 DEF_STUB(short_branch_v4t_thumb_arm) \
2848 DEF_STUB(long_branch_any_arm_pic) \
2849 DEF_STUB(long_branch_any_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2851 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2852 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2853 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2854 DEF_STUB(long_branch_any_tls_pic) \
2855 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2856 DEF_STUB(long_branch_arm_nacl) \
2857 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2858 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2859 DEF_STUB(a8_veneer_b_cond) \
2860 DEF_STUB(a8_veneer_b) \
2861 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2862 DEF_STUB(a8_veneer_blx) \
2863 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2864 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2865
2866#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2867enum elf32_arm_stub_type
2868{
906e58ca 2869 arm_stub_none,
738a79f6 2870 DEF_STUBS
4f4faa4d 2871 max_stub_type
738a79f6
CL		 2872};
2873#undef DEF_STUB
2874
8d9d9490
TP		 2875/* Note the first a8_veneer type. */
2876const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2877
738a79f6
CL		 2878typedef struct
2879{
d3ce72d0 2880 const insn_sequence* template_sequence;
738a79f6
CL		 2881 int template_size;
2882} stub_def;
2883
2884#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2885static const stub_def stub_definitions[] =
2886{
738a79f6
CL		 2887 {NULL, 0},
2888 DEF_STUBS
906e58ca
NC		 2889};
2890
2891struct elf32_arm_stub_hash_entry
2892{
2893 /* Base hash table entry structure. */
2894 struct bfd_hash_entry root;
2895
2896 /* The stub section. */
2897 asection *stub_sec;
2898
2899 /* Offset within stub_sec of the beginning of this stub. */
2900 bfd_vma stub_offset;
2901
2902 /* Given the symbol's value and its section we can determine its final
2903 value when building the stubs (so the stub knows where to jump). */
2904 bfd_vma target_value;
2905 asection *target_section;
2906
8d9d9490
TP		 2907 /* Same as above but for the source of the branch to the stub. Used for
2908 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2909 such, source section does not need to be recorded since Cortex-A8 erratum
2910 workaround stubs are only generated when both source and target are in the
2911 same section. */
2912 bfd_vma source_value;
48229727
JB		 2913
2914 /* The instruction which caused this stub to be generated (only valid for
2915 Cortex-A8 erratum workaround stubs at present). */
2916 unsigned long orig_insn;
2917
461a49ca 2918 /* The stub type. */
906e58ca 2919 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2920 /* Its encoding size in bytes. */
2921 int stub_size;
2922 /* Its template. */
2923 const insn_sequence *stub_template;
2924 /* The size of the template (number of entries). */
2925 int stub_template_size;
906e58ca
NC		 2926
2927 /* The symbol table entry, if any, that this was derived from. */
2928 struct elf32_arm_link_hash_entry *h;
2929
35fc36a8
RS		 2930 /* Type of branch. */
2931 enum arm_st_branch_type branch_type;
906e58ca
NC		 2932
2933 /* Where this stub is being called from, or, in the case of combined
2934 stub sections, the first input section in the group. */
2935 asection *id_sec;
7413f23f
DJ		 2936
2937 /* The name for the local symbol at the start of this stub. The
2938 stub name in the hash table has to be unique; this does not, so
2939 it can be friendlier. */
2940 char *output_name;
906e58ca
NC		 2941};
2942
e489d0ae
PB		 2943/* Used to build a map of a section. This is required for mixed-endian
2944 code/data. */
2945
2946typedef struct elf32_elf_section_map
2947{
2948 bfd_vma vma;
2949 char type;
2950}
2951elf32_arm_section_map;
2952
c7b8f16e
JB		 2953/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2954
2955typedef enum
2956{
2957 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2958 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2959 VFP11_ERRATUM_ARM_VENEER,
2960 VFP11_ERRATUM_THUMB_VENEER
2961}
2962elf32_vfp11_erratum_type;
2963
2964typedef struct elf32_vfp11_erratum_list
2965{
2966 struct elf32_vfp11_erratum_list *next;
2967 bfd_vma vma;
2968 union
2969 {
2970 struct
2971 {
2972 struct elf32_vfp11_erratum_list *veneer;
2973 unsigned int vfp_insn;
2974 } b;
2975 struct
2976 {
2977 struct elf32_vfp11_erratum_list *branch;
2978 unsigned int id;
2979 } v;
2980 } u;
2981 elf32_vfp11_erratum_type type;
2982}
2983elf32_vfp11_erratum_list;
2984
a504d23a
LA		 2985/* Information about a STM32L4XX erratum veneer, or a branch to such a
2986 veneer. */
2987typedef enum
2988{
2989 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2990 STM32L4XX_ERRATUM_VENEER
2991}
2992elf32_stm32l4xx_erratum_type;
2993
2994typedef struct elf32_stm32l4xx_erratum_list
2995{
2996 struct elf32_stm32l4xx_erratum_list *next;
2997 bfd_vma vma;
2998 union
2999 {
3000 struct
3001 {
3002 struct elf32_stm32l4xx_erratum_list *veneer;
3003 unsigned int insn;
3004 } b;
3005 struct
3006 {
3007 struct elf32_stm32l4xx_erratum_list *branch;
3008 unsigned int id;
3009 } v;
3010 } u;
3011 elf32_stm32l4xx_erratum_type type;
3012}
3013elf32_stm32l4xx_erratum_list;
3014
2468f9c9
PB		 3015typedef enum
3016{
3017 DELETE_EXIDX_ENTRY,
3018 INSERT_EXIDX_CANTUNWIND_AT_END
3019}
3020arm_unwind_edit_type;
3021
3022/* A (sorted) list of edits to apply to an unwind table. */
3023typedef struct arm_unwind_table_edit
3024{
3025 arm_unwind_edit_type type;
3026 /* Note: we sometimes want to insert an unwind entry corresponding to a
3027 section different from the one we're currently writing out, so record the
3028 (text) section this edit relates to here. */
3029 asection *linked_section;
3030 unsigned int index;
3031 struct arm_unwind_table_edit *next;
3032}
3033arm_unwind_table_edit;
3034
8e3de13a 3035typedef struct _arm_elf_section_data
e489d0ae 3036{
2468f9c9 3037 /* Information about mapping symbols. */
e489d0ae 3038 struct bfd_elf_section_data elf;
8e3de13a 3039 unsigned int mapcount;
c7b8f16e 3040 unsigned int mapsize;
e489d0ae 3041 elf32_arm_section_map *map;
2468f9c9 3042 /* Information about CPU errata. */
c7b8f16e
JB		 3043 unsigned int erratumcount;
3044 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3045 unsigned int stm32l4xx_erratumcount;
3046 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3047 unsigned int additional_reloc_count;
2468f9c9
PB		 3048 /* Information about unwind tables. */
3049 union
3050 {
3051 /* Unwind info attached to a text section. */
3052 struct
3053 {
3054 asection *arm_exidx_sec;
3055 } text;
3056
3057 /* Unwind info attached to an .ARM.exidx section. */
3058 struct
3059 {
3060 arm_unwind_table_edit *unwind_edit_list;
3061 arm_unwind_table_edit *unwind_edit_tail;
3062 } exidx;
3063 } u;
8e3de13a
NC		 3064}
3065_arm_elf_section_data;
e489d0ae
PB		 3066
3067#define elf32_arm_section_data(sec) \
8e3de13a 3068 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3069
48229727
JB		 3070/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3071 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3072 so may be created multiple times: we use an array of these entries whilst
3073 relaxing which we can refresh easily, then create stubs for each potentially
3074 erratum-triggering instruction once we've settled on a solution. */
3075
b38cadfb
NC		 3076struct a8_erratum_fix
3077{
48229727
JB		 3078 bfd *input_bfd;
3079 asection *section;
3080 bfd_vma offset;
8d9d9490 3081 bfd_vma target_offset;
48229727
JB		 3082 unsigned long orig_insn;
3083 char *stub_name;
3084 enum elf32_arm_stub_type stub_type;
35fc36a8 3085 enum arm_st_branch_type branch_type;
48229727
JB		 3086};
3087
3088/* A table of relocs applied to branches which might trigger Cortex-A8
3089 erratum. */
3090
b38cadfb
NC		 3091struct a8_erratum_reloc
3092{
48229727
JB		 3093 bfd_vma from;
3094 bfd_vma destination;
92750f34
DJ		 3095 struct elf32_arm_link_hash_entry *hash;
3096 const char *sym_name;
48229727 3097 unsigned int r_type;
35fc36a8 3098 enum arm_st_branch_type branch_type;
48229727
JB		 3099 bfd_boolean non_a8_stub;
3100};
3101
ba93b8ac
DJ		 3102/* The size of the thread control block. */
3103#define TCB_SIZE 8
3104
34e77a92
RS		 3105/* ARM-specific information about a PLT entry, over and above the usual
3106 gotplt_union. */
b38cadfb
NC		 3107struct arm_plt_info
3108{
34e77a92
RS		 3109 /* We reference count Thumb references to a PLT entry separately,
3110 so that we can emit the Thumb trampoline only if needed. */
3111 bfd_signed_vma thumb_refcount;
3112
3113 /* Some references from Thumb code may be eliminated by BL->BLX
3114 conversion, so record them separately. */
3115 bfd_signed_vma maybe_thumb_refcount;
3116
3117 /* How many of the recorded PLT accesses were from non-call relocations.
3118 This information is useful when deciding whether anything takes the
3119 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3120 non-call references to the function should resolve directly to the
3121 real runtime target. */
3122 unsigned int noncall_refcount;
3123
3124 /* Since PLT entries have variable size if the Thumb prologue is
3125 used, we need to record the index into .got.plt instead of
3126 recomputing it from the PLT offset. */
3127 bfd_signed_vma got_offset;
3128};
3129
3130/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3131struct arm_local_iplt_info
3132{
34e77a92
RS		 3133 /* The information that is usually found in the generic ELF part of
3134 the hash table entry. */
3135 union gotplt_union root;
3136
3137 /* The information that is usually found in the ARM-specific part of
3138 the hash table entry. */
3139 struct arm_plt_info arm;
3140
3141 /* A list of all potential dynamic relocations against this symbol. */
3142 struct elf_dyn_relocs *dyn_relocs;
3143};
3144
e8b09b87
CL		 3145/* Structure to handle FDPIC support for local functions. */
3146struct fdpic_local {
3147 unsigned int funcdesc_cnt;
3148 unsigned int gotofffuncdesc_cnt;
3149 int funcdesc_offset;
3150};
3151
0ffa91dd 3152struct elf_arm_obj_tdata
ba93b8ac
DJ		 3153{
3154 struct elf_obj_tdata root;
3155
3156 /* tls_type for each local got entry. */
3157 char *local_got_tls_type;
ee065d83 3158
0855e32b
NS		 3159 /* GOTPLT entries for TLS descriptors. */
3160 bfd_vma *local_tlsdesc_gotent;
3161
34e77a92
RS		 3162 /* Information for local symbols that need entries in .iplt. */
3163 struct arm_local_iplt_info **local_iplt;
3164
bf21ed78
MS		 3165 /* Zero to warn when linking objects with incompatible enum sizes. */
3166 int no_enum_size_warning;
a9dc9481
JM		 3167
3168 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3169 int no_wchar_size_warning;
e8b09b87
CL		 3170
3171 /* Maintains FDPIC counters and funcdesc info. */
3172 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3173};
3174
0ffa91dd
NC		 3175#define elf_arm_tdata(bfd) \
3176 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3177
0ffa91dd
NC		 3178#define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3180
0855e32b
NS		 3181#define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3183
34e77a92
RS		 3184#define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3186
e8b09b87
CL		 3187#define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3189
0ffa91dd
NC		 3190#define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
4dfe6ac6 3193 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3194
3195static bfd_boolean
3196elf32_arm_mkobject (bfd *abfd)
3197{
0ffa91dd 3198 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3199 ARM_ELF_DATA);
ba93b8ac
DJ		 3200}
3201
ba93b8ac
DJ		 3202#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3203
e8b09b87
CL		 3204/* Structure to handle FDPIC support for extern functions. */
3205struct fdpic_global {
3206 unsigned int gotofffuncdesc_cnt;
3207 unsigned int gotfuncdesc_cnt;
3208 unsigned int funcdesc_cnt;
3209 int funcdesc_offset;
3210 int gotfuncdesc_offset;
3211};
3212
ba96a88f 3213/* Arm ELF linker hash entry. */
252b5132 3214struct elf32_arm_link_hash_entry
b38cadfb
NC		 3215{
3216 struct elf_link_hash_entry root;
252b5132 3217
b38cadfb
NC		 3218 /* ARM-specific PLT information. */
3219 struct arm_plt_info plt;
ba93b8ac
DJ		 3220
3221#define GOT_UNKNOWN 0
3222#define GOT_NORMAL 1
3223#define GOT_TLS_GD 2
3224#define GOT_TLS_IE 4
0855e32b
NS		 3225#define GOT_TLS_GDESC 8
3226#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3227 unsigned int tls_type : 8;
34e77a92 3228
b38cadfb
NC		 3229 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3230 unsigned int is_iplt : 1;
34e77a92 3231
b38cadfb 3232 unsigned int unused : 23;
a4fd1a8e 3233
b38cadfb
NC		 3234 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3235 starting at the end of the jump table. */
3236 bfd_vma tlsdesc_got;
0855e32b 3237
b38cadfb
NC		 3238 /* The symbol marking the real symbol location for exported thumb
3239 symbols with Arm stubs. */
3240 struct elf_link_hash_entry *export_glue;
906e58ca 3241
b38cadfb 3242 /* A pointer to the most recently used stub hash entry against this
8029a119 3243 symbol. */
b38cadfb 3244 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3245
3246 /* Counter for FDPIC relocations against this symbol. */
3247 struct fdpic_global fdpic_cnts;
b38cadfb 3248};
252b5132 3249
252b5132 3250/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3251#define elf32_arm_link_hash_traverse(table, func, info) \
3252 (elf_link_hash_traverse \
3253 (&(table)->root, \
b7693d02 3254 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3255 (info)))
3256
3257/* Get the ARM elf linker hash table from a link_info structure. */
3258#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3259 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3260 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3261
906e58ca
NC		 3262#define arm_stub_hash_lookup(table, string, create, copy) \
3263 ((struct elf32_arm_stub_hash_entry *) \
3264 bfd_hash_lookup ((table), (string), (create), (copy)))
3265
21d799b5
NC		 3266/* Array to keep track of which stub sections have been created, and
3267 information on stub grouping. */
3268struct map_stub
3269{
3270 /* This is the section to which stubs in the group will be
3271 attached. */
3272 asection *link_sec;
3273 /* The stub section. */
3274 asection *stub_sec;
3275};
3276
0855e32b
NS		 3277#define elf32_arm_compute_jump_table_size(htab) \
3278 ((htab)->next_tls_desc_index * 4)
3279
9b485d32 3280/* ARM ELF linker hash table. */
252b5132 3281struct elf32_arm_link_hash_table
906e58ca
NC		 3282{
3283 /* The main hash table. */
3284 struct elf_link_hash_table root;
252b5132 3285
906e58ca
NC		 3286 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3287 bfd_size_type thumb_glue_size;
252b5132 3288
906e58ca
NC		 3289 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3290 bfd_size_type arm_glue_size;
252b5132 3291
906e58ca
NC		 3292 /* The size in bytes of section containing the ARMv4 BX veneers. */
3293 bfd_size_type bx_glue_size;
845b51d6 3294
906e58ca
NC		 3295 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3296 veneer has been populated. */
3297 bfd_vma bx_glue_offset[15];
845b51d6 3298
906e58ca
NC		 3299 /* The size in bytes of the section containing glue for VFP11 erratum
3300 veneers. */
3301 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3302
a504d23a
LA		 3303 /* The size in bytes of the section containing glue for STM32L4XX erratum
3304 veneers. */
3305 bfd_size_type stm32l4xx_erratum_glue_size;
3306
48229727
JB		 3307 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3308 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3309 elf32_arm_write_section(). */
3310 struct a8_erratum_fix *a8_erratum_fixes;
3311 unsigned int num_a8_erratum_fixes;
3312
906e58ca
NC		 3313 /* An arbitrary input BFD chosen to hold the glue sections. */
3314 bfd * bfd_of_glue_owner;
ba96a88f 3315
906e58ca
NC		 3316 /* Nonzero to output a BE8 image. */
3317 int byteswap_code;
e489d0ae 3318
906e58ca
NC		 3319 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3320 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3321 int target1_is_rel;
9c504268 3322
906e58ca
NC		 3323 /* The relocation to use for R_ARM_TARGET2 relocations. */
3324 int target2_reloc;
eb043451 3325
906e58ca
NC		 3326 /* 0 = Ignore R_ARM_V4BX.
3327 1 = Convert BX to MOV PC.
3328 2 = Generate v4 interworing stubs. */
3329 int fix_v4bx;
319850b4 3330
48229727
JB		 3331 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3332 int fix_cortex_a8;
3333
2de70689
MGD		 3334 /* Whether we should fix the ARM1176 BLX immediate issue. */
3335 int fix_arm1176;
3336
906e58ca
NC		 3337 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3338 int use_blx;
33bfe774 3339
906e58ca
NC		 3340 /* What sort of code sequences we should look for which may trigger the
3341 VFP11 denorm erratum. */
3342 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3343
906e58ca
NC		 3344 /* Global counter for the number of fixes we have emitted. */
3345 int num_vfp11_fixes;
c7b8f16e 3346
a504d23a
LA		 3347 /* What sort of code sequences we should look for which may trigger the
3348 STM32L4XX erratum. */
3349 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3350
3351 /* Global counter for the number of fixes we have emitted. */
3352 int num_stm32l4xx_fixes;
3353
906e58ca
NC		 3354 /* Nonzero to force PIC branch veneers. */
3355 int pic_veneer;
27e55c4d 3356
906e58ca
NC		 3357 /* The number of bytes in the initial entry in the PLT. */
3358 bfd_size_type plt_header_size;
e5a52504 3359
906e58ca
NC		 3360 /* The number of bytes in the subsequent PLT etries. */
3361 bfd_size_type plt_entry_size;
e5a52504 3362
906e58ca 3363 /* True if the target uses REL relocations. */
f3185997 3364 bfd_boolean use_rel;
4e7fd91e 3365
54ddd295
TP		 3366 /* Nonzero if import library must be a secure gateway import library
3367 as per ARMv8-M Security Extensions. */
3368 int cmse_implib;
3369
0955507f
TP		 3370 /* The import library whose symbols' address must remain stable in
3371 the import library generated. */
3372 bfd *in_implib_bfd;
3373
0855e32b
NS		 3374 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3375 bfd_vma next_tls_desc_index;
3376
3377 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3378 bfd_vma num_tls_desc;
3379
906e58ca
NC		 3380 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3381 asection *srelplt2;
00a97672 3382
0855e32b
NS		 3383 /* Offset in .plt section of tls_arm_trampoline. */
3384 bfd_vma tls_trampoline;
3385
5c5a4843 3386 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3387 union
3388 {
3389 bfd_signed_vma refcount;
3390 bfd_vma offset;
3391 } tls_ldm_got;
b7693d02 3392
87d72d41
AM		 3393 /* Small local sym cache. */
3394 struct sym_cache sym_cache;
906e58ca
NC		 3395
3396 /* For convenience in allocate_dynrelocs. */
3397 bfd * obfd;
3398
0855e32b
NS		 3399 /* The amount of space used by the reserved portion of the sgotplt
3400 section, plus whatever space is used by the jump slots. */
3401 bfd_vma sgotplt_jump_table_size;
3402
906e58ca
NC		 3403 /* The stub hash table. */
3404 struct bfd_hash_table stub_hash_table;
3405
3406 /* Linker stub bfd. */
3407 bfd *stub_bfd;
3408
3409 /* Linker call-backs. */
6bde4c52
TP		 3410 asection * (*add_stub_section) (const char *, asection *, asection *,
3411 unsigned int);
906e58ca
NC		 3412 void (*layout_sections_again) (void);
3413
3414 /* Array to keep track of which stub sections have been created, and
3415 information on stub grouping. */
21d799b5 3416 struct map_stub *stub_group;
906e58ca 3417
4ba2ef8f
TP		 3418 /* Input stub section holding secure gateway veneers. */
3419 asection *cmse_stub_sec;
3420
0955507f
TP		 3421 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3422 start to be allocated. */
3423 bfd_vma new_cmse_stub_offset;
3424
fe33d2fa 3425 /* Number of elements in stub_group. */
7292b3ac 3426 unsigned int top_id;
fe33d2fa 3427
906e58ca
NC		 3428 /* Assorted information used by elf32_arm_size_stubs. */
3429 unsigned int bfd_count;
7292b3ac 3430 unsigned int top_index;
906e58ca 3431 asection **input_list;
617a5ada
CL		 3432
3433 /* True if the target system uses FDPIC. */
3434 int fdpic_p;
e8b09b87
CL		 3435
3436 /* Fixup section. Used for FDPIC. */
3437 asection *srofixup;
906e58ca 3438};
252b5132 3439
e8b09b87
CL		 3440/* Add an FDPIC read-only fixup. */
3441static void
3442arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3443{
3444 bfd_vma fixup_offset;
3445
3446 fixup_offset = srofixup->reloc_count++ * 4;
3447 BFD_ASSERT (fixup_offset < srofixup->size);
3448 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3449}
3450
a504d23a
LA		 3451static inline int
3452ctz (unsigned int mask)
3453{
3454#if GCC_VERSION >= 3004
3455 return __builtin_ctz (mask);
3456#else
3457 unsigned int i;
3458
3459 for (i = 0; i < 8 * sizeof (mask); i++)
3460 {
3461 if (mask & 0x1)
3462 break;
3463 mask = (mask >> 1);
3464 }
3465 return i;
3466#endif
3467}
3468
3469static inline int
b25e998d 3470elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3471{
3472#if GCC_VERSION >= 3004
3473 return __builtin_popcount (mask);
3474#else
b25e998d
CG		 3475 unsigned int i;
3476 int sum = 0;
a504d23a
LA		 3477
3478 for (i = 0; i < 8 * sizeof (mask); i++)
3479 {
3480 if (mask & 0x1)
3481 sum++;
3482 mask = (mask >> 1);
3483 }
3484 return sum;
3485#endif
3486}
3487
e8b09b87
CL		 3488static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3489 asection *sreloc, Elf_Internal_Rela *rel);
3490
3491static void
3492arm_elf_fill_funcdesc(bfd *output_bfd,
3493 struct bfd_link_info *info,
3494 int *funcdesc_offset,
3495 int dynindx,
3496 int offset,
3497 bfd_vma addr,
3498 bfd_vma dynreloc_value,
3499 bfd_vma seg)
3500{
3501 if ((*funcdesc_offset & 1) == 0)
3502 {
3503 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3504 asection *sgot = globals->root.sgot;
3505
3506 if (bfd_link_pic(info))
3507 {
3508 asection *srelgot = globals->root.srelgot;
3509 Elf_Internal_Rela outrel;
3510
3511 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3512 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3513 outrel.r_addend = 0;
3514
3515 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3516 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3517 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3518 }
3519 else
3520 {
3521 struct elf_link_hash_entry *hgot = globals->root.hgot;
3522 bfd_vma got_value = hgot->root.u.def.value
3523 + hgot->root.u.def.section->output_section->vma
3524 + hgot->root.u.def.section->output_offset;
3525
3526 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3527 sgot->output_section->vma + sgot->output_offset
3528 + offset);
3529 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3530 sgot->output_section->vma + sgot->output_offset
3531 + offset + 4);
3532 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3533 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3534 }
3535 *funcdesc_offset |= 1;
3536 }
3537}
3538
780a67af
NC		 3539/* Create an entry in an ARM ELF linker hash table. */
3540
3541static struct bfd_hash_entry *
57e8b36a 3542elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3543 struct bfd_hash_table * table,
3544 const char * string)
780a67af
NC		 3545{
3546 struct elf32_arm_link_hash_entry * ret =
3547 (struct elf32_arm_link_hash_entry *) entry;
3548
3549 /* Allocate the structure if it has not already been allocated by a
3550 subclass. */
906e58ca 3551 if (ret == NULL)
21d799b5 3552 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3553 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3554 if (ret == NULL)
780a67af
NC		 3555 return (struct bfd_hash_entry *) ret;
3556
3557 /* Call the allocation method of the superclass. */
3558 ret = ((struct elf32_arm_link_hash_entry *)
3559 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3560 table, string));
57e8b36a 3561 if (ret != NULL)
b7693d02 3562 {
ba93b8ac 3563 ret->tls_type = GOT_UNKNOWN;
0855e32b 3564 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3565 ret->plt.thumb_refcount = 0;
3566 ret->plt.maybe_thumb_refcount = 0;
3567 ret->plt.noncall_refcount = 0;
3568 ret->plt.got_offset = -1;
3569 ret->is_iplt = FALSE;
a4fd1a8e 3570 ret->export_glue = NULL;
906e58ca
NC		 3571
3572 ret->stub_cache = NULL;
e8b09b87
CL		 3573
3574 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3575 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3576 ret->fdpic_cnts.funcdesc_cnt = 0;
3577 ret->fdpic_cnts.funcdesc_offset = -1;
3578 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3579 }
780a67af
NC		 3580
3581 return (struct bfd_hash_entry *) ret;
3582}
3583
34e77a92
RS		 3584/* Ensure that we have allocated bookkeeping structures for ABFD's local
3585 symbols. */
3586
3587static bfd_boolean
3588elf32_arm_allocate_local_sym_info (bfd *abfd)
3589{
3590 if (elf_local_got_refcounts (abfd) == NULL)
3591 {
3592 bfd_size_type num_syms;
3593 bfd_size_type size;
3594 char *data;
3595
3596 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3597 size = num_syms * (sizeof (bfd_signed_vma)
3598 + sizeof (struct arm_local_iplt_info *)
3599 + sizeof (bfd_vma)
e8b09b87
CL		 3600 + sizeof (char)
3601 + sizeof (struct fdpic_local));
34e77a92
RS		 3602 data = bfd_zalloc (abfd, size);
3603 if (data == NULL)
3604 return FALSE;
3605
e8b09b87
CL		 3606 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3607 data += num_syms * sizeof (struct fdpic_local);
3608
34e77a92
RS		 3609 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3610 data += num_syms * sizeof (bfd_signed_vma);
3611
3612 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3613 data += num_syms * sizeof (struct arm_local_iplt_info *);
3614
3615 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3616 data += num_syms * sizeof (bfd_vma);
3617
3618 elf32_arm_local_got_tls_type (abfd) = data;
3619 }
3620 return TRUE;
3621}
3622
3623/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3624 to input bfd ABFD. Create the information if it doesn't already exist.
3625 Return null if an allocation fails. */
3626
3627static struct arm_local_iplt_info *
3628elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3629{
3630 struct arm_local_iplt_info **ptr;
3631
3632 if (!elf32_arm_allocate_local_sym_info (abfd))
3633 return NULL;
3634
3635 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3636 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3637 if (*ptr == NULL)
3638 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3639 return *ptr;
3640}
3641
3642/* Try to obtain PLT information for the symbol with index R_SYMNDX
3643 in ABFD's symbol table. If the symbol is global, H points to its
3644 hash table entry, otherwise H is null.
3645
3646 Return true if the symbol does have PLT information. When returning
3647 true, point *ROOT_PLT at the target-independent reference count/offset
3648 union and *ARM_PLT at the ARM-specific information. */
3649
3650static bfd_boolean
4ba2ef8f
TP		 3651elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3652 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3653 unsigned long r_symndx, union gotplt_union **root_plt,
3654 struct arm_plt_info **arm_plt)
3655{
3656 struct arm_local_iplt_info *local_iplt;
3657
4ba2ef8f
TP		 3658 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3659 return FALSE;
3660
34e77a92
RS		 3661 if (h != NULL)
3662 {
3663 *root_plt = &h->root.plt;
3664 *arm_plt = &h->plt;
3665 return TRUE;
3666 }
3667
3668 if (elf32_arm_local_iplt (abfd) == NULL)
3669 return FALSE;
3670
3671 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3672 if (local_iplt == NULL)
3673 return FALSE;
3674
3675 *root_plt = &local_iplt->root;
3676 *arm_plt = &local_iplt->arm;
3677 return TRUE;
3678}
3679
59029f57
CL		 3680static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3681
34e77a92
RS		 3682/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3683 before it. */
3684
3685static bfd_boolean
3686elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3687 struct arm_plt_info *arm_plt)
3688{
3689 struct elf32_arm_link_hash_table *htab;
3690
3691 htab = elf32_arm_hash_table (info);
59029f57
CL		 3692
3693 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3694 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3695}
3696
3697/* Return a pointer to the head of the dynamic reloc list that should
3698 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3699 ABFD's symbol table. Return null if an error occurs. */
3700
3701static struct elf_dyn_relocs **
3702elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3703 Elf_Internal_Sym *isym)
3704{
3705 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3706 {
3707 struct arm_local_iplt_info *local_iplt;
3708
3709 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3710 if (local_iplt == NULL)
3711 return NULL;
3712 return &local_iplt->dyn_relocs;
3713 }
3714 else
3715 {
3716 /* Track dynamic relocs needed for local syms too.
3717 We really need local syms available to do this
3718 easily. Oh well. */
3719 asection *s;
3720 void *vpp;
3721
3722 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3723 if (s == NULL)
3724 abort ();
3725
3726 vpp = &elf_section_data (s)->local_dynrel;
3727 return (struct elf_dyn_relocs **) vpp;
3728 }
3729}
3730
906e58ca
NC		 3731/* Initialize an entry in the stub hash table. */
3732
3733static struct bfd_hash_entry *
3734stub_hash_newfunc (struct bfd_hash_entry *entry,
3735 struct bfd_hash_table *table,
3736 const char *string)
3737{
3738 /* Allocate the structure if it has not already been allocated by a
3739 subclass. */
3740 if (entry == NULL)
3741 {
21d799b5 3742 entry = (struct bfd_hash_entry *)
99059e56 3743 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3744 if (entry == NULL)
3745 return entry;
3746 }
3747
3748 /* Call the allocation method of the superclass. */
3749 entry = bfd_hash_newfunc (entry, table, string);
3750 if (entry != NULL)
3751 {
3752 struct elf32_arm_stub_hash_entry *eh;
3753
3754 /* Initialize the local fields. */
3755 eh = (struct elf32_arm_stub_hash_entry *) entry;
3756 eh->stub_sec = NULL;
0955507f 3757 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3758 eh->source_value = 0;
906e58ca
NC		 3759 eh->target_value = 0;
3760 eh->target_section = NULL;
cedfb179 3761 eh->orig_insn = 0;
906e58ca 3762 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3763 eh->stub_size = 0;
3764 eh->stub_template = NULL;
0955507f 3765 eh->stub_template_size = -1;
906e58ca
NC		 3766 eh->h = NULL;
3767 eh->id_sec = NULL;
d8d2f433 3768 eh->output_name = NULL;
906e58ca
NC		 3769 }
3770
3771 return entry;
3772}
3773
00a97672 3774/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3775 shortcuts to them in our hash table. */
3776
3777static bfd_boolean
57e8b36a 3778create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3779{
3780 struct elf32_arm_link_hash_table *htab;
3781
e5a52504 3782 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3783 if (htab == NULL)
3784 return FALSE;
3785
e5a52504 3786 /* BPABI objects never have a GOT, or associated sections. */
90c14f0c 3787 if (htab->root.target_os == is_symbian)
e5a52504
MM		 3788 return TRUE;
3789
5e681ec4
PB		 3790 if (! _bfd_elf_create_got_section (dynobj, info))
3791 return FALSE;
3792
e8b09b87
CL		 3793 /* Also create .rofixup. */
3794 if (htab->fdpic_p)
3795 {
3796 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3797 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3798 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
fd361982
AM		 3799 if (htab->srofixup == NULL
3800 || !bfd_set_section_alignment (htab->srofixup, 2))
e8b09b87
CL		 3801 return FALSE;
3802 }
3803
5e681ec4
PB		 3804 return TRUE;
3805}
3806
34e77a92
RS		 3807/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3808
3809static bfd_boolean
3810create_ifunc_sections (struct bfd_link_info *info)
3811{
3812 struct elf32_arm_link_hash_table *htab;
3813 const struct elf_backend_data *bed;
3814 bfd *dynobj;
3815 asection *s;
3816 flagword flags;
b38cadfb 3817
34e77a92
RS		 3818 htab = elf32_arm_hash_table (info);
3819 dynobj = htab->root.dynobj;
3820 bed = get_elf_backend_data (dynobj);
3821 flags = bed->dynamic_sec_flags;
3822
3823 if (htab->root.iplt == NULL)
3824 {
3d4d4302
AM		 3825 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3826 flags | SEC_READONLY | SEC_CODE);
34e77a92 3827 if (s == NULL
fd361982 3828 || !bfd_set_section_alignment (s, bed->plt_alignment))
34e77a92
RS		 3829 return FALSE;
3830 htab->root.iplt = s;
3831 }
3832
3833 if (htab->root.irelplt == NULL)
3834 {
3d4d4302
AM		 3835 s = bfd_make_section_anyway_with_flags (dynobj,
3836 RELOC_SECTION (htab, ".iplt"),
3837 flags | SEC_READONLY);
34e77a92 3838 if (s == NULL
fd361982 3839 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3840 return FALSE;
3841 htab->root.irelplt = s;
3842 }
3843
3844 if (htab->root.igotplt == NULL)
3845 {
3d4d4302 3846 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92 3847 if (s == NULL
fd361982 3848 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3849 return FALSE;
3850 htab->root.igotplt = s;
3851 }
3852 return TRUE;
3853}
3854
eed94f8f
NC		 3855/* Determine if we're dealing with a Thumb only architecture. */
3856
3857static bfd_boolean
3858using_thumb_only (struct elf32_arm_link_hash_table *globals)
3859{
2fd158eb
TP		 3860 int arch;
3861 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3862 Tag_CPU_arch_profile);
eed94f8f 3863
2fd158eb
TP		 3864 if (profile)
3865 return profile == 'M';
eed94f8f 3866
2fd158eb 3867 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3868
60a019a0 3869 /* Force return logic to be reviewed for each new architecture. */
031254f2 3870 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3871
2fd158eb
TP		 3872 if (arch == TAG_CPU_ARCH_V6_M
3873 || arch == TAG_CPU_ARCH_V6S_M
3874 || arch == TAG_CPU_ARCH_V7E_M
3875 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3876 || arch == TAG_CPU_ARCH_V8M_MAIN
3877 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3878 return TRUE;
eed94f8f 3879
2fd158eb 3880 return FALSE;
eed94f8f
NC		 3881}
3882
3883/* Determine if we're dealing with a Thumb-2 object. */
3884
3885static bfd_boolean
3886using_thumb2 (struct elf32_arm_link_hash_table *globals)
3887{
60a019a0
TP		 3888 int arch;
3889 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3890 Tag_THUMB_ISA_use);
3891
3892 if (thumb_isa)
3893 return thumb_isa == 2;
3894
3895 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3896
3897 /* Force return logic to be reviewed for each new architecture. */
031254f2 3898 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3899
3900 return (arch == TAG_CPU_ARCH_V6T2
3901 || arch == TAG_CPU_ARCH_V7
3902 || arch == TAG_CPU_ARCH_V7E_M
3903 || arch == TAG_CPU_ARCH_V8
bff0500d 3904 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3905 || arch == TAG_CPU_ARCH_V8M_MAIN
3906 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3907}
3908
5e866f5a
TP		 3909/* Determine whether Thumb-2 BL instruction is available. */
3910
3911static bfd_boolean
3912using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3913{
3914 int arch =
3915 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3916
3917 /* Force return logic to be reviewed for each new architecture. */
031254f2 3918 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3919
3920 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3921 return (arch == TAG_CPU_ARCH_V6T2
3922 || arch >= TAG_CPU_ARCH_V7);
3923}
3924
00a97672
RS		 3925/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3926 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3927 hash table. */
3928
3929static bfd_boolean
57e8b36a 3930elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3931{
3932 struct elf32_arm_link_hash_table *htab;
3933
3934 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3935 if (htab == NULL)
3936 return FALSE;
3937
362d30a1 3938 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3939 return FALSE;
3940
3941 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3942 return FALSE;
3943
90c14f0c 3944 if (htab->root.target_os == is_vxworks)
00a97672
RS		 3945 {
3946 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3947 return FALSE;
3948
0e1862bb 3949 if (bfd_link_pic (info))
00a97672
RS		 3950 {
3951 htab->plt_header_size = 0;
3952 htab->plt_entry_size
3953 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3954 }
3955 else
3956 {
3957 htab->plt_header_size
3958 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3959 htab->plt_entry_size
3960 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3961 }
aebf9be7
NC		 3962
3963 if (elf_elfheader (dynobj))
3964 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3965 }
eed94f8f
NC		 3966 else
3967 {
3968 /* PR ld/16017
3969 Test for thumb only architectures. Note - we cannot just call
3970 using_thumb_only() as the attributes in the output bfd have not been
3971 initialised at this point, so instead we use the input bfd. */
3972 bfd * saved_obfd = htab->obfd;
3973
3974 htab->obfd = dynobj;
3975 if (using_thumb_only (htab))
3976 {
3977 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3978 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3979 }
3980 htab->obfd = saved_obfd;
3981 }
5e681ec4 3982
7801f98f
CL		 3983 if (htab->fdpic_p) {
3984 htab->plt_header_size = 0;
3985 if (info->flags & DF_BIND_NOW)
3986 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
3987 else
3988 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
3989 }
3990
362d30a1
RS		 3991 if (!htab->root.splt
3992 || !htab->root.srelplt
9d19e4fd
AM		 3993 || !htab->root.sdynbss
3994 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3995 abort ();
3996
3997 return TRUE;
3998}
3999
906e58ca
NC		 4000/* Copy the extra info we tack onto an elf_link_hash_entry. */
4001
4002static void
4003elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4004 struct elf_link_hash_entry *dir,
4005 struct elf_link_hash_entry *ind)
4006{
4007 struct elf32_arm_link_hash_entry *edir, *eind;
4008
4009 edir = (struct elf32_arm_link_hash_entry *) dir;
4010 eind = (struct elf32_arm_link_hash_entry *) ind;
4011
906e58ca
NC		 4012 if (ind->root.type == bfd_link_hash_indirect)
4013 {
4014 /* Copy over PLT info. */
34e77a92
RS		 4015 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4016 eind->plt.thumb_refcount = 0;
4017 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4018 eind->plt.maybe_thumb_refcount = 0;
4019 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4020 eind->plt.noncall_refcount = 0;
4021
e8b09b87
CL		 4022 /* Copy FDPIC counters. */
4023 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4024 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4025 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4026
34e77a92
RS		 4027 /* We should only allocate a function to .iplt once the final
4028 symbol information is known. */
4029 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4030
4031 if (dir->got.refcount <= 0)
4032 {
4033 edir->tls_type = eind->tls_type;
4034 eind->tls_type = GOT_UNKNOWN;
4035 }
4036 }
4037
4038 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4039}
4040
68faa637
AM		 4041/* Destroy an ARM elf linker hash table. */
4042
4043static void
d495ab0d 4044elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4045{
4046 struct elf32_arm_link_hash_table *ret
d495ab0d 4047 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4048
4049 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4050 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4051}
4052
906e58ca
NC		 4053/* Create an ARM elf linker hash table. */
4054
4055static struct bfd_link_hash_table *
4056elf32_arm_link_hash_table_create (bfd *abfd)
4057{
4058 struct elf32_arm_link_hash_table *ret;
986f0783 4059 size_t amt = sizeof (struct elf32_arm_link_hash_table);
906e58ca 4060
7bf52ea2 4061 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4062 if (ret == NULL)
4063 return NULL;
4064
4065 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4066 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4067 sizeof (struct elf32_arm_link_hash_entry),
4068 ARM_ELF_DATA))
906e58ca
NC		 4069 {
4070 free (ret);
4071 return NULL;
4072 }
4073
906e58ca 4074 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4075 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4076#ifdef FOUR_WORD_PLT
4077 ret->plt_header_size = 16;
4078 ret->plt_entry_size = 16;
4079#else
4080 ret->plt_header_size = 20;
1db37fe6 4081 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4082#endif
f3185997 4083 ret->use_rel = TRUE;
906e58ca 4084 ret->obfd = abfd;
617a5ada 4085 ret->fdpic_p = 0;
906e58ca
NC		 4086
4087 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4088 sizeof (struct elf32_arm_stub_hash_entry)))
4089 {
d495ab0d 4090 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4091 return NULL;
4092 }
d495ab0d 4093 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4094
4095 return &ret->root.root;
4096}
4097
cd1dac3d
DG		 4098/* Determine what kind of NOPs are available. */
4099
4100static bfd_boolean
4101arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4102{
4103 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4104 Tag_CPU_arch);
cd1dac3d 4105
60a019a0 4106 /* Force return logic to be reviewed for each new architecture. */
031254f2 4107 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4108
4109 return (arch == TAG_CPU_ARCH_V6T2
4110 || arch == TAG_CPU_ARCH_V6K
4111 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4112 || arch == TAG_CPU_ARCH_V8
4113 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4114}
4115
f4ac8484
DJ		 4116static bfd_boolean
4117arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4118{
4119 switch (stub_type)
4120 {
fea2b4d6 4121 case arm_stub_long_branch_thumb_only:
80c135e5 4122 case arm_stub_long_branch_thumb2_only:
d5a67c02 4123 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4124 case arm_stub_long_branch_v4t_thumb_arm:
4125 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4126 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4127 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4128 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4129 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4130 return TRUE;
4131 case arm_stub_none:
4132 BFD_FAIL ();
4133 return FALSE;
4134 break;
4135 default:
4136 return FALSE;
4137 }
4138}
4139
906e58ca
NC		 4140/* Determine the type of stub needed, if any, for a call. */
4141
4142static enum elf32_arm_stub_type
4143arm_type_of_stub (struct bfd_link_info *info,
4144 asection *input_sec,
4145 const Elf_Internal_Rela *rel,
34e77a92 4146 unsigned char st_type,
35fc36a8 4147 enum arm_st_branch_type *actual_branch_type,
906e58ca 4148 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4149 bfd_vma destination,
4150 asection *sym_sec,
4151 bfd *input_bfd,
4152 const char *name)
906e58ca
NC		 4153{
4154 bfd_vma location;
4155 bfd_signed_vma branch_offset;
4156 unsigned int r_type;
4157 struct elf32_arm_link_hash_table * globals;
5e866f5a 4158 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4159 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4160 int use_plt = 0;
35fc36a8 4161 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4162 union gotplt_union *root_plt;
4163 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4164 int arch;
4165 int thumb2_movw;
906e58ca 4166
35fc36a8 4167 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4168 return stub_type;
4169
906e58ca 4170 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4171 if (globals == NULL)
4172 return stub_type;
906e58ca
NC		 4173
4174 thumb_only = using_thumb_only (globals);
906e58ca 4175 thumb2 = using_thumb2 (globals);
5e866f5a 4176 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4177
d5a67c02
AV		 4178 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4179
4180 /* True for architectures that implement the thumb2 movw instruction. */
4181 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4182
906e58ca
NC		 4183 /* Determine where the call point is. */
4184 location = (input_sec->output_offset
4185 + input_sec->output_section->vma
4186 + rel->r_offset);
4187
906e58ca
NC		 4188 r_type = ELF32_R_TYPE (rel->r_info);
4189
39f21624
NC		 4190 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4191 are considering a function call relocation. */
c5423981 4192 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4193 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4194 && branch_type == ST_BRANCH_TO_ARM)
4195 branch_type = ST_BRANCH_TO_THUMB;
4196
34e77a92
RS		 4197 /* For TLS call relocs, it is the caller's responsibility to provide
4198 the address of the appropriate trampoline. */
4199 if (r_type != R_ARM_TLS_CALL
4200 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4201 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4202 ELF32_R_SYM (rel->r_info), &root_plt,
4203 &arm_plt)
34e77a92 4204 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4205 {
34e77a92 4206 asection *splt;
fe33d2fa 4207
34e77a92
RS		 4208 if (hash == NULL || hash->is_iplt)
4209 splt = globals->root.iplt;
4210 else
4211 splt = globals->root.splt;
4212 if (splt != NULL)
b38cadfb 4213 {
34e77a92
RS		 4214 use_plt = 1;
4215
4216 /* Note when dealing with PLT entries: the main PLT stub is in
4217 ARM mode, so if the branch is in Thumb mode, another
4218 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4219 PLT stub. If a long branch stub is needed, we'll add a
4220 Thumb->Arm one and branch directly to the ARM PLT entry.
4221 Here, we have to check if a pre-PLT Thumb->ARM stub
4222 is needed and if it will be close enough. */
34e77a92
RS		 4223
4224 destination = (splt->output_section->vma
4225 + splt->output_offset
4226 + root_plt->offset);
4227 st_type = STT_FUNC;
2df2751d
CL		 4228
4229 /* Thumb branch/call to PLT: it can become a branch to ARM
4230 or to Thumb. We must perform the same checks and
4231 corrections as in elf32_arm_final_link_relocate. */
4232 if ((r_type == R_ARM_THM_CALL)
4233 || (r_type == R_ARM_THM_JUMP24))
4234 {
4235 if (globals->use_blx
4236 && r_type == R_ARM_THM_CALL
4237 && !thumb_only)
4238 {
4239 /* If the Thumb BLX instruction is available, convert
4240 the BL to a BLX instruction to call the ARM-mode
4241 PLT entry. */
4242 branch_type = ST_BRANCH_TO_ARM;
4243 }
4244 else
4245 {
4246 if (!thumb_only)
4247 /* Target the Thumb stub before the ARM PLT entry. */
4248 destination -= PLT_THUMB_STUB_SIZE;
4249 branch_type = ST_BRANCH_TO_THUMB;
4250 }
4251 }
4252 else
4253 {
4254 branch_type = ST_BRANCH_TO_ARM;
4255 }
34e77a92 4256 }
5fa9e92f 4257 }
34e77a92
RS		 4258 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4259 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4260
fe33d2fa
CL		 4261 branch_offset = (bfd_signed_vma)(destination - location);
4262
0855e32b 4263 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4264 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4265 {
5fa9e92f
CL		 4266 /* Handle cases where:
4267 - this call goes too far (different Thumb/Thumb2 max
99059e56 4268 distance)
155d87d7 4269 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4270 Thumb->Arm branch (not bl). A stub is needed in this case,
4271 but only if this call is not through a PLT entry. Indeed,
695344c0 4272 PLT stubs handle mode switching already. */
5e866f5a 4273 if ((!thumb2_bl
906e58ca
NC		 4274 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4275 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4276 || (thumb2_bl
906e58ca
NC		 4277 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4278 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4279 || (thumb2
4280 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4281 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4282 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4283 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4284 && (((r_type == R_ARM_THM_CALL
4285 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4286 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4287 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4288 && !use_plt))
906e58ca 4289 {
2df2751d
CL		 4290 /* If we need to insert a Thumb-Thumb long branch stub to a
4291 PLT, use one that branches directly to the ARM PLT
4292 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4293 stub, undo this now. */
695344c0
NC		 4294 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4295 {
4296 branch_type = ST_BRANCH_TO_ARM;
4297 branch_offset += PLT_THUMB_STUB_SIZE;
4298 }
2df2751d 4299
35fc36a8 4300 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4301 {
4302 /* Thumb to thumb. */
4303 if (!thumb_only)
4304 {
d5a67c02 4305 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4306 _bfd_error_handler
871b3ab2 4307 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4308 " section with SHF_ARM_PURECODE section"
4309 " attribute is only supported for M-profile"
90b6238f 4310 " targets that implement the movw instruction"),
10463f39 4311 input_bfd, input_sec);
d5a67c02 4312
0e1862bb 4313 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4314 /* PIC stubs. */
155d87d7 4315 ? ((globals->use_blx
9553db3c 4316 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4317 /* V5T and above. Stub starts with ARM code, so
4318 we must be able to switch mode before
4319 reaching it, which is only possible for 'bl'
4320 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4321 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4322 /* On V4T, use Thumb code only. */
d3626fb0 4323 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4324
4325 /* non-PIC stubs. */
155d87d7 4326 : ((globals->use_blx
9553db3c 4327 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4328 /* V5T and above. */
4329 ? arm_stub_long_branch_any_any
4330 /* V4T. */
d3626fb0 4331 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4332 }
4333 else
4334 {
d5a67c02
AV		 4335 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4336 stub_type = arm_stub_long_branch_thumb2_only_pure;
4337 else
4338 {
4339 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4340 _bfd_error_handler
871b3ab2 4341 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4342 " section with SHF_ARM_PURECODE section"
4343 " attribute is only supported for M-profile"
90b6238f 4344 " targets that implement the movw instruction"),
10463f39 4345 input_bfd, input_sec);
d5a67c02
AV		 4346
4347 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4348 /* PIC stub. */
4349 ? arm_stub_long_branch_thumb_only_pic
4350 /* non-PIC stub. */
4351 : (thumb2 ? arm_stub_long_branch_thumb2_only
4352 : arm_stub_long_branch_thumb_only);
4353 }
906e58ca
NC		 4354 }
4355 }
4356 else
4357 {
d5a67c02 4358 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4359 _bfd_error_handler
871b3ab2 4360 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4361 " section with SHF_ARM_PURECODE section"
4362 " attribute is only supported" " for M-profile"
90b6238f 4363 " targets that implement the movw instruction"),
10463f39 4364 input_bfd, input_sec);
d5a67c02 4365
906e58ca 4366 /* Thumb to arm. */
c820be07
NC		 4367 if (sym_sec != NULL
4368 && sym_sec->owner != NULL
4369 && !INTERWORK_FLAG (sym_sec->owner))
4370 {
4eca0228 4371 _bfd_error_handler
90b6238f
AM		 4372 (_("%pB(%s): warning: interworking not enabled;"
4373 " first occurrence: %pB: %s call to %s"),
4374 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4375 }
4376
0855e32b 4377 stub_type =
0e1862bb 4378 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4379 /* PIC stubs. */
0855e32b 4380 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4381 /* TLS PIC stubs. */
0855e32b
NS		 4382 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4383 : arm_stub_long_branch_v4t_thumb_tls_pic)
4384 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4385 /* V5T PIC and above. */
4386 ? arm_stub_long_branch_any_arm_pic
4387 /* V4T PIC stub. */
4388 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4389
4390 /* non-PIC stubs. */
0855e32b 4391 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4392 /* V5T and above. */
4393 ? arm_stub_long_branch_any_any
4394 /* V4T. */
4395 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4396
4397 /* Handle v4t short branches. */
fea2b4d6 4398 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4399 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4400 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4401 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4402 }
4403 }
4404 }
fe33d2fa
CL		 4405 else if (r_type == R_ARM_CALL
4406 || r_type == R_ARM_JUMP24
0855e32b
NS		 4407 || r_type == R_ARM_PLT32
4408 || r_type == R_ARM_TLS_CALL)
906e58ca 4409 {
d5a67c02 4410 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4411 _bfd_error_handler
871b3ab2 4412 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4413 " section with SHF_ARM_PURECODE section"
4414 " attribute is only supported for M-profile"
90b6238f 4415 " targets that implement the movw instruction"),
10463f39 4416 input_bfd, input_sec);
35fc36a8 4417 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4418 {
4419 /* Arm to thumb. */
c820be07
NC		 4420
4421 if (sym_sec != NULL
4422 && sym_sec->owner != NULL
4423 && !INTERWORK_FLAG (sym_sec->owner))
4424 {
4eca0228 4425 _bfd_error_handler
90b6238f
AM		 4426 (_("%pB(%s): warning: interworking not enabled;"
4427 " first occurrence: %pB: %s call to %s"),
4428 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4429 }
4430
4431 /* We have an extra 2-bytes reach because of
4432 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4433 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4434 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4435 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4436 || (r_type == R_ARM_JUMP24)
4437 || (r_type == R_ARM_PLT32))
906e58ca 4438 {
0e1862bb 4439 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4440 /* PIC stubs. */
ebe24dd4
CL		 4441 ? ((globals->use_blx)
4442 /* V5T and above. */
4443 ? arm_stub_long_branch_any_thumb_pic
4444 /* V4T stub. */
4445 : arm_stub_long_branch_v4t_arm_thumb_pic)
4446
c2b4a39d
CL		 4447 /* non-PIC stubs. */
4448 : ((globals->use_blx)
4449 /* V5T and above. */
4450 ? arm_stub_long_branch_any_any
4451 /* V4T. */
4452 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4453 }
4454 }
4455 else
4456 {
4457 /* Arm to arm. */
4458 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4459 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4460 {
0855e32b 4461 stub_type =
0e1862bb 4462 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4463 /* PIC stubs. */
0855e32b 4464 ? (r_type == R_ARM_TLS_CALL
6a631e86 4465 /* TLS PIC Stub. */
0855e32b 4466 ? arm_stub_long_branch_any_tls_pic
90c14f0c 4467 : (globals->root.target_os == is_nacl
7a89b94e
NC		 4468 ? arm_stub_long_branch_arm_nacl_pic
4469 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4470 /* non-PIC stubs. */
90c14f0c 4471 : (globals->root.target_os == is_nacl
7a89b94e
NC		 4472 ? arm_stub_long_branch_arm_nacl
4473 : arm_stub_long_branch_any_any);
906e58ca
NC		 4474 }
4475 }
4476 }
4477
fe33d2fa
CL		 4478 /* If a stub is needed, record the actual destination type. */
4479 if (stub_type != arm_stub_none)
35fc36a8 4480 *actual_branch_type = branch_type;
fe33d2fa 4481
906e58ca
NC		 4482 return stub_type;
4483}
4484
4485/* Build a name for an entry in the stub hash table. */
4486
4487static char *
4488elf32_arm_stub_name (const asection *input_section,
4489 const asection *sym_sec,
4490 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4491 const Elf_Internal_Rela *rel,
4492 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4493{
4494 char *stub_name;
4495 bfd_size_type len;
4496
4497 if (hash)
4498 {
fe33d2fa 4499 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4500 stub_name = (char *) bfd_malloc (len);
906e58ca 4501 if (stub_name != NULL)
fe33d2fa 4502 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4503 input_section->id & 0xffffffff,
4504 hash->root.root.root.string,
fe33d2fa
CL		 4505 (int) rel->r_addend & 0xffffffff,
4506 (int) stub_type);
906e58ca
NC		 4507 }
4508 else
4509 {
fe33d2fa 4510 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4511 stub_name = (char *) bfd_malloc (len);
906e58ca 4512 if (stub_name != NULL)
fe33d2fa 4513 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4514 input_section->id & 0xffffffff,
4515 sym_sec->id & 0xffffffff,
0855e32b
NS		 4516 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4517 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4518 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4519 (int) rel->r_addend & 0xffffffff,
4520 (int) stub_type);
906e58ca
NC		 4521 }
4522
4523 return stub_name;
4524}
4525
4526/* Look up an entry in the stub hash. Stub entries are cached because
4527 creating the stub name takes a bit of time. */
4528
4529static struct elf32_arm_stub_hash_entry *
4530elf32_arm_get_stub_entry (const asection *input_section,
4531 const asection *sym_sec,
4532 struct elf_link_hash_entry *hash,
4533 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4534 struct elf32_arm_link_hash_table *htab,
4535 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4536{
4537 struct elf32_arm_stub_hash_entry *stub_entry;
4538 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4539 const asection *id_sec;
4540
4541 if ((input_section->flags & SEC_CODE) == 0)
4542 return NULL;
4543
4d83e8d9
CL		 4544 /* If the input section is the CMSE stubs one and it needs a long
4545 branch stub to reach it's final destination, give up with an
4546 error message: this is not supported. See PR ld/24709. */
4547 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4548 {
4549 bfd *output_bfd = htab->obfd;
4550 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4551
4552 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4553 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4554 CMSE_STUB_NAME,
4555 (uint64_t)out_sec->output_section->vma
4556 + out_sec->output_offset,
4557 (uint64_t)sym_sec->output_section->vma
4558 + sym_sec->output_offset
4559 + h->root.root.u.def.value);
4560 /* Exit, rather than leave incompletely processed
4561 relocations. */
4562 xexit(1);
4563 }
4564
906e58ca
NC		 4565 /* If this input section is part of a group of sections sharing one
4566 stub section, then use the id of the first section in the group.
4567 Stub names need to include a section id, as there may well be
4568 more than one stub used to reach say, printf, and we need to
4569 distinguish between them. */
c2abbbeb 4570 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4571 id_sec = htab->stub_group[input_section->id].link_sec;
4572
4573 if (h != NULL && h->stub_cache != NULL
4574 && h->stub_cache->h == h
fe33d2fa
CL		 4575 && h->stub_cache->id_sec == id_sec
4576 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4577 {
4578 stub_entry = h->stub_cache;
4579 }
4580 else
4581 {
4582 char *stub_name;
4583
fe33d2fa 4584 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4585 if (stub_name == NULL)
4586 return NULL;
4587
4588 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4589 stub_name, FALSE, FALSE);
4590 if (h != NULL)
4591 h->stub_cache = stub_entry;
4592
4593 free (stub_name);
4594 }
4595
4596 return stub_entry;
4597}
4598
daa4adae
TP		 4599/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4600 section. */
4601
4602static bfd_boolean
4603arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4604{
4605 if (stub_type >= max_stub_type)
4606 abort (); /* Should be unreachable. */
4607
4ba2ef8f
TP		 4608 switch (stub_type)
4609 {
4610 case arm_stub_cmse_branch_thumb_only:
4611 return TRUE;
4612
4613 default:
4614 return FALSE;
4615 }
4616
4617 abort (); /* Should be unreachable. */
daa4adae
TP		 4618}
4619
4620/* Required alignment (as a power of 2) for the dedicated section holding
4621 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4622 with input sections. */
4623
4624static int
4625arm_dedicated_stub_output_section_required_alignment
4626 (enum elf32_arm_stub_type stub_type)
4627{
4628 if (stub_type >= max_stub_type)
4629 abort (); /* Should be unreachable. */
4630
4ba2ef8f
TP		 4631 switch (stub_type)
4632 {
4633 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4634 boundary. */
4635 case arm_stub_cmse_branch_thumb_only:
4636 return 5;
4637
4638 default:
4639 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4640 return 0;
4641 }
4642
4643 abort (); /* Should be unreachable. */
daa4adae
TP		 4644}
4645
4646/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4647 NULL if veneers of this type are interspersed with input sections. */
4648
4649static const char *
4650arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4651{
4652 if (stub_type >= max_stub_type)
4653 abort (); /* Should be unreachable. */
4654
4ba2ef8f
TP		 4655 switch (stub_type)
4656 {
4657 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4658 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4659
4660 default:
4661 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4662 return NULL;
4663 }
4664
4665 abort (); /* Should be unreachable. */
daa4adae
TP		 4666}
4667
4668/* If veneers of type STUB_TYPE should go in a dedicated output section,
4669 returns the address of the hash table field in HTAB holding a pointer to the
4670 corresponding input section. Otherwise, returns NULL. */
4671
4672static asection **
4ba2ef8f
TP		 4673arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4674 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4675{
4676 if (stub_type >= max_stub_type)
4677 abort (); /* Should be unreachable. */
4678
4ba2ef8f
TP		 4679 switch (stub_type)
4680 {
4681 case arm_stub_cmse_branch_thumb_only:
4682 return &htab->cmse_stub_sec;
4683
4684 default:
4685 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4686 return NULL;
4687 }
4688
4689 abort (); /* Should be unreachable. */
daa4adae
TP		 4690}
4691
4692/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4693 is the section that branch into veneer and can be NULL if stub should go in
4694 a dedicated output section. Returns a pointer to the stub section, and the
4695 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4696 LINK_SEC_P may be NULL. */
906e58ca 4697
48229727
JB		 4698static asection *
4699elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4700 struct elf32_arm_link_hash_table *htab,
4701 enum elf32_arm_stub_type stub_type)
906e58ca 4702{
daa4adae
TP		 4703 asection *link_sec, *out_sec, **stub_sec_p;
4704 const char *stub_sec_prefix;
4705 bfd_boolean dedicated_output_section =
4706 arm_dedicated_stub_output_section_required (stub_type);
4707 int align;
906e58ca 4708
daa4adae 4709 if (dedicated_output_section)
906e58ca 4710 {
daa4adae
TP		 4711 bfd *output_bfd = htab->obfd;
4712 const char *out_sec_name =
4713 arm_dedicated_stub_output_section_name (stub_type);
4714 link_sec = NULL;
4715 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4716 stub_sec_prefix = out_sec_name;
4717 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4718 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4719 if (out_sec == NULL)
906e58ca 4720 {
90b6238f 4721 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4722 "section %s"), out_sec_name);
daa4adae 4723 return NULL;
906e58ca 4724 }
daa4adae
TP		 4725 }
4726 else
4727 {
c2abbbeb 4728 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4729 link_sec = htab->stub_group[section->id].link_sec;
4730 BFD_ASSERT (link_sec != NULL);
4731 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4732 if (*stub_sec_p == NULL)
4733 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4734 stub_sec_prefix = link_sec->name;
4735 out_sec = link_sec->output_section;
90c14f0c 4736 align = htab->root.target_os == is_nacl ? 4 : 3;
906e58ca 4737 }
b38cadfb 4738
daa4adae
TP		 4739 if (*stub_sec_p == NULL)
4740 {
4741 size_t namelen;
4742 bfd_size_type len;
4743 char *s_name;
4744
4745 namelen = strlen (stub_sec_prefix);
4746 len = namelen + sizeof (STUB_SUFFIX);
4747 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4748 if (s_name == NULL)
4749 return NULL;
4750
4751 memcpy (s_name, stub_sec_prefix, namelen);
4752 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4753 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4754 align);
4755 if (*stub_sec_p == NULL)
4756 return NULL;
4757
4758 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4759 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4760 | SEC_KEEP;
4761 }
4762
4763 if (!dedicated_output_section)
4764 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4765
48229727
JB		 4766 if (link_sec_p)
4767 *link_sec_p = link_sec;
b38cadfb 4768
daa4adae 4769 return *stub_sec_p;
48229727
JB		 4770}
4771
4772/* Add a new stub entry to the stub hash. Not all fields of the new
4773 stub entry are initialised. */
4774
4775static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4776elf32_arm_add_stub (const char *stub_name, asection *section,
4777 struct elf32_arm_link_hash_table *htab,
4778 enum elf32_arm_stub_type stub_type)
48229727
JB		 4779{
4780 asection *link_sec;
4781 asection *stub_sec;
4782 struct elf32_arm_stub_hash_entry *stub_entry;
4783
daa4adae
TP		 4784 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4785 stub_type);
48229727
JB		 4786 if (stub_sec == NULL)
4787 return NULL;
906e58ca
NC		 4788
4789 /* Enter this entry into the linker stub hash table. */
4790 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4791 TRUE, FALSE);
4792 if (stub_entry == NULL)
4793 {
6bde4c52
TP		 4794 if (section == NULL)
4795 section = stub_sec;
871b3ab2 4796 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4797 section->owner, stub_name);
906e58ca
NC		 4798 return NULL;
4799 }
4800
4801 stub_entry->stub_sec = stub_sec;
0955507f 4802 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4803 stub_entry->id_sec = link_sec;
4804
906e58ca
NC		 4805 return stub_entry;
4806}
4807
4808/* Store an Arm insn into an output section not processed by
4809 elf32_arm_write_section. */
4810
4811static void
8029a119
NC		 4812put_arm_insn (struct elf32_arm_link_hash_table * htab,
4813 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4814{
4815 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4816 bfd_putl32 (val, ptr);
4817 else
4818 bfd_putb32 (val, ptr);
4819}
4820
4821/* Store a 16-bit Thumb insn into an output section not processed by
4822 elf32_arm_write_section. */
4823
4824static void
8029a119
NC		 4825put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4826 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4827{
4828 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4829 bfd_putl16 (val, ptr);
4830 else
4831 bfd_putb16 (val, ptr);
4832}
4833
a504d23a
LA		 4834/* Store a Thumb2 insn into an output section not processed by
4835 elf32_arm_write_section. */
4836
4837static void
4838put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4839 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4840{
4841 /* T2 instructions are 16-bit streamed. */
4842 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4843 {
4844 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4845 bfd_putl16 ((val & 0xffff), ptr + 2);
4846 }
4847 else
4848 {
4849 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4850 bfd_putb16 ((val & 0xffff), ptr + 2);
4851 }
4852}
4853
0855e32b
NS		 4854/* If it's possible to change R_TYPE to a more efficient access
4855 model, return the new reloc type. */
4856
4857static unsigned
b38cadfb 4858elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4859 struct elf_link_hash_entry *h)
4860{
4861 int is_local = (h == NULL);
4862
9cb09e33 4863 if (bfd_link_dll (info)
0e1862bb 4864 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4865 return r_type;
4866
b38cadfb 4867 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4868 switch (r_type)
4869 {
4870 case R_ARM_TLS_GOTDESC:
4871 case R_ARM_TLS_CALL:
4872 case R_ARM_THM_TLS_CALL:
4873 case R_ARM_TLS_DESCSEQ:
4874 case R_ARM_THM_TLS_DESCSEQ:
4875 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4876 }
4877
4878 return r_type;
4879}
4880
48229727
JB		 4881static bfd_reloc_status_type elf32_arm_final_link_relocate
4882 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4883 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4884 const char *, unsigned char, enum arm_st_branch_type,
4885 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4886
4563a860
JB		 4887static unsigned int
4888arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4889{
4890 switch (stub_type)
4891 {
4892 case arm_stub_a8_veneer_b_cond:
4893 case arm_stub_a8_veneer_b:
4894 case arm_stub_a8_veneer_bl:
4895 return 2;
4896
4897 case arm_stub_long_branch_any_any:
4898 case arm_stub_long_branch_v4t_arm_thumb:
4899 case arm_stub_long_branch_thumb_only:
80c135e5 4900 case arm_stub_long_branch_thumb2_only:
d5a67c02 4901 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4902 case arm_stub_long_branch_v4t_thumb_thumb:
4903 case arm_stub_long_branch_v4t_thumb_arm:
4904 case arm_stub_short_branch_v4t_thumb_arm:
4905 case arm_stub_long_branch_any_arm_pic:
4906 case arm_stub_long_branch_any_thumb_pic:
4907 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4908 case arm_stub_long_branch_v4t_arm_thumb_pic:
4909 case arm_stub_long_branch_v4t_thumb_arm_pic:
4910 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4911 case arm_stub_long_branch_any_tls_pic:
4912 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4913 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4914 case arm_stub_a8_veneer_blx:
4915 return 4;
b38cadfb 4916
7a89b94e
NC		 4917 case arm_stub_long_branch_arm_nacl:
4918 case arm_stub_long_branch_arm_nacl_pic:
4919 return 16;
4920
4563a860
JB		 4921 default:
4922 abort (); /* Should be unreachable. */
4923 }
4924}
4925
4f4faa4d
TP		 4926/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4927 veneering (TRUE) or have their own symbol (FALSE). */
4928
4929static bfd_boolean
4930arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4931{
4932 if (stub_type >= max_stub_type)
4933 abort (); /* Should be unreachable. */
4934
4ba2ef8f
TP		 4935 switch (stub_type)
4936 {
4937 case arm_stub_cmse_branch_thumb_only:
4938 return TRUE;
4939
4940 default:
4941 return FALSE;
4942 }
4943
4944 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4945}
4946
d7c5bd02
TP		 4947/* Returns the padding needed for the dedicated section used stubs of type
4948 STUB_TYPE. */
4949
4950static int
4951arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4952{
4953 if (stub_type >= max_stub_type)
4954 abort (); /* Should be unreachable. */
4955
4ba2ef8f
TP		 4956 switch (stub_type)
4957 {
4958 case arm_stub_cmse_branch_thumb_only:
4959 return 32;
4960
4961 default:
4962 return 0;
4963 }
4964
4965 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4966}
4967
0955507f
TP		 4968/* If veneers of type STUB_TYPE should go in a dedicated output section,
4969 returns the address of the hash table field in HTAB holding the offset at
4970 which new veneers should be layed out in the stub section. */
4971
4972static bfd_vma*
4973arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4974 enum elf32_arm_stub_type stub_type)
4975{
4976 switch (stub_type)
4977 {
4978 case arm_stub_cmse_branch_thumb_only:
4979 return &htab->new_cmse_stub_offset;
4980
4981 default:
4982 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4983 return NULL;
4984 }
4985}
4986
906e58ca
NC		 4987static bfd_boolean
4988arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4989 void * in_arg)
4990{
7a89b94e 4991#define MAXRELOCS 3
0955507f 4992 bfd_boolean removed_sg_veneer;
906e58ca 4993 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4994 struct elf32_arm_link_hash_table *globals;
906e58ca 4995 struct bfd_link_info *info;
906e58ca
NC		 4996 asection *stub_sec;
4997 bfd *stub_bfd;
906e58ca
NC		 4998 bfd_byte *loc;
4999 bfd_vma sym_value;
5000 int template_size;
5001 int size;
d3ce72d0 5002 const insn_sequence *template_sequence;
906e58ca 5003 int i;
48229727
JB		 5004 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5005 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5006 int nrelocs = 0;
0955507f 5007 int just_allocated = 0;
906e58ca
NC		 5008
5009 /* Massage our args to the form they really have. */
5010 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5011 info = (struct bfd_link_info *) in_arg;
5012
abf874aa
CL		 5013 /* Fail if the target section could not be assigned to an output
5014 section. The user should fix his linker script. */
5015 if (stub_entry->target_section->output_section == NULL
5016 && info->non_contiguous_regions)
53215f21
CL		 5017 info->callbacks->einfo (_("%F%P: Could not assign '%pA' to an output section. "
5018 "Retry without --enable-non-contiguous-regions.\n"),
5019 stub_entry->target_section);
abf874aa 5020
906e58ca 5021 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5022 if (globals == NULL)
5023 return FALSE;
906e58ca 5024
906e58ca
NC		 5025 stub_sec = stub_entry->stub_sec;
5026
4dfe6ac6 5027 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5028 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5029 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5030 return TRUE;
fe33d2fa 5031
0955507f
TP		 5032 /* Assign a slot at the end of section if none assigned yet. */
5033 if (stub_entry->stub_offset == (bfd_vma) -1)
5034 {
5035 stub_entry->stub_offset = stub_sec->size;
5036 just_allocated = 1;
5037 }
906e58ca
NC		 5038 loc = stub_sec->contents + stub_entry->stub_offset;
5039
5040 stub_bfd = stub_sec->owner;
5041
906e58ca
NC		 5042 /* This is the address of the stub destination. */
5043 sym_value = (stub_entry->target_value
5044 + stub_entry->target_section->output_offset
5045 + stub_entry->target_section->output_section->vma);
5046
d3ce72d0 5047 template_sequence = stub_entry->stub_template;
461a49ca 5048 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5049
5050 size = 0;
461a49ca 5051 for (i = 0; i < template_size; i++)
906e58ca 5052 {
d3ce72d0 5053 switch (template_sequence[i].type)
461a49ca
DJ		 5054 {
5055 case THUMB16_TYPE:
48229727 5056 {
d3ce72d0
NC		 5057 bfd_vma data = (bfd_vma) template_sequence[i].data;
5058 if (template_sequence[i].reloc_addend != 0)
48229727 5059 {
99059e56
RM		 5060 /* We've borrowed the reloc_addend field to mean we should
5061 insert a condition code into this (Thumb-1 branch)
5062 instruction. See THUMB16_BCOND_INSN. */
5063 BFD_ASSERT ((data & 0xff00) == 0xd000);
5064 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5065 }
fe33d2fa 5066 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5067 size += 2;
5068 }
461a49ca 5069 break;
906e58ca 5070
48229727 5071 case THUMB32_TYPE:
fe33d2fa
CL		 5072 bfd_put_16 (stub_bfd,
5073 (template_sequence[i].data >> 16) & 0xffff,
5074 loc + size);
5075 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5076 loc + size + 2);
99059e56
RM		 5077 if (template_sequence[i].r_type != R_ARM_NONE)
5078 {
5079 stub_reloc_idx[nrelocs] = i;
5080 stub_reloc_offset[nrelocs++] = size;
5081 }
5082 size += 4;
5083 break;
48229727 5084
461a49ca 5085 case ARM_TYPE:
fe33d2fa
CL		 5086 bfd_put_32 (stub_bfd, template_sequence[i].data,
5087 loc + size);
461a49ca
DJ		 5088 /* Handle cases where the target is encoded within the
5089 instruction. */
d3ce72d0 5090 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5091 {
48229727
JB		 5092 stub_reloc_idx[nrelocs] = i;
5093 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5094 }
5095 size += 4;
5096 break;
5097
5098 case DATA_TYPE:
d3ce72d0 5099 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5100 stub_reloc_idx[nrelocs] = i;
5101 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5102 size += 4;
5103 break;
5104
5105 default:
5106 BFD_FAIL ();
5107 return FALSE;
5108 }
906e58ca 5109 }
461a49ca 5110
0955507f
TP		 5111 if (just_allocated)
5112 stub_sec->size += size;
906e58ca 5113
461a49ca
DJ		 5114 /* Stub size has already been computed in arm_size_one_stub. Check
5115 consistency. */
5116 BFD_ASSERT (size == stub_entry->stub_size);
5117
906e58ca 5118 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5119 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5120 sym_value |= 1;
5121
0955507f
TP		 5122 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5123 to relocate in each stub. */
5124 removed_sg_veneer =
5125 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5126 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5127
48229727 5128 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5129 {
5130 Elf_Internal_Rela rel;
5131 bfd_boolean unresolved_reloc;
5132 char *error_message;
5133 bfd_vma points_to =
5134 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5135
5136 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5137 rel.r_info = ELF32_R_INFO (0,
5138 template_sequence[stub_reloc_idx[i]].r_type);
5139 rel.r_addend = 0;
5140
5141 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5142 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5143 template should refer back to the instruction after the original
5144 branch. We use target_section as Cortex-A8 erratum workaround stubs
5145 are only generated when both source and target are in the same
5146 section. */
5147 points_to = stub_entry->target_section->output_section->vma
5148 + stub_entry->target_section->output_offset
5149 + stub_entry->source_value;
5150
5151 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5152 (template_sequence[stub_reloc_idx[i]].r_type),
5153 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5154 points_to, info, stub_entry->target_section, "", STT_FUNC,
5155 stub_entry->branch_type,
5156 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5157 &error_message);
5158 }
906e58ca
NC		 5159
5160 return TRUE;
48229727 5161#undef MAXRELOCS
906e58ca
NC		 5162}
5163
48229727
JB		 5164/* Calculate the template, template size and instruction size for a stub.
5165 Return value is the instruction size. */
906e58ca 5166
48229727
JB		 5167static unsigned int
5168find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5169 const insn_sequence **stub_template,
5170 int *stub_template_size)
906e58ca 5171{
d3ce72d0 5172 const insn_sequence *template_sequence = NULL;
48229727
JB		 5173 int template_size = 0, i;
5174 unsigned int size;
906e58ca 5175
d3ce72d0 5176 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5177 if (stub_template)
5178 *stub_template = template_sequence;
5179
48229727 5180 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5181 if (stub_template_size)
5182 *stub_template_size = template_size;
906e58ca
NC		 5183
5184 size = 0;
461a49ca
DJ		 5185 for (i = 0; i < template_size; i++)
5186 {
d3ce72d0 5187 switch (template_sequence[i].type)
461a49ca
DJ		 5188 {
5189 case THUMB16_TYPE:
5190 size += 2;
5191 break;
5192
5193 case ARM_TYPE:
48229727 5194 case THUMB32_TYPE:
461a49ca
DJ		 5195 case DATA_TYPE:
5196 size += 4;
5197 break;
5198
5199 default:
5200 BFD_FAIL ();
2a229407 5201 return 0;
461a49ca
DJ		 5202 }
5203 }
5204
48229727
JB		 5205 return size;
5206}
5207
5208/* As above, but don't actually build the stub. Just bump offset so
5209 we know stub section sizes. */
5210
5211static bfd_boolean
5212arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5213 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5214{
5215 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5216 const insn_sequence *template_sequence;
48229727
JB		 5217 int template_size, size;
5218
5219 /* Massage our args to the form they really have. */
5220 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5221
5222 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5223 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5224
d3ce72d0 5225 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5226 &template_size);
5227
0955507f
TP		 5228 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5229 if (stub_entry->stub_template_size)
5230 {
5231 stub_entry->stub_size = size;
5232 stub_entry->stub_template = template_sequence;
5233 stub_entry->stub_template_size = template_size;
5234 }
5235
5236 /* Already accounted for. */
5237 if (stub_entry->stub_offset != (bfd_vma) -1)
5238 return TRUE;
461a49ca 5239
906e58ca
NC		 5240 size = (size + 7) & ~7;
5241 stub_entry->stub_sec->size += size;
461a49ca 5242
906e58ca
NC		 5243 return TRUE;
5244}
5245
5246/* External entry points for sizing and building linker stubs. */
5247
5248/* Set up various things so that we can make a list of input sections
5249 for each output section included in the link. Returns -1 on error,
5250 0 when no stubs will be needed, and 1 on success. */
5251
5252int
5253elf32_arm_setup_section_lists (bfd *output_bfd,
5254 struct bfd_link_info *info)
5255{
5256 bfd *input_bfd;
5257 unsigned int bfd_count;
7292b3ac 5258 unsigned int top_id, top_index;
906e58ca
NC		 5259 asection *section;
5260 asection **input_list, **list;
986f0783 5261 size_t amt;
906e58ca
NC		 5262 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5263
4dfe6ac6
NC		 5264 if (htab == NULL)
5265 return 0;
906e58ca
NC		 5266 if (! is_elf_hash_table (htab))
5267 return 0;
5268
5269 /* Count the number of input BFDs and find the top input section id. */
5270 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5271 input_bfd != NULL;
c72f2fb2 5272 input_bfd = input_bfd->link.next)
906e58ca
NC		 5273 {
5274 bfd_count += 1;
5275 for (section = input_bfd->sections;
5276 section != NULL;
5277 section = section->next)
5278 {
5279 if (top_id < section->id)
5280 top_id = section->id;
5281 }
5282 }
5283 htab->bfd_count = bfd_count;
5284
5285 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5286 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5287 if (htab->stub_group == NULL)
5288 return -1;
fe33d2fa 5289 htab->top_id = top_id;
906e58ca
NC		 5290
5291 /* We can't use output_bfd->section_count here to find the top output
5292 section index as some sections may have been removed, and
5293 _bfd_strip_section_from_output doesn't renumber the indices. */
5294 for (section = output_bfd->sections, top_index = 0;
5295 section != NULL;
5296 section = section->next)
5297 {
5298 if (top_index < section->index)
5299 top_index = section->index;
5300 }
5301
5302 htab->top_index = top_index;
5303 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5304 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5305 htab->input_list = input_list;
5306 if (input_list == NULL)
5307 return -1;
5308
5309 /* For sections we aren't interested in, mark their entries with a
5310 value we can check later. */
5311 list = input_list + top_index;
5312 do
5313 *list = bfd_abs_section_ptr;
5314 while (list-- != input_list);
5315
5316 for (section = output_bfd->sections;
5317 section != NULL;
5318 section = section->next)
5319 {
5320 if ((section->flags & SEC_CODE) != 0)
5321 input_list[section->index] = NULL;
5322 }
5323
5324 return 1;
5325}
5326
5327/* The linker repeatedly calls this function for each input section,
5328 in the order that input sections are linked into output sections.
5329 Build lists of input sections to determine groupings between which
5330 we may insert linker stubs. */
5331
5332void
5333elf32_arm_next_input_section (struct bfd_link_info *info,
5334 asection *isec)
5335{
5336 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5337
4dfe6ac6
NC		 5338 if (htab == NULL)
5339 return;
5340
906e58ca
NC		 5341 if (isec->output_section->index <= htab->top_index)
5342 {
5343 asection **list = htab->input_list + isec->output_section->index;
5344
a7470592 5345 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5346 {
5347 /* Steal the link_sec pointer for our list. */
5348#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5349 /* This happens to make the list in reverse order,
07d72278 5350 which we reverse later. */
906e58ca
NC		 5351 PREV_SEC (isec) = *list;
5352 *list = isec;
5353 }
5354 }
5355}
5356
5357/* See whether we can group stub sections together. Grouping stub
5358 sections may result in fewer stubs. More importantly, we need to
07d72278 5359 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5360 .fini output sections respectively, because glibc splits the
5361 _init and _fini functions into multiple parts. Putting a stub in
5362 the middle of a function is not a good idea. */
5363
5364static void
5365group_sections (struct elf32_arm_link_hash_table *htab,
5366 bfd_size_type stub_group_size,
07d72278 5367 bfd_boolean stubs_always_after_branch)
906e58ca 5368{
07d72278 5369 asection **list = htab->input_list;
906e58ca
NC		 5370
5371 do
5372 {
5373 asection *tail = *list;
07d72278 5374 asection *head;
906e58ca
NC		 5375
5376 if (tail == bfd_abs_section_ptr)
5377 continue;
5378
07d72278
DJ		 5379 /* Reverse the list: we must avoid placing stubs at the
5380 beginning of the section because the beginning of the text
5381 section may be required for an interrupt vector in bare metal
5382 code. */
5383#define NEXT_SEC PREV_SEC
e780aef2
CL		 5384 head = NULL;
5385 while (tail != NULL)
99059e56
RM		 5386 {
5387 /* Pop from tail. */
5388 asection *item = tail;
5389 tail = PREV_SEC (item);
e780aef2 5390
99059e56
RM		 5391 /* Push on head. */
5392 NEXT_SEC (item) = head;
5393 head = item;
5394 }
07d72278
DJ		 5395
5396 while (head != NULL)
906e58ca
NC		 5397 {
5398 asection *curr;
07d72278 5399 asection *next;
e780aef2
CL		 5400 bfd_vma stub_group_start = head->output_offset;
5401 bfd_vma end_of_next;
906e58ca 5402
07d72278 5403 curr = head;
e780aef2 5404 while (NEXT_SEC (curr) != NULL)
8cd931b7 5405 {
e780aef2
CL		 5406 next = NEXT_SEC (curr);
5407 end_of_next = next->output_offset + next->size;
5408 if (end_of_next - stub_group_start >= stub_group_size)
5409 /* End of NEXT is too far from start, so stop. */
8cd931b7 5410 break;
e780aef2
CL		 5411 /* Add NEXT to the group. */
5412 curr = next;
8cd931b7 5413 }
906e58ca 5414
07d72278 5415 /* OK, the size from the start to the start of CURR is less
906e58ca 5416 than stub_group_size and thus can be handled by one stub
07d72278 5417 section. (Or the head section is itself larger than
906e58ca
NC		 5418 stub_group_size, in which case we may be toast.)
5419 We should really be keeping track of the total size of
5420 stubs added here, as stubs contribute to the final output
7fb9f789 5421 section size. */
906e58ca
NC		 5422 do
5423 {
07d72278 5424 next = NEXT_SEC (head);
906e58ca 5425 /* Set up this stub group. */
07d72278 5426 htab->stub_group[head->id].link_sec = curr;
906e58ca 5427 }
07d72278 5428 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5429
5430 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5431 bytes after the stub section can be handled by it too. */
5432 if (!stubs_always_after_branch)
906e58ca 5433 {
e780aef2
CL		 5434 stub_group_start = curr->output_offset + curr->size;
5435
8cd931b7 5436 while (next != NULL)
906e58ca 5437 {
e780aef2
CL		 5438 end_of_next = next->output_offset + next->size;
5439 if (end_of_next - stub_group_start >= stub_group_size)
5440 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5441 break;
e780aef2 5442 /* Add NEXT to the stub group. */
07d72278
DJ		 5443 head = next;
5444 next = NEXT_SEC (head);
5445 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5446 }
5447 }
07d72278 5448 head = next;
906e58ca
NC		 5449 }
5450 }
07d72278 5451 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5452
5453 free (htab->input_list);
5454#undef PREV_SEC
07d72278 5455#undef NEXT_SEC
906e58ca
NC		 5456}
5457
48229727
JB		 5458/* Comparison function for sorting/searching relocations relating to Cortex-A8
5459 erratum fix. */
5460
5461static int
5462a8_reloc_compare (const void *a, const void *b)
5463{
21d799b5
NC		 5464 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5465 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5466
5467 if (ra->from < rb->from)
5468 return -1;
5469 else if (ra->from > rb->from)
5470 return 1;
5471 else
5472 return 0;
5473}
5474
5475static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5476 const char *, char **);
5477
5478/* Helper function to scan code for sequences which might trigger the Cortex-A8
5479 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5480 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5481 otherwise. */
5482
81694485
NC		 5483static bfd_boolean
5484cortex_a8_erratum_scan (bfd *input_bfd,
5485 struct bfd_link_info *info,
48229727
JB		 5486 struct a8_erratum_fix **a8_fixes_p,
5487 unsigned int *num_a8_fixes_p,
5488 unsigned int *a8_fix_table_size_p,
5489 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5490 unsigned int num_a8_relocs,
5491 unsigned prev_num_a8_fixes,
5492 bfd_boolean *stub_changed_p)
48229727
JB		 5493{
5494 asection *section;
5495 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5496 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5497 unsigned int num_a8_fixes = *num_a8_fixes_p;
5498 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5499
4dfe6ac6
NC		 5500 if (htab == NULL)
5501 return FALSE;
5502
48229727
JB		 5503 for (section = input_bfd->sections;
5504 section != NULL;
5505 section = section->next)
5506 {
5507 bfd_byte *contents = NULL;
5508 struct _arm_elf_section_data *sec_data;
5509 unsigned int span;
5510 bfd_vma base_vma;
5511
5512 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5513 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5514 || (section->flags & SEC_EXCLUDE) != 0
5515 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5516 || (section->output_section == bfd_abs_section_ptr))
5517 continue;
48229727
JB		 5518
5519 base_vma = section->output_section->vma + section->output_offset;
5520
5521 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5522 contents = elf_section_data (section)->this_hdr.contents;
48229727 5523 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5524 return TRUE;
48229727
JB		 5525
5526 sec_data = elf32_arm_section_data (section);
5527
5528 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5529 {
5530 unsigned int span_start = sec_data->map[span].vma;
5531 unsigned int span_end = (span == sec_data->mapcount - 1)
5532 ? section->size : sec_data->map[span + 1].vma;
5533 unsigned int i;
5534 char span_type = sec_data->map[span].type;
5535 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5536
5537 if (span_type != 't')
5538 continue;
5539
5540 /* Span is entirely within a single 4KB region: skip scanning. */
5541 if (((base_vma + span_start) & ~0xfff)
48229727 5542 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5543 continue;
5544
5545 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5546
5547 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5548 * The branch target is in the same 4KB region as the
5549 first half of the branch.
5550 * The instruction before the branch is a 32-bit
5551 length non-branch instruction. */
5552 for (i = span_start; i < span_end;)
5553 {
5554 unsigned int insn = bfd_getl16 (&contents[i]);
5555 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5556 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5557
99059e56
RM		 5558 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5559 insn_32bit = TRUE;
48229727
JB		 5560
5561 if (insn_32bit)
99059e56
RM		 5562 {
5563 /* Load the rest of the insn (in manual-friendly order). */
5564 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5565
5566 /* Encoding T4: B<c>.W. */
5567 is_b = (insn & 0xf800d000) == 0xf0009000;
5568 /* Encoding T1: BL<c>.W. */
5569 is_bl = (insn & 0xf800d000) == 0xf000d000;
5570 /* Encoding T2: BLX<c>.W. */
5571 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5572 /* Encoding T3: B<c>.W (not permitted in IT block). */
5573 is_bcc = (insn & 0xf800d000) == 0xf0008000
5574 && (insn & 0x07f00000) != 0x03800000;
5575 }
5576
5577 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5578
99059e56 5579 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5580 && insn_32bit
5581 && is_32bit_branch
5582 && last_was_32bit
5583 && ! last_was_branch)
99059e56
RM		 5584 {
5585 bfd_signed_vma offset = 0;
5586 bfd_boolean force_target_arm = FALSE;
48229727 5587 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5588 bfd_vma target;
5589 enum elf32_arm_stub_type stub_type = arm_stub_none;
5590 struct a8_erratum_reloc key, *found;
5591 bfd_boolean use_plt = FALSE;
48229727 5592
99059e56
RM		 5593 key.from = base_vma + i;
5594 found = (struct a8_erratum_reloc *)
5595 bsearch (&key, a8_relocs, num_a8_relocs,
5596 sizeof (struct a8_erratum_reloc),
5597 &a8_reloc_compare);
48229727
JB		 5598
5599 if (found)
5600 {
5601 char *error_message = NULL;
5602 struct elf_link_hash_entry *entry;
5603
5604 /* We don't care about the error returned from this
99059e56 5605 function, only if there is glue or not. */
48229727
JB		 5606 entry = find_thumb_glue (info, found->sym_name,
5607 &error_message);
5608
5609 if (entry)
5610 found->non_a8_stub = TRUE;
5611
92750f34 5612 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5613 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5614 && found->hash->root.plt.offset != (bfd_vma) -1)
5615 use_plt = TRUE;
5616
5617 if (found->r_type == R_ARM_THM_CALL)
5618 {
35fc36a8
RS		 5619 if (found->branch_type == ST_BRANCH_TO_ARM
5620 || use_plt)
92750f34
DJ		 5621 force_target_arm = TRUE;
5622 else
5623 force_target_thumb = TRUE;
5624 }
48229727
JB		 5625 }
5626
99059e56 5627 /* Check if we have an offending branch instruction. */
48229727
JB		 5628
5629 if (found && found->non_a8_stub)
5630 /* We've already made a stub for this instruction, e.g.
5631 it's a long branch or a Thumb->ARM stub. Assume that
5632 stub will suffice to work around the A8 erratum (see
5633 setting of always_after_branch above). */
5634 ;
99059e56
RM		 5635 else if (is_bcc)
5636 {
5637 offset = (insn & 0x7ff) << 1;
5638 offset |= (insn & 0x3f0000) >> 4;
5639 offset |= (insn & 0x2000) ? 0x40000 : 0;
5640 offset |= (insn & 0x800) ? 0x80000 : 0;
5641 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5642 if (offset & 0x100000)
5643 offset |= ~ ((bfd_signed_vma) 0xfffff);
5644 stub_type = arm_stub_a8_veneer_b_cond;
5645 }
5646 else if (is_b || is_bl || is_blx)
5647 {
5648 int s = (insn & 0x4000000) != 0;
5649 int j1 = (insn & 0x2000) != 0;
5650 int j2 = (insn & 0x800) != 0;
5651 int i1 = !(j1 ^ s);
5652 int i2 = !(j2 ^ s);
5653
5654 offset = (insn & 0x7ff) << 1;
5655 offset |= (insn & 0x3ff0000) >> 4;
5656 offset |= i2 << 22;
5657 offset |= i1 << 23;
5658 offset |= s << 24;
5659 if (offset & 0x1000000)
5660 offset |= ~ ((bfd_signed_vma) 0xffffff);
5661
5662 if (is_blx)
5663 offset &= ~ ((bfd_signed_vma) 3);
5664
5665 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5666 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5667 }
5668
5669 if (stub_type != arm_stub_none)
5670 {
5671 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5672
5673 /* The original instruction is a BL, but the target is
99059e56 5674 an ARM instruction. If we were not making a stub,
48229727
JB		 5675 the BL would have been converted to a BLX. Use the
5676 BLX stub instead in that case. */
5677 if (htab->use_blx && force_target_arm
5678 && stub_type == arm_stub_a8_veneer_bl)
5679 {
5680 stub_type = arm_stub_a8_veneer_blx;
5681 is_blx = TRUE;
5682 is_bl = FALSE;
5683 }
5684 /* Conversely, if the original instruction was
5685 BLX but the target is Thumb mode, use the BL
5686 stub. */
5687 else if (force_target_thumb
5688 && stub_type == arm_stub_a8_veneer_blx)
5689 {
5690 stub_type = arm_stub_a8_veneer_bl;
5691 is_blx = FALSE;
5692 is_bl = TRUE;
5693 }
5694
99059e56
RM		 5695 if (is_blx)
5696 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5697
99059e56
RM		 5698 /* If we found a relocation, use the proper destination,
5699 not the offset in the (unrelocated) instruction.
48229727
JB		 5700 Note this is always done if we switched the stub type
5701 above. */
99059e56
RM		 5702 if (found)
5703 offset =
81694485 5704 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5705
99059e56
RM		 5706 /* If the stub will use a Thumb-mode branch to a
5707 PLT target, redirect it to the preceding Thumb
5708 entry point. */
5709 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5710 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5711
99059e56 5712 target = pc_for_insn + offset;
48229727 5713
99059e56
RM		 5714 /* The BLX stub is ARM-mode code. Adjust the offset to
5715 take the different PC value (+8 instead of +4) into
48229727 5716 account. */
99059e56
RM		 5717 if (stub_type == arm_stub_a8_veneer_blx)
5718 offset += 4;
5719
5720 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5721 {
5722 char *stub_name = NULL;
5723
5724 if (num_a8_fixes == a8_fix_table_size)
5725 {
5726 a8_fix_table_size *= 2;
5727 a8_fixes = (struct a8_erratum_fix *)
5728 bfd_realloc (a8_fixes,
5729 sizeof (struct a8_erratum_fix)
5730 * a8_fix_table_size);
5731 }
48229727 5732
eb7c4339
NS		 5733 if (num_a8_fixes < prev_num_a8_fixes)
5734 {
5735 /* If we're doing a subsequent scan,
5736 check if we've found the same fix as
5737 before, and try and reuse the stub
5738 name. */
5739 stub_name = a8_fixes[num_a8_fixes].stub_name;
5740 if ((a8_fixes[num_a8_fixes].section != section)
5741 || (a8_fixes[num_a8_fixes].offset != i))
5742 {
5743 free (stub_name);
5744 stub_name = NULL;
5745 *stub_changed_p = TRUE;
5746 }
5747 }
5748
5749 if (!stub_name)
5750 {
21d799b5 5751 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5752 if (stub_name != NULL)
5753 sprintf (stub_name, "%x:%x", section->id, i);
5754 }
48229727 5755
99059e56
RM		 5756 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5757 a8_fixes[num_a8_fixes].section = section;
5758 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5759 a8_fixes[num_a8_fixes].target_offset =
5760 target - base_vma;
99059e56
RM		 5761 a8_fixes[num_a8_fixes].orig_insn = insn;
5762 a8_fixes[num_a8_fixes].stub_name = stub_name;
5763 a8_fixes[num_a8_fixes].stub_type = stub_type;
5764 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5765 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5766
99059e56
RM		 5767 num_a8_fixes++;
5768 }
5769 }
5770 }
48229727 5771
99059e56
RM		 5772 i += insn_32bit ? 4 : 2;
5773 last_was_32bit = insn_32bit;
48229727 5774 last_was_branch = is_32bit_branch;
99059e56
RM		 5775 }
5776 }
48229727
JB		 5777
5778 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5779 free (contents);
48229727 5780 }
fe33d2fa 5781
48229727
JB		 5782 *a8_fixes_p = a8_fixes;
5783 *num_a8_fixes_p = num_a8_fixes;
5784 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5785
81694485 5786 return FALSE;
48229727
JB		 5787}
5788
b715f643
TP		 5789/* Create or update a stub entry depending on whether the stub can already be
5790 found in HTAB. The stub is identified by:
5791 - its type STUB_TYPE
5792 - its source branch (note that several can share the same stub) whose
5793 section and relocation (if any) are given by SECTION and IRELA
5794 respectively
5795 - its target symbol whose input section, hash, name, value and branch type
5796 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5797 respectively
5798
5799 If found, the value of the stub's target symbol is updated from SYM_VALUE
5800 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5801 TRUE and the stub entry is initialized.
5802
0955507f
TP		 5803 Returns the stub that was created or updated, or NULL if an error
5804 occurred. */
b715f643 5805
0955507f 5806static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5807elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5808 enum elf32_arm_stub_type stub_type, asection *section,
5809 Elf_Internal_Rela *irela, asection *sym_sec,
5810 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5811 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5812 bfd_boolean *new_stub)
5813{
5814 const asection *id_sec;
5815 char *stub_name;
5816 struct elf32_arm_stub_hash_entry *stub_entry;
5817 unsigned int r_type;
4f4faa4d 5818 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5819
5820 BFD_ASSERT (stub_type != arm_stub_none);
5821 *new_stub = FALSE;
5822
4f4faa4d
TP		 5823 if (sym_claimed)
5824 stub_name = sym_name;
5825 else
5826 {
5827 BFD_ASSERT (irela);
5828 BFD_ASSERT (section);
c2abbbeb 5829 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5830
4f4faa4d
TP		 5831 /* Support for grouping stub sections. */
5832 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5833
4f4faa4d
TP		 5834 /* Get the name of this stub. */
5835 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5836 stub_type);
5837 if (!stub_name)
0955507f 5838 return NULL;
4f4faa4d 5839 }
b715f643
TP		 5840
5841 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5842 FALSE);
5843 /* The proper stub has already been created, just update its value. */
5844 if (stub_entry != NULL)
5845 {
4f4faa4d
TP		 5846 if (!sym_claimed)
5847 free (stub_name);
b715f643 5848 stub_entry->target_value = sym_value;
0955507f 5849 return stub_entry;
b715f643
TP		 5850 }
5851
daa4adae 5852 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5853 if (stub_entry == NULL)
5854 {
4f4faa4d
TP		 5855 if (!sym_claimed)
5856 free (stub_name);
0955507f 5857 return NULL;
b715f643
TP		 5858 }
5859
5860 stub_entry->target_value = sym_value;
5861 stub_entry->target_section = sym_sec;
5862 stub_entry->stub_type = stub_type;
5863 stub_entry->h = hash;
5864 stub_entry->branch_type = branch_type;
5865
4f4faa4d
TP		 5866 if (sym_claimed)
5867 stub_entry->output_name = sym_name;
5868 else
b715f643 5869 {
4f4faa4d
TP		 5870 if (sym_name == NULL)
5871 sym_name = "unnamed";
5872 stub_entry->output_name = (char *)
5873 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5874 + strlen (sym_name));
5875 if (stub_entry->output_name == NULL)
5876 {
5877 free (stub_name);
0955507f 5878 return NULL;
4f4faa4d 5879 }
b715f643 5880
4f4faa4d
TP		 5881 /* For historical reasons, use the existing names for ARM-to-Thumb and
5882 Thumb-to-ARM stubs. */
5883 r_type = ELF32_R_TYPE (irela->r_info);
5884 if ((r_type == (unsigned int) R_ARM_THM_CALL
5885 || r_type == (unsigned int) R_ARM_THM_JUMP24
5886 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5887 && branch_type == ST_BRANCH_TO_ARM)
5888 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5889 else if ((r_type == (unsigned int) R_ARM_CALL
5890 || r_type == (unsigned int) R_ARM_JUMP24)
5891 && branch_type == ST_BRANCH_TO_THUMB)
5892 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5893 else
5894 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5895 }
b715f643
TP		 5896
5897 *new_stub = TRUE;
0955507f 5898 return stub_entry;
b715f643
TP		 5899}
5900
4ba2ef8f
TP		 5901/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5902 gateway veneer to transition from non secure to secure state and create them
5903 accordingly.
5904
5905 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5906 defines the conditions that govern Secure Gateway veneer creation for a
5907 given symbol <SYM> as follows:
5908 - it has function type
5909 - it has non local binding
5910 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5911 same type, binding and value as <SYM> (called normal symbol).
5912 An entry function can handle secure state transition itself in which case
5913 its special symbol would have a different value from the normal symbol.
5914
5915 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5916 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5917 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5918 created.
4ba2ef8f 5919
0955507f 5920 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5921
5922static bfd_boolean
5923cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5924 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5925 int *cmse_stub_created)
4ba2ef8f
TP		 5926{
5927 const struct elf_backend_data *bed;
5928 Elf_Internal_Shdr *symtab_hdr;
5929 unsigned i, j, sym_count, ext_start;
5930 Elf_Internal_Sym *cmse_sym, *local_syms;
5931 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5932 enum arm_st_branch_type branch_type;
5933 char *sym_name, *lsym_name;
5934 bfd_vma sym_value;
5935 asection *section;
0955507f
TP		 5936 struct elf32_arm_stub_hash_entry *stub_entry;
5937 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5938
5939 bed = get_elf_backend_data (input_bfd);
5940 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5941 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5942 ext_start = symtab_hdr->sh_info;
5943 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5944 && out_attr[Tag_CPU_arch_profile].i == 'M');
5945
5946 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5947 if (local_syms == NULL)
5948 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5949 symtab_hdr->sh_info, 0, NULL, NULL,
5950 NULL);
5951 if (symtab_hdr->sh_info && local_syms == NULL)
5952 return FALSE;
5953
5954 /* Scan symbols. */
5955 for (i = 0; i < sym_count; i++)
5956 {
5957 cmse_invalid = FALSE;
5958
5959 if (i < ext_start)
5960 {
5961 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 5962 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5963 symtab_hdr->sh_link,
5964 cmse_sym->st_name);
baf46cd7
AM		 5965 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
5966 continue;
5967
4ba2ef8f
TP		 5968 /* Special symbol with local binding. */
5969 cmse_invalid = TRUE;
5970 }
5971 else
5972 {
5973 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5974 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 5975 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 5976 continue;
5977
5978 /* Special symbol has incorrect binding or type. */
5979 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5980 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5981 || cmse_hash->root.type != STT_FUNC)
5982 cmse_invalid = TRUE;
5983 }
5984
5985 if (!is_v8m)
5986 {
90b6238f
AM		 5987 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5988 "ARMv8-M architecture or later"),
4eca0228 5989 input_bfd, sym_name);
4ba2ef8f
TP		 5990 is_v8m = TRUE; /* Avoid multiple warning. */
5991 ret = FALSE;
5992 }
5993
5994 if (cmse_invalid)
5995 {
90b6238f
AM		 5996 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
5997 " a global or weak function symbol"),
4eca0228 5998 input_bfd, sym_name);
4ba2ef8f
TP		 5999 ret = FALSE;
6000 if (i < ext_start)
6001 continue;
6002 }
6003
6004 sym_name += strlen (CMSE_PREFIX);
6005 hash = (struct elf32_arm_link_hash_entry *)
6006 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6007
6008 /* No associated normal symbol or it is neither global nor weak. */
6009 if (!hash
6010 || (hash->root.root.type != bfd_link_hash_defined
6011 && hash->root.root.type != bfd_link_hash_defweak)
6012 || hash->root.type != STT_FUNC)
6013 {
6014 /* Initialize here to avoid warning about use of possibly
6015 uninitialized variable. */
6016 j = 0;
6017
6018 if (!hash)
6019 {
6020 /* Searching for a normal symbol with local binding. */
6021 for (; j < ext_start; j++)
6022 {
6023 lsym_name =
6024 bfd_elf_string_from_elf_section (input_bfd,
6025 symtab_hdr->sh_link,
6026 local_syms[j].st_name);
6027 if (!strcmp (sym_name, lsym_name))
6028 break;
6029 }
6030 }
6031
6032 if (hash || j < ext_start)
6033 {
4eca0228 6034 _bfd_error_handler
90b6238f
AM		 6035 (_("%pB: invalid standard symbol `%s'; it must be "
6036 "a global or weak function symbol"),
6037 input_bfd, sym_name);
4ba2ef8f
TP		 6038 }
6039 else
4eca0228 6040 _bfd_error_handler
90b6238f 6041 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6042 ret = FALSE;
6043 if (!hash)
6044 continue;
6045 }
6046
6047 sym_value = hash->root.root.u.def.value;
6048 section = hash->root.root.u.def.section;
6049
6050 if (cmse_hash->root.root.u.def.section != section)
6051 {
4eca0228 6052 _bfd_error_handler
90b6238f 6053 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6054 input_bfd, sym_name);
6055 ret = FALSE;
6056 }
6057 if (cmse_hash->root.root.u.def.value != sym_value)
6058 continue; /* Ignore: could be an entry function starting with SG. */
6059
6060 /* If this section is a link-once section that will be discarded, then
6061 don't create any stubs. */
6062 if (section->output_section == NULL)
6063 {
4eca0228 6064 _bfd_error_handler
90b6238f 6065 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6066 continue;
6067 }
6068
6069 if (hash->root.size == 0)
6070 {
4eca0228 6071 _bfd_error_handler
90b6238f 6072 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6073 ret = FALSE;
6074 }
6075
6076 if (!ret)
6077 continue;
6078 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6079 stub_entry
4ba2ef8f
TP		 6080 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6081 NULL, NULL, section, hash, sym_name,
6082 sym_value, branch_type, &new_stub);
6083
0955507f 6084 if (stub_entry == NULL)
4ba2ef8f
TP		 6085 ret = FALSE;
6086 else
6087 {
6088 BFD_ASSERT (new_stub);
0955507f 6089 (*cmse_stub_created)++;
4ba2ef8f
TP		 6090 }
6091 }
6092
6093 if (!symtab_hdr->contents)
6094 free (local_syms);
6095 return ret;
6096}
6097
0955507f
TP		 6098/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6099 code entry function, ie can be called from non secure code without using a
6100 veneer. */
6101
6102static bfd_boolean
6103cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6104{
42484486 6105 bfd_byte contents[4];
0955507f
TP		 6106 uint32_t first_insn;
6107 asection *section;
6108 file_ptr offset;
6109 bfd *abfd;
6110
6111 /* Defined symbol of function type. */
6112 if (hash->root.root.type != bfd_link_hash_defined
6113 && hash->root.root.type != bfd_link_hash_defweak)
6114 return FALSE;
6115 if (hash->root.type != STT_FUNC)
6116 return FALSE;
6117
6118 /* Read first instruction. */
6119 section = hash->root.root.u.def.section;
6120 abfd = section->owner;
6121 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6122 if (!bfd_get_section_contents (abfd, section, contents, offset,
6123 sizeof (contents)))
0955507f
TP		 6124 return FALSE;
6125
42484486
TP		 6126 first_insn = bfd_get_32 (abfd, contents);
6127
6128 /* Starts by SG instruction. */
0955507f
TP		 6129 return first_insn == 0xe97fe97f;
6130}
6131
6132/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6133 secure gateway veneers (ie. the veneers was not in the input import library)
6134 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6135
6136static bfd_boolean
6137arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6138{
6139 struct elf32_arm_stub_hash_entry *stub_entry;
6140 struct bfd_link_info *info;
6141
6142 /* Massage our args to the form they really have. */
6143 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6144 info = (struct bfd_link_info *) gen_info;
6145
6146 if (info->out_implib_bfd)
6147 return TRUE;
6148
6149 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6150 return TRUE;
6151
6152 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6153 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6154
6155 return TRUE;
6156}
6157
6158/* Set offset of each secure gateway veneers so that its address remain
6159 identical to the one in the input import library referred by
6160 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6161 (present in input import library but absent from the executable being
6162 linked) or if new veneers appeared and there is no output import library
6163 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6164 number of secure gateway veneers found in the input import library.
6165
6166 The function returns whether an error occurred. If no error occurred,
6167 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6168 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6169 veneer observed set for new veneers to be layed out after. */
6170
6171static bfd_boolean
6172set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6173 struct elf32_arm_link_hash_table *htab,
6174 int *cmse_stub_created)
6175{
6176 long symsize;
6177 char *sym_name;
6178 flagword flags;
6179 long i, symcount;
6180 bfd *in_implib_bfd;
6181 asection *stub_out_sec;
6182 bfd_boolean ret = TRUE;
6183 Elf_Internal_Sym *intsym;
6184 const char *out_sec_name;
6185 bfd_size_type cmse_stub_size;
6186 asymbol **sympp = NULL, *sym;
6187 struct elf32_arm_link_hash_entry *hash;
6188 const insn_sequence *cmse_stub_template;
6189 struct elf32_arm_stub_hash_entry *stub_entry;
6190 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6191 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6192 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6193
6194 /* No input secure gateway import library. */
6195 if (!htab->in_implib_bfd)
6196 return TRUE;
6197
6198 in_implib_bfd = htab->in_implib_bfd;
6199 if (!htab->cmse_implib)
6200 {
871b3ab2 6201 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6202 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6203 return FALSE;
6204 }
6205
6206 /* Get symbol table size. */
6207 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6208 if (symsize < 0)
6209 return FALSE;
6210
6211 /* Read in the input secure gateway import library's symbol table. */
9a733151
AM		 6212 sympp = (asymbol **) bfd_malloc (symsize);
6213 if (sympp == NULL)
6214 return FALSE;
6215
0955507f
TP		 6216 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6217 if (symcount < 0)
6218 {
6219 ret = FALSE;
6220 goto free_sym_buf;
6221 }
6222
6223 htab->new_cmse_stub_offset = 0;
6224 cmse_stub_size =
6225 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6226 &cmse_stub_template,
6227 &cmse_stub_template_size);
6228 out_sec_name =
6229 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6230 stub_out_sec =
6231 bfd_get_section_by_name (htab->obfd, out_sec_name);
6232 if (stub_out_sec != NULL)
6233 cmse_stub_sec_vma = stub_out_sec->vma;
6234
6235 /* Set addresses of veneers mentionned in input secure gateway import
6236 library's symbol table. */
6237 for (i = 0; i < symcount; i++)
6238 {
6239 sym = sympp[i];
6240 flags = sym->flags;
6241 sym_name = (char *) bfd_asymbol_name (sym);
6242 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6243
6244 if (sym->section != bfd_abs_section_ptr
6245 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6246 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6247 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6248 != ST_BRANCH_TO_THUMB))
6249 {
90b6238f
AM		 6250 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6251 "symbol should be absolute, global and "
6252 "refer to Thumb functions"),
4eca0228 6253 in_implib_bfd, sym_name);
0955507f
TP		 6254 ret = FALSE;
6255 continue;
6256 }
6257
6258 veneer_value = bfd_asymbol_value (sym);
6259 stub_offset = veneer_value - cmse_stub_sec_vma;
6260 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6261 FALSE, FALSE);
6262 hash = (struct elf32_arm_link_hash_entry *)
6263 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6264
6265 /* Stub entry should have been created by cmse_scan or the symbol be of
6266 a secure function callable from non secure code. */
6267 if (!stub_entry && !hash)
6268 {
6269 bfd_boolean new_stub;
6270
4eca0228 6271 _bfd_error_handler
90b6238f 6272 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6273 hash = (struct elf32_arm_link_hash_entry *)
6274 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6275 stub_entry
6276 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6277 NULL, NULL, bfd_abs_section_ptr, hash,
6278 sym_name, veneer_value,
6279 ST_BRANCH_TO_THUMB, &new_stub);
6280 if (stub_entry == NULL)
6281 ret = FALSE;
6282 else
6283 {
6284 BFD_ASSERT (new_stub);
6285 new_cmse_stubs_created++;
6286 (*cmse_stub_created)++;
6287 }
6288 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6289 stub_entry->stub_offset = stub_offset;
6290 }
6291 /* Symbol found is not callable from non secure code. */
6292 else if (!stub_entry)
6293 {
6294 if (!cmse_entry_fct_p (hash))
6295 {
90b6238f 6296 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6297 sym_name);
0955507f
TP		 6298 ret = FALSE;
6299 }
6300 continue;
6301 }
6302 else
6303 {
6304 /* Only stubs for SG veneers should have been created. */
6305 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6306
6307 /* Check visibility hasn't changed. */
6308 if (!!(flags & BSF_GLOBAL)
6309 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6310 _bfd_error_handler
90b6238f 6311 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6312 sym_name);
6313
6314 stub_entry->stub_offset = stub_offset;
6315 }
6316
6317 /* Size should match that of a SG veneer. */
6318 if (intsym->st_size != cmse_stub_size)
6319 {
90b6238f 6320 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6321 in_implib_bfd, sym_name);
0955507f
TP		 6322 ret = FALSE;
6323 }
6324
6325 /* Previous veneer address is before current SG veneer section. */
6326 if (veneer_value < cmse_stub_sec_vma)
6327 {
6328 /* Avoid offset underflow. */
6329 if (stub_entry)
6330 stub_entry->stub_offset = 0;
6331 stub_offset = 0;
6332 ret = FALSE;
6333 }
6334
6335 /* Complain if stub offset not a multiple of stub size. */
6336 if (stub_offset % cmse_stub_size)
6337 {
4eca0228 6338 _bfd_error_handler
90b6238f
AM		 6339 (_("offset of veneer for entry function `%s' not a multiple of "
6340 "its size"), sym_name);
0955507f
TP		 6341 ret = FALSE;
6342 }
6343
6344 if (!ret)
6345 continue;
6346
6347 new_cmse_stubs_created--;
6348 if (veneer_value < cmse_stub_array_start)
6349 cmse_stub_array_start = veneer_value;
6350 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6351 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6352 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6353 }
6354
6355 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6356 {
6357 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6358 _bfd_error_handler
0955507f
TP		 6359 (_("new entry function(s) introduced but no output import library "
6360 "specified:"));
6361 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6362 }
6363
6364 if (cmse_stub_array_start != cmse_stub_sec_vma)
6365 {
4eca0228 6366 _bfd_error_handler
90b6238f 6367 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6368 out_sec_name);
6369 ret = FALSE;
6370 }
6371
dc1e8a47 6372 free_sym_buf:
0955507f
TP		 6373 free (sympp);
6374 return ret;
6375}
6376
906e58ca
NC		 6377/* Determine and set the size of the stub section for a final link.
6378
6379 The basic idea here is to examine all the relocations looking for
6380 PC-relative calls to a target that is unreachable with a "bl"
6381 instruction. */
6382
6383bfd_boolean
6384elf32_arm_size_stubs (bfd *output_bfd,
6385 bfd *stub_bfd,
6386 struct bfd_link_info *info,
6387 bfd_signed_vma group_size,
7a89b94e 6388 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6389 asection *,
7a89b94e 6390 unsigned int),
906e58ca
NC		 6391 void (*layout_sections_again) (void))
6392{
0955507f 6393 bfd_boolean ret = TRUE;
4ba2ef8f 6394 obj_attribute *out_attr;
0955507f 6395 int cmse_stub_created = 0;
906e58ca 6396 bfd_size_type stub_group_size;
4ba2ef8f 6397 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6398 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6399 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6400 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6401 struct a8_erratum_reloc *a8_relocs = NULL;
6402 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6403
4dfe6ac6
NC		 6404 if (htab == NULL)
6405 return FALSE;
6406
48229727
JB		 6407 if (htab->fix_cortex_a8)
6408 {
21d799b5 6409 a8_fixes = (struct a8_erratum_fix *)
99059e56 6410 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6411 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6412 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6413 }
906e58ca
NC		 6414
6415 /* Propagate mach to stub bfd, because it may not have been
6416 finalized when we created stub_bfd. */
6417 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6418 bfd_get_mach (output_bfd));
6419
6420 /* Stash our params away. */
6421 htab->stub_bfd = stub_bfd;
6422 htab->add_stub_section = add_stub_section;
6423 htab->layout_sections_again = layout_sections_again;
07d72278 6424 stubs_always_after_branch = group_size < 0;
48229727 6425
4ba2ef8f
TP		 6426 out_attr = elf_known_obj_attributes_proc (output_bfd);
6427 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6428
48229727
JB		 6429 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6430 as the first half of a 32-bit branch straddling two 4K pages. This is a
6431 crude way of enforcing that. */
6432 if (htab->fix_cortex_a8)
6433 stubs_always_after_branch = 1;
6434
906e58ca
NC		 6435 if (group_size < 0)
6436 stub_group_size = -group_size;
6437 else
6438 stub_group_size = group_size;
6439
6440 if (stub_group_size == 1)
6441 {
6442 /* Default values. */
6443 /* Thumb branch range is +-4MB has to be used as the default
6444 maximum size (a given section can contain both ARM and Thumb
6445 code, so the worst case has to be taken into account).
6446
6447 This value is 24K less than that, which allows for 2025
6448 12-byte stubs. If we exceed that, then we will fail to link.
6449 The user will have to relink with an explicit group size
6450 option. */
6451 stub_group_size = 4170000;
6452 }
6453
07d72278 6454 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6455
3ae046cc
NS		 6456 /* If we're applying the cortex A8 fix, we need to determine the
6457 program header size now, because we cannot change it later --
6458 that could alter section placements. Notice the A8 erratum fix
6459 ends up requiring the section addresses to remain unchanged
6460 modulo the page size. That's something we cannot represent
6461 inside BFD, and we don't want to force the section alignment to
6462 be the page size. */
6463 if (htab->fix_cortex_a8)
6464 (*htab->layout_sections_again) ();
6465
906e58ca
NC		 6466 while (1)
6467 {
6468 bfd *input_bfd;
6469 unsigned int bfd_indx;
6470 asection *stub_sec;
d7c5bd02 6471 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6472 bfd_boolean stub_changed = FALSE;
6473 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6474
48229727 6475 num_a8_fixes = 0;
906e58ca
NC		 6476 for (input_bfd = info->input_bfds, bfd_indx = 0;
6477 input_bfd != NULL;
c72f2fb2 6478 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6479 {
6480 Elf_Internal_Shdr *symtab_hdr;
6481 asection *section;
6482 Elf_Internal_Sym *local_syms = NULL;
6483
73d5efd7
AM		 6484 if (!is_arm_elf (input_bfd))
6485 continue;
6486 if ((input_bfd->flags & DYNAMIC) != 0
6487 && (elf_sym_hashes (input_bfd) == NULL
6488 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0))
99059e56 6489 continue;
adbcc655 6490
48229727
JB		 6491 num_a8_relocs = 0;
6492
906e58ca
NC		 6493 /* We'll need the symbol table in a second. */
6494 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6495 if (symtab_hdr->sh_info == 0)
6496 continue;
6497
4ba2ef8f
TP		 6498 /* Limit scan of symbols to object file whose profile is
6499 Microcontroller to not hinder performance in the general case. */
6500 if (m_profile && first_veneer_scan)
6501 {
6502 struct elf_link_hash_entry **sym_hashes;
6503
6504 sym_hashes = elf_sym_hashes (input_bfd);
6505 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6506 &cmse_stub_created))
4ba2ef8f 6507 goto error_ret_free_local;
0955507f
TP		 6508
6509 if (cmse_stub_created != 0)
6510 stub_changed = TRUE;
4ba2ef8f
TP		 6511 }
6512
906e58ca
NC		 6513 /* Walk over each section attached to the input bfd. */
6514 for (section = input_bfd->sections;
6515 section != NULL;
6516 section = section->next)
6517 {
6518 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6519
6520 /* If there aren't any relocs, then there's nothing more
6521 to do. */
6522 if ((section->flags & SEC_RELOC) == 0
6523 || section->reloc_count == 0
6524 || (section->flags & SEC_CODE) == 0)
6525 continue;
6526
6527 /* If this section is a link-once section that will be
6528 discarded, then don't create any stubs. */
6529 if (section->output_section == NULL
6530 || section->output_section->owner != output_bfd)
6531 continue;
6532
6533 /* Get the relocs. */
6534 internal_relocs
6535 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6536 NULL, info->keep_memory);
6537 if (internal_relocs == NULL)
6538 goto error_ret_free_local;
6539
6540 /* Now examine each relocation. */
6541 irela = internal_relocs;
6542 irelaend = irela + section->reloc_count;
6543 for (; irela < irelaend; irela++)
6544 {
6545 unsigned int r_type, r_indx;
906e58ca
NC		 6546 asection *sym_sec;
6547 bfd_vma sym_value;
6548 bfd_vma destination;
6549 struct elf32_arm_link_hash_entry *hash;
7413f23f 6550 const char *sym_name;
34e77a92 6551 unsigned char st_type;
35fc36a8 6552 enum arm_st_branch_type branch_type;
48229727 6553 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6554
6555 r_type = ELF32_R_TYPE (irela->r_info);
6556 r_indx = ELF32_R_SYM (irela->r_info);
6557
6558 if (r_type >= (unsigned int) R_ARM_max)
6559 {
6560 bfd_set_error (bfd_error_bad_value);
6561 error_ret_free_internal:
6562 if (elf_section_data (section)->relocs == NULL)
6563 free (internal_relocs);
15dd01b1
TP		 6564 /* Fall through. */
6565 error_ret_free_local:
c9594989 6566 if (symtab_hdr->contents != (unsigned char *) local_syms)
15dd01b1
TP		 6567 free (local_syms);
6568 return FALSE;
906e58ca 6569 }
b38cadfb 6570
0855e32b
NS		 6571 hash = NULL;
6572 if (r_indx >= symtab_hdr->sh_info)
6573 hash = elf32_arm_hash_entry
6574 (elf_sym_hashes (input_bfd)
6575 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6576
0855e32b
NS		 6577 /* Only look for stubs on branch instructions, or
6578 non-relaxed TLSCALL */
906e58ca 6579 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6580 && (r_type != (unsigned int) R_ARM_THM_CALL)
6581 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6582 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6583 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6584 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6585 && (r_type != (unsigned int) R_ARM_PLT32)
6586 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6587 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6588 && r_type == elf32_arm_tls_transition
6589 (info, r_type, &hash->root)
6590 && ((hash ? hash->tls_type
6591 : (elf32_arm_local_got_tls_type
6592 (input_bfd)[r_indx]))
6593 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6594 continue;
6595
6596 /* Now determine the call target, its name, value,
6597 section. */
6598 sym_sec = NULL;
6599 sym_value = 0;
6600 destination = 0;
7413f23f 6601 sym_name = NULL;
b38cadfb 6602
0855e32b
NS		 6603 if (r_type == (unsigned int) R_ARM_TLS_CALL
6604 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6605 {
6606 /* A non-relaxed TLS call. The target is the
6607 plt-resident trampoline and nothing to do
6608 with the symbol. */
6609 BFD_ASSERT (htab->tls_trampoline > 0);
6610 sym_sec = htab->root.splt;
6611 sym_value = htab->tls_trampoline;
6612 hash = 0;
34e77a92 6613 st_type = STT_FUNC;
35fc36a8 6614 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6615 }
6616 else if (!hash)
906e58ca
NC		 6617 {
6618 /* It's a local symbol. */
6619 Elf_Internal_Sym *sym;
906e58ca
NC		 6620
6621 if (local_syms == NULL)
6622 {
6623 local_syms
6624 = (Elf_Internal_Sym *) symtab_hdr->contents;
6625 if (local_syms == NULL)
6626 local_syms
6627 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6628 symtab_hdr->sh_info, 0,
6629 NULL, NULL, NULL);
6630 if (local_syms == NULL)
6631 goto error_ret_free_internal;
6632 }
6633
6634 sym = local_syms + r_indx;
f6d250ce
TS		 6635 if (sym->st_shndx == SHN_UNDEF)
6636 sym_sec = bfd_und_section_ptr;
6637 else if (sym->st_shndx == SHN_ABS)
6638 sym_sec = bfd_abs_section_ptr;
6639 else if (sym->st_shndx == SHN_COMMON)
6640 sym_sec = bfd_com_section_ptr;
6641 else
6642 sym_sec =
6643 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6644
ffcb4889
NS		 6645 if (!sym_sec)
6646 /* This is an undefined symbol. It can never
6a631e86 6647 be resolved. */
ffcb4889 6648 continue;
fe33d2fa 6649
906e58ca
NC		 6650 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6651 sym_value = sym->st_value;
6652 destination = (sym_value + irela->r_addend
6653 + sym_sec->output_offset
6654 + sym_sec->output_section->vma);
34e77a92 6655 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6656 branch_type =
6657 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6658 sym_name
6659 = bfd_elf_string_from_elf_section (input_bfd,
6660 symtab_hdr->sh_link,
6661 sym->st_name);
906e58ca
NC		 6662 }
6663 else
6664 {
6665 /* It's an external symbol. */
906e58ca
NC		 6666 while (hash->root.root.type == bfd_link_hash_indirect
6667 || hash->root.root.type == bfd_link_hash_warning)
6668 hash = ((struct elf32_arm_link_hash_entry *)
6669 hash->root.root.u.i.link);
6670
6671 if (hash->root.root.type == bfd_link_hash_defined
6672 || hash->root.root.type == bfd_link_hash_defweak)
6673 {
6674 sym_sec = hash->root.root.u.def.section;
6675 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6676
6677 struct elf32_arm_link_hash_table *globals =
6678 elf32_arm_hash_table (info);
6679
6680 /* For a destination in a shared library,
6681 use the PLT stub as target address to
6682 decide whether a branch stub is
6683 needed. */
4dfe6ac6 6684 if (globals != NULL
362d30a1 6685 && globals->root.splt != NULL
4dfe6ac6 6686 && hash != NULL
022f8312
CL		 6687 && hash->root.plt.offset != (bfd_vma) -1)
6688 {
362d30a1 6689 sym_sec = globals->root.splt;
022f8312
CL		 6690 sym_value = hash->root.plt.offset;
6691 if (sym_sec->output_section != NULL)
6692 destination = (sym_value
6693 + sym_sec->output_offset
6694 + sym_sec->output_section->vma);
6695 }
6696 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6697 destination = (sym_value + irela->r_addend
6698 + sym_sec->output_offset
6699 + sym_sec->output_section->vma);
6700 }
69c5861e
CL		 6701 else if ((hash->root.root.type == bfd_link_hash_undefined)
6702 || (hash->root.root.type == bfd_link_hash_undefweak))
6703 {
6704 /* For a shared library, use the PLT stub as
6705 target address to decide whether a long
6706 branch stub is needed.
6707 For absolute code, they cannot be handled. */
6708 struct elf32_arm_link_hash_table *globals =
6709 elf32_arm_hash_table (info);
6710
4dfe6ac6 6711 if (globals != NULL
362d30a1 6712 && globals->root.splt != NULL
4dfe6ac6 6713 && hash != NULL
69c5861e
CL		 6714 && hash->root.plt.offset != (bfd_vma) -1)
6715 {
362d30a1 6716 sym_sec = globals->root.splt;
69c5861e
CL		 6717 sym_value = hash->root.plt.offset;
6718 if (sym_sec->output_section != NULL)
6719 destination = (sym_value
6720 + sym_sec->output_offset
6721 + sym_sec->output_section->vma);
6722 }
6723 else
6724 continue;
6725 }
906e58ca
NC		 6726 else
6727 {
6728 bfd_set_error (bfd_error_bad_value);
6729 goto error_ret_free_internal;
6730 }
34e77a92 6731 st_type = hash->root.type;
39d911fc
TP		 6732 branch_type =
6733 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6734 sym_name = hash->root.root.root.string;
906e58ca
NC		 6735 }
6736
48229727 6737 do
7413f23f 6738 {
b715f643 6739 bfd_boolean new_stub;
0955507f 6740 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6741
48229727
JB		 6742 /* Determine what (if any) linker stub is needed. */
6743 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6744 st_type, &branch_type,
6745 hash, destination, sym_sec,
48229727
JB		 6746 input_bfd, sym_name);
6747 if (stub_type == arm_stub_none)
6748 break;
6749
48229727
JB		 6750 /* We've either created a stub for this reloc already,
6751 or we are about to. */
0955507f 6752 stub_entry =
b715f643
TP		 6753 elf32_arm_create_stub (htab, stub_type, section, irela,
6754 sym_sec, hash,
6755 (char *) sym_name, sym_value,
6756 branch_type, &new_stub);
7413f23f 6757
0955507f 6758 created_stub = stub_entry != NULL;
b715f643
TP		 6759 if (!created_stub)
6760 goto error_ret_free_internal;
6761 else if (!new_stub)
6762 break;
99059e56 6763 else
b715f643 6764 stub_changed = TRUE;
99059e56
RM		 6765 }
6766 while (0);
6767
6768 /* Look for relocations which might trigger Cortex-A8
6769 erratum. */
6770 if (htab->fix_cortex_a8
6771 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6772 || r_type == (unsigned int) R_ARM_THM_JUMP19
6773 || r_type == (unsigned int) R_ARM_THM_CALL
6774 || r_type == (unsigned int) R_ARM_THM_XPC22))
6775 {
6776 bfd_vma from = section->output_section->vma
6777 + section->output_offset
6778 + irela->r_offset;
6779
6780 if ((from & 0xfff) == 0xffe)
6781 {
6782 /* Found a candidate. Note we haven't checked the
6783 destination is within 4K here: if we do so (and
6784 don't create an entry in a8_relocs) we can't tell
6785 that a branch should have been relocated when
6786 scanning later. */
6787 if (num_a8_relocs == a8_reloc_table_size)
6788 {
6789 a8_reloc_table_size *= 2;
6790 a8_relocs = (struct a8_erratum_reloc *)
6791 bfd_realloc (a8_relocs,
6792 sizeof (struct a8_erratum_reloc)
6793 * a8_reloc_table_size);
6794 }
6795
6796 a8_relocs[num_a8_relocs].from = from;
6797 a8_relocs[num_a8_relocs].destination = destination;
6798 a8_relocs[num_a8_relocs].r_type = r_type;
6799 a8_relocs[num_a8_relocs].branch_type = branch_type;
6800 a8_relocs[num_a8_relocs].sym_name = sym_name;
6801 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6802 a8_relocs[num_a8_relocs].hash = hash;
6803
6804 num_a8_relocs++;
6805 }
6806 }
906e58ca
NC		 6807 }
6808
99059e56
RM		 6809 /* We're done with the internal relocs, free them. */
6810 if (elf_section_data (section)->relocs == NULL)
6811 free (internal_relocs);
6812 }
48229727 6813
99059e56 6814 if (htab->fix_cortex_a8)
48229727 6815 {
99059e56
RM		 6816 /* Sort relocs which might apply to Cortex-A8 erratum. */
6817 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6818 sizeof (struct a8_erratum_reloc),
99059e56 6819 &a8_reloc_compare);
48229727 6820
99059e56
RM		 6821 /* Scan for branches which might trigger Cortex-A8 erratum. */
6822 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6823 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6824 a8_relocs, num_a8_relocs,
6825 prev_num_a8_fixes, &stub_changed)
6826 != 0)
48229727 6827 goto error_ret_free_local;
5e681ec4 6828 }
7f991970
AM		 6829
6830 if (local_syms != NULL
6831 && symtab_hdr->contents != (unsigned char *) local_syms)
6832 {
6833 if (!info->keep_memory)
6834 free (local_syms);
6835 else
6836 symtab_hdr->contents = (unsigned char *) local_syms;
6837 }
5e681ec4
PB		 6838 }
6839
0955507f
TP		 6840 if (first_veneer_scan
6841 && !set_cmse_veneer_addr_from_implib (info, htab,
6842 &cmse_stub_created))
6843 ret = FALSE;
6844
eb7c4339 6845 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6846 stub_changed = TRUE;
48229727 6847
906e58ca
NC		 6848 if (!stub_changed)
6849 break;
5e681ec4 6850
906e58ca
NC		 6851 /* OK, we've added some stubs. Find out the new size of the
6852 stub sections. */
6853 for (stub_sec = htab->stub_bfd->sections;
6854 stub_sec != NULL;
6855 stub_sec = stub_sec->next)
3e6b1042
DJ		 6856 {
6857 /* Ignore non-stub sections. */
6858 if (!strstr (stub_sec->name, STUB_SUFFIX))
6859 continue;
6860
6861 stub_sec->size = 0;
6862 }
b34b2d70 6863
0955507f
TP		 6864 /* Add new SG veneers after those already in the input import
6865 library. */
6866 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6867 stub_type++)
6868 {
6869 bfd_vma *start_offset_p;
6870 asection **stub_sec_p;
6871
6872 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6873 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6874 if (start_offset_p == NULL)
6875 continue;
6876
6877 BFD_ASSERT (stub_sec_p != NULL);
6878 if (*stub_sec_p != NULL)
6879 (*stub_sec_p)->size = *start_offset_p;
6880 }
6881
d7c5bd02 6882 /* Compute stub section size, considering padding. */
906e58ca 6883 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6884 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6885 stub_type++)
6886 {
6887 int size, padding;
6888 asection **stub_sec_p;
6889
6890 padding = arm_dedicated_stub_section_padding (stub_type);
6891 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6892 /* Skip if no stub input section or no stub section padding
6893 required. */
6894 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6895 continue;
6896 /* Stub section padding required but no dedicated section. */
6897 BFD_ASSERT (stub_sec_p);
6898
6899 size = (*stub_sec_p)->size;
6900 size = (size + padding - 1) & ~(padding - 1);
6901 (*stub_sec_p)->size = size;
6902 }
906e58ca 6903
48229727
JB		 6904 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6905 if (htab->fix_cortex_a8)
99059e56
RM		 6906 for (i = 0; i < num_a8_fixes; i++)
6907 {
48229727 6908 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6909 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6910
6911 if (stub_sec == NULL)
7f991970 6912 return FALSE;
48229727 6913
99059e56
RM		 6914 stub_sec->size
6915 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6916 NULL);
6917 }
48229727
JB		 6918
6919
906e58ca
NC		 6920 /* Ask the linker to do its stuff. */
6921 (*htab->layout_sections_again) ();
4ba2ef8f 6922 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6923 }
6924
48229727
JB		 6925 /* Add stubs for Cortex-A8 erratum fixes now. */
6926 if (htab->fix_cortex_a8)
6927 {
6928 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6929 {
6930 struct elf32_arm_stub_hash_entry *stub_entry;
6931 char *stub_name = a8_fixes[i].stub_name;
6932 asection *section = a8_fixes[i].section;
6933 unsigned int section_id = a8_fixes[i].section->id;
6934 asection *link_sec = htab->stub_group[section_id].link_sec;
6935 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6936 const insn_sequence *template_sequence;
6937 int template_size, size = 0;
6938
6939 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6940 TRUE, FALSE);
6941 if (stub_entry == NULL)
6942 {
871b3ab2 6943 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6944 section->owner, stub_name);
99059e56
RM		 6945 return FALSE;
6946 }
6947
6948 stub_entry->stub_sec = stub_sec;
0955507f 6949 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6950 stub_entry->id_sec = link_sec;
6951 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6952 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6953 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6954 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6955 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6956 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6957
99059e56
RM		 6958 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6959 &template_sequence,
6960 &template_size);
48229727 6961
99059e56
RM		 6962 stub_entry->stub_size = size;
6963 stub_entry->stub_template = template_sequence;
6964 stub_entry->stub_template_size = template_size;
6965 }
48229727
JB		 6966
6967 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6968 elf32_arm_write_section(). */
48229727
JB		 6969 htab->a8_erratum_fixes = a8_fixes;
6970 htab->num_a8_erratum_fixes = num_a8_fixes;
6971 }
6972 else
6973 {
6974 htab->a8_erratum_fixes = NULL;
6975 htab->num_a8_erratum_fixes = 0;
6976 }
0955507f 6977 return ret;
5e681ec4
PB		 6978}
6979
906e58ca
NC		 6980/* Build all the stubs associated with the current output file. The
6981 stubs are kept in a hash table attached to the main linker hash
6982 table. We also set up the .plt entries for statically linked PIC
6983 functions here. This function is called via arm_elf_finish in the
6984 linker. */
252b5132 6985
906e58ca
NC		 6986bfd_boolean
6987elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6988{
906e58ca
NC		 6989 asection *stub_sec;
6990 struct bfd_hash_table *table;
0955507f 6991 enum elf32_arm_stub_type stub_type;
906e58ca 6992 struct elf32_arm_link_hash_table *htab;
252b5132 6993
906e58ca 6994 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6995 if (htab == NULL)
6996 return FALSE;
252b5132 6997
906e58ca
NC		 6998 for (stub_sec = htab->stub_bfd->sections;
6999 stub_sec != NULL;
7000 stub_sec = stub_sec->next)
252b5132 7001 {
906e58ca
NC		 7002 bfd_size_type size;
7003
8029a119 7004 /* Ignore non-stub sections. */
906e58ca
NC		 7005 if (!strstr (stub_sec->name, STUB_SUFFIX))
7006 continue;
7007
d7c5bd02 7008 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7009 must at least be done for stub section requiring padding and for SG
7010 veneers to ensure that a non secure code branching to a removed SG
7011 veneer causes an error. */
906e58ca 7012 size = stub_sec->size;
21d799b5 7013 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7014 if (stub_sec->contents == NULL && size != 0)
7015 return FALSE;
0955507f 7016
906e58ca 7017 stub_sec->size = 0;
252b5132
RH		 7018 }
7019
0955507f
TP		 7020 /* Add new SG veneers after those already in the input import library. */
7021 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7022 {
7023 bfd_vma *start_offset_p;
7024 asection **stub_sec_p;
7025
7026 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7027 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7028 if (start_offset_p == NULL)
7029 continue;
7030
7031 BFD_ASSERT (stub_sec_p != NULL);
7032 if (*stub_sec_p != NULL)
7033 (*stub_sec_p)->size = *start_offset_p;
7034 }
7035
906e58ca
NC		 7036 /* Build the stubs as directed by the stub hash table. */
7037 table = &htab->stub_hash_table;
7038 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7039 if (htab->fix_cortex_a8)
7040 {
7041 /* Place the cortex a8 stubs last. */
7042 htab->fix_cortex_a8 = -1;
7043 bfd_hash_traverse (table, arm_build_one_stub, info);
7044 }
252b5132 7045
906e58ca 7046 return TRUE;
252b5132
RH		 7047}
7048
9b485d32
NC		 7049/* Locate the Thumb encoded calling stub for NAME. */
7050
252b5132 7051static struct elf_link_hash_entry *
57e8b36a
NC		 7052find_thumb_glue (struct bfd_link_info *link_info,
7053 const char *name,
f2a9dd69 7054 char **error_message)
252b5132
RH		 7055{
7056 char *tmp_name;
7057 struct elf_link_hash_entry *hash;
7058 struct elf32_arm_link_hash_table *hash_table;
7059
7060 /* We need a pointer to the armelf specific hash table. */
7061 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7062 if (hash_table == NULL)
7063 return NULL;
252b5132 7064
21d799b5 7065 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7066 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7067
7068 BFD_ASSERT (tmp_name);
7069
7070 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7071
7072 hash = elf_link_hash_lookup
b34976b6 7073 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7074
b1657152 7075 if (hash == NULL
90b6238f
AM		 7076 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7077 "Thumb", tmp_name, name) == -1)
b1657152 7078 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7079
7080 free (tmp_name);
7081
7082 return hash;
7083}
7084
9b485d32
NC		 7085/* Locate the ARM encoded calling stub for NAME. */
7086
252b5132 7087static struct elf_link_hash_entry *
57e8b36a
NC		 7088find_arm_glue (struct bfd_link_info *link_info,
7089 const char *name,
f2a9dd69 7090 char **error_message)
252b5132
RH		 7091{
7092 char *tmp_name;
7093 struct elf_link_hash_entry *myh;
7094 struct elf32_arm_link_hash_table *hash_table;
7095
7096 /* We need a pointer to the elfarm specific hash table. */
7097 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7098 if (hash_table == NULL)
7099 return NULL;
252b5132 7100
21d799b5 7101 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7102 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7103 BFD_ASSERT (tmp_name);
7104
7105 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7106
7107 myh = elf_link_hash_lookup
b34976b6 7108 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7109
b1657152 7110 if (myh == NULL
90b6238f
AM		 7111 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7112 "ARM", tmp_name, name) == -1)
b1657152 7113 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7114
7115 free (tmp_name);
7116
7117 return myh;
7118}
7119
8f6277f5 7120/* ARM->Thumb glue (static images):
252b5132
RH		 7121
7122 .arm
7123 __func_from_arm:
7124 ldr r12, __func_addr
7125 bx r12
7126 __func_addr:
906e58ca 7127 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7128
26079076
PB		 7129 (v5t static images)
7130 .arm
7131 __func_from_arm:
7132 ldr pc, __func_addr
7133 __func_addr:
906e58ca 7134 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7135
8f6277f5
PB		 7136 (relocatable images)
7137 .arm
7138 __func_from_arm:
7139 ldr r12, __func_offset
7140 add r12, r12, pc
7141 bx r12
7142 __func_offset:
8029a119 7143 .word func - . */
8f6277f5
PB		 7144
7145#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7146static const insn32 a2t1_ldr_insn = 0xe59fc000;
7147static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7148static const insn32 a2t3_func_addr_insn = 0x00000001;
7149
26079076
PB		 7150#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7151static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7152static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7153
8f6277f5
PB		 7154#define ARM2THUMB_PIC_GLUE_SIZE 16
7155static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7156static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7157static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7158
07d6d2b8 7159/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7160
07d6d2b8
AM		 7161 .thumb .thumb
7162 .align 2 .align 2
7163 __func_from_thumb: __func_from_thumb:
7164 bx pc push {r6, lr}
7165 nop ldr r6, __func_addr
7166 .arm mov lr, pc
7167 b func bx r6
99059e56
RM		 7168 .arm
7169 ;; back_to_thumb
7170 ldmia r13! {r6, lr}
7171 bx lr
7172 __func_addr:
07d6d2b8 7173 .word func */
252b5132
RH		 7174
7175#define THUMB2ARM_GLUE_SIZE 8
7176static const insn16 t2a1_bx_pc_insn = 0x4778;
7177static const insn16 t2a2_noop_insn = 0x46c0;
7178static const insn32 t2a3_b_insn = 0xea000000;
7179
c7b8f16e 7180#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7181#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7182#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7183
845b51d6
PB		 7184#define ARM_BX_VENEER_SIZE 12
7185static const insn32 armbx1_tst_insn = 0xe3100001;
7186static const insn32 armbx2_moveq_insn = 0x01a0f000;
7187static const insn32 armbx3_bx_insn = 0xe12fff10;
7188
7e392df6 7189#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7190static void
7191arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7192{
7193 asection * s;
8029a119 7194 bfd_byte * contents;
252b5132 7195
8029a119 7196 if (size == 0)
3e6b1042
DJ		 7197 {
7198 /* Do not include empty glue sections in the output. */
7199 if (abfd != NULL)
7200 {
3d4d4302 7201 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7202 if (s != NULL)
7203 s->flags |= SEC_EXCLUDE;
7204 }
7205 return;
7206 }
252b5132 7207
8029a119 7208 BFD_ASSERT (abfd != NULL);
252b5132 7209
3d4d4302 7210 s = bfd_get_linker_section (abfd, name);
8029a119 7211 BFD_ASSERT (s != NULL);
252b5132 7212
b0f4fbf8 7213 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7214
8029a119
NC		 7215 BFD_ASSERT (s->size == size);
7216 s->contents = contents;
7217}
906e58ca 7218
8029a119
NC		 7219bfd_boolean
7220bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7221{
7222 struct elf32_arm_link_hash_table * globals;
906e58ca 7223
8029a119
NC		 7224 globals = elf32_arm_hash_table (info);
7225 BFD_ASSERT (globals != NULL);
906e58ca 7226
8029a119
NC		 7227 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7228 globals->arm_glue_size,
7229 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7230
8029a119
NC		 7231 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7232 globals->thumb_glue_size,
7233 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7234
8029a119
NC		 7235 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7236 globals->vfp11_erratum_glue_size,
7237 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7238
a504d23a
LA		 7239 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7240 globals->stm32l4xx_erratum_glue_size,
7241 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7242
8029a119
NC		 7243 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7244 globals->bx_glue_size,
845b51d6
PB		 7245 ARM_BX_GLUE_SECTION_NAME);
7246
b34976b6 7247 return TRUE;
252b5132
RH		 7248}
7249
a4fd1a8e 7250/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7251 returns the symbol identifying the stub. */
7252
a4fd1a8e 7253static struct elf_link_hash_entry *
57e8b36a
NC		 7254record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7255 struct elf_link_hash_entry * h)
252b5132
RH		 7256{
7257 const char * name = h->root.root.string;
63b0f745 7258 asection * s;
252b5132
RH		 7259 char * tmp_name;
7260 struct elf_link_hash_entry * myh;
14a793b2 7261 struct bfd_link_hash_entry * bh;
252b5132 7262 struct elf32_arm_link_hash_table * globals;
dc810e39 7263 bfd_vma val;
2f475487 7264 bfd_size_type size;
252b5132
RH		 7265
7266 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7267 BFD_ASSERT (globals != NULL);
7268 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7269
3d4d4302 7270 s = bfd_get_linker_section
252b5132
RH		 7271 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7272
252b5132
RH		 7273 BFD_ASSERT (s != NULL);
7274
21d799b5 7275 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7276 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7277 BFD_ASSERT (tmp_name);
7278
7279 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7280
7281 myh = elf_link_hash_lookup
b34976b6 7282 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7283
7284 if (myh != NULL)
7285 {
9b485d32 7286 /* We've already seen this guy. */
252b5132 7287 free (tmp_name);
a4fd1a8e 7288 return myh;
252b5132
RH		 7289 }
7290
57e8b36a
NC		 7291 /* The only trick here is using hash_table->arm_glue_size as the value.
7292 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7293 putting it. The +1 on the value marks that the stub has not been
7294 output yet - not that it is a Thumb function. */
14a793b2 7295 bh = NULL;
dc810e39
AM		 7296 val = globals->arm_glue_size + 1;
7297 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7298 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7299 NULL, TRUE, FALSE, &bh);
252b5132 7300
b7693d02
DJ		 7301 myh = (struct elf_link_hash_entry *) bh;
7302 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7303 myh->forced_local = 1;
7304
252b5132
RH		 7305 free (tmp_name);
7306
0e1862bb
L		 7307 if (bfd_link_pic (link_info)
7308 || globals->root.is_relocatable_executable
27e55c4d 7309 || globals->pic_veneer)
2f475487 7310 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7311 else if (globals->use_blx)
7312 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7313 else
2f475487
AM		 7314 size = ARM2THUMB_STATIC_GLUE_SIZE;
7315
7316 s->size += size;
7317 globals->arm_glue_size += size;
252b5132 7318
a4fd1a8e 7319 return myh;
252b5132
RH		 7320}
7321
845b51d6
PB		 7322/* Allocate space for ARMv4 BX veneers. */
7323
7324static void
7325record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7326{
7327 asection * s;
7328 struct elf32_arm_link_hash_table *globals;
7329 char *tmp_name;
7330 struct elf_link_hash_entry *myh;
7331 struct bfd_link_hash_entry *bh;
7332 bfd_vma val;
7333
7334 /* BX PC does not need a veneer. */
7335 if (reg == 15)
7336 return;
7337
7338 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7339 BFD_ASSERT (globals != NULL);
7340 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7341
7342 /* Check if this veneer has already been allocated. */
7343 if (globals->bx_glue_offset[reg])
7344 return;
7345
3d4d4302 7346 s = bfd_get_linker_section
845b51d6
PB		 7347 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7348
7349 BFD_ASSERT (s != NULL);
7350
7351 /* Add symbol for veneer. */
21d799b5
NC		 7352 tmp_name = (char *)
7353 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
845b51d6 7354 BFD_ASSERT (tmp_name);
906e58ca 7355
845b51d6 7356 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7357
845b51d6
PB		 7358 myh = elf_link_hash_lookup
7359 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7360
845b51d6 7361 BFD_ASSERT (myh == NULL);
906e58ca 7362
845b51d6
PB		 7363 bh = NULL;
7364 val = globals->bx_glue_size;
7365 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7366 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7367 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7368
7369 myh = (struct elf_link_hash_entry *) bh;
7370 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7371 myh->forced_local = 1;
7372
7373 s->size += ARM_BX_VENEER_SIZE;
7374 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7375 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7376}
7377
7378
c7b8f16e
JB		 7379/* Add an entry to the code/data map for section SEC. */
7380
7381static void
7382elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7383{
7384 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7385 unsigned int newidx;
906e58ca 7386
c7b8f16e
JB		 7387 if (sec_data->map == NULL)
7388 {
21d799b5 7389 sec_data->map = (elf32_arm_section_map *)
99059e56 7390 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7391 sec_data->mapcount = 0;
7392 sec_data->mapsize = 1;
7393 }
906e58ca 7394
c7b8f16e 7395 newidx = sec_data->mapcount++;
906e58ca 7396
c7b8f16e
JB		 7397 if (sec_data->mapcount > sec_data->mapsize)
7398 {
7399 sec_data->mapsize *= 2;
21d799b5 7400 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7401 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7402 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7403 }
7404
7405 if (sec_data->map)
7406 {
7407 sec_data->map[newidx].vma = vma;
7408 sec_data->map[newidx].type = type;
c7b8f16e 7409 }
c7b8f16e
JB		 7410}
7411
7412
7413/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7414 veneers are handled for now. */
7415
7416static bfd_vma
7417record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7418 elf32_vfp11_erratum_list *branch,
7419 bfd *branch_bfd,
7420 asection *branch_sec,
7421 unsigned int offset)
c7b8f16e
JB		 7422{
7423 asection *s;
7424 struct elf32_arm_link_hash_table *hash_table;
7425 char *tmp_name;
7426 struct elf_link_hash_entry *myh;
7427 struct bfd_link_hash_entry *bh;
7428 bfd_vma val;
7429 struct _arm_elf_section_data *sec_data;
c7b8f16e 7430 elf32_vfp11_erratum_list *newerr;
906e58ca 7431
c7b8f16e 7432 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7433 BFD_ASSERT (hash_table != NULL);
7434 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7435
3d4d4302 7436 s = bfd_get_linker_section
c7b8f16e 7437 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7438
c7b8f16e 7439 sec_data = elf32_arm_section_data (s);
906e58ca 7440
c7b8f16e 7441 BFD_ASSERT (s != NULL);
906e58ca 7442
21d799b5 7443 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7444 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e 7445 BFD_ASSERT (tmp_name);
906e58ca 7446
c7b8f16e
JB		 7447 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7448 hash_table->num_vfp11_fixes);
906e58ca 7449
c7b8f16e
JB		 7450 myh = elf_link_hash_lookup
7451 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7452
c7b8f16e 7453 BFD_ASSERT (myh == NULL);
906e58ca 7454
c7b8f16e
JB		 7455 bh = NULL;
7456 val = hash_table->vfp11_erratum_glue_size;
7457 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7458 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7459 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7460
7461 myh = (struct elf_link_hash_entry *) bh;
7462 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7463 myh->forced_local = 1;
7464
7465 /* Link veneer back to calling location. */
c7e2358a 7466 sec_data->erratumcount += 1;
21d799b5
NC		 7467 newerr = (elf32_vfp11_erratum_list *)
7468 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7469
c7b8f16e
JB		 7470 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7471 newerr->vma = -1;
7472 newerr->u.v.branch = branch;
7473 newerr->u.v.id = hash_table->num_vfp11_fixes;
7474 branch->u.b.veneer = newerr;
7475
7476 newerr->next = sec_data->erratumlist;
7477 sec_data->erratumlist = newerr;
7478
7479 /* A symbol for the return from the veneer. */
7480 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7481 hash_table->num_vfp11_fixes);
7482
7483 myh = elf_link_hash_lookup
7484 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7485
c7b8f16e
JB		 7486 if (myh != NULL)
7487 abort ();
7488
7489 bh = NULL;
7490 val = offset + 4;
7491 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7492 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7493
c7b8f16e
JB		 7494 myh = (struct elf_link_hash_entry *) bh;
7495 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7496 myh->forced_local = 1;
7497
7498 free (tmp_name);
906e58ca 7499
c7b8f16e
JB		 7500 /* Generate a mapping symbol for the veneer section, and explicitly add an
7501 entry for that symbol to the code/data map for the section. */
7502 if (hash_table->vfp11_erratum_glue_size == 0)
7503 {
7504 bh = NULL;
7505 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7506 ever requires this erratum fix. */
c7b8f16e
JB		 7507 _bfd_generic_link_add_one_symbol (link_info,
7508 hash_table->bfd_of_glue_owner, "$a",
7509 BSF_LOCAL, s, 0, NULL,
99059e56 7510 TRUE, FALSE, &bh);
c7b8f16e
JB		 7511
7512 myh = (struct elf_link_hash_entry *) bh;
7513 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7514 myh->forced_local = 1;
906e58ca 7515
c7b8f16e 7516 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7517 BFDs. We must make a note of this generated mapping symbol
7518 ourselves so that code byteswapping works properly in
7519 elf32_arm_write_section. */
c7b8f16e
JB		 7520 elf32_arm_section_map_add (s, 'a', 0);
7521 }
906e58ca 7522
c7b8f16e
JB		 7523 s->size += VFP11_ERRATUM_VENEER_SIZE;
7524 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7525 hash_table->num_vfp11_fixes++;
906e58ca 7526
c7b8f16e
JB		 7527 /* The offset of the veneer. */
7528 return val;
7529}
7530
a504d23a
LA		 7531/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7532 veneers need to be handled because used only in Cortex-M. */
7533
7534static bfd_vma
7535record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7536 elf32_stm32l4xx_erratum_list *branch,
7537 bfd *branch_bfd,
7538 asection *branch_sec,
7539 unsigned int offset,
7540 bfd_size_type veneer_size)
7541{
7542 asection *s;
7543 struct elf32_arm_link_hash_table *hash_table;
7544 char *tmp_name;
7545 struct elf_link_hash_entry *myh;
7546 struct bfd_link_hash_entry *bh;
7547 bfd_vma val;
7548 struct _arm_elf_section_data *sec_data;
7549 elf32_stm32l4xx_erratum_list *newerr;
7550
7551 hash_table = elf32_arm_hash_table (link_info);
7552 BFD_ASSERT (hash_table != NULL);
7553 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7554
7555 s = bfd_get_linker_section
7556 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7557
7558 BFD_ASSERT (s != NULL);
7559
7560 sec_data = elf32_arm_section_data (s);
7561
7562 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7563 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
a504d23a
LA		 7564 BFD_ASSERT (tmp_name);
7565
7566 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7567 hash_table->num_stm32l4xx_fixes);
7568
7569 myh = elf_link_hash_lookup
7570 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7571
7572 BFD_ASSERT (myh == NULL);
7573
7574 bh = NULL;
7575 val = hash_table->stm32l4xx_erratum_glue_size;
7576 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7577 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7578 NULL, TRUE, FALSE, &bh);
7579
7580 myh = (struct elf_link_hash_entry *) bh;
7581 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7582 myh->forced_local = 1;
7583
7584 /* Link veneer back to calling location. */
7585 sec_data->stm32l4xx_erratumcount += 1;
7586 newerr = (elf32_stm32l4xx_erratum_list *)
7587 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7588
7589 newerr->type = STM32L4XX_ERRATUM_VENEER;
7590 newerr->vma = -1;
7591 newerr->u.v.branch = branch;
7592 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7593 branch->u.b.veneer = newerr;
7594
7595 newerr->next = sec_data->stm32l4xx_erratumlist;
7596 sec_data->stm32l4xx_erratumlist = newerr;
7597
7598 /* A symbol for the return from the veneer. */
7599 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7600 hash_table->num_stm32l4xx_fixes);
7601
7602 myh = elf_link_hash_lookup
7603 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7604
7605 if (myh != NULL)
7606 abort ();
7607
7608 bh = NULL;
7609 val = offset + 4;
7610 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7611 branch_sec, val, NULL, TRUE, FALSE, &bh);
7612
7613 myh = (struct elf_link_hash_entry *) bh;
7614 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7615 myh->forced_local = 1;
7616
7617 free (tmp_name);
7618
7619 /* Generate a mapping symbol for the veneer section, and explicitly add an
7620 entry for that symbol to the code/data map for the section. */
7621 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7622 {
7623 bh = NULL;
7624 /* Creates a THUMB symbol since there is no other choice. */
7625 _bfd_generic_link_add_one_symbol (link_info,
7626 hash_table->bfd_of_glue_owner, "$t",
7627 BSF_LOCAL, s, 0, NULL,
7628 TRUE, FALSE, &bh);
7629
7630 myh = (struct elf_link_hash_entry *) bh;
7631 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7632 myh->forced_local = 1;
7633
7634 /* The elf32_arm_init_maps function only cares about symbols from input
7635 BFDs. We must make a note of this generated mapping symbol
7636 ourselves so that code byteswapping works properly in
7637 elf32_arm_write_section. */
7638 elf32_arm_section_map_add (s, 't', 0);
7639 }
7640
7641 s->size += veneer_size;
7642 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7643 hash_table->num_stm32l4xx_fixes++;
7644
7645 /* The offset of the veneer. */
7646 return val;
7647}
7648
8029a119 7649#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7650 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7651 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7652
7653/* Create a fake section for use by the ARM backend of the linker. */
7654
7655static bfd_boolean
7656arm_make_glue_section (bfd * abfd, const char * name)
7657{
7658 asection * sec;
7659
3d4d4302 7660 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7661 if (sec != NULL)
7662 /* Already made. */
7663 return TRUE;
7664
3d4d4302 7665 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7666
7667 if (sec == NULL
fd361982 7668 || !bfd_set_section_alignment (sec, 2))
8029a119
NC		 7669 return FALSE;
7670
7671 /* Set the gc mark to prevent the section from being removed by garbage
7672 collection, despite the fact that no relocs refer to this section. */
7673 sec->gc_mark = 1;
7674
7675 return TRUE;
7676}
7677
1db37fe6
YG		 7678/* Set size of .plt entries. This function is called from the
7679 linker scripts in ld/emultempl/{armelf}.em. */
7680
7681void
7682bfd_elf32_arm_use_long_plt (void)
7683{
7684 elf32_arm_use_long_plt_entry = TRUE;
7685}
7686
8afb0e02
NC		 7687/* Add the glue sections to ABFD. This function is called from the
7688 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7689
b34976b6 7690bfd_boolean
57e8b36a
NC		 7691bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7692 struct bfd_link_info *info)
252b5132 7693{
a504d23a
LA		 7694 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7695 bfd_boolean dostm32l4xx = globals
7696 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7697 bfd_boolean addglue;
7698
8afb0e02
NC		 7699 /* If we are only performing a partial
7700 link do not bother adding the glue. */
0e1862bb 7701 if (bfd_link_relocatable (info))
b34976b6 7702 return TRUE;
252b5132 7703
a504d23a 7704 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7705 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7706 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7707 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7708
7709 if (!dostm32l4xx)
7710 return addglue;
7711
7712 return addglue
7713 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7714}
7715
daa4adae
TP		 7716/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7717 ensures they are not marked for deletion by
7718 strip_excluded_output_sections () when veneers are going to be created
7719 later. Not doing so would trigger assert on empty section size in
7720 lang_size_sections_1 (). */
7721
7722void
7723bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7724{
7725 enum elf32_arm_stub_type stub_type;
7726
7727 /* If we are only performing a partial
7728 link do not bother adding the glue. */
7729 if (bfd_link_relocatable (info))
7730 return;
7731
7732 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7733 {
7734 asection *out_sec;
7735 const char *out_sec_name;
7736
7737 if (!arm_dedicated_stub_output_section_required (stub_type))
7738 continue;
7739
7740 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7741 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7742 if (out_sec != NULL)
7743 out_sec->flags |= SEC_KEEP;
7744 }
7745}
7746
8afb0e02
NC		 7747/* Select a BFD to be used to hold the sections used by the glue code.
7748 This function is called from the linker scripts in ld/emultempl/
8029a119 7749 {armelf/pe}.em. */
8afb0e02 7750
b34976b6 7751bfd_boolean
57e8b36a 7752bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7753{
7754 struct elf32_arm_link_hash_table *globals;
7755
7756 /* If we are only performing a partial link
7757 do not bother getting a bfd to hold the glue. */
0e1862bb 7758 if (bfd_link_relocatable (info))
b34976b6 7759 return TRUE;
8afb0e02 7760
b7693d02
DJ		 7761 /* Make sure we don't attach the glue sections to a dynamic object. */
7762 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7763
8afb0e02 7764 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7765 BFD_ASSERT (globals != NULL);
7766
7767 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7768 return TRUE;
8afb0e02 7769
252b5132
RH		 7770 /* Save the bfd for later use. */
7771 globals->bfd_of_glue_owner = abfd;
cedb70c5 7772
b34976b6 7773 return TRUE;
252b5132
RH		 7774}
7775
906e58ca
NC		 7776static void
7777check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7778{
2de70689
MGD		 7779 int cpu_arch;
7780
b38cadfb 7781 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7782 Tag_CPU_arch);
7783
7784 if (globals->fix_arm1176)
7785 {
7786 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7787 globals->use_blx = 1;
7788 }
7789 else
7790 {
7791 if (cpu_arch > TAG_CPU_ARCH_V4T)
7792 globals->use_blx = 1;
7793 }
39b41c9c
PB		 7794}
7795
b34976b6 7796bfd_boolean
57e8b36a 7797bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7798 struct bfd_link_info *link_info)
252b5132
RH		 7799{
7800 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7801 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7802 Elf_Internal_Rela *irel, *irelend;
7803 bfd_byte *contents = NULL;
252b5132
RH		 7804
7805 asection *sec;
7806 struct elf32_arm_link_hash_table *globals;
7807
7808 /* If we are only performing a partial link do not bother
7809 to construct any glue. */
0e1862bb 7810 if (bfd_link_relocatable (link_info))
b34976b6 7811 return TRUE;
252b5132 7812
39ce1a6a
NC		 7813 /* Here we have a bfd that is to be included on the link. We have a
7814 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7815 globals = elf32_arm_hash_table (link_info);
252b5132 7816 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7817
7818 check_use_blx (globals);
252b5132 7819
d504ffc8 7820 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7821 {
90b6238f 7822 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7823 abfd);
e489d0ae
PB		 7824 return FALSE;
7825 }
f21f3fe0 7826
39ce1a6a
NC		 7827 /* PR 5398: If we have not decided to include any loadable sections in
7828 the output then we will not have a glue owner bfd. This is OK, it
7829 just means that there is nothing else for us to do here. */
7830 if (globals->bfd_of_glue_owner == NULL)
7831 return TRUE;
7832
252b5132
RH		 7833 /* Rummage around all the relocs and map the glue vectors. */
7834 sec = abfd->sections;
7835
7836 if (sec == NULL)
b34976b6 7837 return TRUE;
252b5132
RH		 7838
7839 for (; sec != NULL; sec = sec->next)
7840 {
7841 if (sec->reloc_count == 0)
7842 continue;
7843
2f475487
AM		 7844 if ((sec->flags & SEC_EXCLUDE) != 0)
7845 continue;
7846
0ffa91dd 7847 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7848
9b485d32 7849 /* Load the relocs. */
6cdc0ccc 7850 internal_relocs
906e58ca 7851 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7852
6cdc0ccc
AM		 7853 if (internal_relocs == NULL)
7854 goto error_return;
252b5132 7855
6cdc0ccc
AM		 7856 irelend = internal_relocs + sec->reloc_count;
7857 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7858 {
7859 long r_type;
7860 unsigned long r_index;
252b5132
RH		 7861
7862 struct elf_link_hash_entry *h;
7863
7864 r_type = ELF32_R_TYPE (irel->r_info);
7865 r_index = ELF32_R_SYM (irel->r_info);
7866
9b485d32 7867 /* These are the only relocation types we care about. */
ba96a88f 7868 if ( r_type != R_ARM_PC24
845b51d6 7869 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7870 continue;
7871
7872 /* Get the section contents if we haven't done so already. */
7873 if (contents == NULL)
7874 {
7875 /* Get cached copy if it exists. */
7876 if (elf_section_data (sec)->this_hdr.contents != NULL)
7877 contents = elf_section_data (sec)->this_hdr.contents;
7878 else
7879 {
7880 /* Go get them off disk. */
57e8b36a 7881 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7882 goto error_return;
7883 }
7884 }
7885
845b51d6
PB		 7886 if (r_type == R_ARM_V4BX)
7887 {
7888 int reg;
7889
7890 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7891 record_arm_bx_glue (link_info, reg);
7892 continue;
7893 }
7894
a7c10850 7895 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7896 h = NULL;
7897
9b485d32 7898 /* We don't care about local symbols. */
252b5132
RH		 7899 if (r_index < symtab_hdr->sh_info)
7900 continue;
7901
9b485d32 7902 /* This is an external symbol. */
252b5132
RH		 7903 r_index -= symtab_hdr->sh_info;
7904 h = (struct elf_link_hash_entry *)
7905 elf_sym_hashes (abfd)[r_index];
7906
7907 /* If the relocation is against a static symbol it must be within
7908 the current section and so cannot be a cross ARM/Thumb relocation. */
7909 if (h == NULL)
7910 continue;
7911
d504ffc8
DJ		 7912 /* If the call will go through a PLT entry then we do not need
7913 glue. */
362d30a1 7914 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7915 continue;
7916
252b5132
RH		 7917 switch (r_type)
7918 {
7919 case R_ARM_PC24:
7920 /* This one is a call from arm code. We need to look up
99059e56
RM		 7921 the target of the call. If it is a thumb target, we
7922 insert glue. */
39d911fc
TP		 7923 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7924 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7925 record_arm_to_thumb_glue (link_info, h);
7926 break;
7927
252b5132 7928 default:
c6596c5e 7929 abort ();
252b5132
RH		 7930 }
7931 }
6cdc0ccc 7932
c9594989 7933 if (elf_section_data (sec)->this_hdr.contents != contents)
6cdc0ccc
AM		 7934 free (contents);
7935 contents = NULL;
7936
c9594989 7937 if (elf_section_data (sec)->relocs != internal_relocs)
6cdc0ccc
AM		 7938 free (internal_relocs);
7939 internal_relocs = NULL;
252b5132
RH		 7940 }
7941
b34976b6 7942 return TRUE;
9a5aca8c 7943
dc1e8a47 7944 error_return:
c9594989 7945 if (elf_section_data (sec)->this_hdr.contents != contents)
6cdc0ccc 7946 free (contents);
c9594989 7947 if (elf_section_data (sec)->relocs != internal_relocs)
6cdc0ccc 7948 free (internal_relocs);
9a5aca8c 7949
b34976b6 7950 return FALSE;
252b5132 7951}
7e392df6 7952#endif
252b5132 7953
eb043451 7954
c7b8f16e
JB		 7955/* Initialise maps of ARM/Thumb/data for input BFDs. */
7956
7957void
7958bfd_elf32_arm_init_maps (bfd *abfd)
7959{
7960 Elf_Internal_Sym *isymbuf;
7961 Elf_Internal_Shdr *hdr;
7962 unsigned int i, localsyms;
7963
af1f4419
NC		 7964 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7965 if (! is_arm_elf (abfd))
7966 return;
7967
c7b8f16e
JB		 7968 if ((abfd->flags & DYNAMIC) != 0)
7969 return;
7970
0ffa91dd 7971 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7972 localsyms = hdr->sh_info;
7973
7974 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7975 should contain the number of local symbols, which should come before any
7976 global symbols. Mapping symbols are always local. */
7977 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7978 NULL);
7979
7980 /* No internal symbols read? Skip this BFD. */
7981 if (isymbuf == NULL)
7982 return;
7983
7984 for (i = 0; i < localsyms; i++)
7985 {
7986 Elf_Internal_Sym *isym = &isymbuf[i];
7987 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7988 const char *name;
906e58ca 7989
c7b8f16e 7990 if (sec != NULL
99059e56
RM		 7991 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7992 {
7993 name = bfd_elf_string_from_elf_section (abfd,
7994 hdr->sh_link, isym->st_name);
906e58ca 7995
99059e56 7996 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7997 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7998 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7999 }
c7b8f16e
JB		 8000 }
8001}
8002
8003
48229727
JB		 8004/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8005 say what they wanted. */
8006
8007void
8008bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8009{
8010 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8011 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8012
4dfe6ac6
NC		 8013 if (globals == NULL)
8014 return;
8015
48229727
JB		 8016 if (globals->fix_cortex_a8 == -1)
8017 {
8018 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8019 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8020 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8021 || out_attr[Tag_CPU_arch_profile].i == 0))
8022 globals->fix_cortex_a8 = 1;
8023 else
8024 globals->fix_cortex_a8 = 0;
8025 }
8026}
8027
8028
c7b8f16e
JB		 8029void
8030bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8031{
8032 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8033 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8034
4dfe6ac6
NC		 8035 if (globals == NULL)
8036 return;
c7b8f16e
JB		 8037 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8038 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8039 {
8040 switch (globals->vfp11_fix)
99059e56
RM		 8041 {
8042 case BFD_ARM_VFP11_FIX_DEFAULT:
8043 case BFD_ARM_VFP11_FIX_NONE:
8044 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8045 break;
8046
8047 default:
8048 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8049 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8050 "workaround is not necessary for target architecture"), obfd);
8051 }
c7b8f16e
JB		 8052 }
8053 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8054 /* For earlier architectures, we might need the workaround, but do not
8055 enable it by default. If users is running with broken hardware, they
8056 must enable the erratum fix explicitly. */
8057 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8058}
8059
a504d23a
LA		 8060void
8061bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8062{
8063 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8064 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8065
8066 if (globals == NULL)
8067 return;
8068
8069 /* We assume only Cortex-M4 may require the fix. */
8070 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8071 || out_attr[Tag_CPU_arch_profile].i != 'M')
8072 {
8073 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8074 /* Give a warning, but do as the user requests anyway. */
4eca0228 8075 _bfd_error_handler
871b3ab2 8076 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8077 "workaround is not necessary for target architecture"), obfd);
8078 }
8079}
c7b8f16e 8080
906e58ca
NC		 8081enum bfd_arm_vfp11_pipe
8082{
c7b8f16e
JB		 8083 VFP11_FMAC,
8084 VFP11_LS,
8085 VFP11_DS,
8086 VFP11_BAD
8087};
8088
8089/* Return a VFP register number. This is encoded as RX:X for single-precision
8090 registers, or X:RX for double-precision registers, where RX is the group of
8091 four bits in the instruction encoding and X is the single extension bit.
8092 RX and X fields are specified using their lowest (starting) bit. The return
8093 value is:
8094
8095 0...31: single-precision registers s0...s31
8096 32...63: double-precision registers d0...d31.
906e58ca 8097
c7b8f16e
JB		 8098 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8099 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8100
c7b8f16e
JB		 8101static unsigned int
8102bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8103 unsigned int x)
c7b8f16e
JB		 8104{
8105 if (is_double)
8106 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8107 else
8108 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8109}
8110
8111/* Set bits in *WMASK according to a register number REG as encoded by
8112 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8113
8114static void
8115bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8116{
8117 if (reg < 32)
8118 *wmask |= 1 << reg;
8119 else if (reg < 48)
8120 *wmask |= 3 << ((reg - 32) * 2);
8121}
8122
8123/* Return TRUE if WMASK overwrites anything in REGS. */
8124
8125static bfd_boolean
8126bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8127{
8128 int i;
906e58ca 8129
c7b8f16e
JB		 8130 for (i = 0; i < numregs; i++)
8131 {
8132 unsigned int reg = regs[i];
8133
8134 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8135 return TRUE;
906e58ca 8136
c7b8f16e
JB		 8137 reg -= 32;
8138
8139 if (reg >= 16)
99059e56 8140 continue;
906e58ca 8141
c7b8f16e 8142 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8143 return TRUE;
c7b8f16e 8144 }
906e58ca 8145
c7b8f16e
JB		 8146 return FALSE;
8147}
8148
8149/* In this function, we're interested in two things: finding input registers
8150 for VFP data-processing instructions, and finding the set of registers which
8151 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8152 hold the written set, so FLDM etc. are easy to deal with (we're only
8153 interested in 32 SP registers or 16 dp registers, due to the VFP version
8154 implemented by the chip in question). DP registers are marked by setting
8155 both SP registers in the write mask). */
8156
8157static enum bfd_arm_vfp11_pipe
8158bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8159 int *numregs)
c7b8f16e 8160{
91d6fa6a 8161 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8162 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8163
8164 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8165 {
8166 unsigned int pqrs;
8167 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8168 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8169
8170 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8171 | ((insn & 0x00300000) >> 19)
8172 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8173
8174 switch (pqrs)
99059e56
RM		 8175 {
8176 case 0: /* fmac[sd]. */
8177 case 1: /* fnmac[sd]. */
8178 case 2: /* fmsc[sd]. */
8179 case 3: /* fnmsc[sd]. */
8180 vpipe = VFP11_FMAC;
8181 bfd_arm_vfp11_write_mask (destmask, fd);
8182 regs[0] = fd;
8183 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8184 regs[2] = fm;
8185 *numregs = 3;
8186 break;
8187
8188 case 4: /* fmul[sd]. */
8189 case 5: /* fnmul[sd]. */
8190 case 6: /* fadd[sd]. */
8191 case 7: /* fsub[sd]. */
8192 vpipe = VFP11_FMAC;
8193 goto vfp_binop;
8194
8195 case 8: /* fdiv[sd]. */
8196 vpipe = VFP11_DS;
8197 vfp_binop:
8198 bfd_arm_vfp11_write_mask (destmask, fd);
8199 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8200 regs[1] = fm;
8201 *numregs = 2;
8202 break;
8203
8204 case 15: /* extended opcode. */
8205 {
8206 unsigned int extn = ((insn >> 15) & 0x1e)
8207 | ((insn >> 7) & 1);
8208
8209 switch (extn)
8210 {
8211 case 0: /* fcpy[sd]. */
8212 case 1: /* fabs[sd]. */
8213 case 2: /* fneg[sd]. */
8214 case 8: /* fcmp[sd]. */
8215 case 9: /* fcmpe[sd]. */
8216 case 10: /* fcmpz[sd]. */
8217 case 11: /* fcmpez[sd]. */
8218 case 16: /* fuito[sd]. */
8219 case 17: /* fsito[sd]. */
8220 case 24: /* ftoui[sd]. */
8221 case 25: /* ftouiz[sd]. */
8222 case 26: /* ftosi[sd]. */
8223 case 27: /* ftosiz[sd]. */
8224 /* These instructions will not bounce due to underflow. */
8225 *numregs = 0;
8226 vpipe = VFP11_FMAC;
8227 break;
8228
8229 case 3: /* fsqrt[sd]. */
8230 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8231 registers to cause the erratum in previous instructions. */
8232 bfd_arm_vfp11_write_mask (destmask, fd);
8233 vpipe = VFP11_DS;
8234 break;
8235
8236 case 15: /* fcvt{ds,sd}. */
8237 {
8238 int rnum = 0;
8239
8240 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8241
8242 /* Only FCVTSD can underflow. */
99059e56
RM		 8243 if ((insn & 0x100) != 0)
8244 regs[rnum++] = fm;
c7b8f16e 8245
99059e56 8246 *numregs = rnum;
c7b8f16e 8247
99059e56
RM		 8248 vpipe = VFP11_FMAC;
8249 }
8250 break;
c7b8f16e 8251
99059e56
RM		 8252 default:
8253 return VFP11_BAD;
8254 }
8255 }
8256 break;
c7b8f16e 8257
99059e56
RM		 8258 default:
8259 return VFP11_BAD;
8260 }
c7b8f16e
JB		 8261 }
8262 /* Two-register transfer. */
8263 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8264 {
8265 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8266
c7b8f16e
JB		 8267 if ((insn & 0x100000) == 0)
8268 {
99059e56
RM		 8269 if (is_double)
8270 bfd_arm_vfp11_write_mask (destmask, fm);
8271 else
8272 {
8273 bfd_arm_vfp11_write_mask (destmask, fm);
8274 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8275 }
c7b8f16e
JB		 8276 }
8277
91d6fa6a 8278 vpipe = VFP11_LS;
c7b8f16e
JB		 8279 }
8280 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8281 {
8282 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8283 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8284
c7b8f16e 8285 switch (puw)
99059e56
RM		 8286 {
8287 case 0: /* Two-reg transfer. We should catch these above. */
8288 abort ();
906e58ca 8289
99059e56
RM		 8290 case 2: /* fldm[sdx]. */
8291 case 3:
8292 case 5:
8293 {
8294 unsigned int i, offset = insn & 0xff;
c7b8f16e 8295
99059e56
RM		 8296 if (is_double)
8297 offset >>= 1;
c7b8f16e 8298
99059e56
RM		 8299 for (i = fd; i < fd + offset; i++)
8300 bfd_arm_vfp11_write_mask (destmask, i);
8301 }
8302 break;
906e58ca 8303
99059e56
RM		 8304 case 4: /* fld[sd]. */
8305 case 6:
8306 bfd_arm_vfp11_write_mask (destmask, fd);
8307 break;
906e58ca 8308
99059e56
RM		 8309 default:
8310 return VFP11_BAD;
8311 }
c7b8f16e 8312
91d6fa6a 8313 vpipe = VFP11_LS;
c7b8f16e
JB		 8314 }
8315 /* Single-register transfer. Note L==0. */
8316 else if ((insn & 0x0f100e10) == 0x0e000a10)
8317 {
8318 unsigned int opcode = (insn >> 21) & 7;
8319 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8320
8321 switch (opcode)
99059e56
RM		 8322 {
8323 case 0: /* fmsr/fmdlr. */
8324 case 1: /* fmdhr. */
8325 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8326 destination register. I don't know if this is exactly right,
8327 but it is the conservative choice. */
8328 bfd_arm_vfp11_write_mask (destmask, fn);
8329 break;
8330
8331 case 7: /* fmxr. */
8332 break;
8333 }
c7b8f16e 8334
91d6fa6a 8335 vpipe = VFP11_LS;
c7b8f16e
JB		 8336 }
8337
91d6fa6a 8338 return vpipe;
c7b8f16e
JB		 8339}
8340
8341
8342static int elf32_arm_compare_mapping (const void * a, const void * b);
8343
8344
8345/* Look for potentially-troublesome code sequences which might trigger the
8346 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8347 (available from ARM) for details of the erratum. A short version is
8348 described in ld.texinfo. */
8349
8350bfd_boolean
8351bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8352{
8353 asection *sec;
8354 bfd_byte *contents = NULL;
8355 int state = 0;
8356 int regs[3], numregs = 0;
8357 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8358 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8359
4dfe6ac6
NC		 8360 if (globals == NULL)
8361 return FALSE;
8362
c7b8f16e
JB		 8363 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8364 The states transition as follows:
906e58ca 8365
c7b8f16e 8366 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8367 A VFP FMAC-pipeline instruction has been seen. Fill
8368 regs[0]..regs[numregs-1] with its input operands. Remember this
8369 instruction in 'first_fmac'.
c7b8f16e
JB		 8370
8371 1 -> 2
99059e56
RM		 8372 Any instruction, except for a VFP instruction which overwrites
8373 regs[*].
906e58ca 8374
c7b8f16e
JB		 8375 1 -> 3 [ -> 0 ] or
8376 2 -> 3 [ -> 0 ]
99059e56
RM		 8377 A VFP instruction has been seen which overwrites any of regs[*].
8378 We must make a veneer! Reset state to 0 before examining next
8379 instruction.
906e58ca 8380
c7b8f16e 8381 2 -> 0
99059e56
RM		 8382 If we fail to match anything in state 2, reset to state 0 and reset
8383 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8384
8385 If the VFP11 vector mode is in use, there must be at least two unrelated
8386 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8387 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8388
8389 /* If we are only performing a partial link do not bother
8390 to construct any glue. */
0e1862bb 8391 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8392 return TRUE;
8393
0ffa91dd
NC		 8394 /* Skip if this bfd does not correspond to an ELF image. */
8395 if (! is_arm_elf (abfd))
8396 return TRUE;
906e58ca 8397
c7b8f16e
JB		 8398 /* We should have chosen a fix type by the time we get here. */
8399 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8400
8401 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8402 return TRUE;
2e6030b9 8403
33a7ffc2
JM		 8404 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8405 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8406 return TRUE;
8407
c7b8f16e
JB		 8408 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8409 {
8410 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8411 struct _arm_elf_section_data *sec_data;
8412
8413 /* If we don't have executable progbits, we're not interested in this
99059e56 8414 section. Also skip if section is to be excluded. */
c7b8f16e 8415 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8416 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8417 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8418 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8419 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8420 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8421 continue;
c7b8f16e
JB		 8422
8423 sec_data = elf32_arm_section_data (sec);
906e58ca 8424
c7b8f16e 8425 if (sec_data->mapcount == 0)
99059e56 8426 continue;
906e58ca 8427
c7b8f16e
JB		 8428 if (elf_section_data (sec)->this_hdr.contents != NULL)
8429 contents = elf_section_data (sec)->this_hdr.contents;
8430 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8431 goto error_return;
8432
8433 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8434 elf32_arm_compare_mapping);
8435
8436 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8437 {
8438 unsigned int span_start = sec_data->map[span].vma;
8439 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8440 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8441 char span_type = sec_data->map[span].type;
8442
8443 /* FIXME: Only ARM mode is supported at present. We may need to
8444 support Thumb-2 mode also at some point. */
8445 if (span_type != 'a')
8446 continue;
8447
8448 for (i = span_start; i < span_end;)
8449 {
8450 unsigned int next_i = i + 4;
8451 unsigned int insn = bfd_big_endian (abfd)
13c9c485
AM		 8452 ? (((unsigned) contents[i] << 24)
8453 | (contents[i + 1] << 16)
8454 | (contents[i + 2] << 8)
8455 | contents[i + 3])
8456 : (((unsigned) contents[i + 3] << 24)
8457 | (contents[i + 2] << 16)
8458 | (contents[i + 1] << 8)
8459 | contents[i]);
99059e56
RM		 8460 unsigned int writemask = 0;
8461 enum bfd_arm_vfp11_pipe vpipe;
8462
8463 switch (state)
8464 {
8465 case 0:
8466 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8467 &numregs);
8468 /* I'm assuming the VFP11 erratum can trigger with denorm
8469 operands on either the FMAC or the DS pipeline. This might
8470 lead to slightly overenthusiastic veneer insertion. */
8471 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8472 {
8473 state = use_vector ? 1 : 2;
8474 first_fmac = i;
8475 veneer_of_insn = insn;
8476 }
8477 break;
8478
8479 case 1:
8480 {
8481 int other_regs[3], other_numregs;
8482 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8483 other_regs,
99059e56
RM		 8484 &other_numregs);
8485 if (vpipe != VFP11_BAD
8486 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8487 numregs))
99059e56
RM		 8488 state = 3;
8489 else
8490 state = 2;
8491 }
8492 break;
8493
8494 case 2:
8495 {
8496 int other_regs[3], other_numregs;
8497 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8498 other_regs,
99059e56
RM		 8499 &other_numregs);
8500 if (vpipe != VFP11_BAD
8501 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8502 numregs))
99059e56
RM		 8503 state = 3;
8504 else
8505 {
8506 state = 0;
8507 next_i = first_fmac + 4;
8508 }
8509 }
8510 break;
8511
8512 case 3:
8513 abort (); /* Should be unreachable. */
8514 }
8515
8516 if (state == 3)
8517 {
8518 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8519 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8520
8521 elf32_arm_section_data (sec)->erratumcount += 1;
8522
8523 newerr->u.b.vfp_insn = veneer_of_insn;
8524
8525 switch (span_type)
8526 {
8527 case 'a':
8528 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8529 break;
8530
8531 default:
8532 abort ();
8533 }
8534
8535 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8536 first_fmac);
8537
99059e56 8538 newerr->vma = -1;
c7b8f16e 8539
99059e56
RM		 8540 newerr->next = sec_data->erratumlist;
8541 sec_data->erratumlist = newerr;
c7b8f16e 8542
99059e56
RM		 8543 state = 0;
8544 }
c7b8f16e 8545
99059e56
RM		 8546 i = next_i;
8547 }
8548 }
906e58ca 8549
c9594989 8550 if (elf_section_data (sec)->this_hdr.contents != contents)
99059e56 8551 free (contents);
c7b8f16e
JB		 8552 contents = NULL;
8553 }
8554
8555 return TRUE;
8556
dc1e8a47 8557 error_return:
c9594989 8558 if (elf_section_data (sec)->this_hdr.contents != contents)
c7b8f16e 8559 free (contents);
906e58ca 8560
c7b8f16e
JB		 8561 return FALSE;
8562}
8563
8564/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8565 after sections have been laid out, using specially-named symbols. */
8566
8567void
8568bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8569 struct bfd_link_info *link_info)
8570{
8571 asection *sec;
8572 struct elf32_arm_link_hash_table *globals;
8573 char *tmp_name;
906e58ca 8574
0e1862bb 8575 if (bfd_link_relocatable (link_info))
c7b8f16e 8576 return;
2e6030b9
MS		 8577
8578 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8579 if (! is_arm_elf (abfd))
2e6030b9
MS		 8580 return;
8581
c7b8f16e 8582 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8583 if (globals == NULL)
8584 return;
906e58ca 8585
21d799b5 8586 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8587 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8588 BFD_ASSERT (tmp_name);
c7b8f16e
JB		 8589
8590 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8591 {
8592 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8593 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8594
c7b8f16e 8595 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8596 {
8597 struct elf_link_hash_entry *myh;
8598 bfd_vma vma;
8599
8600 switch (errnode->type)
8601 {
8602 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8603 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8604 /* Find veneer symbol. */
8605 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8606 errnode->u.b.veneer->u.v.id);
8607
99059e56
RM		 8608 myh = elf_link_hash_lookup
8609 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8610
a504d23a 8611 if (myh == NULL)
90b6238f
AM		 8612 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8613 abfd, "VFP11", tmp_name);
a504d23a
LA		 8614
8615 vma = myh->root.u.def.section->output_section->vma
8616 + myh->root.u.def.section->output_offset
8617 + myh->root.u.def.value;
8618
8619 errnode->u.b.veneer->vma = vma;
8620 break;
8621
8622 case VFP11_ERRATUM_ARM_VENEER:
8623 case VFP11_ERRATUM_THUMB_VENEER:
8624 /* Find return location. */
8625 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8626 errnode->u.v.id);
8627
8628 myh = elf_link_hash_lookup
8629 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8630
8631 if (myh == NULL)
90b6238f
AM		 8632 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8633 abfd, "VFP11", tmp_name);
a504d23a
LA		 8634
8635 vma = myh->root.u.def.section->output_section->vma
8636 + myh->root.u.def.section->output_offset
8637 + myh->root.u.def.value;
8638
8639 errnode->u.v.branch->vma = vma;
8640 break;
8641
8642 default:
8643 abort ();
8644 }
8645 }
8646 }
8647
8648 free (tmp_name);
8649}
8650
8651/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8652 return locations after sections have been laid out, using
8653 specially-named symbols. */
8654
8655void
8656bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8657 struct bfd_link_info *link_info)
8658{
8659 asection *sec;
8660 struct elf32_arm_link_hash_table *globals;
8661 char *tmp_name;
8662
8663 if (bfd_link_relocatable (link_info))
8664 return;
8665
8666 /* Skip if this bfd does not correspond to an ELF image. */
8667 if (! is_arm_elf (abfd))
8668 return;
8669
8670 globals = elf32_arm_hash_table (link_info);
8671 if (globals == NULL)
8672 return;
8673
8674 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8675 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8676 BFD_ASSERT (tmp_name);
a504d23a
LA		 8677
8678 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8679 {
8680 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8681 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8682
8683 for (; errnode != NULL; errnode = errnode->next)
8684 {
8685 struct elf_link_hash_entry *myh;
8686 bfd_vma vma;
8687
8688 switch (errnode->type)
8689 {
8690 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8691 /* Find veneer symbol. */
8692 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8693 errnode->u.b.veneer->u.v.id);
8694
8695 myh = elf_link_hash_lookup
8696 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8697
8698 if (myh == NULL)
90b6238f
AM		 8699 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8700 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8701
8702 vma = myh->root.u.def.section->output_section->vma
8703 + myh->root.u.def.section->output_offset
8704 + myh->root.u.def.value;
8705
8706 errnode->u.b.veneer->vma = vma;
8707 break;
8708
8709 case STM32L4XX_ERRATUM_VENEER:
8710 /* Find return location. */
8711 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8712 errnode->u.v.id);
8713
8714 myh = elf_link_hash_lookup
8715 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8716
8717 if (myh == NULL)
90b6238f
AM		 8718 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8719 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8720
8721 vma = myh->root.u.def.section->output_section->vma
8722 + myh->root.u.def.section->output_offset
8723 + myh->root.u.def.value;
8724
8725 errnode->u.v.branch->vma = vma;
8726 break;
8727
8728 default:
8729 abort ();
8730 }
8731 }
8732 }
8733
8734 free (tmp_name);
8735}
8736
8737static inline bfd_boolean
8738is_thumb2_ldmia (const insn32 insn)
8739{
8740 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8741 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8742 return (insn & 0xffd02000) == 0xe8900000;
8743}
8744
8745static inline bfd_boolean
8746is_thumb2_ldmdb (const insn32 insn)
8747{
8748 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8749 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8750 return (insn & 0xffd02000) == 0xe9100000;
8751}
8752
8753static inline bfd_boolean
8754is_thumb2_vldm (const insn32 insn)
8755{
8756 /* A6.5 Extension register load or store instruction
8757 A7.7.229
9239bbd3
CM		 8758 We look for SP 32-bit and DP 64-bit registers.
8759 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8760 <list> is consecutive 64-bit registers
8761 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8762 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8763 <list> is consecutive 32-bit registers
8764 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8765 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8766 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8767 return
9239bbd3
CM		 8768 (((insn & 0xfe100f00) == 0xec100b00) ||
8769 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8770 && /* (IA without !). */
8771 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8772 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8773 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8774 /* (DB with !). */
8775 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8776}
8777
8778/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8779 VLDM opcode and:
8780 - computes the number and the mode of memory accesses
8781 - decides if the replacement should be done:
8782 . replaces only if > 8-word accesses
8783 . or (testing purposes only) replaces all accesses. */
8784
8785static bfd_boolean
8786stm32l4xx_need_create_replacing_stub (const insn32 insn,
8787 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8788{
9239bbd3 8789 int nb_words = 0;
a504d23a
LA		 8790
8791 /* The field encoding the register list is the same for both LDMIA
8792 and LDMDB encodings. */
8793 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8794 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8795 else if (is_thumb2_vldm (insn))
9239bbd3 8796 nb_words = (insn & 0xff);
a504d23a
LA		 8797
8798 /* DEFAULT mode accounts for the real bug condition situation,
8799 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8800 return
9239bbd3 8801 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8802 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8803}
8804
8805/* Look for potentially-troublesome code sequences which might trigger
8806 the STM STM32L4XX erratum. */
8807
8808bfd_boolean
8809bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8810 struct bfd_link_info *link_info)
8811{
8812 asection *sec;
8813 bfd_byte *contents = NULL;
8814 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8815
8816 if (globals == NULL)
8817 return FALSE;
8818
8819 /* If we are only performing a partial link do not bother
8820 to construct any glue. */
8821 if (bfd_link_relocatable (link_info))
8822 return TRUE;
8823
8824 /* Skip if this bfd does not correspond to an ELF image. */
8825 if (! is_arm_elf (abfd))
8826 return TRUE;
8827
8828 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8829 return TRUE;
8830
8831 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8832 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8833 return TRUE;
8834
8835 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8836 {
8837 unsigned int i, span;
8838 struct _arm_elf_section_data *sec_data;
8839
8840 /* If we don't have executable progbits, we're not interested in this
8841 section. Also skip if section is to be excluded. */
8842 if (elf_section_type (sec) != SHT_PROGBITS
8843 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8844 || (sec->flags & SEC_EXCLUDE) != 0
8845 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8846 || sec->output_section == bfd_abs_section_ptr
8847 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8848 continue;
8849
8850 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8851
a504d23a
LA		 8852 if (sec_data->mapcount == 0)
8853 continue;
c7b8f16e 8854
a504d23a
LA		 8855 if (elf_section_data (sec)->this_hdr.contents != NULL)
8856 contents = elf_section_data (sec)->this_hdr.contents;
8857 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8858 goto error_return;
c7b8f16e 8859
a504d23a
LA		 8860 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8861 elf32_arm_compare_mapping);
c7b8f16e 8862
a504d23a
LA		 8863 for (span = 0; span < sec_data->mapcount; span++)
8864 {
8865 unsigned int span_start = sec_data->map[span].vma;
8866 unsigned int span_end = (span == sec_data->mapcount - 1)
8867 ? sec->size : sec_data->map[span + 1].vma;
8868 char span_type = sec_data->map[span].type;
8869 int itblock_current_pos = 0;
c7b8f16e 8870
a504d23a
LA		 8871 /* Only Thumb2 mode need be supported with this CM4 specific
8872 code, we should not encounter any arm mode eg span_type
8873 != 'a'. */
8874 if (span_type != 't')
8875 continue;
c7b8f16e 8876
a504d23a
LA		 8877 for (i = span_start; i < span_end;)
8878 {
8879 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8880 bfd_boolean insn_32bit = FALSE;
8881 bfd_boolean is_ldm = FALSE;
8882 bfd_boolean is_vldm = FALSE;
8883 bfd_boolean is_not_last_in_it_block = FALSE;
8884
8885 /* The first 16-bits of all 32-bit thumb2 instructions start
8886 with opcode[15..13]=0b111 and the encoded op1 can be anything
8887 except opcode[12..11]!=0b00.
8888 See 32-bit Thumb instruction encoding. */
8889 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8890 insn_32bit = TRUE;
c7b8f16e 8891
a504d23a
LA		 8892 /* Compute the predicate that tells if the instruction
8893 is concerned by the IT block
8894 - Creates an error if there is a ldm that is not
8895 last in the IT block thus cannot be replaced
8896 - Otherwise we can create a branch at the end of the
8897 IT block, it will be controlled naturally by IT
8898 with the proper pseudo-predicate
8899 - So the only interesting predicate is the one that
8900 tells that we are not on the last item of an IT
8901 block. */
8902 if (itblock_current_pos != 0)
8903 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8904
a504d23a
LA		 8905 if (insn_32bit)
8906 {
8907 /* Load the rest of the insn (in manual-friendly order). */
8908 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8909 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8910 is_vldm = is_thumb2_vldm (insn);
8911
8912 /* Veneers are created for (v)ldm depending on
8913 option flags and memory accesses conditions; but
8914 if the instruction is not the last instruction of
8915 an IT block, we cannot create a jump there, so we
8916 bail out. */
5025eb7c
AO		 8917 if ((is_ldm || is_vldm)
8918 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8919 (insn, globals->stm32l4xx_fix))
8920 {
8921 if (is_not_last_in_it_block)
8922 {
4eca0228 8923 _bfd_error_handler
695344c0 8924 /* xgettext:c-format */
871b3ab2 8925 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8926 " in non-last IT block instruction:"
8927 " STM32L4XX veneer cannot be generated; "
8928 "use gcc option -mrestrict-it to generate"
8929 " only one instruction per IT block"),
d42c267e 8930 abfd, sec, i);
a504d23a
LA		 8931 }
8932 else
8933 {
8934 elf32_stm32l4xx_erratum_list *newerr =
8935 (elf32_stm32l4xx_erratum_list *)
8936 bfd_zmalloc
8937 (sizeof (elf32_stm32l4xx_erratum_list));
8938
8939 elf32_arm_section_data (sec)
8940 ->stm32l4xx_erratumcount += 1;
8941 newerr->u.b.insn = insn;
8942 /* We create only thumb branches. */
8943 newerr->type =
8944 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8945 record_stm32l4xx_erratum_veneer
8946 (link_info, newerr, abfd, sec,
8947 i,
8948 is_ldm ?
8949 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8950 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8951 newerr->vma = -1;
8952 newerr->next = sec_data->stm32l4xx_erratumlist;
8953 sec_data->stm32l4xx_erratumlist = newerr;
8954 }
8955 }
8956 }
8957 else
8958 {
8959 /* A7.7.37 IT p208
8960 IT blocks are only encoded in T1
8961 Encoding T1: IT{x{y{z}}} <firstcond>
8962 1 0 1 1 - 1 1 1 1 - firstcond - mask
8963 if mask = '0000' then see 'related encodings'
8964 We don't deal with UNPREDICTABLE, just ignore these.
8965 There can be no nested IT blocks so an IT block
8966 is naturally a new one for which it is worth
8967 computing its size. */
5025eb7c
AO		 8968 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8969 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8970 /* If we have a new IT block we compute its size. */
8971 if (is_newitblock)
8972 {
8973 /* Compute the number of instructions controlled
8974 by the IT block, it will be used to decide
8975 whether we are inside an IT block or not. */
8976 unsigned int mask = insn & 0x000f;
8977 itblock_current_pos = 4 - ctz (mask);
8978 }
8979 }
8980
8981 i += insn_32bit ? 4 : 2;
99059e56
RM		 8982 }
8983 }
a504d23a 8984
c9594989 8985 if (elf_section_data (sec)->this_hdr.contents != contents)
a504d23a
LA		 8986 free (contents);
8987 contents = NULL;
c7b8f16e 8988 }
906e58ca 8989
a504d23a
LA		 8990 return TRUE;
8991
dc1e8a47 8992 error_return:
c9594989 8993 if (elf_section_data (sec)->this_hdr.contents != contents)
a504d23a 8994 free (contents);
c7b8f16e 8995
a504d23a
LA		 8996 return FALSE;
8997}
c7b8f16e 8998
eb043451
PB		 8999/* Set target relocation values needed during linking. */
9000
9001void
68c39892 9002bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9003 struct bfd_link_info *link_info,
68c39892 9004 struct elf32_arm_params *params)
eb043451
PB		 9005{
9006 struct elf32_arm_link_hash_table *globals;
9007
9008 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9009 if (globals == NULL)
9010 return;
eb043451 9011
68c39892 9012 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9013 if (globals->fdpic_p)
9014 globals->target2_reloc = R_ARM_GOT32;
9015 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9016 globals->target2_reloc = R_ARM_REL32;
68c39892 9017 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9018 globals->target2_reloc = R_ARM_ABS32;
68c39892 9019 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9020 globals->target2_reloc = R_ARM_GOT_PREL;
9021 else
9022 {
90b6238f 9023 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9024 params->target2_type);
eb043451 9025 }
68c39892
TP		 9026 globals->fix_v4bx = params->fix_v4bx;
9027 globals->use_blx |= params->use_blx;
9028 globals->vfp11_fix = params->vfp11_denorm_fix;
9029 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9030 if (globals->fdpic_p)
9031 globals->pic_veneer = 1;
9032 else
9033 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9034 globals->fix_cortex_a8 = params->fix_cortex_a8;
9035 globals->fix_arm1176 = params->fix_arm1176;
9036 globals->cmse_implib = params->cmse_implib;
9037 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9038
0ffa91dd 9039 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9040 elf_arm_tdata (output_bfd)->no_enum_size_warning
9041 = params->no_enum_size_warning;
9042 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9043 = params->no_wchar_size_warning;
eb043451 9044}
eb043451 9045
12a0a0fd 9046/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9047
12a0a0fd
PB		 9048static void
9049insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9050{
9051 bfd_vma upper;
9052 bfd_vma lower;
9053 int reloc_sign;
9054
9055 BFD_ASSERT ((offset & 1) == 0);
9056
9057 upper = bfd_get_16 (abfd, insn);
9058 lower = bfd_get_16 (abfd, insn + 2);
9059 reloc_sign = (offset < 0) ? 1 : 0;
9060 upper = (upper & ~(bfd_vma) 0x7ff)
9061 | ((offset >> 12) & 0x3ff)
9062 | (reloc_sign << 10);
906e58ca 9063 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9064 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9065 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9066 | ((offset >> 1) & 0x7ff);
9067 bfd_put_16 (abfd, upper, insn);
9068 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9069}
9070
9b485d32
NC		 9071/* Thumb code calling an ARM function. */
9072
252b5132 9073static int
57e8b36a 9074elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9075 const char * name,
9076 bfd * input_bfd,
9077 bfd * output_bfd,
9078 asection * input_section,
9079 bfd_byte * hit_data,
9080 asection * sym_sec,
9081 bfd_vma offset,
9082 bfd_signed_vma addend,
9083 bfd_vma val,
f2a9dd69 9084 char **error_message)
252b5132 9085{
bcbdc74c 9086 asection * s = 0;
dc810e39 9087 bfd_vma my_offset;
252b5132 9088 long int ret_offset;
bcbdc74c
NC		 9089 struct elf_link_hash_entry * myh;
9090 struct elf32_arm_link_hash_table * globals;
252b5132 9091
f2a9dd69 9092 myh = find_thumb_glue (info, name, error_message);
252b5132 9093 if (myh == NULL)
b34976b6 9094 return FALSE;
252b5132
RH		 9095
9096 globals = elf32_arm_hash_table (info);
252b5132
RH		 9097 BFD_ASSERT (globals != NULL);
9098 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9099
9100 my_offset = myh->root.u.def.value;
9101
3d4d4302
AM		 9102 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9103 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9104
9105 BFD_ASSERT (s != NULL);
9106 BFD_ASSERT (s->contents != NULL);
9107 BFD_ASSERT (s->output_section != NULL);
9108
9109 if ((my_offset & 0x01) == 0x01)
9110 {
9111 if (sym_sec != NULL
9112 && sym_sec->owner != NULL
9113 && !INTERWORK_FLAG (sym_sec->owner))
9114 {
4eca0228 9115 _bfd_error_handler
90b6238f
AM		 9116 (_("%pB(%s): warning: interworking not enabled;"
9117 " first occurrence: %pB: %s call to %s"),
9118 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9119
b34976b6 9120 return FALSE;
252b5132
RH		 9121 }
9122
9123 --my_offset;
9124 myh->root.u.def.value = my_offset;
9125
52ab56c2
PB		 9126 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9127 s->contents + my_offset);
252b5132 9128
52ab56c2
PB		 9129 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9130 s->contents + my_offset + 2);
252b5132
RH		 9131
9132 ret_offset =
9b485d32
NC		 9133 /* Address of destination of the stub. */
9134 ((bfd_signed_vma) val)
252b5132 9135 - ((bfd_signed_vma)
57e8b36a
NC		 9136 /* Offset from the start of the current section
9137 to the start of the stubs. */
9b485d32
NC		 9138 (s->output_offset
9139 /* Offset of the start of this stub from the start of the stubs. */
9140 + my_offset
9141 /* Address of the start of the current section. */
9142 + s->output_section->vma)
9143 /* The branch instruction is 4 bytes into the stub. */
9144 + 4
9145 /* ARM branches work from the pc of the instruction + 8. */
9146 + 8);
252b5132 9147
52ab56c2
PB		 9148 put_arm_insn (globals, output_bfd,
9149 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9150 s->contents + my_offset + 4);
252b5132
RH		 9151 }
9152
9153 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9154
427bfd90
NC		 9155 /* Now go back and fix up the original BL insn to point to here. */
9156 ret_offset =
9157 /* Address of where the stub is located. */
9158 (s->output_section->vma + s->output_offset + my_offset)
9159 /* Address of where the BL is located. */
57e8b36a
NC		 9160 - (input_section->output_section->vma + input_section->output_offset
9161 + offset)
427bfd90
NC		 9162 /* Addend in the relocation. */
9163 - addend
9164 /* Biassing for PC-relative addressing. */
9165 - 8;
252b5132 9166
12a0a0fd 9167 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9168
b34976b6 9169 return TRUE;
252b5132
RH		 9170}
9171
a4fd1a8e 9172/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9173
a4fd1a8e
PB		 9174static struct elf_link_hash_entry *
9175elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9176 const char * name,
9177 bfd * input_bfd,
9178 bfd * output_bfd,
9179 asection * sym_sec,
9180 bfd_vma val,
9181 asection * s,
9182 char ** error_message)
252b5132 9183{
dc810e39 9184 bfd_vma my_offset;
252b5132 9185 long int ret_offset;
bcbdc74c
NC		 9186 struct elf_link_hash_entry * myh;
9187 struct elf32_arm_link_hash_table * globals;
252b5132 9188
f2a9dd69 9189 myh = find_arm_glue (info, name, error_message);
252b5132 9190 if (myh == NULL)
a4fd1a8e 9191 return NULL;
252b5132
RH		 9192
9193 globals = elf32_arm_hash_table (info);
252b5132
RH		 9194 BFD_ASSERT (globals != NULL);
9195 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9196
9197 my_offset = myh->root.u.def.value;
252b5132
RH		 9198
9199 if ((my_offset & 0x01) == 0x01)
9200 {
9201 if (sym_sec != NULL
9202 && sym_sec->owner != NULL
9203 && !INTERWORK_FLAG (sym_sec->owner))
9204 {
4eca0228 9205 _bfd_error_handler
90b6238f
AM		 9206 (_("%pB(%s): warning: interworking not enabled;"
9207 " first occurrence: %pB: %s call to %s"),
9208 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9209 }
9b485d32 9210
252b5132
RH		 9211 --my_offset;
9212 myh->root.u.def.value = my_offset;
9213
0e1862bb
L		 9214 if (bfd_link_pic (info)
9215 || globals->root.is_relocatable_executable
27e55c4d 9216 || globals->pic_veneer)
8f6277f5
PB		 9217 {
9218 /* For relocatable objects we can't use absolute addresses,
9219 so construct the address from a relative offset. */
9220 /* TODO: If the offset is small it's probably worth
9221 constructing the address with adds. */
52ab56c2
PB		 9222 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9223 s->contents + my_offset);
9224 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9225 s->contents + my_offset + 4);
9226 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9227 s->contents + my_offset + 8);
8f6277f5
PB		 9228 /* Adjust the offset by 4 for the position of the add,
9229 and 8 for the pipeline offset. */
9230 ret_offset = (val - (s->output_offset
9231 + s->output_section->vma
9232 + my_offset + 12))
9233 | 1;
9234 bfd_put_32 (output_bfd, ret_offset,
9235 s->contents + my_offset + 12);
9236 }
26079076
PB		 9237 else if (globals->use_blx)
9238 {
9239 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9240 s->contents + my_offset);
9241
9242 /* It's a thumb address. Add the low order bit. */
9243 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9244 s->contents + my_offset + 4);
9245 }
8f6277f5
PB		 9246 else
9247 {
52ab56c2
PB		 9248 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9249 s->contents + my_offset);
252b5132 9250
52ab56c2
PB		 9251 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9252 s->contents + my_offset + 4);
252b5132 9253
8f6277f5
PB		 9254 /* It's a thumb address. Add the low order bit. */
9255 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9256 s->contents + my_offset + 8);
8029a119
NC		 9257
9258 my_offset += 12;
8f6277f5 9259 }
252b5132
RH		 9260 }
9261
9262 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9263
a4fd1a8e
PB		 9264 return myh;
9265}
9266
9267/* Arm code calling a Thumb function. */
9268
9269static int
9270elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9271 const char * name,
9272 bfd * input_bfd,
9273 bfd * output_bfd,
9274 asection * input_section,
9275 bfd_byte * hit_data,
9276 asection * sym_sec,
9277 bfd_vma offset,
9278 bfd_signed_vma addend,
9279 bfd_vma val,
f2a9dd69 9280 char **error_message)
a4fd1a8e
PB		 9281{
9282 unsigned long int tmp;
9283 bfd_vma my_offset;
9284 asection * s;
9285 long int ret_offset;
9286 struct elf_link_hash_entry * myh;
9287 struct elf32_arm_link_hash_table * globals;
9288
9289 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9290 BFD_ASSERT (globals != NULL);
9291 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9292
3d4d4302
AM		 9293 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9294 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9295 BFD_ASSERT (s != NULL);
9296 BFD_ASSERT (s->contents != NULL);
9297 BFD_ASSERT (s->output_section != NULL);
9298
9299 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9300 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9301 if (!myh)
9302 return FALSE;
9303
9304 my_offset = myh->root.u.def.value;
252b5132
RH		 9305 tmp = bfd_get_32 (input_bfd, hit_data);
9306 tmp = tmp & 0xFF000000;
9307
9b485d32 9308 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9309 ret_offset = (s->output_offset
9310 + my_offset
9311 + s->output_section->vma
9312 - (input_section->output_offset
9313 + input_section->output_section->vma
9314 + offset + addend)
9315 - 8);
9a5aca8c 9316
252b5132
RH		 9317 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9318
dc810e39 9319 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9320
b34976b6 9321 return TRUE;
252b5132
RH		 9322}
9323
a4fd1a8e
PB		 9324/* Populate Arm stub for an exported Thumb function. */
9325
9326static bfd_boolean
9327elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9328{
9329 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9330 asection * s;
9331 struct elf_link_hash_entry * myh;
9332 struct elf32_arm_link_hash_entry *eh;
9333 struct elf32_arm_link_hash_table * globals;
9334 asection *sec;
9335 bfd_vma val;
f2a9dd69 9336 char *error_message;
a4fd1a8e 9337
906e58ca 9338 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9339 /* Allocate stubs for exported Thumb functions on v4t. */
9340 if (eh->export_glue == NULL)
9341 return TRUE;
9342
9343 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9344 BFD_ASSERT (globals != NULL);
9345 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9346
3d4d4302
AM		 9347 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9348 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9349 BFD_ASSERT (s != NULL);
9350 BFD_ASSERT (s->contents != NULL);
9351 BFD_ASSERT (s->output_section != NULL);
9352
9353 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9354
9355 BFD_ASSERT (sec->output_section != NULL);
9356
a4fd1a8e
PB		 9357 val = eh->export_glue->root.u.def.value + sec->output_offset
9358 + sec->output_section->vma;
8029a119 9359
a4fd1a8e
PB		 9360 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9361 h->root.u.def.section->owner,
f2a9dd69
DJ		 9362 globals->obfd, sec, val, s,
9363 &error_message);
a4fd1a8e
PB		 9364 BFD_ASSERT (myh);
9365 return TRUE;
9366}
9367
845b51d6
PB		 9368/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9369
9370static bfd_vma
9371elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9372{
9373 bfd_byte *p;
9374 bfd_vma glue_addr;
9375 asection *s;
9376 struct elf32_arm_link_hash_table *globals;
9377
9378 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9379 BFD_ASSERT (globals != NULL);
9380 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9381
3d4d4302
AM		 9382 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9383 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9384 BFD_ASSERT (s != NULL);
9385 BFD_ASSERT (s->contents != NULL);
9386 BFD_ASSERT (s->output_section != NULL);
9387
9388 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9389
9390 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9391
9392 if ((globals->bx_glue_offset[reg] & 1) == 0)
9393 {
9394 p = s->contents + glue_addr;
9395 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9396 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9397 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9398 globals->bx_glue_offset[reg] |= 1;
9399 }
9400
9401 return glue_addr + s->output_section->vma + s->output_offset;
9402}
9403
a4fd1a8e
PB		 9404/* Generate Arm stubs for exported Thumb symbols. */
9405static void
906e58ca 9406elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9407 struct bfd_link_info *link_info)
9408{
9409 struct elf32_arm_link_hash_table * globals;
9410
8029a119
NC		 9411 if (link_info == NULL)
9412 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9413 return;
9414
9415 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9416 if (globals == NULL)
9417 return;
9418
84c08195
PB		 9419 /* If blx is available then exported Thumb symbols are OK and there is
9420 nothing to do. */
a4fd1a8e
PB		 9421 if (globals->use_blx)
9422 return;
9423
9424 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9425 link_info);
9426}
9427
47beaa6a
RS		 9428/* Reserve space for COUNT dynamic relocations in relocation selection
9429 SRELOC. */
9430
9431static void
9432elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9433 bfd_size_type count)
9434{
9435 struct elf32_arm_link_hash_table *htab;
9436
9437 htab = elf32_arm_hash_table (info);
9438 BFD_ASSERT (htab->root.dynamic_sections_created);
9439 if (sreloc == NULL)
9440 abort ();
9441 sreloc->size += RELOC_SIZE (htab) * count;
9442}
9443
34e77a92
RS		 9444/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9445 dynamic, the relocations should go in SRELOC, otherwise they should
9446 go in the special .rel.iplt section. */
9447
9448static void
9449elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9450 bfd_size_type count)
9451{
9452 struct elf32_arm_link_hash_table *htab;
9453
9454 htab = elf32_arm_hash_table (info);
9455 if (!htab->root.dynamic_sections_created)
9456 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9457 else
9458 {
9459 BFD_ASSERT (sreloc != NULL);
9460 sreloc->size += RELOC_SIZE (htab) * count;
9461 }
9462}
9463
47beaa6a
RS		 9464/* Add relocation REL to the end of relocation section SRELOC. */
9465
9466static void
9467elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9468 asection *sreloc, Elf_Internal_Rela *rel)
9469{
9470 bfd_byte *loc;
9471 struct elf32_arm_link_hash_table *htab;
9472
9473 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9474 if (!htab->root.dynamic_sections_created
9475 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9476 sreloc = htab->root.irelplt;
47beaa6a
RS		 9477 if (sreloc == NULL)
9478 abort ();
9479 loc = sreloc->contents;
9480 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9481 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9482 abort ();
9483 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9484}
9485
34e77a92
RS		 9486/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9487 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9488 to .plt. */
9489
9490static void
9491elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9492 bfd_boolean is_iplt_entry,
9493 union gotplt_union *root_plt,
9494 struct arm_plt_info *arm_plt)
9495{
9496 struct elf32_arm_link_hash_table *htab;
9497 asection *splt;
9498 asection *sgotplt;
9499
9500 htab = elf32_arm_hash_table (info);
9501
9502 if (is_iplt_entry)
9503 {
9504 splt = htab->root.iplt;
9505 sgotplt = htab->root.igotplt;
9506
99059e56 9507 /* NaCl uses a special first entry in .iplt too. */
90c14f0c 9508 if (htab->root.target_os == is_nacl && splt->size == 0)
99059e56
RM		 9509 splt->size += htab->plt_header_size;
9510
34e77a92
RS		 9511 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9512 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9513 }
9514 else
9515 {
9516 splt = htab->root.splt;
9517 sgotplt = htab->root.sgotplt;
9518
7801f98f
CL		 9519 if (htab->fdpic_p)
9520 {
9521 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9522 /* For lazy binding, relocations will be put into .rel.plt, in
9523 .rel.got otherwise. */
9524 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9525 if (info->flags & DF_BIND_NOW)
9526 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9527 else
9528 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9529 }
9530 else
9531 {
9532 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9533 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9534 }
34e77a92
RS		 9535
9536 /* If this is the first .plt entry, make room for the special
9537 first entry. */
9538 if (splt->size == 0)
9539 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9540
9541 htab->next_tls_desc_index++;
34e77a92
RS		 9542 }
9543
9544 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9545 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9546 splt->size += PLT_THUMB_STUB_SIZE;
9547 root_plt->offset = splt->size;
9548 splt->size += htab->plt_entry_size;
9549
90c14f0c 9550 if (htab->root.target_os != is_symbian)
34e77a92
RS		 9551 {
9552 /* We also need to make an entry in the .got.plt section, which
9553 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9554 if (is_iplt_entry)
9555 arm_plt->got_offset = sgotplt->size;
9556 else
9557 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9558 if (htab->fdpic_p)
9559 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9560 sgotplt->size += 8;
7801f98f
CL		 9561 else
9562 sgotplt->size += 4;
34e77a92
RS		 9563 }
9564}
9565
b38cadfb
NC		 9566static bfd_vma
9567arm_movw_immediate (bfd_vma value)
9568{
9569 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9570}
9571
9572static bfd_vma
9573arm_movt_immediate (bfd_vma value)
9574{
9575 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9576}
9577
34e77a92
RS		 9578/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9579 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9580 Otherwise, DYNINDX is the index of the symbol in the dynamic
9581 symbol table and SYM_VALUE is undefined.
9582
9583 ROOT_PLT points to the offset of the PLT entry from the start of its
9584 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9585 bookkeeping information.
34e77a92 9586
57460bcf
NC		 9587 Returns FALSE if there was a problem. */
9588
9589static bfd_boolean
34e77a92
RS		 9590elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9591 union gotplt_union *root_plt,
9592 struct arm_plt_info *arm_plt,
9593 int dynindx, bfd_vma sym_value)
9594{
9595 struct elf32_arm_link_hash_table *htab;
9596 asection *sgot;
9597 asection *splt;
9598 asection *srel;
9599 bfd_byte *loc;
9600 bfd_vma plt_index;
9601 Elf_Internal_Rela rel;
9602 bfd_vma plt_header_size;
9603 bfd_vma got_header_size;
9604
9605 htab = elf32_arm_hash_table (info);
9606
9607 /* Pick the appropriate sections and sizes. */
9608 if (dynindx == -1)
9609 {
9610 splt = htab->root.iplt;
9611 sgot = htab->root.igotplt;
9612 srel = htab->root.irelplt;
9613
9614 /* There are no reserved entries in .igot.plt, and no special
9615 first entry in .iplt. */
9616 got_header_size = 0;
9617 plt_header_size = 0;
9618 }
9619 else
9620 {
9621 splt = htab->root.splt;
9622 sgot = htab->root.sgotplt;
9623 srel = htab->root.srelplt;
9624
9625 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9626 plt_header_size = htab->plt_header_size;
9627 }
9628 BFD_ASSERT (splt != NULL && srel != NULL);
9629
9630 /* Fill in the entry in the procedure linkage table. */
90c14f0c 9631 if (htab->root.target_os == is_symbian)
34e77a92
RS		 9632 {
9633 BFD_ASSERT (dynindx >= 0);
9634 put_arm_insn (htab, output_bfd,
9635 elf32_arm_symbian_plt_entry[0],
9636 splt->contents + root_plt->offset);
9637 bfd_put_32 (output_bfd,
9638 elf32_arm_symbian_plt_entry[1],
9639 splt->contents + root_plt->offset + 4);
9640
9641 /* Fill in the entry in the .rel.plt section. */
9642 rel.r_offset = (splt->output_section->vma
9643 + splt->output_offset
9644 + root_plt->offset + 4);
9645 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9646
9647 /* Get the index in the procedure linkage table which
9648 corresponds to this symbol. This is the index of this symbol
9649 in all the symbols for which we are making plt entries. The
9650 first entry in the procedure linkage table is reserved. */
9651 plt_index = ((root_plt->offset - plt_header_size)
9652 / htab->plt_entry_size);
9653 }
9654 else
9655 {
9656 bfd_vma got_offset, got_address, plt_address;
9657 bfd_vma got_displacement, initial_got_entry;
9658 bfd_byte * ptr;
9659
9660 BFD_ASSERT (sgot != NULL);
9661
9662 /* Get the offset into the .(i)got.plt table of the entry that
9663 corresponds to this function. */
9664 got_offset = (arm_plt->got_offset & -2);
9665
9666 /* Get the index in the procedure linkage table which
9667 corresponds to this symbol. This is the index of this symbol
9668 in all the symbols for which we are making plt entries.
9669 After the reserved .got.plt entries, all symbols appear in
9670 the same order as in .plt. */
7801f98f 9671 if (htab->fdpic_p)
4b24dd1a
AM		 9672 /* Function descriptor takes 8 bytes. */
9673 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9674 else
4b24dd1a 9675 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9676
9677 /* Calculate the address of the GOT entry. */
9678 got_address = (sgot->output_section->vma
9679 + sgot->output_offset
9680 + got_offset);
9681
9682 /* ...and the address of the PLT entry. */
9683 plt_address = (splt->output_section->vma
9684 + splt->output_offset
9685 + root_plt->offset);
9686
9687 ptr = splt->contents + root_plt->offset;
90c14f0c 9688 if (htab->root.target_os == is_vxworks && bfd_link_pic (info))
34e77a92
RS		 9689 {
9690 unsigned int i;
9691 bfd_vma val;
9692
9693 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9694 {
9695 val = elf32_arm_vxworks_shared_plt_entry[i];
9696 if (i == 2)
9697 val |= got_address - sgot->output_section->vma;
9698 if (i == 5)
9699 val |= plt_index * RELOC_SIZE (htab);
9700 if (i == 2 || i == 5)
9701 bfd_put_32 (output_bfd, val, ptr);
9702 else
9703 put_arm_insn (htab, output_bfd, val, ptr);
9704 }
9705 }
90c14f0c 9706 else if (htab->root.target_os == is_vxworks)
34e77a92
RS		 9707 {
9708 unsigned int i;
9709 bfd_vma val;
9710
9711 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9712 {
9713 val = elf32_arm_vxworks_exec_plt_entry[i];
9714 if (i == 2)
9715 val |= got_address;
9716 if (i == 4)
9717 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9718 if (i == 5)
9719 val |= plt_index * RELOC_SIZE (htab);
9720 if (i == 2 || i == 5)
9721 bfd_put_32 (output_bfd, val, ptr);
9722 else
9723 put_arm_insn (htab, output_bfd, val, ptr);
9724 }
9725
9726 loc = (htab->srelplt2->contents
9727 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9728
9729 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9730 referencing the GOT for this PLT entry. */
9731 rel.r_offset = plt_address + 8;
9732 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9733 rel.r_addend = got_offset;
9734 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9735 loc += RELOC_SIZE (htab);
9736
9737 /* Create the R_ARM_ABS32 relocation referencing the
9738 beginning of the PLT for this GOT entry. */
9739 rel.r_offset = got_address;
9740 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9741 rel.r_addend = 0;
9742 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9743 }
90c14f0c 9744 else if (htab->root.target_os == is_nacl)
b38cadfb
NC		 9745 {
9746 /* Calculate the displacement between the PLT slot and the
9747 common tail that's part of the special initial PLT slot. */
6034aab8 9748 int32_t tail_displacement
b38cadfb
NC		 9749 = ((splt->output_section->vma + splt->output_offset
9750 + ARM_NACL_PLT_TAIL_OFFSET)
9751 - (plt_address + htab->plt_entry_size + 4));
9752 BFD_ASSERT ((tail_displacement & 3) == 0);
9753 tail_displacement >>= 2;
9754
9755 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9756 || (-tail_displacement & 0xff000000) == 0);
9757
9758 /* Calculate the displacement between the PLT slot and the entry
9759 in the GOT. The offset accounts for the value produced by
9760 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9761 got_displacement = (got_address
99059e56 9762 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9763
9764 /* NaCl does not support interworking at all. */
9765 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9766
9767 put_arm_insn (htab, output_bfd,
9768 elf32_arm_nacl_plt_entry[0]
9769 | arm_movw_immediate (got_displacement),
9770 ptr + 0);
9771 put_arm_insn (htab, output_bfd,
9772 elf32_arm_nacl_plt_entry[1]
9773 | arm_movt_immediate (got_displacement),
9774 ptr + 4);
9775 put_arm_insn (htab, output_bfd,
9776 elf32_arm_nacl_plt_entry[2],
9777 ptr + 8);
9778 put_arm_insn (htab, output_bfd,
9779 elf32_arm_nacl_plt_entry[3]
9780 | (tail_displacement & 0x00ffffff),
9781 ptr + 12);
9782 }
7801f98f
CL		 9783 else if (htab->fdpic_p)
9784 {
59029f57
CL		 9785 const bfd_vma *plt_entry = using_thumb_only(htab)
9786 ? elf32_arm_fdpic_thumb_plt_entry
9787 : elf32_arm_fdpic_plt_entry;
9788
7801f98f
CL		 9789 /* Fill-up Thumb stub if needed. */
9790 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9791 {
9792 put_thumb_insn (htab, output_bfd,
9793 elf32_arm_plt_thumb_stub[0], ptr - 4);
9794 put_thumb_insn (htab, output_bfd,
9795 elf32_arm_plt_thumb_stub[1], ptr - 2);
9796 }
59029f57
CL		 9797 /* As we are using 32 bit instructions even for the Thumb
9798 version, we have to use 'put_arm_insn' instead of
9799 'put_thumb_insn'. */
9800 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9801 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9802 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9803 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9804 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9805
9806 if (!(info->flags & DF_BIND_NOW))
9807 {
9808 /* funcdesc_value_reloc_offset. */
9809 bfd_put_32 (output_bfd,
9810 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9811 ptr + 20);
59029f57
CL		 9812 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9813 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9814 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9815 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9816 }
9817 }
57460bcf
NC		 9818 else if (using_thumb_only (htab))
9819 {
eed94f8f 9820 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9821 if (!using_thumb2 (htab))
eed94f8f
NC		 9822 {
9823 /* FIXME: We ought to be able to generate thumb-1 PLT
9824 instructions... */
90b6238f 9825 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9826 output_bfd);
9827 return FALSE;
9828 }
57460bcf 9829
eed94f8f
NC		 9830 /* Calculate the displacement between the PLT slot and the entry in
9831 the GOT. The 12-byte offset accounts for the value produced by
9832 adding to pc in the 3rd instruction of the PLT stub. */
9833 got_displacement = got_address - (plt_address + 12);
9834
9835 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9836 instead of 'put_thumb_insn'. */
9837 put_arm_insn (htab, output_bfd,
9838 elf32_thumb2_plt_entry[0]
9839 | ((got_displacement & 0x000000ff) << 16)
9840 | ((got_displacement & 0x00000700) << 20)
9841 | ((got_displacement & 0x00000800) >> 1)
9842 | ((got_displacement & 0x0000f000) >> 12),
9843 ptr + 0);
9844 put_arm_insn (htab, output_bfd,
9845 elf32_thumb2_plt_entry[1]
9846 | ((got_displacement & 0x00ff0000) )
9847 | ((got_displacement & 0x07000000) << 4)
9848 | ((got_displacement & 0x08000000) >> 17)
9849 | ((got_displacement & 0xf0000000) >> 28),
9850 ptr + 4);
9851 put_arm_insn (htab, output_bfd,
9852 elf32_thumb2_plt_entry[2],
9853 ptr + 8);
9854 put_arm_insn (htab, output_bfd,
9855 elf32_thumb2_plt_entry[3],
9856 ptr + 12);
57460bcf 9857 }
34e77a92
RS		 9858 else
9859 {
9860 /* Calculate the displacement between the PLT slot and the
9861 entry in the GOT. The eight-byte offset accounts for the
9862 value produced by adding to pc in the first instruction
9863 of the PLT stub. */
9864 got_displacement = got_address - (plt_address + 8);
9865
34e77a92
RS		 9866 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9867 {
9868 put_thumb_insn (htab, output_bfd,
9869 elf32_arm_plt_thumb_stub[0], ptr - 4);
9870 put_thumb_insn (htab, output_bfd,
9871 elf32_arm_plt_thumb_stub[1], ptr - 2);
9872 }
9873
1db37fe6
YG		 9874 if (!elf32_arm_use_long_plt_entry)
9875 {
9876 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9877
9878 put_arm_insn (htab, output_bfd,
9879 elf32_arm_plt_entry_short[0]
9880 | ((got_displacement & 0x0ff00000) >> 20),
9881 ptr + 0);
9882 put_arm_insn (htab, output_bfd,
9883 elf32_arm_plt_entry_short[1]
9884 | ((got_displacement & 0x000ff000) >> 12),
9885 ptr+ 4);
9886 put_arm_insn (htab, output_bfd,
9887 elf32_arm_plt_entry_short[2]
9888 | (got_displacement & 0x00000fff),
9889 ptr + 8);
34e77a92 9890#ifdef FOUR_WORD_PLT
1db37fe6 9891 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9892#endif
1db37fe6
YG		 9893 }
9894 else
9895 {
9896 put_arm_insn (htab, output_bfd,
9897 elf32_arm_plt_entry_long[0]
9898 | ((got_displacement & 0xf0000000) >> 28),
9899 ptr + 0);
9900 put_arm_insn (htab, output_bfd,
9901 elf32_arm_plt_entry_long[1]
9902 | ((got_displacement & 0x0ff00000) >> 20),
9903 ptr + 4);
9904 put_arm_insn (htab, output_bfd,
9905 elf32_arm_plt_entry_long[2]
9906 | ((got_displacement & 0x000ff000) >> 12),
9907 ptr+ 8);
9908 put_arm_insn (htab, output_bfd,
9909 elf32_arm_plt_entry_long[3]
9910 | (got_displacement & 0x00000fff),
9911 ptr + 12);
9912 }
34e77a92
RS		 9913 }
9914
9915 /* Fill in the entry in the .rel(a).(i)plt section. */
9916 rel.r_offset = got_address;
9917 rel.r_addend = 0;
9918 if (dynindx == -1)
9919 {
9920 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9921 The dynamic linker or static executable then calls SYM_VALUE
9922 to determine the correct run-time value of the .igot.plt entry. */
9923 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9924 initial_got_entry = sym_value;
9925 }
9926 else
9927 {
7801f98f
CL		 9928 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9929 used by PLT entry. */
9930 if (htab->fdpic_p)
9931 {
9932 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9933 initial_got_entry = 0;
9934 }
9935 else
9936 {
9937 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9938 initial_got_entry = (splt->output_section->vma
9939 + splt->output_offset);
a7618269
TC		 9940
9941 /* PR ld/16017
9942 When thumb only we need to set the LSB for any address that
9943 will be used with an interworking branch instruction. */
9944 if (using_thumb_only (htab))
9945 initial_got_entry |= 1;
7801f98f 9946 }
34e77a92
RS		 9947 }
9948
9949 /* Fill in the entry in the global offset table. */
9950 bfd_put_32 (output_bfd, initial_got_entry,
9951 sgot->contents + got_offset);
7801f98f
CL		 9952
9953 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9954 {
9955 /* Setup initial funcdesc value. */
9956 /* FIXME: we don't support lazy binding because there is a
9957 race condition between both words getting written and
9958 some other thread attempting to read them. The ARM
9959 architecture does not have an atomic 64 bit load/store
9960 instruction that could be used to prevent it; it is
9961 recommended that threaded FDPIC applications run with the
9962 LD_BIND_NOW environment variable set. */
9963 bfd_put_32(output_bfd, plt_address + 0x18,
9964 sgot->contents + got_offset);
9965 bfd_put_32(output_bfd, -1 /*TODO*/,
9966 sgot->contents + got_offset + 4);
9967 }
34e77a92
RS		 9968 }
9969
aba8c3de
WN		 9970 if (dynindx == -1)
9971 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9972 else
9973 {
7801f98f
CL		 9974 if (htab->fdpic_p)
9975 {
9976 /* For FDPIC we put PLT relocationss into .rel.got when not
9977 lazy binding otherwise we put them in .rel.plt. For now,
9978 we don't support lazy binding so put it in .rel.got. */
9979 if (info->flags & DF_BIND_NOW)
9980 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
9981 else
9982 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
9983 }
9984 else
9985 {
9986 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9987 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9988 }
aba8c3de 9989 }
57460bcf
NC		 9990
9991 return TRUE;
34e77a92
RS		 9992}
9993
eb043451
PB		 9994/* Some relocations map to different relocations depending on the
9995 target. Return the real relocation. */
8029a119 9996
eb043451
PB		 9997static int
9998arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9999 int r_type)
10000{
10001 switch (r_type)
10002 {
10003 case R_ARM_TARGET1:
10004 if (globals->target1_is_rel)
10005 return R_ARM_REL32;
10006 else
10007 return R_ARM_ABS32;
10008
10009 case R_ARM_TARGET2:
10010 return globals->target2_reloc;
10011
10012 default:
10013 return r_type;
10014 }
10015}
eb043451 10016
ba93b8ac
DJ		 10017/* Return the base VMA address which should be subtracted from real addresses
10018 when resolving @dtpoff relocation.
10019 This is PT_TLS segment p_vaddr. */
10020
10021static bfd_vma
10022dtpoff_base (struct bfd_link_info *info)
10023{
10024 /* If tls_sec is NULL, we should have signalled an error already. */
10025 if (elf_hash_table (info)->tls_sec == NULL)
10026 return 0;
10027 return elf_hash_table (info)->tls_sec->vma;
10028}
10029
10030/* Return the relocation value for @tpoff relocation
10031 if STT_TLS virtual address is ADDRESS. */
10032
10033static bfd_vma
10034tpoff (struct bfd_link_info *info, bfd_vma address)
10035{
10036 struct elf_link_hash_table *htab = elf_hash_table (info);
10037 bfd_vma base;
10038
10039 /* If tls_sec is NULL, we should have signalled an error already. */
10040 if (htab->tls_sec == NULL)
10041 return 0;
10042 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10043 return address - htab->tls_sec->vma + base;
10044}
10045
00a97672
RS		 10046/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10047 VALUE is the relocation value. */
10048
10049static bfd_reloc_status_type
10050elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10051{
10052 if (value > 0xfff)
10053 return bfd_reloc_overflow;
10054
10055 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10056 bfd_put_32 (abfd, value, data);
10057 return bfd_reloc_ok;
10058}
10059
0855e32b
NS		 10060/* Handle TLS relaxations. Relaxing is possible for symbols that use
10061 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10062 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10063
10064 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10065 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10066 case of error.
10067
10068 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10069 the pre-relaxed code. It would be nice if the relocs were updated
10070 to match the optimization. */
0855e32b 10071
b38cadfb 10072static bfd_reloc_status_type
0855e32b 10073elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10074 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10075 Elf_Internal_Rela *rel, unsigned long is_local)
10076{
10077 unsigned long insn;
b38cadfb 10078
0855e32b
NS		 10079 switch (ELF32_R_TYPE (rel->r_info))
10080 {
10081 default:
10082 return bfd_reloc_notsupported;
b38cadfb 10083
0855e32b
NS		 10084 case R_ARM_TLS_GOTDESC:
10085 if (is_local)
10086 insn = 0;
10087 else
10088 {
10089 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10090 if (insn & 1)
10091 insn -= 5; /* THUMB */
10092 else
10093 insn -= 8; /* ARM */
10094 }
10095 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10096 return bfd_reloc_continue;
10097
10098 case R_ARM_THM_TLS_DESCSEQ:
10099 /* Thumb insn. */
10100 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10101 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10102 {
10103 if (is_local)
10104 /* nop */
10105 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10106 }
10107 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10108 {
10109 if (is_local)
10110 /* nop */
10111 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10112 else
10113 /* ldr rx,[ry] */
10114 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10115 }
10116 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10117 {
10118 if (is_local)
10119 /* nop */
10120 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10121 else
10122 /* mov r0, rx */
10123 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10124 contents + rel->r_offset);
10125 }
10126 else
10127 {
10128 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10129 /* It's a 32 bit instruction, fetch the rest of it for
10130 error generation. */
10131 insn = (insn << 16)
10132 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10133 _bfd_error_handler
695344c0 10134 /* xgettext:c-format */
2dcf00ce 10135 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10136 "unexpected %s instruction '%#lx' in TLS trampoline"),
10137 input_bfd, input_sec, (uint64_t) rel->r_offset,
10138 "Thumb", insn);
0855e32b
NS		 10139 return bfd_reloc_notsupported;
10140 }
10141 break;
b38cadfb 10142
0855e32b
NS		 10143 case R_ARM_TLS_DESCSEQ:
10144 /* arm insn. */
10145 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10146 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10147 {
10148 if (is_local)
10149 /* mov rx, ry */
10150 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10151 contents + rel->r_offset);
10152 }
10153 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10154 {
10155 if (is_local)
10156 /* nop */
10157 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10158 else
10159 /* ldr rx,[ry] */
10160 bfd_put_32 (input_bfd, insn & 0xfffff000,
10161 contents + rel->r_offset);
10162 }
10163 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10164 {
10165 if (is_local)
10166 /* nop */
10167 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10168 else
10169 /* mov r0, rx */
10170 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10171 contents + rel->r_offset);
10172 }
10173 else
10174 {
4eca0228 10175 _bfd_error_handler
695344c0 10176 /* xgettext:c-format */
2dcf00ce 10177 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10178 "unexpected %s instruction '%#lx' in TLS trampoline"),
10179 input_bfd, input_sec, (uint64_t) rel->r_offset,
10180 "ARM", insn);
0855e32b
NS		 10181 return bfd_reloc_notsupported;
10182 }
10183 break;
10184
10185 case R_ARM_TLS_CALL:
10186 /* GD->IE relaxation, turn the instruction into 'nop' or
10187 'ldr r0, [pc,r0]' */
10188 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10189 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10190 break;
b38cadfb 10191
0855e32b 10192 case R_ARM_THM_TLS_CALL:
6a631e86 10193 /* GD->IE relaxation. */
0855e32b
NS		 10194 if (!is_local)
10195 /* add r0,pc; ldr r0, [r0] */
10196 insn = 0x44786800;
60a019a0 10197 else if (using_thumb2 (globals))
0855e32b
NS		 10198 /* nop.w */
10199 insn = 0xf3af8000;
10200 else
10201 /* nop; nop */
10202 insn = 0xbf00bf00;
b38cadfb 10203
0855e32b
NS		 10204 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10205 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10206 break;
10207 }
10208 return bfd_reloc_ok;
10209}
10210
4962c51a
MS		 10211/* For a given value of n, calculate the value of G_n as required to
10212 deal with group relocations. We return it in the form of an
10213 encoded constant-and-rotation, together with the final residual. If n is
10214 specified as less than zero, then final_residual is filled with the
10215 input value and no further action is performed. */
10216
10217static bfd_vma
10218calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10219{
10220 int current_n;
10221 bfd_vma g_n;
10222 bfd_vma encoded_g_n = 0;
10223 bfd_vma residual = value; /* Also known as Y_n. */
10224
10225 for (current_n = 0; current_n <= n; current_n++)
10226 {
10227 int shift;
10228
10229 /* Calculate which part of the value to mask. */
10230 if (residual == 0)
99059e56 10231 shift = 0;
4962c51a 10232 else
99059e56
RM		 10233 {
10234 int msb;
10235
10236 /* Determine the most significant bit in the residual and
10237 align the resulting value to a 2-bit boundary. */
10238 for (msb = 30; msb >= 0; msb -= 2)
10239 if (residual & (3 << msb))
10240 break;
10241
10242 /* The desired shift is now (msb - 6), or zero, whichever
10243 is the greater. */
10244 shift = msb - 6;
10245 if (shift < 0)
10246 shift = 0;
10247 }
4962c51a
MS		 10248
10249 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10250 g_n = residual & (0xff << shift);
10251 encoded_g_n = (g_n >> shift)
99059e56 10252 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10253
10254 /* Calculate the residual for the next time around. */
10255 residual &= ~g_n;
10256 }
10257
10258 *final_residual = residual;
10259
10260 return encoded_g_n;
10261}
10262
10263/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10264 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10265
4962c51a 10266static int
906e58ca 10267identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10268{
10269 int opcode = insn & 0x1e00000;
10270
10271 if (opcode == 1 << 23) /* ADD */
10272 return 1;
10273
10274 if (opcode == 1 << 22) /* SUB */
10275 return -1;
10276
10277 return 0;
10278}
10279
252b5132 10280/* Perform a relocation as part of a final link. */
9b485d32 10281
252b5132 10282static bfd_reloc_status_type
07d6d2b8
AM		 10283elf32_arm_final_link_relocate (reloc_howto_type * howto,
10284 bfd * input_bfd,
10285 bfd * output_bfd,
10286 asection * input_section,
10287 bfd_byte * contents,
10288 Elf_Internal_Rela * rel,
10289 bfd_vma value,
10290 struct bfd_link_info * info,
10291 asection * sym_sec,
10292 const char * sym_name,
10293 unsigned char st_type,
10294 enum arm_st_branch_type branch_type,
0945cdfd 10295 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10296 bfd_boolean * unresolved_reloc_p,
10297 char ** error_message)
10298{
10299 unsigned long r_type = howto->type;
10300 unsigned long r_symndx;
10301 bfd_byte * hit_data = contents + rel->r_offset;
10302 bfd_vma * local_got_offsets;
10303 bfd_vma * local_tlsdesc_gotents;
10304 asection * sgot;
10305 asection * splt;
10306 asection * sreloc = NULL;
10307 asection * srelgot;
10308 bfd_vma addend;
10309 bfd_signed_vma signed_addend;
10310 unsigned char dynreloc_st_type;
10311 bfd_vma dynreloc_value;
ba96a88f 10312 struct elf32_arm_link_hash_table * globals;
34e77a92 10313 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10314 union gotplt_union *root_plt;
10315 struct arm_plt_info *arm_plt;
10316 bfd_vma plt_offset;
10317 bfd_vma gotplt_offset;
10318 bfd_boolean has_iplt_entry;
10319 bfd_boolean resolved_to_zero;
f21f3fe0 10320
9c504268 10321 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10322 if (globals == NULL)
10323 return bfd_reloc_notsupported;
9c504268 10324
0ffa91dd 10325 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10326 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10327
10328 /* Some relocation types map to different relocations depending on the
9c504268 10329 target. We pick the right one here. */
eb043451 10330 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10331
10332 /* It is possible to have linker relaxations on some TLS access
10333 models. Update our information here. */
10334 r_type = elf32_arm_tls_transition (info, r_type, h);
10335
eb043451
PB		 10336 if (r_type != howto->type)
10337 howto = elf32_arm_howto_from_type (r_type);
9c504268 10338
34e77a92 10339 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10340 sgot = globals->root.sgot;
252b5132 10341 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10342 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10343
34e77a92
RS		 10344 if (globals->root.dynamic_sections_created)
10345 srelgot = globals->root.srelgot;
10346 else
10347 srelgot = NULL;
10348
252b5132
RH		 10349 r_symndx = ELF32_R_SYM (rel->r_info);
10350
4e7fd91e 10351 if (globals->use_rel)
ba96a88f 10352 {
4e7fd91e
PB		 10353 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10354
10355 if (addend & ((howto->src_mask + 1) >> 1))
10356 {
10357 signed_addend = -1;
10358 signed_addend &= ~ howto->src_mask;
10359 signed_addend |= addend;
10360 }
10361 else
10362 signed_addend = addend;
ba96a88f
NC		 10363 }
10364 else
4e7fd91e 10365 addend = signed_addend = rel->r_addend;
f21f3fe0 10366
39f21624
NC		 10367 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10368 are resolving a function call relocation. */
10369 if (using_thumb_only (globals)
10370 && (r_type == R_ARM_THM_CALL
10371 || r_type == R_ARM_THM_JUMP24)
10372 && branch_type == ST_BRANCH_TO_ARM)
10373 branch_type = ST_BRANCH_TO_THUMB;
10374
34e77a92
RS		 10375 /* Record the symbol information that should be used in dynamic
10376 relocations. */
10377 dynreloc_st_type = st_type;
10378 dynreloc_value = value;
10379 if (branch_type == ST_BRANCH_TO_THUMB)
10380 dynreloc_value |= 1;
10381
10382 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10383 VALUE appropriately for relocations that we resolve at link time. */
10384 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10385 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10386 &arm_plt)
34e77a92
RS		 10387 && root_plt->offset != (bfd_vma) -1)
10388 {
10389 plt_offset = root_plt->offset;
10390 gotplt_offset = arm_plt->got_offset;
10391
10392 if (h == NULL || eh->is_iplt)
10393 {
10394 has_iplt_entry = TRUE;
10395 splt = globals->root.iplt;
10396
10397 /* Populate .iplt entries here, because not all of them will
10398 be seen by finish_dynamic_symbol. The lower bit is set if
10399 we have already populated the entry. */
10400 if (plt_offset & 1)
10401 plt_offset--;
10402 else
10403 {
57460bcf
NC		 10404 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10405 -1, dynreloc_value))
10406 root_plt->offset |= 1;
10407 else
10408 return bfd_reloc_notsupported;
34e77a92
RS		 10409 }
10410
10411 /* Static relocations always resolve to the .iplt entry. */
10412 st_type = STT_FUNC;
10413 value = (splt->output_section->vma
10414 + splt->output_offset
10415 + plt_offset);
10416 branch_type = ST_BRANCH_TO_ARM;
10417
10418 /* If there are non-call relocations that resolve to the .iplt
10419 entry, then all dynamic ones must too. */
10420 if (arm_plt->noncall_refcount != 0)
10421 {
10422 dynreloc_st_type = st_type;
10423 dynreloc_value = value;
10424 }
10425 }
10426 else
10427 /* We populate the .plt entry in finish_dynamic_symbol. */
10428 splt = globals->root.splt;
10429 }
10430 else
10431 {
10432 splt = NULL;
10433 plt_offset = (bfd_vma) -1;
10434 gotplt_offset = (bfd_vma) -1;
10435 }
10436
95b03e4a
L		 10437 resolved_to_zero = (h != NULL
10438 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10439
252b5132
RH		 10440 switch (r_type)
10441 {
10442 case R_ARM_NONE:
28a094c2
DJ		 10443 /* We don't need to find a value for this symbol. It's just a
10444 marker. */
10445 *unresolved_reloc_p = FALSE;
252b5132
RH		 10446 return bfd_reloc_ok;
10447
00a97672 10448 case R_ARM_ABS12:
90c14f0c 10449 if (globals->root.target_os != is_vxworks)
00a97672 10450 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10451 /* Fall through. */
00a97672 10452
252b5132
RH		 10453 case R_ARM_PC24:
10454 case R_ARM_ABS32:
bb224fc3 10455 case R_ARM_ABS32_NOI:
252b5132 10456 case R_ARM_REL32:
bb224fc3 10457 case R_ARM_REL32_NOI:
5b5bb741
PB		 10458 case R_ARM_CALL:
10459 case R_ARM_JUMP24:
dfc5f959 10460 case R_ARM_XPC25:
eb043451 10461 case R_ARM_PREL31:
7359ea65 10462 case R_ARM_PLT32:
7359ea65
DJ		 10463 /* Handle relocations which should use the PLT entry. ABS32/REL32
10464 will use the symbol's value, which may point to a PLT entry, but we
10465 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10466 branches in this object should go to it, except if the PLT is too
10467 far away, in which case a long branch stub should be inserted. */
bb224fc3 10468 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10469 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10470 && r_type != R_ARM_CALL
10471 && r_type != R_ARM_JUMP24
10472 && r_type != R_ARM_PLT32)
34e77a92 10473 && plt_offset != (bfd_vma) -1)
7359ea65 10474 {
34e77a92
RS		 10475 /* If we've created a .plt section, and assigned a PLT entry
10476 to this function, it must either be a STT_GNU_IFUNC reference
10477 or not be known to bind locally. In other cases, we should
10478 have cleared the PLT entry by now. */
10479 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10480
10481 value = (splt->output_section->vma
10482 + splt->output_offset
34e77a92 10483 + plt_offset);
0945cdfd 10484 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10485 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10486 contents, rel->r_offset, value,
00a97672 10487 rel->r_addend);
7359ea65
DJ		 10488 }
10489
67687978
PB		 10490 /* When generating a shared object or relocatable executable, these
10491 relocations are copied into the output file to be resolved at
10492 run time. */
0e1862bb 10493 if ((bfd_link_pic (info)
e8b09b87
CL		 10494 || globals->root.is_relocatable_executable
10495 || globals->fdpic_p)
7359ea65 10496 && (input_section->flags & SEC_ALLOC)
90c14f0c 10497 && !(globals->root.target_os == is_vxworks
3348747a
NS		 10498 && strcmp (input_section->output_section->name,
10499 ".tls_vars") == 0)
bb224fc3 10500 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10501 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10502 && !(input_bfd == globals->stub_bfd
10503 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10504 && (h == NULL
95b03e4a
L		 10505 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10506 && !resolved_to_zero)
7359ea65
DJ		 10507 || h->root.type != bfd_link_hash_undefweak)
10508 && r_type != R_ARM_PC24
5b5bb741
PB		 10509 && r_type != R_ARM_CALL
10510 && r_type != R_ARM_JUMP24
ee06dc07 10511 && r_type != R_ARM_PREL31
7359ea65 10512 && r_type != R_ARM_PLT32)
252b5132 10513 {
947216bf 10514 Elf_Internal_Rela outrel;
b34976b6 10515 bfd_boolean skip, relocate;
e8b09b87 10516 int isrofixup = 0;
f21f3fe0 10517
52db4ec2
JW		 10518 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10519 && !h->def_regular)
10520 {
10521 char *v = _("shared object");
10522
0e1862bb 10523 if (bfd_link_executable (info))
52db4ec2
JW		 10524 v = _("PIE executable");
10525
4eca0228 10526 _bfd_error_handler
871b3ab2 10527 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10528 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10529 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10530 return bfd_reloc_notsupported;
10531 }
10532
0945cdfd
DJ		 10533 *unresolved_reloc_p = FALSE;
10534
34e77a92 10535 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10536 {
83bac4b0
NC		 10537 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10538 ! globals->use_rel);
f21f3fe0 10539
83bac4b0 10540 if (sreloc == NULL)
252b5132 10541 return bfd_reloc_notsupported;
252b5132 10542 }
f21f3fe0 10543
b34976b6
AM		 10544 skip = FALSE;
10545 relocate = FALSE;
f21f3fe0 10546
00a97672 10547 outrel.r_addend = addend;
c629eae0
JJ		 10548 outrel.r_offset =
10549 _bfd_elf_section_offset (output_bfd, info, input_section,
10550 rel->r_offset);
10551 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10552 skip = TRUE;
0bb2d96a 10553 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10554 skip = TRUE, relocate = TRUE;
252b5132
RH		 10555 outrel.r_offset += (input_section->output_section->vma
10556 + input_section->output_offset);
f21f3fe0 10557
252b5132 10558 if (skip)
0bb2d96a 10559 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10560 else if (h != NULL
10561 && h->dynindx != -1
0e1862bb 10562 && (!bfd_link_pic (info)
1dcb9720
JW		 10563 || !(bfd_link_pie (info)
10564 || SYMBOLIC_BIND (info, h))
f5385ebf 10565 || !h->def_regular))
5e681ec4 10566 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10567 else
10568 {
a16385dc
MM		 10569 int symbol;
10570
5e681ec4 10571 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10572 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10573 || (globals->fdpic_p && !bfd_link_pic(info)));
90c14f0c 10574 if (globals->root.target_os == is_symbian)
6366ff1e 10575 {
74541ad4
AM		 10576 asection *osec;
10577
6366ff1e
MM		 10578 /* On Symbian OS, the data segment and text segement
10579 can be relocated independently. Therefore, we
10580 must indicate the segment to which this
10581 relocation is relative. The BPABI allows us to
10582 use any symbol in the right segment; we just use
10583 the section symbol as it is convenient. (We
10584 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10585 will not appear in the dynamic symbol table.)
10586
10587 Note that the dynamic linker ignores the section
10588 symbol value, so we don't subtract osec->vma
10589 from the emitted reloc addend. */
10dbd1f3 10590 if (sym_sec)
74541ad4 10591 osec = sym_sec->output_section;
10dbd1f3 10592 else
74541ad4
AM		 10593 osec = input_section->output_section;
10594 symbol = elf_section_data (osec)->dynindx;
10595 if (symbol == 0)
10596 {
10597 struct elf_link_hash_table *htab = elf_hash_table (info);
10598
10599 if ((osec->flags & SEC_READONLY) == 0
10600 && htab->data_index_section != NULL)
10601 osec = htab->data_index_section;
10602 else
10603 osec = htab->text_index_section;
10604 symbol = elf_section_data (osec)->dynindx;
10605 }
6366ff1e
MM		 10606 BFD_ASSERT (symbol != 0);
10607 }
a16385dc
MM		 10608 else
10609 /* On SVR4-ish systems, the dynamic loader cannot
10610 relocate the text and data segments independently,
10611 so the symbol does not matter. */
10612 symbol = 0;
34e77a92
RS		 10613 if (dynreloc_st_type == STT_GNU_IFUNC)
10614 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10615 to the .iplt entry. Instead, every non-call reference
10616 must use an R_ARM_IRELATIVE relocation to obtain the
10617 correct run-time address. */
10618 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10619 else if (globals->fdpic_p && !bfd_link_pic(info))
10620 isrofixup = 1;
34e77a92
RS		 10621 else
10622 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10623 if (globals->use_rel)
10624 relocate = TRUE;
10625 else
34e77a92 10626 outrel.r_addend += dynreloc_value;
252b5132 10627 }
f21f3fe0 10628
e8b09b87
CL		 10629 if (isrofixup)
10630 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10631 else
10632 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10633
f21f3fe0 10634 /* If this reloc is against an external symbol, we do not want to
252b5132 10635 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10636 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10637 if (! relocate)
10638 return bfd_reloc_ok;
9a5aca8c 10639
f21f3fe0 10640 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10641 contents, rel->r_offset,
10642 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10643 }
10644 else switch (r_type)
10645 {
00a97672
RS		 10646 case R_ARM_ABS12:
10647 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10648
dfc5f959 10649 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10650 case R_ARM_CALL:
10651 case R_ARM_JUMP24:
8029a119 10652 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10653 case R_ARM_PLT32:
906e58ca 10654 {
906e58ca
NC		 10655 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10656
dfc5f959 10657 if (r_type == R_ARM_XPC25)
252b5132 10658 {
dfc5f959
NC		 10659 /* Check for Arm calling Arm function. */
10660 /* FIXME: Should we translate the instruction into a BL
10661 instruction instead ? */
35fc36a8 10662 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10663 _bfd_error_handler
90b6238f
AM		 10664 (_("\%pB: warning: %s BLX instruction targets"
10665 " %s function '%s'"),
10666 input_bfd, "ARM",
10667 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10668 }
155d87d7 10669 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10670 {
10671 /* Check for Arm calling Thumb function. */
35fc36a8 10672 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10673 {
f2a9dd69
DJ		 10674 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10675 output_bfd, input_section,
10676 hit_data, sym_sec, rel->r_offset,
10677 signed_addend, value,
10678 error_message))
10679 return bfd_reloc_ok;
10680 else
10681 return bfd_reloc_dangerous;
dfc5f959 10682 }
252b5132 10683 }
ba96a88f 10684
906e58ca 10685 /* Check if a stub has to be inserted because the
8029a119 10686 destination is too far or we are changing mode. */
155d87d7
CL		 10687 if ( r_type == R_ARM_CALL
10688 || r_type == R_ARM_JUMP24
10689 || r_type == R_ARM_PLT32)
906e58ca 10690 {
fe33d2fa
CL		 10691 enum elf32_arm_stub_type stub_type = arm_stub_none;
10692 struct elf32_arm_link_hash_entry *hash;
10693
10694 hash = (struct elf32_arm_link_hash_entry *) h;
10695 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10696 st_type, &branch_type,
10697 hash, value, sym_sec,
fe33d2fa 10698 input_bfd, sym_name);
5fa9e92f 10699
fe33d2fa 10700 if (stub_type != arm_stub_none)
906e58ca
NC		 10701 {
10702 /* The target is out of reach, so redirect the
10703 branch to the local stub for this function. */
906e58ca
NC		 10704 stub_entry = elf32_arm_get_stub_entry (input_section,
10705 sym_sec, h,
fe33d2fa
CL		 10706 rel, globals,
10707 stub_type);
9cd3e4e5
NC		 10708 {
10709 if (stub_entry != NULL)
10710 value = (stub_entry->stub_offset
10711 + stub_entry->stub_sec->output_offset
10712 + stub_entry->stub_sec->output_section->vma);
10713
10714 if (plt_offset != (bfd_vma) -1)
10715 *unresolved_reloc_p = FALSE;
10716 }
906e58ca 10717 }
fe33d2fa
CL		 10718 else
10719 {
10720 /* If the call goes through a PLT entry, make sure to
10721 check distance to the right destination address. */
34e77a92 10722 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10723 {
10724 value = (splt->output_section->vma
10725 + splt->output_offset
34e77a92 10726 + plt_offset);
fe33d2fa
CL		 10727 *unresolved_reloc_p = FALSE;
10728 /* The PLT entry is in ARM mode, regardless of the
10729 target function. */
35fc36a8 10730 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10731 }
10732 }
906e58ca
NC		 10733 }
10734
dea514f5
PB		 10735 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10736 where:
10737 S is the address of the symbol in the relocation.
10738 P is address of the instruction being relocated.
10739 A is the addend (extracted from the instruction) in bytes.
10740
10741 S is held in 'value'.
10742 P is the base address of the section containing the
10743 instruction plus the offset of the reloc into that
10744 section, ie:
10745 (input_section->output_section->vma +
10746 input_section->output_offset +
10747 rel->r_offset).
10748 A is the addend, converted into bytes, ie:
10749 (signed_addend * 4)
10750
10751 Note: None of these operations have knowledge of the pipeline
10752 size of the processor, thus it is up to the assembler to
10753 encode this information into the addend. */
10754 value -= (input_section->output_section->vma
10755 + input_section->output_offset);
10756 value -= rel->r_offset;
4e7fd91e
PB		 10757 if (globals->use_rel)
10758 value += (signed_addend << howto->size);
10759 else
10760 /* RELA addends do not have to be adjusted by howto->size. */
10761 value += signed_addend;
23080146 10762
dcb5e6e6
NC		 10763 signed_addend = value;
10764 signed_addend >>= howto->rightshift;
9a5aca8c 10765
5ab79981 10766 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10767 the next instruction unless a PLT entry will be created.
77b4f08f 10768 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10769 The jump to the next instruction is optimized as a NOP depending
10770 on the architecture. */
ffcb4889 10771 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10772 && plt_offset == (bfd_vma) -1)
77b4f08f 10773 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10774 {
cd1dac3d
DG		 10775 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10776
10777 if (arch_has_arm_nop (globals))
10778 value |= 0x0320f000;
10779 else
10780 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10781 }
10782 else
59f2c4e7 10783 {
9b485d32 10784 /* Perform a signed range check. */
dcb5e6e6 10785 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10786 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10787 return bfd_reloc_overflow;
9a5aca8c 10788
5ab79981 10789 addend = (value & 2);
39b41c9c 10790
5ab79981
PB		 10791 value = (signed_addend & howto->dst_mask)
10792 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10793
5ab79981
PB		 10794 if (r_type == R_ARM_CALL)
10795 {
155d87d7 10796 /* Set the H bit in the BLX instruction. */
35fc36a8 10797 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10798 {
10799 if (addend)
10800 value |= (1 << 24);
10801 else
10802 value &= ~(bfd_vma)(1 << 24);
10803 }
10804
5ab79981 10805 /* Select the correct instruction (BL or BLX). */
906e58ca 10806 /* Only if we are not handling a BL to a stub. In this
8029a119 10807 case, mode switching is performed by the stub. */
35fc36a8 10808 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10809 value |= (1 << 28);
63e1a0fc 10810 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10811 {
10812 value &= ~(bfd_vma)(1 << 28);
10813 value |= (1 << 24);
10814 }
39b41c9c
PB		 10815 }
10816 }
906e58ca 10817 }
252b5132 10818 break;
f21f3fe0 10819
252b5132
RH		 10820 case R_ARM_ABS32:
10821 value += addend;
35fc36a8 10822 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10823 value |= 1;
10824 break;
f21f3fe0 10825
bb224fc3
MS		 10826 case R_ARM_ABS32_NOI:
10827 value += addend;
10828 break;
10829
252b5132 10830 case R_ARM_REL32:
a8bc6c78 10831 value += addend;
35fc36a8 10832 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10833 value |= 1;
252b5132 10834 value -= (input_section->output_section->vma
62efb346 10835 + input_section->output_offset + rel->r_offset);
252b5132 10836 break;
eb043451 10837
bb224fc3
MS		 10838 case R_ARM_REL32_NOI:
10839 value += addend;
10840 value -= (input_section->output_section->vma
10841 + input_section->output_offset + rel->r_offset);
10842 break;
10843
eb043451
PB		 10844 case R_ARM_PREL31:
10845 value -= (input_section->output_section->vma
10846 + input_section->output_offset + rel->r_offset);
10847 value += signed_addend;
10848 if (! h || h->root.type != bfd_link_hash_undefweak)
10849 {
8029a119 10850 /* Check for overflow. */
eb043451
PB		 10851 if ((value ^ (value >> 1)) & (1 << 30))
10852 return bfd_reloc_overflow;
10853 }
10854 value &= 0x7fffffff;
10855 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10856 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10857 value |= 1;
10858 break;
252b5132 10859 }
f21f3fe0 10860
252b5132
RH		 10861 bfd_put_32 (input_bfd, value, hit_data);
10862 return bfd_reloc_ok;
10863
10864 case R_ARM_ABS8:
fd0fd00c
MJ		 10865 /* PR 16202: Refectch the addend using the correct size. */
10866 if (globals->use_rel)
10867 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10868 value += addend;
4e67d4ca
DG		 10869
10870 /* There is no way to tell whether the user intended to use a signed or
10871 unsigned addend. When checking for overflow we accept either,
10872 as specified by the AAELF. */
10873 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10874 return bfd_reloc_overflow;
10875
10876 bfd_put_8 (input_bfd, value, hit_data);
10877 return bfd_reloc_ok;
10878
10879 case R_ARM_ABS16:
fd0fd00c
MJ		 10880 /* PR 16202: Refectch the addend using the correct size. */
10881 if (globals->use_rel)
10882 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10883 value += addend;
10884
4e67d4ca
DG		 10885 /* See comment for R_ARM_ABS8. */
10886 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10887 return bfd_reloc_overflow;
10888
10889 bfd_put_16 (input_bfd, value, hit_data);
10890 return bfd_reloc_ok;
10891
252b5132 10892 case R_ARM_THM_ABS5:
9b485d32 10893 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10894 if (globals->use_rel)
10895 {
10896 /* Need to refetch addend. */
10897 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10898 /* ??? Need to determine shift amount from operand size. */
10899 addend >>= howto->rightshift;
10900 }
252b5132
RH		 10901 value += addend;
10902
10903 /* ??? Isn't value unsigned? */
10904 if ((long) value > 0x1f || (long) value < -0x10)
10905 return bfd_reloc_overflow;
10906
10907 /* ??? Value needs to be properly shifted into place first. */
10908 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10909 bfd_put_16 (input_bfd, value, hit_data);
10910 return bfd_reloc_ok;
10911
2cab6cc3
MS		 10912 case R_ARM_THM_ALU_PREL_11_0:
10913 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10914 {
10915 bfd_vma insn;
10916 bfd_signed_vma relocation;
10917
10918 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10919 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10920
99059e56
RM		 10921 if (globals->use_rel)
10922 {
10923 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10924 | ((insn & (1 << 26)) >> 15);
10925 if (insn & 0xf00000)
10926 signed_addend = -signed_addend;
10927 }
2cab6cc3
MS		 10928
10929 relocation = value + signed_addend;
79f08007 10930 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10931 + input_section->output_offset
10932 + rel->r_offset);
2cab6cc3 10933
8c65b54f
CS		 10934 /* PR 21523: Use an absolute value. The user of this reloc will
10935 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10936 value = llabs (relocation);
2cab6cc3 10937
99059e56
RM		 10938 if (value >= 0x1000)
10939 return bfd_reloc_overflow;
2cab6cc3 10940
e645cf40
AG		 10941 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10942 if (branch_type == ST_BRANCH_TO_THUMB)
10943 value |= 1;
10944
2cab6cc3 10945 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10946 | ((value & 0x700) << 4)
10947 | ((value & 0x800) << 15);
10948 if (relocation < 0)
10949 insn |= 0xa00000;
2cab6cc3
MS		 10950
10951 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10952 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10953
99059e56 10954 return bfd_reloc_ok;
2cab6cc3
MS		 10955 }
10956
e1ec24c6
NC		 10957 case R_ARM_THM_PC8:
10958 /* PR 10073: This reloc is not generated by the GNU toolchain,
10959 but it is supported for compatibility with third party libraries
10960 generated by other compilers, specifically the ARM/IAR. */
10961 {
10962 bfd_vma insn;
10963 bfd_signed_vma relocation;
10964
10965 insn = bfd_get_16 (input_bfd, hit_data);
10966
99059e56 10967 if (globals->use_rel)
79f08007 10968 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10969
10970 relocation = value + addend;
79f08007 10971 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10972 + input_section->output_offset
10973 + rel->r_offset);
e1ec24c6 10974
b6518b38 10975 value = relocation;
e1ec24c6
NC		 10976
10977 /* We do not check for overflow of this reloc. Although strictly
10978 speaking this is incorrect, it appears to be necessary in order
10979 to work with IAR generated relocs. Since GCC and GAS do not
10980 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10981 a problem for them. */
10982 value &= 0x3fc;
10983
10984 insn = (insn & 0xff00) | (value >> 2);
10985
10986 bfd_put_16 (input_bfd, insn, hit_data);
10987
99059e56 10988 return bfd_reloc_ok;
e1ec24c6
NC		 10989 }
10990
2cab6cc3
MS		 10991 case R_ARM_THM_PC12:
10992 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10993 {
10994 bfd_vma insn;
10995 bfd_signed_vma relocation;
10996
10997 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10998 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10999
99059e56
RM		 11000 if (globals->use_rel)
11001 {
11002 signed_addend = insn & 0xfff;
11003 if (!(insn & (1 << 23)))
11004 signed_addend = -signed_addend;
11005 }
2cab6cc3
MS		 11006
11007 relocation = value + signed_addend;
79f08007 11008 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11009 + input_section->output_offset
11010 + rel->r_offset);
2cab6cc3 11011
b6518b38 11012 value = relocation;
2cab6cc3 11013
99059e56
RM		 11014 if (value >= 0x1000)
11015 return bfd_reloc_overflow;
2cab6cc3
MS		 11016
11017 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11018 if (relocation >= 0)
11019 insn |= (1 << 23);
2cab6cc3
MS		 11020
11021 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11022 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11023
99059e56 11024 return bfd_reloc_ok;
2cab6cc3
MS		 11025 }
11026
dfc5f959 11027 case R_ARM_THM_XPC22:
c19d1205 11028 case R_ARM_THM_CALL:
bd97cb95 11029 case R_ARM_THM_JUMP24:
dfc5f959 11030 /* Thumb BL (branch long instruction). */
252b5132 11031 {
b34976b6 11032 bfd_vma relocation;
99059e56 11033 bfd_vma reloc_sign;
b34976b6
AM		 11034 bfd_boolean overflow = FALSE;
11035 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11036 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11037 bfd_signed_vma reloc_signed_max;
11038 bfd_signed_vma reloc_signed_min;
b34976b6 11039 bfd_vma check;
252b5132 11040 bfd_signed_vma signed_check;
e95de063 11041 int bitsize;
cd1dac3d 11042 const int thumb2 = using_thumb2 (globals);
5e866f5a 11043 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11044
5ab79981 11045 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11046 the next instruction unless a PLT entry will be created.
11047 The jump to the next instruction is optimized as a NOP.W for
11048 Thumb-2 enabled architectures. */
19540007 11049 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11050 && plt_offset == (bfd_vma) -1)
5ab79981 11051 {
60a019a0 11052 if (thumb2)
cd1dac3d
DG		 11053 {
11054 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11055 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11056 }
11057 else
11058 {
11059 bfd_put_16 (input_bfd, 0xe000, hit_data);
11060 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11061 }
5ab79981
PB		 11062 return bfd_reloc_ok;
11063 }
11064
e95de063 11065 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11066 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11067 if (globals->use_rel)
11068 {
99059e56
RM		 11069 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11070 bfd_vma upper = upper_insn & 0x3ff;
11071 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11072 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11073 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11074 bfd_vma i1 = j1 ^ s ? 0 : 1;
11075 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11076
99059e56
RM		 11077 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11078 /* Sign extend. */
11079 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11080
4e7fd91e
PB		 11081 signed_addend = addend;
11082 }
cb1afa5c 11083
dfc5f959
NC		 11084 if (r_type == R_ARM_THM_XPC22)
11085 {
11086 /* Check for Thumb to Thumb call. */
11087 /* FIXME: Should we translate the instruction into a BL
11088 instruction instead ? */
35fc36a8 11089 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11090 _bfd_error_handler
90b6238f
AM		 11091 (_("%pB: warning: %s BLX instruction targets"
11092 " %s function '%s'"),
11093 input_bfd, "Thumb",
11094 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11095 }
11096 else
252b5132 11097 {
dfc5f959
NC		 11098 /* If it is not a call to Thumb, assume call to Arm.
11099 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11100 function call at all, but rather a long jump. Calls through
11101 the PLT do not require stubs. */
34e77a92 11102 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11103 {
bd97cb95 11104 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11105 {
11106 /* Convert BL to BLX. */
11107 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11108 }
155d87d7
CL		 11109 else if (( r_type != R_ARM_THM_CALL)
11110 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11111 {
11112 if (elf32_thumb_to_arm_stub
11113 (info, sym_name, input_bfd, output_bfd, input_section,
11114 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11115 error_message))
11116 return bfd_reloc_ok;
11117 else
11118 return bfd_reloc_dangerous;
11119 }
da5938a2 11120 }
35fc36a8
RS		 11121 else if (branch_type == ST_BRANCH_TO_THUMB
11122 && globals->use_blx
bd97cb95 11123 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11124 {
11125 /* Make sure this is a BL. */
11126 lower_insn |= 0x1800;
11127 }
252b5132 11128 }
f21f3fe0 11129
fe33d2fa 11130 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11131 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11132 {
11133 /* Check if a stub has to be inserted because the destination
8029a119 11134 is too far. */
fe33d2fa
CL		 11135 struct elf32_arm_stub_hash_entry *stub_entry;
11136 struct elf32_arm_link_hash_entry *hash;
11137
11138 hash = (struct elf32_arm_link_hash_entry *) h;
11139
11140 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11141 st_type, &branch_type,
11142 hash, value, sym_sec,
fe33d2fa
CL		 11143 input_bfd, sym_name);
11144
11145 if (stub_type != arm_stub_none)
906e58ca
NC		 11146 {
11147 /* The target is out of reach or we are changing modes, so
11148 redirect the branch to the local stub for this
11149 function. */
11150 stub_entry = elf32_arm_get_stub_entry (input_section,
11151 sym_sec, h,
fe33d2fa
CL		 11152 rel, globals,
11153 stub_type);
906e58ca 11154 if (stub_entry != NULL)
9cd3e4e5
NC		 11155 {
11156 value = (stub_entry->stub_offset
11157 + stub_entry->stub_sec->output_offset
11158 + stub_entry->stub_sec->output_section->vma);
11159
11160 if (plt_offset != (bfd_vma) -1)
11161 *unresolved_reloc_p = FALSE;
11162 }
906e58ca 11163
f4ac8484 11164 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11165 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11166 {
11167 if ((stub_entry
11168 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11169 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11170 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11171 }
906e58ca
NC		 11172 }
11173 }
11174
fe33d2fa 11175 /* Handle calls via the PLT. */
34e77a92 11176 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11177 {
11178 value = (splt->output_section->vma
11179 + splt->output_offset
34e77a92 11180 + plt_offset);
fe33d2fa 11181
eed94f8f
NC		 11182 if (globals->use_blx
11183 && r_type == R_ARM_THM_CALL
11184 && ! using_thumb_only (globals))
fe33d2fa
CL		 11185 {
11186 /* If the Thumb BLX instruction is available, convert
11187 the BL to a BLX instruction to call the ARM-mode
11188 PLT entry. */
11189 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11190 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11191 }
11192 else
11193 {
eed94f8f
NC		 11194 if (! using_thumb_only (globals))
11195 /* Target the Thumb stub before the ARM PLT entry. */
11196 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11197 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11198 }
11199 *unresolved_reloc_p = FALSE;
11200 }
11201
ba96a88f 11202 relocation = value + signed_addend;
f21f3fe0 11203
252b5132 11204 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11205 + input_section->output_offset
11206 + rel->r_offset);
9a5aca8c 11207
252b5132
RH		 11208 check = relocation >> howto->rightshift;
11209
11210 /* If this is a signed value, the rightshift just dropped
11211 leading 1 bits (assuming twos complement). */
11212 if ((bfd_signed_vma) relocation >= 0)
11213 signed_check = check;
11214 else
11215 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11216
e95de063
MS		 11217 /* Calculate the permissable maximum and minimum values for
11218 this relocation according to whether we're relocating for
11219 Thumb-2 or not. */
11220 bitsize = howto->bitsize;
5e866f5a 11221 if (!thumb2_bl)
e95de063 11222 bitsize -= 2;
f6ebfac0 11223 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11224 reloc_signed_min = ~reloc_signed_max;
11225
252b5132 11226 /* Assumes two's complement. */
ba96a88f 11227 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11228 overflow = TRUE;
252b5132 11229
bd97cb95 11230 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11231 /* For a BLX instruction, make sure that the relocation is rounded up
11232 to a word boundary. This follows the semantics of the instruction
11233 which specifies that bit 1 of the target address will come from bit
11234 1 of the base address. */
11235 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11236
e95de063
MS		 11237 /* Put RELOCATION back into the insn. Assumes two's complement.
11238 We use the Thumb-2 encoding, which is safe even if dealing with
11239 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11240 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11241 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11242 | ((relocation >> 12) & 0x3ff)
11243 | (reloc_sign << 10);
906e58ca 11244 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11245 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11246 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11247 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11248
252b5132
RH		 11249 /* Put the relocated value back in the object file: */
11250 bfd_put_16 (input_bfd, upper_insn, hit_data);
11251 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11252
11253 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11254 }
11255 break;
11256
c19d1205
ZW		 11257 case R_ARM_THM_JUMP19:
11258 /* Thumb32 conditional branch instruction. */
11259 {
11260 bfd_vma relocation;
11261 bfd_boolean overflow = FALSE;
11262 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11263 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11264 bfd_signed_vma reloc_signed_max = 0xffffe;
11265 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11266 bfd_signed_vma signed_check;
07d6d2b8 11267 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11268 struct elf32_arm_stub_hash_entry *stub_entry;
11269 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11270
11271 /* Need to refetch the addend, reconstruct the top three bits,
11272 and squish the two 11 bit pieces together. */
11273 if (globals->use_rel)
11274 {
11275 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11276 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11277 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11278 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11279 bfd_vma lower = (lower_insn & 0x07ff);
11280
a00a1f35
MS		 11281 upper |= J1 << 6;
11282 upper |= J2 << 7;
11283 upper |= (!S) << 8;
c19d1205
ZW		 11284 upper -= 0x0100; /* Sign extend. */
11285
11286 addend = (upper << 12) | (lower << 1);
11287 signed_addend = addend;
11288 }
11289
bd97cb95 11290 /* Handle calls via the PLT. */
34e77a92 11291 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11292 {
11293 value = (splt->output_section->vma
11294 + splt->output_offset
34e77a92 11295 + plt_offset);
bd97cb95
DJ		 11296 /* Target the Thumb stub before the ARM PLT entry. */
11297 value -= PLT_THUMB_STUB_SIZE;
11298 *unresolved_reloc_p = FALSE;
11299 }
11300
c5423981
TG		 11301 hash = (struct elf32_arm_link_hash_entry *)h;
11302
11303 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11304 st_type, &branch_type,
11305 hash, value, sym_sec,
11306 input_bfd, sym_name);
c5423981
TG		 11307 if (stub_type != arm_stub_none)
11308 {
11309 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11310 sym_sec, h,
11311 rel, globals,
11312 stub_type);
c5423981
TG		 11313 if (stub_entry != NULL)
11314 {
07d6d2b8
AM		 11315 value = (stub_entry->stub_offset
11316 + stub_entry->stub_sec->output_offset
11317 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11318 }
11319 }
c19d1205 11320
99059e56 11321 relocation = value + signed_addend;
c19d1205
ZW		 11322 relocation -= (input_section->output_section->vma
11323 + input_section->output_offset
11324 + rel->r_offset);
a00a1f35 11325 signed_check = (bfd_signed_vma) relocation;
c19d1205 11326
c19d1205
ZW		 11327 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11328 overflow = TRUE;
11329
11330 /* Put RELOCATION back into the insn. */
11331 {
11332 bfd_vma S = (relocation & 0x00100000) >> 20;
11333 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11334 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11335 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11336 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11337
a00a1f35 11338 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11339 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11340 }
11341
11342 /* Put the relocated value back in the object file: */
11343 bfd_put_16 (input_bfd, upper_insn, hit_data);
11344 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11345
11346 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11347 }
11348
11349 case R_ARM_THM_JUMP11:
11350 case R_ARM_THM_JUMP8:
11351 case R_ARM_THM_JUMP6:
51c5503b
NC		 11352 /* Thumb B (branch) instruction). */
11353 {
6cf9e9fe 11354 bfd_signed_vma relocation;
51c5503b
NC		 11355 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11356 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11357 bfd_signed_vma signed_check;
11358
c19d1205
ZW		 11359 /* CZB cannot jump backward. */
11360 if (r_type == R_ARM_THM_JUMP6)
11361 reloc_signed_min = 0;
11362
4e7fd91e 11363 if (globals->use_rel)
6cf9e9fe 11364 {
4e7fd91e
PB		 11365 /* Need to refetch addend. */
11366 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11367 if (addend & ((howto->src_mask + 1) >> 1))
11368 {
11369 signed_addend = -1;
11370 signed_addend &= ~ howto->src_mask;
11371 signed_addend |= addend;
11372 }
11373 else
11374 signed_addend = addend;
11375 /* The value in the insn has been right shifted. We need to
11376 undo this, so that we can perform the address calculation
11377 in terms of bytes. */
11378 signed_addend <<= howto->rightshift;
6cf9e9fe 11379 }
6cf9e9fe 11380 relocation = value + signed_addend;
51c5503b
NC		 11381
11382 relocation -= (input_section->output_section->vma
11383 + input_section->output_offset
11384 + rel->r_offset);
11385
6cf9e9fe
NC		 11386 relocation >>= howto->rightshift;
11387 signed_check = relocation;
c19d1205
ZW		 11388
11389 if (r_type == R_ARM_THM_JUMP6)
11390 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11391 else
11392 relocation &= howto->dst_mask;
51c5503b 11393 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11394
51c5503b
NC		 11395 bfd_put_16 (input_bfd, relocation, hit_data);
11396
11397 /* Assumes two's complement. */
11398 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11399 return bfd_reloc_overflow;
11400
11401 return bfd_reloc_ok;
11402 }
cedb70c5 11403
8375c36b
PB		 11404 case R_ARM_ALU_PCREL7_0:
11405 case R_ARM_ALU_PCREL15_8:
11406 case R_ARM_ALU_PCREL23_15:
11407 {
11408 bfd_vma insn;
11409 bfd_vma relocation;
11410
11411 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11412 if (globals->use_rel)
11413 {
11414 /* Extract the addend. */
11415 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11416 signed_addend = addend;
11417 }
8375c36b
PB		 11418 relocation = value + signed_addend;
11419
11420 relocation -= (input_section->output_section->vma
11421 + input_section->output_offset
11422 + rel->r_offset);
11423 insn = (insn & ~0xfff)
11424 | ((howto->bitpos << 7) & 0xf00)
11425 | ((relocation >> howto->bitpos) & 0xff);
11426 bfd_put_32 (input_bfd, value, hit_data);
11427 }
11428 return bfd_reloc_ok;
11429
252b5132
RH		 11430 case R_ARM_GNU_VTINHERIT:
11431 case R_ARM_GNU_VTENTRY:
11432 return bfd_reloc_ok;
11433
c19d1205 11434 case R_ARM_GOTOFF32:
252b5132 11435 /* Relocation is relative to the start of the
99059e56 11436 global offset table. */
252b5132
RH		 11437
11438 BFD_ASSERT (sgot != NULL);
11439 if (sgot == NULL)
99059e56 11440 return bfd_reloc_notsupported;
9a5aca8c 11441
cedb70c5 11442 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11443 address by one, so that attempts to call the function pointer will
11444 correctly interpret it as Thumb code. */
35fc36a8 11445 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11446 value += 1;
11447
252b5132 11448 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11449 calculation. We always want the start of .got. If we
11450 define _GLOBAL_OFFSET_TABLE in a different way, as is
11451 permitted by the ABI, we might have to change this
11452 calculation. */
252b5132 11453 value -= sgot->output_section->vma;
f21f3fe0 11454 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11455 contents, rel->r_offset, value,
00a97672 11456 rel->r_addend);
252b5132
RH		 11457
11458 case R_ARM_GOTPC:
a7c10850 11459 /* Use global offset table as symbol value. */
252b5132 11460 BFD_ASSERT (sgot != NULL);
f21f3fe0 11461
252b5132 11462 if (sgot == NULL)
99059e56 11463 return bfd_reloc_notsupported;
252b5132 11464
0945cdfd 11465 *unresolved_reloc_p = FALSE;
252b5132 11466 value = sgot->output_section->vma;
f21f3fe0 11467 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11468 contents, rel->r_offset, value,
00a97672 11469 rel->r_addend);
f21f3fe0 11470
252b5132 11471 case R_ARM_GOT32:
eb043451 11472 case R_ARM_GOT_PREL:
252b5132 11473 /* Relocation is to the entry for this symbol in the
99059e56 11474 global offset table. */
252b5132
RH		 11475 if (sgot == NULL)
11476 return bfd_reloc_notsupported;
f21f3fe0 11477
34e77a92
RS		 11478 if (dynreloc_st_type == STT_GNU_IFUNC
11479 && plt_offset != (bfd_vma) -1
11480 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11481 {
11482 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11483 symbol, and the relocation resolves directly to the runtime
11484 target rather than to the .iplt entry. This means that any
11485 .got entry would be the same value as the .igot.plt entry,
11486 so there's no point creating both. */
11487 sgot = globals->root.igotplt;
11488 value = sgot->output_offset + gotplt_offset;
11489 }
11490 else if (h != NULL)
252b5132
RH		 11491 {
11492 bfd_vma off;
f21f3fe0 11493
252b5132
RH		 11494 off = h->got.offset;
11495 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11496 if ((off & 1) != 0)
252b5132 11497 {
b436d854
RS		 11498 /* We have already processsed one GOT relocation against
11499 this symbol. */
11500 off &= ~1;
11501 if (globals->root.dynamic_sections_created
11502 && !SYMBOL_REFERENCES_LOCAL (info, h))
11503 *unresolved_reloc_p = FALSE;
11504 }
11505 else
11506 {
11507 Elf_Internal_Rela outrel;
e8b09b87 11508 int isrofixup = 0;
b436d854 11509
e8b09b87
CL		 11510 if (((h->dynindx != -1) || globals->fdpic_p)
11511 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11512 {
11513 /* If the symbol doesn't resolve locally in a static
11514 object, we have an undefined reference. If the
11515 symbol doesn't resolve locally in a dynamic object,
11516 it should be resolved by the dynamic linker. */
11517 if (globals->root.dynamic_sections_created)
11518 {
11519 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11520 *unresolved_reloc_p = FALSE;
11521 }
11522 else
11523 outrel.r_info = 0;
11524 outrel.r_addend = 0;
11525 }
252b5132
RH		 11526 else
11527 {
34e77a92 11528 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11529 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c 11530 else if (bfd_link_pic (info)
7f026732 11531 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
99059e56
RM		 11532 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11533 else
2376f038
EB		 11534 {
11535 outrel.r_info = 0;
11536 if (globals->fdpic_p)
11537 isrofixup = 1;
11538 }
34e77a92 11539 outrel.r_addend = dynreloc_value;
b436d854 11540 }
ee29b9fb 11541
b436d854
RS		 11542 /* The GOT entry is initialized to zero by default.
11543 See if we should install a different value. */
11544 if (outrel.r_addend != 0
2376f038 11545 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11546 {
11547 bfd_put_32 (output_bfd, outrel.r_addend,
11548 sgot->contents + off);
11549 outrel.r_addend = 0;
252b5132 11550 }
f21f3fe0 11551
2376f038
EB		 11552 if (isrofixup)
11553 arm_elf_add_rofixup (output_bfd,
11554 elf32_arm_hash_table(info)->srofixup,
11555 sgot->output_section->vma
11556 + sgot->output_offset + off);
11557
11558 else if (outrel.r_info != 0)
b436d854
RS		 11559 {
11560 outrel.r_offset = (sgot->output_section->vma
11561 + sgot->output_offset
11562 + off);
11563 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11564 }
2376f038 11565
b436d854
RS		 11566 h->got.offset |= 1;
11567 }
252b5132
RH		 11568 value = sgot->output_offset + off;
11569 }
11570 else
11571 {
11572 bfd_vma off;
f21f3fe0 11573
5025eb7c
AO		 11574 BFD_ASSERT (local_got_offsets != NULL
11575 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11576
252b5132 11577 off = local_got_offsets[r_symndx];
f21f3fe0 11578
252b5132
RH		 11579 /* The offset must always be a multiple of 4. We use the
11580 least significant bit to record whether we have already
9b485d32 11581 generated the necessary reloc. */
252b5132
RH		 11582 if ((off & 1) != 0)
11583 off &= ~1;
11584 else
11585 {
2376f038
EB		 11586 Elf_Internal_Rela outrel;
11587 int isrofixup = 0;
f21f3fe0 11588
2376f038
EB		 11589 if (dynreloc_st_type == STT_GNU_IFUNC)
11590 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11591 else if (bfd_link_pic (info))
11592 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11593 else
252b5132 11594 {
2376f038
EB		 11595 outrel.r_info = 0;
11596 if (globals->fdpic_p)
11597 isrofixup = 1;
11598 }
11599
11600 /* The GOT entry is initialized to zero by default.
11601 See if we should install a different value. */
11602 if (globals->use_rel || outrel.r_info == 0)
11603 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11604
11605 if (isrofixup)
11606 arm_elf_add_rofixup (output_bfd,
11607 globals->srofixup,
11608 sgot->output_section->vma
11609 + sgot->output_offset + off);
f21f3fe0 11610
2376f038
EB		 11611 else if (outrel.r_info != 0)
11612 {
34e77a92 11613 outrel.r_addend = addend + dynreloc_value;
252b5132 11614 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11615 + sgot->output_offset
252b5132 11616 + off);
47beaa6a 11617 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11618 }
f21f3fe0 11619
252b5132
RH		 11620 local_got_offsets[r_symndx] |= 1;
11621 }
f21f3fe0 11622
252b5132
RH		 11623 value = sgot->output_offset + off;
11624 }
eb043451
PB		 11625 if (r_type != R_ARM_GOT32)
11626 value += sgot->output_section->vma;
9a5aca8c 11627
f21f3fe0 11628 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11629 contents, rel->r_offset, value,
00a97672 11630 rel->r_addend);
f21f3fe0 11631
ba93b8ac
DJ		 11632 case R_ARM_TLS_LDO32:
11633 value = value - dtpoff_base (info);
11634
11635 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11636 contents, rel->r_offset, value,
11637 rel->r_addend);
ba93b8ac
DJ		 11638
11639 case R_ARM_TLS_LDM32:
5c5a4843 11640 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11641 {
11642 bfd_vma off;
11643
362d30a1 11644 if (sgot == NULL)
ba93b8ac
DJ		 11645 abort ();
11646
11647 off = globals->tls_ldm_got.offset;
11648
11649 if ((off & 1) != 0)
11650 off &= ~1;
11651 else
11652 {
11653 /* If we don't know the module number, create a relocation
11654 for it. */
9cb09e33 11655 if (bfd_link_dll (info))
ba93b8ac
DJ		 11656 {
11657 Elf_Internal_Rela outrel;
ba93b8ac 11658
362d30a1 11659 if (srelgot == NULL)
ba93b8ac
DJ		 11660 abort ();
11661
00a97672 11662 outrel.r_addend = 0;
362d30a1
RS		 11663 outrel.r_offset = (sgot->output_section->vma
11664 + sgot->output_offset + off);
ba93b8ac
DJ		 11665 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11666
00a97672
RS		 11667 if (globals->use_rel)
11668 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11669 sgot->contents + off);
ba93b8ac 11670
47beaa6a 11671 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11672 }
11673 else
362d30a1 11674 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11675
11676 globals->tls_ldm_got.offset |= 1;
11677 }
11678
5c5a4843 11679 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11680 {
11681 bfd_put_32(output_bfd,
11682 globals->root.sgot->output_offset + off,
11683 contents + rel->r_offset);
11684
11685 return bfd_reloc_ok;
11686 }
11687 else
11688 {
11689 value = sgot->output_section->vma + sgot->output_offset + off
11690 - (input_section->output_section->vma
11691 + input_section->output_offset + rel->r_offset);
ba93b8ac 11692
e8b09b87
CL		 11693 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11694 contents, rel->r_offset, value,
11695 rel->r_addend);
11696 }
ba93b8ac
DJ		 11697 }
11698
0855e32b
NS		 11699 case R_ARM_TLS_CALL:
11700 case R_ARM_THM_TLS_CALL:
ba93b8ac 11701 case R_ARM_TLS_GD32:
5c5a4843 11702 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11703 case R_ARM_TLS_IE32:
5c5a4843 11704 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11705 case R_ARM_TLS_GOTDESC:
11706 case R_ARM_TLS_DESCSEQ:
11707 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11708 {
0855e32b
NS		 11709 bfd_vma off, offplt;
11710 int indx = 0;
ba93b8ac
DJ		 11711 char tls_type;
11712
0855e32b 11713 BFD_ASSERT (sgot != NULL);
ba93b8ac 11714
ba93b8ac
DJ		 11715 if (h != NULL)
11716 {
11717 bfd_boolean dyn;
11718 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11719 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11720 bfd_link_pic (info),
11721 h)
11722 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11723 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11724 {
11725 *unresolved_reloc_p = FALSE;
11726 indx = h->dynindx;
11727 }
11728 off = h->got.offset;
0855e32b 11729 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11730 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11731 }
11732 else
11733 {
0855e32b 11734 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11735 off = local_got_offsets[r_symndx];
0855e32b 11736 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11737 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11738 }
11739
0855e32b 11740 /* Linker relaxations happens from one of the
b38cadfb 11741 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11742 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11743 tls_type = GOT_TLS_IE;
0855e32b
NS		 11744
11745 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11746
11747 if ((off & 1) != 0)
11748 off &= ~1;
11749 else
11750 {
11751 bfd_boolean need_relocs = FALSE;
11752 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11753 int cur_off = off;
11754
11755 /* The GOT entries have not been initialized yet. Do it
11756 now, and emit any relocations. If both an IE GOT and a
11757 GD GOT are necessary, we emit the GD first. */
11758
9cb09e33 11759 if ((bfd_link_dll (info) || indx != 0)
ba93b8ac 11760 && (h == NULL
95b03e4a
L		 11761 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11762 && !resolved_to_zero)
ba93b8ac
DJ		 11763 || h->root.type != bfd_link_hash_undefweak))
11764 {
11765 need_relocs = TRUE;
0855e32b 11766 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11767 }
11768
0855e32b
NS		 11769 if (tls_type & GOT_TLS_GDESC)
11770 {
47beaa6a
RS		 11771 bfd_byte *loc;
11772
0855e32b
NS		 11773 /* We should have relaxed, unless this is an undefined
11774 weak symbol. */
11775 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
9cb09e33 11776 || bfd_link_dll (info));
0855e32b 11777 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11778 <= globals->root.sgotplt->size);
0855e32b
NS		 11779
11780 outrel.r_addend = 0;
11781 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11782 + globals->root.sgotplt->output_offset
11783 + offplt
11784 + globals->sgotplt_jump_table_size);
b38cadfb 11785
0855e32b
NS		 11786 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11787 sreloc = globals->root.srelplt;
11788 loc = sreloc->contents;
11789 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11790 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11791 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11792
11793 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11794
11795 /* For globals, the first word in the relocation gets
11796 the relocation index and the top bit set, or zero,
11797 if we're binding now. For locals, it gets the
11798 symbol's offset in the tls section. */
99059e56 11799 bfd_put_32 (output_bfd,
0855e32b
NS		 11800 !h ? value - elf_hash_table (info)->tls_sec->vma
11801 : info->flags & DF_BIND_NOW ? 0
11802 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11803 globals->root.sgotplt->contents + offplt
11804 + globals->sgotplt_jump_table_size);
11805
0855e32b 11806 /* Second word in the relocation is always zero. */
99059e56 11807 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11808 globals->root.sgotplt->contents + offplt
11809 + globals->sgotplt_jump_table_size + 4);
0855e32b 11810 }
ba93b8ac
DJ		 11811 if (tls_type & GOT_TLS_GD)
11812 {
11813 if (need_relocs)
11814 {
00a97672 11815 outrel.r_addend = 0;
362d30a1
RS		 11816 outrel.r_offset = (sgot->output_section->vma
11817 + sgot->output_offset
00a97672 11818 + cur_off);
ba93b8ac 11819 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11820
00a97672
RS		 11821 if (globals->use_rel)
11822 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11823 sgot->contents + cur_off);
00a97672 11824
47beaa6a 11825 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11826
11827 if (indx == 0)
11828 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11829 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11830 else
11831 {
00a97672 11832 outrel.r_addend = 0;
ba93b8ac
DJ		 11833 outrel.r_info = ELF32_R_INFO (indx,
11834 R_ARM_TLS_DTPOFF32);
11835 outrel.r_offset += 4;
00a97672
RS		 11836
11837 if (globals->use_rel)
11838 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11839 sgot->contents + cur_off + 4);
00a97672 11840
47beaa6a
RS		 11841 elf32_arm_add_dynreloc (output_bfd, info,
11842 srelgot, &outrel);
ba93b8ac
DJ		 11843 }
11844 }
11845 else
11846 {
11847 /* If we are not emitting relocations for a
11848 general dynamic reference, then we must be in a
11849 static link or an executable link with the
11850 symbol binding locally. Mark it as belonging
11851 to module 1, the executable. */
11852 bfd_put_32 (output_bfd, 1,
362d30a1 11853 sgot->contents + cur_off);
ba93b8ac 11854 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11855 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11856 }
11857
11858 cur_off += 8;
11859 }
11860
11861 if (tls_type & GOT_TLS_IE)
11862 {
11863 if (need_relocs)
11864 {
00a97672
RS		 11865 if (indx == 0)
11866 outrel.r_addend = value - dtpoff_base (info);
11867 else
11868 outrel.r_addend = 0;
362d30a1
RS		 11869 outrel.r_offset = (sgot->output_section->vma
11870 + sgot->output_offset
ba93b8ac
DJ		 11871 + cur_off);
11872 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11873
00a97672
RS		 11874 if (globals->use_rel)
11875 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11876 sgot->contents + cur_off);
ba93b8ac 11877
47beaa6a 11878 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11879 }
11880 else
11881 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11882 sgot->contents + cur_off);
ba93b8ac
DJ		 11883 cur_off += 4;
11884 }
11885
11886 if (h != NULL)
11887 h->got.offset |= 1;
11888 else
11889 local_got_offsets[r_symndx] |= 1;
11890 }
11891
5c5a4843 11892 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11893 off += 8;
0855e32b
NS		 11894 else if (tls_type & GOT_TLS_GDESC)
11895 off = offplt;
11896
11897 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11898 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11899 {
11900 bfd_signed_vma offset;
12352d3f
PB		 11901 /* TLS stubs are arm mode. The original symbol is a
11902 data object, so branch_type is bogus. */
11903 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11904 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11905 = arm_type_of_stub (info, input_section, rel,
11906 st_type, &branch_type,
0855e32b
NS		 11907 (struct elf32_arm_link_hash_entry *)h,
11908 globals->tls_trampoline, globals->root.splt,
11909 input_bfd, sym_name);
11910
11911 if (stub_type != arm_stub_none)
11912 {
11913 struct elf32_arm_stub_hash_entry *stub_entry
11914 = elf32_arm_get_stub_entry
11915 (input_section, globals->root.splt, 0, rel,
11916 globals, stub_type);
11917 offset = (stub_entry->stub_offset
11918 + stub_entry->stub_sec->output_offset
11919 + stub_entry->stub_sec->output_section->vma);
11920 }
11921 else
11922 offset = (globals->root.splt->output_section->vma
11923 + globals->root.splt->output_offset
11924 + globals->tls_trampoline);
11925
11926 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11927 {
11928 unsigned long inst;
b38cadfb
NC		 11929
11930 offset -= (input_section->output_section->vma
11931 + input_section->output_offset
11932 + rel->r_offset + 8);
0855e32b
NS		 11933
11934 inst = offset >> 2;
11935 inst &= 0x00ffffff;
11936 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11937 }
11938 else
11939 {
11940 /* Thumb blx encodes the offset in a complicated
11941 fashion. */
11942 unsigned upper_insn, lower_insn;
11943 unsigned neg;
11944
b38cadfb
NC		 11945 offset -= (input_section->output_section->vma
11946 + input_section->output_offset
0855e32b 11947 + rel->r_offset + 4);
b38cadfb 11948
12352d3f
PB		 11949 if (stub_type != arm_stub_none
11950 && arm_stub_is_thumb (stub_type))
11951 {
11952 lower_insn = 0xd000;
11953 }
11954 else
11955 {
11956 lower_insn = 0xc000;
6a631e86 11957 /* Round up the offset to a word boundary. */
12352d3f
PB		 11958 offset = (offset + 2) & ~2;
11959 }
11960
0855e32b
NS		 11961 neg = offset < 0;
11962 upper_insn = (0xf000
11963 | ((offset >> 12) & 0x3ff)
11964 | (neg << 10));
12352d3f 11965 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11966 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11967 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11968 bfd_put_16 (input_bfd, upper_insn, hit_data);
11969 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11970 return bfd_reloc_ok;
11971 }
11972 }
11973 /* These relocations needs special care, as besides the fact
11974 they point somewhere in .gotplt, the addend must be
11975 adjusted accordingly depending on the type of instruction
6a631e86 11976 we refer to. */
0855e32b
NS		 11977 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11978 {
11979 unsigned long data, insn;
11980 unsigned thumb;
b38cadfb 11981
b627f562 11982 data = bfd_get_signed_32 (input_bfd, hit_data);
0855e32b 11983 thumb = data & 1;
b627f562 11984 data &= ~1ul;
b38cadfb 11985
0855e32b
NS		 11986 if (thumb)
11987 {
11988 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11989 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11990 insn = (insn << 16)
11991 | bfd_get_16 (input_bfd,
11992 contents + rel->r_offset - data + 2);
11993 if ((insn & 0xf800c000) == 0xf000c000)
11994 /* bl/blx */
11995 value = -6;
11996 else if ((insn & 0xffffff00) == 0x4400)
11997 /* add */
11998 value = -5;
11999 else
12000 {
4eca0228 12001 _bfd_error_handler
695344c0 12002 /* xgettext:c-format */
2dcf00ce 12003 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12004 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12005 "referenced by TLS_GOTDESC"),
12006 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12007 "Thumb", insn);
0855e32b
NS		 12008 return bfd_reloc_notsupported;
12009 }
12010 }
12011 else
12012 {
12013 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12014
12015 switch (insn >> 24)
12016 {
12017 case 0xeb: /* bl */
12018 case 0xfa: /* blx */
12019 value = -4;
12020 break;
12021
12022 case 0xe0: /* add */
12023 value = -8;
12024 break;
b38cadfb 12025
0855e32b 12026 default:
4eca0228 12027 _bfd_error_handler
695344c0 12028 /* xgettext:c-format */
2dcf00ce 12029 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12030 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12031 "referenced by TLS_GOTDESC"),
12032 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12033 "ARM", insn);
0855e32b
NS		 12034 return bfd_reloc_notsupported;
12035 }
12036 }
b38cadfb 12037
0855e32b
NS		 12038 value += ((globals->root.sgotplt->output_section->vma
12039 + globals->root.sgotplt->output_offset + off)
12040 - (input_section->output_section->vma
12041 + input_section->output_offset
12042 + rel->r_offset)
12043 + globals->sgotplt_jump_table_size);
12044 }
12045 else
12046 value = ((globals->root.sgot->output_section->vma
12047 + globals->root.sgot->output_offset + off)
12048 - (input_section->output_section->vma
12049 + input_section->output_offset + rel->r_offset));
ba93b8ac 12050
5c5a4843
CL		 12051 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12052 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12053 {
12054 /* For FDPIC relocations, resolve to the offset of the GOT
12055 entry from the start of GOT. */
12056 bfd_put_32(output_bfd,
12057 globals->root.sgot->output_offset + off,
12058 contents + rel->r_offset);
12059
12060 return bfd_reloc_ok;
12061 }
12062 else
12063 {
12064 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12065 contents, rel->r_offset, value,
12066 rel->r_addend);
12067 }
ba93b8ac
DJ		 12068 }
12069
12070 case R_ARM_TLS_LE32:
3cbc1e5e 12071 if (bfd_link_dll (info))
ba93b8ac 12072 {
4eca0228 12073 _bfd_error_handler
695344c0 12074 /* xgettext:c-format */
2dcf00ce
AM		 12075 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12076 "in shared object"),
12077 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12078 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12079 }
12080 else
12081 value = tpoff (info, value);
906e58ca 12082
ba93b8ac 12083 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12084 contents, rel->r_offset, value,
12085 rel->r_addend);
ba93b8ac 12086
319850b4
JB		 12087 case R_ARM_V4BX:
12088 if (globals->fix_v4bx)
845b51d6
PB		 12089 {
12090 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12091
845b51d6
PB		 12092 /* Ensure that we have a BX instruction. */
12093 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12094
845b51d6
PB		 12095 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12096 {
12097 /* Branch to veneer. */
12098 bfd_vma glue_addr;
12099 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12100 glue_addr -= input_section->output_section->vma
12101 + input_section->output_offset
12102 + rel->r_offset + 8;
12103 insn = (insn & 0xf0000000) | 0x0a000000
12104 | ((glue_addr >> 2) & 0x00ffffff);
12105 }
12106 else
12107 {
12108 /* Preserve Rm (lowest four bits) and the condition code
12109 (highest four bits). Other bits encode MOV PC,Rm. */
12110 insn = (insn & 0xf000000f) | 0x01a0f000;
12111 }
319850b4 12112
845b51d6
PB		 12113 bfd_put_32 (input_bfd, insn, hit_data);
12114 }
319850b4
JB		 12115 return bfd_reloc_ok;
12116
b6895b4f
PB		 12117 case R_ARM_MOVW_ABS_NC:
12118 case R_ARM_MOVT_ABS:
12119 case R_ARM_MOVW_PREL_NC:
12120 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12121 /* Until we properly support segment-base-relative addressing then
12122 we assume the segment base to be zero, as for the group relocations.
12123 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12124 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12125 case R_ARM_MOVW_BREL_NC:
12126 case R_ARM_MOVW_BREL:
12127 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12128 {
12129 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12130
12131 if (globals->use_rel)
12132 {
12133 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12134 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12135 }
92f5d02b 12136
b6895b4f 12137 value += signed_addend;
b6895b4f
PB		 12138
12139 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12140 value -= (input_section->output_section->vma
12141 + input_section->output_offset + rel->r_offset);
12142
92f5d02b 12143 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12144 return bfd_reloc_overflow;
92f5d02b 12145
35fc36a8 12146 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12147 value |= 1;
12148
12149 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12150 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12151 value >>= 16;
12152
12153 insn &= 0xfff0f000;
12154 insn |= value & 0xfff;
12155 insn |= (value & 0xf000) << 4;
12156 bfd_put_32 (input_bfd, insn, hit_data);
12157 }
12158 return bfd_reloc_ok;
12159
12160 case R_ARM_THM_MOVW_ABS_NC:
12161 case R_ARM_THM_MOVT_ABS:
12162 case R_ARM_THM_MOVW_PREL_NC:
12163 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12164 /* Until we properly support segment-base-relative addressing then
12165 we assume the segment base to be zero, as for the above relocations.
12166 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12167 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12168 as R_ARM_THM_MOVT_ABS. */
12169 case R_ARM_THM_MOVW_BREL_NC:
12170 case R_ARM_THM_MOVW_BREL:
12171 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12172 {
12173 bfd_vma insn;
906e58ca 12174
b6895b4f
PB		 12175 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12176 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12177
12178 if (globals->use_rel)
12179 {
12180 addend = ((insn >> 4) & 0xf000)
12181 | ((insn >> 15) & 0x0800)
12182 | ((insn >> 4) & 0x0700)
07d6d2b8 12183 | (insn & 0x00ff);
39623e12 12184 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12185 }
92f5d02b 12186
b6895b4f 12187 value += signed_addend;
b6895b4f
PB		 12188
12189 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12190 value -= (input_section->output_section->vma
12191 + input_section->output_offset + rel->r_offset);
12192
92f5d02b 12193 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12194 return bfd_reloc_overflow;
92f5d02b 12195
35fc36a8 12196 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12197 value |= 1;
12198
12199 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12200 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12201 value >>= 16;
12202
12203 insn &= 0xfbf08f00;
12204 insn |= (value & 0xf000) << 4;
12205 insn |= (value & 0x0800) << 15;
12206 insn |= (value & 0x0700) << 4;
12207 insn |= (value & 0x00ff);
12208
12209 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12210 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12211 }
12212 return bfd_reloc_ok;
12213
4962c51a
MS		 12214 case R_ARM_ALU_PC_G0_NC:
12215 case R_ARM_ALU_PC_G1_NC:
12216 case R_ARM_ALU_PC_G0:
12217 case R_ARM_ALU_PC_G1:
12218 case R_ARM_ALU_PC_G2:
12219 case R_ARM_ALU_SB_G0_NC:
12220 case R_ARM_ALU_SB_G1_NC:
12221 case R_ARM_ALU_SB_G0:
12222 case R_ARM_ALU_SB_G1:
12223 case R_ARM_ALU_SB_G2:
12224 {
12225 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12226 bfd_vma pc = input_section->output_section->vma
4962c51a 12227 + input_section->output_offset + rel->r_offset;
31a91d61 12228 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12229 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12230 bfd_vma residual;
12231 bfd_vma g_n;
4962c51a 12232 bfd_signed_vma signed_value;
99059e56
RM		 12233 int group = 0;
12234
12235 /* Determine which group of bits to select. */
12236 switch (r_type)
12237 {
12238 case R_ARM_ALU_PC_G0_NC:
12239 case R_ARM_ALU_PC_G0:
12240 case R_ARM_ALU_SB_G0_NC:
12241 case R_ARM_ALU_SB_G0:
12242 group = 0;
12243 break;
12244
12245 case R_ARM_ALU_PC_G1_NC:
12246 case R_ARM_ALU_PC_G1:
12247 case R_ARM_ALU_SB_G1_NC:
12248 case R_ARM_ALU_SB_G1:
12249 group = 1;
12250 break;
12251
12252 case R_ARM_ALU_PC_G2:
12253 case R_ARM_ALU_SB_G2:
12254 group = 2;
12255 break;
12256
12257 default:
12258 abort ();
12259 }
12260
12261 /* If REL, extract the addend from the insn. If RELA, it will
12262 have already been fetched for us. */
4962c51a 12263 if (globals->use_rel)
99059e56
RM		 12264 {
12265 int negative;
12266 bfd_vma constant = insn & 0xff;
12267 bfd_vma rotation = (insn & 0xf00) >> 8;
12268
12269 if (rotation == 0)
12270 signed_addend = constant;
12271 else
12272 {
12273 /* Compensate for the fact that in the instruction, the
12274 rotation is stored in multiples of 2 bits. */
12275 rotation *= 2;
12276
12277 /* Rotate "constant" right by "rotation" bits. */
12278 signed_addend = (constant >> rotation) |
12279 (constant << (8 * sizeof (bfd_vma) - rotation));
12280 }
12281
12282 /* Determine if the instruction is an ADD or a SUB.
12283 (For REL, this determines the sign of the addend.) */
12284 negative = identify_add_or_sub (insn);
12285 if (negative == 0)
12286 {
4eca0228 12287 _bfd_error_handler
695344c0 12288 /* xgettext:c-format */
90b6238f 12289 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12290 "are allowed for ALU group relocations"),
12291 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12292 return bfd_reloc_overflow;
12293 }
12294
12295 signed_addend *= negative;
12296 }
4962c51a
MS		 12297
12298 /* Compute the value (X) to go in the place. */
99059e56
RM		 12299 if (r_type == R_ARM_ALU_PC_G0_NC
12300 || r_type == R_ARM_ALU_PC_G1_NC
12301 || r_type == R_ARM_ALU_PC_G0
12302 || r_type == R_ARM_ALU_PC_G1
12303 || r_type == R_ARM_ALU_PC_G2)
12304 /* PC relative. */
12305 signed_value = value - pc + signed_addend;
12306 else
12307 /* Section base relative. */
12308 signed_value = value - sb + signed_addend;
12309
12310 /* If the target symbol is a Thumb function, then set the
12311 Thumb bit in the address. */
35fc36a8 12312 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12313 signed_value |= 1;
12314
99059e56
RM		 12315 /* Calculate the value of the relevant G_n, in encoded
12316 constant-with-rotation format. */
b6518b38
NC		 12317 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12318 group, &residual);
99059e56
RM		 12319
12320 /* Check for overflow if required. */
12321 if ((r_type == R_ARM_ALU_PC_G0
12322 || r_type == R_ARM_ALU_PC_G1
12323 || r_type == R_ARM_ALU_PC_G2
12324 || r_type == R_ARM_ALU_SB_G0
12325 || r_type == R_ARM_ALU_SB_G1
12326 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12327 {
4eca0228 12328 _bfd_error_handler
695344c0 12329 /* xgettext:c-format */
90b6238f 12330 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12331 "splitting %#" PRIx64 " for group relocation %s"),
12332 input_bfd, input_section, (uint64_t) rel->r_offset,
12333 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12334 howto->name);
99059e56
RM		 12335 return bfd_reloc_overflow;
12336 }
12337
12338 /* Mask out the value and the ADD/SUB part of the opcode; take care
12339 not to destroy the S bit. */
12340 insn &= 0xff1ff000;
12341
12342 /* Set the opcode according to whether the value to go in the
12343 place is negative. */
12344 if (signed_value < 0)
12345 insn |= 1 << 22;
12346 else
12347 insn |= 1 << 23;
12348
12349 /* Encode the offset. */
12350 insn |= g_n;
4962c51a
MS		 12351
12352 bfd_put_32 (input_bfd, insn, hit_data);
12353 }
12354 return bfd_reloc_ok;
12355
12356 case R_ARM_LDR_PC_G0:
12357 case R_ARM_LDR_PC_G1:
12358 case R_ARM_LDR_PC_G2:
12359 case R_ARM_LDR_SB_G0:
12360 case R_ARM_LDR_SB_G1:
12361 case R_ARM_LDR_SB_G2:
12362 {
12363 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12364 bfd_vma pc = input_section->output_section->vma
4962c51a 12365 + input_section->output_offset + rel->r_offset;
31a91d61 12366 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12367 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12368 bfd_vma residual;
4962c51a 12369 bfd_signed_vma signed_value;
99059e56
RM		 12370 int group = 0;
12371
12372 /* Determine which groups of bits to calculate. */
12373 switch (r_type)
12374 {
12375 case R_ARM_LDR_PC_G0:
12376 case R_ARM_LDR_SB_G0:
12377 group = 0;
12378 break;
12379
12380 case R_ARM_LDR_PC_G1:
12381 case R_ARM_LDR_SB_G1:
12382 group = 1;
12383 break;
12384
12385 case R_ARM_LDR_PC_G2:
12386 case R_ARM_LDR_SB_G2:
12387 group = 2;
12388 break;
12389
12390 default:
12391 abort ();
12392 }
12393
12394 /* If REL, extract the addend from the insn. If RELA, it will
12395 have already been fetched for us. */
4962c51a 12396 if (globals->use_rel)
99059e56
RM		 12397 {
12398 int negative = (insn & (1 << 23)) ? 1 : -1;
12399 signed_addend = negative * (insn & 0xfff);
12400 }
4962c51a
MS		 12401
12402 /* Compute the value (X) to go in the place. */
99059e56
RM		 12403 if (r_type == R_ARM_LDR_PC_G0
12404 || r_type == R_ARM_LDR_PC_G1
12405 || r_type == R_ARM_LDR_PC_G2)
12406 /* PC relative. */
12407 signed_value = value - pc + signed_addend;
12408 else
12409 /* Section base relative. */
12410 signed_value = value - sb + signed_addend;
12411
12412 /* Calculate the value of the relevant G_{n-1} to obtain
12413 the residual at that stage. */
b6518b38
NC		 12414 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12415 group - 1, &residual);
99059e56
RM		 12416
12417 /* Check for overflow. */
12418 if (residual >= 0x1000)
12419 {
4eca0228 12420 _bfd_error_handler
695344c0 12421 /* xgettext:c-format */
90b6238f 12422 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12423 "splitting %#" PRIx64 " for group relocation %s"),
12424 input_bfd, input_section, (uint64_t) rel->r_offset,
12425 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12426 howto->name);
99059e56
RM		 12427 return bfd_reloc_overflow;
12428 }
12429
12430 /* Mask out the value and U bit. */
12431 insn &= 0xff7ff000;
12432
12433 /* Set the U bit if the value to go in the place is non-negative. */
12434 if (signed_value >= 0)
12435 insn |= 1 << 23;
12436
12437 /* Encode the offset. */
12438 insn |= residual;
4962c51a
MS		 12439
12440 bfd_put_32 (input_bfd, insn, hit_data);
12441 }
12442 return bfd_reloc_ok;
12443
12444 case R_ARM_LDRS_PC_G0:
12445 case R_ARM_LDRS_PC_G1:
12446 case R_ARM_LDRS_PC_G2:
12447 case R_ARM_LDRS_SB_G0:
12448 case R_ARM_LDRS_SB_G1:
12449 case R_ARM_LDRS_SB_G2:
12450 {
12451 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12452 bfd_vma pc = input_section->output_section->vma
4962c51a 12453 + input_section->output_offset + rel->r_offset;
31a91d61 12454 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12455 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12456 bfd_vma residual;
4962c51a 12457 bfd_signed_vma signed_value;
99059e56
RM		 12458 int group = 0;
12459
12460 /* Determine which groups of bits to calculate. */
12461 switch (r_type)
12462 {
12463 case R_ARM_LDRS_PC_G0:
12464 case R_ARM_LDRS_SB_G0:
12465 group = 0;
12466 break;
12467
12468 case R_ARM_LDRS_PC_G1:
12469 case R_ARM_LDRS_SB_G1:
12470 group = 1;
12471 break;
12472
12473 case R_ARM_LDRS_PC_G2:
12474 case R_ARM_LDRS_SB_G2:
12475 group = 2;
12476 break;
12477
12478 default:
12479 abort ();
12480 }
12481
12482 /* If REL, extract the addend from the insn. If RELA, it will
12483 have already been fetched for us. */
4962c51a 12484 if (globals->use_rel)
99059e56
RM		 12485 {
12486 int negative = (insn & (1 << 23)) ? 1 : -1;
12487 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12488 }
4962c51a
MS		 12489
12490 /* Compute the value (X) to go in the place. */
99059e56
RM		 12491 if (r_type == R_ARM_LDRS_PC_G0
12492 || r_type == R_ARM_LDRS_PC_G1
12493 || r_type == R_ARM_LDRS_PC_G2)
12494 /* PC relative. */
12495 signed_value = value - pc + signed_addend;
12496 else
12497 /* Section base relative. */
12498 signed_value = value - sb + signed_addend;
12499
12500 /* Calculate the value of the relevant G_{n-1} to obtain
12501 the residual at that stage. */
b6518b38
NC		 12502 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12503 group - 1, &residual);
99059e56
RM		 12504
12505 /* Check for overflow. */
12506 if (residual >= 0x100)
12507 {
4eca0228 12508 _bfd_error_handler
695344c0 12509 /* xgettext:c-format */
90b6238f 12510 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12511 "splitting %#" PRIx64 " for group relocation %s"),
12512 input_bfd, input_section, (uint64_t) rel->r_offset,
12513 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12514 howto->name);
99059e56
RM		 12515 return bfd_reloc_overflow;
12516 }
12517
12518 /* Mask out the value and U bit. */
12519 insn &= 0xff7ff0f0;
12520
12521 /* Set the U bit if the value to go in the place is non-negative. */
12522 if (signed_value >= 0)
12523 insn |= 1 << 23;
12524
12525 /* Encode the offset. */
12526 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12527
12528 bfd_put_32 (input_bfd, insn, hit_data);
12529 }
12530 return bfd_reloc_ok;
12531
12532 case R_ARM_LDC_PC_G0:
12533 case R_ARM_LDC_PC_G1:
12534 case R_ARM_LDC_PC_G2:
12535 case R_ARM_LDC_SB_G0:
12536 case R_ARM_LDC_SB_G1:
12537 case R_ARM_LDC_SB_G2:
12538 {
12539 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12540 bfd_vma pc = input_section->output_section->vma
4962c51a 12541 + input_section->output_offset + rel->r_offset;
31a91d61 12542 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12543 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12544 bfd_vma residual;
4962c51a 12545 bfd_signed_vma signed_value;
99059e56
RM		 12546 int group = 0;
12547
12548 /* Determine which groups of bits to calculate. */
12549 switch (r_type)
12550 {
12551 case R_ARM_LDC_PC_G0:
12552 case R_ARM_LDC_SB_G0:
12553 group = 0;
12554 break;
12555
12556 case R_ARM_LDC_PC_G1:
12557 case R_ARM_LDC_SB_G1:
12558 group = 1;
12559 break;
12560
12561 case R_ARM_LDC_PC_G2:
12562 case R_ARM_LDC_SB_G2:
12563 group = 2;
12564 break;
12565
12566 default:
12567 abort ();
12568 }
12569
12570 /* If REL, extract the addend from the insn. If RELA, it will
12571 have already been fetched for us. */
4962c51a 12572 if (globals->use_rel)
99059e56
RM		 12573 {
12574 int negative = (insn & (1 << 23)) ? 1 : -1;
12575 signed_addend = negative * ((insn & 0xff) << 2);
12576 }
4962c51a
MS		 12577
12578 /* Compute the value (X) to go in the place. */
99059e56
RM		 12579 if (r_type == R_ARM_LDC_PC_G0
12580 || r_type == R_ARM_LDC_PC_G1
12581 || r_type == R_ARM_LDC_PC_G2)
12582 /* PC relative. */
12583 signed_value = value - pc + signed_addend;
12584 else
12585 /* Section base relative. */
12586 signed_value = value - sb + signed_addend;
12587
12588 /* Calculate the value of the relevant G_{n-1} to obtain
12589 the residual at that stage. */
b6518b38
NC		 12590 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12591 group - 1, &residual);
99059e56
RM		 12592
12593 /* Check for overflow. (The absolute value to go in the place must be
12594 divisible by four and, after having been divided by four, must
12595 fit in eight bits.) */
12596 if ((residual & 0x3) != 0 || residual >= 0x400)
12597 {
4eca0228 12598 _bfd_error_handler
695344c0 12599 /* xgettext:c-format */
90b6238f 12600 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12601 "splitting %#" PRIx64 " for group relocation %s"),
12602 input_bfd, input_section, (uint64_t) rel->r_offset,
12603 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12604 howto->name);
99059e56
RM		 12605 return bfd_reloc_overflow;
12606 }
12607
12608 /* Mask out the value and U bit. */
12609 insn &= 0xff7fff00;
12610
12611 /* Set the U bit if the value to go in the place is non-negative. */
12612 if (signed_value >= 0)
12613 insn |= 1 << 23;
12614
12615 /* Encode the offset. */
12616 insn |= residual >> 2;
4962c51a
MS		 12617
12618 bfd_put_32 (input_bfd, insn, hit_data);
12619 }
12620 return bfd_reloc_ok;
12621
72d98d16
MG		 12622 case R_ARM_THM_ALU_ABS_G0_NC:
12623 case R_ARM_THM_ALU_ABS_G1_NC:
12624 case R_ARM_THM_ALU_ABS_G2_NC:
12625 case R_ARM_THM_ALU_ABS_G3_NC:
12626 {
12627 const int shift_array[4] = {0, 8, 16, 24};
12628 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12629 bfd_vma addr = value;
12630 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12631
12632 /* Compute address. */
12633 if (globals->use_rel)
12634 signed_addend = insn & 0xff;
12635 addr += signed_addend;
12636 if (branch_type == ST_BRANCH_TO_THUMB)
12637 addr |= 1;
12638 /* Clean imm8 insn. */
12639 insn &= 0xff00;
12640 /* And update with correct part of address. */
12641 insn |= (addr >> shift) & 0xff;
12642 /* Update insn. */
12643 bfd_put_16 (input_bfd, insn, hit_data);
12644 }
12645
12646 *unresolved_reloc_p = FALSE;
12647 return bfd_reloc_ok;
12648
e8b09b87
CL		 12649 case R_ARM_GOTOFFFUNCDESC:
12650 {
4b24dd1a 12651 if (h == NULL)
e8b09b87
CL		 12652 {
12653 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12654 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12655 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12656 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12657 bfd_vma seg = -1;
12658
12659 if (bfd_link_pic(info) && dynindx == 0)
12660 abort();
12661
12662 /* Resolve relocation. */
12663 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12664 , contents + rel->r_offset);
12665 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12666 not done yet. */
12667 arm_elf_fill_funcdesc(output_bfd, info,
12668 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12669 dynindx, offset, addr, dynreloc_value, seg);
12670 }
12671 else
12672 {
12673 int dynindx;
12674 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12675 bfd_vma addr;
12676 bfd_vma seg = -1;
12677
12678 /* For static binaries, sym_sec can be null. */
12679 if (sym_sec)
12680 {
12681 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12682 addr = dynreloc_value - sym_sec->output_section->vma;
12683 }
12684 else
12685 {
12686 dynindx = 0;
12687 addr = 0;
12688 }
12689
12690 if (bfd_link_pic(info) && dynindx == 0)
12691 abort();
12692
12693 /* This case cannot occur since funcdesc is allocated by
12694 the dynamic loader so we cannot resolve the relocation. */
12695 if (h->dynindx != -1)
12696 abort();
12697
12698 /* Resolve relocation. */
12699 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12700 contents + rel->r_offset);
12701 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12702 arm_elf_fill_funcdesc(output_bfd, info,
12703 &eh->fdpic_cnts.funcdesc_offset,
12704 dynindx, offset, addr, dynreloc_value, seg);
12705 }
12706 }
12707 *unresolved_reloc_p = FALSE;
12708 return bfd_reloc_ok;
12709
12710 case R_ARM_GOTFUNCDESC:
12711 {
4b24dd1a 12712 if (h != NULL)
e8b09b87
CL		 12713 {
12714 Elf_Internal_Rela outrel;
12715
12716 /* Resolve relocation. */
12717 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12718 + sgot->output_offset),
12719 contents + rel->r_offset);
12720 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12721 if(h->dynindx == -1)
12722 {
12723 int dynindx;
12724 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12725 bfd_vma addr;
12726 bfd_vma seg = -1;
12727
12728 /* For static binaries sym_sec can be null. */
12729 if (sym_sec)
12730 {
12731 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12732 addr = dynreloc_value - sym_sec->output_section->vma;
12733 }
12734 else
12735 {
12736 dynindx = 0;
12737 addr = 0;
12738 }
12739
12740 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12741 arm_elf_fill_funcdesc(output_bfd, info,
12742 &eh->fdpic_cnts.funcdesc_offset,
12743 dynindx, offset, addr, dynreloc_value, seg);
12744 }
12745
12746 /* Add a dynamic relocation on GOT entry if not already done. */
12747 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12748 {
12749 if (h->dynindx == -1)
12750 {
12751 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12752 if (h->root.type == bfd_link_hash_undefweak)
12753 bfd_put_32(output_bfd, 0, sgot->contents
12754 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12755 else
12756 bfd_put_32(output_bfd, sgot->output_section->vma
12757 + sgot->output_offset
12758 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12759 sgot->contents
12760 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12761 }
12762 else
12763 {
12764 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12765 }
12766 outrel.r_offset = sgot->output_section->vma
12767 + sgot->output_offset
12768 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12769 outrel.r_addend = 0;
12770 if (h->dynindx == -1 && !bfd_link_pic(info))
12771 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12772 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12773 else
4b24dd1a
AM		 12774 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12775 outrel.r_offset);
e8b09b87
CL		 12776 else
12777 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12778 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12779 }
12780 }
12781 else
12782 {
12783 /* Such relocation on static function should not have been
12784 emitted by the compiler. */
12785 abort();
12786 }
12787 }
12788 *unresolved_reloc_p = FALSE;
12789 return bfd_reloc_ok;
12790
12791 case R_ARM_FUNCDESC:
12792 {
4b24dd1a 12793 if (h == NULL)
e8b09b87
CL		 12794 {
12795 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12796 Elf_Internal_Rela outrel;
12797 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12798 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12799 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12800 bfd_vma seg = -1;
12801
12802 if (bfd_link_pic(info) && dynindx == 0)
12803 abort();
12804
12805 /* Replace static FUNCDESC relocation with a
12806 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12807 executable. */
12808 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12809 outrel.r_offset = input_section->output_section->vma
12810 + input_section->output_offset + rel->r_offset;
12811 outrel.r_addend = 0;
12812 if (bfd_link_pic(info))
12813 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12814 else
12815 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12816
12817 bfd_put_32 (input_bfd, sgot->output_section->vma
12818 + sgot->output_offset + offset, hit_data);
12819
12820 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12821 arm_elf_fill_funcdesc(output_bfd, info,
12822 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12823 dynindx, offset, addr, dynreloc_value, seg);
12824 }
12825 else
12826 {
12827 if (h->dynindx == -1)
12828 {
12829 int dynindx;
12830 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12831 bfd_vma addr;
12832 bfd_vma seg = -1;
12833 Elf_Internal_Rela outrel;
12834
12835 /* For static binaries sym_sec can be null. */
12836 if (sym_sec)
12837 {
12838 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12839 addr = dynreloc_value - sym_sec->output_section->vma;
12840 }
12841 else
12842 {
12843 dynindx = 0;
12844 addr = 0;
12845 }
12846
12847 if (bfd_link_pic(info) && dynindx == 0)
12848 abort();
12849
12850 /* Replace static FUNCDESC relocation with a
12851 R_ARM_RELATIVE dynamic relocation. */
12852 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12853 outrel.r_offset = input_section->output_section->vma
12854 + input_section->output_offset + rel->r_offset;
12855 outrel.r_addend = 0;
12856 if (bfd_link_pic(info))
12857 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12858 else
12859 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12860
12861 bfd_put_32 (input_bfd, sgot->output_section->vma
12862 + sgot->output_offset + offset, hit_data);
12863
12864 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12865 arm_elf_fill_funcdesc(output_bfd, info,
12866 &eh->fdpic_cnts.funcdesc_offset,
12867 dynindx, offset, addr, dynreloc_value, seg);
12868 }
12869 else
12870 {
12871 Elf_Internal_Rela outrel;
12872
12873 /* Add a dynamic relocation. */
12874 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12875 outrel.r_offset = input_section->output_section->vma
12876 + input_section->output_offset + rel->r_offset;
12877 outrel.r_addend = 0;
12878 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12879 }
12880 }
12881 }
12882 *unresolved_reloc_p = FALSE;
12883 return bfd_reloc_ok;
12884
e5d6e09e
AV		 12885 case R_ARM_THM_BF16:
12886 {
12887 bfd_vma relocation;
12888 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12889 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12890
12891 if (globals->use_rel)
12892 {
12893 bfd_vma immA = (upper_insn & 0x001f);
12894 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12895 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12896 addend = (immA << 12);
12897 addend |= (immB << 2);
12898 addend |= (immC << 1);
12899 addend |= 1;
12900 /* Sign extend. */
e6f65e75 12901 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12902 }
12903
e6f65e75 12904 relocation = value + signed_addend;
e5d6e09e
AV		 12905 relocation -= (input_section->output_section->vma
12906 + input_section->output_offset
12907 + rel->r_offset);
12908
12909 /* Put RELOCATION back into the insn. */
12910 {
12911 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12912 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12913 bfd_vma immC = (relocation & 0x00000002) >> 1;
12914
12915 upper_insn = (upper_insn & 0xffe0) | immA;
12916 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12917 }
12918
12919 /* Put the relocated value back in the object file: */
12920 bfd_put_16 (input_bfd, upper_insn, hit_data);
12921 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12922
12923 return bfd_reloc_ok;
12924 }
12925
1889da70
AV		 12926 case R_ARM_THM_BF12:
12927 {
12928 bfd_vma relocation;
12929 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12930 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12931
12932 if (globals->use_rel)
12933 {
12934 bfd_vma immA = (upper_insn & 0x0001);
12935 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12936 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12937 addend = (immA << 12);
12938 addend |= (immB << 2);
12939 addend |= (immC << 1);
12940 addend |= 1;
12941 /* Sign extend. */
12942 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 12943 signed_addend = addend;
1889da70
AV		 12944 }
12945
e6f65e75 12946 relocation = value + signed_addend;
1889da70
AV		 12947 relocation -= (input_section->output_section->vma
12948 + input_section->output_offset
12949 + rel->r_offset);
12950
12951 /* Put RELOCATION back into the insn. */
12952 {
12953 bfd_vma immA = (relocation & 0x00001000) >> 12;
12954 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12955 bfd_vma immC = (relocation & 0x00000002) >> 1;
12956
12957 upper_insn = (upper_insn & 0xfffe) | immA;
12958 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12959 }
12960
12961 /* Put the relocated value back in the object file: */
12962 bfd_put_16 (input_bfd, upper_insn, hit_data);
12963 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12964
12965 return bfd_reloc_ok;
12966 }
12967
1caf72a5
AV		 12968 case R_ARM_THM_BF18:
12969 {
12970 bfd_vma relocation;
12971 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12972 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12973
12974 if (globals->use_rel)
12975 {
12976 bfd_vma immA = (upper_insn & 0x007f);
12977 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12978 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12979 addend = (immA << 12);
12980 addend |= (immB << 2);
12981 addend |= (immC << 1);
12982 addend |= 1;
12983 /* Sign extend. */
12984 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 12985 signed_addend = addend;
1caf72a5
AV		 12986 }
12987
e6f65e75 12988 relocation = value + signed_addend;
1caf72a5
AV		 12989 relocation -= (input_section->output_section->vma
12990 + input_section->output_offset
12991 + rel->r_offset);
12992
12993 /* Put RELOCATION back into the insn. */
12994 {
12995 bfd_vma immA = (relocation & 0x0007f000) >> 12;
12996 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12997 bfd_vma immC = (relocation & 0x00000002) >> 1;
12998
12999 upper_insn = (upper_insn & 0xff80) | immA;
13000 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13001 }
13002
13003 /* Put the relocated value back in the object file: */
13004 bfd_put_16 (input_bfd, upper_insn, hit_data);
13005 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13006
13007 return bfd_reloc_ok;
13008 }
13009
252b5132
RH		 13010 default:
13011 return bfd_reloc_notsupported;
13012 }
13013}
13014
98c1d4aa
NC		 13015/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13016static void
07d6d2b8
AM		 13017arm_add_to_rel (bfd * abfd,
13018 bfd_byte * address,
57e8b36a 13019 reloc_howto_type * howto,
07d6d2b8 13020 bfd_signed_vma increment)
98c1d4aa 13021{
98c1d4aa
NC		 13022 bfd_signed_vma addend;
13023
bd97cb95
DJ		 13024 if (howto->type == R_ARM_THM_CALL
13025 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13026 {
9a5aca8c
AM		 13027 int upper_insn, lower_insn;
13028 int upper, lower;
98c1d4aa 13029
9a5aca8c
AM		 13030 upper_insn = bfd_get_16 (abfd, address);
13031 lower_insn = bfd_get_16 (abfd, address + 2);
13032 upper = upper_insn & 0x7ff;
13033 lower = lower_insn & 0x7ff;
13034
13035 addend = (upper << 12) | (lower << 1);
ddda4409 13036 addend += increment;
9a5aca8c 13037 addend >>= 1;
98c1d4aa 13038
9a5aca8c
AM		 13039 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13040 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13041
dc810e39
AM		 13042 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13043 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13044 }
13045 else
13046 {
07d6d2b8 13047 bfd_vma contents;
9a5aca8c
AM		 13048
13049 contents = bfd_get_32 (abfd, address);
13050
13051 /* Get the (signed) value from the instruction. */
13052 addend = contents & howto->src_mask;
13053 if (addend & ((howto->src_mask + 1) >> 1))
13054 {
13055 bfd_signed_vma mask;
13056
13057 mask = -1;
13058 mask &= ~ howto->src_mask;
13059 addend |= mask;
13060 }
13061
13062 /* Add in the increment, (which is a byte value). */
13063 switch (howto->type)
13064 {
13065 default:
13066 addend += increment;
13067 break;
13068
13069 case R_ARM_PC24:
c6596c5e 13070 case R_ARM_PLT32:
5b5bb741
PB		 13071 case R_ARM_CALL:
13072 case R_ARM_JUMP24:
9a5aca8c 13073 addend <<= howto->size;
dc810e39 13074 addend += increment;
9a5aca8c
AM		 13075
13076 /* Should we check for overflow here ? */
13077
13078 /* Drop any undesired bits. */
13079 addend >>= howto->rightshift;
13080 break;
13081 }
13082
13083 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13084
13085 bfd_put_32 (abfd, contents, address);
ddda4409 13086 }
98c1d4aa 13087}
252b5132 13088
ba93b8ac
DJ		 13089#define IS_ARM_TLS_RELOC(R_TYPE) \
13090 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13091 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13092 || (R_TYPE) == R_ARM_TLS_LDO32 \
13093 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13094 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13095 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13096 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13097 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13098 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13099 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13100 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13101 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13102
13103/* Specific set of relocations for the gnu tls dialect. */
13104#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13105 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13106 || (R_TYPE) == R_ARM_TLS_CALL \
13107 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13108 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13109 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13110
252b5132 13111/* Relocate an ARM ELF section. */
906e58ca 13112
b34976b6 13113static bfd_boolean
07d6d2b8 13114elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13115 struct bfd_link_info * info,
07d6d2b8
AM		 13116 bfd * input_bfd,
13117 asection * input_section,
13118 bfd_byte * contents,
13119 Elf_Internal_Rela * relocs,
13120 Elf_Internal_Sym * local_syms,
13121 asection ** local_sections)
252b5132 13122{
b34976b6
AM		 13123 Elf_Internal_Shdr *symtab_hdr;
13124 struct elf_link_hash_entry **sym_hashes;
13125 Elf_Internal_Rela *rel;
13126 Elf_Internal_Rela *relend;
13127 const char *name;
b32d3aa2 13128 struct elf32_arm_link_hash_table * globals;
252b5132 13129
4e7fd91e 13130 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13131 if (globals == NULL)
13132 return FALSE;
b491616a 13133
0ffa91dd 13134 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13135 sym_hashes = elf_sym_hashes (input_bfd);
13136
13137 rel = relocs;
13138 relend = relocs + input_section->reloc_count;
13139 for (; rel < relend; rel++)
13140 {
07d6d2b8
AM		 13141 int r_type;
13142 reloc_howto_type * howto;
13143 unsigned long r_symndx;
13144 Elf_Internal_Sym * sym;
13145 asection * sec;
252b5132 13146 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13147 bfd_vma relocation;
13148 bfd_reloc_status_type r;
13149 arelent bfd_reloc;
13150 char sym_type;
13151 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13152 char *error_message = NULL;
f21f3fe0 13153
252b5132 13154 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13155 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13156 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13157
ba96a88f 13158 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13159 || r_type == R_ARM_GNU_VTINHERIT)
13160 continue;
252b5132 13161
47aeb64c
NC		 13162 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13163
13164 if (howto == NULL)
13165 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13166
252b5132
RH		 13167 h = NULL;
13168 sym = NULL;
13169 sec = NULL;
9b485d32 13170
252b5132
RH		 13171 if (r_symndx < symtab_hdr->sh_info)
13172 {
13173 sym = local_syms + r_symndx;
ba93b8ac 13174 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13175 sec = local_sections[r_symndx];
ffcb4889
NS		 13176
13177 /* An object file might have a reference to a local
13178 undefined symbol. This is a daft object file, but we
13179 should at least do something about it. V4BX & NONE
13180 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13181 allowed to use the undefined symbol, so allow those.
13182 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13183 if (r_type != R_ARM_V4BX
13184 && r_type != R_ARM_NONE
77b4f08f 13185 && r_symndx != STN_UNDEF
ffcb4889
NS		 13186 && bfd_is_und_section (sec)
13187 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13188 (*info->callbacks->undefined_symbol)
13189 (info, bfd_elf_string_from_elf_section
13190 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13191 input_bfd, input_section,
13192 rel->r_offset, TRUE);
b38cadfb 13193
4e7fd91e 13194 if (globals->use_rel)
f8df10f4 13195 {
4e7fd91e
PB		 13196 relocation = (sec->output_section->vma
13197 + sec->output_offset
13198 + sym->st_value);
0e1862bb 13199 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13200 && (sec->flags & SEC_MERGE)
13201 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13202 {
4e7fd91e
PB		 13203 asection *msec;
13204 bfd_vma addend, value;
13205
39623e12 13206 switch (r_type)
4e7fd91e 13207 {
39623e12
PB		 13208 case R_ARM_MOVW_ABS_NC:
13209 case R_ARM_MOVT_ABS:
13210 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13211 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13212 addend = (addend ^ 0x8000) - 0x8000;
13213 break;
f8df10f4 13214
39623e12
PB		 13215 case R_ARM_THM_MOVW_ABS_NC:
13216 case R_ARM_THM_MOVT_ABS:
13217 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13218 << 16;
13219 value |= bfd_get_16 (input_bfd,
13220 contents + rel->r_offset + 2);
13221 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13222 | ((value & 0x04000000) >> 15);
13223 addend = (addend ^ 0x8000) - 0x8000;
13224 break;
f8df10f4 13225
39623e12
PB		 13226 default:
13227 if (howto->rightshift
13228 || (howto->src_mask & (howto->src_mask + 1)))
13229 {
4eca0228 13230 _bfd_error_handler
695344c0 13231 /* xgettext:c-format */
2dcf00ce
AM		 13232 (_("%pB(%pA+%#" PRIx64 "): "
13233 "%s relocation against SEC_MERGE section"),
39623e12 13234 input_bfd, input_section,
2dcf00ce 13235 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13236 return FALSE;
13237 }
13238
13239 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13240
13241 /* Get the (signed) value from the instruction. */
13242 addend = value & howto->src_mask;
13243 if (addend & ((howto->src_mask + 1) >> 1))
13244 {
13245 bfd_signed_vma mask;
13246
13247 mask = -1;
13248 mask &= ~ howto->src_mask;
13249 addend |= mask;
13250 }
13251 break;
4e7fd91e 13252 }
39623e12 13253
4e7fd91e
PB		 13254 msec = sec;
13255 addend =
13256 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13257 - relocation;
13258 addend += msec->output_section->vma + msec->output_offset;
39623e12 13259
cc643b88 13260 /* Cases here must match those in the preceding
39623e12
PB		 13261 switch statement. */
13262 switch (r_type)
13263 {
13264 case R_ARM_MOVW_ABS_NC:
13265 case R_ARM_MOVT_ABS:
13266 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13267 | (addend & 0xfff);
13268 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13269 break;
13270
13271 case R_ARM_THM_MOVW_ABS_NC:
13272 case R_ARM_THM_MOVT_ABS:
13273 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13274 | (addend & 0xff) | ((addend & 0x0800) << 15);
13275 bfd_put_16 (input_bfd, value >> 16,
13276 contents + rel->r_offset);
13277 bfd_put_16 (input_bfd, value,
13278 contents + rel->r_offset + 2);
13279 break;
13280
13281 default:
13282 value = (value & ~ howto->dst_mask)
13283 | (addend & howto->dst_mask);
13284 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13285 break;
13286 }
f8df10f4 13287 }
f8df10f4 13288 }
4e7fd91e
PB		 13289 else
13290 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13291 }
13292 else
13293 {
62d887d4 13294 bfd_boolean warned, ignored;
560e09e9 13295
b2a8e766
AM		 13296 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13297 r_symndx, symtab_hdr, sym_hashes,
13298 h, sec, relocation,
62d887d4 13299 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13300
13301 sym_type = h->type;
252b5132
RH		 13302 }
13303
dbaa2011 13304 if (sec != NULL && discarded_section (sec))
e4067dbb 13305 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13306 rel, 1, relend, howto, 0, contents);
ab96bf03 13307
0e1862bb 13308 if (bfd_link_relocatable (info))
ab96bf03
AM		 13309 {
13310 /* This is a relocatable link. We don't have to change
13311 anything, unless the reloc is against a section symbol,
13312 in which case we have to adjust according to where the
13313 section symbol winds up in the output section. */
13314 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13315 {
13316 if (globals->use_rel)
13317 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13318 howto, (bfd_signed_vma) sec->output_offset);
13319 else
13320 rel->r_addend += sec->output_offset;
13321 }
13322 continue;
13323 }
13324
252b5132
RH		 13325 if (h != NULL)
13326 name = h->root.root.string;
13327 else
13328 {
13329 name = (bfd_elf_string_from_elf_section
13330 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13331 if (name == NULL || *name == '\0')
fd361982 13332 name = bfd_section_name (sec);
252b5132 13333 }
f21f3fe0 13334
cf35638d 13335 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13336 && r_type != R_ARM_NONE
13337 && (h == NULL
13338 || h->root.type == bfd_link_hash_defined
13339 || h->root.type == bfd_link_hash_defweak)
13340 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13341 {
4eca0228 13342 _bfd_error_handler
ba93b8ac 13343 ((sym_type == STT_TLS
695344c0 13344 /* xgettext:c-format */
2dcf00ce 13345 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13346 /* xgettext:c-format */
2dcf00ce 13347 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13348 input_bfd,
13349 input_section,
2dcf00ce 13350 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13351 howto->name,
13352 name);
13353 }
13354
0855e32b 13355 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13356 done, i.e., the relaxation produced the final output we want,
13357 and we won't let anybody mess with it. Also, we have to do
13358 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13359 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13360 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13361 || (IS_ARM_TLS_GNU_RELOC (r_type)
13362 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13363 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13364 & GOT_TLS_GDESC)))
13365 {
13366 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13367 contents, rel, h == NULL);
13368 /* This may have been marked unresolved because it came from
13369 a shared library. But we've just dealt with that. */
13370 unresolved_reloc = 0;
13371 }
13372 else
13373 r = bfd_reloc_continue;
b38cadfb 13374
39d911fc
TP		 13375 if (r == bfd_reloc_continue)
13376 {
13377 unsigned char branch_type =
13378 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13379 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13380
13381 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13382 input_section, contents, rel,
13383 relocation, info, sec, name,
13384 sym_type, branch_type, h,
13385 &unresolved_reloc,
13386 &error_message);
13387 }
0945cdfd
DJ		 13388
13389 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13390 because such sections are not SEC_ALLOC and thus ld.so will
13391 not process them. */
13392 if (unresolved_reloc
99059e56
RM		 13393 && !((input_section->flags & SEC_DEBUGGING) != 0
13394 && h->def_dynamic)
1d5316ab
AM		 13395 && _bfd_elf_section_offset (output_bfd, info, input_section,
13396 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13397 {
4eca0228 13398 _bfd_error_handler
695344c0 13399 /* xgettext:c-format */
2dcf00ce
AM		 13400 (_("%pB(%pA+%#" PRIx64 "): "
13401 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13402 input_bfd,
13403 input_section,
2dcf00ce 13404 (uint64_t) rel->r_offset,
843fe662
L		 13405 howto->name,
13406 h->root.root.string);
0945cdfd
DJ		 13407 return FALSE;
13408 }
252b5132
RH		 13409
13410 if (r != bfd_reloc_ok)
13411 {
252b5132
RH		 13412 switch (r)
13413 {
13414 case bfd_reloc_overflow:
cf919dfd
PB		 13415 /* If the overflowing reloc was to an undefined symbol,
13416 we have already printed one error message and there
13417 is no point complaining again. */
1a72702b
AM		 13418 if (!h || h->root.type != bfd_link_hash_undefined)
13419 (*info->callbacks->reloc_overflow)
13420 (info, (h ? &h->root : NULL), name, howto->name,
13421 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13422 break;
13423
13424 case bfd_reloc_undefined:
1a72702b
AM		 13425 (*info->callbacks->undefined_symbol)
13426 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13427 break;
13428
13429 case bfd_reloc_outofrange:
f2a9dd69 13430 error_message = _("out of range");
252b5132
RH		 13431 goto common_error;
13432
13433 case bfd_reloc_notsupported:
f2a9dd69 13434 error_message = _("unsupported relocation");
252b5132
RH		 13435 goto common_error;
13436
13437 case bfd_reloc_dangerous:
f2a9dd69 13438 /* error_message should already be set. */
252b5132
RH		 13439 goto common_error;
13440
13441 default:
f2a9dd69 13442 error_message = _("unknown error");
8029a119 13443 /* Fall through. */
252b5132
RH		 13444
13445 common_error:
f2a9dd69 13446 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13447 (*info->callbacks->reloc_dangerous)
13448 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13449 break;
13450 }
13451 }
13452 }
13453
b34976b6 13454 return TRUE;
252b5132
RH		 13455}
13456
91d6fa6a 13457/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13458 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13459 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13460 maintaining that condition). */
13461
13462static void
13463add_unwind_table_edit (arm_unwind_table_edit **head,
13464 arm_unwind_table_edit **tail,
13465 arm_unwind_edit_type type,
13466 asection *linked_section,
91d6fa6a 13467 unsigned int tindex)
2468f9c9 13468{
21d799b5
NC		 13469 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13470 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13471
2468f9c9
PB		 13472 new_edit->type = type;
13473 new_edit->linked_section = linked_section;
91d6fa6a 13474 new_edit->index = tindex;
b38cadfb 13475
91d6fa6a 13476 if (tindex > 0)
2468f9c9
PB		 13477 {
13478 new_edit->next = NULL;
13479
13480 if (*tail)
13481 (*tail)->next = new_edit;
13482
13483 (*tail) = new_edit;
13484
13485 if (!*head)
13486 (*head) = new_edit;
13487 }
13488 else
13489 {
13490 new_edit->next = *head;
13491
13492 if (!*tail)
13493 *tail = new_edit;
13494
13495 *head = new_edit;
13496 }
13497}
13498
13499static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13500
13501/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13502static void
13503adjust_exidx_size(asection *exidx_sec, int adjust)
13504{
13505 asection *out_sec;
13506
13507 if (!exidx_sec->rawsize)
13508 exidx_sec->rawsize = exidx_sec->size;
13509
fd361982 13510 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
2468f9c9
PB		 13511 out_sec = exidx_sec->output_section;
13512 /* Adjust size of output section. */
fd361982 13513 bfd_set_section_size (out_sec, out_sec->size +adjust);
2468f9c9
PB		 13514}
13515
13516/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13517static void
13518insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13519{
13520 struct _arm_elf_section_data *exidx_arm_data;
13521
13522 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13523 add_unwind_table_edit (
13524 &exidx_arm_data->u.exidx.unwind_edit_list,
13525 &exidx_arm_data->u.exidx.unwind_edit_tail,
13526 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13527
491d01d3
YU		 13528 exidx_arm_data->additional_reloc_count++;
13529
2468f9c9
PB		 13530 adjust_exidx_size(exidx_sec, 8);
13531}
13532
13533/* Scan .ARM.exidx tables, and create a list describing edits which should be
13534 made to those tables, such that:
b38cadfb 13535
2468f9c9
PB		 13536 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13537 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13538 codes which have been inlined into the index).
2468f9c9 13539
85fdf906
AH		 13540 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13541
2468f9c9 13542 The edits are applied when the tables are written
b38cadfb 13543 (in elf32_arm_write_section). */
2468f9c9
PB		 13544
13545bfd_boolean
13546elf32_arm_fix_exidx_coverage (asection **text_section_order,
13547 unsigned int num_text_sections,
85fdf906
AH		 13548 struct bfd_link_info *info,
13549 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13550{
13551 bfd *inp;
13552 unsigned int last_second_word = 0, i;
13553 asection *last_exidx_sec = NULL;
13554 asection *last_text_sec = NULL;
13555 int last_unwind_type = -1;
13556
13557 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13558 text sections. */
c72f2fb2 13559 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13560 {
13561 asection *sec;
b38cadfb 13562
2468f9c9 13563 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13564 {
2468f9c9
PB		 13565 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13566 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13567
dec9d5df 13568 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13569 continue;
b38cadfb 13570
2468f9c9
PB		 13571 if (elf_sec->linked_to)
13572 {
13573 Elf_Internal_Shdr *linked_hdr
99059e56 13574 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13575 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13576 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13577
13578 if (linked_sec_arm_data == NULL)
99059e56 13579 continue;
2468f9c9
PB		 13580
13581 /* Link this .ARM.exidx section back from the text section it
99059e56 13582 describes. */
2468f9c9
PB		 13583 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13584 }
13585 }
13586 }
13587
13588 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13589 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13590 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13591
13592 for (i = 0; i < num_text_sections; i++)
13593 {
13594 asection *sec = text_section_order[i];
13595 asection *exidx_sec;
13596 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13597 struct _arm_elf_section_data *exidx_arm_data;
13598 bfd_byte *contents = NULL;
13599 int deleted_exidx_bytes = 0;
13600 bfd_vma j;
13601 arm_unwind_table_edit *unwind_edit_head = NULL;
13602 arm_unwind_table_edit *unwind_edit_tail = NULL;
13603 Elf_Internal_Shdr *hdr;
13604 bfd *ibfd;
13605
13606 if (arm_data == NULL)
99059e56 13607 continue;
2468f9c9
PB		 13608
13609 exidx_sec = arm_data->u.text.arm_exidx_sec;
13610 if (exidx_sec == NULL)
13611 {
13612 /* Section has no unwind data. */
13613 if (last_unwind_type == 0 || !last_exidx_sec)
13614 continue;
13615
13616 /* Ignore zero sized sections. */
13617 if (sec->size == 0)
13618 continue;
13619
13620 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13621 last_unwind_type = 0;
13622 continue;
13623 }
13624
22a8f80e
PB		 13625 /* Skip /DISCARD/ sections. */
13626 if (bfd_is_abs_section (exidx_sec->output_section))
13627 continue;
13628
2468f9c9
PB		 13629 hdr = &elf_section_data (exidx_sec)->this_hdr;
13630 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13631 continue;
b38cadfb 13632
2468f9c9
PB		 13633 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13634 if (exidx_arm_data == NULL)
99059e56 13635 continue;
b38cadfb 13636
2468f9c9 13637 ibfd = exidx_sec->owner;
b38cadfb 13638
2468f9c9
PB		 13639 if (hdr->contents != NULL)
13640 contents = hdr->contents;
13641 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13642 /* An error? */
13643 continue;
13644
ac06903d
YU		 13645 if (last_unwind_type > 0)
13646 {
13647 unsigned int first_word = bfd_get_32 (ibfd, contents);
13648 /* Add cantunwind if first unwind item does not match section
13649 start. */
13650 if (first_word != sec->vma)
13651 {
13652 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13653 last_unwind_type = 0;
13654 }
13655 }
13656
2468f9c9
PB		 13657 for (j = 0; j < hdr->sh_size; j += 8)
13658 {
13659 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13660 int unwind_type;
13661 int elide = 0;
13662
13663 /* An EXIDX_CANTUNWIND entry. */
13664 if (second_word == 1)
13665 {
13666 if (last_unwind_type == 0)
13667 elide = 1;
13668 unwind_type = 0;
13669 }
13670 /* Inlined unwinding data. Merge if equal to previous. */
13671 else if ((second_word & 0x80000000) != 0)
13672 {
85fdf906
AH		 13673 if (merge_exidx_entries
13674 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13675 elide = 1;
13676 unwind_type = 1;
13677 last_second_word = second_word;
13678 }
13679 /* Normal table entry. In theory we could merge these too,
13680 but duplicate entries are likely to be much less common. */
13681 else
13682 unwind_type = 2;
13683
491d01d3 13684 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13685 {
13686 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13687 DELETE_EXIDX_ENTRY, NULL, j / 8);
13688
13689 deleted_exidx_bytes += 8;
13690 }
13691
13692 last_unwind_type = unwind_type;
13693 }
13694
13695 /* Free contents if we allocated it ourselves. */
13696 if (contents != hdr->contents)
99059e56 13697 free (contents);
2468f9c9
PB		 13698
13699 /* Record edits to be applied later (in elf32_arm_write_section). */
13700 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13701 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13702
2468f9c9
PB		 13703 if (deleted_exidx_bytes > 0)
13704 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13705
13706 last_exidx_sec = exidx_sec;
13707 last_text_sec = sec;
13708 }
13709
13710 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13711 if (!bfd_link_relocatable (info) && last_exidx_sec
13712 && last_unwind_type != 0)
2468f9c9
PB		 13713 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13714
13715 return TRUE;
13716}
13717
3e6b1042
DJ		 13718static bfd_boolean
13719elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13720 bfd *ibfd, const char *name)
13721{
13722 asection *sec, *osec;
13723
3d4d4302 13724 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13725 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13726 return TRUE;
13727
13728 osec = sec->output_section;
13729 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13730 return TRUE;
13731
13732 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13733 sec->output_offset, sec->size))
13734 return FALSE;
13735
13736 return TRUE;
13737}
13738
13739static bfd_boolean
13740elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13741{
13742 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13743 asection *sec, *osec;
3e6b1042 13744
4dfe6ac6
NC		 13745 if (globals == NULL)
13746 return FALSE;
13747
3e6b1042
DJ		 13748 /* Invoke the regular ELF backend linker to do all the work. */
13749 if (!bfd_elf_final_link (abfd, info))
13750 return FALSE;
13751
fe33d2fa
CL		 13752 /* Process stub sections (eg BE8 encoding, ...). */
13753 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13754 unsigned int i;
cdb21a0a
NS		 13755 for (i=0; i<htab->top_id; i++)
13756 {
13757 sec = htab->stub_group[i].stub_sec;
13758 /* Only process it once, in its link_sec slot. */
13759 if (sec && i == htab->stub_group[i].link_sec->id)
13760 {
13761 osec = sec->output_section;
13762 elf32_arm_write_section (abfd, info, sec, sec->contents);
13763 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13764 sec->output_offset, sec->size))
13765 return FALSE;
13766 }
fe33d2fa 13767 }
fe33d2fa 13768
3e6b1042
DJ		 13769 /* Write out any glue sections now that we have created all the
13770 stubs. */
13771 if (globals->bfd_of_glue_owner != NULL)
13772 {
13773 if (! elf32_arm_output_glue_section (info, abfd,
13774 globals->bfd_of_glue_owner,
13775 ARM2THUMB_GLUE_SECTION_NAME))
13776 return FALSE;
13777
13778 if (! elf32_arm_output_glue_section (info, abfd,
13779 globals->bfd_of_glue_owner,
13780 THUMB2ARM_GLUE_SECTION_NAME))
13781 return FALSE;
13782
13783 if (! elf32_arm_output_glue_section (info, abfd,
13784 globals->bfd_of_glue_owner,
13785 VFP11_ERRATUM_VENEER_SECTION_NAME))
13786 return FALSE;
13787
a504d23a
LA		 13788 if (! elf32_arm_output_glue_section (info, abfd,
13789 globals->bfd_of_glue_owner,
13790 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13791 return FALSE;
13792
3e6b1042
DJ		 13793 if (! elf32_arm_output_glue_section (info, abfd,
13794 globals->bfd_of_glue_owner,
13795 ARM_BX_GLUE_SECTION_NAME))
13796 return FALSE;
13797 }
13798
13799 return TRUE;
13800}
13801
5968a7b8
NC		 13802/* Return a best guess for the machine number based on the attributes. */
13803
13804static unsigned int
13805bfd_arm_get_mach_from_attributes (bfd * abfd)
13806{
13807 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13808
13809 switch (arch)
13810 {
c0c468d5 13811 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13812 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13813 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13814 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13815
13816 case TAG_CPU_ARCH_V5TE:
13817 {
13818 char * name;
13819
13820 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13821 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13822
13823 if (name)
13824 {
13825 if (strcmp (name, "IWMMXT2") == 0)
13826 return bfd_mach_arm_iWMMXt2;
13827
13828 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13829 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13830
13831 if (strcmp (name, "XSCALE") == 0)
13832 {
13833 int wmmx;
13834
13835 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13836 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13837 switch (wmmx)
13838 {
13839 case 1: return bfd_mach_arm_iWMMXt;
13840 case 2: return bfd_mach_arm_iWMMXt2;
13841 default: return bfd_mach_arm_XScale;
13842 }
13843 }
5968a7b8
NC		 13844 }
13845
13846 return bfd_mach_arm_5TE;
13847 }
13848
c0c468d5
TP		 13849 case TAG_CPU_ARCH_V5TEJ:
13850 return bfd_mach_arm_5TEJ;
13851 case TAG_CPU_ARCH_V6:
13852 return bfd_mach_arm_6;
13853 case TAG_CPU_ARCH_V6KZ:
13854 return bfd_mach_arm_6KZ;
13855 case TAG_CPU_ARCH_V6T2:
13856 return bfd_mach_arm_6T2;
13857 case TAG_CPU_ARCH_V6K:
13858 return bfd_mach_arm_6K;
13859 case TAG_CPU_ARCH_V7:
13860 return bfd_mach_arm_7;
13861 case TAG_CPU_ARCH_V6_M:
13862 return bfd_mach_arm_6M;
13863 case TAG_CPU_ARCH_V6S_M:
13864 return bfd_mach_arm_6SM;
13865 case TAG_CPU_ARCH_V7E_M:
13866 return bfd_mach_arm_7EM;
13867 case TAG_CPU_ARCH_V8:
13868 return bfd_mach_arm_8;
13869 case TAG_CPU_ARCH_V8R:
13870 return bfd_mach_arm_8R;
13871 case TAG_CPU_ARCH_V8M_BASE:
13872 return bfd_mach_arm_8M_BASE;
13873 case TAG_CPU_ARCH_V8M_MAIN:
13874 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13875 case TAG_CPU_ARCH_V8_1M_MAIN:
13876 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13877
5968a7b8 13878 default:
c0c468d5
TP		 13879 /* Force entry to be added for any new known Tag_CPU_arch value. */
13880 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13881
13882 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13883 return bfd_mach_arm_unknown;
13884 }
13885}
13886
c178919b
NC		 13887/* Set the right machine number. */
13888
13889static bfd_boolean
57e8b36a 13890elf32_arm_object_p (bfd *abfd)
c178919b 13891{
5a6c6817 13892 unsigned int mach;
57e8b36a 13893
5a6c6817 13894 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13895
5968a7b8
NC		 13896 if (mach == bfd_mach_arm_unknown)
13897 {
13898 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13899 mach = bfd_mach_arm_ep9312;
13900 else
13901 mach = bfd_arm_get_mach_from_attributes (abfd);
13902 }
c178919b 13903
5968a7b8 13904 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13905 return TRUE;
13906}
13907
fc830a83 13908/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13909
b34976b6 13910static bfd_boolean
57e8b36a 13911elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13912{
13913 if (elf_flags_init (abfd)
13914 && elf_elfheader (abfd)->e_flags != flags)
13915 {
fc830a83
NC		 13916 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13917 {
fd2ec330 13918 if (flags & EF_ARM_INTERWORK)
4eca0228 13919 _bfd_error_handler
90b6238f 13920 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13921 abfd);
fc830a83 13922 else
d003868e 13923 _bfd_error_handler
90b6238f 13924 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13925 abfd);
fc830a83 13926 }
252b5132
RH		 13927 }
13928 else
13929 {
13930 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13931 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13932 }
13933
b34976b6 13934 return TRUE;
252b5132
RH		 13935}
13936
fc830a83 13937/* Copy backend specific data from one object module to another. */
9b485d32 13938
b34976b6 13939static bfd_boolean
57e8b36a 13940elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13941{
13942 flagword in_flags;
13943 flagword out_flags;
13944
0ffa91dd 13945 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13946 return TRUE;
252b5132 13947
fc830a83 13948 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13949 out_flags = elf_elfheader (obfd)->e_flags;
13950
fc830a83
NC		 13951 if (elf_flags_init (obfd)
13952 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13953 && in_flags != out_flags)
252b5132 13954 {
252b5132 13955 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13956 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13957 return FALSE;
252b5132
RH		 13958
13959 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13960 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13961 return FALSE;
252b5132
RH		 13962
13963 /* If the src and dest have different interworking flags
99059e56 13964 then turn off the interworking bit. */
fd2ec330 13965 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13966 {
fd2ec330 13967 if (out_flags & EF_ARM_INTERWORK)
d003868e 13968 _bfd_error_handler
90b6238f 13969 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13970 obfd, ibfd);
252b5132 13971
fd2ec330 13972 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13973 }
1006ba19
PB		 13974
13975 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13976 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13977 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13978 }
13979
13980 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13981 elf_flags_init (obfd) = TRUE;
252b5132 13982
e2349352 13983 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13984}
13985
13986/* Values for Tag_ABI_PCS_R9_use. */
13987enum
13988{
13989 AEABI_R9_V6,
13990 AEABI_R9_SB,
13991 AEABI_R9_TLS,
13992 AEABI_R9_unused
13993};
13994
13995/* Values for Tag_ABI_PCS_RW_data. */
13996enum
13997{
13998 AEABI_PCS_RW_data_absolute,
13999 AEABI_PCS_RW_data_PCrel,
14000 AEABI_PCS_RW_data_SBrel,
14001 AEABI_PCS_RW_data_unused
14002};
14003
14004/* Values for Tag_ABI_enum_size. */
14005enum
14006{
14007 AEABI_enum_unused,
14008 AEABI_enum_short,
14009 AEABI_enum_wide,
14010 AEABI_enum_forced_wide
14011};
14012
104d59d1
JM		 14013/* Determine whether an object attribute tag takes an integer, a
14014 string or both. */
906e58ca 14015
104d59d1
JM		 14016static int
14017elf32_arm_obj_attrs_arg_type (int tag)
14018{
14019 if (tag == Tag_compatibility)
3483fe2e 14020 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14021 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14022 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14023 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14024 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14025 else if (tag < 32)
3483fe2e 14026 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14027 else
3483fe2e 14028 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14029}
14030
5aa6ff7c
AS		 14031/* The ABI defines that Tag_conformance should be emitted first, and that
14032 Tag_nodefaults should be second (if either is defined). This sets those
14033 two positions, and bumps up the position of all the remaining tags to
14034 compensate. */
14035static int
14036elf32_arm_obj_attrs_order (int num)
14037{
3de4a297 14038 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14039 return Tag_conformance;
3de4a297 14040 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14041 return Tag_nodefaults;
14042 if ((num - 2) < Tag_nodefaults)
14043 return num - 2;
14044 if ((num - 1) < Tag_conformance)
14045 return num - 1;
14046 return num;
14047}
14048
e8b36cd1
JM		 14049/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14050static bfd_boolean
14051elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14052{
14053 if ((tag & 127) < 64)
14054 {
14055 _bfd_error_handler
90b6238f 14056 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14057 abfd, tag);
14058 bfd_set_error (bfd_error_bad_value);
14059 return FALSE;
14060 }
14061 else
14062 {
14063 _bfd_error_handler
90b6238f 14064 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14065 abfd, tag);
14066 return TRUE;
14067 }
14068}
14069
91e22acd
AS		 14070/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14071 Returns -1 if no architecture could be read. */
14072
14073static int
14074get_secondary_compatible_arch (bfd *abfd)
14075{
14076 obj_attribute *attr =
14077 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14078
14079 /* Note: the tag and its argument below are uleb128 values, though
14080 currently-defined values fit in one byte for each. */
14081 if (attr->s
14082 && attr->s[0] == Tag_CPU_arch
14083 && (attr->s[1] & 128) != 128
14084 && attr->s[2] == 0)
14085 return attr->s[1];
14086
14087 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14088 return -1;
14089}
14090
14091/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14092 The tag is removed if ARCH is -1. */
14093
8e79c3df 14094static void
91e22acd 14095set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14096{
91e22acd
AS		 14097 obj_attribute *attr =
14098 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14099
91e22acd
AS		 14100 if (arch == -1)
14101 {
14102 attr->s = NULL;
14103 return;
8e79c3df 14104 }
91e22acd
AS		 14105
14106 /* Note: the tag and its argument below are uleb128 values, though
14107 currently-defined values fit in one byte for each. */
14108 if (!attr->s)
21d799b5 14109 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14110 attr->s[0] = Tag_CPU_arch;
14111 attr->s[1] = arch;
14112 attr->s[2] = '\0';
8e79c3df
CM		 14113}
14114
91e22acd
AS		 14115/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14116 into account. */
14117
14118static int
14119tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14120 int newtag, int secondary_compat)
8e79c3df 14121{
91e22acd
AS		 14122#define T(X) TAG_CPU_ARCH_##X
14123 int tagl, tagh, result;
14124 const int v6t2[] =
14125 {
14126 T(V6T2), /* PRE_V4. */
14127 T(V6T2), /* V4. */
14128 T(V6T2), /* V4T. */
14129 T(V6T2), /* V5T. */
14130 T(V6T2), /* V5TE. */
14131 T(V6T2), /* V5TEJ. */
14132 T(V6T2), /* V6. */
14133 T(V7), /* V6KZ. */
14134 T(V6T2) /* V6T2. */
14135 };
14136 const int v6k[] =
14137 {
14138 T(V6K), /* PRE_V4. */
14139 T(V6K), /* V4. */
14140 T(V6K), /* V4T. */
14141 T(V6K), /* V5T. */
14142 T(V6K), /* V5TE. */
14143 T(V6K), /* V5TEJ. */
14144 T(V6K), /* V6. */
14145 T(V6KZ), /* V6KZ. */
14146 T(V7), /* V6T2. */
14147 T(V6K) /* V6K. */
14148 };
14149 const int v7[] =
14150 {
14151 T(V7), /* PRE_V4. */
14152 T(V7), /* V4. */
14153 T(V7), /* V4T. */
14154 T(V7), /* V5T. */
14155 T(V7), /* V5TE. */
14156 T(V7), /* V5TEJ. */
14157 T(V7), /* V6. */
14158 T(V7), /* V6KZ. */
14159 T(V7), /* V6T2. */
14160 T(V7), /* V6K. */
14161 T(V7) /* V7. */
14162 };
14163 const int v6_m[] =
14164 {
07d6d2b8
AM		 14165 -1, /* PRE_V4. */
14166 -1, /* V4. */
91e22acd
AS		 14167 T(V6K), /* V4T. */
14168 T(V6K), /* V5T. */
14169 T(V6K), /* V5TE. */
14170 T(V6K), /* V5TEJ. */
14171 T(V6K), /* V6. */
14172 T(V6KZ), /* V6KZ. */
14173 T(V7), /* V6T2. */
14174 T(V6K), /* V6K. */
14175 T(V7), /* V7. */
14176 T(V6_M) /* V6_M. */
14177 };
14178 const int v6s_m[] =
14179 {
07d6d2b8
AM		 14180 -1, /* PRE_V4. */
14181 -1, /* V4. */
91e22acd
AS		 14182 T(V6K), /* V4T. */
14183 T(V6K), /* V5T. */
14184 T(V6K), /* V5TE. */
14185 T(V6K), /* V5TEJ. */
14186 T(V6K), /* V6. */
14187 T(V6KZ), /* V6KZ. */
14188 T(V7), /* V6T2. */
14189 T(V6K), /* V6K. */
14190 T(V7), /* V7. */
14191 T(V6S_M), /* V6_M. */
14192 T(V6S_M) /* V6S_M. */
14193 };
9e3c6df6
PB		 14194 const int v7e_m[] =
14195 {
07d6d2b8
AM		 14196 -1, /* PRE_V4. */
14197 -1, /* V4. */
9e3c6df6
PB		 14198 T(V7E_M), /* V4T. */
14199 T(V7E_M), /* V5T. */
14200 T(V7E_M), /* V5TE. */
14201 T(V7E_M), /* V5TEJ. */
14202 T(V7E_M), /* V6. */
14203 T(V7E_M), /* V6KZ. */
14204 T(V7E_M), /* V6T2. */
14205 T(V7E_M), /* V6K. */
14206 T(V7E_M), /* V7. */
14207 T(V7E_M), /* V6_M. */
14208 T(V7E_M), /* V6S_M. */
14209 T(V7E_M) /* V7E_M. */
14210 };
bca38921
MGD		 14211 const int v8[] =
14212 {
14213 T(V8), /* PRE_V4. */
14214 T(V8), /* V4. */
14215 T(V8), /* V4T. */
14216 T(V8), /* V5T. */
14217 T(V8), /* V5TE. */
14218 T(V8), /* V5TEJ. */
14219 T(V8), /* V6. */
14220 T(V8), /* V6KZ. */
14221 T(V8), /* V6T2. */
14222 T(V8), /* V6K. */
14223 T(V8), /* V7. */
14224 T(V8), /* V6_M. */
14225 T(V8), /* V6S_M. */
14226 T(V8), /* V7E_M. */
14227 T(V8) /* V8. */
14228 };
bff0500d
TP		 14229 const int v8r[] =
14230 {
14231 T(V8R), /* PRE_V4. */
14232 T(V8R), /* V4. */
14233 T(V8R), /* V4T. */
14234 T(V8R), /* V5T. */
14235 T(V8R), /* V5TE. */
14236 T(V8R), /* V5TEJ. */
14237 T(V8R), /* V6. */
14238 T(V8R), /* V6KZ. */
14239 T(V8R), /* V6T2. */
14240 T(V8R), /* V6K. */
14241 T(V8R), /* V7. */
14242 T(V8R), /* V6_M. */
14243 T(V8R), /* V6S_M. */
14244 T(V8R), /* V7E_M. */
14245 T(V8), /* V8. */
14246 T(V8R), /* V8R. */
14247 };
2fd158eb
TP		 14248 const int v8m_baseline[] =
14249 {
14250 -1, /* PRE_V4. */
14251 -1, /* V4. */
14252 -1, /* V4T. */
14253 -1, /* V5T. */
14254 -1, /* V5TE. */
14255 -1, /* V5TEJ. */
14256 -1, /* V6. */
14257 -1, /* V6KZ. */
14258 -1, /* V6T2. */
14259 -1, /* V6K. */
14260 -1, /* V7. */
14261 T(V8M_BASE), /* V6_M. */
14262 T(V8M_BASE), /* V6S_M. */
14263 -1, /* V7E_M. */
14264 -1, /* V8. */
bff0500d 14265 -1, /* V8R. */
2fd158eb
TP		 14266 T(V8M_BASE) /* V8-M BASELINE. */
14267 };
14268 const int v8m_mainline[] =
14269 {
14270 -1, /* PRE_V4. */
14271 -1, /* V4. */
14272 -1, /* V4T. */
14273 -1, /* V5T. */
14274 -1, /* V5TE. */
14275 -1, /* V5TEJ. */
14276 -1, /* V6. */
14277 -1, /* V6KZ. */
14278 -1, /* V6T2. */
14279 -1, /* V6K. */
14280 T(V8M_MAIN), /* V7. */
14281 T(V8M_MAIN), /* V6_M. */
14282 T(V8M_MAIN), /* V6S_M. */
14283 T(V8M_MAIN), /* V7E_M. */
14284 -1, /* V8. */
bff0500d 14285 -1, /* V8R. */
2fd158eb
TP		 14286 T(V8M_MAIN), /* V8-M BASELINE. */
14287 T(V8M_MAIN) /* V8-M MAINLINE. */
14288 };
031254f2
AV		 14289 const int v8_1m_mainline[] =
14290 {
14291 -1, /* PRE_V4. */
14292 -1, /* V4. */
14293 -1, /* V4T. */
14294 -1, /* V5T. */
14295 -1, /* V5TE. */
14296 -1, /* V5TEJ. */
14297 -1, /* V6. */
14298 -1, /* V6KZ. */
14299 -1, /* V6T2. */
14300 -1, /* V6K. */
14301 T(V8_1M_MAIN), /* V7. */
14302 T(V8_1M_MAIN), /* V6_M. */
14303 T(V8_1M_MAIN), /* V6S_M. */
14304 T(V8_1M_MAIN), /* V7E_M. */
14305 -1, /* V8. */
14306 -1, /* V8R. */
14307 T(V8_1M_MAIN), /* V8-M BASELINE. */
14308 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14309 -1, /* Unused (18). */
14310 -1, /* Unused (19). */
14311 -1, /* Unused (20). */
14312 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14313 };
91e22acd
AS		 14314 const int v4t_plus_v6_m[] =
14315 {
14316 -1, /* PRE_V4. */
14317 -1, /* V4. */
14318 T(V4T), /* V4T. */
14319 T(V5T), /* V5T. */
14320 T(V5TE), /* V5TE. */
14321 T(V5TEJ), /* V5TEJ. */
14322 T(V6), /* V6. */
14323 T(V6KZ), /* V6KZ. */
14324 T(V6T2), /* V6T2. */
14325 T(V6K), /* V6K. */
14326 T(V7), /* V7. */
14327 T(V6_M), /* V6_M. */
14328 T(V6S_M), /* V6S_M. */
9e3c6df6 14329 T(V7E_M), /* V7E_M. */
bca38921 14330 T(V8), /* V8. */
bff0500d 14331 -1, /* V8R. */
2fd158eb
TP		 14332 T(V8M_BASE), /* V8-M BASELINE. */
14333 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14334 -1, /* Unused (18). */
14335 -1, /* Unused (19). */
14336 -1, /* Unused (20). */
14337 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14338 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14339 };
14340 const int *comb[] =
14341 {
14342 v6t2,
14343 v6k,
14344 v7,
14345 v6_m,
14346 v6s_m,
9e3c6df6 14347 v7e_m,
bca38921 14348 v8,
bff0500d 14349 v8r,
2fd158eb
TP		 14350 v8m_baseline,
14351 v8m_mainline,
031254f2
AV		 14352 NULL,
14353 NULL,
14354 NULL,
14355 v8_1m_mainline,
91e22acd
AS		 14356 /* Pseudo-architecture. */
14357 v4t_plus_v6_m
14358 };
14359
14360 /* Check we've not got a higher architecture than we know about. */
14361
9e3c6df6 14362 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14363 {
90b6238f 14364 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14365 return -1;
14366 }
14367
14368 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14369
14370 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14371 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14372 oldtag = T(V4T_PLUS_V6_M);
14373
14374 /* And override the new tag if we have a Tag_also_compatible_with on the
14375 input. */
14376
14377 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14378 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14379 newtag = T(V4T_PLUS_V6_M);
14380
14381 tagl = (oldtag < newtag) ? oldtag : newtag;
14382 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14383
14384 /* Architectures before V6KZ add features monotonically. */
14385 if (tagh <= TAG_CPU_ARCH_V6KZ)
14386 return result;
14387
4ed7ed8d 14388 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14389
14390 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14391 as the canonical version. */
14392 if (result == T(V4T_PLUS_V6_M))
14393 {
14394 result = T(V4T);
14395 *secondary_compat_out = T(V6_M);
14396 }
14397 else
14398 *secondary_compat_out = -1;
14399
14400 if (result == -1)
14401 {
90b6238f 14402 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14403 ibfd, oldtag, newtag);
14404 return -1;
14405 }
14406
14407 return result;
14408#undef T
8e79c3df
CM		 14409}
14410
ac56ee8f
MGD		 14411/* Query attributes object to see if integer divide instructions may be
14412 present in an object. */
14413static bfd_boolean
14414elf32_arm_attributes_accept_div (const obj_attribute *attr)
14415{
14416 int arch = attr[Tag_CPU_arch].i;
14417 int profile = attr[Tag_CPU_arch_profile].i;
14418
14419 switch (attr[Tag_DIV_use].i)
14420 {
14421 case 0:
14422 /* Integer divide allowed if instruction contained in archetecture. */
14423 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14424 return TRUE;
14425 else if (arch >= TAG_CPU_ARCH_V7E_M)
14426 return TRUE;
14427 else
14428 return FALSE;
14429
14430 case 1:
14431 /* Integer divide explicitly prohibited. */
14432 return FALSE;
14433
14434 default:
14435 /* Unrecognised case - treat as allowing divide everywhere. */
14436 case 2:
14437 /* Integer divide allowed in ARM state. */
14438 return TRUE;
14439 }
14440}
14441
14442/* Query attributes object to see if integer divide instructions are
14443 forbidden to be in the object. This is not the inverse of
14444 elf32_arm_attributes_accept_div. */
14445static bfd_boolean
14446elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14447{
14448 return attr[Tag_DIV_use].i == 1;
14449}
14450
ee065d83
PB		 14451/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14452 are conflicting attributes. */
906e58ca 14453
ee065d83 14454static bfd_boolean
50e03d47 14455elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14456{
50e03d47 14457 bfd *obfd = info->output_bfd;
104d59d1
JM		 14458 obj_attribute *in_attr;
14459 obj_attribute *out_attr;
ee065d83
PB		 14460 /* Some tags have 0 = don't care, 1 = strong requirement,
14461 2 = weak requirement. */
91e22acd 14462 static const int order_021[3] = {0, 2, 1};
ee065d83 14463 int i;
91e22acd 14464 bfd_boolean result = TRUE;
9274e9de 14465 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14466
3e6b1042
DJ		 14467 /* Skip the linker stubs file. This preserves previous behavior
14468 of accepting unknown attributes in the first input file - but
14469 is that a bug? */
14470 if (ibfd->flags & BFD_LINKER_CREATED)
14471 return TRUE;
14472
9274e9de
TG		 14473 /* Skip any input that hasn't attribute section.
14474 This enables to link object files without attribute section with
14475 any others. */
14476 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14477 return TRUE;
14478
104d59d1 14479 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14480 {
14481 /* This is the first object. Copy the attributes. */
104d59d1 14482 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14483
cd21e546
MGD		 14484 out_attr = elf_known_obj_attributes_proc (obfd);
14485
004ae526
PB		 14486 /* Use the Tag_null value to indicate the attributes have been
14487 initialized. */
cd21e546 14488 out_attr[0].i = 1;
004ae526 14489
cd21e546
MGD		 14490 /* We do not output objects with Tag_MPextension_use_legacy - we move
14491 the attribute's value to Tag_MPextension_use. */
14492 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14493 {
14494 if (out_attr[Tag_MPextension_use].i != 0
14495 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14496 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14497 {
14498 _bfd_error_handler
871b3ab2 14499 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14500 "Tag_MPextension_use attributes"), ibfd);
14501 result = FALSE;
14502 }
14503
14504 out_attr[Tag_MPextension_use] =
14505 out_attr[Tag_MPextension_use_legacy];
14506 out_attr[Tag_MPextension_use_legacy].type = 0;
14507 out_attr[Tag_MPextension_use_legacy].i = 0;
14508 }
14509
14510 return result;
ee065d83
PB		 14511 }
14512
104d59d1
JM		 14513 in_attr = elf_known_obj_attributes_proc (ibfd);
14514 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14515 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14516 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14517 {
5c294fee
TG		 14518 /* Ignore mismatches if the object doesn't use floating point or is
14519 floating point ABI independent. */
14520 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14521 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14522 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14523 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14524 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14525 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14526 {
14527 _bfd_error_handler
871b3ab2 14528 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14529 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14530 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14531 result = FALSE;
ee065d83
PB		 14532 }
14533 }
14534
3de4a297 14535 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14536 {
14537 /* Merge this attribute with existing attributes. */
14538 switch (i)
14539 {
14540 case Tag_CPU_raw_name:
14541 case Tag_CPU_name:
6a631e86 14542 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14543 break;
14544
14545 case Tag_ABI_optimization_goals:
14546 case Tag_ABI_FP_optimization_goals:
14547 /* Use the first value seen. */
14548 break;
14549
14550 case Tag_CPU_arch:
91e22acd
AS		 14551 {
14552 int secondary_compat = -1, secondary_compat_out = -1;
14553 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14554 int arch_attr;
14555 static const char *name_table[] =
14556 {
91e22acd
AS		 14557 /* These aren't real CPU names, but we can't guess
14558 that from the architecture version alone. */
14559 "Pre v4",
14560 "ARM v4",
14561 "ARM v4T",
14562 "ARM v5T",
14563 "ARM v5TE",
14564 "ARM v5TEJ",
14565 "ARM v6",
14566 "ARM v6KZ",
14567 "ARM v6T2",
14568 "ARM v6K",
14569 "ARM v7",
14570 "ARM v6-M",
bca38921 14571 "ARM v6S-M",
2fd158eb
TP		 14572 "ARM v8",
14573 "",
14574 "ARM v8-M.baseline",
14575 "ARM v8-M.mainline",
91e22acd
AS		 14576 };
14577
14578 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14579 secondary_compat = get_secondary_compatible_arch (ibfd);
14580 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14581 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14582 &secondary_compat_out,
14583 in_attr[i].i,
14584 secondary_compat);
14585
14586 /* Return with error if failed to merge. */
14587 if (arch_attr == -1)
14588 return FALSE;
14589
14590 out_attr[i].i = arch_attr;
14591
91e22acd
AS		 14592 set_secondary_compatible_arch (obfd, secondary_compat_out);
14593
14594 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14595 if (out_attr[i].i == saved_out_attr)
14596 ; /* Leave the names alone. */
14597 else if (out_attr[i].i == in_attr[i].i)
14598 {
14599 /* The output architecture has been changed to match the
14600 input architecture. Use the input names. */
14601 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14602 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14603 : NULL;
14604 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14605 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14606 : NULL;
14607 }
14608 else
14609 {
14610 out_attr[Tag_CPU_name].s = NULL;
14611 out_attr[Tag_CPU_raw_name].s = NULL;
14612 }
14613
14614 /* If we still don't have a value for Tag_CPU_name,
14615 make one up now. Tag_CPU_raw_name remains blank. */
14616 if (out_attr[Tag_CPU_name].s == NULL
14617 && out_attr[i].i < ARRAY_SIZE (name_table))
14618 out_attr[Tag_CPU_name].s =
14619 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14620 }
14621 break;
14622
ee065d83
PB		 14623 case Tag_ARM_ISA_use:
14624 case Tag_THUMB_ISA_use:
ee065d83 14625 case Tag_WMMX_arch:
91e22acd
AS		 14626 case Tag_Advanced_SIMD_arch:
14627 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14628 case Tag_ABI_FP_rounding:
ee065d83
PB		 14629 case Tag_ABI_FP_exceptions:
14630 case Tag_ABI_FP_user_exceptions:
14631 case Tag_ABI_FP_number_model:
75375b3e 14632 case Tag_FP_HP_extension:
91e22acd
AS		 14633 case Tag_CPU_unaligned_access:
14634 case Tag_T2EE_use:
91e22acd 14635 case Tag_MPextension_use:
a7ad558c 14636 case Tag_MVE_arch:
ee065d83
PB		 14637 /* Use the largest value specified. */
14638 if (in_attr[i].i > out_attr[i].i)
14639 out_attr[i].i = in_attr[i].i;
14640 break;
14641
75375b3e 14642 case Tag_ABI_align_preserved:
91e22acd
AS		 14643 case Tag_ABI_PCS_RO_data:
14644 /* Use the smallest value specified. */
14645 if (in_attr[i].i < out_attr[i].i)
14646 out_attr[i].i = in_attr[i].i;
14647 break;
14648
75375b3e 14649 case Tag_ABI_align_needed:
91e22acd 14650 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14651 && (in_attr[Tag_ABI_align_preserved].i == 0
14652 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14653 {
91e22acd
AS		 14654 /* This error message should be enabled once all non-conformant
14655 binaries in the toolchain have had the attributes set
14656 properly.
ee065d83 14657 _bfd_error_handler
871b3ab2 14658 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14659 obfd, ibfd);
14660 result = FALSE; */
ee065d83 14661 }
91e22acd
AS		 14662 /* Fall through. */
14663 case Tag_ABI_FP_denormal:
14664 case Tag_ABI_PCS_GOT_use:
14665 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14666 value if greater than 2 (for future-proofing). */
14667 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14668 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14669 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14670 out_attr[i].i = in_attr[i].i;
14671 break;
91e22acd 14672
75375b3e
MGD		 14673 case Tag_Virtualization_use:
14674 /* The virtualization tag effectively stores two bits of
14675 information: the intended use of TrustZone (in bit 0), and the
14676 intended use of Virtualization (in bit 1). */
14677 if (out_attr[i].i == 0)
14678 out_attr[i].i = in_attr[i].i;
14679 else if (in_attr[i].i != 0
14680 && in_attr[i].i != out_attr[i].i)
14681 {
14682 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14683 out_attr[i].i = 3;
14684 else
14685 {
14686 _bfd_error_handler
871b3ab2
AM		 14687 (_("error: %pB: unable to merge virtualization attributes "
14688 "with %pB"),
75375b3e
MGD		 14689 obfd, ibfd);
14690 result = FALSE;
14691 }
14692 }
14693 break;
91e22acd
AS		 14694
14695 case Tag_CPU_arch_profile:
14696 if (out_attr[i].i != in_attr[i].i)
14697 {
14698 /* 0 will merge with anything.
14699 'A' and 'S' merge to 'A'.
14700 'R' and 'S' merge to 'R'.
99059e56 14701 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14702 if (out_attr[i].i == 0
14703 || (out_attr[i].i == 'S'
14704 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14705 out_attr[i].i = in_attr[i].i;
14706 else if (in_attr[i].i == 0
14707 || (in_attr[i].i == 'S'
14708 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14709 ; /* Do nothing. */
91e22acd
AS		 14710 else
14711 {
14712 _bfd_error_handler
90b6238f 14713 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14714 ibfd,
14715 in_attr[i].i ? in_attr[i].i : '0',
14716 out_attr[i].i ? out_attr[i].i : '0');
14717 result = FALSE;
14718 }
14719 }
14720 break;
15afaa63
TP		 14721
14722 case Tag_DSP_extension:
14723 /* No need to change output value if any of:
14724 - pre (<=) ARMv5T input architecture (do not have DSP)
14725 - M input profile not ARMv7E-M and do not have DSP. */
14726 if (in_attr[Tag_CPU_arch].i <= 3
14727 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14728 && in_attr[Tag_CPU_arch].i != 13
14729 && in_attr[i].i == 0))
14730 ; /* Do nothing. */
14731 /* Output value should be 0 if DSP part of architecture, ie.
14732 - post (>=) ARMv5te architecture output
14733 - A, R or S profile output or ARMv7E-M output architecture. */
14734 else if (out_attr[Tag_CPU_arch].i >= 4
14735 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14736 || out_attr[Tag_CPU_arch_profile].i == 'R'
14737 || out_attr[Tag_CPU_arch_profile].i == 'S'
14738 || out_attr[Tag_CPU_arch].i == 13))
14739 out_attr[i].i = 0;
14740 /* Otherwise, DSP instructions are added and not part of output
14741 architecture. */
14742 else
14743 out_attr[i].i = 1;
14744 break;
14745
75375b3e 14746 case Tag_FP_arch:
62f3b8c8 14747 {
4547cb56
NC		 14748 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14749 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14750 when it's 0. It might mean absence of FP hardware if
99654aaf 14751 Tag_FP_arch is zero. */
4547cb56 14752
a715796b 14753#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14754 static const struct
14755 {
14756 int ver;
14757 int regs;
bca38921 14758 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14759 {
14760 {0, 0},
14761 {1, 16},
14762 {2, 16},
14763 {3, 32},
14764 {3, 16},
14765 {4, 32},
bca38921 14766 {4, 16},
a715796b
TG		 14767 {8, 32},
14768 {8, 16}
62f3b8c8
PB		 14769 };
14770 int ver;
14771 int regs;
14772 int newval;
14773
4547cb56
NC		 14774 /* If the output has no requirement about FP hardware,
14775 follow the requirement of the input. */
14776 if (out_attr[i].i == 0)
14777 {
4ec192e6
RE		 14778 /* This assert is still reasonable, we shouldn't
14779 produce the suspicious build attribute
14780 combination (See below for in_attr). */
4547cb56
NC		 14781 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14782 out_attr[i].i = in_attr[i].i;
14783 out_attr[Tag_ABI_HardFP_use].i
14784 = in_attr[Tag_ABI_HardFP_use].i;
14785 break;
14786 }
14787 /* If the input has no requirement about FP hardware, do
14788 nothing. */
14789 else if (in_attr[i].i == 0)
14790 {
4ec192e6
RE		 14791 /* We used to assert that Tag_ABI_HardFP_use was
14792 zero here, but we should never assert when
14793 consuming an object file that has suspicious
14794 build attributes. The single precision variant
14795 of 'no FP architecture' is still 'no FP
14796 architecture', so we just ignore the tag in this
14797 case. */
4547cb56
NC		 14798 break;
14799 }
14800
14801 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14802 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14803
14804 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14805 do nothing. */
14806 if (in_attr[Tag_ABI_HardFP_use].i == 0
14807 && out_attr[Tag_ABI_HardFP_use].i == 0)
14808 ;
14809 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14810 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14811 else if (in_attr[Tag_ABI_HardFP_use].i
14812 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14813 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14814
14815 /* Now we can handle Tag_FP_arch. */
14816
bca38921
MGD		 14817 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14818 pick the biggest. */
14819 if (in_attr[i].i >= VFP_VERSION_COUNT
14820 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14821 {
14822 out_attr[i] = in_attr[i];
14823 break;
14824 }
14825 /* The output uses the superset of input features
14826 (ISA version) and registers. */
14827 ver = vfp_versions[in_attr[i].i].ver;
14828 if (ver < vfp_versions[out_attr[i].i].ver)
14829 ver = vfp_versions[out_attr[i].i].ver;
14830 regs = vfp_versions[in_attr[i].i].regs;
14831 if (regs < vfp_versions[out_attr[i].i].regs)
14832 regs = vfp_versions[out_attr[i].i].regs;
14833 /* This assumes all possible supersets are also a valid
99059e56 14834 options. */
bca38921 14835 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14836 {
14837 if (regs == vfp_versions[newval].regs
14838 && ver == vfp_versions[newval].ver)
14839 break;
14840 }
14841 out_attr[i].i = newval;
14842 }
b1cc4aeb 14843 break;
ee065d83
PB		 14844 case Tag_PCS_config:
14845 if (out_attr[i].i == 0)
14846 out_attr[i].i = in_attr[i].i;
b6009aca 14847 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14848 {
14849 /* It's sometimes ok to mix different configs, so this is only
99059e56 14850 a warning. */
ee065d83 14851 _bfd_error_handler
90b6238f 14852 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14853 }
14854 break;
14855 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14856 if (in_attr[i].i != out_attr[i].i
14857 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14858 && in_attr[i].i != AEABI_R9_unused)
14859 {
14860 _bfd_error_handler
90b6238f 14861 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14862 result = FALSE;
ee065d83
PB		 14863 }
14864 if (out_attr[i].i == AEABI_R9_unused)
14865 out_attr[i].i = in_attr[i].i;
14866 break;
14867 case Tag_ABI_PCS_RW_data:
14868 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14869 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14870 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14871 {
14872 _bfd_error_handler
871b3ab2 14873 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14874 ibfd);
91e22acd 14875 result = FALSE;
ee065d83
PB		 14876 }
14877 /* Use the smallest value specified. */
14878 if (in_attr[i].i < out_attr[i].i)
14879 out_attr[i].i = in_attr[i].i;
14880 break;
ee065d83 14881 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14882 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14883 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14884 {
14885 _bfd_error_handler
871b3ab2 14886 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14887 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14888 }
a9dc9481 14889 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14890 out_attr[i].i = in_attr[i].i;
14891 break;
ee065d83
PB		 14892 case Tag_ABI_enum_size:
14893 if (in_attr[i].i != AEABI_enum_unused)
14894 {
14895 if (out_attr[i].i == AEABI_enum_unused
14896 || out_attr[i].i == AEABI_enum_forced_wide)
14897 {
14898 /* The existing object is compatible with anything.
14899 Use whatever requirements the new object has. */
14900 out_attr[i].i = in_attr[i].i;
14901 }
14902 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14903 && out_attr[i].i != in_attr[i].i
0ffa91dd 14904 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14905 {
91e22acd 14906 static const char *aeabi_enum_names[] =
bf21ed78 14907 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14908 const char *in_name =
14909 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14910 ? aeabi_enum_names[in_attr[i].i]
14911 : "<unknown>";
14912 const char *out_name =
14913 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14914 ? aeabi_enum_names[out_attr[i].i]
14915 : "<unknown>";
ee065d83 14916 _bfd_error_handler
871b3ab2 14917 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14918 ibfd, in_name, out_name);
ee065d83
PB		 14919 }
14920 }
14921 break;
14922 case Tag_ABI_VFP_args:
14923 /* Aready done. */
14924 break;
14925 case Tag_ABI_WMMX_args:
14926 if (in_attr[i].i != out_attr[i].i)
14927 {
14928 _bfd_error_handler
871b3ab2 14929 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14930 ibfd, obfd);
91e22acd 14931 result = FALSE;
ee065d83
PB		 14932 }
14933 break;
7b86a9fa
AS		 14934 case Tag_compatibility:
14935 /* Merged in target-independent code. */
14936 break;
91e22acd 14937 case Tag_ABI_HardFP_use:
4547cb56 14938 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14939 break;
14940 case Tag_ABI_FP_16bit_format:
14941 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14942 {
14943 if (in_attr[i].i != out_attr[i].i)
14944 {
14945 _bfd_error_handler
871b3ab2 14946 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14947 ibfd, obfd);
14948 result = FALSE;
14949 }
14950 }
14951 if (in_attr[i].i != 0)
14952 out_attr[i].i = in_attr[i].i;
14953 break;
7b86a9fa 14954
cd21e546 14955 case Tag_DIV_use:
ac56ee8f
MGD		 14956 /* A value of zero on input means that the divide instruction may
14957 be used if available in the base architecture as specified via
14958 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14959 the user did not want divide instructions. A value of 2
14960 explicitly means that divide instructions were allowed in ARM
14961 and Thumb state. */
14962 if (in_attr[i].i == out_attr[i].i)
14963 /* Do nothing. */ ;
14964 else if (elf32_arm_attributes_forbid_div (in_attr)
14965 && !elf32_arm_attributes_accept_div (out_attr))
14966 out_attr[i].i = 1;
14967 else if (elf32_arm_attributes_forbid_div (out_attr)
14968 && elf32_arm_attributes_accept_div (in_attr))
14969 out_attr[i].i = in_attr[i].i;
14970 else if (in_attr[i].i == 2)
14971 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14972 break;
14973
14974 case Tag_MPextension_use_legacy:
14975 /* We don't output objects with Tag_MPextension_use_legacy - we
14976 move the value to Tag_MPextension_use. */
14977 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14978 {
14979 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14980 {
14981 _bfd_error_handler
871b3ab2 14982 (_("%pB has both the current and legacy "
b38cadfb 14983 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14984 ibfd);
14985 result = FALSE;
14986 }
14987 }
14988
14989 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14990 out_attr[Tag_MPextension_use] = in_attr[i];
14991
14992 break;
14993
91e22acd 14994 case Tag_nodefaults:
2d0bb761
AS		 14995 /* This tag is set if it exists, but the value is unused (and is
14996 typically zero). We don't actually need to do anything here -
14997 the merge happens automatically when the type flags are merged
14998 below. */
91e22acd
AS		 14999 break;
15000 case Tag_also_compatible_with:
15001 /* Already done in Tag_CPU_arch. */
15002 break;
15003 case Tag_conformance:
15004 /* Keep the attribute if it matches. Throw it away otherwise.
15005 No attribute means no claim to conform. */
15006 if (!in_attr[i].s || !out_attr[i].s
15007 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15008 out_attr[i].s = NULL;
15009 break;
3cfad14c 15010
91e22acd 15011 default:
e8b36cd1
JM		 15012 result
15013 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15014 }
15015
15016 /* If out_attr was copied from in_attr then it won't have a type yet. */
15017 if (in_attr[i].type && !out_attr[i].type)
15018 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15019 }
15020
104d59d1 15021 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15022 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15023 return FALSE;
ee065d83 15024
104d59d1 15025 /* Check for any attributes not known on ARM. */
e8b36cd1 15026 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15027
91e22acd 15028 return result;
252b5132
RH		 15029}
15030
3a4a14e9
PB		 15031
15032/* Return TRUE if the two EABI versions are incompatible. */
15033
15034static bfd_boolean
15035elf32_arm_versions_compatible (unsigned iver, unsigned over)
15036{
15037 /* v4 and v5 are the same spec before and after it was released,
15038 so allow mixing them. */
15039 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15040 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15041 return TRUE;
15042
15043 return (iver == over);
15044}
15045
252b5132
RH		 15046/* Merge backend specific data from an object file to the output
15047 object file when linking. */
9b485d32 15048
b34976b6 15049static bfd_boolean
50e03d47 15050elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15051
9b485d32
NC		 15052/* Display the flags field. */
15053
b34976b6 15054static bfd_boolean
57e8b36a 15055elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15056{
fc830a83
NC		 15057 FILE * file = (FILE *) ptr;
15058 unsigned long flags;
252b5132
RH		 15059
15060 BFD_ASSERT (abfd != NULL && ptr != NULL);
15061
15062 /* Print normal ELF private data. */
15063 _bfd_elf_print_private_bfd_data (abfd, ptr);
15064
fc830a83 15065 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15066 /* Ignore init flag - it may not be set, despite the flags field
15067 containing valid data. */
252b5132 15068
9b485d32 15069 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15070
fc830a83
NC		 15071 switch (EF_ARM_EABI_VERSION (flags))
15072 {
15073 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15074 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15075 official ARM ELF extended ABI. Hence they are only decoded if
15076 the EABI version is not set. */
fd2ec330 15077 if (flags & EF_ARM_INTERWORK)
9b485d32 15078 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15079
fd2ec330 15080 if (flags & EF_ARM_APCS_26)
6c571f00 15081 fprintf (file, " [APCS-26]");
fc830a83 15082 else
6c571f00 15083 fprintf (file, " [APCS-32]");
9a5aca8c 15084
96a846ea
RE		 15085 if (flags & EF_ARM_VFP_FLOAT)
15086 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15087 else if (flags & EF_ARM_MAVERICK_FLOAT)
15088 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15089 else
15090 fprintf (file, _(" [FPA float format]"));
15091
fd2ec330 15092 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15093 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15094
fd2ec330 15095 if (flags & EF_ARM_PIC)
9b485d32 15096 fprintf (file, _(" [position independent]"));
fc830a83 15097
fd2ec330 15098 if (flags & EF_ARM_NEW_ABI)
9b485d32 15099 fprintf (file, _(" [new ABI]"));
9a5aca8c 15100
fd2ec330 15101 if (flags & EF_ARM_OLD_ABI)
9b485d32 15102 fprintf (file, _(" [old ABI]"));
9a5aca8c 15103
fd2ec330 15104 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15105 fprintf (file, _(" [software FP]"));
9a5aca8c 15106
96a846ea
RE		 15107 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15108 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15109 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15110 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15111 break;
9a5aca8c 15112
fc830a83 15113 case EF_ARM_EABI_VER1:
9b485d32 15114 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15115
fc830a83 15116 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15117 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15118 else
9b485d32 15119 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15120
fc830a83
NC		 15121 flags &= ~ EF_ARM_SYMSARESORTED;
15122 break;
9a5aca8c 15123
fd2ec330
PB		 15124 case EF_ARM_EABI_VER2:
15125 fprintf (file, _(" [Version2 EABI]"));
15126
15127 if (flags & EF_ARM_SYMSARESORTED)
15128 fprintf (file, _(" [sorted symbol table]"));
15129 else
15130 fprintf (file, _(" [unsorted symbol table]"));
15131
15132 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15133 fprintf (file, _(" [dynamic symbols use segment index]"));
15134
15135 if (flags & EF_ARM_MAPSYMSFIRST)
15136 fprintf (file, _(" [mapping symbols precede others]"));
15137
99e4ae17 15138 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15139 | EF_ARM_MAPSYMSFIRST);
15140 break;
15141
d507cf36
PB		 15142 case EF_ARM_EABI_VER3:
15143 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15144 break;
15145
15146 case EF_ARM_EABI_VER4:
15147 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15148 goto eabi;
d507cf36 15149
3a4a14e9
PB		 15150 case EF_ARM_EABI_VER5:
15151 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15152
15153 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15154 fprintf (file, _(" [soft-float ABI]"));
15155
15156 if (flags & EF_ARM_ABI_FLOAT_HARD)
15157 fprintf (file, _(" [hard-float ABI]"));
15158
15159 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15160
3a4a14e9 15161 eabi:
d507cf36
PB		 15162 if (flags & EF_ARM_BE8)
15163 fprintf (file, _(" [BE8]"));
15164
15165 if (flags & EF_ARM_LE8)
15166 fprintf (file, _(" [LE8]"));
15167
15168 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15169 break;
15170
fc830a83 15171 default:
9b485d32 15172 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15173 break;
15174 }
252b5132 15175
fc830a83 15176 flags &= ~ EF_ARM_EABIMASK;
252b5132 15177
fc830a83 15178 if (flags & EF_ARM_RELEXEC)
9b485d32 15179 fprintf (file, _(" [relocatable executable]"));
252b5132 15180
18a20338
CL		 15181 if (flags & EF_ARM_PIC)
15182 fprintf (file, _(" [position independent]"));
15183
15184 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15185 fprintf (file, _(" [FDPIC ABI supplement]"));
15186
15187 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15188
15189 if (flags)
9b485d32 15190 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15191
252b5132
RH		 15192 fputc ('\n', file);
15193
b34976b6 15194 return TRUE;
252b5132
RH		 15195}
15196
15197static int
57e8b36a 15198elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15199{
2f0ca46a
NC		 15200 switch (ELF_ST_TYPE (elf_sym->st_info))
15201 {
15202 case STT_ARM_TFUNC:
15203 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15204
2f0ca46a
NC		 15205 case STT_ARM_16BIT:
15206 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15207 This allows us to distinguish between data used by Thumb instructions
15208 and non-data (which is probably code) inside Thumb regions of an
15209 executable. */
1a0eb693 15210 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15211 return ELF_ST_TYPE (elf_sym->st_info);
15212 break;
9a5aca8c 15213
ce855c42
NC		 15214 default:
15215 break;
2f0ca46a
NC		 15216 }
15217
15218 return type;
252b5132 15219}
f21f3fe0 15220
252b5132 15221static asection *
07adf181
AM		 15222elf32_arm_gc_mark_hook (asection *sec,
15223 struct bfd_link_info *info,
15224 Elf_Internal_Rela *rel,
15225 struct elf_link_hash_entry *h,
15226 Elf_Internal_Sym *sym)
252b5132
RH		 15227{
15228 if (h != NULL)
07adf181 15229 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15230 {
15231 case R_ARM_GNU_VTINHERIT:
15232 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15233 return NULL;
15234 }
9ad5cbcf 15235
07adf181 15236 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15237}
15238
780a67af
NC		 15239/* Look through the relocs for a section during the first phase. */
15240
b34976b6 15241static bfd_boolean
57e8b36a
NC		 15242elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15243 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15244{
b34976b6
AM		 15245 Elf_Internal_Shdr *symtab_hdr;
15246 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15247 const Elf_Internal_Rela *rel;
15248 const Elf_Internal_Rela *rel_end;
15249 bfd *dynobj;
5e681ec4 15250 asection *sreloc;
5e681ec4 15251 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15252 bfd_boolean call_reloc_p;
15253 bfd_boolean may_become_dynamic_p;
15254 bfd_boolean may_need_local_target_p;
ce98a316 15255 unsigned long nsyms;
9a5aca8c 15256
0e1862bb 15257 if (bfd_link_relocatable (info))
b34976b6 15258 return TRUE;
9a5aca8c 15259
0ffa91dd
NC		 15260 BFD_ASSERT (is_arm_elf (abfd));
15261
5e681ec4 15262 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15263 if (htab == NULL)
15264 return FALSE;
15265
5e681ec4 15266 sreloc = NULL;
9a5aca8c 15267
67687978
PB		 15268 /* Create dynamic sections for relocatable executables so that we can
15269 copy relocations. */
15270 if (htab->root.is_relocatable_executable
15271 && ! htab->root.dynamic_sections_created)
15272 {
15273 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15274 return FALSE;
15275 }
15276
cbc704f3
RS		 15277 if (htab->root.dynobj == NULL)
15278 htab->root.dynobj = abfd;
34e77a92
RS		 15279 if (!create_ifunc_sections (info))
15280 return FALSE;
cbc704f3
RS		 15281
15282 dynobj = htab->root.dynobj;
15283
0ffa91dd 15284 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15285 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15286 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15287
252b5132
RH		 15288 rel_end = relocs + sec->reloc_count;
15289 for (rel = relocs; rel < rel_end; rel++)
15290 {
34e77a92 15291 Elf_Internal_Sym *isym;
252b5132 15292 struct elf_link_hash_entry *h;
b7693d02 15293 struct elf32_arm_link_hash_entry *eh;
d42c267e 15294 unsigned int r_symndx;
eb043451 15295 int r_type;
9a5aca8c 15296
252b5132 15297 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15298 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15299 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15300
ce98a316
NC		 15301 if (r_symndx >= nsyms
15302 /* PR 9934: It is possible to have relocations that do not
15303 refer to symbols, thus it is also possible to have an
15304 object file containing relocations but no symbol table. */
cf35638d 15305 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15306 {
871b3ab2 15307 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15308 r_symndx);
ba93b8ac
DJ		 15309 return FALSE;
15310 }
15311
34e77a92
RS		 15312 h = NULL;
15313 isym = NULL;
15314 if (nsyms > 0)
973a3492 15315 {
34e77a92
RS		 15316 if (r_symndx < symtab_hdr->sh_info)
15317 {
15318 /* A local symbol. */
15319 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15320 abfd, r_symndx);
15321 if (isym == NULL)
15322 return FALSE;
15323 }
15324 else
15325 {
15326 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15327 while (h->root.type == bfd_link_hash_indirect
15328 || h->root.type == bfd_link_hash_warning)
15329 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15330 }
973a3492 15331 }
9a5aca8c 15332
b7693d02
DJ		 15333 eh = (struct elf32_arm_link_hash_entry *) h;
15334
f6e32f6d
RS		 15335 call_reloc_p = FALSE;
15336 may_become_dynamic_p = FALSE;
15337 may_need_local_target_p = FALSE;
15338
0855e32b
NS		 15339 /* Could be done earlier, if h were already available. */
15340 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15341 switch (r_type)
99059e56 15342 {
e8b09b87
CL		 15343 case R_ARM_GOTOFFFUNCDESC:
15344 {
15345 if (h == NULL)
15346 {
15347 if (!elf32_arm_allocate_local_sym_info (abfd))
15348 return FALSE;
15349 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15350 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15351 }
15352 else
15353 {
15354 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15355 }
15356 }
15357 break;
15358
15359 case R_ARM_GOTFUNCDESC:
15360 {
15361 if (h == NULL)
15362 {
15363 /* Such a relocation is not supposed to be generated
15364 by gcc on a static function. */
15365 /* Anyway if needed it could be handled. */
15366 abort();
15367 }
15368 else
15369 {
15370 eh->fdpic_cnts.gotfuncdesc_cnt++;
15371 }
15372 }
15373 break;
15374
15375 case R_ARM_FUNCDESC:
15376 {
15377 if (h == NULL)
15378 {
15379 if (!elf32_arm_allocate_local_sym_info (abfd))
15380 return FALSE;
15381 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15382 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15383 }
15384 else
15385 {
15386 eh->fdpic_cnts.funcdesc_cnt++;
15387 }
15388 }
15389 break;
15390
5e681ec4 15391 case R_ARM_GOT32:
eb043451 15392 case R_ARM_GOT_PREL:
ba93b8ac 15393 case R_ARM_TLS_GD32:
5c5a4843 15394 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15395 case R_ARM_TLS_IE32:
5c5a4843 15396 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15397 case R_ARM_TLS_GOTDESC:
15398 case R_ARM_TLS_DESCSEQ:
15399 case R_ARM_THM_TLS_DESCSEQ:
15400 case R_ARM_TLS_CALL:
15401 case R_ARM_THM_TLS_CALL:
5e681ec4 15402 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15403 {
15404 int tls_type, old_tls_type;
5e681ec4 15405
ba93b8ac
DJ		 15406 switch (r_type)
15407 {
15408 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15409 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15410
ba93b8ac 15411 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15412 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15413
0855e32b
NS		 15414 case R_ARM_TLS_GOTDESC:
15415 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15416 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15417 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15418
ba93b8ac
DJ		 15419 default: tls_type = GOT_NORMAL; break;
15420 }
252b5132 15421
0e1862bb 15422 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15423 info->flags |= DF_STATIC_TLS;
15424
ba93b8ac
DJ		 15425 if (h != NULL)
15426 {
15427 h->got.refcount++;
15428 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15429 }
15430 else
15431 {
ba93b8ac 15432 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15433 if (!elf32_arm_allocate_local_sym_info (abfd))
15434 return FALSE;
15435 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15436 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15437 }
15438
0855e32b 15439 /* If a variable is accessed with both tls methods, two
99059e56 15440 slots may be created. */
0855e32b
NS		 15441 if (GOT_TLS_GD_ANY_P (old_tls_type)
15442 && GOT_TLS_GD_ANY_P (tls_type))
15443 tls_type |= old_tls_type;
15444
15445 /* We will already have issued an error message if there
15446 is a TLS/non-TLS mismatch, based on the symbol
15447 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15448 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15449 && tls_type != GOT_NORMAL)
15450 tls_type |= old_tls_type;
15451
0855e32b 15452 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15453 method, we're able to relax. Turn off the GDESC flag,
15454 without messing up with any other kind of tls types
6a631e86 15455 that may be involved. */
0855e32b
NS		 15456 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15457 tls_type &= ~GOT_TLS_GDESC;
15458
ba93b8ac
DJ		 15459 if (old_tls_type != tls_type)
15460 {
15461 if (h != NULL)
15462 elf32_arm_hash_entry (h)->tls_type = tls_type;
15463 else
15464 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15465 }
15466 }
8029a119 15467 /* Fall through. */
ba93b8ac
DJ		 15468
15469 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15470 case R_ARM_TLS_LDM32_FDPIC:
15471 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15472 htab->tls_ldm_got.refcount++;
8029a119 15473 /* Fall through. */
252b5132 15474
c19d1205 15475 case R_ARM_GOTOFF32:
5e681ec4 15476 case R_ARM_GOTPC:
cbc704f3
RS		 15477 if (htab->root.sgot == NULL
15478 && !create_got_section (htab->root.dynobj, info))
15479 return FALSE;
252b5132
RH		 15480 break;
15481
252b5132 15482 case R_ARM_PC24:
7359ea65 15483 case R_ARM_PLT32:
5b5bb741
PB		 15484 case R_ARM_CALL:
15485 case R_ARM_JUMP24:
eb043451 15486 case R_ARM_PREL31:
c19d1205 15487 case R_ARM_THM_CALL:
bd97cb95
DJ		 15488 case R_ARM_THM_JUMP24:
15489 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15490 call_reloc_p = TRUE;
15491 may_need_local_target_p = TRUE;
15492 break;
15493
15494 case R_ARM_ABS12:
15495 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15496 ldr __GOTT_INDEX__ offsets. */
90c14f0c 15497 if (htab->root.target_os != is_vxworks)
f6e32f6d
RS		 15498 {
15499 may_need_local_target_p = TRUE;
15500 break;
15501 }
aebf9be7 15502 else goto jump_over;
9eaff861 15503
f6e32f6d 15504 /* Fall through. */
39623e12 15505
96c23d59
JM		 15506 case R_ARM_MOVW_ABS_NC:
15507 case R_ARM_MOVT_ABS:
15508 case R_ARM_THM_MOVW_ABS_NC:
15509 case R_ARM_THM_MOVT_ABS:
0e1862bb 15510 if (bfd_link_pic (info))
96c23d59 15511 {
4eca0228 15512 _bfd_error_handler
871b3ab2 15513 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15514 abfd, elf32_arm_howto_table_1[r_type].name,
15515 (h) ? h->root.root.string : "a local symbol");
15516 bfd_set_error (bfd_error_bad_value);
15517 return FALSE;
15518 }
15519
15520 /* Fall through. */
39623e12
PB		 15521 case R_ARM_ABS32:
15522 case R_ARM_ABS32_NOI:
aebf9be7 15523 jump_over:
0e1862bb 15524 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15525 {
15526 h->pointer_equality_needed = 1;
15527 }
15528 /* Fall through. */
39623e12
PB		 15529 case R_ARM_REL32:
15530 case R_ARM_REL32_NOI:
b6895b4f
PB		 15531 case R_ARM_MOVW_PREL_NC:
15532 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15533 case R_ARM_THM_MOVW_PREL_NC:
15534 case R_ARM_THM_MOVT_PREL:
39623e12 15535
b7693d02 15536 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15537 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15538 || htab->fdpic_p)
34e77a92
RS		 15539 && (sec->flags & SEC_ALLOC) != 0)
15540 {
15541 if (h == NULL
469a3493 15542 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15543 {
15544 /* In shared libraries and relocatable executables,
15545 we treat local relative references as calls;
15546 see the related SYMBOL_CALLS_LOCAL code in
15547 allocate_dynrelocs. */
15548 call_reloc_p = TRUE;
15549 may_need_local_target_p = TRUE;
15550 }
15551 else
15552 /* We are creating a shared library or relocatable
15553 executable, and this is a reloc against a global symbol,
15554 or a non-PC-relative reloc against a local symbol.
15555 We may need to copy the reloc into the output. */
15556 may_become_dynamic_p = TRUE;
15557 }
f6e32f6d
RS		 15558 else
15559 may_need_local_target_p = TRUE;
252b5132
RH		 15560 break;
15561
99059e56
RM		 15562 /* This relocation describes the C++ object vtable hierarchy.
15563 Reconstruct it for later use during GC. */
15564 case R_ARM_GNU_VTINHERIT:
15565 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15566 return FALSE;
15567 break;
15568
15569 /* This relocation describes which C++ vtable entries are actually
15570 used. Record for later use during GC. */
15571 case R_ARM_GNU_VTENTRY:
a0ea3a14 15572 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15573 return FALSE;
15574 break;
15575 }
f6e32f6d
RS		 15576
15577 if (h != NULL)
15578 {
15579 if (call_reloc_p)
15580 /* We may need a .plt entry if the function this reloc
15581 refers to is in a different object, regardless of the
15582 symbol's type. We can't tell for sure yet, because
15583 something later might force the symbol local. */
15584 h->needs_plt = 1;
15585 else if (may_need_local_target_p)
15586 /* If this reloc is in a read-only section, we might
15587 need a copy reloc. We can't check reliably at this
15588 stage whether the section is read-only, as input
15589 sections have not yet been mapped to output sections.
15590 Tentatively set the flag for now, and correct in
15591 adjust_dynamic_symbol. */
15592 h->non_got_ref = 1;
15593 }
15594
34e77a92
RS		 15595 if (may_need_local_target_p
15596 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15597 {
34e77a92
RS		 15598 union gotplt_union *root_plt;
15599 struct arm_plt_info *arm_plt;
15600 struct arm_local_iplt_info *local_iplt;
15601
15602 if (h != NULL)
15603 {
15604 root_plt = &h->plt;
15605 arm_plt = &eh->plt;
15606 }
15607 else
15608 {
15609 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15610 if (local_iplt == NULL)
15611 return FALSE;
15612 root_plt = &local_iplt->root;
15613 arm_plt = &local_iplt->arm;
15614 }
15615
f6e32f6d
RS		 15616 /* If the symbol is a function that doesn't bind locally,
15617 this relocation will need a PLT entry. */
a8c887dd
NC		 15618 if (root_plt->refcount != -1)
15619 root_plt->refcount += 1;
34e77a92
RS		 15620
15621 if (!call_reloc_p)
15622 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15623
15624 /* It's too early to use htab->use_blx here, so we have to
15625 record possible blx references separately from
15626 relocs that definitely need a thumb stub. */
15627
15628 if (r_type == R_ARM_THM_CALL)
34e77a92 15629 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15630
15631 if (r_type == R_ARM_THM_JUMP24
15632 || r_type == R_ARM_THM_JUMP19)
34e77a92 15633 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15634 }
15635
15636 if (may_become_dynamic_p)
15637 {
15638 struct elf_dyn_relocs *p, **head;
15639
15640 /* Create a reloc section in dynobj. */
15641 if (sreloc == NULL)
15642 {
15643 sreloc = _bfd_elf_make_dynamic_reloc_section
15644 (sec, dynobj, 2, abfd, ! htab->use_rel);
15645
15646 if (sreloc == NULL)
15647 return FALSE;
15648
15649 /* BPABI objects never have dynamic relocations mapped. */
90c14f0c 15650 if (htab->root.target_os == is_symbian)
f6e32f6d
RS		 15651 {
15652 flagword flags;
15653
fd361982 15654 flags = bfd_section_flags (sreloc);
f6e32f6d 15655 flags &= ~(SEC_LOAD | SEC_ALLOC);
fd361982 15656 bfd_set_section_flags (sreloc, flags);
f6e32f6d
RS		 15657 }
15658 }
15659
15660 /* If this is a global symbol, count the number of
15661 relocations we need for this symbol. */
15662 if (h != NULL)
190eb1dd 15663 head = &h->dyn_relocs;
f6e32f6d
RS		 15664 else
15665 {
34e77a92
RS		 15666 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15667 if (head == NULL)
f6e32f6d 15668 return FALSE;
f6e32f6d
RS		 15669 }
15670
15671 p = *head;
15672 if (p == NULL || p->sec != sec)
15673 {
986f0783 15674 size_t amt = sizeof *p;
f6e32f6d
RS		 15675
15676 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15677 if (p == NULL)
15678 return FALSE;
15679 p->next = *head;
15680 *head = p;
15681 p->sec = sec;
15682 p->count = 0;
15683 p->pc_count = 0;
15684 }
15685
469a3493 15686 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15687 p->pc_count += 1;
15688 p->count += 1;
e8b09b87
CL		 15689 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15690 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15691 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15692 that will become rofixup. */
15693 /* This is due to the fact that we suppose all will become rofixup. */
15694 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15695 _bfd_error_handler
15696 (_("FDPIC does not yet support %s relocation"
15697 " to become dynamic for executable"),
15698 elf32_arm_howto_table_1[r_type].name);
15699 abort();
15700 }
f6e32f6d 15701 }
252b5132 15702 }
f21f3fe0 15703
b34976b6 15704 return TRUE;
252b5132
RH		 15705}
15706
9eaff861
AO		 15707static void
15708elf32_arm_update_relocs (asection *o,
15709 struct bfd_elf_section_reloc_data *reldata)
15710{
15711 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15712 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15713 const struct elf_backend_data *bed;
15714 _arm_elf_section_data *eado;
15715 struct bfd_link_order *p;
15716 bfd_byte *erela_head, *erela;
15717 Elf_Internal_Rela *irela_head, *irela;
15718 Elf_Internal_Shdr *rel_hdr;
15719 bfd *abfd;
15720 unsigned int count;
15721
15722 eado = get_arm_elf_section_data (o);
15723
15724 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15725 return;
15726
15727 abfd = o->owner;
15728 bed = get_elf_backend_data (abfd);
15729 rel_hdr = reldata->hdr;
15730
15731 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15732 {
15733 swap_in = bed->s->swap_reloc_in;
15734 swap_out = bed->s->swap_reloc_out;
15735 }
15736 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15737 {
15738 swap_in = bed->s->swap_reloca_in;
15739 swap_out = bed->s->swap_reloca_out;
15740 }
15741 else
15742 abort ();
15743
15744 erela_head = rel_hdr->contents;
15745 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15746 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15747
15748 erela = erela_head;
15749 irela = irela_head;
15750 count = 0;
15751
15752 for (p = o->map_head.link_order; p; p = p->next)
15753 {
15754 if (p->type == bfd_section_reloc_link_order
15755 || p->type == bfd_symbol_reloc_link_order)
15756 {
15757 (*swap_in) (abfd, erela, irela);
15758 erela += rel_hdr->sh_entsize;
15759 irela++;
15760 count++;
15761 }
15762 else if (p->type == bfd_indirect_link_order)
15763 {
15764 struct bfd_elf_section_reloc_data *input_reldata;
15765 arm_unwind_table_edit *edit_list, *edit_tail;
15766 _arm_elf_section_data *eadi;
15767 bfd_size_type j;
15768 bfd_vma offset;
15769 asection *i;
15770
15771 i = p->u.indirect.section;
15772
15773 eadi = get_arm_elf_section_data (i);
15774 edit_list = eadi->u.exidx.unwind_edit_list;
15775 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15776 offset = i->output_offset;
9eaff861
AO		 15777
15778 if (eadi->elf.rel.hdr &&
15779 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15780 input_reldata = &eadi->elf.rel;
15781 else if (eadi->elf.rela.hdr &&
15782 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15783 input_reldata = &eadi->elf.rela;
15784 else
15785 abort ();
15786
15787 if (edit_list)
15788 {
15789 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15790 {
15791 arm_unwind_table_edit *edit_node, *edit_next;
15792 bfd_vma bias;
c48182bf 15793 bfd_vma reloc_index;
9eaff861
AO		 15794
15795 (*swap_in) (abfd, erela, irela);
c48182bf 15796 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15797
15798 bias = 0;
15799 edit_node = edit_list;
15800 for (edit_next = edit_list;
c48182bf 15801 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15802 edit_next = edit_node->next)
15803 {
15804 bias++;
15805 edit_node = edit_next;
15806 }
15807
15808 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15809 || edit_node->index != reloc_index)
9eaff861
AO		 15810 {
15811 irela->r_offset -= bias * 8;
15812 irela++;
15813 count++;
15814 }
15815
15816 erela += rel_hdr->sh_entsize;
15817 }
15818
15819 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15820 {
15821 /* New relocation entity. */
15822 asection *text_sec = edit_tail->linked_section;
15823 asection *text_out = text_sec->output_section;
15824 bfd_vma exidx_offset = offset + i->size - 8;
15825
15826 irela->r_addend = 0;
15827 irela->r_offset = exidx_offset;
15828 irela->r_info = ELF32_R_INFO
15829 (text_out->target_index, R_ARM_PREL31);
15830 irela++;
15831 count++;
15832 }
15833 }
15834 else
15835 {
15836 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15837 {
15838 (*swap_in) (abfd, erela, irela);
15839 erela += rel_hdr->sh_entsize;
15840 irela++;
15841 }
15842
15843 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15844 }
15845 }
15846 }
15847
15848 reldata->count = count;
15849 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15850
15851 erela = erela_head;
15852 irela = irela_head;
15853 while (count > 0)
15854 {
15855 (*swap_out) (abfd, irela, erela);
15856 erela += rel_hdr->sh_entsize;
15857 irela++;
15858 count--;
15859 }
15860
15861 free (irela_head);
15862
15863 /* Hashes are no longer valid. */
15864 free (reldata->hashes);
15865 reldata->hashes = NULL;
15866}
15867
6a5bb875 15868/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15869 required if the corresponding code section is marked. Similarly, ARMv8-M
15870 secure entry functions can only be referenced by SG veneers which are
15871 created after the GC process. They need to be marked in case they reside in
15872 their own section (as would be the case if code was compiled with
15873 -ffunction-sections). */
6a5bb875
PB		 15874
15875static bfd_boolean
906e58ca
NC		 15876elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15877 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15878{
15879 bfd *sub;
15880 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15881 asection *cmse_sec;
15882 obj_attribute *out_attr;
15883 Elf_Internal_Shdr *symtab_hdr;
15884 unsigned i, sym_count, ext_start;
15885 const struct elf_backend_data *bed;
15886 struct elf_link_hash_entry **sym_hashes;
15887 struct elf32_arm_link_hash_entry *cmse_hash;
15888 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15889 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15890 asection *isec;
6a5bb875 15891
7f6ab9f8
AM		 15892 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15893
4ba2ef8f
TP		 15894 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15895 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15896 && out_attr[Tag_CPU_arch_profile].i == 'M';
15897
6a5bb875
PB		 15898 /* Marking EH data may cause additional code sections to be marked,
15899 requiring multiple passes. */
15900 again = TRUE;
15901 while (again)
15902 {
15903 again = FALSE;
c72f2fb2 15904 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15905 {
15906 asection *o;
15907
0ffa91dd 15908 if (! is_arm_elf (sub))
6a5bb875
PB		 15909 continue;
15910
15911 elf_shdrp = elf_elfsections (sub);
15912 for (o = sub->sections; o != NULL; o = o->next)
15913 {
15914 Elf_Internal_Shdr *hdr;
0ffa91dd 15915
6a5bb875 15916 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15917 if (hdr->sh_type == SHT_ARM_EXIDX
15918 && hdr->sh_link
15919 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15920 && !o->gc_mark
15921 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15922 {
15923 again = TRUE;
15924 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15925 return FALSE;
15926 }
15927 }
4ba2ef8f
TP		 15928
15929 /* Mark section holding ARMv8-M secure entry functions. We mark all
15930 of them so no need for a second browsing. */
15931 if (is_v8m && first_bfd_browse)
15932 {
15933 sym_hashes = elf_sym_hashes (sub);
15934 bed = get_elf_backend_data (sub);
15935 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15936 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15937 ext_start = symtab_hdr->sh_info;
15938
15939 /* Scan symbols. */
15940 for (i = ext_start; i < sym_count; i++)
15941 {
15942 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15943
15944 /* Assume it is a special symbol. If not, cmse_scan will
15945 warn about it and user can do something about it. */
baf46cd7
AM		 15946 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
15947 CMSE_PREFIX))
4ba2ef8f
TP		 15948 {
15949 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15950 if (!cmse_sec->gc_mark
15951 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 15952 return FALSE;
bb32413f
SP		 15953 /* The debug sections related to these secure entry
15954 functions are marked on enabling below flag. */
15955 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 15956 }
15957 }
bb32413f
SP		 15958
15959 if (debug_sec_need_to_be_marked)
15960 {
15961 /* Looping over all the sections of the object file containing
15962 Armv8-M secure entry functions and marking all the debug
15963 sections. */
15964 for (isec = sub->sections; isec != NULL; isec = isec->next)
15965 {
15966 /* If not a debug sections, skip it. */
15967 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
15968 isec->gc_mark = 1 ;
15969 }
15970 debug_sec_need_to_be_marked = FALSE;
15971 }
4ba2ef8f 15972 }
6a5bb875 15973 }
4ba2ef8f 15974 first_bfd_browse = FALSE;
6a5bb875
PB		 15975 }
15976
15977 return TRUE;
15978}
15979
3c9458e9
NC		 15980/* Treat mapping symbols as special target symbols. */
15981
15982static bfd_boolean
15983elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15984{
b0796911
PB		 15985 return bfd_is_arm_special_symbol_name (sym->name,
15986 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15987}
15988
e7679060
AM		 15989/* If the ELF symbol SYM might be a function in SEC, return the
15990 function size and set *CODE_OFF to the function's entry point,
15991 otherwise return zero. */
252b5132 15992
e7679060
AM		 15993static bfd_size_type
15994elf32_arm_maybe_function_sym (const asymbol *sym, asection *sec,
15995 bfd_vma *code_off)
15996{
15997 bfd_size_type size;
252b5132 15998
e7679060
AM		 15999 if ((sym->flags & (BSF_SECTION_SYM | BSF_FILE | BSF_OBJECT
16000 | BSF_THREAD_LOCAL | BSF_RELC | BSF_SRELC)) != 0
16001 || sym->section != sec)
16002 return 0;
252b5132 16003
e7679060
AM		 16004 if (!(sym->flags & BSF_SYNTHETIC))
16005 switch (ELF_ST_TYPE (((elf_symbol_type *) sym)->internal_elf_sym.st_info))
16006 {
252b5132
RH		 16007 case STT_FUNC:
16008 case STT_ARM_TFUNC:
9d2da7ca 16009 case STT_NOTYPE:
252b5132 16010 break;
e7679060
AM		 16011 default:
16012 return 0;
16013 }
0367ecfb 16014
e7679060
AM		 16015 if ((sym->flags & BSF_LOCAL)
16016 && bfd_is_arm_special_symbol_name (sym->name,
16017 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16018 return 0;
0367ecfb 16019
e7679060
AM		 16020 *code_off = sym->value;
16021 size = 0;
16022 if (!(sym->flags & BSF_SYNTHETIC))
16023 size = ((elf_symbol_type *) sym)->internal_elf_sym.st_size;
16024 if (size == 0)
16025 size = 1;
16026 return size;
252b5132
RH		 16027}
16028
4ab527b0 16029static bfd_boolean
07d6d2b8 16030elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16031 const char ** filename_ptr,
16032 const char ** functionname_ptr,
16033 unsigned int * line_ptr)
16034{
16035 bfd_boolean found;
16036 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16037 functionname_ptr, line_ptr,
16038 & elf_tdata (abfd)->dwarf2_find_line_info);
16039 return found;
16040}
16041
252b5132
RH		 16042/* Adjust a symbol defined by a dynamic object and referenced by a
16043 regular object. The current definition is in some section of the
16044 dynamic object, but we're not including those sections. We have to
16045 change the definition to something the rest of the link can
16046 understand. */
16047
b34976b6 16048static bfd_boolean
57e8b36a
NC		 16049elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16050 struct elf_link_hash_entry * h)
252b5132
RH		 16051{
16052 bfd * dynobj;
5474d94f 16053 asection *s, *srel;
b7693d02 16054 struct elf32_arm_link_hash_entry * eh;
67687978 16055 struct elf32_arm_link_hash_table *globals;
252b5132 16056
67687978 16057 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16058 if (globals == NULL)
16059 return FALSE;
16060
252b5132
RH		 16061 dynobj = elf_hash_table (info)->dynobj;
16062
16063 /* Make sure we know what is going on here. */
16064 BFD_ASSERT (dynobj != NULL
f5385ebf 16065 && (h->needs_plt
34e77a92 16066 || h->type == STT_GNU_IFUNC
60d67dc8 16067 || h->is_weakalias
f5385ebf
AM		 16068 || (h->def_dynamic
16069 && h->ref_regular
16070 && !h->def_regular)));
252b5132 16071
b7693d02
DJ		 16072 eh = (struct elf32_arm_link_hash_entry *) h;
16073
252b5132
RH		 16074 /* If this is a function, put it in the procedure linkage table. We
16075 will fill in the contents of the procedure linkage table later,
16076 when we know the address of the .got section. */
34e77a92 16077 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16078 {
34e77a92
RS		 16079 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16080 symbol binds locally. */
5e681ec4 16081 if (h->plt.refcount <= 0
34e77a92
RS		 16082 || (h->type != STT_GNU_IFUNC
16083 && (SYMBOL_CALLS_LOCAL (info, h)
16084 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16085 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16086 {
16087 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16088 file, but the symbol was never referred to by a dynamic
16089 object, or if all references were garbage collected. In
16090 such a case, we don't actually need to build a procedure
16091 linkage table, and we can just do a PC24 reloc instead. */
16092 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16093 eh->plt.thumb_refcount = 0;
16094 eh->plt.maybe_thumb_refcount = 0;
16095 eh->plt.noncall_refcount = 0;
f5385ebf 16096 h->needs_plt = 0;
252b5132
RH		 16097 }
16098
b34976b6 16099 return TRUE;
252b5132 16100 }
5e681ec4 16101 else
b7693d02
DJ		 16102 {
16103 /* It's possible that we incorrectly decided a .plt reloc was
16104 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16105 in check_relocs. We can't decide accurately between function
16106 and non-function syms in check-relocs; Objects loaded later in
16107 the link may change h->type. So fix it now. */
16108 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16109 eh->plt.thumb_refcount = 0;
16110 eh->plt.maybe_thumb_refcount = 0;
16111 eh->plt.noncall_refcount = 0;
b7693d02 16112 }
252b5132
RH		 16113
16114 /* If this is a weak symbol, and there is a real definition, the
16115 processor independent code will have arranged for us to see the
16116 real definition first, and we can just use the same value. */
60d67dc8 16117 if (h->is_weakalias)
252b5132 16118 {
60d67dc8
AM		 16119 struct elf_link_hash_entry *def = weakdef (h);
16120 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16121 h->root.u.def.section = def->root.u.def.section;
16122 h->root.u.def.value = def->root.u.def.value;
b34976b6 16123 return TRUE;
252b5132
RH		 16124 }
16125
ba93b8ac
DJ		 16126 /* If there are no non-GOT references, we do not need a copy
16127 relocation. */
16128 if (!h->non_got_ref)
16129 return TRUE;
16130
252b5132
RH		 16131 /* This is a reference to a symbol defined by a dynamic object which
16132 is not a function. */
16133
16134 /* If we are creating a shared library, we must presume that the
16135 only references to the symbol are via the global offset table.
16136 For such cases we need not do anything here; the relocations will
67687978
PB		 16137 be handled correctly by relocate_section. Relocatable executables
16138 can reference data in shared objects directly, so we don't need to
16139 do anything here. */
0e1862bb 16140 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16141 return TRUE;
252b5132
RH		 16142
16143 /* We must allocate the symbol in our .dynbss section, which will
16144 become part of the .bss section of the executable. There will be
16145 an entry for this symbol in the .dynsym section. The dynamic
16146 object will contain position independent code, so all references
16147 from the dynamic object to this symbol will go through the global
16148 offset table. The dynamic linker will use the .dynsym entry to
16149 determine the address it must put in the global offset table, so
16150 both the dynamic object and the regular object will refer to the
16151 same memory location for the variable. */
5522f910
NC		 16152 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16153 linker to copy the initial value out of the dynamic object and into
16154 the runtime process image. We need to remember the offset into the
00a97672 16155 .rel(a).bss section we are going to use. */
5474d94f
AM		 16156 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16157 {
16158 s = globals->root.sdynrelro;
16159 srel = globals->root.sreldynrelro;
16160 }
16161 else
16162 {
16163 s = globals->root.sdynbss;
16164 srel = globals->root.srelbss;
16165 }
5522f910
NC		 16166 if (info->nocopyreloc == 0
16167 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16168 && h->size != 0)
252b5132 16169 {
47beaa6a 16170 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16171 h->needs_copy = 1;
252b5132
RH		 16172 }
16173
6cabe1ea 16174 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16175}
16176
5e681ec4
PB		 16177/* Allocate space in .plt, .got and associated reloc sections for
16178 dynamic relocs. */
16179
16180static bfd_boolean
47beaa6a 16181allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16182{
16183 struct bfd_link_info *info;
16184 struct elf32_arm_link_hash_table *htab;
16185 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16186 struct elf_dyn_relocs *p;
5e681ec4
PB		 16187
16188 if (h->root.type == bfd_link_hash_indirect)
16189 return TRUE;
16190
e6a6bb22
AM		 16191 eh = (struct elf32_arm_link_hash_entry *) h;
16192
5e681ec4
PB		 16193 info = (struct bfd_link_info *) inf;
16194 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16195 if (htab == NULL)
16196 return FALSE;
5e681ec4 16197
34e77a92 16198 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16199 && h->plt.refcount > 0)
16200 {
16201 /* Make sure this symbol is output as a dynamic symbol.
16202 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16203 if (h->dynindx == -1 && !h->forced_local
16204 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16205 {
c152c796 16206 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16207 return FALSE;
16208 }
16209
34e77a92
RS		 16210 /* If the call in the PLT entry binds locally, the associated
16211 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16212 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16213 than the .plt section. */
16214 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16215 {
16216 eh->is_iplt = 1;
16217 if (eh->plt.noncall_refcount == 0
16218 && SYMBOL_REFERENCES_LOCAL (info, h))
16219 /* All non-call references can be resolved directly.
16220 This means that they can (and in some cases, must)
16221 resolve directly to the run-time target, rather than
16222 to the PLT. That in turns means that any .got entry
16223 would be equal to the .igot.plt entry, so there's
16224 no point having both. */
16225 h->got.refcount = 0;
16226 }
16227
0e1862bb 16228 if (bfd_link_pic (info)
34e77a92 16229 || eh->is_iplt
7359ea65 16230 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16231 {
34e77a92 16232 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16233
5e681ec4
PB		 16234 /* If this symbol is not defined in a regular file, and we are
16235 not generating a shared library, then set the symbol to this
16236 location in the .plt. This is required to make function
16237 pointers compare as equal between the normal executable and
16238 the shared library. */
0e1862bb 16239 if (! bfd_link_pic (info)
f5385ebf 16240 && !h->def_regular)
5e681ec4 16241 {
34e77a92 16242 h->root.u.def.section = htab->root.splt;
5e681ec4 16243 h->root.u.def.value = h->plt.offset;
5e681ec4 16244
67d74e43
DJ		 16245 /* Make sure the function is not marked as Thumb, in case
16246 it is the target of an ABS32 relocation, which will
16247 point to the PLT entry. */
39d911fc 16248 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16249 }
022f8312 16250
00a97672
RS		 16251 /* VxWorks executables have a second set of relocations for
16252 each PLT entry. They go in a separate relocation section,
16253 which is processed by the kernel loader. */
90c14f0c 16254 if (htab->root.target_os == is_vxworks && !bfd_link_pic (info))
00a97672
RS		 16255 {
16256 /* There is a relocation for the initial PLT entry:
16257 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16258 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16259 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16260
16261 /* There are two extra relocations for each subsequent
16262 PLT entry: an R_ARM_32 relocation for the GOT entry,
16263 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16264 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16265 }
5e681ec4
PB		 16266 }
16267 else
16268 {
16269 h->plt.offset = (bfd_vma) -1;
f5385ebf 16270 h->needs_plt = 0;
5e681ec4
PB		 16271 }
16272 }
16273 else
16274 {
16275 h->plt.offset = (bfd_vma) -1;
f5385ebf 16276 h->needs_plt = 0;
5e681ec4
PB		 16277 }
16278
0855e32b
NS		 16279 eh = (struct elf32_arm_link_hash_entry *) h;
16280 eh->tlsdesc_got = (bfd_vma) -1;
16281
5e681ec4
PB		 16282 if (h->got.refcount > 0)
16283 {
16284 asection *s;
16285 bfd_boolean dyn;
ba93b8ac
DJ		 16286 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16287 int indx;
5e681ec4
PB		 16288
16289 /* Make sure this symbol is output as a dynamic symbol.
16290 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16291 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16292 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16293 {
c152c796 16294 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16295 return FALSE;
16296 }
16297
90c14f0c 16298 if (htab->root.target_os != is_symbian)
e5a52504 16299 {
362d30a1 16300 s = htab->root.sgot;
e5a52504 16301 h->got.offset = s->size;
ba93b8ac
DJ		 16302
16303 if (tls_type == GOT_UNKNOWN)
16304 abort ();
16305
16306 if (tls_type == GOT_NORMAL)
16307 /* Non-TLS symbols need one GOT slot. */
16308 s->size += 4;
16309 else
16310 {
99059e56
RM		 16311 if (tls_type & GOT_TLS_GDESC)
16312 {
0855e32b 16313 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16314 eh->tlsdesc_got
0855e32b
NS		 16315 = (htab->root.sgotplt->size
16316 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16317 htab->root.sgotplt->size += 8;
16318 h->got.offset = (bfd_vma) -2;
34e77a92 16319 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16320 reloc in the middle of .got.plt. */
99059e56
RM		 16321 htab->num_tls_desc++;
16322 }
0855e32b 16323
ba93b8ac 16324 if (tls_type & GOT_TLS_GD)
0855e32b 16325 {
5c5a4843
CL		 16326 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16327 consecutive GOT slots. If the symbol is both GD
16328 and GDESC, got.offset may have been
16329 overwritten. */
0855e32b
NS		 16330 h->got.offset = s->size;
16331 s->size += 8;
16332 }
16333
ba93b8ac 16334 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16335 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16336 slot. */
ba93b8ac
DJ		 16337 s->size += 4;
16338 }
16339
e5a52504 16340 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16341
16342 indx = 0;
0e1862bb
L		 16343 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16344 bfd_link_pic (info),
16345 h)
16346 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16347 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16348 indx = h->dynindx;
16349
16350 if (tls_type != GOT_NORMAL
9cb09e33 16351 && (bfd_link_dll (info) || indx != 0)
ba93b8ac
DJ		 16352 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16353 || h->root.type != bfd_link_hash_undefweak))
16354 {
16355 if (tls_type & GOT_TLS_IE)
47beaa6a 16356 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16357
16358 if (tls_type & GOT_TLS_GD)
47beaa6a 16359 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16360
b38cadfb 16361 if (tls_type & GOT_TLS_GDESC)
0855e32b 16362 {
47beaa6a 16363 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16364 /* GDESC needs a trampoline to jump to. */
16365 htab->tls_trampoline = -1;
16366 }
16367
16368 /* Only GD needs it. GDESC just emits one relocation per
16369 2 entries. */
b38cadfb 16370 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16371 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16372 }
e8b09b87
CL		 16373 else if (((indx != -1) || htab->fdpic_p)
16374 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16375 {
16376 if (htab->root.dynamic_sections_created)
16377 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16378 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16379 }
34e77a92
RS		 16380 else if (h->type == STT_GNU_IFUNC
16381 && eh->plt.noncall_refcount == 0)
16382 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16383 they all resolve dynamically instead. Reserve room for the
16384 GOT entry's R_ARM_IRELATIVE relocation. */
16385 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb 16386 else if (bfd_link_pic (info)
7f026732 16387 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
b436d854 16388 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16389 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16390 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16391 /* Reserve room for rofixup for FDPIC executable. */
16392 /* TLS relocs do not need space since they are completely
16393 resolved. */
16394 htab->srofixup->size += 4;
e5a52504 16395 }
5e681ec4
PB		 16396 }
16397 else
16398 h->got.offset = (bfd_vma) -1;
16399
e8b09b87
CL		 16400 /* FDPIC support. */
16401 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16402 {
16403 /* Symbol musn't be exported. */
16404 if (h->dynindx != -1)
16405 abort();
16406
16407 /* We only allocate one function descriptor with its associated relocation. */
16408 if (eh->fdpic_cnts.funcdesc_offset == -1)
16409 {
16410 asection *s = htab->root.sgot;
16411
16412 eh->fdpic_cnts.funcdesc_offset = s->size;
16413 s->size += 8;
16414 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16415 if (bfd_link_pic(info))
16416 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16417 else
16418 htab->srofixup->size += 8;
16419 }
16420 }
16421
16422 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16423 {
16424 asection *s = htab->root.sgot;
16425
16426 if (htab->root.dynamic_sections_created && h->dynindx == -1
16427 && !h->forced_local)
16428 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16429 return FALSE;
16430
16431 if (h->dynindx == -1)
16432 {
16433 /* We only allocate one function descriptor with its associated relocation. q */
16434 if (eh->fdpic_cnts.funcdesc_offset == -1)
16435 {
16436
16437 eh->fdpic_cnts.funcdesc_offset = s->size;
16438 s->size += 8;
16439 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16440 if (bfd_link_pic(info))
16441 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16442 else
16443 htab->srofixup->size += 8;
16444 }
16445 }
16446
16447 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16448 R_ARM_RELATIVE/rofixup relocation on it. */
16449 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16450 s->size += 4;
16451 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16452 htab->srofixup->size += 4;
e8b09b87 16453 else
4b24dd1a 16454 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16455 }
16456
16457 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16458 {
16459 if (htab->root.dynamic_sections_created && h->dynindx == -1
16460 && !h->forced_local)
16461 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16462 return FALSE;
16463
16464 if (h->dynindx == -1)
16465 {
16466 /* We only allocate one function descriptor with its associated relocation. */
16467 if (eh->fdpic_cnts.funcdesc_offset == -1)
16468 {
16469 asection *s = htab->root.sgot;
16470
16471 eh->fdpic_cnts.funcdesc_offset = s->size;
16472 s->size += 8;
16473 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16474 if (bfd_link_pic(info))
16475 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16476 else
16477 htab->srofixup->size += 8;
16478 }
16479 }
16480 if (h->dynindx == -1 && !bfd_link_pic(info))
16481 {
16482 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16483 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16484 }
16485 else
16486 {
16487 /* Will need one dynamic reloc per reference. will be either
16488 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16489 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16490 eh->fdpic_cnts.funcdesc_cnt);
16491 }
16492 }
16493
a4fd1a8e
PB		 16494 /* Allocate stubs for exported Thumb functions on v4t. */
16495 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16496 && h->def_regular
39d911fc 16497 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16498 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16499 {
16500 struct elf_link_hash_entry * th;
16501 struct bfd_link_hash_entry * bh;
16502 struct elf_link_hash_entry * myh;
16503 char name[1024];
16504 asection *s;
16505 bh = NULL;
16506 /* Create a new symbol to regist the real location of the function. */
16507 s = h->root.u.def.section;
906e58ca 16508 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16509 _bfd_generic_link_add_one_symbol (info, s->owner,
16510 name, BSF_GLOBAL, s,
16511 h->root.u.def.value,
16512 NULL, TRUE, FALSE, &bh);
16513
16514 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16515 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16516 myh->forced_local = 1;
39d911fc 16517 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16518 eh->export_glue = myh;
16519 th = record_arm_to_thumb_glue (info, h);
16520 /* Point the symbol at the stub. */
16521 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16522 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16523 h->root.u.def.section = th->root.u.def.section;
16524 h->root.u.def.value = th->root.u.def.value & ~1;
16525 }
16526
190eb1dd 16527 if (h->dyn_relocs == NULL)
5e681ec4
PB		 16528 return TRUE;
16529
16530 /* In the shared -Bsymbolic case, discard space allocated for
16531 dynamic pc-relative relocs against symbols which turn out to be
16532 defined in regular objects. For the normal shared case, discard
16533 space for pc-relative relocs that have become local due to symbol
16534 visibility changes. */
16535
e8b09b87 16536 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16537 {
469a3493
RM		 16538 /* Relocs that use pc_count are PC-relative forms, which will appear
16539 on something like ".long foo - ." or "movw REG, foo - .". We want
16540 calls to protected symbols to resolve directly to the function
16541 rather than going via the plt. If people want function pointer
16542 comparisons to work as expected then they should avoid writing
16543 assembly like ".long foo - .". */
ba93b8ac
DJ		 16544 if (SYMBOL_CALLS_LOCAL (info, h))
16545 {
0bdcacaf 16546 struct elf_dyn_relocs **pp;
ba93b8ac 16547
190eb1dd 16548 for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16549 {
16550 p->count -= p->pc_count;
16551 p->pc_count = 0;
16552 if (p->count == 0)
16553 *pp = p->next;
16554 else
16555 pp = &p->next;
16556 }
16557 }
16558
90c14f0c 16559 if (htab->root.target_os == is_vxworks)
3348747a 16560 {
0bdcacaf 16561 struct elf_dyn_relocs **pp;
3348747a 16562
190eb1dd 16563 for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
3348747a 16564 {
0bdcacaf 16565 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16566 *pp = p->next;
16567 else
16568 pp = &p->next;
16569 }
16570 }
16571
ba93b8ac 16572 /* Also discard relocs on undefined weak syms with non-default
99059e56 16573 visibility. */
190eb1dd 16574 if (h->dyn_relocs != NULL
5e681ec4 16575 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16576 {
95b03e4a
L		 16577 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16578 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
190eb1dd 16579 h->dyn_relocs = NULL;
22d606e9
AM		 16580
16581 /* Make sure undefined weak symbols are output as a dynamic
16582 symbol in PIEs. */
e8b09b87 16583 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16584 && !h->forced_local)
16585 {
16586 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16587 return FALSE;
16588 }
16589 }
16590
67687978
PB		 16591 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16592 && h->root.type == bfd_link_hash_new)
16593 {
16594 /* Output absolute symbols so that we can create relocations
16595 against them. For normal symbols we output a relocation
16596 against the section that contains them. */
16597 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16598 return FALSE;
16599 }
16600
5e681ec4
PB		 16601 }
16602 else
16603 {
16604 /* For the non-shared case, discard space for relocs against
16605 symbols which turn out to need copy relocs or are not
16606 dynamic. */
16607
f5385ebf
AM		 16608 if (!h->non_got_ref
16609 && ((h->def_dynamic
16610 && !h->def_regular)
5e681ec4
PB		 16611 || (htab->root.dynamic_sections_created
16612 && (h->root.type == bfd_link_hash_undefweak
16613 || h->root.type == bfd_link_hash_undefined))))
16614 {
16615 /* Make sure this symbol is output as a dynamic symbol.
16616 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16617 if (h->dynindx == -1 && !h->forced_local
16618 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16619 {
c152c796 16620 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16621 return FALSE;
16622 }
16623
16624 /* If that succeeded, we know we'll be keeping all the
16625 relocs. */
16626 if (h->dynindx != -1)
16627 goto keep;
16628 }
16629
190eb1dd 16630 h->dyn_relocs = NULL;
5e681ec4
PB		 16631
16632 keep: ;
16633 }
16634
16635 /* Finally, allocate space. */
190eb1dd 16636 for (p = h->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16637 {
0bdcacaf 16638 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16639
34e77a92
RS		 16640 if (h->type == STT_GNU_IFUNC
16641 && eh->plt.noncall_refcount == 0
16642 && SYMBOL_REFERENCES_LOCAL (info, h))
16643 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16644 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16645 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16646 else if (htab->fdpic_p && !bfd_link_pic(info))
16647 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16648 else
16649 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16650 }
16651
16652 return TRUE;
16653}
16654
d504ffc8
DJ		 16655void
16656bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16657 int byteswap_code)
16658{
16659 struct elf32_arm_link_hash_table *globals;
16660
16661 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16662 if (globals == NULL)
16663 return;
16664
d504ffc8
DJ		 16665 globals->byteswap_code = byteswap_code;
16666}
16667
252b5132
RH		 16668/* Set the sizes of the dynamic sections. */
16669
b34976b6 16670static bfd_boolean
57e8b36a
NC		 16671elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16672 struct bfd_link_info * info)
252b5132
RH		 16673{
16674 bfd * dynobj;
16675 asection * s;
b34976b6 16676 bfd_boolean relocs;
5e681ec4
PB		 16677 bfd *ibfd;
16678 struct elf32_arm_link_hash_table *htab;
252b5132 16679
5e681ec4 16680 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16681 if (htab == NULL)
16682 return FALSE;
16683
252b5132
RH		 16684 dynobj = elf_hash_table (info)->dynobj;
16685 BFD_ASSERT (dynobj != NULL);
39b41c9c 16686 check_use_blx (htab);
252b5132
RH		 16687
16688 if (elf_hash_table (info)->dynamic_sections_created)
16689 {
16690 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16691 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16692 {
3d4d4302 16693 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16694 BFD_ASSERT (s != NULL);
eea6121a 16695 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16696 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16697 }
16698 }
5e681ec4
PB		 16699
16700 /* Set up .got offsets for local syms, and space for local dynamic
16701 relocs. */
c72f2fb2 16702 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16703 {
5e681ec4
PB		 16704 bfd_signed_vma *local_got;
16705 bfd_signed_vma *end_local_got;
34e77a92 16706 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16707 char *local_tls_type;
0855e32b 16708 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16709 bfd_size_type locsymcount;
16710 Elf_Internal_Shdr *symtab_hdr;
16711 asection *srel;
34e77a92 16712 unsigned int symndx;
e8b09b87 16713 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16714
0ffa91dd 16715 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16716 continue;
16717
16718 for (s = ibfd->sections; s != NULL; s = s->next)
16719 {
0bdcacaf 16720 struct elf_dyn_relocs *p;
5e681ec4 16721
0bdcacaf 16722 for (p = (struct elf_dyn_relocs *)
99059e56 16723 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16724 {
0bdcacaf
RS		 16725 if (!bfd_is_abs_section (p->sec)
16726 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16727 {
16728 /* Input section has been discarded, either because
16729 it is a copy of a linkonce section or due to
16730 linker script /DISCARD/, so we'll be discarding
16731 the relocs too. */
16732 }
90c14f0c 16733 else if (htab->root.target_os == is_vxworks
0bdcacaf 16734 && strcmp (p->sec->output_section->name,
3348747a
NS		 16735 ".tls_vars") == 0)
16736 {
16737 /* Relocations in vxworks .tls_vars sections are
16738 handled specially by the loader. */
16739 }
5e681ec4
PB		 16740 else if (p->count != 0)
16741 {
0bdcacaf 16742 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16743 if (htab->fdpic_p && !bfd_link_pic(info))
16744 htab->srofixup->size += 4 * p->count;
16745 else
16746 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16747 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16748 info->flags |= DF_TEXTREL;
16749 }
16750 }
16751 }
16752
16753 local_got = elf_local_got_refcounts (ibfd);
16754 if (!local_got)
16755 continue;
16756
0ffa91dd 16757 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16758 locsymcount = symtab_hdr->sh_info;
16759 end_local_got = local_got + locsymcount;
34e77a92 16760 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16761 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16762 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16763 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16764 symndx = 0;
362d30a1
RS		 16765 s = htab->root.sgot;
16766 srel = htab->root.srelgot;
0855e32b 16767 for (; local_got < end_local_got;
34e77a92 16768 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16769 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16770 {
0855e32b 16771 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16772 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16773
16774 /* FDPIC support. */
16775 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16776 {
16777 if (local_fdpic_cnts->funcdesc_offset == -1)
16778 {
16779 local_fdpic_cnts->funcdesc_offset = s->size;
16780 s->size += 8;
16781
16782 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16783 if (bfd_link_pic(info))
16784 elf32_arm_allocate_dynrelocs (info, srel, 1);
16785 else
16786 htab->srofixup->size += 8;
16787 }
16788 }
16789
16790 if (local_fdpic_cnts->funcdesc_cnt > 0)
16791 {
16792 if (local_fdpic_cnts->funcdesc_offset == -1)
16793 {
16794 local_fdpic_cnts->funcdesc_offset = s->size;
16795 s->size += 8;
16796
16797 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16798 if (bfd_link_pic(info))
16799 elf32_arm_allocate_dynrelocs (info, srel, 1);
16800 else
16801 htab->srofixup->size += 8;
16802 }
16803
16804 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16805 if (bfd_link_pic(info))
16806 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16807 else
16808 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16809 }
16810
34e77a92
RS		 16811 if (local_iplt != NULL)
16812 {
16813 struct elf_dyn_relocs *p;
16814
16815 if (local_iplt->root.refcount > 0)
16816 {
16817 elf32_arm_allocate_plt_entry (info, TRUE,
16818 &local_iplt->root,
16819 &local_iplt->arm);
16820 if (local_iplt->arm.noncall_refcount == 0)
16821 /* All references to the PLT are calls, so all
16822 non-call references can resolve directly to the
16823 run-time target. This means that the .got entry
16824 would be the same as the .igot.plt entry, so there's
16825 no point creating both. */
16826 *local_got = 0;
16827 }
16828 else
16829 {
16830 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16831 local_iplt->root.offset = (bfd_vma) -1;
16832 }
16833
16834 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16835 {
16836 asection *psrel;
16837
16838 psrel = elf_section_data (p->sec)->sreloc;
16839 if (local_iplt->arm.noncall_refcount == 0)
16840 elf32_arm_allocate_irelocs (info, psrel, p->count);
16841 else
16842 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16843 }
16844 }
5e681ec4
PB		 16845 if (*local_got > 0)
16846 {
34e77a92
RS		 16847 Elf_Internal_Sym *isym;
16848
eea6121a 16849 *local_got = s->size;
ba93b8ac
DJ		 16850 if (*local_tls_type & GOT_TLS_GD)
16851 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16852 s->size += 8;
0855e32b
NS		 16853 if (*local_tls_type & GOT_TLS_GDESC)
16854 {
16855 *local_tlsdesc_gotent = htab->root.sgotplt->size
16856 - elf32_arm_compute_jump_table_size (htab);
16857 htab->root.sgotplt->size += 8;
16858 *local_got = (bfd_vma) -2;
34e77a92 16859 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16860 reloc in the middle of .got.plt. */
99059e56 16861 htab->num_tls_desc++;
0855e32b 16862 }
ba93b8ac
DJ		 16863 if (*local_tls_type & GOT_TLS_IE)
16864 s->size += 4;
ba93b8ac 16865
0855e32b
NS		 16866 if (*local_tls_type & GOT_NORMAL)
16867 {
16868 /* If the symbol is both GD and GDESC, *local_got
16869 may have been overwritten. */
16870 *local_got = s->size;
16871 s->size += 4;
16872 }
16873
34e77a92
RS		 16874 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
16875 if (isym == NULL)
16876 return FALSE;
16877
16878 /* If all references to an STT_GNU_IFUNC PLT are calls,
16879 then all non-call references, including this GOT entry,
16880 resolve directly to the run-time target. */
16881 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16882 && (local_iplt == NULL
16883 || local_iplt->arm.noncall_refcount == 0))
16884 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16885 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16886 {
e8b09b87 16887 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16888 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16889 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16890 htab->srofixup->size += 4;
99059e56 16891
e8b09b87
CL		 16892 if ((bfd_link_pic (info) || htab->fdpic_p)
16893 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16894 {
16895 elf32_arm_allocate_dynrelocs (info,
16896 htab->root.srelplt, 1);
16897 htab->tls_trampoline = -1;
16898 }
0855e32b 16899 }
5e681ec4
PB		 16900 }
16901 else
16902 *local_got = (bfd_vma) -1;
16903 }
252b5132
RH		 16904 }
16905
ba93b8ac
DJ		 16906 if (htab->tls_ldm_got.refcount > 0)
16907 {
16908 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 16909 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 16910 htab->tls_ldm_got.offset = htab->root.sgot->size;
16911 htab->root.sgot->size += 8;
0e1862bb 16912 if (bfd_link_pic (info))
47beaa6a 16913 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16914 }
16915 else
16916 htab->tls_ldm_got.offset = -1;
16917
e8b09b87
CL		 16918 /* At the very end of the .rofixup section is a pointer to the GOT,
16919 reserve space for it. */
16920 if (htab->fdpic_p && htab->srofixup != NULL)
16921 htab->srofixup->size += 4;
16922
5e681ec4
PB		 16923 /* Allocate global sym .plt and .got entries, and space for global
16924 sym dynamic relocs. */
47beaa6a 16925 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16926
d504ffc8 16927 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16928 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16929 {
0ffa91dd 16930 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16931 continue;
16932
c7b8f16e
JB		 16933 /* Initialise mapping tables for code/data. */
16934 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16935
c7b8f16e 16936 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16937 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16938 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 16939 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 16940 }
d504ffc8 16941
3e6b1042
DJ		 16942 /* Allocate space for the glue sections now that we've sized them. */
16943 bfd_elf32_arm_allocate_interworking_sections (info);
16944
0855e32b
NS		 16945 /* For every jump slot reserved in the sgotplt, reloc_count is
16946 incremented. However, when we reserve space for TLS descriptors,
16947 it's not incremented, so in order to compute the space reserved
16948 for them, it suffices to multiply the reloc count by the jump
16949 slot size. */
16950 if (htab->root.srelplt)
16951 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16952
16953 if (htab->tls_trampoline)
16954 {
16955 if (htab->root.splt->size == 0)
16956 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16957
0855e32b
NS		 16958 htab->tls_trampoline = htab->root.splt->size;
16959 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16960
0855e32b 16961 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16962 PLT and GOT entries they require. */
9bcc30e4
L		 16963 if ((info->flags & DF_BIND_NOW))
16964 htab->root.tlsdesc_plt = 0;
16965 else
0855e32b 16966 {
9bcc30e4 16967 htab->root.tlsdesc_got = htab->root.sgot->size;
0855e32b
NS		 16968 htab->root.sgot->size += 4;
16969
9bcc30e4 16970 htab->root.tlsdesc_plt = htab->root.splt->size;
0855e32b
NS		 16971 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16972 }
16973 }
16974
252b5132
RH		 16975 /* The check_relocs and adjust_dynamic_symbol entry points have
16976 determined the sizes of the various dynamic sections. Allocate
16977 memory for them. */
b34976b6 16978 relocs = FALSE;
252b5132
RH		 16979 for (s = dynobj->sections; s != NULL; s = s->next)
16980 {
16981 const char * name;
252b5132
RH		 16982
16983 if ((s->flags & SEC_LINKER_CREATED) == 0)
16984 continue;
16985
16986 /* It's OK to base decisions on the section name, because none
16987 of the dynobj section names depend upon the input files. */
fd361982 16988 name = bfd_section_name (s);
252b5132 16989
34e77a92 16990 if (s == htab->root.splt)
252b5132 16991 {
c456f082 16992 /* Remember whether there is a PLT. */
3084d7a2 16993 ;
252b5132 16994 }
0112cd26 16995 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16996 {
c456f082 16997 if (s->size != 0)
252b5132 16998 {
252b5132 16999 /* Remember whether there are any reloc sections other
00a97672 17000 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17001 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17002 relocs = TRUE;
252b5132
RH		 17003
17004 /* We use the reloc_count field as a counter if we need
17005 to copy relocs into the output file. */
17006 s->reloc_count = 0;
17007 }
17008 }
34e77a92
RS		 17009 else if (s != htab->root.sgot
17010 && s != htab->root.sgotplt
17011 && s != htab->root.iplt
17012 && s != htab->root.igotplt
5474d94f 17013 && s != htab->root.sdynbss
e8b09b87
CL		 17014 && s != htab->root.sdynrelro
17015 && s != htab->srofixup)
252b5132
RH		 17016 {
17017 /* It's not one of our sections, so don't allocate space. */
17018 continue;
17019 }
17020
c456f082 17021 if (s->size == 0)
252b5132 17022 {
c456f082 17023 /* If we don't need this section, strip it from the
00a97672
RS		 17024 output file. This is mostly to handle .rel(a).bss and
17025 .rel(a).plt. We must create both sections in
c456f082
AM		 17026 create_dynamic_sections, because they must be created
17027 before the linker maps input sections to output
17028 sections. The linker does that before
17029 adjust_dynamic_symbol is called, and it is that
17030 function which decides whether anything needs to go
17031 into these sections. */
8423293d 17032 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17033 continue;
17034 }
17035
c456f082
AM		 17036 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17037 continue;
17038
252b5132 17039 /* Allocate memory for the section contents. */
21d799b5 17040 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17041 if (s->contents == NULL)
b34976b6 17042 return FALSE;
252b5132
RH		 17043 }
17044
3084d7a2
L		 17045 return _bfd_elf_maybe_vxworks_add_dynamic_tags (output_bfd, info,
17046 relocs);
252b5132
RH		 17047}
17048
0855e32b
NS		 17049/* Size sections even though they're not dynamic. We use it to setup
17050 _TLS_MODULE_BASE_, if needed. */
17051
17052static bfd_boolean
17053elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17054 struct bfd_link_info *info)
0855e32b
NS		 17055{
17056 asection *tls_sec;
cb10292c
CL		 17057 struct elf32_arm_link_hash_table *htab;
17058
17059 htab = elf32_arm_hash_table (info);
0855e32b 17060
0e1862bb 17061 if (bfd_link_relocatable (info))
0855e32b
NS		 17062 return TRUE;
17063
17064 tls_sec = elf_hash_table (info)->tls_sec;
17065
17066 if (tls_sec)
17067 {
17068 struct elf_link_hash_entry *tlsbase;
17069
17070 tlsbase = elf_link_hash_lookup
17071 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17072
17073 if (tlsbase)
99059e56
RM		 17074 {
17075 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17076 const struct elf_backend_data *bed
99059e56 17077 = get_elf_backend_data (output_bfd);
0855e32b 17078
99059e56 17079 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17080 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17081 tls_sec, 0, NULL, FALSE,
17082 bed->collect, &bh)))
17083 return FALSE;
b38cadfb 17084
99059e56
RM		 17085 tlsbase->type = STT_TLS;
17086 tlsbase = (struct elf_link_hash_entry *)bh;
17087 tlsbase->def_regular = 1;
17088 tlsbase->other = STV_HIDDEN;
17089 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17090 }
17091 }
cb10292c
CL		 17092
17093 if (htab->fdpic_p && !bfd_link_relocatable (info)
17094 && !bfd_elf_stack_segment_size (output_bfd, info,
17095 "__stacksize", DEFAULT_STACK_SIZE))
17096 return FALSE;
17097
0855e32b
NS		 17098 return TRUE;
17099}
17100
252b5132
RH		 17101/* Finish up dynamic symbol handling. We set the contents of various
17102 dynamic sections here. */
17103
b34976b6 17104static bfd_boolean
906e58ca
NC		 17105elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17106 struct bfd_link_info * info,
17107 struct elf_link_hash_entry * h,
17108 Elf_Internal_Sym * sym)
252b5132 17109{
e5a52504 17110 struct elf32_arm_link_hash_table *htab;
b7693d02 17111 struct elf32_arm_link_hash_entry *eh;
252b5132 17112
e5a52504 17113 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17114 if (htab == NULL)
17115 return FALSE;
17116
b7693d02 17117 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17118
17119 if (h->plt.offset != (bfd_vma) -1)
17120 {
34e77a92 17121 if (!eh->is_iplt)
e5a52504 17122 {
34e77a92 17123 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17124 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17125 h->dynindx, 0))
17126 return FALSE;
e5a52504 17127 }
57e8b36a 17128
f5385ebf 17129 if (!h->def_regular)
252b5132
RH		 17130 {
17131 /* Mark the symbol as undefined, rather than as defined in
3a635617 17132 the .plt section. */
252b5132 17133 sym->st_shndx = SHN_UNDEF;
3a635617 17134 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17135 Otherwise, the PLT entry would provide a definition for
17136 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17137 and so the symbol would never be NULL. Leave the value if
17138 there were any relocations where pointer equality matters
17139 (this is a clue for the dynamic linker, to make function
17140 pointer comparisons work between an application and shared
17141 library). */
97323ad1 17142 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17143 sym->st_value = 0;
252b5132 17144 }
34e77a92
RS		 17145 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17146 {
17147 /* At least one non-call relocation references this .iplt entry,
17148 so the .iplt entry is the function's canonical address. */
17149 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17150 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17151 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17152 (output_bfd, htab->root.iplt->output_section));
17153 sym->st_value = (h->plt.offset
17154 + htab->root.iplt->output_section->vma
17155 + htab->root.iplt->output_offset);
17156 }
252b5132
RH		 17157 }
17158
f5385ebf 17159 if (h->needs_copy)
252b5132
RH		 17160 {
17161 asection * s;
947216bf 17162 Elf_Internal_Rela rel;
252b5132
RH		 17163
17164 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17165 BFD_ASSERT (h->dynindx != -1
17166 && (h->root.type == bfd_link_hash_defined
17167 || h->root.type == bfd_link_hash_defweak));
17168
00a97672 17169 rel.r_addend = 0;
252b5132
RH		 17170 rel.r_offset = (h->root.u.def.value
17171 + h->root.u.def.section->output_section->vma
17172 + h->root.u.def.section->output_offset);
17173 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17174 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17175 s = htab->root.sreldynrelro;
17176 else
17177 s = htab->root.srelbss;
47beaa6a 17178 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17179 }
17180
00a97672 17181 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17182 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17183 it is relative to the ".got" section. */
9637f6ef 17184 if (h == htab->root.hdynamic
90c14f0c
L		 17185 || (!htab->fdpic_p
17186 && htab->root.target_os != is_vxworks
17187 && h == htab->root.hgot))
252b5132
RH		 17188 sym->st_shndx = SHN_ABS;
17189
b34976b6 17190 return TRUE;
252b5132
RH		 17191}
17192
0855e32b
NS		 17193static void
17194arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17195 void *contents,
17196 const unsigned long *template, unsigned count)
17197{
17198 unsigned ix;
b38cadfb 17199
0855e32b
NS		 17200 for (ix = 0; ix != count; ix++)
17201 {
17202 unsigned long insn = template[ix];
17203
17204 /* Emit mov pc,rx if bx is not permitted. */
17205 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17206 insn = (insn & 0xf000000f) | 0x01a0f000;
17207 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17208 }
17209}
17210
99059e56
RM		 17211/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17212 other variants, NaCl needs this entry in a static executable's
17213 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17214 zero. For .iplt really only the last bundle is useful, and .iplt
17215 could have a shorter first entry, with each individual PLT entry's
17216 relative branch calculated differently so it targets the last
17217 bundle instead of the instruction before it (labelled .Lplt_tail
17218 above). But it's simpler to keep the size and layout of PLT0
17219 consistent with the dynamic case, at the cost of some dead code at
17220 the start of .iplt and the one dead store to the stack at the start
17221 of .Lplt_tail. */
17222static void
17223arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17224 asection *plt, bfd_vma got_displacement)
17225{
17226 unsigned int i;
17227
17228 put_arm_insn (htab, output_bfd,
17229 elf32_arm_nacl_plt0_entry[0]
17230 | arm_movw_immediate (got_displacement),
17231 plt->contents + 0);
17232 put_arm_insn (htab, output_bfd,
17233 elf32_arm_nacl_plt0_entry[1]
17234 | arm_movt_immediate (got_displacement),
17235 plt->contents + 4);
17236
17237 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17238 put_arm_insn (htab, output_bfd,
17239 elf32_arm_nacl_plt0_entry[i],
17240 plt->contents + (i * 4));
17241}
17242
252b5132
RH		 17243/* Finish up the dynamic sections. */
17244
b34976b6 17245static bfd_boolean
57e8b36a 17246elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17247{
17248 bfd * dynobj;
17249 asection * sgot;
17250 asection * sdyn;
4dfe6ac6
NC		 17251 struct elf32_arm_link_hash_table *htab;
17252
17253 htab = elf32_arm_hash_table (info);
17254 if (htab == NULL)
17255 return FALSE;
252b5132
RH		 17256
17257 dynobj = elf_hash_table (info)->dynobj;
17258
362d30a1 17259 sgot = htab->root.sgotplt;
894891db
NC		 17260 /* A broken linker script might have discarded the dynamic sections.
17261 Catch this here so that we do not seg-fault later on. */
17262 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17263 return FALSE;
3d4d4302 17264 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17265
17266 if (elf_hash_table (info)->dynamic_sections_created)
17267 {
17268 asection *splt;
17269 Elf32_External_Dyn *dyncon, *dynconend;
17270
362d30a1 17271 splt = htab->root.splt;
24a1ba0f 17272 BFD_ASSERT (splt != NULL && sdyn != NULL);
90c14f0c 17273 BFD_ASSERT (htab->root.target_os == is_symbian || sgot != NULL);
252b5132
RH		 17274
17275 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17276 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17277
252b5132
RH		 17278 for (; dyncon < dynconend; dyncon++)
17279 {
17280 Elf_Internal_Dyn dyn;
17281 const char * name;
17282 asection * s;
17283
17284 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17285
17286 switch (dyn.d_tag)
17287 {
229fcec5
MM		 17288 unsigned int type;
17289
252b5132 17290 default:
90c14f0c 17291 if (htab->root.target_os == is_vxworks
7a2b07ff
NS		 17292 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17293 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17294 break;
17295
229fcec5
MM		 17296 case DT_HASH:
17297 name = ".hash";
17298 goto get_vma_if_bpabi;
17299 case DT_STRTAB:
17300 name = ".dynstr";
17301 goto get_vma_if_bpabi;
17302 case DT_SYMTAB:
17303 name = ".dynsym";
17304 goto get_vma_if_bpabi;
c0042f5d
MM		 17305 case DT_VERSYM:
17306 name = ".gnu.version";
17307 goto get_vma_if_bpabi;
17308 case DT_VERDEF:
17309 name = ".gnu.version_d";
17310 goto get_vma_if_bpabi;
17311 case DT_VERNEED:
17312 name = ".gnu.version_r";
17313 goto get_vma_if_bpabi;
17314
252b5132 17315 case DT_PLTGOT:
90c14f0c
L		 17316 name = (htab->root.target_os == is_symbian
17317 ? ".got" : ".got.plt");
252b5132
RH		 17318 goto get_vma;
17319 case DT_JMPREL:
00a97672 17320 name = RELOC_SECTION (htab, ".plt");
252b5132 17321 get_vma:
4ade44b7 17322 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17323 if (s == NULL)
17324 {
4eca0228 17325 _bfd_error_handler
4ade44b7 17326 (_("could not find section %s"), name);
05456594
NC		 17327 bfd_set_error (bfd_error_invalid_operation);
17328 return FALSE;
17329 }
90c14f0c 17330 if (htab->root.target_os != is_symbian)
4ade44b7 17331 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17332 else
17333 /* In the BPABI, tags in the PT_DYNAMIC section point
17334 at the file offset, not the memory address, for the
17335 convenience of the post linker. */
4ade44b7 17336 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17337 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17338 break;
17339
229fcec5 17340 get_vma_if_bpabi:
90c14f0c 17341 if (htab->root.target_os == is_symbian)
229fcec5
MM		 17342 goto get_vma;
17343 break;
17344
252b5132 17345 case DT_PLTRELSZ:
362d30a1 17346 s = htab->root.srelplt;
252b5132 17347 BFD_ASSERT (s != NULL);
eea6121a 17348 dyn.d_un.d_val = s->size;
252b5132
RH		 17349 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17350 break;
906e58ca 17351
252b5132 17352 case DT_RELSZ:
00a97672 17353 case DT_RELASZ:
229fcec5
MM		 17354 case DT_REL:
17355 case DT_RELA:
229fcec5
MM		 17356 /* In the BPABI, the DT_REL tag must point at the file
17357 offset, not the VMA, of the first relocation
17358 section. So, we use code similar to that in
17359 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17360 relocation section, since relocation sections are
17361 never allocated under the BPABI. PLT relocs are also
17362 included. */
90c14f0c 17363 if (htab->root.target_os == is_symbian)
229fcec5
MM		 17364 {
17365 unsigned int i;
17366 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17367 ? SHT_REL : SHT_RELA);
17368 dyn.d_un.d_val = 0;
17369 for (i = 1; i < elf_numsections (output_bfd); i++)
17370 {
906e58ca 17371 Elf_Internal_Shdr *hdr
229fcec5
MM		 17372 = elf_elfsections (output_bfd)[i];
17373 if (hdr->sh_type == type)
17374 {
906e58ca 17375 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17376 || dyn.d_tag == DT_RELASZ)
17377 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17378 else if ((ufile_ptr) hdr->sh_offset
17379 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17380 dyn.d_un.d_val = hdr->sh_offset;
17381 }
17382 }
17383 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17384 }
252b5132 17385 break;
88f7bcd5 17386
0855e32b 17387 case DT_TLSDESC_PLT:
99059e56 17388 s = htab->root.splt;
0855e32b 17389 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
9bcc30e4 17390 + htab->root.tlsdesc_plt);
0855e32b
NS		 17391 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17392 break;
17393
17394 case DT_TLSDESC_GOT:
99059e56 17395 s = htab->root.sgot;
0855e32b 17396 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
9bcc30e4 17397 + htab->root.tlsdesc_got);
0855e32b
NS		 17398 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17399 break;
17400
88f7bcd5
NC		 17401 /* Set the bottom bit of DT_INIT/FINI if the
17402 corresponding function is Thumb. */
17403 case DT_INIT:
17404 name = info->init_function;
17405 goto get_sym;
17406 case DT_FINI:
17407 name = info->fini_function;
17408 get_sym:
17409 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17410 then there is nothing to adjust. */
88f7bcd5
NC		 17411 if (dyn.d_un.d_val != 0)
17412 {
17413 struct elf_link_hash_entry * eh;
17414
17415 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17416 FALSE, FALSE, TRUE);
39d911fc
TP		 17417 if (eh != NULL
17418 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17419 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17420 {
17421 dyn.d_un.d_val |= 1;
b34976b6 17422 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17423 }
17424 }
17425 break;
252b5132
RH		 17426 }
17427 }
17428
24a1ba0f 17429 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17430 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17431 {
00a97672
RS		 17432 const bfd_vma *plt0_entry;
17433 bfd_vma got_address, plt_address, got_displacement;
17434
17435 /* Calculate the addresses of the GOT and PLT. */
17436 got_address = sgot->output_section->vma + sgot->output_offset;
17437 plt_address = splt->output_section->vma + splt->output_offset;
17438
90c14f0c 17439 if (htab->root.target_os == is_vxworks)
00a97672
RS		 17440 {
17441 /* The VxWorks GOT is relocated by the dynamic linker.
17442 Therefore, we must emit relocations rather than simply
17443 computing the values now. */
17444 Elf_Internal_Rela rel;
17445
17446 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17447 put_arm_insn (htab, output_bfd, plt0_entry[0],
17448 splt->contents + 0);
17449 put_arm_insn (htab, output_bfd, plt0_entry[1],
17450 splt->contents + 4);
17451 put_arm_insn (htab, output_bfd, plt0_entry[2],
17452 splt->contents + 8);
00a97672
RS		 17453 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17454
8029a119 17455 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17456 rel.r_offset = plt_address + 12;
17457 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17458 rel.r_addend = 0;
17459 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17460 htab->srelplt2->contents);
17461 }
90c14f0c 17462 else if (htab->root.target_os == is_nacl)
99059e56
RM		 17463 arm_nacl_put_plt0 (htab, output_bfd, splt,
17464 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17465 else if (using_thumb_only (htab))
17466 {
17467 got_displacement = got_address - (plt_address + 12);
17468
17469 plt0_entry = elf32_thumb2_plt0_entry;
17470 put_arm_insn (htab, output_bfd, plt0_entry[0],
17471 splt->contents + 0);
17472 put_arm_insn (htab, output_bfd, plt0_entry[1],
17473 splt->contents + 4);
17474 put_arm_insn (htab, output_bfd, plt0_entry[2],
17475 splt->contents + 8);
17476
17477 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17478 }
00a97672
RS		 17479 else
17480 {
17481 got_displacement = got_address - (plt_address + 16);
17482
17483 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17484 put_arm_insn (htab, output_bfd, plt0_entry[0],
17485 splt->contents + 0);
17486 put_arm_insn (htab, output_bfd, plt0_entry[1],
17487 splt->contents + 4);
17488 put_arm_insn (htab, output_bfd, plt0_entry[2],
17489 splt->contents + 8);
17490 put_arm_insn (htab, output_bfd, plt0_entry[3],
17491 splt->contents + 12);
5e681ec4 17492
5e681ec4 17493#ifdef FOUR_WORD_PLT
00a97672
RS		 17494 /* The displacement value goes in the otherwise-unused
17495 last word of the second entry. */
17496 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17497#else
00a97672 17498 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17499#endif
00a97672 17500 }
f7a74f8c 17501 }
252b5132
RH		 17502
17503 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17504 really seem like the right value. */
74541ad4
AM		 17505 if (splt->output_section->owner == output_bfd)
17506 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17507
9bcc30e4 17508 if (htab->root.tlsdesc_plt)
0855e32b
NS		 17509 {
17510 bfd_vma got_address
17511 = sgot->output_section->vma + sgot->output_offset;
17512 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17513 + htab->root.sgot->output_offset);
17514 bfd_vma plt_address
17515 = splt->output_section->vma + splt->output_offset;
17516
b38cadfb 17517 arm_put_trampoline (htab, output_bfd,
9bcc30e4 17518 splt->contents + htab->root.tlsdesc_plt,
0855e32b
NS		 17519 dl_tlsdesc_lazy_trampoline, 6);
17520
17521 bfd_put_32 (output_bfd,
9bcc30e4
L		 17522 gotplt_address + htab->root.tlsdesc_got
17523 - (plt_address + htab->root.tlsdesc_plt)
0855e32b 17524 - dl_tlsdesc_lazy_trampoline[6],
9bcc30e4 17525 splt->contents + htab->root.tlsdesc_plt + 24);
0855e32b 17526 bfd_put_32 (output_bfd,
9bcc30e4 17527 got_address - (plt_address + htab->root.tlsdesc_plt)
0855e32b 17528 - dl_tlsdesc_lazy_trampoline[7],
9bcc30e4 17529 splt->contents + htab->root.tlsdesc_plt + 24 + 4);
0855e32b
NS		 17530 }
17531
17532 if (htab->tls_trampoline)
17533 {
b38cadfb 17534 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17535 splt->contents + htab->tls_trampoline,
17536 tls_trampoline, 3);
17537#ifdef FOUR_WORD_PLT
17538 bfd_put_32 (output_bfd, 0x00000000,
17539 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17540#endif
0855e32b
NS		 17541 }
17542
90c14f0c 17543 if (htab->root.target_os == is_vxworks
0e1862bb
L		 17544 && !bfd_link_pic (info)
17545 && htab->root.splt->size > 0)
00a97672
RS		 17546 {
17547 /* Correct the .rel(a).plt.unloaded relocations. They will have
17548 incorrect symbol indexes. */
17549 int num_plts;
eed62c48 17550 unsigned char *p;
00a97672 17551
362d30a1 17552 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17553 / htab->plt_entry_size);
17554 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17555
17556 for (; num_plts; num_plts--)
17557 {
17558 Elf_Internal_Rela rel;
17559
17560 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17561 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17562 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17563 p += RELOC_SIZE (htab);
17564
17565 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17566 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17567 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17568 p += RELOC_SIZE (htab);
17569 }
17570 }
252b5132
RH		 17571 }
17572
90c14f0c
L		 17573 if (htab->root.target_os == is_nacl
17574 && htab->root.iplt != NULL
17575 && htab->root.iplt->size > 0)
99059e56
RM		 17576 /* NaCl uses a special first entry in .iplt too. */
17577 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17578
252b5132 17579 /* Fill in the first three entries in the global offset table. */
229fcec5 17580 if (sgot)
252b5132 17581 {
229fcec5
MM		 17582 if (sgot->size > 0)
17583 {
17584 if (sdyn == NULL)
17585 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17586 else
17587 bfd_put_32 (output_bfd,
17588 sdyn->output_section->vma + sdyn->output_offset,
17589 sgot->contents);
17590 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17591 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17592 }
252b5132 17593
229fcec5
MM		 17594 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17595 }
252b5132 17596
e8b09b87
CL		 17597 /* At the very end of the .rofixup section is a pointer to the GOT. */
17598 if (htab->fdpic_p && htab->srofixup != NULL)
17599 {
17600 struct elf_link_hash_entry *hgot = htab->root.hgot;
17601
17602 bfd_vma got_value = hgot->root.u.def.value
17603 + hgot->root.u.def.section->output_section->vma
17604 + hgot->root.u.def.section->output_offset;
17605
17606 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17607
17608 /* Make sure we allocated and generated the same number of fixups. */
17609 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17610 }
17611
b34976b6 17612 return TRUE;
252b5132
RH		 17613}
17614
ed7e9d0b
AM		 17615static bfd_boolean
17616elf32_arm_init_file_header (bfd *abfd, struct bfd_link_info *link_info)
ba96a88f 17617{
9b485d32 17618 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17619 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17620 struct elf_segment_map *m;
ba96a88f 17621
ed7e9d0b
AM		 17622 if (!_bfd_elf_init_file_header (abfd, link_info))
17623 return FALSE;
17624
ba96a88f
NC		 17625 i_ehdrp = elf_elfheader (abfd);
17626
94a3258f
PB		 17627 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17628 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
ba96a88f 17629 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17630
93204d3a
PB		 17631 if (link_info)
17632 {
17633 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17634 if (globals != NULL && globals->byteswap_code)
93204d3a 17635 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17636
17637 if (globals->fdpic_p)
17638 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17639 }
3bfcb652
NC		 17640
17641 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17642 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17643 {
17644 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17645 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17646 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17647 else
17648 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17649 }
ac4c9b04
MG		 17650
17651 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17652 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17653 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17654 {
17655 unsigned int j;
17656
17657 if (m->count == 0)
17658 continue;
17659 for (j = 0; j < m->count; j++)
17660 {
f0728ee3 17661 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17662 break;
17663 }
17664 if (j == m->count)
17665 {
17666 m->p_flags = PF_X;
17667 m->p_flags_valid = 1;
17668 }
17669 }
ed7e9d0b 17670 return TRUE;
ba96a88f
NC		 17671}
17672
99e4ae17 17673static enum elf_reloc_type_class
7e612e98
AM		 17674elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17675 const asection *rel_sec ATTRIBUTE_UNUSED,
17676 const Elf_Internal_Rela *rela)
99e4ae17 17677{
f51e552e 17678 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17679 {
17680 case R_ARM_RELATIVE:
17681 return reloc_class_relative;
17682 case R_ARM_JUMP_SLOT:
17683 return reloc_class_plt;
17684 case R_ARM_COPY:
17685 return reloc_class_copy;
109575d7
JW		 17686 case R_ARM_IRELATIVE:
17687 return reloc_class_ifunc;
99e4ae17
AJ		 17688 default:
17689 return reloc_class_normal;
17690 }
17691}
17692
e489d0ae 17693static void
cc364be6 17694arm_final_write_processing (bfd *abfd)
e16bb312 17695{
5a6c6817 17696 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17697}
17698
cc364be6
AM		 17699static bfd_boolean
17700elf32_arm_final_write_processing (bfd *abfd)
06f44071 17701{
cc364be6
AM		 17702 arm_final_write_processing (abfd);
17703 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17704}
17705
40a18ebd
NC		 17706/* Return TRUE if this is an unwinding table entry. */
17707
17708static bfd_boolean
17709is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17710{
0112cd26
NC		 17711 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17712 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17713}
17714
17715
17716/* Set the type and flags for an ARM section. We do this by
17717 the section name, which is a hack, but ought to work. */
17718
17719static bfd_boolean
17720elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17721{
17722 const char * name;
17723
fd361982 17724 name = bfd_section_name (sec);
40a18ebd
NC		 17725
17726 if (is_arm_elf_unwind_section_name (abfd, name))
17727 {
17728 hdr->sh_type = SHT_ARM_EXIDX;
17729 hdr->sh_flags |= SHF_LINK_ORDER;
17730 }
ac4c9b04 17731
f0728ee3
AV		 17732 if (sec->flags & SEC_ELF_PURECODE)
17733 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17734
40a18ebd
NC		 17735 return TRUE;
17736}
17737
6dc132d9
L		 17738/* Handle an ARM specific section when reading an object file. This is
17739 called when bfd_section_from_shdr finds a section with an unknown
17740 type. */
40a18ebd
NC		 17741
17742static bfd_boolean
17743elf32_arm_section_from_shdr (bfd *abfd,
17744 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17745 const char *name,
17746 int shindex)
40a18ebd
NC		 17747{
17748 /* There ought to be a place to keep ELF backend specific flags, but
17749 at the moment there isn't one. We just keep track of the
17750 sections by their name, instead. Fortunately, the ABI gives
17751 names for all the ARM specific sections, so we will probably get
17752 away with this. */
17753 switch (hdr->sh_type)
17754 {
17755 case SHT_ARM_EXIDX:
0951f019
RE		 17756 case SHT_ARM_PREEMPTMAP:
17757 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17758 break;
17759
17760 default:
17761 return FALSE;
17762 }
17763
6dc132d9 17764 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17765 return FALSE;
17766
17767 return TRUE;
17768}
e489d0ae 17769
44444f50
NC		 17770static _arm_elf_section_data *
17771get_arm_elf_section_data (asection * sec)
17772{
47b2e99c
JZ		 17773 if (sec && sec->owner && is_arm_elf (sec->owner))
17774 return elf32_arm_section_data (sec);
44444f50
NC		 17775 else
17776 return NULL;
8e3de13a
NC		 17777}
17778
4e617b1e
PB		 17779typedef struct
17780{
57402f1e 17781 void *flaginfo;
4e617b1e 17782 struct bfd_link_info *info;
91a5743d
PB		 17783 asection *sec;
17784 int sec_shndx;
6e0b88f1
AM		 17785 int (*func) (void *, const char *, Elf_Internal_Sym *,
17786 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17787} output_arch_syminfo;
17788
17789enum map_symbol_type
17790{
17791 ARM_MAP_ARM,
17792 ARM_MAP_THUMB,
17793 ARM_MAP_DATA
17794};
17795
17796
7413f23f 17797/* Output a single mapping symbol. */
4e617b1e
PB		 17798
17799static bfd_boolean
7413f23f
DJ		 17800elf32_arm_output_map_sym (output_arch_syminfo *osi,
17801 enum map_symbol_type type,
17802 bfd_vma offset)
4e617b1e
PB		 17803{
17804 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17805 Elf_Internal_Sym sym;
17806
91a5743d
PB		 17807 sym.st_value = osi->sec->output_section->vma
17808 + osi->sec->output_offset
17809 + offset;
4e617b1e
PB		 17810 sym.st_size = 0;
17811 sym.st_other = 0;
17812 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17813 sym.st_shndx = osi->sec_shndx;
35fc36a8 17814 sym.st_target_internal = 0;
fe33d2fa 17815 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17816 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17817}
17818
34e77a92
RS		 17819/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17820 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17821
17822static bfd_boolean
34e77a92
RS		 17823elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17824 bfd_boolean is_iplt_entry_p,
17825 union gotplt_union *root_plt,
17826 struct arm_plt_info *arm_plt)
4e617b1e 17827{
4e617b1e 17828 struct elf32_arm_link_hash_table *htab;
34e77a92 17829 bfd_vma addr, plt_header_size;
4e617b1e 17830
34e77a92 17831 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17832 return TRUE;
17833
4dfe6ac6
NC		 17834 htab = elf32_arm_hash_table (osi->info);
17835 if (htab == NULL)
17836 return FALSE;
17837
34e77a92
RS		 17838 if (is_iplt_entry_p)
17839 {
17840 osi->sec = htab->root.iplt;
17841 plt_header_size = 0;
17842 }
17843 else
17844 {
17845 osi->sec = htab->root.splt;
17846 plt_header_size = htab->plt_header_size;
17847 }
17848 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
17849 (osi->info->output_bfd, osi->sec->output_section));
17850
17851 addr = root_plt->offset & -2;
90c14f0c 17852 if (htab->root.target_os == is_symbian)
4e617b1e 17853 {
7413f23f 17854 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17855 return FALSE;
7413f23f 17856 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 17857 return FALSE;
17858 }
90c14f0c 17859 else if (htab->root.target_os == is_vxworks)
4e617b1e 17860 {
7413f23f 17861 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17862 return FALSE;
7413f23f 17863 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 17864 return FALSE;
7413f23f 17865 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 17866 return FALSE;
7413f23f 17867 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 17868 return FALSE;
17869 }
90c14f0c 17870 else if (htab->root.target_os == is_nacl)
b38cadfb
NC		 17871 {
17872 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17873 return FALSE;
17874 }
7801f98f
CL		 17875 else if (htab->fdpic_p)
17876 {
59029f57
CL		 17877 enum map_symbol_type type = using_thumb_only(htab)
17878 ? ARM_MAP_THUMB
17879 : ARM_MAP_ARM;
17880
7801f98f 17881 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 17882 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
17883 return FALSE;
59029f57 17884 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 17885 return FALSE;
7801f98f 17886 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 17887 return FALSE;
7801f98f 17888 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 17889 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
17890 return FALSE;
7801f98f 17891 }
eed94f8f
NC		 17892 else if (using_thumb_only (htab))
17893 {
17894 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17895 return FALSE;
6a631e86 17896 }
4e617b1e
PB		 17897 else
17898 {
34e77a92 17899 bfd_boolean thumb_stub_p;
bd97cb95 17900
34e77a92
RS		 17901 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17902 if (thumb_stub_p)
4e617b1e 17903 {
7413f23f 17904 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17905 return FALSE;
17906 }
17907#ifdef FOUR_WORD_PLT
7413f23f 17908 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17909 return FALSE;
7413f23f 17910 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17911 return FALSE;
17912#else
906e58ca 17913 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17914 so only need to output a mapping symbol for the first PLT entry and
17915 entries with thumb thunks. */
34e77a92 17916 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17917 {
7413f23f 17918 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17919 return FALSE;
17920 }
17921#endif
17922 }
17923
17924 return TRUE;
17925}
17926
34e77a92
RS		 17927/* Output mapping symbols for PLT entries associated with H. */
17928
17929static bfd_boolean
17930elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17931{
17932 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17933 struct elf32_arm_link_hash_entry *eh;
17934
17935 if (h->root.type == bfd_link_hash_indirect)
17936 return TRUE;
17937
17938 if (h->root.type == bfd_link_hash_warning)
17939 /* When warning symbols are created, they **replace** the "real"
17940 entry in the hash table, thus we never get to see the real
17941 symbol in a hash traversal. So look at it now. */
17942 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17943
17944 eh = (struct elf32_arm_link_hash_entry *) h;
17945 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17946 &h->plt, &eh->plt);
17947}
17948
4f4faa4d
TP		 17949/* Bind a veneered symbol to its veneer identified by its hash entry
17950 STUB_ENTRY. The veneered location thus loose its symbol. */
17951
17952static void
17953arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17954{
17955 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17956
17957 BFD_ASSERT (hash);
17958 hash->root.root.u.def.section = stub_entry->stub_sec;
17959 hash->root.root.u.def.value = stub_entry->stub_offset;
17960 hash->root.size = stub_entry->stub_size;
17961}
17962
7413f23f
DJ		 17963/* Output a single local symbol for a generated stub. */
17964
17965static bfd_boolean
17966elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17967 bfd_vma offset, bfd_vma size)
17968{
7413f23f
DJ		 17969 Elf_Internal_Sym sym;
17970
7413f23f
DJ		 17971 sym.st_value = osi->sec->output_section->vma
17972 + osi->sec->output_offset
17973 + offset;
17974 sym.st_size = size;
17975 sym.st_other = 0;
17976 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17977 sym.st_shndx = osi->sec_shndx;
35fc36a8 17978 sym.st_target_internal = 0;
57402f1e 17979 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17980}
4e617b1e 17981
da5938a2 17982static bfd_boolean
8029a119
NC		 17983arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17984 void * in_arg)
da5938a2
NC		 17985{
17986 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17987 asection *stub_sec;
17988 bfd_vma addr;
7413f23f 17989 char *stub_name;
9a008db3 17990 output_arch_syminfo *osi;
d3ce72d0 17991 const insn_sequence *template_sequence;
461a49ca
DJ		 17992 enum stub_insn_type prev_type;
17993 int size;
17994 int i;
17995 enum map_symbol_type sym_type;
da5938a2
NC		 17996
17997 /* Massage our args to the form they really have. */
17998 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17999 osi = (output_arch_syminfo *) in_arg;
da5938a2 18000
da5938a2
NC		 18001 stub_sec = stub_entry->stub_sec;
18002
18003 /* Ensure this stub is attached to the current section being
7413f23f 18004 processed. */
da5938a2
NC		 18005 if (stub_sec != osi->sec)
18006 return TRUE;
18007
7413f23f 18008 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18009 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18010
18011 if (arm_stub_sym_claimed (stub_entry->stub_type))
18012 arm_stub_claim_sym (stub_entry);
18013 else
7413f23f 18014 {
4f4faa4d
TP		 18015 stub_name = stub_entry->output_name;
18016 switch (template_sequence[0].type)
18017 {
18018 case ARM_TYPE:
18019 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18020 stub_entry->stub_size))
18021 return FALSE;
18022 break;
18023 case THUMB16_TYPE:
18024 case THUMB32_TYPE:
18025 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18026 stub_entry->stub_size))
18027 return FALSE;
18028 break;
18029 default:
18030 BFD_FAIL ();
18031 return 0;
18032 }
7413f23f 18033 }
da5938a2 18034
461a49ca
DJ		 18035 prev_type = DATA_TYPE;
18036 size = 0;
18037 for (i = 0; i < stub_entry->stub_template_size; i++)
18038 {
d3ce72d0 18039 switch (template_sequence[i].type)
461a49ca
DJ		 18040 {
18041 case ARM_TYPE:
18042 sym_type = ARM_MAP_ARM;
18043 break;
18044
18045 case THUMB16_TYPE:
48229727 18046 case THUMB32_TYPE:
461a49ca
DJ		 18047 sym_type = ARM_MAP_THUMB;
18048 break;
18049
18050 case DATA_TYPE:
18051 sym_type = ARM_MAP_DATA;
18052 break;
18053
18054 default:
18055 BFD_FAIL ();
4e31c731 18056 return FALSE;
461a49ca
DJ		 18057 }
18058
d3ce72d0 18059 if (template_sequence[i].type != prev_type)
461a49ca 18060 {
d3ce72d0 18061 prev_type = template_sequence[i].type;
461a49ca
DJ		 18062 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18063 return FALSE;
18064 }
18065
d3ce72d0 18066 switch (template_sequence[i].type)
461a49ca
DJ		 18067 {
18068 case ARM_TYPE:
48229727 18069 case THUMB32_TYPE:
461a49ca
DJ		 18070 size += 4;
18071 break;
18072
18073 case THUMB16_TYPE:
18074 size += 2;
18075 break;
18076
18077 case DATA_TYPE:
18078 size += 4;
18079 break;
18080
18081 default:
18082 BFD_FAIL ();
4e31c731 18083 return FALSE;
461a49ca
DJ		 18084 }
18085 }
18086
da5938a2
NC		 18087 return TRUE;
18088}
18089
33811162
DG		 18090/* Output mapping symbols for linker generated sections,
18091 and for those data-only sections that do not have a
18092 $d. */
4e617b1e
PB		 18093
18094static bfd_boolean
18095elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18096 struct bfd_link_info *info,
57402f1e 18097 void *flaginfo,
6e0b88f1
AM		 18098 int (*func) (void *, const char *,
18099 Elf_Internal_Sym *,
18100 asection *,
18101 struct elf_link_hash_entry *))
4e617b1e
PB		 18102{
18103 output_arch_syminfo osi;
18104 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18105 bfd_vma offset;
18106 bfd_size_type size;
33811162 18107 bfd *input_bfd;
4e617b1e
PB		 18108
18109 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18110 if (htab == NULL)
18111 return FALSE;
18112
906e58ca 18113 check_use_blx (htab);
91a5743d 18114
57402f1e 18115 osi.flaginfo = flaginfo;
4e617b1e
PB		 18116 osi.info = info;
18117 osi.func = func;
906e58ca 18118
33811162
DG		 18119 /* Add a $d mapping symbol to data-only sections that
18120 don't have any mapping symbol. This may result in (harmless) redundant
18121 mapping symbols. */
18122 for (input_bfd = info->input_bfds;
18123 input_bfd != NULL;
c72f2fb2 18124 input_bfd = input_bfd->link.next)
33811162
DG		 18125 {
18126 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18127 for (osi.sec = input_bfd->sections;
18128 osi.sec != NULL;
18129 osi.sec = osi.sec->next)
18130 {
18131 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18132 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18133 != 0)
33811162
DG		 18134 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18135 == SEC_HAS_CONTENTS
18136 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18137 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18138 && osi.sec->size > 0
18139 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18140 {
18141 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18142 (output_bfd, osi.sec->output_section);
18143 if (osi.sec_shndx != (int)SHN_BAD)
18144 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18145 }
18146 }
18147 }
18148
91a5743d
PB		 18149 /* ARM->Thumb glue. */
18150 if (htab->arm_glue_size > 0)
18151 {
3d4d4302
AM		 18152 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18153 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18154
18155 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18156 (output_bfd, osi.sec->output_section);
0e1862bb 18157 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18158 || htab->pic_veneer)
18159 size = ARM2THUMB_PIC_GLUE_SIZE;
18160 else if (htab->use_blx)
18161 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18162 else
18163 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18164
91a5743d
PB		 18165 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18166 {
7413f23f
DJ		 18167 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18168 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18169 }
18170 }
18171
18172 /* Thumb->ARM glue. */
18173 if (htab->thumb_glue_size > 0)
18174 {
3d4d4302
AM		 18175 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18176 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18177
18178 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18179 (output_bfd, osi.sec->output_section);
18180 size = THUMB2ARM_GLUE_SIZE;
18181
18182 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18183 {
7413f23f
DJ		 18184 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18185 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18186 }
18187 }
18188
845b51d6
PB		 18189 /* ARMv4 BX veneers. */
18190 if (htab->bx_glue_size > 0)
18191 {
3d4d4302
AM		 18192 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18193 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18194
18195 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18196 (output_bfd, osi.sec->output_section);
18197
7413f23f 18198 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18199 }
18200
8029a119
NC		 18201 /* Long calls stubs. */
18202 if (htab->stub_bfd && htab->stub_bfd->sections)
18203 {
da5938a2 18204 asection* stub_sec;
8029a119 18205
da5938a2
NC		 18206 for (stub_sec = htab->stub_bfd->sections;
18207 stub_sec != NULL;
8029a119
NC		 18208 stub_sec = stub_sec->next)
18209 {
18210 /* Ignore non-stub sections. */
18211 if (!strstr (stub_sec->name, STUB_SUFFIX))
18212 continue;
da5938a2 18213
8029a119 18214 osi.sec = stub_sec;
da5938a2 18215
8029a119
NC		 18216 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18217 (output_bfd, osi.sec->output_section);
da5938a2 18218
8029a119
NC		 18219 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18220 }
18221 }
da5938a2 18222
91a5743d 18223 /* Finally, output mapping symbols for the PLT. */
34e77a92 18224 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18225 {
34e77a92
RS		 18226 osi.sec = htab->root.splt;
18227 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18228 (output_bfd, osi.sec->output_section));
18229
18230 /* Output mapping symbols for the plt header. SymbianOS does not have a
18231 plt header. */
90c14f0c 18232 if (htab->root.target_os == is_vxworks)
34e77a92
RS		 18233 {
18234 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18235 if (!bfd_link_pic (info))
34e77a92
RS		 18236 {
18237 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18238 return FALSE;
18239 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18240 return FALSE;
18241 }
18242 }
90c14f0c 18243 else if (htab->root.target_os == is_nacl)
b38cadfb
NC		 18244 {
18245 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18246 return FALSE;
18247 }
59029f57 18248 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18249 {
18250 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18251 return FALSE;
18252 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18253 return FALSE;
18254 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18255 return FALSE;
18256 }
90c14f0c 18257 else if (htab->root.target_os != is_symbian && !htab->fdpic_p)
4e617b1e 18258 {
7413f23f 18259 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18260 return FALSE;
34e77a92
RS		 18261#ifndef FOUR_WORD_PLT
18262 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18263 return FALSE;
34e77a92 18264#endif
4e617b1e
PB		 18265 }
18266 }
90c14f0c
L		 18267 if (htab->root.target_os == is_nacl
18268 && htab->root.iplt
18269 && htab->root.iplt->size > 0)
99059e56
RM		 18270 {
18271 /* NaCl uses a special first entry in .iplt too. */
18272 osi.sec = htab->root.iplt;
18273 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18274 (output_bfd, osi.sec->output_section));
18275 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18276 return FALSE;
18277 }
34e77a92
RS		 18278 if ((htab->root.splt && htab->root.splt->size > 0)
18279 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18280 {
34e77a92
RS		 18281 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18282 for (input_bfd = info->input_bfds;
18283 input_bfd != NULL;
c72f2fb2 18284 input_bfd = input_bfd->link.next)
34e77a92
RS		 18285 {
18286 struct arm_local_iplt_info **local_iplt;
18287 unsigned int i, num_syms;
4e617b1e 18288
34e77a92
RS		 18289 local_iplt = elf32_arm_local_iplt (input_bfd);
18290 if (local_iplt != NULL)
18291 {
18292 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18293 for (i = 0; i < num_syms; i++)
18294 if (local_iplt[i] != NULL
18295 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18296 &local_iplt[i]->root,
18297 &local_iplt[i]->arm))
18298 return FALSE;
18299 }
18300 }
18301 }
9bcc30e4 18302 if (htab->root.tlsdesc_plt != 0)
0855e32b
NS		 18303 {
18304 /* Mapping symbols for the lazy tls trampoline. */
9bcc30e4
L		 18305 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM,
18306 htab->root.tlsdesc_plt))
0855e32b 18307 return FALSE;
b38cadfb 18308
0855e32b 18309 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
9bcc30e4 18310 htab->root.tlsdesc_plt + 24))
0855e32b
NS		 18311 return FALSE;
18312 }
18313 if (htab->tls_trampoline != 0)
18314 {
18315 /* Mapping symbols for the tls trampoline. */
18316 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18317 return FALSE;
18318#ifdef FOUR_WORD_PLT
18319 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18320 htab->tls_trampoline + 12))
18321 return FALSE;
b38cadfb 18322#endif
0855e32b 18323 }
b38cadfb 18324
4e617b1e
PB		 18325 return TRUE;
18326}
18327
54ddd295
TP		 18328/* Filter normal symbols of CMSE entry functions of ABFD to include in
18329 the import library. All SYMCOUNT symbols of ABFD can be examined
18330 from their pointers in SYMS. Pointers of symbols to keep should be
18331 stored continuously at the beginning of that array.
18332
18333 Returns the number of symbols to keep. */
18334
18335static unsigned int
18336elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18337 struct bfd_link_info *info,
18338 asymbol **syms, long symcount)
18339{
18340 size_t maxnamelen;
18341 char *cmse_name;
18342 long src_count, dst_count = 0;
18343 struct elf32_arm_link_hash_table *htab;
18344
18345 htab = elf32_arm_hash_table (info);
18346 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18347 symcount = 0;
18348
18349 maxnamelen = 128;
18350 cmse_name = (char *) bfd_malloc (maxnamelen);
7a0fb7be
NC		 18351 BFD_ASSERT (cmse_name);
18352
54ddd295
TP		 18353 for (src_count = 0; src_count < symcount; src_count++)
18354 {
18355 struct elf32_arm_link_hash_entry *cmse_hash;
18356 asymbol *sym;
18357 flagword flags;
18358 char *name;
18359 size_t namelen;
18360
18361 sym = syms[src_count];
18362 flags = sym->flags;
18363 name = (char *) bfd_asymbol_name (sym);
18364
18365 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18366 continue;
18367 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18368 continue;
18369
18370 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18371 if (namelen > maxnamelen)
18372 {
18373 cmse_name = (char *)
18374 bfd_realloc (cmse_name, namelen);
18375 maxnamelen = namelen;
18376 }
18377 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18378 cmse_hash = (struct elf32_arm_link_hash_entry *)
18379 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18380
18381 if (!cmse_hash
18382 || (cmse_hash->root.root.type != bfd_link_hash_defined
18383 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18384 || cmse_hash->root.type != STT_FUNC)
18385 continue;
18386
54ddd295
TP		 18387 syms[dst_count++] = sym;
18388 }
18389 free (cmse_name);
18390
18391 syms[dst_count] = NULL;
18392
18393 return dst_count;
18394}
18395
18396/* Filter symbols of ABFD to include in the import library. All
18397 SYMCOUNT symbols of ABFD can be examined from their pointers in
18398 SYMS. Pointers of symbols to keep should be stored continuously at
18399 the beginning of that array.
18400
18401 Returns the number of symbols to keep. */
18402
18403static unsigned int
18404elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18405 struct bfd_link_info *info,
18406 asymbol **syms, long symcount)
18407{
18408 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18409
046734ff
TP		 18410 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18411 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18412 library to be a relocatable object file. */
18413 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18414 if (globals->cmse_implib)
18415 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18416 else
18417 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18418}
18419
e489d0ae
PB		 18420/* Allocate target specific section data. */
18421
18422static bfd_boolean
18423elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18424{
f592407e
AM		 18425 if (!sec->used_by_bfd)
18426 {
18427 _arm_elf_section_data *sdata;
986f0783 18428 size_t amt = sizeof (*sdata);
e489d0ae 18429
21d799b5 18430 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18431 if (sdata == NULL)
18432 return FALSE;
18433 sec->used_by_bfd = sdata;
18434 }
e489d0ae
PB		 18435
18436 return _bfd_elf_new_section_hook (abfd, sec);
18437}
18438
18439
18440/* Used to order a list of mapping symbols by address. */
18441
18442static int
18443elf32_arm_compare_mapping (const void * a, const void * b)
18444{
7f6a71ff
JM		 18445 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18446 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18447
18448 if (amap->vma > bmap->vma)
18449 return 1;
18450 else if (amap->vma < bmap->vma)
18451 return -1;
18452 else if (amap->type > bmap->type)
18453 /* Ensure results do not depend on the host qsort for objects with
18454 multiple mapping symbols at the same address by sorting on type
18455 after vma. */
18456 return 1;
18457 else if (amap->type < bmap->type)
18458 return -1;
18459 else
18460 return 0;
e489d0ae
PB		 18461}
18462
2468f9c9
PB		 18463/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18464
18465static unsigned long
18466offset_prel31 (unsigned long addr, bfd_vma offset)
18467{
18468 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18469}
18470
18471/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18472 relocations. */
18473
18474static void
18475copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18476{
18477 unsigned long first_word = bfd_get_32 (output_bfd, from);
18478 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18479
2468f9c9
PB		 18480 /* High bit of first word is supposed to be zero. */
18481 if ((first_word & 0x80000000ul) == 0)
18482 first_word = offset_prel31 (first_word, offset);
b38cadfb 18483
2468f9c9
PB		 18484 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18485 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18486 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18487 second_word = offset_prel31 (second_word, offset);
b38cadfb 18488
2468f9c9
PB		 18489 bfd_put_32 (output_bfd, first_word, to);
18490 bfd_put_32 (output_bfd, second_word, to + 4);
18491}
e489d0ae 18492
48229727
JB		 18493/* Data for make_branch_to_a8_stub(). */
18494
b38cadfb
NC		 18495struct a8_branch_to_stub_data
18496{
48229727
JB		 18497 asection *writing_section;
18498 bfd_byte *contents;
18499};
18500
18501
18502/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18503 places for a particular section. */
18504
18505static bfd_boolean
18506make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18507 void *in_arg)
48229727
JB		 18508{
18509 struct elf32_arm_stub_hash_entry *stub_entry;
18510 struct a8_branch_to_stub_data *data;
18511 bfd_byte *contents;
18512 unsigned long branch_insn;
18513 bfd_vma veneered_insn_loc, veneer_entry_loc;
18514 bfd_signed_vma branch_offset;
18515 bfd *abfd;
8d9d9490 18516 unsigned int loc;
48229727
JB		 18517
18518 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18519 data = (struct a8_branch_to_stub_data *) in_arg;
18520
18521 if (stub_entry->target_section != data->writing_section
4563a860 18522 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18523 return TRUE;
18524
18525 contents = data->contents;
18526
8d9d9490
TP		 18527 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18528 generated when both source and target are in the same section. */
48229727
JB		 18529 veneered_insn_loc = stub_entry->target_section->output_section->vma
18530 + stub_entry->target_section->output_offset
8d9d9490 18531 + stub_entry->source_value;
48229727
JB		 18532
18533 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18534 + stub_entry->stub_sec->output_offset
18535 + stub_entry->stub_offset;
18536
18537 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18538 veneered_insn_loc &= ~3u;
18539
18540 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18541
18542 abfd = stub_entry->target_section->owner;
8d9d9490 18543 loc = stub_entry->source_value;
48229727
JB		 18544
18545 /* We attempt to avoid this condition by setting stubs_always_after_branch
18546 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18547 This check is just to be on the safe side... */
18548 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18549 {
871b3ab2 18550 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18551 "allocated in unsafe location"), abfd);
48229727
JB		 18552 return FALSE;
18553 }
18554
18555 switch (stub_entry->stub_type)
18556 {
18557 case arm_stub_a8_veneer_b:
18558 case arm_stub_a8_veneer_b_cond:
18559 branch_insn = 0xf0009000;
18560 goto jump24;
18561
18562 case arm_stub_a8_veneer_blx:
18563 branch_insn = 0xf000e800;
18564 goto jump24;
18565
18566 case arm_stub_a8_veneer_bl:
18567 {
18568 unsigned int i1, j1, i2, j2, s;
18569
18570 branch_insn = 0xf000d000;
18571
18572 jump24:
18573 if (branch_offset < -16777216 || branch_offset > 16777214)
18574 {
18575 /* There's not much we can do apart from complain if this
18576 happens. */
871b3ab2 18577 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18578 "of range (input file too large)"), abfd);
48229727
JB		 18579 return FALSE;
18580 }
18581
18582 /* i1 = not(j1 eor s), so:
18583 not i1 = j1 eor s
18584 j1 = (not i1) eor s. */
18585
18586 branch_insn |= (branch_offset >> 1) & 0x7ff;
18587 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18588 i2 = (branch_offset >> 22) & 1;
18589 i1 = (branch_offset >> 23) & 1;
18590 s = (branch_offset >> 24) & 1;
18591 j1 = (!i1) ^ s;
18592 j2 = (!i2) ^ s;
18593 branch_insn |= j2 << 11;
18594 branch_insn |= j1 << 13;
18595 branch_insn |= s << 26;
18596 }
18597 break;
18598
18599 default:
18600 BFD_FAIL ();
18601 return FALSE;
18602 }
18603
8d9d9490
TP		 18604 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18605 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18606
18607 return TRUE;
18608}
18609
a504d23a
LA		 18610/* Beginning of stm32l4xx work-around. */
18611
18612/* Functions encoding instructions necessary for the emission of the
18613 fix-stm32l4xx-629360.
18614 Encoding is extracted from the
18615 ARM (C) Architecture Reference Manual
18616 ARMv7-A and ARMv7-R edition
18617 ARM DDI 0406C.b (ID072512). */
18618
18619static inline bfd_vma
82188b29 18620create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18621{
18622 /* A8.8.18 B (A8-334)
18623 B target_address (Encoding T4). */
18624 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18625 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18626 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18627
a504d23a
LA		 18628 int s = ((branch_offset & 0x1000000) >> 24);
18629 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18630 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18631
18632 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18633 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18634
18635 bfd_vma patched_inst = 0xf0009000
18636 | s << 26 /* S. */
18637 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18638 | j1 << 13 /* J1. */
18639 | j2 << 11 /* J2. */
18640 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18641
18642 return patched_inst;
18643}
18644
18645static inline bfd_vma
18646create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18647{
18648 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18649 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18650 bfd_vma patched_inst = 0xe8900000
18651 | (/*W=*/wback << 21)
18652 | (base_reg << 16)
18653 | (reg_mask & 0x0000ffff);
18654
18655 return patched_inst;
18656}
18657
18658static inline bfd_vma
18659create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18660{
18661 /* A8.8.60 LDMDB/LDMEA (A8-402)
18662 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18663 bfd_vma patched_inst = 0xe9100000
18664 | (/*W=*/wback << 21)
18665 | (base_reg << 16)
18666 | (reg_mask & 0x0000ffff);
18667
18668 return patched_inst;
18669}
18670
18671static inline bfd_vma
18672create_instruction_mov (int target_reg, int source_reg)
18673{
18674 /* A8.8.103 MOV (register) (A8-486)
18675 MOV Rd, Rm (Encoding T1). */
18676 bfd_vma patched_inst = 0x4600
18677 | (target_reg & 0x7)
18678 | ((target_reg & 0x8) >> 3) << 7
18679 | (source_reg << 3);
18680
18681 return patched_inst;
18682}
18683
18684static inline bfd_vma
18685create_instruction_sub (int target_reg, int source_reg, int value)
18686{
18687 /* A8.8.221 SUB (immediate) (A8-708)
18688 SUB Rd, Rn, #value (Encoding T3). */
18689 bfd_vma patched_inst = 0xf1a00000
18690 | (target_reg << 8)
18691 | (source_reg << 16)
18692 | (/*S=*/0 << 20)
18693 | ((value & 0x800) >> 11) << 26
18694 | ((value & 0x700) >> 8) << 12
18695 | (value & 0x0ff);
18696
18697 return patched_inst;
18698}
18699
18700static inline bfd_vma
9239bbd3 18701create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18702 int first_reg)
18703{
18704 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18705 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18706 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18707 | (/*W=*/wback << 21)
18708 | (base_reg << 16)
9239bbd3
CM		 18709 | (num_words & 0x000000ff)
18710 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18711 | (first_reg & 0x00000001) << 22;
18712
18713 return patched_inst;
18714}
18715
18716static inline bfd_vma
9239bbd3
CM		 18717create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18718 int first_reg)
a504d23a
LA		 18719{
18720 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18721 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18722 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18723 | (base_reg << 16)
9239bbd3
CM		 18724 | (num_words & 0x000000ff)
18725 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18726 | (first_reg & 0x00000001) << 22;
18727
18728 return patched_inst;
18729}
18730
18731static inline bfd_vma
18732create_instruction_udf_w (int value)
18733{
18734 /* A8.8.247 UDF (A8-758)
18735 Undefined (Encoding T2). */
18736 bfd_vma patched_inst = 0xf7f0a000
18737 | (value & 0x00000fff)
18738 | (value & 0x000f0000) << 16;
18739
18740 return patched_inst;
18741}
18742
18743static inline bfd_vma
18744create_instruction_udf (int value)
18745{
18746 /* A8.8.247 UDF (A8-758)
18747 Undefined (Encoding T1). */
18748 bfd_vma patched_inst = 0xde00
18749 | (value & 0xff);
18750
18751 return patched_inst;
18752}
18753
18754/* Functions writing an instruction in memory, returning the next
18755 memory position to write to. */
18756
18757static inline bfd_byte *
18758push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18759 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18760{
18761 put_thumb2_insn (htab, output_bfd, insn, pt);
18762 return pt + 4;
18763}
18764
18765static inline bfd_byte *
18766push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18767 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18768{
18769 put_thumb_insn (htab, output_bfd, insn, pt);
18770 return pt + 2;
18771}
18772
18773/* Function filling up a region in memory with T1 and T2 UDFs taking
18774 care of alignment. */
18775
18776static bfd_byte *
18777stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18778 bfd * output_bfd,
18779 const bfd_byte * const base_stub_contents,
18780 bfd_byte * const from_stub_contents,
18781 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18782{
18783 bfd_byte *current_stub_contents = from_stub_contents;
18784
18785 /* Fill the remaining of the stub with deterministic contents : UDF
18786 instructions.
18787 Check if realignment is needed on modulo 4 frontier using T1, to
18788 further use T2. */
18789 if ((current_stub_contents < end_stub_contents)
18790 && !((current_stub_contents - base_stub_contents) % 2)
18791 && ((current_stub_contents - base_stub_contents) % 4))
18792 current_stub_contents =
18793 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18794 create_instruction_udf (0));
18795
18796 for (; current_stub_contents < end_stub_contents;)
18797 current_stub_contents =
18798 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18799 create_instruction_udf_w (0));
18800
18801 return current_stub_contents;
18802}
18803
18804/* Functions writing the stream of instructions equivalent to the
18805 derived sequence for ldmia, ldmdb, vldm respectively. */
18806
18807static void
18808stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18809 bfd * output_bfd,
18810 const insn32 initial_insn,
18811 const bfd_byte *const initial_insn_addr,
18812 bfd_byte *const base_stub_contents)
18813{
18814 int wback = (initial_insn & 0x00200000) >> 21;
18815 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18816 int insn_all_registers = initial_insn & 0x0000ffff;
18817 int insn_low_registers, insn_high_registers;
18818 int usable_register_mask;
b25e998d 18819 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18820 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18821 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18822 bfd_byte *current_stub_contents = base_stub_contents;
18823
18824 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18825
18826 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18827 smaller than 8 registers load sequences that do not cause the
18828 hardware issue. */
18829 if (nb_registers <= 8)
18830 {
18831 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18832 current_stub_contents =
18833 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18834 initial_insn);
18835
18836 /* B initial_insn_addr+4. */
18837 if (!restore_pc)
18838 current_stub_contents =
18839 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18840 create_instruction_branch_absolute
82188b29 18841 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18842
18843 /* Fill the remaining of the stub with deterministic contents. */
18844 current_stub_contents =
18845 stm32l4xx_fill_stub_udf (htab, output_bfd,
18846 base_stub_contents, current_stub_contents,
18847 base_stub_contents +
18848 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18849
18850 return;
18851 }
18852
18853 /* - reg_list[13] == 0. */
18854 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
18855
18856 /* - reg_list[14] & reg_list[15] != 1. */
18857 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18858
18859 /* - if (wback==1) reg_list[rn] == 0. */
18860 BFD_ASSERT (!wback || !restore_rn);
18861
18862 /* - nb_registers > 8. */
b25e998d 18863 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18864
18865 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18866
18867 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18868 - One with the 7 lowest registers (register mask 0x007F)
18869 This LDM will finally contain between 2 and 7 registers
18870 - One with the 7 highest registers (register mask 0xDF80)
18871 This ldm will finally contain between 2 and 7 registers. */
18872 insn_low_registers = insn_all_registers & 0x007F;
18873 insn_high_registers = insn_all_registers & 0xDF80;
18874
18875 /* A spare register may be needed during this veneer to temporarily
18876 handle the base register. This register will be restored with the
18877 last LDM operation.
18878 The usable register may be any general purpose register (that
18879 excludes PC, SP, LR : register mask is 0x1FFF). */
18880 usable_register_mask = 0x1FFF;
18881
18882 /* Generate the stub function. */
18883 if (wback)
18884 {
18885 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18886 current_stub_contents =
18887 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18888 create_instruction_ldmia
18889 (rn, /*wback=*/1, insn_low_registers));
18890
18891 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18892 current_stub_contents =
18893 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18894 create_instruction_ldmia
18895 (rn, /*wback=*/1, insn_high_registers));
18896 if (!restore_pc)
18897 {
18898 /* B initial_insn_addr+4. */
18899 current_stub_contents =
18900 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18901 create_instruction_branch_absolute
82188b29 18902 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18903 }
18904 }
18905 else /* if (!wback). */
18906 {
18907 ri = rn;
18908
18909 /* If Rn is not part of the high-register-list, move it there. */
18910 if (!(insn_high_registers & (1 << rn)))
18911 {
18912 /* Choose a Ri in the high-register-list that will be restored. */
18913 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18914
18915 /* MOV Ri, Rn. */
18916 current_stub_contents =
18917 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18918 create_instruction_mov (ri, rn));
18919 }
18920
18921 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18922 current_stub_contents =
18923 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18924 create_instruction_ldmia
18925 (ri, /*wback=*/1, insn_low_registers));
18926
18927 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18928 current_stub_contents =
18929 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18930 create_instruction_ldmia
18931 (ri, /*wback=*/0, insn_high_registers));
18932
18933 if (!restore_pc)
18934 {
18935 /* B initial_insn_addr+4. */
18936 current_stub_contents =
18937 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18938 create_instruction_branch_absolute
82188b29 18939 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18940 }
18941 }
18942
18943 /* Fill the remaining of the stub with deterministic contents. */
18944 current_stub_contents =
18945 stm32l4xx_fill_stub_udf (htab, output_bfd,
18946 base_stub_contents, current_stub_contents,
18947 base_stub_contents +
18948 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18949}
18950
18951static void
18952stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18953 bfd * output_bfd,
18954 const insn32 initial_insn,
18955 const bfd_byte *const initial_insn_addr,
18956 bfd_byte *const base_stub_contents)
18957{
18958 int wback = (initial_insn & 0x00200000) >> 21;
18959 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18960 int insn_all_registers = initial_insn & 0x0000ffff;
18961 int insn_low_registers, insn_high_registers;
18962 int usable_register_mask;
18963 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18964 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18965 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18966 bfd_byte *current_stub_contents = base_stub_contents;
18967
18968 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18969
18970 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18971 smaller than 8 registers load sequences that do not cause the
18972 hardware issue. */
18973 if (nb_registers <= 8)
18974 {
18975 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18976 current_stub_contents =
18977 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18978 initial_insn);
18979
18980 /* B initial_insn_addr+4. */
18981 current_stub_contents =
18982 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18983 create_instruction_branch_absolute
82188b29 18984 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18985
18986 /* Fill the remaining of the stub with deterministic contents. */
18987 current_stub_contents =
18988 stm32l4xx_fill_stub_udf (htab, output_bfd,
18989 base_stub_contents, current_stub_contents,
18990 base_stub_contents +
18991 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18992
18993 return;
18994 }
18995
18996 /* - reg_list[13] == 0. */
18997 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18998
18999 /* - reg_list[14] & reg_list[15] != 1. */
19000 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19001
19002 /* - if (wback==1) reg_list[rn] == 0. */
19003 BFD_ASSERT (!wback || !restore_rn);
19004
19005 /* - nb_registers > 8. */
b25e998d 19006 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19007
19008 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19009
19010 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19011 - One with the 7 lowest registers (register mask 0x007F)
19012 This LDM will finally contain between 2 and 7 registers
19013 - One with the 7 highest registers (register mask 0xDF80)
19014 This ldm will finally contain between 2 and 7 registers. */
19015 insn_low_registers = insn_all_registers & 0x007F;
19016 insn_high_registers = insn_all_registers & 0xDF80;
19017
19018 /* A spare register may be needed during this veneer to temporarily
19019 handle the base register. This register will be restored with
19020 the last LDM operation.
19021 The usable register may be any general purpose register (that excludes
19022 PC, SP, LR : register mask is 0x1FFF). */
19023 usable_register_mask = 0x1FFF;
19024
19025 /* Generate the stub function. */
19026 if (!wback && !restore_pc && !restore_rn)
19027 {
19028 /* Choose a Ri in the low-register-list that will be restored. */
19029 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19030
19031 /* MOV Ri, Rn. */
19032 current_stub_contents =
19033 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19034 create_instruction_mov (ri, rn));
19035
19036 /* LDMDB Ri!, {R-high-register-list}. */
19037 current_stub_contents =
19038 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19039 create_instruction_ldmdb
19040 (ri, /*wback=*/1, insn_high_registers));
19041
19042 /* LDMDB Ri, {R-low-register-list}. */
19043 current_stub_contents =
19044 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19045 create_instruction_ldmdb
19046 (ri, /*wback=*/0, insn_low_registers));
19047
19048 /* B initial_insn_addr+4. */
19049 current_stub_contents =
19050 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19051 create_instruction_branch_absolute
82188b29 19052 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19053 }
19054 else if (wback && !restore_pc && !restore_rn)
19055 {
19056 /* LDMDB Rn!, {R-high-register-list}. */
19057 current_stub_contents =
19058 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19059 create_instruction_ldmdb
19060 (rn, /*wback=*/1, insn_high_registers));
19061
19062 /* LDMDB Rn!, {R-low-register-list}. */
19063 current_stub_contents =
19064 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19065 create_instruction_ldmdb
19066 (rn, /*wback=*/1, insn_low_registers));
19067
19068 /* B initial_insn_addr+4. */
19069 current_stub_contents =
19070 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19071 create_instruction_branch_absolute
82188b29 19072 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19073 }
19074 else if (!wback && restore_pc && !restore_rn)
19075 {
19076 /* Choose a Ri in the high-register-list that will be restored. */
19077 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19078
19079 /* SUB Ri, Rn, #(4*nb_registers). */
19080 current_stub_contents =
19081 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19082 create_instruction_sub (ri, rn, (4 * nb_registers)));
19083
19084 /* LDMIA Ri!, {R-low-register-list}. */
19085 current_stub_contents =
19086 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19087 create_instruction_ldmia
19088 (ri, /*wback=*/1, insn_low_registers));
19089
19090 /* LDMIA Ri, {R-high-register-list}. */
19091 current_stub_contents =
19092 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19093 create_instruction_ldmia
19094 (ri, /*wback=*/0, insn_high_registers));
19095 }
19096 else if (wback && restore_pc && !restore_rn)
19097 {
19098 /* Choose a Ri in the high-register-list that will be restored. */
19099 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19100
19101 /* SUB Rn, Rn, #(4*nb_registers) */
19102 current_stub_contents =
19103 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19104 create_instruction_sub (rn, rn, (4 * nb_registers)));
19105
19106 /* MOV Ri, Rn. */
19107 current_stub_contents =
19108 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19109 create_instruction_mov (ri, rn));
19110
19111 /* LDMIA Ri!, {R-low-register-list}. */
19112 current_stub_contents =
19113 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19114 create_instruction_ldmia
19115 (ri, /*wback=*/1, insn_low_registers));
19116
19117 /* LDMIA Ri, {R-high-register-list}. */
19118 current_stub_contents =
19119 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19120 create_instruction_ldmia
19121 (ri, /*wback=*/0, insn_high_registers));
19122 }
19123 else if (!wback && !restore_pc && restore_rn)
19124 {
19125 ri = rn;
19126 if (!(insn_low_registers & (1 << rn)))
19127 {
19128 /* Choose a Ri in the low-register-list that will be restored. */
19129 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19130
19131 /* MOV Ri, Rn. */
19132 current_stub_contents =
19133 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19134 create_instruction_mov (ri, rn));
19135 }
19136
19137 /* LDMDB Ri!, {R-high-register-list}. */
19138 current_stub_contents =
19139 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19140 create_instruction_ldmdb
19141 (ri, /*wback=*/1, insn_high_registers));
19142
19143 /* LDMDB Ri, {R-low-register-list}. */
19144 current_stub_contents =
19145 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19146 create_instruction_ldmdb
19147 (ri, /*wback=*/0, insn_low_registers));
19148
19149 /* B initial_insn_addr+4. */
19150 current_stub_contents =
19151 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19152 create_instruction_branch_absolute
82188b29 19153 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19154 }
19155 else if (!wback && restore_pc && restore_rn)
19156 {
19157 ri = rn;
19158 if (!(insn_high_registers & (1 << rn)))
19159 {
19160 /* Choose a Ri in the high-register-list that will be restored. */
19161 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19162 }
19163
19164 /* SUB Ri, Rn, #(4*nb_registers). */
19165 current_stub_contents =
19166 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19167 create_instruction_sub (ri, rn, (4 * nb_registers)));
19168
19169 /* LDMIA Ri!, {R-low-register-list}. */
19170 current_stub_contents =
19171 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19172 create_instruction_ldmia
19173 (ri, /*wback=*/1, insn_low_registers));
19174
19175 /* LDMIA Ri, {R-high-register-list}. */
19176 current_stub_contents =
19177 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19178 create_instruction_ldmia
19179 (ri, /*wback=*/0, insn_high_registers));
19180 }
19181 else if (wback && restore_rn)
19182 {
19183 /* The assembler should not have accepted to encode this. */
19184 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19185 "undefined behavior.\n");
19186 }
19187
19188 /* Fill the remaining of the stub with deterministic contents. */
19189 current_stub_contents =
19190 stm32l4xx_fill_stub_udf (htab, output_bfd,
19191 base_stub_contents, current_stub_contents,
19192 base_stub_contents +
19193 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19194
19195}
19196
19197static void
19198stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19199 bfd * output_bfd,
19200 const insn32 initial_insn,
19201 const bfd_byte *const initial_insn_addr,
19202 bfd_byte *const base_stub_contents)
19203{
13c9c485 19204 int num_words = initial_insn & 0xff;
a504d23a
LA		 19205 bfd_byte *current_stub_contents = base_stub_contents;
19206
19207 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19208
19209 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19210 smaller than 8 words load sequences that do not cause the
a504d23a 19211 hardware issue. */
9239bbd3 19212 if (num_words <= 8)
a504d23a
LA		 19213 {
19214 /* Untouched instruction. */
19215 current_stub_contents =
19216 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19217 initial_insn);
19218
19219 /* B initial_insn_addr+4. */
19220 current_stub_contents =
19221 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19222 create_instruction_branch_absolute
82188b29 19223 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19224 }
19225 else
19226 {
9eaff861 19227 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19228 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19229 bfd_boolean is_ia_nobang = /* (IA without !). */
19230 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19231 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19232 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19233 bfd_boolean is_db_bang = /* (DB with !). */
19234 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19235 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19236 /* d = UInt (Vd:D);. */
9239bbd3 19237 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19238 | (((unsigned int)initial_insn << 9) >> 31);
19239
9239bbd3
CM		 19240 /* Compute the number of 8-words chunks needed to split. */
19241 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19242 int chunk;
19243
19244 /* The test coverage has been done assuming the following
19245 hypothesis that exactly one of the previous is_ predicates is
19246 true. */
9239bbd3
CM		 19247 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19248 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19249
9239bbd3 19250 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19251 cases, then we emit the adjustments:
19252
19253 vldm rx, {...}
19254 -> vldm rx!, {8_words_or_less} for each needed 8_word
19255 -> sub rx, rx, #size (list)
19256
19257 vldm rx!, {...}
19258 -> vldm rx!, {8_words_or_less} for each needed 8_word
19259 This also handles vpop instruction (when rx is sp)
19260
19261 vldmd rx!, {...}
19262 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19263 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19264 {
9239bbd3
CM		 19265 bfd_vma new_insn = 0;
19266
a504d23a
LA		 19267 if (is_ia_nobang || is_ia_bang)
19268 {
9239bbd3
CM		 19269 new_insn = create_instruction_vldmia
19270 (base_reg,
19271 is_dp,
19272 /*wback= . */1,
19273 chunks - (chunk + 1) ?
19274 8 : num_words - chunk * 8,
19275 first_reg + chunk * 8);
a504d23a
LA		 19276 }
19277 else if (is_db_bang)
19278 {
9239bbd3
CM		 19279 new_insn = create_instruction_vldmdb
19280 (base_reg,
19281 is_dp,
19282 chunks - (chunk + 1) ?
19283 8 : num_words - chunk * 8,
19284 first_reg + chunk * 8);
a504d23a 19285 }
9239bbd3
CM		 19286
19287 if (new_insn)
19288 current_stub_contents =
19289 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19290 new_insn);
a504d23a
LA		 19291 }
19292
19293 /* Only this case requires the base register compensation
19294 subtract. */
19295 if (is_ia_nobang)
19296 {
19297 current_stub_contents =
19298 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19299 create_instruction_sub
9239bbd3 19300 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19301 }
19302
19303 /* B initial_insn_addr+4. */
19304 current_stub_contents =
19305 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19306 create_instruction_branch_absolute
82188b29 19307 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19308 }
19309
19310 /* Fill the remaining of the stub with deterministic contents. */
19311 current_stub_contents =
19312 stm32l4xx_fill_stub_udf (htab, output_bfd,
19313 base_stub_contents, current_stub_contents,
19314 base_stub_contents +
19315 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19316}
19317
19318static void
19319stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19320 bfd * output_bfd,
19321 const insn32 wrong_insn,
19322 const bfd_byte *const wrong_insn_addr,
19323 bfd_byte *const stub_contents)
19324{
19325 if (is_thumb2_ldmia (wrong_insn))
19326 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19327 wrong_insn, wrong_insn_addr,
19328 stub_contents);
19329 else if (is_thumb2_ldmdb (wrong_insn))
19330 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19331 wrong_insn, wrong_insn_addr,
19332 stub_contents);
19333 else if (is_thumb2_vldm (wrong_insn))
19334 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19335 wrong_insn, wrong_insn_addr,
19336 stub_contents);
19337}
19338
19339/* End of stm32l4xx work-around. */
19340
19341
e489d0ae
PB		 19342/* Do code byteswapping. Return FALSE afterwards so that the section is
19343 written out as normal. */
19344
19345static bfd_boolean
c7b8f16e 19346elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19347 struct bfd_link_info *link_info,
19348 asection *sec,
e489d0ae
PB		 19349 bfd_byte *contents)
19350{
48229727 19351 unsigned int mapcount, errcount;
8e3de13a 19352 _arm_elf_section_data *arm_data;
c7b8f16e 19353 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19354 elf32_arm_section_map *map;
c7b8f16e 19355 elf32_vfp11_erratum_list *errnode;
a504d23a 19356 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19357 bfd_vma ptr;
19358 bfd_vma end;
c7b8f16e 19359 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19360 bfd_byte tmp;
48229727 19361 unsigned int i;
57e8b36a 19362
4dfe6ac6
NC		 19363 if (globals == NULL)
19364 return FALSE;
19365
8e3de13a
NC		 19366 /* If this section has not been allocated an _arm_elf_section_data
19367 structure then we cannot record anything. */
19368 arm_data = get_arm_elf_section_data (sec);
19369 if (arm_data == NULL)
19370 return FALSE;
19371
19372 mapcount = arm_data->mapcount;
19373 map = arm_data->map;
c7b8f16e
JB		 19374 errcount = arm_data->erratumcount;
19375
19376 if (errcount != 0)
19377 {
19378 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19379
19380 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19381 errnode = errnode->next)
19382 {
19383 bfd_vma target = errnode->vma - offset;
19384
19385 switch (errnode->type)
19386 {
19387 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19388 {
19389 bfd_vma branch_to_veneer;
19390 /* Original condition code of instruction, plus bit mask for
19391 ARM B instruction. */
19392 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19393 | 0x0a000000;
c7b8f16e
JB		 19394
19395 /* The instruction is before the label. */
91d6fa6a 19396 target -= 4;
c7b8f16e
JB		 19397
19398 /* Above offset included in -4 below. */
19399 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19400 - errnode->vma - 4;
c7b8f16e
JB		 19401
19402 if ((signed) branch_to_veneer < -(1 << 25)
19403 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19404 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19405 "range"), output_bfd);
c7b8f16e 19406
99059e56
RM		 19407 insn |= (branch_to_veneer >> 2) & 0xffffff;
19408 contents[endianflip ^ target] = insn & 0xff;
19409 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19410 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19411 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19412 }
19413 break;
c7b8f16e
JB		 19414
19415 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19416 {
19417 bfd_vma branch_from_veneer;
19418 unsigned int insn;
c7b8f16e 19419
99059e56
RM		 19420 /* Take size of veneer into account. */
19421 branch_from_veneer = errnode->u.v.branch->vma
19422 - errnode->vma - 12;
c7b8f16e
JB		 19423
19424 if ((signed) branch_from_veneer < -(1 << 25)
19425 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19426 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19427 "range"), output_bfd);
c7b8f16e 19428
99059e56
RM		 19429 /* Original instruction. */
19430 insn = errnode->u.v.branch->u.b.vfp_insn;
19431 contents[endianflip ^ target] = insn & 0xff;
19432 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19433 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19434 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19435
19436 /* Branch back to insn after original insn. */
19437 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19438 contents[endianflip ^ (target + 4)] = insn & 0xff;
19439 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19440 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19441 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19442 }
19443 break;
c7b8f16e 19444
99059e56
RM		 19445 default:
19446 abort ();
19447 }
19448 }
c7b8f16e 19449 }
e489d0ae 19450
a504d23a
LA		 19451 if (arm_data->stm32l4xx_erratumcount != 0)
19452 {
19453 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19454 stm32l4xx_errnode != 0;
19455 stm32l4xx_errnode = stm32l4xx_errnode->next)
19456 {
19457 bfd_vma target = stm32l4xx_errnode->vma - offset;
19458
19459 switch (stm32l4xx_errnode->type)
19460 {
19461 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19462 {
19463 unsigned int insn;
19464 bfd_vma branch_to_veneer =
19465 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19466
19467 if ((signed) branch_to_veneer < -(1 << 24)
19468 || (signed) branch_to_veneer >= (1 << 24))
19469 {
19470 bfd_vma out_of_range =
19471 ((signed) branch_to_veneer < -(1 << 24)) ?
19472 - branch_to_veneer - (1 << 24) :
19473 ((signed) branch_to_veneer >= (1 << 24)) ?
19474 branch_to_veneer - (1 << 24) : 0;
19475
4eca0228 19476 _bfd_error_handler
2dcf00ce 19477 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19478 "cannot create STM32L4XX veneer; "
19479 "jump out of range by %" PRId64 " bytes; "
19480 "cannot encode branch instruction"),
a504d23a 19481 output_bfd,
2dcf00ce
AM		 19482 (uint64_t) (stm32l4xx_errnode->vma - 4),
19483 (int64_t) out_of_range);
a504d23a
LA		 19484 continue;
19485 }
19486
19487 insn = create_instruction_branch_absolute
82188b29 19488 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19489
a2699ef2
AM		 19490 /* The instruction is before the label. */
19491 target -= 4;
19492
a504d23a
LA		 19493 put_thumb2_insn (globals, output_bfd,
19494 (bfd_vma) insn, contents + target);
19495 }
19496 break;
19497
19498 case STM32L4XX_ERRATUM_VENEER:
19499 {
82188b29
NC		 19500 bfd_byte * veneer;
19501 bfd_byte * veneer_r;
a504d23a
LA		 19502 unsigned int insn;
19503
82188b29
NC		 19504 veneer = contents + target;
19505 veneer_r = veneer
19506 + stm32l4xx_errnode->u.b.veneer->vma
19507 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19508
19509 if ((signed) (veneer_r - veneer -
19510 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19511 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19512 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19513 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19514 || (signed) (veneer_r - veneer) >= (1 << 24))
19515 {
90b6238f
AM		 19516 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19517 "veneer"), output_bfd);
a504d23a
LA		 19518 continue;
19519 }
19520
19521 /* Original instruction. */
19522 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19523
19524 stm32l4xx_create_replacing_stub
19525 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19526 }
19527 break;
19528
19529 default:
19530 abort ();
19531 }
19532 }
19533 }
19534
2468f9c9
PB		 19535 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19536 {
19537 arm_unwind_table_edit *edit_node
99059e56 19538 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19539 /* Now, sec->size is the size of the section we will write. The original
99059e56 19540 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19541 markers) was sec->rawsize. (This isn't the case if we perform no
19542 edits, then rawsize will be zero and we should use size). */
21d799b5 19543 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19544 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19545 unsigned int in_index, out_index;
19546 bfd_vma add_to_offsets = 0;
19547
7a0fb7be
NC		 19548 if (edited_contents == NULL)
19549 return FALSE;
2468f9c9 19550 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19551 {
2468f9c9
PB		 19552 if (edit_node)
19553 {
19554 unsigned int edit_index = edit_node->index;
b38cadfb 19555
2468f9c9 19556 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19557 {
2468f9c9
PB		 19558 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19559 contents + in_index * 8, add_to_offsets);
19560 out_index++;
19561 in_index++;
19562 }
19563 else if (in_index == edit_index
19564 || (in_index * 8 >= input_size
19565 && edit_index == UINT_MAX))
99059e56 19566 {
2468f9c9
PB		 19567 switch (edit_node->type)
19568 {
19569 case DELETE_EXIDX_ENTRY:
19570 in_index++;
19571 add_to_offsets += 8;
19572 break;
b38cadfb 19573
2468f9c9
PB		 19574 case INSERT_EXIDX_CANTUNWIND_AT_END:
19575 {
99059e56 19576 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19577 bfd_vma text_offset = text_sec->output_section->vma
19578 + text_sec->output_offset
19579 + text_sec->size;
19580 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19581 unsigned long prel31_offset;
2468f9c9
PB		 19582
19583 /* Note: this is meant to be equivalent to an
19584 R_ARM_PREL31 relocation. These synthetic
19585 EXIDX_CANTUNWIND markers are not relocated by the
19586 usual BFD method. */
19587 prel31_offset = (text_offset - exidx_offset)
19588 & 0x7ffffffful;
491d01d3
YU		 19589 if (bfd_link_relocatable (link_info))
19590 {
19591 /* Here relocation for new EXIDX_CANTUNWIND is
19592 created, so there is no need to
19593 adjust offset by hand. */
19594 prel31_offset = text_sec->output_offset
19595 + text_sec->size;
491d01d3 19596 }
2468f9c9
PB		 19597
19598 /* First address we can't unwind. */
19599 bfd_put_32 (output_bfd, prel31_offset,
19600 &edited_contents[out_index * 8]);
19601
19602 /* Code for EXIDX_CANTUNWIND. */
19603 bfd_put_32 (output_bfd, 0x1,
19604 &edited_contents[out_index * 8 + 4]);
19605
19606 out_index++;
19607 add_to_offsets -= 8;
19608 }
19609 break;
19610 }
b38cadfb 19611
2468f9c9
PB		 19612 edit_node = edit_node->next;
19613 }
19614 }
19615 else
19616 {
19617 /* No more edits, copy remaining entries verbatim. */
19618 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19619 contents + in_index * 8, add_to_offsets);
19620 out_index++;
19621 in_index++;
19622 }
19623 }
19624
19625 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19626 bfd_set_section_contents (output_bfd, sec->output_section,
19627 edited_contents,
19628 (file_ptr) sec->output_offset, sec->size);
19629
19630 return TRUE;
19631 }
19632
48229727
JB		 19633 /* Fix code to point to Cortex-A8 erratum stubs. */
19634 if (globals->fix_cortex_a8)
19635 {
19636 struct a8_branch_to_stub_data data;
19637
19638 data.writing_section = sec;
19639 data.contents = contents;
19640
a504d23a
LA		 19641 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19642 & data);
48229727
JB		 19643 }
19644
e489d0ae
PB		 19645 if (mapcount == 0)
19646 return FALSE;
19647
c7b8f16e 19648 if (globals->byteswap_code)
e489d0ae 19649 {
c7b8f16e 19650 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19651
c7b8f16e
JB		 19652 ptr = map[0].vma;
19653 for (i = 0; i < mapcount; i++)
99059e56
RM		 19654 {
19655 if (i == mapcount - 1)
c7b8f16e 19656 end = sec->size;
99059e56
RM		 19657 else
19658 end = map[i + 1].vma;
e489d0ae 19659
99059e56 19660 switch (map[i].type)
e489d0ae 19661 {
c7b8f16e
JB		 19662 case 'a':
19663 /* Byte swap code words. */
19664 while (ptr + 3 < end)
99059e56
RM		 19665 {
19666 tmp = contents[ptr];
19667 contents[ptr] = contents[ptr + 3];
19668 contents[ptr + 3] = tmp;
19669 tmp = contents[ptr + 1];
19670 contents[ptr + 1] = contents[ptr + 2];
19671 contents[ptr + 2] = tmp;
19672 ptr += 4;
19673 }
c7b8f16e 19674 break;
e489d0ae 19675
c7b8f16e
JB		 19676 case 't':
19677 /* Byte swap code halfwords. */
19678 while (ptr + 1 < end)
99059e56
RM		 19679 {
19680 tmp = contents[ptr];
19681 contents[ptr] = contents[ptr + 1];
19682 contents[ptr + 1] = tmp;
19683 ptr += 2;
19684 }
c7b8f16e
JB		 19685 break;
19686
19687 case 'd':
19688 /* Leave data alone. */
19689 break;
19690 }
99059e56
RM		 19691 ptr = end;
19692 }
e489d0ae 19693 }
8e3de13a 19694
93204d3a 19695 free (map);
47b2e99c 19696 arm_data->mapcount = -1;
c7b8f16e 19697 arm_data->mapsize = 0;
8e3de13a 19698 arm_data->map = NULL;
8e3de13a 19699
e489d0ae
PB		 19700 return FALSE;
19701}
19702
0beaef2b
PB		 19703/* Mangle thumb function symbols as we read them in. */
19704
8384fb8f 19705static bfd_boolean
0beaef2b
PB		 19706elf32_arm_swap_symbol_in (bfd * abfd,
19707 const void *psrc,
19708 const void *pshn,
19709 Elf_Internal_Sym *dst)
19710{
8384fb8f
AM		 19711 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19712 return FALSE;
39d911fc 19713 dst->st_target_internal = 0;
0beaef2b
PB		 19714
19715 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19716 the address. */
63e1a0fc
PB		 19717 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19718 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19719 {
63e1a0fc
PB		 19720 if (dst->st_value & 1)
19721 {
19722 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19723 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19724 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19725 }
19726 else
39d911fc 19727 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19728 }
19729 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19730 {
19731 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19732 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19733 }
35fc36a8 19734 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19735 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19736 else
39d911fc 19737 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19738
8384fb8f 19739 return TRUE;
0beaef2b
PB		 19740}
19741
19742
19743/* Mangle thumb function symbols as we write them out. */
19744
19745static void
19746elf32_arm_swap_symbol_out (bfd *abfd,
19747 const Elf_Internal_Sym *src,
19748 void *cdst,
19749 void *shndx)
19750{
19751 Elf_Internal_Sym newsym;
19752
19753 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19754 of the address set, as per the new EABI. We do this unconditionally
19755 because objcopy does not set the elf header flags until after
19756 it writes out the symbol table. */
39d911fc 19757 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19758 {
19759 newsym = *src;
34e77a92
RS		 19760 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19761 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19762 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19763 {
19764 /* Do this only for defined symbols. At link type, the static
19765 linker will simulate the work of dynamic linker of resolving
19766 symbols and will carry over the thumbness of found symbols to
19767 the output symbol table. It's not clear how it happens, but
19768 the thumbness of undefined symbols can well be different at
19769 runtime, and writing '1' for them will be confusing for users
19770 and possibly for dynamic linker itself.
19771 */
19772 newsym.st_value |= 1;
19773 }
906e58ca 19774
0beaef2b
PB		 19775 src = &newsym;
19776 }
19777 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19778}
19779
b294bdf8
MM		 19780/* Add the PT_ARM_EXIDX program header. */
19781
19782static bfd_boolean
906e58ca 19783elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19784 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19785{
19786 struct elf_segment_map *m;
19787 asection *sec;
19788
19789 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19790 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19791 {
19792 /* If there is already a PT_ARM_EXIDX header, then we do not
19793 want to add another one. This situation arises when running
19794 "strip"; the input binary already has the header. */
12bd6957 19795 m = elf_seg_map (abfd);
b294bdf8
MM		 19796 while (m && m->p_type != PT_ARM_EXIDX)
19797 m = m->next;
19798 if (!m)
19799 {
21d799b5 19800 m = (struct elf_segment_map *)
99059e56 19801 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19802 if (m == NULL)
19803 return FALSE;
19804 m->p_type = PT_ARM_EXIDX;
19805 m->count = 1;
19806 m->sections[0] = sec;
19807
12bd6957
AM		 19808 m->next = elf_seg_map (abfd);
19809 elf_seg_map (abfd) = m;
b294bdf8
MM		 19810 }
19811 }
19812
19813 return TRUE;
19814}
19815
19816/* We may add a PT_ARM_EXIDX program header. */
19817
19818static int
a6b96beb
AM		 19819elf32_arm_additional_program_headers (bfd *abfd,
19820 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19821{
19822 asection *sec;
19823
19824 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19825 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19826 return 1;
19827 else
19828 return 0;
19829}
19830
34e77a92
RS		 19831/* Hook called by the linker routine which adds symbols from an object
19832 file. */
19833
19834static bfd_boolean
19835elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19836 Elf_Internal_Sym *sym, const char **namep,
19837 flagword *flagsp, asection **secp, bfd_vma *valp)
19838{
c792917c
NC		 19839 if (elf32_arm_hash_table (info) == NULL)
19840 return FALSE;
19841
90c14f0c 19842 if (elf32_arm_hash_table (info)->root.target_os == is_vxworks
34e77a92
RS		 19843 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
19844 flagsp, secp, valp))
19845 return FALSE;
19846
19847 return TRUE;
19848}
19849
0beaef2b 19850/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 19851const struct elf_size_info elf32_arm_size_info =
19852{
0beaef2b
PB		 19853 sizeof (Elf32_External_Ehdr),
19854 sizeof (Elf32_External_Phdr),
19855 sizeof (Elf32_External_Shdr),
19856 sizeof (Elf32_External_Rel),
19857 sizeof (Elf32_External_Rela),
19858 sizeof (Elf32_External_Sym),
19859 sizeof (Elf32_External_Dyn),
19860 sizeof (Elf_External_Note),
19861 4,
19862 1,
19863 32, 2,
19864 ELFCLASS32, EV_CURRENT,
19865 bfd_elf32_write_out_phdrs,
19866 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 19867 bfd_elf32_checksum_contents,
0beaef2b
PB		 19868 bfd_elf32_write_relocs,
19869 elf32_arm_swap_symbol_in,
19870 elf32_arm_swap_symbol_out,
19871 bfd_elf32_slurp_reloc_table,
19872 bfd_elf32_slurp_symbol_table,
19873 bfd_elf32_swap_dyn_in,
19874 bfd_elf32_swap_dyn_out,
19875 bfd_elf32_swap_reloc_in,
19876 bfd_elf32_swap_reloc_out,
19877 bfd_elf32_swap_reloca_in,
19878 bfd_elf32_swap_reloca_out
19879};
19880
685e70ae
VK		 19881static bfd_vma
19882read_code32 (const bfd *abfd, const bfd_byte *addr)
19883{
19884 /* V7 BE8 code is always little endian. */
19885 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19886 return bfd_getl32 (addr);
19887
19888 return bfd_get_32 (abfd, addr);
19889}
19890
19891static bfd_vma
19892read_code16 (const bfd *abfd, const bfd_byte *addr)
19893{
19894 /* V7 BE8 code is always little endian. */
19895 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19896 return bfd_getl16 (addr);
19897
19898 return bfd_get_16 (abfd, addr);
19899}
19900
6a631e86
YG		 19901/* Return size of plt0 entry starting at ADDR
19902 or (bfd_vma) -1 if size can not be determined. */
19903
19904static bfd_vma
19905elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19906{
19907 bfd_vma first_word;
19908 bfd_vma plt0_size;
19909
685e70ae 19910 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19911
19912 if (first_word == elf32_arm_plt0_entry[0])
19913 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19914 else if (first_word == elf32_thumb2_plt0_entry[0])
19915 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19916 else
19917 /* We don't yet handle this PLT format. */
19918 return (bfd_vma) -1;
19919
19920 return plt0_size;
19921}
19922
19923/* Return size of plt entry starting at offset OFFSET
19924 of plt section located at address START
19925 or (bfd_vma) -1 if size can not be determined. */
19926
19927static bfd_vma
19928elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19929{
19930 bfd_vma first_insn;
19931 bfd_vma plt_size = 0;
19932 const bfd_byte *addr = start + offset;
19933
19934 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19935 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19936 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19937
19938 /* Respect Thumb stub if necessary. */
685e70ae 19939 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19940 {
19941 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19942 }
19943
19944 /* Strip immediate from first add. */
685e70ae 19945 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19946
19947#ifdef FOUR_WORD_PLT
19948 if (first_insn == elf32_arm_plt_entry[0])
19949 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19950#else
19951 if (first_insn == elf32_arm_plt_entry_long[0])
19952 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19953 else if (first_insn == elf32_arm_plt_entry_short[0])
19954 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19955#endif
19956 else
19957 /* We don't yet handle this PLT format. */
19958 return (bfd_vma) -1;
19959
19960 return plt_size;
19961}
19962
19963/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19964
19965static long
19966elf32_arm_get_synthetic_symtab (bfd *abfd,
19967 long symcount ATTRIBUTE_UNUSED,
19968 asymbol **syms ATTRIBUTE_UNUSED,
19969 long dynsymcount,
19970 asymbol **dynsyms,
19971 asymbol **ret)
19972{
19973 asection *relplt;
19974 asymbol *s;
19975 arelent *p;
19976 long count, i, n;
19977 size_t size;
19978 Elf_Internal_Shdr *hdr;
19979 char *names;
19980 asection *plt;
19981 bfd_vma offset;
19982 bfd_byte *data;
19983
19984 *ret = NULL;
19985
19986 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19987 return 0;
19988
19989 if (dynsymcount <= 0)
19990 return 0;
19991
19992 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19993 if (relplt == NULL)
19994 return 0;
19995
19996 hdr = &elf_section_data (relplt)->this_hdr;
19997 if (hdr->sh_link != elf_dynsymtab (abfd)
19998 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19999 return 0;
20000
20001 plt = bfd_get_section_by_name (abfd, ".plt");
20002 if (plt == NULL)
20003 return 0;
20004
20005 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20006 return -1;
20007
20008 data = plt->contents;
20009 if (data == NULL)
20010 {
20011 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20012 return -1;
20013 bfd_cache_section_contents((asection *) plt, data);
20014 }
20015
20016 count = relplt->size / hdr->sh_entsize;
20017 size = count * sizeof (asymbol);
20018 p = relplt->relocation;
20019 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20020 {
20021 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20022 if (p->addend != 0)
20023 size += sizeof ("+0x") - 1 + 8;
20024 }
20025
20026 s = *ret = (asymbol *) bfd_malloc (size);
20027 if (s == NULL)
20028 return -1;
20029
20030 offset = elf32_arm_plt0_size (abfd, data);
20031 if (offset == (bfd_vma) -1)
20032 return -1;
20033
20034 names = (char *) (s + count);
20035 p = relplt->relocation;
20036 n = 0;
20037 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20038 {
20039 size_t len;
20040
20041 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20042 if (plt_size == (bfd_vma) -1)
20043 break;
20044
20045 *s = **p->sym_ptr_ptr;
20046 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20047 we are defining a symbol, ensure one of them is set. */
20048 if ((s->flags & BSF_LOCAL) == 0)
20049 s->flags |= BSF_GLOBAL;
20050 s->flags |= BSF_SYNTHETIC;
20051 s->section = plt;
20052 s->value = offset;
20053 s->name = names;
20054 s->udata.p = NULL;
20055 len = strlen ((*p->sym_ptr_ptr)->name);
20056 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20057 names += len;
20058 if (p->addend != 0)
20059 {
20060 char buf[30], *a;
20061
20062 memcpy (names, "+0x", sizeof ("+0x") - 1);
20063 names += sizeof ("+0x") - 1;
20064 bfd_sprintf_vma (abfd, buf, p->addend);
20065 for (a = buf; *a == '0'; ++a)
20066 ;
20067 len = strlen (a);
20068 memcpy (names, a, len);
20069 names += len;
20070 }
20071 memcpy (names, "@plt", sizeof ("@plt"));
20072 names += sizeof ("@plt");
20073 ++s, ++n;
20074 offset += plt_size;
20075 }
20076
20077 return n;
20078}
20079
ac4c9b04 20080static bfd_boolean
8c803a2d 20081elf32_arm_section_flags (const Elf_Internal_Shdr *hdr)
ac4c9b04 20082{
f0728ee3 20083 if (hdr->sh_flags & SHF_ARM_PURECODE)
8c803a2d 20084 hdr->bfd_section->flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20085 return TRUE;
20086}
20087
20088static flagword
20089elf32_arm_lookup_section_flags (char *flag_name)
20090{
f0728ee3
AV		 20091 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20092 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20093
20094 return SEC_NO_FLAGS;
20095}
20096
491d01d3
YU		 20097static unsigned int
20098elf32_arm_count_additional_relocs (asection *sec)
20099{
20100 struct _arm_elf_section_data *arm_data;
20101 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20102
6342be70 20103 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20104}
20105
5522f910 20106/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20107 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20108 FALSE otherwise. ISECTION is the best guess matching section from the
20109 input bfd IBFD, but it might be NULL. */
20110
20111static bfd_boolean
20112elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20113 bfd *obfd ATTRIBUTE_UNUSED,
20114 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20115 Elf_Internal_Shdr *osection)
20116{
20117 switch (osection->sh_type)
20118 {
20119 case SHT_ARM_EXIDX:
20120 {
20121 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20122 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20123 unsigned i = 0;
20124
20125 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20126 osection->sh_info = 0;
20127
20128 /* The sh_link field must be set to the text section associated with
20129 this index section. Unfortunately the ARM EHABI does not specify
20130 exactly how to determine this association. Our caller does try
20131 to match up OSECTION with its corresponding input section however
20132 so that is a good first guess. */
20133 if (isection != NULL
20134 && osection->bfd_section != NULL
20135 && isection->bfd_section != NULL
20136 && isection->bfd_section->output_section != NULL
20137 && isection->bfd_section->output_section == osection->bfd_section
20138 && iheaders != NULL
20139 && isection->sh_link > 0
20140 && isection->sh_link < elf_numsections (ibfd)
20141 && iheaders[isection->sh_link]->bfd_section != NULL
20142 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20143 )
20144 {
20145 for (i = elf_numsections (obfd); i-- > 0;)
20146 if (oheaders[i]->bfd_section
20147 == iheaders[isection->sh_link]->bfd_section->output_section)
20148 break;
20149 }
9eaff861 20150
5522f910
NC		 20151 if (i == 0)
20152 {
20153 /* Failing that we have to find a matching section ourselves. If
20154 we had the output section name available we could compare that
20155 with input section names. Unfortunately we don't. So instead
20156 we use a simple heuristic and look for the nearest executable
20157 section before this one. */
20158 for (i = elf_numsections (obfd); i-- > 0;)
20159 if (oheaders[i] == osection)
20160 break;
20161 if (i == 0)
20162 break;
20163
20164 while (i-- > 0)
20165 if (oheaders[i]->sh_type == SHT_PROGBITS
20166 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20167 == (SHF_ALLOC | SHF_EXECINSTR))
20168 break;
20169 }
20170
20171 if (i)
20172 {
20173 osection->sh_link = i;
20174 /* If the text section was part of a group
20175 then the index section should be too. */
20176 if (oheaders[i]->sh_flags & SHF_GROUP)
20177 osection->sh_flags |= SHF_GROUP;
20178 return TRUE;
20179 }
20180 }
20181 break;
20182
20183 case SHT_ARM_PREEMPTMAP:
20184 osection->sh_flags = SHF_ALLOC;
20185 break;
20186
20187 case SHT_ARM_ATTRIBUTES:
20188 case SHT_ARM_DEBUGOVERLAY:
20189 case SHT_ARM_OVERLAYSECTION:
20190 default:
20191 break;
20192 }
20193
20194 return FALSE;
20195}
20196
d691934d
NC		 20197/* Returns TRUE if NAME is an ARM mapping symbol.
20198 Traditionally the symbols $a, $d and $t have been used.
20199 The ARM ELF standard also defines $x (for A64 code). It also allows a
20200 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20201 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20202 not support them here. $t.x indicates the start of ThumbEE instructions. */
20203
20204static bfd_boolean
20205is_arm_mapping_symbol (const char * name)
20206{
20207 return name != NULL /* Paranoia. */
20208 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20209 the mapping symbols could have acquired a prefix.
20210 We do not support this here, since such symbols no
20211 longer conform to the ARM ELF ABI. */
20212 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20213 && (name[2] == 0 || name[2] == '.');
20214 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20215 any characters that follow the period are legal characters for the body
20216 of a symbol's name. For now we just assume that this is the case. */
20217}
20218
fca2a38f
NC		 20219/* Make sure that mapping symbols in object files are not removed via the
20220 "strip --strip-unneeded" tool. These symbols are needed in order to
20221 correctly generate interworking veneers, and for byte swapping code
20222 regions. Once an object file has been linked, it is safe to remove the
20223 symbols as they will no longer be needed. */
20224
20225static void
20226elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20227{
20228 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20229 && sym->section != bfd_abs_section_ptr
d691934d 20230 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20231 sym->flags |= BSF_KEEP;
20232}
20233
5522f910
NC		 20234#undef elf_backend_copy_special_section_fields
20235#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20236
252b5132 20237#define ELF_ARCH bfd_arch_arm
ae95ffa6 20238#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20239#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20240#ifdef __QNXTARGET__
20241#define ELF_MAXPAGESIZE 0x1000
20242#else
7572ca89 20243#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20244#endif
b1342370 20245#define ELF_MINPAGESIZE 0x1000
24718e3b 20246#define ELF_COMMONPAGESIZE 0x1000
252b5132 20247
07d6d2b8 20248#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20249
99e4ae17
AJ		 20250#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20251#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20252#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20253#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20254#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20255#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20256#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8 20257#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20258#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20259#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20260#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20261#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20262
07d6d2b8 20263#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
e7679060 20264#define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
07d6d2b8 20265#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20266#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20267#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20268#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20269#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20270#define elf_backend_write_section elf32_arm_write_section
252b5132 20271#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20272#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20273#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20274#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20275#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20276#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20277#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ed7e9d0b 20278#define elf_backend_init_file_header elf32_arm_init_file_header
99e4ae17 20279#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20280#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20281#define elf_backend_fake_sections elf32_arm_fake_sections
20282#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20283#define elf_backend_final_write_processing elf32_arm_final_write_processing
20284#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20285#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20286#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20287#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20288#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20289#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20290#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20291#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20292#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20293#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20294
20295#define elf_backend_can_refcount 1
20296#define elf_backend_can_gc_sections 1
20297#define elf_backend_plt_readonly 1
20298#define elf_backend_want_got_plt 1
20299#define elf_backend_want_plt_sym 0
5474d94f 20300#define elf_backend_want_dynrelro 1
906e58ca
NC		 20301#define elf_backend_may_use_rel_p 1
20302#define elf_backend_may_use_rela_p 0
4e7fd91e 20303#define elf_backend_default_use_rela_p 0
64f52338 20304#define elf_backend_dtrel_excludes_plt 1
252b5132 20305
04f7c78d 20306#define elf_backend_got_header_size 12
b68a20d6 20307#define elf_backend_extern_protected_data 1
04f7c78d 20308
07d6d2b8 20309#undef elf_backend_obj_attrs_vendor
906e58ca 20310#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20311#undef elf_backend_obj_attrs_section
906e58ca 20312#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20313#undef elf_backend_obj_attrs_arg_type
906e58ca 20314#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20315#undef elf_backend_obj_attrs_section_type
104d59d1 20316#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20317#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20318#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20319
07d6d2b8 20320#undef elf_backend_section_flags
ac4c9b04 20321#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20322#undef elf_backend_lookup_section_flags_hook
20323#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20324
a2f63b2e
MR		 20325#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20326
252b5132 20327#include "elf32-target.h"
7f266840 20328
b38cadfb
NC		 20329/* Native Client targets. */
20330
20331#undef TARGET_LITTLE_SYM
6d00b590 20332#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20333#undef TARGET_LITTLE_NAME
20334#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20335#undef TARGET_BIG_SYM
6d00b590 20336#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20337#undef TARGET_BIG_NAME
20338#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20339
20340/* Like elf32_arm_link_hash_table_create -- but overrides
20341 appropriately for NaCl. */
20342
20343static struct bfd_link_hash_table *
20344elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20345{
20346 struct bfd_link_hash_table *ret;
20347
20348 ret = elf32_arm_link_hash_table_create (abfd);
20349 if (ret)
20350 {
20351 struct elf32_arm_link_hash_table *htab
20352 = (struct elf32_arm_link_hash_table *) ret;
20353
b38cadfb
NC		 20354 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20355 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20356 }
20357 return ret;
20358}
20359
20360/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20361 really need to use elf32_arm_modify_segment_map. But we do it
20362 anyway just to reduce gratuitous differences with the stock ARM backend. */
20363
20364static bfd_boolean
20365elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20366{
20367 return (elf32_arm_modify_segment_map (abfd, info)
20368 && nacl_modify_segment_map (abfd, info));
20369}
20370
cc364be6
AM		 20371static bfd_boolean
20372elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20373{
cc364be6
AM		 20374 arm_final_write_processing (abfd);
20375 return nacl_final_write_processing (abfd);
887badb3
RM		 20376}
20377
6a631e86
YG		 20378static bfd_vma
20379elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20380 const arelent *rel ATTRIBUTE_UNUSED)
20381{
20382 return plt->vma
20383 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20384 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20385}
887badb3 20386
b38cadfb 20387#undef elf32_bed
6a631e86 20388#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20389#undef bfd_elf32_bfd_link_hash_table_create
20390#define bfd_elf32_bfd_link_hash_table_create \
20391 elf32_arm_nacl_link_hash_table_create
20392#undef elf_backend_plt_alignment
6a631e86 20393#define elf_backend_plt_alignment 4
b38cadfb
NC		 20394#undef elf_backend_modify_segment_map
20395#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
6d6c25c8
AM		 20396#undef elf_backend_modify_headers
20397#define elf_backend_modify_headers nacl_modify_headers
887badb3
RM		 20398#undef elf_backend_final_write_processing
20399#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20400#undef bfd_elf32_get_synthetic_symtab
20401#undef elf_backend_plt_sym_val
20402#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20403#undef elf_backend_copy_special_section_fields
b38cadfb 20404
887badb3
RM		 20405#undef ELF_MINPAGESIZE
20406#undef ELF_COMMONPAGESIZE
20407
90c14f0c
L		 20408#undef ELF_TARGET_OS
20409#define ELF_TARGET_OS is_nacl
b38cadfb
NC		 20410
20411#include "elf32-target.h"
20412
20413/* Reset to defaults. */
20414#undef elf_backend_plt_alignment
20415#undef elf_backend_modify_segment_map
20416#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
6d6c25c8 20417#undef elf_backend_modify_headers
887badb3
RM		 20418#undef elf_backend_final_write_processing
20419#define elf_backend_final_write_processing elf32_arm_final_write_processing
20420#undef ELF_MINPAGESIZE
20421#define ELF_MINPAGESIZE 0x1000
20422#undef ELF_COMMONPAGESIZE
20423#define ELF_COMMONPAGESIZE 0x1000
20424
b38cadfb 20425
617a5ada
CL		 20426/* FDPIC Targets. */
20427
20428#undef TARGET_LITTLE_SYM
20429#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20430#undef TARGET_LITTLE_NAME
20431#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20432#undef TARGET_BIG_SYM
20433#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20434#undef TARGET_BIG_NAME
20435#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20436#undef elf_match_priority
20437#define elf_match_priority 128
18a20338
CL		 20438#undef ELF_OSABI
20439#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20440
20441/* Like elf32_arm_link_hash_table_create -- but overrides
20442 appropriately for FDPIC. */
20443
20444static struct bfd_link_hash_table *
20445elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20446{
20447 struct bfd_link_hash_table *ret;
20448
20449 ret = elf32_arm_link_hash_table_create (abfd);
20450 if (ret)
20451 {
20452 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20453
20454 htab->fdpic_p = 1;
20455 }
20456 return ret;
20457}
20458
e8b09b87
CL		 20459/* We need dynamic symbols for every section, since segments can
20460 relocate independently. */
20461static bfd_boolean
20462elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20463 struct bfd_link_info *info
20464 ATTRIBUTE_UNUSED,
20465 asection *p ATTRIBUTE_UNUSED)
20466{
20467 switch (elf_section_data (p)->this_hdr.sh_type)
20468 {
20469 case SHT_PROGBITS:
20470 case SHT_NOBITS:
20471 /* If sh_type is yet undecided, assume it could be
20472 SHT_PROGBITS/SHT_NOBITS. */
20473 case SHT_NULL:
20474 return FALSE;
20475
20476 /* There shouldn't be section relative relocations
20477 against any other section. */
20478 default:
20479 return TRUE;
20480 }
20481}
20482
617a5ada
CL		 20483#undef elf32_bed
20484#define elf32_bed elf32_arm_fdpic_bed
20485
20486#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20487#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20488
e8b09b87
CL		 20489#undef elf_backend_omit_section_dynsym
20490#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20491
90c14f0c
L		 20492#undef ELF_TARGET_OS
20493
617a5ada 20494#include "elf32-target.h"
e8b09b87 20495
617a5ada 20496#undef elf_match_priority
18a20338 20497#undef ELF_OSABI
e8b09b87 20498#undef elf_backend_omit_section_dynsym
617a5ada 20499
906e58ca 20500/* VxWorks Targets. */
4e7fd91e 20501
07d6d2b8
AM		 20502#undef TARGET_LITTLE_SYM
20503#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20504#undef TARGET_LITTLE_NAME
20505#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20506#undef TARGET_BIG_SYM
20507#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20508#undef TARGET_BIG_NAME
20509#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20510
20511/* Like elf32_arm_link_hash_table_create -- but overrides
20512 appropriately for VxWorks. */
906e58ca 20513
4e7fd91e
PB		 20514static struct bfd_link_hash_table *
20515elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20516{
20517 struct bfd_link_hash_table *ret;
20518
20519 ret = elf32_arm_link_hash_table_create (abfd);
20520 if (ret)
20521 {
20522 struct elf32_arm_link_hash_table *htab
00a97672 20523 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e
PB		 20524 htab->use_rel = 0;
20525 }
20526 return ret;
906e58ca 20527}
4e7fd91e 20528
cc364be6
AM		 20529static bfd_boolean
20530elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20531{
cc364be6
AM		 20532 arm_final_write_processing (abfd);
20533 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20534}
20535
906e58ca 20536#undef elf32_bed
4e7fd91e
PB		 20537#define elf32_bed elf32_arm_vxworks_bed
20538
906e58ca
NC		 20539#undef bfd_elf32_bfd_link_hash_table_create
20540#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20541#undef elf_backend_final_write_processing
20542#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20543#undef elf_backend_emit_relocs
9eaff861 20544#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20545
906e58ca 20546#undef elf_backend_may_use_rel_p
00a97672 20547#define elf_backend_may_use_rel_p 0
906e58ca 20548#undef elf_backend_may_use_rela_p
00a97672 20549#define elf_backend_may_use_rela_p 1
906e58ca 20550#undef elf_backend_default_use_rela_p
00a97672 20551#define elf_backend_default_use_rela_p 1
906e58ca 20552#undef elf_backend_want_plt_sym
00a97672 20553#define elf_backend_want_plt_sym 1
906e58ca 20554#undef ELF_MAXPAGESIZE
00a97672 20555#define ELF_MAXPAGESIZE 0x1000
90c14f0c
L		 20556#undef ELF_TARGET_OS
20557#define ELF_TARGET_OS is_vxworks
4e7fd91e
PB		 20558
20559#include "elf32-target.h"
20560
20561
21d799b5
NC		 20562/* Merge backend specific data from an object file to the output
20563 object file when linking. */
20564
20565static bfd_boolean
50e03d47 20566elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20567{
50e03d47 20568 bfd *obfd = info->output_bfd;
21d799b5
NC		 20569 flagword out_flags;
20570 flagword in_flags;
20571 bfd_boolean flags_compatible = TRUE;
20572 asection *sec;
20573
cc643b88 20574 /* Check if we have the same endianness. */
50e03d47 20575 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20576 return FALSE;
20577
20578 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20579 return TRUE;
20580
50e03d47 20581 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20582 return FALSE;
20583
20584 /* The input BFD must have had its flags initialised. */
20585 /* The following seems bogus to me -- The flags are initialized in
20586 the assembler but I don't think an elf_flags_init field is
20587 written into the object. */
20588 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20589
20590 in_flags = elf_elfheader (ibfd)->e_flags;
20591 out_flags = elf_elfheader (obfd)->e_flags;
20592
20593 /* In theory there is no reason why we couldn't handle this. However
20594 in practice it isn't even close to working and there is no real
20595 reason to want it. */
20596 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20597 && !(ibfd->flags & DYNAMIC)
20598 && (in_flags & EF_ARM_BE8))
20599 {
871b3ab2 20600 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20601 ibfd);
20602 return FALSE;
20603 }
20604
20605 if (!elf_flags_init (obfd))
20606 {
20607 /* If the input is the default architecture and had the default
20608 flags then do not bother setting the flags for the output
20609 architecture, instead allow future merges to do this. If no
20610 future merges ever set these flags then they will retain their
99059e56
RM		 20611 uninitialised values, which surprise surprise, correspond
20612 to the default values. */
21d799b5
NC		 20613 if (bfd_get_arch_info (ibfd)->the_default
20614 && elf_elfheader (ibfd)->e_flags == 0)
20615 return TRUE;
20616
20617 elf_flags_init (obfd) = TRUE;
20618 elf_elfheader (obfd)->e_flags = in_flags;
20619
20620 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20621 && bfd_get_arch_info (obfd)->the_default)
20622 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20623
20624 return TRUE;
20625 }
20626
20627 /* Determine what should happen if the input ARM architecture
20628 does not match the output ARM architecture. */
20629 if (! bfd_arm_merge_machines (ibfd, obfd))
20630 return FALSE;
20631
20632 /* Identical flags must be compatible. */
20633 if (in_flags == out_flags)
20634 return TRUE;
20635
20636 /* Check to see if the input BFD actually contains any sections. If
20637 not, its flags may not have been initialised either, but it
20638 cannot actually cause any incompatiblity. Do not short-circuit
20639 dynamic objects; their section list may be emptied by
20640 elf_link_add_object_symbols.
20641
20642 Also check to see if there are no code sections in the input.
20643 In this case there is no need to check for code specific flags.
20644 XXX - do we need to worry about floating-point format compatability
20645 in data sections ? */
20646 if (!(ibfd->flags & DYNAMIC))
20647 {
20648 bfd_boolean null_input_bfd = TRUE;
20649 bfd_boolean only_data_sections = TRUE;
20650
20651 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20652 {
20653 /* Ignore synthetic glue sections. */
20654 if (strcmp (sec->name, ".glue_7")
20655 && strcmp (sec->name, ".glue_7t"))
20656 {
fd361982 20657 if ((bfd_section_flags (sec)
21d799b5
NC		 20658 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20659 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20660 only_data_sections = FALSE;
21d799b5
NC		 20661
20662 null_input_bfd = FALSE;
20663 break;
20664 }
20665 }
20666
20667 if (null_input_bfd || only_data_sections)
20668 return TRUE;
20669 }
20670
20671 /* Complain about various flag mismatches. */
20672 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20673 EF_ARM_EABI_VERSION (out_flags)))
20674 {
20675 _bfd_error_handler
90b6238f 20676 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20677 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20678 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20679 return FALSE;
20680 }
20681
20682 /* Not sure what needs to be checked for EABI versions >= 1. */
20683 /* VxWorks libraries do not use these flags. */
20684 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20685 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20686 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20687 {
20688 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20689 {
20690 _bfd_error_handler
871b3ab2 20691 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20692 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20693 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20694 flags_compatible = FALSE;
20695 }
20696
20697 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20698 {
20699 if (in_flags & EF_ARM_APCS_FLOAT)
20700 _bfd_error_handler
871b3ab2 20701 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20702 ibfd, obfd);
20703 else
20704 _bfd_error_handler
871b3ab2 20705 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20706 ibfd, obfd);
20707
20708 flags_compatible = FALSE;
20709 }
20710
20711 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20712 {
20713 if (in_flags & EF_ARM_VFP_FLOAT)
20714 _bfd_error_handler
90b6238f
AM		 20715 (_("error: %pB uses %s instructions, whereas %pB does not"),
20716 ibfd, "VFP", obfd);
21d799b5
NC		 20717 else
20718 _bfd_error_handler
90b6238f
AM		 20719 (_("error: %pB uses %s instructions, whereas %pB does not"),
20720 ibfd, "FPA", obfd);
21d799b5
NC		 20721
20722 flags_compatible = FALSE;
20723 }
20724
20725 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20726 {
20727 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20728 _bfd_error_handler
90b6238f
AM		 20729 (_("error: %pB uses %s instructions, whereas %pB does not"),
20730 ibfd, "Maverick", obfd);
21d799b5
NC		 20731 else
20732 _bfd_error_handler
90b6238f
AM		 20733 (_("error: %pB does not use %s instructions, whereas %pB does"),
20734 ibfd, "Maverick", obfd);
21d799b5
NC		 20735
20736 flags_compatible = FALSE;
20737 }
20738
20739#ifdef EF_ARM_SOFT_FLOAT
20740 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20741 {
20742 /* We can allow interworking between code that is VFP format
20743 layout, and uses either soft float or integer regs for
20744 passing floating point arguments and results. We already
20745 know that the APCS_FLOAT flags match; similarly for VFP
20746 flags. */
20747 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20748 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20749 {
20750 if (in_flags & EF_ARM_SOFT_FLOAT)
20751 _bfd_error_handler
871b3ab2 20752 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20753 ibfd, obfd);
20754 else
20755 _bfd_error_handler
871b3ab2 20756 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20757 ibfd, obfd);
20758
20759 flags_compatible = FALSE;
20760 }
20761 }
20762#endif
20763
20764 /* Interworking mismatch is only a warning. */
20765 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20766 {
20767 if (in_flags & EF_ARM_INTERWORK)
20768 {
20769 _bfd_error_handler
90b6238f 20770 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20771 ibfd, obfd);
20772 }
20773 else
20774 {
20775 _bfd_error_handler
90b6238f 20776 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20777 ibfd, obfd);
20778 }
20779 }
20780 }
20781
20782 return flags_compatible;
20783}
20784
20785
906e58ca 20786/* Symbian OS Targets. */
7f266840 20787
07d6d2b8
AM		 20788#undef TARGET_LITTLE_SYM
20789#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20790#undef TARGET_LITTLE_NAME
20791#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20792#undef TARGET_BIG_SYM
20793#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20794#undef TARGET_BIG_NAME
20795#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20796
20797/* Like elf32_arm_link_hash_table_create -- but overrides
20798 appropriately for Symbian OS. */
906e58ca 20799
7f266840
DJ		 20800static struct bfd_link_hash_table *
20801elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20802{
20803 struct bfd_link_hash_table *ret;
20804
20805 ret = elf32_arm_link_hash_table_create (abfd);
20806 if (ret)
20807 {
20808 struct elf32_arm_link_hash_table *htab
20809 = (struct elf32_arm_link_hash_table *)ret;
20810 /* There is no PLT header for Symbian OS. */
20811 htab->plt_header_size = 0;
95720a86
DJ		 20812 /* The PLT entries are each one instruction and one word. */
20813 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
33bfe774
JB		 20814 /* Symbian uses armv5t or above, so use_blx is always true. */
20815 htab->use_blx = 1;
67687978 20816 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20817 }
20818 return ret;
906e58ca 20819}
7f266840 20820
b35d266b 20821static const struct bfd_elf_special_section
551b43fd 20822elf32_arm_symbian_special_sections[] =
7f266840 20823{
5cd3778d
MM		 20824 /* In a BPABI executable, the dynamic linking sections do not go in
20825 the loadable read-only segment. The post-linker may wish to
20826 refer to these sections, but they are not part of the final
20827 program image. */
07d6d2b8
AM		 20828 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20829 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20830 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20831 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20832 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20833 /* These sections do not need to be writable as the SymbianOS
20834 postlinker will arrange things so that no dynamic relocation is
20835 required. */
07d6d2b8
AM		 20836 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20837 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20838 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 20839 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 20840};
20841
c3c76620 20842static void
906e58ca 20843elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 20844 struct bfd_link_info *link_info)
c3c76620
MM		 20845{
20846 /* BPABI objects are never loaded directly by an OS kernel; they are
20847 processed by a postlinker first, into an OS-specific format. If
20848 the D_PAGED bit is set on the file, BFD will align segments on
20849 page boundaries, so that an OS can directly map the file. With
20850 BPABI objects, that just results in wasted space. In addition,
20851 because we clear the D_PAGED bit, map_sections_to_segments will
20852 recognize that the program headers should not be mapped into any
20853 loadable segment. */
20854 abfd->flags &= ~D_PAGED;
906e58ca 20855 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 20856}
7f266840
DJ		 20857
20858static bfd_boolean
906e58ca 20859elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 20860 struct bfd_link_info *info)
7f266840
DJ		 20861{
20862 struct elf_segment_map *m;
20863 asection *dynsec;
20864
7f266840
DJ		 20865 /* BPABI shared libraries and executables should have a PT_DYNAMIC
20866 segment. However, because the .dynamic section is not marked
20867 with SEC_LOAD, the generic ELF code will not create such a
20868 segment. */
20869 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
20870 if (dynsec)
20871 {
12bd6957 20872 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 20873 if (m->p_type == PT_DYNAMIC)
20874 break;
20875
20876 if (m == NULL)
20877 {
20878 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 20879 m->next = elf_seg_map (abfd);
20880 elf_seg_map (abfd) = m;
8ded5a0f 20881 }
7f266840
DJ		 20882 }
20883
b294bdf8
MM		 20884 /* Also call the generic arm routine. */
20885 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 20886}
20887
95720a86
DJ		 20888/* Return address for Ith PLT stub in section PLT, for relocation REL
20889 or (bfd_vma) -1 if it should not be included. */
20890
20891static bfd_vma
20892elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
20893 const arelent *rel ATTRIBUTE_UNUSED)
20894{
20895 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
20896}
20897
8029a119 20898#undef elf32_bed
7f266840
DJ		 20899#define elf32_bed elf32_arm_symbian_bed
20900
20901/* The dynamic sections are not allocated on SymbianOS; the postlinker
20902 will process them and then discard them. */
906e58ca 20903#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 20904#define ELF_DYNAMIC_SEC_FLAGS \
20905 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
20906
9eaff861 20907#undef elf_backend_emit_relocs
c3c76620 20908
906e58ca
NC		 20909#undef bfd_elf32_bfd_link_hash_table_create
20910#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
20911#undef elf_backend_special_sections
07d6d2b8 20912#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 20913#undef elf_backend_begin_write_processing
20914#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
20915#undef elf_backend_final_write_processing
20916#define elf_backend_final_write_processing elf32_arm_final_write_processing
20917
20918#undef elf_backend_modify_segment_map
7f266840
DJ		 20919#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
20920
20921/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 20922#undef elf_backend_got_header_size
7f266840
DJ		 20923#define elf_backend_got_header_size 0
20924
20925/* Similarly, there is no .got.plt section. */
906e58ca 20926#undef elf_backend_want_got_plt
7f266840
DJ		 20927#define elf_backend_want_got_plt 0
20928
906e58ca 20929#undef elf_backend_plt_sym_val
95720a86
DJ		 20930#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
20931
906e58ca 20932#undef elf_backend_may_use_rel_p
00a97672 20933#define elf_backend_may_use_rel_p 1
906e58ca 20934#undef elf_backend_may_use_rela_p
00a97672 20935#define elf_backend_may_use_rela_p 0
906e58ca 20936#undef elf_backend_default_use_rela_p
00a97672 20937#define elf_backend_default_use_rela_p 0
906e58ca 20938#undef elf_backend_want_plt_sym
00a97672 20939#define elf_backend_want_plt_sym 0
64f52338
AM		 20940#undef elf_backend_dtrel_excludes_plt
20941#define elf_backend_dtrel_excludes_plt 0
906e58ca 20942#undef ELF_MAXPAGESIZE
00a97672 20943#define ELF_MAXPAGESIZE 0x8000
90c14f0c
L		 20944#undef ELF_TARGET_OS
20945#define ELF_TARGET_OS is_symbian
4e7fd91e 20946
7f266840 20947#include "elf32-target.h"
GDB Binutils - Deliverables
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