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Fix issues with multiple inferiors
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
b3adc24a 2 Copyright (C) 1998-2020 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
f37164d7
AM		 31#include "elf32-arm.h"
32#include "cpu-arm.h"
7f266840 33
00a97672
RS		 34/* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36#define RELOC_SECTION(HTAB, NAME) \
37 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
38
39/* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41#define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
45
46/* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48#define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
52
53/* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55#define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
59
f3185997 60#define elf_info_to_howto NULL
07d6d2b8 61#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 62
63#define ARM_ELF_ABI_VERSION 0
64#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65
79f08007
YZ		 66/* The Adjusted Place, as defined by AAELF. */
67#define Pa(X) ((X) & 0xfffffffc)
68
3e6b1042
DJ		 69static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
70 struct bfd_link_info *link_info,
71 asection *sec,
72 bfd_byte *contents);
73
7f266840
DJ		 74/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
77
c19d1205 78static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 79{
8029a119 80 /* No relocation. */
7f266840
DJ		 81 HOWTO (R_ARM_NONE, /* type */
82 0, /* rightshift */
6346d5ca 83 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 84 0, /* bitsize */
85 FALSE, /* pc_relative */
86 0, /* bitpos */
87 complain_overflow_dont,/* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_ARM_NONE", /* name */
90 FALSE, /* partial_inplace */
91 0, /* src_mask */
92 0, /* dst_mask */
93 FALSE), /* pcrel_offset */
94
95 HOWTO (R_ARM_PC24, /* type */
96 2, /* rightshift */
97 2, /* size (0 = byte, 1 = short, 2 = long) */
98 24, /* bitsize */
99 TRUE, /* pc_relative */
100 0, /* bitpos */
101 complain_overflow_signed,/* complain_on_overflow */
102 bfd_elf_generic_reloc, /* special_function */
103 "R_ARM_PC24", /* name */
104 FALSE, /* partial_inplace */
105 0x00ffffff, /* src_mask */
106 0x00ffffff, /* dst_mask */
107 TRUE), /* pcrel_offset */
108
109 /* 32 bit absolute */
110 HOWTO (R_ARM_ABS32, /* type */
111 0, /* rightshift */
112 2, /* size (0 = byte, 1 = short, 2 = long) */
113 32, /* bitsize */
114 FALSE, /* pc_relative */
115 0, /* bitpos */
116 complain_overflow_bitfield,/* complain_on_overflow */
117 bfd_elf_generic_reloc, /* special_function */
118 "R_ARM_ABS32", /* name */
119 FALSE, /* partial_inplace */
120 0xffffffff, /* src_mask */
121 0xffffffff, /* dst_mask */
122 FALSE), /* pcrel_offset */
123
124 /* standard 32bit pc-relative reloc */
125 HOWTO (R_ARM_REL32, /* type */
126 0, /* rightshift */
127 2, /* size (0 = byte, 1 = short, 2 = long) */
128 32, /* bitsize */
129 TRUE, /* pc_relative */
130 0, /* bitpos */
131 complain_overflow_bitfield,/* complain_on_overflow */
132 bfd_elf_generic_reloc, /* special_function */
133 "R_ARM_REL32", /* name */
134 FALSE, /* partial_inplace */
135 0xffffffff, /* src_mask */
136 0xffffffff, /* dst_mask */
137 TRUE), /* pcrel_offset */
138
c19d1205 139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 140 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 141 0, /* rightshift */
142 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 143 32, /* bitsize */
144 TRUE, /* pc_relative */
7f266840 145 0, /* bitpos */
4962c51a 146 complain_overflow_dont,/* complain_on_overflow */
7f266840 147 bfd_elf_generic_reloc, /* special_function */
4962c51a 148 "R_ARM_LDR_PC_G0", /* name */
7f266840 149 FALSE, /* partial_inplace */
4962c51a
MS		 150 0xffffffff, /* src_mask */
151 0xffffffff, /* dst_mask */
152 TRUE), /* pcrel_offset */
7f266840
DJ		 153
154 /* 16 bit absolute */
155 HOWTO (R_ARM_ABS16, /* type */
156 0, /* rightshift */
157 1, /* size (0 = byte, 1 = short, 2 = long) */
158 16, /* bitsize */
159 FALSE, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield,/* complain_on_overflow */
162 bfd_elf_generic_reloc, /* special_function */
163 "R_ARM_ABS16", /* name */
164 FALSE, /* partial_inplace */
165 0x0000ffff, /* src_mask */
166 0x0000ffff, /* dst_mask */
167 FALSE), /* pcrel_offset */
168
169 /* 12 bit absolute */
170 HOWTO (R_ARM_ABS12, /* type */
171 0, /* rightshift */
172 2, /* size (0 = byte, 1 = short, 2 = long) */
173 12, /* bitsize */
174 FALSE, /* pc_relative */
175 0, /* bitpos */
176 complain_overflow_bitfield,/* complain_on_overflow */
177 bfd_elf_generic_reloc, /* special_function */
178 "R_ARM_ABS12", /* name */
179 FALSE, /* partial_inplace */
00a97672
RS		 180 0x00000fff, /* src_mask */
181 0x00000fff, /* dst_mask */
7f266840
DJ		 182 FALSE), /* pcrel_offset */
183
184 HOWTO (R_ARM_THM_ABS5, /* type */
185 6, /* rightshift */
186 1, /* size (0 = byte, 1 = short, 2 = long) */
187 5, /* bitsize */
188 FALSE, /* pc_relative */
189 0, /* bitpos */
190 complain_overflow_bitfield,/* complain_on_overflow */
191 bfd_elf_generic_reloc, /* special_function */
192 "R_ARM_THM_ABS5", /* name */
193 FALSE, /* partial_inplace */
194 0x000007e0, /* src_mask */
195 0x000007e0, /* dst_mask */
196 FALSE), /* pcrel_offset */
197
198 /* 8 bit absolute */
199 HOWTO (R_ARM_ABS8, /* type */
200 0, /* rightshift */
201 0, /* size (0 = byte, 1 = short, 2 = long) */
202 8, /* bitsize */
203 FALSE, /* pc_relative */
204 0, /* bitpos */
205 complain_overflow_bitfield,/* complain_on_overflow */
206 bfd_elf_generic_reloc, /* special_function */
207 "R_ARM_ABS8", /* name */
208 FALSE, /* partial_inplace */
209 0x000000ff, /* src_mask */
210 0x000000ff, /* dst_mask */
211 FALSE), /* pcrel_offset */
212
213 HOWTO (R_ARM_SBREL32, /* type */
214 0, /* rightshift */
215 2, /* size (0 = byte, 1 = short, 2 = long) */
216 32, /* bitsize */
217 FALSE, /* pc_relative */
218 0, /* bitpos */
219 complain_overflow_dont,/* complain_on_overflow */
220 bfd_elf_generic_reloc, /* special_function */
221 "R_ARM_SBREL32", /* name */
222 FALSE, /* partial_inplace */
223 0xffffffff, /* src_mask */
224 0xffffffff, /* dst_mask */
225 FALSE), /* pcrel_offset */
226
c19d1205 227 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 228 1, /* rightshift */
229 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 230 24, /* bitsize */
7f266840
DJ		 231 TRUE, /* pc_relative */
232 0, /* bitpos */
233 complain_overflow_signed,/* complain_on_overflow */
234 bfd_elf_generic_reloc, /* special_function */
c19d1205 235 "R_ARM_THM_CALL", /* name */
7f266840 236 FALSE, /* partial_inplace */
7f6ab9f8
AM		 237 0x07ff2fff, /* src_mask */
238 0x07ff2fff, /* dst_mask */
7f266840
DJ		 239 TRUE), /* pcrel_offset */
240
07d6d2b8 241 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 242 1, /* rightshift */
243 1, /* size (0 = byte, 1 = short, 2 = long) */
244 8, /* bitsize */
245 TRUE, /* pc_relative */
246 0, /* bitpos */
247 complain_overflow_signed,/* complain_on_overflow */
248 bfd_elf_generic_reloc, /* special_function */
249 "R_ARM_THM_PC8", /* name */
250 FALSE, /* partial_inplace */
251 0x000000ff, /* src_mask */
252 0x000000ff, /* dst_mask */
253 TRUE), /* pcrel_offset */
254
c19d1205 255 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 256 1, /* rightshift */
257 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 258 32, /* bitsize */
259 FALSE, /* pc_relative */
7f266840
DJ		 260 0, /* bitpos */
261 complain_overflow_signed,/* complain_on_overflow */
262 bfd_elf_generic_reloc, /* special_function */
c19d1205 263 "R_ARM_BREL_ADJ", /* name */
7f266840 264 FALSE, /* partial_inplace */
c19d1205
ZW		 265 0xffffffff, /* src_mask */
266 0xffffffff, /* dst_mask */
267 FALSE), /* pcrel_offset */
7f266840 268
0855e32b 269 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 270 0, /* rightshift */
0855e32b
NS		 271 2, /* size (0 = byte, 1 = short, 2 = long) */
272 32, /* bitsize */
7f266840
DJ		 273 FALSE, /* pc_relative */
274 0, /* bitpos */
0855e32b 275 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 276 bfd_elf_generic_reloc, /* special_function */
0855e32b 277 "R_ARM_TLS_DESC", /* name */
7f266840 278 FALSE, /* partial_inplace */
0855e32b
NS		 279 0xffffffff, /* src_mask */
280 0xffffffff, /* dst_mask */
7f266840
DJ		 281 FALSE), /* pcrel_offset */
282
283 HOWTO (R_ARM_THM_SWI8, /* type */
284 0, /* rightshift */
285 0, /* size (0 = byte, 1 = short, 2 = long) */
286 0, /* bitsize */
287 FALSE, /* pc_relative */
288 0, /* bitpos */
289 complain_overflow_signed,/* complain_on_overflow */
290 bfd_elf_generic_reloc, /* special_function */
291 "R_ARM_SWI8", /* name */
292 FALSE, /* partial_inplace */
293 0x00000000, /* src_mask */
294 0x00000000, /* dst_mask */
295 FALSE), /* pcrel_offset */
296
297 /* BLX instruction for the ARM. */
298 HOWTO (R_ARM_XPC25, /* type */
299 2, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 301 24, /* bitsize */
7f266840
DJ		 302 TRUE, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_signed,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_ARM_XPC25", /* name */
307 FALSE, /* partial_inplace */
308 0x00ffffff, /* src_mask */
309 0x00ffffff, /* dst_mask */
310 TRUE), /* pcrel_offset */
311
312 /* BLX instruction for the Thumb. */
313 HOWTO (R_ARM_THM_XPC22, /* type */
314 2, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 316 24, /* bitsize */
7f266840
DJ		 317 TRUE, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_signed,/* complain_on_overflow */
320 bfd_elf_generic_reloc, /* special_function */
321 "R_ARM_THM_XPC22", /* name */
322 FALSE, /* partial_inplace */
7f6ab9f8
AM		 323 0x07ff2fff, /* src_mask */
324 0x07ff2fff, /* dst_mask */
7f266840
DJ		 325 TRUE), /* pcrel_offset */
326
ba93b8ac 327 /* Dynamic TLS relocations. */
7f266840 328
ba93b8ac 329 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 330 0, /* rightshift */
331 2, /* size (0 = byte, 1 = short, 2 = long) */
332 32, /* bitsize */
333 FALSE, /* pc_relative */
334 0, /* bitpos */
99059e56
RM		 335 complain_overflow_bitfield,/* complain_on_overflow */
336 bfd_elf_generic_reloc, /* special_function */
337 "R_ARM_TLS_DTPMOD32", /* name */
338 TRUE, /* partial_inplace */
339 0xffffffff, /* src_mask */
340 0xffffffff, /* dst_mask */
07d6d2b8 341 FALSE), /* pcrel_offset */
7f266840 342
ba93b8ac 343 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 344 0, /* rightshift */
345 2, /* size (0 = byte, 1 = short, 2 = long) */
346 32, /* bitsize */
347 FALSE, /* pc_relative */
348 0, /* bitpos */
99059e56
RM		 349 complain_overflow_bitfield,/* complain_on_overflow */
350 bfd_elf_generic_reloc, /* special_function */
351 "R_ARM_TLS_DTPOFF32", /* name */
352 TRUE, /* partial_inplace */
353 0xffffffff, /* src_mask */
354 0xffffffff, /* dst_mask */
07d6d2b8 355 FALSE), /* pcrel_offset */
7f266840 356
ba93b8ac 357 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 358 0, /* rightshift */
359 2, /* size (0 = byte, 1 = short, 2 = long) */
360 32, /* bitsize */
361 FALSE, /* pc_relative */
362 0, /* bitpos */
99059e56
RM		 363 complain_overflow_bitfield,/* complain_on_overflow */
364 bfd_elf_generic_reloc, /* special_function */
365 "R_ARM_TLS_TPOFF32", /* name */
366 TRUE, /* partial_inplace */
367 0xffffffff, /* src_mask */
368 0xffffffff, /* dst_mask */
07d6d2b8 369 FALSE), /* pcrel_offset */
7f266840
DJ		 370
371 /* Relocs used in ARM Linux */
372
373 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 374 0, /* rightshift */
375 2, /* size (0 = byte, 1 = short, 2 = long) */
376 32, /* bitsize */
377 FALSE, /* pc_relative */
378 0, /* bitpos */
99059e56
RM		 379 complain_overflow_bitfield,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_ARM_COPY", /* name */
382 TRUE, /* partial_inplace */
383 0xffffffff, /* src_mask */
384 0xffffffff, /* dst_mask */
07d6d2b8 385 FALSE), /* pcrel_offset */
7f266840
DJ		 386
387 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 388 0, /* rightshift */
389 2, /* size (0 = byte, 1 = short, 2 = long) */
390 32, /* bitsize */
391 FALSE, /* pc_relative */
392 0, /* bitpos */
99059e56
RM		 393 complain_overflow_bitfield,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_ARM_GLOB_DAT", /* name */
396 TRUE, /* partial_inplace */
397 0xffffffff, /* src_mask */
398 0xffffffff, /* dst_mask */
07d6d2b8 399 FALSE), /* pcrel_offset */
7f266840
DJ		 400
401 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 402 0, /* rightshift */
403 2, /* size (0 = byte, 1 = short, 2 = long) */
404 32, /* bitsize */
405 FALSE, /* pc_relative */
406 0, /* bitpos */
99059e56
RM		 407 complain_overflow_bitfield,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_ARM_JUMP_SLOT", /* name */
410 TRUE, /* partial_inplace */
411 0xffffffff, /* src_mask */
412 0xffffffff, /* dst_mask */
07d6d2b8 413 FALSE), /* pcrel_offset */
7f266840
DJ		 414
415 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 416 0, /* rightshift */
417 2, /* size (0 = byte, 1 = short, 2 = long) */
418 32, /* bitsize */
419 FALSE, /* pc_relative */
420 0, /* bitpos */
99059e56
RM		 421 complain_overflow_bitfield,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_ARM_RELATIVE", /* name */
424 TRUE, /* partial_inplace */
425 0xffffffff, /* src_mask */
426 0xffffffff, /* dst_mask */
07d6d2b8 427 FALSE), /* pcrel_offset */
7f266840 428
c19d1205 429 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 430 0, /* rightshift */
431 2, /* size (0 = byte, 1 = short, 2 = long) */
432 32, /* bitsize */
433 FALSE, /* pc_relative */
434 0, /* bitpos */
99059e56
RM		 435 complain_overflow_bitfield,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_ARM_GOTOFF32", /* name */
438 TRUE, /* partial_inplace */
439 0xffffffff, /* src_mask */
440 0xffffffff, /* dst_mask */
07d6d2b8 441 FALSE), /* pcrel_offset */
7f266840
DJ		 442
443 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 444 0, /* rightshift */
445 2, /* size (0 = byte, 1 = short, 2 = long) */
446 32, /* bitsize */
99059e56 447 TRUE, /* pc_relative */
07d6d2b8 448 0, /* bitpos */
99059e56
RM		 449 complain_overflow_bitfield,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_ARM_GOTPC", /* name */
452 TRUE, /* partial_inplace */
453 0xffffffff, /* src_mask */
454 0xffffffff, /* dst_mask */
455 TRUE), /* pcrel_offset */
7f266840
DJ		 456
457 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 458 0, /* rightshift */
459 2, /* size (0 = byte, 1 = short, 2 = long) */
460 32, /* bitsize */
99059e56 461 FALSE, /* pc_relative */
07d6d2b8 462 0, /* bitpos */
99059e56
RM		 463 complain_overflow_bitfield,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_ARM_GOT32", /* name */
466 TRUE, /* partial_inplace */
467 0xffffffff, /* src_mask */
468 0xffffffff, /* dst_mask */
469 FALSE), /* pcrel_offset */
7f266840
DJ		 470
471 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 472 2, /* rightshift */
473 2, /* size (0 = byte, 1 = short, 2 = long) */
474 24, /* bitsize */
99059e56 475 TRUE, /* pc_relative */
07d6d2b8 476 0, /* bitpos */
99059e56
RM		 477 complain_overflow_bitfield,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_ARM_PLT32", /* name */
480 FALSE, /* partial_inplace */
481 0x00ffffff, /* src_mask */
482 0x00ffffff, /* dst_mask */
483 TRUE), /* pcrel_offset */
7f266840
DJ		 484
485 HOWTO (R_ARM_CALL, /* type */
486 2, /* rightshift */
487 2, /* size (0 = byte, 1 = short, 2 = long) */
488 24, /* bitsize */
489 TRUE, /* pc_relative */
490 0, /* bitpos */
491 complain_overflow_signed,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_ARM_CALL", /* name */
494 FALSE, /* partial_inplace */
495 0x00ffffff, /* src_mask */
496 0x00ffffff, /* dst_mask */
497 TRUE), /* pcrel_offset */
498
499 HOWTO (R_ARM_JUMP24, /* type */
500 2, /* rightshift */
501 2, /* size (0 = byte, 1 = short, 2 = long) */
502 24, /* bitsize */
503 TRUE, /* pc_relative */
504 0, /* bitpos */
505 complain_overflow_signed,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_ARM_JUMP24", /* name */
508 FALSE, /* partial_inplace */
509 0x00ffffff, /* src_mask */
510 0x00ffffff, /* dst_mask */
511 TRUE), /* pcrel_offset */
512
c19d1205
ZW		 513 HOWTO (R_ARM_THM_JUMP24, /* type */
514 1, /* rightshift */
515 2, /* size (0 = byte, 1 = short, 2 = long) */
516 24, /* bitsize */
517 TRUE, /* pc_relative */
7f266840 518 0, /* bitpos */
c19d1205 519 complain_overflow_signed,/* complain_on_overflow */
7f266840 520 bfd_elf_generic_reloc, /* special_function */
c19d1205 521 "R_ARM_THM_JUMP24", /* name */
7f266840 522 FALSE, /* partial_inplace */
c19d1205
ZW		 523 0x07ff2fff, /* src_mask */
524 0x07ff2fff, /* dst_mask */
525 TRUE), /* pcrel_offset */
7f266840 526
c19d1205 527 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 528 0, /* rightshift */
c19d1205
ZW		 529 2, /* size (0 = byte, 1 = short, 2 = long) */
530 32, /* bitsize */
7f266840
DJ		 531 FALSE, /* pc_relative */
532 0, /* bitpos */
533 complain_overflow_dont,/* complain_on_overflow */
534 bfd_elf_generic_reloc, /* special_function */
c19d1205 535 "R_ARM_BASE_ABS", /* name */
7f266840 536 FALSE, /* partial_inplace */
c19d1205
ZW		 537 0xffffffff, /* src_mask */
538 0xffffffff, /* dst_mask */
7f266840
DJ		 539 FALSE), /* pcrel_offset */
540
541 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
542 0, /* rightshift */
543 2, /* size (0 = byte, 1 = short, 2 = long) */
544 12, /* bitsize */
545 TRUE, /* pc_relative */
546 0, /* bitpos */
547 complain_overflow_dont,/* complain_on_overflow */
548 bfd_elf_generic_reloc, /* special_function */
549 "R_ARM_ALU_PCREL_7_0", /* name */
550 FALSE, /* partial_inplace */
551 0x00000fff, /* src_mask */
552 0x00000fff, /* dst_mask */
553 TRUE), /* pcrel_offset */
554
555 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
556 0, /* rightshift */
557 2, /* size (0 = byte, 1 = short, 2 = long) */
558 12, /* bitsize */
559 TRUE, /* pc_relative */
560 8, /* bitpos */
561 complain_overflow_dont,/* complain_on_overflow */
562 bfd_elf_generic_reloc, /* special_function */
563 "R_ARM_ALU_PCREL_15_8",/* name */
564 FALSE, /* partial_inplace */
565 0x00000fff, /* src_mask */
566 0x00000fff, /* dst_mask */
567 TRUE), /* pcrel_offset */
568
569 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
570 0, /* rightshift */
571 2, /* size (0 = byte, 1 = short, 2 = long) */
572 12, /* bitsize */
573 TRUE, /* pc_relative */
574 16, /* bitpos */
575 complain_overflow_dont,/* complain_on_overflow */
576 bfd_elf_generic_reloc, /* special_function */
577 "R_ARM_ALU_PCREL_23_15",/* name */
578 FALSE, /* partial_inplace */
579 0x00000fff, /* src_mask */
580 0x00000fff, /* dst_mask */
581 TRUE), /* pcrel_offset */
582
583 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
584 0, /* rightshift */
585 2, /* size (0 = byte, 1 = short, 2 = long) */
586 12, /* bitsize */
587 FALSE, /* pc_relative */
588 0, /* bitpos */
589 complain_overflow_dont,/* complain_on_overflow */
590 bfd_elf_generic_reloc, /* special_function */
591 "R_ARM_LDR_SBREL_11_0",/* name */
592 FALSE, /* partial_inplace */
593 0x00000fff, /* src_mask */
594 0x00000fff, /* dst_mask */
595 FALSE), /* pcrel_offset */
596
597 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
598 0, /* rightshift */
599 2, /* size (0 = byte, 1 = short, 2 = long) */
600 8, /* bitsize */
601 FALSE, /* pc_relative */
602 12, /* bitpos */
603 complain_overflow_dont,/* complain_on_overflow */
604 bfd_elf_generic_reloc, /* special_function */
605 "R_ARM_ALU_SBREL_19_12",/* name */
606 FALSE, /* partial_inplace */
607 0x000ff000, /* src_mask */
608 0x000ff000, /* dst_mask */
609 FALSE), /* pcrel_offset */
610
611 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
612 0, /* rightshift */
613 2, /* size (0 = byte, 1 = short, 2 = long) */
614 8, /* bitsize */
615 FALSE, /* pc_relative */
616 20, /* bitpos */
617 complain_overflow_dont,/* complain_on_overflow */
618 bfd_elf_generic_reloc, /* special_function */
619 "R_ARM_ALU_SBREL_27_20",/* name */
620 FALSE, /* partial_inplace */
621 0x0ff00000, /* src_mask */
622 0x0ff00000, /* dst_mask */
623 FALSE), /* pcrel_offset */
624
625 HOWTO (R_ARM_TARGET1, /* type */
626 0, /* rightshift */
627 2, /* size (0 = byte, 1 = short, 2 = long) */
628 32, /* bitsize */
629 FALSE, /* pc_relative */
630 0, /* bitpos */
631 complain_overflow_dont,/* complain_on_overflow */
632 bfd_elf_generic_reloc, /* special_function */
633 "R_ARM_TARGET1", /* name */
634 FALSE, /* partial_inplace */
635 0xffffffff, /* src_mask */
636 0xffffffff, /* dst_mask */
637 FALSE), /* pcrel_offset */
638
639 HOWTO (R_ARM_ROSEGREL32, /* type */
640 0, /* rightshift */
641 2, /* size (0 = byte, 1 = short, 2 = long) */
642 32, /* bitsize */
643 FALSE, /* pc_relative */
644 0, /* bitpos */
645 complain_overflow_dont,/* complain_on_overflow */
646 bfd_elf_generic_reloc, /* special_function */
647 "R_ARM_ROSEGREL32", /* name */
648 FALSE, /* partial_inplace */
649 0xffffffff, /* src_mask */
650 0xffffffff, /* dst_mask */
651 FALSE), /* pcrel_offset */
652
653 HOWTO (R_ARM_V4BX, /* type */
654 0, /* rightshift */
655 2, /* size (0 = byte, 1 = short, 2 = long) */
656 32, /* bitsize */
657 FALSE, /* pc_relative */
658 0, /* bitpos */
659 complain_overflow_dont,/* complain_on_overflow */
660 bfd_elf_generic_reloc, /* special_function */
661 "R_ARM_V4BX", /* name */
662 FALSE, /* partial_inplace */
663 0xffffffff, /* src_mask */
664 0xffffffff, /* dst_mask */
665 FALSE), /* pcrel_offset */
666
667 HOWTO (R_ARM_TARGET2, /* type */
668 0, /* rightshift */
669 2, /* size (0 = byte, 1 = short, 2 = long) */
670 32, /* bitsize */
671 FALSE, /* pc_relative */
672 0, /* bitpos */
673 complain_overflow_signed,/* complain_on_overflow */
674 bfd_elf_generic_reloc, /* special_function */
675 "R_ARM_TARGET2", /* name */
676 FALSE, /* partial_inplace */
677 0xffffffff, /* src_mask */
678 0xffffffff, /* dst_mask */
679 TRUE), /* pcrel_offset */
680
681 HOWTO (R_ARM_PREL31, /* type */
682 0, /* rightshift */
683 2, /* size (0 = byte, 1 = short, 2 = long) */
684 31, /* bitsize */
685 TRUE, /* pc_relative */
686 0, /* bitpos */
687 complain_overflow_signed,/* complain_on_overflow */
688 bfd_elf_generic_reloc, /* special_function */
689 "R_ARM_PREL31", /* name */
690 FALSE, /* partial_inplace */
691 0x7fffffff, /* src_mask */
692 0x7fffffff, /* dst_mask */
693 TRUE), /* pcrel_offset */
c19d1205
ZW		 694
695 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
696 0, /* rightshift */
697 2, /* size (0 = byte, 1 = short, 2 = long) */
698 16, /* bitsize */
699 FALSE, /* pc_relative */
700 0, /* bitpos */
701 complain_overflow_dont,/* complain_on_overflow */
702 bfd_elf_generic_reloc, /* special_function */
703 "R_ARM_MOVW_ABS_NC", /* name */
704 FALSE, /* partial_inplace */
39623e12
PB		 705 0x000f0fff, /* src_mask */
706 0x000f0fff, /* dst_mask */
c19d1205
ZW		 707 FALSE), /* pcrel_offset */
708
709 HOWTO (R_ARM_MOVT_ABS, /* type */
710 0, /* rightshift */
711 2, /* size (0 = byte, 1 = short, 2 = long) */
712 16, /* bitsize */
713 FALSE, /* pc_relative */
714 0, /* bitpos */
715 complain_overflow_bitfield,/* complain_on_overflow */
716 bfd_elf_generic_reloc, /* special_function */
717 "R_ARM_MOVT_ABS", /* name */
718 FALSE, /* partial_inplace */
39623e12
PB		 719 0x000f0fff, /* src_mask */
720 0x000f0fff, /* dst_mask */
c19d1205
ZW		 721 FALSE), /* pcrel_offset */
722
723 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
724 0, /* rightshift */
725 2, /* size (0 = byte, 1 = short, 2 = long) */
726 16, /* bitsize */
727 TRUE, /* pc_relative */
728 0, /* bitpos */
729 complain_overflow_dont,/* complain_on_overflow */
730 bfd_elf_generic_reloc, /* special_function */
731 "R_ARM_MOVW_PREL_NC", /* name */
732 FALSE, /* partial_inplace */
39623e12
PB		 733 0x000f0fff, /* src_mask */
734 0x000f0fff, /* dst_mask */
c19d1205
ZW		 735 TRUE), /* pcrel_offset */
736
737 HOWTO (R_ARM_MOVT_PREL, /* type */
738 0, /* rightshift */
739 2, /* size (0 = byte, 1 = short, 2 = long) */
740 16, /* bitsize */
741 TRUE, /* pc_relative */
742 0, /* bitpos */
743 complain_overflow_bitfield,/* complain_on_overflow */
744 bfd_elf_generic_reloc, /* special_function */
745 "R_ARM_MOVT_PREL", /* name */
746 FALSE, /* partial_inplace */
39623e12
PB		 747 0x000f0fff, /* src_mask */
748 0x000f0fff, /* dst_mask */
c19d1205
ZW		 749 TRUE), /* pcrel_offset */
750
751 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
752 0, /* rightshift */
753 2, /* size (0 = byte, 1 = short, 2 = long) */
754 16, /* bitsize */
755 FALSE, /* pc_relative */
756 0, /* bitpos */
757 complain_overflow_dont,/* complain_on_overflow */
758 bfd_elf_generic_reloc, /* special_function */
759 "R_ARM_THM_MOVW_ABS_NC",/* name */
760 FALSE, /* partial_inplace */
761 0x040f70ff, /* src_mask */
762 0x040f70ff, /* dst_mask */
763 FALSE), /* pcrel_offset */
764
765 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
766 0, /* rightshift */
767 2, /* size (0 = byte, 1 = short, 2 = long) */
768 16, /* bitsize */
769 FALSE, /* pc_relative */
770 0, /* bitpos */
771 complain_overflow_bitfield,/* complain_on_overflow */
772 bfd_elf_generic_reloc, /* special_function */
773 "R_ARM_THM_MOVT_ABS", /* name */
774 FALSE, /* partial_inplace */
775 0x040f70ff, /* src_mask */
776 0x040f70ff, /* dst_mask */
777 FALSE), /* pcrel_offset */
778
779 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
780 0, /* rightshift */
781 2, /* size (0 = byte, 1 = short, 2 = long) */
782 16, /* bitsize */
783 TRUE, /* pc_relative */
784 0, /* bitpos */
785 complain_overflow_dont,/* complain_on_overflow */
786 bfd_elf_generic_reloc, /* special_function */
787 "R_ARM_THM_MOVW_PREL_NC",/* name */
788 FALSE, /* partial_inplace */
789 0x040f70ff, /* src_mask */
790 0x040f70ff, /* dst_mask */
791 TRUE), /* pcrel_offset */
792
793 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
794 0, /* rightshift */
795 2, /* size (0 = byte, 1 = short, 2 = long) */
796 16, /* bitsize */
797 TRUE, /* pc_relative */
798 0, /* bitpos */
799 complain_overflow_bitfield,/* complain_on_overflow */
800 bfd_elf_generic_reloc, /* special_function */
801 "R_ARM_THM_MOVT_PREL", /* name */
802 FALSE, /* partial_inplace */
803 0x040f70ff, /* src_mask */
804 0x040f70ff, /* dst_mask */
805 TRUE), /* pcrel_offset */
806
807 HOWTO (R_ARM_THM_JUMP19, /* type */
808 1, /* rightshift */
809 2, /* size (0 = byte, 1 = short, 2 = long) */
810 19, /* bitsize */
811 TRUE, /* pc_relative */
812 0, /* bitpos */
813 complain_overflow_signed,/* complain_on_overflow */
814 bfd_elf_generic_reloc, /* special_function */
815 "R_ARM_THM_JUMP19", /* name */
816 FALSE, /* partial_inplace */
817 0x043f2fff, /* src_mask */
818 0x043f2fff, /* dst_mask */
819 TRUE), /* pcrel_offset */
820
821 HOWTO (R_ARM_THM_JUMP6, /* type */
822 1, /* rightshift */
823 1, /* size (0 = byte, 1 = short, 2 = long) */
824 6, /* bitsize */
825 TRUE, /* pc_relative */
826 0, /* bitpos */
827 complain_overflow_unsigned,/* complain_on_overflow */
828 bfd_elf_generic_reloc, /* special_function */
829 "R_ARM_THM_JUMP6", /* name */
830 FALSE, /* partial_inplace */
831 0x02f8, /* src_mask */
832 0x02f8, /* dst_mask */
833 TRUE), /* pcrel_offset */
834
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
838 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
839 0, /* rightshift */
840 2, /* size (0 = byte, 1 = short, 2 = long) */
841 13, /* bitsize */
842 TRUE, /* pc_relative */
843 0, /* bitpos */
2cab6cc3 844 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 845 bfd_elf_generic_reloc, /* special_function */
846 "R_ARM_THM_ALU_PREL_11_0",/* name */
847 FALSE, /* partial_inplace */
2cab6cc3
MS		 848 0xffffffff, /* src_mask */
849 0xffffffff, /* dst_mask */
c19d1205
ZW		 850 TRUE), /* pcrel_offset */
851
852 HOWTO (R_ARM_THM_PC12, /* type */
853 0, /* rightshift */
854 2, /* size (0 = byte, 1 = short, 2 = long) */
855 13, /* bitsize */
856 TRUE, /* pc_relative */
857 0, /* bitpos */
2cab6cc3 858 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 859 bfd_elf_generic_reloc, /* special_function */
860 "R_ARM_THM_PC12", /* name */
861 FALSE, /* partial_inplace */
2cab6cc3
MS		 862 0xffffffff, /* src_mask */
863 0xffffffff, /* dst_mask */
c19d1205
ZW		 864 TRUE), /* pcrel_offset */
865
866 HOWTO (R_ARM_ABS32_NOI, /* type */
867 0, /* rightshift */
868 2, /* size (0 = byte, 1 = short, 2 = long) */
869 32, /* bitsize */
870 FALSE, /* pc_relative */
871 0, /* bitpos */
872 complain_overflow_dont,/* complain_on_overflow */
873 bfd_elf_generic_reloc, /* special_function */
874 "R_ARM_ABS32_NOI", /* name */
875 FALSE, /* partial_inplace */
876 0xffffffff, /* src_mask */
877 0xffffffff, /* dst_mask */
878 FALSE), /* pcrel_offset */
879
880 HOWTO (R_ARM_REL32_NOI, /* type */
881 0, /* rightshift */
882 2, /* size (0 = byte, 1 = short, 2 = long) */
883 32, /* bitsize */
884 TRUE, /* pc_relative */
885 0, /* bitpos */
886 complain_overflow_dont,/* complain_on_overflow */
887 bfd_elf_generic_reloc, /* special_function */
888 "R_ARM_REL32_NOI", /* name */
889 FALSE, /* partial_inplace */
890 0xffffffff, /* src_mask */
891 0xffffffff, /* dst_mask */
892 FALSE), /* pcrel_offset */
7f266840 893
4962c51a
MS		 894 /* Group relocations. */
895
896 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
897 0, /* rightshift */
898 2, /* size (0 = byte, 1 = short, 2 = long) */
899 32, /* bitsize */
900 TRUE, /* pc_relative */
901 0, /* bitpos */
902 complain_overflow_dont,/* complain_on_overflow */
903 bfd_elf_generic_reloc, /* special_function */
904 "R_ARM_ALU_PC_G0_NC", /* name */
905 FALSE, /* partial_inplace */
906 0xffffffff, /* src_mask */
907 0xffffffff, /* dst_mask */
908 TRUE), /* pcrel_offset */
909
07d6d2b8 910 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 911 0, /* rightshift */
912 2, /* size (0 = byte, 1 = short, 2 = long) */
913 32, /* bitsize */
914 TRUE, /* pc_relative */
915 0, /* bitpos */
916 complain_overflow_dont,/* complain_on_overflow */
917 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 918 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 919 FALSE, /* partial_inplace */
920 0xffffffff, /* src_mask */
921 0xffffffff, /* dst_mask */
922 TRUE), /* pcrel_offset */
923
924 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
925 0, /* rightshift */
926 2, /* size (0 = byte, 1 = short, 2 = long) */
927 32, /* bitsize */
928 TRUE, /* pc_relative */
929 0, /* bitpos */
930 complain_overflow_dont,/* complain_on_overflow */
931 bfd_elf_generic_reloc, /* special_function */
932 "R_ARM_ALU_PC_G1_NC", /* name */
933 FALSE, /* partial_inplace */
934 0xffffffff, /* src_mask */
935 0xffffffff, /* dst_mask */
936 TRUE), /* pcrel_offset */
937
07d6d2b8 938 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 939 0, /* rightshift */
940 2, /* size (0 = byte, 1 = short, 2 = long) */
941 32, /* bitsize */
942 TRUE, /* pc_relative */
943 0, /* bitpos */
944 complain_overflow_dont,/* complain_on_overflow */
945 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 946 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 947 FALSE, /* partial_inplace */
948 0xffffffff, /* src_mask */
949 0xffffffff, /* dst_mask */
950 TRUE), /* pcrel_offset */
951
07d6d2b8 952 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 953 0, /* rightshift */
954 2, /* size (0 = byte, 1 = short, 2 = long) */
955 32, /* bitsize */
956 TRUE, /* pc_relative */
957 0, /* bitpos */
958 complain_overflow_dont,/* complain_on_overflow */
959 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 960 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 961 FALSE, /* partial_inplace */
962 0xffffffff, /* src_mask */
963 0xffffffff, /* dst_mask */
964 TRUE), /* pcrel_offset */
965
07d6d2b8 966 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 967 0, /* rightshift */
968 2, /* size (0 = byte, 1 = short, 2 = long) */
969 32, /* bitsize */
970 TRUE, /* pc_relative */
971 0, /* bitpos */
972 complain_overflow_dont,/* complain_on_overflow */
973 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 974 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 975 FALSE, /* partial_inplace */
976 0xffffffff, /* src_mask */
977 0xffffffff, /* dst_mask */
978 TRUE), /* pcrel_offset */
979
07d6d2b8 980 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 981 0, /* rightshift */
982 2, /* size (0 = byte, 1 = short, 2 = long) */
983 32, /* bitsize */
984 TRUE, /* pc_relative */
985 0, /* bitpos */
986 complain_overflow_dont,/* complain_on_overflow */
987 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 988 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 989 FALSE, /* partial_inplace */
990 0xffffffff, /* src_mask */
991 0xffffffff, /* dst_mask */
992 TRUE), /* pcrel_offset */
993
07d6d2b8 994 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 995 0, /* rightshift */
996 2, /* size (0 = byte, 1 = short, 2 = long) */
997 32, /* bitsize */
998 TRUE, /* pc_relative */
999 0, /* bitpos */
1000 complain_overflow_dont,/* complain_on_overflow */
1001 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1002 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1003 FALSE, /* partial_inplace */
1004 0xffffffff, /* src_mask */
1005 0xffffffff, /* dst_mask */
1006 TRUE), /* pcrel_offset */
1007
07d6d2b8 1008 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1009 0, /* rightshift */
1010 2, /* size (0 = byte, 1 = short, 2 = long) */
1011 32, /* bitsize */
1012 TRUE, /* pc_relative */
1013 0, /* bitpos */
1014 complain_overflow_dont,/* complain_on_overflow */
1015 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1016 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1017 FALSE, /* partial_inplace */
1018 0xffffffff, /* src_mask */
1019 0xffffffff, /* dst_mask */
1020 TRUE), /* pcrel_offset */
1021
07d6d2b8 1022 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1023 0, /* rightshift */
1024 2, /* size (0 = byte, 1 = short, 2 = long) */
1025 32, /* bitsize */
1026 TRUE, /* pc_relative */
1027 0, /* bitpos */
1028 complain_overflow_dont,/* complain_on_overflow */
1029 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1030 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1031 FALSE, /* partial_inplace */
1032 0xffffffff, /* src_mask */
1033 0xffffffff, /* dst_mask */
1034 TRUE), /* pcrel_offset */
1035
07d6d2b8 1036 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1037 0, /* rightshift */
1038 2, /* size (0 = byte, 1 = short, 2 = long) */
1039 32, /* bitsize */
1040 TRUE, /* pc_relative */
1041 0, /* bitpos */
1042 complain_overflow_dont,/* complain_on_overflow */
1043 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1044 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1045 FALSE, /* partial_inplace */
1046 0xffffffff, /* src_mask */
1047 0xffffffff, /* dst_mask */
1048 TRUE), /* pcrel_offset */
1049
07d6d2b8 1050 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1051 0, /* rightshift */
1052 2, /* size (0 = byte, 1 = short, 2 = long) */
1053 32, /* bitsize */
1054 TRUE, /* pc_relative */
1055 0, /* bitpos */
1056 complain_overflow_dont,/* complain_on_overflow */
1057 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1058 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1059 FALSE, /* partial_inplace */
1060 0xffffffff, /* src_mask */
1061 0xffffffff, /* dst_mask */
1062 TRUE), /* pcrel_offset */
1063
07d6d2b8 1064 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1065 0, /* rightshift */
1066 2, /* size (0 = byte, 1 = short, 2 = long) */
1067 32, /* bitsize */
1068 TRUE, /* pc_relative */
1069 0, /* bitpos */
1070 complain_overflow_dont,/* complain_on_overflow */
1071 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1072 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1073 FALSE, /* partial_inplace */
1074 0xffffffff, /* src_mask */
1075 0xffffffff, /* dst_mask */
1076 TRUE), /* pcrel_offset */
1077
07d6d2b8 1078 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1079 0, /* rightshift */
1080 2, /* size (0 = byte, 1 = short, 2 = long) */
1081 32, /* bitsize */
1082 TRUE, /* pc_relative */
1083 0, /* bitpos */
1084 complain_overflow_dont,/* complain_on_overflow */
1085 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1086 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1087 FALSE, /* partial_inplace */
1088 0xffffffff, /* src_mask */
1089 0xffffffff, /* dst_mask */
1090 TRUE), /* pcrel_offset */
1091
07d6d2b8 1092 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1093 0, /* rightshift */
1094 2, /* size (0 = byte, 1 = short, 2 = long) */
1095 32, /* bitsize */
1096 TRUE, /* pc_relative */
1097 0, /* bitpos */
1098 complain_overflow_dont,/* complain_on_overflow */
1099 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1100 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1101 FALSE, /* partial_inplace */
1102 0xffffffff, /* src_mask */
1103 0xffffffff, /* dst_mask */
1104 TRUE), /* pcrel_offset */
1105
07d6d2b8 1106 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1107 0, /* rightshift */
1108 2, /* size (0 = byte, 1 = short, 2 = long) */
1109 32, /* bitsize */
1110 TRUE, /* pc_relative */
1111 0, /* bitpos */
1112 complain_overflow_dont,/* complain_on_overflow */
1113 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1114 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1115 FALSE, /* partial_inplace */
1116 0xffffffff, /* src_mask */
1117 0xffffffff, /* dst_mask */
1118 TRUE), /* pcrel_offset */
1119
07d6d2b8 1120 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1121 0, /* rightshift */
1122 2, /* size (0 = byte, 1 = short, 2 = long) */
1123 32, /* bitsize */
1124 TRUE, /* pc_relative */
1125 0, /* bitpos */
1126 complain_overflow_dont,/* complain_on_overflow */
1127 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1128 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1129 FALSE, /* partial_inplace */
1130 0xffffffff, /* src_mask */
1131 0xffffffff, /* dst_mask */
1132 TRUE), /* pcrel_offset */
1133
07d6d2b8 1134 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1135 0, /* rightshift */
1136 2, /* size (0 = byte, 1 = short, 2 = long) */
1137 32, /* bitsize */
1138 TRUE, /* pc_relative */
1139 0, /* bitpos */
1140 complain_overflow_dont,/* complain_on_overflow */
1141 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1142 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1143 FALSE, /* partial_inplace */
1144 0xffffffff, /* src_mask */
1145 0xffffffff, /* dst_mask */
1146 TRUE), /* pcrel_offset */
1147
07d6d2b8 1148 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1149 0, /* rightshift */
1150 2, /* size (0 = byte, 1 = short, 2 = long) */
1151 32, /* bitsize */
1152 TRUE, /* pc_relative */
1153 0, /* bitpos */
1154 complain_overflow_dont,/* complain_on_overflow */
1155 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1156 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1157 FALSE, /* partial_inplace */
1158 0xffffffff, /* src_mask */
1159 0xffffffff, /* dst_mask */
1160 TRUE), /* pcrel_offset */
1161
07d6d2b8 1162 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1163 0, /* rightshift */
1164 2, /* size (0 = byte, 1 = short, 2 = long) */
1165 32, /* bitsize */
1166 TRUE, /* pc_relative */
1167 0, /* bitpos */
1168 complain_overflow_dont,/* complain_on_overflow */
1169 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1170 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1171 FALSE, /* partial_inplace */
1172 0xffffffff, /* src_mask */
1173 0xffffffff, /* dst_mask */
1174 TRUE), /* pcrel_offset */
1175
07d6d2b8 1176 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1177 0, /* rightshift */
1178 2, /* size (0 = byte, 1 = short, 2 = long) */
1179 32, /* bitsize */
1180 TRUE, /* pc_relative */
1181 0, /* bitpos */
1182 complain_overflow_dont,/* complain_on_overflow */
1183 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1184 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1185 FALSE, /* partial_inplace */
1186 0xffffffff, /* src_mask */
1187 0xffffffff, /* dst_mask */
1188 TRUE), /* pcrel_offset */
1189
07d6d2b8 1190 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1191 0, /* rightshift */
1192 2, /* size (0 = byte, 1 = short, 2 = long) */
1193 32, /* bitsize */
1194 TRUE, /* pc_relative */
1195 0, /* bitpos */
1196 complain_overflow_dont,/* complain_on_overflow */
1197 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1198 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1199 FALSE, /* partial_inplace */
1200 0xffffffff, /* src_mask */
1201 0xffffffff, /* dst_mask */
1202 TRUE), /* pcrel_offset */
1203
07d6d2b8 1204 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1205 0, /* rightshift */
1206 2, /* size (0 = byte, 1 = short, 2 = long) */
1207 32, /* bitsize */
1208 TRUE, /* pc_relative */
1209 0, /* bitpos */
1210 complain_overflow_dont,/* complain_on_overflow */
1211 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1212 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1213 FALSE, /* partial_inplace */
1214 0xffffffff, /* src_mask */
1215 0xffffffff, /* dst_mask */
1216 TRUE), /* pcrel_offset */
1217
07d6d2b8 1218 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1219 0, /* rightshift */
1220 2, /* size (0 = byte, 1 = short, 2 = long) */
1221 32, /* bitsize */
1222 TRUE, /* pc_relative */
1223 0, /* bitpos */
1224 complain_overflow_dont,/* complain_on_overflow */
1225 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1226 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1227 FALSE, /* partial_inplace */
1228 0xffffffff, /* src_mask */
1229 0xffffffff, /* dst_mask */
1230 TRUE), /* pcrel_offset */
1231
07d6d2b8 1232 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1233 0, /* rightshift */
1234 2, /* size (0 = byte, 1 = short, 2 = long) */
1235 32, /* bitsize */
1236 TRUE, /* pc_relative */
1237 0, /* bitpos */
1238 complain_overflow_dont,/* complain_on_overflow */
1239 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1240 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1241 FALSE, /* partial_inplace */
1242 0xffffffff, /* src_mask */
1243 0xffffffff, /* dst_mask */
1244 TRUE), /* pcrel_offset */
1245
07d6d2b8 1246 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1247 0, /* rightshift */
1248 2, /* size (0 = byte, 1 = short, 2 = long) */
1249 32, /* bitsize */
1250 TRUE, /* pc_relative */
1251 0, /* bitpos */
1252 complain_overflow_dont,/* complain_on_overflow */
1253 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1254 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1255 FALSE, /* partial_inplace */
1256 0xffffffff, /* src_mask */
1257 0xffffffff, /* dst_mask */
1258 TRUE), /* pcrel_offset */
1259
07d6d2b8 1260 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1261 0, /* rightshift */
1262 2, /* size (0 = byte, 1 = short, 2 = long) */
1263 32, /* bitsize */
1264 TRUE, /* pc_relative */
1265 0, /* bitpos */
1266 complain_overflow_dont,/* complain_on_overflow */
1267 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1268 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1269 FALSE, /* partial_inplace */
1270 0xffffffff, /* src_mask */
1271 0xffffffff, /* dst_mask */
1272 TRUE), /* pcrel_offset */
1273
1274 /* End of group relocations. */
c19d1205 1275
c19d1205
ZW		 1276 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1277 0, /* rightshift */
1278 2, /* size (0 = byte, 1 = short, 2 = long) */
1279 16, /* bitsize */
1280 FALSE, /* pc_relative */
1281 0, /* bitpos */
1282 complain_overflow_dont,/* complain_on_overflow */
1283 bfd_elf_generic_reloc, /* special_function */
1284 "R_ARM_MOVW_BREL_NC", /* name */
1285 FALSE, /* partial_inplace */
1286 0x0000ffff, /* src_mask */
1287 0x0000ffff, /* dst_mask */
1288 FALSE), /* pcrel_offset */
1289
1290 HOWTO (R_ARM_MOVT_BREL, /* type */
1291 0, /* rightshift */
1292 2, /* size (0 = byte, 1 = short, 2 = long) */
1293 16, /* bitsize */
1294 FALSE, /* pc_relative */
1295 0, /* bitpos */
1296 complain_overflow_bitfield,/* complain_on_overflow */
1297 bfd_elf_generic_reloc, /* special_function */
1298 "R_ARM_MOVT_BREL", /* name */
1299 FALSE, /* partial_inplace */
1300 0x0000ffff, /* src_mask */
1301 0x0000ffff, /* dst_mask */
1302 FALSE), /* pcrel_offset */
1303
1304 HOWTO (R_ARM_MOVW_BREL, /* type */
1305 0, /* rightshift */
1306 2, /* size (0 = byte, 1 = short, 2 = long) */
1307 16, /* bitsize */
1308 FALSE, /* pc_relative */
1309 0, /* bitpos */
1310 complain_overflow_dont,/* complain_on_overflow */
1311 bfd_elf_generic_reloc, /* special_function */
1312 "R_ARM_MOVW_BREL", /* name */
1313 FALSE, /* partial_inplace */
1314 0x0000ffff, /* src_mask */
1315 0x0000ffff, /* dst_mask */
1316 FALSE), /* pcrel_offset */
1317
1318 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1319 0, /* rightshift */
1320 2, /* size (0 = byte, 1 = short, 2 = long) */
1321 16, /* bitsize */
1322 FALSE, /* pc_relative */
1323 0, /* bitpos */
1324 complain_overflow_dont,/* complain_on_overflow */
1325 bfd_elf_generic_reloc, /* special_function */
1326 "R_ARM_THM_MOVW_BREL_NC",/* name */
1327 FALSE, /* partial_inplace */
1328 0x040f70ff, /* src_mask */
1329 0x040f70ff, /* dst_mask */
1330 FALSE), /* pcrel_offset */
1331
1332 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1333 0, /* rightshift */
1334 2, /* size (0 = byte, 1 = short, 2 = long) */
1335 16, /* bitsize */
1336 FALSE, /* pc_relative */
1337 0, /* bitpos */
1338 complain_overflow_bitfield,/* complain_on_overflow */
1339 bfd_elf_generic_reloc, /* special_function */
1340 "R_ARM_THM_MOVT_BREL", /* name */
1341 FALSE, /* partial_inplace */
1342 0x040f70ff, /* src_mask */
1343 0x040f70ff, /* dst_mask */
1344 FALSE), /* pcrel_offset */
1345
1346 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1347 0, /* rightshift */
1348 2, /* size (0 = byte, 1 = short, 2 = long) */
1349 16, /* bitsize */
1350 FALSE, /* pc_relative */
1351 0, /* bitpos */
1352 complain_overflow_dont,/* complain_on_overflow */
1353 bfd_elf_generic_reloc, /* special_function */
1354 "R_ARM_THM_MOVW_BREL", /* name */
1355 FALSE, /* partial_inplace */
1356 0x040f70ff, /* src_mask */
1357 0x040f70ff, /* dst_mask */
1358 FALSE), /* pcrel_offset */
1359
0855e32b
NS		 1360 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1361 0, /* rightshift */
1362 2, /* size (0 = byte, 1 = short, 2 = long) */
1363 32, /* bitsize */
1364 FALSE, /* pc_relative */
1365 0, /* bitpos */
1366 complain_overflow_bitfield,/* complain_on_overflow */
1367 NULL, /* special_function */
1368 "R_ARM_TLS_GOTDESC", /* name */
1369 TRUE, /* partial_inplace */
1370 0xffffffff, /* src_mask */
1371 0xffffffff, /* dst_mask */
1372 FALSE), /* pcrel_offset */
1373
1374 HOWTO (R_ARM_TLS_CALL, /* type */
1375 0, /* rightshift */
1376 2, /* size (0 = byte, 1 = short, 2 = long) */
1377 24, /* bitsize */
1378 FALSE, /* pc_relative */
1379 0, /* bitpos */
1380 complain_overflow_dont,/* complain_on_overflow */
1381 bfd_elf_generic_reloc, /* special_function */
1382 "R_ARM_TLS_CALL", /* name */
1383 FALSE, /* partial_inplace */
1384 0x00ffffff, /* src_mask */
1385 0x00ffffff, /* dst_mask */
1386 FALSE), /* pcrel_offset */
1387
1388 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1389 0, /* rightshift */
1390 2, /* size (0 = byte, 1 = short, 2 = long) */
1391 0, /* bitsize */
1392 FALSE, /* pc_relative */
1393 0, /* bitpos */
1394 complain_overflow_bitfield,/* complain_on_overflow */
1395 bfd_elf_generic_reloc, /* special_function */
1396 "R_ARM_TLS_DESCSEQ", /* name */
1397 FALSE, /* partial_inplace */
1398 0x00000000, /* src_mask */
1399 0x00000000, /* dst_mask */
1400 FALSE), /* pcrel_offset */
1401
1402 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1403 0, /* rightshift */
1404 2, /* size (0 = byte, 1 = short, 2 = long) */
1405 24, /* bitsize */
1406 FALSE, /* pc_relative */
1407 0, /* bitpos */
1408 complain_overflow_dont,/* complain_on_overflow */
1409 bfd_elf_generic_reloc, /* special_function */
1410 "R_ARM_THM_TLS_CALL", /* name */
1411 FALSE, /* partial_inplace */
1412 0x07ff07ff, /* src_mask */
1413 0x07ff07ff, /* dst_mask */
1414 FALSE), /* pcrel_offset */
c19d1205
ZW		 1415
1416 HOWTO (R_ARM_PLT32_ABS, /* type */
1417 0, /* rightshift */
1418 2, /* size (0 = byte, 1 = short, 2 = long) */
1419 32, /* bitsize */
1420 FALSE, /* pc_relative */
1421 0, /* bitpos */
1422 complain_overflow_dont,/* complain_on_overflow */
1423 bfd_elf_generic_reloc, /* special_function */
1424 "R_ARM_PLT32_ABS", /* name */
1425 FALSE, /* partial_inplace */
1426 0xffffffff, /* src_mask */
1427 0xffffffff, /* dst_mask */
1428 FALSE), /* pcrel_offset */
1429
1430 HOWTO (R_ARM_GOT_ABS, /* type */
1431 0, /* rightshift */
1432 2, /* size (0 = byte, 1 = short, 2 = long) */
1433 32, /* bitsize */
1434 FALSE, /* pc_relative */
1435 0, /* bitpos */
1436 complain_overflow_dont,/* complain_on_overflow */
1437 bfd_elf_generic_reloc, /* special_function */
1438 "R_ARM_GOT_ABS", /* name */
1439 FALSE, /* partial_inplace */
1440 0xffffffff, /* src_mask */
1441 0xffffffff, /* dst_mask */
1442 FALSE), /* pcrel_offset */
1443
1444 HOWTO (R_ARM_GOT_PREL, /* type */
1445 0, /* rightshift */
1446 2, /* size (0 = byte, 1 = short, 2 = long) */
1447 32, /* bitsize */
1448 TRUE, /* pc_relative */
1449 0, /* bitpos */
1450 complain_overflow_dont, /* complain_on_overflow */
1451 bfd_elf_generic_reloc, /* special_function */
1452 "R_ARM_GOT_PREL", /* name */
1453 FALSE, /* partial_inplace */
1454 0xffffffff, /* src_mask */
1455 0xffffffff, /* dst_mask */
1456 TRUE), /* pcrel_offset */
1457
1458 HOWTO (R_ARM_GOT_BREL12, /* type */
1459 0, /* rightshift */
1460 2, /* size (0 = byte, 1 = short, 2 = long) */
1461 12, /* bitsize */
1462 FALSE, /* pc_relative */
1463 0, /* bitpos */
1464 complain_overflow_bitfield,/* complain_on_overflow */
1465 bfd_elf_generic_reloc, /* special_function */
1466 "R_ARM_GOT_BREL12", /* name */
1467 FALSE, /* partial_inplace */
1468 0x00000fff, /* src_mask */
1469 0x00000fff, /* dst_mask */
1470 FALSE), /* pcrel_offset */
1471
1472 HOWTO (R_ARM_GOTOFF12, /* type */
1473 0, /* rightshift */
1474 2, /* size (0 = byte, 1 = short, 2 = long) */
1475 12, /* bitsize */
1476 FALSE, /* pc_relative */
1477 0, /* bitpos */
1478 complain_overflow_bitfield,/* complain_on_overflow */
1479 bfd_elf_generic_reloc, /* special_function */
1480 "R_ARM_GOTOFF12", /* name */
1481 FALSE, /* partial_inplace */
1482 0x00000fff, /* src_mask */
1483 0x00000fff, /* dst_mask */
1484 FALSE), /* pcrel_offset */
1485
07d6d2b8 1486 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1487
1488 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1489 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1490 0, /* rightshift */
1491 2, /* size (0 = byte, 1 = short, 2 = long) */
1492 0, /* bitsize */
1493 FALSE, /* pc_relative */
1494 0, /* bitpos */
99059e56 1495 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1496 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1497 "R_ARM_GNU_VTENTRY", /* name */
1498 FALSE, /* partial_inplace */
1499 0, /* src_mask */
1500 0, /* dst_mask */
1501 FALSE), /* pcrel_offset */
c19d1205
ZW		 1502
1503 /* GNU extension to record C++ vtable hierarchy */
1504 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1505 0, /* rightshift */
1506 2, /* size (0 = byte, 1 = short, 2 = long) */
1507 0, /* bitsize */
1508 FALSE, /* pc_relative */
1509 0, /* bitpos */
99059e56 1510 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1511 NULL, /* special_function */
99059e56 1512 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1513 FALSE, /* partial_inplace */
1514 0, /* src_mask */
1515 0, /* dst_mask */
1516 FALSE), /* pcrel_offset */
c19d1205
ZW		 1517
1518 HOWTO (R_ARM_THM_JUMP11, /* type */
1519 1, /* rightshift */
1520 1, /* size (0 = byte, 1 = short, 2 = long) */
1521 11, /* bitsize */
1522 TRUE, /* pc_relative */
1523 0, /* bitpos */
1524 complain_overflow_signed, /* complain_on_overflow */
1525 bfd_elf_generic_reloc, /* special_function */
1526 "R_ARM_THM_JUMP11", /* name */
1527 FALSE, /* partial_inplace */
1528 0x000007ff, /* src_mask */
1529 0x000007ff, /* dst_mask */
1530 TRUE), /* pcrel_offset */
1531
1532 HOWTO (R_ARM_THM_JUMP8, /* type */
1533 1, /* rightshift */
1534 1, /* size (0 = byte, 1 = short, 2 = long) */
1535 8, /* bitsize */
1536 TRUE, /* pc_relative */
1537 0, /* bitpos */
1538 complain_overflow_signed, /* complain_on_overflow */
1539 bfd_elf_generic_reloc, /* special_function */
1540 "R_ARM_THM_JUMP8", /* name */
1541 FALSE, /* partial_inplace */
1542 0x000000ff, /* src_mask */
1543 0x000000ff, /* dst_mask */
1544 TRUE), /* pcrel_offset */
ba93b8ac 1545
c19d1205
ZW		 1546 /* TLS relocations */
1547 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1548 0, /* rightshift */
1549 2, /* size (0 = byte, 1 = short, 2 = long) */
1550 32, /* bitsize */
1551 FALSE, /* pc_relative */
1552 0, /* bitpos */
99059e56
RM		 1553 complain_overflow_bitfield,/* complain_on_overflow */
1554 NULL, /* special_function */
1555 "R_ARM_TLS_GD32", /* name */
1556 TRUE, /* partial_inplace */
1557 0xffffffff, /* src_mask */
1558 0xffffffff, /* dst_mask */
07d6d2b8 1559 FALSE), /* pcrel_offset */
ba93b8ac 1560
ba93b8ac 1561 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1562 0, /* rightshift */
1563 2, /* size (0 = byte, 1 = short, 2 = long) */
1564 32, /* bitsize */
1565 FALSE, /* pc_relative */
1566 0, /* bitpos */
99059e56
RM		 1567 complain_overflow_bitfield,/* complain_on_overflow */
1568 bfd_elf_generic_reloc, /* special_function */
1569 "R_ARM_TLS_LDM32", /* name */
1570 TRUE, /* partial_inplace */
1571 0xffffffff, /* src_mask */
1572 0xffffffff, /* dst_mask */
07d6d2b8 1573 FALSE), /* pcrel_offset */
ba93b8ac 1574
c19d1205 1575 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1576 0, /* rightshift */
1577 2, /* size (0 = byte, 1 = short, 2 = long) */
1578 32, /* bitsize */
1579 FALSE, /* pc_relative */
1580 0, /* bitpos */
99059e56
RM		 1581 complain_overflow_bitfield,/* complain_on_overflow */
1582 bfd_elf_generic_reloc, /* special_function */
1583 "R_ARM_TLS_LDO32", /* name */
1584 TRUE, /* partial_inplace */
1585 0xffffffff, /* src_mask */
1586 0xffffffff, /* dst_mask */
07d6d2b8 1587 FALSE), /* pcrel_offset */
ba93b8ac 1588
ba93b8ac 1589 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1590 0, /* rightshift */
1591 2, /* size (0 = byte, 1 = short, 2 = long) */
1592 32, /* bitsize */
1593 FALSE, /* pc_relative */
1594 0, /* bitpos */
99059e56
RM		 1595 complain_overflow_bitfield,/* complain_on_overflow */
1596 NULL, /* special_function */
1597 "R_ARM_TLS_IE32", /* name */
1598 TRUE, /* partial_inplace */
1599 0xffffffff, /* src_mask */
1600 0xffffffff, /* dst_mask */
07d6d2b8 1601 FALSE), /* pcrel_offset */
7f266840 1602
c19d1205 1603 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1604 0, /* rightshift */
1605 2, /* size (0 = byte, 1 = short, 2 = long) */
1606 32, /* bitsize */
1607 FALSE, /* pc_relative */
1608 0, /* bitpos */
99059e56 1609 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1610 NULL, /* special_function */
99059e56
RM		 1611 "R_ARM_TLS_LE32", /* name */
1612 TRUE, /* partial_inplace */
1613 0xffffffff, /* src_mask */
1614 0xffffffff, /* dst_mask */
07d6d2b8 1615 FALSE), /* pcrel_offset */
7f266840 1616
c19d1205
ZW		 1617 HOWTO (R_ARM_TLS_LDO12, /* type */
1618 0, /* rightshift */
1619 2, /* size (0 = byte, 1 = short, 2 = long) */
1620 12, /* bitsize */
1621 FALSE, /* pc_relative */
7f266840 1622 0, /* bitpos */
c19d1205 1623 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1624 bfd_elf_generic_reloc, /* special_function */
c19d1205 1625 "R_ARM_TLS_LDO12", /* name */
7f266840 1626 FALSE, /* partial_inplace */
c19d1205
ZW		 1627 0x00000fff, /* src_mask */
1628 0x00000fff, /* dst_mask */
1629 FALSE), /* pcrel_offset */
7f266840 1630
c19d1205
ZW		 1631 HOWTO (R_ARM_TLS_LE12, /* type */
1632 0, /* rightshift */
1633 2, /* size (0 = byte, 1 = short, 2 = long) */
1634 12, /* bitsize */
1635 FALSE, /* pc_relative */
7f266840 1636 0, /* bitpos */
c19d1205 1637 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1638 bfd_elf_generic_reloc, /* special_function */
c19d1205 1639 "R_ARM_TLS_LE12", /* name */
7f266840 1640 FALSE, /* partial_inplace */
c19d1205
ZW		 1641 0x00000fff, /* src_mask */
1642 0x00000fff, /* dst_mask */
1643 FALSE), /* pcrel_offset */
7f266840 1644
c19d1205 1645 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1646 0, /* rightshift */
1647 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1648 12, /* bitsize */
1649 FALSE, /* pc_relative */
7f266840 1650 0, /* bitpos */
c19d1205 1651 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1652 bfd_elf_generic_reloc, /* special_function */
c19d1205 1653 "R_ARM_TLS_IE12GP", /* name */
7f266840 1654 FALSE, /* partial_inplace */
c19d1205
ZW		 1655 0x00000fff, /* src_mask */
1656 0x00000fff, /* dst_mask */
1657 FALSE), /* pcrel_offset */
0855e32b 1658
34e77a92 1659 /* 112-127 private relocations. */
0855e32b
NS		 1660 EMPTY_HOWTO (112),
1661 EMPTY_HOWTO (113),
1662 EMPTY_HOWTO (114),
1663 EMPTY_HOWTO (115),
1664 EMPTY_HOWTO (116),
1665 EMPTY_HOWTO (117),
1666 EMPTY_HOWTO (118),
1667 EMPTY_HOWTO (119),
1668 EMPTY_HOWTO (120),
1669 EMPTY_HOWTO (121),
1670 EMPTY_HOWTO (122),
1671 EMPTY_HOWTO (123),
1672 EMPTY_HOWTO (124),
1673 EMPTY_HOWTO (125),
1674 EMPTY_HOWTO (126),
1675 EMPTY_HOWTO (127),
34e77a92
RS		 1676
1677 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1678 EMPTY_HOWTO (128),
1679
1680 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1681 0, /* rightshift */
1682 1, /* size (0 = byte, 1 = short, 2 = long) */
1683 0, /* bitsize */
1684 FALSE, /* pc_relative */
1685 0, /* bitpos */
1686 complain_overflow_bitfield,/* complain_on_overflow */
1687 bfd_elf_generic_reloc, /* special_function */
1688 "R_ARM_THM_TLS_DESCSEQ",/* name */
1689 FALSE, /* partial_inplace */
1690 0x00000000, /* src_mask */
1691 0x00000000, /* dst_mask */
1692 FALSE), /* pcrel_offset */
72d98d16
MG		 1693 EMPTY_HOWTO (130),
1694 EMPTY_HOWTO (131),
1695 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1696 0, /* rightshift. */
1697 1, /* size (0 = byte, 1 = short, 2 = long). */
1698 16, /* bitsize. */
1699 FALSE, /* pc_relative. */
1700 0, /* bitpos. */
1701 complain_overflow_bitfield,/* complain_on_overflow. */
1702 bfd_elf_generic_reloc, /* special_function. */
1703 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1704 FALSE, /* partial_inplace. */
1705 0x00000000, /* src_mask. */
1706 0x00000000, /* dst_mask. */
1707 FALSE), /* pcrel_offset. */
1708 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1709 0, /* rightshift. */
1710 1, /* size (0 = byte, 1 = short, 2 = long). */
1711 16, /* bitsize. */
1712 FALSE, /* pc_relative. */
1713 0, /* bitpos. */
1714 complain_overflow_bitfield,/* complain_on_overflow. */
1715 bfd_elf_generic_reloc, /* special_function. */
1716 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1717 FALSE, /* partial_inplace. */
1718 0x00000000, /* src_mask. */
1719 0x00000000, /* dst_mask. */
1720 FALSE), /* pcrel_offset. */
1721 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1722 0, /* rightshift. */
1723 1, /* size (0 = byte, 1 = short, 2 = long). */
1724 16, /* bitsize. */
1725 FALSE, /* pc_relative. */
1726 0, /* bitpos. */
1727 complain_overflow_bitfield,/* complain_on_overflow. */
1728 bfd_elf_generic_reloc, /* special_function. */
1729 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1730 FALSE, /* partial_inplace. */
1731 0x00000000, /* src_mask. */
1732 0x00000000, /* dst_mask. */
1733 FALSE), /* pcrel_offset. */
1734 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1735 0, /* rightshift. */
1736 1, /* size (0 = byte, 1 = short, 2 = long). */
1737 16, /* bitsize. */
1738 FALSE, /* pc_relative. */
1739 0, /* bitpos. */
1740 complain_overflow_bitfield,/* complain_on_overflow. */
1741 bfd_elf_generic_reloc, /* special_function. */
1742 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1743 FALSE, /* partial_inplace. */
1744 0x00000000, /* src_mask. */
1745 0x00000000, /* dst_mask. */
1746 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1747 /* Relocations for Armv8.1-M Mainline. */
1748 HOWTO (R_ARM_THM_BF16, /* type. */
1749 0, /* rightshift. */
1750 1, /* size (0 = byte, 1 = short, 2 = long). */
1751 16, /* bitsize. */
1752 TRUE, /* pc_relative. */
1753 0, /* bitpos. */
1754 complain_overflow_dont,/* do not complain_on_overflow. */
1755 bfd_elf_generic_reloc, /* special_function. */
1756 "R_ARM_THM_BF16", /* name. */
1757 FALSE, /* partial_inplace. */
1758 0x001f0ffe, /* src_mask. */
1759 0x001f0ffe, /* dst_mask. */
1760 TRUE), /* pcrel_offset. */
1889da70
AV		 1761 HOWTO (R_ARM_THM_BF12, /* type. */
1762 0, /* rightshift. */
1763 1, /* size (0 = byte, 1 = short, 2 = long). */
1764 12, /* bitsize. */
1765 TRUE, /* pc_relative. */
1766 0, /* bitpos. */
1767 complain_overflow_dont,/* do not complain_on_overflow. */
1768 bfd_elf_generic_reloc, /* special_function. */
1769 "R_ARM_THM_BF12", /* name. */
1770 FALSE, /* partial_inplace. */
1771 0x00010ffe, /* src_mask. */
1772 0x00010ffe, /* dst_mask. */
1773 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1774 HOWTO (R_ARM_THM_BF18, /* type. */
1775 0, /* rightshift. */
1776 1, /* size (0 = byte, 1 = short, 2 = long). */
1777 18, /* bitsize. */
1778 TRUE, /* pc_relative. */
1779 0, /* bitpos. */
1780 complain_overflow_dont,/* do not complain_on_overflow. */
1781 bfd_elf_generic_reloc, /* special_function. */
1782 "R_ARM_THM_BF18", /* name. */
1783 FALSE, /* partial_inplace. */
1784 0x007f0ffe, /* src_mask. */
1785 0x007f0ffe, /* dst_mask. */
1786 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1787};
1788
34e77a92 1789/* 160 onwards: */
5c5a4843 1790static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1791{
1792 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1793 0, /* rightshift */
1794 2, /* size (0 = byte, 1 = short, 2 = long) */
1795 32, /* bitsize */
1796 FALSE, /* pc_relative */
1797 0, /* bitpos */
99059e56
RM		 1798 complain_overflow_bitfield,/* complain_on_overflow */
1799 bfd_elf_generic_reloc, /* special_function */
1800 "R_ARM_IRELATIVE", /* name */
1801 TRUE, /* partial_inplace */
1802 0xffffffff, /* src_mask */
1803 0xffffffff, /* dst_mask */
188fd7ae
CL		 1804 FALSE), /* pcrel_offset */
1805 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1806 0, /* rightshift */
1807 2, /* size (0 = byte, 1 = short, 2 = long) */
1808 32, /* bitsize */
1809 FALSE, /* pc_relative */
1810 0, /* bitpos */
1811 complain_overflow_bitfield,/* complain_on_overflow */
1812 bfd_elf_generic_reloc, /* special_function */
1813 "R_ARM_GOTFUNCDESC", /* name */
1814 FALSE, /* partial_inplace */
1815 0, /* src_mask */
1816 0xffffffff, /* dst_mask */
1817 FALSE), /* pcrel_offset */
1818 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1819 0, /* rightshift */
1820 2, /* size (0 = byte, 1 = short, 2 = long) */
1821 32, /* bitsize */
1822 FALSE, /* pc_relative */
1823 0, /* bitpos */
1824 complain_overflow_bitfield,/* complain_on_overflow */
1825 bfd_elf_generic_reloc, /* special_function */
1826 "R_ARM_GOTOFFFUNCDESC",/* name */
1827 FALSE, /* partial_inplace */
1828 0, /* src_mask */
1829 0xffffffff, /* dst_mask */
1830 FALSE), /* pcrel_offset */
1831 HOWTO (R_ARM_FUNCDESC, /* type */
1832 0, /* rightshift */
1833 2, /* size (0 = byte, 1 = short, 2 = long) */
1834 32, /* bitsize */
1835 FALSE, /* pc_relative */
1836 0, /* bitpos */
1837 complain_overflow_bitfield,/* complain_on_overflow */
1838 bfd_elf_generic_reloc, /* special_function */
1839 "R_ARM_FUNCDESC", /* name */
1840 FALSE, /* partial_inplace */
1841 0, /* src_mask */
1842 0xffffffff, /* dst_mask */
1843 FALSE), /* pcrel_offset */
1844 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1845 0, /* rightshift */
1846 2, /* size (0 = byte, 1 = short, 2 = long) */
1847 64, /* bitsize */
1848 FALSE, /* pc_relative */
1849 0, /* bitpos */
1850 complain_overflow_bitfield,/* complain_on_overflow */
1851 bfd_elf_generic_reloc, /* special_function */
1852 "R_ARM_FUNCDESC_VALUE",/* name */
1853 FALSE, /* partial_inplace */
1854 0, /* src_mask */
1855 0xffffffff, /* dst_mask */
1856 FALSE), /* pcrel_offset */
5c5a4843
CL		 1857 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1858 0, /* rightshift */
1859 2, /* size (0 = byte, 1 = short, 2 = long) */
1860 32, /* bitsize */
1861 FALSE, /* pc_relative */
1862 0, /* bitpos */
1863 complain_overflow_bitfield,/* complain_on_overflow */
1864 bfd_elf_generic_reloc, /* special_function */
1865 "R_ARM_TLS_GD32_FDPIC",/* name */
1866 FALSE, /* partial_inplace */
1867 0, /* src_mask */
1868 0xffffffff, /* dst_mask */
1869 FALSE), /* pcrel_offset */
1870 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1871 0, /* rightshift */
1872 2, /* size (0 = byte, 1 = short, 2 = long) */
1873 32, /* bitsize */
1874 FALSE, /* pc_relative */
1875 0, /* bitpos */
1876 complain_overflow_bitfield,/* complain_on_overflow */
1877 bfd_elf_generic_reloc, /* special_function */
1878 "R_ARM_TLS_LDM32_FDPIC",/* name */
1879 FALSE, /* partial_inplace */
1880 0, /* src_mask */
1881 0xffffffff, /* dst_mask */
1882 FALSE), /* pcrel_offset */
1883 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1884 0, /* rightshift */
1885 2, /* size (0 = byte, 1 = short, 2 = long) */
1886 32, /* bitsize */
1887 FALSE, /* pc_relative */
1888 0, /* bitpos */
1889 complain_overflow_bitfield,/* complain_on_overflow */
1890 bfd_elf_generic_reloc, /* special_function */
1891 "R_ARM_TLS_IE32_FDPIC",/* name */
1892 FALSE, /* partial_inplace */
1893 0, /* src_mask */
1894 0xffffffff, /* dst_mask */
1895 FALSE), /* pcrel_offset */
34e77a92 1896};
c19d1205 1897
34e77a92
RS		 1898/* 249-255 extended, currently unused, relocations: */
1899static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1900{
1901 HOWTO (R_ARM_RREL32, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RREL32", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RABS32, /* type */
1916 0, /* rightshift */
1917 0, /* size (0 = byte, 1 = short, 2 = long) */
1918 0, /* bitsize */
1919 FALSE, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RABS32", /* name */
1924 FALSE, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 FALSE), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RPC24, /* type */
1930 0, /* rightshift */
1931 0, /* size (0 = byte, 1 = short, 2 = long) */
1932 0, /* bitsize */
1933 FALSE, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RPC24", /* name */
1938 FALSE, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 FALSE), /* pcrel_offset */
1942
1943 HOWTO (R_ARM_RBASE, /* type */
1944 0, /* rightshift */
1945 0, /* size (0 = byte, 1 = short, 2 = long) */
1946 0, /* bitsize */
1947 FALSE, /* pc_relative */
1948 0, /* bitpos */
1949 complain_overflow_dont,/* complain_on_overflow */
1950 bfd_elf_generic_reloc, /* special_function */
1951 "R_ARM_RBASE", /* name */
1952 FALSE, /* partial_inplace */
1953 0, /* src_mask */
1954 0, /* dst_mask */
1955 FALSE) /* pcrel_offset */
1956};
1957
1958static reloc_howto_type *
1959elf32_arm_howto_from_type (unsigned int r_type)
1960{
906e58ca 1961 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1962 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1963
188fd7ae
CL		 1964 if (r_type >= R_ARM_IRELATIVE
1965 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1966 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1967
c19d1205 1968 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1969 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1970 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1971
c19d1205 1972 return NULL;
7f266840
DJ		 1973}
1974
f3185997
NC		 1975static bfd_boolean
1976elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1977 Elf_Internal_Rela * elf_reloc)
1978{
1979 unsigned int r_type;
1980
1981 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1982 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1983 {
1984 /* xgettext:c-format */
1985 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1986 abfd, r_type);
1987 bfd_set_error (bfd_error_bad_value);
1988 return FALSE;
1989 }
1990 return TRUE;
7f266840
DJ		 1991}
1992
1993struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1996 unsigned char elf_reloc_val;
7f266840
DJ		 1997 };
1998
1999/* All entries in this list must also be present in elf32_arm_howto_table. */
2000static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
2001 {
07d6d2b8 2002 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2003 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2004 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2005 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2006 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2007 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2008 {BFD_RELOC_32, R_ARM_ABS32},
2009 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2010 {BFD_RELOC_8, R_ARM_ABS8},
2011 {BFD_RELOC_16, R_ARM_ABS16},
2012 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2013 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2014 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2018 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2019 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2020 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2021 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2022 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2023 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2024 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2025 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2026 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2027 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2028 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2029 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2030 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2031 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2032 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2033 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2034 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2035 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2038 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2039 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2040 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2041 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2042 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2043 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2044 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2045 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2046 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2047 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2048 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2049 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2050 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2051 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2052 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2053 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2054 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2055 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2056 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2057 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2058 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2059 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2060 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2061 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2062 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2064 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2065 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2066 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2068 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2069 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2070 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2071 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2072 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2073 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2074 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2075 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2076 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2077 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2078 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2079 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2080 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2082 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2083 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2084 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2085 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2086 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2087 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2088 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2089 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2090 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2091 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2092 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2093 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2094 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2097 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2098 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2100 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2101 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2102 };
2103
2104static reloc_howto_type *
f1c71a59
ZW		 2105elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2106 bfd_reloc_code_real_type code)
7f266840
DJ		 2107{
2108 unsigned int i;
8029a119 2109
906e58ca 2110 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2111 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2112 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2113
c19d1205 2114 return NULL;
7f266840
DJ		 2115}
2116
157090f7
AM		 2117static reloc_howto_type *
2118elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2119 const char *r_name)
2120{
2121 unsigned int i;
2122
906e58ca 2123 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2124 if (elf32_arm_howto_table_1[i].name != NULL
2125 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2126 return &elf32_arm_howto_table_1[i];
2127
906e58ca 2128 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2129 if (elf32_arm_howto_table_2[i].name != NULL
2130 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2131 return &elf32_arm_howto_table_2[i];
2132
34e77a92
RS		 2133 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2134 if (elf32_arm_howto_table_3[i].name != NULL
2135 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2136 return &elf32_arm_howto_table_3[i];
2137
157090f7
AM		 2138 return NULL;
2139}
2140
906e58ca
NC		 2141/* Support for core dump NOTE sections. */
2142
7f266840 2143static bfd_boolean
f1c71a59 2144elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2145{
2146 int offset;
2147 size_t size;
2148
2149 switch (note->descsz)
2150 {
2151 default:
2152 return FALSE;
2153
8029a119 2154 case 148: /* Linux/ARM 32-bit. */
7f266840 2155 /* pr_cursig */
228e534f 2156 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2157
2158 /* pr_pid */
228e534f 2159 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2160
2161 /* pr_reg */
2162 offset = 72;
2163 size = 72;
2164
2165 break;
2166 }
2167
2168 /* Make a ".reg/999" section. */
2169 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2170 size, note->descpos + offset);
2171}
2172
2173static bfd_boolean
f1c71a59 2174elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2175{
2176 switch (note->descsz)
2177 {
2178 default:
2179 return FALSE;
2180
8029a119 2181 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2182 elf_tdata (abfd)->core->pid
4395ee08 2183 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2184 elf_tdata (abfd)->core->program
7f266840 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2186 elf_tdata (abfd)->core->command
7f266840
DJ		 2187 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2188 }
2189
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
7f266840 2193 {
228e534f 2194 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2195 int n = strlen (command);
2196
2197 if (0 < n && command[n - 1] == ' ')
2198 command[n - 1] = '\0';
2199 }
2200
2201 return TRUE;
2202}
2203
1f20dca5
UW		 2204static char *
2205elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2206 int note_type, ...)
2207{
2208 switch (note_type)
2209 {
2210 default:
2211 return NULL;
2212
2213 case NT_PRPSINFO:
2214 {
602f1657 2215 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2216 va_list ap;
2217
2218 va_start (ap, note_type);
2219 memset (data, 0, sizeof (data));
2220 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2221#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2222 DIAGNOSTIC_PUSH;
be3e27bb 2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
95da9854
L		 2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228#endif
1f20dca5 2229 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2230#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2231 DIAGNOSTIC_POP;
fe75810f 2232#endif
1f20dca5
UW		 2233 va_end (ap);
2234
2235 return elfcore_write_note (abfd, buf, bufsiz,
2236 "CORE", note_type, data, sizeof (data));
2237 }
2238
2239 case NT_PRSTATUS:
2240 {
2241 char data[148];
2242 va_list ap;
2243 long pid;
2244 int cursig;
2245 const void *greg;
2246
2247 va_start (ap, note_type);
2248 memset (data, 0, sizeof (data));
2249 pid = va_arg (ap, long);
2250 bfd_put_32 (abfd, pid, data + 24);
2251 cursig = va_arg (ap, int);
2252 bfd_put_16 (abfd, cursig, data + 12);
2253 greg = va_arg (ap, const void *);
2254 memcpy (data + 72, greg, 72);
2255 va_end (ap);
2256
2257 return elfcore_write_note (abfd, buf, bufsiz,
2258 "CORE", note_type, data, sizeof (data));
2259 }
2260 }
2261}
2262
07d6d2b8
AM		 2263#define TARGET_LITTLE_SYM arm_elf32_le_vec
2264#define TARGET_LITTLE_NAME "elf32-littlearm"
2265#define TARGET_BIG_SYM arm_elf32_be_vec
2266#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2267
2268#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2270#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2271
252b5132
RH		 2272typedef unsigned long int insn32;
2273typedef unsigned short int insn16;
2274
3a4a14e9
PB		 2275/* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
57e8b36a 2277#define INTERWORK_FLAG(abfd) \
3a4a14e9 2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2281
252b5132
RH		 2282/* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
9b485d32 2285 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2286#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2287#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2288
2289#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2290#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2291
c7b8f16e
JB		 2292#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2293#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2294
a504d23a
LA		 2295#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2296#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2297
845b51d6
PB		 2298#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2299#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2300
7413f23f
DJ		 2301#define STUB_ENTRY_NAME "__%s_veneer"
2302
4ba2ef8f
TP		 2303#define CMSE_PREFIX "__acle_se_"
2304
4d83e8d9
CL		 2305#define CMSE_STUB_NAME ".gnu.sgstubs"
2306
252b5132
RH		 2307/* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2309#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2310
cb10292c
CL		 2311/* FDPIC default stack size. */
2312#define DEFAULT_STACK_SIZE 0x8000
2313
0855e32b 2314static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2315{
2316 0xe08e0000, /* add r0, lr, r0 */
2317 0xe5901004, /* ldr r1, [r0,#4] */
2318 0xe12fff11, /* bx r1 */
2319};
0855e32b
NS		 2320
2321static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2322{
2323 0xe52d2004, /* push {r2} */
2324 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2325 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2326 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2327 0xe081100f, /* 2: add r1, pc */
2328 0xe12fff12, /* bx r2 */
2329 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2330 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2331 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2332};
0855e32b 2333
b4e87f2c
TC		 2334/* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2338
7801f98f
CL		 2339/* ARM FDPIC PLT entry. */
2340/* The last 5 words contain PLT lazy fragment code and data. */
2341static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2342 {
2343 0xe59fc008, /* ldr r12, .L1 */
2344 0xe08cc009, /* add r12, r12, r9 */
2345 0xe59c9004, /* ldr r9, [r12, #4] */
2346 0xe59cf000, /* ldr pc, [r12] */
2347 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2348 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2349 0xe51fc00c, /* ldr r12, [pc, #-12] */
2350 0xe92d1000, /* push {r12} */
2351 0xe599c004, /* ldr r12, [r9, #4] */
2352 0xe599f000, /* ldr pc, [r9] */
2353 };
2354
59029f57
CL		 2355/* Thumb FDPIC PLT entry. */
2356/* The last 5 words contain PLT lazy fragment code and data. */
2357static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2358 {
2359 0xc00cf8df, /* ldr.w r12, .L1 */
2360 0x0c09eb0c, /* add.w r12, r12, r9 */
2361 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2362 0xf000f8dc, /* ldr.w pc, [r12] */
2363 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2364 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2365 0xc008f85f, /* ldr.w r12, .L2 */
2366 0xcd04f84d, /* push {r12} */
2367 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2368 0xf000f8d9, /* ldr.w pc, [r9] */
2369 };
2370
5e681ec4
PB		 2371#ifdef FOUR_WORD_PLT
2372
252b5132
RH		 2373/* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
59f2c4e7 2375 called before the relocation has been set up calls the dynamic
9b485d32 2376 linker first. */
e5a52504 2377static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2378{
2379 0xe52de004, /* str lr, [sp, #-4]! */
2380 0xe59fe010, /* ldr lr, [pc, #16] */
2381 0xe08fe00e, /* add lr, pc, lr */
2382 0xe5bef008, /* ldr pc, [lr, #8]! */
2383};
5e681ec4
PB		 2384
2385/* Subsequent entries in a procedure linkage table look like
2386 this. */
e5a52504 2387static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2388{
2389 0xe28fc600, /* add ip, pc, #NN */
2390 0xe28cca00, /* add ip, ip, #NN */
2391 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2392 0x00000000, /* unused */
2393};
5e681ec4 2394
eed94f8f 2395#else /* not FOUR_WORD_PLT */
5e681ec4 2396
5e681ec4
PB		 2397/* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
e5a52504 2401static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2402{
07d6d2b8
AM		 2403 0xe52de004, /* str lr, [sp, #-4]! */
2404 0xe59fe004, /* ldr lr, [pc, #4] */
2405 0xe08fe00e, /* add lr, pc, lr */
2406 0xe5bef008, /* ldr pc, [lr, #8]! */
2407 0x00000000, /* &GOT[0] - . */
b38cadfb 2408};
252b5132 2409
1db37fe6
YG		 2410/* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2412static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2413{
2414 0xe28fc600, /* add ip, pc, #0xNN00000 */
2415 0xe28cca00, /* add ip, ip, #0xNN000 */
2416 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2417};
5e681ec4 2418
1db37fe6
YG		 2419/* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2421static const bfd_vma elf32_arm_plt_entry_long [] =
2422{
07d6d2b8
AM		 2423 0xe28fc200, /* add ip, pc, #0xN0000000 */
2424 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2425 0xe28cca00, /* add ip, ip, #0xNN000 */
2426 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2427};
2428
2429static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2430
eed94f8f
NC		 2431#endif /* not FOUR_WORD_PLT */
2432
2433/* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2436static const bfd_vma elf32_thumb2_plt0_entry [] =
2437{
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2440 0xf8dfb500, /* push {lr} */
2441 0x44fee008, /* ldr.w lr, [pc, #8] */
2442 /* add lr, pc */
eed94f8f 2443 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2444 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2445};
2446
2447/* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2449static const bfd_vma elf32_thumb2_plt_entry [] =
2450{
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2453 0x0c00f240, /* movw ip, #0xNNNN */
2454 0x0c00f2c0, /* movt ip, #0xNNNN */
2455 0xf8dc44fc, /* add ip, pc */
b4e87f2c
TC		 2456 0xe7fdf000 /* ldr.w pc, [ip] */
2457 /* b .-2 */
eed94f8f 2458};
252b5132 2459
00a97672
RS		 2460/* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2462static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2463{
07d6d2b8
AM		 2464 0xe52dc008, /* str ip,[sp,#-8]! */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe59cf008, /* ldr pc,[ip,#8] */
2467 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2468};
00a97672
RS		 2469
2470/* The format of subsequent entries in a VxWorks executable. */
2471static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2472{
07d6d2b8
AM		 2473 0xe59fc000, /* ldr ip,[pc] */
2474 0xe59cf000, /* ldr pc,[ip] */
2475 0x00000000, /* .long @got */
2476 0xe59fc000, /* ldr ip,[pc] */
2477 0xea000000, /* b _PLT */
2478 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2479};
00a97672
RS		 2480
2481/* The format of entries in a VxWorks shared library. */
2482static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2483{
07d6d2b8
AM		 2484 0xe59fc000, /* ldr ip,[pc] */
2485 0xe79cf009, /* ldr pc,[ip,r9] */
2486 0x00000000, /* .long @got */
2487 0xe59fc000, /* ldr ip,[pc] */
2488 0xe599f008, /* ldr pc,[r9,#8] */
2489 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2490};
00a97672 2491
b7693d02
DJ		 2492/* An initial stub used if the PLT entry is referenced from Thumb code. */
2493#define PLT_THUMB_STUB_SIZE 4
2494static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2495{
2496 0x4778, /* bx pc */
b4e87f2c 2497 0xe7fd /* b .-2 */
b38cadfb 2498};
b7693d02 2499
e5a52504
MM		 2500/* The entries in a PLT when using a DLL-based target with multiple
2501 address spaces. */
906e58ca 2502static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2503{
07d6d2b8
AM		 2504 0xe51ff004, /* ldr pc, [pc, #-4] */
2505 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2506};
2507
2508/* The first entry in a procedure linkage table looks like
2509 this. It is set up so that any shared library function that is
2510 called before the relocation has been set up calls the dynamic
2511 linker first. */
2512static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2513{
2514 /* First bundle: */
2515 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2516 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2517 0xe08cc00f, /* add ip, ip, pc */
2518 0xe52dc008, /* str ip, [sp, #-8]! */
2519 /* Second bundle: */
edccdf7c
RM		 2520 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2521 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2522 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2523 0xe12fff1c, /* bx ip */
b38cadfb 2524 /* Third bundle: */
edccdf7c
RM		 2525 0xe320f000, /* nop */
2526 0xe320f000, /* nop */
2527 0xe320f000, /* nop */
b38cadfb
NC		 2528 /* .Lplt_tail: */
2529 0xe50dc004, /* str ip, [sp, #-4] */
2530 /* Fourth bundle: */
edccdf7c
RM		 2531 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2532 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2533 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2534 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2535};
2536#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2537
2538/* Subsequent entries in a procedure linkage table look like this. */
2539static const bfd_vma elf32_arm_nacl_plt_entry [] =
2540{
2541 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2542 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2543 0xe08cc00f, /* add ip, ip, pc */
2544 0xea000000, /* b .Lplt_tail */
2545};
e5a52504 2546
906e58ca
NC		 2547#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2548#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2549#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2550#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2551#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2552#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2553#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2554#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2555
461a49ca 2556enum stub_insn_type
b38cadfb
NC		 2557{
2558 THUMB16_TYPE = 1,
2559 THUMB32_TYPE,
2560 ARM_TYPE,
2561 DATA_TYPE
2562};
461a49ca 2563
48229727
JB		 2564#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2565/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2566 is inserted in arm_build_one_stub(). */
2567#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2568#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2569#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2570#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2571#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2572#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2573#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2574#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2575
2576typedef struct
2577{
07d6d2b8 2578 bfd_vma data;
b38cadfb 2579 enum stub_insn_type type;
07d6d2b8
AM		 2580 unsigned int r_type;
2581 int reloc_addend;
461a49ca
DJ		 2582} insn_sequence;
2583
b4e87f2c
TC		 2584/* See note [Thumb nop sequence] when adding a veneer. */
2585
fea2b4d6
CL		 2586/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2587 to reach the stub if necessary. */
461a49ca 2588static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2589{
07d6d2b8 2590 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2591 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2592};
906e58ca 2593
fea2b4d6
CL		 2594/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2595 available. */
461a49ca 2596static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2597{
07d6d2b8
AM		 2598 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2599 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2600 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2601};
906e58ca 2602
d3626fb0 2603/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2604static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2605{
07d6d2b8
AM		 2606 THUMB16_INSN (0xb401), /* push {r0} */
2607 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2608 THUMB16_INSN (0x4684), /* mov ip, r0 */
2609 THUMB16_INSN (0xbc01), /* pop {r0} */
2610 THUMB16_INSN (0x4760), /* bx ip */
2611 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2612 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2613};
906e58ca 2614
80c135e5
TP		 2615/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2616static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2617{
07d6d2b8 2618 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2619 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2620};
2621
d5a67c02
AV		 2622/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2623 M-profile architectures. */
2624static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2625{
2626 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2627 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2628 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2629};
2630
d3626fb0
CL		 2631/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2632 allowed. */
2633static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2634{
07d6d2b8 2635 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2636 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2637 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2638 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2639 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2640};
d3626fb0 2641
fea2b4d6
CL		 2642/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2643 available. */
461a49ca 2644static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2645{
07d6d2b8 2646 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2647 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2648 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2649 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2650};
906e58ca 2651
fea2b4d6
CL		 2652/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2653 one, when the destination is close enough. */
461a49ca 2654static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2655{
07d6d2b8 2656 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2657 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2658 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2659};
c820be07 2660
cf3eccff 2661/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2662 blx to reach the stub if necessary. */
cf3eccff 2663static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2666 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2667 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2668};
906e58ca 2669
cf3eccff
DJ		 2670/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2671 blx to reach the stub if necessary. We can not add into pc;
2672 it is not guaranteed to mode switch (different in ARMv6 and
2673 ARMv7). */
2674static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2677 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2678 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2679 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2680};
cf3eccff 2681
ebe24dd4
CL		 2682/* V4T ARM -> ARM long branch stub, PIC. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2684{
07d6d2b8
AM		 2685 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2686 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2687 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2688 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2689};
ebe24dd4
CL		 2690
2691/* V4T Thumb -> ARM long branch stub, PIC. */
2692static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2693{
07d6d2b8 2694 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2695 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2696 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2697 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2698 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2699};
ebe24dd4 2700
d3626fb0
CL		 2701/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2702 architectures. */
ebe24dd4 2703static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2704{
07d6d2b8
AM		 2705 THUMB16_INSN (0xb401), /* push {r0} */
2706 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2707 THUMB16_INSN (0x46fc), /* mov ip, pc */
2708 THUMB16_INSN (0x4484), /* add ip, r0 */
2709 THUMB16_INSN (0xbc01), /* pop {r0} */
2710 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2711 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2712};
ebe24dd4 2713
d3626fb0
CL		 2714/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2715 allowed. */
2716static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2717{
07d6d2b8 2718 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2719 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2720 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2721 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2722 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2723 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2724};
d3626fb0 2725
0855e32b
NS		 2726/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2727 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2728static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2729{
07d6d2b8
AM		 2730 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2731 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2732 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2733};
2734
2735/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2736 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2737static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2738{
07d6d2b8 2739 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2740 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2741 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2742 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2743 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2744};
2745
7a89b94e
NC		 2746/* NaCl ARM -> ARM long branch stub. */
2747static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2748{
2749 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2750 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2751 ARM_INSN (0xe12fff1c), /* bx ip */
2752 ARM_INSN (0xe320f000), /* nop */
2753 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2754 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2755 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2756 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2757};
2758
2759/* NaCl ARM -> ARM long branch stub, PIC. */
2760static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2761{
2762 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2763 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2764 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2765 ARM_INSN (0xe12fff1c), /* bx ip */
2766 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2767 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2768 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2769 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2770};
2771
4ba2ef8f
TP		 2772/* Stub used for transition to secure state (aka SG veneer). */
2773static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2774{
2775 THUMB32_INSN (0xe97fe97f), /* sg. */
2776 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2777};
2778
7a89b94e 2779
48229727
JB		 2780/* Cortex-A8 erratum-workaround stubs. */
2781
2782/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2783 can't use a conditional branch to reach this stub). */
2784
2785static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2786{
07d6d2b8 2787 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2788 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2789 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2790};
48229727
JB		 2791
2792/* Stub used for b.w and bl.w instructions. */
2793
2794static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2795{
2796 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2797};
48229727
JB		 2798
2799static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2800{
2801 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2802};
48229727
JB		 2803
2804/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2805 instruction (which switches to ARM mode) to point to this stub. Jump to the
2806 real destination using an ARM-mode branch. */
2807
2808static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2809{
2810 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2811};
48229727 2812
9553db3c
NC		 2813/* For each section group there can be a specially created linker section
2814 to hold the stubs for that group. The name of the stub section is based
2815 upon the name of another section within that group with the suffix below
2816 applied.
2817
2818 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2819 create what appeared to be a linker stub section when it actually
2820 contained user code/data. For example, consider this fragment:
b38cadfb 2821
9553db3c
NC		 2822 const char * stubborn_problems[] = { "np" };
2823
2824 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2825 section called:
2826
2827 .data.rel.local.stubborn_problems
2828
2829 This then causes problems in arm32_arm_build_stubs() as it triggers:
2830
2831 // Ignore non-stub sections.
2832 if (!strstr (stub_sec->name, STUB_SUFFIX))
2833 continue;
2834
2835 And so the section would be ignored instead of being processed. Hence
2836 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2837 C identifier. */
2838#define STUB_SUFFIX ".__stub"
906e58ca 2839
738a79f6
CL		 2840/* One entry per long/short branch stub defined above. */
2841#define DEF_STUBS \
2842 DEF_STUB(long_branch_any_any) \
2843 DEF_STUB(long_branch_v4t_arm_thumb) \
2844 DEF_STUB(long_branch_thumb_only) \
2845 DEF_STUB(long_branch_v4t_thumb_thumb) \
2846 DEF_STUB(long_branch_v4t_thumb_arm) \
2847 DEF_STUB(short_branch_v4t_thumb_arm) \
2848 DEF_STUB(long_branch_any_arm_pic) \
2849 DEF_STUB(long_branch_any_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2851 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2852 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2853 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2854 DEF_STUB(long_branch_any_tls_pic) \
2855 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2856 DEF_STUB(long_branch_arm_nacl) \
2857 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2858 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2859 DEF_STUB(a8_veneer_b_cond) \
2860 DEF_STUB(a8_veneer_b) \
2861 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2862 DEF_STUB(a8_veneer_blx) \
2863 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2864 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2865
2866#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2867enum elf32_arm_stub_type
2868{
906e58ca 2869 arm_stub_none,
738a79f6 2870 DEF_STUBS
4f4faa4d 2871 max_stub_type
738a79f6
CL		 2872};
2873#undef DEF_STUB
2874
8d9d9490
TP		 2875/* Note the first a8_veneer type. */
2876const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2877
738a79f6
CL		 2878typedef struct
2879{
d3ce72d0 2880 const insn_sequence* template_sequence;
738a79f6
CL		 2881 int template_size;
2882} stub_def;
2883
2884#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2885static const stub_def stub_definitions[] =
2886{
738a79f6
CL		 2887 {NULL, 0},
2888 DEF_STUBS
906e58ca
NC		 2889};
2890
2891struct elf32_arm_stub_hash_entry
2892{
2893 /* Base hash table entry structure. */
2894 struct bfd_hash_entry root;
2895
2896 /* The stub section. */
2897 asection *stub_sec;
2898
2899 /* Offset within stub_sec of the beginning of this stub. */
2900 bfd_vma stub_offset;
2901
2902 /* Given the symbol's value and its section we can determine its final
2903 value when building the stubs (so the stub knows where to jump). */
2904 bfd_vma target_value;
2905 asection *target_section;
2906
8d9d9490
TP		 2907 /* Same as above but for the source of the branch to the stub. Used for
2908 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2909 such, source section does not need to be recorded since Cortex-A8 erratum
2910 workaround stubs are only generated when both source and target are in the
2911 same section. */
2912 bfd_vma source_value;
48229727
JB		 2913
2914 /* The instruction which caused this stub to be generated (only valid for
2915 Cortex-A8 erratum workaround stubs at present). */
2916 unsigned long orig_insn;
2917
461a49ca 2918 /* The stub type. */
906e58ca 2919 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2920 /* Its encoding size in bytes. */
2921 int stub_size;
2922 /* Its template. */
2923 const insn_sequence *stub_template;
2924 /* The size of the template (number of entries). */
2925 int stub_template_size;
906e58ca
NC		 2926
2927 /* The symbol table entry, if any, that this was derived from. */
2928 struct elf32_arm_link_hash_entry *h;
2929
35fc36a8
RS		 2930 /* Type of branch. */
2931 enum arm_st_branch_type branch_type;
906e58ca
NC		 2932
2933 /* Where this stub is being called from, or, in the case of combined
2934 stub sections, the first input section in the group. */
2935 asection *id_sec;
7413f23f
DJ		 2936
2937 /* The name for the local symbol at the start of this stub. The
2938 stub name in the hash table has to be unique; this does not, so
2939 it can be friendlier. */
2940 char *output_name;
906e58ca
NC		 2941};
2942
e489d0ae
PB		 2943/* Used to build a map of a section. This is required for mixed-endian
2944 code/data. */
2945
2946typedef struct elf32_elf_section_map
2947{
2948 bfd_vma vma;
2949 char type;
2950}
2951elf32_arm_section_map;
2952
c7b8f16e
JB		 2953/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2954
2955typedef enum
2956{
2957 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2958 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2959 VFP11_ERRATUM_ARM_VENEER,
2960 VFP11_ERRATUM_THUMB_VENEER
2961}
2962elf32_vfp11_erratum_type;
2963
2964typedef struct elf32_vfp11_erratum_list
2965{
2966 struct elf32_vfp11_erratum_list *next;
2967 bfd_vma vma;
2968 union
2969 {
2970 struct
2971 {
2972 struct elf32_vfp11_erratum_list *veneer;
2973 unsigned int vfp_insn;
2974 } b;
2975 struct
2976 {
2977 struct elf32_vfp11_erratum_list *branch;
2978 unsigned int id;
2979 } v;
2980 } u;
2981 elf32_vfp11_erratum_type type;
2982}
2983elf32_vfp11_erratum_list;
2984
a504d23a
LA		 2985/* Information about a STM32L4XX erratum veneer, or a branch to such a
2986 veneer. */
2987typedef enum
2988{
2989 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2990 STM32L4XX_ERRATUM_VENEER
2991}
2992elf32_stm32l4xx_erratum_type;
2993
2994typedef struct elf32_stm32l4xx_erratum_list
2995{
2996 struct elf32_stm32l4xx_erratum_list *next;
2997 bfd_vma vma;
2998 union
2999 {
3000 struct
3001 {
3002 struct elf32_stm32l4xx_erratum_list *veneer;
3003 unsigned int insn;
3004 } b;
3005 struct
3006 {
3007 struct elf32_stm32l4xx_erratum_list *branch;
3008 unsigned int id;
3009 } v;
3010 } u;
3011 elf32_stm32l4xx_erratum_type type;
3012}
3013elf32_stm32l4xx_erratum_list;
3014
2468f9c9
PB		 3015typedef enum
3016{
3017 DELETE_EXIDX_ENTRY,
3018 INSERT_EXIDX_CANTUNWIND_AT_END
3019}
3020arm_unwind_edit_type;
3021
3022/* A (sorted) list of edits to apply to an unwind table. */
3023typedef struct arm_unwind_table_edit
3024{
3025 arm_unwind_edit_type type;
3026 /* Note: we sometimes want to insert an unwind entry corresponding to a
3027 section different from the one we're currently writing out, so record the
3028 (text) section this edit relates to here. */
3029 asection *linked_section;
3030 unsigned int index;
3031 struct arm_unwind_table_edit *next;
3032}
3033arm_unwind_table_edit;
3034
8e3de13a 3035typedef struct _arm_elf_section_data
e489d0ae 3036{
2468f9c9 3037 /* Information about mapping symbols. */
e489d0ae 3038 struct bfd_elf_section_data elf;
8e3de13a 3039 unsigned int mapcount;
c7b8f16e 3040 unsigned int mapsize;
e489d0ae 3041 elf32_arm_section_map *map;
2468f9c9 3042 /* Information about CPU errata. */
c7b8f16e
JB		 3043 unsigned int erratumcount;
3044 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3045 unsigned int stm32l4xx_erratumcount;
3046 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3047 unsigned int additional_reloc_count;
2468f9c9
PB		 3048 /* Information about unwind tables. */
3049 union
3050 {
3051 /* Unwind info attached to a text section. */
3052 struct
3053 {
3054 asection *arm_exidx_sec;
3055 } text;
3056
3057 /* Unwind info attached to an .ARM.exidx section. */
3058 struct
3059 {
3060 arm_unwind_table_edit *unwind_edit_list;
3061 arm_unwind_table_edit *unwind_edit_tail;
3062 } exidx;
3063 } u;
8e3de13a
NC		 3064}
3065_arm_elf_section_data;
e489d0ae
PB		 3066
3067#define elf32_arm_section_data(sec) \
8e3de13a 3068 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3069
48229727
JB		 3070/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3071 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3072 so may be created multiple times: we use an array of these entries whilst
3073 relaxing which we can refresh easily, then create stubs for each potentially
3074 erratum-triggering instruction once we've settled on a solution. */
3075
b38cadfb
NC		 3076struct a8_erratum_fix
3077{
48229727
JB		 3078 bfd *input_bfd;
3079 asection *section;
3080 bfd_vma offset;
8d9d9490 3081 bfd_vma target_offset;
48229727
JB		 3082 unsigned long orig_insn;
3083 char *stub_name;
3084 enum elf32_arm_stub_type stub_type;
35fc36a8 3085 enum arm_st_branch_type branch_type;
48229727
JB		 3086};
3087
3088/* A table of relocs applied to branches which might trigger Cortex-A8
3089 erratum. */
3090
b38cadfb
NC		 3091struct a8_erratum_reloc
3092{
48229727
JB		 3093 bfd_vma from;
3094 bfd_vma destination;
92750f34
DJ		 3095 struct elf32_arm_link_hash_entry *hash;
3096 const char *sym_name;
48229727 3097 unsigned int r_type;
35fc36a8 3098 enum arm_st_branch_type branch_type;
48229727
JB		 3099 bfd_boolean non_a8_stub;
3100};
3101
ba93b8ac
DJ		 3102/* The size of the thread control block. */
3103#define TCB_SIZE 8
3104
34e77a92
RS		 3105/* ARM-specific information about a PLT entry, over and above the usual
3106 gotplt_union. */
b38cadfb
NC		 3107struct arm_plt_info
3108{
34e77a92
RS		 3109 /* We reference count Thumb references to a PLT entry separately,
3110 so that we can emit the Thumb trampoline only if needed. */
3111 bfd_signed_vma thumb_refcount;
3112
3113 /* Some references from Thumb code may be eliminated by BL->BLX
3114 conversion, so record them separately. */
3115 bfd_signed_vma maybe_thumb_refcount;
3116
3117 /* How many of the recorded PLT accesses were from non-call relocations.
3118 This information is useful when deciding whether anything takes the
3119 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3120 non-call references to the function should resolve directly to the
3121 real runtime target. */
3122 unsigned int noncall_refcount;
3123
3124 /* Since PLT entries have variable size if the Thumb prologue is
3125 used, we need to record the index into .got.plt instead of
3126 recomputing it from the PLT offset. */
3127 bfd_signed_vma got_offset;
3128};
3129
3130/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3131struct arm_local_iplt_info
3132{
34e77a92
RS		 3133 /* The information that is usually found in the generic ELF part of
3134 the hash table entry. */
3135 union gotplt_union root;
3136
3137 /* The information that is usually found in the ARM-specific part of
3138 the hash table entry. */
3139 struct arm_plt_info arm;
3140
3141 /* A list of all potential dynamic relocations against this symbol. */
3142 struct elf_dyn_relocs *dyn_relocs;
3143};
3144
e8b09b87
CL		 3145/* Structure to handle FDPIC support for local functions. */
3146struct fdpic_local {
3147 unsigned int funcdesc_cnt;
3148 unsigned int gotofffuncdesc_cnt;
3149 int funcdesc_offset;
3150};
3151
0ffa91dd 3152struct elf_arm_obj_tdata
ba93b8ac
DJ		 3153{
3154 struct elf_obj_tdata root;
3155
3156 /* tls_type for each local got entry. */
3157 char *local_got_tls_type;
ee065d83 3158
0855e32b
NS		 3159 /* GOTPLT entries for TLS descriptors. */
3160 bfd_vma *local_tlsdesc_gotent;
3161
34e77a92
RS		 3162 /* Information for local symbols that need entries in .iplt. */
3163 struct arm_local_iplt_info **local_iplt;
3164
bf21ed78
MS		 3165 /* Zero to warn when linking objects with incompatible enum sizes. */
3166 int no_enum_size_warning;
a9dc9481
JM		 3167
3168 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3169 int no_wchar_size_warning;
e8b09b87
CL		 3170
3171 /* Maintains FDPIC counters and funcdesc info. */
3172 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3173};
3174
0ffa91dd
NC		 3175#define elf_arm_tdata(bfd) \
3176 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3177
0ffa91dd
NC		 3178#define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3180
0855e32b
NS		 3181#define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3183
34e77a92
RS		 3184#define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3186
e8b09b87
CL		 3187#define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3189
0ffa91dd
NC		 3190#define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
4dfe6ac6 3193 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3194
3195static bfd_boolean
3196elf32_arm_mkobject (bfd *abfd)
3197{
0ffa91dd 3198 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3199 ARM_ELF_DATA);
ba93b8ac
DJ		 3200}
3201
ba93b8ac
DJ		 3202#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3203
e8b09b87
CL		 3204/* Structure to handle FDPIC support for extern functions. */
3205struct fdpic_global {
3206 unsigned int gotofffuncdesc_cnt;
3207 unsigned int gotfuncdesc_cnt;
3208 unsigned int funcdesc_cnt;
3209 int funcdesc_offset;
3210 int gotfuncdesc_offset;
3211};
3212
ba96a88f 3213/* Arm ELF linker hash entry. */
252b5132 3214struct elf32_arm_link_hash_entry
b38cadfb
NC		 3215{
3216 struct elf_link_hash_entry root;
252b5132 3217
b38cadfb
NC		 3218 /* Track dynamic relocs copied for this symbol. */
3219 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3220
b38cadfb
NC		 3221 /* ARM-specific PLT information. */
3222 struct arm_plt_info plt;
ba93b8ac
DJ		 3223
3224#define GOT_UNKNOWN 0
3225#define GOT_NORMAL 1
3226#define GOT_TLS_GD 2
3227#define GOT_TLS_IE 4
0855e32b
NS		 3228#define GOT_TLS_GDESC 8
3229#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3230 unsigned int tls_type : 8;
34e77a92 3231
b38cadfb
NC		 3232 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3233 unsigned int is_iplt : 1;
34e77a92 3234
b38cadfb 3235 unsigned int unused : 23;
a4fd1a8e 3236
b38cadfb
NC		 3237 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3238 starting at the end of the jump table. */
3239 bfd_vma tlsdesc_got;
0855e32b 3240
b38cadfb
NC		 3241 /* The symbol marking the real symbol location for exported thumb
3242 symbols with Arm stubs. */
3243 struct elf_link_hash_entry *export_glue;
906e58ca 3244
b38cadfb 3245 /* A pointer to the most recently used stub hash entry against this
8029a119 3246 symbol. */
b38cadfb 3247 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3248
3249 /* Counter for FDPIC relocations against this symbol. */
3250 struct fdpic_global fdpic_cnts;
b38cadfb 3251};
252b5132 3252
252b5132 3253/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3254#define elf32_arm_link_hash_traverse(table, func, info) \
3255 (elf_link_hash_traverse \
3256 (&(table)->root, \
b7693d02 3257 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3258 (info)))
3259
3260/* Get the ARM elf linker hash table from a link_info structure. */
3261#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3262 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3263 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3264
906e58ca
NC		 3265#define arm_stub_hash_lookup(table, string, create, copy) \
3266 ((struct elf32_arm_stub_hash_entry *) \
3267 bfd_hash_lookup ((table), (string), (create), (copy)))
3268
21d799b5
NC		 3269/* Array to keep track of which stub sections have been created, and
3270 information on stub grouping. */
3271struct map_stub
3272{
3273 /* This is the section to which stubs in the group will be
3274 attached. */
3275 asection *link_sec;
3276 /* The stub section. */
3277 asection *stub_sec;
3278};
3279
0855e32b
NS		 3280#define elf32_arm_compute_jump_table_size(htab) \
3281 ((htab)->next_tls_desc_index * 4)
3282
9b485d32 3283/* ARM ELF linker hash table. */
252b5132 3284struct elf32_arm_link_hash_table
906e58ca
NC		 3285{
3286 /* The main hash table. */
3287 struct elf_link_hash_table root;
252b5132 3288
906e58ca
NC		 3289 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3290 bfd_size_type thumb_glue_size;
252b5132 3291
906e58ca
NC		 3292 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3293 bfd_size_type arm_glue_size;
252b5132 3294
906e58ca
NC		 3295 /* The size in bytes of section containing the ARMv4 BX veneers. */
3296 bfd_size_type bx_glue_size;
845b51d6 3297
906e58ca
NC		 3298 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3299 veneer has been populated. */
3300 bfd_vma bx_glue_offset[15];
845b51d6 3301
906e58ca
NC		 3302 /* The size in bytes of the section containing glue for VFP11 erratum
3303 veneers. */
3304 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3305
a504d23a
LA		 3306 /* The size in bytes of the section containing glue for STM32L4XX erratum
3307 veneers. */
3308 bfd_size_type stm32l4xx_erratum_glue_size;
3309
48229727
JB		 3310 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3311 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3312 elf32_arm_write_section(). */
3313 struct a8_erratum_fix *a8_erratum_fixes;
3314 unsigned int num_a8_erratum_fixes;
3315
906e58ca
NC		 3316 /* An arbitrary input BFD chosen to hold the glue sections. */
3317 bfd * bfd_of_glue_owner;
ba96a88f 3318
906e58ca
NC		 3319 /* Nonzero to output a BE8 image. */
3320 int byteswap_code;
e489d0ae 3321
906e58ca
NC		 3322 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3323 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3324 int target1_is_rel;
9c504268 3325
906e58ca
NC		 3326 /* The relocation to use for R_ARM_TARGET2 relocations. */
3327 int target2_reloc;
eb043451 3328
906e58ca
NC		 3329 /* 0 = Ignore R_ARM_V4BX.
3330 1 = Convert BX to MOV PC.
3331 2 = Generate v4 interworing stubs. */
3332 int fix_v4bx;
319850b4 3333
48229727
JB		 3334 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3335 int fix_cortex_a8;
3336
2de70689
MGD		 3337 /* Whether we should fix the ARM1176 BLX immediate issue. */
3338 int fix_arm1176;
3339
906e58ca
NC		 3340 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3341 int use_blx;
33bfe774 3342
906e58ca
NC		 3343 /* What sort of code sequences we should look for which may trigger the
3344 VFP11 denorm erratum. */
3345 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3346
906e58ca
NC		 3347 /* Global counter for the number of fixes we have emitted. */
3348 int num_vfp11_fixes;
c7b8f16e 3349
a504d23a
LA		 3350 /* What sort of code sequences we should look for which may trigger the
3351 STM32L4XX erratum. */
3352 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3353
3354 /* Global counter for the number of fixes we have emitted. */
3355 int num_stm32l4xx_fixes;
3356
906e58ca
NC		 3357 /* Nonzero to force PIC branch veneers. */
3358 int pic_veneer;
27e55c4d 3359
906e58ca
NC		 3360 /* The number of bytes in the initial entry in the PLT. */
3361 bfd_size_type plt_header_size;
e5a52504 3362
906e58ca
NC		 3363 /* The number of bytes in the subsequent PLT etries. */
3364 bfd_size_type plt_entry_size;
e5a52504 3365
906e58ca
NC		 3366 /* True if the target system is VxWorks. */
3367 int vxworks_p;
00a97672 3368
906e58ca
NC		 3369 /* True if the target system is Symbian OS. */
3370 int symbian_p;
e5a52504 3371
b38cadfb
NC		 3372 /* True if the target system is Native Client. */
3373 int nacl_p;
3374
906e58ca 3375 /* True if the target uses REL relocations. */
f3185997 3376 bfd_boolean use_rel;
4e7fd91e 3377
54ddd295
TP		 3378 /* Nonzero if import library must be a secure gateway import library
3379 as per ARMv8-M Security Extensions. */
3380 int cmse_implib;
3381
0955507f
TP		 3382 /* The import library whose symbols' address must remain stable in
3383 the import library generated. */
3384 bfd *in_implib_bfd;
3385
0855e32b
NS		 3386 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3387 bfd_vma next_tls_desc_index;
3388
3389 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3390 bfd_vma num_tls_desc;
3391
906e58ca
NC		 3392 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3393 asection *srelplt2;
00a97672 3394
0855e32b
NS		 3395 /* The offset into splt of the PLT entry for the TLS descriptor
3396 resolver. Special values are 0, if not necessary (or not found
3397 to be necessary yet), and -1 if needed but not determined
3398 yet. */
3399 bfd_vma dt_tlsdesc_plt;
3400
3401 /* The offset into sgot of the GOT entry used by the PLT entry
3402 above. */
b38cadfb 3403 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3404
3405 /* Offset in .plt section of tls_arm_trampoline. */
3406 bfd_vma tls_trampoline;
3407
5c5a4843 3408 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3409 union
3410 {
3411 bfd_signed_vma refcount;
3412 bfd_vma offset;
3413 } tls_ldm_got;
b7693d02 3414
87d72d41
AM		 3415 /* Small local sym cache. */
3416 struct sym_cache sym_cache;
906e58ca
NC		 3417
3418 /* For convenience in allocate_dynrelocs. */
3419 bfd * obfd;
3420
0855e32b
NS		 3421 /* The amount of space used by the reserved portion of the sgotplt
3422 section, plus whatever space is used by the jump slots. */
3423 bfd_vma sgotplt_jump_table_size;
3424
906e58ca
NC		 3425 /* The stub hash table. */
3426 struct bfd_hash_table stub_hash_table;
3427
3428 /* Linker stub bfd. */
3429 bfd *stub_bfd;
3430
3431 /* Linker call-backs. */
6bde4c52
TP		 3432 asection * (*add_stub_section) (const char *, asection *, asection *,
3433 unsigned int);
906e58ca
NC		 3434 void (*layout_sections_again) (void);
3435
3436 /* Array to keep track of which stub sections have been created, and
3437 information on stub grouping. */
21d799b5 3438 struct map_stub *stub_group;
906e58ca 3439
4ba2ef8f
TP		 3440 /* Input stub section holding secure gateway veneers. */
3441 asection *cmse_stub_sec;
3442
0955507f
TP		 3443 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3444 start to be allocated. */
3445 bfd_vma new_cmse_stub_offset;
3446
fe33d2fa 3447 /* Number of elements in stub_group. */
7292b3ac 3448 unsigned int top_id;
fe33d2fa 3449
906e58ca
NC		 3450 /* Assorted information used by elf32_arm_size_stubs. */
3451 unsigned int bfd_count;
7292b3ac 3452 unsigned int top_index;
906e58ca 3453 asection **input_list;
617a5ada
CL		 3454
3455 /* True if the target system uses FDPIC. */
3456 int fdpic_p;
e8b09b87
CL		 3457
3458 /* Fixup section. Used for FDPIC. */
3459 asection *srofixup;
906e58ca 3460};
252b5132 3461
e8b09b87
CL		 3462/* Add an FDPIC read-only fixup. */
3463static void
3464arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3465{
3466 bfd_vma fixup_offset;
3467
3468 fixup_offset = srofixup->reloc_count++ * 4;
3469 BFD_ASSERT (fixup_offset < srofixup->size);
3470 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3471}
3472
a504d23a
LA		 3473static inline int
3474ctz (unsigned int mask)
3475{
3476#if GCC_VERSION >= 3004
3477 return __builtin_ctz (mask);
3478#else
3479 unsigned int i;
3480
3481 for (i = 0; i < 8 * sizeof (mask); i++)
3482 {
3483 if (mask & 0x1)
3484 break;
3485 mask = (mask >> 1);
3486 }
3487 return i;
3488#endif
3489}
3490
3491static inline int
b25e998d 3492elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3493{
3494#if GCC_VERSION >= 3004
3495 return __builtin_popcount (mask);
3496#else
b25e998d
CG		 3497 unsigned int i;
3498 int sum = 0;
a504d23a
LA		 3499
3500 for (i = 0; i < 8 * sizeof (mask); i++)
3501 {
3502 if (mask & 0x1)
3503 sum++;
3504 mask = (mask >> 1);
3505 }
3506 return sum;
3507#endif
3508}
3509
e8b09b87
CL		 3510static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3511 asection *sreloc, Elf_Internal_Rela *rel);
3512
3513static void
3514arm_elf_fill_funcdesc(bfd *output_bfd,
3515 struct bfd_link_info *info,
3516 int *funcdesc_offset,
3517 int dynindx,
3518 int offset,
3519 bfd_vma addr,
3520 bfd_vma dynreloc_value,
3521 bfd_vma seg)
3522{
3523 if ((*funcdesc_offset & 1) == 0)
3524 {
3525 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3526 asection *sgot = globals->root.sgot;
3527
3528 if (bfd_link_pic(info))
3529 {
3530 asection *srelgot = globals->root.srelgot;
3531 Elf_Internal_Rela outrel;
3532
3533 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3534 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3535 outrel.r_addend = 0;
3536
3537 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3538 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3539 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3540 }
3541 else
3542 {
3543 struct elf_link_hash_entry *hgot = globals->root.hgot;
3544 bfd_vma got_value = hgot->root.u.def.value
3545 + hgot->root.u.def.section->output_section->vma
3546 + hgot->root.u.def.section->output_offset;
3547
3548 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3549 sgot->output_section->vma + sgot->output_offset
3550 + offset);
3551 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3552 sgot->output_section->vma + sgot->output_offset
3553 + offset + 4);
3554 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3555 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3556 }
3557 *funcdesc_offset |= 1;
3558 }
3559}
3560
780a67af
NC		 3561/* Create an entry in an ARM ELF linker hash table. */
3562
3563static struct bfd_hash_entry *
57e8b36a 3564elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3565 struct bfd_hash_table * table,
3566 const char * string)
780a67af
NC		 3567{
3568 struct elf32_arm_link_hash_entry * ret =
3569 (struct elf32_arm_link_hash_entry *) entry;
3570
3571 /* Allocate the structure if it has not already been allocated by a
3572 subclass. */
906e58ca 3573 if (ret == NULL)
21d799b5 3574 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3575 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3576 if (ret == NULL)
780a67af
NC		 3577 return (struct bfd_hash_entry *) ret;
3578
3579 /* Call the allocation method of the superclass. */
3580 ret = ((struct elf32_arm_link_hash_entry *)
3581 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3582 table, string));
57e8b36a 3583 if (ret != NULL)
b7693d02 3584 {
0bdcacaf 3585 ret->dyn_relocs = NULL;
ba93b8ac 3586 ret->tls_type = GOT_UNKNOWN;
0855e32b 3587 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3588 ret->plt.thumb_refcount = 0;
3589 ret->plt.maybe_thumb_refcount = 0;
3590 ret->plt.noncall_refcount = 0;
3591 ret->plt.got_offset = -1;
3592 ret->is_iplt = FALSE;
a4fd1a8e 3593 ret->export_glue = NULL;
906e58ca
NC		 3594
3595 ret->stub_cache = NULL;
e8b09b87
CL		 3596
3597 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3598 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3599 ret->fdpic_cnts.funcdesc_cnt = 0;
3600 ret->fdpic_cnts.funcdesc_offset = -1;
3601 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3602 }
780a67af
NC		 3603
3604 return (struct bfd_hash_entry *) ret;
3605}
3606
34e77a92
RS		 3607/* Ensure that we have allocated bookkeeping structures for ABFD's local
3608 symbols. */
3609
3610static bfd_boolean
3611elf32_arm_allocate_local_sym_info (bfd *abfd)
3612{
3613 if (elf_local_got_refcounts (abfd) == NULL)
3614 {
3615 bfd_size_type num_syms;
3616 bfd_size_type size;
3617 char *data;
3618
3619 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3620 size = num_syms * (sizeof (bfd_signed_vma)
3621 + sizeof (struct arm_local_iplt_info *)
3622 + sizeof (bfd_vma)
e8b09b87
CL		 3623 + sizeof (char)
3624 + sizeof (struct fdpic_local));
34e77a92
RS		 3625 data = bfd_zalloc (abfd, size);
3626 if (data == NULL)
3627 return FALSE;
3628
e8b09b87
CL		 3629 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3630 data += num_syms * sizeof (struct fdpic_local);
3631
34e77a92
RS		 3632 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3633 data += num_syms * sizeof (bfd_signed_vma);
3634
3635 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3636 data += num_syms * sizeof (struct arm_local_iplt_info *);
3637
3638 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3639 data += num_syms * sizeof (bfd_vma);
3640
3641 elf32_arm_local_got_tls_type (abfd) = data;
3642 }
3643 return TRUE;
3644}
3645
3646/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3647 to input bfd ABFD. Create the information if it doesn't already exist.
3648 Return null if an allocation fails. */
3649
3650static struct arm_local_iplt_info *
3651elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3652{
3653 struct arm_local_iplt_info **ptr;
3654
3655 if (!elf32_arm_allocate_local_sym_info (abfd))
3656 return NULL;
3657
3658 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3659 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3660 if (*ptr == NULL)
3661 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3662 return *ptr;
3663}
3664
3665/* Try to obtain PLT information for the symbol with index R_SYMNDX
3666 in ABFD's symbol table. If the symbol is global, H points to its
3667 hash table entry, otherwise H is null.
3668
3669 Return true if the symbol does have PLT information. When returning
3670 true, point *ROOT_PLT at the target-independent reference count/offset
3671 union and *ARM_PLT at the ARM-specific information. */
3672
3673static bfd_boolean
4ba2ef8f
TP		 3674elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3675 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3676 unsigned long r_symndx, union gotplt_union **root_plt,
3677 struct arm_plt_info **arm_plt)
3678{
3679 struct arm_local_iplt_info *local_iplt;
3680
4ba2ef8f
TP		 3681 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3682 return FALSE;
3683
34e77a92
RS		 3684 if (h != NULL)
3685 {
3686 *root_plt = &h->root.plt;
3687 *arm_plt = &h->plt;
3688 return TRUE;
3689 }
3690
3691 if (elf32_arm_local_iplt (abfd) == NULL)
3692 return FALSE;
3693
3694 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3695 if (local_iplt == NULL)
3696 return FALSE;
3697
3698 *root_plt = &local_iplt->root;
3699 *arm_plt = &local_iplt->arm;
3700 return TRUE;
3701}
3702
59029f57
CL		 3703static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3704
34e77a92
RS		 3705/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3706 before it. */
3707
3708static bfd_boolean
3709elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3710 struct arm_plt_info *arm_plt)
3711{
3712 struct elf32_arm_link_hash_table *htab;
3713
3714 htab = elf32_arm_hash_table (info);
59029f57
CL		 3715
3716 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3717 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3718}
3719
3720/* Return a pointer to the head of the dynamic reloc list that should
3721 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3722 ABFD's symbol table. Return null if an error occurs. */
3723
3724static struct elf_dyn_relocs **
3725elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3726 Elf_Internal_Sym *isym)
3727{
3728 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3729 {
3730 struct arm_local_iplt_info *local_iplt;
3731
3732 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3733 if (local_iplt == NULL)
3734 return NULL;
3735 return &local_iplt->dyn_relocs;
3736 }
3737 else
3738 {
3739 /* Track dynamic relocs needed for local syms too.
3740 We really need local syms available to do this
3741 easily. Oh well. */
3742 asection *s;
3743 void *vpp;
3744
3745 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3746 if (s == NULL)
3747 abort ();
3748
3749 vpp = &elf_section_data (s)->local_dynrel;
3750 return (struct elf_dyn_relocs **) vpp;
3751 }
3752}
3753
906e58ca
NC		 3754/* Initialize an entry in the stub hash table. */
3755
3756static struct bfd_hash_entry *
3757stub_hash_newfunc (struct bfd_hash_entry *entry,
3758 struct bfd_hash_table *table,
3759 const char *string)
3760{
3761 /* Allocate the structure if it has not already been allocated by a
3762 subclass. */
3763 if (entry == NULL)
3764 {
21d799b5 3765 entry = (struct bfd_hash_entry *)
99059e56 3766 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3767 if (entry == NULL)
3768 return entry;
3769 }
3770
3771 /* Call the allocation method of the superclass. */
3772 entry = bfd_hash_newfunc (entry, table, string);
3773 if (entry != NULL)
3774 {
3775 struct elf32_arm_stub_hash_entry *eh;
3776
3777 /* Initialize the local fields. */
3778 eh = (struct elf32_arm_stub_hash_entry *) entry;
3779 eh->stub_sec = NULL;
0955507f 3780 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3781 eh->source_value = 0;
906e58ca
NC		 3782 eh->target_value = 0;
3783 eh->target_section = NULL;
cedfb179 3784 eh->orig_insn = 0;
906e58ca 3785 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3786 eh->stub_size = 0;
3787 eh->stub_template = NULL;
0955507f 3788 eh->stub_template_size = -1;
906e58ca
NC		 3789 eh->h = NULL;
3790 eh->id_sec = NULL;
d8d2f433 3791 eh->output_name = NULL;
906e58ca
NC		 3792 }
3793
3794 return entry;
3795}
3796
00a97672 3797/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3798 shortcuts to them in our hash table. */
3799
3800static bfd_boolean
57e8b36a 3801create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3802{
3803 struct elf32_arm_link_hash_table *htab;
3804
e5a52504 3805 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3806 if (htab == NULL)
3807 return FALSE;
3808
e5a52504
MM		 3809 /* BPABI objects never have a GOT, or associated sections. */
3810 if (htab->symbian_p)
3811 return TRUE;
3812
5e681ec4
PB		 3813 if (! _bfd_elf_create_got_section (dynobj, info))
3814 return FALSE;
3815
e8b09b87
CL		 3816 /* Also create .rofixup. */
3817 if (htab->fdpic_p)
3818 {
3819 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3820 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3821 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
fd361982
AM		 3822 if (htab->srofixup == NULL
3823 || !bfd_set_section_alignment (htab->srofixup, 2))
e8b09b87
CL		 3824 return FALSE;
3825 }
3826
5e681ec4
PB		 3827 return TRUE;
3828}
3829
34e77a92
RS		 3830/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3831
3832static bfd_boolean
3833create_ifunc_sections (struct bfd_link_info *info)
3834{
3835 struct elf32_arm_link_hash_table *htab;
3836 const struct elf_backend_data *bed;
3837 bfd *dynobj;
3838 asection *s;
3839 flagword flags;
b38cadfb 3840
34e77a92
RS		 3841 htab = elf32_arm_hash_table (info);
3842 dynobj = htab->root.dynobj;
3843 bed = get_elf_backend_data (dynobj);
3844 flags = bed->dynamic_sec_flags;
3845
3846 if (htab->root.iplt == NULL)
3847 {
3d4d4302
AM		 3848 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3849 flags | SEC_READONLY | SEC_CODE);
34e77a92 3850 if (s == NULL
fd361982 3851 || !bfd_set_section_alignment (s, bed->plt_alignment))
34e77a92
RS		 3852 return FALSE;
3853 htab->root.iplt = s;
3854 }
3855
3856 if (htab->root.irelplt == NULL)
3857 {
3d4d4302
AM		 3858 s = bfd_make_section_anyway_with_flags (dynobj,
3859 RELOC_SECTION (htab, ".iplt"),
3860 flags | SEC_READONLY);
34e77a92 3861 if (s == NULL
fd361982 3862 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3863 return FALSE;
3864 htab->root.irelplt = s;
3865 }
3866
3867 if (htab->root.igotplt == NULL)
3868 {
3d4d4302 3869 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92 3870 if (s == NULL
fd361982 3871 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3872 return FALSE;
3873 htab->root.igotplt = s;
3874 }
3875 return TRUE;
3876}
3877
eed94f8f
NC		 3878/* Determine if we're dealing with a Thumb only architecture. */
3879
3880static bfd_boolean
3881using_thumb_only (struct elf32_arm_link_hash_table *globals)
3882{
2fd158eb
TP		 3883 int arch;
3884 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3885 Tag_CPU_arch_profile);
eed94f8f 3886
2fd158eb
TP		 3887 if (profile)
3888 return profile == 'M';
eed94f8f 3889
2fd158eb 3890 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3891
60a019a0 3892 /* Force return logic to be reviewed for each new architecture. */
031254f2 3893 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3894
2fd158eb
TP		 3895 if (arch == TAG_CPU_ARCH_V6_M
3896 || arch == TAG_CPU_ARCH_V6S_M
3897 || arch == TAG_CPU_ARCH_V7E_M
3898 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3899 || arch == TAG_CPU_ARCH_V8M_MAIN
3900 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3901 return TRUE;
eed94f8f 3902
2fd158eb 3903 return FALSE;
eed94f8f
NC		 3904}
3905
3906/* Determine if we're dealing with a Thumb-2 object. */
3907
3908static bfd_boolean
3909using_thumb2 (struct elf32_arm_link_hash_table *globals)
3910{
60a019a0
TP		 3911 int arch;
3912 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3913 Tag_THUMB_ISA_use);
3914
3915 if (thumb_isa)
3916 return thumb_isa == 2;
3917
3918 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3919
3920 /* Force return logic to be reviewed for each new architecture. */
031254f2 3921 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3922
3923 return (arch == TAG_CPU_ARCH_V6T2
3924 || arch == TAG_CPU_ARCH_V7
3925 || arch == TAG_CPU_ARCH_V7E_M
3926 || arch == TAG_CPU_ARCH_V8
bff0500d 3927 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3928 || arch == TAG_CPU_ARCH_V8M_MAIN
3929 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3930}
3931
5e866f5a
TP		 3932/* Determine whether Thumb-2 BL instruction is available. */
3933
3934static bfd_boolean
3935using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3936{
3937 int arch =
3938 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3939
3940 /* Force return logic to be reviewed for each new architecture. */
031254f2 3941 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3942
3943 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3944 return (arch == TAG_CPU_ARCH_V6T2
3945 || arch >= TAG_CPU_ARCH_V7);
3946}
3947
00a97672
RS		 3948/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3949 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3950 hash table. */
3951
3952static bfd_boolean
57e8b36a 3953elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3954{
3955 struct elf32_arm_link_hash_table *htab;
3956
3957 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3958 if (htab == NULL)
3959 return FALSE;
3960
362d30a1 3961 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3962 return FALSE;
3963
3964 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3965 return FALSE;
3966
00a97672
RS		 3967 if (htab->vxworks_p)
3968 {
3969 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3970 return FALSE;
3971
0e1862bb 3972 if (bfd_link_pic (info))
00a97672
RS		 3973 {
3974 htab->plt_header_size = 0;
3975 htab->plt_entry_size
3976 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3977 }
3978 else
3979 {
3980 htab->plt_header_size
3981 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3982 htab->plt_entry_size
3983 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3984 }
aebf9be7
NC		 3985
3986 if (elf_elfheader (dynobj))
3987 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3988 }
eed94f8f
NC		 3989 else
3990 {
3991 /* PR ld/16017
3992 Test for thumb only architectures. Note - we cannot just call
3993 using_thumb_only() as the attributes in the output bfd have not been
3994 initialised at this point, so instead we use the input bfd. */
3995 bfd * saved_obfd = htab->obfd;
3996
3997 htab->obfd = dynobj;
3998 if (using_thumb_only (htab))
3999 {
4000 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
4001 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
4002 }
4003 htab->obfd = saved_obfd;
4004 }
5e681ec4 4005
7801f98f
CL		 4006 if (htab->fdpic_p) {
4007 htab->plt_header_size = 0;
4008 if (info->flags & DF_BIND_NOW)
4009 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
4010 else
4011 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
4012 }
4013
362d30a1
RS		 4014 if (!htab->root.splt
4015 || !htab->root.srelplt
9d19e4fd
AM		 4016 || !htab->root.sdynbss
4017 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 4018 abort ();
4019
4020 return TRUE;
4021}
4022
906e58ca
NC		 4023/* Copy the extra info we tack onto an elf_link_hash_entry. */
4024
4025static void
4026elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4027 struct elf_link_hash_entry *dir,
4028 struct elf_link_hash_entry *ind)
4029{
4030 struct elf32_arm_link_hash_entry *edir, *eind;
4031
4032 edir = (struct elf32_arm_link_hash_entry *) dir;
4033 eind = (struct elf32_arm_link_hash_entry *) ind;
4034
0bdcacaf 4035 if (eind->dyn_relocs != NULL)
906e58ca 4036 {
0bdcacaf 4037 if (edir->dyn_relocs != NULL)
906e58ca 4038 {
0bdcacaf
RS		 4039 struct elf_dyn_relocs **pp;
4040 struct elf_dyn_relocs *p;
906e58ca
NC		 4041
4042 /* Add reloc counts against the indirect sym to the direct sym
4043 list. Merge any entries against the same section. */
0bdcacaf 4044 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 4045 {
0bdcacaf 4046 struct elf_dyn_relocs *q;
906e58ca 4047
0bdcacaf
RS		 4048 for (q = edir->dyn_relocs; q != NULL; q = q->next)
4049 if (q->sec == p->sec)
906e58ca
NC		 4050 {
4051 q->pc_count += p->pc_count;
4052 q->count += p->count;
4053 *pp = p->next;
4054 break;
4055 }
4056 if (q == NULL)
4057 pp = &p->next;
4058 }
0bdcacaf 4059 *pp = edir->dyn_relocs;
906e58ca
NC		 4060 }
4061
0bdcacaf
RS		 4062 edir->dyn_relocs = eind->dyn_relocs;
4063 eind->dyn_relocs = NULL;
906e58ca
NC		 4064 }
4065
4066 if (ind->root.type == bfd_link_hash_indirect)
4067 {
4068 /* Copy over PLT info. */
34e77a92
RS		 4069 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4070 eind->plt.thumb_refcount = 0;
4071 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4072 eind->plt.maybe_thumb_refcount = 0;
4073 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4074 eind->plt.noncall_refcount = 0;
4075
e8b09b87
CL		 4076 /* Copy FDPIC counters. */
4077 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4078 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4079 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4080
34e77a92
RS		 4081 /* We should only allocate a function to .iplt once the final
4082 symbol information is known. */
4083 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4084
4085 if (dir->got.refcount <= 0)
4086 {
4087 edir->tls_type = eind->tls_type;
4088 eind->tls_type = GOT_UNKNOWN;
4089 }
4090 }
4091
4092 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4093}
4094
68faa637
AM		 4095/* Destroy an ARM elf linker hash table. */
4096
4097static void
d495ab0d 4098elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4099{
4100 struct elf32_arm_link_hash_table *ret
d495ab0d 4101 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4102
4103 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4104 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4105}
4106
906e58ca
NC		 4107/* Create an ARM elf linker hash table. */
4108
4109static struct bfd_link_hash_table *
4110elf32_arm_link_hash_table_create (bfd *abfd)
4111{
4112 struct elf32_arm_link_hash_table *ret;
4113 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4114
7bf52ea2 4115 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4116 if (ret == NULL)
4117 return NULL;
4118
4119 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4120 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4121 sizeof (struct elf32_arm_link_hash_entry),
4122 ARM_ELF_DATA))
906e58ca
NC		 4123 {
4124 free (ret);
4125 return NULL;
4126 }
4127
906e58ca 4128 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4129 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4130#ifdef FOUR_WORD_PLT
4131 ret->plt_header_size = 16;
4132 ret->plt_entry_size = 16;
4133#else
4134 ret->plt_header_size = 20;
1db37fe6 4135 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4136#endif
f3185997 4137 ret->use_rel = TRUE;
906e58ca 4138 ret->obfd = abfd;
617a5ada 4139 ret->fdpic_p = 0;
906e58ca
NC		 4140
4141 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4142 sizeof (struct elf32_arm_stub_hash_entry)))
4143 {
d495ab0d 4144 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4145 return NULL;
4146 }
d495ab0d 4147 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4148
4149 return &ret->root.root;
4150}
4151
cd1dac3d
DG		 4152/* Determine what kind of NOPs are available. */
4153
4154static bfd_boolean
4155arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4156{
4157 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4158 Tag_CPU_arch);
cd1dac3d 4159
60a019a0 4160 /* Force return logic to be reviewed for each new architecture. */
031254f2 4161 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4162
4163 return (arch == TAG_CPU_ARCH_V6T2
4164 || arch == TAG_CPU_ARCH_V6K
4165 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4166 || arch == TAG_CPU_ARCH_V8
4167 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4168}
4169
f4ac8484
DJ		 4170static bfd_boolean
4171arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4172{
4173 switch (stub_type)
4174 {
fea2b4d6 4175 case arm_stub_long_branch_thumb_only:
80c135e5 4176 case arm_stub_long_branch_thumb2_only:
d5a67c02 4177 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4178 case arm_stub_long_branch_v4t_thumb_arm:
4179 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4180 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4181 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4182 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4183 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4184 return TRUE;
4185 case arm_stub_none:
4186 BFD_FAIL ();
4187 return FALSE;
4188 break;
4189 default:
4190 return FALSE;
4191 }
4192}
4193
906e58ca
NC		 4194/* Determine the type of stub needed, if any, for a call. */
4195
4196static enum elf32_arm_stub_type
4197arm_type_of_stub (struct bfd_link_info *info,
4198 asection *input_sec,
4199 const Elf_Internal_Rela *rel,
34e77a92 4200 unsigned char st_type,
35fc36a8 4201 enum arm_st_branch_type *actual_branch_type,
906e58ca 4202 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4203 bfd_vma destination,
4204 asection *sym_sec,
4205 bfd *input_bfd,
4206 const char *name)
906e58ca
NC		 4207{
4208 bfd_vma location;
4209 bfd_signed_vma branch_offset;
4210 unsigned int r_type;
4211 struct elf32_arm_link_hash_table * globals;
5e866f5a 4212 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4213 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4214 int use_plt = 0;
35fc36a8 4215 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4216 union gotplt_union *root_plt;
4217 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4218 int arch;
4219 int thumb2_movw;
906e58ca 4220
35fc36a8 4221 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4222 return stub_type;
4223
906e58ca 4224 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4225 if (globals == NULL)
4226 return stub_type;
906e58ca
NC		 4227
4228 thumb_only = using_thumb_only (globals);
906e58ca 4229 thumb2 = using_thumb2 (globals);
5e866f5a 4230 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4231
d5a67c02
AV		 4232 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4233
4234 /* True for architectures that implement the thumb2 movw instruction. */
4235 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4236
906e58ca
NC		 4237 /* Determine where the call point is. */
4238 location = (input_sec->output_offset
4239 + input_sec->output_section->vma
4240 + rel->r_offset);
4241
906e58ca
NC		 4242 r_type = ELF32_R_TYPE (rel->r_info);
4243
39f21624
NC		 4244 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4245 are considering a function call relocation. */
c5423981 4246 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4247 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4248 && branch_type == ST_BRANCH_TO_ARM)
4249 branch_type = ST_BRANCH_TO_THUMB;
4250
34e77a92
RS		 4251 /* For TLS call relocs, it is the caller's responsibility to provide
4252 the address of the appropriate trampoline. */
4253 if (r_type != R_ARM_TLS_CALL
4254 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4255 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4256 ELF32_R_SYM (rel->r_info), &root_plt,
4257 &arm_plt)
34e77a92 4258 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4259 {
34e77a92 4260 asection *splt;
fe33d2fa 4261
34e77a92
RS		 4262 if (hash == NULL || hash->is_iplt)
4263 splt = globals->root.iplt;
4264 else
4265 splt = globals->root.splt;
4266 if (splt != NULL)
b38cadfb 4267 {
34e77a92
RS		 4268 use_plt = 1;
4269
4270 /* Note when dealing with PLT entries: the main PLT stub is in
4271 ARM mode, so if the branch is in Thumb mode, another
4272 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4273 PLT stub. If a long branch stub is needed, we'll add a
4274 Thumb->Arm one and branch directly to the ARM PLT entry.
4275 Here, we have to check if a pre-PLT Thumb->ARM stub
4276 is needed and if it will be close enough. */
34e77a92
RS		 4277
4278 destination = (splt->output_section->vma
4279 + splt->output_offset
4280 + root_plt->offset);
4281 st_type = STT_FUNC;
2df2751d
CL		 4282
4283 /* Thumb branch/call to PLT: it can become a branch to ARM
4284 or to Thumb. We must perform the same checks and
4285 corrections as in elf32_arm_final_link_relocate. */
4286 if ((r_type == R_ARM_THM_CALL)
4287 || (r_type == R_ARM_THM_JUMP24))
4288 {
4289 if (globals->use_blx
4290 && r_type == R_ARM_THM_CALL
4291 && !thumb_only)
4292 {
4293 /* If the Thumb BLX instruction is available, convert
4294 the BL to a BLX instruction to call the ARM-mode
4295 PLT entry. */
4296 branch_type = ST_BRANCH_TO_ARM;
4297 }
4298 else
4299 {
4300 if (!thumb_only)
4301 /* Target the Thumb stub before the ARM PLT entry. */
4302 destination -= PLT_THUMB_STUB_SIZE;
4303 branch_type = ST_BRANCH_TO_THUMB;
4304 }
4305 }
4306 else
4307 {
4308 branch_type = ST_BRANCH_TO_ARM;
4309 }
34e77a92 4310 }
5fa9e92f 4311 }
34e77a92
RS		 4312 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4313 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4314
fe33d2fa
CL		 4315 branch_offset = (bfd_signed_vma)(destination - location);
4316
0855e32b 4317 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4318 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4319 {
5fa9e92f
CL		 4320 /* Handle cases where:
4321 - this call goes too far (different Thumb/Thumb2 max
99059e56 4322 distance)
155d87d7 4323 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4324 Thumb->Arm branch (not bl). A stub is needed in this case,
4325 but only if this call is not through a PLT entry. Indeed,
695344c0 4326 PLT stubs handle mode switching already. */
5e866f5a 4327 if ((!thumb2_bl
906e58ca
NC		 4328 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4329 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4330 || (thumb2_bl
906e58ca
NC		 4331 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4332 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4333 || (thumb2
4334 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4335 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4336 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4337 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4338 && (((r_type == R_ARM_THM_CALL
4339 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4340 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4341 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4342 && !use_plt))
906e58ca 4343 {
2df2751d
CL		 4344 /* If we need to insert a Thumb-Thumb long branch stub to a
4345 PLT, use one that branches directly to the ARM PLT
4346 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4347 stub, undo this now. */
695344c0
NC		 4348 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4349 {
4350 branch_type = ST_BRANCH_TO_ARM;
4351 branch_offset += PLT_THUMB_STUB_SIZE;
4352 }
2df2751d 4353
35fc36a8 4354 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4355 {
4356 /* Thumb to thumb. */
4357 if (!thumb_only)
4358 {
d5a67c02 4359 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4360 _bfd_error_handler
871b3ab2 4361 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4362 " section with SHF_ARM_PURECODE section"
4363 " attribute is only supported for M-profile"
90b6238f 4364 " targets that implement the movw instruction"),
10463f39 4365 input_bfd, input_sec);
d5a67c02 4366
0e1862bb 4367 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4368 /* PIC stubs. */
155d87d7 4369 ? ((globals->use_blx
9553db3c 4370 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4371 /* V5T and above. Stub starts with ARM code, so
4372 we must be able to switch mode before
4373 reaching it, which is only possible for 'bl'
4374 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4375 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4376 /* On V4T, use Thumb code only. */
d3626fb0 4377 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4378
4379 /* non-PIC stubs. */
155d87d7 4380 : ((globals->use_blx
9553db3c 4381 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4382 /* V5T and above. */
4383 ? arm_stub_long_branch_any_any
4384 /* V4T. */
d3626fb0 4385 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4386 }
4387 else
4388 {
d5a67c02
AV		 4389 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4390 stub_type = arm_stub_long_branch_thumb2_only_pure;
4391 else
4392 {
4393 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4394 _bfd_error_handler
871b3ab2 4395 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4396 " section with SHF_ARM_PURECODE section"
4397 " attribute is only supported for M-profile"
90b6238f 4398 " targets that implement the movw instruction"),
10463f39 4399 input_bfd, input_sec);
d5a67c02
AV		 4400
4401 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4402 /* PIC stub. */
4403 ? arm_stub_long_branch_thumb_only_pic
4404 /* non-PIC stub. */
4405 : (thumb2 ? arm_stub_long_branch_thumb2_only
4406 : arm_stub_long_branch_thumb_only);
4407 }
906e58ca
NC		 4408 }
4409 }
4410 else
4411 {
d5a67c02 4412 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4413 _bfd_error_handler
871b3ab2 4414 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4415 " section with SHF_ARM_PURECODE section"
4416 " attribute is only supported" " for M-profile"
90b6238f 4417 " targets that implement the movw instruction"),
10463f39 4418 input_bfd, input_sec);
d5a67c02 4419
906e58ca 4420 /* Thumb to arm. */
c820be07
NC		 4421 if (sym_sec != NULL
4422 && sym_sec->owner != NULL
4423 && !INTERWORK_FLAG (sym_sec->owner))
4424 {
4eca0228 4425 _bfd_error_handler
90b6238f
AM		 4426 (_("%pB(%s): warning: interworking not enabled;"
4427 " first occurrence: %pB: %s call to %s"),
4428 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4429 }
4430
0855e32b 4431 stub_type =
0e1862bb 4432 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4433 /* PIC stubs. */
0855e32b 4434 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4435 /* TLS PIC stubs. */
0855e32b
NS		 4436 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4437 : arm_stub_long_branch_v4t_thumb_tls_pic)
4438 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4439 /* V5T PIC and above. */
4440 ? arm_stub_long_branch_any_arm_pic
4441 /* V4T PIC stub. */
4442 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4443
4444 /* non-PIC stubs. */
0855e32b 4445 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4446 /* V5T and above. */
4447 ? arm_stub_long_branch_any_any
4448 /* V4T. */
4449 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4450
4451 /* Handle v4t short branches. */
fea2b4d6 4452 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4453 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4454 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4455 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4456 }
4457 }
4458 }
fe33d2fa
CL		 4459 else if (r_type == R_ARM_CALL
4460 || r_type == R_ARM_JUMP24
0855e32b
NS		 4461 || r_type == R_ARM_PLT32
4462 || r_type == R_ARM_TLS_CALL)
906e58ca 4463 {
d5a67c02 4464 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4465 _bfd_error_handler
871b3ab2 4466 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4467 " section with SHF_ARM_PURECODE section"
4468 " attribute is only supported for M-profile"
90b6238f 4469 " targets that implement the movw instruction"),
10463f39 4470 input_bfd, input_sec);
35fc36a8 4471 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4472 {
4473 /* Arm to thumb. */
c820be07
NC		 4474
4475 if (sym_sec != NULL
4476 && sym_sec->owner != NULL
4477 && !INTERWORK_FLAG (sym_sec->owner))
4478 {
4eca0228 4479 _bfd_error_handler
90b6238f
AM		 4480 (_("%pB(%s): warning: interworking not enabled;"
4481 " first occurrence: %pB: %s call to %s"),
4482 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4483 }
4484
4485 /* We have an extra 2-bytes reach because of
4486 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4487 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4488 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4489 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4490 || (r_type == R_ARM_JUMP24)
4491 || (r_type == R_ARM_PLT32))
906e58ca 4492 {
0e1862bb 4493 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4494 /* PIC stubs. */
ebe24dd4
CL		 4495 ? ((globals->use_blx)
4496 /* V5T and above. */
4497 ? arm_stub_long_branch_any_thumb_pic
4498 /* V4T stub. */
4499 : arm_stub_long_branch_v4t_arm_thumb_pic)
4500
c2b4a39d
CL		 4501 /* non-PIC stubs. */
4502 : ((globals->use_blx)
4503 /* V5T and above. */
4504 ? arm_stub_long_branch_any_any
4505 /* V4T. */
4506 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4507 }
4508 }
4509 else
4510 {
4511 /* Arm to arm. */
4512 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4513 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4514 {
0855e32b 4515 stub_type =
0e1862bb 4516 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4517 /* PIC stubs. */
0855e32b 4518 ? (r_type == R_ARM_TLS_CALL
6a631e86 4519 /* TLS PIC Stub. */
0855e32b 4520 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4521 : (globals->nacl_p
4522 ? arm_stub_long_branch_arm_nacl_pic
4523 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4524 /* non-PIC stubs. */
7a89b94e
NC		 4525 : (globals->nacl_p
4526 ? arm_stub_long_branch_arm_nacl
4527 : arm_stub_long_branch_any_any);
906e58ca
NC		 4528 }
4529 }
4530 }
4531
fe33d2fa
CL		 4532 /* If a stub is needed, record the actual destination type. */
4533 if (stub_type != arm_stub_none)
35fc36a8 4534 *actual_branch_type = branch_type;
fe33d2fa 4535
906e58ca
NC		 4536 return stub_type;
4537}
4538
4539/* Build a name for an entry in the stub hash table. */
4540
4541static char *
4542elf32_arm_stub_name (const asection *input_section,
4543 const asection *sym_sec,
4544 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4545 const Elf_Internal_Rela *rel,
4546 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4547{
4548 char *stub_name;
4549 bfd_size_type len;
4550
4551 if (hash)
4552 {
fe33d2fa 4553 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4554 stub_name = (char *) bfd_malloc (len);
906e58ca 4555 if (stub_name != NULL)
fe33d2fa 4556 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4557 input_section->id & 0xffffffff,
4558 hash->root.root.root.string,
fe33d2fa
CL		 4559 (int) rel->r_addend & 0xffffffff,
4560 (int) stub_type);
906e58ca
NC		 4561 }
4562 else
4563 {
fe33d2fa 4564 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4565 stub_name = (char *) bfd_malloc (len);
906e58ca 4566 if (stub_name != NULL)
fe33d2fa 4567 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4568 input_section->id & 0xffffffff,
4569 sym_sec->id & 0xffffffff,
0855e32b
NS		 4570 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4571 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4572 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4573 (int) rel->r_addend & 0xffffffff,
4574 (int) stub_type);
906e58ca
NC		 4575 }
4576
4577 return stub_name;
4578}
4579
4580/* Look up an entry in the stub hash. Stub entries are cached because
4581 creating the stub name takes a bit of time. */
4582
4583static struct elf32_arm_stub_hash_entry *
4584elf32_arm_get_stub_entry (const asection *input_section,
4585 const asection *sym_sec,
4586 struct elf_link_hash_entry *hash,
4587 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4588 struct elf32_arm_link_hash_table *htab,
4589 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4590{
4591 struct elf32_arm_stub_hash_entry *stub_entry;
4592 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4593 const asection *id_sec;
4594
4595 if ((input_section->flags & SEC_CODE) == 0)
4596 return NULL;
4597
4d83e8d9
CL		 4598 /* If the input section is the CMSE stubs one and it needs a long
4599 branch stub to reach it's final destination, give up with an
4600 error message: this is not supported. See PR ld/24709. */
4601 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4602 {
4603 bfd *output_bfd = htab->obfd;
4604 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4605
4606 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4607 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4608 CMSE_STUB_NAME,
4609 (uint64_t)out_sec->output_section->vma
4610 + out_sec->output_offset,
4611 (uint64_t)sym_sec->output_section->vma
4612 + sym_sec->output_offset
4613 + h->root.root.u.def.value);
4614 /* Exit, rather than leave incompletely processed
4615 relocations. */
4616 xexit(1);
4617 }
4618
906e58ca
NC		 4619 /* If this input section is part of a group of sections sharing one
4620 stub section, then use the id of the first section in the group.
4621 Stub names need to include a section id, as there may well be
4622 more than one stub used to reach say, printf, and we need to
4623 distinguish between them. */
c2abbbeb 4624 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4625 id_sec = htab->stub_group[input_section->id].link_sec;
4626
4627 if (h != NULL && h->stub_cache != NULL
4628 && h->stub_cache->h == h
fe33d2fa
CL		 4629 && h->stub_cache->id_sec == id_sec
4630 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4631 {
4632 stub_entry = h->stub_cache;
4633 }
4634 else
4635 {
4636 char *stub_name;
4637
fe33d2fa 4638 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4639 if (stub_name == NULL)
4640 return NULL;
4641
4642 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4643 stub_name, FALSE, FALSE);
4644 if (h != NULL)
4645 h->stub_cache = stub_entry;
4646
4647 free (stub_name);
4648 }
4649
4650 return stub_entry;
4651}
4652
daa4adae
TP		 4653/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4654 section. */
4655
4656static bfd_boolean
4657arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4658{
4659 if (stub_type >= max_stub_type)
4660 abort (); /* Should be unreachable. */
4661
4ba2ef8f
TP		 4662 switch (stub_type)
4663 {
4664 case arm_stub_cmse_branch_thumb_only:
4665 return TRUE;
4666
4667 default:
4668 return FALSE;
4669 }
4670
4671 abort (); /* Should be unreachable. */
daa4adae
TP		 4672}
4673
4674/* Required alignment (as a power of 2) for the dedicated section holding
4675 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4676 with input sections. */
4677
4678static int
4679arm_dedicated_stub_output_section_required_alignment
4680 (enum elf32_arm_stub_type stub_type)
4681{
4682 if (stub_type >= max_stub_type)
4683 abort (); /* Should be unreachable. */
4684
4ba2ef8f
TP		 4685 switch (stub_type)
4686 {
4687 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4688 boundary. */
4689 case arm_stub_cmse_branch_thumb_only:
4690 return 5;
4691
4692 default:
4693 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4694 return 0;
4695 }
4696
4697 abort (); /* Should be unreachable. */
daa4adae
TP		 4698}
4699
4700/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4701 NULL if veneers of this type are interspersed with input sections. */
4702
4703static const char *
4704arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4705{
4706 if (stub_type >= max_stub_type)
4707 abort (); /* Should be unreachable. */
4708
4ba2ef8f
TP		 4709 switch (stub_type)
4710 {
4711 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4712 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4713
4714 default:
4715 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4716 return NULL;
4717 }
4718
4719 abort (); /* Should be unreachable. */
daa4adae
TP		 4720}
4721
4722/* If veneers of type STUB_TYPE should go in a dedicated output section,
4723 returns the address of the hash table field in HTAB holding a pointer to the
4724 corresponding input section. Otherwise, returns NULL. */
4725
4726static asection **
4ba2ef8f
TP		 4727arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4728 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4729{
4730 if (stub_type >= max_stub_type)
4731 abort (); /* Should be unreachable. */
4732
4ba2ef8f
TP		 4733 switch (stub_type)
4734 {
4735 case arm_stub_cmse_branch_thumb_only:
4736 return &htab->cmse_stub_sec;
4737
4738 default:
4739 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4740 return NULL;
4741 }
4742
4743 abort (); /* Should be unreachable. */
daa4adae
TP		 4744}
4745
4746/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4747 is the section that branch into veneer and can be NULL if stub should go in
4748 a dedicated output section. Returns a pointer to the stub section, and the
4749 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4750 LINK_SEC_P may be NULL. */
906e58ca 4751
48229727
JB		 4752static asection *
4753elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4754 struct elf32_arm_link_hash_table *htab,
4755 enum elf32_arm_stub_type stub_type)
906e58ca 4756{
daa4adae
TP		 4757 asection *link_sec, *out_sec, **stub_sec_p;
4758 const char *stub_sec_prefix;
4759 bfd_boolean dedicated_output_section =
4760 arm_dedicated_stub_output_section_required (stub_type);
4761 int align;
906e58ca 4762
daa4adae 4763 if (dedicated_output_section)
906e58ca 4764 {
daa4adae
TP		 4765 bfd *output_bfd = htab->obfd;
4766 const char *out_sec_name =
4767 arm_dedicated_stub_output_section_name (stub_type);
4768 link_sec = NULL;
4769 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4770 stub_sec_prefix = out_sec_name;
4771 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4772 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4773 if (out_sec == NULL)
906e58ca 4774 {
90b6238f 4775 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4776 "section %s"), out_sec_name);
daa4adae 4777 return NULL;
906e58ca 4778 }
daa4adae
TP		 4779 }
4780 else
4781 {
c2abbbeb 4782 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4783 link_sec = htab->stub_group[section->id].link_sec;
4784 BFD_ASSERT (link_sec != NULL);
4785 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4786 if (*stub_sec_p == NULL)
4787 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4788 stub_sec_prefix = link_sec->name;
4789 out_sec = link_sec->output_section;
4790 align = htab->nacl_p ? 4 : 3;
906e58ca 4791 }
b38cadfb 4792
daa4adae
TP		 4793 if (*stub_sec_p == NULL)
4794 {
4795 size_t namelen;
4796 bfd_size_type len;
4797 char *s_name;
4798
4799 namelen = strlen (stub_sec_prefix);
4800 len = namelen + sizeof (STUB_SUFFIX);
4801 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4802 if (s_name == NULL)
4803 return NULL;
4804
4805 memcpy (s_name, stub_sec_prefix, namelen);
4806 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4807 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4808 align);
4809 if (*stub_sec_p == NULL)
4810 return NULL;
4811
4812 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4813 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4814 | SEC_KEEP;
4815 }
4816
4817 if (!dedicated_output_section)
4818 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4819
48229727
JB		 4820 if (link_sec_p)
4821 *link_sec_p = link_sec;
b38cadfb 4822
daa4adae 4823 return *stub_sec_p;
48229727
JB		 4824}
4825
4826/* Add a new stub entry to the stub hash. Not all fields of the new
4827 stub entry are initialised. */
4828
4829static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4830elf32_arm_add_stub (const char *stub_name, asection *section,
4831 struct elf32_arm_link_hash_table *htab,
4832 enum elf32_arm_stub_type stub_type)
48229727
JB		 4833{
4834 asection *link_sec;
4835 asection *stub_sec;
4836 struct elf32_arm_stub_hash_entry *stub_entry;
4837
daa4adae
TP		 4838 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4839 stub_type);
48229727
JB		 4840 if (stub_sec == NULL)
4841 return NULL;
906e58ca
NC		 4842
4843 /* Enter this entry into the linker stub hash table. */
4844 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4845 TRUE, FALSE);
4846 if (stub_entry == NULL)
4847 {
6bde4c52
TP		 4848 if (section == NULL)
4849 section = stub_sec;
871b3ab2 4850 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4851 section->owner, stub_name);
906e58ca
NC		 4852 return NULL;
4853 }
4854
4855 stub_entry->stub_sec = stub_sec;
0955507f 4856 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4857 stub_entry->id_sec = link_sec;
4858
906e58ca
NC		 4859 return stub_entry;
4860}
4861
4862/* Store an Arm insn into an output section not processed by
4863 elf32_arm_write_section. */
4864
4865static void
8029a119
NC		 4866put_arm_insn (struct elf32_arm_link_hash_table * htab,
4867 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4868{
4869 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4870 bfd_putl32 (val, ptr);
4871 else
4872 bfd_putb32 (val, ptr);
4873}
4874
4875/* Store a 16-bit Thumb insn into an output section not processed by
4876 elf32_arm_write_section. */
4877
4878static void
8029a119
NC		 4879put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4880 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4881{
4882 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4883 bfd_putl16 (val, ptr);
4884 else
4885 bfd_putb16 (val, ptr);
4886}
4887
a504d23a
LA		 4888/* Store a Thumb2 insn into an output section not processed by
4889 elf32_arm_write_section. */
4890
4891static void
4892put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4893 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4894{
4895 /* T2 instructions are 16-bit streamed. */
4896 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4897 {
4898 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4899 bfd_putl16 ((val & 0xffff), ptr + 2);
4900 }
4901 else
4902 {
4903 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4904 bfd_putb16 ((val & 0xffff), ptr + 2);
4905 }
4906}
4907
0855e32b
NS		 4908/* If it's possible to change R_TYPE to a more efficient access
4909 model, return the new reloc type. */
4910
4911static unsigned
b38cadfb 4912elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4913 struct elf_link_hash_entry *h)
4914{
4915 int is_local = (h == NULL);
4916
9cb09e33 4917 if (bfd_link_dll (info)
0e1862bb 4918 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4919 return r_type;
4920
b38cadfb 4921 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4922 switch (r_type)
4923 {
4924 case R_ARM_TLS_GOTDESC:
4925 case R_ARM_TLS_CALL:
4926 case R_ARM_THM_TLS_CALL:
4927 case R_ARM_TLS_DESCSEQ:
4928 case R_ARM_THM_TLS_DESCSEQ:
4929 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4930 }
4931
4932 return r_type;
4933}
4934
48229727
JB		 4935static bfd_reloc_status_type elf32_arm_final_link_relocate
4936 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4937 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4938 const char *, unsigned char, enum arm_st_branch_type,
4939 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4940
4563a860
JB		 4941static unsigned int
4942arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4943{
4944 switch (stub_type)
4945 {
4946 case arm_stub_a8_veneer_b_cond:
4947 case arm_stub_a8_veneer_b:
4948 case arm_stub_a8_veneer_bl:
4949 return 2;
4950
4951 case arm_stub_long_branch_any_any:
4952 case arm_stub_long_branch_v4t_arm_thumb:
4953 case arm_stub_long_branch_thumb_only:
80c135e5 4954 case arm_stub_long_branch_thumb2_only:
d5a67c02 4955 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4956 case arm_stub_long_branch_v4t_thumb_thumb:
4957 case arm_stub_long_branch_v4t_thumb_arm:
4958 case arm_stub_short_branch_v4t_thumb_arm:
4959 case arm_stub_long_branch_any_arm_pic:
4960 case arm_stub_long_branch_any_thumb_pic:
4961 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4962 case arm_stub_long_branch_v4t_arm_thumb_pic:
4963 case arm_stub_long_branch_v4t_thumb_arm_pic:
4964 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4965 case arm_stub_long_branch_any_tls_pic:
4966 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4967 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4968 case arm_stub_a8_veneer_blx:
4969 return 4;
b38cadfb 4970
7a89b94e
NC		 4971 case arm_stub_long_branch_arm_nacl:
4972 case arm_stub_long_branch_arm_nacl_pic:
4973 return 16;
4974
4563a860
JB		 4975 default:
4976 abort (); /* Should be unreachable. */
4977 }
4978}
4979
4f4faa4d
TP		 4980/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4981 veneering (TRUE) or have their own symbol (FALSE). */
4982
4983static bfd_boolean
4984arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4985{
4986 if (stub_type >= max_stub_type)
4987 abort (); /* Should be unreachable. */
4988
4ba2ef8f
TP		 4989 switch (stub_type)
4990 {
4991 case arm_stub_cmse_branch_thumb_only:
4992 return TRUE;
4993
4994 default:
4995 return FALSE;
4996 }
4997
4998 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4999}
5000
d7c5bd02
TP		 5001/* Returns the padding needed for the dedicated section used stubs of type
5002 STUB_TYPE. */
5003
5004static int
5005arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
5006{
5007 if (stub_type >= max_stub_type)
5008 abort (); /* Should be unreachable. */
5009
4ba2ef8f
TP		 5010 switch (stub_type)
5011 {
5012 case arm_stub_cmse_branch_thumb_only:
5013 return 32;
5014
5015 default:
5016 return 0;
5017 }
5018
5019 abort (); /* Should be unreachable. */
d7c5bd02
TP		 5020}
5021
0955507f
TP		 5022/* If veneers of type STUB_TYPE should go in a dedicated output section,
5023 returns the address of the hash table field in HTAB holding the offset at
5024 which new veneers should be layed out in the stub section. */
5025
5026static bfd_vma*
5027arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
5028 enum elf32_arm_stub_type stub_type)
5029{
5030 switch (stub_type)
5031 {
5032 case arm_stub_cmse_branch_thumb_only:
5033 return &htab->new_cmse_stub_offset;
5034
5035 default:
5036 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
5037 return NULL;
5038 }
5039}
5040
906e58ca
NC		 5041static bfd_boolean
5042arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5043 void * in_arg)
5044{
7a89b94e 5045#define MAXRELOCS 3
0955507f 5046 bfd_boolean removed_sg_veneer;
906e58ca 5047 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5048 struct elf32_arm_link_hash_table *globals;
906e58ca 5049 struct bfd_link_info *info;
906e58ca
NC		 5050 asection *stub_sec;
5051 bfd *stub_bfd;
906e58ca
NC		 5052 bfd_byte *loc;
5053 bfd_vma sym_value;
5054 int template_size;
5055 int size;
d3ce72d0 5056 const insn_sequence *template_sequence;
906e58ca 5057 int i;
48229727
JB		 5058 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5059 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5060 int nrelocs = 0;
0955507f 5061 int just_allocated = 0;
906e58ca
NC		 5062
5063 /* Massage our args to the form they really have. */
5064 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5065 info = (struct bfd_link_info *) in_arg;
5066
5067 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5068 if (globals == NULL)
5069 return FALSE;
906e58ca 5070
906e58ca
NC		 5071 stub_sec = stub_entry->stub_sec;
5072
4dfe6ac6 5073 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5074 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5075 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5076 return TRUE;
fe33d2fa 5077
0955507f
TP		 5078 /* Assign a slot at the end of section if none assigned yet. */
5079 if (stub_entry->stub_offset == (bfd_vma) -1)
5080 {
5081 stub_entry->stub_offset = stub_sec->size;
5082 just_allocated = 1;
5083 }
906e58ca
NC		 5084 loc = stub_sec->contents + stub_entry->stub_offset;
5085
5086 stub_bfd = stub_sec->owner;
5087
906e58ca
NC		 5088 /* This is the address of the stub destination. */
5089 sym_value = (stub_entry->target_value
5090 + stub_entry->target_section->output_offset
5091 + stub_entry->target_section->output_section->vma);
5092
d3ce72d0 5093 template_sequence = stub_entry->stub_template;
461a49ca 5094 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5095
5096 size = 0;
461a49ca 5097 for (i = 0; i < template_size; i++)
906e58ca 5098 {
d3ce72d0 5099 switch (template_sequence[i].type)
461a49ca
DJ		 5100 {
5101 case THUMB16_TYPE:
48229727 5102 {
d3ce72d0
NC		 5103 bfd_vma data = (bfd_vma) template_sequence[i].data;
5104 if (template_sequence[i].reloc_addend != 0)
48229727 5105 {
99059e56
RM		 5106 /* We've borrowed the reloc_addend field to mean we should
5107 insert a condition code into this (Thumb-1 branch)
5108 instruction. See THUMB16_BCOND_INSN. */
5109 BFD_ASSERT ((data & 0xff00) == 0xd000);
5110 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5111 }
fe33d2fa 5112 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5113 size += 2;
5114 }
461a49ca 5115 break;
906e58ca 5116
48229727 5117 case THUMB32_TYPE:
fe33d2fa
CL		 5118 bfd_put_16 (stub_bfd,
5119 (template_sequence[i].data >> 16) & 0xffff,
5120 loc + size);
5121 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5122 loc + size + 2);
99059e56
RM		 5123 if (template_sequence[i].r_type != R_ARM_NONE)
5124 {
5125 stub_reloc_idx[nrelocs] = i;
5126 stub_reloc_offset[nrelocs++] = size;
5127 }
5128 size += 4;
5129 break;
48229727 5130
461a49ca 5131 case ARM_TYPE:
fe33d2fa
CL		 5132 bfd_put_32 (stub_bfd, template_sequence[i].data,
5133 loc + size);
461a49ca
DJ		 5134 /* Handle cases where the target is encoded within the
5135 instruction. */
d3ce72d0 5136 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5137 {
48229727
JB		 5138 stub_reloc_idx[nrelocs] = i;
5139 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5140 }
5141 size += 4;
5142 break;
5143
5144 case DATA_TYPE:
d3ce72d0 5145 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5146 stub_reloc_idx[nrelocs] = i;
5147 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5148 size += 4;
5149 break;
5150
5151 default:
5152 BFD_FAIL ();
5153 return FALSE;
5154 }
906e58ca 5155 }
461a49ca 5156
0955507f
TP		 5157 if (just_allocated)
5158 stub_sec->size += size;
906e58ca 5159
461a49ca
DJ		 5160 /* Stub size has already been computed in arm_size_one_stub. Check
5161 consistency. */
5162 BFD_ASSERT (size == stub_entry->stub_size);
5163
906e58ca 5164 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5165 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5166 sym_value |= 1;
5167
0955507f
TP		 5168 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5169 to relocate in each stub. */
5170 removed_sg_veneer =
5171 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5172 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5173
48229727 5174 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5175 {
5176 Elf_Internal_Rela rel;
5177 bfd_boolean unresolved_reloc;
5178 char *error_message;
5179 bfd_vma points_to =
5180 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5181
5182 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5183 rel.r_info = ELF32_R_INFO (0,
5184 template_sequence[stub_reloc_idx[i]].r_type);
5185 rel.r_addend = 0;
5186
5187 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5188 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5189 template should refer back to the instruction after the original
5190 branch. We use target_section as Cortex-A8 erratum workaround stubs
5191 are only generated when both source and target are in the same
5192 section. */
5193 points_to = stub_entry->target_section->output_section->vma
5194 + stub_entry->target_section->output_offset
5195 + stub_entry->source_value;
5196
5197 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5198 (template_sequence[stub_reloc_idx[i]].r_type),
5199 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5200 points_to, info, stub_entry->target_section, "", STT_FUNC,
5201 stub_entry->branch_type,
5202 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5203 &error_message);
5204 }
906e58ca
NC		 5205
5206 return TRUE;
48229727 5207#undef MAXRELOCS
906e58ca
NC		 5208}
5209
48229727
JB		 5210/* Calculate the template, template size and instruction size for a stub.
5211 Return value is the instruction size. */
906e58ca 5212
48229727
JB		 5213static unsigned int
5214find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5215 const insn_sequence **stub_template,
5216 int *stub_template_size)
906e58ca 5217{
d3ce72d0 5218 const insn_sequence *template_sequence = NULL;
48229727
JB		 5219 int template_size = 0, i;
5220 unsigned int size;
906e58ca 5221
d3ce72d0 5222 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5223 if (stub_template)
5224 *stub_template = template_sequence;
5225
48229727 5226 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5227 if (stub_template_size)
5228 *stub_template_size = template_size;
906e58ca
NC		 5229
5230 size = 0;
461a49ca
DJ		 5231 for (i = 0; i < template_size; i++)
5232 {
d3ce72d0 5233 switch (template_sequence[i].type)
461a49ca
DJ		 5234 {
5235 case THUMB16_TYPE:
5236 size += 2;
5237 break;
5238
5239 case ARM_TYPE:
48229727 5240 case THUMB32_TYPE:
461a49ca
DJ		 5241 case DATA_TYPE:
5242 size += 4;
5243 break;
5244
5245 default:
5246 BFD_FAIL ();
2a229407 5247 return 0;
461a49ca
DJ		 5248 }
5249 }
5250
48229727
JB		 5251 return size;
5252}
5253
5254/* As above, but don't actually build the stub. Just bump offset so
5255 we know stub section sizes. */
5256
5257static bfd_boolean
5258arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5259 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5260{
5261 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5262 const insn_sequence *template_sequence;
48229727
JB		 5263 int template_size, size;
5264
5265 /* Massage our args to the form they really have. */
5266 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5267
5268 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5269 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5270
d3ce72d0 5271 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5272 &template_size);
5273
0955507f
TP		 5274 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5275 if (stub_entry->stub_template_size)
5276 {
5277 stub_entry->stub_size = size;
5278 stub_entry->stub_template = template_sequence;
5279 stub_entry->stub_template_size = template_size;
5280 }
5281
5282 /* Already accounted for. */
5283 if (stub_entry->stub_offset != (bfd_vma) -1)
5284 return TRUE;
461a49ca 5285
906e58ca
NC		 5286 size = (size + 7) & ~7;
5287 stub_entry->stub_sec->size += size;
461a49ca 5288
906e58ca
NC		 5289 return TRUE;
5290}
5291
5292/* External entry points for sizing and building linker stubs. */
5293
5294/* Set up various things so that we can make a list of input sections
5295 for each output section included in the link. Returns -1 on error,
5296 0 when no stubs will be needed, and 1 on success. */
5297
5298int
5299elf32_arm_setup_section_lists (bfd *output_bfd,
5300 struct bfd_link_info *info)
5301{
5302 bfd *input_bfd;
5303 unsigned int bfd_count;
7292b3ac 5304 unsigned int top_id, top_index;
906e58ca
NC		 5305 asection *section;
5306 asection **input_list, **list;
5307 bfd_size_type amt;
5308 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5309
4dfe6ac6
NC		 5310 if (htab == NULL)
5311 return 0;
906e58ca
NC		 5312 if (! is_elf_hash_table (htab))
5313 return 0;
5314
5315 /* Count the number of input BFDs and find the top input section id. */
5316 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5317 input_bfd != NULL;
c72f2fb2 5318 input_bfd = input_bfd->link.next)
906e58ca
NC		 5319 {
5320 bfd_count += 1;
5321 for (section = input_bfd->sections;
5322 section != NULL;
5323 section = section->next)
5324 {
5325 if (top_id < section->id)
5326 top_id = section->id;
5327 }
5328 }
5329 htab->bfd_count = bfd_count;
5330
5331 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5332 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5333 if (htab->stub_group == NULL)
5334 return -1;
fe33d2fa 5335 htab->top_id = top_id;
906e58ca
NC		 5336
5337 /* We can't use output_bfd->section_count here to find the top output
5338 section index as some sections may have been removed, and
5339 _bfd_strip_section_from_output doesn't renumber the indices. */
5340 for (section = output_bfd->sections, top_index = 0;
5341 section != NULL;
5342 section = section->next)
5343 {
5344 if (top_index < section->index)
5345 top_index = section->index;
5346 }
5347
5348 htab->top_index = top_index;
5349 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5350 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5351 htab->input_list = input_list;
5352 if (input_list == NULL)
5353 return -1;
5354
5355 /* For sections we aren't interested in, mark their entries with a
5356 value we can check later. */
5357 list = input_list + top_index;
5358 do
5359 *list = bfd_abs_section_ptr;
5360 while (list-- != input_list);
5361
5362 for (section = output_bfd->sections;
5363 section != NULL;
5364 section = section->next)
5365 {
5366 if ((section->flags & SEC_CODE) != 0)
5367 input_list[section->index] = NULL;
5368 }
5369
5370 return 1;
5371}
5372
5373/* The linker repeatedly calls this function for each input section,
5374 in the order that input sections are linked into output sections.
5375 Build lists of input sections to determine groupings between which
5376 we may insert linker stubs. */
5377
5378void
5379elf32_arm_next_input_section (struct bfd_link_info *info,
5380 asection *isec)
5381{
5382 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5383
4dfe6ac6
NC		 5384 if (htab == NULL)
5385 return;
5386
906e58ca
NC		 5387 if (isec->output_section->index <= htab->top_index)
5388 {
5389 asection **list = htab->input_list + isec->output_section->index;
5390
a7470592 5391 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5392 {
5393 /* Steal the link_sec pointer for our list. */
5394#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5395 /* This happens to make the list in reverse order,
07d72278 5396 which we reverse later. */
906e58ca
NC		 5397 PREV_SEC (isec) = *list;
5398 *list = isec;
5399 }
5400 }
5401}
5402
5403/* See whether we can group stub sections together. Grouping stub
5404 sections may result in fewer stubs. More importantly, we need to
07d72278 5405 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5406 .fini output sections respectively, because glibc splits the
5407 _init and _fini functions into multiple parts. Putting a stub in
5408 the middle of a function is not a good idea. */
5409
5410static void
5411group_sections (struct elf32_arm_link_hash_table *htab,
5412 bfd_size_type stub_group_size,
07d72278 5413 bfd_boolean stubs_always_after_branch)
906e58ca 5414{
07d72278 5415 asection **list = htab->input_list;
906e58ca
NC		 5416
5417 do
5418 {
5419 asection *tail = *list;
07d72278 5420 asection *head;
906e58ca
NC		 5421
5422 if (tail == bfd_abs_section_ptr)
5423 continue;
5424
07d72278
DJ		 5425 /* Reverse the list: we must avoid placing stubs at the
5426 beginning of the section because the beginning of the text
5427 section may be required for an interrupt vector in bare metal
5428 code. */
5429#define NEXT_SEC PREV_SEC
e780aef2
CL		 5430 head = NULL;
5431 while (tail != NULL)
99059e56
RM		 5432 {
5433 /* Pop from tail. */
5434 asection *item = tail;
5435 tail = PREV_SEC (item);
e780aef2 5436
99059e56
RM		 5437 /* Push on head. */
5438 NEXT_SEC (item) = head;
5439 head = item;
5440 }
07d72278
DJ		 5441
5442 while (head != NULL)
906e58ca
NC		 5443 {
5444 asection *curr;
07d72278 5445 asection *next;
e780aef2
CL		 5446 bfd_vma stub_group_start = head->output_offset;
5447 bfd_vma end_of_next;
906e58ca 5448
07d72278 5449 curr = head;
e780aef2 5450 while (NEXT_SEC (curr) != NULL)
8cd931b7 5451 {
e780aef2
CL		 5452 next = NEXT_SEC (curr);
5453 end_of_next = next->output_offset + next->size;
5454 if (end_of_next - stub_group_start >= stub_group_size)
5455 /* End of NEXT is too far from start, so stop. */
8cd931b7 5456 break;
e780aef2
CL		 5457 /* Add NEXT to the group. */
5458 curr = next;
8cd931b7 5459 }
906e58ca 5460
07d72278 5461 /* OK, the size from the start to the start of CURR is less
906e58ca 5462 than stub_group_size and thus can be handled by one stub
07d72278 5463 section. (Or the head section is itself larger than
906e58ca
NC		 5464 stub_group_size, in which case we may be toast.)
5465 We should really be keeping track of the total size of
5466 stubs added here, as stubs contribute to the final output
7fb9f789 5467 section size. */
906e58ca
NC		 5468 do
5469 {
07d72278 5470 next = NEXT_SEC (head);
906e58ca 5471 /* Set up this stub group. */
07d72278 5472 htab->stub_group[head->id].link_sec = curr;
906e58ca 5473 }
07d72278 5474 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5475
5476 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5477 bytes after the stub section can be handled by it too. */
5478 if (!stubs_always_after_branch)
906e58ca 5479 {
e780aef2
CL		 5480 stub_group_start = curr->output_offset + curr->size;
5481
8cd931b7 5482 while (next != NULL)
906e58ca 5483 {
e780aef2
CL		 5484 end_of_next = next->output_offset + next->size;
5485 if (end_of_next - stub_group_start >= stub_group_size)
5486 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5487 break;
e780aef2 5488 /* Add NEXT to the stub group. */
07d72278
DJ		 5489 head = next;
5490 next = NEXT_SEC (head);
5491 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5492 }
5493 }
07d72278 5494 head = next;
906e58ca
NC		 5495 }
5496 }
07d72278 5497 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5498
5499 free (htab->input_list);
5500#undef PREV_SEC
07d72278 5501#undef NEXT_SEC
906e58ca
NC		 5502}
5503
48229727
JB		 5504/* Comparison function for sorting/searching relocations relating to Cortex-A8
5505 erratum fix. */
5506
5507static int
5508a8_reloc_compare (const void *a, const void *b)
5509{
21d799b5
NC		 5510 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5511 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5512
5513 if (ra->from < rb->from)
5514 return -1;
5515 else if (ra->from > rb->from)
5516 return 1;
5517 else
5518 return 0;
5519}
5520
5521static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5522 const char *, char **);
5523
5524/* Helper function to scan code for sequences which might trigger the Cortex-A8
5525 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5526 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5527 otherwise. */
5528
81694485
NC		 5529static bfd_boolean
5530cortex_a8_erratum_scan (bfd *input_bfd,
5531 struct bfd_link_info *info,
48229727
JB		 5532 struct a8_erratum_fix **a8_fixes_p,
5533 unsigned int *num_a8_fixes_p,
5534 unsigned int *a8_fix_table_size_p,
5535 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5536 unsigned int num_a8_relocs,
5537 unsigned prev_num_a8_fixes,
5538 bfd_boolean *stub_changed_p)
48229727
JB		 5539{
5540 asection *section;
5541 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5542 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5543 unsigned int num_a8_fixes = *num_a8_fixes_p;
5544 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5545
4dfe6ac6
NC		 5546 if (htab == NULL)
5547 return FALSE;
5548
48229727
JB		 5549 for (section = input_bfd->sections;
5550 section != NULL;
5551 section = section->next)
5552 {
5553 bfd_byte *contents = NULL;
5554 struct _arm_elf_section_data *sec_data;
5555 unsigned int span;
5556 bfd_vma base_vma;
5557
5558 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5559 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5560 || (section->flags & SEC_EXCLUDE) != 0
5561 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5562 || (section->output_section == bfd_abs_section_ptr))
5563 continue;
48229727
JB		 5564
5565 base_vma = section->output_section->vma + section->output_offset;
5566
5567 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5568 contents = elf_section_data (section)->this_hdr.contents;
48229727 5569 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5570 return TRUE;
48229727
JB		 5571
5572 sec_data = elf32_arm_section_data (section);
5573
5574 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5575 {
5576 unsigned int span_start = sec_data->map[span].vma;
5577 unsigned int span_end = (span == sec_data->mapcount - 1)
5578 ? section->size : sec_data->map[span + 1].vma;
5579 unsigned int i;
5580 char span_type = sec_data->map[span].type;
5581 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5582
5583 if (span_type != 't')
5584 continue;
5585
5586 /* Span is entirely within a single 4KB region: skip scanning. */
5587 if (((base_vma + span_start) & ~0xfff)
48229727 5588 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5589 continue;
5590
5591 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5592
5593 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5594 * The branch target is in the same 4KB region as the
5595 first half of the branch.
5596 * The instruction before the branch is a 32-bit
5597 length non-branch instruction. */
5598 for (i = span_start; i < span_end;)
5599 {
5600 unsigned int insn = bfd_getl16 (&contents[i]);
5601 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5602 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5603
99059e56
RM		 5604 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5605 insn_32bit = TRUE;
48229727
JB		 5606
5607 if (insn_32bit)
99059e56
RM		 5608 {
5609 /* Load the rest of the insn (in manual-friendly order). */
5610 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5611
5612 /* Encoding T4: B<c>.W. */
5613 is_b = (insn & 0xf800d000) == 0xf0009000;
5614 /* Encoding T1: BL<c>.W. */
5615 is_bl = (insn & 0xf800d000) == 0xf000d000;
5616 /* Encoding T2: BLX<c>.W. */
5617 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5618 /* Encoding T3: B<c>.W (not permitted in IT block). */
5619 is_bcc = (insn & 0xf800d000) == 0xf0008000
5620 && (insn & 0x07f00000) != 0x03800000;
5621 }
5622
5623 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5624
99059e56 5625 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5626 && insn_32bit
5627 && is_32bit_branch
5628 && last_was_32bit
5629 && ! last_was_branch)
99059e56
RM		 5630 {
5631 bfd_signed_vma offset = 0;
5632 bfd_boolean force_target_arm = FALSE;
48229727 5633 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5634 bfd_vma target;
5635 enum elf32_arm_stub_type stub_type = arm_stub_none;
5636 struct a8_erratum_reloc key, *found;
5637 bfd_boolean use_plt = FALSE;
48229727 5638
99059e56
RM		 5639 key.from = base_vma + i;
5640 found = (struct a8_erratum_reloc *)
5641 bsearch (&key, a8_relocs, num_a8_relocs,
5642 sizeof (struct a8_erratum_reloc),
5643 &a8_reloc_compare);
48229727
JB		 5644
5645 if (found)
5646 {
5647 char *error_message = NULL;
5648 struct elf_link_hash_entry *entry;
5649
5650 /* We don't care about the error returned from this
99059e56 5651 function, only if there is glue or not. */
48229727
JB		 5652 entry = find_thumb_glue (info, found->sym_name,
5653 &error_message);
5654
5655 if (entry)
5656 found->non_a8_stub = TRUE;
5657
92750f34 5658 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5659 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5660 && found->hash->root.plt.offset != (bfd_vma) -1)
5661 use_plt = TRUE;
5662
5663 if (found->r_type == R_ARM_THM_CALL)
5664 {
35fc36a8
RS		 5665 if (found->branch_type == ST_BRANCH_TO_ARM
5666 || use_plt)
92750f34
DJ		 5667 force_target_arm = TRUE;
5668 else
5669 force_target_thumb = TRUE;
5670 }
48229727
JB		 5671 }
5672
99059e56 5673 /* Check if we have an offending branch instruction. */
48229727
JB		 5674
5675 if (found && found->non_a8_stub)
5676 /* We've already made a stub for this instruction, e.g.
5677 it's a long branch or a Thumb->ARM stub. Assume that
5678 stub will suffice to work around the A8 erratum (see
5679 setting of always_after_branch above). */
5680 ;
99059e56
RM		 5681 else if (is_bcc)
5682 {
5683 offset = (insn & 0x7ff) << 1;
5684 offset |= (insn & 0x3f0000) >> 4;
5685 offset |= (insn & 0x2000) ? 0x40000 : 0;
5686 offset |= (insn & 0x800) ? 0x80000 : 0;
5687 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5688 if (offset & 0x100000)
5689 offset |= ~ ((bfd_signed_vma) 0xfffff);
5690 stub_type = arm_stub_a8_veneer_b_cond;
5691 }
5692 else if (is_b || is_bl || is_blx)
5693 {
5694 int s = (insn & 0x4000000) != 0;
5695 int j1 = (insn & 0x2000) != 0;
5696 int j2 = (insn & 0x800) != 0;
5697 int i1 = !(j1 ^ s);
5698 int i2 = !(j2 ^ s);
5699
5700 offset = (insn & 0x7ff) << 1;
5701 offset |= (insn & 0x3ff0000) >> 4;
5702 offset |= i2 << 22;
5703 offset |= i1 << 23;
5704 offset |= s << 24;
5705 if (offset & 0x1000000)
5706 offset |= ~ ((bfd_signed_vma) 0xffffff);
5707
5708 if (is_blx)
5709 offset &= ~ ((bfd_signed_vma) 3);
5710
5711 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5712 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5713 }
5714
5715 if (stub_type != arm_stub_none)
5716 {
5717 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5718
5719 /* The original instruction is a BL, but the target is
99059e56 5720 an ARM instruction. If we were not making a stub,
48229727
JB		 5721 the BL would have been converted to a BLX. Use the
5722 BLX stub instead in that case. */
5723 if (htab->use_blx && force_target_arm
5724 && stub_type == arm_stub_a8_veneer_bl)
5725 {
5726 stub_type = arm_stub_a8_veneer_blx;
5727 is_blx = TRUE;
5728 is_bl = FALSE;
5729 }
5730 /* Conversely, if the original instruction was
5731 BLX but the target is Thumb mode, use the BL
5732 stub. */
5733 else if (force_target_thumb
5734 && stub_type == arm_stub_a8_veneer_blx)
5735 {
5736 stub_type = arm_stub_a8_veneer_bl;
5737 is_blx = FALSE;
5738 is_bl = TRUE;
5739 }
5740
99059e56
RM		 5741 if (is_blx)
5742 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5743
99059e56
RM		 5744 /* If we found a relocation, use the proper destination,
5745 not the offset in the (unrelocated) instruction.
48229727
JB		 5746 Note this is always done if we switched the stub type
5747 above. */
99059e56
RM		 5748 if (found)
5749 offset =
81694485 5750 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5751
99059e56
RM		 5752 /* If the stub will use a Thumb-mode branch to a
5753 PLT target, redirect it to the preceding Thumb
5754 entry point. */
5755 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5756 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5757
99059e56 5758 target = pc_for_insn + offset;
48229727 5759
99059e56
RM		 5760 /* The BLX stub is ARM-mode code. Adjust the offset to
5761 take the different PC value (+8 instead of +4) into
48229727 5762 account. */
99059e56
RM		 5763 if (stub_type == arm_stub_a8_veneer_blx)
5764 offset += 4;
5765
5766 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5767 {
5768 char *stub_name = NULL;
5769
5770 if (num_a8_fixes == a8_fix_table_size)
5771 {
5772 a8_fix_table_size *= 2;
5773 a8_fixes = (struct a8_erratum_fix *)
5774 bfd_realloc (a8_fixes,
5775 sizeof (struct a8_erratum_fix)
5776 * a8_fix_table_size);
5777 }
48229727 5778
eb7c4339
NS		 5779 if (num_a8_fixes < prev_num_a8_fixes)
5780 {
5781 /* If we're doing a subsequent scan,
5782 check if we've found the same fix as
5783 before, and try and reuse the stub
5784 name. */
5785 stub_name = a8_fixes[num_a8_fixes].stub_name;
5786 if ((a8_fixes[num_a8_fixes].section != section)
5787 || (a8_fixes[num_a8_fixes].offset != i))
5788 {
5789 free (stub_name);
5790 stub_name = NULL;
5791 *stub_changed_p = TRUE;
5792 }
5793 }
5794
5795 if (!stub_name)
5796 {
21d799b5 5797 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5798 if (stub_name != NULL)
5799 sprintf (stub_name, "%x:%x", section->id, i);
5800 }
48229727 5801
99059e56
RM		 5802 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5803 a8_fixes[num_a8_fixes].section = section;
5804 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5805 a8_fixes[num_a8_fixes].target_offset =
5806 target - base_vma;
99059e56
RM		 5807 a8_fixes[num_a8_fixes].orig_insn = insn;
5808 a8_fixes[num_a8_fixes].stub_name = stub_name;
5809 a8_fixes[num_a8_fixes].stub_type = stub_type;
5810 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5811 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5812
99059e56
RM		 5813 num_a8_fixes++;
5814 }
5815 }
5816 }
48229727 5817
99059e56
RM		 5818 i += insn_32bit ? 4 : 2;
5819 last_was_32bit = insn_32bit;
48229727 5820 last_was_branch = is_32bit_branch;
99059e56
RM		 5821 }
5822 }
48229727
JB		 5823
5824 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5825 free (contents);
48229727 5826 }
fe33d2fa 5827
48229727
JB		 5828 *a8_fixes_p = a8_fixes;
5829 *num_a8_fixes_p = num_a8_fixes;
5830 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5831
81694485 5832 return FALSE;
48229727
JB		 5833}
5834
b715f643
TP		 5835/* Create or update a stub entry depending on whether the stub can already be
5836 found in HTAB. The stub is identified by:
5837 - its type STUB_TYPE
5838 - its source branch (note that several can share the same stub) whose
5839 section and relocation (if any) are given by SECTION and IRELA
5840 respectively
5841 - its target symbol whose input section, hash, name, value and branch type
5842 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5843 respectively
5844
5845 If found, the value of the stub's target symbol is updated from SYM_VALUE
5846 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5847 TRUE and the stub entry is initialized.
5848
0955507f
TP		 5849 Returns the stub that was created or updated, or NULL if an error
5850 occurred. */
b715f643 5851
0955507f 5852static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5853elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5854 enum elf32_arm_stub_type stub_type, asection *section,
5855 Elf_Internal_Rela *irela, asection *sym_sec,
5856 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5857 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5858 bfd_boolean *new_stub)
5859{
5860 const asection *id_sec;
5861 char *stub_name;
5862 struct elf32_arm_stub_hash_entry *stub_entry;
5863 unsigned int r_type;
4f4faa4d 5864 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5865
5866 BFD_ASSERT (stub_type != arm_stub_none);
5867 *new_stub = FALSE;
5868
4f4faa4d
TP		 5869 if (sym_claimed)
5870 stub_name = sym_name;
5871 else
5872 {
5873 BFD_ASSERT (irela);
5874 BFD_ASSERT (section);
c2abbbeb 5875 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5876
4f4faa4d
TP		 5877 /* Support for grouping stub sections. */
5878 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5879
4f4faa4d
TP		 5880 /* Get the name of this stub. */
5881 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5882 stub_type);
5883 if (!stub_name)
0955507f 5884 return NULL;
4f4faa4d 5885 }
b715f643
TP		 5886
5887 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5888 FALSE);
5889 /* The proper stub has already been created, just update its value. */
5890 if (stub_entry != NULL)
5891 {
4f4faa4d
TP		 5892 if (!sym_claimed)
5893 free (stub_name);
b715f643 5894 stub_entry->target_value = sym_value;
0955507f 5895 return stub_entry;
b715f643
TP		 5896 }
5897
daa4adae 5898 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5899 if (stub_entry == NULL)
5900 {
4f4faa4d
TP		 5901 if (!sym_claimed)
5902 free (stub_name);
0955507f 5903 return NULL;
b715f643
TP		 5904 }
5905
5906 stub_entry->target_value = sym_value;
5907 stub_entry->target_section = sym_sec;
5908 stub_entry->stub_type = stub_type;
5909 stub_entry->h = hash;
5910 stub_entry->branch_type = branch_type;
5911
4f4faa4d
TP		 5912 if (sym_claimed)
5913 stub_entry->output_name = sym_name;
5914 else
b715f643 5915 {
4f4faa4d
TP		 5916 if (sym_name == NULL)
5917 sym_name = "unnamed";
5918 stub_entry->output_name = (char *)
5919 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5920 + strlen (sym_name));
5921 if (stub_entry->output_name == NULL)
5922 {
5923 free (stub_name);
0955507f 5924 return NULL;
4f4faa4d 5925 }
b715f643 5926
4f4faa4d
TP		 5927 /* For historical reasons, use the existing names for ARM-to-Thumb and
5928 Thumb-to-ARM stubs. */
5929 r_type = ELF32_R_TYPE (irela->r_info);
5930 if ((r_type == (unsigned int) R_ARM_THM_CALL
5931 || r_type == (unsigned int) R_ARM_THM_JUMP24
5932 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5933 && branch_type == ST_BRANCH_TO_ARM)
5934 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5935 else if ((r_type == (unsigned int) R_ARM_CALL
5936 || r_type == (unsigned int) R_ARM_JUMP24)
5937 && branch_type == ST_BRANCH_TO_THUMB)
5938 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5939 else
5940 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5941 }
b715f643
TP		 5942
5943 *new_stub = TRUE;
0955507f 5944 return stub_entry;
b715f643
TP		 5945}
5946
4ba2ef8f
TP		 5947/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5948 gateway veneer to transition from non secure to secure state and create them
5949 accordingly.
5950
5951 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5952 defines the conditions that govern Secure Gateway veneer creation for a
5953 given symbol <SYM> as follows:
5954 - it has function type
5955 - it has non local binding
5956 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5957 same type, binding and value as <SYM> (called normal symbol).
5958 An entry function can handle secure state transition itself in which case
5959 its special symbol would have a different value from the normal symbol.
5960
5961 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5962 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5963 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5964 created.
4ba2ef8f 5965
0955507f 5966 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5967
5968static bfd_boolean
5969cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5970 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5971 int *cmse_stub_created)
4ba2ef8f
TP		 5972{
5973 const struct elf_backend_data *bed;
5974 Elf_Internal_Shdr *symtab_hdr;
5975 unsigned i, j, sym_count, ext_start;
5976 Elf_Internal_Sym *cmse_sym, *local_syms;
5977 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5978 enum arm_st_branch_type branch_type;
5979 char *sym_name, *lsym_name;
5980 bfd_vma sym_value;
5981 asection *section;
0955507f
TP		 5982 struct elf32_arm_stub_hash_entry *stub_entry;
5983 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5984
5985 bed = get_elf_backend_data (input_bfd);
5986 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5987 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5988 ext_start = symtab_hdr->sh_info;
5989 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5990 && out_attr[Tag_CPU_arch_profile].i == 'M');
5991
5992 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5993 if (local_syms == NULL)
5994 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5995 symtab_hdr->sh_info, 0, NULL, NULL,
5996 NULL);
5997 if (symtab_hdr->sh_info && local_syms == NULL)
5998 return FALSE;
5999
6000 /* Scan symbols. */
6001 for (i = 0; i < sym_count; i++)
6002 {
6003 cmse_invalid = FALSE;
6004
6005 if (i < ext_start)
6006 {
6007 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 6008 sym_name = bfd_elf_string_from_elf_section (input_bfd,
6009 symtab_hdr->sh_link,
6010 cmse_sym->st_name);
baf46cd7
AM		 6011 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
6012 continue;
6013
4ba2ef8f
TP		 6014 /* Special symbol with local binding. */
6015 cmse_invalid = TRUE;
6016 }
6017 else
6018 {
6019 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
6020 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 6021 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 6022 continue;
6023
6024 /* Special symbol has incorrect binding or type. */
6025 if ((cmse_hash->root.root.type != bfd_link_hash_defined
6026 && cmse_hash->root.root.type != bfd_link_hash_defweak)
6027 || cmse_hash->root.type != STT_FUNC)
6028 cmse_invalid = TRUE;
6029 }
6030
6031 if (!is_v8m)
6032 {
90b6238f
AM		 6033 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
6034 "ARMv8-M architecture or later"),
4eca0228 6035 input_bfd, sym_name);
4ba2ef8f
TP		 6036 is_v8m = TRUE; /* Avoid multiple warning. */
6037 ret = FALSE;
6038 }
6039
6040 if (cmse_invalid)
6041 {
90b6238f
AM		 6042 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6043 " a global or weak function symbol"),
4eca0228 6044 input_bfd, sym_name);
4ba2ef8f
TP		 6045 ret = FALSE;
6046 if (i < ext_start)
6047 continue;
6048 }
6049
6050 sym_name += strlen (CMSE_PREFIX);
6051 hash = (struct elf32_arm_link_hash_entry *)
6052 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6053
6054 /* No associated normal symbol or it is neither global nor weak. */
6055 if (!hash
6056 || (hash->root.root.type != bfd_link_hash_defined
6057 && hash->root.root.type != bfd_link_hash_defweak)
6058 || hash->root.type != STT_FUNC)
6059 {
6060 /* Initialize here to avoid warning about use of possibly
6061 uninitialized variable. */
6062 j = 0;
6063
6064 if (!hash)
6065 {
6066 /* Searching for a normal symbol with local binding. */
6067 for (; j < ext_start; j++)
6068 {
6069 lsym_name =
6070 bfd_elf_string_from_elf_section (input_bfd,
6071 symtab_hdr->sh_link,
6072 local_syms[j].st_name);
6073 if (!strcmp (sym_name, lsym_name))
6074 break;
6075 }
6076 }
6077
6078 if (hash || j < ext_start)
6079 {
4eca0228 6080 _bfd_error_handler
90b6238f
AM		 6081 (_("%pB: invalid standard symbol `%s'; it must be "
6082 "a global or weak function symbol"),
6083 input_bfd, sym_name);
4ba2ef8f
TP		 6084 }
6085 else
4eca0228 6086 _bfd_error_handler
90b6238f 6087 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6088 ret = FALSE;
6089 if (!hash)
6090 continue;
6091 }
6092
6093 sym_value = hash->root.root.u.def.value;
6094 section = hash->root.root.u.def.section;
6095
6096 if (cmse_hash->root.root.u.def.section != section)
6097 {
4eca0228 6098 _bfd_error_handler
90b6238f 6099 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6100 input_bfd, sym_name);
6101 ret = FALSE;
6102 }
6103 if (cmse_hash->root.root.u.def.value != sym_value)
6104 continue; /* Ignore: could be an entry function starting with SG. */
6105
6106 /* If this section is a link-once section that will be discarded, then
6107 don't create any stubs. */
6108 if (section->output_section == NULL)
6109 {
4eca0228 6110 _bfd_error_handler
90b6238f 6111 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6112 continue;
6113 }
6114
6115 if (hash->root.size == 0)
6116 {
4eca0228 6117 _bfd_error_handler
90b6238f 6118 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6119 ret = FALSE;
6120 }
6121
6122 if (!ret)
6123 continue;
6124 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6125 stub_entry
4ba2ef8f
TP		 6126 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6127 NULL, NULL, section, hash, sym_name,
6128 sym_value, branch_type, &new_stub);
6129
0955507f 6130 if (stub_entry == NULL)
4ba2ef8f
TP		 6131 ret = FALSE;
6132 else
6133 {
6134 BFD_ASSERT (new_stub);
0955507f 6135 (*cmse_stub_created)++;
4ba2ef8f
TP		 6136 }
6137 }
6138
6139 if (!symtab_hdr->contents)
6140 free (local_syms);
6141 return ret;
6142}
6143
0955507f
TP		 6144/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6145 code entry function, ie can be called from non secure code without using a
6146 veneer. */
6147
6148static bfd_boolean
6149cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6150{
42484486 6151 bfd_byte contents[4];
0955507f
TP		 6152 uint32_t first_insn;
6153 asection *section;
6154 file_ptr offset;
6155 bfd *abfd;
6156
6157 /* Defined symbol of function type. */
6158 if (hash->root.root.type != bfd_link_hash_defined
6159 && hash->root.root.type != bfd_link_hash_defweak)
6160 return FALSE;
6161 if (hash->root.type != STT_FUNC)
6162 return FALSE;
6163
6164 /* Read first instruction. */
6165 section = hash->root.root.u.def.section;
6166 abfd = section->owner;
6167 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6168 if (!bfd_get_section_contents (abfd, section, contents, offset,
6169 sizeof (contents)))
0955507f
TP		 6170 return FALSE;
6171
42484486
TP		 6172 first_insn = bfd_get_32 (abfd, contents);
6173
6174 /* Starts by SG instruction. */
0955507f
TP		 6175 return first_insn == 0xe97fe97f;
6176}
6177
6178/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6179 secure gateway veneers (ie. the veneers was not in the input import library)
6180 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6181
6182static bfd_boolean
6183arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6184{
6185 struct elf32_arm_stub_hash_entry *stub_entry;
6186 struct bfd_link_info *info;
6187
6188 /* Massage our args to the form they really have. */
6189 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6190 info = (struct bfd_link_info *) gen_info;
6191
6192 if (info->out_implib_bfd)
6193 return TRUE;
6194
6195 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6196 return TRUE;
6197
6198 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6199 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6200
6201 return TRUE;
6202}
6203
6204/* Set offset of each secure gateway veneers so that its address remain
6205 identical to the one in the input import library referred by
6206 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6207 (present in input import library but absent from the executable being
6208 linked) or if new veneers appeared and there is no output import library
6209 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6210 number of secure gateway veneers found in the input import library.
6211
6212 The function returns whether an error occurred. If no error occurred,
6213 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6214 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6215 veneer observed set for new veneers to be layed out after. */
6216
6217static bfd_boolean
6218set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6219 struct elf32_arm_link_hash_table *htab,
6220 int *cmse_stub_created)
6221{
6222 long symsize;
6223 char *sym_name;
6224 flagword flags;
6225 long i, symcount;
6226 bfd *in_implib_bfd;
6227 asection *stub_out_sec;
6228 bfd_boolean ret = TRUE;
6229 Elf_Internal_Sym *intsym;
6230 const char *out_sec_name;
6231 bfd_size_type cmse_stub_size;
6232 asymbol **sympp = NULL, *sym;
6233 struct elf32_arm_link_hash_entry *hash;
6234 const insn_sequence *cmse_stub_template;
6235 struct elf32_arm_stub_hash_entry *stub_entry;
6236 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6237 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6238 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6239
6240 /* No input secure gateway import library. */
6241 if (!htab->in_implib_bfd)
6242 return TRUE;
6243
6244 in_implib_bfd = htab->in_implib_bfd;
6245 if (!htab->cmse_implib)
6246 {
871b3ab2 6247 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6248 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6249 return FALSE;
6250 }
6251
6252 /* Get symbol table size. */
6253 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6254 if (symsize < 0)
6255 return FALSE;
6256
6257 /* Read in the input secure gateway import library's symbol table. */
9a733151
AM		 6258 sympp = (asymbol **) bfd_malloc (symsize);
6259 if (sympp == NULL)
6260 return FALSE;
6261
0955507f
TP		 6262 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6263 if (symcount < 0)
6264 {
6265 ret = FALSE;
6266 goto free_sym_buf;
6267 }
6268
6269 htab->new_cmse_stub_offset = 0;
6270 cmse_stub_size =
6271 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6272 &cmse_stub_template,
6273 &cmse_stub_template_size);
6274 out_sec_name =
6275 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6276 stub_out_sec =
6277 bfd_get_section_by_name (htab->obfd, out_sec_name);
6278 if (stub_out_sec != NULL)
6279 cmse_stub_sec_vma = stub_out_sec->vma;
6280
6281 /* Set addresses of veneers mentionned in input secure gateway import
6282 library's symbol table. */
6283 for (i = 0; i < symcount; i++)
6284 {
6285 sym = sympp[i];
6286 flags = sym->flags;
6287 sym_name = (char *) bfd_asymbol_name (sym);
6288 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6289
6290 if (sym->section != bfd_abs_section_ptr
6291 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6292 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6293 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6294 != ST_BRANCH_TO_THUMB))
6295 {
90b6238f
AM		 6296 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6297 "symbol should be absolute, global and "
6298 "refer to Thumb functions"),
4eca0228 6299 in_implib_bfd, sym_name);
0955507f
TP		 6300 ret = FALSE;
6301 continue;
6302 }
6303
6304 veneer_value = bfd_asymbol_value (sym);
6305 stub_offset = veneer_value - cmse_stub_sec_vma;
6306 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6307 FALSE, FALSE);
6308 hash = (struct elf32_arm_link_hash_entry *)
6309 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6310
6311 /* Stub entry should have been created by cmse_scan or the symbol be of
6312 a secure function callable from non secure code. */
6313 if (!stub_entry && !hash)
6314 {
6315 bfd_boolean new_stub;
6316
4eca0228 6317 _bfd_error_handler
90b6238f 6318 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6319 hash = (struct elf32_arm_link_hash_entry *)
6320 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6321 stub_entry
6322 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6323 NULL, NULL, bfd_abs_section_ptr, hash,
6324 sym_name, veneer_value,
6325 ST_BRANCH_TO_THUMB, &new_stub);
6326 if (stub_entry == NULL)
6327 ret = FALSE;
6328 else
6329 {
6330 BFD_ASSERT (new_stub);
6331 new_cmse_stubs_created++;
6332 (*cmse_stub_created)++;
6333 }
6334 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6335 stub_entry->stub_offset = stub_offset;
6336 }
6337 /* Symbol found is not callable from non secure code. */
6338 else if (!stub_entry)
6339 {
6340 if (!cmse_entry_fct_p (hash))
6341 {
90b6238f 6342 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6343 sym_name);
0955507f
TP		 6344 ret = FALSE;
6345 }
6346 continue;
6347 }
6348 else
6349 {
6350 /* Only stubs for SG veneers should have been created. */
6351 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6352
6353 /* Check visibility hasn't changed. */
6354 if (!!(flags & BSF_GLOBAL)
6355 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6356 _bfd_error_handler
90b6238f 6357 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6358 sym_name);
6359
6360 stub_entry->stub_offset = stub_offset;
6361 }
6362
6363 /* Size should match that of a SG veneer. */
6364 if (intsym->st_size != cmse_stub_size)
6365 {
90b6238f 6366 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6367 in_implib_bfd, sym_name);
0955507f
TP		 6368 ret = FALSE;
6369 }
6370
6371 /* Previous veneer address is before current SG veneer section. */
6372 if (veneer_value < cmse_stub_sec_vma)
6373 {
6374 /* Avoid offset underflow. */
6375 if (stub_entry)
6376 stub_entry->stub_offset = 0;
6377 stub_offset = 0;
6378 ret = FALSE;
6379 }
6380
6381 /* Complain if stub offset not a multiple of stub size. */
6382 if (stub_offset % cmse_stub_size)
6383 {
4eca0228 6384 _bfd_error_handler
90b6238f
AM		 6385 (_("offset of veneer for entry function `%s' not a multiple of "
6386 "its size"), sym_name);
0955507f
TP		 6387 ret = FALSE;
6388 }
6389
6390 if (!ret)
6391 continue;
6392
6393 new_cmse_stubs_created--;
6394 if (veneer_value < cmse_stub_array_start)
6395 cmse_stub_array_start = veneer_value;
6396 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6397 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6398 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6399 }
6400
6401 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6402 {
6403 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6404 _bfd_error_handler
0955507f
TP		 6405 (_("new entry function(s) introduced but no output import library "
6406 "specified:"));
6407 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6408 }
6409
6410 if (cmse_stub_array_start != cmse_stub_sec_vma)
6411 {
4eca0228 6412 _bfd_error_handler
90b6238f 6413 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6414 out_sec_name);
6415 ret = FALSE;
6416 }
6417
6418free_sym_buf:
6419 free (sympp);
6420 return ret;
6421}
6422
906e58ca
NC		 6423/* Determine and set the size of the stub section for a final link.
6424
6425 The basic idea here is to examine all the relocations looking for
6426 PC-relative calls to a target that is unreachable with a "bl"
6427 instruction. */
6428
6429bfd_boolean
6430elf32_arm_size_stubs (bfd *output_bfd,
6431 bfd *stub_bfd,
6432 struct bfd_link_info *info,
6433 bfd_signed_vma group_size,
7a89b94e 6434 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6435 asection *,
7a89b94e 6436 unsigned int),
906e58ca
NC		 6437 void (*layout_sections_again) (void))
6438{
0955507f 6439 bfd_boolean ret = TRUE;
4ba2ef8f 6440 obj_attribute *out_attr;
0955507f 6441 int cmse_stub_created = 0;
906e58ca 6442 bfd_size_type stub_group_size;
4ba2ef8f 6443 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6444 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6445 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6446 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6447 struct a8_erratum_reloc *a8_relocs = NULL;
6448 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6449
4dfe6ac6
NC		 6450 if (htab == NULL)
6451 return FALSE;
6452
48229727
JB		 6453 if (htab->fix_cortex_a8)
6454 {
21d799b5 6455 a8_fixes = (struct a8_erratum_fix *)
99059e56 6456 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6457 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6458 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6459 }
906e58ca
NC		 6460
6461 /* Propagate mach to stub bfd, because it may not have been
6462 finalized when we created stub_bfd. */
6463 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6464 bfd_get_mach (output_bfd));
6465
6466 /* Stash our params away. */
6467 htab->stub_bfd = stub_bfd;
6468 htab->add_stub_section = add_stub_section;
6469 htab->layout_sections_again = layout_sections_again;
07d72278 6470 stubs_always_after_branch = group_size < 0;
48229727 6471
4ba2ef8f
TP		 6472 out_attr = elf_known_obj_attributes_proc (output_bfd);
6473 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6474
48229727
JB		 6475 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6476 as the first half of a 32-bit branch straddling two 4K pages. This is a
6477 crude way of enforcing that. */
6478 if (htab->fix_cortex_a8)
6479 stubs_always_after_branch = 1;
6480
906e58ca
NC		 6481 if (group_size < 0)
6482 stub_group_size = -group_size;
6483 else
6484 stub_group_size = group_size;
6485
6486 if (stub_group_size == 1)
6487 {
6488 /* Default values. */
6489 /* Thumb branch range is +-4MB has to be used as the default
6490 maximum size (a given section can contain both ARM and Thumb
6491 code, so the worst case has to be taken into account).
6492
6493 This value is 24K less than that, which allows for 2025
6494 12-byte stubs. If we exceed that, then we will fail to link.
6495 The user will have to relink with an explicit group size
6496 option. */
6497 stub_group_size = 4170000;
6498 }
6499
07d72278 6500 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6501
3ae046cc
NS		 6502 /* If we're applying the cortex A8 fix, we need to determine the
6503 program header size now, because we cannot change it later --
6504 that could alter section placements. Notice the A8 erratum fix
6505 ends up requiring the section addresses to remain unchanged
6506 modulo the page size. That's something we cannot represent
6507 inside BFD, and we don't want to force the section alignment to
6508 be the page size. */
6509 if (htab->fix_cortex_a8)
6510 (*htab->layout_sections_again) ();
6511
906e58ca
NC		 6512 while (1)
6513 {
6514 bfd *input_bfd;
6515 unsigned int bfd_indx;
6516 asection *stub_sec;
d7c5bd02 6517 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6518 bfd_boolean stub_changed = FALSE;
6519 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6520
48229727 6521 num_a8_fixes = 0;
906e58ca
NC		 6522 for (input_bfd = info->input_bfds, bfd_indx = 0;
6523 input_bfd != NULL;
c72f2fb2 6524 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6525 {
6526 Elf_Internal_Shdr *symtab_hdr;
6527 asection *section;
6528 Elf_Internal_Sym *local_syms = NULL;
6529
73d5efd7
AM		 6530 if (!is_arm_elf (input_bfd))
6531 continue;
6532 if ((input_bfd->flags & DYNAMIC) != 0
6533 && (elf_sym_hashes (input_bfd) == NULL
6534 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0))
99059e56 6535 continue;
adbcc655 6536
48229727
JB		 6537 num_a8_relocs = 0;
6538
906e58ca
NC		 6539 /* We'll need the symbol table in a second. */
6540 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6541 if (symtab_hdr->sh_info == 0)
6542 continue;
6543
4ba2ef8f
TP		 6544 /* Limit scan of symbols to object file whose profile is
6545 Microcontroller to not hinder performance in the general case. */
6546 if (m_profile && first_veneer_scan)
6547 {
6548 struct elf_link_hash_entry **sym_hashes;
6549
6550 sym_hashes = elf_sym_hashes (input_bfd);
6551 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6552 &cmse_stub_created))
4ba2ef8f 6553 goto error_ret_free_local;
0955507f
TP		 6554
6555 if (cmse_stub_created != 0)
6556 stub_changed = TRUE;
4ba2ef8f
TP		 6557 }
6558
906e58ca
NC		 6559 /* Walk over each section attached to the input bfd. */
6560 for (section = input_bfd->sections;
6561 section != NULL;
6562 section = section->next)
6563 {
6564 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6565
6566 /* If there aren't any relocs, then there's nothing more
6567 to do. */
6568 if ((section->flags & SEC_RELOC) == 0
6569 || section->reloc_count == 0
6570 || (section->flags & SEC_CODE) == 0)
6571 continue;
6572
6573 /* If this section is a link-once section that will be
6574 discarded, then don't create any stubs. */
6575 if (section->output_section == NULL
6576 || section->output_section->owner != output_bfd)
6577 continue;
6578
6579 /* Get the relocs. */
6580 internal_relocs
6581 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6582 NULL, info->keep_memory);
6583 if (internal_relocs == NULL)
6584 goto error_ret_free_local;
6585
6586 /* Now examine each relocation. */
6587 irela = internal_relocs;
6588 irelaend = irela + section->reloc_count;
6589 for (; irela < irelaend; irela++)
6590 {
6591 unsigned int r_type, r_indx;
906e58ca
NC		 6592 asection *sym_sec;
6593 bfd_vma sym_value;
6594 bfd_vma destination;
6595 struct elf32_arm_link_hash_entry *hash;
7413f23f 6596 const char *sym_name;
34e77a92 6597 unsigned char st_type;
35fc36a8 6598 enum arm_st_branch_type branch_type;
48229727 6599 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6600
6601 r_type = ELF32_R_TYPE (irela->r_info);
6602 r_indx = ELF32_R_SYM (irela->r_info);
6603
6604 if (r_type >= (unsigned int) R_ARM_max)
6605 {
6606 bfd_set_error (bfd_error_bad_value);
6607 error_ret_free_internal:
6608 if (elf_section_data (section)->relocs == NULL)
6609 free (internal_relocs);
15dd01b1
TP		 6610 /* Fall through. */
6611 error_ret_free_local:
6612 if (local_syms != NULL
6613 && (symtab_hdr->contents
6614 != (unsigned char *) local_syms))
6615 free (local_syms);
6616 return FALSE;
906e58ca 6617 }
b38cadfb 6618
0855e32b
NS		 6619 hash = NULL;
6620 if (r_indx >= symtab_hdr->sh_info)
6621 hash = elf32_arm_hash_entry
6622 (elf_sym_hashes (input_bfd)
6623 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6624
0855e32b
NS		 6625 /* Only look for stubs on branch instructions, or
6626 non-relaxed TLSCALL */
906e58ca 6627 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6628 && (r_type != (unsigned int) R_ARM_THM_CALL)
6629 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6630 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6631 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6632 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6633 && (r_type != (unsigned int) R_ARM_PLT32)
6634 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6635 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6636 && r_type == elf32_arm_tls_transition
6637 (info, r_type, &hash->root)
6638 && ((hash ? hash->tls_type
6639 : (elf32_arm_local_got_tls_type
6640 (input_bfd)[r_indx]))
6641 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6642 continue;
6643
6644 /* Now determine the call target, its name, value,
6645 section. */
6646 sym_sec = NULL;
6647 sym_value = 0;
6648 destination = 0;
7413f23f 6649 sym_name = NULL;
b38cadfb 6650
0855e32b
NS		 6651 if (r_type == (unsigned int) R_ARM_TLS_CALL
6652 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6653 {
6654 /* A non-relaxed TLS call. The target is the
6655 plt-resident trampoline and nothing to do
6656 with the symbol. */
6657 BFD_ASSERT (htab->tls_trampoline > 0);
6658 sym_sec = htab->root.splt;
6659 sym_value = htab->tls_trampoline;
6660 hash = 0;
34e77a92 6661 st_type = STT_FUNC;
35fc36a8 6662 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6663 }
6664 else if (!hash)
906e58ca
NC		 6665 {
6666 /* It's a local symbol. */
6667 Elf_Internal_Sym *sym;
906e58ca
NC		 6668
6669 if (local_syms == NULL)
6670 {
6671 local_syms
6672 = (Elf_Internal_Sym *) symtab_hdr->contents;
6673 if (local_syms == NULL)
6674 local_syms
6675 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6676 symtab_hdr->sh_info, 0,
6677 NULL, NULL, NULL);
6678 if (local_syms == NULL)
6679 goto error_ret_free_internal;
6680 }
6681
6682 sym = local_syms + r_indx;
f6d250ce
TS		 6683 if (sym->st_shndx == SHN_UNDEF)
6684 sym_sec = bfd_und_section_ptr;
6685 else if (sym->st_shndx == SHN_ABS)
6686 sym_sec = bfd_abs_section_ptr;
6687 else if (sym->st_shndx == SHN_COMMON)
6688 sym_sec = bfd_com_section_ptr;
6689 else
6690 sym_sec =
6691 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6692
ffcb4889
NS		 6693 if (!sym_sec)
6694 /* This is an undefined symbol. It can never
6a631e86 6695 be resolved. */
ffcb4889 6696 continue;
fe33d2fa 6697
906e58ca
NC		 6698 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6699 sym_value = sym->st_value;
6700 destination = (sym_value + irela->r_addend
6701 + sym_sec->output_offset
6702 + sym_sec->output_section->vma);
34e77a92 6703 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6704 branch_type =
6705 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6706 sym_name
6707 = bfd_elf_string_from_elf_section (input_bfd,
6708 symtab_hdr->sh_link,
6709 sym->st_name);
906e58ca
NC		 6710 }
6711 else
6712 {
6713 /* It's an external symbol. */
906e58ca
NC		 6714 while (hash->root.root.type == bfd_link_hash_indirect
6715 || hash->root.root.type == bfd_link_hash_warning)
6716 hash = ((struct elf32_arm_link_hash_entry *)
6717 hash->root.root.u.i.link);
6718
6719 if (hash->root.root.type == bfd_link_hash_defined
6720 || hash->root.root.type == bfd_link_hash_defweak)
6721 {
6722 sym_sec = hash->root.root.u.def.section;
6723 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6724
6725 struct elf32_arm_link_hash_table *globals =
6726 elf32_arm_hash_table (info);
6727
6728 /* For a destination in a shared library,
6729 use the PLT stub as target address to
6730 decide whether a branch stub is
6731 needed. */
4dfe6ac6 6732 if (globals != NULL
362d30a1 6733 && globals->root.splt != NULL
4dfe6ac6 6734 && hash != NULL
022f8312
CL		 6735 && hash->root.plt.offset != (bfd_vma) -1)
6736 {
362d30a1 6737 sym_sec = globals->root.splt;
022f8312
CL		 6738 sym_value = hash->root.plt.offset;
6739 if (sym_sec->output_section != NULL)
6740 destination = (sym_value
6741 + sym_sec->output_offset
6742 + sym_sec->output_section->vma);
6743 }
6744 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6745 destination = (sym_value + irela->r_addend
6746 + sym_sec->output_offset
6747 + sym_sec->output_section->vma);
6748 }
69c5861e
CL		 6749 else if ((hash->root.root.type == bfd_link_hash_undefined)
6750 || (hash->root.root.type == bfd_link_hash_undefweak))
6751 {
6752 /* For a shared library, use the PLT stub as
6753 target address to decide whether a long
6754 branch stub is needed.
6755 For absolute code, they cannot be handled. */
6756 struct elf32_arm_link_hash_table *globals =
6757 elf32_arm_hash_table (info);
6758
4dfe6ac6 6759 if (globals != NULL
362d30a1 6760 && globals->root.splt != NULL
4dfe6ac6 6761 && hash != NULL
69c5861e
CL		 6762 && hash->root.plt.offset != (bfd_vma) -1)
6763 {
362d30a1 6764 sym_sec = globals->root.splt;
69c5861e
CL		 6765 sym_value = hash->root.plt.offset;
6766 if (sym_sec->output_section != NULL)
6767 destination = (sym_value
6768 + sym_sec->output_offset
6769 + sym_sec->output_section->vma);
6770 }
6771 else
6772 continue;
6773 }
906e58ca
NC		 6774 else
6775 {
6776 bfd_set_error (bfd_error_bad_value);
6777 goto error_ret_free_internal;
6778 }
34e77a92 6779 st_type = hash->root.type;
39d911fc
TP		 6780 branch_type =
6781 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6782 sym_name = hash->root.root.root.string;
906e58ca
NC		 6783 }
6784
48229727 6785 do
7413f23f 6786 {
b715f643 6787 bfd_boolean new_stub;
0955507f 6788 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6789
48229727
JB		 6790 /* Determine what (if any) linker stub is needed. */
6791 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6792 st_type, &branch_type,
6793 hash, destination, sym_sec,
48229727
JB		 6794 input_bfd, sym_name);
6795 if (stub_type == arm_stub_none)
6796 break;
6797
48229727
JB		 6798 /* We've either created a stub for this reloc already,
6799 or we are about to. */
0955507f 6800 stub_entry =
b715f643
TP		 6801 elf32_arm_create_stub (htab, stub_type, section, irela,
6802 sym_sec, hash,
6803 (char *) sym_name, sym_value,
6804 branch_type, &new_stub);
7413f23f 6805
0955507f 6806 created_stub = stub_entry != NULL;
b715f643
TP		 6807 if (!created_stub)
6808 goto error_ret_free_internal;
6809 else if (!new_stub)
6810 break;
99059e56 6811 else
b715f643 6812 stub_changed = TRUE;
99059e56
RM		 6813 }
6814 while (0);
6815
6816 /* Look for relocations which might trigger Cortex-A8
6817 erratum. */
6818 if (htab->fix_cortex_a8
6819 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6820 || r_type == (unsigned int) R_ARM_THM_JUMP19
6821 || r_type == (unsigned int) R_ARM_THM_CALL
6822 || r_type == (unsigned int) R_ARM_THM_XPC22))
6823 {
6824 bfd_vma from = section->output_section->vma
6825 + section->output_offset
6826 + irela->r_offset;
6827
6828 if ((from & 0xfff) == 0xffe)
6829 {
6830 /* Found a candidate. Note we haven't checked the
6831 destination is within 4K here: if we do so (and
6832 don't create an entry in a8_relocs) we can't tell
6833 that a branch should have been relocated when
6834 scanning later. */
6835 if (num_a8_relocs == a8_reloc_table_size)
6836 {
6837 a8_reloc_table_size *= 2;
6838 a8_relocs = (struct a8_erratum_reloc *)
6839 bfd_realloc (a8_relocs,
6840 sizeof (struct a8_erratum_reloc)
6841 * a8_reloc_table_size);
6842 }
6843
6844 a8_relocs[num_a8_relocs].from = from;
6845 a8_relocs[num_a8_relocs].destination = destination;
6846 a8_relocs[num_a8_relocs].r_type = r_type;
6847 a8_relocs[num_a8_relocs].branch_type = branch_type;
6848 a8_relocs[num_a8_relocs].sym_name = sym_name;
6849 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6850 a8_relocs[num_a8_relocs].hash = hash;
6851
6852 num_a8_relocs++;
6853 }
6854 }
906e58ca
NC		 6855 }
6856
99059e56
RM		 6857 /* We're done with the internal relocs, free them. */
6858 if (elf_section_data (section)->relocs == NULL)
6859 free (internal_relocs);
6860 }
48229727 6861
99059e56 6862 if (htab->fix_cortex_a8)
48229727 6863 {
99059e56
RM		 6864 /* Sort relocs which might apply to Cortex-A8 erratum. */
6865 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6866 sizeof (struct a8_erratum_reloc),
99059e56 6867 &a8_reloc_compare);
48229727 6868
99059e56
RM		 6869 /* Scan for branches which might trigger Cortex-A8 erratum. */
6870 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6871 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6872 a8_relocs, num_a8_relocs,
6873 prev_num_a8_fixes, &stub_changed)
6874 != 0)
48229727 6875 goto error_ret_free_local;
5e681ec4 6876 }
7f991970
AM		 6877
6878 if (local_syms != NULL
6879 && symtab_hdr->contents != (unsigned char *) local_syms)
6880 {
6881 if (!info->keep_memory)
6882 free (local_syms);
6883 else
6884 symtab_hdr->contents = (unsigned char *) local_syms;
6885 }
5e681ec4
PB		 6886 }
6887
0955507f
TP		 6888 if (first_veneer_scan
6889 && !set_cmse_veneer_addr_from_implib (info, htab,
6890 &cmse_stub_created))
6891 ret = FALSE;
6892
eb7c4339 6893 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6894 stub_changed = TRUE;
48229727 6895
906e58ca
NC		 6896 if (!stub_changed)
6897 break;
5e681ec4 6898
906e58ca
NC		 6899 /* OK, we've added some stubs. Find out the new size of the
6900 stub sections. */
6901 for (stub_sec = htab->stub_bfd->sections;
6902 stub_sec != NULL;
6903 stub_sec = stub_sec->next)
3e6b1042
DJ		 6904 {
6905 /* Ignore non-stub sections. */
6906 if (!strstr (stub_sec->name, STUB_SUFFIX))
6907 continue;
6908
6909 stub_sec->size = 0;
6910 }
b34b2d70 6911
0955507f
TP		 6912 /* Add new SG veneers after those already in the input import
6913 library. */
6914 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6915 stub_type++)
6916 {
6917 bfd_vma *start_offset_p;
6918 asection **stub_sec_p;
6919
6920 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6921 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6922 if (start_offset_p == NULL)
6923 continue;
6924
6925 BFD_ASSERT (stub_sec_p != NULL);
6926 if (*stub_sec_p != NULL)
6927 (*stub_sec_p)->size = *start_offset_p;
6928 }
6929
d7c5bd02 6930 /* Compute stub section size, considering padding. */
906e58ca 6931 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6932 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6933 stub_type++)
6934 {
6935 int size, padding;
6936 asection **stub_sec_p;
6937
6938 padding = arm_dedicated_stub_section_padding (stub_type);
6939 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6940 /* Skip if no stub input section or no stub section padding
6941 required. */
6942 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6943 continue;
6944 /* Stub section padding required but no dedicated section. */
6945 BFD_ASSERT (stub_sec_p);
6946
6947 size = (*stub_sec_p)->size;
6948 size = (size + padding - 1) & ~(padding - 1);
6949 (*stub_sec_p)->size = size;
6950 }
906e58ca 6951
48229727
JB		 6952 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6953 if (htab->fix_cortex_a8)
99059e56
RM		 6954 for (i = 0; i < num_a8_fixes; i++)
6955 {
48229727 6956 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6957 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6958
6959 if (stub_sec == NULL)
7f991970 6960 return FALSE;
48229727 6961
99059e56
RM		 6962 stub_sec->size
6963 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6964 NULL);
6965 }
48229727
JB		 6966
6967
906e58ca
NC		 6968 /* Ask the linker to do its stuff. */
6969 (*htab->layout_sections_again) ();
4ba2ef8f 6970 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6971 }
6972
48229727
JB		 6973 /* Add stubs for Cortex-A8 erratum fixes now. */
6974 if (htab->fix_cortex_a8)
6975 {
6976 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6977 {
6978 struct elf32_arm_stub_hash_entry *stub_entry;
6979 char *stub_name = a8_fixes[i].stub_name;
6980 asection *section = a8_fixes[i].section;
6981 unsigned int section_id = a8_fixes[i].section->id;
6982 asection *link_sec = htab->stub_group[section_id].link_sec;
6983 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6984 const insn_sequence *template_sequence;
6985 int template_size, size = 0;
6986
6987 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6988 TRUE, FALSE);
6989 if (stub_entry == NULL)
6990 {
871b3ab2 6991 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6992 section->owner, stub_name);
99059e56
RM		 6993 return FALSE;
6994 }
6995
6996 stub_entry->stub_sec = stub_sec;
0955507f 6997 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6998 stub_entry->id_sec = link_sec;
6999 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 7000 stub_entry->source_value = a8_fixes[i].offset;
99059e56 7001 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 7002 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 7003 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 7004 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 7005
99059e56
RM		 7006 size = find_stub_size_and_template (a8_fixes[i].stub_type,
7007 &template_sequence,
7008 &template_size);
48229727 7009
99059e56
RM		 7010 stub_entry->stub_size = size;
7011 stub_entry->stub_template = template_sequence;
7012 stub_entry->stub_template_size = template_size;
7013 }
48229727
JB		 7014
7015 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 7016 elf32_arm_write_section(). */
48229727
JB		 7017 htab->a8_erratum_fixes = a8_fixes;
7018 htab->num_a8_erratum_fixes = num_a8_fixes;
7019 }
7020 else
7021 {
7022 htab->a8_erratum_fixes = NULL;
7023 htab->num_a8_erratum_fixes = 0;
7024 }
0955507f 7025 return ret;
5e681ec4
PB		 7026}
7027
906e58ca
NC		 7028/* Build all the stubs associated with the current output file. The
7029 stubs are kept in a hash table attached to the main linker hash
7030 table. We also set up the .plt entries for statically linked PIC
7031 functions here. This function is called via arm_elf_finish in the
7032 linker. */
252b5132 7033
906e58ca
NC		 7034bfd_boolean
7035elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 7036{
906e58ca
NC		 7037 asection *stub_sec;
7038 struct bfd_hash_table *table;
0955507f 7039 enum elf32_arm_stub_type stub_type;
906e58ca 7040 struct elf32_arm_link_hash_table *htab;
252b5132 7041
906e58ca 7042 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 7043 if (htab == NULL)
7044 return FALSE;
252b5132 7045
906e58ca
NC		 7046 for (stub_sec = htab->stub_bfd->sections;
7047 stub_sec != NULL;
7048 stub_sec = stub_sec->next)
252b5132 7049 {
906e58ca
NC		 7050 bfd_size_type size;
7051
8029a119 7052 /* Ignore non-stub sections. */
906e58ca
NC		 7053 if (!strstr (stub_sec->name, STUB_SUFFIX))
7054 continue;
7055
d7c5bd02 7056 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7057 must at least be done for stub section requiring padding and for SG
7058 veneers to ensure that a non secure code branching to a removed SG
7059 veneer causes an error. */
906e58ca 7060 size = stub_sec->size;
21d799b5 7061 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7062 if (stub_sec->contents == NULL && size != 0)
7063 return FALSE;
0955507f 7064
906e58ca 7065 stub_sec->size = 0;
252b5132
RH		 7066 }
7067
0955507f
TP		 7068 /* Add new SG veneers after those already in the input import library. */
7069 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7070 {
7071 bfd_vma *start_offset_p;
7072 asection **stub_sec_p;
7073
7074 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7075 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7076 if (start_offset_p == NULL)
7077 continue;
7078
7079 BFD_ASSERT (stub_sec_p != NULL);
7080 if (*stub_sec_p != NULL)
7081 (*stub_sec_p)->size = *start_offset_p;
7082 }
7083
906e58ca
NC		 7084 /* Build the stubs as directed by the stub hash table. */
7085 table = &htab->stub_hash_table;
7086 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7087 if (htab->fix_cortex_a8)
7088 {
7089 /* Place the cortex a8 stubs last. */
7090 htab->fix_cortex_a8 = -1;
7091 bfd_hash_traverse (table, arm_build_one_stub, info);
7092 }
252b5132 7093
906e58ca 7094 return TRUE;
252b5132
RH		 7095}
7096
9b485d32
NC		 7097/* Locate the Thumb encoded calling stub for NAME. */
7098
252b5132 7099static struct elf_link_hash_entry *
57e8b36a
NC		 7100find_thumb_glue (struct bfd_link_info *link_info,
7101 const char *name,
f2a9dd69 7102 char **error_message)
252b5132
RH		 7103{
7104 char *tmp_name;
7105 struct elf_link_hash_entry *hash;
7106 struct elf32_arm_link_hash_table *hash_table;
7107
7108 /* We need a pointer to the armelf specific hash table. */
7109 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7110 if (hash_table == NULL)
7111 return NULL;
252b5132 7112
21d799b5 7113 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7114 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7115
7116 BFD_ASSERT (tmp_name);
7117
7118 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7119
7120 hash = elf_link_hash_lookup
b34976b6 7121 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7122
b1657152 7123 if (hash == NULL
90b6238f
AM		 7124 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7125 "Thumb", tmp_name, name) == -1)
b1657152 7126 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7127
7128 free (tmp_name);
7129
7130 return hash;
7131}
7132
9b485d32
NC		 7133/* Locate the ARM encoded calling stub for NAME. */
7134
252b5132 7135static struct elf_link_hash_entry *
57e8b36a
NC		 7136find_arm_glue (struct bfd_link_info *link_info,
7137 const char *name,
f2a9dd69 7138 char **error_message)
252b5132
RH		 7139{
7140 char *tmp_name;
7141 struct elf_link_hash_entry *myh;
7142 struct elf32_arm_link_hash_table *hash_table;
7143
7144 /* We need a pointer to the elfarm specific hash table. */
7145 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7146 if (hash_table == NULL)
7147 return NULL;
252b5132 7148
21d799b5 7149 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7150 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7151 BFD_ASSERT (tmp_name);
7152
7153 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7154
7155 myh = elf_link_hash_lookup
b34976b6 7156 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7157
b1657152 7158 if (myh == NULL
90b6238f
AM		 7159 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7160 "ARM", tmp_name, name) == -1)
b1657152 7161 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7162
7163 free (tmp_name);
7164
7165 return myh;
7166}
7167
8f6277f5 7168/* ARM->Thumb glue (static images):
252b5132
RH		 7169
7170 .arm
7171 __func_from_arm:
7172 ldr r12, __func_addr
7173 bx r12
7174 __func_addr:
906e58ca 7175 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7176
26079076
PB		 7177 (v5t static images)
7178 .arm
7179 __func_from_arm:
7180 ldr pc, __func_addr
7181 __func_addr:
906e58ca 7182 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7183
8f6277f5
PB		 7184 (relocatable images)
7185 .arm
7186 __func_from_arm:
7187 ldr r12, __func_offset
7188 add r12, r12, pc
7189 bx r12
7190 __func_offset:
8029a119 7191 .word func - . */
8f6277f5
PB		 7192
7193#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7194static const insn32 a2t1_ldr_insn = 0xe59fc000;
7195static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7196static const insn32 a2t3_func_addr_insn = 0x00000001;
7197
26079076
PB		 7198#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7199static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7200static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7201
8f6277f5
PB		 7202#define ARM2THUMB_PIC_GLUE_SIZE 16
7203static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7204static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7205static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7206
07d6d2b8 7207/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7208
07d6d2b8
AM		 7209 .thumb .thumb
7210 .align 2 .align 2
7211 __func_from_thumb: __func_from_thumb:
7212 bx pc push {r6, lr}
7213 nop ldr r6, __func_addr
7214 .arm mov lr, pc
7215 b func bx r6
99059e56
RM		 7216 .arm
7217 ;; back_to_thumb
7218 ldmia r13! {r6, lr}
7219 bx lr
7220 __func_addr:
07d6d2b8 7221 .word func */
252b5132
RH		 7222
7223#define THUMB2ARM_GLUE_SIZE 8
7224static const insn16 t2a1_bx_pc_insn = 0x4778;
7225static const insn16 t2a2_noop_insn = 0x46c0;
7226static const insn32 t2a3_b_insn = 0xea000000;
7227
c7b8f16e 7228#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7229#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7230#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7231
845b51d6
PB		 7232#define ARM_BX_VENEER_SIZE 12
7233static const insn32 armbx1_tst_insn = 0xe3100001;
7234static const insn32 armbx2_moveq_insn = 0x01a0f000;
7235static const insn32 armbx3_bx_insn = 0xe12fff10;
7236
7e392df6 7237#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7238static void
7239arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7240{
7241 asection * s;
8029a119 7242 bfd_byte * contents;
252b5132 7243
8029a119 7244 if (size == 0)
3e6b1042
DJ		 7245 {
7246 /* Do not include empty glue sections in the output. */
7247 if (abfd != NULL)
7248 {
3d4d4302 7249 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7250 if (s != NULL)
7251 s->flags |= SEC_EXCLUDE;
7252 }
7253 return;
7254 }
252b5132 7255
8029a119 7256 BFD_ASSERT (abfd != NULL);
252b5132 7257
3d4d4302 7258 s = bfd_get_linker_section (abfd, name);
8029a119 7259 BFD_ASSERT (s != NULL);
252b5132 7260
b0f4fbf8 7261 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7262
8029a119
NC		 7263 BFD_ASSERT (s->size == size);
7264 s->contents = contents;
7265}
906e58ca 7266
8029a119
NC		 7267bfd_boolean
7268bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7269{
7270 struct elf32_arm_link_hash_table * globals;
906e58ca 7271
8029a119
NC		 7272 globals = elf32_arm_hash_table (info);
7273 BFD_ASSERT (globals != NULL);
906e58ca 7274
8029a119
NC		 7275 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7276 globals->arm_glue_size,
7277 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7278
8029a119
NC		 7279 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7280 globals->thumb_glue_size,
7281 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7282
8029a119
NC		 7283 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7284 globals->vfp11_erratum_glue_size,
7285 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7286
a504d23a
LA		 7287 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7288 globals->stm32l4xx_erratum_glue_size,
7289 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7290
8029a119
NC		 7291 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7292 globals->bx_glue_size,
845b51d6
PB		 7293 ARM_BX_GLUE_SECTION_NAME);
7294
b34976b6 7295 return TRUE;
252b5132
RH		 7296}
7297
a4fd1a8e 7298/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7299 returns the symbol identifying the stub. */
7300
a4fd1a8e 7301static struct elf_link_hash_entry *
57e8b36a
NC		 7302record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7303 struct elf_link_hash_entry * h)
252b5132
RH		 7304{
7305 const char * name = h->root.root.string;
63b0f745 7306 asection * s;
252b5132
RH		 7307 char * tmp_name;
7308 struct elf_link_hash_entry * myh;
14a793b2 7309 struct bfd_link_hash_entry * bh;
252b5132 7310 struct elf32_arm_link_hash_table * globals;
dc810e39 7311 bfd_vma val;
2f475487 7312 bfd_size_type size;
252b5132
RH		 7313
7314 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7315 BFD_ASSERT (globals != NULL);
7316 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7317
3d4d4302 7318 s = bfd_get_linker_section
252b5132
RH		 7319 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7320
252b5132
RH		 7321 BFD_ASSERT (s != NULL);
7322
21d799b5 7323 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7324 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7325 BFD_ASSERT (tmp_name);
7326
7327 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7328
7329 myh = elf_link_hash_lookup
b34976b6 7330 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7331
7332 if (myh != NULL)
7333 {
9b485d32 7334 /* We've already seen this guy. */
252b5132 7335 free (tmp_name);
a4fd1a8e 7336 return myh;
252b5132
RH		 7337 }
7338
57e8b36a
NC		 7339 /* The only trick here is using hash_table->arm_glue_size as the value.
7340 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7341 putting it. The +1 on the value marks that the stub has not been
7342 output yet - not that it is a Thumb function. */
14a793b2 7343 bh = NULL;
dc810e39
AM		 7344 val = globals->arm_glue_size + 1;
7345 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7346 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7347 NULL, TRUE, FALSE, &bh);
252b5132 7348
b7693d02
DJ		 7349 myh = (struct elf_link_hash_entry *) bh;
7350 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7351 myh->forced_local = 1;
7352
252b5132
RH		 7353 free (tmp_name);
7354
0e1862bb
L		 7355 if (bfd_link_pic (link_info)
7356 || globals->root.is_relocatable_executable
27e55c4d 7357 || globals->pic_veneer)
2f475487 7358 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7359 else if (globals->use_blx)
7360 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7361 else
2f475487
AM		 7362 size = ARM2THUMB_STATIC_GLUE_SIZE;
7363
7364 s->size += size;
7365 globals->arm_glue_size += size;
252b5132 7366
a4fd1a8e 7367 return myh;
252b5132
RH		 7368}
7369
845b51d6
PB		 7370/* Allocate space for ARMv4 BX veneers. */
7371
7372static void
7373record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7374{
7375 asection * s;
7376 struct elf32_arm_link_hash_table *globals;
7377 char *tmp_name;
7378 struct elf_link_hash_entry *myh;
7379 struct bfd_link_hash_entry *bh;
7380 bfd_vma val;
7381
7382 /* BX PC does not need a veneer. */
7383 if (reg == 15)
7384 return;
7385
7386 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7387 BFD_ASSERT (globals != NULL);
7388 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7389
7390 /* Check if this veneer has already been allocated. */
7391 if (globals->bx_glue_offset[reg])
7392 return;
7393
3d4d4302 7394 s = bfd_get_linker_section
845b51d6
PB		 7395 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7396
7397 BFD_ASSERT (s != NULL);
7398
7399 /* Add symbol for veneer. */
21d799b5
NC		 7400 tmp_name = (char *)
7401 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
845b51d6 7402 BFD_ASSERT (tmp_name);
906e58ca 7403
845b51d6 7404 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7405
845b51d6
PB		 7406 myh = elf_link_hash_lookup
7407 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7408
845b51d6 7409 BFD_ASSERT (myh == NULL);
906e58ca 7410
845b51d6
PB		 7411 bh = NULL;
7412 val = globals->bx_glue_size;
7413 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7414 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7415 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7416
7417 myh = (struct elf_link_hash_entry *) bh;
7418 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7419 myh->forced_local = 1;
7420
7421 s->size += ARM_BX_VENEER_SIZE;
7422 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7423 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7424}
7425
7426
c7b8f16e
JB		 7427/* Add an entry to the code/data map for section SEC. */
7428
7429static void
7430elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7431{
7432 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7433 unsigned int newidx;
906e58ca 7434
c7b8f16e
JB		 7435 if (sec_data->map == NULL)
7436 {
21d799b5 7437 sec_data->map = (elf32_arm_section_map *)
99059e56 7438 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7439 sec_data->mapcount = 0;
7440 sec_data->mapsize = 1;
7441 }
906e58ca 7442
c7b8f16e 7443 newidx = sec_data->mapcount++;
906e58ca 7444
c7b8f16e
JB		 7445 if (sec_data->mapcount > sec_data->mapsize)
7446 {
7447 sec_data->mapsize *= 2;
21d799b5 7448 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7449 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7450 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7451 }
7452
7453 if (sec_data->map)
7454 {
7455 sec_data->map[newidx].vma = vma;
7456 sec_data->map[newidx].type = type;
c7b8f16e 7457 }
c7b8f16e
JB		 7458}
7459
7460
7461/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7462 veneers are handled for now. */
7463
7464static bfd_vma
7465record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7466 elf32_vfp11_erratum_list *branch,
7467 bfd *branch_bfd,
7468 asection *branch_sec,
7469 unsigned int offset)
c7b8f16e
JB		 7470{
7471 asection *s;
7472 struct elf32_arm_link_hash_table *hash_table;
7473 char *tmp_name;
7474 struct elf_link_hash_entry *myh;
7475 struct bfd_link_hash_entry *bh;
7476 bfd_vma val;
7477 struct _arm_elf_section_data *sec_data;
c7b8f16e 7478 elf32_vfp11_erratum_list *newerr;
906e58ca 7479
c7b8f16e 7480 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7481 BFD_ASSERT (hash_table != NULL);
7482 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7483
3d4d4302 7484 s = bfd_get_linker_section
c7b8f16e 7485 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7486
c7b8f16e 7487 sec_data = elf32_arm_section_data (s);
906e58ca 7488
c7b8f16e 7489 BFD_ASSERT (s != NULL);
906e58ca 7490
21d799b5 7491 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7492 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e 7493 BFD_ASSERT (tmp_name);
906e58ca 7494
c7b8f16e
JB		 7495 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7496 hash_table->num_vfp11_fixes);
906e58ca 7497
c7b8f16e
JB		 7498 myh = elf_link_hash_lookup
7499 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7500
c7b8f16e 7501 BFD_ASSERT (myh == NULL);
906e58ca 7502
c7b8f16e
JB		 7503 bh = NULL;
7504 val = hash_table->vfp11_erratum_glue_size;
7505 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7506 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7507 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7508
7509 myh = (struct elf_link_hash_entry *) bh;
7510 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7511 myh->forced_local = 1;
7512
7513 /* Link veneer back to calling location. */
c7e2358a 7514 sec_data->erratumcount += 1;
21d799b5
NC		 7515 newerr = (elf32_vfp11_erratum_list *)
7516 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7517
c7b8f16e
JB		 7518 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7519 newerr->vma = -1;
7520 newerr->u.v.branch = branch;
7521 newerr->u.v.id = hash_table->num_vfp11_fixes;
7522 branch->u.b.veneer = newerr;
7523
7524 newerr->next = sec_data->erratumlist;
7525 sec_data->erratumlist = newerr;
7526
7527 /* A symbol for the return from the veneer. */
7528 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7529 hash_table->num_vfp11_fixes);
7530
7531 myh = elf_link_hash_lookup
7532 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7533
c7b8f16e
JB		 7534 if (myh != NULL)
7535 abort ();
7536
7537 bh = NULL;
7538 val = offset + 4;
7539 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7540 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7541
c7b8f16e
JB		 7542 myh = (struct elf_link_hash_entry *) bh;
7543 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7544 myh->forced_local = 1;
7545
7546 free (tmp_name);
906e58ca 7547
c7b8f16e
JB		 7548 /* Generate a mapping symbol for the veneer section, and explicitly add an
7549 entry for that symbol to the code/data map for the section. */
7550 if (hash_table->vfp11_erratum_glue_size == 0)
7551 {
7552 bh = NULL;
7553 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7554 ever requires this erratum fix. */
c7b8f16e
JB		 7555 _bfd_generic_link_add_one_symbol (link_info,
7556 hash_table->bfd_of_glue_owner, "$a",
7557 BSF_LOCAL, s, 0, NULL,
99059e56 7558 TRUE, FALSE, &bh);
c7b8f16e
JB		 7559
7560 myh = (struct elf_link_hash_entry *) bh;
7561 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7562 myh->forced_local = 1;
906e58ca 7563
c7b8f16e 7564 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7565 BFDs. We must make a note of this generated mapping symbol
7566 ourselves so that code byteswapping works properly in
7567 elf32_arm_write_section. */
c7b8f16e
JB		 7568 elf32_arm_section_map_add (s, 'a', 0);
7569 }
906e58ca 7570
c7b8f16e
JB		 7571 s->size += VFP11_ERRATUM_VENEER_SIZE;
7572 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7573 hash_table->num_vfp11_fixes++;
906e58ca 7574
c7b8f16e
JB		 7575 /* The offset of the veneer. */
7576 return val;
7577}
7578
a504d23a
LA		 7579/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7580 veneers need to be handled because used only in Cortex-M. */
7581
7582static bfd_vma
7583record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7584 elf32_stm32l4xx_erratum_list *branch,
7585 bfd *branch_bfd,
7586 asection *branch_sec,
7587 unsigned int offset,
7588 bfd_size_type veneer_size)
7589{
7590 asection *s;
7591 struct elf32_arm_link_hash_table *hash_table;
7592 char *tmp_name;
7593 struct elf_link_hash_entry *myh;
7594 struct bfd_link_hash_entry *bh;
7595 bfd_vma val;
7596 struct _arm_elf_section_data *sec_data;
7597 elf32_stm32l4xx_erratum_list *newerr;
7598
7599 hash_table = elf32_arm_hash_table (link_info);
7600 BFD_ASSERT (hash_table != NULL);
7601 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7602
7603 s = bfd_get_linker_section
7604 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7605
7606 BFD_ASSERT (s != NULL);
7607
7608 sec_data = elf32_arm_section_data (s);
7609
7610 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7611 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
a504d23a
LA		 7612 BFD_ASSERT (tmp_name);
7613
7614 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7615 hash_table->num_stm32l4xx_fixes);
7616
7617 myh = elf_link_hash_lookup
7618 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7619
7620 BFD_ASSERT (myh == NULL);
7621
7622 bh = NULL;
7623 val = hash_table->stm32l4xx_erratum_glue_size;
7624 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7625 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7626 NULL, TRUE, FALSE, &bh);
7627
7628 myh = (struct elf_link_hash_entry *) bh;
7629 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7630 myh->forced_local = 1;
7631
7632 /* Link veneer back to calling location. */
7633 sec_data->stm32l4xx_erratumcount += 1;
7634 newerr = (elf32_stm32l4xx_erratum_list *)
7635 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7636
7637 newerr->type = STM32L4XX_ERRATUM_VENEER;
7638 newerr->vma = -1;
7639 newerr->u.v.branch = branch;
7640 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7641 branch->u.b.veneer = newerr;
7642
7643 newerr->next = sec_data->stm32l4xx_erratumlist;
7644 sec_data->stm32l4xx_erratumlist = newerr;
7645
7646 /* A symbol for the return from the veneer. */
7647 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7648 hash_table->num_stm32l4xx_fixes);
7649
7650 myh = elf_link_hash_lookup
7651 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7652
7653 if (myh != NULL)
7654 abort ();
7655
7656 bh = NULL;
7657 val = offset + 4;
7658 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7659 branch_sec, val, NULL, TRUE, FALSE, &bh);
7660
7661 myh = (struct elf_link_hash_entry *) bh;
7662 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7663 myh->forced_local = 1;
7664
7665 free (tmp_name);
7666
7667 /* Generate a mapping symbol for the veneer section, and explicitly add an
7668 entry for that symbol to the code/data map for the section. */
7669 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7670 {
7671 bh = NULL;
7672 /* Creates a THUMB symbol since there is no other choice. */
7673 _bfd_generic_link_add_one_symbol (link_info,
7674 hash_table->bfd_of_glue_owner, "$t",
7675 BSF_LOCAL, s, 0, NULL,
7676 TRUE, FALSE, &bh);
7677
7678 myh = (struct elf_link_hash_entry *) bh;
7679 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7680 myh->forced_local = 1;
7681
7682 /* The elf32_arm_init_maps function only cares about symbols from input
7683 BFDs. We must make a note of this generated mapping symbol
7684 ourselves so that code byteswapping works properly in
7685 elf32_arm_write_section. */
7686 elf32_arm_section_map_add (s, 't', 0);
7687 }
7688
7689 s->size += veneer_size;
7690 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7691 hash_table->num_stm32l4xx_fixes++;
7692
7693 /* The offset of the veneer. */
7694 return val;
7695}
7696
8029a119 7697#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7698 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7699 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7700
7701/* Create a fake section for use by the ARM backend of the linker. */
7702
7703static bfd_boolean
7704arm_make_glue_section (bfd * abfd, const char * name)
7705{
7706 asection * sec;
7707
3d4d4302 7708 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7709 if (sec != NULL)
7710 /* Already made. */
7711 return TRUE;
7712
3d4d4302 7713 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7714
7715 if (sec == NULL
fd361982 7716 || !bfd_set_section_alignment (sec, 2))
8029a119
NC		 7717 return FALSE;
7718
7719 /* Set the gc mark to prevent the section from being removed by garbage
7720 collection, despite the fact that no relocs refer to this section. */
7721 sec->gc_mark = 1;
7722
7723 return TRUE;
7724}
7725
1db37fe6
YG		 7726/* Set size of .plt entries. This function is called from the
7727 linker scripts in ld/emultempl/{armelf}.em. */
7728
7729void
7730bfd_elf32_arm_use_long_plt (void)
7731{
7732 elf32_arm_use_long_plt_entry = TRUE;
7733}
7734
8afb0e02
NC		 7735/* Add the glue sections to ABFD. This function is called from the
7736 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7737
b34976b6 7738bfd_boolean
57e8b36a
NC		 7739bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7740 struct bfd_link_info *info)
252b5132 7741{
a504d23a
LA		 7742 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7743 bfd_boolean dostm32l4xx = globals
7744 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7745 bfd_boolean addglue;
7746
8afb0e02
NC		 7747 /* If we are only performing a partial
7748 link do not bother adding the glue. */
0e1862bb 7749 if (bfd_link_relocatable (info))
b34976b6 7750 return TRUE;
252b5132 7751
a504d23a 7752 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7753 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7754 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7755 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7756
7757 if (!dostm32l4xx)
7758 return addglue;
7759
7760 return addglue
7761 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7762}
7763
daa4adae
TP		 7764/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7765 ensures they are not marked for deletion by
7766 strip_excluded_output_sections () when veneers are going to be created
7767 later. Not doing so would trigger assert on empty section size in
7768 lang_size_sections_1 (). */
7769
7770void
7771bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7772{
7773 enum elf32_arm_stub_type stub_type;
7774
7775 /* If we are only performing a partial
7776 link do not bother adding the glue. */
7777 if (bfd_link_relocatable (info))
7778 return;
7779
7780 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7781 {
7782 asection *out_sec;
7783 const char *out_sec_name;
7784
7785 if (!arm_dedicated_stub_output_section_required (stub_type))
7786 continue;
7787
7788 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7789 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7790 if (out_sec != NULL)
7791 out_sec->flags |= SEC_KEEP;
7792 }
7793}
7794
8afb0e02
NC		 7795/* Select a BFD to be used to hold the sections used by the glue code.
7796 This function is called from the linker scripts in ld/emultempl/
8029a119 7797 {armelf/pe}.em. */
8afb0e02 7798
b34976b6 7799bfd_boolean
57e8b36a 7800bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7801{
7802 struct elf32_arm_link_hash_table *globals;
7803
7804 /* If we are only performing a partial link
7805 do not bother getting a bfd to hold the glue. */
0e1862bb 7806 if (bfd_link_relocatable (info))
b34976b6 7807 return TRUE;
8afb0e02 7808
b7693d02
DJ		 7809 /* Make sure we don't attach the glue sections to a dynamic object. */
7810 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7811
8afb0e02 7812 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7813 BFD_ASSERT (globals != NULL);
7814
7815 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7816 return TRUE;
8afb0e02 7817
252b5132
RH		 7818 /* Save the bfd for later use. */
7819 globals->bfd_of_glue_owner = abfd;
cedb70c5 7820
b34976b6 7821 return TRUE;
252b5132
RH		 7822}
7823
906e58ca
NC		 7824static void
7825check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7826{
2de70689
MGD		 7827 int cpu_arch;
7828
b38cadfb 7829 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7830 Tag_CPU_arch);
7831
7832 if (globals->fix_arm1176)
7833 {
7834 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7835 globals->use_blx = 1;
7836 }
7837 else
7838 {
7839 if (cpu_arch > TAG_CPU_ARCH_V4T)
7840 globals->use_blx = 1;
7841 }
39b41c9c
PB		 7842}
7843
b34976b6 7844bfd_boolean
57e8b36a 7845bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7846 struct bfd_link_info *link_info)
252b5132
RH		 7847{
7848 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7849 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7850 Elf_Internal_Rela *irel, *irelend;
7851 bfd_byte *contents = NULL;
252b5132
RH		 7852
7853 asection *sec;
7854 struct elf32_arm_link_hash_table *globals;
7855
7856 /* If we are only performing a partial link do not bother
7857 to construct any glue. */
0e1862bb 7858 if (bfd_link_relocatable (link_info))
b34976b6 7859 return TRUE;
252b5132 7860
39ce1a6a
NC		 7861 /* Here we have a bfd that is to be included on the link. We have a
7862 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7863 globals = elf32_arm_hash_table (link_info);
252b5132 7864 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7865
7866 check_use_blx (globals);
252b5132 7867
d504ffc8 7868 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7869 {
90b6238f 7870 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7871 abfd);
e489d0ae
PB		 7872 return FALSE;
7873 }
f21f3fe0 7874
39ce1a6a
NC		 7875 /* PR 5398: If we have not decided to include any loadable sections in
7876 the output then we will not have a glue owner bfd. This is OK, it
7877 just means that there is nothing else for us to do here. */
7878 if (globals->bfd_of_glue_owner == NULL)
7879 return TRUE;
7880
252b5132
RH		 7881 /* Rummage around all the relocs and map the glue vectors. */
7882 sec = abfd->sections;
7883
7884 if (sec == NULL)
b34976b6 7885 return TRUE;
252b5132
RH		 7886
7887 for (; sec != NULL; sec = sec->next)
7888 {
7889 if (sec->reloc_count == 0)
7890 continue;
7891
2f475487
AM		 7892 if ((sec->flags & SEC_EXCLUDE) != 0)
7893 continue;
7894
0ffa91dd 7895 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7896
9b485d32 7897 /* Load the relocs. */
6cdc0ccc 7898 internal_relocs
906e58ca 7899 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7900
6cdc0ccc
AM		 7901 if (internal_relocs == NULL)
7902 goto error_return;
252b5132 7903
6cdc0ccc
AM		 7904 irelend = internal_relocs + sec->reloc_count;
7905 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7906 {
7907 long r_type;
7908 unsigned long r_index;
252b5132
RH		 7909
7910 struct elf_link_hash_entry *h;
7911
7912 r_type = ELF32_R_TYPE (irel->r_info);
7913 r_index = ELF32_R_SYM (irel->r_info);
7914
9b485d32 7915 /* These are the only relocation types we care about. */
ba96a88f 7916 if ( r_type != R_ARM_PC24
845b51d6 7917 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7918 continue;
7919
7920 /* Get the section contents if we haven't done so already. */
7921 if (contents == NULL)
7922 {
7923 /* Get cached copy if it exists. */
7924 if (elf_section_data (sec)->this_hdr.contents != NULL)
7925 contents = elf_section_data (sec)->this_hdr.contents;
7926 else
7927 {
7928 /* Go get them off disk. */
57e8b36a 7929 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7930 goto error_return;
7931 }
7932 }
7933
845b51d6
PB		 7934 if (r_type == R_ARM_V4BX)
7935 {
7936 int reg;
7937
7938 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7939 record_arm_bx_glue (link_info, reg);
7940 continue;
7941 }
7942
a7c10850 7943 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7944 h = NULL;
7945
9b485d32 7946 /* We don't care about local symbols. */
252b5132
RH		 7947 if (r_index < symtab_hdr->sh_info)
7948 continue;
7949
9b485d32 7950 /* This is an external symbol. */
252b5132
RH		 7951 r_index -= symtab_hdr->sh_info;
7952 h = (struct elf_link_hash_entry *)
7953 elf_sym_hashes (abfd)[r_index];
7954
7955 /* If the relocation is against a static symbol it must be within
7956 the current section and so cannot be a cross ARM/Thumb relocation. */
7957 if (h == NULL)
7958 continue;
7959
d504ffc8
DJ		 7960 /* If the call will go through a PLT entry then we do not need
7961 glue. */
362d30a1 7962 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7963 continue;
7964
252b5132
RH		 7965 switch (r_type)
7966 {
7967 case R_ARM_PC24:
7968 /* This one is a call from arm code. We need to look up
99059e56
RM		 7969 the target of the call. If it is a thumb target, we
7970 insert glue. */
39d911fc
TP		 7971 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7972 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7973 record_arm_to_thumb_glue (link_info, h);
7974 break;
7975
252b5132 7976 default:
c6596c5e 7977 abort ();
252b5132
RH		 7978 }
7979 }
6cdc0ccc
AM		 7980
7981 if (contents != NULL
7982 && elf_section_data (sec)->this_hdr.contents != contents)
7983 free (contents);
7984 contents = NULL;
7985
7986 if (internal_relocs != NULL
7987 && elf_section_data (sec)->relocs != internal_relocs)
7988 free (internal_relocs);
7989 internal_relocs = NULL;
252b5132
RH		 7990 }
7991
b34976b6 7992 return TRUE;
9a5aca8c 7993
252b5132 7994error_return:
6cdc0ccc
AM		 7995 if (contents != NULL
7996 && elf_section_data (sec)->this_hdr.contents != contents)
7997 free (contents);
7998 if (internal_relocs != NULL
7999 && elf_section_data (sec)->relocs != internal_relocs)
8000 free (internal_relocs);
9a5aca8c 8001
b34976b6 8002 return FALSE;
252b5132 8003}
7e392df6 8004#endif
252b5132 8005
eb043451 8006
c7b8f16e
JB		 8007/* Initialise maps of ARM/Thumb/data for input BFDs. */
8008
8009void
8010bfd_elf32_arm_init_maps (bfd *abfd)
8011{
8012 Elf_Internal_Sym *isymbuf;
8013 Elf_Internal_Shdr *hdr;
8014 unsigned int i, localsyms;
8015
af1f4419
NC		 8016 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8017 if (! is_arm_elf (abfd))
8018 return;
8019
c7b8f16e
JB		 8020 if ((abfd->flags & DYNAMIC) != 0)
8021 return;
8022
0ffa91dd 8023 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 8024 localsyms = hdr->sh_info;
8025
8026 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8027 should contain the number of local symbols, which should come before any
8028 global symbols. Mapping symbols are always local. */
8029 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
8030 NULL);
8031
8032 /* No internal symbols read? Skip this BFD. */
8033 if (isymbuf == NULL)
8034 return;
8035
8036 for (i = 0; i < localsyms; i++)
8037 {
8038 Elf_Internal_Sym *isym = &isymbuf[i];
8039 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
8040 const char *name;
906e58ca 8041
c7b8f16e 8042 if (sec != NULL
99059e56
RM		 8043 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8044 {
8045 name = bfd_elf_string_from_elf_section (abfd,
8046 hdr->sh_link, isym->st_name);
906e58ca 8047
99059e56 8048 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8049 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8050 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8051 }
c7b8f16e
JB		 8052 }
8053}
8054
8055
48229727
JB		 8056/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8057 say what they wanted. */
8058
8059void
8060bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8061{
8062 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8063 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8064
4dfe6ac6
NC		 8065 if (globals == NULL)
8066 return;
8067
48229727
JB		 8068 if (globals->fix_cortex_a8 == -1)
8069 {
8070 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8071 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8072 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8073 || out_attr[Tag_CPU_arch_profile].i == 0))
8074 globals->fix_cortex_a8 = 1;
8075 else
8076 globals->fix_cortex_a8 = 0;
8077 }
8078}
8079
8080
c7b8f16e
JB		 8081void
8082bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8083{
8084 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8085 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8086
4dfe6ac6
NC		 8087 if (globals == NULL)
8088 return;
c7b8f16e
JB		 8089 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8090 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8091 {
8092 switch (globals->vfp11_fix)
99059e56
RM		 8093 {
8094 case BFD_ARM_VFP11_FIX_DEFAULT:
8095 case BFD_ARM_VFP11_FIX_NONE:
8096 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8097 break;
8098
8099 default:
8100 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8101 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8102 "workaround is not necessary for target architecture"), obfd);
8103 }
c7b8f16e
JB		 8104 }
8105 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8106 /* For earlier architectures, we might need the workaround, but do not
8107 enable it by default. If users is running with broken hardware, they
8108 must enable the erratum fix explicitly. */
8109 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8110}
8111
a504d23a
LA		 8112void
8113bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8114{
8115 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8116 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8117
8118 if (globals == NULL)
8119 return;
8120
8121 /* We assume only Cortex-M4 may require the fix. */
8122 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8123 || out_attr[Tag_CPU_arch_profile].i != 'M')
8124 {
8125 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8126 /* Give a warning, but do as the user requests anyway. */
4eca0228 8127 _bfd_error_handler
871b3ab2 8128 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8129 "workaround is not necessary for target architecture"), obfd);
8130 }
8131}
c7b8f16e 8132
906e58ca
NC		 8133enum bfd_arm_vfp11_pipe
8134{
c7b8f16e
JB		 8135 VFP11_FMAC,
8136 VFP11_LS,
8137 VFP11_DS,
8138 VFP11_BAD
8139};
8140
8141/* Return a VFP register number. This is encoded as RX:X for single-precision
8142 registers, or X:RX for double-precision registers, where RX is the group of
8143 four bits in the instruction encoding and X is the single extension bit.
8144 RX and X fields are specified using their lowest (starting) bit. The return
8145 value is:
8146
8147 0...31: single-precision registers s0...s31
8148 32...63: double-precision registers d0...d31.
906e58ca 8149
c7b8f16e
JB		 8150 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8151 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8152
c7b8f16e
JB		 8153static unsigned int
8154bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8155 unsigned int x)
c7b8f16e
JB		 8156{
8157 if (is_double)
8158 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8159 else
8160 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8161}
8162
8163/* Set bits in *WMASK according to a register number REG as encoded by
8164 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8165
8166static void
8167bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8168{
8169 if (reg < 32)
8170 *wmask |= 1 << reg;
8171 else if (reg < 48)
8172 *wmask |= 3 << ((reg - 32) * 2);
8173}
8174
8175/* Return TRUE if WMASK overwrites anything in REGS. */
8176
8177static bfd_boolean
8178bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8179{
8180 int i;
906e58ca 8181
c7b8f16e
JB		 8182 for (i = 0; i < numregs; i++)
8183 {
8184 unsigned int reg = regs[i];
8185
8186 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8187 return TRUE;
906e58ca 8188
c7b8f16e
JB		 8189 reg -= 32;
8190
8191 if (reg >= 16)
99059e56 8192 continue;
906e58ca 8193
c7b8f16e 8194 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8195 return TRUE;
c7b8f16e 8196 }
906e58ca 8197
c7b8f16e
JB		 8198 return FALSE;
8199}
8200
8201/* In this function, we're interested in two things: finding input registers
8202 for VFP data-processing instructions, and finding the set of registers which
8203 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8204 hold the written set, so FLDM etc. are easy to deal with (we're only
8205 interested in 32 SP registers or 16 dp registers, due to the VFP version
8206 implemented by the chip in question). DP registers are marked by setting
8207 both SP registers in the write mask). */
8208
8209static enum bfd_arm_vfp11_pipe
8210bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8211 int *numregs)
c7b8f16e 8212{
91d6fa6a 8213 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8214 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8215
8216 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8217 {
8218 unsigned int pqrs;
8219 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8220 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8221
8222 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8223 | ((insn & 0x00300000) >> 19)
8224 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8225
8226 switch (pqrs)
99059e56
RM		 8227 {
8228 case 0: /* fmac[sd]. */
8229 case 1: /* fnmac[sd]. */
8230 case 2: /* fmsc[sd]. */
8231 case 3: /* fnmsc[sd]. */
8232 vpipe = VFP11_FMAC;
8233 bfd_arm_vfp11_write_mask (destmask, fd);
8234 regs[0] = fd;
8235 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8236 regs[2] = fm;
8237 *numregs = 3;
8238 break;
8239
8240 case 4: /* fmul[sd]. */
8241 case 5: /* fnmul[sd]. */
8242 case 6: /* fadd[sd]. */
8243 case 7: /* fsub[sd]. */
8244 vpipe = VFP11_FMAC;
8245 goto vfp_binop;
8246
8247 case 8: /* fdiv[sd]. */
8248 vpipe = VFP11_DS;
8249 vfp_binop:
8250 bfd_arm_vfp11_write_mask (destmask, fd);
8251 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8252 regs[1] = fm;
8253 *numregs = 2;
8254 break;
8255
8256 case 15: /* extended opcode. */
8257 {
8258 unsigned int extn = ((insn >> 15) & 0x1e)
8259 | ((insn >> 7) & 1);
8260
8261 switch (extn)
8262 {
8263 case 0: /* fcpy[sd]. */
8264 case 1: /* fabs[sd]. */
8265 case 2: /* fneg[sd]. */
8266 case 8: /* fcmp[sd]. */
8267 case 9: /* fcmpe[sd]. */
8268 case 10: /* fcmpz[sd]. */
8269 case 11: /* fcmpez[sd]. */
8270 case 16: /* fuito[sd]. */
8271 case 17: /* fsito[sd]. */
8272 case 24: /* ftoui[sd]. */
8273 case 25: /* ftouiz[sd]. */
8274 case 26: /* ftosi[sd]. */
8275 case 27: /* ftosiz[sd]. */
8276 /* These instructions will not bounce due to underflow. */
8277 *numregs = 0;
8278 vpipe = VFP11_FMAC;
8279 break;
8280
8281 case 3: /* fsqrt[sd]. */
8282 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8283 registers to cause the erratum in previous instructions. */
8284 bfd_arm_vfp11_write_mask (destmask, fd);
8285 vpipe = VFP11_DS;
8286 break;
8287
8288 case 15: /* fcvt{ds,sd}. */
8289 {
8290 int rnum = 0;
8291
8292 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8293
8294 /* Only FCVTSD can underflow. */
99059e56
RM		 8295 if ((insn & 0x100) != 0)
8296 regs[rnum++] = fm;
c7b8f16e 8297
99059e56 8298 *numregs = rnum;
c7b8f16e 8299
99059e56
RM		 8300 vpipe = VFP11_FMAC;
8301 }
8302 break;
c7b8f16e 8303
99059e56
RM		 8304 default:
8305 return VFP11_BAD;
8306 }
8307 }
8308 break;
c7b8f16e 8309
99059e56
RM		 8310 default:
8311 return VFP11_BAD;
8312 }
c7b8f16e
JB		 8313 }
8314 /* Two-register transfer. */
8315 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8316 {
8317 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8318
c7b8f16e
JB		 8319 if ((insn & 0x100000) == 0)
8320 {
99059e56
RM		 8321 if (is_double)
8322 bfd_arm_vfp11_write_mask (destmask, fm);
8323 else
8324 {
8325 bfd_arm_vfp11_write_mask (destmask, fm);
8326 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8327 }
c7b8f16e
JB		 8328 }
8329
91d6fa6a 8330 vpipe = VFP11_LS;
c7b8f16e
JB		 8331 }
8332 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8333 {
8334 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8335 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8336
c7b8f16e 8337 switch (puw)
99059e56
RM		 8338 {
8339 case 0: /* Two-reg transfer. We should catch these above. */
8340 abort ();
906e58ca 8341
99059e56
RM		 8342 case 2: /* fldm[sdx]. */
8343 case 3:
8344 case 5:
8345 {
8346 unsigned int i, offset = insn & 0xff;
c7b8f16e 8347
99059e56
RM		 8348 if (is_double)
8349 offset >>= 1;
c7b8f16e 8350
99059e56
RM		 8351 for (i = fd; i < fd + offset; i++)
8352 bfd_arm_vfp11_write_mask (destmask, i);
8353 }
8354 break;
906e58ca 8355
99059e56
RM		 8356 case 4: /* fld[sd]. */
8357 case 6:
8358 bfd_arm_vfp11_write_mask (destmask, fd);
8359 break;
906e58ca 8360
99059e56
RM		 8361 default:
8362 return VFP11_BAD;
8363 }
c7b8f16e 8364
91d6fa6a 8365 vpipe = VFP11_LS;
c7b8f16e
JB		 8366 }
8367 /* Single-register transfer. Note L==0. */
8368 else if ((insn & 0x0f100e10) == 0x0e000a10)
8369 {
8370 unsigned int opcode = (insn >> 21) & 7;
8371 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8372
8373 switch (opcode)
99059e56
RM		 8374 {
8375 case 0: /* fmsr/fmdlr. */
8376 case 1: /* fmdhr. */
8377 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8378 destination register. I don't know if this is exactly right,
8379 but it is the conservative choice. */
8380 bfd_arm_vfp11_write_mask (destmask, fn);
8381 break;
8382
8383 case 7: /* fmxr. */
8384 break;
8385 }
c7b8f16e 8386
91d6fa6a 8387 vpipe = VFP11_LS;
c7b8f16e
JB		 8388 }
8389
91d6fa6a 8390 return vpipe;
c7b8f16e
JB		 8391}
8392
8393
8394static int elf32_arm_compare_mapping (const void * a, const void * b);
8395
8396
8397/* Look for potentially-troublesome code sequences which might trigger the
8398 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8399 (available from ARM) for details of the erratum. A short version is
8400 described in ld.texinfo. */
8401
8402bfd_boolean
8403bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8404{
8405 asection *sec;
8406 bfd_byte *contents = NULL;
8407 int state = 0;
8408 int regs[3], numregs = 0;
8409 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8410 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8411
4dfe6ac6
NC		 8412 if (globals == NULL)
8413 return FALSE;
8414
c7b8f16e
JB		 8415 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8416 The states transition as follows:
906e58ca 8417
c7b8f16e 8418 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8419 A VFP FMAC-pipeline instruction has been seen. Fill
8420 regs[0]..regs[numregs-1] with its input operands. Remember this
8421 instruction in 'first_fmac'.
c7b8f16e
JB		 8422
8423 1 -> 2
99059e56
RM		 8424 Any instruction, except for a VFP instruction which overwrites
8425 regs[*].
906e58ca 8426
c7b8f16e
JB		 8427 1 -> 3 [ -> 0 ] or
8428 2 -> 3 [ -> 0 ]
99059e56
RM		 8429 A VFP instruction has been seen which overwrites any of regs[*].
8430 We must make a veneer! Reset state to 0 before examining next
8431 instruction.
906e58ca 8432
c7b8f16e 8433 2 -> 0
99059e56
RM		 8434 If we fail to match anything in state 2, reset to state 0 and reset
8435 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8436
8437 If the VFP11 vector mode is in use, there must be at least two unrelated
8438 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8439 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8440
8441 /* If we are only performing a partial link do not bother
8442 to construct any glue. */
0e1862bb 8443 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8444 return TRUE;
8445
0ffa91dd
NC		 8446 /* Skip if this bfd does not correspond to an ELF image. */
8447 if (! is_arm_elf (abfd))
8448 return TRUE;
906e58ca 8449
c7b8f16e
JB		 8450 /* We should have chosen a fix type by the time we get here. */
8451 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8452
8453 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8454 return TRUE;
2e6030b9 8455
33a7ffc2
JM		 8456 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8457 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8458 return TRUE;
8459
c7b8f16e
JB		 8460 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8461 {
8462 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8463 struct _arm_elf_section_data *sec_data;
8464
8465 /* If we don't have executable progbits, we're not interested in this
99059e56 8466 section. Also skip if section is to be excluded. */
c7b8f16e 8467 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8468 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8469 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8470 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8471 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8472 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8473 continue;
c7b8f16e
JB		 8474
8475 sec_data = elf32_arm_section_data (sec);
906e58ca 8476
c7b8f16e 8477 if (sec_data->mapcount == 0)
99059e56 8478 continue;
906e58ca 8479
c7b8f16e
JB		 8480 if (elf_section_data (sec)->this_hdr.contents != NULL)
8481 contents = elf_section_data (sec)->this_hdr.contents;
8482 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8483 goto error_return;
8484
8485 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8486 elf32_arm_compare_mapping);
8487
8488 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8489 {
8490 unsigned int span_start = sec_data->map[span].vma;
8491 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8492 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8493 char span_type = sec_data->map[span].type;
8494
8495 /* FIXME: Only ARM mode is supported at present. We may need to
8496 support Thumb-2 mode also at some point. */
8497 if (span_type != 'a')
8498 continue;
8499
8500 for (i = span_start; i < span_end;)
8501 {
8502 unsigned int next_i = i + 4;
8503 unsigned int insn = bfd_big_endian (abfd)
13c9c485
AM		 8504 ? (((unsigned) contents[i] << 24)
8505 | (contents[i + 1] << 16)
8506 | (contents[i + 2] << 8)
8507 | contents[i + 3])
8508 : (((unsigned) contents[i + 3] << 24)
8509 | (contents[i + 2] << 16)
8510 | (contents[i + 1] << 8)
8511 | contents[i]);
99059e56
RM		 8512 unsigned int writemask = 0;
8513 enum bfd_arm_vfp11_pipe vpipe;
8514
8515 switch (state)
8516 {
8517 case 0:
8518 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8519 &numregs);
8520 /* I'm assuming the VFP11 erratum can trigger with denorm
8521 operands on either the FMAC or the DS pipeline. This might
8522 lead to slightly overenthusiastic veneer insertion. */
8523 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8524 {
8525 state = use_vector ? 1 : 2;
8526 first_fmac = i;
8527 veneer_of_insn = insn;
8528 }
8529 break;
8530
8531 case 1:
8532 {
8533 int other_regs[3], other_numregs;
8534 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8535 other_regs,
99059e56
RM		 8536 &other_numregs);
8537 if (vpipe != VFP11_BAD
8538 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8539 numregs))
99059e56
RM		 8540 state = 3;
8541 else
8542 state = 2;
8543 }
8544 break;
8545
8546 case 2:
8547 {
8548 int other_regs[3], other_numregs;
8549 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8550 other_regs,
99059e56
RM		 8551 &other_numregs);
8552 if (vpipe != VFP11_BAD
8553 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8554 numregs))
99059e56
RM		 8555 state = 3;
8556 else
8557 {
8558 state = 0;
8559 next_i = first_fmac + 4;
8560 }
8561 }
8562 break;
8563
8564 case 3:
8565 abort (); /* Should be unreachable. */
8566 }
8567
8568 if (state == 3)
8569 {
8570 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8571 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8572
8573 elf32_arm_section_data (sec)->erratumcount += 1;
8574
8575 newerr->u.b.vfp_insn = veneer_of_insn;
8576
8577 switch (span_type)
8578 {
8579 case 'a':
8580 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8581 break;
8582
8583 default:
8584 abort ();
8585 }
8586
8587 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8588 first_fmac);
8589
99059e56 8590 newerr->vma = -1;
c7b8f16e 8591
99059e56
RM		 8592 newerr->next = sec_data->erratumlist;
8593 sec_data->erratumlist = newerr;
c7b8f16e 8594
99059e56
RM		 8595 state = 0;
8596 }
c7b8f16e 8597
99059e56
RM		 8598 i = next_i;
8599 }
8600 }
906e58ca 8601
c7b8f16e 8602 if (contents != NULL
99059e56
RM		 8603 && elf_section_data (sec)->this_hdr.contents != contents)
8604 free (contents);
c7b8f16e
JB		 8605 contents = NULL;
8606 }
8607
8608 return TRUE;
8609
8610error_return:
8611 if (contents != NULL
8612 && elf_section_data (sec)->this_hdr.contents != contents)
8613 free (contents);
906e58ca 8614
c7b8f16e
JB		 8615 return FALSE;
8616}
8617
8618/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8619 after sections have been laid out, using specially-named symbols. */
8620
8621void
8622bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8623 struct bfd_link_info *link_info)
8624{
8625 asection *sec;
8626 struct elf32_arm_link_hash_table *globals;
8627 char *tmp_name;
906e58ca 8628
0e1862bb 8629 if (bfd_link_relocatable (link_info))
c7b8f16e 8630 return;
2e6030b9
MS		 8631
8632 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8633 if (! is_arm_elf (abfd))
2e6030b9
MS		 8634 return;
8635
c7b8f16e 8636 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8637 if (globals == NULL)
8638 return;
906e58ca 8639
21d799b5 8640 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8641 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8642 BFD_ASSERT (tmp_name);
c7b8f16e
JB		 8643
8644 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8645 {
8646 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8647 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8648
c7b8f16e 8649 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8650 {
8651 struct elf_link_hash_entry *myh;
8652 bfd_vma vma;
8653
8654 switch (errnode->type)
8655 {
8656 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8657 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8658 /* Find veneer symbol. */
8659 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8660 errnode->u.b.veneer->u.v.id);
8661
99059e56
RM		 8662 myh = elf_link_hash_lookup
8663 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8664
a504d23a 8665 if (myh == NULL)
90b6238f
AM		 8666 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8667 abfd, "VFP11", tmp_name);
a504d23a
LA		 8668
8669 vma = myh->root.u.def.section->output_section->vma
8670 + myh->root.u.def.section->output_offset
8671 + myh->root.u.def.value;
8672
8673 errnode->u.b.veneer->vma = vma;
8674 break;
8675
8676 case VFP11_ERRATUM_ARM_VENEER:
8677 case VFP11_ERRATUM_THUMB_VENEER:
8678 /* Find return location. */
8679 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8680 errnode->u.v.id);
8681
8682 myh = elf_link_hash_lookup
8683 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8684
8685 if (myh == NULL)
90b6238f
AM		 8686 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8687 abfd, "VFP11", tmp_name);
a504d23a
LA		 8688
8689 vma = myh->root.u.def.section->output_section->vma
8690 + myh->root.u.def.section->output_offset
8691 + myh->root.u.def.value;
8692
8693 errnode->u.v.branch->vma = vma;
8694 break;
8695
8696 default:
8697 abort ();
8698 }
8699 }
8700 }
8701
8702 free (tmp_name);
8703}
8704
8705/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8706 return locations after sections have been laid out, using
8707 specially-named symbols. */
8708
8709void
8710bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8711 struct bfd_link_info *link_info)
8712{
8713 asection *sec;
8714 struct elf32_arm_link_hash_table *globals;
8715 char *tmp_name;
8716
8717 if (bfd_link_relocatable (link_info))
8718 return;
8719
8720 /* Skip if this bfd does not correspond to an ELF image. */
8721 if (! is_arm_elf (abfd))
8722 return;
8723
8724 globals = elf32_arm_hash_table (link_info);
8725 if (globals == NULL)
8726 return;
8727
8728 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8729 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8730 BFD_ASSERT (tmp_name);
a504d23a
LA		 8731
8732 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8733 {
8734 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8735 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8736
8737 for (; errnode != NULL; errnode = errnode->next)
8738 {
8739 struct elf_link_hash_entry *myh;
8740 bfd_vma vma;
8741
8742 switch (errnode->type)
8743 {
8744 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8745 /* Find veneer symbol. */
8746 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8747 errnode->u.b.veneer->u.v.id);
8748
8749 myh = elf_link_hash_lookup
8750 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8751
8752 if (myh == NULL)
90b6238f
AM		 8753 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8754 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8755
8756 vma = myh->root.u.def.section->output_section->vma
8757 + myh->root.u.def.section->output_offset
8758 + myh->root.u.def.value;
8759
8760 errnode->u.b.veneer->vma = vma;
8761 break;
8762
8763 case STM32L4XX_ERRATUM_VENEER:
8764 /* Find return location. */
8765 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8766 errnode->u.v.id);
8767
8768 myh = elf_link_hash_lookup
8769 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8770
8771 if (myh == NULL)
90b6238f
AM		 8772 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8773 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8774
8775 vma = myh->root.u.def.section->output_section->vma
8776 + myh->root.u.def.section->output_offset
8777 + myh->root.u.def.value;
8778
8779 errnode->u.v.branch->vma = vma;
8780 break;
8781
8782 default:
8783 abort ();
8784 }
8785 }
8786 }
8787
8788 free (tmp_name);
8789}
8790
8791static inline bfd_boolean
8792is_thumb2_ldmia (const insn32 insn)
8793{
8794 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8795 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8796 return (insn & 0xffd02000) == 0xe8900000;
8797}
8798
8799static inline bfd_boolean
8800is_thumb2_ldmdb (const insn32 insn)
8801{
8802 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8803 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8804 return (insn & 0xffd02000) == 0xe9100000;
8805}
8806
8807static inline bfd_boolean
8808is_thumb2_vldm (const insn32 insn)
8809{
8810 /* A6.5 Extension register load or store instruction
8811 A7.7.229
9239bbd3
CM		 8812 We look for SP 32-bit and DP 64-bit registers.
8813 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8814 <list> is consecutive 64-bit registers
8815 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8816 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8817 <list> is consecutive 32-bit registers
8818 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8819 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8820 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8821 return
9239bbd3
CM		 8822 (((insn & 0xfe100f00) == 0xec100b00) ||
8823 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8824 && /* (IA without !). */
8825 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8826 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8827 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8828 /* (DB with !). */
8829 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8830}
8831
8832/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8833 VLDM opcode and:
8834 - computes the number and the mode of memory accesses
8835 - decides if the replacement should be done:
8836 . replaces only if > 8-word accesses
8837 . or (testing purposes only) replaces all accesses. */
8838
8839static bfd_boolean
8840stm32l4xx_need_create_replacing_stub (const insn32 insn,
8841 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8842{
9239bbd3 8843 int nb_words = 0;
a504d23a
LA		 8844
8845 /* The field encoding the register list is the same for both LDMIA
8846 and LDMDB encodings. */
8847 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8848 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8849 else if (is_thumb2_vldm (insn))
9239bbd3 8850 nb_words = (insn & 0xff);
a504d23a
LA		 8851
8852 /* DEFAULT mode accounts for the real bug condition situation,
8853 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8854 return
9239bbd3 8855 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8856 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8857}
8858
8859/* Look for potentially-troublesome code sequences which might trigger
8860 the STM STM32L4XX erratum. */
8861
8862bfd_boolean
8863bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8864 struct bfd_link_info *link_info)
8865{
8866 asection *sec;
8867 bfd_byte *contents = NULL;
8868 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8869
8870 if (globals == NULL)
8871 return FALSE;
8872
8873 /* If we are only performing a partial link do not bother
8874 to construct any glue. */
8875 if (bfd_link_relocatable (link_info))
8876 return TRUE;
8877
8878 /* Skip if this bfd does not correspond to an ELF image. */
8879 if (! is_arm_elf (abfd))
8880 return TRUE;
8881
8882 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8883 return TRUE;
8884
8885 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8886 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8887 return TRUE;
8888
8889 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8890 {
8891 unsigned int i, span;
8892 struct _arm_elf_section_data *sec_data;
8893
8894 /* If we don't have executable progbits, we're not interested in this
8895 section. Also skip if section is to be excluded. */
8896 if (elf_section_type (sec) != SHT_PROGBITS
8897 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8898 || (sec->flags & SEC_EXCLUDE) != 0
8899 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8900 || sec->output_section == bfd_abs_section_ptr
8901 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8902 continue;
8903
8904 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8905
a504d23a
LA		 8906 if (sec_data->mapcount == 0)
8907 continue;
c7b8f16e 8908
a504d23a
LA		 8909 if (elf_section_data (sec)->this_hdr.contents != NULL)
8910 contents = elf_section_data (sec)->this_hdr.contents;
8911 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8912 goto error_return;
c7b8f16e 8913
a504d23a
LA		 8914 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8915 elf32_arm_compare_mapping);
c7b8f16e 8916
a504d23a
LA		 8917 for (span = 0; span < sec_data->mapcount; span++)
8918 {
8919 unsigned int span_start = sec_data->map[span].vma;
8920 unsigned int span_end = (span == sec_data->mapcount - 1)
8921 ? sec->size : sec_data->map[span + 1].vma;
8922 char span_type = sec_data->map[span].type;
8923 int itblock_current_pos = 0;
c7b8f16e 8924
a504d23a
LA		 8925 /* Only Thumb2 mode need be supported with this CM4 specific
8926 code, we should not encounter any arm mode eg span_type
8927 != 'a'. */
8928 if (span_type != 't')
8929 continue;
c7b8f16e 8930
a504d23a
LA		 8931 for (i = span_start; i < span_end;)
8932 {
8933 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8934 bfd_boolean insn_32bit = FALSE;
8935 bfd_boolean is_ldm = FALSE;
8936 bfd_boolean is_vldm = FALSE;
8937 bfd_boolean is_not_last_in_it_block = FALSE;
8938
8939 /* The first 16-bits of all 32-bit thumb2 instructions start
8940 with opcode[15..13]=0b111 and the encoded op1 can be anything
8941 except opcode[12..11]!=0b00.
8942 See 32-bit Thumb instruction encoding. */
8943 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8944 insn_32bit = TRUE;
c7b8f16e 8945
a504d23a
LA		 8946 /* Compute the predicate that tells if the instruction
8947 is concerned by the IT block
8948 - Creates an error if there is a ldm that is not
8949 last in the IT block thus cannot be replaced
8950 - Otherwise we can create a branch at the end of the
8951 IT block, it will be controlled naturally by IT
8952 with the proper pseudo-predicate
8953 - So the only interesting predicate is the one that
8954 tells that we are not on the last item of an IT
8955 block. */
8956 if (itblock_current_pos != 0)
8957 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8958
a504d23a
LA		 8959 if (insn_32bit)
8960 {
8961 /* Load the rest of the insn (in manual-friendly order). */
8962 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8963 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8964 is_vldm = is_thumb2_vldm (insn);
8965
8966 /* Veneers are created for (v)ldm depending on
8967 option flags and memory accesses conditions; but
8968 if the instruction is not the last instruction of
8969 an IT block, we cannot create a jump there, so we
8970 bail out. */
5025eb7c
AO		 8971 if ((is_ldm || is_vldm)
8972 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8973 (insn, globals->stm32l4xx_fix))
8974 {
8975 if (is_not_last_in_it_block)
8976 {
4eca0228 8977 _bfd_error_handler
695344c0 8978 /* xgettext:c-format */
871b3ab2 8979 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8980 " in non-last IT block instruction:"
8981 " STM32L4XX veneer cannot be generated; "
8982 "use gcc option -mrestrict-it to generate"
8983 " only one instruction per IT block"),
d42c267e 8984 abfd, sec, i);
a504d23a
LA		 8985 }
8986 else
8987 {
8988 elf32_stm32l4xx_erratum_list *newerr =
8989 (elf32_stm32l4xx_erratum_list *)
8990 bfd_zmalloc
8991 (sizeof (elf32_stm32l4xx_erratum_list));
8992
8993 elf32_arm_section_data (sec)
8994 ->stm32l4xx_erratumcount += 1;
8995 newerr->u.b.insn = insn;
8996 /* We create only thumb branches. */
8997 newerr->type =
8998 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8999 record_stm32l4xx_erratum_veneer
9000 (link_info, newerr, abfd, sec,
9001 i,
9002 is_ldm ?
9003 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
9004 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
9005 newerr->vma = -1;
9006 newerr->next = sec_data->stm32l4xx_erratumlist;
9007 sec_data->stm32l4xx_erratumlist = newerr;
9008 }
9009 }
9010 }
9011 else
9012 {
9013 /* A7.7.37 IT p208
9014 IT blocks are only encoded in T1
9015 Encoding T1: IT{x{y{z}}} <firstcond>
9016 1 0 1 1 - 1 1 1 1 - firstcond - mask
9017 if mask = '0000' then see 'related encodings'
9018 We don't deal with UNPREDICTABLE, just ignore these.
9019 There can be no nested IT blocks so an IT block
9020 is naturally a new one for which it is worth
9021 computing its size. */
5025eb7c
AO		 9022 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
9023 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 9024 /* If we have a new IT block we compute its size. */
9025 if (is_newitblock)
9026 {
9027 /* Compute the number of instructions controlled
9028 by the IT block, it will be used to decide
9029 whether we are inside an IT block or not. */
9030 unsigned int mask = insn & 0x000f;
9031 itblock_current_pos = 4 - ctz (mask);
9032 }
9033 }
9034
9035 i += insn_32bit ? 4 : 2;
99059e56
RM		 9036 }
9037 }
a504d23a
LA		 9038
9039 if (contents != NULL
9040 && elf_section_data (sec)->this_hdr.contents != contents)
9041 free (contents);
9042 contents = NULL;
c7b8f16e 9043 }
906e58ca 9044
a504d23a
LA		 9045 return TRUE;
9046
9047error_return:
9048 if (contents != NULL
9049 && elf_section_data (sec)->this_hdr.contents != contents)
9050 free (contents);
c7b8f16e 9051
a504d23a
LA		 9052 return FALSE;
9053}
c7b8f16e 9054
eb043451
PB		 9055/* Set target relocation values needed during linking. */
9056
9057void
68c39892 9058bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9059 struct bfd_link_info *link_info,
68c39892 9060 struct elf32_arm_params *params)
eb043451
PB		 9061{
9062 struct elf32_arm_link_hash_table *globals;
9063
9064 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9065 if (globals == NULL)
9066 return;
eb043451 9067
68c39892 9068 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9069 if (globals->fdpic_p)
9070 globals->target2_reloc = R_ARM_GOT32;
9071 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9072 globals->target2_reloc = R_ARM_REL32;
68c39892 9073 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9074 globals->target2_reloc = R_ARM_ABS32;
68c39892 9075 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9076 globals->target2_reloc = R_ARM_GOT_PREL;
9077 else
9078 {
90b6238f 9079 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9080 params->target2_type);
eb043451 9081 }
68c39892
TP		 9082 globals->fix_v4bx = params->fix_v4bx;
9083 globals->use_blx |= params->use_blx;
9084 globals->vfp11_fix = params->vfp11_denorm_fix;
9085 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9086 if (globals->fdpic_p)
9087 globals->pic_veneer = 1;
9088 else
9089 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9090 globals->fix_cortex_a8 = params->fix_cortex_a8;
9091 globals->fix_arm1176 = params->fix_arm1176;
9092 globals->cmse_implib = params->cmse_implib;
9093 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9094
0ffa91dd 9095 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9096 elf_arm_tdata (output_bfd)->no_enum_size_warning
9097 = params->no_enum_size_warning;
9098 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9099 = params->no_wchar_size_warning;
eb043451 9100}
eb043451 9101
12a0a0fd 9102/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9103
12a0a0fd
PB		 9104static void
9105insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9106{
9107 bfd_vma upper;
9108 bfd_vma lower;
9109 int reloc_sign;
9110
9111 BFD_ASSERT ((offset & 1) == 0);
9112
9113 upper = bfd_get_16 (abfd, insn);
9114 lower = bfd_get_16 (abfd, insn + 2);
9115 reloc_sign = (offset < 0) ? 1 : 0;
9116 upper = (upper & ~(bfd_vma) 0x7ff)
9117 | ((offset >> 12) & 0x3ff)
9118 | (reloc_sign << 10);
906e58ca 9119 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9120 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9121 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9122 | ((offset >> 1) & 0x7ff);
9123 bfd_put_16 (abfd, upper, insn);
9124 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9125}
9126
9b485d32
NC		 9127/* Thumb code calling an ARM function. */
9128
252b5132 9129static int
57e8b36a 9130elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9131 const char * name,
9132 bfd * input_bfd,
9133 bfd * output_bfd,
9134 asection * input_section,
9135 bfd_byte * hit_data,
9136 asection * sym_sec,
9137 bfd_vma offset,
9138 bfd_signed_vma addend,
9139 bfd_vma val,
f2a9dd69 9140 char **error_message)
252b5132 9141{
bcbdc74c 9142 asection * s = 0;
dc810e39 9143 bfd_vma my_offset;
252b5132 9144 long int ret_offset;
bcbdc74c
NC		 9145 struct elf_link_hash_entry * myh;
9146 struct elf32_arm_link_hash_table * globals;
252b5132 9147
f2a9dd69 9148 myh = find_thumb_glue (info, name, error_message);
252b5132 9149 if (myh == NULL)
b34976b6 9150 return FALSE;
252b5132
RH		 9151
9152 globals = elf32_arm_hash_table (info);
252b5132
RH		 9153 BFD_ASSERT (globals != NULL);
9154 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9155
9156 my_offset = myh->root.u.def.value;
9157
3d4d4302
AM		 9158 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9159 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9160
9161 BFD_ASSERT (s != NULL);
9162 BFD_ASSERT (s->contents != NULL);
9163 BFD_ASSERT (s->output_section != NULL);
9164
9165 if ((my_offset & 0x01) == 0x01)
9166 {
9167 if (sym_sec != NULL
9168 && sym_sec->owner != NULL
9169 && !INTERWORK_FLAG (sym_sec->owner))
9170 {
4eca0228 9171 _bfd_error_handler
90b6238f
AM		 9172 (_("%pB(%s): warning: interworking not enabled;"
9173 " first occurrence: %pB: %s call to %s"),
9174 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9175
b34976b6 9176 return FALSE;
252b5132
RH		 9177 }
9178
9179 --my_offset;
9180 myh->root.u.def.value = my_offset;
9181
52ab56c2
PB		 9182 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9183 s->contents + my_offset);
252b5132 9184
52ab56c2
PB		 9185 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9186 s->contents + my_offset + 2);
252b5132
RH		 9187
9188 ret_offset =
9b485d32
NC		 9189 /* Address of destination of the stub. */
9190 ((bfd_signed_vma) val)
252b5132 9191 - ((bfd_signed_vma)
57e8b36a
NC		 9192 /* Offset from the start of the current section
9193 to the start of the stubs. */
9b485d32
NC		 9194 (s->output_offset
9195 /* Offset of the start of this stub from the start of the stubs. */
9196 + my_offset
9197 /* Address of the start of the current section. */
9198 + s->output_section->vma)
9199 /* The branch instruction is 4 bytes into the stub. */
9200 + 4
9201 /* ARM branches work from the pc of the instruction + 8. */
9202 + 8);
252b5132 9203
52ab56c2
PB		 9204 put_arm_insn (globals, output_bfd,
9205 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9206 s->contents + my_offset + 4);
252b5132
RH		 9207 }
9208
9209 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9210
427bfd90
NC		 9211 /* Now go back and fix up the original BL insn to point to here. */
9212 ret_offset =
9213 /* Address of where the stub is located. */
9214 (s->output_section->vma + s->output_offset + my_offset)
9215 /* Address of where the BL is located. */
57e8b36a
NC		 9216 - (input_section->output_section->vma + input_section->output_offset
9217 + offset)
427bfd90
NC		 9218 /* Addend in the relocation. */
9219 - addend
9220 /* Biassing for PC-relative addressing. */
9221 - 8;
252b5132 9222
12a0a0fd 9223 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9224
b34976b6 9225 return TRUE;
252b5132
RH		 9226}
9227
a4fd1a8e 9228/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9229
a4fd1a8e
PB		 9230static struct elf_link_hash_entry *
9231elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9232 const char * name,
9233 bfd * input_bfd,
9234 bfd * output_bfd,
9235 asection * sym_sec,
9236 bfd_vma val,
9237 asection * s,
9238 char ** error_message)
252b5132 9239{
dc810e39 9240 bfd_vma my_offset;
252b5132 9241 long int ret_offset;
bcbdc74c
NC		 9242 struct elf_link_hash_entry * myh;
9243 struct elf32_arm_link_hash_table * globals;
252b5132 9244
f2a9dd69 9245 myh = find_arm_glue (info, name, error_message);
252b5132 9246 if (myh == NULL)
a4fd1a8e 9247 return NULL;
252b5132
RH		 9248
9249 globals = elf32_arm_hash_table (info);
252b5132
RH		 9250 BFD_ASSERT (globals != NULL);
9251 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9252
9253 my_offset = myh->root.u.def.value;
252b5132
RH		 9254
9255 if ((my_offset & 0x01) == 0x01)
9256 {
9257 if (sym_sec != NULL
9258 && sym_sec->owner != NULL
9259 && !INTERWORK_FLAG (sym_sec->owner))
9260 {
4eca0228 9261 _bfd_error_handler
90b6238f
AM		 9262 (_("%pB(%s): warning: interworking not enabled;"
9263 " first occurrence: %pB: %s call to %s"),
9264 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9265 }
9b485d32 9266
252b5132
RH		 9267 --my_offset;
9268 myh->root.u.def.value = my_offset;
9269
0e1862bb
L		 9270 if (bfd_link_pic (info)
9271 || globals->root.is_relocatable_executable
27e55c4d 9272 || globals->pic_veneer)
8f6277f5
PB		 9273 {
9274 /* For relocatable objects we can't use absolute addresses,
9275 so construct the address from a relative offset. */
9276 /* TODO: If the offset is small it's probably worth
9277 constructing the address with adds. */
52ab56c2
PB		 9278 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9279 s->contents + my_offset);
9280 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9281 s->contents + my_offset + 4);
9282 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9283 s->contents + my_offset + 8);
8f6277f5
PB		 9284 /* Adjust the offset by 4 for the position of the add,
9285 and 8 for the pipeline offset. */
9286 ret_offset = (val - (s->output_offset
9287 + s->output_section->vma
9288 + my_offset + 12))
9289 | 1;
9290 bfd_put_32 (output_bfd, ret_offset,
9291 s->contents + my_offset + 12);
9292 }
26079076
PB		 9293 else if (globals->use_blx)
9294 {
9295 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9296 s->contents + my_offset);
9297
9298 /* It's a thumb address. Add the low order bit. */
9299 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9300 s->contents + my_offset + 4);
9301 }
8f6277f5
PB		 9302 else
9303 {
52ab56c2
PB		 9304 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9305 s->contents + my_offset);
252b5132 9306
52ab56c2
PB		 9307 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9308 s->contents + my_offset + 4);
252b5132 9309
8f6277f5
PB		 9310 /* It's a thumb address. Add the low order bit. */
9311 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9312 s->contents + my_offset + 8);
8029a119
NC		 9313
9314 my_offset += 12;
8f6277f5 9315 }
252b5132
RH		 9316 }
9317
9318 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9319
a4fd1a8e
PB		 9320 return myh;
9321}
9322
9323/* Arm code calling a Thumb function. */
9324
9325static int
9326elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9327 const char * name,
9328 bfd * input_bfd,
9329 bfd * output_bfd,
9330 asection * input_section,
9331 bfd_byte * hit_data,
9332 asection * sym_sec,
9333 bfd_vma offset,
9334 bfd_signed_vma addend,
9335 bfd_vma val,
f2a9dd69 9336 char **error_message)
a4fd1a8e
PB		 9337{
9338 unsigned long int tmp;
9339 bfd_vma my_offset;
9340 asection * s;
9341 long int ret_offset;
9342 struct elf_link_hash_entry * myh;
9343 struct elf32_arm_link_hash_table * globals;
9344
9345 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9346 BFD_ASSERT (globals != NULL);
9347 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9348
3d4d4302
AM		 9349 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9350 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9351 BFD_ASSERT (s != NULL);
9352 BFD_ASSERT (s->contents != NULL);
9353 BFD_ASSERT (s->output_section != NULL);
9354
9355 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9356 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9357 if (!myh)
9358 return FALSE;
9359
9360 my_offset = myh->root.u.def.value;
252b5132
RH		 9361 tmp = bfd_get_32 (input_bfd, hit_data);
9362 tmp = tmp & 0xFF000000;
9363
9b485d32 9364 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9365 ret_offset = (s->output_offset
9366 + my_offset
9367 + s->output_section->vma
9368 - (input_section->output_offset
9369 + input_section->output_section->vma
9370 + offset + addend)
9371 - 8);
9a5aca8c 9372
252b5132
RH		 9373 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9374
dc810e39 9375 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9376
b34976b6 9377 return TRUE;
252b5132
RH		 9378}
9379
a4fd1a8e
PB		 9380/* Populate Arm stub for an exported Thumb function. */
9381
9382static bfd_boolean
9383elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9384{
9385 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9386 asection * s;
9387 struct elf_link_hash_entry * myh;
9388 struct elf32_arm_link_hash_entry *eh;
9389 struct elf32_arm_link_hash_table * globals;
9390 asection *sec;
9391 bfd_vma val;
f2a9dd69 9392 char *error_message;
a4fd1a8e 9393
906e58ca 9394 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9395 /* Allocate stubs for exported Thumb functions on v4t. */
9396 if (eh->export_glue == NULL)
9397 return TRUE;
9398
9399 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9400 BFD_ASSERT (globals != NULL);
9401 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9402
3d4d4302
AM		 9403 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9404 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9405 BFD_ASSERT (s != NULL);
9406 BFD_ASSERT (s->contents != NULL);
9407 BFD_ASSERT (s->output_section != NULL);
9408
9409 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9410
9411 BFD_ASSERT (sec->output_section != NULL);
9412
a4fd1a8e
PB		 9413 val = eh->export_glue->root.u.def.value + sec->output_offset
9414 + sec->output_section->vma;
8029a119 9415
a4fd1a8e
PB		 9416 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9417 h->root.u.def.section->owner,
f2a9dd69
DJ		 9418 globals->obfd, sec, val, s,
9419 &error_message);
a4fd1a8e
PB		 9420 BFD_ASSERT (myh);
9421 return TRUE;
9422}
9423
845b51d6
PB		 9424/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9425
9426static bfd_vma
9427elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9428{
9429 bfd_byte *p;
9430 bfd_vma glue_addr;
9431 asection *s;
9432 struct elf32_arm_link_hash_table *globals;
9433
9434 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9435 BFD_ASSERT (globals != NULL);
9436 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9437
3d4d4302
AM		 9438 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9439 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9440 BFD_ASSERT (s != NULL);
9441 BFD_ASSERT (s->contents != NULL);
9442 BFD_ASSERT (s->output_section != NULL);
9443
9444 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9445
9446 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9447
9448 if ((globals->bx_glue_offset[reg] & 1) == 0)
9449 {
9450 p = s->contents + glue_addr;
9451 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9452 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9453 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9454 globals->bx_glue_offset[reg] |= 1;
9455 }
9456
9457 return glue_addr + s->output_section->vma + s->output_offset;
9458}
9459
a4fd1a8e
PB		 9460/* Generate Arm stubs for exported Thumb symbols. */
9461static void
906e58ca 9462elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9463 struct bfd_link_info *link_info)
9464{
9465 struct elf32_arm_link_hash_table * globals;
9466
8029a119
NC		 9467 if (link_info == NULL)
9468 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9469 return;
9470
9471 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9472 if (globals == NULL)
9473 return;
9474
84c08195
PB		 9475 /* If blx is available then exported Thumb symbols are OK and there is
9476 nothing to do. */
a4fd1a8e
PB		 9477 if (globals->use_blx)
9478 return;
9479
9480 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9481 link_info);
9482}
9483
47beaa6a
RS		 9484/* Reserve space for COUNT dynamic relocations in relocation selection
9485 SRELOC. */
9486
9487static void
9488elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9489 bfd_size_type count)
9490{
9491 struct elf32_arm_link_hash_table *htab;
9492
9493 htab = elf32_arm_hash_table (info);
9494 BFD_ASSERT (htab->root.dynamic_sections_created);
9495 if (sreloc == NULL)
9496 abort ();
9497 sreloc->size += RELOC_SIZE (htab) * count;
9498}
9499
34e77a92
RS		 9500/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9501 dynamic, the relocations should go in SRELOC, otherwise they should
9502 go in the special .rel.iplt section. */
9503
9504static void
9505elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9506 bfd_size_type count)
9507{
9508 struct elf32_arm_link_hash_table *htab;
9509
9510 htab = elf32_arm_hash_table (info);
9511 if (!htab->root.dynamic_sections_created)
9512 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9513 else
9514 {
9515 BFD_ASSERT (sreloc != NULL);
9516 sreloc->size += RELOC_SIZE (htab) * count;
9517 }
9518}
9519
47beaa6a
RS		 9520/* Add relocation REL to the end of relocation section SRELOC. */
9521
9522static void
9523elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9524 asection *sreloc, Elf_Internal_Rela *rel)
9525{
9526 bfd_byte *loc;
9527 struct elf32_arm_link_hash_table *htab;
9528
9529 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9530 if (!htab->root.dynamic_sections_created
9531 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9532 sreloc = htab->root.irelplt;
47beaa6a
RS		 9533 if (sreloc == NULL)
9534 abort ();
9535 loc = sreloc->contents;
9536 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9537 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9538 abort ();
9539 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9540}
9541
34e77a92
RS		 9542/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9543 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9544 to .plt. */
9545
9546static void
9547elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9548 bfd_boolean is_iplt_entry,
9549 union gotplt_union *root_plt,
9550 struct arm_plt_info *arm_plt)
9551{
9552 struct elf32_arm_link_hash_table *htab;
9553 asection *splt;
9554 asection *sgotplt;
9555
9556 htab = elf32_arm_hash_table (info);
9557
9558 if (is_iplt_entry)
9559 {
9560 splt = htab->root.iplt;
9561 sgotplt = htab->root.igotplt;
9562
99059e56
RM		 9563 /* NaCl uses a special first entry in .iplt too. */
9564 if (htab->nacl_p && splt->size == 0)
9565 splt->size += htab->plt_header_size;
9566
34e77a92
RS		 9567 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9568 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9569 }
9570 else
9571 {
9572 splt = htab->root.splt;
9573 sgotplt = htab->root.sgotplt;
9574
7801f98f
CL		 9575 if (htab->fdpic_p)
9576 {
9577 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9578 /* For lazy binding, relocations will be put into .rel.plt, in
9579 .rel.got otherwise. */
9580 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9581 if (info->flags & DF_BIND_NOW)
9582 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9583 else
9584 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9585 }
9586 else
9587 {
9588 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9589 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9590 }
34e77a92
RS		 9591
9592 /* If this is the first .plt entry, make room for the special
9593 first entry. */
9594 if (splt->size == 0)
9595 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9596
9597 htab->next_tls_desc_index++;
34e77a92
RS		 9598 }
9599
9600 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9601 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9602 splt->size += PLT_THUMB_STUB_SIZE;
9603 root_plt->offset = splt->size;
9604 splt->size += htab->plt_entry_size;
9605
9606 if (!htab->symbian_p)
9607 {
9608 /* We also need to make an entry in the .got.plt section, which
9609 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9610 if (is_iplt_entry)
9611 arm_plt->got_offset = sgotplt->size;
9612 else
9613 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9614 if (htab->fdpic_p)
9615 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9616 sgotplt->size += 8;
7801f98f
CL		 9617 else
9618 sgotplt->size += 4;
34e77a92
RS		 9619 }
9620}
9621
b38cadfb
NC		 9622static bfd_vma
9623arm_movw_immediate (bfd_vma value)
9624{
9625 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9626}
9627
9628static bfd_vma
9629arm_movt_immediate (bfd_vma value)
9630{
9631 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9632}
9633
34e77a92
RS		 9634/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9635 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9636 Otherwise, DYNINDX is the index of the symbol in the dynamic
9637 symbol table and SYM_VALUE is undefined.
9638
9639 ROOT_PLT points to the offset of the PLT entry from the start of its
9640 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9641 bookkeeping information.
34e77a92 9642
57460bcf
NC		 9643 Returns FALSE if there was a problem. */
9644
9645static bfd_boolean
34e77a92
RS		 9646elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9647 union gotplt_union *root_plt,
9648 struct arm_plt_info *arm_plt,
9649 int dynindx, bfd_vma sym_value)
9650{
9651 struct elf32_arm_link_hash_table *htab;
9652 asection *sgot;
9653 asection *splt;
9654 asection *srel;
9655 bfd_byte *loc;
9656 bfd_vma plt_index;
9657 Elf_Internal_Rela rel;
9658 bfd_vma plt_header_size;
9659 bfd_vma got_header_size;
9660
9661 htab = elf32_arm_hash_table (info);
9662
9663 /* Pick the appropriate sections and sizes. */
9664 if (dynindx == -1)
9665 {
9666 splt = htab->root.iplt;
9667 sgot = htab->root.igotplt;
9668 srel = htab->root.irelplt;
9669
9670 /* There are no reserved entries in .igot.plt, and no special
9671 first entry in .iplt. */
9672 got_header_size = 0;
9673 plt_header_size = 0;
9674 }
9675 else
9676 {
9677 splt = htab->root.splt;
9678 sgot = htab->root.sgotplt;
9679 srel = htab->root.srelplt;
9680
9681 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9682 plt_header_size = htab->plt_header_size;
9683 }
9684 BFD_ASSERT (splt != NULL && srel != NULL);
9685
9686 /* Fill in the entry in the procedure linkage table. */
9687 if (htab->symbian_p)
9688 {
9689 BFD_ASSERT (dynindx >= 0);
9690 put_arm_insn (htab, output_bfd,
9691 elf32_arm_symbian_plt_entry[0],
9692 splt->contents + root_plt->offset);
9693 bfd_put_32 (output_bfd,
9694 elf32_arm_symbian_plt_entry[1],
9695 splt->contents + root_plt->offset + 4);
9696
9697 /* Fill in the entry in the .rel.plt section. */
9698 rel.r_offset = (splt->output_section->vma
9699 + splt->output_offset
9700 + root_plt->offset + 4);
9701 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9702
9703 /* Get the index in the procedure linkage table which
9704 corresponds to this symbol. This is the index of this symbol
9705 in all the symbols for which we are making plt entries. The
9706 first entry in the procedure linkage table is reserved. */
9707 plt_index = ((root_plt->offset - plt_header_size)
9708 / htab->plt_entry_size);
9709 }
9710 else
9711 {
9712 bfd_vma got_offset, got_address, plt_address;
9713 bfd_vma got_displacement, initial_got_entry;
9714 bfd_byte * ptr;
9715
9716 BFD_ASSERT (sgot != NULL);
9717
9718 /* Get the offset into the .(i)got.plt table of the entry that
9719 corresponds to this function. */
9720 got_offset = (arm_plt->got_offset & -2);
9721
9722 /* Get the index in the procedure linkage table which
9723 corresponds to this symbol. This is the index of this symbol
9724 in all the symbols for which we are making plt entries.
9725 After the reserved .got.plt entries, all symbols appear in
9726 the same order as in .plt. */
7801f98f 9727 if (htab->fdpic_p)
4b24dd1a
AM		 9728 /* Function descriptor takes 8 bytes. */
9729 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9730 else
4b24dd1a 9731 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9732
9733 /* Calculate the address of the GOT entry. */
9734 got_address = (sgot->output_section->vma
9735 + sgot->output_offset
9736 + got_offset);
9737
9738 /* ...and the address of the PLT entry. */
9739 plt_address = (splt->output_section->vma
9740 + splt->output_offset
9741 + root_plt->offset);
9742
9743 ptr = splt->contents + root_plt->offset;
0e1862bb 9744 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9745 {
9746 unsigned int i;
9747 bfd_vma val;
9748
9749 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9750 {
9751 val = elf32_arm_vxworks_shared_plt_entry[i];
9752 if (i == 2)
9753 val |= got_address - sgot->output_section->vma;
9754 if (i == 5)
9755 val |= plt_index * RELOC_SIZE (htab);
9756 if (i == 2 || i == 5)
9757 bfd_put_32 (output_bfd, val, ptr);
9758 else
9759 put_arm_insn (htab, output_bfd, val, ptr);
9760 }
9761 }
9762 else if (htab->vxworks_p)
9763 {
9764 unsigned int i;
9765 bfd_vma val;
9766
9767 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9768 {
9769 val = elf32_arm_vxworks_exec_plt_entry[i];
9770 if (i == 2)
9771 val |= got_address;
9772 if (i == 4)
9773 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9774 if (i == 5)
9775 val |= plt_index * RELOC_SIZE (htab);
9776 if (i == 2 || i == 5)
9777 bfd_put_32 (output_bfd, val, ptr);
9778 else
9779 put_arm_insn (htab, output_bfd, val, ptr);
9780 }
9781
9782 loc = (htab->srelplt2->contents
9783 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9784
9785 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9786 referencing the GOT for this PLT entry. */
9787 rel.r_offset = plt_address + 8;
9788 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9789 rel.r_addend = got_offset;
9790 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9791 loc += RELOC_SIZE (htab);
9792
9793 /* Create the R_ARM_ABS32 relocation referencing the
9794 beginning of the PLT for this GOT entry. */
9795 rel.r_offset = got_address;
9796 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9797 rel.r_addend = 0;
9798 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9799 }
b38cadfb
NC		 9800 else if (htab->nacl_p)
9801 {
9802 /* Calculate the displacement between the PLT slot and the
9803 common tail that's part of the special initial PLT slot. */
6034aab8 9804 int32_t tail_displacement
b38cadfb
NC		 9805 = ((splt->output_section->vma + splt->output_offset
9806 + ARM_NACL_PLT_TAIL_OFFSET)
9807 - (plt_address + htab->plt_entry_size + 4));
9808 BFD_ASSERT ((tail_displacement & 3) == 0);
9809 tail_displacement >>= 2;
9810
9811 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9812 || (-tail_displacement & 0xff000000) == 0);
9813
9814 /* Calculate the displacement between the PLT slot and the entry
9815 in the GOT. The offset accounts for the value produced by
9816 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9817 got_displacement = (got_address
99059e56 9818 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9819
9820 /* NaCl does not support interworking at all. */
9821 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9822
9823 put_arm_insn (htab, output_bfd,
9824 elf32_arm_nacl_plt_entry[0]
9825 | arm_movw_immediate (got_displacement),
9826 ptr + 0);
9827 put_arm_insn (htab, output_bfd,
9828 elf32_arm_nacl_plt_entry[1]
9829 | arm_movt_immediate (got_displacement),
9830 ptr + 4);
9831 put_arm_insn (htab, output_bfd,
9832 elf32_arm_nacl_plt_entry[2],
9833 ptr + 8);
9834 put_arm_insn (htab, output_bfd,
9835 elf32_arm_nacl_plt_entry[3]
9836 | (tail_displacement & 0x00ffffff),
9837 ptr + 12);
9838 }
7801f98f
CL		 9839 else if (htab->fdpic_p)
9840 {
59029f57
CL		 9841 const bfd_vma *plt_entry = using_thumb_only(htab)
9842 ? elf32_arm_fdpic_thumb_plt_entry
9843 : elf32_arm_fdpic_plt_entry;
9844
7801f98f
CL		 9845 /* Fill-up Thumb stub if needed. */
9846 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9847 {
9848 put_thumb_insn (htab, output_bfd,
9849 elf32_arm_plt_thumb_stub[0], ptr - 4);
9850 put_thumb_insn (htab, output_bfd,
9851 elf32_arm_plt_thumb_stub[1], ptr - 2);
9852 }
59029f57
CL		 9853 /* As we are using 32 bit instructions even for the Thumb
9854 version, we have to use 'put_arm_insn' instead of
9855 'put_thumb_insn'. */
9856 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9857 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9858 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9859 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9860 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9861
9862 if (!(info->flags & DF_BIND_NOW))
9863 {
9864 /* funcdesc_value_reloc_offset. */
9865 bfd_put_32 (output_bfd,
9866 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9867 ptr + 20);
59029f57
CL		 9868 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9869 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9870 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9871 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9872 }
9873 }
57460bcf
NC		 9874 else if (using_thumb_only (htab))
9875 {
eed94f8f 9876 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9877 if (!using_thumb2 (htab))
eed94f8f
NC		 9878 {
9879 /* FIXME: We ought to be able to generate thumb-1 PLT
9880 instructions... */
90b6238f 9881 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9882 output_bfd);
9883 return FALSE;
9884 }
57460bcf 9885
eed94f8f
NC		 9886 /* Calculate the displacement between the PLT slot and the entry in
9887 the GOT. The 12-byte offset accounts for the value produced by
9888 adding to pc in the 3rd instruction of the PLT stub. */
9889 got_displacement = got_address - (plt_address + 12);
9890
9891 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9892 instead of 'put_thumb_insn'. */
9893 put_arm_insn (htab, output_bfd,
9894 elf32_thumb2_plt_entry[0]
9895 | ((got_displacement & 0x000000ff) << 16)
9896 | ((got_displacement & 0x00000700) << 20)
9897 | ((got_displacement & 0x00000800) >> 1)
9898 | ((got_displacement & 0x0000f000) >> 12),
9899 ptr + 0);
9900 put_arm_insn (htab, output_bfd,
9901 elf32_thumb2_plt_entry[1]
9902 | ((got_displacement & 0x00ff0000) )
9903 | ((got_displacement & 0x07000000) << 4)
9904 | ((got_displacement & 0x08000000) >> 17)
9905 | ((got_displacement & 0xf0000000) >> 28),
9906 ptr + 4);
9907 put_arm_insn (htab, output_bfd,
9908 elf32_thumb2_plt_entry[2],
9909 ptr + 8);
9910 put_arm_insn (htab, output_bfd,
9911 elf32_thumb2_plt_entry[3],
9912 ptr + 12);
57460bcf 9913 }
34e77a92
RS		 9914 else
9915 {
9916 /* Calculate the displacement between the PLT slot and the
9917 entry in the GOT. The eight-byte offset accounts for the
9918 value produced by adding to pc in the first instruction
9919 of the PLT stub. */
9920 got_displacement = got_address - (plt_address + 8);
9921
34e77a92
RS		 9922 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9923 {
9924 put_thumb_insn (htab, output_bfd,
9925 elf32_arm_plt_thumb_stub[0], ptr - 4);
9926 put_thumb_insn (htab, output_bfd,
9927 elf32_arm_plt_thumb_stub[1], ptr - 2);
9928 }
9929
1db37fe6
YG		 9930 if (!elf32_arm_use_long_plt_entry)
9931 {
9932 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9933
9934 put_arm_insn (htab, output_bfd,
9935 elf32_arm_plt_entry_short[0]
9936 | ((got_displacement & 0x0ff00000) >> 20),
9937 ptr + 0);
9938 put_arm_insn (htab, output_bfd,
9939 elf32_arm_plt_entry_short[1]
9940 | ((got_displacement & 0x000ff000) >> 12),
9941 ptr+ 4);
9942 put_arm_insn (htab, output_bfd,
9943 elf32_arm_plt_entry_short[2]
9944 | (got_displacement & 0x00000fff),
9945 ptr + 8);
34e77a92 9946#ifdef FOUR_WORD_PLT
1db37fe6 9947 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9948#endif
1db37fe6
YG		 9949 }
9950 else
9951 {
9952 put_arm_insn (htab, output_bfd,
9953 elf32_arm_plt_entry_long[0]
9954 | ((got_displacement & 0xf0000000) >> 28),
9955 ptr + 0);
9956 put_arm_insn (htab, output_bfd,
9957 elf32_arm_plt_entry_long[1]
9958 | ((got_displacement & 0x0ff00000) >> 20),
9959 ptr + 4);
9960 put_arm_insn (htab, output_bfd,
9961 elf32_arm_plt_entry_long[2]
9962 | ((got_displacement & 0x000ff000) >> 12),
9963 ptr+ 8);
9964 put_arm_insn (htab, output_bfd,
9965 elf32_arm_plt_entry_long[3]
9966 | (got_displacement & 0x00000fff),
9967 ptr + 12);
9968 }
34e77a92
RS		 9969 }
9970
9971 /* Fill in the entry in the .rel(a).(i)plt section. */
9972 rel.r_offset = got_address;
9973 rel.r_addend = 0;
9974 if (dynindx == -1)
9975 {
9976 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9977 The dynamic linker or static executable then calls SYM_VALUE
9978 to determine the correct run-time value of the .igot.plt entry. */
9979 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9980 initial_got_entry = sym_value;
9981 }
9982 else
9983 {
7801f98f
CL		 9984 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9985 used by PLT entry. */
9986 if (htab->fdpic_p)
9987 {
9988 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9989 initial_got_entry = 0;
9990 }
9991 else
9992 {
9993 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9994 initial_got_entry = (splt->output_section->vma
9995 + splt->output_offset);
9996 }
34e77a92
RS		 9997 }
9998
9999 /* Fill in the entry in the global offset table. */
10000 bfd_put_32 (output_bfd, initial_got_entry,
10001 sgot->contents + got_offset);
7801f98f
CL		 10002
10003 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
10004 {
10005 /* Setup initial funcdesc value. */
10006 /* FIXME: we don't support lazy binding because there is a
10007 race condition between both words getting written and
10008 some other thread attempting to read them. The ARM
10009 architecture does not have an atomic 64 bit load/store
10010 instruction that could be used to prevent it; it is
10011 recommended that threaded FDPIC applications run with the
10012 LD_BIND_NOW environment variable set. */
10013 bfd_put_32(output_bfd, plt_address + 0x18,
10014 sgot->contents + got_offset);
10015 bfd_put_32(output_bfd, -1 /*TODO*/,
10016 sgot->contents + got_offset + 4);
10017 }
34e77a92
RS		 10018 }
10019
aba8c3de
WN		 10020 if (dynindx == -1)
10021 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
10022 else
10023 {
7801f98f
CL		 10024 if (htab->fdpic_p)
10025 {
10026 /* For FDPIC we put PLT relocationss into .rel.got when not
10027 lazy binding otherwise we put them in .rel.plt. For now,
10028 we don't support lazy binding so put it in .rel.got. */
10029 if (info->flags & DF_BIND_NOW)
10030 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
10031 else
10032 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
10033 }
10034 else
10035 {
10036 loc = srel->contents + plt_index * RELOC_SIZE (htab);
10037 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
10038 }
aba8c3de 10039 }
57460bcf
NC		 10040
10041 return TRUE;
34e77a92
RS		 10042}
10043
eb043451
PB		 10044/* Some relocations map to different relocations depending on the
10045 target. Return the real relocation. */
8029a119 10046
eb043451
PB		 10047static int
10048arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10049 int r_type)
10050{
10051 switch (r_type)
10052 {
10053 case R_ARM_TARGET1:
10054 if (globals->target1_is_rel)
10055 return R_ARM_REL32;
10056 else
10057 return R_ARM_ABS32;
10058
10059 case R_ARM_TARGET2:
10060 return globals->target2_reloc;
10061
10062 default:
10063 return r_type;
10064 }
10065}
eb043451 10066
ba93b8ac
DJ		 10067/* Return the base VMA address which should be subtracted from real addresses
10068 when resolving @dtpoff relocation.
10069 This is PT_TLS segment p_vaddr. */
10070
10071static bfd_vma
10072dtpoff_base (struct bfd_link_info *info)
10073{
10074 /* If tls_sec is NULL, we should have signalled an error already. */
10075 if (elf_hash_table (info)->tls_sec == NULL)
10076 return 0;
10077 return elf_hash_table (info)->tls_sec->vma;
10078}
10079
10080/* Return the relocation value for @tpoff relocation
10081 if STT_TLS virtual address is ADDRESS. */
10082
10083static bfd_vma
10084tpoff (struct bfd_link_info *info, bfd_vma address)
10085{
10086 struct elf_link_hash_table *htab = elf_hash_table (info);
10087 bfd_vma base;
10088
10089 /* If tls_sec is NULL, we should have signalled an error already. */
10090 if (htab->tls_sec == NULL)
10091 return 0;
10092 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10093 return address - htab->tls_sec->vma + base;
10094}
10095
00a97672
RS		 10096/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10097 VALUE is the relocation value. */
10098
10099static bfd_reloc_status_type
10100elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10101{
10102 if (value > 0xfff)
10103 return bfd_reloc_overflow;
10104
10105 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10106 bfd_put_32 (abfd, value, data);
10107 return bfd_reloc_ok;
10108}
10109
0855e32b
NS		 10110/* Handle TLS relaxations. Relaxing is possible for symbols that use
10111 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10112 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10113
10114 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10115 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10116 case of error.
10117
10118 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10119 the pre-relaxed code. It would be nice if the relocs were updated
10120 to match the optimization. */
0855e32b 10121
b38cadfb 10122static bfd_reloc_status_type
0855e32b 10123elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10124 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10125 Elf_Internal_Rela *rel, unsigned long is_local)
10126{
10127 unsigned long insn;
b38cadfb 10128
0855e32b
NS		 10129 switch (ELF32_R_TYPE (rel->r_info))
10130 {
10131 default:
10132 return bfd_reloc_notsupported;
b38cadfb 10133
0855e32b
NS		 10134 case R_ARM_TLS_GOTDESC:
10135 if (is_local)
10136 insn = 0;
10137 else
10138 {
10139 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10140 if (insn & 1)
10141 insn -= 5; /* THUMB */
10142 else
10143 insn -= 8; /* ARM */
10144 }
10145 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10146 return bfd_reloc_continue;
10147
10148 case R_ARM_THM_TLS_DESCSEQ:
10149 /* Thumb insn. */
10150 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10151 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10152 {
10153 if (is_local)
10154 /* nop */
10155 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10156 }
10157 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10158 {
10159 if (is_local)
10160 /* nop */
10161 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10162 else
10163 /* ldr rx,[ry] */
10164 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10165 }
10166 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10167 {
10168 if (is_local)
10169 /* nop */
10170 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10171 else
10172 /* mov r0, rx */
10173 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10174 contents + rel->r_offset);
10175 }
10176 else
10177 {
10178 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10179 /* It's a 32 bit instruction, fetch the rest of it for
10180 error generation. */
10181 insn = (insn << 16)
10182 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10183 _bfd_error_handler
695344c0 10184 /* xgettext:c-format */
2dcf00ce 10185 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10186 "unexpected %s instruction '%#lx' in TLS trampoline"),
10187 input_bfd, input_sec, (uint64_t) rel->r_offset,
10188 "Thumb", insn);
0855e32b
NS		 10189 return bfd_reloc_notsupported;
10190 }
10191 break;
b38cadfb 10192
0855e32b
NS		 10193 case R_ARM_TLS_DESCSEQ:
10194 /* arm insn. */
10195 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10196 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10197 {
10198 if (is_local)
10199 /* mov rx, ry */
10200 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10201 contents + rel->r_offset);
10202 }
10203 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10204 {
10205 if (is_local)
10206 /* nop */
10207 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10208 else
10209 /* ldr rx,[ry] */
10210 bfd_put_32 (input_bfd, insn & 0xfffff000,
10211 contents + rel->r_offset);
10212 }
10213 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10214 {
10215 if (is_local)
10216 /* nop */
10217 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10218 else
10219 /* mov r0, rx */
10220 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10221 contents + rel->r_offset);
10222 }
10223 else
10224 {
4eca0228 10225 _bfd_error_handler
695344c0 10226 /* xgettext:c-format */
2dcf00ce 10227 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10228 "unexpected %s instruction '%#lx' in TLS trampoline"),
10229 input_bfd, input_sec, (uint64_t) rel->r_offset,
10230 "ARM", insn);
0855e32b
NS		 10231 return bfd_reloc_notsupported;
10232 }
10233 break;
10234
10235 case R_ARM_TLS_CALL:
10236 /* GD->IE relaxation, turn the instruction into 'nop' or
10237 'ldr r0, [pc,r0]' */
10238 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10239 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10240 break;
b38cadfb 10241
0855e32b 10242 case R_ARM_THM_TLS_CALL:
6a631e86 10243 /* GD->IE relaxation. */
0855e32b
NS		 10244 if (!is_local)
10245 /* add r0,pc; ldr r0, [r0] */
10246 insn = 0x44786800;
60a019a0 10247 else if (using_thumb2 (globals))
0855e32b
NS		 10248 /* nop.w */
10249 insn = 0xf3af8000;
10250 else
10251 /* nop; nop */
10252 insn = 0xbf00bf00;
b38cadfb 10253
0855e32b
NS		 10254 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10255 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10256 break;
10257 }
10258 return bfd_reloc_ok;
10259}
10260
4962c51a
MS		 10261/* For a given value of n, calculate the value of G_n as required to
10262 deal with group relocations. We return it in the form of an
10263 encoded constant-and-rotation, together with the final residual. If n is
10264 specified as less than zero, then final_residual is filled with the
10265 input value and no further action is performed. */
10266
10267static bfd_vma
10268calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10269{
10270 int current_n;
10271 bfd_vma g_n;
10272 bfd_vma encoded_g_n = 0;
10273 bfd_vma residual = value; /* Also known as Y_n. */
10274
10275 for (current_n = 0; current_n <= n; current_n++)
10276 {
10277 int shift;
10278
10279 /* Calculate which part of the value to mask. */
10280 if (residual == 0)
99059e56 10281 shift = 0;
4962c51a 10282 else
99059e56
RM		 10283 {
10284 int msb;
10285
10286 /* Determine the most significant bit in the residual and
10287 align the resulting value to a 2-bit boundary. */
10288 for (msb = 30; msb >= 0; msb -= 2)
10289 if (residual & (3 << msb))
10290 break;
10291
10292 /* The desired shift is now (msb - 6), or zero, whichever
10293 is the greater. */
10294 shift = msb - 6;
10295 if (shift < 0)
10296 shift = 0;
10297 }
4962c51a
MS		 10298
10299 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10300 g_n = residual & (0xff << shift);
10301 encoded_g_n = (g_n >> shift)
99059e56 10302 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10303
10304 /* Calculate the residual for the next time around. */
10305 residual &= ~g_n;
10306 }
10307
10308 *final_residual = residual;
10309
10310 return encoded_g_n;
10311}
10312
10313/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10314 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10315
4962c51a 10316static int
906e58ca 10317identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10318{
10319 int opcode = insn & 0x1e00000;
10320
10321 if (opcode == 1 << 23) /* ADD */
10322 return 1;
10323
10324 if (opcode == 1 << 22) /* SUB */
10325 return -1;
10326
10327 return 0;
10328}
10329
252b5132 10330/* Perform a relocation as part of a final link. */
9b485d32 10331
252b5132 10332static bfd_reloc_status_type
07d6d2b8
AM		 10333elf32_arm_final_link_relocate (reloc_howto_type * howto,
10334 bfd * input_bfd,
10335 bfd * output_bfd,
10336 asection * input_section,
10337 bfd_byte * contents,
10338 Elf_Internal_Rela * rel,
10339 bfd_vma value,
10340 struct bfd_link_info * info,
10341 asection * sym_sec,
10342 const char * sym_name,
10343 unsigned char st_type,
10344 enum arm_st_branch_type branch_type,
0945cdfd 10345 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10346 bfd_boolean * unresolved_reloc_p,
10347 char ** error_message)
10348{
10349 unsigned long r_type = howto->type;
10350 unsigned long r_symndx;
10351 bfd_byte * hit_data = contents + rel->r_offset;
10352 bfd_vma * local_got_offsets;
10353 bfd_vma * local_tlsdesc_gotents;
10354 asection * sgot;
10355 asection * splt;
10356 asection * sreloc = NULL;
10357 asection * srelgot;
10358 bfd_vma addend;
10359 bfd_signed_vma signed_addend;
10360 unsigned char dynreloc_st_type;
10361 bfd_vma dynreloc_value;
ba96a88f 10362 struct elf32_arm_link_hash_table * globals;
34e77a92 10363 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10364 union gotplt_union *root_plt;
10365 struct arm_plt_info *arm_plt;
10366 bfd_vma plt_offset;
10367 bfd_vma gotplt_offset;
10368 bfd_boolean has_iplt_entry;
10369 bfd_boolean resolved_to_zero;
f21f3fe0 10370
9c504268 10371 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10372 if (globals == NULL)
10373 return bfd_reloc_notsupported;
9c504268 10374
0ffa91dd 10375 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10376 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10377
10378 /* Some relocation types map to different relocations depending on the
9c504268 10379 target. We pick the right one here. */
eb043451 10380 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10381
10382 /* It is possible to have linker relaxations on some TLS access
10383 models. Update our information here. */
10384 r_type = elf32_arm_tls_transition (info, r_type, h);
10385
eb043451
PB		 10386 if (r_type != howto->type)
10387 howto = elf32_arm_howto_from_type (r_type);
9c504268 10388
34e77a92 10389 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10390 sgot = globals->root.sgot;
252b5132 10391 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10392 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10393
34e77a92
RS		 10394 if (globals->root.dynamic_sections_created)
10395 srelgot = globals->root.srelgot;
10396 else
10397 srelgot = NULL;
10398
252b5132
RH		 10399 r_symndx = ELF32_R_SYM (rel->r_info);
10400
4e7fd91e 10401 if (globals->use_rel)
ba96a88f 10402 {
4e7fd91e
PB		 10403 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10404
10405 if (addend & ((howto->src_mask + 1) >> 1))
10406 {
10407 signed_addend = -1;
10408 signed_addend &= ~ howto->src_mask;
10409 signed_addend |= addend;
10410 }
10411 else
10412 signed_addend = addend;
ba96a88f
NC		 10413 }
10414 else
4e7fd91e 10415 addend = signed_addend = rel->r_addend;
f21f3fe0 10416
39f21624
NC		 10417 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10418 are resolving a function call relocation. */
10419 if (using_thumb_only (globals)
10420 && (r_type == R_ARM_THM_CALL
10421 || r_type == R_ARM_THM_JUMP24)
10422 && branch_type == ST_BRANCH_TO_ARM)
10423 branch_type = ST_BRANCH_TO_THUMB;
10424
34e77a92
RS		 10425 /* Record the symbol information that should be used in dynamic
10426 relocations. */
10427 dynreloc_st_type = st_type;
10428 dynreloc_value = value;
10429 if (branch_type == ST_BRANCH_TO_THUMB)
10430 dynreloc_value |= 1;
10431
10432 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10433 VALUE appropriately for relocations that we resolve at link time. */
10434 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10435 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10436 &arm_plt)
34e77a92
RS		 10437 && root_plt->offset != (bfd_vma) -1)
10438 {
10439 plt_offset = root_plt->offset;
10440 gotplt_offset = arm_plt->got_offset;
10441
10442 if (h == NULL || eh->is_iplt)
10443 {
10444 has_iplt_entry = TRUE;
10445 splt = globals->root.iplt;
10446
10447 /* Populate .iplt entries here, because not all of them will
10448 be seen by finish_dynamic_symbol. The lower bit is set if
10449 we have already populated the entry. */
10450 if (plt_offset & 1)
10451 plt_offset--;
10452 else
10453 {
57460bcf
NC		 10454 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10455 -1, dynreloc_value))
10456 root_plt->offset |= 1;
10457 else
10458 return bfd_reloc_notsupported;
34e77a92
RS		 10459 }
10460
10461 /* Static relocations always resolve to the .iplt entry. */
10462 st_type = STT_FUNC;
10463 value = (splt->output_section->vma
10464 + splt->output_offset
10465 + plt_offset);
10466 branch_type = ST_BRANCH_TO_ARM;
10467
10468 /* If there are non-call relocations that resolve to the .iplt
10469 entry, then all dynamic ones must too. */
10470 if (arm_plt->noncall_refcount != 0)
10471 {
10472 dynreloc_st_type = st_type;
10473 dynreloc_value = value;
10474 }
10475 }
10476 else
10477 /* We populate the .plt entry in finish_dynamic_symbol. */
10478 splt = globals->root.splt;
10479 }
10480 else
10481 {
10482 splt = NULL;
10483 plt_offset = (bfd_vma) -1;
10484 gotplt_offset = (bfd_vma) -1;
10485 }
10486
95b03e4a
L		 10487 resolved_to_zero = (h != NULL
10488 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10489
252b5132
RH		 10490 switch (r_type)
10491 {
10492 case R_ARM_NONE:
28a094c2
DJ		 10493 /* We don't need to find a value for this symbol. It's just a
10494 marker. */
10495 *unresolved_reloc_p = FALSE;
252b5132
RH		 10496 return bfd_reloc_ok;
10497
00a97672
RS		 10498 case R_ARM_ABS12:
10499 if (!globals->vxworks_p)
10500 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10501 /* Fall through. */
00a97672 10502
252b5132
RH		 10503 case R_ARM_PC24:
10504 case R_ARM_ABS32:
bb224fc3 10505 case R_ARM_ABS32_NOI:
252b5132 10506 case R_ARM_REL32:
bb224fc3 10507 case R_ARM_REL32_NOI:
5b5bb741
PB		 10508 case R_ARM_CALL:
10509 case R_ARM_JUMP24:
dfc5f959 10510 case R_ARM_XPC25:
eb043451 10511 case R_ARM_PREL31:
7359ea65 10512 case R_ARM_PLT32:
7359ea65
DJ		 10513 /* Handle relocations which should use the PLT entry. ABS32/REL32
10514 will use the symbol's value, which may point to a PLT entry, but we
10515 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10516 branches in this object should go to it, except if the PLT is too
10517 far away, in which case a long branch stub should be inserted. */
bb224fc3 10518 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10519 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10520 && r_type != R_ARM_CALL
10521 && r_type != R_ARM_JUMP24
10522 && r_type != R_ARM_PLT32)
34e77a92 10523 && plt_offset != (bfd_vma) -1)
7359ea65 10524 {
34e77a92
RS		 10525 /* If we've created a .plt section, and assigned a PLT entry
10526 to this function, it must either be a STT_GNU_IFUNC reference
10527 or not be known to bind locally. In other cases, we should
10528 have cleared the PLT entry by now. */
10529 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10530
10531 value = (splt->output_section->vma
10532 + splt->output_offset
34e77a92 10533 + plt_offset);
0945cdfd 10534 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10535 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10536 contents, rel->r_offset, value,
00a97672 10537 rel->r_addend);
7359ea65
DJ		 10538 }
10539
67687978
PB		 10540 /* When generating a shared object or relocatable executable, these
10541 relocations are copied into the output file to be resolved at
10542 run time. */
0e1862bb 10543 if ((bfd_link_pic (info)
e8b09b87
CL		 10544 || globals->root.is_relocatable_executable
10545 || globals->fdpic_p)
7359ea65 10546 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10547 && !(globals->vxworks_p
3348747a
NS		 10548 && strcmp (input_section->output_section->name,
10549 ".tls_vars") == 0)
bb224fc3 10550 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10551 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10552 && !(input_bfd == globals->stub_bfd
10553 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10554 && (h == NULL
95b03e4a
L		 10555 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10556 && !resolved_to_zero)
7359ea65
DJ		 10557 || h->root.type != bfd_link_hash_undefweak)
10558 && r_type != R_ARM_PC24
5b5bb741
PB		 10559 && r_type != R_ARM_CALL
10560 && r_type != R_ARM_JUMP24
ee06dc07 10561 && r_type != R_ARM_PREL31
7359ea65 10562 && r_type != R_ARM_PLT32)
252b5132 10563 {
947216bf 10564 Elf_Internal_Rela outrel;
b34976b6 10565 bfd_boolean skip, relocate;
e8b09b87 10566 int isrofixup = 0;
f21f3fe0 10567
52db4ec2
JW		 10568 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10569 && !h->def_regular)
10570 {
10571 char *v = _("shared object");
10572
0e1862bb 10573 if (bfd_link_executable (info))
52db4ec2
JW		 10574 v = _("PIE executable");
10575
4eca0228 10576 _bfd_error_handler
871b3ab2 10577 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10578 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10579 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10580 return bfd_reloc_notsupported;
10581 }
10582
0945cdfd
DJ		 10583 *unresolved_reloc_p = FALSE;
10584
34e77a92 10585 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10586 {
83bac4b0
NC		 10587 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10588 ! globals->use_rel);
f21f3fe0 10589
83bac4b0 10590 if (sreloc == NULL)
252b5132 10591 return bfd_reloc_notsupported;
252b5132 10592 }
f21f3fe0 10593
b34976b6
AM		 10594 skip = FALSE;
10595 relocate = FALSE;
f21f3fe0 10596
00a97672 10597 outrel.r_addend = addend;
c629eae0
JJ		 10598 outrel.r_offset =
10599 _bfd_elf_section_offset (output_bfd, info, input_section,
10600 rel->r_offset);
10601 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10602 skip = TRUE;
0bb2d96a 10603 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10604 skip = TRUE, relocate = TRUE;
252b5132
RH		 10605 outrel.r_offset += (input_section->output_section->vma
10606 + input_section->output_offset);
f21f3fe0 10607
252b5132 10608 if (skip)
0bb2d96a 10609 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10610 else if (h != NULL
10611 && h->dynindx != -1
0e1862bb 10612 && (!bfd_link_pic (info)
1dcb9720
JW		 10613 || !(bfd_link_pie (info)
10614 || SYMBOLIC_BIND (info, h))
f5385ebf 10615 || !h->def_regular))
5e681ec4 10616 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10617 else
10618 {
a16385dc
MM		 10619 int symbol;
10620
5e681ec4 10621 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10622 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10623 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10624 if (globals->symbian_p)
6366ff1e 10625 {
74541ad4
AM		 10626 asection *osec;
10627
6366ff1e
MM		 10628 /* On Symbian OS, the data segment and text segement
10629 can be relocated independently. Therefore, we
10630 must indicate the segment to which this
10631 relocation is relative. The BPABI allows us to
10632 use any symbol in the right segment; we just use
10633 the section symbol as it is convenient. (We
10634 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10635 will not appear in the dynamic symbol table.)
10636
10637 Note that the dynamic linker ignores the section
10638 symbol value, so we don't subtract osec->vma
10639 from the emitted reloc addend. */
10dbd1f3 10640 if (sym_sec)
74541ad4 10641 osec = sym_sec->output_section;
10dbd1f3 10642 else
74541ad4
AM		 10643 osec = input_section->output_section;
10644 symbol = elf_section_data (osec)->dynindx;
10645 if (symbol == 0)
10646 {
10647 struct elf_link_hash_table *htab = elf_hash_table (info);
10648
10649 if ((osec->flags & SEC_READONLY) == 0
10650 && htab->data_index_section != NULL)
10651 osec = htab->data_index_section;
10652 else
10653 osec = htab->text_index_section;
10654 symbol = elf_section_data (osec)->dynindx;
10655 }
6366ff1e
MM		 10656 BFD_ASSERT (symbol != 0);
10657 }
a16385dc
MM		 10658 else
10659 /* On SVR4-ish systems, the dynamic loader cannot
10660 relocate the text and data segments independently,
10661 so the symbol does not matter. */
10662 symbol = 0;
34e77a92
RS		 10663 if (dynreloc_st_type == STT_GNU_IFUNC)
10664 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10665 to the .iplt entry. Instead, every non-call reference
10666 must use an R_ARM_IRELATIVE relocation to obtain the
10667 correct run-time address. */
10668 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10669 else if (globals->fdpic_p && !bfd_link_pic(info))
10670 isrofixup = 1;
34e77a92
RS		 10671 else
10672 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10673 if (globals->use_rel)
10674 relocate = TRUE;
10675 else
34e77a92 10676 outrel.r_addend += dynreloc_value;
252b5132 10677 }
f21f3fe0 10678
e8b09b87
CL		 10679 if (isrofixup)
10680 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10681 else
10682 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10683
f21f3fe0 10684 /* If this reloc is against an external symbol, we do not want to
252b5132 10685 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10686 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10687 if (! relocate)
10688 return bfd_reloc_ok;
9a5aca8c 10689
f21f3fe0 10690 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10691 contents, rel->r_offset,
10692 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10693 }
10694 else switch (r_type)
10695 {
00a97672
RS		 10696 case R_ARM_ABS12:
10697 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10698
dfc5f959 10699 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10700 case R_ARM_CALL:
10701 case R_ARM_JUMP24:
8029a119 10702 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10703 case R_ARM_PLT32:
906e58ca 10704 {
906e58ca
NC		 10705 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10706
dfc5f959 10707 if (r_type == R_ARM_XPC25)
252b5132 10708 {
dfc5f959
NC		 10709 /* Check for Arm calling Arm function. */
10710 /* FIXME: Should we translate the instruction into a BL
10711 instruction instead ? */
35fc36a8 10712 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10713 _bfd_error_handler
90b6238f
AM		 10714 (_("\%pB: warning: %s BLX instruction targets"
10715 " %s function '%s'"),
10716 input_bfd, "ARM",
10717 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10718 }
155d87d7 10719 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10720 {
10721 /* Check for Arm calling Thumb function. */
35fc36a8 10722 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10723 {
f2a9dd69
DJ		 10724 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10725 output_bfd, input_section,
10726 hit_data, sym_sec, rel->r_offset,
10727 signed_addend, value,
10728 error_message))
10729 return bfd_reloc_ok;
10730 else
10731 return bfd_reloc_dangerous;
dfc5f959 10732 }
252b5132 10733 }
ba96a88f 10734
906e58ca 10735 /* Check if a stub has to be inserted because the
8029a119 10736 destination is too far or we are changing mode. */
155d87d7
CL		 10737 if ( r_type == R_ARM_CALL
10738 || r_type == R_ARM_JUMP24
10739 || r_type == R_ARM_PLT32)
906e58ca 10740 {
fe33d2fa
CL		 10741 enum elf32_arm_stub_type stub_type = arm_stub_none;
10742 struct elf32_arm_link_hash_entry *hash;
10743
10744 hash = (struct elf32_arm_link_hash_entry *) h;
10745 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10746 st_type, &branch_type,
10747 hash, value, sym_sec,
fe33d2fa 10748 input_bfd, sym_name);
5fa9e92f 10749
fe33d2fa 10750 if (stub_type != arm_stub_none)
906e58ca
NC		 10751 {
10752 /* The target is out of reach, so redirect the
10753 branch to the local stub for this function. */
906e58ca
NC		 10754 stub_entry = elf32_arm_get_stub_entry (input_section,
10755 sym_sec, h,
fe33d2fa
CL		 10756 rel, globals,
10757 stub_type);
9cd3e4e5
NC		 10758 {
10759 if (stub_entry != NULL)
10760 value = (stub_entry->stub_offset
10761 + stub_entry->stub_sec->output_offset
10762 + stub_entry->stub_sec->output_section->vma);
10763
10764 if (plt_offset != (bfd_vma) -1)
10765 *unresolved_reloc_p = FALSE;
10766 }
906e58ca 10767 }
fe33d2fa
CL		 10768 else
10769 {
10770 /* If the call goes through a PLT entry, make sure to
10771 check distance to the right destination address. */
34e77a92 10772 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10773 {
10774 value = (splt->output_section->vma
10775 + splt->output_offset
34e77a92 10776 + plt_offset);
fe33d2fa
CL		 10777 *unresolved_reloc_p = FALSE;
10778 /* The PLT entry is in ARM mode, regardless of the
10779 target function. */
35fc36a8 10780 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10781 }
10782 }
906e58ca
NC		 10783 }
10784
dea514f5
PB		 10785 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10786 where:
10787 S is the address of the symbol in the relocation.
10788 P is address of the instruction being relocated.
10789 A is the addend (extracted from the instruction) in bytes.
10790
10791 S is held in 'value'.
10792 P is the base address of the section containing the
10793 instruction plus the offset of the reloc into that
10794 section, ie:
10795 (input_section->output_section->vma +
10796 input_section->output_offset +
10797 rel->r_offset).
10798 A is the addend, converted into bytes, ie:
10799 (signed_addend * 4)
10800
10801 Note: None of these operations have knowledge of the pipeline
10802 size of the processor, thus it is up to the assembler to
10803 encode this information into the addend. */
10804 value -= (input_section->output_section->vma
10805 + input_section->output_offset);
10806 value -= rel->r_offset;
4e7fd91e
PB		 10807 if (globals->use_rel)
10808 value += (signed_addend << howto->size);
10809 else
10810 /* RELA addends do not have to be adjusted by howto->size. */
10811 value += signed_addend;
23080146 10812
dcb5e6e6
NC		 10813 signed_addend = value;
10814 signed_addend >>= howto->rightshift;
9a5aca8c 10815
5ab79981 10816 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10817 the next instruction unless a PLT entry will be created.
77b4f08f 10818 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10819 The jump to the next instruction is optimized as a NOP depending
10820 on the architecture. */
ffcb4889 10821 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10822 && plt_offset == (bfd_vma) -1)
77b4f08f 10823 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10824 {
cd1dac3d
DG		 10825 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10826
10827 if (arch_has_arm_nop (globals))
10828 value |= 0x0320f000;
10829 else
10830 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10831 }
10832 else
59f2c4e7 10833 {
9b485d32 10834 /* Perform a signed range check. */
dcb5e6e6 10835 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10836 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10837 return bfd_reloc_overflow;
9a5aca8c 10838
5ab79981 10839 addend = (value & 2);
39b41c9c 10840
5ab79981
PB		 10841 value = (signed_addend & howto->dst_mask)
10842 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10843
5ab79981
PB		 10844 if (r_type == R_ARM_CALL)
10845 {
155d87d7 10846 /* Set the H bit in the BLX instruction. */
35fc36a8 10847 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10848 {
10849 if (addend)
10850 value |= (1 << 24);
10851 else
10852 value &= ~(bfd_vma)(1 << 24);
10853 }
10854
5ab79981 10855 /* Select the correct instruction (BL or BLX). */
906e58ca 10856 /* Only if we are not handling a BL to a stub. In this
8029a119 10857 case, mode switching is performed by the stub. */
35fc36a8 10858 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10859 value |= (1 << 28);
63e1a0fc 10860 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10861 {
10862 value &= ~(bfd_vma)(1 << 28);
10863 value |= (1 << 24);
10864 }
39b41c9c
PB		 10865 }
10866 }
906e58ca 10867 }
252b5132 10868 break;
f21f3fe0 10869
252b5132
RH		 10870 case R_ARM_ABS32:
10871 value += addend;
35fc36a8 10872 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10873 value |= 1;
10874 break;
f21f3fe0 10875
bb224fc3
MS		 10876 case R_ARM_ABS32_NOI:
10877 value += addend;
10878 break;
10879
252b5132 10880 case R_ARM_REL32:
a8bc6c78 10881 value += addend;
35fc36a8 10882 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10883 value |= 1;
252b5132 10884 value -= (input_section->output_section->vma
62efb346 10885 + input_section->output_offset + rel->r_offset);
252b5132 10886 break;
eb043451 10887
bb224fc3
MS		 10888 case R_ARM_REL32_NOI:
10889 value += addend;
10890 value -= (input_section->output_section->vma
10891 + input_section->output_offset + rel->r_offset);
10892 break;
10893
eb043451
PB		 10894 case R_ARM_PREL31:
10895 value -= (input_section->output_section->vma
10896 + input_section->output_offset + rel->r_offset);
10897 value += signed_addend;
10898 if (! h || h->root.type != bfd_link_hash_undefweak)
10899 {
8029a119 10900 /* Check for overflow. */
eb043451
PB		 10901 if ((value ^ (value >> 1)) & (1 << 30))
10902 return bfd_reloc_overflow;
10903 }
10904 value &= 0x7fffffff;
10905 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10906 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10907 value |= 1;
10908 break;
252b5132 10909 }
f21f3fe0 10910
252b5132
RH		 10911 bfd_put_32 (input_bfd, value, hit_data);
10912 return bfd_reloc_ok;
10913
10914 case R_ARM_ABS8:
fd0fd00c
MJ		 10915 /* PR 16202: Refectch the addend using the correct size. */
10916 if (globals->use_rel)
10917 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10918 value += addend;
4e67d4ca
DG		 10919
10920 /* There is no way to tell whether the user intended to use a signed or
10921 unsigned addend. When checking for overflow we accept either,
10922 as specified by the AAELF. */
10923 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10924 return bfd_reloc_overflow;
10925
10926 bfd_put_8 (input_bfd, value, hit_data);
10927 return bfd_reloc_ok;
10928
10929 case R_ARM_ABS16:
fd0fd00c
MJ		 10930 /* PR 16202: Refectch the addend using the correct size. */
10931 if (globals->use_rel)
10932 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10933 value += addend;
10934
4e67d4ca
DG		 10935 /* See comment for R_ARM_ABS8. */
10936 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10937 return bfd_reloc_overflow;
10938
10939 bfd_put_16 (input_bfd, value, hit_data);
10940 return bfd_reloc_ok;
10941
252b5132 10942 case R_ARM_THM_ABS5:
9b485d32 10943 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10944 if (globals->use_rel)
10945 {
10946 /* Need to refetch addend. */
10947 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10948 /* ??? Need to determine shift amount from operand size. */
10949 addend >>= howto->rightshift;
10950 }
252b5132
RH		 10951 value += addend;
10952
10953 /* ??? Isn't value unsigned? */
10954 if ((long) value > 0x1f || (long) value < -0x10)
10955 return bfd_reloc_overflow;
10956
10957 /* ??? Value needs to be properly shifted into place first. */
10958 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10959 bfd_put_16 (input_bfd, value, hit_data);
10960 return bfd_reloc_ok;
10961
2cab6cc3
MS		 10962 case R_ARM_THM_ALU_PREL_11_0:
10963 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10964 {
10965 bfd_vma insn;
10966 bfd_signed_vma relocation;
10967
10968 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10969 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10970
99059e56
RM		 10971 if (globals->use_rel)
10972 {
10973 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10974 | ((insn & (1 << 26)) >> 15);
10975 if (insn & 0xf00000)
10976 signed_addend = -signed_addend;
10977 }
2cab6cc3
MS		 10978
10979 relocation = value + signed_addend;
79f08007 10980 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10981 + input_section->output_offset
10982 + rel->r_offset);
2cab6cc3 10983
8c65b54f
CS		 10984 /* PR 21523: Use an absolute value. The user of this reloc will
10985 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10986 value = llabs (relocation);
2cab6cc3 10987
99059e56
RM		 10988 if (value >= 0x1000)
10989 return bfd_reloc_overflow;
2cab6cc3 10990
e645cf40
AG		 10991 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10992 if (branch_type == ST_BRANCH_TO_THUMB)
10993 value |= 1;
10994
2cab6cc3 10995 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10996 | ((value & 0x700) << 4)
10997 | ((value & 0x800) << 15);
10998 if (relocation < 0)
10999 insn |= 0xa00000;
2cab6cc3
MS		 11000
11001 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11002 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11003
99059e56 11004 return bfd_reloc_ok;
2cab6cc3
MS		 11005 }
11006
e1ec24c6
NC		 11007 case R_ARM_THM_PC8:
11008 /* PR 10073: This reloc is not generated by the GNU toolchain,
11009 but it is supported for compatibility with third party libraries
11010 generated by other compilers, specifically the ARM/IAR. */
11011 {
11012 bfd_vma insn;
11013 bfd_signed_vma relocation;
11014
11015 insn = bfd_get_16 (input_bfd, hit_data);
11016
99059e56 11017 if (globals->use_rel)
79f08007 11018 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 11019
11020 relocation = value + addend;
79f08007 11021 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11022 + input_section->output_offset
11023 + rel->r_offset);
e1ec24c6 11024
b6518b38 11025 value = relocation;
e1ec24c6
NC		 11026
11027 /* We do not check for overflow of this reloc. Although strictly
11028 speaking this is incorrect, it appears to be necessary in order
11029 to work with IAR generated relocs. Since GCC and GAS do not
11030 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11031 a problem for them. */
11032 value &= 0x3fc;
11033
11034 insn = (insn & 0xff00) | (value >> 2);
11035
11036 bfd_put_16 (input_bfd, insn, hit_data);
11037
99059e56 11038 return bfd_reloc_ok;
e1ec24c6
NC		 11039 }
11040
2cab6cc3
MS		 11041 case R_ARM_THM_PC12:
11042 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11043 {
11044 bfd_vma insn;
11045 bfd_signed_vma relocation;
11046
11047 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11048 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11049
99059e56
RM		 11050 if (globals->use_rel)
11051 {
11052 signed_addend = insn & 0xfff;
11053 if (!(insn & (1 << 23)))
11054 signed_addend = -signed_addend;
11055 }
2cab6cc3
MS		 11056
11057 relocation = value + signed_addend;
79f08007 11058 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11059 + input_section->output_offset
11060 + rel->r_offset);
2cab6cc3 11061
b6518b38 11062 value = relocation;
2cab6cc3 11063
99059e56
RM		 11064 if (value >= 0x1000)
11065 return bfd_reloc_overflow;
2cab6cc3
MS		 11066
11067 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11068 if (relocation >= 0)
11069 insn |= (1 << 23);
2cab6cc3
MS		 11070
11071 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11072 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11073
99059e56 11074 return bfd_reloc_ok;
2cab6cc3
MS		 11075 }
11076
dfc5f959 11077 case R_ARM_THM_XPC22:
c19d1205 11078 case R_ARM_THM_CALL:
bd97cb95 11079 case R_ARM_THM_JUMP24:
dfc5f959 11080 /* Thumb BL (branch long instruction). */
252b5132 11081 {
b34976b6 11082 bfd_vma relocation;
99059e56 11083 bfd_vma reloc_sign;
b34976b6
AM		 11084 bfd_boolean overflow = FALSE;
11085 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11086 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11087 bfd_signed_vma reloc_signed_max;
11088 bfd_signed_vma reloc_signed_min;
b34976b6 11089 bfd_vma check;
252b5132 11090 bfd_signed_vma signed_check;
e95de063 11091 int bitsize;
cd1dac3d 11092 const int thumb2 = using_thumb2 (globals);
5e866f5a 11093 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11094
5ab79981 11095 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11096 the next instruction unless a PLT entry will be created.
11097 The jump to the next instruction is optimized as a NOP.W for
11098 Thumb-2 enabled architectures. */
19540007 11099 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11100 && plt_offset == (bfd_vma) -1)
5ab79981 11101 {
60a019a0 11102 if (thumb2)
cd1dac3d
DG		 11103 {
11104 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11105 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11106 }
11107 else
11108 {
11109 bfd_put_16 (input_bfd, 0xe000, hit_data);
11110 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11111 }
5ab79981
PB		 11112 return bfd_reloc_ok;
11113 }
11114
e95de063 11115 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11116 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11117 if (globals->use_rel)
11118 {
99059e56
RM		 11119 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11120 bfd_vma upper = upper_insn & 0x3ff;
11121 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11122 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11123 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11124 bfd_vma i1 = j1 ^ s ? 0 : 1;
11125 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11126
99059e56
RM		 11127 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11128 /* Sign extend. */
11129 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11130
4e7fd91e
PB		 11131 signed_addend = addend;
11132 }
cb1afa5c 11133
dfc5f959
NC		 11134 if (r_type == R_ARM_THM_XPC22)
11135 {
11136 /* Check for Thumb to Thumb call. */
11137 /* FIXME: Should we translate the instruction into a BL
11138 instruction instead ? */
35fc36a8 11139 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11140 _bfd_error_handler
90b6238f
AM		 11141 (_("%pB: warning: %s BLX instruction targets"
11142 " %s function '%s'"),
11143 input_bfd, "Thumb",
11144 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11145 }
11146 else
252b5132 11147 {
dfc5f959
NC		 11148 /* If it is not a call to Thumb, assume call to Arm.
11149 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11150 function call at all, but rather a long jump. Calls through
11151 the PLT do not require stubs. */
34e77a92 11152 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11153 {
bd97cb95 11154 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11155 {
11156 /* Convert BL to BLX. */
11157 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11158 }
155d87d7
CL		 11159 else if (( r_type != R_ARM_THM_CALL)
11160 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11161 {
11162 if (elf32_thumb_to_arm_stub
11163 (info, sym_name, input_bfd, output_bfd, input_section,
11164 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11165 error_message))
11166 return bfd_reloc_ok;
11167 else
11168 return bfd_reloc_dangerous;
11169 }
da5938a2 11170 }
35fc36a8
RS		 11171 else if (branch_type == ST_BRANCH_TO_THUMB
11172 && globals->use_blx
bd97cb95 11173 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11174 {
11175 /* Make sure this is a BL. */
11176 lower_insn |= 0x1800;
11177 }
252b5132 11178 }
f21f3fe0 11179
fe33d2fa 11180 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11181 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11182 {
11183 /* Check if a stub has to be inserted because the destination
8029a119 11184 is too far. */
fe33d2fa
CL		 11185 struct elf32_arm_stub_hash_entry *stub_entry;
11186 struct elf32_arm_link_hash_entry *hash;
11187
11188 hash = (struct elf32_arm_link_hash_entry *) h;
11189
11190 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11191 st_type, &branch_type,
11192 hash, value, sym_sec,
fe33d2fa
CL		 11193 input_bfd, sym_name);
11194
11195 if (stub_type != arm_stub_none)
906e58ca
NC		 11196 {
11197 /* The target is out of reach or we are changing modes, so
11198 redirect the branch to the local stub for this
11199 function. */
11200 stub_entry = elf32_arm_get_stub_entry (input_section,
11201 sym_sec, h,
fe33d2fa
CL		 11202 rel, globals,
11203 stub_type);
906e58ca 11204 if (stub_entry != NULL)
9cd3e4e5
NC		 11205 {
11206 value = (stub_entry->stub_offset
11207 + stub_entry->stub_sec->output_offset
11208 + stub_entry->stub_sec->output_section->vma);
11209
11210 if (plt_offset != (bfd_vma) -1)
11211 *unresolved_reloc_p = FALSE;
11212 }
906e58ca 11213
f4ac8484 11214 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11215 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11216 {
11217 if ((stub_entry
11218 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11219 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11220 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11221 }
906e58ca
NC		 11222 }
11223 }
11224
fe33d2fa 11225 /* Handle calls via the PLT. */
34e77a92 11226 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11227 {
11228 value = (splt->output_section->vma
11229 + splt->output_offset
34e77a92 11230 + plt_offset);
fe33d2fa 11231
eed94f8f
NC		 11232 if (globals->use_blx
11233 && r_type == R_ARM_THM_CALL
11234 && ! using_thumb_only (globals))
fe33d2fa
CL		 11235 {
11236 /* If the Thumb BLX instruction is available, convert
11237 the BL to a BLX instruction to call the ARM-mode
11238 PLT entry. */
11239 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11240 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11241 }
11242 else
11243 {
eed94f8f
NC		 11244 if (! using_thumb_only (globals))
11245 /* Target the Thumb stub before the ARM PLT entry. */
11246 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11247 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11248 }
11249 *unresolved_reloc_p = FALSE;
11250 }
11251
ba96a88f 11252 relocation = value + signed_addend;
f21f3fe0 11253
252b5132 11254 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11255 + input_section->output_offset
11256 + rel->r_offset);
9a5aca8c 11257
252b5132
RH		 11258 check = relocation >> howto->rightshift;
11259
11260 /* If this is a signed value, the rightshift just dropped
11261 leading 1 bits (assuming twos complement). */
11262 if ((bfd_signed_vma) relocation >= 0)
11263 signed_check = check;
11264 else
11265 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11266
e95de063
MS		 11267 /* Calculate the permissable maximum and minimum values for
11268 this relocation according to whether we're relocating for
11269 Thumb-2 or not. */
11270 bitsize = howto->bitsize;
5e866f5a 11271 if (!thumb2_bl)
e95de063 11272 bitsize -= 2;
f6ebfac0 11273 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11274 reloc_signed_min = ~reloc_signed_max;
11275
252b5132 11276 /* Assumes two's complement. */
ba96a88f 11277 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11278 overflow = TRUE;
252b5132 11279
bd97cb95 11280 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11281 /* For a BLX instruction, make sure that the relocation is rounded up
11282 to a word boundary. This follows the semantics of the instruction
11283 which specifies that bit 1 of the target address will come from bit
11284 1 of the base address. */
11285 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11286
e95de063
MS		 11287 /* Put RELOCATION back into the insn. Assumes two's complement.
11288 We use the Thumb-2 encoding, which is safe even if dealing with
11289 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11290 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11291 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11292 | ((relocation >> 12) & 0x3ff)
11293 | (reloc_sign << 10);
906e58ca 11294 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11295 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11296 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11297 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11298
252b5132
RH		 11299 /* Put the relocated value back in the object file: */
11300 bfd_put_16 (input_bfd, upper_insn, hit_data);
11301 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11302
11303 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11304 }
11305 break;
11306
c19d1205
ZW		 11307 case R_ARM_THM_JUMP19:
11308 /* Thumb32 conditional branch instruction. */
11309 {
11310 bfd_vma relocation;
11311 bfd_boolean overflow = FALSE;
11312 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11313 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11314 bfd_signed_vma reloc_signed_max = 0xffffe;
11315 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11316 bfd_signed_vma signed_check;
07d6d2b8 11317 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11318 struct elf32_arm_stub_hash_entry *stub_entry;
11319 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11320
11321 /* Need to refetch the addend, reconstruct the top three bits,
11322 and squish the two 11 bit pieces together. */
11323 if (globals->use_rel)
11324 {
11325 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11326 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11327 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11328 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11329 bfd_vma lower = (lower_insn & 0x07ff);
11330
a00a1f35
MS		 11331 upper |= J1 << 6;
11332 upper |= J2 << 7;
11333 upper |= (!S) << 8;
c19d1205
ZW		 11334 upper -= 0x0100; /* Sign extend. */
11335
11336 addend = (upper << 12) | (lower << 1);
11337 signed_addend = addend;
11338 }
11339
bd97cb95 11340 /* Handle calls via the PLT. */
34e77a92 11341 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11342 {
11343 value = (splt->output_section->vma
11344 + splt->output_offset
34e77a92 11345 + plt_offset);
bd97cb95
DJ		 11346 /* Target the Thumb stub before the ARM PLT entry. */
11347 value -= PLT_THUMB_STUB_SIZE;
11348 *unresolved_reloc_p = FALSE;
11349 }
11350
c5423981
TG		 11351 hash = (struct elf32_arm_link_hash_entry *)h;
11352
11353 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11354 st_type, &branch_type,
11355 hash, value, sym_sec,
11356 input_bfd, sym_name);
c5423981
TG		 11357 if (stub_type != arm_stub_none)
11358 {
11359 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11360 sym_sec, h,
11361 rel, globals,
11362 stub_type);
c5423981
TG		 11363 if (stub_entry != NULL)
11364 {
07d6d2b8
AM		 11365 value = (stub_entry->stub_offset
11366 + stub_entry->stub_sec->output_offset
11367 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11368 }
11369 }
c19d1205 11370
99059e56 11371 relocation = value + signed_addend;
c19d1205
ZW		 11372 relocation -= (input_section->output_section->vma
11373 + input_section->output_offset
11374 + rel->r_offset);
a00a1f35 11375 signed_check = (bfd_signed_vma) relocation;
c19d1205 11376
c19d1205
ZW		 11377 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11378 overflow = TRUE;
11379
11380 /* Put RELOCATION back into the insn. */
11381 {
11382 bfd_vma S = (relocation & 0x00100000) >> 20;
11383 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11384 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11385 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11386 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11387
a00a1f35 11388 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11389 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11390 }
11391
11392 /* Put the relocated value back in the object file: */
11393 bfd_put_16 (input_bfd, upper_insn, hit_data);
11394 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11395
11396 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11397 }
11398
11399 case R_ARM_THM_JUMP11:
11400 case R_ARM_THM_JUMP8:
11401 case R_ARM_THM_JUMP6:
51c5503b
NC		 11402 /* Thumb B (branch) instruction). */
11403 {
6cf9e9fe 11404 bfd_signed_vma relocation;
51c5503b
NC		 11405 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11406 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11407 bfd_signed_vma signed_check;
11408
c19d1205
ZW		 11409 /* CZB cannot jump backward. */
11410 if (r_type == R_ARM_THM_JUMP6)
11411 reloc_signed_min = 0;
11412
4e7fd91e 11413 if (globals->use_rel)
6cf9e9fe 11414 {
4e7fd91e
PB		 11415 /* Need to refetch addend. */
11416 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11417 if (addend & ((howto->src_mask + 1) >> 1))
11418 {
11419 signed_addend = -1;
11420 signed_addend &= ~ howto->src_mask;
11421 signed_addend |= addend;
11422 }
11423 else
11424 signed_addend = addend;
11425 /* The value in the insn has been right shifted. We need to
11426 undo this, so that we can perform the address calculation
11427 in terms of bytes. */
11428 signed_addend <<= howto->rightshift;
6cf9e9fe 11429 }
6cf9e9fe 11430 relocation = value + signed_addend;
51c5503b
NC		 11431
11432 relocation -= (input_section->output_section->vma
11433 + input_section->output_offset
11434 + rel->r_offset);
11435
6cf9e9fe
NC		 11436 relocation >>= howto->rightshift;
11437 signed_check = relocation;
c19d1205
ZW		 11438
11439 if (r_type == R_ARM_THM_JUMP6)
11440 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11441 else
11442 relocation &= howto->dst_mask;
51c5503b 11443 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11444
51c5503b
NC		 11445 bfd_put_16 (input_bfd, relocation, hit_data);
11446
11447 /* Assumes two's complement. */
11448 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11449 return bfd_reloc_overflow;
11450
11451 return bfd_reloc_ok;
11452 }
cedb70c5 11453
8375c36b
PB		 11454 case R_ARM_ALU_PCREL7_0:
11455 case R_ARM_ALU_PCREL15_8:
11456 case R_ARM_ALU_PCREL23_15:
11457 {
11458 bfd_vma insn;
11459 bfd_vma relocation;
11460
11461 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11462 if (globals->use_rel)
11463 {
11464 /* Extract the addend. */
11465 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11466 signed_addend = addend;
11467 }
8375c36b
PB		 11468 relocation = value + signed_addend;
11469
11470 relocation -= (input_section->output_section->vma
11471 + input_section->output_offset
11472 + rel->r_offset);
11473 insn = (insn & ~0xfff)
11474 | ((howto->bitpos << 7) & 0xf00)
11475 | ((relocation >> howto->bitpos) & 0xff);
11476 bfd_put_32 (input_bfd, value, hit_data);
11477 }
11478 return bfd_reloc_ok;
11479
252b5132
RH		 11480 case R_ARM_GNU_VTINHERIT:
11481 case R_ARM_GNU_VTENTRY:
11482 return bfd_reloc_ok;
11483
c19d1205 11484 case R_ARM_GOTOFF32:
252b5132 11485 /* Relocation is relative to the start of the
99059e56 11486 global offset table. */
252b5132
RH		 11487
11488 BFD_ASSERT (sgot != NULL);
11489 if (sgot == NULL)
99059e56 11490 return bfd_reloc_notsupported;
9a5aca8c 11491
cedb70c5 11492 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11493 address by one, so that attempts to call the function pointer will
11494 correctly interpret it as Thumb code. */
35fc36a8 11495 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11496 value += 1;
11497
252b5132 11498 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11499 calculation. We always want the start of .got. If we
11500 define _GLOBAL_OFFSET_TABLE in a different way, as is
11501 permitted by the ABI, we might have to change this
11502 calculation. */
252b5132 11503 value -= sgot->output_section->vma;
f21f3fe0 11504 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11505 contents, rel->r_offset, value,
00a97672 11506 rel->r_addend);
252b5132
RH		 11507
11508 case R_ARM_GOTPC:
a7c10850 11509 /* Use global offset table as symbol value. */
252b5132 11510 BFD_ASSERT (sgot != NULL);
f21f3fe0 11511
252b5132 11512 if (sgot == NULL)
99059e56 11513 return bfd_reloc_notsupported;
252b5132 11514
0945cdfd 11515 *unresolved_reloc_p = FALSE;
252b5132 11516 value = sgot->output_section->vma;
f21f3fe0 11517 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11518 contents, rel->r_offset, value,
00a97672 11519 rel->r_addend);
f21f3fe0 11520
252b5132 11521 case R_ARM_GOT32:
eb043451 11522 case R_ARM_GOT_PREL:
252b5132 11523 /* Relocation is to the entry for this symbol in the
99059e56 11524 global offset table. */
252b5132
RH		 11525 if (sgot == NULL)
11526 return bfd_reloc_notsupported;
f21f3fe0 11527
34e77a92
RS		 11528 if (dynreloc_st_type == STT_GNU_IFUNC
11529 && plt_offset != (bfd_vma) -1
11530 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11531 {
11532 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11533 symbol, and the relocation resolves directly to the runtime
11534 target rather than to the .iplt entry. This means that any
11535 .got entry would be the same value as the .igot.plt entry,
11536 so there's no point creating both. */
11537 sgot = globals->root.igotplt;
11538 value = sgot->output_offset + gotplt_offset;
11539 }
11540 else if (h != NULL)
252b5132
RH		 11541 {
11542 bfd_vma off;
f21f3fe0 11543
252b5132
RH		 11544 off = h->got.offset;
11545 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11546 if ((off & 1) != 0)
252b5132 11547 {
b436d854
RS		 11548 /* We have already processsed one GOT relocation against
11549 this symbol. */
11550 off &= ~1;
11551 if (globals->root.dynamic_sections_created
11552 && !SYMBOL_REFERENCES_LOCAL (info, h))
11553 *unresolved_reloc_p = FALSE;
11554 }
11555 else
11556 {
11557 Elf_Internal_Rela outrel;
e8b09b87 11558 int isrofixup = 0;
b436d854 11559
e8b09b87
CL		 11560 if (((h->dynindx != -1) || globals->fdpic_p)
11561 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11562 {
11563 /* If the symbol doesn't resolve locally in a static
11564 object, we have an undefined reference. If the
11565 symbol doesn't resolve locally in a dynamic object,
11566 it should be resolved by the dynamic linker. */
11567 if (globals->root.dynamic_sections_created)
11568 {
11569 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11570 *unresolved_reloc_p = FALSE;
11571 }
11572 else
11573 outrel.r_info = 0;
11574 outrel.r_addend = 0;
11575 }
252b5132
RH		 11576 else
11577 {
34e77a92 11578 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11579 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c 11580 else if (bfd_link_pic (info)
7f026732 11581 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
99059e56
RM		 11582 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11583 else
2376f038
EB		 11584 {
11585 outrel.r_info = 0;
11586 if (globals->fdpic_p)
11587 isrofixup = 1;
11588 }
34e77a92 11589 outrel.r_addend = dynreloc_value;
b436d854 11590 }
ee29b9fb 11591
b436d854
RS		 11592 /* The GOT entry is initialized to zero by default.
11593 See if we should install a different value. */
11594 if (outrel.r_addend != 0
2376f038 11595 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11596 {
11597 bfd_put_32 (output_bfd, outrel.r_addend,
11598 sgot->contents + off);
11599 outrel.r_addend = 0;
252b5132 11600 }
f21f3fe0 11601
2376f038
EB		 11602 if (isrofixup)
11603 arm_elf_add_rofixup (output_bfd,
11604 elf32_arm_hash_table(info)->srofixup,
11605 sgot->output_section->vma
11606 + sgot->output_offset + off);
11607
11608 else if (outrel.r_info != 0)
b436d854
RS		 11609 {
11610 outrel.r_offset = (sgot->output_section->vma
11611 + sgot->output_offset
11612 + off);
11613 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11614 }
2376f038 11615
b436d854
RS		 11616 h->got.offset |= 1;
11617 }
252b5132
RH		 11618 value = sgot->output_offset + off;
11619 }
11620 else
11621 {
11622 bfd_vma off;
f21f3fe0 11623
5025eb7c
AO		 11624 BFD_ASSERT (local_got_offsets != NULL
11625 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11626
252b5132 11627 off = local_got_offsets[r_symndx];
f21f3fe0 11628
252b5132
RH		 11629 /* The offset must always be a multiple of 4. We use the
11630 least significant bit to record whether we have already
9b485d32 11631 generated the necessary reloc. */
252b5132
RH		 11632 if ((off & 1) != 0)
11633 off &= ~1;
11634 else
11635 {
2376f038
EB		 11636 Elf_Internal_Rela outrel;
11637 int isrofixup = 0;
f21f3fe0 11638
2376f038
EB		 11639 if (dynreloc_st_type == STT_GNU_IFUNC)
11640 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11641 else if (bfd_link_pic (info))
11642 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11643 else
252b5132 11644 {
2376f038
EB		 11645 outrel.r_info = 0;
11646 if (globals->fdpic_p)
11647 isrofixup = 1;
11648 }
11649
11650 /* The GOT entry is initialized to zero by default.
11651 See if we should install a different value. */
11652 if (globals->use_rel || outrel.r_info == 0)
11653 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11654
11655 if (isrofixup)
11656 arm_elf_add_rofixup (output_bfd,
11657 globals->srofixup,
11658 sgot->output_section->vma
11659 + sgot->output_offset + off);
f21f3fe0 11660
2376f038
EB		 11661 else if (outrel.r_info != 0)
11662 {
34e77a92 11663 outrel.r_addend = addend + dynreloc_value;
252b5132 11664 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11665 + sgot->output_offset
252b5132 11666 + off);
47beaa6a 11667 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11668 }
f21f3fe0 11669
252b5132
RH		 11670 local_got_offsets[r_symndx] |= 1;
11671 }
f21f3fe0 11672
252b5132
RH		 11673 value = sgot->output_offset + off;
11674 }
eb043451
PB		 11675 if (r_type != R_ARM_GOT32)
11676 value += sgot->output_section->vma;
9a5aca8c 11677
f21f3fe0 11678 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11679 contents, rel->r_offset, value,
00a97672 11680 rel->r_addend);
f21f3fe0 11681
ba93b8ac
DJ		 11682 case R_ARM_TLS_LDO32:
11683 value = value - dtpoff_base (info);
11684
11685 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11686 contents, rel->r_offset, value,
11687 rel->r_addend);
ba93b8ac
DJ		 11688
11689 case R_ARM_TLS_LDM32:
5c5a4843 11690 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11691 {
11692 bfd_vma off;
11693
362d30a1 11694 if (sgot == NULL)
ba93b8ac
DJ		 11695 abort ();
11696
11697 off = globals->tls_ldm_got.offset;
11698
11699 if ((off & 1) != 0)
11700 off &= ~1;
11701 else
11702 {
11703 /* If we don't know the module number, create a relocation
11704 for it. */
9cb09e33 11705 if (bfd_link_dll (info))
ba93b8ac
DJ		 11706 {
11707 Elf_Internal_Rela outrel;
ba93b8ac 11708
362d30a1 11709 if (srelgot == NULL)
ba93b8ac
DJ		 11710 abort ();
11711
00a97672 11712 outrel.r_addend = 0;
362d30a1
RS		 11713 outrel.r_offset = (sgot->output_section->vma
11714 + sgot->output_offset + off);
ba93b8ac
DJ		 11715 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11716
00a97672
RS		 11717 if (globals->use_rel)
11718 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11719 sgot->contents + off);
ba93b8ac 11720
47beaa6a 11721 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11722 }
11723 else
362d30a1 11724 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11725
11726 globals->tls_ldm_got.offset |= 1;
11727 }
11728
5c5a4843 11729 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11730 {
11731 bfd_put_32(output_bfd,
11732 globals->root.sgot->output_offset + off,
11733 contents + rel->r_offset);
11734
11735 return bfd_reloc_ok;
11736 }
11737 else
11738 {
11739 value = sgot->output_section->vma + sgot->output_offset + off
11740 - (input_section->output_section->vma
11741 + input_section->output_offset + rel->r_offset);
ba93b8ac 11742
e8b09b87
CL		 11743 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11744 contents, rel->r_offset, value,
11745 rel->r_addend);
11746 }
ba93b8ac
DJ		 11747 }
11748
0855e32b
NS		 11749 case R_ARM_TLS_CALL:
11750 case R_ARM_THM_TLS_CALL:
ba93b8ac 11751 case R_ARM_TLS_GD32:
5c5a4843 11752 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11753 case R_ARM_TLS_IE32:
5c5a4843 11754 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11755 case R_ARM_TLS_GOTDESC:
11756 case R_ARM_TLS_DESCSEQ:
11757 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11758 {
0855e32b
NS		 11759 bfd_vma off, offplt;
11760 int indx = 0;
ba93b8ac
DJ		 11761 char tls_type;
11762
0855e32b 11763 BFD_ASSERT (sgot != NULL);
ba93b8ac 11764
ba93b8ac
DJ		 11765 if (h != NULL)
11766 {
11767 bfd_boolean dyn;
11768 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11769 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11770 bfd_link_pic (info),
11771 h)
11772 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11773 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11774 {
11775 *unresolved_reloc_p = FALSE;
11776 indx = h->dynindx;
11777 }
11778 off = h->got.offset;
0855e32b 11779 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11780 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11781 }
11782 else
11783 {
0855e32b 11784 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11785 off = local_got_offsets[r_symndx];
0855e32b 11786 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11787 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11788 }
11789
0855e32b 11790 /* Linker relaxations happens from one of the
b38cadfb 11791 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11792 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11793 tls_type = GOT_TLS_IE;
0855e32b
NS		 11794
11795 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11796
11797 if ((off & 1) != 0)
11798 off &= ~1;
11799 else
11800 {
11801 bfd_boolean need_relocs = FALSE;
11802 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11803 int cur_off = off;
11804
11805 /* The GOT entries have not been initialized yet. Do it
11806 now, and emit any relocations. If both an IE GOT and a
11807 GD GOT are necessary, we emit the GD first. */
11808
9cb09e33 11809 if ((bfd_link_dll (info) || indx != 0)
ba93b8ac 11810 && (h == NULL
95b03e4a
L		 11811 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11812 && !resolved_to_zero)
ba93b8ac
DJ		 11813 || h->root.type != bfd_link_hash_undefweak))
11814 {
11815 need_relocs = TRUE;
0855e32b 11816 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11817 }
11818
0855e32b
NS		 11819 if (tls_type & GOT_TLS_GDESC)
11820 {
47beaa6a
RS		 11821 bfd_byte *loc;
11822
0855e32b
NS		 11823 /* We should have relaxed, unless this is an undefined
11824 weak symbol. */
11825 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
9cb09e33 11826 || bfd_link_dll (info));
0855e32b 11827 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11828 <= globals->root.sgotplt->size);
0855e32b
NS		 11829
11830 outrel.r_addend = 0;
11831 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11832 + globals->root.sgotplt->output_offset
11833 + offplt
11834 + globals->sgotplt_jump_table_size);
b38cadfb 11835
0855e32b
NS		 11836 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11837 sreloc = globals->root.srelplt;
11838 loc = sreloc->contents;
11839 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11840 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11841 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11842
11843 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11844
11845 /* For globals, the first word in the relocation gets
11846 the relocation index and the top bit set, or zero,
11847 if we're binding now. For locals, it gets the
11848 symbol's offset in the tls section. */
99059e56 11849 bfd_put_32 (output_bfd,
0855e32b
NS		 11850 !h ? value - elf_hash_table (info)->tls_sec->vma
11851 : info->flags & DF_BIND_NOW ? 0
11852 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11853 globals->root.sgotplt->contents + offplt
11854 + globals->sgotplt_jump_table_size);
11855
0855e32b 11856 /* Second word in the relocation is always zero. */
99059e56 11857 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11858 globals->root.sgotplt->contents + offplt
11859 + globals->sgotplt_jump_table_size + 4);
0855e32b 11860 }
ba93b8ac
DJ		 11861 if (tls_type & GOT_TLS_GD)
11862 {
11863 if (need_relocs)
11864 {
00a97672 11865 outrel.r_addend = 0;
362d30a1
RS		 11866 outrel.r_offset = (sgot->output_section->vma
11867 + sgot->output_offset
00a97672 11868 + cur_off);
ba93b8ac 11869 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11870
00a97672
RS		 11871 if (globals->use_rel)
11872 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11873 sgot->contents + cur_off);
00a97672 11874
47beaa6a 11875 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11876
11877 if (indx == 0)
11878 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11879 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11880 else
11881 {
00a97672 11882 outrel.r_addend = 0;
ba93b8ac
DJ		 11883 outrel.r_info = ELF32_R_INFO (indx,
11884 R_ARM_TLS_DTPOFF32);
11885 outrel.r_offset += 4;
00a97672
RS		 11886
11887 if (globals->use_rel)
11888 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11889 sgot->contents + cur_off + 4);
00a97672 11890
47beaa6a
RS		 11891 elf32_arm_add_dynreloc (output_bfd, info,
11892 srelgot, &outrel);
ba93b8ac
DJ		 11893 }
11894 }
11895 else
11896 {
11897 /* If we are not emitting relocations for a
11898 general dynamic reference, then we must be in a
11899 static link or an executable link with the
11900 symbol binding locally. Mark it as belonging
11901 to module 1, the executable. */
11902 bfd_put_32 (output_bfd, 1,
362d30a1 11903 sgot->contents + cur_off);
ba93b8ac 11904 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11905 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11906 }
11907
11908 cur_off += 8;
11909 }
11910
11911 if (tls_type & GOT_TLS_IE)
11912 {
11913 if (need_relocs)
11914 {
00a97672
RS		 11915 if (indx == 0)
11916 outrel.r_addend = value - dtpoff_base (info);
11917 else
11918 outrel.r_addend = 0;
362d30a1
RS		 11919 outrel.r_offset = (sgot->output_section->vma
11920 + sgot->output_offset
ba93b8ac
DJ		 11921 + cur_off);
11922 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11923
00a97672
RS		 11924 if (globals->use_rel)
11925 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11926 sgot->contents + cur_off);
ba93b8ac 11927
47beaa6a 11928 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11929 }
11930 else
11931 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11932 sgot->contents + cur_off);
ba93b8ac
DJ		 11933 cur_off += 4;
11934 }
11935
11936 if (h != NULL)
11937 h->got.offset |= 1;
11938 else
11939 local_got_offsets[r_symndx] |= 1;
11940 }
11941
5c5a4843 11942 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11943 off += 8;
0855e32b
NS		 11944 else if (tls_type & GOT_TLS_GDESC)
11945 off = offplt;
11946
11947 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11948 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11949 {
11950 bfd_signed_vma offset;
12352d3f
PB		 11951 /* TLS stubs are arm mode. The original symbol is a
11952 data object, so branch_type is bogus. */
11953 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11954 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11955 = arm_type_of_stub (info, input_section, rel,
11956 st_type, &branch_type,
0855e32b
NS		 11957 (struct elf32_arm_link_hash_entry *)h,
11958 globals->tls_trampoline, globals->root.splt,
11959 input_bfd, sym_name);
11960
11961 if (stub_type != arm_stub_none)
11962 {
11963 struct elf32_arm_stub_hash_entry *stub_entry
11964 = elf32_arm_get_stub_entry
11965 (input_section, globals->root.splt, 0, rel,
11966 globals, stub_type);
11967 offset = (stub_entry->stub_offset
11968 + stub_entry->stub_sec->output_offset
11969 + stub_entry->stub_sec->output_section->vma);
11970 }
11971 else
11972 offset = (globals->root.splt->output_section->vma
11973 + globals->root.splt->output_offset
11974 + globals->tls_trampoline);
11975
11976 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11977 {
11978 unsigned long inst;
b38cadfb
NC		 11979
11980 offset -= (input_section->output_section->vma
11981 + input_section->output_offset
11982 + rel->r_offset + 8);
0855e32b
NS		 11983
11984 inst = offset >> 2;
11985 inst &= 0x00ffffff;
11986 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11987 }
11988 else
11989 {
11990 /* Thumb blx encodes the offset in a complicated
11991 fashion. */
11992 unsigned upper_insn, lower_insn;
11993 unsigned neg;
11994
b38cadfb
NC		 11995 offset -= (input_section->output_section->vma
11996 + input_section->output_offset
0855e32b 11997 + rel->r_offset + 4);
b38cadfb 11998
12352d3f
PB		 11999 if (stub_type != arm_stub_none
12000 && arm_stub_is_thumb (stub_type))
12001 {
12002 lower_insn = 0xd000;
12003 }
12004 else
12005 {
12006 lower_insn = 0xc000;
6a631e86 12007 /* Round up the offset to a word boundary. */
12352d3f
PB		 12008 offset = (offset + 2) & ~2;
12009 }
12010
0855e32b
NS		 12011 neg = offset < 0;
12012 upper_insn = (0xf000
12013 | ((offset >> 12) & 0x3ff)
12014 | (neg << 10));
12352d3f 12015 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 12016 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 12017 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 12018 bfd_put_16 (input_bfd, upper_insn, hit_data);
12019 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12020 return bfd_reloc_ok;
12021 }
12022 }
12023 /* These relocations needs special care, as besides the fact
12024 they point somewhere in .gotplt, the addend must be
12025 adjusted accordingly depending on the type of instruction
6a631e86 12026 we refer to. */
0855e32b
NS		 12027 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
12028 {
12029 unsigned long data, insn;
12030 unsigned thumb;
b38cadfb 12031
b627f562 12032 data = bfd_get_signed_32 (input_bfd, hit_data);
0855e32b 12033 thumb = data & 1;
b627f562 12034 data &= ~1ul;
b38cadfb 12035
0855e32b
NS		 12036 if (thumb)
12037 {
12038 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
12039 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
12040 insn = (insn << 16)
12041 | bfd_get_16 (input_bfd,
12042 contents + rel->r_offset - data + 2);
12043 if ((insn & 0xf800c000) == 0xf000c000)
12044 /* bl/blx */
12045 value = -6;
12046 else if ((insn & 0xffffff00) == 0x4400)
12047 /* add */
12048 value = -5;
12049 else
12050 {
4eca0228 12051 _bfd_error_handler
695344c0 12052 /* xgettext:c-format */
2dcf00ce 12053 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12054 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12055 "referenced by TLS_GOTDESC"),
12056 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12057 "Thumb", insn);
0855e32b
NS		 12058 return bfd_reloc_notsupported;
12059 }
12060 }
12061 else
12062 {
12063 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12064
12065 switch (insn >> 24)
12066 {
12067 case 0xeb: /* bl */
12068 case 0xfa: /* blx */
12069 value = -4;
12070 break;
12071
12072 case 0xe0: /* add */
12073 value = -8;
12074 break;
b38cadfb 12075
0855e32b 12076 default:
4eca0228 12077 _bfd_error_handler
695344c0 12078 /* xgettext:c-format */
2dcf00ce 12079 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12080 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12081 "referenced by TLS_GOTDESC"),
12082 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12083 "ARM", insn);
0855e32b
NS		 12084 return bfd_reloc_notsupported;
12085 }
12086 }
b38cadfb 12087
0855e32b
NS		 12088 value += ((globals->root.sgotplt->output_section->vma
12089 + globals->root.sgotplt->output_offset + off)
12090 - (input_section->output_section->vma
12091 + input_section->output_offset
12092 + rel->r_offset)
12093 + globals->sgotplt_jump_table_size);
12094 }
12095 else
12096 value = ((globals->root.sgot->output_section->vma
12097 + globals->root.sgot->output_offset + off)
12098 - (input_section->output_section->vma
12099 + input_section->output_offset + rel->r_offset));
ba93b8ac 12100
5c5a4843
CL		 12101 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12102 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12103 {
12104 /* For FDPIC relocations, resolve to the offset of the GOT
12105 entry from the start of GOT. */
12106 bfd_put_32(output_bfd,
12107 globals->root.sgot->output_offset + off,
12108 contents + rel->r_offset);
12109
12110 return bfd_reloc_ok;
12111 }
12112 else
12113 {
12114 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12115 contents, rel->r_offset, value,
12116 rel->r_addend);
12117 }
ba93b8ac
DJ		 12118 }
12119
12120 case R_ARM_TLS_LE32:
3cbc1e5e 12121 if (bfd_link_dll (info))
ba93b8ac 12122 {
4eca0228 12123 _bfd_error_handler
695344c0 12124 /* xgettext:c-format */
2dcf00ce
AM		 12125 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12126 "in shared object"),
12127 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12128 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12129 }
12130 else
12131 value = tpoff (info, value);
906e58ca 12132
ba93b8ac 12133 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12134 contents, rel->r_offset, value,
12135 rel->r_addend);
ba93b8ac 12136
319850b4
JB		 12137 case R_ARM_V4BX:
12138 if (globals->fix_v4bx)
845b51d6
PB		 12139 {
12140 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12141
845b51d6
PB		 12142 /* Ensure that we have a BX instruction. */
12143 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12144
845b51d6
PB		 12145 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12146 {
12147 /* Branch to veneer. */
12148 bfd_vma glue_addr;
12149 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12150 glue_addr -= input_section->output_section->vma
12151 + input_section->output_offset
12152 + rel->r_offset + 8;
12153 insn = (insn & 0xf0000000) | 0x0a000000
12154 | ((glue_addr >> 2) & 0x00ffffff);
12155 }
12156 else
12157 {
12158 /* Preserve Rm (lowest four bits) and the condition code
12159 (highest four bits). Other bits encode MOV PC,Rm. */
12160 insn = (insn & 0xf000000f) | 0x01a0f000;
12161 }
319850b4 12162
845b51d6
PB		 12163 bfd_put_32 (input_bfd, insn, hit_data);
12164 }
319850b4
JB		 12165 return bfd_reloc_ok;
12166
b6895b4f
PB		 12167 case R_ARM_MOVW_ABS_NC:
12168 case R_ARM_MOVT_ABS:
12169 case R_ARM_MOVW_PREL_NC:
12170 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12171 /* Until we properly support segment-base-relative addressing then
12172 we assume the segment base to be zero, as for the group relocations.
12173 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12174 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12175 case R_ARM_MOVW_BREL_NC:
12176 case R_ARM_MOVW_BREL:
12177 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12178 {
12179 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12180
12181 if (globals->use_rel)
12182 {
12183 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12184 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12185 }
92f5d02b 12186
b6895b4f 12187 value += signed_addend;
b6895b4f
PB		 12188
12189 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12190 value -= (input_section->output_section->vma
12191 + input_section->output_offset + rel->r_offset);
12192
92f5d02b 12193 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12194 return bfd_reloc_overflow;
92f5d02b 12195
35fc36a8 12196 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12197 value |= 1;
12198
12199 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12200 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12201 value >>= 16;
12202
12203 insn &= 0xfff0f000;
12204 insn |= value & 0xfff;
12205 insn |= (value & 0xf000) << 4;
12206 bfd_put_32 (input_bfd, insn, hit_data);
12207 }
12208 return bfd_reloc_ok;
12209
12210 case R_ARM_THM_MOVW_ABS_NC:
12211 case R_ARM_THM_MOVT_ABS:
12212 case R_ARM_THM_MOVW_PREL_NC:
12213 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12214 /* Until we properly support segment-base-relative addressing then
12215 we assume the segment base to be zero, as for the above relocations.
12216 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12217 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12218 as R_ARM_THM_MOVT_ABS. */
12219 case R_ARM_THM_MOVW_BREL_NC:
12220 case R_ARM_THM_MOVW_BREL:
12221 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12222 {
12223 bfd_vma insn;
906e58ca 12224
b6895b4f
PB		 12225 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12226 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12227
12228 if (globals->use_rel)
12229 {
12230 addend = ((insn >> 4) & 0xf000)
12231 | ((insn >> 15) & 0x0800)
12232 | ((insn >> 4) & 0x0700)
07d6d2b8 12233 | (insn & 0x00ff);
39623e12 12234 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12235 }
92f5d02b 12236
b6895b4f 12237 value += signed_addend;
b6895b4f
PB		 12238
12239 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12240 value -= (input_section->output_section->vma
12241 + input_section->output_offset + rel->r_offset);
12242
92f5d02b 12243 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12244 return bfd_reloc_overflow;
92f5d02b 12245
35fc36a8 12246 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12247 value |= 1;
12248
12249 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12250 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12251 value >>= 16;
12252
12253 insn &= 0xfbf08f00;
12254 insn |= (value & 0xf000) << 4;
12255 insn |= (value & 0x0800) << 15;
12256 insn |= (value & 0x0700) << 4;
12257 insn |= (value & 0x00ff);
12258
12259 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12260 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12261 }
12262 return bfd_reloc_ok;
12263
4962c51a
MS		 12264 case R_ARM_ALU_PC_G0_NC:
12265 case R_ARM_ALU_PC_G1_NC:
12266 case R_ARM_ALU_PC_G0:
12267 case R_ARM_ALU_PC_G1:
12268 case R_ARM_ALU_PC_G2:
12269 case R_ARM_ALU_SB_G0_NC:
12270 case R_ARM_ALU_SB_G1_NC:
12271 case R_ARM_ALU_SB_G0:
12272 case R_ARM_ALU_SB_G1:
12273 case R_ARM_ALU_SB_G2:
12274 {
12275 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12276 bfd_vma pc = input_section->output_section->vma
4962c51a 12277 + input_section->output_offset + rel->r_offset;
31a91d61 12278 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12279 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12280 bfd_vma residual;
12281 bfd_vma g_n;
4962c51a 12282 bfd_signed_vma signed_value;
99059e56
RM		 12283 int group = 0;
12284
12285 /* Determine which group of bits to select. */
12286 switch (r_type)
12287 {
12288 case R_ARM_ALU_PC_G0_NC:
12289 case R_ARM_ALU_PC_G0:
12290 case R_ARM_ALU_SB_G0_NC:
12291 case R_ARM_ALU_SB_G0:
12292 group = 0;
12293 break;
12294
12295 case R_ARM_ALU_PC_G1_NC:
12296 case R_ARM_ALU_PC_G1:
12297 case R_ARM_ALU_SB_G1_NC:
12298 case R_ARM_ALU_SB_G1:
12299 group = 1;
12300 break;
12301
12302 case R_ARM_ALU_PC_G2:
12303 case R_ARM_ALU_SB_G2:
12304 group = 2;
12305 break;
12306
12307 default:
12308 abort ();
12309 }
12310
12311 /* If REL, extract the addend from the insn. If RELA, it will
12312 have already been fetched for us. */
4962c51a 12313 if (globals->use_rel)
99059e56
RM		 12314 {
12315 int negative;
12316 bfd_vma constant = insn & 0xff;
12317 bfd_vma rotation = (insn & 0xf00) >> 8;
12318
12319 if (rotation == 0)
12320 signed_addend = constant;
12321 else
12322 {
12323 /* Compensate for the fact that in the instruction, the
12324 rotation is stored in multiples of 2 bits. */
12325 rotation *= 2;
12326
12327 /* Rotate "constant" right by "rotation" bits. */
12328 signed_addend = (constant >> rotation) |
12329 (constant << (8 * sizeof (bfd_vma) - rotation));
12330 }
12331
12332 /* Determine if the instruction is an ADD or a SUB.
12333 (For REL, this determines the sign of the addend.) */
12334 negative = identify_add_or_sub (insn);
12335 if (negative == 0)
12336 {
4eca0228 12337 _bfd_error_handler
695344c0 12338 /* xgettext:c-format */
90b6238f 12339 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12340 "are allowed for ALU group relocations"),
12341 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12342 return bfd_reloc_overflow;
12343 }
12344
12345 signed_addend *= negative;
12346 }
4962c51a
MS		 12347
12348 /* Compute the value (X) to go in the place. */
99059e56
RM		 12349 if (r_type == R_ARM_ALU_PC_G0_NC
12350 || r_type == R_ARM_ALU_PC_G1_NC
12351 || r_type == R_ARM_ALU_PC_G0
12352 || r_type == R_ARM_ALU_PC_G1
12353 || r_type == R_ARM_ALU_PC_G2)
12354 /* PC relative. */
12355 signed_value = value - pc + signed_addend;
12356 else
12357 /* Section base relative. */
12358 signed_value = value - sb + signed_addend;
12359
12360 /* If the target symbol is a Thumb function, then set the
12361 Thumb bit in the address. */
35fc36a8 12362 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12363 signed_value |= 1;
12364
99059e56
RM		 12365 /* Calculate the value of the relevant G_n, in encoded
12366 constant-with-rotation format. */
b6518b38
NC		 12367 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12368 group, &residual);
99059e56
RM		 12369
12370 /* Check for overflow if required. */
12371 if ((r_type == R_ARM_ALU_PC_G0
12372 || r_type == R_ARM_ALU_PC_G1
12373 || r_type == R_ARM_ALU_PC_G2
12374 || r_type == R_ARM_ALU_SB_G0
12375 || r_type == R_ARM_ALU_SB_G1
12376 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12377 {
4eca0228 12378 _bfd_error_handler
695344c0 12379 /* xgettext:c-format */
90b6238f 12380 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12381 "splitting %#" PRIx64 " for group relocation %s"),
12382 input_bfd, input_section, (uint64_t) rel->r_offset,
12383 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12384 howto->name);
99059e56
RM		 12385 return bfd_reloc_overflow;
12386 }
12387
12388 /* Mask out the value and the ADD/SUB part of the opcode; take care
12389 not to destroy the S bit. */
12390 insn &= 0xff1ff000;
12391
12392 /* Set the opcode according to whether the value to go in the
12393 place is negative. */
12394 if (signed_value < 0)
12395 insn |= 1 << 22;
12396 else
12397 insn |= 1 << 23;
12398
12399 /* Encode the offset. */
12400 insn |= g_n;
4962c51a
MS		 12401
12402 bfd_put_32 (input_bfd, insn, hit_data);
12403 }
12404 return bfd_reloc_ok;
12405
12406 case R_ARM_LDR_PC_G0:
12407 case R_ARM_LDR_PC_G1:
12408 case R_ARM_LDR_PC_G2:
12409 case R_ARM_LDR_SB_G0:
12410 case R_ARM_LDR_SB_G1:
12411 case R_ARM_LDR_SB_G2:
12412 {
12413 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12414 bfd_vma pc = input_section->output_section->vma
4962c51a 12415 + input_section->output_offset + rel->r_offset;
31a91d61 12416 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12417 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12418 bfd_vma residual;
4962c51a 12419 bfd_signed_vma signed_value;
99059e56
RM		 12420 int group = 0;
12421
12422 /* Determine which groups of bits to calculate. */
12423 switch (r_type)
12424 {
12425 case R_ARM_LDR_PC_G0:
12426 case R_ARM_LDR_SB_G0:
12427 group = 0;
12428 break;
12429
12430 case R_ARM_LDR_PC_G1:
12431 case R_ARM_LDR_SB_G1:
12432 group = 1;
12433 break;
12434
12435 case R_ARM_LDR_PC_G2:
12436 case R_ARM_LDR_SB_G2:
12437 group = 2;
12438 break;
12439
12440 default:
12441 abort ();
12442 }
12443
12444 /* If REL, extract the addend from the insn. If RELA, it will
12445 have already been fetched for us. */
4962c51a 12446 if (globals->use_rel)
99059e56
RM		 12447 {
12448 int negative = (insn & (1 << 23)) ? 1 : -1;
12449 signed_addend = negative * (insn & 0xfff);
12450 }
4962c51a
MS		 12451
12452 /* Compute the value (X) to go in the place. */
99059e56
RM		 12453 if (r_type == R_ARM_LDR_PC_G0
12454 || r_type == R_ARM_LDR_PC_G1
12455 || r_type == R_ARM_LDR_PC_G2)
12456 /* PC relative. */
12457 signed_value = value - pc + signed_addend;
12458 else
12459 /* Section base relative. */
12460 signed_value = value - sb + signed_addend;
12461
12462 /* Calculate the value of the relevant G_{n-1} to obtain
12463 the residual at that stage. */
b6518b38
NC		 12464 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12465 group - 1, &residual);
99059e56
RM		 12466
12467 /* Check for overflow. */
12468 if (residual >= 0x1000)
12469 {
4eca0228 12470 _bfd_error_handler
695344c0 12471 /* xgettext:c-format */
90b6238f 12472 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12473 "splitting %#" PRIx64 " for group relocation %s"),
12474 input_bfd, input_section, (uint64_t) rel->r_offset,
12475 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12476 howto->name);
99059e56
RM		 12477 return bfd_reloc_overflow;
12478 }
12479
12480 /* Mask out the value and U bit. */
12481 insn &= 0xff7ff000;
12482
12483 /* Set the U bit if the value to go in the place is non-negative. */
12484 if (signed_value >= 0)
12485 insn |= 1 << 23;
12486
12487 /* Encode the offset. */
12488 insn |= residual;
4962c51a
MS		 12489
12490 bfd_put_32 (input_bfd, insn, hit_data);
12491 }
12492 return bfd_reloc_ok;
12493
12494 case R_ARM_LDRS_PC_G0:
12495 case R_ARM_LDRS_PC_G1:
12496 case R_ARM_LDRS_PC_G2:
12497 case R_ARM_LDRS_SB_G0:
12498 case R_ARM_LDRS_SB_G1:
12499 case R_ARM_LDRS_SB_G2:
12500 {
12501 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12502 bfd_vma pc = input_section->output_section->vma
4962c51a 12503 + input_section->output_offset + rel->r_offset;
31a91d61 12504 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12505 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12506 bfd_vma residual;
4962c51a 12507 bfd_signed_vma signed_value;
99059e56
RM		 12508 int group = 0;
12509
12510 /* Determine which groups of bits to calculate. */
12511 switch (r_type)
12512 {
12513 case R_ARM_LDRS_PC_G0:
12514 case R_ARM_LDRS_SB_G0:
12515 group = 0;
12516 break;
12517
12518 case R_ARM_LDRS_PC_G1:
12519 case R_ARM_LDRS_SB_G1:
12520 group = 1;
12521 break;
12522
12523 case R_ARM_LDRS_PC_G2:
12524 case R_ARM_LDRS_SB_G2:
12525 group = 2;
12526 break;
12527
12528 default:
12529 abort ();
12530 }
12531
12532 /* If REL, extract the addend from the insn. If RELA, it will
12533 have already been fetched for us. */
4962c51a 12534 if (globals->use_rel)
99059e56
RM		 12535 {
12536 int negative = (insn & (1 << 23)) ? 1 : -1;
12537 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12538 }
4962c51a
MS		 12539
12540 /* Compute the value (X) to go in the place. */
99059e56
RM		 12541 if (r_type == R_ARM_LDRS_PC_G0
12542 || r_type == R_ARM_LDRS_PC_G1
12543 || r_type == R_ARM_LDRS_PC_G2)
12544 /* PC relative. */
12545 signed_value = value - pc + signed_addend;
12546 else
12547 /* Section base relative. */
12548 signed_value = value - sb + signed_addend;
12549
12550 /* Calculate the value of the relevant G_{n-1} to obtain
12551 the residual at that stage. */
b6518b38
NC		 12552 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12553 group - 1, &residual);
99059e56
RM		 12554
12555 /* Check for overflow. */
12556 if (residual >= 0x100)
12557 {
4eca0228 12558 _bfd_error_handler
695344c0 12559 /* xgettext:c-format */
90b6238f 12560 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12561 "splitting %#" PRIx64 " for group relocation %s"),
12562 input_bfd, input_section, (uint64_t) rel->r_offset,
12563 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12564 howto->name);
99059e56
RM		 12565 return bfd_reloc_overflow;
12566 }
12567
12568 /* Mask out the value and U bit. */
12569 insn &= 0xff7ff0f0;
12570
12571 /* Set the U bit if the value to go in the place is non-negative. */
12572 if (signed_value >= 0)
12573 insn |= 1 << 23;
12574
12575 /* Encode the offset. */
12576 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12577
12578 bfd_put_32 (input_bfd, insn, hit_data);
12579 }
12580 return bfd_reloc_ok;
12581
12582 case R_ARM_LDC_PC_G0:
12583 case R_ARM_LDC_PC_G1:
12584 case R_ARM_LDC_PC_G2:
12585 case R_ARM_LDC_SB_G0:
12586 case R_ARM_LDC_SB_G1:
12587 case R_ARM_LDC_SB_G2:
12588 {
12589 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12590 bfd_vma pc = input_section->output_section->vma
4962c51a 12591 + input_section->output_offset + rel->r_offset;
31a91d61 12592 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12593 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12594 bfd_vma residual;
4962c51a 12595 bfd_signed_vma signed_value;
99059e56
RM		 12596 int group = 0;
12597
12598 /* Determine which groups of bits to calculate. */
12599 switch (r_type)
12600 {
12601 case R_ARM_LDC_PC_G0:
12602 case R_ARM_LDC_SB_G0:
12603 group = 0;
12604 break;
12605
12606 case R_ARM_LDC_PC_G1:
12607 case R_ARM_LDC_SB_G1:
12608 group = 1;
12609 break;
12610
12611 case R_ARM_LDC_PC_G2:
12612 case R_ARM_LDC_SB_G2:
12613 group = 2;
12614 break;
12615
12616 default:
12617 abort ();
12618 }
12619
12620 /* If REL, extract the addend from the insn. If RELA, it will
12621 have already been fetched for us. */
4962c51a 12622 if (globals->use_rel)
99059e56
RM		 12623 {
12624 int negative = (insn & (1 << 23)) ? 1 : -1;
12625 signed_addend = negative * ((insn & 0xff) << 2);
12626 }
4962c51a
MS		 12627
12628 /* Compute the value (X) to go in the place. */
99059e56
RM		 12629 if (r_type == R_ARM_LDC_PC_G0
12630 || r_type == R_ARM_LDC_PC_G1
12631 || r_type == R_ARM_LDC_PC_G2)
12632 /* PC relative. */
12633 signed_value = value - pc + signed_addend;
12634 else
12635 /* Section base relative. */
12636 signed_value = value - sb + signed_addend;
12637
12638 /* Calculate the value of the relevant G_{n-1} to obtain
12639 the residual at that stage. */
b6518b38
NC		 12640 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12641 group - 1, &residual);
99059e56
RM		 12642
12643 /* Check for overflow. (The absolute value to go in the place must be
12644 divisible by four and, after having been divided by four, must
12645 fit in eight bits.) */
12646 if ((residual & 0x3) != 0 || residual >= 0x400)
12647 {
4eca0228 12648 _bfd_error_handler
695344c0 12649 /* xgettext:c-format */
90b6238f 12650 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12651 "splitting %#" PRIx64 " for group relocation %s"),
12652 input_bfd, input_section, (uint64_t) rel->r_offset,
12653 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12654 howto->name);
99059e56
RM		 12655 return bfd_reloc_overflow;
12656 }
12657
12658 /* Mask out the value and U bit. */
12659 insn &= 0xff7fff00;
12660
12661 /* Set the U bit if the value to go in the place is non-negative. */
12662 if (signed_value >= 0)
12663 insn |= 1 << 23;
12664
12665 /* Encode the offset. */
12666 insn |= residual >> 2;
4962c51a
MS		 12667
12668 bfd_put_32 (input_bfd, insn, hit_data);
12669 }
12670 return bfd_reloc_ok;
12671
72d98d16
MG		 12672 case R_ARM_THM_ALU_ABS_G0_NC:
12673 case R_ARM_THM_ALU_ABS_G1_NC:
12674 case R_ARM_THM_ALU_ABS_G2_NC:
12675 case R_ARM_THM_ALU_ABS_G3_NC:
12676 {
12677 const int shift_array[4] = {0, 8, 16, 24};
12678 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12679 bfd_vma addr = value;
12680 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12681
12682 /* Compute address. */
12683 if (globals->use_rel)
12684 signed_addend = insn & 0xff;
12685 addr += signed_addend;
12686 if (branch_type == ST_BRANCH_TO_THUMB)
12687 addr |= 1;
12688 /* Clean imm8 insn. */
12689 insn &= 0xff00;
12690 /* And update with correct part of address. */
12691 insn |= (addr >> shift) & 0xff;
12692 /* Update insn. */
12693 bfd_put_16 (input_bfd, insn, hit_data);
12694 }
12695
12696 *unresolved_reloc_p = FALSE;
12697 return bfd_reloc_ok;
12698
e8b09b87
CL		 12699 case R_ARM_GOTOFFFUNCDESC:
12700 {
4b24dd1a 12701 if (h == NULL)
e8b09b87
CL		 12702 {
12703 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12704 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12705 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12706 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12707 bfd_vma seg = -1;
12708
12709 if (bfd_link_pic(info) && dynindx == 0)
12710 abort();
12711
12712 /* Resolve relocation. */
12713 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12714 , contents + rel->r_offset);
12715 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12716 not done yet. */
12717 arm_elf_fill_funcdesc(output_bfd, info,
12718 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12719 dynindx, offset, addr, dynreloc_value, seg);
12720 }
12721 else
12722 {
12723 int dynindx;
12724 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12725 bfd_vma addr;
12726 bfd_vma seg = -1;
12727
12728 /* For static binaries, sym_sec can be null. */
12729 if (sym_sec)
12730 {
12731 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12732 addr = dynreloc_value - sym_sec->output_section->vma;
12733 }
12734 else
12735 {
12736 dynindx = 0;
12737 addr = 0;
12738 }
12739
12740 if (bfd_link_pic(info) && dynindx == 0)
12741 abort();
12742
12743 /* This case cannot occur since funcdesc is allocated by
12744 the dynamic loader so we cannot resolve the relocation. */
12745 if (h->dynindx != -1)
12746 abort();
12747
12748 /* Resolve relocation. */
12749 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12750 contents + rel->r_offset);
12751 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12752 arm_elf_fill_funcdesc(output_bfd, info,
12753 &eh->fdpic_cnts.funcdesc_offset,
12754 dynindx, offset, addr, dynreloc_value, seg);
12755 }
12756 }
12757 *unresolved_reloc_p = FALSE;
12758 return bfd_reloc_ok;
12759
12760 case R_ARM_GOTFUNCDESC:
12761 {
4b24dd1a 12762 if (h != NULL)
e8b09b87
CL		 12763 {
12764 Elf_Internal_Rela outrel;
12765
12766 /* Resolve relocation. */
12767 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12768 + sgot->output_offset),
12769 contents + rel->r_offset);
12770 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12771 if(h->dynindx == -1)
12772 {
12773 int dynindx;
12774 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12775 bfd_vma addr;
12776 bfd_vma seg = -1;
12777
12778 /* For static binaries sym_sec can be null. */
12779 if (sym_sec)
12780 {
12781 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12782 addr = dynreloc_value - sym_sec->output_section->vma;
12783 }
12784 else
12785 {
12786 dynindx = 0;
12787 addr = 0;
12788 }
12789
12790 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12791 arm_elf_fill_funcdesc(output_bfd, info,
12792 &eh->fdpic_cnts.funcdesc_offset,
12793 dynindx, offset, addr, dynreloc_value, seg);
12794 }
12795
12796 /* Add a dynamic relocation on GOT entry if not already done. */
12797 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12798 {
12799 if (h->dynindx == -1)
12800 {
12801 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12802 if (h->root.type == bfd_link_hash_undefweak)
12803 bfd_put_32(output_bfd, 0, sgot->contents
12804 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12805 else
12806 bfd_put_32(output_bfd, sgot->output_section->vma
12807 + sgot->output_offset
12808 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12809 sgot->contents
12810 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12811 }
12812 else
12813 {
12814 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12815 }
12816 outrel.r_offset = sgot->output_section->vma
12817 + sgot->output_offset
12818 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12819 outrel.r_addend = 0;
12820 if (h->dynindx == -1 && !bfd_link_pic(info))
12821 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12822 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12823 else
4b24dd1a
AM		 12824 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12825 outrel.r_offset);
e8b09b87
CL		 12826 else
12827 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12828 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12829 }
12830 }
12831 else
12832 {
12833 /* Such relocation on static function should not have been
12834 emitted by the compiler. */
12835 abort();
12836 }
12837 }
12838 *unresolved_reloc_p = FALSE;
12839 return bfd_reloc_ok;
12840
12841 case R_ARM_FUNCDESC:
12842 {
4b24dd1a 12843 if (h == NULL)
e8b09b87
CL		 12844 {
12845 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12846 Elf_Internal_Rela outrel;
12847 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12848 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12849 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12850 bfd_vma seg = -1;
12851
12852 if (bfd_link_pic(info) && dynindx == 0)
12853 abort();
12854
12855 /* Replace static FUNCDESC relocation with a
12856 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12857 executable. */
12858 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12859 outrel.r_offset = input_section->output_section->vma
12860 + input_section->output_offset + rel->r_offset;
12861 outrel.r_addend = 0;
12862 if (bfd_link_pic(info))
12863 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12864 else
12865 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12866
12867 bfd_put_32 (input_bfd, sgot->output_section->vma
12868 + sgot->output_offset + offset, hit_data);
12869
12870 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12871 arm_elf_fill_funcdesc(output_bfd, info,
12872 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12873 dynindx, offset, addr, dynreloc_value, seg);
12874 }
12875 else
12876 {
12877 if (h->dynindx == -1)
12878 {
12879 int dynindx;
12880 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12881 bfd_vma addr;
12882 bfd_vma seg = -1;
12883 Elf_Internal_Rela outrel;
12884
12885 /* For static binaries sym_sec can be null. */
12886 if (sym_sec)
12887 {
12888 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12889 addr = dynreloc_value - sym_sec->output_section->vma;
12890 }
12891 else
12892 {
12893 dynindx = 0;
12894 addr = 0;
12895 }
12896
12897 if (bfd_link_pic(info) && dynindx == 0)
12898 abort();
12899
12900 /* Replace static FUNCDESC relocation with a
12901 R_ARM_RELATIVE dynamic relocation. */
12902 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12903 outrel.r_offset = input_section->output_section->vma
12904 + input_section->output_offset + rel->r_offset;
12905 outrel.r_addend = 0;
12906 if (bfd_link_pic(info))
12907 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12908 else
12909 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12910
12911 bfd_put_32 (input_bfd, sgot->output_section->vma
12912 + sgot->output_offset + offset, hit_data);
12913
12914 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12915 arm_elf_fill_funcdesc(output_bfd, info,
12916 &eh->fdpic_cnts.funcdesc_offset,
12917 dynindx, offset, addr, dynreloc_value, seg);
12918 }
12919 else
12920 {
12921 Elf_Internal_Rela outrel;
12922
12923 /* Add a dynamic relocation. */
12924 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12925 outrel.r_offset = input_section->output_section->vma
12926 + input_section->output_offset + rel->r_offset;
12927 outrel.r_addend = 0;
12928 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12929 }
12930 }
12931 }
12932 *unresolved_reloc_p = FALSE;
12933 return bfd_reloc_ok;
12934
e5d6e09e
AV		 12935 case R_ARM_THM_BF16:
12936 {
12937 bfd_vma relocation;
12938 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12939 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12940
12941 if (globals->use_rel)
12942 {
12943 bfd_vma immA = (upper_insn & 0x001f);
12944 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12945 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12946 addend = (immA << 12);
12947 addend |= (immB << 2);
12948 addend |= (immC << 1);
12949 addend |= 1;
12950 /* Sign extend. */
e6f65e75 12951 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12952 }
12953
e6f65e75 12954 relocation = value + signed_addend;
e5d6e09e
AV		 12955 relocation -= (input_section->output_section->vma
12956 + input_section->output_offset
12957 + rel->r_offset);
12958
12959 /* Put RELOCATION back into the insn. */
12960 {
12961 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12962 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12963 bfd_vma immC = (relocation & 0x00000002) >> 1;
12964
12965 upper_insn = (upper_insn & 0xffe0) | immA;
12966 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12967 }
12968
12969 /* Put the relocated value back in the object file: */
12970 bfd_put_16 (input_bfd, upper_insn, hit_data);
12971 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12972
12973 return bfd_reloc_ok;
12974 }
12975
1889da70
AV		 12976 case R_ARM_THM_BF12:
12977 {
12978 bfd_vma relocation;
12979 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12980 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12981
12982 if (globals->use_rel)
12983 {
12984 bfd_vma immA = (upper_insn & 0x0001);
12985 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12986 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12987 addend = (immA << 12);
12988 addend |= (immB << 2);
12989 addend |= (immC << 1);
12990 addend |= 1;
12991 /* Sign extend. */
12992 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 12993 signed_addend = addend;
1889da70
AV		 12994 }
12995
e6f65e75 12996 relocation = value + signed_addend;
1889da70
AV		 12997 relocation -= (input_section->output_section->vma
12998 + input_section->output_offset
12999 + rel->r_offset);
13000
13001 /* Put RELOCATION back into the insn. */
13002 {
13003 bfd_vma immA = (relocation & 0x00001000) >> 12;
13004 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13005 bfd_vma immC = (relocation & 0x00000002) >> 1;
13006
13007 upper_insn = (upper_insn & 0xfffe) | immA;
13008 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13009 }
13010
13011 /* Put the relocated value back in the object file: */
13012 bfd_put_16 (input_bfd, upper_insn, hit_data);
13013 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13014
13015 return bfd_reloc_ok;
13016 }
13017
1caf72a5
AV		 13018 case R_ARM_THM_BF18:
13019 {
13020 bfd_vma relocation;
13021 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
13022 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
13023
13024 if (globals->use_rel)
13025 {
13026 bfd_vma immA = (upper_insn & 0x007f);
13027 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
13028 bfd_vma immC = (lower_insn & 0x0800) >> 11;
13029 addend = (immA << 12);
13030 addend |= (immB << 2);
13031 addend |= (immC << 1);
13032 addend |= 1;
13033 /* Sign extend. */
13034 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 13035 signed_addend = addend;
1caf72a5
AV		 13036 }
13037
e6f65e75 13038 relocation = value + signed_addend;
1caf72a5
AV		 13039 relocation -= (input_section->output_section->vma
13040 + input_section->output_offset
13041 + rel->r_offset);
13042
13043 /* Put RELOCATION back into the insn. */
13044 {
13045 bfd_vma immA = (relocation & 0x0007f000) >> 12;
13046 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13047 bfd_vma immC = (relocation & 0x00000002) >> 1;
13048
13049 upper_insn = (upper_insn & 0xff80) | immA;
13050 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13051 }
13052
13053 /* Put the relocated value back in the object file: */
13054 bfd_put_16 (input_bfd, upper_insn, hit_data);
13055 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13056
13057 return bfd_reloc_ok;
13058 }
13059
252b5132
RH		 13060 default:
13061 return bfd_reloc_notsupported;
13062 }
13063}
13064
98c1d4aa
NC		 13065/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13066static void
07d6d2b8
AM		 13067arm_add_to_rel (bfd * abfd,
13068 bfd_byte * address,
57e8b36a 13069 reloc_howto_type * howto,
07d6d2b8 13070 bfd_signed_vma increment)
98c1d4aa 13071{
98c1d4aa
NC		 13072 bfd_signed_vma addend;
13073
bd97cb95
DJ		 13074 if (howto->type == R_ARM_THM_CALL
13075 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13076 {
9a5aca8c
AM		 13077 int upper_insn, lower_insn;
13078 int upper, lower;
98c1d4aa 13079
9a5aca8c
AM		 13080 upper_insn = bfd_get_16 (abfd, address);
13081 lower_insn = bfd_get_16 (abfd, address + 2);
13082 upper = upper_insn & 0x7ff;
13083 lower = lower_insn & 0x7ff;
13084
13085 addend = (upper << 12) | (lower << 1);
ddda4409 13086 addend += increment;
9a5aca8c 13087 addend >>= 1;
98c1d4aa 13088
9a5aca8c
AM		 13089 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13090 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13091
dc810e39
AM		 13092 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13093 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13094 }
13095 else
13096 {
07d6d2b8 13097 bfd_vma contents;
9a5aca8c
AM		 13098
13099 contents = bfd_get_32 (abfd, address);
13100
13101 /* Get the (signed) value from the instruction. */
13102 addend = contents & howto->src_mask;
13103 if (addend & ((howto->src_mask + 1) >> 1))
13104 {
13105 bfd_signed_vma mask;
13106
13107 mask = -1;
13108 mask &= ~ howto->src_mask;
13109 addend |= mask;
13110 }
13111
13112 /* Add in the increment, (which is a byte value). */
13113 switch (howto->type)
13114 {
13115 default:
13116 addend += increment;
13117 break;
13118
13119 case R_ARM_PC24:
c6596c5e 13120 case R_ARM_PLT32:
5b5bb741
PB		 13121 case R_ARM_CALL:
13122 case R_ARM_JUMP24:
9a5aca8c 13123 addend <<= howto->size;
dc810e39 13124 addend += increment;
9a5aca8c
AM		 13125
13126 /* Should we check for overflow here ? */
13127
13128 /* Drop any undesired bits. */
13129 addend >>= howto->rightshift;
13130 break;
13131 }
13132
13133 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13134
13135 bfd_put_32 (abfd, contents, address);
ddda4409 13136 }
98c1d4aa 13137}
252b5132 13138
ba93b8ac
DJ		 13139#define IS_ARM_TLS_RELOC(R_TYPE) \
13140 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13141 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13142 || (R_TYPE) == R_ARM_TLS_LDO32 \
13143 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13144 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13145 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13146 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13147 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13148 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13149 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13150 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13151 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13152
13153/* Specific set of relocations for the gnu tls dialect. */
13154#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13155 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13156 || (R_TYPE) == R_ARM_TLS_CALL \
13157 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13158 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13159 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13160
252b5132 13161/* Relocate an ARM ELF section. */
906e58ca 13162
b34976b6 13163static bfd_boolean
07d6d2b8 13164elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13165 struct bfd_link_info * info,
07d6d2b8
AM		 13166 bfd * input_bfd,
13167 asection * input_section,
13168 bfd_byte * contents,
13169 Elf_Internal_Rela * relocs,
13170 Elf_Internal_Sym * local_syms,
13171 asection ** local_sections)
252b5132 13172{
b34976b6
AM		 13173 Elf_Internal_Shdr *symtab_hdr;
13174 struct elf_link_hash_entry **sym_hashes;
13175 Elf_Internal_Rela *rel;
13176 Elf_Internal_Rela *relend;
13177 const char *name;
b32d3aa2 13178 struct elf32_arm_link_hash_table * globals;
252b5132 13179
4e7fd91e 13180 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13181 if (globals == NULL)
13182 return FALSE;
b491616a 13183
0ffa91dd 13184 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13185 sym_hashes = elf_sym_hashes (input_bfd);
13186
13187 rel = relocs;
13188 relend = relocs + input_section->reloc_count;
13189 for (; rel < relend; rel++)
13190 {
07d6d2b8
AM		 13191 int r_type;
13192 reloc_howto_type * howto;
13193 unsigned long r_symndx;
13194 Elf_Internal_Sym * sym;
13195 asection * sec;
252b5132 13196 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13197 bfd_vma relocation;
13198 bfd_reloc_status_type r;
13199 arelent bfd_reloc;
13200 char sym_type;
13201 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13202 char *error_message = NULL;
f21f3fe0 13203
252b5132 13204 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13205 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13206 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13207
ba96a88f 13208 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13209 || r_type == R_ARM_GNU_VTINHERIT)
13210 continue;
252b5132 13211
47aeb64c
NC		 13212 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13213
13214 if (howto == NULL)
13215 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13216
252b5132
RH		 13217 h = NULL;
13218 sym = NULL;
13219 sec = NULL;
9b485d32 13220
252b5132
RH		 13221 if (r_symndx < symtab_hdr->sh_info)
13222 {
13223 sym = local_syms + r_symndx;
ba93b8ac 13224 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13225 sec = local_sections[r_symndx];
ffcb4889
NS		 13226
13227 /* An object file might have a reference to a local
13228 undefined symbol. This is a daft object file, but we
13229 should at least do something about it. V4BX & NONE
13230 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13231 allowed to use the undefined symbol, so allow those.
13232 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13233 if (r_type != R_ARM_V4BX
13234 && r_type != R_ARM_NONE
77b4f08f 13235 && r_symndx != STN_UNDEF
ffcb4889
NS		 13236 && bfd_is_und_section (sec)
13237 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13238 (*info->callbacks->undefined_symbol)
13239 (info, bfd_elf_string_from_elf_section
13240 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13241 input_bfd, input_section,
13242 rel->r_offset, TRUE);
b38cadfb 13243
4e7fd91e 13244 if (globals->use_rel)
f8df10f4 13245 {
4e7fd91e
PB		 13246 relocation = (sec->output_section->vma
13247 + sec->output_offset
13248 + sym->st_value);
0e1862bb 13249 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13250 && (sec->flags & SEC_MERGE)
13251 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13252 {
4e7fd91e
PB		 13253 asection *msec;
13254 bfd_vma addend, value;
13255
39623e12 13256 switch (r_type)
4e7fd91e 13257 {
39623e12
PB		 13258 case R_ARM_MOVW_ABS_NC:
13259 case R_ARM_MOVT_ABS:
13260 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13261 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13262 addend = (addend ^ 0x8000) - 0x8000;
13263 break;
f8df10f4 13264
39623e12
PB		 13265 case R_ARM_THM_MOVW_ABS_NC:
13266 case R_ARM_THM_MOVT_ABS:
13267 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13268 << 16;
13269 value |= bfd_get_16 (input_bfd,
13270 contents + rel->r_offset + 2);
13271 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13272 | ((value & 0x04000000) >> 15);
13273 addend = (addend ^ 0x8000) - 0x8000;
13274 break;
f8df10f4 13275
39623e12
PB		 13276 default:
13277 if (howto->rightshift
13278 || (howto->src_mask & (howto->src_mask + 1)))
13279 {
4eca0228 13280 _bfd_error_handler
695344c0 13281 /* xgettext:c-format */
2dcf00ce
AM		 13282 (_("%pB(%pA+%#" PRIx64 "): "
13283 "%s relocation against SEC_MERGE section"),
39623e12 13284 input_bfd, input_section,
2dcf00ce 13285 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13286 return FALSE;
13287 }
13288
13289 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13290
13291 /* Get the (signed) value from the instruction. */
13292 addend = value & howto->src_mask;
13293 if (addend & ((howto->src_mask + 1) >> 1))
13294 {
13295 bfd_signed_vma mask;
13296
13297 mask = -1;
13298 mask &= ~ howto->src_mask;
13299 addend |= mask;
13300 }
13301 break;
4e7fd91e 13302 }
39623e12 13303
4e7fd91e
PB		 13304 msec = sec;
13305 addend =
13306 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13307 - relocation;
13308 addend += msec->output_section->vma + msec->output_offset;
39623e12 13309
cc643b88 13310 /* Cases here must match those in the preceding
39623e12
PB		 13311 switch statement. */
13312 switch (r_type)
13313 {
13314 case R_ARM_MOVW_ABS_NC:
13315 case R_ARM_MOVT_ABS:
13316 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13317 | (addend & 0xfff);
13318 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13319 break;
13320
13321 case R_ARM_THM_MOVW_ABS_NC:
13322 case R_ARM_THM_MOVT_ABS:
13323 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13324 | (addend & 0xff) | ((addend & 0x0800) << 15);
13325 bfd_put_16 (input_bfd, value >> 16,
13326 contents + rel->r_offset);
13327 bfd_put_16 (input_bfd, value,
13328 contents + rel->r_offset + 2);
13329 break;
13330
13331 default:
13332 value = (value & ~ howto->dst_mask)
13333 | (addend & howto->dst_mask);
13334 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13335 break;
13336 }
f8df10f4 13337 }
f8df10f4 13338 }
4e7fd91e
PB		 13339 else
13340 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13341 }
13342 else
13343 {
62d887d4 13344 bfd_boolean warned, ignored;
560e09e9 13345
b2a8e766
AM		 13346 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13347 r_symndx, symtab_hdr, sym_hashes,
13348 h, sec, relocation,
62d887d4 13349 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13350
13351 sym_type = h->type;
252b5132
RH		 13352 }
13353
dbaa2011 13354 if (sec != NULL && discarded_section (sec))
e4067dbb 13355 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13356 rel, 1, relend, howto, 0, contents);
ab96bf03 13357
0e1862bb 13358 if (bfd_link_relocatable (info))
ab96bf03
AM		 13359 {
13360 /* This is a relocatable link. We don't have to change
13361 anything, unless the reloc is against a section symbol,
13362 in which case we have to adjust according to where the
13363 section symbol winds up in the output section. */
13364 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13365 {
13366 if (globals->use_rel)
13367 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13368 howto, (bfd_signed_vma) sec->output_offset);
13369 else
13370 rel->r_addend += sec->output_offset;
13371 }
13372 continue;
13373 }
13374
252b5132
RH		 13375 if (h != NULL)
13376 name = h->root.root.string;
13377 else
13378 {
13379 name = (bfd_elf_string_from_elf_section
13380 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13381 if (name == NULL || *name == '\0')
fd361982 13382 name = bfd_section_name (sec);
252b5132 13383 }
f21f3fe0 13384
cf35638d 13385 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13386 && r_type != R_ARM_NONE
13387 && (h == NULL
13388 || h->root.type == bfd_link_hash_defined
13389 || h->root.type == bfd_link_hash_defweak)
13390 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13391 {
4eca0228 13392 _bfd_error_handler
ba93b8ac 13393 ((sym_type == STT_TLS
695344c0 13394 /* xgettext:c-format */
2dcf00ce 13395 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13396 /* xgettext:c-format */
2dcf00ce 13397 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13398 input_bfd,
13399 input_section,
2dcf00ce 13400 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13401 howto->name,
13402 name);
13403 }
13404
0855e32b 13405 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13406 done, i.e., the relaxation produced the final output we want,
13407 and we won't let anybody mess with it. Also, we have to do
13408 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13409 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13410 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13411 || (IS_ARM_TLS_GNU_RELOC (r_type)
13412 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13413 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13414 & GOT_TLS_GDESC)))
13415 {
13416 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13417 contents, rel, h == NULL);
13418 /* This may have been marked unresolved because it came from
13419 a shared library. But we've just dealt with that. */
13420 unresolved_reloc = 0;
13421 }
13422 else
13423 r = bfd_reloc_continue;
b38cadfb 13424
39d911fc
TP		 13425 if (r == bfd_reloc_continue)
13426 {
13427 unsigned char branch_type =
13428 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13429 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13430
13431 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13432 input_section, contents, rel,
13433 relocation, info, sec, name,
13434 sym_type, branch_type, h,
13435 &unresolved_reloc,
13436 &error_message);
13437 }
0945cdfd
DJ		 13438
13439 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13440 because such sections are not SEC_ALLOC and thus ld.so will
13441 not process them. */
13442 if (unresolved_reloc
99059e56
RM		 13443 && !((input_section->flags & SEC_DEBUGGING) != 0
13444 && h->def_dynamic)
1d5316ab
AM		 13445 && _bfd_elf_section_offset (output_bfd, info, input_section,
13446 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13447 {
4eca0228 13448 _bfd_error_handler
695344c0 13449 /* xgettext:c-format */
2dcf00ce
AM		 13450 (_("%pB(%pA+%#" PRIx64 "): "
13451 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13452 input_bfd,
13453 input_section,
2dcf00ce 13454 (uint64_t) rel->r_offset,
843fe662
L		 13455 howto->name,
13456 h->root.root.string);
0945cdfd
DJ		 13457 return FALSE;
13458 }
252b5132
RH		 13459
13460 if (r != bfd_reloc_ok)
13461 {
252b5132
RH		 13462 switch (r)
13463 {
13464 case bfd_reloc_overflow:
cf919dfd
PB		 13465 /* If the overflowing reloc was to an undefined symbol,
13466 we have already printed one error message and there
13467 is no point complaining again. */
1a72702b
AM		 13468 if (!h || h->root.type != bfd_link_hash_undefined)
13469 (*info->callbacks->reloc_overflow)
13470 (info, (h ? &h->root : NULL), name, howto->name,
13471 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13472 break;
13473
13474 case bfd_reloc_undefined:
1a72702b
AM		 13475 (*info->callbacks->undefined_symbol)
13476 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13477 break;
13478
13479 case bfd_reloc_outofrange:
f2a9dd69 13480 error_message = _("out of range");
252b5132
RH		 13481 goto common_error;
13482
13483 case bfd_reloc_notsupported:
f2a9dd69 13484 error_message = _("unsupported relocation");
252b5132
RH		 13485 goto common_error;
13486
13487 case bfd_reloc_dangerous:
f2a9dd69 13488 /* error_message should already be set. */
252b5132
RH		 13489 goto common_error;
13490
13491 default:
f2a9dd69 13492 error_message = _("unknown error");
8029a119 13493 /* Fall through. */
252b5132
RH		 13494
13495 common_error:
f2a9dd69 13496 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13497 (*info->callbacks->reloc_dangerous)
13498 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13499 break;
13500 }
13501 }
13502 }
13503
b34976b6 13504 return TRUE;
252b5132
RH		 13505}
13506
91d6fa6a 13507/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13508 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13509 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13510 maintaining that condition). */
13511
13512static void
13513add_unwind_table_edit (arm_unwind_table_edit **head,
13514 arm_unwind_table_edit **tail,
13515 arm_unwind_edit_type type,
13516 asection *linked_section,
91d6fa6a 13517 unsigned int tindex)
2468f9c9 13518{
21d799b5
NC		 13519 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13520 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13521
2468f9c9
PB		 13522 new_edit->type = type;
13523 new_edit->linked_section = linked_section;
91d6fa6a 13524 new_edit->index = tindex;
b38cadfb 13525
91d6fa6a 13526 if (tindex > 0)
2468f9c9
PB		 13527 {
13528 new_edit->next = NULL;
13529
13530 if (*tail)
13531 (*tail)->next = new_edit;
13532
13533 (*tail) = new_edit;
13534
13535 if (!*head)
13536 (*head) = new_edit;
13537 }
13538 else
13539 {
13540 new_edit->next = *head;
13541
13542 if (!*tail)
13543 *tail = new_edit;
13544
13545 *head = new_edit;
13546 }
13547}
13548
13549static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13550
13551/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13552static void
13553adjust_exidx_size(asection *exidx_sec, int adjust)
13554{
13555 asection *out_sec;
13556
13557 if (!exidx_sec->rawsize)
13558 exidx_sec->rawsize = exidx_sec->size;
13559
fd361982 13560 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
2468f9c9
PB		 13561 out_sec = exidx_sec->output_section;
13562 /* Adjust size of output section. */
fd361982 13563 bfd_set_section_size (out_sec, out_sec->size +adjust);
2468f9c9
PB		 13564}
13565
13566/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13567static void
13568insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13569{
13570 struct _arm_elf_section_data *exidx_arm_data;
13571
13572 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13573 add_unwind_table_edit (
13574 &exidx_arm_data->u.exidx.unwind_edit_list,
13575 &exidx_arm_data->u.exidx.unwind_edit_tail,
13576 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13577
491d01d3
YU		 13578 exidx_arm_data->additional_reloc_count++;
13579
2468f9c9
PB		 13580 adjust_exidx_size(exidx_sec, 8);
13581}
13582
13583/* Scan .ARM.exidx tables, and create a list describing edits which should be
13584 made to those tables, such that:
b38cadfb 13585
2468f9c9
PB		 13586 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13587 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13588 codes which have been inlined into the index).
2468f9c9 13589
85fdf906
AH		 13590 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13591
2468f9c9 13592 The edits are applied when the tables are written
b38cadfb 13593 (in elf32_arm_write_section). */
2468f9c9
PB		 13594
13595bfd_boolean
13596elf32_arm_fix_exidx_coverage (asection **text_section_order,
13597 unsigned int num_text_sections,
85fdf906
AH		 13598 struct bfd_link_info *info,
13599 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13600{
13601 bfd *inp;
13602 unsigned int last_second_word = 0, i;
13603 asection *last_exidx_sec = NULL;
13604 asection *last_text_sec = NULL;
13605 int last_unwind_type = -1;
13606
13607 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13608 text sections. */
c72f2fb2 13609 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13610 {
13611 asection *sec;
b38cadfb 13612
2468f9c9 13613 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13614 {
2468f9c9
PB		 13615 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13616 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13617
dec9d5df 13618 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13619 continue;
b38cadfb 13620
2468f9c9
PB		 13621 if (elf_sec->linked_to)
13622 {
13623 Elf_Internal_Shdr *linked_hdr
99059e56 13624 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13625 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13626 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13627
13628 if (linked_sec_arm_data == NULL)
99059e56 13629 continue;
2468f9c9
PB		 13630
13631 /* Link this .ARM.exidx section back from the text section it
99059e56 13632 describes. */
2468f9c9
PB		 13633 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13634 }
13635 }
13636 }
13637
13638 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13639 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13640 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13641
13642 for (i = 0; i < num_text_sections; i++)
13643 {
13644 asection *sec = text_section_order[i];
13645 asection *exidx_sec;
13646 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13647 struct _arm_elf_section_data *exidx_arm_data;
13648 bfd_byte *contents = NULL;
13649 int deleted_exidx_bytes = 0;
13650 bfd_vma j;
13651 arm_unwind_table_edit *unwind_edit_head = NULL;
13652 arm_unwind_table_edit *unwind_edit_tail = NULL;
13653 Elf_Internal_Shdr *hdr;
13654 bfd *ibfd;
13655
13656 if (arm_data == NULL)
99059e56 13657 continue;
2468f9c9
PB		 13658
13659 exidx_sec = arm_data->u.text.arm_exidx_sec;
13660 if (exidx_sec == NULL)
13661 {
13662 /* Section has no unwind data. */
13663 if (last_unwind_type == 0 || !last_exidx_sec)
13664 continue;
13665
13666 /* Ignore zero sized sections. */
13667 if (sec->size == 0)
13668 continue;
13669
13670 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13671 last_unwind_type = 0;
13672 continue;
13673 }
13674
22a8f80e
PB		 13675 /* Skip /DISCARD/ sections. */
13676 if (bfd_is_abs_section (exidx_sec->output_section))
13677 continue;
13678
2468f9c9
PB		 13679 hdr = &elf_section_data (exidx_sec)->this_hdr;
13680 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13681 continue;
b38cadfb 13682
2468f9c9
PB		 13683 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13684 if (exidx_arm_data == NULL)
99059e56 13685 continue;
b38cadfb 13686
2468f9c9 13687 ibfd = exidx_sec->owner;
b38cadfb 13688
2468f9c9
PB		 13689 if (hdr->contents != NULL)
13690 contents = hdr->contents;
13691 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13692 /* An error? */
13693 continue;
13694
ac06903d
YU		 13695 if (last_unwind_type > 0)
13696 {
13697 unsigned int first_word = bfd_get_32 (ibfd, contents);
13698 /* Add cantunwind if first unwind item does not match section
13699 start. */
13700 if (first_word != sec->vma)
13701 {
13702 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13703 last_unwind_type = 0;
13704 }
13705 }
13706
2468f9c9
PB		 13707 for (j = 0; j < hdr->sh_size; j += 8)
13708 {
13709 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13710 int unwind_type;
13711 int elide = 0;
13712
13713 /* An EXIDX_CANTUNWIND entry. */
13714 if (second_word == 1)
13715 {
13716 if (last_unwind_type == 0)
13717 elide = 1;
13718 unwind_type = 0;
13719 }
13720 /* Inlined unwinding data. Merge if equal to previous. */
13721 else if ((second_word & 0x80000000) != 0)
13722 {
85fdf906
AH		 13723 if (merge_exidx_entries
13724 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13725 elide = 1;
13726 unwind_type = 1;
13727 last_second_word = second_word;
13728 }
13729 /* Normal table entry. In theory we could merge these too,
13730 but duplicate entries are likely to be much less common. */
13731 else
13732 unwind_type = 2;
13733
491d01d3 13734 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13735 {
13736 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13737 DELETE_EXIDX_ENTRY, NULL, j / 8);
13738
13739 deleted_exidx_bytes += 8;
13740 }
13741
13742 last_unwind_type = unwind_type;
13743 }
13744
13745 /* Free contents if we allocated it ourselves. */
13746 if (contents != hdr->contents)
99059e56 13747 free (contents);
2468f9c9
PB		 13748
13749 /* Record edits to be applied later (in elf32_arm_write_section). */
13750 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13751 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13752
2468f9c9
PB		 13753 if (deleted_exidx_bytes > 0)
13754 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13755
13756 last_exidx_sec = exidx_sec;
13757 last_text_sec = sec;
13758 }
13759
13760 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13761 if (!bfd_link_relocatable (info) && last_exidx_sec
13762 && last_unwind_type != 0)
2468f9c9
PB		 13763 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13764
13765 return TRUE;
13766}
13767
3e6b1042
DJ		 13768static bfd_boolean
13769elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13770 bfd *ibfd, const char *name)
13771{
13772 asection *sec, *osec;
13773
3d4d4302 13774 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13775 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13776 return TRUE;
13777
13778 osec = sec->output_section;
13779 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13780 return TRUE;
13781
13782 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13783 sec->output_offset, sec->size))
13784 return FALSE;
13785
13786 return TRUE;
13787}
13788
13789static bfd_boolean
13790elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13791{
13792 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13793 asection *sec, *osec;
3e6b1042 13794
4dfe6ac6
NC		 13795 if (globals == NULL)
13796 return FALSE;
13797
3e6b1042
DJ		 13798 /* Invoke the regular ELF backend linker to do all the work. */
13799 if (!bfd_elf_final_link (abfd, info))
13800 return FALSE;
13801
fe33d2fa
CL		 13802 /* Process stub sections (eg BE8 encoding, ...). */
13803 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13804 unsigned int i;
cdb21a0a
NS		 13805 for (i=0; i<htab->top_id; i++)
13806 {
13807 sec = htab->stub_group[i].stub_sec;
13808 /* Only process it once, in its link_sec slot. */
13809 if (sec && i == htab->stub_group[i].link_sec->id)
13810 {
13811 osec = sec->output_section;
13812 elf32_arm_write_section (abfd, info, sec, sec->contents);
13813 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13814 sec->output_offset, sec->size))
13815 return FALSE;
13816 }
fe33d2fa 13817 }
fe33d2fa 13818
3e6b1042
DJ		 13819 /* Write out any glue sections now that we have created all the
13820 stubs. */
13821 if (globals->bfd_of_glue_owner != NULL)
13822 {
13823 if (! elf32_arm_output_glue_section (info, abfd,
13824 globals->bfd_of_glue_owner,
13825 ARM2THUMB_GLUE_SECTION_NAME))
13826 return FALSE;
13827
13828 if (! elf32_arm_output_glue_section (info, abfd,
13829 globals->bfd_of_glue_owner,
13830 THUMB2ARM_GLUE_SECTION_NAME))
13831 return FALSE;
13832
13833 if (! elf32_arm_output_glue_section (info, abfd,
13834 globals->bfd_of_glue_owner,
13835 VFP11_ERRATUM_VENEER_SECTION_NAME))
13836 return FALSE;
13837
a504d23a
LA		 13838 if (! elf32_arm_output_glue_section (info, abfd,
13839 globals->bfd_of_glue_owner,
13840 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13841 return FALSE;
13842
3e6b1042
DJ		 13843 if (! elf32_arm_output_glue_section (info, abfd,
13844 globals->bfd_of_glue_owner,
13845 ARM_BX_GLUE_SECTION_NAME))
13846 return FALSE;
13847 }
13848
13849 return TRUE;
13850}
13851
5968a7b8
NC		 13852/* Return a best guess for the machine number based on the attributes. */
13853
13854static unsigned int
13855bfd_arm_get_mach_from_attributes (bfd * abfd)
13856{
13857 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13858
13859 switch (arch)
13860 {
c0c468d5 13861 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13862 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13863 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13864 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13865
13866 case TAG_CPU_ARCH_V5TE:
13867 {
13868 char * name;
13869
13870 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13871 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13872
13873 if (name)
13874 {
13875 if (strcmp (name, "IWMMXT2") == 0)
13876 return bfd_mach_arm_iWMMXt2;
13877
13878 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13879 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13880
13881 if (strcmp (name, "XSCALE") == 0)
13882 {
13883 int wmmx;
13884
13885 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13886 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13887 switch (wmmx)
13888 {
13889 case 1: return bfd_mach_arm_iWMMXt;
13890 case 2: return bfd_mach_arm_iWMMXt2;
13891 default: return bfd_mach_arm_XScale;
13892 }
13893 }
5968a7b8
NC		 13894 }
13895
13896 return bfd_mach_arm_5TE;
13897 }
13898
c0c468d5
TP		 13899 case TAG_CPU_ARCH_V5TEJ:
13900 return bfd_mach_arm_5TEJ;
13901 case TAG_CPU_ARCH_V6:
13902 return bfd_mach_arm_6;
13903 case TAG_CPU_ARCH_V6KZ:
13904 return bfd_mach_arm_6KZ;
13905 case TAG_CPU_ARCH_V6T2:
13906 return bfd_mach_arm_6T2;
13907 case TAG_CPU_ARCH_V6K:
13908 return bfd_mach_arm_6K;
13909 case TAG_CPU_ARCH_V7:
13910 return bfd_mach_arm_7;
13911 case TAG_CPU_ARCH_V6_M:
13912 return bfd_mach_arm_6M;
13913 case TAG_CPU_ARCH_V6S_M:
13914 return bfd_mach_arm_6SM;
13915 case TAG_CPU_ARCH_V7E_M:
13916 return bfd_mach_arm_7EM;
13917 case TAG_CPU_ARCH_V8:
13918 return bfd_mach_arm_8;
13919 case TAG_CPU_ARCH_V8R:
13920 return bfd_mach_arm_8R;
13921 case TAG_CPU_ARCH_V8M_BASE:
13922 return bfd_mach_arm_8M_BASE;
13923 case TAG_CPU_ARCH_V8M_MAIN:
13924 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13925 case TAG_CPU_ARCH_V8_1M_MAIN:
13926 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13927
5968a7b8 13928 default:
c0c468d5
TP		 13929 /* Force entry to be added for any new known Tag_CPU_arch value. */
13930 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13931
13932 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13933 return bfd_mach_arm_unknown;
13934 }
13935}
13936
c178919b
NC		 13937/* Set the right machine number. */
13938
13939static bfd_boolean
57e8b36a 13940elf32_arm_object_p (bfd *abfd)
c178919b 13941{
5a6c6817 13942 unsigned int mach;
57e8b36a 13943
5a6c6817 13944 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13945
5968a7b8
NC		 13946 if (mach == bfd_mach_arm_unknown)
13947 {
13948 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13949 mach = bfd_mach_arm_ep9312;
13950 else
13951 mach = bfd_arm_get_mach_from_attributes (abfd);
13952 }
c178919b 13953
5968a7b8 13954 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13955 return TRUE;
13956}
13957
fc830a83 13958/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13959
b34976b6 13960static bfd_boolean
57e8b36a 13961elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13962{
13963 if (elf_flags_init (abfd)
13964 && elf_elfheader (abfd)->e_flags != flags)
13965 {
fc830a83
NC		 13966 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13967 {
fd2ec330 13968 if (flags & EF_ARM_INTERWORK)
4eca0228 13969 _bfd_error_handler
90b6238f 13970 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13971 abfd);
fc830a83 13972 else
d003868e 13973 _bfd_error_handler
90b6238f 13974 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13975 abfd);
fc830a83 13976 }
252b5132
RH		 13977 }
13978 else
13979 {
13980 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13981 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13982 }
13983
b34976b6 13984 return TRUE;
252b5132
RH		 13985}
13986
fc830a83 13987/* Copy backend specific data from one object module to another. */
9b485d32 13988
b34976b6 13989static bfd_boolean
57e8b36a 13990elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13991{
13992 flagword in_flags;
13993 flagword out_flags;
13994
0ffa91dd 13995 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13996 return TRUE;
252b5132 13997
fc830a83 13998 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13999 out_flags = elf_elfheader (obfd)->e_flags;
14000
fc830a83
NC		 14001 if (elf_flags_init (obfd)
14002 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
14003 && in_flags != out_flags)
252b5132 14004 {
252b5132 14005 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 14006 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 14007 return FALSE;
252b5132
RH		 14008
14009 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 14010 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 14011 return FALSE;
252b5132
RH		 14012
14013 /* If the src and dest have different interworking flags
99059e56 14014 then turn off the interworking bit. */
fd2ec330 14015 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 14016 {
fd2ec330 14017 if (out_flags & EF_ARM_INTERWORK)
d003868e 14018 _bfd_error_handler
90b6238f 14019 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 14020 obfd, ibfd);
252b5132 14021
fd2ec330 14022 in_flags &= ~EF_ARM_INTERWORK;
252b5132 14023 }
1006ba19
PB		 14024
14025 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 14026 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
14027 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 14028 }
14029
14030 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 14031 elf_flags_init (obfd) = TRUE;
252b5132 14032
e2349352 14033 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 14034}
14035
14036/* Values for Tag_ABI_PCS_R9_use. */
14037enum
14038{
14039 AEABI_R9_V6,
14040 AEABI_R9_SB,
14041 AEABI_R9_TLS,
14042 AEABI_R9_unused
14043};
14044
14045/* Values for Tag_ABI_PCS_RW_data. */
14046enum
14047{
14048 AEABI_PCS_RW_data_absolute,
14049 AEABI_PCS_RW_data_PCrel,
14050 AEABI_PCS_RW_data_SBrel,
14051 AEABI_PCS_RW_data_unused
14052};
14053
14054/* Values for Tag_ABI_enum_size. */
14055enum
14056{
14057 AEABI_enum_unused,
14058 AEABI_enum_short,
14059 AEABI_enum_wide,
14060 AEABI_enum_forced_wide
14061};
14062
104d59d1
JM		 14063/* Determine whether an object attribute tag takes an integer, a
14064 string or both. */
906e58ca 14065
104d59d1
JM		 14066static int
14067elf32_arm_obj_attrs_arg_type (int tag)
14068{
14069 if (tag == Tag_compatibility)
3483fe2e 14070 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14071 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14072 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14073 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14074 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14075 else if (tag < 32)
3483fe2e 14076 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14077 else
3483fe2e 14078 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14079}
14080
5aa6ff7c
AS		 14081/* The ABI defines that Tag_conformance should be emitted first, and that
14082 Tag_nodefaults should be second (if either is defined). This sets those
14083 two positions, and bumps up the position of all the remaining tags to
14084 compensate. */
14085static int
14086elf32_arm_obj_attrs_order (int num)
14087{
3de4a297 14088 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14089 return Tag_conformance;
3de4a297 14090 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14091 return Tag_nodefaults;
14092 if ((num - 2) < Tag_nodefaults)
14093 return num - 2;
14094 if ((num - 1) < Tag_conformance)
14095 return num - 1;
14096 return num;
14097}
14098
e8b36cd1
JM		 14099/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14100static bfd_boolean
14101elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14102{
14103 if ((tag & 127) < 64)
14104 {
14105 _bfd_error_handler
90b6238f 14106 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14107 abfd, tag);
14108 bfd_set_error (bfd_error_bad_value);
14109 return FALSE;
14110 }
14111 else
14112 {
14113 _bfd_error_handler
90b6238f 14114 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14115 abfd, tag);
14116 return TRUE;
14117 }
14118}
14119
91e22acd
AS		 14120/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14121 Returns -1 if no architecture could be read. */
14122
14123static int
14124get_secondary_compatible_arch (bfd *abfd)
14125{
14126 obj_attribute *attr =
14127 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14128
14129 /* Note: the tag and its argument below are uleb128 values, though
14130 currently-defined values fit in one byte for each. */
14131 if (attr->s
14132 && attr->s[0] == Tag_CPU_arch
14133 && (attr->s[1] & 128) != 128
14134 && attr->s[2] == 0)
14135 return attr->s[1];
14136
14137 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14138 return -1;
14139}
14140
14141/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14142 The tag is removed if ARCH is -1. */
14143
8e79c3df 14144static void
91e22acd 14145set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14146{
91e22acd
AS		 14147 obj_attribute *attr =
14148 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14149
91e22acd
AS		 14150 if (arch == -1)
14151 {
14152 attr->s = NULL;
14153 return;
8e79c3df 14154 }
91e22acd
AS		 14155
14156 /* Note: the tag and its argument below are uleb128 values, though
14157 currently-defined values fit in one byte for each. */
14158 if (!attr->s)
21d799b5 14159 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14160 attr->s[0] = Tag_CPU_arch;
14161 attr->s[1] = arch;
14162 attr->s[2] = '\0';
8e79c3df
CM		 14163}
14164
91e22acd
AS		 14165/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14166 into account. */
14167
14168static int
14169tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14170 int newtag, int secondary_compat)
8e79c3df 14171{
91e22acd
AS		 14172#define T(X) TAG_CPU_ARCH_##X
14173 int tagl, tagh, result;
14174 const int v6t2[] =
14175 {
14176 T(V6T2), /* PRE_V4. */
14177 T(V6T2), /* V4. */
14178 T(V6T2), /* V4T. */
14179 T(V6T2), /* V5T. */
14180 T(V6T2), /* V5TE. */
14181 T(V6T2), /* V5TEJ. */
14182 T(V6T2), /* V6. */
14183 T(V7), /* V6KZ. */
14184 T(V6T2) /* V6T2. */
14185 };
14186 const int v6k[] =
14187 {
14188 T(V6K), /* PRE_V4. */
14189 T(V6K), /* V4. */
14190 T(V6K), /* V4T. */
14191 T(V6K), /* V5T. */
14192 T(V6K), /* V5TE. */
14193 T(V6K), /* V5TEJ. */
14194 T(V6K), /* V6. */
14195 T(V6KZ), /* V6KZ. */
14196 T(V7), /* V6T2. */
14197 T(V6K) /* V6K. */
14198 };
14199 const int v7[] =
14200 {
14201 T(V7), /* PRE_V4. */
14202 T(V7), /* V4. */
14203 T(V7), /* V4T. */
14204 T(V7), /* V5T. */
14205 T(V7), /* V5TE. */
14206 T(V7), /* V5TEJ. */
14207 T(V7), /* V6. */
14208 T(V7), /* V6KZ. */
14209 T(V7), /* V6T2. */
14210 T(V7), /* V6K. */
14211 T(V7) /* V7. */
14212 };
14213 const int v6_m[] =
14214 {
07d6d2b8
AM		 14215 -1, /* PRE_V4. */
14216 -1, /* V4. */
91e22acd
AS		 14217 T(V6K), /* V4T. */
14218 T(V6K), /* V5T. */
14219 T(V6K), /* V5TE. */
14220 T(V6K), /* V5TEJ. */
14221 T(V6K), /* V6. */
14222 T(V6KZ), /* V6KZ. */
14223 T(V7), /* V6T2. */
14224 T(V6K), /* V6K. */
14225 T(V7), /* V7. */
14226 T(V6_M) /* V6_M. */
14227 };
14228 const int v6s_m[] =
14229 {
07d6d2b8
AM		 14230 -1, /* PRE_V4. */
14231 -1, /* V4. */
91e22acd
AS		 14232 T(V6K), /* V4T. */
14233 T(V6K), /* V5T. */
14234 T(V6K), /* V5TE. */
14235 T(V6K), /* V5TEJ. */
14236 T(V6K), /* V6. */
14237 T(V6KZ), /* V6KZ. */
14238 T(V7), /* V6T2. */
14239 T(V6K), /* V6K. */
14240 T(V7), /* V7. */
14241 T(V6S_M), /* V6_M. */
14242 T(V6S_M) /* V6S_M. */
14243 };
9e3c6df6
PB		 14244 const int v7e_m[] =
14245 {
07d6d2b8
AM		 14246 -1, /* PRE_V4. */
14247 -1, /* V4. */
9e3c6df6
PB		 14248 T(V7E_M), /* V4T. */
14249 T(V7E_M), /* V5T. */
14250 T(V7E_M), /* V5TE. */
14251 T(V7E_M), /* V5TEJ. */
14252 T(V7E_M), /* V6. */
14253 T(V7E_M), /* V6KZ. */
14254 T(V7E_M), /* V6T2. */
14255 T(V7E_M), /* V6K. */
14256 T(V7E_M), /* V7. */
14257 T(V7E_M), /* V6_M. */
14258 T(V7E_M), /* V6S_M. */
14259 T(V7E_M) /* V7E_M. */
14260 };
bca38921
MGD		 14261 const int v8[] =
14262 {
14263 T(V8), /* PRE_V4. */
14264 T(V8), /* V4. */
14265 T(V8), /* V4T. */
14266 T(V8), /* V5T. */
14267 T(V8), /* V5TE. */
14268 T(V8), /* V5TEJ. */
14269 T(V8), /* V6. */
14270 T(V8), /* V6KZ. */
14271 T(V8), /* V6T2. */
14272 T(V8), /* V6K. */
14273 T(V8), /* V7. */
14274 T(V8), /* V6_M. */
14275 T(V8), /* V6S_M. */
14276 T(V8), /* V7E_M. */
14277 T(V8) /* V8. */
14278 };
bff0500d
TP		 14279 const int v8r[] =
14280 {
14281 T(V8R), /* PRE_V4. */
14282 T(V8R), /* V4. */
14283 T(V8R), /* V4T. */
14284 T(V8R), /* V5T. */
14285 T(V8R), /* V5TE. */
14286 T(V8R), /* V5TEJ. */
14287 T(V8R), /* V6. */
14288 T(V8R), /* V6KZ. */
14289 T(V8R), /* V6T2. */
14290 T(V8R), /* V6K. */
14291 T(V8R), /* V7. */
14292 T(V8R), /* V6_M. */
14293 T(V8R), /* V6S_M. */
14294 T(V8R), /* V7E_M. */
14295 T(V8), /* V8. */
14296 T(V8R), /* V8R. */
14297 };
2fd158eb
TP		 14298 const int v8m_baseline[] =
14299 {
14300 -1, /* PRE_V4. */
14301 -1, /* V4. */
14302 -1, /* V4T. */
14303 -1, /* V5T. */
14304 -1, /* V5TE. */
14305 -1, /* V5TEJ. */
14306 -1, /* V6. */
14307 -1, /* V6KZ. */
14308 -1, /* V6T2. */
14309 -1, /* V6K. */
14310 -1, /* V7. */
14311 T(V8M_BASE), /* V6_M. */
14312 T(V8M_BASE), /* V6S_M. */
14313 -1, /* V7E_M. */
14314 -1, /* V8. */
bff0500d 14315 -1, /* V8R. */
2fd158eb
TP		 14316 T(V8M_BASE) /* V8-M BASELINE. */
14317 };
14318 const int v8m_mainline[] =
14319 {
14320 -1, /* PRE_V4. */
14321 -1, /* V4. */
14322 -1, /* V4T. */
14323 -1, /* V5T. */
14324 -1, /* V5TE. */
14325 -1, /* V5TEJ. */
14326 -1, /* V6. */
14327 -1, /* V6KZ. */
14328 -1, /* V6T2. */
14329 -1, /* V6K. */
14330 T(V8M_MAIN), /* V7. */
14331 T(V8M_MAIN), /* V6_M. */
14332 T(V8M_MAIN), /* V6S_M. */
14333 T(V8M_MAIN), /* V7E_M. */
14334 -1, /* V8. */
bff0500d 14335 -1, /* V8R. */
2fd158eb
TP		 14336 T(V8M_MAIN), /* V8-M BASELINE. */
14337 T(V8M_MAIN) /* V8-M MAINLINE. */
14338 };
031254f2
AV		 14339 const int v8_1m_mainline[] =
14340 {
14341 -1, /* PRE_V4. */
14342 -1, /* V4. */
14343 -1, /* V4T. */
14344 -1, /* V5T. */
14345 -1, /* V5TE. */
14346 -1, /* V5TEJ. */
14347 -1, /* V6. */
14348 -1, /* V6KZ. */
14349 -1, /* V6T2. */
14350 -1, /* V6K. */
14351 T(V8_1M_MAIN), /* V7. */
14352 T(V8_1M_MAIN), /* V6_M. */
14353 T(V8_1M_MAIN), /* V6S_M. */
14354 T(V8_1M_MAIN), /* V7E_M. */
14355 -1, /* V8. */
14356 -1, /* V8R. */
14357 T(V8_1M_MAIN), /* V8-M BASELINE. */
14358 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14359 -1, /* Unused (18). */
14360 -1, /* Unused (19). */
14361 -1, /* Unused (20). */
14362 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14363 };
91e22acd
AS		 14364 const int v4t_plus_v6_m[] =
14365 {
14366 -1, /* PRE_V4. */
14367 -1, /* V4. */
14368 T(V4T), /* V4T. */
14369 T(V5T), /* V5T. */
14370 T(V5TE), /* V5TE. */
14371 T(V5TEJ), /* V5TEJ. */
14372 T(V6), /* V6. */
14373 T(V6KZ), /* V6KZ. */
14374 T(V6T2), /* V6T2. */
14375 T(V6K), /* V6K. */
14376 T(V7), /* V7. */
14377 T(V6_M), /* V6_M. */
14378 T(V6S_M), /* V6S_M. */
9e3c6df6 14379 T(V7E_M), /* V7E_M. */
bca38921 14380 T(V8), /* V8. */
bff0500d 14381 -1, /* V8R. */
2fd158eb
TP		 14382 T(V8M_BASE), /* V8-M BASELINE. */
14383 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14384 -1, /* Unused (18). */
14385 -1, /* Unused (19). */
14386 -1, /* Unused (20). */
14387 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14388 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14389 };
14390 const int *comb[] =
14391 {
14392 v6t2,
14393 v6k,
14394 v7,
14395 v6_m,
14396 v6s_m,
9e3c6df6 14397 v7e_m,
bca38921 14398 v8,
bff0500d 14399 v8r,
2fd158eb
TP		 14400 v8m_baseline,
14401 v8m_mainline,
031254f2
AV		 14402 NULL,
14403 NULL,
14404 NULL,
14405 v8_1m_mainline,
91e22acd
AS		 14406 /* Pseudo-architecture. */
14407 v4t_plus_v6_m
14408 };
14409
14410 /* Check we've not got a higher architecture than we know about. */
14411
9e3c6df6 14412 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14413 {
90b6238f 14414 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14415 return -1;
14416 }
14417
14418 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14419
14420 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14421 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14422 oldtag = T(V4T_PLUS_V6_M);
14423
14424 /* And override the new tag if we have a Tag_also_compatible_with on the
14425 input. */
14426
14427 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14428 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14429 newtag = T(V4T_PLUS_V6_M);
14430
14431 tagl = (oldtag < newtag) ? oldtag : newtag;
14432 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14433
14434 /* Architectures before V6KZ add features monotonically. */
14435 if (tagh <= TAG_CPU_ARCH_V6KZ)
14436 return result;
14437
4ed7ed8d 14438 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14439
14440 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14441 as the canonical version. */
14442 if (result == T(V4T_PLUS_V6_M))
14443 {
14444 result = T(V4T);
14445 *secondary_compat_out = T(V6_M);
14446 }
14447 else
14448 *secondary_compat_out = -1;
14449
14450 if (result == -1)
14451 {
90b6238f 14452 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14453 ibfd, oldtag, newtag);
14454 return -1;
14455 }
14456
14457 return result;
14458#undef T
8e79c3df
CM		 14459}
14460
ac56ee8f
MGD		 14461/* Query attributes object to see if integer divide instructions may be
14462 present in an object. */
14463static bfd_boolean
14464elf32_arm_attributes_accept_div (const obj_attribute *attr)
14465{
14466 int arch = attr[Tag_CPU_arch].i;
14467 int profile = attr[Tag_CPU_arch_profile].i;
14468
14469 switch (attr[Tag_DIV_use].i)
14470 {
14471 case 0:
14472 /* Integer divide allowed if instruction contained in archetecture. */
14473 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14474 return TRUE;
14475 else if (arch >= TAG_CPU_ARCH_V7E_M)
14476 return TRUE;
14477 else
14478 return FALSE;
14479
14480 case 1:
14481 /* Integer divide explicitly prohibited. */
14482 return FALSE;
14483
14484 default:
14485 /* Unrecognised case - treat as allowing divide everywhere. */
14486 case 2:
14487 /* Integer divide allowed in ARM state. */
14488 return TRUE;
14489 }
14490}
14491
14492/* Query attributes object to see if integer divide instructions are
14493 forbidden to be in the object. This is not the inverse of
14494 elf32_arm_attributes_accept_div. */
14495static bfd_boolean
14496elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14497{
14498 return attr[Tag_DIV_use].i == 1;
14499}
14500
ee065d83
PB		 14501/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14502 are conflicting attributes. */
906e58ca 14503
ee065d83 14504static bfd_boolean
50e03d47 14505elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14506{
50e03d47 14507 bfd *obfd = info->output_bfd;
104d59d1
JM		 14508 obj_attribute *in_attr;
14509 obj_attribute *out_attr;
ee065d83
PB		 14510 /* Some tags have 0 = don't care, 1 = strong requirement,
14511 2 = weak requirement. */
91e22acd 14512 static const int order_021[3] = {0, 2, 1};
ee065d83 14513 int i;
91e22acd 14514 bfd_boolean result = TRUE;
9274e9de 14515 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14516
3e6b1042
DJ		 14517 /* Skip the linker stubs file. This preserves previous behavior
14518 of accepting unknown attributes in the first input file - but
14519 is that a bug? */
14520 if (ibfd->flags & BFD_LINKER_CREATED)
14521 return TRUE;
14522
9274e9de
TG		 14523 /* Skip any input that hasn't attribute section.
14524 This enables to link object files without attribute section with
14525 any others. */
14526 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14527 return TRUE;
14528
104d59d1 14529 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14530 {
14531 /* This is the first object. Copy the attributes. */
104d59d1 14532 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14533
cd21e546
MGD		 14534 out_attr = elf_known_obj_attributes_proc (obfd);
14535
004ae526
PB		 14536 /* Use the Tag_null value to indicate the attributes have been
14537 initialized. */
cd21e546 14538 out_attr[0].i = 1;
004ae526 14539
cd21e546
MGD		 14540 /* We do not output objects with Tag_MPextension_use_legacy - we move
14541 the attribute's value to Tag_MPextension_use. */
14542 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14543 {
14544 if (out_attr[Tag_MPextension_use].i != 0
14545 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14546 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14547 {
14548 _bfd_error_handler
871b3ab2 14549 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14550 "Tag_MPextension_use attributes"), ibfd);
14551 result = FALSE;
14552 }
14553
14554 out_attr[Tag_MPextension_use] =
14555 out_attr[Tag_MPextension_use_legacy];
14556 out_attr[Tag_MPextension_use_legacy].type = 0;
14557 out_attr[Tag_MPextension_use_legacy].i = 0;
14558 }
14559
14560 return result;
ee065d83
PB		 14561 }
14562
104d59d1
JM		 14563 in_attr = elf_known_obj_attributes_proc (ibfd);
14564 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14565 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14566 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14567 {
5c294fee
TG		 14568 /* Ignore mismatches if the object doesn't use floating point or is
14569 floating point ABI independent. */
14570 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14571 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14572 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14573 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14574 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14575 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14576 {
14577 _bfd_error_handler
871b3ab2 14578 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14579 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14580 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14581 result = FALSE;
ee065d83
PB		 14582 }
14583 }
14584
3de4a297 14585 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14586 {
14587 /* Merge this attribute with existing attributes. */
14588 switch (i)
14589 {
14590 case Tag_CPU_raw_name:
14591 case Tag_CPU_name:
6a631e86 14592 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14593 break;
14594
14595 case Tag_ABI_optimization_goals:
14596 case Tag_ABI_FP_optimization_goals:
14597 /* Use the first value seen. */
14598 break;
14599
14600 case Tag_CPU_arch:
91e22acd
AS		 14601 {
14602 int secondary_compat = -1, secondary_compat_out = -1;
14603 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14604 int arch_attr;
14605 static const char *name_table[] =
14606 {
91e22acd
AS		 14607 /* These aren't real CPU names, but we can't guess
14608 that from the architecture version alone. */
14609 "Pre v4",
14610 "ARM v4",
14611 "ARM v4T",
14612 "ARM v5T",
14613 "ARM v5TE",
14614 "ARM v5TEJ",
14615 "ARM v6",
14616 "ARM v6KZ",
14617 "ARM v6T2",
14618 "ARM v6K",
14619 "ARM v7",
14620 "ARM v6-M",
bca38921 14621 "ARM v6S-M",
2fd158eb
TP		 14622 "ARM v8",
14623 "",
14624 "ARM v8-M.baseline",
14625 "ARM v8-M.mainline",
91e22acd
AS		 14626 };
14627
14628 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14629 secondary_compat = get_secondary_compatible_arch (ibfd);
14630 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14631 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14632 &secondary_compat_out,
14633 in_attr[i].i,
14634 secondary_compat);
14635
14636 /* Return with error if failed to merge. */
14637 if (arch_attr == -1)
14638 return FALSE;
14639
14640 out_attr[i].i = arch_attr;
14641
91e22acd
AS		 14642 set_secondary_compatible_arch (obfd, secondary_compat_out);
14643
14644 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14645 if (out_attr[i].i == saved_out_attr)
14646 ; /* Leave the names alone. */
14647 else if (out_attr[i].i == in_attr[i].i)
14648 {
14649 /* The output architecture has been changed to match the
14650 input architecture. Use the input names. */
14651 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14652 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14653 : NULL;
14654 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14655 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14656 : NULL;
14657 }
14658 else
14659 {
14660 out_attr[Tag_CPU_name].s = NULL;
14661 out_attr[Tag_CPU_raw_name].s = NULL;
14662 }
14663
14664 /* If we still don't have a value for Tag_CPU_name,
14665 make one up now. Tag_CPU_raw_name remains blank. */
14666 if (out_attr[Tag_CPU_name].s == NULL
14667 && out_attr[i].i < ARRAY_SIZE (name_table))
14668 out_attr[Tag_CPU_name].s =
14669 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14670 }
14671 break;
14672
ee065d83
PB		 14673 case Tag_ARM_ISA_use:
14674 case Tag_THUMB_ISA_use:
ee065d83 14675 case Tag_WMMX_arch:
91e22acd
AS		 14676 case Tag_Advanced_SIMD_arch:
14677 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14678 case Tag_ABI_FP_rounding:
ee065d83
PB		 14679 case Tag_ABI_FP_exceptions:
14680 case Tag_ABI_FP_user_exceptions:
14681 case Tag_ABI_FP_number_model:
75375b3e 14682 case Tag_FP_HP_extension:
91e22acd
AS		 14683 case Tag_CPU_unaligned_access:
14684 case Tag_T2EE_use:
91e22acd 14685 case Tag_MPextension_use:
a7ad558c 14686 case Tag_MVE_arch:
ee065d83
PB		 14687 /* Use the largest value specified. */
14688 if (in_attr[i].i > out_attr[i].i)
14689 out_attr[i].i = in_attr[i].i;
14690 break;
14691
75375b3e 14692 case Tag_ABI_align_preserved:
91e22acd
AS		 14693 case Tag_ABI_PCS_RO_data:
14694 /* Use the smallest value specified. */
14695 if (in_attr[i].i < out_attr[i].i)
14696 out_attr[i].i = in_attr[i].i;
14697 break;
14698
75375b3e 14699 case Tag_ABI_align_needed:
91e22acd 14700 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14701 && (in_attr[Tag_ABI_align_preserved].i == 0
14702 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14703 {
91e22acd
AS		 14704 /* This error message should be enabled once all non-conformant
14705 binaries in the toolchain have had the attributes set
14706 properly.
ee065d83 14707 _bfd_error_handler
871b3ab2 14708 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14709 obfd, ibfd);
14710 result = FALSE; */
ee065d83 14711 }
91e22acd
AS		 14712 /* Fall through. */
14713 case Tag_ABI_FP_denormal:
14714 case Tag_ABI_PCS_GOT_use:
14715 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14716 value if greater than 2 (for future-proofing). */
14717 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14718 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14719 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14720 out_attr[i].i = in_attr[i].i;
14721 break;
91e22acd 14722
75375b3e
MGD		 14723 case Tag_Virtualization_use:
14724 /* The virtualization tag effectively stores two bits of
14725 information: the intended use of TrustZone (in bit 0), and the
14726 intended use of Virtualization (in bit 1). */
14727 if (out_attr[i].i == 0)
14728 out_attr[i].i = in_attr[i].i;
14729 else if (in_attr[i].i != 0
14730 && in_attr[i].i != out_attr[i].i)
14731 {
14732 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14733 out_attr[i].i = 3;
14734 else
14735 {
14736 _bfd_error_handler
871b3ab2
AM		 14737 (_("error: %pB: unable to merge virtualization attributes "
14738 "with %pB"),
75375b3e
MGD		 14739 obfd, ibfd);
14740 result = FALSE;
14741 }
14742 }
14743 break;
91e22acd
AS		 14744
14745 case Tag_CPU_arch_profile:
14746 if (out_attr[i].i != in_attr[i].i)
14747 {
14748 /* 0 will merge with anything.
14749 'A' and 'S' merge to 'A'.
14750 'R' and 'S' merge to 'R'.
99059e56 14751 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14752 if (out_attr[i].i == 0
14753 || (out_attr[i].i == 'S'
14754 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14755 out_attr[i].i = in_attr[i].i;
14756 else if (in_attr[i].i == 0
14757 || (in_attr[i].i == 'S'
14758 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14759 ; /* Do nothing. */
91e22acd
AS		 14760 else
14761 {
14762 _bfd_error_handler
90b6238f 14763 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14764 ibfd,
14765 in_attr[i].i ? in_attr[i].i : '0',
14766 out_attr[i].i ? out_attr[i].i : '0');
14767 result = FALSE;
14768 }
14769 }
14770 break;
15afaa63
TP		 14771
14772 case Tag_DSP_extension:
14773 /* No need to change output value if any of:
14774 - pre (<=) ARMv5T input architecture (do not have DSP)
14775 - M input profile not ARMv7E-M and do not have DSP. */
14776 if (in_attr[Tag_CPU_arch].i <= 3
14777 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14778 && in_attr[Tag_CPU_arch].i != 13
14779 && in_attr[i].i == 0))
14780 ; /* Do nothing. */
14781 /* Output value should be 0 if DSP part of architecture, ie.
14782 - post (>=) ARMv5te architecture output
14783 - A, R or S profile output or ARMv7E-M output architecture. */
14784 else if (out_attr[Tag_CPU_arch].i >= 4
14785 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14786 || out_attr[Tag_CPU_arch_profile].i == 'R'
14787 || out_attr[Tag_CPU_arch_profile].i == 'S'
14788 || out_attr[Tag_CPU_arch].i == 13))
14789 out_attr[i].i = 0;
14790 /* Otherwise, DSP instructions are added and not part of output
14791 architecture. */
14792 else
14793 out_attr[i].i = 1;
14794 break;
14795
75375b3e 14796 case Tag_FP_arch:
62f3b8c8 14797 {
4547cb56
NC		 14798 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14799 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14800 when it's 0. It might mean absence of FP hardware if
99654aaf 14801 Tag_FP_arch is zero. */
4547cb56 14802
a715796b 14803#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14804 static const struct
14805 {
14806 int ver;
14807 int regs;
bca38921 14808 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14809 {
14810 {0, 0},
14811 {1, 16},
14812 {2, 16},
14813 {3, 32},
14814 {3, 16},
14815 {4, 32},
bca38921 14816 {4, 16},
a715796b
TG		 14817 {8, 32},
14818 {8, 16}
62f3b8c8
PB		 14819 };
14820 int ver;
14821 int regs;
14822 int newval;
14823
4547cb56
NC		 14824 /* If the output has no requirement about FP hardware,
14825 follow the requirement of the input. */
14826 if (out_attr[i].i == 0)
14827 {
4ec192e6
RE		 14828 /* This assert is still reasonable, we shouldn't
14829 produce the suspicious build attribute
14830 combination (See below for in_attr). */
4547cb56
NC		 14831 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14832 out_attr[i].i = in_attr[i].i;
14833 out_attr[Tag_ABI_HardFP_use].i
14834 = in_attr[Tag_ABI_HardFP_use].i;
14835 break;
14836 }
14837 /* If the input has no requirement about FP hardware, do
14838 nothing. */
14839 else if (in_attr[i].i == 0)
14840 {
4ec192e6
RE		 14841 /* We used to assert that Tag_ABI_HardFP_use was
14842 zero here, but we should never assert when
14843 consuming an object file that has suspicious
14844 build attributes. The single precision variant
14845 of 'no FP architecture' is still 'no FP
14846 architecture', so we just ignore the tag in this
14847 case. */
4547cb56
NC		 14848 break;
14849 }
14850
14851 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14852 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14853
14854 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14855 do nothing. */
14856 if (in_attr[Tag_ABI_HardFP_use].i == 0
14857 && out_attr[Tag_ABI_HardFP_use].i == 0)
14858 ;
14859 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14860 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14861 else if (in_attr[Tag_ABI_HardFP_use].i
14862 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14863 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14864
14865 /* Now we can handle Tag_FP_arch. */
14866
bca38921
MGD		 14867 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14868 pick the biggest. */
14869 if (in_attr[i].i >= VFP_VERSION_COUNT
14870 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14871 {
14872 out_attr[i] = in_attr[i];
14873 break;
14874 }
14875 /* The output uses the superset of input features
14876 (ISA version) and registers. */
14877 ver = vfp_versions[in_attr[i].i].ver;
14878 if (ver < vfp_versions[out_attr[i].i].ver)
14879 ver = vfp_versions[out_attr[i].i].ver;
14880 regs = vfp_versions[in_attr[i].i].regs;
14881 if (regs < vfp_versions[out_attr[i].i].regs)
14882 regs = vfp_versions[out_attr[i].i].regs;
14883 /* This assumes all possible supersets are also a valid
99059e56 14884 options. */
bca38921 14885 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14886 {
14887 if (regs == vfp_versions[newval].regs
14888 && ver == vfp_versions[newval].ver)
14889 break;
14890 }
14891 out_attr[i].i = newval;
14892 }
b1cc4aeb 14893 break;
ee065d83
PB		 14894 case Tag_PCS_config:
14895 if (out_attr[i].i == 0)
14896 out_attr[i].i = in_attr[i].i;
b6009aca 14897 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14898 {
14899 /* It's sometimes ok to mix different configs, so this is only
99059e56 14900 a warning. */
ee065d83 14901 _bfd_error_handler
90b6238f 14902 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14903 }
14904 break;
14905 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14906 if (in_attr[i].i != out_attr[i].i
14907 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14908 && in_attr[i].i != AEABI_R9_unused)
14909 {
14910 _bfd_error_handler
90b6238f 14911 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14912 result = FALSE;
ee065d83
PB		 14913 }
14914 if (out_attr[i].i == AEABI_R9_unused)
14915 out_attr[i].i = in_attr[i].i;
14916 break;
14917 case Tag_ABI_PCS_RW_data:
14918 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14919 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14920 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14921 {
14922 _bfd_error_handler
871b3ab2 14923 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14924 ibfd);
91e22acd 14925 result = FALSE;
ee065d83
PB		 14926 }
14927 /* Use the smallest value specified. */
14928 if (in_attr[i].i < out_attr[i].i)
14929 out_attr[i].i = in_attr[i].i;
14930 break;
ee065d83 14931 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14932 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14933 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14934 {
14935 _bfd_error_handler
871b3ab2 14936 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14937 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14938 }
a9dc9481 14939 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14940 out_attr[i].i = in_attr[i].i;
14941 break;
ee065d83
PB		 14942 case Tag_ABI_enum_size:
14943 if (in_attr[i].i != AEABI_enum_unused)
14944 {
14945 if (out_attr[i].i == AEABI_enum_unused
14946 || out_attr[i].i == AEABI_enum_forced_wide)
14947 {
14948 /* The existing object is compatible with anything.
14949 Use whatever requirements the new object has. */
14950 out_attr[i].i = in_attr[i].i;
14951 }
14952 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14953 && out_attr[i].i != in_attr[i].i
0ffa91dd 14954 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14955 {
91e22acd 14956 static const char *aeabi_enum_names[] =
bf21ed78 14957 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14958 const char *in_name =
14959 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14960 ? aeabi_enum_names[in_attr[i].i]
14961 : "<unknown>";
14962 const char *out_name =
14963 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14964 ? aeabi_enum_names[out_attr[i].i]
14965 : "<unknown>";
ee065d83 14966 _bfd_error_handler
871b3ab2 14967 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14968 ibfd, in_name, out_name);
ee065d83
PB		 14969 }
14970 }
14971 break;
14972 case Tag_ABI_VFP_args:
14973 /* Aready done. */
14974 break;
14975 case Tag_ABI_WMMX_args:
14976 if (in_attr[i].i != out_attr[i].i)
14977 {
14978 _bfd_error_handler
871b3ab2 14979 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14980 ibfd, obfd);
91e22acd 14981 result = FALSE;
ee065d83
PB		 14982 }
14983 break;
7b86a9fa
AS		 14984 case Tag_compatibility:
14985 /* Merged in target-independent code. */
14986 break;
91e22acd 14987 case Tag_ABI_HardFP_use:
4547cb56 14988 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14989 break;
14990 case Tag_ABI_FP_16bit_format:
14991 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14992 {
14993 if (in_attr[i].i != out_attr[i].i)
14994 {
14995 _bfd_error_handler
871b3ab2 14996 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14997 ibfd, obfd);
14998 result = FALSE;
14999 }
15000 }
15001 if (in_attr[i].i != 0)
15002 out_attr[i].i = in_attr[i].i;
15003 break;
7b86a9fa 15004
cd21e546 15005 case Tag_DIV_use:
ac56ee8f
MGD		 15006 /* A value of zero on input means that the divide instruction may
15007 be used if available in the base architecture as specified via
15008 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15009 the user did not want divide instructions. A value of 2
15010 explicitly means that divide instructions were allowed in ARM
15011 and Thumb state. */
15012 if (in_attr[i].i == out_attr[i].i)
15013 /* Do nothing. */ ;
15014 else if (elf32_arm_attributes_forbid_div (in_attr)
15015 && !elf32_arm_attributes_accept_div (out_attr))
15016 out_attr[i].i = 1;
15017 else if (elf32_arm_attributes_forbid_div (out_attr)
15018 && elf32_arm_attributes_accept_div (in_attr))
15019 out_attr[i].i = in_attr[i].i;
15020 else if (in_attr[i].i == 2)
15021 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 15022 break;
15023
15024 case Tag_MPextension_use_legacy:
15025 /* We don't output objects with Tag_MPextension_use_legacy - we
15026 move the value to Tag_MPextension_use. */
15027 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
15028 {
15029 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
15030 {
15031 _bfd_error_handler
871b3ab2 15032 (_("%pB has both the current and legacy "
b38cadfb 15033 "Tag_MPextension_use attributes"),
cd21e546
MGD		 15034 ibfd);
15035 result = FALSE;
15036 }
15037 }
15038
15039 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15040 out_attr[Tag_MPextension_use] = in_attr[i];
15041
15042 break;
15043
91e22acd 15044 case Tag_nodefaults:
2d0bb761
AS		 15045 /* This tag is set if it exists, but the value is unused (and is
15046 typically zero). We don't actually need to do anything here -
15047 the merge happens automatically when the type flags are merged
15048 below. */
91e22acd
AS		 15049 break;
15050 case Tag_also_compatible_with:
15051 /* Already done in Tag_CPU_arch. */
15052 break;
15053 case Tag_conformance:
15054 /* Keep the attribute if it matches. Throw it away otherwise.
15055 No attribute means no claim to conform. */
15056 if (!in_attr[i].s || !out_attr[i].s
15057 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15058 out_attr[i].s = NULL;
15059 break;
3cfad14c 15060
91e22acd 15061 default:
e8b36cd1
JM		 15062 result
15063 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15064 }
15065
15066 /* If out_attr was copied from in_attr then it won't have a type yet. */
15067 if (in_attr[i].type && !out_attr[i].type)
15068 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15069 }
15070
104d59d1 15071 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15072 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15073 return FALSE;
ee065d83 15074
104d59d1 15075 /* Check for any attributes not known on ARM. */
e8b36cd1 15076 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15077
91e22acd 15078 return result;
252b5132
RH		 15079}
15080
3a4a14e9
PB		 15081
15082/* Return TRUE if the two EABI versions are incompatible. */
15083
15084static bfd_boolean
15085elf32_arm_versions_compatible (unsigned iver, unsigned over)
15086{
15087 /* v4 and v5 are the same spec before and after it was released,
15088 so allow mixing them. */
15089 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15090 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15091 return TRUE;
15092
15093 return (iver == over);
15094}
15095
252b5132
RH		 15096/* Merge backend specific data from an object file to the output
15097 object file when linking. */
9b485d32 15098
b34976b6 15099static bfd_boolean
50e03d47 15100elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15101
9b485d32
NC		 15102/* Display the flags field. */
15103
b34976b6 15104static bfd_boolean
57e8b36a 15105elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15106{
fc830a83
NC		 15107 FILE * file = (FILE *) ptr;
15108 unsigned long flags;
252b5132
RH		 15109
15110 BFD_ASSERT (abfd != NULL && ptr != NULL);
15111
15112 /* Print normal ELF private data. */
15113 _bfd_elf_print_private_bfd_data (abfd, ptr);
15114
fc830a83 15115 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15116 /* Ignore init flag - it may not be set, despite the flags field
15117 containing valid data. */
252b5132 15118
9b485d32 15119 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15120
fc830a83
NC		 15121 switch (EF_ARM_EABI_VERSION (flags))
15122 {
15123 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15124 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15125 official ARM ELF extended ABI. Hence they are only decoded if
15126 the EABI version is not set. */
fd2ec330 15127 if (flags & EF_ARM_INTERWORK)
9b485d32 15128 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15129
fd2ec330 15130 if (flags & EF_ARM_APCS_26)
6c571f00 15131 fprintf (file, " [APCS-26]");
fc830a83 15132 else
6c571f00 15133 fprintf (file, " [APCS-32]");
9a5aca8c 15134
96a846ea
RE		 15135 if (flags & EF_ARM_VFP_FLOAT)
15136 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15137 else if (flags & EF_ARM_MAVERICK_FLOAT)
15138 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15139 else
15140 fprintf (file, _(" [FPA float format]"));
15141
fd2ec330 15142 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15143 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15144
fd2ec330 15145 if (flags & EF_ARM_PIC)
9b485d32 15146 fprintf (file, _(" [position independent]"));
fc830a83 15147
fd2ec330 15148 if (flags & EF_ARM_NEW_ABI)
9b485d32 15149 fprintf (file, _(" [new ABI]"));
9a5aca8c 15150
fd2ec330 15151 if (flags & EF_ARM_OLD_ABI)
9b485d32 15152 fprintf (file, _(" [old ABI]"));
9a5aca8c 15153
fd2ec330 15154 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15155 fprintf (file, _(" [software FP]"));
9a5aca8c 15156
96a846ea
RE		 15157 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15158 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15159 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15160 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15161 break;
9a5aca8c 15162
fc830a83 15163 case EF_ARM_EABI_VER1:
9b485d32 15164 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15165
fc830a83 15166 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15167 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15168 else
9b485d32 15169 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15170
fc830a83
NC		 15171 flags &= ~ EF_ARM_SYMSARESORTED;
15172 break;
9a5aca8c 15173
fd2ec330
PB		 15174 case EF_ARM_EABI_VER2:
15175 fprintf (file, _(" [Version2 EABI]"));
15176
15177 if (flags & EF_ARM_SYMSARESORTED)
15178 fprintf (file, _(" [sorted symbol table]"));
15179 else
15180 fprintf (file, _(" [unsorted symbol table]"));
15181
15182 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15183 fprintf (file, _(" [dynamic symbols use segment index]"));
15184
15185 if (flags & EF_ARM_MAPSYMSFIRST)
15186 fprintf (file, _(" [mapping symbols precede others]"));
15187
99e4ae17 15188 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15189 | EF_ARM_MAPSYMSFIRST);
15190 break;
15191
d507cf36
PB		 15192 case EF_ARM_EABI_VER3:
15193 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15194 break;
15195
15196 case EF_ARM_EABI_VER4:
15197 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15198 goto eabi;
d507cf36 15199
3a4a14e9
PB		 15200 case EF_ARM_EABI_VER5:
15201 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15202
15203 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15204 fprintf (file, _(" [soft-float ABI]"));
15205
15206 if (flags & EF_ARM_ABI_FLOAT_HARD)
15207 fprintf (file, _(" [hard-float ABI]"));
15208
15209 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15210
3a4a14e9 15211 eabi:
d507cf36
PB		 15212 if (flags & EF_ARM_BE8)
15213 fprintf (file, _(" [BE8]"));
15214
15215 if (flags & EF_ARM_LE8)
15216 fprintf (file, _(" [LE8]"));
15217
15218 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15219 break;
15220
fc830a83 15221 default:
9b485d32 15222 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15223 break;
15224 }
252b5132 15225
fc830a83 15226 flags &= ~ EF_ARM_EABIMASK;
252b5132 15227
fc830a83 15228 if (flags & EF_ARM_RELEXEC)
9b485d32 15229 fprintf (file, _(" [relocatable executable]"));
252b5132 15230
18a20338
CL		 15231 if (flags & EF_ARM_PIC)
15232 fprintf (file, _(" [position independent]"));
15233
15234 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15235 fprintf (file, _(" [FDPIC ABI supplement]"));
15236
15237 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15238
15239 if (flags)
9b485d32 15240 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15241
252b5132
RH		 15242 fputc ('\n', file);
15243
b34976b6 15244 return TRUE;
252b5132
RH		 15245}
15246
15247static int
57e8b36a 15248elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15249{
2f0ca46a
NC		 15250 switch (ELF_ST_TYPE (elf_sym->st_info))
15251 {
15252 case STT_ARM_TFUNC:
15253 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15254
2f0ca46a
NC		 15255 case STT_ARM_16BIT:
15256 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15257 This allows us to distinguish between data used by Thumb instructions
15258 and non-data (which is probably code) inside Thumb regions of an
15259 executable. */
1a0eb693 15260 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15261 return ELF_ST_TYPE (elf_sym->st_info);
15262 break;
9a5aca8c 15263
ce855c42
NC		 15264 default:
15265 break;
2f0ca46a
NC		 15266 }
15267
15268 return type;
252b5132 15269}
f21f3fe0 15270
252b5132 15271static asection *
07adf181
AM		 15272elf32_arm_gc_mark_hook (asection *sec,
15273 struct bfd_link_info *info,
15274 Elf_Internal_Rela *rel,
15275 struct elf_link_hash_entry *h,
15276 Elf_Internal_Sym *sym)
252b5132
RH		 15277{
15278 if (h != NULL)
07adf181 15279 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15280 {
15281 case R_ARM_GNU_VTINHERIT:
15282 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15283 return NULL;
15284 }
9ad5cbcf 15285
07adf181 15286 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15287}
15288
780a67af
NC		 15289/* Look through the relocs for a section during the first phase. */
15290
b34976b6 15291static bfd_boolean
57e8b36a
NC		 15292elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15293 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15294{
b34976b6
AM		 15295 Elf_Internal_Shdr *symtab_hdr;
15296 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15297 const Elf_Internal_Rela *rel;
15298 const Elf_Internal_Rela *rel_end;
15299 bfd *dynobj;
5e681ec4 15300 asection *sreloc;
5e681ec4 15301 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15302 bfd_boolean call_reloc_p;
15303 bfd_boolean may_become_dynamic_p;
15304 bfd_boolean may_need_local_target_p;
ce98a316 15305 unsigned long nsyms;
9a5aca8c 15306
0e1862bb 15307 if (bfd_link_relocatable (info))
b34976b6 15308 return TRUE;
9a5aca8c 15309
0ffa91dd
NC		 15310 BFD_ASSERT (is_arm_elf (abfd));
15311
5e681ec4 15312 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15313 if (htab == NULL)
15314 return FALSE;
15315
5e681ec4 15316 sreloc = NULL;
9a5aca8c 15317
67687978
PB		 15318 /* Create dynamic sections for relocatable executables so that we can
15319 copy relocations. */
15320 if (htab->root.is_relocatable_executable
15321 && ! htab->root.dynamic_sections_created)
15322 {
15323 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15324 return FALSE;
15325 }
15326
cbc704f3
RS		 15327 if (htab->root.dynobj == NULL)
15328 htab->root.dynobj = abfd;
34e77a92
RS		 15329 if (!create_ifunc_sections (info))
15330 return FALSE;
cbc704f3
RS		 15331
15332 dynobj = htab->root.dynobj;
15333
0ffa91dd 15334 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15335 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15336 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15337
252b5132
RH		 15338 rel_end = relocs + sec->reloc_count;
15339 for (rel = relocs; rel < rel_end; rel++)
15340 {
34e77a92 15341 Elf_Internal_Sym *isym;
252b5132 15342 struct elf_link_hash_entry *h;
b7693d02 15343 struct elf32_arm_link_hash_entry *eh;
d42c267e 15344 unsigned int r_symndx;
eb043451 15345 int r_type;
9a5aca8c 15346
252b5132 15347 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15348 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15349 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15350
ce98a316
NC		 15351 if (r_symndx >= nsyms
15352 /* PR 9934: It is possible to have relocations that do not
15353 refer to symbols, thus it is also possible to have an
15354 object file containing relocations but no symbol table. */
cf35638d 15355 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15356 {
871b3ab2 15357 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15358 r_symndx);
ba93b8ac
DJ		 15359 return FALSE;
15360 }
15361
34e77a92
RS		 15362 h = NULL;
15363 isym = NULL;
15364 if (nsyms > 0)
973a3492 15365 {
34e77a92
RS		 15366 if (r_symndx < symtab_hdr->sh_info)
15367 {
15368 /* A local symbol. */
15369 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15370 abfd, r_symndx);
15371 if (isym == NULL)
15372 return FALSE;
15373 }
15374 else
15375 {
15376 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15377 while (h->root.type == bfd_link_hash_indirect
15378 || h->root.type == bfd_link_hash_warning)
15379 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15380 }
973a3492 15381 }
9a5aca8c 15382
b7693d02
DJ		 15383 eh = (struct elf32_arm_link_hash_entry *) h;
15384
f6e32f6d
RS		 15385 call_reloc_p = FALSE;
15386 may_become_dynamic_p = FALSE;
15387 may_need_local_target_p = FALSE;
15388
0855e32b
NS		 15389 /* Could be done earlier, if h were already available. */
15390 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15391 switch (r_type)
99059e56 15392 {
e8b09b87
CL		 15393 case R_ARM_GOTOFFFUNCDESC:
15394 {
15395 if (h == NULL)
15396 {
15397 if (!elf32_arm_allocate_local_sym_info (abfd))
15398 return FALSE;
15399 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15400 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15401 }
15402 else
15403 {
15404 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15405 }
15406 }
15407 break;
15408
15409 case R_ARM_GOTFUNCDESC:
15410 {
15411 if (h == NULL)
15412 {
15413 /* Such a relocation is not supposed to be generated
15414 by gcc on a static function. */
15415 /* Anyway if needed it could be handled. */
15416 abort();
15417 }
15418 else
15419 {
15420 eh->fdpic_cnts.gotfuncdesc_cnt++;
15421 }
15422 }
15423 break;
15424
15425 case R_ARM_FUNCDESC:
15426 {
15427 if (h == NULL)
15428 {
15429 if (!elf32_arm_allocate_local_sym_info (abfd))
15430 return FALSE;
15431 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15432 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15433 }
15434 else
15435 {
15436 eh->fdpic_cnts.funcdesc_cnt++;
15437 }
15438 }
15439 break;
15440
5e681ec4 15441 case R_ARM_GOT32:
eb043451 15442 case R_ARM_GOT_PREL:
ba93b8ac 15443 case R_ARM_TLS_GD32:
5c5a4843 15444 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15445 case R_ARM_TLS_IE32:
5c5a4843 15446 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15447 case R_ARM_TLS_GOTDESC:
15448 case R_ARM_TLS_DESCSEQ:
15449 case R_ARM_THM_TLS_DESCSEQ:
15450 case R_ARM_TLS_CALL:
15451 case R_ARM_THM_TLS_CALL:
5e681ec4 15452 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15453 {
15454 int tls_type, old_tls_type;
5e681ec4 15455
ba93b8ac
DJ		 15456 switch (r_type)
15457 {
15458 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15459 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15460
ba93b8ac 15461 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15462 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15463
0855e32b
NS		 15464 case R_ARM_TLS_GOTDESC:
15465 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15466 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15467 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15468
ba93b8ac
DJ		 15469 default: tls_type = GOT_NORMAL; break;
15470 }
252b5132 15471
0e1862bb 15472 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15473 info->flags |= DF_STATIC_TLS;
15474
ba93b8ac
DJ		 15475 if (h != NULL)
15476 {
15477 h->got.refcount++;
15478 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15479 }
15480 else
15481 {
ba93b8ac 15482 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15483 if (!elf32_arm_allocate_local_sym_info (abfd))
15484 return FALSE;
15485 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15486 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15487 }
15488
0855e32b 15489 /* If a variable is accessed with both tls methods, two
99059e56 15490 slots may be created. */
0855e32b
NS		 15491 if (GOT_TLS_GD_ANY_P (old_tls_type)
15492 && GOT_TLS_GD_ANY_P (tls_type))
15493 tls_type |= old_tls_type;
15494
15495 /* We will already have issued an error message if there
15496 is a TLS/non-TLS mismatch, based on the symbol
15497 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15498 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15499 && tls_type != GOT_NORMAL)
15500 tls_type |= old_tls_type;
15501
0855e32b 15502 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15503 method, we're able to relax. Turn off the GDESC flag,
15504 without messing up with any other kind of tls types
6a631e86 15505 that may be involved. */
0855e32b
NS		 15506 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15507 tls_type &= ~GOT_TLS_GDESC;
15508
ba93b8ac
DJ		 15509 if (old_tls_type != tls_type)
15510 {
15511 if (h != NULL)
15512 elf32_arm_hash_entry (h)->tls_type = tls_type;
15513 else
15514 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15515 }
15516 }
8029a119 15517 /* Fall through. */
ba93b8ac
DJ		 15518
15519 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15520 case R_ARM_TLS_LDM32_FDPIC:
15521 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15522 htab->tls_ldm_got.refcount++;
8029a119 15523 /* Fall through. */
252b5132 15524
c19d1205 15525 case R_ARM_GOTOFF32:
5e681ec4 15526 case R_ARM_GOTPC:
cbc704f3
RS		 15527 if (htab->root.sgot == NULL
15528 && !create_got_section (htab->root.dynobj, info))
15529 return FALSE;
252b5132
RH		 15530 break;
15531
252b5132 15532 case R_ARM_PC24:
7359ea65 15533 case R_ARM_PLT32:
5b5bb741
PB		 15534 case R_ARM_CALL:
15535 case R_ARM_JUMP24:
eb043451 15536 case R_ARM_PREL31:
c19d1205 15537 case R_ARM_THM_CALL:
bd97cb95
DJ		 15538 case R_ARM_THM_JUMP24:
15539 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15540 call_reloc_p = TRUE;
15541 may_need_local_target_p = TRUE;
15542 break;
15543
15544 case R_ARM_ABS12:
15545 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15546 ldr __GOTT_INDEX__ offsets. */
15547 if (!htab->vxworks_p)
15548 {
15549 may_need_local_target_p = TRUE;
15550 break;
15551 }
aebf9be7 15552 else goto jump_over;
9eaff861 15553
f6e32f6d 15554 /* Fall through. */
39623e12 15555
96c23d59
JM		 15556 case R_ARM_MOVW_ABS_NC:
15557 case R_ARM_MOVT_ABS:
15558 case R_ARM_THM_MOVW_ABS_NC:
15559 case R_ARM_THM_MOVT_ABS:
0e1862bb 15560 if (bfd_link_pic (info))
96c23d59 15561 {
4eca0228 15562 _bfd_error_handler
871b3ab2 15563 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15564 abfd, elf32_arm_howto_table_1[r_type].name,
15565 (h) ? h->root.root.string : "a local symbol");
15566 bfd_set_error (bfd_error_bad_value);
15567 return FALSE;
15568 }
15569
15570 /* Fall through. */
39623e12
PB		 15571 case R_ARM_ABS32:
15572 case R_ARM_ABS32_NOI:
aebf9be7 15573 jump_over:
0e1862bb 15574 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15575 {
15576 h->pointer_equality_needed = 1;
15577 }
15578 /* Fall through. */
39623e12
PB		 15579 case R_ARM_REL32:
15580 case R_ARM_REL32_NOI:
b6895b4f
PB		 15581 case R_ARM_MOVW_PREL_NC:
15582 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15583 case R_ARM_THM_MOVW_PREL_NC:
15584 case R_ARM_THM_MOVT_PREL:
39623e12 15585
b7693d02 15586 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15587 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15588 || htab->fdpic_p)
34e77a92
RS		 15589 && (sec->flags & SEC_ALLOC) != 0)
15590 {
15591 if (h == NULL
469a3493 15592 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15593 {
15594 /* In shared libraries and relocatable executables,
15595 we treat local relative references as calls;
15596 see the related SYMBOL_CALLS_LOCAL code in
15597 allocate_dynrelocs. */
15598 call_reloc_p = TRUE;
15599 may_need_local_target_p = TRUE;
15600 }
15601 else
15602 /* We are creating a shared library or relocatable
15603 executable, and this is a reloc against a global symbol,
15604 or a non-PC-relative reloc against a local symbol.
15605 We may need to copy the reloc into the output. */
15606 may_become_dynamic_p = TRUE;
15607 }
f6e32f6d
RS		 15608 else
15609 may_need_local_target_p = TRUE;
252b5132
RH		 15610 break;
15611
99059e56
RM		 15612 /* This relocation describes the C++ object vtable hierarchy.
15613 Reconstruct it for later use during GC. */
15614 case R_ARM_GNU_VTINHERIT:
15615 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15616 return FALSE;
15617 break;
15618
15619 /* This relocation describes which C++ vtable entries are actually
15620 used. Record for later use during GC. */
15621 case R_ARM_GNU_VTENTRY:
a0ea3a14 15622 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15623 return FALSE;
15624 break;
15625 }
f6e32f6d
RS		 15626
15627 if (h != NULL)
15628 {
15629 if (call_reloc_p)
15630 /* We may need a .plt entry if the function this reloc
15631 refers to is in a different object, regardless of the
15632 symbol's type. We can't tell for sure yet, because
15633 something later might force the symbol local. */
15634 h->needs_plt = 1;
15635 else if (may_need_local_target_p)
15636 /* If this reloc is in a read-only section, we might
15637 need a copy reloc. We can't check reliably at this
15638 stage whether the section is read-only, as input
15639 sections have not yet been mapped to output sections.
15640 Tentatively set the flag for now, and correct in
15641 adjust_dynamic_symbol. */
15642 h->non_got_ref = 1;
15643 }
15644
34e77a92
RS		 15645 if (may_need_local_target_p
15646 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15647 {
34e77a92
RS		 15648 union gotplt_union *root_plt;
15649 struct arm_plt_info *arm_plt;
15650 struct arm_local_iplt_info *local_iplt;
15651
15652 if (h != NULL)
15653 {
15654 root_plt = &h->plt;
15655 arm_plt = &eh->plt;
15656 }
15657 else
15658 {
15659 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15660 if (local_iplt == NULL)
15661 return FALSE;
15662 root_plt = &local_iplt->root;
15663 arm_plt = &local_iplt->arm;
15664 }
15665
f6e32f6d
RS		 15666 /* If the symbol is a function that doesn't bind locally,
15667 this relocation will need a PLT entry. */
a8c887dd
NC		 15668 if (root_plt->refcount != -1)
15669 root_plt->refcount += 1;
34e77a92
RS		 15670
15671 if (!call_reloc_p)
15672 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15673
15674 /* It's too early to use htab->use_blx here, so we have to
15675 record possible blx references separately from
15676 relocs that definitely need a thumb stub. */
15677
15678 if (r_type == R_ARM_THM_CALL)
34e77a92 15679 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15680
15681 if (r_type == R_ARM_THM_JUMP24
15682 || r_type == R_ARM_THM_JUMP19)
34e77a92 15683 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15684 }
15685
15686 if (may_become_dynamic_p)
15687 {
15688 struct elf_dyn_relocs *p, **head;
15689
15690 /* Create a reloc section in dynobj. */
15691 if (sreloc == NULL)
15692 {
15693 sreloc = _bfd_elf_make_dynamic_reloc_section
15694 (sec, dynobj, 2, abfd, ! htab->use_rel);
15695
15696 if (sreloc == NULL)
15697 return FALSE;
15698
15699 /* BPABI objects never have dynamic relocations mapped. */
15700 if (htab->symbian_p)
15701 {
15702 flagword flags;
15703
fd361982 15704 flags = bfd_section_flags (sreloc);
f6e32f6d 15705 flags &= ~(SEC_LOAD | SEC_ALLOC);
fd361982 15706 bfd_set_section_flags (sreloc, flags);
f6e32f6d
RS		 15707 }
15708 }
15709
15710 /* If this is a global symbol, count the number of
15711 relocations we need for this symbol. */
15712 if (h != NULL)
15713 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15714 else
15715 {
34e77a92
RS		 15716 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15717 if (head == NULL)
f6e32f6d 15718 return FALSE;
f6e32f6d
RS		 15719 }
15720
15721 p = *head;
15722 if (p == NULL || p->sec != sec)
15723 {
15724 bfd_size_type amt = sizeof *p;
15725
15726 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15727 if (p == NULL)
15728 return FALSE;
15729 p->next = *head;
15730 *head = p;
15731 p->sec = sec;
15732 p->count = 0;
15733 p->pc_count = 0;
15734 }
15735
469a3493 15736 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15737 p->pc_count += 1;
15738 p->count += 1;
e8b09b87
CL		 15739 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15740 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15741 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15742 that will become rofixup. */
15743 /* This is due to the fact that we suppose all will become rofixup. */
15744 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15745 _bfd_error_handler
15746 (_("FDPIC does not yet support %s relocation"
15747 " to become dynamic for executable"),
15748 elf32_arm_howto_table_1[r_type].name);
15749 abort();
15750 }
f6e32f6d 15751 }
252b5132 15752 }
f21f3fe0 15753
b34976b6 15754 return TRUE;
252b5132
RH		 15755}
15756
9eaff861
AO		 15757static void
15758elf32_arm_update_relocs (asection *o,
15759 struct bfd_elf_section_reloc_data *reldata)
15760{
15761 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15762 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15763 const struct elf_backend_data *bed;
15764 _arm_elf_section_data *eado;
15765 struct bfd_link_order *p;
15766 bfd_byte *erela_head, *erela;
15767 Elf_Internal_Rela *irela_head, *irela;
15768 Elf_Internal_Shdr *rel_hdr;
15769 bfd *abfd;
15770 unsigned int count;
15771
15772 eado = get_arm_elf_section_data (o);
15773
15774 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15775 return;
15776
15777 abfd = o->owner;
15778 bed = get_elf_backend_data (abfd);
15779 rel_hdr = reldata->hdr;
15780
15781 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15782 {
15783 swap_in = bed->s->swap_reloc_in;
15784 swap_out = bed->s->swap_reloc_out;
15785 }
15786 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15787 {
15788 swap_in = bed->s->swap_reloca_in;
15789 swap_out = bed->s->swap_reloca_out;
15790 }
15791 else
15792 abort ();
15793
15794 erela_head = rel_hdr->contents;
15795 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15796 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15797
15798 erela = erela_head;
15799 irela = irela_head;
15800 count = 0;
15801
15802 for (p = o->map_head.link_order; p; p = p->next)
15803 {
15804 if (p->type == bfd_section_reloc_link_order
15805 || p->type == bfd_symbol_reloc_link_order)
15806 {
15807 (*swap_in) (abfd, erela, irela);
15808 erela += rel_hdr->sh_entsize;
15809 irela++;
15810 count++;
15811 }
15812 else if (p->type == bfd_indirect_link_order)
15813 {
15814 struct bfd_elf_section_reloc_data *input_reldata;
15815 arm_unwind_table_edit *edit_list, *edit_tail;
15816 _arm_elf_section_data *eadi;
15817 bfd_size_type j;
15818 bfd_vma offset;
15819 asection *i;
15820
15821 i = p->u.indirect.section;
15822
15823 eadi = get_arm_elf_section_data (i);
15824 edit_list = eadi->u.exidx.unwind_edit_list;
15825 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15826 offset = i->output_offset;
9eaff861
AO		 15827
15828 if (eadi->elf.rel.hdr &&
15829 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15830 input_reldata = &eadi->elf.rel;
15831 else if (eadi->elf.rela.hdr &&
15832 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15833 input_reldata = &eadi->elf.rela;
15834 else
15835 abort ();
15836
15837 if (edit_list)
15838 {
15839 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15840 {
15841 arm_unwind_table_edit *edit_node, *edit_next;
15842 bfd_vma bias;
c48182bf 15843 bfd_vma reloc_index;
9eaff861
AO		 15844
15845 (*swap_in) (abfd, erela, irela);
c48182bf 15846 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15847
15848 bias = 0;
15849 edit_node = edit_list;
15850 for (edit_next = edit_list;
c48182bf 15851 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15852 edit_next = edit_node->next)
15853 {
15854 bias++;
15855 edit_node = edit_next;
15856 }
15857
15858 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15859 || edit_node->index != reloc_index)
9eaff861
AO		 15860 {
15861 irela->r_offset -= bias * 8;
15862 irela++;
15863 count++;
15864 }
15865
15866 erela += rel_hdr->sh_entsize;
15867 }
15868
15869 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15870 {
15871 /* New relocation entity. */
15872 asection *text_sec = edit_tail->linked_section;
15873 asection *text_out = text_sec->output_section;
15874 bfd_vma exidx_offset = offset + i->size - 8;
15875
15876 irela->r_addend = 0;
15877 irela->r_offset = exidx_offset;
15878 irela->r_info = ELF32_R_INFO
15879 (text_out->target_index, R_ARM_PREL31);
15880 irela++;
15881 count++;
15882 }
15883 }
15884 else
15885 {
15886 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15887 {
15888 (*swap_in) (abfd, erela, irela);
15889 erela += rel_hdr->sh_entsize;
15890 irela++;
15891 }
15892
15893 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15894 }
15895 }
15896 }
15897
15898 reldata->count = count;
15899 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15900
15901 erela = erela_head;
15902 irela = irela_head;
15903 while (count > 0)
15904 {
15905 (*swap_out) (abfd, irela, erela);
15906 erela += rel_hdr->sh_entsize;
15907 irela++;
15908 count--;
15909 }
15910
15911 free (irela_head);
15912
15913 /* Hashes are no longer valid. */
15914 free (reldata->hashes);
15915 reldata->hashes = NULL;
15916}
15917
6a5bb875 15918/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15919 required if the corresponding code section is marked. Similarly, ARMv8-M
15920 secure entry functions can only be referenced by SG veneers which are
15921 created after the GC process. They need to be marked in case they reside in
15922 their own section (as would be the case if code was compiled with
15923 -ffunction-sections). */
6a5bb875
PB		 15924
15925static bfd_boolean
906e58ca
NC		 15926elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15927 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15928{
15929 bfd *sub;
15930 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15931 asection *cmse_sec;
15932 obj_attribute *out_attr;
15933 Elf_Internal_Shdr *symtab_hdr;
15934 unsigned i, sym_count, ext_start;
15935 const struct elf_backend_data *bed;
15936 struct elf_link_hash_entry **sym_hashes;
15937 struct elf32_arm_link_hash_entry *cmse_hash;
15938 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15939 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15940 asection *isec;
6a5bb875 15941
7f6ab9f8
AM		 15942 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15943
4ba2ef8f
TP		 15944 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15945 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15946 && out_attr[Tag_CPU_arch_profile].i == 'M';
15947
6a5bb875
PB		 15948 /* Marking EH data may cause additional code sections to be marked,
15949 requiring multiple passes. */
15950 again = TRUE;
15951 while (again)
15952 {
15953 again = FALSE;
c72f2fb2 15954 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15955 {
15956 asection *o;
15957
0ffa91dd 15958 if (! is_arm_elf (sub))
6a5bb875
PB		 15959 continue;
15960
15961 elf_shdrp = elf_elfsections (sub);
15962 for (o = sub->sections; o != NULL; o = o->next)
15963 {
15964 Elf_Internal_Shdr *hdr;
0ffa91dd 15965
6a5bb875 15966 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15967 if (hdr->sh_type == SHT_ARM_EXIDX
15968 && hdr->sh_link
15969 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15970 && !o->gc_mark
15971 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15972 {
15973 again = TRUE;
15974 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15975 return FALSE;
15976 }
15977 }
4ba2ef8f
TP		 15978
15979 /* Mark section holding ARMv8-M secure entry functions. We mark all
15980 of them so no need for a second browsing. */
15981 if (is_v8m && first_bfd_browse)
15982 {
15983 sym_hashes = elf_sym_hashes (sub);
15984 bed = get_elf_backend_data (sub);
15985 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15986 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15987 ext_start = symtab_hdr->sh_info;
15988
15989 /* Scan symbols. */
15990 for (i = ext_start; i < sym_count; i++)
15991 {
15992 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15993
15994 /* Assume it is a special symbol. If not, cmse_scan will
15995 warn about it and user can do something about it. */
baf46cd7
AM		 15996 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
15997 CMSE_PREFIX))
4ba2ef8f
TP		 15998 {
15999 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 16000 if (!cmse_sec->gc_mark
16001 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 16002 return FALSE;
bb32413f
SP		 16003 /* The debug sections related to these secure entry
16004 functions are marked on enabling below flag. */
16005 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 16006 }
16007 }
bb32413f
SP		 16008
16009 if (debug_sec_need_to_be_marked)
16010 {
16011 /* Looping over all the sections of the object file containing
16012 Armv8-M secure entry functions and marking all the debug
16013 sections. */
16014 for (isec = sub->sections; isec != NULL; isec = isec->next)
16015 {
16016 /* If not a debug sections, skip it. */
16017 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
16018 isec->gc_mark = 1 ;
16019 }
16020 debug_sec_need_to_be_marked = FALSE;
16021 }
4ba2ef8f 16022 }
6a5bb875 16023 }
4ba2ef8f 16024 first_bfd_browse = FALSE;
6a5bb875
PB		 16025 }
16026
16027 return TRUE;
16028}
16029
3c9458e9
NC		 16030/* Treat mapping symbols as special target symbols. */
16031
16032static bfd_boolean
16033elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
16034{
b0796911
PB		 16035 return bfd_is_arm_special_symbol_name (sym->name,
16036 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 16037}
16038
e7679060
AM		 16039/* If the ELF symbol SYM might be a function in SEC, return the
16040 function size and set *CODE_OFF to the function's entry point,
16041 otherwise return zero. */
252b5132 16042
e7679060
AM		 16043static bfd_size_type
16044elf32_arm_maybe_function_sym (const asymbol *sym, asection *sec,
16045 bfd_vma *code_off)
16046{
16047 bfd_size_type size;
252b5132 16048
e7679060
AM		 16049 if ((sym->flags & (BSF_SECTION_SYM | BSF_FILE | BSF_OBJECT
16050 | BSF_THREAD_LOCAL | BSF_RELC | BSF_SRELC)) != 0
16051 || sym->section != sec)
16052 return 0;
252b5132 16053
e7679060
AM		 16054 if (!(sym->flags & BSF_SYNTHETIC))
16055 switch (ELF_ST_TYPE (((elf_symbol_type *) sym)->internal_elf_sym.st_info))
16056 {
252b5132
RH		 16057 case STT_FUNC:
16058 case STT_ARM_TFUNC:
9d2da7ca 16059 case STT_NOTYPE:
252b5132 16060 break;
e7679060
AM		 16061 default:
16062 return 0;
16063 }
0367ecfb 16064
e7679060
AM		 16065 if ((sym->flags & BSF_LOCAL)
16066 && bfd_is_arm_special_symbol_name (sym->name,
16067 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16068 return 0;
0367ecfb 16069
e7679060
AM		 16070 *code_off = sym->value;
16071 size = 0;
16072 if (!(sym->flags & BSF_SYNTHETIC))
16073 size = ((elf_symbol_type *) sym)->internal_elf_sym.st_size;
16074 if (size == 0)
16075 size = 1;
16076 return size;
252b5132
RH		 16077}
16078
4ab527b0 16079static bfd_boolean
07d6d2b8 16080elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16081 const char ** filename_ptr,
16082 const char ** functionname_ptr,
16083 unsigned int * line_ptr)
16084{
16085 bfd_boolean found;
16086 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16087 functionname_ptr, line_ptr,
16088 & elf_tdata (abfd)->dwarf2_find_line_info);
16089 return found;
16090}
16091
63c1f59d
AM		 16092/* Find dynamic relocs for H that apply to read-only sections. */
16093
16094static asection *
16095readonly_dynrelocs (struct elf_link_hash_entry *h)
16096{
16097 struct elf_dyn_relocs *p;
16098
16099 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
16100 {
16101 asection *s = p->sec->output_section;
16102
16103 if (s != NULL && (s->flags & SEC_READONLY) != 0)
16104 return p->sec;
16105 }
16106 return NULL;
16107}
16108
252b5132
RH		 16109/* Adjust a symbol defined by a dynamic object and referenced by a
16110 regular object. The current definition is in some section of the
16111 dynamic object, but we're not including those sections. We have to
16112 change the definition to something the rest of the link can
16113 understand. */
16114
b34976b6 16115static bfd_boolean
57e8b36a
NC		 16116elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16117 struct elf_link_hash_entry * h)
252b5132
RH		 16118{
16119 bfd * dynobj;
5474d94f 16120 asection *s, *srel;
b7693d02 16121 struct elf32_arm_link_hash_entry * eh;
67687978 16122 struct elf32_arm_link_hash_table *globals;
252b5132 16123
67687978 16124 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16125 if (globals == NULL)
16126 return FALSE;
16127
252b5132
RH		 16128 dynobj = elf_hash_table (info)->dynobj;
16129
16130 /* Make sure we know what is going on here. */
16131 BFD_ASSERT (dynobj != NULL
f5385ebf 16132 && (h->needs_plt
34e77a92 16133 || h->type == STT_GNU_IFUNC
60d67dc8 16134 || h->is_weakalias
f5385ebf
AM		 16135 || (h->def_dynamic
16136 && h->ref_regular
16137 && !h->def_regular)));
252b5132 16138
b7693d02
DJ		 16139 eh = (struct elf32_arm_link_hash_entry *) h;
16140
252b5132
RH		 16141 /* If this is a function, put it in the procedure linkage table. We
16142 will fill in the contents of the procedure linkage table later,
16143 when we know the address of the .got section. */
34e77a92 16144 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16145 {
34e77a92
RS		 16146 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16147 symbol binds locally. */
5e681ec4 16148 if (h->plt.refcount <= 0
34e77a92
RS		 16149 || (h->type != STT_GNU_IFUNC
16150 && (SYMBOL_CALLS_LOCAL (info, h)
16151 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16152 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16153 {
16154 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16155 file, but the symbol was never referred to by a dynamic
16156 object, or if all references were garbage collected. In
16157 such a case, we don't actually need to build a procedure
16158 linkage table, and we can just do a PC24 reloc instead. */
16159 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16160 eh->plt.thumb_refcount = 0;
16161 eh->plt.maybe_thumb_refcount = 0;
16162 eh->plt.noncall_refcount = 0;
f5385ebf 16163 h->needs_plt = 0;
252b5132
RH		 16164 }
16165
b34976b6 16166 return TRUE;
252b5132 16167 }
5e681ec4 16168 else
b7693d02
DJ		 16169 {
16170 /* It's possible that we incorrectly decided a .plt reloc was
16171 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16172 in check_relocs. We can't decide accurately between function
16173 and non-function syms in check-relocs; Objects loaded later in
16174 the link may change h->type. So fix it now. */
16175 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16176 eh->plt.thumb_refcount = 0;
16177 eh->plt.maybe_thumb_refcount = 0;
16178 eh->plt.noncall_refcount = 0;
b7693d02 16179 }
252b5132
RH		 16180
16181 /* If this is a weak symbol, and there is a real definition, the
16182 processor independent code will have arranged for us to see the
16183 real definition first, and we can just use the same value. */
60d67dc8 16184 if (h->is_weakalias)
252b5132 16185 {
60d67dc8
AM		 16186 struct elf_link_hash_entry *def = weakdef (h);
16187 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16188 h->root.u.def.section = def->root.u.def.section;
16189 h->root.u.def.value = def->root.u.def.value;
b34976b6 16190 return TRUE;
252b5132
RH		 16191 }
16192
ba93b8ac
DJ		 16193 /* If there are no non-GOT references, we do not need a copy
16194 relocation. */
16195 if (!h->non_got_ref)
16196 return TRUE;
16197
252b5132
RH		 16198 /* This is a reference to a symbol defined by a dynamic object which
16199 is not a function. */
16200
16201 /* If we are creating a shared library, we must presume that the
16202 only references to the symbol are via the global offset table.
16203 For such cases we need not do anything here; the relocations will
67687978
PB		 16204 be handled correctly by relocate_section. Relocatable executables
16205 can reference data in shared objects directly, so we don't need to
16206 do anything here. */
0e1862bb 16207 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16208 return TRUE;
252b5132
RH		 16209
16210 /* We must allocate the symbol in our .dynbss section, which will
16211 become part of the .bss section of the executable. There will be
16212 an entry for this symbol in the .dynsym section. The dynamic
16213 object will contain position independent code, so all references
16214 from the dynamic object to this symbol will go through the global
16215 offset table. The dynamic linker will use the .dynsym entry to
16216 determine the address it must put in the global offset table, so
16217 both the dynamic object and the regular object will refer to the
16218 same memory location for the variable. */
5522f910
NC		 16219 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16220 linker to copy the initial value out of the dynamic object and into
16221 the runtime process image. We need to remember the offset into the
00a97672 16222 .rel(a).bss section we are going to use. */
5474d94f
AM		 16223 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16224 {
16225 s = globals->root.sdynrelro;
16226 srel = globals->root.sreldynrelro;
16227 }
16228 else
16229 {
16230 s = globals->root.sdynbss;
16231 srel = globals->root.srelbss;
16232 }
5522f910
NC		 16233 if (info->nocopyreloc == 0
16234 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16235 && h->size != 0)
252b5132 16236 {
47beaa6a 16237 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16238 h->needs_copy = 1;
252b5132
RH		 16239 }
16240
6cabe1ea 16241 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16242}
16243
5e681ec4
PB		 16244/* Allocate space in .plt, .got and associated reloc sections for
16245 dynamic relocs. */
16246
16247static bfd_boolean
47beaa6a 16248allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16249{
16250 struct bfd_link_info *info;
16251 struct elf32_arm_link_hash_table *htab;
16252 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16253 struct elf_dyn_relocs *p;
5e681ec4
PB		 16254
16255 if (h->root.type == bfd_link_hash_indirect)
16256 return TRUE;
16257
e6a6bb22
AM		 16258 eh = (struct elf32_arm_link_hash_entry *) h;
16259
5e681ec4
PB		 16260 info = (struct bfd_link_info *) inf;
16261 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16262 if (htab == NULL)
16263 return FALSE;
5e681ec4 16264
34e77a92 16265 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16266 && h->plt.refcount > 0)
16267 {
16268 /* Make sure this symbol is output as a dynamic symbol.
16269 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16270 if (h->dynindx == -1 && !h->forced_local
16271 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16272 {
c152c796 16273 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16274 return FALSE;
16275 }
16276
34e77a92
RS		 16277 /* If the call in the PLT entry binds locally, the associated
16278 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16279 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16280 than the .plt section. */
16281 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16282 {
16283 eh->is_iplt = 1;
16284 if (eh->plt.noncall_refcount == 0
16285 && SYMBOL_REFERENCES_LOCAL (info, h))
16286 /* All non-call references can be resolved directly.
16287 This means that they can (and in some cases, must)
16288 resolve directly to the run-time target, rather than
16289 to the PLT. That in turns means that any .got entry
16290 would be equal to the .igot.plt entry, so there's
16291 no point having both. */
16292 h->got.refcount = 0;
16293 }
16294
0e1862bb 16295 if (bfd_link_pic (info)
34e77a92 16296 || eh->is_iplt
7359ea65 16297 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16298 {
34e77a92 16299 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16300
5e681ec4
PB		 16301 /* If this symbol is not defined in a regular file, and we are
16302 not generating a shared library, then set the symbol to this
16303 location in the .plt. This is required to make function
16304 pointers compare as equal between the normal executable and
16305 the shared library. */
0e1862bb 16306 if (! bfd_link_pic (info)
f5385ebf 16307 && !h->def_regular)
5e681ec4 16308 {
34e77a92 16309 h->root.u.def.section = htab->root.splt;
5e681ec4 16310 h->root.u.def.value = h->plt.offset;
5e681ec4 16311
67d74e43
DJ		 16312 /* Make sure the function is not marked as Thumb, in case
16313 it is the target of an ABS32 relocation, which will
16314 point to the PLT entry. */
39d911fc 16315 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16316 }
022f8312 16317
00a97672
RS		 16318 /* VxWorks executables have a second set of relocations for
16319 each PLT entry. They go in a separate relocation section,
16320 which is processed by the kernel loader. */
0e1862bb 16321 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16322 {
16323 /* There is a relocation for the initial PLT entry:
16324 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16325 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16326 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16327
16328 /* There are two extra relocations for each subsequent
16329 PLT entry: an R_ARM_32 relocation for the GOT entry,
16330 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16331 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16332 }
5e681ec4
PB		 16333 }
16334 else
16335 {
16336 h->plt.offset = (bfd_vma) -1;
f5385ebf 16337 h->needs_plt = 0;
5e681ec4
PB		 16338 }
16339 }
16340 else
16341 {
16342 h->plt.offset = (bfd_vma) -1;
f5385ebf 16343 h->needs_plt = 0;
5e681ec4
PB		 16344 }
16345
0855e32b
NS		 16346 eh = (struct elf32_arm_link_hash_entry *) h;
16347 eh->tlsdesc_got = (bfd_vma) -1;
16348
5e681ec4
PB		 16349 if (h->got.refcount > 0)
16350 {
16351 asection *s;
16352 bfd_boolean dyn;
ba93b8ac
DJ		 16353 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16354 int indx;
5e681ec4
PB		 16355
16356 /* Make sure this symbol is output as a dynamic symbol.
16357 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16358 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16359 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16360 {
c152c796 16361 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16362 return FALSE;
16363 }
16364
e5a52504
MM		 16365 if (!htab->symbian_p)
16366 {
362d30a1 16367 s = htab->root.sgot;
e5a52504 16368 h->got.offset = s->size;
ba93b8ac
DJ		 16369
16370 if (tls_type == GOT_UNKNOWN)
16371 abort ();
16372
16373 if (tls_type == GOT_NORMAL)
16374 /* Non-TLS symbols need one GOT slot. */
16375 s->size += 4;
16376 else
16377 {
99059e56
RM		 16378 if (tls_type & GOT_TLS_GDESC)
16379 {
0855e32b 16380 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16381 eh->tlsdesc_got
0855e32b
NS		 16382 = (htab->root.sgotplt->size
16383 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16384 htab->root.sgotplt->size += 8;
16385 h->got.offset = (bfd_vma) -2;
34e77a92 16386 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16387 reloc in the middle of .got.plt. */
99059e56
RM		 16388 htab->num_tls_desc++;
16389 }
0855e32b 16390
ba93b8ac 16391 if (tls_type & GOT_TLS_GD)
0855e32b 16392 {
5c5a4843
CL		 16393 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16394 consecutive GOT slots. If the symbol is both GD
16395 and GDESC, got.offset may have been
16396 overwritten. */
0855e32b
NS		 16397 h->got.offset = s->size;
16398 s->size += 8;
16399 }
16400
ba93b8ac 16401 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16402 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16403 slot. */
ba93b8ac
DJ		 16404 s->size += 4;
16405 }
16406
e5a52504 16407 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16408
16409 indx = 0;
0e1862bb
L		 16410 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16411 bfd_link_pic (info),
16412 h)
16413 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16414 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16415 indx = h->dynindx;
16416
16417 if (tls_type != GOT_NORMAL
9cb09e33 16418 && (bfd_link_dll (info) || indx != 0)
ba93b8ac
DJ		 16419 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16420 || h->root.type != bfd_link_hash_undefweak))
16421 {
16422 if (tls_type & GOT_TLS_IE)
47beaa6a 16423 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16424
16425 if (tls_type & GOT_TLS_GD)
47beaa6a 16426 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16427
b38cadfb 16428 if (tls_type & GOT_TLS_GDESC)
0855e32b 16429 {
47beaa6a 16430 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16431 /* GDESC needs a trampoline to jump to. */
16432 htab->tls_trampoline = -1;
16433 }
16434
16435 /* Only GD needs it. GDESC just emits one relocation per
16436 2 entries. */
b38cadfb 16437 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16438 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16439 }
e8b09b87
CL		 16440 else if (((indx != -1) || htab->fdpic_p)
16441 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16442 {
16443 if (htab->root.dynamic_sections_created)
16444 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16445 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16446 }
34e77a92
RS		 16447 else if (h->type == STT_GNU_IFUNC
16448 && eh->plt.noncall_refcount == 0)
16449 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16450 they all resolve dynamically instead. Reserve room for the
16451 GOT entry's R_ARM_IRELATIVE relocation. */
16452 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb 16453 else if (bfd_link_pic (info)
7f026732 16454 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
b436d854 16455 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16456 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16457 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16458 /* Reserve room for rofixup for FDPIC executable. */
16459 /* TLS relocs do not need space since they are completely
16460 resolved. */
16461 htab->srofixup->size += 4;
e5a52504 16462 }
5e681ec4
PB		 16463 }
16464 else
16465 h->got.offset = (bfd_vma) -1;
16466
e8b09b87
CL		 16467 /* FDPIC support. */
16468 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16469 {
16470 /* Symbol musn't be exported. */
16471 if (h->dynindx != -1)
16472 abort();
16473
16474 /* We only allocate one function descriptor with its associated relocation. */
16475 if (eh->fdpic_cnts.funcdesc_offset == -1)
16476 {
16477 asection *s = htab->root.sgot;
16478
16479 eh->fdpic_cnts.funcdesc_offset = s->size;
16480 s->size += 8;
16481 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16482 if (bfd_link_pic(info))
16483 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16484 else
16485 htab->srofixup->size += 8;
16486 }
16487 }
16488
16489 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16490 {
16491 asection *s = htab->root.sgot;
16492
16493 if (htab->root.dynamic_sections_created && h->dynindx == -1
16494 && !h->forced_local)
16495 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16496 return FALSE;
16497
16498 if (h->dynindx == -1)
16499 {
16500 /* We only allocate one function descriptor with its associated relocation. q */
16501 if (eh->fdpic_cnts.funcdesc_offset == -1)
16502 {
16503
16504 eh->fdpic_cnts.funcdesc_offset = s->size;
16505 s->size += 8;
16506 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16507 if (bfd_link_pic(info))
16508 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16509 else
16510 htab->srofixup->size += 8;
16511 }
16512 }
16513
16514 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16515 R_ARM_RELATIVE/rofixup relocation on it. */
16516 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16517 s->size += 4;
16518 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16519 htab->srofixup->size += 4;
e8b09b87 16520 else
4b24dd1a 16521 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16522 }
16523
16524 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16525 {
16526 if (htab->root.dynamic_sections_created && h->dynindx == -1
16527 && !h->forced_local)
16528 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16529 return FALSE;
16530
16531 if (h->dynindx == -1)
16532 {
16533 /* We only allocate one function descriptor with its associated relocation. */
16534 if (eh->fdpic_cnts.funcdesc_offset == -1)
16535 {
16536 asection *s = htab->root.sgot;
16537
16538 eh->fdpic_cnts.funcdesc_offset = s->size;
16539 s->size += 8;
16540 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16541 if (bfd_link_pic(info))
16542 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16543 else
16544 htab->srofixup->size += 8;
16545 }
16546 }
16547 if (h->dynindx == -1 && !bfd_link_pic(info))
16548 {
16549 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16550 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16551 }
16552 else
16553 {
16554 /* Will need one dynamic reloc per reference. will be either
16555 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16556 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16557 eh->fdpic_cnts.funcdesc_cnt);
16558 }
16559 }
16560
a4fd1a8e
PB		 16561 /* Allocate stubs for exported Thumb functions on v4t. */
16562 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16563 && h->def_regular
39d911fc 16564 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16565 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16566 {
16567 struct elf_link_hash_entry * th;
16568 struct bfd_link_hash_entry * bh;
16569 struct elf_link_hash_entry * myh;
16570 char name[1024];
16571 asection *s;
16572 bh = NULL;
16573 /* Create a new symbol to regist the real location of the function. */
16574 s = h->root.u.def.section;
906e58ca 16575 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16576 _bfd_generic_link_add_one_symbol (info, s->owner,
16577 name, BSF_GLOBAL, s,
16578 h->root.u.def.value,
16579 NULL, TRUE, FALSE, &bh);
16580
16581 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16582 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16583 myh->forced_local = 1;
39d911fc 16584 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16585 eh->export_glue = myh;
16586 th = record_arm_to_thumb_glue (info, h);
16587 /* Point the symbol at the stub. */
16588 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16589 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16590 h->root.u.def.section = th->root.u.def.section;
16591 h->root.u.def.value = th->root.u.def.value & ~1;
16592 }
16593
0bdcacaf 16594 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16595 return TRUE;
16596
16597 /* In the shared -Bsymbolic case, discard space allocated for
16598 dynamic pc-relative relocs against symbols which turn out to be
16599 defined in regular objects. For the normal shared case, discard
16600 space for pc-relative relocs that have become local due to symbol
16601 visibility changes. */
16602
e8b09b87 16603 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16604 {
469a3493
RM		 16605 /* Relocs that use pc_count are PC-relative forms, which will appear
16606 on something like ".long foo - ." or "movw REG, foo - .". We want
16607 calls to protected symbols to resolve directly to the function
16608 rather than going via the plt. If people want function pointer
16609 comparisons to work as expected then they should avoid writing
16610 assembly like ".long foo - .". */
ba93b8ac
DJ		 16611 if (SYMBOL_CALLS_LOCAL (info, h))
16612 {
0bdcacaf 16613 struct elf_dyn_relocs **pp;
ba93b8ac 16614
0bdcacaf 16615 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16616 {
16617 p->count -= p->pc_count;
16618 p->pc_count = 0;
16619 if (p->count == 0)
16620 *pp = p->next;
16621 else
16622 pp = &p->next;
16623 }
16624 }
16625
4dfe6ac6 16626 if (htab->vxworks_p)
3348747a 16627 {
0bdcacaf 16628 struct elf_dyn_relocs **pp;
3348747a 16629
0bdcacaf 16630 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16631 {
0bdcacaf 16632 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16633 *pp = p->next;
16634 else
16635 pp = &p->next;
16636 }
16637 }
16638
ba93b8ac 16639 /* Also discard relocs on undefined weak syms with non-default
99059e56 16640 visibility. */
0bdcacaf 16641 if (eh->dyn_relocs != NULL
5e681ec4 16642 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16643 {
95b03e4a
L		 16644 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16645 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16646 eh->dyn_relocs = NULL;
22d606e9
AM		 16647
16648 /* Make sure undefined weak symbols are output as a dynamic
16649 symbol in PIEs. */
e8b09b87 16650 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16651 && !h->forced_local)
16652 {
16653 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16654 return FALSE;
16655 }
16656 }
16657
67687978
PB		 16658 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16659 && h->root.type == bfd_link_hash_new)
16660 {
16661 /* Output absolute symbols so that we can create relocations
16662 against them. For normal symbols we output a relocation
16663 against the section that contains them. */
16664 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16665 return FALSE;
16666 }
16667
5e681ec4
PB		 16668 }
16669 else
16670 {
16671 /* For the non-shared case, discard space for relocs against
16672 symbols which turn out to need copy relocs or are not
16673 dynamic. */
16674
f5385ebf
AM		 16675 if (!h->non_got_ref
16676 && ((h->def_dynamic
16677 && !h->def_regular)
5e681ec4
PB		 16678 || (htab->root.dynamic_sections_created
16679 && (h->root.type == bfd_link_hash_undefweak
16680 || h->root.type == bfd_link_hash_undefined))))
16681 {
16682 /* Make sure this symbol is output as a dynamic symbol.
16683 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16684 if (h->dynindx == -1 && !h->forced_local
16685 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16686 {
c152c796 16687 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16688 return FALSE;
16689 }
16690
16691 /* If that succeeded, we know we'll be keeping all the
16692 relocs. */
16693 if (h->dynindx != -1)
16694 goto keep;
16695 }
16696
0bdcacaf 16697 eh->dyn_relocs = NULL;
5e681ec4
PB		 16698
16699 keep: ;
16700 }
16701
16702 /* Finally, allocate space. */
0bdcacaf 16703 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16704 {
0bdcacaf 16705 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16706
34e77a92
RS		 16707 if (h->type == STT_GNU_IFUNC
16708 && eh->plt.noncall_refcount == 0
16709 && SYMBOL_REFERENCES_LOCAL (info, h))
16710 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16711 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16712 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16713 else if (htab->fdpic_p && !bfd_link_pic(info))
16714 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16715 else
16716 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16717 }
16718
16719 return TRUE;
16720}
16721
63c1f59d
AM		 16722/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16723 read-only sections. */
08d1f311
DJ		 16724
16725static bfd_boolean
63c1f59d 16726maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16727{
63c1f59d 16728 asection *sec;
08d1f311 16729
63c1f59d
AM		 16730 if (h->root.type == bfd_link_hash_indirect)
16731 return TRUE;
08d1f311 16732
63c1f59d
AM		 16733 sec = readonly_dynrelocs (h);
16734 if (sec != NULL)
16735 {
16736 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16737
63c1f59d
AM		 16738 info->flags |= DF_TEXTREL;
16739 info->callbacks->minfo
c1c8c1ef 16740 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16741 sec->owner, h->root.root.string, sec);
08d1f311 16742
63c1f59d
AM		 16743 /* Not an error, just cut short the traversal. */
16744 return FALSE;
08d1f311 16745 }
cb10292c 16746
08d1f311
DJ		 16747 return TRUE;
16748}
16749
d504ffc8
DJ		 16750void
16751bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16752 int byteswap_code)
16753{
16754 struct elf32_arm_link_hash_table *globals;
16755
16756 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16757 if (globals == NULL)
16758 return;
16759
d504ffc8
DJ		 16760 globals->byteswap_code = byteswap_code;
16761}
16762
252b5132
RH		 16763/* Set the sizes of the dynamic sections. */
16764
b34976b6 16765static bfd_boolean
57e8b36a
NC		 16766elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16767 struct bfd_link_info * info)
252b5132
RH		 16768{
16769 bfd * dynobj;
16770 asection * s;
b34976b6
AM		 16771 bfd_boolean plt;
16772 bfd_boolean relocs;
5e681ec4
PB		 16773 bfd *ibfd;
16774 struct elf32_arm_link_hash_table *htab;
252b5132 16775
5e681ec4 16776 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16777 if (htab == NULL)
16778 return FALSE;
16779
252b5132
RH		 16780 dynobj = elf_hash_table (info)->dynobj;
16781 BFD_ASSERT (dynobj != NULL);
39b41c9c 16782 check_use_blx (htab);
252b5132
RH		 16783
16784 if (elf_hash_table (info)->dynamic_sections_created)
16785 {
16786 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16787 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16788 {
3d4d4302 16789 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16790 BFD_ASSERT (s != NULL);
eea6121a 16791 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16792 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16793 }
16794 }
5e681ec4
PB		 16795
16796 /* Set up .got offsets for local syms, and space for local dynamic
16797 relocs. */
c72f2fb2 16798 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16799 {
5e681ec4
PB		 16800 bfd_signed_vma *local_got;
16801 bfd_signed_vma *end_local_got;
34e77a92 16802 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16803 char *local_tls_type;
0855e32b 16804 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16805 bfd_size_type locsymcount;
16806 Elf_Internal_Shdr *symtab_hdr;
16807 asection *srel;
4dfe6ac6 16808 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16809 unsigned int symndx;
e8b09b87 16810 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16811
0ffa91dd 16812 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16813 continue;
16814
16815 for (s = ibfd->sections; s != NULL; s = s->next)
16816 {
0bdcacaf 16817 struct elf_dyn_relocs *p;
5e681ec4 16818
0bdcacaf 16819 for (p = (struct elf_dyn_relocs *)
99059e56 16820 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16821 {
0bdcacaf
RS		 16822 if (!bfd_is_abs_section (p->sec)
16823 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16824 {
16825 /* Input section has been discarded, either because
16826 it is a copy of a linkonce section or due to
16827 linker script /DISCARD/, so we'll be discarding
16828 the relocs too. */
16829 }
3348747a 16830 else if (is_vxworks
0bdcacaf 16831 && strcmp (p->sec->output_section->name,
3348747a
NS		 16832 ".tls_vars") == 0)
16833 {
16834 /* Relocations in vxworks .tls_vars sections are
16835 handled specially by the loader. */
16836 }
5e681ec4
PB		 16837 else if (p->count != 0)
16838 {
0bdcacaf 16839 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16840 if (htab->fdpic_p && !bfd_link_pic(info))
16841 htab->srofixup->size += 4 * p->count;
16842 else
16843 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16844 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16845 info->flags |= DF_TEXTREL;
16846 }
16847 }
16848 }
16849
16850 local_got = elf_local_got_refcounts (ibfd);
16851 if (!local_got)
16852 continue;
16853
0ffa91dd 16854 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16855 locsymcount = symtab_hdr->sh_info;
16856 end_local_got = local_got + locsymcount;
34e77a92 16857 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16858 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16859 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16860 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16861 symndx = 0;
362d30a1
RS		 16862 s = htab->root.sgot;
16863 srel = htab->root.srelgot;
0855e32b 16864 for (; local_got < end_local_got;
34e77a92 16865 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16866 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16867 {
0855e32b 16868 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16869 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16870
16871 /* FDPIC support. */
16872 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16873 {
16874 if (local_fdpic_cnts->funcdesc_offset == -1)
16875 {
16876 local_fdpic_cnts->funcdesc_offset = s->size;
16877 s->size += 8;
16878
16879 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16880 if (bfd_link_pic(info))
16881 elf32_arm_allocate_dynrelocs (info, srel, 1);
16882 else
16883 htab->srofixup->size += 8;
16884 }
16885 }
16886
16887 if (local_fdpic_cnts->funcdesc_cnt > 0)
16888 {
16889 if (local_fdpic_cnts->funcdesc_offset == -1)
16890 {
16891 local_fdpic_cnts->funcdesc_offset = s->size;
16892 s->size += 8;
16893
16894 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16895 if (bfd_link_pic(info))
16896 elf32_arm_allocate_dynrelocs (info, srel, 1);
16897 else
16898 htab->srofixup->size += 8;
16899 }
16900
16901 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16902 if (bfd_link_pic(info))
16903 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16904 else
16905 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16906 }
16907
34e77a92
RS		 16908 if (local_iplt != NULL)
16909 {
16910 struct elf_dyn_relocs *p;
16911
16912 if (local_iplt->root.refcount > 0)
16913 {
16914 elf32_arm_allocate_plt_entry (info, TRUE,
16915 &local_iplt->root,
16916 &local_iplt->arm);
16917 if (local_iplt->arm.noncall_refcount == 0)
16918 /* All references to the PLT are calls, so all
16919 non-call references can resolve directly to the
16920 run-time target. This means that the .got entry
16921 would be the same as the .igot.plt entry, so there's
16922 no point creating both. */
16923 *local_got = 0;
16924 }
16925 else
16926 {
16927 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16928 local_iplt->root.offset = (bfd_vma) -1;
16929 }
16930
16931 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16932 {
16933 asection *psrel;
16934
16935 psrel = elf_section_data (p->sec)->sreloc;
16936 if (local_iplt->arm.noncall_refcount == 0)
16937 elf32_arm_allocate_irelocs (info, psrel, p->count);
16938 else
16939 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16940 }
16941 }
5e681ec4
PB		 16942 if (*local_got > 0)
16943 {
34e77a92
RS		 16944 Elf_Internal_Sym *isym;
16945
eea6121a 16946 *local_got = s->size;
ba93b8ac
DJ		 16947 if (*local_tls_type & GOT_TLS_GD)
16948 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16949 s->size += 8;
0855e32b
NS		 16950 if (*local_tls_type & GOT_TLS_GDESC)
16951 {
16952 *local_tlsdesc_gotent = htab->root.sgotplt->size
16953 - elf32_arm_compute_jump_table_size (htab);
16954 htab->root.sgotplt->size += 8;
16955 *local_got = (bfd_vma) -2;
34e77a92 16956 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16957 reloc in the middle of .got.plt. */
99059e56 16958 htab->num_tls_desc++;
0855e32b 16959 }
ba93b8ac
DJ		 16960 if (*local_tls_type & GOT_TLS_IE)
16961 s->size += 4;
ba93b8ac 16962
0855e32b
NS		 16963 if (*local_tls_type & GOT_NORMAL)
16964 {
16965 /* If the symbol is both GD and GDESC, *local_got
16966 may have been overwritten. */
16967 *local_got = s->size;
16968 s->size += 4;
16969 }
16970
34e77a92
RS		 16971 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
16972 if (isym == NULL)
16973 return FALSE;
16974
16975 /* If all references to an STT_GNU_IFUNC PLT are calls,
16976 then all non-call references, including this GOT entry,
16977 resolve directly to the run-time target. */
16978 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16979 && (local_iplt == NULL
16980 || local_iplt->arm.noncall_refcount == 0))
16981 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16982 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16983 {
e8b09b87 16984 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16985 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16986 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16987 htab->srofixup->size += 4;
99059e56 16988
e8b09b87
CL		 16989 if ((bfd_link_pic (info) || htab->fdpic_p)
16990 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16991 {
16992 elf32_arm_allocate_dynrelocs (info,
16993 htab->root.srelplt, 1);
16994 htab->tls_trampoline = -1;
16995 }
0855e32b 16996 }
5e681ec4
PB		 16997 }
16998 else
16999 *local_got = (bfd_vma) -1;
17000 }
252b5132
RH		 17001 }
17002
ba93b8ac
DJ		 17003 if (htab->tls_ldm_got.refcount > 0)
17004 {
17005 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 17006 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 17007 htab->tls_ldm_got.offset = htab->root.sgot->size;
17008 htab->root.sgot->size += 8;
0e1862bb 17009 if (bfd_link_pic (info))
47beaa6a 17010 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 17011 }
17012 else
17013 htab->tls_ldm_got.offset = -1;
17014
e8b09b87
CL		 17015 /* At the very end of the .rofixup section is a pointer to the GOT,
17016 reserve space for it. */
17017 if (htab->fdpic_p && htab->srofixup != NULL)
17018 htab->srofixup->size += 4;
17019
5e681ec4
PB		 17020 /* Allocate global sym .plt and .got entries, and space for global
17021 sym dynamic relocs. */
47beaa6a 17022 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 17023
d504ffc8 17024 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 17025 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 17026 {
0ffa91dd 17027 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 17028 continue;
17029
c7b8f16e
JB		 17030 /* Initialise mapping tables for code/data. */
17031 bfd_elf32_arm_init_maps (ibfd);
906e58ca 17032
c7b8f16e 17033 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 17034 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
17035 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 17036 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 17037 }
d504ffc8 17038
3e6b1042
DJ		 17039 /* Allocate space for the glue sections now that we've sized them. */
17040 bfd_elf32_arm_allocate_interworking_sections (info);
17041
0855e32b
NS		 17042 /* For every jump slot reserved in the sgotplt, reloc_count is
17043 incremented. However, when we reserve space for TLS descriptors,
17044 it's not incremented, so in order to compute the space reserved
17045 for them, it suffices to multiply the reloc count by the jump
17046 slot size. */
17047 if (htab->root.srelplt)
17048 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
17049
17050 if (htab->tls_trampoline)
17051 {
17052 if (htab->root.splt->size == 0)
17053 htab->root.splt->size += htab->plt_header_size;
b38cadfb 17054
0855e32b
NS		 17055 htab->tls_trampoline = htab->root.splt->size;
17056 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 17057
0855e32b 17058 /* If we're not using lazy TLS relocations, don't generate the
99059e56 17059 PLT and GOT entries they require. */
0855e32b
NS		 17060 if (!(info->flags & DF_BIND_NOW))
17061 {
17062 htab->dt_tlsdesc_got = htab->root.sgot->size;
17063 htab->root.sgot->size += 4;
17064
17065 htab->dt_tlsdesc_plt = htab->root.splt->size;
17066 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
17067 }
17068 }
17069
252b5132
RH		 17070 /* The check_relocs and adjust_dynamic_symbol entry points have
17071 determined the sizes of the various dynamic sections. Allocate
17072 memory for them. */
b34976b6
AM		 17073 plt = FALSE;
17074 relocs = FALSE;
252b5132
RH		 17075 for (s = dynobj->sections; s != NULL; s = s->next)
17076 {
17077 const char * name;
252b5132
RH		 17078
17079 if ((s->flags & SEC_LINKER_CREATED) == 0)
17080 continue;
17081
17082 /* It's OK to base decisions on the section name, because none
17083 of the dynobj section names depend upon the input files. */
fd361982 17084 name = bfd_section_name (s);
252b5132 17085
34e77a92 17086 if (s == htab->root.splt)
252b5132 17087 {
c456f082
AM		 17088 /* Remember whether there is a PLT. */
17089 plt = s->size != 0;
252b5132 17090 }
0112cd26 17091 else if (CONST_STRNEQ (name, ".rel"))
252b5132 17092 {
c456f082 17093 if (s->size != 0)
252b5132 17094 {
252b5132 17095 /* Remember whether there are any reloc sections other
00a97672 17096 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17097 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17098 relocs = TRUE;
252b5132
RH		 17099
17100 /* We use the reloc_count field as a counter if we need
17101 to copy relocs into the output file. */
17102 s->reloc_count = 0;
17103 }
17104 }
34e77a92
RS		 17105 else if (s != htab->root.sgot
17106 && s != htab->root.sgotplt
17107 && s != htab->root.iplt
17108 && s != htab->root.igotplt
5474d94f 17109 && s != htab->root.sdynbss
e8b09b87
CL		 17110 && s != htab->root.sdynrelro
17111 && s != htab->srofixup)
252b5132
RH		 17112 {
17113 /* It's not one of our sections, so don't allocate space. */
17114 continue;
17115 }
17116
c456f082 17117 if (s->size == 0)
252b5132 17118 {
c456f082 17119 /* If we don't need this section, strip it from the
00a97672
RS		 17120 output file. This is mostly to handle .rel(a).bss and
17121 .rel(a).plt. We must create both sections in
c456f082
AM		 17122 create_dynamic_sections, because they must be created
17123 before the linker maps input sections to output
17124 sections. The linker does that before
17125 adjust_dynamic_symbol is called, and it is that
17126 function which decides whether anything needs to go
17127 into these sections. */
8423293d 17128 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17129 continue;
17130 }
17131
c456f082
AM		 17132 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17133 continue;
17134
252b5132 17135 /* Allocate memory for the section contents. */
21d799b5 17136 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17137 if (s->contents == NULL)
b34976b6 17138 return FALSE;
252b5132
RH		 17139 }
17140
17141 if (elf_hash_table (info)->dynamic_sections_created)
17142 {
17143 /* Add some entries to the .dynamic section. We fill in the
17144 values later, in elf32_arm_finish_dynamic_sections, but we
17145 must add the entries now so that we get the correct size for
17146 the .dynamic section. The DT_DEBUG entry is filled in by the
17147 dynamic linker and used by the debugger. */
dc810e39 17148#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17149 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17150
0e1862bb 17151 if (bfd_link_executable (info))
252b5132 17152 {
dc810e39 17153 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17154 return FALSE;
252b5132
RH		 17155 }
17156
17157 if (plt)
17158 {
dc810e39
AM		 17159 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17160 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17161 || !add_dynamic_entry (DT_PLTREL,
17162 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17163 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17164 return FALSE;
0855e32b 17165
5025eb7c
AO		 17166 if (htab->dt_tlsdesc_plt
17167 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17168 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17169 return FALSE;
252b5132
RH		 17170 }
17171
17172 if (relocs)
17173 {
00a97672
RS		 17174 if (htab->use_rel)
17175 {
17176 if (!add_dynamic_entry (DT_REL, 0)
17177 || !add_dynamic_entry (DT_RELSZ, 0)
17178 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17179 return FALSE;
17180 }
17181 else
17182 {
17183 if (!add_dynamic_entry (DT_RELA, 0)
17184 || !add_dynamic_entry (DT_RELASZ, 0)
17185 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17186 return FALSE;
17187 }
252b5132
RH		 17188 }
17189
08d1f311
DJ		 17190 /* If any dynamic relocs apply to a read-only section,
17191 then we need a DT_TEXTREL entry. */
17192 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17193 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17194
99e4ae17 17195 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17196 {
dc810e39 17197 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17198 return FALSE;
252b5132 17199 }
7a2b07ff
NS		 17200 if (htab->vxworks_p
17201 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17202 return FALSE;
252b5132 17203 }
8532796c 17204#undef add_dynamic_entry
252b5132 17205
b34976b6 17206 return TRUE;
252b5132
RH		 17207}
17208
0855e32b
NS		 17209/* Size sections even though they're not dynamic. We use it to setup
17210 _TLS_MODULE_BASE_, if needed. */
17211
17212static bfd_boolean
17213elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17214 struct bfd_link_info *info)
0855e32b
NS		 17215{
17216 asection *tls_sec;
cb10292c
CL		 17217 struct elf32_arm_link_hash_table *htab;
17218
17219 htab = elf32_arm_hash_table (info);
0855e32b 17220
0e1862bb 17221 if (bfd_link_relocatable (info))
0855e32b
NS		 17222 return TRUE;
17223
17224 tls_sec = elf_hash_table (info)->tls_sec;
17225
17226 if (tls_sec)
17227 {
17228 struct elf_link_hash_entry *tlsbase;
17229
17230 tlsbase = elf_link_hash_lookup
17231 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17232
17233 if (tlsbase)
99059e56
RM		 17234 {
17235 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17236 const struct elf_backend_data *bed
99059e56 17237 = get_elf_backend_data (output_bfd);
0855e32b 17238
99059e56 17239 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17240 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17241 tls_sec, 0, NULL, FALSE,
17242 bed->collect, &bh)))
17243 return FALSE;
b38cadfb 17244
99059e56
RM		 17245 tlsbase->type = STT_TLS;
17246 tlsbase = (struct elf_link_hash_entry *)bh;
17247 tlsbase->def_regular = 1;
17248 tlsbase->other = STV_HIDDEN;
17249 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17250 }
17251 }
cb10292c
CL		 17252
17253 if (htab->fdpic_p && !bfd_link_relocatable (info)
17254 && !bfd_elf_stack_segment_size (output_bfd, info,
17255 "__stacksize", DEFAULT_STACK_SIZE))
17256 return FALSE;
17257
0855e32b
NS		 17258 return TRUE;
17259}
17260
252b5132
RH		 17261/* Finish up dynamic symbol handling. We set the contents of various
17262 dynamic sections here. */
17263
b34976b6 17264static bfd_boolean
906e58ca
NC		 17265elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17266 struct bfd_link_info * info,
17267 struct elf_link_hash_entry * h,
17268 Elf_Internal_Sym * sym)
252b5132 17269{
e5a52504 17270 struct elf32_arm_link_hash_table *htab;
b7693d02 17271 struct elf32_arm_link_hash_entry *eh;
252b5132 17272
e5a52504 17273 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17274 if (htab == NULL)
17275 return FALSE;
17276
b7693d02 17277 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17278
17279 if (h->plt.offset != (bfd_vma) -1)
17280 {
34e77a92 17281 if (!eh->is_iplt)
e5a52504 17282 {
34e77a92 17283 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17284 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17285 h->dynindx, 0))
17286 return FALSE;
e5a52504 17287 }
57e8b36a 17288
f5385ebf 17289 if (!h->def_regular)
252b5132
RH		 17290 {
17291 /* Mark the symbol as undefined, rather than as defined in
3a635617 17292 the .plt section. */
252b5132 17293 sym->st_shndx = SHN_UNDEF;
3a635617 17294 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17295 Otherwise, the PLT entry would provide a definition for
17296 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17297 and so the symbol would never be NULL. Leave the value if
17298 there were any relocations where pointer equality matters
17299 (this is a clue for the dynamic linker, to make function
17300 pointer comparisons work between an application and shared
17301 library). */
97323ad1 17302 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17303 sym->st_value = 0;
252b5132 17304 }
34e77a92
RS		 17305 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17306 {
17307 /* At least one non-call relocation references this .iplt entry,
17308 so the .iplt entry is the function's canonical address. */
17309 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17310 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17311 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17312 (output_bfd, htab->root.iplt->output_section));
17313 sym->st_value = (h->plt.offset
17314 + htab->root.iplt->output_section->vma
17315 + htab->root.iplt->output_offset);
17316 }
252b5132
RH		 17317 }
17318
f5385ebf 17319 if (h->needs_copy)
252b5132
RH		 17320 {
17321 asection * s;
947216bf 17322 Elf_Internal_Rela rel;
252b5132
RH		 17323
17324 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17325 BFD_ASSERT (h->dynindx != -1
17326 && (h->root.type == bfd_link_hash_defined
17327 || h->root.type == bfd_link_hash_defweak));
17328
00a97672 17329 rel.r_addend = 0;
252b5132
RH		 17330 rel.r_offset = (h->root.u.def.value
17331 + h->root.u.def.section->output_section->vma
17332 + h->root.u.def.section->output_offset);
17333 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17334 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17335 s = htab->root.sreldynrelro;
17336 else
17337 s = htab->root.srelbss;
47beaa6a 17338 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17339 }
17340
00a97672 17341 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17342 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17343 it is relative to the ".got" section. */
9637f6ef 17344 if (h == htab->root.hdynamic
fac7bd64 17345 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17346 sym->st_shndx = SHN_ABS;
17347
b34976b6 17348 return TRUE;
252b5132
RH		 17349}
17350
0855e32b
NS		 17351static void
17352arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17353 void *contents,
17354 const unsigned long *template, unsigned count)
17355{
17356 unsigned ix;
b38cadfb 17357
0855e32b
NS		 17358 for (ix = 0; ix != count; ix++)
17359 {
17360 unsigned long insn = template[ix];
17361
17362 /* Emit mov pc,rx if bx is not permitted. */
17363 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17364 insn = (insn & 0xf000000f) | 0x01a0f000;
17365 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17366 }
17367}
17368
99059e56
RM		 17369/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17370 other variants, NaCl needs this entry in a static executable's
17371 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17372 zero. For .iplt really only the last bundle is useful, and .iplt
17373 could have a shorter first entry, with each individual PLT entry's
17374 relative branch calculated differently so it targets the last
17375 bundle instead of the instruction before it (labelled .Lplt_tail
17376 above). But it's simpler to keep the size and layout of PLT0
17377 consistent with the dynamic case, at the cost of some dead code at
17378 the start of .iplt and the one dead store to the stack at the start
17379 of .Lplt_tail. */
17380static void
17381arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17382 asection *plt, bfd_vma got_displacement)
17383{
17384 unsigned int i;
17385
17386 put_arm_insn (htab, output_bfd,
17387 elf32_arm_nacl_plt0_entry[0]
17388 | arm_movw_immediate (got_displacement),
17389 plt->contents + 0);
17390 put_arm_insn (htab, output_bfd,
17391 elf32_arm_nacl_plt0_entry[1]
17392 | arm_movt_immediate (got_displacement),
17393 plt->contents + 4);
17394
17395 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17396 put_arm_insn (htab, output_bfd,
17397 elf32_arm_nacl_plt0_entry[i],
17398 plt->contents + (i * 4));
17399}
17400
252b5132
RH		 17401/* Finish up the dynamic sections. */
17402
b34976b6 17403static bfd_boolean
57e8b36a 17404elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17405{
17406 bfd * dynobj;
17407 asection * sgot;
17408 asection * sdyn;
4dfe6ac6
NC		 17409 struct elf32_arm_link_hash_table *htab;
17410
17411 htab = elf32_arm_hash_table (info);
17412 if (htab == NULL)
17413 return FALSE;
252b5132
RH		 17414
17415 dynobj = elf_hash_table (info)->dynobj;
17416
362d30a1 17417 sgot = htab->root.sgotplt;
894891db
NC		 17418 /* A broken linker script might have discarded the dynamic sections.
17419 Catch this here so that we do not seg-fault later on. */
17420 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17421 return FALSE;
3d4d4302 17422 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17423
17424 if (elf_hash_table (info)->dynamic_sections_created)
17425 {
17426 asection *splt;
17427 Elf32_External_Dyn *dyncon, *dynconend;
17428
362d30a1 17429 splt = htab->root.splt;
24a1ba0f 17430 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17431 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17432
17433 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17434 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17435
252b5132
RH		 17436 for (; dyncon < dynconend; dyncon++)
17437 {
17438 Elf_Internal_Dyn dyn;
17439 const char * name;
17440 asection * s;
17441
17442 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17443
17444 switch (dyn.d_tag)
17445 {
229fcec5
MM		 17446 unsigned int type;
17447
252b5132 17448 default:
7a2b07ff
NS		 17449 if (htab->vxworks_p
17450 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17451 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17452 break;
17453
229fcec5
MM		 17454 case DT_HASH:
17455 name = ".hash";
17456 goto get_vma_if_bpabi;
17457 case DT_STRTAB:
17458 name = ".dynstr";
17459 goto get_vma_if_bpabi;
17460 case DT_SYMTAB:
17461 name = ".dynsym";
17462 goto get_vma_if_bpabi;
c0042f5d
MM		 17463 case DT_VERSYM:
17464 name = ".gnu.version";
17465 goto get_vma_if_bpabi;
17466 case DT_VERDEF:
17467 name = ".gnu.version_d";
17468 goto get_vma_if_bpabi;
17469 case DT_VERNEED:
17470 name = ".gnu.version_r";
17471 goto get_vma_if_bpabi;
17472
252b5132 17473 case DT_PLTGOT:
4ade44b7 17474 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17475 goto get_vma;
17476 case DT_JMPREL:
00a97672 17477 name = RELOC_SECTION (htab, ".plt");
252b5132 17478 get_vma:
4ade44b7 17479 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17480 if (s == NULL)
17481 {
4eca0228 17482 _bfd_error_handler
4ade44b7 17483 (_("could not find section %s"), name);
05456594
NC		 17484 bfd_set_error (bfd_error_invalid_operation);
17485 return FALSE;
17486 }
229fcec5 17487 if (!htab->symbian_p)
4ade44b7 17488 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17489 else
17490 /* In the BPABI, tags in the PT_DYNAMIC section point
17491 at the file offset, not the memory address, for the
17492 convenience of the post linker. */
4ade44b7 17493 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17494 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17495 break;
17496
229fcec5
MM		 17497 get_vma_if_bpabi:
17498 if (htab->symbian_p)
17499 goto get_vma;
17500 break;
17501
252b5132 17502 case DT_PLTRELSZ:
362d30a1 17503 s = htab->root.srelplt;
252b5132 17504 BFD_ASSERT (s != NULL);
eea6121a 17505 dyn.d_un.d_val = s->size;
252b5132
RH		 17506 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17507 break;
906e58ca 17508
252b5132 17509 case DT_RELSZ:
00a97672 17510 case DT_RELASZ:
229fcec5
MM		 17511 case DT_REL:
17512 case DT_RELA:
229fcec5
MM		 17513 /* In the BPABI, the DT_REL tag must point at the file
17514 offset, not the VMA, of the first relocation
17515 section. So, we use code similar to that in
17516 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17517 relocation section, since relocation sections are
17518 never allocated under the BPABI. PLT relocs are also
17519 included. */
229fcec5
MM		 17520 if (htab->symbian_p)
17521 {
17522 unsigned int i;
17523 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17524 ? SHT_REL : SHT_RELA);
17525 dyn.d_un.d_val = 0;
17526 for (i = 1; i < elf_numsections (output_bfd); i++)
17527 {
906e58ca 17528 Elf_Internal_Shdr *hdr
229fcec5
MM		 17529 = elf_elfsections (output_bfd)[i];
17530 if (hdr->sh_type == type)
17531 {
906e58ca 17532 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17533 || dyn.d_tag == DT_RELASZ)
17534 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17535 else if ((ufile_ptr) hdr->sh_offset
17536 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17537 dyn.d_un.d_val = hdr->sh_offset;
17538 }
17539 }
17540 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17541 }
252b5132 17542 break;
88f7bcd5 17543
0855e32b 17544 case DT_TLSDESC_PLT:
99059e56 17545 s = htab->root.splt;
0855e32b
NS		 17546 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17547 + htab->dt_tlsdesc_plt);
17548 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17549 break;
17550
17551 case DT_TLSDESC_GOT:
99059e56 17552 s = htab->root.sgot;
0855e32b 17553 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17554 + htab->dt_tlsdesc_got);
0855e32b
NS		 17555 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17556 break;
17557
88f7bcd5
NC		 17558 /* Set the bottom bit of DT_INIT/FINI if the
17559 corresponding function is Thumb. */
17560 case DT_INIT:
17561 name = info->init_function;
17562 goto get_sym;
17563 case DT_FINI:
17564 name = info->fini_function;
17565 get_sym:
17566 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17567 then there is nothing to adjust. */
88f7bcd5
NC		 17568 if (dyn.d_un.d_val != 0)
17569 {
17570 struct elf_link_hash_entry * eh;
17571
17572 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17573 FALSE, FALSE, TRUE);
39d911fc
TP		 17574 if (eh != NULL
17575 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17576 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17577 {
17578 dyn.d_un.d_val |= 1;
b34976b6 17579 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17580 }
17581 }
17582 break;
252b5132
RH		 17583 }
17584 }
17585
24a1ba0f 17586 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17587 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17588 {
00a97672
RS		 17589 const bfd_vma *plt0_entry;
17590 bfd_vma got_address, plt_address, got_displacement;
17591
17592 /* Calculate the addresses of the GOT and PLT. */
17593 got_address = sgot->output_section->vma + sgot->output_offset;
17594 plt_address = splt->output_section->vma + splt->output_offset;
17595
17596 if (htab->vxworks_p)
17597 {
17598 /* The VxWorks GOT is relocated by the dynamic linker.
17599 Therefore, we must emit relocations rather than simply
17600 computing the values now. */
17601 Elf_Internal_Rela rel;
17602
17603 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17604 put_arm_insn (htab, output_bfd, plt0_entry[0],
17605 splt->contents + 0);
17606 put_arm_insn (htab, output_bfd, plt0_entry[1],
17607 splt->contents + 4);
17608 put_arm_insn (htab, output_bfd, plt0_entry[2],
17609 splt->contents + 8);
00a97672
RS		 17610 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17611
8029a119 17612 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17613 rel.r_offset = plt_address + 12;
17614 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17615 rel.r_addend = 0;
17616 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17617 htab->srelplt2->contents);
17618 }
b38cadfb 17619 else if (htab->nacl_p)
99059e56
RM		 17620 arm_nacl_put_plt0 (htab, output_bfd, splt,
17621 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17622 else if (using_thumb_only (htab))
17623 {
17624 got_displacement = got_address - (plt_address + 12);
17625
17626 plt0_entry = elf32_thumb2_plt0_entry;
17627 put_arm_insn (htab, output_bfd, plt0_entry[0],
17628 splt->contents + 0);
17629 put_arm_insn (htab, output_bfd, plt0_entry[1],
17630 splt->contents + 4);
17631 put_arm_insn (htab, output_bfd, plt0_entry[2],
17632 splt->contents + 8);
17633
17634 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17635 }
00a97672
RS		 17636 else
17637 {
17638 got_displacement = got_address - (plt_address + 16);
17639
17640 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17641 put_arm_insn (htab, output_bfd, plt0_entry[0],
17642 splt->contents + 0);
17643 put_arm_insn (htab, output_bfd, plt0_entry[1],
17644 splt->contents + 4);
17645 put_arm_insn (htab, output_bfd, plt0_entry[2],
17646 splt->contents + 8);
17647 put_arm_insn (htab, output_bfd, plt0_entry[3],
17648 splt->contents + 12);
5e681ec4 17649
5e681ec4 17650#ifdef FOUR_WORD_PLT
00a97672
RS		 17651 /* The displacement value goes in the otherwise-unused
17652 last word of the second entry. */
17653 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17654#else
00a97672 17655 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17656#endif
00a97672 17657 }
f7a74f8c 17658 }
252b5132
RH		 17659
17660 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17661 really seem like the right value. */
74541ad4
AM		 17662 if (splt->output_section->owner == output_bfd)
17663 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17664
0855e32b
NS		 17665 if (htab->dt_tlsdesc_plt)
17666 {
17667 bfd_vma got_address
17668 = sgot->output_section->vma + sgot->output_offset;
17669 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17670 + htab->root.sgot->output_offset);
17671 bfd_vma plt_address
17672 = splt->output_section->vma + splt->output_offset;
17673
b38cadfb 17674 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17675 splt->contents + htab->dt_tlsdesc_plt,
17676 dl_tlsdesc_lazy_trampoline, 6);
17677
17678 bfd_put_32 (output_bfd,
17679 gotplt_address + htab->dt_tlsdesc_got
17680 - (plt_address + htab->dt_tlsdesc_plt)
17681 - dl_tlsdesc_lazy_trampoline[6],
17682 splt->contents + htab->dt_tlsdesc_plt + 24);
17683 bfd_put_32 (output_bfd,
17684 got_address - (plt_address + htab->dt_tlsdesc_plt)
17685 - dl_tlsdesc_lazy_trampoline[7],
17686 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17687 }
17688
17689 if (htab->tls_trampoline)
17690 {
b38cadfb 17691 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17692 splt->contents + htab->tls_trampoline,
17693 tls_trampoline, 3);
17694#ifdef FOUR_WORD_PLT
17695 bfd_put_32 (output_bfd, 0x00000000,
17696 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17697#endif
0855e32b
NS		 17698 }
17699
0e1862bb
L		 17700 if (htab->vxworks_p
17701 && !bfd_link_pic (info)
17702 && htab->root.splt->size > 0)
00a97672
RS		 17703 {
17704 /* Correct the .rel(a).plt.unloaded relocations. They will have
17705 incorrect symbol indexes. */
17706 int num_plts;
eed62c48 17707 unsigned char *p;
00a97672 17708
362d30a1 17709 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17710 / htab->plt_entry_size);
17711 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17712
17713 for (; num_plts; num_plts--)
17714 {
17715 Elf_Internal_Rela rel;
17716
17717 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17718 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17719 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17720 p += RELOC_SIZE (htab);
17721
17722 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17723 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17724 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17725 p += RELOC_SIZE (htab);
17726 }
17727 }
252b5132
RH		 17728 }
17729
99059e56
RM		 17730 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17731 /* NaCl uses a special first entry in .iplt too. */
17732 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17733
252b5132 17734 /* Fill in the first three entries in the global offset table. */
229fcec5 17735 if (sgot)
252b5132 17736 {
229fcec5
MM		 17737 if (sgot->size > 0)
17738 {
17739 if (sdyn == NULL)
17740 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17741 else
17742 bfd_put_32 (output_bfd,
17743 sdyn->output_section->vma + sdyn->output_offset,
17744 sgot->contents);
17745 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17746 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17747 }
252b5132 17748
229fcec5
MM		 17749 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17750 }
252b5132 17751
e8b09b87
CL		 17752 /* At the very end of the .rofixup section is a pointer to the GOT. */
17753 if (htab->fdpic_p && htab->srofixup != NULL)
17754 {
17755 struct elf_link_hash_entry *hgot = htab->root.hgot;
17756
17757 bfd_vma got_value = hgot->root.u.def.value
17758 + hgot->root.u.def.section->output_section->vma
17759 + hgot->root.u.def.section->output_offset;
17760
17761 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17762
17763 /* Make sure we allocated and generated the same number of fixups. */
17764 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17765 }
17766
b34976b6 17767 return TRUE;
252b5132
RH		 17768}
17769
ed7e9d0b
AM		 17770static bfd_boolean
17771elf32_arm_init_file_header (bfd *abfd, struct bfd_link_info *link_info)
ba96a88f 17772{
9b485d32 17773 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17774 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17775 struct elf_segment_map *m;
ba96a88f 17776
ed7e9d0b
AM		 17777 if (!_bfd_elf_init_file_header (abfd, link_info))
17778 return FALSE;
17779
ba96a88f
NC		 17780 i_ehdrp = elf_elfheader (abfd);
17781
94a3258f
PB		 17782 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17783 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
ba96a88f 17784 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17785
93204d3a
PB		 17786 if (link_info)
17787 {
17788 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17789 if (globals != NULL && globals->byteswap_code)
93204d3a 17790 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17791
17792 if (globals->fdpic_p)
17793 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17794 }
3bfcb652
NC		 17795
17796 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17797 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17798 {
17799 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17800 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17801 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17802 else
17803 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17804 }
ac4c9b04
MG		 17805
17806 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17807 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17808 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17809 {
17810 unsigned int j;
17811
17812 if (m->count == 0)
17813 continue;
17814 for (j = 0; j < m->count; j++)
17815 {
f0728ee3 17816 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17817 break;
17818 }
17819 if (j == m->count)
17820 {
17821 m->p_flags = PF_X;
17822 m->p_flags_valid = 1;
17823 }
17824 }
ed7e9d0b 17825 return TRUE;
ba96a88f
NC		 17826}
17827
99e4ae17 17828static enum elf_reloc_type_class
7e612e98
AM		 17829elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17830 const asection *rel_sec ATTRIBUTE_UNUSED,
17831 const Elf_Internal_Rela *rela)
99e4ae17 17832{
f51e552e 17833 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17834 {
17835 case R_ARM_RELATIVE:
17836 return reloc_class_relative;
17837 case R_ARM_JUMP_SLOT:
17838 return reloc_class_plt;
17839 case R_ARM_COPY:
17840 return reloc_class_copy;
109575d7
JW		 17841 case R_ARM_IRELATIVE:
17842 return reloc_class_ifunc;
99e4ae17
AJ		 17843 default:
17844 return reloc_class_normal;
17845 }
17846}
17847
e489d0ae 17848static void
cc364be6 17849arm_final_write_processing (bfd *abfd)
e16bb312 17850{
5a6c6817 17851 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17852}
17853
cc364be6
AM		 17854static bfd_boolean
17855elf32_arm_final_write_processing (bfd *abfd)
06f44071 17856{
cc364be6
AM		 17857 arm_final_write_processing (abfd);
17858 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17859}
17860
40a18ebd
NC		 17861/* Return TRUE if this is an unwinding table entry. */
17862
17863static bfd_boolean
17864is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17865{
0112cd26
NC		 17866 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17867 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17868}
17869
17870
17871/* Set the type and flags for an ARM section. We do this by
17872 the section name, which is a hack, but ought to work. */
17873
17874static bfd_boolean
17875elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17876{
17877 const char * name;
17878
fd361982 17879 name = bfd_section_name (sec);
40a18ebd
NC		 17880
17881 if (is_arm_elf_unwind_section_name (abfd, name))
17882 {
17883 hdr->sh_type = SHT_ARM_EXIDX;
17884 hdr->sh_flags |= SHF_LINK_ORDER;
17885 }
ac4c9b04 17886
f0728ee3
AV		 17887 if (sec->flags & SEC_ELF_PURECODE)
17888 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17889
40a18ebd
NC		 17890 return TRUE;
17891}
17892
6dc132d9
L		 17893/* Handle an ARM specific section when reading an object file. This is
17894 called when bfd_section_from_shdr finds a section with an unknown
17895 type. */
40a18ebd
NC		 17896
17897static bfd_boolean
17898elf32_arm_section_from_shdr (bfd *abfd,
17899 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17900 const char *name,
17901 int shindex)
40a18ebd
NC		 17902{
17903 /* There ought to be a place to keep ELF backend specific flags, but
17904 at the moment there isn't one. We just keep track of the
17905 sections by their name, instead. Fortunately, the ABI gives
17906 names for all the ARM specific sections, so we will probably get
17907 away with this. */
17908 switch (hdr->sh_type)
17909 {
17910 case SHT_ARM_EXIDX:
0951f019
RE		 17911 case SHT_ARM_PREEMPTMAP:
17912 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17913 break;
17914
17915 default:
17916 return FALSE;
17917 }
17918
6dc132d9 17919 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17920 return FALSE;
17921
17922 return TRUE;
17923}
e489d0ae 17924
44444f50
NC		 17925static _arm_elf_section_data *
17926get_arm_elf_section_data (asection * sec)
17927{
47b2e99c
JZ		 17928 if (sec && sec->owner && is_arm_elf (sec->owner))
17929 return elf32_arm_section_data (sec);
44444f50
NC		 17930 else
17931 return NULL;
8e3de13a
NC		 17932}
17933
4e617b1e
PB		 17934typedef struct
17935{
57402f1e 17936 void *flaginfo;
4e617b1e 17937 struct bfd_link_info *info;
91a5743d
PB		 17938 asection *sec;
17939 int sec_shndx;
6e0b88f1
AM		 17940 int (*func) (void *, const char *, Elf_Internal_Sym *,
17941 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17942} output_arch_syminfo;
17943
17944enum map_symbol_type
17945{
17946 ARM_MAP_ARM,
17947 ARM_MAP_THUMB,
17948 ARM_MAP_DATA
17949};
17950
17951
7413f23f 17952/* Output a single mapping symbol. */
4e617b1e
PB		 17953
17954static bfd_boolean
7413f23f
DJ		 17955elf32_arm_output_map_sym (output_arch_syminfo *osi,
17956 enum map_symbol_type type,
17957 bfd_vma offset)
4e617b1e
PB		 17958{
17959 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17960 Elf_Internal_Sym sym;
17961
91a5743d
PB		 17962 sym.st_value = osi->sec->output_section->vma
17963 + osi->sec->output_offset
17964 + offset;
4e617b1e
PB		 17965 sym.st_size = 0;
17966 sym.st_other = 0;
17967 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17968 sym.st_shndx = osi->sec_shndx;
35fc36a8 17969 sym.st_target_internal = 0;
fe33d2fa 17970 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17971 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17972}
17973
34e77a92
RS		 17974/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17975 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17976
17977static bfd_boolean
34e77a92
RS		 17978elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17979 bfd_boolean is_iplt_entry_p,
17980 union gotplt_union *root_plt,
17981 struct arm_plt_info *arm_plt)
4e617b1e 17982{
4e617b1e 17983 struct elf32_arm_link_hash_table *htab;
34e77a92 17984 bfd_vma addr, plt_header_size;
4e617b1e 17985
34e77a92 17986 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17987 return TRUE;
17988
4dfe6ac6
NC		 17989 htab = elf32_arm_hash_table (osi->info);
17990 if (htab == NULL)
17991 return FALSE;
17992
34e77a92
RS		 17993 if (is_iplt_entry_p)
17994 {
17995 osi->sec = htab->root.iplt;
17996 plt_header_size = 0;
17997 }
17998 else
17999 {
18000 osi->sec = htab->root.splt;
18001 plt_header_size = htab->plt_header_size;
18002 }
18003 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
18004 (osi->info->output_bfd, osi->sec->output_section));
18005
18006 addr = root_plt->offset & -2;
4e617b1e
PB		 18007 if (htab->symbian_p)
18008 {
7413f23f 18009 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18010 return FALSE;
7413f23f 18011 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 18012 return FALSE;
18013 }
18014 else if (htab->vxworks_p)
18015 {
7413f23f 18016 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18017 return FALSE;
7413f23f 18018 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 18019 return FALSE;
7413f23f 18020 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 18021 return FALSE;
7413f23f 18022 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 18023 return FALSE;
18024 }
b38cadfb
NC		 18025 else if (htab->nacl_p)
18026 {
18027 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
18028 return FALSE;
18029 }
7801f98f
CL		 18030 else if (htab->fdpic_p)
18031 {
59029f57
CL		 18032 enum map_symbol_type type = using_thumb_only(htab)
18033 ? ARM_MAP_THUMB
18034 : ARM_MAP_ARM;
18035
7801f98f 18036 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 18037 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
18038 return FALSE;
59029f57 18039 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 18040 return FALSE;
7801f98f 18041 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 18042 return FALSE;
7801f98f 18043 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 18044 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
18045 return FALSE;
7801f98f 18046 }
eed94f8f
NC		 18047 else if (using_thumb_only (htab))
18048 {
18049 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
18050 return FALSE;
6a631e86 18051 }
4e617b1e
PB		 18052 else
18053 {
34e77a92 18054 bfd_boolean thumb_stub_p;
bd97cb95 18055
34e77a92
RS		 18056 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
18057 if (thumb_stub_p)
4e617b1e 18058 {
7413f23f 18059 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 18060 return FALSE;
18061 }
18062#ifdef FOUR_WORD_PLT
7413f23f 18063 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18064 return FALSE;
7413f23f 18065 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 18066 return FALSE;
18067#else
906e58ca 18068 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 18069 so only need to output a mapping symbol for the first PLT entry and
18070 entries with thumb thunks. */
34e77a92 18071 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 18072 {
7413f23f 18073 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 18074 return FALSE;
18075 }
18076#endif
18077 }
18078
18079 return TRUE;
18080}
18081
34e77a92
RS		 18082/* Output mapping symbols for PLT entries associated with H. */
18083
18084static bfd_boolean
18085elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
18086{
18087 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
18088 struct elf32_arm_link_hash_entry *eh;
18089
18090 if (h->root.type == bfd_link_hash_indirect)
18091 return TRUE;
18092
18093 if (h->root.type == bfd_link_hash_warning)
18094 /* When warning symbols are created, they **replace** the "real"
18095 entry in the hash table, thus we never get to see the real
18096 symbol in a hash traversal. So look at it now. */
18097 h = (struct elf_link_hash_entry *) h->root.u.i.link;
18098
18099 eh = (struct elf32_arm_link_hash_entry *) h;
18100 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
18101 &h->plt, &eh->plt);
18102}
18103
4f4faa4d
TP		 18104/* Bind a veneered symbol to its veneer identified by its hash entry
18105 STUB_ENTRY. The veneered location thus loose its symbol. */
18106
18107static void
18108arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
18109{
18110 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
18111
18112 BFD_ASSERT (hash);
18113 hash->root.root.u.def.section = stub_entry->stub_sec;
18114 hash->root.root.u.def.value = stub_entry->stub_offset;
18115 hash->root.size = stub_entry->stub_size;
18116}
18117
7413f23f
DJ		 18118/* Output a single local symbol for a generated stub. */
18119
18120static bfd_boolean
18121elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18122 bfd_vma offset, bfd_vma size)
18123{
7413f23f
DJ		 18124 Elf_Internal_Sym sym;
18125
7413f23f
DJ		 18126 sym.st_value = osi->sec->output_section->vma
18127 + osi->sec->output_offset
18128 + offset;
18129 sym.st_size = size;
18130 sym.st_other = 0;
18131 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18132 sym.st_shndx = osi->sec_shndx;
35fc36a8 18133 sym.st_target_internal = 0;
57402f1e 18134 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 18135}
4e617b1e 18136
da5938a2 18137static bfd_boolean
8029a119
NC		 18138arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18139 void * in_arg)
da5938a2
NC		 18140{
18141 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 18142 asection *stub_sec;
18143 bfd_vma addr;
7413f23f 18144 char *stub_name;
9a008db3 18145 output_arch_syminfo *osi;
d3ce72d0 18146 const insn_sequence *template_sequence;
461a49ca
DJ		 18147 enum stub_insn_type prev_type;
18148 int size;
18149 int i;
18150 enum map_symbol_type sym_type;
da5938a2
NC		 18151
18152 /* Massage our args to the form they really have. */
18153 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 18154 osi = (output_arch_syminfo *) in_arg;
da5938a2 18155
da5938a2
NC		 18156 stub_sec = stub_entry->stub_sec;
18157
18158 /* Ensure this stub is attached to the current section being
7413f23f 18159 processed. */
da5938a2
NC		 18160 if (stub_sec != osi->sec)
18161 return TRUE;
18162
7413f23f 18163 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18164 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18165
18166 if (arm_stub_sym_claimed (stub_entry->stub_type))
18167 arm_stub_claim_sym (stub_entry);
18168 else
7413f23f 18169 {
4f4faa4d
TP		 18170 stub_name = stub_entry->output_name;
18171 switch (template_sequence[0].type)
18172 {
18173 case ARM_TYPE:
18174 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18175 stub_entry->stub_size))
18176 return FALSE;
18177 break;
18178 case THUMB16_TYPE:
18179 case THUMB32_TYPE:
18180 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18181 stub_entry->stub_size))
18182 return FALSE;
18183 break;
18184 default:
18185 BFD_FAIL ();
18186 return 0;
18187 }
7413f23f 18188 }
da5938a2 18189
461a49ca
DJ		 18190 prev_type = DATA_TYPE;
18191 size = 0;
18192 for (i = 0; i < stub_entry->stub_template_size; i++)
18193 {
d3ce72d0 18194 switch (template_sequence[i].type)
461a49ca
DJ		 18195 {
18196 case ARM_TYPE:
18197 sym_type = ARM_MAP_ARM;
18198 break;
18199
18200 case THUMB16_TYPE:
48229727 18201 case THUMB32_TYPE:
461a49ca
DJ		 18202 sym_type = ARM_MAP_THUMB;
18203 break;
18204
18205 case DATA_TYPE:
18206 sym_type = ARM_MAP_DATA;
18207 break;
18208
18209 default:
18210 BFD_FAIL ();
4e31c731 18211 return FALSE;
461a49ca
DJ		 18212 }
18213
d3ce72d0 18214 if (template_sequence[i].type != prev_type)
461a49ca 18215 {
d3ce72d0 18216 prev_type = template_sequence[i].type;
461a49ca
DJ		 18217 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18218 return FALSE;
18219 }
18220
d3ce72d0 18221 switch (template_sequence[i].type)
461a49ca
DJ		 18222 {
18223 case ARM_TYPE:
48229727 18224 case THUMB32_TYPE:
461a49ca
DJ		 18225 size += 4;
18226 break;
18227
18228 case THUMB16_TYPE:
18229 size += 2;
18230 break;
18231
18232 case DATA_TYPE:
18233 size += 4;
18234 break;
18235
18236 default:
18237 BFD_FAIL ();
4e31c731 18238 return FALSE;
461a49ca
DJ		 18239 }
18240 }
18241
da5938a2
NC		 18242 return TRUE;
18243}
18244
33811162
DG		 18245/* Output mapping symbols for linker generated sections,
18246 and for those data-only sections that do not have a
18247 $d. */
4e617b1e
PB		 18248
18249static bfd_boolean
18250elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18251 struct bfd_link_info *info,
57402f1e 18252 void *flaginfo,
6e0b88f1
AM		 18253 int (*func) (void *, const char *,
18254 Elf_Internal_Sym *,
18255 asection *,
18256 struct elf_link_hash_entry *))
4e617b1e
PB		 18257{
18258 output_arch_syminfo osi;
18259 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18260 bfd_vma offset;
18261 bfd_size_type size;
33811162 18262 bfd *input_bfd;
4e617b1e
PB		 18263
18264 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18265 if (htab == NULL)
18266 return FALSE;
18267
906e58ca 18268 check_use_blx (htab);
91a5743d 18269
57402f1e 18270 osi.flaginfo = flaginfo;
4e617b1e
PB		 18271 osi.info = info;
18272 osi.func = func;
906e58ca 18273
33811162
DG		 18274 /* Add a $d mapping symbol to data-only sections that
18275 don't have any mapping symbol. This may result in (harmless) redundant
18276 mapping symbols. */
18277 for (input_bfd = info->input_bfds;
18278 input_bfd != NULL;
c72f2fb2 18279 input_bfd = input_bfd->link.next)
33811162
DG		 18280 {
18281 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18282 for (osi.sec = input_bfd->sections;
18283 osi.sec != NULL;
18284 osi.sec = osi.sec->next)
18285 {
18286 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18287 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18288 != 0)
33811162
DG		 18289 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18290 == SEC_HAS_CONTENTS
18291 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18292 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18293 && osi.sec->size > 0
18294 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18295 {
18296 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18297 (output_bfd, osi.sec->output_section);
18298 if (osi.sec_shndx != (int)SHN_BAD)
18299 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18300 }
18301 }
18302 }
18303
91a5743d
PB		 18304 /* ARM->Thumb glue. */
18305 if (htab->arm_glue_size > 0)
18306 {
3d4d4302
AM		 18307 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18308 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18309
18310 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18311 (output_bfd, osi.sec->output_section);
0e1862bb 18312 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18313 || htab->pic_veneer)
18314 size = ARM2THUMB_PIC_GLUE_SIZE;
18315 else if (htab->use_blx)
18316 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18317 else
18318 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18319
91a5743d
PB		 18320 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18321 {
7413f23f
DJ		 18322 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18323 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18324 }
18325 }
18326
18327 /* Thumb->ARM glue. */
18328 if (htab->thumb_glue_size > 0)
18329 {
3d4d4302
AM		 18330 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18331 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18332
18333 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18334 (output_bfd, osi.sec->output_section);
18335 size = THUMB2ARM_GLUE_SIZE;
18336
18337 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18338 {
7413f23f
DJ		 18339 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18340 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18341 }
18342 }
18343
845b51d6
PB		 18344 /* ARMv4 BX veneers. */
18345 if (htab->bx_glue_size > 0)
18346 {
3d4d4302
AM		 18347 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18348 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18349
18350 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18351 (output_bfd, osi.sec->output_section);
18352
7413f23f 18353 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18354 }
18355
8029a119
NC		 18356 /* Long calls stubs. */
18357 if (htab->stub_bfd && htab->stub_bfd->sections)
18358 {
da5938a2 18359 asection* stub_sec;
8029a119 18360
da5938a2
NC		 18361 for (stub_sec = htab->stub_bfd->sections;
18362 stub_sec != NULL;
8029a119
NC		 18363 stub_sec = stub_sec->next)
18364 {
18365 /* Ignore non-stub sections. */
18366 if (!strstr (stub_sec->name, STUB_SUFFIX))
18367 continue;
da5938a2 18368
8029a119 18369 osi.sec = stub_sec;
da5938a2 18370
8029a119
NC		 18371 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18372 (output_bfd, osi.sec->output_section);
da5938a2 18373
8029a119
NC		 18374 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18375 }
18376 }
da5938a2 18377
91a5743d 18378 /* Finally, output mapping symbols for the PLT. */
34e77a92 18379 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18380 {
34e77a92
RS		 18381 osi.sec = htab->root.splt;
18382 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18383 (output_bfd, osi.sec->output_section));
18384
18385 /* Output mapping symbols for the plt header. SymbianOS does not have a
18386 plt header. */
18387 if (htab->vxworks_p)
18388 {
18389 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18390 if (!bfd_link_pic (info))
34e77a92
RS		 18391 {
18392 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18393 return FALSE;
18394 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18395 return FALSE;
18396 }
18397 }
b38cadfb
NC		 18398 else if (htab->nacl_p)
18399 {
18400 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18401 return FALSE;
18402 }
59029f57 18403 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18404 {
18405 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18406 return FALSE;
18407 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18408 return FALSE;
18409 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18410 return FALSE;
18411 }
e8b09b87 18412 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18413 {
7413f23f 18414 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18415 return FALSE;
34e77a92
RS		 18416#ifndef FOUR_WORD_PLT
18417 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18418 return FALSE;
34e77a92 18419#endif
4e617b1e
PB		 18420 }
18421 }
99059e56
RM		 18422 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18423 {
18424 /* NaCl uses a special first entry in .iplt too. */
18425 osi.sec = htab->root.iplt;
18426 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18427 (output_bfd, osi.sec->output_section));
18428 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18429 return FALSE;
18430 }
34e77a92
RS		 18431 if ((htab->root.splt && htab->root.splt->size > 0)
18432 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18433 {
34e77a92
RS		 18434 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18435 for (input_bfd = info->input_bfds;
18436 input_bfd != NULL;
c72f2fb2 18437 input_bfd = input_bfd->link.next)
34e77a92
RS		 18438 {
18439 struct arm_local_iplt_info **local_iplt;
18440 unsigned int i, num_syms;
4e617b1e 18441
34e77a92
RS		 18442 local_iplt = elf32_arm_local_iplt (input_bfd);
18443 if (local_iplt != NULL)
18444 {
18445 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18446 for (i = 0; i < num_syms; i++)
18447 if (local_iplt[i] != NULL
18448 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18449 &local_iplt[i]->root,
18450 &local_iplt[i]->arm))
18451 return FALSE;
18452 }
18453 }
18454 }
0855e32b
NS		 18455 if (htab->dt_tlsdesc_plt != 0)
18456 {
18457 /* Mapping symbols for the lazy tls trampoline. */
18458 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18459 return FALSE;
b38cadfb 18460
0855e32b
NS		 18461 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18462 htab->dt_tlsdesc_plt + 24))
18463 return FALSE;
18464 }
18465 if (htab->tls_trampoline != 0)
18466 {
18467 /* Mapping symbols for the tls trampoline. */
18468 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18469 return FALSE;
18470#ifdef FOUR_WORD_PLT
18471 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18472 htab->tls_trampoline + 12))
18473 return FALSE;
b38cadfb 18474#endif
0855e32b 18475 }
b38cadfb 18476
4e617b1e
PB		 18477 return TRUE;
18478}
18479
54ddd295
TP		 18480/* Filter normal symbols of CMSE entry functions of ABFD to include in
18481 the import library. All SYMCOUNT symbols of ABFD can be examined
18482 from their pointers in SYMS. Pointers of symbols to keep should be
18483 stored continuously at the beginning of that array.
18484
18485 Returns the number of symbols to keep. */
18486
18487static unsigned int
18488elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18489 struct bfd_link_info *info,
18490 asymbol **syms, long symcount)
18491{
18492 size_t maxnamelen;
18493 char *cmse_name;
18494 long src_count, dst_count = 0;
18495 struct elf32_arm_link_hash_table *htab;
18496
18497 htab = elf32_arm_hash_table (info);
18498 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18499 symcount = 0;
18500
18501 maxnamelen = 128;
18502 cmse_name = (char *) bfd_malloc (maxnamelen);
7a0fb7be
NC		 18503 BFD_ASSERT (cmse_name);
18504
54ddd295
TP		 18505 for (src_count = 0; src_count < symcount; src_count++)
18506 {
18507 struct elf32_arm_link_hash_entry *cmse_hash;
18508 asymbol *sym;
18509 flagword flags;
18510 char *name;
18511 size_t namelen;
18512
18513 sym = syms[src_count];
18514 flags = sym->flags;
18515 name = (char *) bfd_asymbol_name (sym);
18516
18517 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18518 continue;
18519 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18520 continue;
18521
18522 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18523 if (namelen > maxnamelen)
18524 {
18525 cmse_name = (char *)
18526 bfd_realloc (cmse_name, namelen);
18527 maxnamelen = namelen;
18528 }
18529 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18530 cmse_hash = (struct elf32_arm_link_hash_entry *)
18531 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18532
18533 if (!cmse_hash
18534 || (cmse_hash->root.root.type != bfd_link_hash_defined
18535 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18536 || cmse_hash->root.type != STT_FUNC)
18537 continue;
18538
54ddd295
TP		 18539 syms[dst_count++] = sym;
18540 }
18541 free (cmse_name);
18542
18543 syms[dst_count] = NULL;
18544
18545 return dst_count;
18546}
18547
18548/* Filter symbols of ABFD to include in the import library. All
18549 SYMCOUNT symbols of ABFD can be examined from their pointers in
18550 SYMS. Pointers of symbols to keep should be stored continuously at
18551 the beginning of that array.
18552
18553 Returns the number of symbols to keep. */
18554
18555static unsigned int
18556elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18557 struct bfd_link_info *info,
18558 asymbol **syms, long symcount)
18559{
18560 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18561
046734ff
TP		 18562 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18563 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18564 library to be a relocatable object file. */
18565 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18566 if (globals->cmse_implib)
18567 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18568 else
18569 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18570}
18571
e489d0ae
PB		 18572/* Allocate target specific section data. */
18573
18574static bfd_boolean
18575elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18576{
f592407e
AM		 18577 if (!sec->used_by_bfd)
18578 {
18579 _arm_elf_section_data *sdata;
18580 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18581
21d799b5 18582 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18583 if (sdata == NULL)
18584 return FALSE;
18585 sec->used_by_bfd = sdata;
18586 }
e489d0ae
PB		 18587
18588 return _bfd_elf_new_section_hook (abfd, sec);
18589}
18590
18591
18592/* Used to order a list of mapping symbols by address. */
18593
18594static int
18595elf32_arm_compare_mapping (const void * a, const void * b)
18596{
7f6a71ff
JM		 18597 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18598 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18599
18600 if (amap->vma > bmap->vma)
18601 return 1;
18602 else if (amap->vma < bmap->vma)
18603 return -1;
18604 else if (amap->type > bmap->type)
18605 /* Ensure results do not depend on the host qsort for objects with
18606 multiple mapping symbols at the same address by sorting on type
18607 after vma. */
18608 return 1;
18609 else if (amap->type < bmap->type)
18610 return -1;
18611 else
18612 return 0;
e489d0ae
PB		 18613}
18614
2468f9c9
PB		 18615/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18616
18617static unsigned long
18618offset_prel31 (unsigned long addr, bfd_vma offset)
18619{
18620 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18621}
18622
18623/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18624 relocations. */
18625
18626static void
18627copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18628{
18629 unsigned long first_word = bfd_get_32 (output_bfd, from);
18630 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18631
2468f9c9
PB		 18632 /* High bit of first word is supposed to be zero. */
18633 if ((first_word & 0x80000000ul) == 0)
18634 first_word = offset_prel31 (first_word, offset);
b38cadfb 18635
2468f9c9
PB		 18636 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18637 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18638 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18639 second_word = offset_prel31 (second_word, offset);
b38cadfb 18640
2468f9c9
PB		 18641 bfd_put_32 (output_bfd, first_word, to);
18642 bfd_put_32 (output_bfd, second_word, to + 4);
18643}
e489d0ae 18644
48229727
JB		 18645/* Data for make_branch_to_a8_stub(). */
18646
b38cadfb
NC		 18647struct a8_branch_to_stub_data
18648{
48229727
JB		 18649 asection *writing_section;
18650 bfd_byte *contents;
18651};
18652
18653
18654/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18655 places for a particular section. */
18656
18657static bfd_boolean
18658make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18659 void *in_arg)
48229727
JB		 18660{
18661 struct elf32_arm_stub_hash_entry *stub_entry;
18662 struct a8_branch_to_stub_data *data;
18663 bfd_byte *contents;
18664 unsigned long branch_insn;
18665 bfd_vma veneered_insn_loc, veneer_entry_loc;
18666 bfd_signed_vma branch_offset;
18667 bfd *abfd;
8d9d9490 18668 unsigned int loc;
48229727
JB		 18669
18670 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18671 data = (struct a8_branch_to_stub_data *) in_arg;
18672
18673 if (stub_entry->target_section != data->writing_section
4563a860 18674 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18675 return TRUE;
18676
18677 contents = data->contents;
18678
8d9d9490
TP		 18679 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18680 generated when both source and target are in the same section. */
48229727
JB		 18681 veneered_insn_loc = stub_entry->target_section->output_section->vma
18682 + stub_entry->target_section->output_offset
8d9d9490 18683 + stub_entry->source_value;
48229727
JB		 18684
18685 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18686 + stub_entry->stub_sec->output_offset
18687 + stub_entry->stub_offset;
18688
18689 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18690 veneered_insn_loc &= ~3u;
18691
18692 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18693
18694 abfd = stub_entry->target_section->owner;
8d9d9490 18695 loc = stub_entry->source_value;
48229727
JB		 18696
18697 /* We attempt to avoid this condition by setting stubs_always_after_branch
18698 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18699 This check is just to be on the safe side... */
18700 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18701 {
871b3ab2 18702 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18703 "allocated in unsafe location"), abfd);
48229727
JB		 18704 return FALSE;
18705 }
18706
18707 switch (stub_entry->stub_type)
18708 {
18709 case arm_stub_a8_veneer_b:
18710 case arm_stub_a8_veneer_b_cond:
18711 branch_insn = 0xf0009000;
18712 goto jump24;
18713
18714 case arm_stub_a8_veneer_blx:
18715 branch_insn = 0xf000e800;
18716 goto jump24;
18717
18718 case arm_stub_a8_veneer_bl:
18719 {
18720 unsigned int i1, j1, i2, j2, s;
18721
18722 branch_insn = 0xf000d000;
18723
18724 jump24:
18725 if (branch_offset < -16777216 || branch_offset > 16777214)
18726 {
18727 /* There's not much we can do apart from complain if this
18728 happens. */
871b3ab2 18729 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18730 "of range (input file too large)"), abfd);
48229727
JB		 18731 return FALSE;
18732 }
18733
18734 /* i1 = not(j1 eor s), so:
18735 not i1 = j1 eor s
18736 j1 = (not i1) eor s. */
18737
18738 branch_insn |= (branch_offset >> 1) & 0x7ff;
18739 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18740 i2 = (branch_offset >> 22) & 1;
18741 i1 = (branch_offset >> 23) & 1;
18742 s = (branch_offset >> 24) & 1;
18743 j1 = (!i1) ^ s;
18744 j2 = (!i2) ^ s;
18745 branch_insn |= j2 << 11;
18746 branch_insn |= j1 << 13;
18747 branch_insn |= s << 26;
18748 }
18749 break;
18750
18751 default:
18752 BFD_FAIL ();
18753 return FALSE;
18754 }
18755
8d9d9490
TP		 18756 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18757 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18758
18759 return TRUE;
18760}
18761
a504d23a
LA		 18762/* Beginning of stm32l4xx work-around. */
18763
18764/* Functions encoding instructions necessary for the emission of the
18765 fix-stm32l4xx-629360.
18766 Encoding is extracted from the
18767 ARM (C) Architecture Reference Manual
18768 ARMv7-A and ARMv7-R edition
18769 ARM DDI 0406C.b (ID072512). */
18770
18771static inline bfd_vma
82188b29 18772create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18773{
18774 /* A8.8.18 B (A8-334)
18775 B target_address (Encoding T4). */
18776 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18777 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18778 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18779
a504d23a
LA		 18780 int s = ((branch_offset & 0x1000000) >> 24);
18781 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18782 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18783
18784 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18785 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18786
18787 bfd_vma patched_inst = 0xf0009000
18788 | s << 26 /* S. */
18789 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18790 | j1 << 13 /* J1. */
18791 | j2 << 11 /* J2. */
18792 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18793
18794 return patched_inst;
18795}
18796
18797static inline bfd_vma
18798create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18799{
18800 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18801 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18802 bfd_vma patched_inst = 0xe8900000
18803 | (/*W=*/wback << 21)
18804 | (base_reg << 16)
18805 | (reg_mask & 0x0000ffff);
18806
18807 return patched_inst;
18808}
18809
18810static inline bfd_vma
18811create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18812{
18813 /* A8.8.60 LDMDB/LDMEA (A8-402)
18814 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18815 bfd_vma patched_inst = 0xe9100000
18816 | (/*W=*/wback << 21)
18817 | (base_reg << 16)
18818 | (reg_mask & 0x0000ffff);
18819
18820 return patched_inst;
18821}
18822
18823static inline bfd_vma
18824create_instruction_mov (int target_reg, int source_reg)
18825{
18826 /* A8.8.103 MOV (register) (A8-486)
18827 MOV Rd, Rm (Encoding T1). */
18828 bfd_vma patched_inst = 0x4600
18829 | (target_reg & 0x7)
18830 | ((target_reg & 0x8) >> 3) << 7
18831 | (source_reg << 3);
18832
18833 return patched_inst;
18834}
18835
18836static inline bfd_vma
18837create_instruction_sub (int target_reg, int source_reg, int value)
18838{
18839 /* A8.8.221 SUB (immediate) (A8-708)
18840 SUB Rd, Rn, #value (Encoding T3). */
18841 bfd_vma patched_inst = 0xf1a00000
18842 | (target_reg << 8)
18843 | (source_reg << 16)
18844 | (/*S=*/0 << 20)
18845 | ((value & 0x800) >> 11) << 26
18846 | ((value & 0x700) >> 8) << 12
18847 | (value & 0x0ff);
18848
18849 return patched_inst;
18850}
18851
18852static inline bfd_vma
9239bbd3 18853create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18854 int first_reg)
18855{
18856 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18857 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18858 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18859 | (/*W=*/wback << 21)
18860 | (base_reg << 16)
9239bbd3
CM		 18861 | (num_words & 0x000000ff)
18862 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18863 | (first_reg & 0x00000001) << 22;
18864
18865 return patched_inst;
18866}
18867
18868static inline bfd_vma
9239bbd3
CM		 18869create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18870 int first_reg)
a504d23a
LA		 18871{
18872 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18873 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18874 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18875 | (base_reg << 16)
9239bbd3
CM		 18876 | (num_words & 0x000000ff)
18877 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18878 | (first_reg & 0x00000001) << 22;
18879
18880 return patched_inst;
18881}
18882
18883static inline bfd_vma
18884create_instruction_udf_w (int value)
18885{
18886 /* A8.8.247 UDF (A8-758)
18887 Undefined (Encoding T2). */
18888 bfd_vma patched_inst = 0xf7f0a000
18889 | (value & 0x00000fff)
18890 | (value & 0x000f0000) << 16;
18891
18892 return patched_inst;
18893}
18894
18895static inline bfd_vma
18896create_instruction_udf (int value)
18897{
18898 /* A8.8.247 UDF (A8-758)
18899 Undefined (Encoding T1). */
18900 bfd_vma patched_inst = 0xde00
18901 | (value & 0xff);
18902
18903 return patched_inst;
18904}
18905
18906/* Functions writing an instruction in memory, returning the next
18907 memory position to write to. */
18908
18909static inline bfd_byte *
18910push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18911 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18912{
18913 put_thumb2_insn (htab, output_bfd, insn, pt);
18914 return pt + 4;
18915}
18916
18917static inline bfd_byte *
18918push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18919 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18920{
18921 put_thumb_insn (htab, output_bfd, insn, pt);
18922 return pt + 2;
18923}
18924
18925/* Function filling up a region in memory with T1 and T2 UDFs taking
18926 care of alignment. */
18927
18928static bfd_byte *
18929stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18930 bfd * output_bfd,
18931 const bfd_byte * const base_stub_contents,
18932 bfd_byte * const from_stub_contents,
18933 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18934{
18935 bfd_byte *current_stub_contents = from_stub_contents;
18936
18937 /* Fill the remaining of the stub with deterministic contents : UDF
18938 instructions.
18939 Check if realignment is needed on modulo 4 frontier using T1, to
18940 further use T2. */
18941 if ((current_stub_contents < end_stub_contents)
18942 && !((current_stub_contents - base_stub_contents) % 2)
18943 && ((current_stub_contents - base_stub_contents) % 4))
18944 current_stub_contents =
18945 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18946 create_instruction_udf (0));
18947
18948 for (; current_stub_contents < end_stub_contents;)
18949 current_stub_contents =
18950 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18951 create_instruction_udf_w (0));
18952
18953 return current_stub_contents;
18954}
18955
18956/* Functions writing the stream of instructions equivalent to the
18957 derived sequence for ldmia, ldmdb, vldm respectively. */
18958
18959static void
18960stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18961 bfd * output_bfd,
18962 const insn32 initial_insn,
18963 const bfd_byte *const initial_insn_addr,
18964 bfd_byte *const base_stub_contents)
18965{
18966 int wback = (initial_insn & 0x00200000) >> 21;
18967 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18968 int insn_all_registers = initial_insn & 0x0000ffff;
18969 int insn_low_registers, insn_high_registers;
18970 int usable_register_mask;
b25e998d 18971 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18972 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18973 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18974 bfd_byte *current_stub_contents = base_stub_contents;
18975
18976 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18977
18978 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18979 smaller than 8 registers load sequences that do not cause the
18980 hardware issue. */
18981 if (nb_registers <= 8)
18982 {
18983 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18984 current_stub_contents =
18985 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18986 initial_insn);
18987
18988 /* B initial_insn_addr+4. */
18989 if (!restore_pc)
18990 current_stub_contents =
18991 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18992 create_instruction_branch_absolute
82188b29 18993 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18994
18995 /* Fill the remaining of the stub with deterministic contents. */
18996 current_stub_contents =
18997 stm32l4xx_fill_stub_udf (htab, output_bfd,
18998 base_stub_contents, current_stub_contents,
18999 base_stub_contents +
19000 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19001
19002 return;
19003 }
19004
19005 /* - reg_list[13] == 0. */
19006 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
19007
19008 /* - reg_list[14] & reg_list[15] != 1. */
19009 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19010
19011 /* - if (wback==1) reg_list[rn] == 0. */
19012 BFD_ASSERT (!wback || !restore_rn);
19013
19014 /* - nb_registers > 8. */
b25e998d 19015 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19016
19017 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19018
19019 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
19020 - One with the 7 lowest registers (register mask 0x007F)
19021 This LDM will finally contain between 2 and 7 registers
19022 - One with the 7 highest registers (register mask 0xDF80)
19023 This ldm will finally contain between 2 and 7 registers. */
19024 insn_low_registers = insn_all_registers & 0x007F;
19025 insn_high_registers = insn_all_registers & 0xDF80;
19026
19027 /* A spare register may be needed during this veneer to temporarily
19028 handle the base register. This register will be restored with the
19029 last LDM operation.
19030 The usable register may be any general purpose register (that
19031 excludes PC, SP, LR : register mask is 0x1FFF). */
19032 usable_register_mask = 0x1FFF;
19033
19034 /* Generate the stub function. */
19035 if (wback)
19036 {
19037 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
19038 current_stub_contents =
19039 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19040 create_instruction_ldmia
19041 (rn, /*wback=*/1, insn_low_registers));
19042
19043 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19044 current_stub_contents =
19045 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19046 create_instruction_ldmia
19047 (rn, /*wback=*/1, insn_high_registers));
19048 if (!restore_pc)
19049 {
19050 /* B initial_insn_addr+4. */
19051 current_stub_contents =
19052 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19053 create_instruction_branch_absolute
82188b29 19054 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19055 }
19056 }
19057 else /* if (!wback). */
19058 {
19059 ri = rn;
19060
19061 /* If Rn is not part of the high-register-list, move it there. */
19062 if (!(insn_high_registers & (1 << rn)))
19063 {
19064 /* Choose a Ri in the high-register-list that will be restored. */
19065 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19066
19067 /* MOV Ri, Rn. */
19068 current_stub_contents =
19069 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19070 create_instruction_mov (ri, rn));
19071 }
19072
19073 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19074 current_stub_contents =
19075 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19076 create_instruction_ldmia
19077 (ri, /*wback=*/1, insn_low_registers));
19078
19079 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19080 current_stub_contents =
19081 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19082 create_instruction_ldmia
19083 (ri, /*wback=*/0, insn_high_registers));
19084
19085 if (!restore_pc)
19086 {
19087 /* B initial_insn_addr+4. */
19088 current_stub_contents =
19089 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19090 create_instruction_branch_absolute
82188b29 19091 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19092 }
19093 }
19094
19095 /* Fill the remaining of the stub with deterministic contents. */
19096 current_stub_contents =
19097 stm32l4xx_fill_stub_udf (htab, output_bfd,
19098 base_stub_contents, current_stub_contents,
19099 base_stub_contents +
19100 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19101}
19102
19103static void
19104stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19105 bfd * output_bfd,
19106 const insn32 initial_insn,
19107 const bfd_byte *const initial_insn_addr,
19108 bfd_byte *const base_stub_contents)
19109{
19110 int wback = (initial_insn & 0x00200000) >> 21;
19111 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19112 int insn_all_registers = initial_insn & 0x0000ffff;
19113 int insn_low_registers, insn_high_registers;
19114 int usable_register_mask;
19115 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19116 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 19117 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19118 bfd_byte *current_stub_contents = base_stub_contents;
19119
19120 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19121
19122 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19123 smaller than 8 registers load sequences that do not cause the
19124 hardware issue. */
19125 if (nb_registers <= 8)
19126 {
19127 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19128 current_stub_contents =
19129 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19130 initial_insn);
19131
19132 /* B initial_insn_addr+4. */
19133 current_stub_contents =
19134 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19135 create_instruction_branch_absolute
82188b29 19136 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19137
19138 /* Fill the remaining of the stub with deterministic contents. */
19139 current_stub_contents =
19140 stm32l4xx_fill_stub_udf (htab, output_bfd,
19141 base_stub_contents, current_stub_contents,
19142 base_stub_contents +
19143 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19144
19145 return;
19146 }
19147
19148 /* - reg_list[13] == 0. */
19149 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19150
19151 /* - reg_list[14] & reg_list[15] != 1. */
19152 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19153
19154 /* - if (wback==1) reg_list[rn] == 0. */
19155 BFD_ASSERT (!wback || !restore_rn);
19156
19157 /* - nb_registers > 8. */
b25e998d 19158 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19159
19160 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19161
19162 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19163 - One with the 7 lowest registers (register mask 0x007F)
19164 This LDM will finally contain between 2 and 7 registers
19165 - One with the 7 highest registers (register mask 0xDF80)
19166 This ldm will finally contain between 2 and 7 registers. */
19167 insn_low_registers = insn_all_registers & 0x007F;
19168 insn_high_registers = insn_all_registers & 0xDF80;
19169
19170 /* A spare register may be needed during this veneer to temporarily
19171 handle the base register. This register will be restored with
19172 the last LDM operation.
19173 The usable register may be any general purpose register (that excludes
19174 PC, SP, LR : register mask is 0x1FFF). */
19175 usable_register_mask = 0x1FFF;
19176
19177 /* Generate the stub function. */
19178 if (!wback && !restore_pc && !restore_rn)
19179 {
19180 /* Choose a Ri in the low-register-list that will be restored. */
19181 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19182
19183 /* MOV Ri, Rn. */
19184 current_stub_contents =
19185 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19186 create_instruction_mov (ri, rn));
19187
19188 /* LDMDB Ri!, {R-high-register-list}. */
19189 current_stub_contents =
19190 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19191 create_instruction_ldmdb
19192 (ri, /*wback=*/1, insn_high_registers));
19193
19194 /* LDMDB Ri, {R-low-register-list}. */
19195 current_stub_contents =
19196 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19197 create_instruction_ldmdb
19198 (ri, /*wback=*/0, insn_low_registers));
19199
19200 /* B initial_insn_addr+4. */
19201 current_stub_contents =
19202 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19203 create_instruction_branch_absolute
82188b29 19204 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19205 }
19206 else if (wback && !restore_pc && !restore_rn)
19207 {
19208 /* LDMDB Rn!, {R-high-register-list}. */
19209 current_stub_contents =
19210 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19211 create_instruction_ldmdb
19212 (rn, /*wback=*/1, insn_high_registers));
19213
19214 /* LDMDB Rn!, {R-low-register-list}. */
19215 current_stub_contents =
19216 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19217 create_instruction_ldmdb
19218 (rn, /*wback=*/1, insn_low_registers));
19219
19220 /* B initial_insn_addr+4. */
19221 current_stub_contents =
19222 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19223 create_instruction_branch_absolute
82188b29 19224 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19225 }
19226 else if (!wback && restore_pc && !restore_rn)
19227 {
19228 /* Choose a Ri in the high-register-list that will be restored. */
19229 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19230
19231 /* SUB Ri, Rn, #(4*nb_registers). */
19232 current_stub_contents =
19233 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19234 create_instruction_sub (ri, rn, (4 * nb_registers)));
19235
19236 /* LDMIA Ri!, {R-low-register-list}. */
19237 current_stub_contents =
19238 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19239 create_instruction_ldmia
19240 (ri, /*wback=*/1, insn_low_registers));
19241
19242 /* LDMIA Ri, {R-high-register-list}. */
19243 current_stub_contents =
19244 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19245 create_instruction_ldmia
19246 (ri, /*wback=*/0, insn_high_registers));
19247 }
19248 else if (wback && restore_pc && !restore_rn)
19249 {
19250 /* Choose a Ri in the high-register-list that will be restored. */
19251 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19252
19253 /* SUB Rn, Rn, #(4*nb_registers) */
19254 current_stub_contents =
19255 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19256 create_instruction_sub (rn, rn, (4 * nb_registers)));
19257
19258 /* MOV Ri, Rn. */
19259 current_stub_contents =
19260 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19261 create_instruction_mov (ri, rn));
19262
19263 /* LDMIA Ri!, {R-low-register-list}. */
19264 current_stub_contents =
19265 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19266 create_instruction_ldmia
19267 (ri, /*wback=*/1, insn_low_registers));
19268
19269 /* LDMIA Ri, {R-high-register-list}. */
19270 current_stub_contents =
19271 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19272 create_instruction_ldmia
19273 (ri, /*wback=*/0, insn_high_registers));
19274 }
19275 else if (!wback && !restore_pc && restore_rn)
19276 {
19277 ri = rn;
19278 if (!(insn_low_registers & (1 << rn)))
19279 {
19280 /* Choose a Ri in the low-register-list that will be restored. */
19281 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19282
19283 /* MOV Ri, Rn. */
19284 current_stub_contents =
19285 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19286 create_instruction_mov (ri, rn));
19287 }
19288
19289 /* LDMDB Ri!, {R-high-register-list}. */
19290 current_stub_contents =
19291 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19292 create_instruction_ldmdb
19293 (ri, /*wback=*/1, insn_high_registers));
19294
19295 /* LDMDB Ri, {R-low-register-list}. */
19296 current_stub_contents =
19297 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19298 create_instruction_ldmdb
19299 (ri, /*wback=*/0, insn_low_registers));
19300
19301 /* B initial_insn_addr+4. */
19302 current_stub_contents =
19303 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19304 create_instruction_branch_absolute
82188b29 19305 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19306 }
19307 else if (!wback && restore_pc && restore_rn)
19308 {
19309 ri = rn;
19310 if (!(insn_high_registers & (1 << rn)))
19311 {
19312 /* Choose a Ri in the high-register-list that will be restored. */
19313 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19314 }
19315
19316 /* SUB Ri, Rn, #(4*nb_registers). */
19317 current_stub_contents =
19318 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19319 create_instruction_sub (ri, rn, (4 * nb_registers)));
19320
19321 /* LDMIA Ri!, {R-low-register-list}. */
19322 current_stub_contents =
19323 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19324 create_instruction_ldmia
19325 (ri, /*wback=*/1, insn_low_registers));
19326
19327 /* LDMIA Ri, {R-high-register-list}. */
19328 current_stub_contents =
19329 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19330 create_instruction_ldmia
19331 (ri, /*wback=*/0, insn_high_registers));
19332 }
19333 else if (wback && restore_rn)
19334 {
19335 /* The assembler should not have accepted to encode this. */
19336 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19337 "undefined behavior.\n");
19338 }
19339
19340 /* Fill the remaining of the stub with deterministic contents. */
19341 current_stub_contents =
19342 stm32l4xx_fill_stub_udf (htab, output_bfd,
19343 base_stub_contents, current_stub_contents,
19344 base_stub_contents +
19345 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19346
19347}
19348
19349static void
19350stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19351 bfd * output_bfd,
19352 const insn32 initial_insn,
19353 const bfd_byte *const initial_insn_addr,
19354 bfd_byte *const base_stub_contents)
19355{
13c9c485 19356 int num_words = initial_insn & 0xff;
a504d23a
LA		 19357 bfd_byte *current_stub_contents = base_stub_contents;
19358
19359 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19360
19361 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19362 smaller than 8 words load sequences that do not cause the
a504d23a 19363 hardware issue. */
9239bbd3 19364 if (num_words <= 8)
a504d23a
LA		 19365 {
19366 /* Untouched instruction. */
19367 current_stub_contents =
19368 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19369 initial_insn);
19370
19371 /* B initial_insn_addr+4. */
19372 current_stub_contents =
19373 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19374 create_instruction_branch_absolute
82188b29 19375 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19376 }
19377 else
19378 {
9eaff861 19379 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19380 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19381 bfd_boolean is_ia_nobang = /* (IA without !). */
19382 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19383 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19384 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19385 bfd_boolean is_db_bang = /* (DB with !). */
19386 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19387 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19388 /* d = UInt (Vd:D);. */
9239bbd3 19389 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19390 | (((unsigned int)initial_insn << 9) >> 31);
19391
9239bbd3
CM		 19392 /* Compute the number of 8-words chunks needed to split. */
19393 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19394 int chunk;
19395
19396 /* The test coverage has been done assuming the following
19397 hypothesis that exactly one of the previous is_ predicates is
19398 true. */
9239bbd3
CM		 19399 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19400 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19401
9239bbd3 19402 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19403 cases, then we emit the adjustments:
19404
19405 vldm rx, {...}
19406 -> vldm rx!, {8_words_or_less} for each needed 8_word
19407 -> sub rx, rx, #size (list)
19408
19409 vldm rx!, {...}
19410 -> vldm rx!, {8_words_or_less} for each needed 8_word
19411 This also handles vpop instruction (when rx is sp)
19412
19413 vldmd rx!, {...}
19414 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19415 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19416 {
9239bbd3
CM		 19417 bfd_vma new_insn = 0;
19418
a504d23a
LA		 19419 if (is_ia_nobang || is_ia_bang)
19420 {
9239bbd3
CM		 19421 new_insn = create_instruction_vldmia
19422 (base_reg,
19423 is_dp,
19424 /*wback= . */1,
19425 chunks - (chunk + 1) ?
19426 8 : num_words - chunk * 8,
19427 first_reg + chunk * 8);
a504d23a
LA		 19428 }
19429 else if (is_db_bang)
19430 {
9239bbd3
CM		 19431 new_insn = create_instruction_vldmdb
19432 (base_reg,
19433 is_dp,
19434 chunks - (chunk + 1) ?
19435 8 : num_words - chunk * 8,
19436 first_reg + chunk * 8);
a504d23a 19437 }
9239bbd3
CM		 19438
19439 if (new_insn)
19440 current_stub_contents =
19441 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19442 new_insn);
a504d23a
LA		 19443 }
19444
19445 /* Only this case requires the base register compensation
19446 subtract. */
19447 if (is_ia_nobang)
19448 {
19449 current_stub_contents =
19450 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19451 create_instruction_sub
9239bbd3 19452 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19453 }
19454
19455 /* B initial_insn_addr+4. */
19456 current_stub_contents =
19457 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19458 create_instruction_branch_absolute
82188b29 19459 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19460 }
19461
19462 /* Fill the remaining of the stub with deterministic contents. */
19463 current_stub_contents =
19464 stm32l4xx_fill_stub_udf (htab, output_bfd,
19465 base_stub_contents, current_stub_contents,
19466 base_stub_contents +
19467 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19468}
19469
19470static void
19471stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19472 bfd * output_bfd,
19473 const insn32 wrong_insn,
19474 const bfd_byte *const wrong_insn_addr,
19475 bfd_byte *const stub_contents)
19476{
19477 if (is_thumb2_ldmia (wrong_insn))
19478 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19479 wrong_insn, wrong_insn_addr,
19480 stub_contents);
19481 else if (is_thumb2_ldmdb (wrong_insn))
19482 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19483 wrong_insn, wrong_insn_addr,
19484 stub_contents);
19485 else if (is_thumb2_vldm (wrong_insn))
19486 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19487 wrong_insn, wrong_insn_addr,
19488 stub_contents);
19489}
19490
19491/* End of stm32l4xx work-around. */
19492
19493
e489d0ae
PB		 19494/* Do code byteswapping. Return FALSE afterwards so that the section is
19495 written out as normal. */
19496
19497static bfd_boolean
c7b8f16e 19498elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19499 struct bfd_link_info *link_info,
19500 asection *sec,
e489d0ae
PB		 19501 bfd_byte *contents)
19502{
48229727 19503 unsigned int mapcount, errcount;
8e3de13a 19504 _arm_elf_section_data *arm_data;
c7b8f16e 19505 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19506 elf32_arm_section_map *map;
c7b8f16e 19507 elf32_vfp11_erratum_list *errnode;
a504d23a 19508 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19509 bfd_vma ptr;
19510 bfd_vma end;
c7b8f16e 19511 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19512 bfd_byte tmp;
48229727 19513 unsigned int i;
57e8b36a 19514
4dfe6ac6
NC		 19515 if (globals == NULL)
19516 return FALSE;
19517
8e3de13a
NC		 19518 /* If this section has not been allocated an _arm_elf_section_data
19519 structure then we cannot record anything. */
19520 arm_data = get_arm_elf_section_data (sec);
19521 if (arm_data == NULL)
19522 return FALSE;
19523
19524 mapcount = arm_data->mapcount;
19525 map = arm_data->map;
c7b8f16e
JB		 19526 errcount = arm_data->erratumcount;
19527
19528 if (errcount != 0)
19529 {
19530 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19531
19532 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19533 errnode = errnode->next)
19534 {
19535 bfd_vma target = errnode->vma - offset;
19536
19537 switch (errnode->type)
19538 {
19539 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19540 {
19541 bfd_vma branch_to_veneer;
19542 /* Original condition code of instruction, plus bit mask for
19543 ARM B instruction. */
19544 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19545 | 0x0a000000;
c7b8f16e
JB		 19546
19547 /* The instruction is before the label. */
91d6fa6a 19548 target -= 4;
c7b8f16e
JB		 19549
19550 /* Above offset included in -4 below. */
19551 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19552 - errnode->vma - 4;
c7b8f16e
JB		 19553
19554 if ((signed) branch_to_veneer < -(1 << 25)
19555 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19556 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19557 "range"), output_bfd);
c7b8f16e 19558
99059e56
RM		 19559 insn |= (branch_to_veneer >> 2) & 0xffffff;
19560 contents[endianflip ^ target] = insn & 0xff;
19561 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19562 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19563 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19564 }
19565 break;
c7b8f16e
JB		 19566
19567 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19568 {
19569 bfd_vma branch_from_veneer;
19570 unsigned int insn;
c7b8f16e 19571
99059e56
RM		 19572 /* Take size of veneer into account. */
19573 branch_from_veneer = errnode->u.v.branch->vma
19574 - errnode->vma - 12;
c7b8f16e
JB		 19575
19576 if ((signed) branch_from_veneer < -(1 << 25)
19577 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19578 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19579 "range"), output_bfd);
c7b8f16e 19580
99059e56
RM		 19581 /* Original instruction. */
19582 insn = errnode->u.v.branch->u.b.vfp_insn;
19583 contents[endianflip ^ target] = insn & 0xff;
19584 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19585 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19586 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19587
19588 /* Branch back to insn after original insn. */
19589 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19590 contents[endianflip ^ (target + 4)] = insn & 0xff;
19591 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19592 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19593 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19594 }
19595 break;
c7b8f16e 19596
99059e56
RM		 19597 default:
19598 abort ();
19599 }
19600 }
c7b8f16e 19601 }
e489d0ae 19602
a504d23a
LA		 19603 if (arm_data->stm32l4xx_erratumcount != 0)
19604 {
19605 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19606 stm32l4xx_errnode != 0;
19607 stm32l4xx_errnode = stm32l4xx_errnode->next)
19608 {
19609 bfd_vma target = stm32l4xx_errnode->vma - offset;
19610
19611 switch (stm32l4xx_errnode->type)
19612 {
19613 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19614 {
19615 unsigned int insn;
19616 bfd_vma branch_to_veneer =
19617 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19618
19619 if ((signed) branch_to_veneer < -(1 << 24)
19620 || (signed) branch_to_veneer >= (1 << 24))
19621 {
19622 bfd_vma out_of_range =
19623 ((signed) branch_to_veneer < -(1 << 24)) ?
19624 - branch_to_veneer - (1 << 24) :
19625 ((signed) branch_to_veneer >= (1 << 24)) ?
19626 branch_to_veneer - (1 << 24) : 0;
19627
4eca0228 19628 _bfd_error_handler
2dcf00ce 19629 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19630 "cannot create STM32L4XX veneer; "
19631 "jump out of range by %" PRId64 " bytes; "
19632 "cannot encode branch instruction"),
a504d23a 19633 output_bfd,
2dcf00ce
AM		 19634 (uint64_t) (stm32l4xx_errnode->vma - 4),
19635 (int64_t) out_of_range);
a504d23a
LA		 19636 continue;
19637 }
19638
19639 insn = create_instruction_branch_absolute
82188b29 19640 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19641
a2699ef2
AM		 19642 /* The instruction is before the label. */
19643 target -= 4;
19644
a504d23a
LA		 19645 put_thumb2_insn (globals, output_bfd,
19646 (bfd_vma) insn, contents + target);
19647 }
19648 break;
19649
19650 case STM32L4XX_ERRATUM_VENEER:
19651 {
82188b29
NC		 19652 bfd_byte * veneer;
19653 bfd_byte * veneer_r;
a504d23a
LA		 19654 unsigned int insn;
19655
82188b29
NC		 19656 veneer = contents + target;
19657 veneer_r = veneer
19658 + stm32l4xx_errnode->u.b.veneer->vma
19659 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19660
19661 if ((signed) (veneer_r - veneer -
19662 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19663 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19664 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19665 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19666 || (signed) (veneer_r - veneer) >= (1 << 24))
19667 {
90b6238f
AM		 19668 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19669 "veneer"), output_bfd);
a504d23a
LA		 19670 continue;
19671 }
19672
19673 /* Original instruction. */
19674 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19675
19676 stm32l4xx_create_replacing_stub
19677 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19678 }
19679 break;
19680
19681 default:
19682 abort ();
19683 }
19684 }
19685 }
19686
2468f9c9
PB		 19687 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19688 {
19689 arm_unwind_table_edit *edit_node
99059e56 19690 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19691 /* Now, sec->size is the size of the section we will write. The original
99059e56 19692 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19693 markers) was sec->rawsize. (This isn't the case if we perform no
19694 edits, then rawsize will be zero and we should use size). */
21d799b5 19695 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19696 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19697 unsigned int in_index, out_index;
19698 bfd_vma add_to_offsets = 0;
19699
7a0fb7be
NC		 19700 if (edited_contents == NULL)
19701 return FALSE;
2468f9c9 19702 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19703 {
2468f9c9
PB		 19704 if (edit_node)
19705 {
19706 unsigned int edit_index = edit_node->index;
b38cadfb 19707
2468f9c9 19708 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19709 {
2468f9c9
PB		 19710 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19711 contents + in_index * 8, add_to_offsets);
19712 out_index++;
19713 in_index++;
19714 }
19715 else if (in_index == edit_index
19716 || (in_index * 8 >= input_size
19717 && edit_index == UINT_MAX))
99059e56 19718 {
2468f9c9
PB		 19719 switch (edit_node->type)
19720 {
19721 case DELETE_EXIDX_ENTRY:
19722 in_index++;
19723 add_to_offsets += 8;
19724 break;
b38cadfb 19725
2468f9c9
PB		 19726 case INSERT_EXIDX_CANTUNWIND_AT_END:
19727 {
99059e56 19728 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19729 bfd_vma text_offset = text_sec->output_section->vma
19730 + text_sec->output_offset
19731 + text_sec->size;
19732 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19733 unsigned long prel31_offset;
2468f9c9
PB		 19734
19735 /* Note: this is meant to be equivalent to an
19736 R_ARM_PREL31 relocation. These synthetic
19737 EXIDX_CANTUNWIND markers are not relocated by the
19738 usual BFD method. */
19739 prel31_offset = (text_offset - exidx_offset)
19740 & 0x7ffffffful;
491d01d3
YU		 19741 if (bfd_link_relocatable (link_info))
19742 {
19743 /* Here relocation for new EXIDX_CANTUNWIND is
19744 created, so there is no need to
19745 adjust offset by hand. */
19746 prel31_offset = text_sec->output_offset
19747 + text_sec->size;
491d01d3 19748 }
2468f9c9
PB		 19749
19750 /* First address we can't unwind. */
19751 bfd_put_32 (output_bfd, prel31_offset,
19752 &edited_contents[out_index * 8]);
19753
19754 /* Code for EXIDX_CANTUNWIND. */
19755 bfd_put_32 (output_bfd, 0x1,
19756 &edited_contents[out_index * 8 + 4]);
19757
19758 out_index++;
19759 add_to_offsets -= 8;
19760 }
19761 break;
19762 }
b38cadfb 19763
2468f9c9
PB		 19764 edit_node = edit_node->next;
19765 }
19766 }
19767 else
19768 {
19769 /* No more edits, copy remaining entries verbatim. */
19770 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19771 contents + in_index * 8, add_to_offsets);
19772 out_index++;
19773 in_index++;
19774 }
19775 }
19776
19777 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19778 bfd_set_section_contents (output_bfd, sec->output_section,
19779 edited_contents,
19780 (file_ptr) sec->output_offset, sec->size);
19781
19782 return TRUE;
19783 }
19784
48229727
JB		 19785 /* Fix code to point to Cortex-A8 erratum stubs. */
19786 if (globals->fix_cortex_a8)
19787 {
19788 struct a8_branch_to_stub_data data;
19789
19790 data.writing_section = sec;
19791 data.contents = contents;
19792
a504d23a
LA		 19793 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19794 & data);
48229727
JB		 19795 }
19796
e489d0ae
PB		 19797 if (mapcount == 0)
19798 return FALSE;
19799
c7b8f16e 19800 if (globals->byteswap_code)
e489d0ae 19801 {
c7b8f16e 19802 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19803
c7b8f16e
JB		 19804 ptr = map[0].vma;
19805 for (i = 0; i < mapcount; i++)
99059e56
RM		 19806 {
19807 if (i == mapcount - 1)
c7b8f16e 19808 end = sec->size;
99059e56
RM		 19809 else
19810 end = map[i + 1].vma;
e489d0ae 19811
99059e56 19812 switch (map[i].type)
e489d0ae 19813 {
c7b8f16e
JB		 19814 case 'a':
19815 /* Byte swap code words. */
19816 while (ptr + 3 < end)
99059e56
RM		 19817 {
19818 tmp = contents[ptr];
19819 contents[ptr] = contents[ptr + 3];
19820 contents[ptr + 3] = tmp;
19821 tmp = contents[ptr + 1];
19822 contents[ptr + 1] = contents[ptr + 2];
19823 contents[ptr + 2] = tmp;
19824 ptr += 4;
19825 }
c7b8f16e 19826 break;
e489d0ae 19827
c7b8f16e
JB		 19828 case 't':
19829 /* Byte swap code halfwords. */
19830 while (ptr + 1 < end)
99059e56
RM		 19831 {
19832 tmp = contents[ptr];
19833 contents[ptr] = contents[ptr + 1];
19834 contents[ptr + 1] = tmp;
19835 ptr += 2;
19836 }
c7b8f16e
JB		 19837 break;
19838
19839 case 'd':
19840 /* Leave data alone. */
19841 break;
19842 }
99059e56
RM		 19843 ptr = end;
19844 }
e489d0ae 19845 }
8e3de13a 19846
93204d3a 19847 free (map);
47b2e99c 19848 arm_data->mapcount = -1;
c7b8f16e 19849 arm_data->mapsize = 0;
8e3de13a 19850 arm_data->map = NULL;
8e3de13a 19851
e489d0ae
PB		 19852 return FALSE;
19853}
19854
0beaef2b
PB		 19855/* Mangle thumb function symbols as we read them in. */
19856
8384fb8f 19857static bfd_boolean
0beaef2b
PB		 19858elf32_arm_swap_symbol_in (bfd * abfd,
19859 const void *psrc,
19860 const void *pshn,
19861 Elf_Internal_Sym *dst)
19862{
8384fb8f
AM		 19863 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19864 return FALSE;
39d911fc 19865 dst->st_target_internal = 0;
0beaef2b
PB		 19866
19867 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19868 the address. */
63e1a0fc
PB		 19869 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19870 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19871 {
63e1a0fc
PB		 19872 if (dst->st_value & 1)
19873 {
19874 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19875 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19876 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19877 }
19878 else
39d911fc 19879 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19880 }
19881 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19882 {
19883 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19884 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19885 }
35fc36a8 19886 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19887 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19888 else
39d911fc 19889 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19890
8384fb8f 19891 return TRUE;
0beaef2b
PB		 19892}
19893
19894
19895/* Mangle thumb function symbols as we write them out. */
19896
19897static void
19898elf32_arm_swap_symbol_out (bfd *abfd,
19899 const Elf_Internal_Sym *src,
19900 void *cdst,
19901 void *shndx)
19902{
19903 Elf_Internal_Sym newsym;
19904
19905 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19906 of the address set, as per the new EABI. We do this unconditionally
19907 because objcopy does not set the elf header flags until after
19908 it writes out the symbol table. */
39d911fc 19909 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19910 {
19911 newsym = *src;
34e77a92
RS		 19912 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19913 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19914 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19915 {
19916 /* Do this only for defined symbols. At link type, the static
19917 linker will simulate the work of dynamic linker of resolving
19918 symbols and will carry over the thumbness of found symbols to
19919 the output symbol table. It's not clear how it happens, but
19920 the thumbness of undefined symbols can well be different at
19921 runtime, and writing '1' for them will be confusing for users
19922 and possibly for dynamic linker itself.
19923 */
19924 newsym.st_value |= 1;
19925 }
906e58ca 19926
0beaef2b
PB		 19927 src = &newsym;
19928 }
19929 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19930}
19931
b294bdf8
MM		 19932/* Add the PT_ARM_EXIDX program header. */
19933
19934static bfd_boolean
906e58ca 19935elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19936 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19937{
19938 struct elf_segment_map *m;
19939 asection *sec;
19940
19941 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19942 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19943 {
19944 /* If there is already a PT_ARM_EXIDX header, then we do not
19945 want to add another one. This situation arises when running
19946 "strip"; the input binary already has the header. */
12bd6957 19947 m = elf_seg_map (abfd);
b294bdf8
MM		 19948 while (m && m->p_type != PT_ARM_EXIDX)
19949 m = m->next;
19950 if (!m)
19951 {
21d799b5 19952 m = (struct elf_segment_map *)
99059e56 19953 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19954 if (m == NULL)
19955 return FALSE;
19956 m->p_type = PT_ARM_EXIDX;
19957 m->count = 1;
19958 m->sections[0] = sec;
19959
12bd6957
AM		 19960 m->next = elf_seg_map (abfd);
19961 elf_seg_map (abfd) = m;
b294bdf8
MM		 19962 }
19963 }
19964
19965 return TRUE;
19966}
19967
19968/* We may add a PT_ARM_EXIDX program header. */
19969
19970static int
a6b96beb
AM		 19971elf32_arm_additional_program_headers (bfd *abfd,
19972 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19973{
19974 asection *sec;
19975
19976 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19977 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19978 return 1;
19979 else
19980 return 0;
19981}
19982
34e77a92
RS		 19983/* Hook called by the linker routine which adds symbols from an object
19984 file. */
19985
19986static bfd_boolean
19987elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19988 Elf_Internal_Sym *sym, const char **namep,
19989 flagword *flagsp, asection **secp, bfd_vma *valp)
19990{
c792917c
NC		 19991 if (elf32_arm_hash_table (info) == NULL)
19992 return FALSE;
19993
34e77a92
RS		 19994 if (elf32_arm_hash_table (info)->vxworks_p
19995 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
19996 flagsp, secp, valp))
19997 return FALSE;
19998
19999 return TRUE;
20000}
20001
0beaef2b 20002/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 20003const struct elf_size_info elf32_arm_size_info =
20004{
0beaef2b
PB		 20005 sizeof (Elf32_External_Ehdr),
20006 sizeof (Elf32_External_Phdr),
20007 sizeof (Elf32_External_Shdr),
20008 sizeof (Elf32_External_Rel),
20009 sizeof (Elf32_External_Rela),
20010 sizeof (Elf32_External_Sym),
20011 sizeof (Elf32_External_Dyn),
20012 sizeof (Elf_External_Note),
20013 4,
20014 1,
20015 32, 2,
20016 ELFCLASS32, EV_CURRENT,
20017 bfd_elf32_write_out_phdrs,
20018 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 20019 bfd_elf32_checksum_contents,
0beaef2b
PB		 20020 bfd_elf32_write_relocs,
20021 elf32_arm_swap_symbol_in,
20022 elf32_arm_swap_symbol_out,
20023 bfd_elf32_slurp_reloc_table,
20024 bfd_elf32_slurp_symbol_table,
20025 bfd_elf32_swap_dyn_in,
20026 bfd_elf32_swap_dyn_out,
20027 bfd_elf32_swap_reloc_in,
20028 bfd_elf32_swap_reloc_out,
20029 bfd_elf32_swap_reloca_in,
20030 bfd_elf32_swap_reloca_out
20031};
20032
685e70ae
VK		 20033static bfd_vma
20034read_code32 (const bfd *abfd, const bfd_byte *addr)
20035{
20036 /* V7 BE8 code is always little endian. */
20037 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20038 return bfd_getl32 (addr);
20039
20040 return bfd_get_32 (abfd, addr);
20041}
20042
20043static bfd_vma
20044read_code16 (const bfd *abfd, const bfd_byte *addr)
20045{
20046 /* V7 BE8 code is always little endian. */
20047 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20048 return bfd_getl16 (addr);
20049
20050 return bfd_get_16 (abfd, addr);
20051}
20052
6a631e86
YG		 20053/* Return size of plt0 entry starting at ADDR
20054 or (bfd_vma) -1 if size can not be determined. */
20055
20056static bfd_vma
20057elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
20058{
20059 bfd_vma first_word;
20060 bfd_vma plt0_size;
20061
685e70ae 20062 first_word = read_code32 (abfd, addr);
6a631e86
YG		 20063
20064 if (first_word == elf32_arm_plt0_entry[0])
20065 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
20066 else if (first_word == elf32_thumb2_plt0_entry[0])
20067 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
20068 else
20069 /* We don't yet handle this PLT format. */
20070 return (bfd_vma) -1;
20071
20072 return plt0_size;
20073}
20074
20075/* Return size of plt entry starting at offset OFFSET
20076 of plt section located at address START
20077 or (bfd_vma) -1 if size can not be determined. */
20078
20079static bfd_vma
20080elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
20081{
20082 bfd_vma first_insn;
20083 bfd_vma plt_size = 0;
20084 const bfd_byte *addr = start + offset;
20085
20086 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 20087 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 20088 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
20089
20090 /* Respect Thumb stub if necessary. */
685e70ae 20091 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 20092 {
20093 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
20094 }
20095
20096 /* Strip immediate from first add. */
685e70ae 20097 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 20098
20099#ifdef FOUR_WORD_PLT
20100 if (first_insn == elf32_arm_plt_entry[0])
20101 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20102#else
20103 if (first_insn == elf32_arm_plt_entry_long[0])
20104 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20105 else if (first_insn == elf32_arm_plt_entry_short[0])
20106 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20107#endif
20108 else
20109 /* We don't yet handle this PLT format. */
20110 return (bfd_vma) -1;
20111
20112 return plt_size;
20113}
20114
20115/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20116
20117static long
20118elf32_arm_get_synthetic_symtab (bfd *abfd,
20119 long symcount ATTRIBUTE_UNUSED,
20120 asymbol **syms ATTRIBUTE_UNUSED,
20121 long dynsymcount,
20122 asymbol **dynsyms,
20123 asymbol **ret)
20124{
20125 asection *relplt;
20126 asymbol *s;
20127 arelent *p;
20128 long count, i, n;
20129 size_t size;
20130 Elf_Internal_Shdr *hdr;
20131 char *names;
20132 asection *plt;
20133 bfd_vma offset;
20134 bfd_byte *data;
20135
20136 *ret = NULL;
20137
20138 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20139 return 0;
20140
20141 if (dynsymcount <= 0)
20142 return 0;
20143
20144 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20145 if (relplt == NULL)
20146 return 0;
20147
20148 hdr = &elf_section_data (relplt)->this_hdr;
20149 if (hdr->sh_link != elf_dynsymtab (abfd)
20150 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20151 return 0;
20152
20153 plt = bfd_get_section_by_name (abfd, ".plt");
20154 if (plt == NULL)
20155 return 0;
20156
20157 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20158 return -1;
20159
20160 data = plt->contents;
20161 if (data == NULL)
20162 {
20163 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20164 return -1;
20165 bfd_cache_section_contents((asection *) plt, data);
20166 }
20167
20168 count = relplt->size / hdr->sh_entsize;
20169 size = count * sizeof (asymbol);
20170 p = relplt->relocation;
20171 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20172 {
20173 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20174 if (p->addend != 0)
20175 size += sizeof ("+0x") - 1 + 8;
20176 }
20177
20178 s = *ret = (asymbol *) bfd_malloc (size);
20179 if (s == NULL)
20180 return -1;
20181
20182 offset = elf32_arm_plt0_size (abfd, data);
20183 if (offset == (bfd_vma) -1)
20184 return -1;
20185
20186 names = (char *) (s + count);
20187 p = relplt->relocation;
20188 n = 0;
20189 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20190 {
20191 size_t len;
20192
20193 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20194 if (plt_size == (bfd_vma) -1)
20195 break;
20196
20197 *s = **p->sym_ptr_ptr;
20198 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20199 we are defining a symbol, ensure one of them is set. */
20200 if ((s->flags & BSF_LOCAL) == 0)
20201 s->flags |= BSF_GLOBAL;
20202 s->flags |= BSF_SYNTHETIC;
20203 s->section = plt;
20204 s->value = offset;
20205 s->name = names;
20206 s->udata.p = NULL;
20207 len = strlen ((*p->sym_ptr_ptr)->name);
20208 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20209 names += len;
20210 if (p->addend != 0)
20211 {
20212 char buf[30], *a;
20213
20214 memcpy (names, "+0x", sizeof ("+0x") - 1);
20215 names += sizeof ("+0x") - 1;
20216 bfd_sprintf_vma (abfd, buf, p->addend);
20217 for (a = buf; *a == '0'; ++a)
20218 ;
20219 len = strlen (a);
20220 memcpy (names, a, len);
20221 names += len;
20222 }
20223 memcpy (names, "@plt", sizeof ("@plt"));
20224 names += sizeof ("@plt");
20225 ++s, ++n;
20226 offset += plt_size;
20227 }
20228
20229 return n;
20230}
20231
ac4c9b04
MG		 20232static bfd_boolean
20233elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
20234{
f0728ee3
AV		 20235 if (hdr->sh_flags & SHF_ARM_PURECODE)
20236 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20237 return TRUE;
20238}
20239
20240static flagword
20241elf32_arm_lookup_section_flags (char *flag_name)
20242{
f0728ee3
AV		 20243 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20244 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20245
20246 return SEC_NO_FLAGS;
20247}
20248
491d01d3
YU		 20249static unsigned int
20250elf32_arm_count_additional_relocs (asection *sec)
20251{
20252 struct _arm_elf_section_data *arm_data;
20253 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20254
6342be70 20255 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20256}
20257
5522f910 20258/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20259 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20260 FALSE otherwise. ISECTION is the best guess matching section from the
20261 input bfd IBFD, but it might be NULL. */
20262
20263static bfd_boolean
20264elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20265 bfd *obfd ATTRIBUTE_UNUSED,
20266 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20267 Elf_Internal_Shdr *osection)
20268{
20269 switch (osection->sh_type)
20270 {
20271 case SHT_ARM_EXIDX:
20272 {
20273 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20274 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20275 unsigned i = 0;
20276
20277 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20278 osection->sh_info = 0;
20279
20280 /* The sh_link field must be set to the text section associated with
20281 this index section. Unfortunately the ARM EHABI does not specify
20282 exactly how to determine this association. Our caller does try
20283 to match up OSECTION with its corresponding input section however
20284 so that is a good first guess. */
20285 if (isection != NULL
20286 && osection->bfd_section != NULL
20287 && isection->bfd_section != NULL
20288 && isection->bfd_section->output_section != NULL
20289 && isection->bfd_section->output_section == osection->bfd_section
20290 && iheaders != NULL
20291 && isection->sh_link > 0
20292 && isection->sh_link < elf_numsections (ibfd)
20293 && iheaders[isection->sh_link]->bfd_section != NULL
20294 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20295 )
20296 {
20297 for (i = elf_numsections (obfd); i-- > 0;)
20298 if (oheaders[i]->bfd_section
20299 == iheaders[isection->sh_link]->bfd_section->output_section)
20300 break;
20301 }
9eaff861 20302
5522f910
NC		 20303 if (i == 0)
20304 {
20305 /* Failing that we have to find a matching section ourselves. If
20306 we had the output section name available we could compare that
20307 with input section names. Unfortunately we don't. So instead
20308 we use a simple heuristic and look for the nearest executable
20309 section before this one. */
20310 for (i = elf_numsections (obfd); i-- > 0;)
20311 if (oheaders[i] == osection)
20312 break;
20313 if (i == 0)
20314 break;
20315
20316 while (i-- > 0)
20317 if (oheaders[i]->sh_type == SHT_PROGBITS
20318 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20319 == (SHF_ALLOC | SHF_EXECINSTR))
20320 break;
20321 }
20322
20323 if (i)
20324 {
20325 osection->sh_link = i;
20326 /* If the text section was part of a group
20327 then the index section should be too. */
20328 if (oheaders[i]->sh_flags & SHF_GROUP)
20329 osection->sh_flags |= SHF_GROUP;
20330 return TRUE;
20331 }
20332 }
20333 break;
20334
20335 case SHT_ARM_PREEMPTMAP:
20336 osection->sh_flags = SHF_ALLOC;
20337 break;
20338
20339 case SHT_ARM_ATTRIBUTES:
20340 case SHT_ARM_DEBUGOVERLAY:
20341 case SHT_ARM_OVERLAYSECTION:
20342 default:
20343 break;
20344 }
20345
20346 return FALSE;
20347}
20348
d691934d
NC		 20349/* Returns TRUE if NAME is an ARM mapping symbol.
20350 Traditionally the symbols $a, $d and $t have been used.
20351 The ARM ELF standard also defines $x (for A64 code). It also allows a
20352 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20353 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20354 not support them here. $t.x indicates the start of ThumbEE instructions. */
20355
20356static bfd_boolean
20357is_arm_mapping_symbol (const char * name)
20358{
20359 return name != NULL /* Paranoia. */
20360 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20361 the mapping symbols could have acquired a prefix.
20362 We do not support this here, since such symbols no
20363 longer conform to the ARM ELF ABI. */
20364 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20365 && (name[2] == 0 || name[2] == '.');
20366 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20367 any characters that follow the period are legal characters for the body
20368 of a symbol's name. For now we just assume that this is the case. */
20369}
20370
fca2a38f
NC		 20371/* Make sure that mapping symbols in object files are not removed via the
20372 "strip --strip-unneeded" tool. These symbols are needed in order to
20373 correctly generate interworking veneers, and for byte swapping code
20374 regions. Once an object file has been linked, it is safe to remove the
20375 symbols as they will no longer be needed. */
20376
20377static void
20378elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20379{
20380 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20381 && sym->section != bfd_abs_section_ptr
d691934d 20382 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20383 sym->flags |= BSF_KEEP;
20384}
20385
5522f910
NC		 20386#undef elf_backend_copy_special_section_fields
20387#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20388
252b5132 20389#define ELF_ARCH bfd_arch_arm
ae95ffa6 20390#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20391#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20392#ifdef __QNXTARGET__
20393#define ELF_MAXPAGESIZE 0x1000
20394#else
7572ca89 20395#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20396#endif
b1342370 20397#define ELF_MINPAGESIZE 0x1000
24718e3b 20398#define ELF_COMMONPAGESIZE 0x1000
252b5132 20399
07d6d2b8 20400#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20401
99e4ae17
AJ		 20402#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20403#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20404#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20405#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20406#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20407#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20408#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8 20409#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20410#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20411#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20412#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20413#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20414
07d6d2b8 20415#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
e7679060 20416#define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
07d6d2b8 20417#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20418#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20419#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20420#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20421#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20422#define elf_backend_write_section elf32_arm_write_section
252b5132 20423#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20424#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20425#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20426#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20427#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20428#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20429#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ed7e9d0b 20430#define elf_backend_init_file_header elf32_arm_init_file_header
99e4ae17 20431#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20432#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20433#define elf_backend_fake_sections elf32_arm_fake_sections
20434#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20435#define elf_backend_final_write_processing elf32_arm_final_write_processing
20436#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20437#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20438#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20439#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20440#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20441#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20442#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20443#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20444#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20445#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20446
20447#define elf_backend_can_refcount 1
20448#define elf_backend_can_gc_sections 1
20449#define elf_backend_plt_readonly 1
20450#define elf_backend_want_got_plt 1
20451#define elf_backend_want_plt_sym 0
5474d94f 20452#define elf_backend_want_dynrelro 1
906e58ca
NC		 20453#define elf_backend_may_use_rel_p 1
20454#define elf_backend_may_use_rela_p 0
4e7fd91e 20455#define elf_backend_default_use_rela_p 0
64f52338 20456#define elf_backend_dtrel_excludes_plt 1
252b5132 20457
04f7c78d 20458#define elf_backend_got_header_size 12
b68a20d6 20459#define elf_backend_extern_protected_data 1
04f7c78d 20460
07d6d2b8 20461#undef elf_backend_obj_attrs_vendor
906e58ca 20462#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20463#undef elf_backend_obj_attrs_section
906e58ca 20464#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20465#undef elf_backend_obj_attrs_arg_type
906e58ca 20466#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20467#undef elf_backend_obj_attrs_section_type
104d59d1 20468#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20469#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20470#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20471
07d6d2b8 20472#undef elf_backend_section_flags
ac4c9b04 20473#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20474#undef elf_backend_lookup_section_flags_hook
20475#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20476
a2f63b2e
MR		 20477#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20478
252b5132 20479#include "elf32-target.h"
7f266840 20480
b38cadfb
NC		 20481/* Native Client targets. */
20482
20483#undef TARGET_LITTLE_SYM
6d00b590 20484#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20485#undef TARGET_LITTLE_NAME
20486#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20487#undef TARGET_BIG_SYM
6d00b590 20488#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20489#undef TARGET_BIG_NAME
20490#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20491
20492/* Like elf32_arm_link_hash_table_create -- but overrides
20493 appropriately for NaCl. */
20494
20495static struct bfd_link_hash_table *
20496elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20497{
20498 struct bfd_link_hash_table *ret;
20499
20500 ret = elf32_arm_link_hash_table_create (abfd);
20501 if (ret)
20502 {
20503 struct elf32_arm_link_hash_table *htab
20504 = (struct elf32_arm_link_hash_table *) ret;
20505
20506 htab->nacl_p = 1;
20507
20508 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20509 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20510 }
20511 return ret;
20512}
20513
20514/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20515 really need to use elf32_arm_modify_segment_map. But we do it
20516 anyway just to reduce gratuitous differences with the stock ARM backend. */
20517
20518static bfd_boolean
20519elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20520{
20521 return (elf32_arm_modify_segment_map (abfd, info)
20522 && nacl_modify_segment_map (abfd, info));
20523}
20524
cc364be6
AM		 20525static bfd_boolean
20526elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20527{
cc364be6
AM		 20528 arm_final_write_processing (abfd);
20529 return nacl_final_write_processing (abfd);
887badb3
RM		 20530}
20531
6a631e86
YG		 20532static bfd_vma
20533elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20534 const arelent *rel ATTRIBUTE_UNUSED)
20535{
20536 return plt->vma
20537 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20538 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20539}
887badb3 20540
b38cadfb 20541#undef elf32_bed
6a631e86 20542#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20543#undef bfd_elf32_bfd_link_hash_table_create
20544#define bfd_elf32_bfd_link_hash_table_create \
20545 elf32_arm_nacl_link_hash_table_create
20546#undef elf_backend_plt_alignment
6a631e86 20547#define elf_backend_plt_alignment 4
b38cadfb
NC		 20548#undef elf_backend_modify_segment_map
20549#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
6d6c25c8
AM		 20550#undef elf_backend_modify_headers
20551#define elf_backend_modify_headers nacl_modify_headers
887badb3
RM		 20552#undef elf_backend_final_write_processing
20553#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20554#undef bfd_elf32_get_synthetic_symtab
20555#undef elf_backend_plt_sym_val
20556#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20557#undef elf_backend_copy_special_section_fields
b38cadfb 20558
887badb3
RM		 20559#undef ELF_MINPAGESIZE
20560#undef ELF_COMMONPAGESIZE
20561
b38cadfb
NC		 20562
20563#include "elf32-target.h"
20564
20565/* Reset to defaults. */
20566#undef elf_backend_plt_alignment
20567#undef elf_backend_modify_segment_map
20568#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
6d6c25c8 20569#undef elf_backend_modify_headers
887badb3
RM		 20570#undef elf_backend_final_write_processing
20571#define elf_backend_final_write_processing elf32_arm_final_write_processing
20572#undef ELF_MINPAGESIZE
20573#define ELF_MINPAGESIZE 0x1000
20574#undef ELF_COMMONPAGESIZE
20575#define ELF_COMMONPAGESIZE 0x1000
20576
b38cadfb 20577
617a5ada
CL		 20578/* FDPIC Targets. */
20579
20580#undef TARGET_LITTLE_SYM
20581#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20582#undef TARGET_LITTLE_NAME
20583#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20584#undef TARGET_BIG_SYM
20585#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20586#undef TARGET_BIG_NAME
20587#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20588#undef elf_match_priority
20589#define elf_match_priority 128
18a20338
CL		 20590#undef ELF_OSABI
20591#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20592
20593/* Like elf32_arm_link_hash_table_create -- but overrides
20594 appropriately for FDPIC. */
20595
20596static struct bfd_link_hash_table *
20597elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20598{
20599 struct bfd_link_hash_table *ret;
20600
20601 ret = elf32_arm_link_hash_table_create (abfd);
20602 if (ret)
20603 {
20604 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20605
20606 htab->fdpic_p = 1;
20607 }
20608 return ret;
20609}
20610
e8b09b87
CL		 20611/* We need dynamic symbols for every section, since segments can
20612 relocate independently. */
20613static bfd_boolean
20614elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20615 struct bfd_link_info *info
20616 ATTRIBUTE_UNUSED,
20617 asection *p ATTRIBUTE_UNUSED)
20618{
20619 switch (elf_section_data (p)->this_hdr.sh_type)
20620 {
20621 case SHT_PROGBITS:
20622 case SHT_NOBITS:
20623 /* If sh_type is yet undecided, assume it could be
20624 SHT_PROGBITS/SHT_NOBITS. */
20625 case SHT_NULL:
20626 return FALSE;
20627
20628 /* There shouldn't be section relative relocations
20629 against any other section. */
20630 default:
20631 return TRUE;
20632 }
20633}
20634
617a5ada
CL		 20635#undef elf32_bed
20636#define elf32_bed elf32_arm_fdpic_bed
20637
20638#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20639#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20640
e8b09b87
CL		 20641#undef elf_backend_omit_section_dynsym
20642#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20643
617a5ada 20644#include "elf32-target.h"
e8b09b87 20645
617a5ada 20646#undef elf_match_priority
18a20338 20647#undef ELF_OSABI
e8b09b87 20648#undef elf_backend_omit_section_dynsym
617a5ada 20649
906e58ca 20650/* VxWorks Targets. */
4e7fd91e 20651
07d6d2b8
AM		 20652#undef TARGET_LITTLE_SYM
20653#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20654#undef TARGET_LITTLE_NAME
20655#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20656#undef TARGET_BIG_SYM
20657#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20658#undef TARGET_BIG_NAME
20659#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20660
20661/* Like elf32_arm_link_hash_table_create -- but overrides
20662 appropriately for VxWorks. */
906e58ca 20663
4e7fd91e
PB		 20664static struct bfd_link_hash_table *
20665elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20666{
20667 struct bfd_link_hash_table *ret;
20668
20669 ret = elf32_arm_link_hash_table_create (abfd);
20670 if (ret)
20671 {
20672 struct elf32_arm_link_hash_table *htab
00a97672 20673 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20674 htab->use_rel = 0;
00a97672 20675 htab->vxworks_p = 1;
4e7fd91e
PB		 20676 }
20677 return ret;
906e58ca 20678}
4e7fd91e 20679
cc364be6
AM		 20680static bfd_boolean
20681elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20682{
cc364be6
AM		 20683 arm_final_write_processing (abfd);
20684 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20685}
20686
906e58ca 20687#undef elf32_bed
4e7fd91e
PB		 20688#define elf32_bed elf32_arm_vxworks_bed
20689
906e58ca
NC		 20690#undef bfd_elf32_bfd_link_hash_table_create
20691#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20692#undef elf_backend_final_write_processing
20693#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20694#undef elf_backend_emit_relocs
9eaff861 20695#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20696
906e58ca 20697#undef elf_backend_may_use_rel_p
00a97672 20698#define elf_backend_may_use_rel_p 0
906e58ca 20699#undef elf_backend_may_use_rela_p
00a97672 20700#define elf_backend_may_use_rela_p 1
906e58ca 20701#undef elf_backend_default_use_rela_p
00a97672 20702#define elf_backend_default_use_rela_p 1
906e58ca 20703#undef elf_backend_want_plt_sym
00a97672 20704#define elf_backend_want_plt_sym 1
906e58ca 20705#undef ELF_MAXPAGESIZE
00a97672 20706#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20707
20708#include "elf32-target.h"
20709
20710
21d799b5
NC		 20711/* Merge backend specific data from an object file to the output
20712 object file when linking. */
20713
20714static bfd_boolean
50e03d47 20715elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20716{
50e03d47 20717 bfd *obfd = info->output_bfd;
21d799b5
NC		 20718 flagword out_flags;
20719 flagword in_flags;
20720 bfd_boolean flags_compatible = TRUE;
20721 asection *sec;
20722
cc643b88 20723 /* Check if we have the same endianness. */
50e03d47 20724 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20725 return FALSE;
20726
20727 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20728 return TRUE;
20729
50e03d47 20730 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20731 return FALSE;
20732
20733 /* The input BFD must have had its flags initialised. */
20734 /* The following seems bogus to me -- The flags are initialized in
20735 the assembler but I don't think an elf_flags_init field is
20736 written into the object. */
20737 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20738
20739 in_flags = elf_elfheader (ibfd)->e_flags;
20740 out_flags = elf_elfheader (obfd)->e_flags;
20741
20742 /* In theory there is no reason why we couldn't handle this. However
20743 in practice it isn't even close to working and there is no real
20744 reason to want it. */
20745 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20746 && !(ibfd->flags & DYNAMIC)
20747 && (in_flags & EF_ARM_BE8))
20748 {
871b3ab2 20749 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20750 ibfd);
20751 return FALSE;
20752 }
20753
20754 if (!elf_flags_init (obfd))
20755 {
20756 /* If the input is the default architecture and had the default
20757 flags then do not bother setting the flags for the output
20758 architecture, instead allow future merges to do this. If no
20759 future merges ever set these flags then they will retain their
99059e56
RM		 20760 uninitialised values, which surprise surprise, correspond
20761 to the default values. */
21d799b5
NC		 20762 if (bfd_get_arch_info (ibfd)->the_default
20763 && elf_elfheader (ibfd)->e_flags == 0)
20764 return TRUE;
20765
20766 elf_flags_init (obfd) = TRUE;
20767 elf_elfheader (obfd)->e_flags = in_flags;
20768
20769 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20770 && bfd_get_arch_info (obfd)->the_default)
20771 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20772
20773 return TRUE;
20774 }
20775
20776 /* Determine what should happen if the input ARM architecture
20777 does not match the output ARM architecture. */
20778 if (! bfd_arm_merge_machines (ibfd, obfd))
20779 return FALSE;
20780
20781 /* Identical flags must be compatible. */
20782 if (in_flags == out_flags)
20783 return TRUE;
20784
20785 /* Check to see if the input BFD actually contains any sections. If
20786 not, its flags may not have been initialised either, but it
20787 cannot actually cause any incompatiblity. Do not short-circuit
20788 dynamic objects; their section list may be emptied by
20789 elf_link_add_object_symbols.
20790
20791 Also check to see if there are no code sections in the input.
20792 In this case there is no need to check for code specific flags.
20793 XXX - do we need to worry about floating-point format compatability
20794 in data sections ? */
20795 if (!(ibfd->flags & DYNAMIC))
20796 {
20797 bfd_boolean null_input_bfd = TRUE;
20798 bfd_boolean only_data_sections = TRUE;
20799
20800 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20801 {
20802 /* Ignore synthetic glue sections. */
20803 if (strcmp (sec->name, ".glue_7")
20804 && strcmp (sec->name, ".glue_7t"))
20805 {
fd361982 20806 if ((bfd_section_flags (sec)
21d799b5
NC		 20807 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20808 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20809 only_data_sections = FALSE;
21d799b5
NC		 20810
20811 null_input_bfd = FALSE;
20812 break;
20813 }
20814 }
20815
20816 if (null_input_bfd || only_data_sections)
20817 return TRUE;
20818 }
20819
20820 /* Complain about various flag mismatches. */
20821 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20822 EF_ARM_EABI_VERSION (out_flags)))
20823 {
20824 _bfd_error_handler
90b6238f 20825 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20826 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20827 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20828 return FALSE;
20829 }
20830
20831 /* Not sure what needs to be checked for EABI versions >= 1. */
20832 /* VxWorks libraries do not use these flags. */
20833 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20834 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20835 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20836 {
20837 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20838 {
20839 _bfd_error_handler
871b3ab2 20840 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20841 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20842 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20843 flags_compatible = FALSE;
20844 }
20845
20846 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20847 {
20848 if (in_flags & EF_ARM_APCS_FLOAT)
20849 _bfd_error_handler
871b3ab2 20850 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20851 ibfd, obfd);
20852 else
20853 _bfd_error_handler
871b3ab2 20854 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20855 ibfd, obfd);
20856
20857 flags_compatible = FALSE;
20858 }
20859
20860 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20861 {
20862 if (in_flags & EF_ARM_VFP_FLOAT)
20863 _bfd_error_handler
90b6238f
AM		 20864 (_("error: %pB uses %s instructions, whereas %pB does not"),
20865 ibfd, "VFP", obfd);
21d799b5
NC		 20866 else
20867 _bfd_error_handler
90b6238f
AM		 20868 (_("error: %pB uses %s instructions, whereas %pB does not"),
20869 ibfd, "FPA", obfd);
21d799b5
NC		 20870
20871 flags_compatible = FALSE;
20872 }
20873
20874 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20875 {
20876 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20877 _bfd_error_handler
90b6238f
AM		 20878 (_("error: %pB uses %s instructions, whereas %pB does not"),
20879 ibfd, "Maverick", obfd);
21d799b5
NC		 20880 else
20881 _bfd_error_handler
90b6238f
AM		 20882 (_("error: %pB does not use %s instructions, whereas %pB does"),
20883 ibfd, "Maverick", obfd);
21d799b5
NC		 20884
20885 flags_compatible = FALSE;
20886 }
20887
20888#ifdef EF_ARM_SOFT_FLOAT
20889 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20890 {
20891 /* We can allow interworking between code that is VFP format
20892 layout, and uses either soft float or integer regs for
20893 passing floating point arguments and results. We already
20894 know that the APCS_FLOAT flags match; similarly for VFP
20895 flags. */
20896 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20897 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20898 {
20899 if (in_flags & EF_ARM_SOFT_FLOAT)
20900 _bfd_error_handler
871b3ab2 20901 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20902 ibfd, obfd);
20903 else
20904 _bfd_error_handler
871b3ab2 20905 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20906 ibfd, obfd);
20907
20908 flags_compatible = FALSE;
20909 }
20910 }
20911#endif
20912
20913 /* Interworking mismatch is only a warning. */
20914 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20915 {
20916 if (in_flags & EF_ARM_INTERWORK)
20917 {
20918 _bfd_error_handler
90b6238f 20919 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20920 ibfd, obfd);
20921 }
20922 else
20923 {
20924 _bfd_error_handler
90b6238f 20925 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20926 ibfd, obfd);
20927 }
20928 }
20929 }
20930
20931 return flags_compatible;
20932}
20933
20934
906e58ca 20935/* Symbian OS Targets. */
7f266840 20936
07d6d2b8
AM		 20937#undef TARGET_LITTLE_SYM
20938#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20939#undef TARGET_LITTLE_NAME
20940#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20941#undef TARGET_BIG_SYM
20942#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20943#undef TARGET_BIG_NAME
20944#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20945
20946/* Like elf32_arm_link_hash_table_create -- but overrides
20947 appropriately for Symbian OS. */
906e58ca 20948
7f266840
DJ		 20949static struct bfd_link_hash_table *
20950elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20951{
20952 struct bfd_link_hash_table *ret;
20953
20954 ret = elf32_arm_link_hash_table_create (abfd);
20955 if (ret)
20956 {
20957 struct elf32_arm_link_hash_table *htab
20958 = (struct elf32_arm_link_hash_table *)ret;
20959 /* There is no PLT header for Symbian OS. */
20960 htab->plt_header_size = 0;
95720a86
DJ		 20961 /* The PLT entries are each one instruction and one word. */
20962 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 20963 htab->symbian_p = 1;
33bfe774
JB		 20964 /* Symbian uses armv5t or above, so use_blx is always true. */
20965 htab->use_blx = 1;
67687978 20966 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20967 }
20968 return ret;
906e58ca 20969}
7f266840 20970
b35d266b 20971static const struct bfd_elf_special_section
551b43fd 20972elf32_arm_symbian_special_sections[] =
7f266840 20973{
5cd3778d
MM		 20974 /* In a BPABI executable, the dynamic linking sections do not go in
20975 the loadable read-only segment. The post-linker may wish to
20976 refer to these sections, but they are not part of the final
20977 program image. */
07d6d2b8
AM		 20978 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20979 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20980 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20981 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20982 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20983 /* These sections do not need to be writable as the SymbianOS
20984 postlinker will arrange things so that no dynamic relocation is
20985 required. */
07d6d2b8
AM		 20986 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20987 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20988 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 20989 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 20990};
20991
c3c76620 20992static void
906e58ca 20993elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 20994 struct bfd_link_info *link_info)
c3c76620
MM		 20995{
20996 /* BPABI objects are never loaded directly by an OS kernel; they are
20997 processed by a postlinker first, into an OS-specific format. If
20998 the D_PAGED bit is set on the file, BFD will align segments on
20999 page boundaries, so that an OS can directly map the file. With
21000 BPABI objects, that just results in wasted space. In addition,
21001 because we clear the D_PAGED bit, map_sections_to_segments will
21002 recognize that the program headers should not be mapped into any
21003 loadable segment. */
21004 abfd->flags &= ~D_PAGED;
906e58ca 21005 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 21006}
7f266840
DJ		 21007
21008static bfd_boolean
906e58ca 21009elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 21010 struct bfd_link_info *info)
7f266840
DJ		 21011{
21012 struct elf_segment_map *m;
21013 asection *dynsec;
21014
7f266840
DJ		 21015 /* BPABI shared libraries and executables should have a PT_DYNAMIC
21016 segment. However, because the .dynamic section is not marked
21017 with SEC_LOAD, the generic ELF code will not create such a
21018 segment. */
21019 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
21020 if (dynsec)
21021 {
12bd6957 21022 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 21023 if (m->p_type == PT_DYNAMIC)
21024 break;
21025
21026 if (m == NULL)
21027 {
21028 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 21029 m->next = elf_seg_map (abfd);
21030 elf_seg_map (abfd) = m;
8ded5a0f 21031 }
7f266840
DJ		 21032 }
21033
b294bdf8
MM		 21034 /* Also call the generic arm routine. */
21035 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 21036}
21037
95720a86
DJ		 21038/* Return address for Ith PLT stub in section PLT, for relocation REL
21039 or (bfd_vma) -1 if it should not be included. */
21040
21041static bfd_vma
21042elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
21043 const arelent *rel ATTRIBUTE_UNUSED)
21044{
21045 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
21046}
21047
8029a119 21048#undef elf32_bed
7f266840
DJ		 21049#define elf32_bed elf32_arm_symbian_bed
21050
21051/* The dynamic sections are not allocated on SymbianOS; the postlinker
21052 will process them and then discard them. */
906e58ca 21053#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 21054#define ELF_DYNAMIC_SEC_FLAGS \
21055 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
21056
9eaff861 21057#undef elf_backend_emit_relocs
c3c76620 21058
906e58ca
NC		 21059#undef bfd_elf32_bfd_link_hash_table_create
21060#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
21061#undef elf_backend_special_sections
07d6d2b8 21062#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 21063#undef elf_backend_begin_write_processing
21064#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
21065#undef elf_backend_final_write_processing
21066#define elf_backend_final_write_processing elf32_arm_final_write_processing
21067
21068#undef elf_backend_modify_segment_map
7f266840
DJ		 21069#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
21070
21071/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 21072#undef elf_backend_got_header_size
7f266840
DJ		 21073#define elf_backend_got_header_size 0
21074
21075/* Similarly, there is no .got.plt section. */
906e58ca 21076#undef elf_backend_want_got_plt
7f266840
DJ		 21077#define elf_backend_want_got_plt 0
21078
906e58ca 21079#undef elf_backend_plt_sym_val
95720a86
DJ		 21080#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21081
906e58ca 21082#undef elf_backend_may_use_rel_p
00a97672 21083#define elf_backend_may_use_rel_p 1
906e58ca 21084#undef elf_backend_may_use_rela_p
00a97672 21085#define elf_backend_may_use_rela_p 0
906e58ca 21086#undef elf_backend_default_use_rela_p
00a97672 21087#define elf_backend_default_use_rela_p 0
906e58ca 21088#undef elf_backend_want_plt_sym
00a97672 21089#define elf_backend_want_plt_sym 0
64f52338
AM		 21090#undef elf_backend_dtrel_excludes_plt
21091#define elf_backend_dtrel_excludes_plt 0
906e58ca 21092#undef ELF_MAXPAGESIZE
00a97672 21093#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 21094
7f266840 21095#include "elf32-target.h"
GDB Binutils - Deliverables
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