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Add support for ARMv8-M Mainline with DSP extension
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
252b5132
RH		 2141/* The name of the dynamic interpreter. This is put in the .interp
2142 section. */
2143#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2144
0855e32b 2145static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2146{
2147 0xe08e0000, /* add r0, lr, r0 */
2148 0xe5901004, /* ldr r1, [r0,#4] */
2149 0xe12fff11, /* bx r1 */
2150};
0855e32b
NS		 2151
2152static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2153{
2154 0xe52d2004, /* push {r2} */
2155 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2156 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2157 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2158 0xe081100f, /* 2: add r1, pc */
2159 0xe12fff12, /* bx r2 */
2160 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2161 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2162 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2163};
0855e32b 2164
5e681ec4
PB		 2165#ifdef FOUR_WORD_PLT
2166
252b5132
RH		 2167/* The first entry in a procedure linkage table looks like
2168 this. It is set up so that any shared library function that is
59f2c4e7 2169 called before the relocation has been set up calls the dynamic
9b485d32 2170 linker first. */
e5a52504 2171static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2172{
2173 0xe52de004, /* str lr, [sp, #-4]! */
2174 0xe59fe010, /* ldr lr, [pc, #16] */
2175 0xe08fe00e, /* add lr, pc, lr */
2176 0xe5bef008, /* ldr pc, [lr, #8]! */
2177};
5e681ec4
PB		 2178
2179/* Subsequent entries in a procedure linkage table look like
2180 this. */
e5a52504 2181static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2182{
2183 0xe28fc600, /* add ip, pc, #NN */
2184 0xe28cca00, /* add ip, ip, #NN */
2185 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2186 0x00000000, /* unused */
2187};
5e681ec4 2188
eed94f8f 2189#else /* not FOUR_WORD_PLT */
5e681ec4 2190
5e681ec4
PB		 2191/* The first entry in a procedure linkage table looks like
2192 this. It is set up so that any shared library function that is
2193 called before the relocation has been set up calls the dynamic
2194 linker first. */
e5a52504 2195static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2196{
2197 0xe52de004, /* str lr, [sp, #-4]! */
2198 0xe59fe004, /* ldr lr, [pc, #4] */
2199 0xe08fe00e, /* add lr, pc, lr */
2200 0xe5bef008, /* ldr pc, [lr, #8]! */
2201 0x00000000, /* &GOT[0] - . */
2202};
252b5132 2203
1db37fe6
YG		 2204/* By default subsequent entries in a procedure linkage table look like
2205 this. Offsets that don't fit into 28 bits will cause link error. */
2206static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2207{
2208 0xe28fc600, /* add ip, pc, #0xNN00000 */
2209 0xe28cca00, /* add ip, ip, #0xNN000 */
2210 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2211};
5e681ec4 2212
1db37fe6
YG		 2213/* When explicitly asked, we'll use this "long" entry format
2214 which can cope with arbitrary displacements. */
2215static const bfd_vma elf32_arm_plt_entry_long [] =
2216{
2217 0xe28fc200, /* add ip, pc, #0xN0000000 */
2218 0xe28cc600, /* add ip, ip, #0xNN00000 */
2219 0xe28cca00, /* add ip, ip, #0xNN000 */
2220 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2221};
2222
2223static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2224
eed94f8f
NC		 2225#endif /* not FOUR_WORD_PLT */
2226
2227/* The first entry in a procedure linkage table looks like this.
2228 It is set up so that any shared library function that is called before the
2229 relocation has been set up calls the dynamic linker first. */
2230static const bfd_vma elf32_thumb2_plt0_entry [] =
2231{
2232 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2233 an instruction maybe encoded to one or two array elements. */
2234 0xf8dfb500, /* push {lr} */
2235 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2236 /* add lr, pc */
eed94f8f
NC		 2237 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2238 0x00000000, /* &GOT[0] - . */
2239};
2240
2241/* Subsequent entries in a procedure linkage table for thumb only target
2242 look like this. */
2243static const bfd_vma elf32_thumb2_plt_entry [] =
2244{
2245 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2246 an instruction maybe encoded to one or two array elements. */
2247 0x0c00f240, /* movw ip, #0xNNNN */
2248 0x0c00f2c0, /* movt ip, #0xNNNN */
2249 0xf8dc44fc, /* add ip, pc */
2250 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2251 /* nop */
eed94f8f 2252};
252b5132 2253
00a97672
RS		 2254/* The format of the first entry in the procedure linkage table
2255 for a VxWorks executable. */
2256static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2257{
2258 0xe52dc008, /* str ip,[sp,#-8]! */
2259 0xe59fc000, /* ldr ip,[pc] */
2260 0xe59cf008, /* ldr pc,[ip,#8] */
2261 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2262};
00a97672
RS		 2263
2264/* The format of subsequent entries in a VxWorks executable. */
2265static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2266{
2267 0xe59fc000, /* ldr ip,[pc] */
2268 0xe59cf000, /* ldr pc,[ip] */
2269 0x00000000, /* .long @got */
2270 0xe59fc000, /* ldr ip,[pc] */
2271 0xea000000, /* b _PLT */
2272 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2273};
00a97672
RS		 2274
2275/* The format of entries in a VxWorks shared library. */
2276static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2277{
2278 0xe59fc000, /* ldr ip,[pc] */
2279 0xe79cf009, /* ldr pc,[ip,r9] */
2280 0x00000000, /* .long @got */
2281 0xe59fc000, /* ldr ip,[pc] */
2282 0xe599f008, /* ldr pc,[r9,#8] */
2283 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2284};
00a97672 2285
b7693d02
DJ		 2286/* An initial stub used if the PLT entry is referenced from Thumb code. */
2287#define PLT_THUMB_STUB_SIZE 4
2288static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2289{
2290 0x4778, /* bx pc */
2291 0x46c0 /* nop */
2292};
b7693d02 2293
e5a52504
MM		 2294/* The entries in a PLT when using a DLL-based target with multiple
2295 address spaces. */
906e58ca 2296static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2297{
2298 0xe51ff004, /* ldr pc, [pc, #-4] */
2299 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2300};
2301
2302/* The first entry in a procedure linkage table looks like
2303 this. It is set up so that any shared library function that is
2304 called before the relocation has been set up calls the dynamic
2305 linker first. */
2306static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2307{
2308 /* First bundle: */
2309 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2310 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2311 0xe08cc00f, /* add ip, ip, pc */
2312 0xe52dc008, /* str ip, [sp, #-8]! */
2313 /* Second bundle: */
edccdf7c
RM		 2314 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2315 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2316 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2317 0xe12fff1c, /* bx ip */
b38cadfb 2318 /* Third bundle: */
edccdf7c
RM		 2319 0xe320f000, /* nop */
2320 0xe320f000, /* nop */
2321 0xe320f000, /* nop */
b38cadfb
NC		 2322 /* .Lplt_tail: */
2323 0xe50dc004, /* str ip, [sp, #-4] */
2324 /* Fourth bundle: */
edccdf7c
RM		 2325 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2326 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2327 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2328 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2329};
2330#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2331
2332/* Subsequent entries in a procedure linkage table look like this. */
2333static const bfd_vma elf32_arm_nacl_plt_entry [] =
2334{
2335 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2336 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2337 0xe08cc00f, /* add ip, ip, pc */
2338 0xea000000, /* b .Lplt_tail */
2339};
e5a52504 2340
906e58ca
NC		 2341#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2342#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2343#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2344#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2345#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2346#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2347#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2348#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2349
461a49ca 2350enum stub_insn_type
b38cadfb
NC		 2351{
2352 THUMB16_TYPE = 1,
2353 THUMB32_TYPE,
2354 ARM_TYPE,
2355 DATA_TYPE
2356};
461a49ca 2357
48229727
JB		 2358#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2359/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2360 is inserted in arm_build_one_stub(). */
2361#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2362#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2363#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2364#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2365#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2366#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2367
2368typedef struct
2369{
b38cadfb
NC		 2370 bfd_vma data;
2371 enum stub_insn_type type;
2372 unsigned int r_type;
2373 int reloc_addend;
461a49ca
DJ		 2374} insn_sequence;
2375
fea2b4d6
CL		 2376/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2377 to reach the stub if necessary. */
461a49ca 2378static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2379{
2380 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2381 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2382};
906e58ca 2383
fea2b4d6
CL		 2384/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2385 available. */
461a49ca 2386static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2387{
2388 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2389 ARM_INSN (0xe12fff1c), /* bx ip */
2390 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2391};
906e58ca 2392
d3626fb0 2393/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2394static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2395{
2396 THUMB16_INSN (0xb401), /* push {r0} */
2397 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2398 THUMB16_INSN (0x4684), /* mov ip, r0 */
2399 THUMB16_INSN (0xbc01), /* pop {r0} */
2400 THUMB16_INSN (0x4760), /* bx ip */
2401 THUMB16_INSN (0xbf00), /* nop */
2402 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2403};
906e58ca 2404
d3626fb0
CL		 2405/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2406 allowed. */
2407static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2408{
2409 THUMB16_INSN (0x4778), /* bx pc */
2410 THUMB16_INSN (0x46c0), /* nop */
2411 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2412 ARM_INSN (0xe12fff1c), /* bx ip */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2414};
d3626fb0 2415
fea2b4d6
CL		 2416/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2417 available. */
461a49ca 2418static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2419{
2420 THUMB16_INSN (0x4778), /* bx pc */
2421 THUMB16_INSN (0x46c0), /* nop */
2422 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2423 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2424};
906e58ca 2425
fea2b4d6
CL		 2426/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2427 one, when the destination is close enough. */
461a49ca 2428static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2429{
2430 THUMB16_INSN (0x4778), /* bx pc */
2431 THUMB16_INSN (0x46c0), /* nop */
2432 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2433};
c820be07 2434
cf3eccff 2435/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2436 blx to reach the stub if necessary. */
cf3eccff 2437static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2438{
2439 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2440 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2441 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2442};
906e58ca 2443
cf3eccff
DJ		 2444/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2445 blx to reach the stub if necessary. We can not add into pc;
2446 it is not guaranteed to mode switch (different in ARMv6 and
2447 ARMv7). */
2448static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2449{
2450 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2451 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2452 ARM_INSN (0xe12fff1c), /* bx ip */
2453 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2454};
cf3eccff 2455
ebe24dd4
CL		 2456/* V4T ARM -> ARM long branch stub, PIC. */
2457static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2460 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2461 ARM_INSN (0xe12fff1c), /* bx ip */
2462 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2463};
ebe24dd4
CL		 2464
2465/* V4T Thumb -> ARM long branch stub, PIC. */
2466static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2467{
2468 THUMB16_INSN (0x4778), /* bx pc */
2469 THUMB16_INSN (0x46c0), /* nop */
2470 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2471 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2472 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2473};
ebe24dd4 2474
d3626fb0
CL		 2475/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2476 architectures. */
ebe24dd4 2477static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2478{
2479 THUMB16_INSN (0xb401), /* push {r0} */
2480 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2481 THUMB16_INSN (0x46fc), /* mov ip, pc */
2482 THUMB16_INSN (0x4484), /* add ip, r0 */
2483 THUMB16_INSN (0xbc01), /* pop {r0} */
2484 THUMB16_INSN (0x4760), /* bx ip */
2485 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2486};
ebe24dd4 2487
d3626fb0
CL		 2488/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2489 allowed. */
2490static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2491{
2492 THUMB16_INSN (0x4778), /* bx pc */
2493 THUMB16_INSN (0x46c0), /* nop */
2494 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2495 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2496 ARM_INSN (0xe12fff1c), /* bx ip */
2497 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2498};
d3626fb0 2499
0855e32b
NS		 2500/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2501 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2502static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2503{
b38cadfb
NC		 2504 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2505 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2506 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2507};
2508
2509/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2510 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2511static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2512{
b38cadfb
NC		 2513 THUMB16_INSN (0x4778), /* bx pc */
2514 THUMB16_INSN (0x46c0), /* nop */
2515 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2516 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2517 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2518};
2519
7a89b94e
NC		 2520/* NaCl ARM -> ARM long branch stub. */
2521static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2522{
2523 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2524 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2525 ARM_INSN (0xe12fff1c), /* bx ip */
2526 ARM_INSN (0xe320f000), /* nop */
2527 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2528 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2529 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2530 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2531};
2532
2533/* NaCl ARM -> ARM long branch stub, PIC. */
2534static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2535{
2536 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2537 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2538 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2539 ARM_INSN (0xe12fff1c), /* bx ip */
2540 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2541 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2542 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2543 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2544};
2545
2546
48229727
JB		 2547/* Cortex-A8 erratum-workaround stubs. */
2548
2549/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2550 can't use a conditional branch to reach this stub). */
2551
2552static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2553{
2554 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2555 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2556 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2557};
48229727
JB		 2558
2559/* Stub used for b.w and bl.w instructions. */
2560
2561static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2562{
2563 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2564};
48229727
JB		 2565
2566static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2567{
2568 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2569};
48229727
JB		 2570
2571/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2572 instruction (which switches to ARM mode) to point to this stub. Jump to the
2573 real destination using an ARM-mode branch. */
2574
2575static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2576{
2577 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2578};
48229727 2579
9553db3c
NC		 2580/* For each section group there can be a specially created linker section
2581 to hold the stubs for that group. The name of the stub section is based
2582 upon the name of another section within that group with the suffix below
2583 applied.
2584
2585 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2586 create what appeared to be a linker stub section when it actually
2587 contained user code/data. For example, consider this fragment:
b38cadfb 2588
9553db3c
NC		 2589 const char * stubborn_problems[] = { "np" };
2590
2591 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2592 section called:
2593
2594 .data.rel.local.stubborn_problems
2595
2596 This then causes problems in arm32_arm_build_stubs() as it triggers:
2597
2598 // Ignore non-stub sections.
2599 if (!strstr (stub_sec->name, STUB_SUFFIX))
2600 continue;
2601
2602 And so the section would be ignored instead of being processed. Hence
2603 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2604 C identifier. */
2605#define STUB_SUFFIX ".__stub"
906e58ca 2606
738a79f6
CL		 2607/* One entry per long/short branch stub defined above. */
2608#define DEF_STUBS \
2609 DEF_STUB(long_branch_any_any) \
2610 DEF_STUB(long_branch_v4t_arm_thumb) \
2611 DEF_STUB(long_branch_thumb_only) \
2612 DEF_STUB(long_branch_v4t_thumb_thumb) \
2613 DEF_STUB(long_branch_v4t_thumb_arm) \
2614 DEF_STUB(short_branch_v4t_thumb_arm) \
2615 DEF_STUB(long_branch_any_arm_pic) \
2616 DEF_STUB(long_branch_any_thumb_pic) \
2617 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2618 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2619 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2620 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2621 DEF_STUB(long_branch_any_tls_pic) \
2622 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2623 DEF_STUB(long_branch_arm_nacl) \
2624 DEF_STUB(long_branch_arm_nacl_pic) \
48229727
JB		 2625 DEF_STUB(a8_veneer_b_cond) \
2626 DEF_STUB(a8_veneer_b) \
2627 DEF_STUB(a8_veneer_bl) \
2628 DEF_STUB(a8_veneer_blx)
738a79f6
CL		 2629
2630#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2631enum elf32_arm_stub_type
2632{
906e58ca 2633 arm_stub_none,
738a79f6 2634 DEF_STUBS
6a631e86 2635 /* Note the first a8_veneer type. */
eb7c4339 2636 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
738a79f6
CL		 2637};
2638#undef DEF_STUB
2639
2640typedef struct
2641{
d3ce72d0 2642 const insn_sequence* template_sequence;
738a79f6
CL		 2643 int template_size;
2644} stub_def;
2645
2646#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2647static const stub_def stub_definitions[] =
2648{
738a79f6
CL		 2649 {NULL, 0},
2650 DEF_STUBS
906e58ca
NC		 2651};
2652
2653struct elf32_arm_stub_hash_entry
2654{
2655 /* Base hash table entry structure. */
2656 struct bfd_hash_entry root;
2657
2658 /* The stub section. */
2659 asection *stub_sec;
2660
2661 /* Offset within stub_sec of the beginning of this stub. */
2662 bfd_vma stub_offset;
2663
2664 /* Given the symbol's value and its section we can determine its final
2665 value when building the stubs (so the stub knows where to jump). */
2666 bfd_vma target_value;
2667 asection *target_section;
2668
48229727
JB		 2669 /* Offset to apply to relocation referencing target_value. */
2670 bfd_vma target_addend;
2671
2672 /* The instruction which caused this stub to be generated (only valid for
2673 Cortex-A8 erratum workaround stubs at present). */
2674 unsigned long orig_insn;
2675
461a49ca 2676 /* The stub type. */
906e58ca 2677 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2678 /* Its encoding size in bytes. */
2679 int stub_size;
2680 /* Its template. */
2681 const insn_sequence *stub_template;
2682 /* The size of the template (number of entries). */
2683 int stub_template_size;
906e58ca
NC		 2684
2685 /* The symbol table entry, if any, that this was derived from. */
2686 struct elf32_arm_link_hash_entry *h;
2687
35fc36a8
RS		 2688 /* Type of branch. */
2689 enum arm_st_branch_type branch_type;
906e58ca
NC		 2690
2691 /* Where this stub is being called from, or, in the case of combined
2692 stub sections, the first input section in the group. */
2693 asection *id_sec;
7413f23f
DJ		 2694
2695 /* The name for the local symbol at the start of this stub. The
2696 stub name in the hash table has to be unique; this does not, so
2697 it can be friendlier. */
2698 char *output_name;
906e58ca
NC		 2699};
2700
e489d0ae
PB		 2701/* Used to build a map of a section. This is required for mixed-endian
2702 code/data. */
2703
2704typedef struct elf32_elf_section_map
2705{
2706 bfd_vma vma;
2707 char type;
2708}
2709elf32_arm_section_map;
2710
c7b8f16e
JB		 2711/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2712
2713typedef enum
2714{
2715 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2716 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2717 VFP11_ERRATUM_ARM_VENEER,
2718 VFP11_ERRATUM_THUMB_VENEER
2719}
2720elf32_vfp11_erratum_type;
2721
2722typedef struct elf32_vfp11_erratum_list
2723{
2724 struct elf32_vfp11_erratum_list *next;
2725 bfd_vma vma;
2726 union
2727 {
2728 struct
2729 {
2730 struct elf32_vfp11_erratum_list *veneer;
2731 unsigned int vfp_insn;
2732 } b;
2733 struct
2734 {
2735 struct elf32_vfp11_erratum_list *branch;
2736 unsigned int id;
2737 } v;
2738 } u;
2739 elf32_vfp11_erratum_type type;
2740}
2741elf32_vfp11_erratum_list;
2742
a504d23a
LA		 2743/* Information about a STM32L4XX erratum veneer, or a branch to such a
2744 veneer. */
2745typedef enum
2746{
2747 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2748 STM32L4XX_ERRATUM_VENEER
2749}
2750elf32_stm32l4xx_erratum_type;
2751
2752typedef struct elf32_stm32l4xx_erratum_list
2753{
2754 struct elf32_stm32l4xx_erratum_list *next;
2755 bfd_vma vma;
2756 union
2757 {
2758 struct
2759 {
2760 struct elf32_stm32l4xx_erratum_list *veneer;
2761 unsigned int insn;
2762 } b;
2763 struct
2764 {
2765 struct elf32_stm32l4xx_erratum_list *branch;
2766 unsigned int id;
2767 } v;
2768 } u;
2769 elf32_stm32l4xx_erratum_type type;
2770}
2771elf32_stm32l4xx_erratum_list;
2772
2468f9c9
PB		 2773typedef enum
2774{
2775 DELETE_EXIDX_ENTRY,
2776 INSERT_EXIDX_CANTUNWIND_AT_END
2777}
2778arm_unwind_edit_type;
2779
2780/* A (sorted) list of edits to apply to an unwind table. */
2781typedef struct arm_unwind_table_edit
2782{
2783 arm_unwind_edit_type type;
2784 /* Note: we sometimes want to insert an unwind entry corresponding to a
2785 section different from the one we're currently writing out, so record the
2786 (text) section this edit relates to here. */
2787 asection *linked_section;
2788 unsigned int index;
2789 struct arm_unwind_table_edit *next;
2790}
2791arm_unwind_table_edit;
2792
8e3de13a 2793typedef struct _arm_elf_section_data
e489d0ae 2794{
2468f9c9 2795 /* Information about mapping symbols. */
e489d0ae 2796 struct bfd_elf_section_data elf;
8e3de13a 2797 unsigned int mapcount;
c7b8f16e 2798 unsigned int mapsize;
e489d0ae 2799 elf32_arm_section_map *map;
2468f9c9 2800 /* Information about CPU errata. */
c7b8f16e
JB		 2801 unsigned int erratumcount;
2802 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2803 unsigned int stm32l4xx_erratumcount;
2804 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2805 unsigned int additional_reloc_count;
2468f9c9
PB		 2806 /* Information about unwind tables. */
2807 union
2808 {
2809 /* Unwind info attached to a text section. */
2810 struct
2811 {
2812 asection *arm_exidx_sec;
2813 } text;
2814
2815 /* Unwind info attached to an .ARM.exidx section. */
2816 struct
2817 {
2818 arm_unwind_table_edit *unwind_edit_list;
2819 arm_unwind_table_edit *unwind_edit_tail;
2820 } exidx;
2821 } u;
8e3de13a
NC		 2822}
2823_arm_elf_section_data;
e489d0ae
PB		 2824
2825#define elf32_arm_section_data(sec) \
8e3de13a 2826 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2827
48229727
JB		 2828/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2829 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2830 so may be created multiple times: we use an array of these entries whilst
2831 relaxing which we can refresh easily, then create stubs for each potentially
2832 erratum-triggering instruction once we've settled on a solution. */
2833
b38cadfb
NC		 2834struct a8_erratum_fix
2835{
48229727
JB		 2836 bfd *input_bfd;
2837 asection *section;
2838 bfd_vma offset;
2839 bfd_vma addend;
2840 unsigned long orig_insn;
2841 char *stub_name;
2842 enum elf32_arm_stub_type stub_type;
35fc36a8 2843 enum arm_st_branch_type branch_type;
48229727
JB		 2844};
2845
2846/* A table of relocs applied to branches which might trigger Cortex-A8
2847 erratum. */
2848
b38cadfb
NC		 2849struct a8_erratum_reloc
2850{
48229727
JB		 2851 bfd_vma from;
2852 bfd_vma destination;
92750f34
DJ		 2853 struct elf32_arm_link_hash_entry *hash;
2854 const char *sym_name;
48229727 2855 unsigned int r_type;
35fc36a8 2856 enum arm_st_branch_type branch_type;
48229727
JB		 2857 bfd_boolean non_a8_stub;
2858};
2859
ba93b8ac
DJ		 2860/* The size of the thread control block. */
2861#define TCB_SIZE 8
2862
34e77a92
RS		 2863/* ARM-specific information about a PLT entry, over and above the usual
2864 gotplt_union. */
b38cadfb
NC		 2865struct arm_plt_info
2866{
34e77a92
RS		 2867 /* We reference count Thumb references to a PLT entry separately,
2868 so that we can emit the Thumb trampoline only if needed. */
2869 bfd_signed_vma thumb_refcount;
2870
2871 /* Some references from Thumb code may be eliminated by BL->BLX
2872 conversion, so record them separately. */
2873 bfd_signed_vma maybe_thumb_refcount;
2874
2875 /* How many of the recorded PLT accesses were from non-call relocations.
2876 This information is useful when deciding whether anything takes the
2877 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2878 non-call references to the function should resolve directly to the
2879 real runtime target. */
2880 unsigned int noncall_refcount;
2881
2882 /* Since PLT entries have variable size if the Thumb prologue is
2883 used, we need to record the index into .got.plt instead of
2884 recomputing it from the PLT offset. */
2885 bfd_signed_vma got_offset;
2886};
2887
2888/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2889struct arm_local_iplt_info
2890{
34e77a92
RS		 2891 /* The information that is usually found in the generic ELF part of
2892 the hash table entry. */
2893 union gotplt_union root;
2894
2895 /* The information that is usually found in the ARM-specific part of
2896 the hash table entry. */
2897 struct arm_plt_info arm;
2898
2899 /* A list of all potential dynamic relocations against this symbol. */
2900 struct elf_dyn_relocs *dyn_relocs;
2901};
2902
0ffa91dd 2903struct elf_arm_obj_tdata
ba93b8ac
DJ		 2904{
2905 struct elf_obj_tdata root;
2906
2907 /* tls_type for each local got entry. */
2908 char *local_got_tls_type;
ee065d83 2909
0855e32b
NS		 2910 /* GOTPLT entries for TLS descriptors. */
2911 bfd_vma *local_tlsdesc_gotent;
2912
34e77a92
RS		 2913 /* Information for local symbols that need entries in .iplt. */
2914 struct arm_local_iplt_info **local_iplt;
2915
bf21ed78
MS		 2916 /* Zero to warn when linking objects with incompatible enum sizes. */
2917 int no_enum_size_warning;
a9dc9481
JM		 2918
2919 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2920 int no_wchar_size_warning;
ba93b8ac
DJ		 2921};
2922
0ffa91dd
NC		 2923#define elf_arm_tdata(bfd) \
2924 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2925
0ffa91dd
NC		 2926#define elf32_arm_local_got_tls_type(bfd) \
2927 (elf_arm_tdata (bfd)->local_got_tls_type)
2928
0855e32b
NS		 2929#define elf32_arm_local_tlsdesc_gotent(bfd) \
2930 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2931
34e77a92
RS		 2932#define elf32_arm_local_iplt(bfd) \
2933 (elf_arm_tdata (bfd)->local_iplt)
2934
0ffa91dd
NC		 2935#define is_arm_elf(bfd) \
2936 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2937 && elf_tdata (bfd) != NULL \
4dfe6ac6 2938 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2939
2940static bfd_boolean
2941elf32_arm_mkobject (bfd *abfd)
2942{
0ffa91dd 2943 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2944 ARM_ELF_DATA);
ba93b8ac
DJ		 2945}
2946
ba93b8ac
DJ		 2947#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2948
ba96a88f 2949/* Arm ELF linker hash entry. */
252b5132 2950struct elf32_arm_link_hash_entry
b38cadfb
NC		 2951{
2952 struct elf_link_hash_entry root;
252b5132 2953
b38cadfb
NC		 2954 /* Track dynamic relocs copied for this symbol. */
2955 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2956
b38cadfb
NC		 2957 /* ARM-specific PLT information. */
2958 struct arm_plt_info plt;
ba93b8ac
DJ		 2959
2960#define GOT_UNKNOWN 0
2961#define GOT_NORMAL 1
2962#define GOT_TLS_GD 2
2963#define GOT_TLS_IE 4
0855e32b
NS		 2964#define GOT_TLS_GDESC 8
2965#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 2966 unsigned int tls_type : 8;
34e77a92 2967
b38cadfb
NC		 2968 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2969 unsigned int is_iplt : 1;
34e77a92 2970
b38cadfb 2971 unsigned int unused : 23;
a4fd1a8e 2972
b38cadfb
NC		 2973 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2974 starting at the end of the jump table. */
2975 bfd_vma tlsdesc_got;
0855e32b 2976
b38cadfb
NC		 2977 /* The symbol marking the real symbol location for exported thumb
2978 symbols with Arm stubs. */
2979 struct elf_link_hash_entry *export_glue;
906e58ca 2980
b38cadfb 2981 /* A pointer to the most recently used stub hash entry against this
8029a119 2982 symbol. */
b38cadfb
NC		 2983 struct elf32_arm_stub_hash_entry *stub_cache;
2984};
252b5132 2985
252b5132 2986/* Traverse an arm ELF linker hash table. */
252b5132
RH		 2987#define elf32_arm_link_hash_traverse(table, func, info) \
2988 (elf_link_hash_traverse \
2989 (&(table)->root, \
b7693d02 2990 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 2991 (info)))
2992
2993/* Get the ARM elf linker hash table from a link_info structure. */
2994#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 2995 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2996 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 2997
906e58ca
NC		 2998#define arm_stub_hash_lookup(table, string, create, copy) \
2999 ((struct elf32_arm_stub_hash_entry *) \
3000 bfd_hash_lookup ((table), (string), (create), (copy)))
3001
21d799b5
NC		 3002/* Array to keep track of which stub sections have been created, and
3003 information on stub grouping. */
3004struct map_stub
3005{
3006 /* This is the section to which stubs in the group will be
3007 attached. */
3008 asection *link_sec;
3009 /* The stub section. */
3010 asection *stub_sec;
3011};
3012
0855e32b
NS		 3013#define elf32_arm_compute_jump_table_size(htab) \
3014 ((htab)->next_tls_desc_index * 4)
3015
9b485d32 3016/* ARM ELF linker hash table. */
252b5132 3017struct elf32_arm_link_hash_table
906e58ca
NC		 3018{
3019 /* The main hash table. */
3020 struct elf_link_hash_table root;
252b5132 3021
906e58ca
NC		 3022 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3023 bfd_size_type thumb_glue_size;
252b5132 3024
906e58ca
NC		 3025 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3026 bfd_size_type arm_glue_size;
252b5132 3027
906e58ca
NC		 3028 /* The size in bytes of section containing the ARMv4 BX veneers. */
3029 bfd_size_type bx_glue_size;
845b51d6 3030
906e58ca
NC		 3031 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3032 veneer has been populated. */
3033 bfd_vma bx_glue_offset[15];
845b51d6 3034
906e58ca
NC		 3035 /* The size in bytes of the section containing glue for VFP11 erratum
3036 veneers. */
3037 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3038
a504d23a
LA		 3039 /* The size in bytes of the section containing glue for STM32L4XX erratum
3040 veneers. */
3041 bfd_size_type stm32l4xx_erratum_glue_size;
3042
48229727
JB		 3043 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3044 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3045 elf32_arm_write_section(). */
3046 struct a8_erratum_fix *a8_erratum_fixes;
3047 unsigned int num_a8_erratum_fixes;
3048
906e58ca
NC		 3049 /* An arbitrary input BFD chosen to hold the glue sections. */
3050 bfd * bfd_of_glue_owner;
ba96a88f 3051
906e58ca
NC		 3052 /* Nonzero to output a BE8 image. */
3053 int byteswap_code;
e489d0ae 3054
906e58ca
NC		 3055 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3056 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3057 int target1_is_rel;
9c504268 3058
906e58ca
NC		 3059 /* The relocation to use for R_ARM_TARGET2 relocations. */
3060 int target2_reloc;
eb043451 3061
906e58ca
NC		 3062 /* 0 = Ignore R_ARM_V4BX.
3063 1 = Convert BX to MOV PC.
3064 2 = Generate v4 interworing stubs. */
3065 int fix_v4bx;
319850b4 3066
48229727
JB		 3067 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3068 int fix_cortex_a8;
3069
2de70689
MGD		 3070 /* Whether we should fix the ARM1176 BLX immediate issue. */
3071 int fix_arm1176;
3072
906e58ca
NC		 3073 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3074 int use_blx;
33bfe774 3075
906e58ca
NC		 3076 /* What sort of code sequences we should look for which may trigger the
3077 VFP11 denorm erratum. */
3078 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3079
906e58ca
NC		 3080 /* Global counter for the number of fixes we have emitted. */
3081 int num_vfp11_fixes;
c7b8f16e 3082
a504d23a
LA		 3083 /* What sort of code sequences we should look for which may trigger the
3084 STM32L4XX erratum. */
3085 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3086
3087 /* Global counter for the number of fixes we have emitted. */
3088 int num_stm32l4xx_fixes;
3089
906e58ca
NC		 3090 /* Nonzero to force PIC branch veneers. */
3091 int pic_veneer;
27e55c4d 3092
906e58ca
NC		 3093 /* The number of bytes in the initial entry in the PLT. */
3094 bfd_size_type plt_header_size;
e5a52504 3095
906e58ca
NC		 3096 /* The number of bytes in the subsequent PLT etries. */
3097 bfd_size_type plt_entry_size;
e5a52504 3098
906e58ca
NC		 3099 /* True if the target system is VxWorks. */
3100 int vxworks_p;
00a97672 3101
906e58ca
NC		 3102 /* True if the target system is Symbian OS. */
3103 int symbian_p;
e5a52504 3104
b38cadfb
NC		 3105 /* True if the target system is Native Client. */
3106 int nacl_p;
3107
906e58ca
NC		 3108 /* True if the target uses REL relocations. */
3109 int use_rel;
4e7fd91e 3110
0855e32b
NS		 3111 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3112 bfd_vma next_tls_desc_index;
3113
3114 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3115 bfd_vma num_tls_desc;
3116
906e58ca 3117 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3118 asection *sdynbss;
3119 asection *srelbss;
5e681ec4 3120
906e58ca
NC		 3121 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3122 asection *srelplt2;
00a97672 3123
0855e32b
NS		 3124 /* The offset into splt of the PLT entry for the TLS descriptor
3125 resolver. Special values are 0, if not necessary (or not found
3126 to be necessary yet), and -1 if needed but not determined
3127 yet. */
3128 bfd_vma dt_tlsdesc_plt;
3129
3130 /* The offset into sgot of the GOT entry used by the PLT entry
3131 above. */
b38cadfb 3132 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3133
3134 /* Offset in .plt section of tls_arm_trampoline. */
3135 bfd_vma tls_trampoline;
3136
906e58ca
NC		 3137 /* Data for R_ARM_TLS_LDM32 relocations. */
3138 union
3139 {
3140 bfd_signed_vma refcount;
3141 bfd_vma offset;
3142 } tls_ldm_got;
b7693d02 3143
87d72d41
AM		 3144 /* Small local sym cache. */
3145 struct sym_cache sym_cache;
906e58ca
NC		 3146
3147 /* For convenience in allocate_dynrelocs. */
3148 bfd * obfd;
3149
0855e32b
NS		 3150 /* The amount of space used by the reserved portion of the sgotplt
3151 section, plus whatever space is used by the jump slots. */
3152 bfd_vma sgotplt_jump_table_size;
3153
906e58ca
NC		 3154 /* The stub hash table. */
3155 struct bfd_hash_table stub_hash_table;
3156
3157 /* Linker stub bfd. */
3158 bfd *stub_bfd;
3159
3160 /* Linker call-backs. */
7a89b94e 3161 asection * (*add_stub_section) (const char *, asection *, unsigned int);
906e58ca
NC		 3162 void (*layout_sections_again) (void);
3163
3164 /* Array to keep track of which stub sections have been created, and
3165 information on stub grouping. */
21d799b5 3166 struct map_stub *stub_group;
906e58ca 3167
fe33d2fa 3168 /* Number of elements in stub_group. */
7292b3ac 3169 unsigned int top_id;
fe33d2fa 3170
906e58ca
NC		 3171 /* Assorted information used by elf32_arm_size_stubs. */
3172 unsigned int bfd_count;
7292b3ac 3173 unsigned int top_index;
906e58ca
NC		 3174 asection **input_list;
3175};
252b5132 3176
a504d23a
LA		 3177static inline int
3178ctz (unsigned int mask)
3179{
3180#if GCC_VERSION >= 3004
3181 return __builtin_ctz (mask);
3182#else
3183 unsigned int i;
3184
3185 for (i = 0; i < 8 * sizeof (mask); i++)
3186 {
3187 if (mask & 0x1)
3188 break;
3189 mask = (mask >> 1);
3190 }
3191 return i;
3192#endif
3193}
3194
3195static inline int
3196popcount (unsigned int mask)
3197{
3198#if GCC_VERSION >= 3004
3199 return __builtin_popcount (mask);
3200#else
3201 unsigned int i, sum = 0;
3202
3203 for (i = 0; i < 8 * sizeof (mask); i++)
3204 {
3205 if (mask & 0x1)
3206 sum++;
3207 mask = (mask >> 1);
3208 }
3209 return sum;
3210#endif
3211}
3212
780a67af
NC		 3213/* Create an entry in an ARM ELF linker hash table. */
3214
3215static struct bfd_hash_entry *
57e8b36a 3216elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3217 struct bfd_hash_table * table,
3218 const char * string)
780a67af
NC		 3219{
3220 struct elf32_arm_link_hash_entry * ret =
3221 (struct elf32_arm_link_hash_entry *) entry;
3222
3223 /* Allocate the structure if it has not already been allocated by a
3224 subclass. */
906e58ca 3225 if (ret == NULL)
21d799b5 3226 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3227 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3228 if (ret == NULL)
780a67af
NC		 3229 return (struct bfd_hash_entry *) ret;
3230
3231 /* Call the allocation method of the superclass. */
3232 ret = ((struct elf32_arm_link_hash_entry *)
3233 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3234 table, string));
57e8b36a 3235 if (ret != NULL)
b7693d02 3236 {
0bdcacaf 3237 ret->dyn_relocs = NULL;
ba93b8ac 3238 ret->tls_type = GOT_UNKNOWN;
0855e32b 3239 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3240 ret->plt.thumb_refcount = 0;
3241 ret->plt.maybe_thumb_refcount = 0;
3242 ret->plt.noncall_refcount = 0;
3243 ret->plt.got_offset = -1;
3244 ret->is_iplt = FALSE;
a4fd1a8e 3245 ret->export_glue = NULL;
906e58ca
NC		 3246
3247 ret->stub_cache = NULL;
b7693d02 3248 }
780a67af
NC		 3249
3250 return (struct bfd_hash_entry *) ret;
3251}
3252
34e77a92
RS		 3253/* Ensure that we have allocated bookkeeping structures for ABFD's local
3254 symbols. */
3255
3256static bfd_boolean
3257elf32_arm_allocate_local_sym_info (bfd *abfd)
3258{
3259 if (elf_local_got_refcounts (abfd) == NULL)
3260 {
3261 bfd_size_type num_syms;
3262 bfd_size_type size;
3263 char *data;
3264
3265 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3266 size = num_syms * (sizeof (bfd_signed_vma)
3267 + sizeof (struct arm_local_iplt_info *)
3268 + sizeof (bfd_vma)
3269 + sizeof (char));
3270 data = bfd_zalloc (abfd, size);
3271 if (data == NULL)
3272 return FALSE;
3273
3274 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3275 data += num_syms * sizeof (bfd_signed_vma);
3276
3277 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3278 data += num_syms * sizeof (struct arm_local_iplt_info *);
3279
3280 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3281 data += num_syms * sizeof (bfd_vma);
3282
3283 elf32_arm_local_got_tls_type (abfd) = data;
3284 }
3285 return TRUE;
3286}
3287
3288/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3289 to input bfd ABFD. Create the information if it doesn't already exist.
3290 Return null if an allocation fails. */
3291
3292static struct arm_local_iplt_info *
3293elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3294{
3295 struct arm_local_iplt_info **ptr;
3296
3297 if (!elf32_arm_allocate_local_sym_info (abfd))
3298 return NULL;
3299
3300 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3301 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3302 if (*ptr == NULL)
3303 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3304 return *ptr;
3305}
3306
3307/* Try to obtain PLT information for the symbol with index R_SYMNDX
3308 in ABFD's symbol table. If the symbol is global, H points to its
3309 hash table entry, otherwise H is null.
3310
3311 Return true if the symbol does have PLT information. When returning
3312 true, point *ROOT_PLT at the target-independent reference count/offset
3313 union and *ARM_PLT at the ARM-specific information. */
3314
3315static bfd_boolean
3316elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_entry *h,
3317 unsigned long r_symndx, union gotplt_union **root_plt,
3318 struct arm_plt_info **arm_plt)
3319{
3320 struct arm_local_iplt_info *local_iplt;
3321
3322 if (h != NULL)
3323 {
3324 *root_plt = &h->root.plt;
3325 *arm_plt = &h->plt;
3326 return TRUE;
3327 }
3328
3329 if (elf32_arm_local_iplt (abfd) == NULL)
3330 return FALSE;
3331
3332 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3333 if (local_iplt == NULL)
3334 return FALSE;
3335
3336 *root_plt = &local_iplt->root;
3337 *arm_plt = &local_iplt->arm;
3338 return TRUE;
3339}
3340
3341/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3342 before it. */
3343
3344static bfd_boolean
3345elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3346 struct arm_plt_info *arm_plt)
3347{
3348 struct elf32_arm_link_hash_table *htab;
3349
3350 htab = elf32_arm_hash_table (info);
3351 return (arm_plt->thumb_refcount != 0
3352 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3353}
3354
3355/* Return a pointer to the head of the dynamic reloc list that should
3356 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3357 ABFD's symbol table. Return null if an error occurs. */
3358
3359static struct elf_dyn_relocs **
3360elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3361 Elf_Internal_Sym *isym)
3362{
3363 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3364 {
3365 struct arm_local_iplt_info *local_iplt;
3366
3367 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3368 if (local_iplt == NULL)
3369 return NULL;
3370 return &local_iplt->dyn_relocs;
3371 }
3372 else
3373 {
3374 /* Track dynamic relocs needed for local syms too.
3375 We really need local syms available to do this
3376 easily. Oh well. */
3377 asection *s;
3378 void *vpp;
3379
3380 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3381 if (s == NULL)
3382 abort ();
3383
3384 vpp = &elf_section_data (s)->local_dynrel;
3385 return (struct elf_dyn_relocs **) vpp;
3386 }
3387}
3388
906e58ca
NC		 3389/* Initialize an entry in the stub hash table. */
3390
3391static struct bfd_hash_entry *
3392stub_hash_newfunc (struct bfd_hash_entry *entry,
3393 struct bfd_hash_table *table,
3394 const char *string)
3395{
3396 /* Allocate the structure if it has not already been allocated by a
3397 subclass. */
3398 if (entry == NULL)
3399 {
21d799b5 3400 entry = (struct bfd_hash_entry *)
99059e56 3401 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3402 if (entry == NULL)
3403 return entry;
3404 }
3405
3406 /* Call the allocation method of the superclass. */
3407 entry = bfd_hash_newfunc (entry, table, string);
3408 if (entry != NULL)
3409 {
3410 struct elf32_arm_stub_hash_entry *eh;
3411
3412 /* Initialize the local fields. */
3413 eh = (struct elf32_arm_stub_hash_entry *) entry;
3414 eh->stub_sec = NULL;
3415 eh->stub_offset = 0;
3416 eh->target_value = 0;
3417 eh->target_section = NULL;
cedfb179
DK		 3418 eh->target_addend = 0;
3419 eh->orig_insn = 0;
906e58ca 3420 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3421 eh->stub_size = 0;
3422 eh->stub_template = NULL;
3423 eh->stub_template_size = 0;
906e58ca
NC		 3424 eh->h = NULL;
3425 eh->id_sec = NULL;
d8d2f433 3426 eh->output_name = NULL;
906e58ca
NC		 3427 }
3428
3429 return entry;
3430}
3431
00a97672 3432/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3433 shortcuts to them in our hash table. */
3434
3435static bfd_boolean
57e8b36a 3436create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3437{
3438 struct elf32_arm_link_hash_table *htab;
3439
e5a52504 3440 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3441 if (htab == NULL)
3442 return FALSE;
3443
e5a52504
MM		 3444 /* BPABI objects never have a GOT, or associated sections. */
3445 if (htab->symbian_p)
3446 return TRUE;
3447
5e681ec4
PB		 3448 if (! _bfd_elf_create_got_section (dynobj, info))
3449 return FALSE;
3450
5e681ec4
PB		 3451 return TRUE;
3452}
3453
34e77a92
RS		 3454/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3455
3456static bfd_boolean
3457create_ifunc_sections (struct bfd_link_info *info)
3458{
3459 struct elf32_arm_link_hash_table *htab;
3460 const struct elf_backend_data *bed;
3461 bfd *dynobj;
3462 asection *s;
3463 flagword flags;
b38cadfb 3464
34e77a92
RS		 3465 htab = elf32_arm_hash_table (info);
3466 dynobj = htab->root.dynobj;
3467 bed = get_elf_backend_data (dynobj);
3468 flags = bed->dynamic_sec_flags;
3469
3470 if (htab->root.iplt == NULL)
3471 {
3d4d4302
AM		 3472 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3473 flags | SEC_READONLY | SEC_CODE);
34e77a92 3474 if (s == NULL
a0f49396 3475 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3476 return FALSE;
3477 htab->root.iplt = s;
3478 }
3479
3480 if (htab->root.irelplt == NULL)
3481 {
3d4d4302
AM		 3482 s = bfd_make_section_anyway_with_flags (dynobj,
3483 RELOC_SECTION (htab, ".iplt"),
3484 flags | SEC_READONLY);
34e77a92 3485 if (s == NULL
a0f49396 3486 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3487 return FALSE;
3488 htab->root.irelplt = s;
3489 }
3490
3491 if (htab->root.igotplt == NULL)
3492 {
3d4d4302 3493 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3494 if (s == NULL
3495 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3496 return FALSE;
3497 htab->root.igotplt = s;
3498 }
3499 return TRUE;
3500}
3501
eed94f8f
NC		 3502/* Determine if we're dealing with a Thumb only architecture. */
3503
3504static bfd_boolean
3505using_thumb_only (struct elf32_arm_link_hash_table *globals)
3506{
2fd158eb
TP		 3507 int arch;
3508 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3509 Tag_CPU_arch_profile);
eed94f8f 3510
2fd158eb
TP		 3511 if (profile)
3512 return profile == 'M';
eed94f8f 3513
2fd158eb 3514 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3515
2fd158eb
TP		 3516 if (arch == TAG_CPU_ARCH_V6_M
3517 || arch == TAG_CPU_ARCH_V6S_M
3518 || arch == TAG_CPU_ARCH_V7E_M
3519 || arch == TAG_CPU_ARCH_V8M_BASE
3520 || arch == TAG_CPU_ARCH_V8M_MAIN)
3521 return TRUE;
eed94f8f 3522
2fd158eb 3523 return FALSE;
eed94f8f
NC		 3524}
3525
3526/* Determine if we're dealing with a Thumb-2 object. */
3527
3528static bfd_boolean
3529using_thumb2 (struct elf32_arm_link_hash_table *globals)
3530{
3531 int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3532 Tag_CPU_arch);
3533 return arch == TAG_CPU_ARCH_V6T2 || arch >= TAG_CPU_ARCH_V7;
3534}
3535
00a97672
RS		 3536/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3537 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3538 hash table. */
3539
3540static bfd_boolean
57e8b36a 3541elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3542{
3543 struct elf32_arm_link_hash_table *htab;
3544
3545 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3546 if (htab == NULL)
3547 return FALSE;
3548
362d30a1 3549 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3550 return FALSE;
3551
3552 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3553 return FALSE;
3554
3d4d4302 3555 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3556 if (!bfd_link_pic (info))
3d4d4302
AM		 3557 htab->srelbss = bfd_get_linker_section (dynobj,
3558 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3559
3560 if (htab->vxworks_p)
3561 {
3562 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3563 return FALSE;
3564
0e1862bb 3565 if (bfd_link_pic (info))
00a97672
RS		 3566 {
3567 htab->plt_header_size = 0;
3568 htab->plt_entry_size
3569 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3570 }
3571 else
3572 {
3573 htab->plt_header_size
3574 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3575 htab->plt_entry_size
3576 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3577 }
aebf9be7
NC		 3578
3579 if (elf_elfheader (dynobj))
3580 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3581 }
eed94f8f
NC		 3582 else
3583 {
3584 /* PR ld/16017
3585 Test for thumb only architectures. Note - we cannot just call
3586 using_thumb_only() as the attributes in the output bfd have not been
3587 initialised at this point, so instead we use the input bfd. */
3588 bfd * saved_obfd = htab->obfd;
3589
3590 htab->obfd = dynobj;
3591 if (using_thumb_only (htab))
3592 {
3593 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3594 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3595 }
3596 htab->obfd = saved_obfd;
3597 }
5e681ec4 3598
362d30a1
RS		 3599 if (!htab->root.splt
3600 || !htab->root.srelplt
e5a52504 3601 || !htab->sdynbss
0e1862bb 3602 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3603 abort ();
3604
3605 return TRUE;
3606}
3607
906e58ca
NC		 3608/* Copy the extra info we tack onto an elf_link_hash_entry. */
3609
3610static void
3611elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3612 struct elf_link_hash_entry *dir,
3613 struct elf_link_hash_entry *ind)
3614{
3615 struct elf32_arm_link_hash_entry *edir, *eind;
3616
3617 edir = (struct elf32_arm_link_hash_entry *) dir;
3618 eind = (struct elf32_arm_link_hash_entry *) ind;
3619
0bdcacaf 3620 if (eind->dyn_relocs != NULL)
906e58ca 3621 {
0bdcacaf 3622 if (edir->dyn_relocs != NULL)
906e58ca 3623 {
0bdcacaf
RS		 3624 struct elf_dyn_relocs **pp;
3625 struct elf_dyn_relocs *p;
906e58ca
NC		 3626
3627 /* Add reloc counts against the indirect sym to the direct sym
3628 list. Merge any entries against the same section. */
0bdcacaf 3629 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3630 {
0bdcacaf 3631 struct elf_dyn_relocs *q;
906e58ca 3632
0bdcacaf
RS		 3633 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3634 if (q->sec == p->sec)
906e58ca
NC		 3635 {
3636 q->pc_count += p->pc_count;
3637 q->count += p->count;
3638 *pp = p->next;
3639 break;
3640 }
3641 if (q == NULL)
3642 pp = &p->next;
3643 }
0bdcacaf 3644 *pp = edir->dyn_relocs;
906e58ca
NC		 3645 }
3646
0bdcacaf
RS		 3647 edir->dyn_relocs = eind->dyn_relocs;
3648 eind->dyn_relocs = NULL;
906e58ca
NC		 3649 }
3650
3651 if (ind->root.type == bfd_link_hash_indirect)
3652 {
3653 /* Copy over PLT info. */
34e77a92
RS		 3654 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3655 eind->plt.thumb_refcount = 0;
3656 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3657 eind->plt.maybe_thumb_refcount = 0;
3658 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3659 eind->plt.noncall_refcount = 0;
3660
3661 /* We should only allocate a function to .iplt once the final
3662 symbol information is known. */
3663 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3664
3665 if (dir->got.refcount <= 0)
3666 {
3667 edir->tls_type = eind->tls_type;
3668 eind->tls_type = GOT_UNKNOWN;
3669 }
3670 }
3671
3672 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3673}
3674
68faa637
AM		 3675/* Destroy an ARM elf linker hash table. */
3676
3677static void
d495ab0d 3678elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3679{
3680 struct elf32_arm_link_hash_table *ret
d495ab0d 3681 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3682
3683 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3684 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3685}
3686
906e58ca
NC		 3687/* Create an ARM elf linker hash table. */
3688
3689static struct bfd_link_hash_table *
3690elf32_arm_link_hash_table_create (bfd *abfd)
3691{
3692 struct elf32_arm_link_hash_table *ret;
3693 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3694
7bf52ea2 3695 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3696 if (ret == NULL)
3697 return NULL;
3698
3699 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3700 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3701 sizeof (struct elf32_arm_link_hash_entry),
3702 ARM_ELF_DATA))
906e58ca
NC		 3703 {
3704 free (ret);
3705 return NULL;
3706 }
3707
906e58ca 3708 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3709 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3710#ifdef FOUR_WORD_PLT
3711 ret->plt_header_size = 16;
3712 ret->plt_entry_size = 16;
3713#else
3714 ret->plt_header_size = 20;
1db37fe6 3715 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3716#endif
906e58ca 3717 ret->use_rel = 1;
906e58ca 3718 ret->obfd = abfd;
906e58ca
NC		 3719
3720 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3721 sizeof (struct elf32_arm_stub_hash_entry)))
3722 {
d495ab0d 3723 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3724 return NULL;
3725 }
d495ab0d 3726 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3727
3728 return &ret->root.root;
3729}
3730
cd1dac3d
DG		 3731/* Determine what kind of NOPs are available. */
3732
3733static bfd_boolean
3734arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3735{
3736 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3737 Tag_CPU_arch);
3738 return arch == TAG_CPU_ARCH_V6T2
3739 || arch == TAG_CPU_ARCH_V6K
9e3c6df6
PB		 3740 || arch == TAG_CPU_ARCH_V7
3741 || arch == TAG_CPU_ARCH_V7E_M;
cd1dac3d
DG		 3742}
3743
3744static bfd_boolean
3745arch_has_thumb2_nop (struct elf32_arm_link_hash_table *globals)
3746{
3747 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3748 Tag_CPU_arch);
9e3c6df6
PB		 3749 return (arch == TAG_CPU_ARCH_V6T2 || arch == TAG_CPU_ARCH_V7
3750 || arch == TAG_CPU_ARCH_V7E_M);
cd1dac3d
DG		 3751}
3752
f4ac8484
DJ		 3753static bfd_boolean
3754arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3755{
3756 switch (stub_type)
3757 {
fea2b4d6
CL		 3758 case arm_stub_long_branch_thumb_only:
3759 case arm_stub_long_branch_v4t_thumb_arm:
3760 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3761 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3762 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3763 case arm_stub_long_branch_thumb_only_pic:
f4ac8484
DJ		 3764 return TRUE;
3765 case arm_stub_none:
3766 BFD_FAIL ();
3767 return FALSE;
3768 break;
3769 default:
3770 return FALSE;
3771 }
3772}
3773
906e58ca
NC		 3774/* Determine the type of stub needed, if any, for a call. */
3775
3776static enum elf32_arm_stub_type
3777arm_type_of_stub (struct bfd_link_info *info,
3778 asection *input_sec,
3779 const Elf_Internal_Rela *rel,
34e77a92 3780 unsigned char st_type,
35fc36a8 3781 enum arm_st_branch_type *actual_branch_type,
906e58ca 3782 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3783 bfd_vma destination,
3784 asection *sym_sec,
3785 bfd *input_bfd,
3786 const char *name)
906e58ca
NC		 3787{
3788 bfd_vma location;
3789 bfd_signed_vma branch_offset;
3790 unsigned int r_type;
3791 struct elf32_arm_link_hash_table * globals;
3792 int thumb2;
3793 int thumb_only;
3794 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3795 int use_plt = 0;
35fc36a8 3796 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3797 union gotplt_union *root_plt;
3798 struct arm_plt_info *arm_plt;
906e58ca 3799
35fc36a8 3800 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3801 return stub_type;
3802
906e58ca 3803 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3804 if (globals == NULL)
3805 return stub_type;
906e58ca
NC		 3806
3807 thumb_only = using_thumb_only (globals);
3808
3809 thumb2 = using_thumb2 (globals);
3810
3811 /* Determine where the call point is. */
3812 location = (input_sec->output_offset
3813 + input_sec->output_section->vma
3814 + rel->r_offset);
3815
906e58ca
NC		 3816 r_type = ELF32_R_TYPE (rel->r_info);
3817
39f21624
NC		 3818 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3819 are considering a function call relocation. */
c5423981
TG		 3820 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3821 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3822 && branch_type == ST_BRANCH_TO_ARM)
3823 branch_type = ST_BRANCH_TO_THUMB;
3824
34e77a92
RS		 3825 /* For TLS call relocs, it is the caller's responsibility to provide
3826 the address of the appropriate trampoline. */
3827 if (r_type != R_ARM_TLS_CALL
3828 && r_type != R_ARM_THM_TLS_CALL
3829 && elf32_arm_get_plt_info (input_bfd, hash, ELF32_R_SYM (rel->r_info),
3830 &root_plt, &arm_plt)
3831 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3832 {
34e77a92 3833 asection *splt;
fe33d2fa 3834
34e77a92
RS		 3835 if (hash == NULL || hash->is_iplt)
3836 splt = globals->root.iplt;
3837 else
3838 splt = globals->root.splt;
3839 if (splt != NULL)
b38cadfb 3840 {
34e77a92
RS		 3841 use_plt = 1;
3842
3843 /* Note when dealing with PLT entries: the main PLT stub is in
3844 ARM mode, so if the branch is in Thumb mode, another
3845 Thumb->ARM stub will be inserted later just before the ARM
3846 PLT stub. We don't take this extra distance into account
3847 here, because if a long branch stub is needed, we'll add a
3848 Thumb->Arm one and branch directly to the ARM PLT entry
3849 because it avoids spreading offset corrections in several
3850 places. */
3851
3852 destination = (splt->output_section->vma
3853 + splt->output_offset
3854 + root_plt->offset);
3855 st_type = STT_FUNC;
3856 branch_type = ST_BRANCH_TO_ARM;
3857 }
5fa9e92f 3858 }
34e77a92
RS		 3859 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3860 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3861
fe33d2fa
CL		 3862 branch_offset = (bfd_signed_vma)(destination - location);
3863
0855e32b 3864 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3865 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3866 {
5fa9e92f
CL		 3867 /* Handle cases where:
3868 - this call goes too far (different Thumb/Thumb2 max
99059e56 3869 distance)
155d87d7 3870 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3871 Thumb->Arm branch (not bl). A stub is needed in this case,
3872 but only if this call is not through a PLT entry. Indeed,
3873 PLT stubs handle mode switching already.
5fa9e92f 3874 */
906e58ca
NC		 3875 if ((!thumb2
3876 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3877 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
3878 || (thumb2
3879 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3880 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3881 || (thumb2
3882 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3883 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3884 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3885 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3886 && (((r_type == R_ARM_THM_CALL
3887 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3888 || (r_type == R_ARM_THM_JUMP24)
3889 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3890 && !use_plt))
906e58ca 3891 {
35fc36a8 3892 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3893 {
3894 /* Thumb to thumb. */
3895 if (!thumb_only)
3896 {
0e1862bb 3897 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3898 /* PIC stubs. */
155d87d7 3899 ? ((globals->use_blx
9553db3c 3900 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 3901 /* V5T and above. Stub starts with ARM code, so
3902 we must be able to switch mode before
3903 reaching it, which is only possible for 'bl'
3904 (ie R_ARM_THM_CALL relocation). */
cf3eccff 3905 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 3906 /* On V4T, use Thumb code only. */
d3626fb0 3907 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 3908
3909 /* non-PIC stubs. */
155d87d7 3910 : ((globals->use_blx
9553db3c 3911 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 3912 /* V5T and above. */
3913 ? arm_stub_long_branch_any_any
3914 /* V4T. */
d3626fb0 3915 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 3916 }
3917 else
3918 {
0e1862bb 3919 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
ebe24dd4
CL		 3920 /* PIC stub. */
3921 ? arm_stub_long_branch_thumb_only_pic
c2b4a39d
CL		 3922 /* non-PIC stub. */
3923 : arm_stub_long_branch_thumb_only;
906e58ca
NC		 3924 }
3925 }
3926 else
3927 {
3928 /* Thumb to arm. */
c820be07
NC		 3929 if (sym_sec != NULL
3930 && sym_sec->owner != NULL
3931 && !INTERWORK_FLAG (sym_sec->owner))
3932 {
3933 (*_bfd_error_handler)
3934 (_("%B(%s): warning: interworking not enabled.\n"
3935 " first occurrence: %B: Thumb call to ARM"),
3936 sym_sec->owner, input_bfd, name);
3937 }
3938
0855e32b 3939 stub_type =
0e1862bb 3940 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3941 /* PIC stubs. */
0855e32b 3942 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 3943 /* TLS PIC stubs. */
0855e32b
NS		 3944 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
3945 : arm_stub_long_branch_v4t_thumb_tls_pic)
3946 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
3947 /* V5T PIC and above. */
3948 ? arm_stub_long_branch_any_arm_pic
3949 /* V4T PIC stub. */
3950 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 3951
3952 /* non-PIC stubs. */
0855e32b 3953 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 3954 /* V5T and above. */
3955 ? arm_stub_long_branch_any_any
3956 /* V4T. */
3957 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 3958
3959 /* Handle v4t short branches. */
fea2b4d6 3960 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 3961 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
3962 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 3963 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 3964 }
3965 }
3966 }
fe33d2fa
CL		 3967 else if (r_type == R_ARM_CALL
3968 || r_type == R_ARM_JUMP24
0855e32b
NS		 3969 || r_type == R_ARM_PLT32
3970 || r_type == R_ARM_TLS_CALL)
906e58ca 3971 {
35fc36a8 3972 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3973 {
3974 /* Arm to thumb. */
c820be07
NC		 3975
3976 if (sym_sec != NULL
3977 && sym_sec->owner != NULL
3978 && !INTERWORK_FLAG (sym_sec->owner))
3979 {
3980 (*_bfd_error_handler)
3981 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 3982 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 3983 sym_sec->owner, input_bfd, name);
3984 }
3985
3986 /* We have an extra 2-bytes reach because of
3987 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 3988 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
3989 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 3990 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 3991 || (r_type == R_ARM_JUMP24)
3992 || (r_type == R_ARM_PLT32))
906e58ca 3993 {
0e1862bb 3994 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3995 /* PIC stubs. */
ebe24dd4
CL		 3996 ? ((globals->use_blx)
3997 /* V5T and above. */
3998 ? arm_stub_long_branch_any_thumb_pic
3999 /* V4T stub. */
4000 : arm_stub_long_branch_v4t_arm_thumb_pic)
4001
c2b4a39d
CL		 4002 /* non-PIC stubs. */
4003 : ((globals->use_blx)
4004 /* V5T and above. */
4005 ? arm_stub_long_branch_any_any
4006 /* V4T. */
4007 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4008 }
4009 }
4010 else
4011 {
4012 /* Arm to arm. */
4013 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4014 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4015 {
0855e32b 4016 stub_type =
0e1862bb 4017 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4018 /* PIC stubs. */
0855e32b 4019 ? (r_type == R_ARM_TLS_CALL
6a631e86 4020 /* TLS PIC Stub. */
0855e32b 4021 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4022 : (globals->nacl_p
4023 ? arm_stub_long_branch_arm_nacl_pic
4024 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4025 /* non-PIC stubs. */
7a89b94e
NC		 4026 : (globals->nacl_p
4027 ? arm_stub_long_branch_arm_nacl
4028 : arm_stub_long_branch_any_any);
906e58ca
NC		 4029 }
4030 }
4031 }
4032
fe33d2fa
CL		 4033 /* If a stub is needed, record the actual destination type. */
4034 if (stub_type != arm_stub_none)
35fc36a8 4035 *actual_branch_type = branch_type;
fe33d2fa 4036
906e58ca
NC		 4037 return stub_type;
4038}
4039
4040/* Build a name for an entry in the stub hash table. */
4041
4042static char *
4043elf32_arm_stub_name (const asection *input_section,
4044 const asection *sym_sec,
4045 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4046 const Elf_Internal_Rela *rel,
4047 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4048{
4049 char *stub_name;
4050 bfd_size_type len;
4051
4052 if (hash)
4053 {
fe33d2fa 4054 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4055 stub_name = (char *) bfd_malloc (len);
906e58ca 4056 if (stub_name != NULL)
fe33d2fa 4057 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4058 input_section->id & 0xffffffff,
4059 hash->root.root.root.string,
fe33d2fa
CL		 4060 (int) rel->r_addend & 0xffffffff,
4061 (int) stub_type);
906e58ca
NC		 4062 }
4063 else
4064 {
fe33d2fa 4065 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4066 stub_name = (char *) bfd_malloc (len);
906e58ca 4067 if (stub_name != NULL)
fe33d2fa 4068 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4069 input_section->id & 0xffffffff,
4070 sym_sec->id & 0xffffffff,
0855e32b
NS		 4071 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4072 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4073 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4074 (int) rel->r_addend & 0xffffffff,
4075 (int) stub_type);
906e58ca
NC		 4076 }
4077
4078 return stub_name;
4079}
4080
4081/* Look up an entry in the stub hash. Stub entries are cached because
4082 creating the stub name takes a bit of time. */
4083
4084static struct elf32_arm_stub_hash_entry *
4085elf32_arm_get_stub_entry (const asection *input_section,
4086 const asection *sym_sec,
4087 struct elf_link_hash_entry *hash,
4088 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4089 struct elf32_arm_link_hash_table *htab,
4090 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4091{
4092 struct elf32_arm_stub_hash_entry *stub_entry;
4093 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4094 const asection *id_sec;
4095
4096 if ((input_section->flags & SEC_CODE) == 0)
4097 return NULL;
4098
4099 /* If this input section is part of a group of sections sharing one
4100 stub section, then use the id of the first section in the group.
4101 Stub names need to include a section id, as there may well be
4102 more than one stub used to reach say, printf, and we need to
4103 distinguish between them. */
4104 id_sec = htab->stub_group[input_section->id].link_sec;
4105
4106 if (h != NULL && h->stub_cache != NULL
4107 && h->stub_cache->h == h
fe33d2fa
CL		 4108 && h->stub_cache->id_sec == id_sec
4109 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4110 {
4111 stub_entry = h->stub_cache;
4112 }
4113 else
4114 {
4115 char *stub_name;
4116
fe33d2fa 4117 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4118 if (stub_name == NULL)
4119 return NULL;
4120
4121 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4122 stub_name, FALSE, FALSE);
4123 if (h != NULL)
4124 h->stub_cache = stub_entry;
4125
4126 free (stub_name);
4127 }
4128
4129 return stub_entry;
4130}
4131
48229727 4132/* Find or create a stub section. Returns a pointer to the stub section, and
b38cadfb 4133 the section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4134 LINK_SEC_P may be NULL. */
906e58ca 4135
48229727
JB		 4136static asection *
4137elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
4138 struct elf32_arm_link_hash_table *htab)
906e58ca
NC		 4139{
4140 asection *link_sec;
4141 asection *stub_sec;
906e58ca
NC		 4142
4143 link_sec = htab->stub_group[section->id].link_sec;
9553db3c 4144 BFD_ASSERT (link_sec != NULL);
906e58ca 4145 stub_sec = htab->stub_group[section->id].stub_sec;
9553db3c 4146
906e58ca
NC		 4147 if (stub_sec == NULL)
4148 {
4149 stub_sec = htab->stub_group[link_sec->id].stub_sec;
4150 if (stub_sec == NULL)
4151 {
4152 size_t namelen;
4153 bfd_size_type len;
4154 char *s_name;
4155
4156 namelen = strlen (link_sec->name);
4157 len = namelen + sizeof (STUB_SUFFIX);
21d799b5 4158 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
906e58ca
NC		 4159 if (s_name == NULL)
4160 return NULL;
4161
4162 memcpy (s_name, link_sec->name, namelen);
4163 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
7a89b94e
NC		 4164 stub_sec = (*htab->add_stub_section) (s_name, link_sec,
4165 htab->nacl_p ? 4 : 3);
906e58ca
NC		 4166 if (stub_sec == NULL)
4167 return NULL;
4168 htab->stub_group[link_sec->id].stub_sec = stub_sec;
4169 }
4170 htab->stub_group[section->id].stub_sec = stub_sec;
4171 }
b38cadfb 4172
48229727
JB		 4173 if (link_sec_p)
4174 *link_sec_p = link_sec;
b38cadfb 4175
48229727
JB		 4176 return stub_sec;
4177}
4178
4179/* Add a new stub entry to the stub hash. Not all fields of the new
4180 stub entry are initialised. */
4181
4182static struct elf32_arm_stub_hash_entry *
4183elf32_arm_add_stub (const char *stub_name,
4184 asection *section,
4185 struct elf32_arm_link_hash_table *htab)
4186{
4187 asection *link_sec;
4188 asection *stub_sec;
4189 struct elf32_arm_stub_hash_entry *stub_entry;
4190
4191 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab);
4192 if (stub_sec == NULL)
4193 return NULL;
906e58ca
NC		 4194
4195 /* Enter this entry into the linker stub hash table. */
4196 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4197 TRUE, FALSE);
4198 if (stub_entry == NULL)
4199 {
4200 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4201 section->owner,
4202 stub_name);
4203 return NULL;
4204 }
4205
4206 stub_entry->stub_sec = stub_sec;
4207 stub_entry->stub_offset = 0;
4208 stub_entry->id_sec = link_sec;
4209
906e58ca
NC		 4210 return stub_entry;
4211}
4212
4213/* Store an Arm insn into an output section not processed by
4214 elf32_arm_write_section. */
4215
4216static void
8029a119
NC		 4217put_arm_insn (struct elf32_arm_link_hash_table * htab,
4218 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4219{
4220 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4221 bfd_putl32 (val, ptr);
4222 else
4223 bfd_putb32 (val, ptr);
4224}
4225
4226/* Store a 16-bit Thumb insn into an output section not processed by
4227 elf32_arm_write_section. */
4228
4229static void
8029a119
NC		 4230put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4231 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4232{
4233 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4234 bfd_putl16 (val, ptr);
4235 else
4236 bfd_putb16 (val, ptr);
4237}
4238
a504d23a
LA		 4239/* Store a Thumb2 insn into an output section not processed by
4240 elf32_arm_write_section. */
4241
4242static void
4243put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4244 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4245{
4246 /* T2 instructions are 16-bit streamed. */
4247 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4248 {
4249 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4250 bfd_putl16 ((val & 0xffff), ptr + 2);
4251 }
4252 else
4253 {
4254 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4255 bfd_putb16 ((val & 0xffff), ptr + 2);
4256 }
4257}
4258
0855e32b
NS		 4259/* If it's possible to change R_TYPE to a more efficient access
4260 model, return the new reloc type. */
4261
4262static unsigned
b38cadfb 4263elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4264 struct elf_link_hash_entry *h)
4265{
4266 int is_local = (h == NULL);
4267
0e1862bb
L		 4268 if (bfd_link_pic (info)
4269 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4270 return r_type;
4271
b38cadfb 4272 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4273 switch (r_type)
4274 {
4275 case R_ARM_TLS_GOTDESC:
4276 case R_ARM_TLS_CALL:
4277 case R_ARM_THM_TLS_CALL:
4278 case R_ARM_TLS_DESCSEQ:
4279 case R_ARM_THM_TLS_DESCSEQ:
4280 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4281 }
4282
4283 return r_type;
4284}
4285
48229727
JB		 4286static bfd_reloc_status_type elf32_arm_final_link_relocate
4287 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4288 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4289 const char *, unsigned char, enum arm_st_branch_type,
4290 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4291
4563a860
JB		 4292static unsigned int
4293arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4294{
4295 switch (stub_type)
4296 {
4297 case arm_stub_a8_veneer_b_cond:
4298 case arm_stub_a8_veneer_b:
4299 case arm_stub_a8_veneer_bl:
4300 return 2;
4301
4302 case arm_stub_long_branch_any_any:
4303 case arm_stub_long_branch_v4t_arm_thumb:
4304 case arm_stub_long_branch_thumb_only:
4305 case arm_stub_long_branch_v4t_thumb_thumb:
4306 case arm_stub_long_branch_v4t_thumb_arm:
4307 case arm_stub_short_branch_v4t_thumb_arm:
4308 case arm_stub_long_branch_any_arm_pic:
4309 case arm_stub_long_branch_any_thumb_pic:
4310 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4311 case arm_stub_long_branch_v4t_arm_thumb_pic:
4312 case arm_stub_long_branch_v4t_thumb_arm_pic:
4313 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4314 case arm_stub_long_branch_any_tls_pic:
4315 case arm_stub_long_branch_v4t_thumb_tls_pic:
4563a860
JB		 4316 case arm_stub_a8_veneer_blx:
4317 return 4;
b38cadfb 4318
7a89b94e
NC		 4319 case arm_stub_long_branch_arm_nacl:
4320 case arm_stub_long_branch_arm_nacl_pic:
4321 return 16;
4322
4563a860
JB		 4323 default:
4324 abort (); /* Should be unreachable. */
4325 }
4326}
4327
906e58ca
NC		 4328static bfd_boolean
4329arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4330 void * in_arg)
4331{
7a89b94e 4332#define MAXRELOCS 3
906e58ca 4333 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4334 struct elf32_arm_link_hash_table *globals;
906e58ca 4335 struct bfd_link_info *info;
906e58ca
NC		 4336 asection *stub_sec;
4337 bfd *stub_bfd;
906e58ca
NC		 4338 bfd_byte *loc;
4339 bfd_vma sym_value;
4340 int template_size;
4341 int size;
d3ce72d0 4342 const insn_sequence *template_sequence;
906e58ca 4343 int i;
48229727
JB		 4344 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4345 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4346 int nrelocs = 0;
906e58ca
NC		 4347
4348 /* Massage our args to the form they really have. */
4349 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4350 info = (struct bfd_link_info *) in_arg;
4351
4352 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4353 if (globals == NULL)
4354 return FALSE;
906e58ca 4355
906e58ca
NC		 4356 stub_sec = stub_entry->stub_sec;
4357
4dfe6ac6 4358 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4359 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4360 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4361 return TRUE;
fe33d2fa 4362
906e58ca
NC		 4363 /* Make a note of the offset within the stubs for this entry. */
4364 stub_entry->stub_offset = stub_sec->size;
4365 loc = stub_sec->contents + stub_entry->stub_offset;
4366
4367 stub_bfd = stub_sec->owner;
4368
906e58ca
NC		 4369 /* This is the address of the stub destination. */
4370 sym_value = (stub_entry->target_value
4371 + stub_entry->target_section->output_offset
4372 + stub_entry->target_section->output_section->vma);
4373
d3ce72d0 4374 template_sequence = stub_entry->stub_template;
461a49ca 4375 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4376
4377 size = 0;
461a49ca 4378 for (i = 0; i < template_size; i++)
906e58ca 4379 {
d3ce72d0 4380 switch (template_sequence[i].type)
461a49ca
DJ		 4381 {
4382 case THUMB16_TYPE:
48229727 4383 {
d3ce72d0
NC		 4384 bfd_vma data = (bfd_vma) template_sequence[i].data;
4385 if (template_sequence[i].reloc_addend != 0)
48229727 4386 {
99059e56
RM		 4387 /* We've borrowed the reloc_addend field to mean we should
4388 insert a condition code into this (Thumb-1 branch)
4389 instruction. See THUMB16_BCOND_INSN. */
4390 BFD_ASSERT ((data & 0xff00) == 0xd000);
4391 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4392 }
fe33d2fa 4393 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4394 size += 2;
4395 }
461a49ca 4396 break;
906e58ca 4397
48229727 4398 case THUMB32_TYPE:
fe33d2fa
CL		 4399 bfd_put_16 (stub_bfd,
4400 (template_sequence[i].data >> 16) & 0xffff,
4401 loc + size);
4402 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4403 loc + size + 2);
99059e56
RM		 4404 if (template_sequence[i].r_type != R_ARM_NONE)
4405 {
4406 stub_reloc_idx[nrelocs] = i;
4407 stub_reloc_offset[nrelocs++] = size;
4408 }
4409 size += 4;
4410 break;
48229727 4411
461a49ca 4412 case ARM_TYPE:
fe33d2fa
CL		 4413 bfd_put_32 (stub_bfd, template_sequence[i].data,
4414 loc + size);
461a49ca
DJ		 4415 /* Handle cases where the target is encoded within the
4416 instruction. */
d3ce72d0 4417 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4418 {
48229727
JB		 4419 stub_reloc_idx[nrelocs] = i;
4420 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4421 }
4422 size += 4;
4423 break;
4424
4425 case DATA_TYPE:
d3ce72d0 4426 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4427 stub_reloc_idx[nrelocs] = i;
4428 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4429 size += 4;
4430 break;
4431
4432 default:
4433 BFD_FAIL ();
4434 return FALSE;
4435 }
906e58ca 4436 }
461a49ca 4437
906e58ca
NC		 4438 stub_sec->size += size;
4439
461a49ca
DJ		 4440 /* Stub size has already been computed in arm_size_one_stub. Check
4441 consistency. */
4442 BFD_ASSERT (size == stub_entry->stub_size);
4443
906e58ca 4444 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4445 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4446 sym_value |= 1;
4447
48229727
JB		 4448 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4449 in each stub. */
4450 BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS);
c820be07 4451
48229727 4452 for (i = 0; i < nrelocs; i++)
d3ce72d0
NC		 4453 if (template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_JUMP24
4454 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_JUMP19
4455 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_CALL
4456 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_XPC22)
48229727
JB		 4457 {
4458 Elf_Internal_Rela rel;
4459 bfd_boolean unresolved_reloc;
4460 char *error_message;
35fc36a8
RS		 4461 enum arm_st_branch_type branch_type
4462 = (template_sequence[stub_reloc_idx[i]].r_type != R_ARM_THM_XPC22
4463 ? ST_BRANCH_TO_THUMB : ST_BRANCH_TO_ARM);
48229727
JB		 4464 bfd_vma points_to = sym_value + stub_entry->target_addend;
4465
4466 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
d3ce72d0 4467 rel.r_info = ELF32_R_INFO (0,
99059e56 4468 template_sequence[stub_reloc_idx[i]].r_type);
d3ce72d0 4469 rel.r_addend = template_sequence[stub_reloc_idx[i]].reloc_addend;
48229727
JB		 4470
4471 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4472 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4473 template should refer back to the instruction after the original
4474 branch. */
4475 points_to = sym_value;
4476
33c6a8fc
JB		 4477 /* There may be unintended consequences if this is not true. */
4478 BFD_ASSERT (stub_entry->h == NULL);
4479
48229727
JB		 4480 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4481 properly. We should probably use this function unconditionally,
4482 rather than only for certain relocations listed in the enclosing
4483 conditional, for the sake of consistency. */
4484 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
d3ce72d0 4485 (template_sequence[stub_reloc_idx[i]].r_type),
48229727 4486 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
34e77a92
RS		 4487 points_to, info, stub_entry->target_section, "", STT_FUNC,
4488 branch_type, (struct elf_link_hash_entry *) stub_entry->h,
4489 &unresolved_reloc, &error_message);
48229727
JB		 4490 }
4491 else
4492 {
fe33d2fa
CL		 4493 Elf_Internal_Rela rel;
4494 bfd_boolean unresolved_reloc;
4495 char *error_message;
4496 bfd_vma points_to = sym_value + stub_entry->target_addend
4497 + template_sequence[stub_reloc_idx[i]].reloc_addend;
4498
4499 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4500 rel.r_info = ELF32_R_INFO (0,
99059e56 4501 template_sequence[stub_reloc_idx[i]].r_type);
fe33d2fa
CL		 4502 rel.r_addend = 0;
4503
4504 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4505 (template_sequence[stub_reloc_idx[i]].r_type),
4506 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
34e77a92 4507 points_to, info, stub_entry->target_section, "", STT_FUNC,
35fc36a8 4508 stub_entry->branch_type,
fe33d2fa
CL		 4509 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4510 &error_message);
48229727 4511 }
906e58ca
NC		 4512
4513 return TRUE;
48229727 4514#undef MAXRELOCS
906e58ca
NC		 4515}
4516
48229727
JB		 4517/* Calculate the template, template size and instruction size for a stub.
4518 Return value is the instruction size. */
906e58ca 4519
48229727
JB		 4520static unsigned int
4521find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4522 const insn_sequence **stub_template,
4523 int *stub_template_size)
906e58ca 4524{
d3ce72d0 4525 const insn_sequence *template_sequence = NULL;
48229727
JB		 4526 int template_size = 0, i;
4527 unsigned int size;
906e58ca 4528
d3ce72d0 4529 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4530 if (stub_template)
4531 *stub_template = template_sequence;
4532
48229727 4533 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4534 if (stub_template_size)
4535 *stub_template_size = template_size;
906e58ca
NC		 4536
4537 size = 0;
461a49ca
DJ		 4538 for (i = 0; i < template_size; i++)
4539 {
d3ce72d0 4540 switch (template_sequence[i].type)
461a49ca
DJ		 4541 {
4542 case THUMB16_TYPE:
4543 size += 2;
4544 break;
4545
4546 case ARM_TYPE:
48229727 4547 case THUMB32_TYPE:
461a49ca
DJ		 4548 case DATA_TYPE:
4549 size += 4;
4550 break;
4551
4552 default:
4553 BFD_FAIL ();
2a229407 4554 return 0;
461a49ca
DJ		 4555 }
4556 }
4557
48229727
JB		 4558 return size;
4559}
4560
4561/* As above, but don't actually build the stub. Just bump offset so
4562 we know stub section sizes. */
4563
4564static bfd_boolean
4565arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4566 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4567{
4568 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4569 const insn_sequence *template_sequence;
48229727
JB		 4570 int template_size, size;
4571
4572 /* Massage our args to the form they really have. */
4573 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4574
4575 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4576 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4577
d3ce72d0 4578 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4579 &template_size);
4580
461a49ca 4581 stub_entry->stub_size = size;
d3ce72d0 4582 stub_entry->stub_template = template_sequence;
461a49ca
DJ		 4583 stub_entry->stub_template_size = template_size;
4584
906e58ca
NC		 4585 size = (size + 7) & ~7;
4586 stub_entry->stub_sec->size += size;
461a49ca 4587
906e58ca
NC		 4588 return TRUE;
4589}
4590
4591/* External entry points for sizing and building linker stubs. */
4592
4593/* Set up various things so that we can make a list of input sections
4594 for each output section included in the link. Returns -1 on error,
4595 0 when no stubs will be needed, and 1 on success. */
4596
4597int
4598elf32_arm_setup_section_lists (bfd *output_bfd,
4599 struct bfd_link_info *info)
4600{
4601 bfd *input_bfd;
4602 unsigned int bfd_count;
7292b3ac 4603 unsigned int top_id, top_index;
906e58ca
NC		 4604 asection *section;
4605 asection **input_list, **list;
4606 bfd_size_type amt;
4607 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4608
4dfe6ac6
NC		 4609 if (htab == NULL)
4610 return 0;
906e58ca
NC		 4611 if (! is_elf_hash_table (htab))
4612 return 0;
4613
4614 /* Count the number of input BFDs and find the top input section id. */
4615 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4616 input_bfd != NULL;
c72f2fb2 4617 input_bfd = input_bfd->link.next)
906e58ca
NC		 4618 {
4619 bfd_count += 1;
4620 for (section = input_bfd->sections;
4621 section != NULL;
4622 section = section->next)
4623 {
4624 if (top_id < section->id)
4625 top_id = section->id;
4626 }
4627 }
4628 htab->bfd_count = bfd_count;
4629
4630 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4631 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4632 if (htab->stub_group == NULL)
4633 return -1;
fe33d2fa 4634 htab->top_id = top_id;
906e58ca
NC		 4635
4636 /* We can't use output_bfd->section_count here to find the top output
4637 section index as some sections may have been removed, and
4638 _bfd_strip_section_from_output doesn't renumber the indices. */
4639 for (section = output_bfd->sections, top_index = 0;
4640 section != NULL;
4641 section = section->next)
4642 {
4643 if (top_index < section->index)
4644 top_index = section->index;
4645 }
4646
4647 htab->top_index = top_index;
4648 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4649 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4650 htab->input_list = input_list;
4651 if (input_list == NULL)
4652 return -1;
4653
4654 /* For sections we aren't interested in, mark their entries with a
4655 value we can check later. */
4656 list = input_list + top_index;
4657 do
4658 *list = bfd_abs_section_ptr;
4659 while (list-- != input_list);
4660
4661 for (section = output_bfd->sections;
4662 section != NULL;
4663 section = section->next)
4664 {
4665 if ((section->flags & SEC_CODE) != 0)
4666 input_list[section->index] = NULL;
4667 }
4668
4669 return 1;
4670}
4671
4672/* The linker repeatedly calls this function for each input section,
4673 in the order that input sections are linked into output sections.
4674 Build lists of input sections to determine groupings between which
4675 we may insert linker stubs. */
4676
4677void
4678elf32_arm_next_input_section (struct bfd_link_info *info,
4679 asection *isec)
4680{
4681 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4682
4dfe6ac6
NC		 4683 if (htab == NULL)
4684 return;
4685
906e58ca
NC		 4686 if (isec->output_section->index <= htab->top_index)
4687 {
4688 asection **list = htab->input_list + isec->output_section->index;
4689
a7470592 4690 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 4691 {
4692 /* Steal the link_sec pointer for our list. */
4693#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4694 /* This happens to make the list in reverse order,
07d72278 4695 which we reverse later. */
906e58ca
NC		 4696 PREV_SEC (isec) = *list;
4697 *list = isec;
4698 }
4699 }
4700}
4701
4702/* See whether we can group stub sections together. Grouping stub
4703 sections may result in fewer stubs. More importantly, we need to
07d72278 4704 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 4705 .fini output sections respectively, because glibc splits the
4706 _init and _fini functions into multiple parts. Putting a stub in
4707 the middle of a function is not a good idea. */
4708
4709static void
4710group_sections (struct elf32_arm_link_hash_table *htab,
4711 bfd_size_type stub_group_size,
07d72278 4712 bfd_boolean stubs_always_after_branch)
906e58ca 4713{
07d72278 4714 asection **list = htab->input_list;
906e58ca
NC		 4715
4716 do
4717 {
4718 asection *tail = *list;
07d72278 4719 asection *head;
906e58ca
NC		 4720
4721 if (tail == bfd_abs_section_ptr)
4722 continue;
4723
07d72278
DJ		 4724 /* Reverse the list: we must avoid placing stubs at the
4725 beginning of the section because the beginning of the text
4726 section may be required for an interrupt vector in bare metal
4727 code. */
4728#define NEXT_SEC PREV_SEC
e780aef2
CL		 4729 head = NULL;
4730 while (tail != NULL)
99059e56
RM		 4731 {
4732 /* Pop from tail. */
4733 asection *item = tail;
4734 tail = PREV_SEC (item);
e780aef2 4735
99059e56
RM		 4736 /* Push on head. */
4737 NEXT_SEC (item) = head;
4738 head = item;
4739 }
07d72278
DJ		 4740
4741 while (head != NULL)
906e58ca
NC		 4742 {
4743 asection *curr;
07d72278 4744 asection *next;
e780aef2
CL		 4745 bfd_vma stub_group_start = head->output_offset;
4746 bfd_vma end_of_next;
906e58ca 4747
07d72278 4748 curr = head;
e780aef2 4749 while (NEXT_SEC (curr) != NULL)
8cd931b7 4750 {
e780aef2
CL		 4751 next = NEXT_SEC (curr);
4752 end_of_next = next->output_offset + next->size;
4753 if (end_of_next - stub_group_start >= stub_group_size)
4754 /* End of NEXT is too far from start, so stop. */
8cd931b7 4755 break;
e780aef2
CL		 4756 /* Add NEXT to the group. */
4757 curr = next;
8cd931b7 4758 }
906e58ca 4759
07d72278 4760 /* OK, the size from the start to the start of CURR is less
906e58ca 4761 than stub_group_size and thus can be handled by one stub
07d72278 4762 section. (Or the head section is itself larger than
906e58ca
NC		 4763 stub_group_size, in which case we may be toast.)
4764 We should really be keeping track of the total size of
4765 stubs added here, as stubs contribute to the final output
7fb9f789 4766 section size. */
906e58ca
NC		 4767 do
4768 {
07d72278 4769 next = NEXT_SEC (head);
906e58ca 4770 /* Set up this stub group. */
07d72278 4771 htab->stub_group[head->id].link_sec = curr;
906e58ca 4772 }
07d72278 4773 while (head != curr && (head = next) != NULL);
906e58ca
NC		 4774
4775 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 4776 bytes after the stub section can be handled by it too. */
4777 if (!stubs_always_after_branch)
906e58ca 4778 {
e780aef2
CL		 4779 stub_group_start = curr->output_offset + curr->size;
4780
8cd931b7 4781 while (next != NULL)
906e58ca 4782 {
e780aef2
CL		 4783 end_of_next = next->output_offset + next->size;
4784 if (end_of_next - stub_group_start >= stub_group_size)
4785 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 4786 break;
e780aef2 4787 /* Add NEXT to the stub group. */
07d72278
DJ		 4788 head = next;
4789 next = NEXT_SEC (head);
4790 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 4791 }
4792 }
07d72278 4793 head = next;
906e58ca
NC		 4794 }
4795 }
07d72278 4796 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 4797
4798 free (htab->input_list);
4799#undef PREV_SEC
07d72278 4800#undef NEXT_SEC
906e58ca
NC		 4801}
4802
48229727
JB		 4803/* Comparison function for sorting/searching relocations relating to Cortex-A8
4804 erratum fix. */
4805
4806static int
4807a8_reloc_compare (const void *a, const void *b)
4808{
21d799b5
NC		 4809 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
4810 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 4811
4812 if (ra->from < rb->from)
4813 return -1;
4814 else if (ra->from > rb->from)
4815 return 1;
4816 else
4817 return 0;
4818}
4819
4820static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
4821 const char *, char **);
4822
4823/* Helper function to scan code for sequences which might trigger the Cortex-A8
4824 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 4825 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 4826 otherwise. */
4827
81694485
NC		 4828static bfd_boolean
4829cortex_a8_erratum_scan (bfd *input_bfd,
4830 struct bfd_link_info *info,
48229727
JB		 4831 struct a8_erratum_fix **a8_fixes_p,
4832 unsigned int *num_a8_fixes_p,
4833 unsigned int *a8_fix_table_size_p,
4834 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 4835 unsigned int num_a8_relocs,
4836 unsigned prev_num_a8_fixes,
4837 bfd_boolean *stub_changed_p)
48229727
JB		 4838{
4839 asection *section;
4840 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4841 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
4842 unsigned int num_a8_fixes = *num_a8_fixes_p;
4843 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
4844
4dfe6ac6
NC		 4845 if (htab == NULL)
4846 return FALSE;
4847
48229727
JB		 4848 for (section = input_bfd->sections;
4849 section != NULL;
4850 section = section->next)
4851 {
4852 bfd_byte *contents = NULL;
4853 struct _arm_elf_section_data *sec_data;
4854 unsigned int span;
4855 bfd_vma base_vma;
4856
4857 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 4858 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
4859 || (section->flags & SEC_EXCLUDE) != 0
4860 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
4861 || (section->output_section == bfd_abs_section_ptr))
4862 continue;
48229727
JB		 4863
4864 base_vma = section->output_section->vma + section->output_offset;
4865
4866 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 4867 contents = elf_section_data (section)->this_hdr.contents;
48229727 4868 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 4869 return TRUE;
48229727
JB		 4870
4871 sec_data = elf32_arm_section_data (section);
4872
4873 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 4874 {
4875 unsigned int span_start = sec_data->map[span].vma;
4876 unsigned int span_end = (span == sec_data->mapcount - 1)
4877 ? section->size : sec_data->map[span + 1].vma;
4878 unsigned int i;
4879 char span_type = sec_data->map[span].type;
4880 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
4881
4882 if (span_type != 't')
4883 continue;
4884
4885 /* Span is entirely within a single 4KB region: skip scanning. */
4886 if (((base_vma + span_start) & ~0xfff)
48229727 4887 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 4888 continue;
4889
4890 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4891
4892 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4893 * The branch target is in the same 4KB region as the
4894 first half of the branch.
4895 * The instruction before the branch is a 32-bit
4896 length non-branch instruction. */
4897 for (i = span_start; i < span_end;)
4898 {
4899 unsigned int insn = bfd_getl16 (&contents[i]);
4900 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 4901 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
4902
99059e56
RM		 4903 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
4904 insn_32bit = TRUE;
48229727
JB		 4905
4906 if (insn_32bit)
99059e56
RM		 4907 {
4908 /* Load the rest of the insn (in manual-friendly order). */
4909 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
4910
4911 /* Encoding T4: B<c>.W. */
4912 is_b = (insn & 0xf800d000) == 0xf0009000;
4913 /* Encoding T1: BL<c>.W. */
4914 is_bl = (insn & 0xf800d000) == 0xf000d000;
4915 /* Encoding T2: BLX<c>.W. */
4916 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 4917 /* Encoding T3: B<c>.W (not permitted in IT block). */
4918 is_bcc = (insn & 0xf800d000) == 0xf0008000
4919 && (insn & 0x07f00000) != 0x03800000;
4920 }
4921
4922 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 4923
99059e56 4924 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 4925 && insn_32bit
4926 && is_32bit_branch
4927 && last_was_32bit
4928 && ! last_was_branch)
99059e56
RM		 4929 {
4930 bfd_signed_vma offset = 0;
4931 bfd_boolean force_target_arm = FALSE;
48229727 4932 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 4933 bfd_vma target;
4934 enum elf32_arm_stub_type stub_type = arm_stub_none;
4935 struct a8_erratum_reloc key, *found;
4936 bfd_boolean use_plt = FALSE;
48229727 4937
99059e56
RM		 4938 key.from = base_vma + i;
4939 found = (struct a8_erratum_reloc *)
4940 bsearch (&key, a8_relocs, num_a8_relocs,
4941 sizeof (struct a8_erratum_reloc),
4942 &a8_reloc_compare);
48229727
JB		 4943
4944 if (found)
4945 {
4946 char *error_message = NULL;
4947 struct elf_link_hash_entry *entry;
4948
4949 /* We don't care about the error returned from this
99059e56 4950 function, only if there is glue or not. */
48229727
JB		 4951 entry = find_thumb_glue (info, found->sym_name,
4952 &error_message);
4953
4954 if (entry)
4955 found->non_a8_stub = TRUE;
4956
92750f34 4957 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 4958 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 4959 && found->hash->root.plt.offset != (bfd_vma) -1)
4960 use_plt = TRUE;
4961
4962 if (found->r_type == R_ARM_THM_CALL)
4963 {
35fc36a8
RS		 4964 if (found->branch_type == ST_BRANCH_TO_ARM
4965 || use_plt)
92750f34
DJ		 4966 force_target_arm = TRUE;
4967 else
4968 force_target_thumb = TRUE;
4969 }
48229727
JB		 4970 }
4971
99059e56 4972 /* Check if we have an offending branch instruction. */
48229727
JB		 4973
4974 if (found && found->non_a8_stub)
4975 /* We've already made a stub for this instruction, e.g.
4976 it's a long branch or a Thumb->ARM stub. Assume that
4977 stub will suffice to work around the A8 erratum (see
4978 setting of always_after_branch above). */
4979 ;
99059e56
RM		 4980 else if (is_bcc)
4981 {
4982 offset = (insn & 0x7ff) << 1;
4983 offset |= (insn & 0x3f0000) >> 4;
4984 offset |= (insn & 0x2000) ? 0x40000 : 0;
4985 offset |= (insn & 0x800) ? 0x80000 : 0;
4986 offset |= (insn & 0x4000000) ? 0x100000 : 0;
4987 if (offset & 0x100000)
4988 offset |= ~ ((bfd_signed_vma) 0xfffff);
4989 stub_type = arm_stub_a8_veneer_b_cond;
4990 }
4991 else if (is_b || is_bl || is_blx)
4992 {
4993 int s = (insn & 0x4000000) != 0;
4994 int j1 = (insn & 0x2000) != 0;
4995 int j2 = (insn & 0x800) != 0;
4996 int i1 = !(j1 ^ s);
4997 int i2 = !(j2 ^ s);
4998
4999 offset = (insn & 0x7ff) << 1;
5000 offset |= (insn & 0x3ff0000) >> 4;
5001 offset |= i2 << 22;
5002 offset |= i1 << 23;
5003 offset |= s << 24;
5004 if (offset & 0x1000000)
5005 offset |= ~ ((bfd_signed_vma) 0xffffff);
5006
5007 if (is_blx)
5008 offset &= ~ ((bfd_signed_vma) 3);
5009
5010 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5011 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5012 }
5013
5014 if (stub_type != arm_stub_none)
5015 {
5016 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5017
5018 /* The original instruction is a BL, but the target is
99059e56 5019 an ARM instruction. If we were not making a stub,
48229727
JB		 5020 the BL would have been converted to a BLX. Use the
5021 BLX stub instead in that case. */
5022 if (htab->use_blx && force_target_arm
5023 && stub_type == arm_stub_a8_veneer_bl)
5024 {
5025 stub_type = arm_stub_a8_veneer_blx;
5026 is_blx = TRUE;
5027 is_bl = FALSE;
5028 }
5029 /* Conversely, if the original instruction was
5030 BLX but the target is Thumb mode, use the BL
5031 stub. */
5032 else if (force_target_thumb
5033 && stub_type == arm_stub_a8_veneer_blx)
5034 {
5035 stub_type = arm_stub_a8_veneer_bl;
5036 is_blx = FALSE;
5037 is_bl = TRUE;
5038 }
5039
99059e56
RM		 5040 if (is_blx)
5041 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5042
99059e56
RM		 5043 /* If we found a relocation, use the proper destination,
5044 not the offset in the (unrelocated) instruction.
48229727
JB		 5045 Note this is always done if we switched the stub type
5046 above. */
99059e56
RM		 5047 if (found)
5048 offset =
81694485 5049 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5050
99059e56
RM		 5051 /* If the stub will use a Thumb-mode branch to a
5052 PLT target, redirect it to the preceding Thumb
5053 entry point. */
5054 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5055 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5056
99059e56 5057 target = pc_for_insn + offset;
48229727 5058
99059e56
RM		 5059 /* The BLX stub is ARM-mode code. Adjust the offset to
5060 take the different PC value (+8 instead of +4) into
48229727 5061 account. */
99059e56
RM		 5062 if (stub_type == arm_stub_a8_veneer_blx)
5063 offset += 4;
5064
5065 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5066 {
5067 char *stub_name = NULL;
5068
5069 if (num_a8_fixes == a8_fix_table_size)
5070 {
5071 a8_fix_table_size *= 2;
5072 a8_fixes = (struct a8_erratum_fix *)
5073 bfd_realloc (a8_fixes,
5074 sizeof (struct a8_erratum_fix)
5075 * a8_fix_table_size);
5076 }
48229727 5077
eb7c4339
NS		 5078 if (num_a8_fixes < prev_num_a8_fixes)
5079 {
5080 /* If we're doing a subsequent scan,
5081 check if we've found the same fix as
5082 before, and try and reuse the stub
5083 name. */
5084 stub_name = a8_fixes[num_a8_fixes].stub_name;
5085 if ((a8_fixes[num_a8_fixes].section != section)
5086 || (a8_fixes[num_a8_fixes].offset != i))
5087 {
5088 free (stub_name);
5089 stub_name = NULL;
5090 *stub_changed_p = TRUE;
5091 }
5092 }
5093
5094 if (!stub_name)
5095 {
21d799b5 5096 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5097 if (stub_name != NULL)
5098 sprintf (stub_name, "%x:%x", section->id, i);
5099 }
48229727 5100
99059e56
RM		 5101 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5102 a8_fixes[num_a8_fixes].section = section;
5103 a8_fixes[num_a8_fixes].offset = i;
5104 a8_fixes[num_a8_fixes].addend = offset;
5105 a8_fixes[num_a8_fixes].orig_insn = insn;
5106 a8_fixes[num_a8_fixes].stub_name = stub_name;
5107 a8_fixes[num_a8_fixes].stub_type = stub_type;
5108 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5109 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5110
99059e56
RM		 5111 num_a8_fixes++;
5112 }
5113 }
5114 }
48229727 5115
99059e56
RM		 5116 i += insn_32bit ? 4 : 2;
5117 last_was_32bit = insn_32bit;
48229727 5118 last_was_branch = is_32bit_branch;
99059e56
RM		 5119 }
5120 }
48229727
JB		 5121
5122 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5123 free (contents);
48229727 5124 }
fe33d2fa 5125
48229727
JB		 5126 *a8_fixes_p = a8_fixes;
5127 *num_a8_fixes_p = num_a8_fixes;
5128 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5129
81694485 5130 return FALSE;
48229727
JB		 5131}
5132
906e58ca
NC		 5133/* Determine and set the size of the stub section for a final link.
5134
5135 The basic idea here is to examine all the relocations looking for
5136 PC-relative calls to a target that is unreachable with a "bl"
5137 instruction. */
5138
5139bfd_boolean
5140elf32_arm_size_stubs (bfd *output_bfd,
5141 bfd *stub_bfd,
5142 struct bfd_link_info *info,
5143 bfd_signed_vma group_size,
7a89b94e
NC		 5144 asection * (*add_stub_section) (const char *, asection *,
5145 unsigned int),
906e58ca
NC		 5146 void (*layout_sections_again) (void))
5147{
5148 bfd_size_type stub_group_size;
07d72278 5149 bfd_boolean stubs_always_after_branch;
906e58ca 5150 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 5151 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 5152 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 5153 struct a8_erratum_reloc *a8_relocs = NULL;
5154 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
5155
4dfe6ac6
NC		 5156 if (htab == NULL)
5157 return FALSE;
5158
48229727
JB		 5159 if (htab->fix_cortex_a8)
5160 {
21d799b5 5161 a8_fixes = (struct a8_erratum_fix *)
99059e56 5162 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 5163 a8_relocs = (struct a8_erratum_reloc *)
99059e56 5164 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 5165 }
906e58ca
NC		 5166
5167 /* Propagate mach to stub bfd, because it may not have been
5168 finalized when we created stub_bfd. */
5169 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
5170 bfd_get_mach (output_bfd));
5171
5172 /* Stash our params away. */
5173 htab->stub_bfd = stub_bfd;
5174 htab->add_stub_section = add_stub_section;
5175 htab->layout_sections_again = layout_sections_again;
07d72278 5176 stubs_always_after_branch = group_size < 0;
48229727
JB		 5177
5178 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5179 as the first half of a 32-bit branch straddling two 4K pages. This is a
5180 crude way of enforcing that. */
5181 if (htab->fix_cortex_a8)
5182 stubs_always_after_branch = 1;
5183
906e58ca
NC		 5184 if (group_size < 0)
5185 stub_group_size = -group_size;
5186 else
5187 stub_group_size = group_size;
5188
5189 if (stub_group_size == 1)
5190 {
5191 /* Default values. */
5192 /* Thumb branch range is +-4MB has to be used as the default
5193 maximum size (a given section can contain both ARM and Thumb
5194 code, so the worst case has to be taken into account).
5195
5196 This value is 24K less than that, which allows for 2025
5197 12-byte stubs. If we exceed that, then we will fail to link.
5198 The user will have to relink with an explicit group size
5199 option. */
5200 stub_group_size = 4170000;
5201 }
5202
07d72278 5203 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 5204
3ae046cc
NS		 5205 /* If we're applying the cortex A8 fix, we need to determine the
5206 program header size now, because we cannot change it later --
5207 that could alter section placements. Notice the A8 erratum fix
5208 ends up requiring the section addresses to remain unchanged
5209 modulo the page size. That's something we cannot represent
5210 inside BFD, and we don't want to force the section alignment to
5211 be the page size. */
5212 if (htab->fix_cortex_a8)
5213 (*htab->layout_sections_again) ();
5214
906e58ca
NC		 5215 while (1)
5216 {
5217 bfd *input_bfd;
5218 unsigned int bfd_indx;
5219 asection *stub_sec;
eb7c4339
NS		 5220 bfd_boolean stub_changed = FALSE;
5221 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 5222
48229727 5223 num_a8_fixes = 0;
906e58ca
NC		 5224 for (input_bfd = info->input_bfds, bfd_indx = 0;
5225 input_bfd != NULL;
c72f2fb2 5226 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 5227 {
5228 Elf_Internal_Shdr *symtab_hdr;
5229 asection *section;
5230 Elf_Internal_Sym *local_syms = NULL;
5231
99059e56
RM		 5232 if (!is_arm_elf (input_bfd))
5233 continue;
adbcc655 5234
48229727
JB		 5235 num_a8_relocs = 0;
5236
906e58ca
NC		 5237 /* We'll need the symbol table in a second. */
5238 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5239 if (symtab_hdr->sh_info == 0)
5240 continue;
5241
5242 /* Walk over each section attached to the input bfd. */
5243 for (section = input_bfd->sections;
5244 section != NULL;
5245 section = section->next)
5246 {
5247 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
5248
5249 /* If there aren't any relocs, then there's nothing more
5250 to do. */
5251 if ((section->flags & SEC_RELOC) == 0
5252 || section->reloc_count == 0
5253 || (section->flags & SEC_CODE) == 0)
5254 continue;
5255
5256 /* If this section is a link-once section that will be
5257 discarded, then don't create any stubs. */
5258 if (section->output_section == NULL
5259 || section->output_section->owner != output_bfd)
5260 continue;
5261
5262 /* Get the relocs. */
5263 internal_relocs
5264 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
5265 NULL, info->keep_memory);
5266 if (internal_relocs == NULL)
5267 goto error_ret_free_local;
5268
5269 /* Now examine each relocation. */
5270 irela = internal_relocs;
5271 irelaend = irela + section->reloc_count;
5272 for (; irela < irelaend; irela++)
5273 {
5274 unsigned int r_type, r_indx;
5275 enum elf32_arm_stub_type stub_type;
5276 struct elf32_arm_stub_hash_entry *stub_entry;
5277 asection *sym_sec;
5278 bfd_vma sym_value;
5279 bfd_vma destination;
5280 struct elf32_arm_link_hash_entry *hash;
7413f23f 5281 const char *sym_name;
906e58ca
NC		 5282 char *stub_name;
5283 const asection *id_sec;
34e77a92 5284 unsigned char st_type;
35fc36a8 5285 enum arm_st_branch_type branch_type;
48229727 5286 bfd_boolean created_stub = FALSE;
906e58ca
NC		 5287
5288 r_type = ELF32_R_TYPE (irela->r_info);
5289 r_indx = ELF32_R_SYM (irela->r_info);
5290
5291 if (r_type >= (unsigned int) R_ARM_max)
5292 {
5293 bfd_set_error (bfd_error_bad_value);
5294 error_ret_free_internal:
5295 if (elf_section_data (section)->relocs == NULL)
5296 free (internal_relocs);
15dd01b1
TP		 5297 /* Fall through. */
5298 error_ret_free_local:
5299 if (local_syms != NULL
5300 && (symtab_hdr->contents
5301 != (unsigned char *) local_syms))
5302 free (local_syms);
5303 return FALSE;
906e58ca 5304 }
b38cadfb 5305
0855e32b
NS		 5306 hash = NULL;
5307 if (r_indx >= symtab_hdr->sh_info)
5308 hash = elf32_arm_hash_entry
5309 (elf_sym_hashes (input_bfd)
5310 [r_indx - symtab_hdr->sh_info]);
b38cadfb 5311
0855e32b
NS		 5312 /* Only look for stubs on branch instructions, or
5313 non-relaxed TLSCALL */
906e58ca 5314 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 5315 && (r_type != (unsigned int) R_ARM_THM_CALL)
5316 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 5317 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
5318 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 5319 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 5320 && (r_type != (unsigned int) R_ARM_PLT32)
5321 && !((r_type == (unsigned int) R_ARM_TLS_CALL
5322 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5323 && r_type == elf32_arm_tls_transition
5324 (info, r_type, &hash->root)
5325 && ((hash ? hash->tls_type
5326 : (elf32_arm_local_got_tls_type
5327 (input_bfd)[r_indx]))
5328 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 5329 continue;
5330
5331 /* Now determine the call target, its name, value,
5332 section. */
5333 sym_sec = NULL;
5334 sym_value = 0;
5335 destination = 0;
7413f23f 5336 sym_name = NULL;
b38cadfb 5337
0855e32b
NS		 5338 if (r_type == (unsigned int) R_ARM_TLS_CALL
5339 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5340 {
5341 /* A non-relaxed TLS call. The target is the
5342 plt-resident trampoline and nothing to do
5343 with the symbol. */
5344 BFD_ASSERT (htab->tls_trampoline > 0);
5345 sym_sec = htab->root.splt;
5346 sym_value = htab->tls_trampoline;
5347 hash = 0;
34e77a92 5348 st_type = STT_FUNC;
35fc36a8 5349 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 5350 }
5351 else if (!hash)
906e58ca
NC		 5352 {
5353 /* It's a local symbol. */
5354 Elf_Internal_Sym *sym;
906e58ca
NC		 5355
5356 if (local_syms == NULL)
5357 {
5358 local_syms
5359 = (Elf_Internal_Sym *) symtab_hdr->contents;
5360 if (local_syms == NULL)
5361 local_syms
5362 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5363 symtab_hdr->sh_info, 0,
5364 NULL, NULL, NULL);
5365 if (local_syms == NULL)
5366 goto error_ret_free_internal;
5367 }
5368
5369 sym = local_syms + r_indx;
f6d250ce
TS		 5370 if (sym->st_shndx == SHN_UNDEF)
5371 sym_sec = bfd_und_section_ptr;
5372 else if (sym->st_shndx == SHN_ABS)
5373 sym_sec = bfd_abs_section_ptr;
5374 else if (sym->st_shndx == SHN_COMMON)
5375 sym_sec = bfd_com_section_ptr;
5376 else
5377 sym_sec =
5378 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
5379
ffcb4889
NS		 5380 if (!sym_sec)
5381 /* This is an undefined symbol. It can never
6a631e86 5382 be resolved. */
ffcb4889 5383 continue;
fe33d2fa 5384
906e58ca
NC		 5385 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
5386 sym_value = sym->st_value;
5387 destination = (sym_value + irela->r_addend
5388 + sym_sec->output_offset
5389 + sym_sec->output_section->vma);
34e77a92 5390 st_type = ELF_ST_TYPE (sym->st_info);
35fc36a8 5391 branch_type = ARM_SYM_BRANCH_TYPE (sym);
7413f23f
DJ		 5392 sym_name
5393 = bfd_elf_string_from_elf_section (input_bfd,
5394 symtab_hdr->sh_link,
5395 sym->st_name);
906e58ca
NC		 5396 }
5397 else
5398 {
5399 /* It's an external symbol. */
906e58ca
NC		 5400 while (hash->root.root.type == bfd_link_hash_indirect
5401 || hash->root.root.type == bfd_link_hash_warning)
5402 hash = ((struct elf32_arm_link_hash_entry *)
5403 hash->root.root.u.i.link);
5404
5405 if (hash->root.root.type == bfd_link_hash_defined
5406 || hash->root.root.type == bfd_link_hash_defweak)
5407 {
5408 sym_sec = hash->root.root.u.def.section;
5409 sym_value = hash->root.root.u.def.value;
022f8312
CL		 5410
5411 struct elf32_arm_link_hash_table *globals =
5412 elf32_arm_hash_table (info);
5413
5414 /* For a destination in a shared library,
5415 use the PLT stub as target address to
5416 decide whether a branch stub is
5417 needed. */
4dfe6ac6 5418 if (globals != NULL
362d30a1 5419 && globals->root.splt != NULL
4dfe6ac6 5420 && hash != NULL
022f8312
CL		 5421 && hash->root.plt.offset != (bfd_vma) -1)
5422 {
362d30a1 5423 sym_sec = globals->root.splt;
022f8312
CL		 5424 sym_value = hash->root.plt.offset;
5425 if (sym_sec->output_section != NULL)
5426 destination = (sym_value
5427 + sym_sec->output_offset
5428 + sym_sec->output_section->vma);
5429 }
5430 else if (sym_sec->output_section != NULL)
906e58ca
NC		 5431 destination = (sym_value + irela->r_addend
5432 + sym_sec->output_offset
5433 + sym_sec->output_section->vma);
5434 }
69c5861e
CL		 5435 else if ((hash->root.root.type == bfd_link_hash_undefined)
5436 || (hash->root.root.type == bfd_link_hash_undefweak))
5437 {
5438 /* For a shared library, use the PLT stub as
5439 target address to decide whether a long
5440 branch stub is needed.
5441 For absolute code, they cannot be handled. */
5442 struct elf32_arm_link_hash_table *globals =
5443 elf32_arm_hash_table (info);
5444
4dfe6ac6 5445 if (globals != NULL
362d30a1 5446 && globals->root.splt != NULL
4dfe6ac6 5447 && hash != NULL
69c5861e
CL		 5448 && hash->root.plt.offset != (bfd_vma) -1)
5449 {
362d30a1 5450 sym_sec = globals->root.splt;
69c5861e
CL		 5451 sym_value = hash->root.plt.offset;
5452 if (sym_sec->output_section != NULL)
5453 destination = (sym_value
5454 + sym_sec->output_offset
5455 + sym_sec->output_section->vma);
5456 }
5457 else
5458 continue;
5459 }
906e58ca
NC		 5460 else
5461 {
5462 bfd_set_error (bfd_error_bad_value);
5463 goto error_ret_free_internal;
5464 }
34e77a92 5465 st_type = hash->root.type;
35fc36a8 5466 branch_type = hash->root.target_internal;
7413f23f 5467 sym_name = hash->root.root.root.string;
906e58ca
NC		 5468 }
5469
48229727 5470 do
7413f23f 5471 {
48229727
JB		 5472 /* Determine what (if any) linker stub is needed. */
5473 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 5474 st_type, &branch_type,
5475 hash, destination, sym_sec,
48229727
JB		 5476 input_bfd, sym_name);
5477 if (stub_type == arm_stub_none)
5478 break;
5479
5480 /* Support for grouping stub sections. */
5481 id_sec = htab->stub_group[section->id].link_sec;
5482
5483 /* Get the name of this stub. */
5484 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash,
fe33d2fa 5485 irela, stub_type);
48229727
JB		 5486 if (!stub_name)
5487 goto error_ret_free_internal;
5488
5489 /* We've either created a stub for this reloc already,
5490 or we are about to. */
5491 created_stub = TRUE;
5492
5493 stub_entry = arm_stub_hash_lookup
5494 (&htab->stub_hash_table, stub_name,
5495 FALSE, FALSE);
5496 if (stub_entry != NULL)
5497 {
5498 /* The proper stub has already been created. */
5499 free (stub_name);
eb7c4339 5500 stub_entry->target_value = sym_value;
48229727
JB		 5501 break;
5502 }
7413f23f 5503
48229727
JB		 5504 stub_entry = elf32_arm_add_stub (stub_name, section,
5505 htab);
5506 if (stub_entry == NULL)
5507 {
5508 free (stub_name);
5509 goto error_ret_free_internal;
5510 }
7413f23f 5511
99059e56
RM		 5512 stub_entry->target_value = sym_value;
5513 stub_entry->target_section = sym_sec;
5514 stub_entry->stub_type = stub_type;
5515 stub_entry->h = hash;
5516 stub_entry->branch_type = branch_type;
5517
5518 if (sym_name == NULL)
5519 sym_name = "unnamed";
5520 stub_entry->output_name = (char *)
5521 bfd_alloc (htab->stub_bfd,
5522 sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5523 + strlen (sym_name));
5524 if (stub_entry->output_name == NULL)
5525 {
5526 free (stub_name);
5527 goto error_ret_free_internal;
5528 }
5529
5530 /* For historical reasons, use the existing names for
5531 ARM-to-Thumb and Thumb-to-ARM stubs. */
5532 if ((r_type == (unsigned int) R_ARM_THM_CALL
c5423981
TG		 5533 || r_type == (unsigned int) R_ARM_THM_JUMP24
5534 || r_type == (unsigned int) R_ARM_THM_JUMP19)
35fc36a8 5535 && branch_type == ST_BRANCH_TO_ARM)
99059e56
RM		 5536 sprintf (stub_entry->output_name,
5537 THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5538 else if ((r_type == (unsigned int) R_ARM_CALL
35fc36a8
RS		 5539 || r_type == (unsigned int) R_ARM_JUMP24)
5540 && branch_type == ST_BRANCH_TO_THUMB)
99059e56
RM		 5541 sprintf (stub_entry->output_name,
5542 ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5543 else
5544 sprintf (stub_entry->output_name, STUB_ENTRY_NAME,
5545 sym_name);
5546
5547 stub_changed = TRUE;
5548 }
5549 while (0);
5550
5551 /* Look for relocations which might trigger Cortex-A8
5552 erratum. */
5553 if (htab->fix_cortex_a8
5554 && (r_type == (unsigned int) R_ARM_THM_JUMP24
5555 || r_type == (unsigned int) R_ARM_THM_JUMP19
5556 || r_type == (unsigned int) R_ARM_THM_CALL
5557 || r_type == (unsigned int) R_ARM_THM_XPC22))
5558 {
5559 bfd_vma from = section->output_section->vma
5560 + section->output_offset
5561 + irela->r_offset;
5562
5563 if ((from & 0xfff) == 0xffe)
5564 {
5565 /* Found a candidate. Note we haven't checked the
5566 destination is within 4K here: if we do so (and
5567 don't create an entry in a8_relocs) we can't tell
5568 that a branch should have been relocated when
5569 scanning later. */
5570 if (num_a8_relocs == a8_reloc_table_size)
5571 {
5572 a8_reloc_table_size *= 2;
5573 a8_relocs = (struct a8_erratum_reloc *)
5574 bfd_realloc (a8_relocs,
5575 sizeof (struct a8_erratum_reloc)
5576 * a8_reloc_table_size);
5577 }
5578
5579 a8_relocs[num_a8_relocs].from = from;
5580 a8_relocs[num_a8_relocs].destination = destination;
5581 a8_relocs[num_a8_relocs].r_type = r_type;
5582 a8_relocs[num_a8_relocs].branch_type = branch_type;
5583 a8_relocs[num_a8_relocs].sym_name = sym_name;
5584 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
5585 a8_relocs[num_a8_relocs].hash = hash;
5586
5587 num_a8_relocs++;
5588 }
5589 }
906e58ca
NC		 5590 }
5591
99059e56
RM		 5592 /* We're done with the internal relocs, free them. */
5593 if (elf_section_data (section)->relocs == NULL)
5594 free (internal_relocs);
5595 }
48229727 5596
99059e56 5597 if (htab->fix_cortex_a8)
48229727 5598 {
99059e56
RM		 5599 /* Sort relocs which might apply to Cortex-A8 erratum. */
5600 qsort (a8_relocs, num_a8_relocs,
eb7c4339 5601 sizeof (struct a8_erratum_reloc),
99059e56 5602 &a8_reloc_compare);
48229727 5603
99059e56
RM		 5604 /* Scan for branches which might trigger Cortex-A8 erratum. */
5605 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 5606 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 5607 a8_relocs, num_a8_relocs,
5608 prev_num_a8_fixes, &stub_changed)
5609 != 0)
48229727 5610 goto error_ret_free_local;
5e681ec4 5611 }
5e681ec4
PB		 5612 }
5613
eb7c4339 5614 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 5615 stub_changed = TRUE;
48229727 5616
906e58ca
NC		 5617 if (!stub_changed)
5618 break;
5e681ec4 5619
906e58ca
NC		 5620 /* OK, we've added some stubs. Find out the new size of the
5621 stub sections. */
5622 for (stub_sec = htab->stub_bfd->sections;
5623 stub_sec != NULL;
5624 stub_sec = stub_sec->next)
3e6b1042
DJ		 5625 {
5626 /* Ignore non-stub sections. */
5627 if (!strstr (stub_sec->name, STUB_SUFFIX))
5628 continue;
5629
5630 stub_sec->size = 0;
5631 }
b34b2d70 5632
906e58ca
NC		 5633 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
5634
48229727
JB		 5635 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5636 if (htab->fix_cortex_a8)
99059e56
RM		 5637 for (i = 0; i < num_a8_fixes; i++)
5638 {
48229727
JB		 5639 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
5640 a8_fixes[i].section, htab);
5641
5642 if (stub_sec == NULL)
5643 goto error_ret_free_local;
5644
99059e56
RM		 5645 stub_sec->size
5646 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
5647 NULL);
5648 }
48229727
JB		 5649
5650
906e58ca
NC		 5651 /* Ask the linker to do its stuff. */
5652 (*htab->layout_sections_again) ();
ba93b8ac
DJ		 5653 }
5654
48229727
JB		 5655 /* Add stubs for Cortex-A8 erratum fixes now. */
5656 if (htab->fix_cortex_a8)
5657 {
5658 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 5659 {
5660 struct elf32_arm_stub_hash_entry *stub_entry;
5661 char *stub_name = a8_fixes[i].stub_name;
5662 asection *section = a8_fixes[i].section;
5663 unsigned int section_id = a8_fixes[i].section->id;
5664 asection *link_sec = htab->stub_group[section_id].link_sec;
5665 asection *stub_sec = htab->stub_group[section_id].stub_sec;
5666 const insn_sequence *template_sequence;
5667 int template_size, size = 0;
5668
5669 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
5670 TRUE, FALSE);
5671 if (stub_entry == NULL)
5672 {
5673 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
5674 section->owner,
5675 stub_name);
5676 return FALSE;
5677 }
5678
5679 stub_entry->stub_sec = stub_sec;
5680 stub_entry->stub_offset = 0;
5681 stub_entry->id_sec = link_sec;
5682 stub_entry->stub_type = a8_fixes[i].stub_type;
5683 stub_entry->target_section = a8_fixes[i].section;
5684 stub_entry->target_value = a8_fixes[i].offset;
5685 stub_entry->target_addend = a8_fixes[i].addend;
5686 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 5687 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 5688
99059e56
RM		 5689 size = find_stub_size_and_template (a8_fixes[i].stub_type,
5690 &template_sequence,
5691 &template_size);
48229727 5692
99059e56
RM		 5693 stub_entry->stub_size = size;
5694 stub_entry->stub_template = template_sequence;
5695 stub_entry->stub_template_size = template_size;
5696 }
48229727
JB		 5697
5698 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 5699 elf32_arm_write_section(). */
48229727
JB		 5700 htab->a8_erratum_fixes = a8_fixes;
5701 htab->num_a8_erratum_fixes = num_a8_fixes;
5702 }
5703 else
5704 {
5705 htab->a8_erratum_fixes = NULL;
5706 htab->num_a8_erratum_fixes = 0;
5707 }
906e58ca 5708 return TRUE;
5e681ec4
PB		 5709}
5710
906e58ca
NC		 5711/* Build all the stubs associated with the current output file. The
5712 stubs are kept in a hash table attached to the main linker hash
5713 table. We also set up the .plt entries for statically linked PIC
5714 functions here. This function is called via arm_elf_finish in the
5715 linker. */
252b5132 5716
906e58ca
NC		 5717bfd_boolean
5718elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 5719{
906e58ca
NC		 5720 asection *stub_sec;
5721 struct bfd_hash_table *table;
5722 struct elf32_arm_link_hash_table *htab;
252b5132 5723
906e58ca 5724 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5725 if (htab == NULL)
5726 return FALSE;
252b5132 5727
906e58ca
NC		 5728 for (stub_sec = htab->stub_bfd->sections;
5729 stub_sec != NULL;
5730 stub_sec = stub_sec->next)
252b5132 5731 {
906e58ca
NC		 5732 bfd_size_type size;
5733
8029a119 5734 /* Ignore non-stub sections. */
906e58ca
NC		 5735 if (!strstr (stub_sec->name, STUB_SUFFIX))
5736 continue;
5737
5738 /* Allocate memory to hold the linker stubs. */
5739 size = stub_sec->size;
21d799b5 5740 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 5741 if (stub_sec->contents == NULL && size != 0)
5742 return FALSE;
5743 stub_sec->size = 0;
252b5132
RH		 5744 }
5745
906e58ca
NC		 5746 /* Build the stubs as directed by the stub hash table. */
5747 table = &htab->stub_hash_table;
5748 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 5749 if (htab->fix_cortex_a8)
5750 {
5751 /* Place the cortex a8 stubs last. */
5752 htab->fix_cortex_a8 = -1;
5753 bfd_hash_traverse (table, arm_build_one_stub, info);
5754 }
252b5132 5755
906e58ca 5756 return TRUE;
252b5132
RH		 5757}
5758
9b485d32
NC		 5759/* Locate the Thumb encoded calling stub for NAME. */
5760
252b5132 5761static struct elf_link_hash_entry *
57e8b36a
NC		 5762find_thumb_glue (struct bfd_link_info *link_info,
5763 const char *name,
f2a9dd69 5764 char **error_message)
252b5132
RH		 5765{
5766 char *tmp_name;
5767 struct elf_link_hash_entry *hash;
5768 struct elf32_arm_link_hash_table *hash_table;
5769
5770 /* We need a pointer to the armelf specific hash table. */
5771 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5772 if (hash_table == NULL)
5773 return NULL;
252b5132 5774
21d799b5 5775 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5776 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5777
5778 BFD_ASSERT (tmp_name);
5779
5780 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
5781
5782 hash = elf_link_hash_lookup
b34976b6 5783 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5784
b1657152
AM		 5785 if (hash == NULL
5786 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
5787 tmp_name, name) == -1)
5788 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5789
5790 free (tmp_name);
5791
5792 return hash;
5793}
5794
9b485d32
NC		 5795/* Locate the ARM encoded calling stub for NAME. */
5796
252b5132 5797static struct elf_link_hash_entry *
57e8b36a
NC		 5798find_arm_glue (struct bfd_link_info *link_info,
5799 const char *name,
f2a9dd69 5800 char **error_message)
252b5132
RH		 5801{
5802 char *tmp_name;
5803 struct elf_link_hash_entry *myh;
5804 struct elf32_arm_link_hash_table *hash_table;
5805
5806 /* We need a pointer to the elfarm specific hash table. */
5807 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5808 if (hash_table == NULL)
5809 return NULL;
252b5132 5810
21d799b5 5811 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5812 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5813
5814 BFD_ASSERT (tmp_name);
5815
5816 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5817
5818 myh = elf_link_hash_lookup
b34976b6 5819 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5820
b1657152
AM		 5821 if (myh == NULL
5822 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
5823 tmp_name, name) == -1)
5824 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5825
5826 free (tmp_name);
5827
5828 return myh;
5829}
5830
8f6277f5 5831/* ARM->Thumb glue (static images):
252b5132
RH		 5832
5833 .arm
5834 __func_from_arm:
5835 ldr r12, __func_addr
5836 bx r12
5837 __func_addr:
906e58ca 5838 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 5839
26079076
PB		 5840 (v5t static images)
5841 .arm
5842 __func_from_arm:
5843 ldr pc, __func_addr
5844 __func_addr:
906e58ca 5845 .word func @ behave as if you saw a ARM_32 reloc.
26079076 5846
8f6277f5
PB		 5847 (relocatable images)
5848 .arm
5849 __func_from_arm:
5850 ldr r12, __func_offset
5851 add r12, r12, pc
5852 bx r12
5853 __func_offset:
8029a119 5854 .word func - . */
8f6277f5
PB		 5855
5856#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 5857static const insn32 a2t1_ldr_insn = 0xe59fc000;
5858static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
5859static const insn32 a2t3_func_addr_insn = 0x00000001;
5860
26079076
PB		 5861#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5862static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
5863static const insn32 a2t2v5_func_addr_insn = 0x00000001;
5864
8f6277f5
PB		 5865#define ARM2THUMB_PIC_GLUE_SIZE 16
5866static const insn32 a2t1p_ldr_insn = 0xe59fc004;
5867static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
5868static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
5869
9b485d32 5870/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 5871
8029a119
NC		 5872 .thumb .thumb
5873 .align 2 .align 2
5874 __func_from_thumb: __func_from_thumb:
5875 bx pc push {r6, lr}
5876 nop ldr r6, __func_addr
5877 .arm mov lr, pc
5878 b func bx r6
99059e56
RM		 5879 .arm
5880 ;; back_to_thumb
5881 ldmia r13! {r6, lr}
5882 bx lr
5883 __func_addr:
5884 .word func */
252b5132
RH		 5885
5886#define THUMB2ARM_GLUE_SIZE 8
5887static const insn16 t2a1_bx_pc_insn = 0x4778;
5888static const insn16 t2a2_noop_insn = 0x46c0;
5889static const insn32 t2a3_b_insn = 0xea000000;
5890
c7b8f16e 5891#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 5892#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
5893#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 5894
845b51d6
PB		 5895#define ARM_BX_VENEER_SIZE 12
5896static const insn32 armbx1_tst_insn = 0xe3100001;
5897static const insn32 armbx2_moveq_insn = 0x01a0f000;
5898static const insn32 armbx3_bx_insn = 0xe12fff10;
5899
7e392df6 5900#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 5901static void
5902arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 5903{
5904 asection * s;
8029a119 5905 bfd_byte * contents;
252b5132 5906
8029a119 5907 if (size == 0)
3e6b1042
DJ		 5908 {
5909 /* Do not include empty glue sections in the output. */
5910 if (abfd != NULL)
5911 {
3d4d4302 5912 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 5913 if (s != NULL)
5914 s->flags |= SEC_EXCLUDE;
5915 }
5916 return;
5917 }
252b5132 5918
8029a119 5919 BFD_ASSERT (abfd != NULL);
252b5132 5920
3d4d4302 5921 s = bfd_get_linker_section (abfd, name);
8029a119 5922 BFD_ASSERT (s != NULL);
252b5132 5923
21d799b5 5924 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 5925
8029a119
NC		 5926 BFD_ASSERT (s->size == size);
5927 s->contents = contents;
5928}
906e58ca 5929
8029a119
NC		 5930bfd_boolean
5931bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
5932{
5933 struct elf32_arm_link_hash_table * globals;
906e58ca 5934
8029a119
NC		 5935 globals = elf32_arm_hash_table (info);
5936 BFD_ASSERT (globals != NULL);
906e58ca 5937
8029a119
NC		 5938 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5939 globals->arm_glue_size,
5940 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 5941
8029a119
NC		 5942 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5943 globals->thumb_glue_size,
5944 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 5945
8029a119
NC		 5946 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5947 globals->vfp11_erratum_glue_size,
5948 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 5949
a504d23a
LA		 5950 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5951 globals->stm32l4xx_erratum_glue_size,
5952 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
5953
8029a119
NC		 5954 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5955 globals->bx_glue_size,
845b51d6
PB		 5956 ARM_BX_GLUE_SECTION_NAME);
5957
b34976b6 5958 return TRUE;
252b5132
RH		 5959}
5960
a4fd1a8e 5961/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 5962 returns the symbol identifying the stub. */
5963
a4fd1a8e 5964static struct elf_link_hash_entry *
57e8b36a
NC		 5965record_arm_to_thumb_glue (struct bfd_link_info * link_info,
5966 struct elf_link_hash_entry * h)
252b5132
RH		 5967{
5968 const char * name = h->root.root.string;
63b0f745 5969 asection * s;
252b5132
RH		 5970 char * tmp_name;
5971 struct elf_link_hash_entry * myh;
14a793b2 5972 struct bfd_link_hash_entry * bh;
252b5132 5973 struct elf32_arm_link_hash_table * globals;
dc810e39 5974 bfd_vma val;
2f475487 5975 bfd_size_type size;
252b5132
RH		 5976
5977 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 5978 BFD_ASSERT (globals != NULL);
5979 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
5980
3d4d4302 5981 s = bfd_get_linker_section
252b5132
RH		 5982 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
5983
252b5132
RH		 5984 BFD_ASSERT (s != NULL);
5985
21d799b5 5986 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5987 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5988
5989 BFD_ASSERT (tmp_name);
5990
5991 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5992
5993 myh = elf_link_hash_lookup
b34976b6 5994 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 5995
5996 if (myh != NULL)
5997 {
9b485d32 5998 /* We've already seen this guy. */
252b5132 5999 free (tmp_name);
a4fd1a8e 6000 return myh;
252b5132
RH		 6001 }
6002
57e8b36a
NC		 6003 /* The only trick here is using hash_table->arm_glue_size as the value.
6004 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6005 putting it. The +1 on the value marks that the stub has not been
6006 output yet - not that it is a Thumb function. */
14a793b2 6007 bh = NULL;
dc810e39
AM		 6008 val = globals->arm_glue_size + 1;
6009 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6010 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6011 NULL, TRUE, FALSE, &bh);
252b5132 6012
b7693d02
DJ		 6013 myh = (struct elf_link_hash_entry *) bh;
6014 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6015 myh->forced_local = 1;
6016
252b5132
RH		 6017 free (tmp_name);
6018
0e1862bb
L		 6019 if (bfd_link_pic (link_info)
6020 || globals->root.is_relocatable_executable
27e55c4d 6021 || globals->pic_veneer)
2f475487 6022 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6023 else if (globals->use_blx)
6024 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6025 else
2f475487
AM		 6026 size = ARM2THUMB_STATIC_GLUE_SIZE;
6027
6028 s->size += size;
6029 globals->arm_glue_size += size;
252b5132 6030
a4fd1a8e 6031 return myh;
252b5132
RH		 6032}
6033
845b51d6
PB		 6034/* Allocate space for ARMv4 BX veneers. */
6035
6036static void
6037record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6038{
6039 asection * s;
6040 struct elf32_arm_link_hash_table *globals;
6041 char *tmp_name;
6042 struct elf_link_hash_entry *myh;
6043 struct bfd_link_hash_entry *bh;
6044 bfd_vma val;
6045
6046 /* BX PC does not need a veneer. */
6047 if (reg == 15)
6048 return;
6049
6050 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 6051 BFD_ASSERT (globals != NULL);
6052 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6053
6054 /* Check if this veneer has already been allocated. */
6055 if (globals->bx_glue_offset[reg])
6056 return;
6057
3d4d4302 6058 s = bfd_get_linker_section
845b51d6
PB		 6059 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
6060
6061 BFD_ASSERT (s != NULL);
6062
6063 /* Add symbol for veneer. */
21d799b5
NC		 6064 tmp_name = (char *)
6065 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 6066
845b51d6 6067 BFD_ASSERT (tmp_name);
906e58ca 6068
845b51d6 6069 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 6070
845b51d6
PB		 6071 myh = elf_link_hash_lookup
6072 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6073
845b51d6 6074 BFD_ASSERT (myh == NULL);
906e58ca 6075
845b51d6
PB		 6076 bh = NULL;
6077 val = globals->bx_glue_size;
6078 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 6079 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6080 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 6081
6082 myh = (struct elf_link_hash_entry *) bh;
6083 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6084 myh->forced_local = 1;
6085
6086 s->size += ARM_BX_VENEER_SIZE;
6087 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
6088 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
6089}
6090
6091
c7b8f16e
JB		 6092/* Add an entry to the code/data map for section SEC. */
6093
6094static void
6095elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
6096{
6097 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
6098 unsigned int newidx;
906e58ca 6099
c7b8f16e
JB		 6100 if (sec_data->map == NULL)
6101 {
21d799b5 6102 sec_data->map = (elf32_arm_section_map *)
99059e56 6103 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 6104 sec_data->mapcount = 0;
6105 sec_data->mapsize = 1;
6106 }
906e58ca 6107
c7b8f16e 6108 newidx = sec_data->mapcount++;
906e58ca 6109
c7b8f16e
JB		 6110 if (sec_data->mapcount > sec_data->mapsize)
6111 {
6112 sec_data->mapsize *= 2;
21d799b5 6113 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 6114 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
6115 * sizeof (elf32_arm_section_map));
515ef31d
NC		 6116 }
6117
6118 if (sec_data->map)
6119 {
6120 sec_data->map[newidx].vma = vma;
6121 sec_data->map[newidx].type = type;
c7b8f16e 6122 }
c7b8f16e
JB		 6123}
6124
6125
6126/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6127 veneers are handled for now. */
6128
6129static bfd_vma
6130record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 6131 elf32_vfp11_erratum_list *branch,
6132 bfd *branch_bfd,
6133 asection *branch_sec,
6134 unsigned int offset)
c7b8f16e
JB		 6135{
6136 asection *s;
6137 struct elf32_arm_link_hash_table *hash_table;
6138 char *tmp_name;
6139 struct elf_link_hash_entry *myh;
6140 struct bfd_link_hash_entry *bh;
6141 bfd_vma val;
6142 struct _arm_elf_section_data *sec_data;
c7b8f16e 6143 elf32_vfp11_erratum_list *newerr;
906e58ca 6144
c7b8f16e 6145 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 6146 BFD_ASSERT (hash_table != NULL);
6147 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 6148
3d4d4302 6149 s = bfd_get_linker_section
c7b8f16e 6150 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 6151
c7b8f16e 6152 sec_data = elf32_arm_section_data (s);
906e58ca 6153
c7b8f16e 6154 BFD_ASSERT (s != NULL);
906e58ca 6155
21d799b5 6156 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 6157 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 6158
c7b8f16e 6159 BFD_ASSERT (tmp_name);
906e58ca 6160
c7b8f16e
JB		 6161 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
6162 hash_table->num_vfp11_fixes);
906e58ca 6163
c7b8f16e
JB		 6164 myh = elf_link_hash_lookup
6165 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6166
c7b8f16e 6167 BFD_ASSERT (myh == NULL);
906e58ca 6168
c7b8f16e
JB		 6169 bh = NULL;
6170 val = hash_table->vfp11_erratum_glue_size;
6171 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 6172 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6173 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 6174
6175 myh = (struct elf_link_hash_entry *) bh;
6176 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6177 myh->forced_local = 1;
6178
6179 /* Link veneer back to calling location. */
c7e2358a 6180 sec_data->erratumcount += 1;
21d799b5
NC		 6181 newerr = (elf32_vfp11_erratum_list *)
6182 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 6183
c7b8f16e
JB		 6184 newerr->type = VFP11_ERRATUM_ARM_VENEER;
6185 newerr->vma = -1;
6186 newerr->u.v.branch = branch;
6187 newerr->u.v.id = hash_table->num_vfp11_fixes;
6188 branch->u.b.veneer = newerr;
6189
6190 newerr->next = sec_data->erratumlist;
6191 sec_data->erratumlist = newerr;
6192
6193 /* A symbol for the return from the veneer. */
6194 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
6195 hash_table->num_vfp11_fixes);
6196
6197 myh = elf_link_hash_lookup
6198 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6199
c7b8f16e
JB		 6200 if (myh != NULL)
6201 abort ();
6202
6203 bh = NULL;
6204 val = offset + 4;
6205 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6206 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 6207
c7b8f16e
JB		 6208 myh = (struct elf_link_hash_entry *) bh;
6209 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6210 myh->forced_local = 1;
6211
6212 free (tmp_name);
906e58ca 6213
c7b8f16e
JB		 6214 /* Generate a mapping symbol for the veneer section, and explicitly add an
6215 entry for that symbol to the code/data map for the section. */
6216 if (hash_table->vfp11_erratum_glue_size == 0)
6217 {
6218 bh = NULL;
6219 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 6220 ever requires this erratum fix. */
c7b8f16e
JB		 6221 _bfd_generic_link_add_one_symbol (link_info,
6222 hash_table->bfd_of_glue_owner, "$a",
6223 BSF_LOCAL, s, 0, NULL,
99059e56 6224 TRUE, FALSE, &bh);
c7b8f16e
JB		 6225
6226 myh = (struct elf_link_hash_entry *) bh;
6227 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6228 myh->forced_local = 1;
906e58ca 6229
c7b8f16e 6230 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 6231 BFDs. We must make a note of this generated mapping symbol
6232 ourselves so that code byteswapping works properly in
6233 elf32_arm_write_section. */
c7b8f16e
JB		 6234 elf32_arm_section_map_add (s, 'a', 0);
6235 }
906e58ca 6236
c7b8f16e
JB		 6237 s->size += VFP11_ERRATUM_VENEER_SIZE;
6238 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
6239 hash_table->num_vfp11_fixes++;
906e58ca 6240
c7b8f16e
JB		 6241 /* The offset of the veneer. */
6242 return val;
6243}
6244
a504d23a
LA		 6245/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6246 veneers need to be handled because used only in Cortex-M. */
6247
6248static bfd_vma
6249record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
6250 elf32_stm32l4xx_erratum_list *branch,
6251 bfd *branch_bfd,
6252 asection *branch_sec,
6253 unsigned int offset,
6254 bfd_size_type veneer_size)
6255{
6256 asection *s;
6257 struct elf32_arm_link_hash_table *hash_table;
6258 char *tmp_name;
6259 struct elf_link_hash_entry *myh;
6260 struct bfd_link_hash_entry *bh;
6261 bfd_vma val;
6262 struct _arm_elf_section_data *sec_data;
6263 elf32_stm32l4xx_erratum_list *newerr;
6264
6265 hash_table = elf32_arm_hash_table (link_info);
6266 BFD_ASSERT (hash_table != NULL);
6267 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
6268
6269 s = bfd_get_linker_section
6270 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6271
6272 BFD_ASSERT (s != NULL);
6273
6274 sec_data = elf32_arm_section_data (s);
6275
6276 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
6277 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
6278
6279 BFD_ASSERT (tmp_name);
6280
6281 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
6282 hash_table->num_stm32l4xx_fixes);
6283
6284 myh = elf_link_hash_lookup
6285 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6286
6287 BFD_ASSERT (myh == NULL);
6288
6289 bh = NULL;
6290 val = hash_table->stm32l4xx_erratum_glue_size;
6291 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
6292 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6293 NULL, TRUE, FALSE, &bh);
6294
6295 myh = (struct elf_link_hash_entry *) bh;
6296 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6297 myh->forced_local = 1;
6298
6299 /* Link veneer back to calling location. */
6300 sec_data->stm32l4xx_erratumcount += 1;
6301 newerr = (elf32_stm32l4xx_erratum_list *)
6302 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
6303
6304 newerr->type = STM32L4XX_ERRATUM_VENEER;
6305 newerr->vma = -1;
6306 newerr->u.v.branch = branch;
6307 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
6308 branch->u.b.veneer = newerr;
6309
6310 newerr->next = sec_data->stm32l4xx_erratumlist;
6311 sec_data->stm32l4xx_erratumlist = newerr;
6312
6313 /* A symbol for the return from the veneer. */
6314 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
6315 hash_table->num_stm32l4xx_fixes);
6316
6317 myh = elf_link_hash_lookup
6318 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6319
6320 if (myh != NULL)
6321 abort ();
6322
6323 bh = NULL;
6324 val = offset + 4;
6325 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6326 branch_sec, val, NULL, TRUE, FALSE, &bh);
6327
6328 myh = (struct elf_link_hash_entry *) bh;
6329 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6330 myh->forced_local = 1;
6331
6332 free (tmp_name);
6333
6334 /* Generate a mapping symbol for the veneer section, and explicitly add an
6335 entry for that symbol to the code/data map for the section. */
6336 if (hash_table->stm32l4xx_erratum_glue_size == 0)
6337 {
6338 bh = NULL;
6339 /* Creates a THUMB symbol since there is no other choice. */
6340 _bfd_generic_link_add_one_symbol (link_info,
6341 hash_table->bfd_of_glue_owner, "$t",
6342 BSF_LOCAL, s, 0, NULL,
6343 TRUE, FALSE, &bh);
6344
6345 myh = (struct elf_link_hash_entry *) bh;
6346 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6347 myh->forced_local = 1;
6348
6349 /* The elf32_arm_init_maps function only cares about symbols from input
6350 BFDs. We must make a note of this generated mapping symbol
6351 ourselves so that code byteswapping works properly in
6352 elf32_arm_write_section. */
6353 elf32_arm_section_map_add (s, 't', 0);
6354 }
6355
6356 s->size += veneer_size;
6357 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
6358 hash_table->num_stm32l4xx_fixes++;
6359
6360 /* The offset of the veneer. */
6361 return val;
6362}
6363
8029a119 6364#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 6365 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6366 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 6367
6368/* Create a fake section for use by the ARM backend of the linker. */
6369
6370static bfd_boolean
6371arm_make_glue_section (bfd * abfd, const char * name)
6372{
6373 asection * sec;
6374
3d4d4302 6375 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 6376 if (sec != NULL)
6377 /* Already made. */
6378 return TRUE;
6379
3d4d4302 6380 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 6381
6382 if (sec == NULL
6383 || !bfd_set_section_alignment (abfd, sec, 2))
6384 return FALSE;
6385
6386 /* Set the gc mark to prevent the section from being removed by garbage
6387 collection, despite the fact that no relocs refer to this section. */
6388 sec->gc_mark = 1;
6389
6390 return TRUE;
6391}
6392
1db37fe6
YG		 6393/* Set size of .plt entries. This function is called from the
6394 linker scripts in ld/emultempl/{armelf}.em. */
6395
6396void
6397bfd_elf32_arm_use_long_plt (void)
6398{
6399 elf32_arm_use_long_plt_entry = TRUE;
6400}
6401
8afb0e02
NC		 6402/* Add the glue sections to ABFD. This function is called from the
6403 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 6404
b34976b6 6405bfd_boolean
57e8b36a
NC		 6406bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
6407 struct bfd_link_info *info)
252b5132 6408{
a504d23a
LA		 6409 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
6410 bfd_boolean dostm32l4xx = globals
6411 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
6412 bfd_boolean addglue;
6413
8afb0e02
NC		 6414 /* If we are only performing a partial
6415 link do not bother adding the glue. */
0e1862bb 6416 if (bfd_link_relocatable (info))
b34976b6 6417 return TRUE;
252b5132 6418
a504d23a 6419 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 6420 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
6421 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
6422 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 6423
6424 if (!dostm32l4xx)
6425 return addglue;
6426
6427 return addglue
6428 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 6429}
6430
6431/* Select a BFD to be used to hold the sections used by the glue code.
6432 This function is called from the linker scripts in ld/emultempl/
8029a119 6433 {armelf/pe}.em. */
8afb0e02 6434
b34976b6 6435bfd_boolean
57e8b36a 6436bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 6437{
6438 struct elf32_arm_link_hash_table *globals;
6439
6440 /* If we are only performing a partial link
6441 do not bother getting a bfd to hold the glue. */
0e1862bb 6442 if (bfd_link_relocatable (info))
b34976b6 6443 return TRUE;
8afb0e02 6444
b7693d02
DJ		 6445 /* Make sure we don't attach the glue sections to a dynamic object. */
6446 BFD_ASSERT (!(abfd->flags & DYNAMIC));
6447
8afb0e02 6448 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 6449 BFD_ASSERT (globals != NULL);
6450
6451 if (globals->bfd_of_glue_owner != NULL)
b34976b6 6452 return TRUE;
8afb0e02 6453
252b5132
RH		 6454 /* Save the bfd for later use. */
6455 globals->bfd_of_glue_owner = abfd;
cedb70c5 6456
b34976b6 6457 return TRUE;
252b5132
RH		 6458}
6459
906e58ca
NC		 6460static void
6461check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 6462{
2de70689
MGD		 6463 int cpu_arch;
6464
b38cadfb 6465 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 6466 Tag_CPU_arch);
6467
6468 if (globals->fix_arm1176)
6469 {
6470 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
6471 globals->use_blx = 1;
6472 }
6473 else
6474 {
6475 if (cpu_arch > TAG_CPU_ARCH_V4T)
6476 globals->use_blx = 1;
6477 }
39b41c9c
PB		 6478}
6479
b34976b6 6480bfd_boolean
57e8b36a 6481bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 6482 struct bfd_link_info *link_info)
252b5132
RH		 6483{
6484 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 6485 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 6486 Elf_Internal_Rela *irel, *irelend;
6487 bfd_byte *contents = NULL;
252b5132
RH		 6488
6489 asection *sec;
6490 struct elf32_arm_link_hash_table *globals;
6491
6492 /* If we are only performing a partial link do not bother
6493 to construct any glue. */
0e1862bb 6494 if (bfd_link_relocatable (link_info))
b34976b6 6495 return TRUE;
252b5132 6496
39ce1a6a
NC		 6497 /* Here we have a bfd that is to be included on the link. We have a
6498 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 6499 globals = elf32_arm_hash_table (link_info);
252b5132 6500 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 6501
6502 check_use_blx (globals);
252b5132 6503
d504ffc8 6504 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 6505 {
d003868e
AM		 6506 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
6507 abfd);
e489d0ae
PB		 6508 return FALSE;
6509 }
f21f3fe0 6510
39ce1a6a
NC		 6511 /* PR 5398: If we have not decided to include any loadable sections in
6512 the output then we will not have a glue owner bfd. This is OK, it
6513 just means that there is nothing else for us to do here. */
6514 if (globals->bfd_of_glue_owner == NULL)
6515 return TRUE;
6516
252b5132
RH		 6517 /* Rummage around all the relocs and map the glue vectors. */
6518 sec = abfd->sections;
6519
6520 if (sec == NULL)
b34976b6 6521 return TRUE;
252b5132
RH		 6522
6523 for (; sec != NULL; sec = sec->next)
6524 {
6525 if (sec->reloc_count == 0)
6526 continue;
6527
2f475487
AM		 6528 if ((sec->flags & SEC_EXCLUDE) != 0)
6529 continue;
6530
0ffa91dd 6531 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 6532
9b485d32 6533 /* Load the relocs. */
6cdc0ccc 6534 internal_relocs
906e58ca 6535 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 6536
6cdc0ccc
AM		 6537 if (internal_relocs == NULL)
6538 goto error_return;
252b5132 6539
6cdc0ccc
AM		 6540 irelend = internal_relocs + sec->reloc_count;
6541 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 6542 {
6543 long r_type;
6544 unsigned long r_index;
252b5132
RH		 6545
6546 struct elf_link_hash_entry *h;
6547
6548 r_type = ELF32_R_TYPE (irel->r_info);
6549 r_index = ELF32_R_SYM (irel->r_info);
6550
9b485d32 6551 /* These are the only relocation types we care about. */
ba96a88f 6552 if ( r_type != R_ARM_PC24
845b51d6 6553 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 6554 continue;
6555
6556 /* Get the section contents if we haven't done so already. */
6557 if (contents == NULL)
6558 {
6559 /* Get cached copy if it exists. */
6560 if (elf_section_data (sec)->this_hdr.contents != NULL)
6561 contents = elf_section_data (sec)->this_hdr.contents;
6562 else
6563 {
6564 /* Go get them off disk. */
57e8b36a 6565 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 6566 goto error_return;
6567 }
6568 }
6569
845b51d6
PB		 6570 if (r_type == R_ARM_V4BX)
6571 {
6572 int reg;
6573
6574 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
6575 record_arm_bx_glue (link_info, reg);
6576 continue;
6577 }
6578
a7c10850 6579 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 6580 h = NULL;
6581
9b485d32 6582 /* We don't care about local symbols. */
252b5132
RH		 6583 if (r_index < symtab_hdr->sh_info)
6584 continue;
6585
9b485d32 6586 /* This is an external symbol. */
252b5132
RH		 6587 r_index -= symtab_hdr->sh_info;
6588 h = (struct elf_link_hash_entry *)
6589 elf_sym_hashes (abfd)[r_index];
6590
6591 /* If the relocation is against a static symbol it must be within
6592 the current section and so cannot be a cross ARM/Thumb relocation. */
6593 if (h == NULL)
6594 continue;
6595
d504ffc8
DJ		 6596 /* If the call will go through a PLT entry then we do not need
6597 glue. */
362d30a1 6598 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 6599 continue;
6600
252b5132
RH		 6601 switch (r_type)
6602 {
6603 case R_ARM_PC24:
6604 /* This one is a call from arm code. We need to look up
99059e56
RM		 6605 the target of the call. If it is a thumb target, we
6606 insert glue. */
35fc36a8 6607 if (h->target_internal == ST_BRANCH_TO_THUMB)
252b5132
RH		 6608 record_arm_to_thumb_glue (link_info, h);
6609 break;
6610
252b5132 6611 default:
c6596c5e 6612 abort ();
252b5132
RH		 6613 }
6614 }
6cdc0ccc
AM		 6615
6616 if (contents != NULL
6617 && elf_section_data (sec)->this_hdr.contents != contents)
6618 free (contents);
6619 contents = NULL;
6620
6621 if (internal_relocs != NULL
6622 && elf_section_data (sec)->relocs != internal_relocs)
6623 free (internal_relocs);
6624 internal_relocs = NULL;
252b5132
RH		 6625 }
6626
b34976b6 6627 return TRUE;
9a5aca8c 6628
252b5132 6629error_return:
6cdc0ccc
AM		 6630 if (contents != NULL
6631 && elf_section_data (sec)->this_hdr.contents != contents)
6632 free (contents);
6633 if (internal_relocs != NULL
6634 && elf_section_data (sec)->relocs != internal_relocs)
6635 free (internal_relocs);
9a5aca8c 6636
b34976b6 6637 return FALSE;
252b5132 6638}
7e392df6 6639#endif
252b5132 6640
eb043451 6641
c7b8f16e
JB		 6642/* Initialise maps of ARM/Thumb/data for input BFDs. */
6643
6644void
6645bfd_elf32_arm_init_maps (bfd *abfd)
6646{
6647 Elf_Internal_Sym *isymbuf;
6648 Elf_Internal_Shdr *hdr;
6649 unsigned int i, localsyms;
6650
af1f4419
NC		 6651 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6652 if (! is_arm_elf (abfd))
6653 return;
6654
c7b8f16e
JB		 6655 if ((abfd->flags & DYNAMIC) != 0)
6656 return;
6657
0ffa91dd 6658 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 6659 localsyms = hdr->sh_info;
6660
6661 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6662 should contain the number of local symbols, which should come before any
6663 global symbols. Mapping symbols are always local. */
6664 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
6665 NULL);
6666
6667 /* No internal symbols read? Skip this BFD. */
6668 if (isymbuf == NULL)
6669 return;
6670
6671 for (i = 0; i < localsyms; i++)
6672 {
6673 Elf_Internal_Sym *isym = &isymbuf[i];
6674 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
6675 const char *name;
906e58ca 6676
c7b8f16e 6677 if (sec != NULL
99059e56
RM		 6678 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
6679 {
6680 name = bfd_elf_string_from_elf_section (abfd,
6681 hdr->sh_link, isym->st_name);
906e58ca 6682
99059e56 6683 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 6684 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 6685 elf32_arm_section_map_add (sec, name[1], isym->st_value);
6686 }
c7b8f16e
JB		 6687 }
6688}
6689
6690
48229727
JB		 6691/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6692 say what they wanted. */
6693
6694void
6695bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
6696{
6697 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6698 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6699
4dfe6ac6
NC		 6700 if (globals == NULL)
6701 return;
6702
48229727
JB		 6703 if (globals->fix_cortex_a8 == -1)
6704 {
6705 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6706 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
6707 && (out_attr[Tag_CPU_arch_profile].i == 'A'
6708 || out_attr[Tag_CPU_arch_profile].i == 0))
6709 globals->fix_cortex_a8 = 1;
6710 else
6711 globals->fix_cortex_a8 = 0;
6712 }
6713}
6714
6715
c7b8f16e
JB		 6716void
6717bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
6718{
6719 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 6720 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 6721
4dfe6ac6
NC		 6722 if (globals == NULL)
6723 return;
c7b8f16e
JB		 6724 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6725 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
6726 {
6727 switch (globals->vfp11_fix)
99059e56
RM		 6728 {
6729 case BFD_ARM_VFP11_FIX_DEFAULT:
6730 case BFD_ARM_VFP11_FIX_NONE:
6731 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6732 break;
6733
6734 default:
6735 /* Give a warning, but do as the user requests anyway. */
6736 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
6737 "workaround is not necessary for target architecture"), obfd);
6738 }
c7b8f16e
JB		 6739 }
6740 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
6741 /* For earlier architectures, we might need the workaround, but do not
6742 enable it by default. If users is running with broken hardware, they
6743 must enable the erratum fix explicitly. */
6744 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6745}
6746
a504d23a
LA		 6747void
6748bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
6749{
6750 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6751 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6752
6753 if (globals == NULL)
6754 return;
6755
6756 /* We assume only Cortex-M4 may require the fix. */
6757 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
6758 || out_attr[Tag_CPU_arch_profile].i != 'M')
6759 {
6760 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
6761 /* Give a warning, but do as the user requests anyway. */
6762 (*_bfd_error_handler)
6763 (_("%B: warning: selected STM32L4XX erratum "
6764 "workaround is not necessary for target architecture"), obfd);
6765 }
6766}
c7b8f16e 6767
906e58ca
NC		 6768enum bfd_arm_vfp11_pipe
6769{
c7b8f16e
JB		 6770 VFP11_FMAC,
6771 VFP11_LS,
6772 VFP11_DS,
6773 VFP11_BAD
6774};
6775
6776/* Return a VFP register number. This is encoded as RX:X for single-precision
6777 registers, or X:RX for double-precision registers, where RX is the group of
6778 four bits in the instruction encoding and X is the single extension bit.
6779 RX and X fields are specified using their lowest (starting) bit. The return
6780 value is:
6781
6782 0...31: single-precision registers s0...s31
6783 32...63: double-precision registers d0...d31.
906e58ca 6784
c7b8f16e
JB		 6785 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6786 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 6787
c7b8f16e
JB		 6788static unsigned int
6789bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 6790 unsigned int x)
c7b8f16e
JB		 6791{
6792 if (is_double)
6793 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
6794 else
6795 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
6796}
6797
6798/* Set bits in *WMASK according to a register number REG as encoded by
6799 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6800
6801static void
6802bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
6803{
6804 if (reg < 32)
6805 *wmask |= 1 << reg;
6806 else if (reg < 48)
6807 *wmask |= 3 << ((reg - 32) * 2);
6808}
6809
6810/* Return TRUE if WMASK overwrites anything in REGS. */
6811
6812static bfd_boolean
6813bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
6814{
6815 int i;
906e58ca 6816
c7b8f16e
JB		 6817 for (i = 0; i < numregs; i++)
6818 {
6819 unsigned int reg = regs[i];
6820
6821 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 6822 return TRUE;
906e58ca 6823
c7b8f16e
JB		 6824 reg -= 32;
6825
6826 if (reg >= 16)
99059e56 6827 continue;
906e58ca 6828
c7b8f16e 6829 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 6830 return TRUE;
c7b8f16e 6831 }
906e58ca 6832
c7b8f16e
JB		 6833 return FALSE;
6834}
6835
6836/* In this function, we're interested in two things: finding input registers
6837 for VFP data-processing instructions, and finding the set of registers which
6838 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6839 hold the written set, so FLDM etc. are easy to deal with (we're only
6840 interested in 32 SP registers or 16 dp registers, due to the VFP version
6841 implemented by the chip in question). DP registers are marked by setting
6842 both SP registers in the write mask). */
6843
6844static enum bfd_arm_vfp11_pipe
6845bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 6846 int *numregs)
c7b8f16e 6847{
91d6fa6a 6848 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 6849 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
6850
6851 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
6852 {
6853 unsigned int pqrs;
6854 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6855 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
6856
6857 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 6858 | ((insn & 0x00300000) >> 19)
6859 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 6860
6861 switch (pqrs)
99059e56
RM		 6862 {
6863 case 0: /* fmac[sd]. */
6864 case 1: /* fnmac[sd]. */
6865 case 2: /* fmsc[sd]. */
6866 case 3: /* fnmsc[sd]. */
6867 vpipe = VFP11_FMAC;
6868 bfd_arm_vfp11_write_mask (destmask, fd);
6869 regs[0] = fd;
6870 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6871 regs[2] = fm;
6872 *numregs = 3;
6873 break;
6874
6875 case 4: /* fmul[sd]. */
6876 case 5: /* fnmul[sd]. */
6877 case 6: /* fadd[sd]. */
6878 case 7: /* fsub[sd]. */
6879 vpipe = VFP11_FMAC;
6880 goto vfp_binop;
6881
6882 case 8: /* fdiv[sd]. */
6883 vpipe = VFP11_DS;
6884 vfp_binop:
6885 bfd_arm_vfp11_write_mask (destmask, fd);
6886 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6887 regs[1] = fm;
6888 *numregs = 2;
6889 break;
6890
6891 case 15: /* extended opcode. */
6892 {
6893 unsigned int extn = ((insn >> 15) & 0x1e)
6894 | ((insn >> 7) & 1);
6895
6896 switch (extn)
6897 {
6898 case 0: /* fcpy[sd]. */
6899 case 1: /* fabs[sd]. */
6900 case 2: /* fneg[sd]. */
6901 case 8: /* fcmp[sd]. */
6902 case 9: /* fcmpe[sd]. */
6903 case 10: /* fcmpz[sd]. */
6904 case 11: /* fcmpez[sd]. */
6905 case 16: /* fuito[sd]. */
6906 case 17: /* fsito[sd]. */
6907 case 24: /* ftoui[sd]. */
6908 case 25: /* ftouiz[sd]. */
6909 case 26: /* ftosi[sd]. */
6910 case 27: /* ftosiz[sd]. */
6911 /* These instructions will not bounce due to underflow. */
6912 *numregs = 0;
6913 vpipe = VFP11_FMAC;
6914 break;
6915
6916 case 3: /* fsqrt[sd]. */
6917 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6918 registers to cause the erratum in previous instructions. */
6919 bfd_arm_vfp11_write_mask (destmask, fd);
6920 vpipe = VFP11_DS;
6921 break;
6922
6923 case 15: /* fcvt{ds,sd}. */
6924 {
6925 int rnum = 0;
6926
6927 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 6928
6929 /* Only FCVTSD can underflow. */
99059e56
RM		 6930 if ((insn & 0x100) != 0)
6931 regs[rnum++] = fm;
c7b8f16e 6932
99059e56 6933 *numregs = rnum;
c7b8f16e 6934
99059e56
RM		 6935 vpipe = VFP11_FMAC;
6936 }
6937 break;
c7b8f16e 6938
99059e56
RM		 6939 default:
6940 return VFP11_BAD;
6941 }
6942 }
6943 break;
c7b8f16e 6944
99059e56
RM		 6945 default:
6946 return VFP11_BAD;
6947 }
c7b8f16e
JB		 6948 }
6949 /* Two-register transfer. */
6950 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
6951 {
6952 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 6953
c7b8f16e
JB		 6954 if ((insn & 0x100000) == 0)
6955 {
99059e56
RM		 6956 if (is_double)
6957 bfd_arm_vfp11_write_mask (destmask, fm);
6958 else
6959 {
6960 bfd_arm_vfp11_write_mask (destmask, fm);
6961 bfd_arm_vfp11_write_mask (destmask, fm + 1);
6962 }
c7b8f16e
JB		 6963 }
6964
91d6fa6a 6965 vpipe = VFP11_LS;
c7b8f16e
JB		 6966 }
6967 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
6968 {
6969 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6970 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 6971
c7b8f16e 6972 switch (puw)
99059e56
RM		 6973 {
6974 case 0: /* Two-reg transfer. We should catch these above. */
6975 abort ();
906e58ca 6976
99059e56
RM		 6977 case 2: /* fldm[sdx]. */
6978 case 3:
6979 case 5:
6980 {
6981 unsigned int i, offset = insn & 0xff;
c7b8f16e 6982
99059e56
RM		 6983 if (is_double)
6984 offset >>= 1;
c7b8f16e 6985
99059e56
RM		 6986 for (i = fd; i < fd + offset; i++)
6987 bfd_arm_vfp11_write_mask (destmask, i);
6988 }
6989 break;
906e58ca 6990
99059e56
RM		 6991 case 4: /* fld[sd]. */
6992 case 6:
6993 bfd_arm_vfp11_write_mask (destmask, fd);
6994 break;
906e58ca 6995
99059e56
RM		 6996 default:
6997 return VFP11_BAD;
6998 }
c7b8f16e 6999
91d6fa6a 7000 vpipe = VFP11_LS;
c7b8f16e
JB		 7001 }
7002 /* Single-register transfer. Note L==0. */
7003 else if ((insn & 0x0f100e10) == 0x0e000a10)
7004 {
7005 unsigned int opcode = (insn >> 21) & 7;
7006 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
7007
7008 switch (opcode)
99059e56
RM		 7009 {
7010 case 0: /* fmsr/fmdlr. */
7011 case 1: /* fmdhr. */
7012 /* Mark fmdhr and fmdlr as writing to the whole of the DP
7013 destination register. I don't know if this is exactly right,
7014 but it is the conservative choice. */
7015 bfd_arm_vfp11_write_mask (destmask, fn);
7016 break;
7017
7018 case 7: /* fmxr. */
7019 break;
7020 }
c7b8f16e 7021
91d6fa6a 7022 vpipe = VFP11_LS;
c7b8f16e
JB		 7023 }
7024
91d6fa6a 7025 return vpipe;
c7b8f16e
JB		 7026}
7027
7028
7029static int elf32_arm_compare_mapping (const void * a, const void * b);
7030
7031
7032/* Look for potentially-troublesome code sequences which might trigger the
7033 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
7034 (available from ARM) for details of the erratum. A short version is
7035 described in ld.texinfo. */
7036
7037bfd_boolean
7038bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
7039{
7040 asection *sec;
7041 bfd_byte *contents = NULL;
7042 int state = 0;
7043 int regs[3], numregs = 0;
7044 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7045 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 7046
4dfe6ac6
NC		 7047 if (globals == NULL)
7048 return FALSE;
7049
c7b8f16e
JB		 7050 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
7051 The states transition as follows:
906e58ca 7052
c7b8f16e 7053 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 7054 A VFP FMAC-pipeline instruction has been seen. Fill
7055 regs[0]..regs[numregs-1] with its input operands. Remember this
7056 instruction in 'first_fmac'.
c7b8f16e
JB		 7057
7058 1 -> 2
99059e56
RM		 7059 Any instruction, except for a VFP instruction which overwrites
7060 regs[*].
906e58ca 7061
c7b8f16e
JB		 7062 1 -> 3 [ -> 0 ] or
7063 2 -> 3 [ -> 0 ]
99059e56
RM		 7064 A VFP instruction has been seen which overwrites any of regs[*].
7065 We must make a veneer! Reset state to 0 before examining next
7066 instruction.
906e58ca 7067
c7b8f16e 7068 2 -> 0
99059e56
RM		 7069 If we fail to match anything in state 2, reset to state 0 and reset
7070 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 7071
7072 If the VFP11 vector mode is in use, there must be at least two unrelated
7073 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 7074 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 7075
7076 /* If we are only performing a partial link do not bother
7077 to construct any glue. */
0e1862bb 7078 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 7079 return TRUE;
7080
0ffa91dd
NC		 7081 /* Skip if this bfd does not correspond to an ELF image. */
7082 if (! is_arm_elf (abfd))
7083 return TRUE;
906e58ca 7084
c7b8f16e
JB		 7085 /* We should have chosen a fix type by the time we get here. */
7086 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
7087
7088 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
7089 return TRUE;
2e6030b9 7090
33a7ffc2
JM		 7091 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7092 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7093 return TRUE;
7094
c7b8f16e
JB		 7095 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7096 {
7097 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
7098 struct _arm_elf_section_data *sec_data;
7099
7100 /* If we don't have executable progbits, we're not interested in this
99059e56 7101 section. Also skip if section is to be excluded. */
c7b8f16e 7102 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 7103 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7104 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 7105 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 7106 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 7107 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
7108 continue;
c7b8f16e
JB		 7109
7110 sec_data = elf32_arm_section_data (sec);
906e58ca 7111
c7b8f16e 7112 if (sec_data->mapcount == 0)
99059e56 7113 continue;
906e58ca 7114
c7b8f16e
JB		 7115 if (elf_section_data (sec)->this_hdr.contents != NULL)
7116 contents = elf_section_data (sec)->this_hdr.contents;
7117 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7118 goto error_return;
7119
7120 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7121 elf32_arm_compare_mapping);
7122
7123 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 7124 {
7125 unsigned int span_start = sec_data->map[span].vma;
7126 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 7127 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 7128 char span_type = sec_data->map[span].type;
7129
7130 /* FIXME: Only ARM mode is supported at present. We may need to
7131 support Thumb-2 mode also at some point. */
7132 if (span_type != 'a')
7133 continue;
7134
7135 for (i = span_start; i < span_end;)
7136 {
7137 unsigned int next_i = i + 4;
7138 unsigned int insn = bfd_big_endian (abfd)
7139 ? (contents[i] << 24)
7140 | (contents[i + 1] << 16)
7141 | (contents[i + 2] << 8)
7142 | contents[i + 3]
7143 : (contents[i + 3] << 24)
7144 | (contents[i + 2] << 16)
7145 | (contents[i + 1] << 8)
7146 | contents[i];
7147 unsigned int writemask = 0;
7148 enum bfd_arm_vfp11_pipe vpipe;
7149
7150 switch (state)
7151 {
7152 case 0:
7153 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
7154 &numregs);
7155 /* I'm assuming the VFP11 erratum can trigger with denorm
7156 operands on either the FMAC or the DS pipeline. This might
7157 lead to slightly overenthusiastic veneer insertion. */
7158 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
7159 {
7160 state = use_vector ? 1 : 2;
7161 first_fmac = i;
7162 veneer_of_insn = insn;
7163 }
7164 break;
7165
7166 case 1:
7167 {
7168 int other_regs[3], other_numregs;
7169 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7170 other_regs,
99059e56
RM		 7171 &other_numregs);
7172 if (vpipe != VFP11_BAD
7173 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7174 numregs))
99059e56
RM		 7175 state = 3;
7176 else
7177 state = 2;
7178 }
7179 break;
7180
7181 case 2:
7182 {
7183 int other_regs[3], other_numregs;
7184 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7185 other_regs,
99059e56
RM		 7186 &other_numregs);
7187 if (vpipe != VFP11_BAD
7188 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7189 numregs))
99059e56
RM		 7190 state = 3;
7191 else
7192 {
7193 state = 0;
7194 next_i = first_fmac + 4;
7195 }
7196 }
7197 break;
7198
7199 case 3:
7200 abort (); /* Should be unreachable. */
7201 }
7202
7203 if (state == 3)
7204 {
7205 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
7206 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7207
7208 elf32_arm_section_data (sec)->erratumcount += 1;
7209
7210 newerr->u.b.vfp_insn = veneer_of_insn;
7211
7212 switch (span_type)
7213 {
7214 case 'a':
7215 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
7216 break;
7217
7218 default:
7219 abort ();
7220 }
7221
7222 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 7223 first_fmac);
7224
99059e56 7225 newerr->vma = -1;
c7b8f16e 7226
99059e56
RM		 7227 newerr->next = sec_data->erratumlist;
7228 sec_data->erratumlist = newerr;
c7b8f16e 7229
99059e56
RM		 7230 state = 0;
7231 }
c7b8f16e 7232
99059e56
RM		 7233 i = next_i;
7234 }
7235 }
906e58ca 7236
c7b8f16e 7237 if (contents != NULL
99059e56
RM		 7238 && elf_section_data (sec)->this_hdr.contents != contents)
7239 free (contents);
c7b8f16e
JB		 7240 contents = NULL;
7241 }
7242
7243 return TRUE;
7244
7245error_return:
7246 if (contents != NULL
7247 && elf_section_data (sec)->this_hdr.contents != contents)
7248 free (contents);
906e58ca 7249
c7b8f16e
JB		 7250 return FALSE;
7251}
7252
7253/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7254 after sections have been laid out, using specially-named symbols. */
7255
7256void
7257bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
7258 struct bfd_link_info *link_info)
7259{
7260 asection *sec;
7261 struct elf32_arm_link_hash_table *globals;
7262 char *tmp_name;
906e58ca 7263
0e1862bb 7264 if (bfd_link_relocatable (link_info))
c7b8f16e 7265 return;
2e6030b9
MS		 7266
7267 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 7268 if (! is_arm_elf (abfd))
2e6030b9
MS		 7269 return;
7270
c7b8f16e 7271 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7272 if (globals == NULL)
7273 return;
906e58ca 7274
21d799b5 7275 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7276 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 7277
7278 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7279 {
7280 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7281 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 7282
c7b8f16e 7283 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 7284 {
7285 struct elf_link_hash_entry *myh;
7286 bfd_vma vma;
7287
7288 switch (errnode->type)
7289 {
7290 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
7291 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
7292 /* Find veneer symbol. */
7293 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 7294 errnode->u.b.veneer->u.v.id);
7295
99059e56
RM		 7296 myh = elf_link_hash_lookup
7297 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 7298
a504d23a
LA		 7299 if (myh == NULL)
7300 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7301 "`%s'"), abfd, tmp_name);
7302
7303 vma = myh->root.u.def.section->output_section->vma
7304 + myh->root.u.def.section->output_offset
7305 + myh->root.u.def.value;
7306
7307 errnode->u.b.veneer->vma = vma;
7308 break;
7309
7310 case VFP11_ERRATUM_ARM_VENEER:
7311 case VFP11_ERRATUM_THUMB_VENEER:
7312 /* Find return location. */
7313 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7314 errnode->u.v.id);
7315
7316 myh = elf_link_hash_lookup
7317 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7318
7319 if (myh == NULL)
7320 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7321 "`%s'"), abfd, tmp_name);
7322
7323 vma = myh->root.u.def.section->output_section->vma
7324 + myh->root.u.def.section->output_offset
7325 + myh->root.u.def.value;
7326
7327 errnode->u.v.branch->vma = vma;
7328 break;
7329
7330 default:
7331 abort ();
7332 }
7333 }
7334 }
7335
7336 free (tmp_name);
7337}
7338
7339/* Find virtual-memory addresses for STM32L4XX erratum veneers and
7340 return locations after sections have been laid out, using
7341 specially-named symbols. */
7342
7343void
7344bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
7345 struct bfd_link_info *link_info)
7346{
7347 asection *sec;
7348 struct elf32_arm_link_hash_table *globals;
7349 char *tmp_name;
7350
7351 if (bfd_link_relocatable (link_info))
7352 return;
7353
7354 /* Skip if this bfd does not correspond to an ELF image. */
7355 if (! is_arm_elf (abfd))
7356 return;
7357
7358 globals = elf32_arm_hash_table (link_info);
7359 if (globals == NULL)
7360 return;
7361
7362 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7363 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7364
7365 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7366 {
7367 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7368 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
7369
7370 for (; errnode != NULL; errnode = errnode->next)
7371 {
7372 struct elf_link_hash_entry *myh;
7373 bfd_vma vma;
7374
7375 switch (errnode->type)
7376 {
7377 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
7378 /* Find veneer symbol. */
7379 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7380 errnode->u.b.veneer->u.v.id);
7381
7382 myh = elf_link_hash_lookup
7383 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7384
7385 if (myh == NULL)
7386 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7387 "`%s'"), abfd, tmp_name);
7388
7389 vma = myh->root.u.def.section->output_section->vma
7390 + myh->root.u.def.section->output_offset
7391 + myh->root.u.def.value;
7392
7393 errnode->u.b.veneer->vma = vma;
7394 break;
7395
7396 case STM32L4XX_ERRATUM_VENEER:
7397 /* Find return location. */
7398 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7399 errnode->u.v.id);
7400
7401 myh = elf_link_hash_lookup
7402 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7403
7404 if (myh == NULL)
7405 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7406 "`%s'"), abfd, tmp_name);
7407
7408 vma = myh->root.u.def.section->output_section->vma
7409 + myh->root.u.def.section->output_offset
7410 + myh->root.u.def.value;
7411
7412 errnode->u.v.branch->vma = vma;
7413 break;
7414
7415 default:
7416 abort ();
7417 }
7418 }
7419 }
7420
7421 free (tmp_name);
7422}
7423
7424static inline bfd_boolean
7425is_thumb2_ldmia (const insn32 insn)
7426{
7427 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
7428 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
7429 return (insn & 0xffd02000) == 0xe8900000;
7430}
7431
7432static inline bfd_boolean
7433is_thumb2_ldmdb (const insn32 insn)
7434{
7435 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
7436 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
7437 return (insn & 0xffd02000) == 0xe9100000;
7438}
7439
7440static inline bfd_boolean
7441is_thumb2_vldm (const insn32 insn)
7442{
7443 /* A6.5 Extension register load or store instruction
7444 A7.7.229
9239bbd3
CM		 7445 We look for SP 32-bit and DP 64-bit registers.
7446 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
7447 <list> is consecutive 64-bit registers
7448 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 7449 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
7450 <list> is consecutive 32-bit registers
7451 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
7452 if P==0 && U==1 && W==1 && Rn=1101 VPOP
7453 if PUW=010 || PUW=011 || PUW=101 VLDM. */
7454 return
9239bbd3
CM		 7455 (((insn & 0xfe100f00) == 0xec100b00) ||
7456 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 7457 && /* (IA without !). */
7458 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 7459 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 7460 || ((((insn << 7) >> 28) & 0xd) == 0x5)
7461 /* (DB with !). */
7462 || ((((insn << 7) >> 28) & 0xd) == 0x9));
7463}
7464
7465/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
7466 VLDM opcode and:
7467 - computes the number and the mode of memory accesses
7468 - decides if the replacement should be done:
7469 . replaces only if > 8-word accesses
7470 . or (testing purposes only) replaces all accesses. */
7471
7472static bfd_boolean
7473stm32l4xx_need_create_replacing_stub (const insn32 insn,
7474 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
7475{
9239bbd3 7476 int nb_words = 0;
a504d23a
LA		 7477
7478 /* The field encoding the register list is the same for both LDMIA
7479 and LDMDB encodings. */
7480 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 7481 nb_words = popcount (insn & 0x0000ffff);
a504d23a 7482 else if (is_thumb2_vldm (insn))
9239bbd3 7483 nb_words = (insn & 0xff);
a504d23a
LA		 7484
7485 /* DEFAULT mode accounts for the real bug condition situation,
7486 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
7487 return
9239bbd3 7488 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 7489 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
7490}
7491
7492/* Look for potentially-troublesome code sequences which might trigger
7493 the STM STM32L4XX erratum. */
7494
7495bfd_boolean
7496bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
7497 struct bfd_link_info *link_info)
7498{
7499 asection *sec;
7500 bfd_byte *contents = NULL;
7501 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7502
7503 if (globals == NULL)
7504 return FALSE;
7505
7506 /* If we are only performing a partial link do not bother
7507 to construct any glue. */
7508 if (bfd_link_relocatable (link_info))
7509 return TRUE;
7510
7511 /* Skip if this bfd does not correspond to an ELF image. */
7512 if (! is_arm_elf (abfd))
7513 return TRUE;
7514
7515 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
7516 return TRUE;
7517
7518 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7519 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7520 return TRUE;
7521
7522 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7523 {
7524 unsigned int i, span;
7525 struct _arm_elf_section_data *sec_data;
7526
7527 /* If we don't have executable progbits, we're not interested in this
7528 section. Also skip if section is to be excluded. */
7529 if (elf_section_type (sec) != SHT_PROGBITS
7530 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7531 || (sec->flags & SEC_EXCLUDE) != 0
7532 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
7533 || sec->output_section == bfd_abs_section_ptr
7534 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
7535 continue;
7536
7537 sec_data = elf32_arm_section_data (sec);
c7b8f16e 7538
a504d23a
LA		 7539 if (sec_data->mapcount == 0)
7540 continue;
c7b8f16e 7541
a504d23a
LA		 7542 if (elf_section_data (sec)->this_hdr.contents != NULL)
7543 contents = elf_section_data (sec)->this_hdr.contents;
7544 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7545 goto error_return;
c7b8f16e 7546
a504d23a
LA		 7547 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7548 elf32_arm_compare_mapping);
c7b8f16e 7549
a504d23a
LA		 7550 for (span = 0; span < sec_data->mapcount; span++)
7551 {
7552 unsigned int span_start = sec_data->map[span].vma;
7553 unsigned int span_end = (span == sec_data->mapcount - 1)
7554 ? sec->size : sec_data->map[span + 1].vma;
7555 char span_type = sec_data->map[span].type;
7556 int itblock_current_pos = 0;
c7b8f16e 7557
a504d23a
LA		 7558 /* Only Thumb2 mode need be supported with this CM4 specific
7559 code, we should not encounter any arm mode eg span_type
7560 != 'a'. */
7561 if (span_type != 't')
7562 continue;
c7b8f16e 7563
a504d23a
LA		 7564 for (i = span_start; i < span_end;)
7565 {
7566 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
7567 bfd_boolean insn_32bit = FALSE;
7568 bfd_boolean is_ldm = FALSE;
7569 bfd_boolean is_vldm = FALSE;
7570 bfd_boolean is_not_last_in_it_block = FALSE;
7571
7572 /* The first 16-bits of all 32-bit thumb2 instructions start
7573 with opcode[15..13]=0b111 and the encoded op1 can be anything
7574 except opcode[12..11]!=0b00.
7575 See 32-bit Thumb instruction encoding. */
7576 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
7577 insn_32bit = TRUE;
c7b8f16e 7578
a504d23a
LA		 7579 /* Compute the predicate that tells if the instruction
7580 is concerned by the IT block
7581 - Creates an error if there is a ldm that is not
7582 last in the IT block thus cannot be replaced
7583 - Otherwise we can create a branch at the end of the
7584 IT block, it will be controlled naturally by IT
7585 with the proper pseudo-predicate
7586 - So the only interesting predicate is the one that
7587 tells that we are not on the last item of an IT
7588 block. */
7589 if (itblock_current_pos != 0)
7590 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 7591
a504d23a
LA		 7592 if (insn_32bit)
7593 {
7594 /* Load the rest of the insn (in manual-friendly order). */
7595 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
7596 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
7597 is_vldm = is_thumb2_vldm (insn);
7598
7599 /* Veneers are created for (v)ldm depending on
7600 option flags and memory accesses conditions; but
7601 if the instruction is not the last instruction of
7602 an IT block, we cannot create a jump there, so we
7603 bail out. */
7604 if ((is_ldm || is_vldm) &&
7605 stm32l4xx_need_create_replacing_stub
7606 (insn, globals->stm32l4xx_fix))
7607 {
7608 if (is_not_last_in_it_block)
7609 {
7610 (*_bfd_error_handler)
7611 /* Note - overlong line used here to allow for translation. */
7612 (_("\
7613%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
7614 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
7615 abfd, sec, (long)i);
7616 }
7617 else
7618 {
7619 elf32_stm32l4xx_erratum_list *newerr =
7620 (elf32_stm32l4xx_erratum_list *)
7621 bfd_zmalloc
7622 (sizeof (elf32_stm32l4xx_erratum_list));
7623
7624 elf32_arm_section_data (sec)
7625 ->stm32l4xx_erratumcount += 1;
7626 newerr->u.b.insn = insn;
7627 /* We create only thumb branches. */
7628 newerr->type =
7629 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
7630 record_stm32l4xx_erratum_veneer
7631 (link_info, newerr, abfd, sec,
7632 i,
7633 is_ldm ?
7634 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
7635 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
7636 newerr->vma = -1;
7637 newerr->next = sec_data->stm32l4xx_erratumlist;
7638 sec_data->stm32l4xx_erratumlist = newerr;
7639 }
7640 }
7641 }
7642 else
7643 {
7644 /* A7.7.37 IT p208
7645 IT blocks are only encoded in T1
7646 Encoding T1: IT{x{y{z}}} <firstcond>
7647 1 0 1 1 - 1 1 1 1 - firstcond - mask
7648 if mask = '0000' then see 'related encodings'
7649 We don't deal with UNPREDICTABLE, just ignore these.
7650 There can be no nested IT blocks so an IT block
7651 is naturally a new one for which it is worth
7652 computing its size. */
7653 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
7654 ((insn & 0x000f) != 0x0000);
7655 /* If we have a new IT block we compute its size. */
7656 if (is_newitblock)
7657 {
7658 /* Compute the number of instructions controlled
7659 by the IT block, it will be used to decide
7660 whether we are inside an IT block or not. */
7661 unsigned int mask = insn & 0x000f;
7662 itblock_current_pos = 4 - ctz (mask);
7663 }
7664 }
7665
7666 i += insn_32bit ? 4 : 2;
99059e56
RM		 7667 }
7668 }
a504d23a
LA		 7669
7670 if (contents != NULL
7671 && elf_section_data (sec)->this_hdr.contents != contents)
7672 free (contents);
7673 contents = NULL;
c7b8f16e 7674 }
906e58ca 7675
a504d23a
LA		 7676 return TRUE;
7677
7678error_return:
7679 if (contents != NULL
7680 && elf_section_data (sec)->this_hdr.contents != contents)
7681 free (contents);
c7b8f16e 7682
a504d23a
LA		 7683 return FALSE;
7684}
c7b8f16e 7685
eb043451
PB		 7686/* Set target relocation values needed during linking. */
7687
7688void
bf21ed78
MS		 7689bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
7690 struct bfd_link_info *link_info,
eb043451 7691 int target1_is_rel,
319850b4 7692 char * target2_type,
99059e56 7693 int fix_v4bx,
c7b8f16e 7694 int use_blx,
99059e56 7695 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 7696 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 7697 int no_enum_warn, int no_wchar_warn,
2de70689
MGD		 7698 int pic_veneer, int fix_cortex_a8,
7699 int fix_arm1176)
eb043451
PB		 7700{
7701 struct elf32_arm_link_hash_table *globals;
7702
7703 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7704 if (globals == NULL)
7705 return;
eb043451
PB		 7706
7707 globals->target1_is_rel = target1_is_rel;
7708 if (strcmp (target2_type, "rel") == 0)
7709 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 7710 else if (strcmp (target2_type, "abs") == 0)
7711 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 7712 else if (strcmp (target2_type, "got-rel") == 0)
7713 globals->target2_reloc = R_ARM_GOT_PREL;
7714 else
7715 {
7716 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
7717 target2_type);
7718 }
319850b4 7719 globals->fix_v4bx = fix_v4bx;
33bfe774 7720 globals->use_blx |= use_blx;
c7b8f16e 7721 globals->vfp11_fix = vfp11_fix;
a504d23a 7722 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 7723 globals->pic_veneer = pic_veneer;
48229727 7724 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 7725 globals->fix_arm1176 = fix_arm1176;
bf21ed78 7726
0ffa91dd
NC		 7727 BFD_ASSERT (is_arm_elf (output_bfd));
7728 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 7729 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 7730}
eb043451 7731
12a0a0fd 7732/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 7733
12a0a0fd
PB		 7734static void
7735insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
7736{
7737 bfd_vma upper;
7738 bfd_vma lower;
7739 int reloc_sign;
7740
7741 BFD_ASSERT ((offset & 1) == 0);
7742
7743 upper = bfd_get_16 (abfd, insn);
7744 lower = bfd_get_16 (abfd, insn + 2);
7745 reloc_sign = (offset < 0) ? 1 : 0;
7746 upper = (upper & ~(bfd_vma) 0x7ff)
7747 | ((offset >> 12) & 0x3ff)
7748 | (reloc_sign << 10);
906e58ca 7749 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 7750 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
7751 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
7752 | ((offset >> 1) & 0x7ff);
7753 bfd_put_16 (abfd, upper, insn);
7754 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 7755}
7756
9b485d32
NC		 7757/* Thumb code calling an ARM function. */
7758
252b5132 7759static int
57e8b36a
NC		 7760elf32_thumb_to_arm_stub (struct bfd_link_info * info,
7761 const char * name,
7762 bfd * input_bfd,
7763 bfd * output_bfd,
7764 asection * input_section,
7765 bfd_byte * hit_data,
7766 asection * sym_sec,
7767 bfd_vma offset,
7768 bfd_signed_vma addend,
f2a9dd69
DJ		 7769 bfd_vma val,
7770 char **error_message)
252b5132 7771{
bcbdc74c 7772 asection * s = 0;
dc810e39 7773 bfd_vma my_offset;
252b5132 7774 long int ret_offset;
bcbdc74c
NC		 7775 struct elf_link_hash_entry * myh;
7776 struct elf32_arm_link_hash_table * globals;
252b5132 7777
f2a9dd69 7778 myh = find_thumb_glue (info, name, error_message);
252b5132 7779 if (myh == NULL)
b34976b6 7780 return FALSE;
252b5132
RH		 7781
7782 globals = elf32_arm_hash_table (info);
252b5132
RH		 7783 BFD_ASSERT (globals != NULL);
7784 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7785
7786 my_offset = myh->root.u.def.value;
7787
3d4d4302
AM		 7788 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7789 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 7790
7791 BFD_ASSERT (s != NULL);
7792 BFD_ASSERT (s->contents != NULL);
7793 BFD_ASSERT (s->output_section != NULL);
7794
7795 if ((my_offset & 0x01) == 0x01)
7796 {
7797 if (sym_sec != NULL
7798 && sym_sec->owner != NULL
7799 && !INTERWORK_FLAG (sym_sec->owner))
7800 {
8f615d07 7801 (*_bfd_error_handler)
d003868e 7802 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 7803 " first occurrence: %B: Thumb call to ARM"),
d003868e 7804 sym_sec->owner, input_bfd, name);
252b5132 7805
b34976b6 7806 return FALSE;
252b5132
RH		 7807 }
7808
7809 --my_offset;
7810 myh->root.u.def.value = my_offset;
7811
52ab56c2
PB		 7812 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
7813 s->contents + my_offset);
252b5132 7814
52ab56c2
PB		 7815 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
7816 s->contents + my_offset + 2);
252b5132
RH		 7817
7818 ret_offset =
9b485d32
NC		 7819 /* Address of destination of the stub. */
7820 ((bfd_signed_vma) val)
252b5132 7821 - ((bfd_signed_vma)
57e8b36a
NC		 7822 /* Offset from the start of the current section
7823 to the start of the stubs. */
9b485d32
NC		 7824 (s->output_offset
7825 /* Offset of the start of this stub from the start of the stubs. */
7826 + my_offset
7827 /* Address of the start of the current section. */
7828 + s->output_section->vma)
7829 /* The branch instruction is 4 bytes into the stub. */
7830 + 4
7831 /* ARM branches work from the pc of the instruction + 8. */
7832 + 8);
252b5132 7833
52ab56c2
PB		 7834 put_arm_insn (globals, output_bfd,
7835 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
7836 s->contents + my_offset + 4);
252b5132
RH		 7837 }
7838
7839 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
7840
427bfd90
NC		 7841 /* Now go back and fix up the original BL insn to point to here. */
7842 ret_offset =
7843 /* Address of where the stub is located. */
7844 (s->output_section->vma + s->output_offset + my_offset)
7845 /* Address of where the BL is located. */
57e8b36a
NC		 7846 - (input_section->output_section->vma + input_section->output_offset
7847 + offset)
427bfd90
NC		 7848 /* Addend in the relocation. */
7849 - addend
7850 /* Biassing for PC-relative addressing. */
7851 - 8;
252b5132 7852
12a0a0fd 7853 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 7854
b34976b6 7855 return TRUE;
252b5132
RH		 7856}
7857
a4fd1a8e 7858/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 7859
a4fd1a8e
PB		 7860static struct elf_link_hash_entry *
7861elf32_arm_create_thumb_stub (struct bfd_link_info * info,
7862 const char * name,
7863 bfd * input_bfd,
7864 bfd * output_bfd,
7865 asection * sym_sec,
7866 bfd_vma val,
8029a119
NC		 7867 asection * s,
7868 char ** error_message)
252b5132 7869{
dc810e39 7870 bfd_vma my_offset;
252b5132 7871 long int ret_offset;
bcbdc74c
NC		 7872 struct elf_link_hash_entry * myh;
7873 struct elf32_arm_link_hash_table * globals;
252b5132 7874
f2a9dd69 7875 myh = find_arm_glue (info, name, error_message);
252b5132 7876 if (myh == NULL)
a4fd1a8e 7877 return NULL;
252b5132
RH		 7878
7879 globals = elf32_arm_hash_table (info);
252b5132
RH		 7880 BFD_ASSERT (globals != NULL);
7881 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7882
7883 my_offset = myh->root.u.def.value;
252b5132
RH		 7884
7885 if ((my_offset & 0x01) == 0x01)
7886 {
7887 if (sym_sec != NULL
7888 && sym_sec->owner != NULL
7889 && !INTERWORK_FLAG (sym_sec->owner))
7890 {
8f615d07 7891 (*_bfd_error_handler)
d003868e
AM		 7892 (_("%B(%s): warning: interworking not enabled.\n"
7893 " first occurrence: %B: arm call to thumb"),
7894 sym_sec->owner, input_bfd, name);
252b5132 7895 }
9b485d32 7896
252b5132
RH		 7897 --my_offset;
7898 myh->root.u.def.value = my_offset;
7899
0e1862bb
L		 7900 if (bfd_link_pic (info)
7901 || globals->root.is_relocatable_executable
27e55c4d 7902 || globals->pic_veneer)
8f6277f5
PB		 7903 {
7904 /* For relocatable objects we can't use absolute addresses,
7905 so construct the address from a relative offset. */
7906 /* TODO: If the offset is small it's probably worth
7907 constructing the address with adds. */
52ab56c2
PB		 7908 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
7909 s->contents + my_offset);
7910 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
7911 s->contents + my_offset + 4);
7912 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
7913 s->contents + my_offset + 8);
8f6277f5
PB		 7914 /* Adjust the offset by 4 for the position of the add,
7915 and 8 for the pipeline offset. */
7916 ret_offset = (val - (s->output_offset
7917 + s->output_section->vma
7918 + my_offset + 12))
7919 | 1;
7920 bfd_put_32 (output_bfd, ret_offset,
7921 s->contents + my_offset + 12);
7922 }
26079076
PB		 7923 else if (globals->use_blx)
7924 {
7925 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
7926 s->contents + my_offset);
7927
7928 /* It's a thumb address. Add the low order bit. */
7929 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
7930 s->contents + my_offset + 4);
7931 }
8f6277f5
PB		 7932 else
7933 {
52ab56c2
PB		 7934 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
7935 s->contents + my_offset);
252b5132 7936
52ab56c2
PB		 7937 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
7938 s->contents + my_offset + 4);
252b5132 7939
8f6277f5
PB		 7940 /* It's a thumb address. Add the low order bit. */
7941 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
7942 s->contents + my_offset + 8);
8029a119
NC		 7943
7944 my_offset += 12;
8f6277f5 7945 }
252b5132
RH		 7946 }
7947
7948 BFD_ASSERT (my_offset <= globals->arm_glue_size);
7949
a4fd1a8e
PB		 7950 return myh;
7951}
7952
7953/* Arm code calling a Thumb function. */
7954
7955static int
7956elf32_arm_to_thumb_stub (struct bfd_link_info * info,
7957 const char * name,
7958 bfd * input_bfd,
7959 bfd * output_bfd,
7960 asection * input_section,
7961 bfd_byte * hit_data,
7962 asection * sym_sec,
7963 bfd_vma offset,
7964 bfd_signed_vma addend,
f2a9dd69
DJ		 7965 bfd_vma val,
7966 char **error_message)
a4fd1a8e
PB		 7967{
7968 unsigned long int tmp;
7969 bfd_vma my_offset;
7970 asection * s;
7971 long int ret_offset;
7972 struct elf_link_hash_entry * myh;
7973 struct elf32_arm_link_hash_table * globals;
7974
7975 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 7976 BFD_ASSERT (globals != NULL);
7977 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7978
3d4d4302
AM		 7979 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7980 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 7981 BFD_ASSERT (s != NULL);
7982 BFD_ASSERT (s->contents != NULL);
7983 BFD_ASSERT (s->output_section != NULL);
7984
7985 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 7986 sym_sec, val, s, error_message);
a4fd1a8e
PB		 7987 if (!myh)
7988 return FALSE;
7989
7990 my_offset = myh->root.u.def.value;
252b5132
RH		 7991 tmp = bfd_get_32 (input_bfd, hit_data);
7992 tmp = tmp & 0xFF000000;
7993
9b485d32 7994 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 7995 ret_offset = (s->output_offset
7996 + my_offset
7997 + s->output_section->vma
7998 - (input_section->output_offset
7999 + input_section->output_section->vma
8000 + offset + addend)
8001 - 8);
9a5aca8c 8002
252b5132
RH		 8003 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
8004
dc810e39 8005 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 8006
b34976b6 8007 return TRUE;
252b5132
RH		 8008}
8009
a4fd1a8e
PB		 8010/* Populate Arm stub for an exported Thumb function. */
8011
8012static bfd_boolean
8013elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
8014{
8015 struct bfd_link_info * info = (struct bfd_link_info *) inf;
8016 asection * s;
8017 struct elf_link_hash_entry * myh;
8018 struct elf32_arm_link_hash_entry *eh;
8019 struct elf32_arm_link_hash_table * globals;
8020 asection *sec;
8021 bfd_vma val;
f2a9dd69 8022 char *error_message;
a4fd1a8e 8023
906e58ca 8024 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 8025 /* Allocate stubs for exported Thumb functions on v4t. */
8026 if (eh->export_glue == NULL)
8027 return TRUE;
8028
8029 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8030 BFD_ASSERT (globals != NULL);
8031 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8032
3d4d4302
AM		 8033 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8034 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8035 BFD_ASSERT (s != NULL);
8036 BFD_ASSERT (s->contents != NULL);
8037 BFD_ASSERT (s->output_section != NULL);
8038
8039 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 8040
8041 BFD_ASSERT (sec->output_section != NULL);
8042
a4fd1a8e
PB		 8043 val = eh->export_glue->root.u.def.value + sec->output_offset
8044 + sec->output_section->vma;
8029a119 8045
a4fd1a8e
PB		 8046 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
8047 h->root.u.def.section->owner,
f2a9dd69
DJ		 8048 globals->obfd, sec, val, s,
8049 &error_message);
a4fd1a8e
PB		 8050 BFD_ASSERT (myh);
8051 return TRUE;
8052}
8053
845b51d6
PB		 8054/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
8055
8056static bfd_vma
8057elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
8058{
8059 bfd_byte *p;
8060 bfd_vma glue_addr;
8061 asection *s;
8062 struct elf32_arm_link_hash_table *globals;
8063
8064 globals = elf32_arm_hash_table (info);
845b51d6
PB		 8065 BFD_ASSERT (globals != NULL);
8066 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8067
3d4d4302
AM		 8068 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8069 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 8070 BFD_ASSERT (s != NULL);
8071 BFD_ASSERT (s->contents != NULL);
8072 BFD_ASSERT (s->output_section != NULL);
8073
8074 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
8075
8076 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
8077
8078 if ((globals->bx_glue_offset[reg] & 1) == 0)
8079 {
8080 p = s->contents + glue_addr;
8081 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
8082 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
8083 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
8084 globals->bx_glue_offset[reg] |= 1;
8085 }
8086
8087 return glue_addr + s->output_section->vma + s->output_offset;
8088}
8089
a4fd1a8e
PB		 8090/* Generate Arm stubs for exported Thumb symbols. */
8091static void
906e58ca 8092elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 8093 struct bfd_link_info *link_info)
8094{
8095 struct elf32_arm_link_hash_table * globals;
8096
8029a119
NC		 8097 if (link_info == NULL)
8098 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 8099 return;
8100
8101 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8102 if (globals == NULL)
8103 return;
8104
84c08195
PB		 8105 /* If blx is available then exported Thumb symbols are OK and there is
8106 nothing to do. */
a4fd1a8e
PB		 8107 if (globals->use_blx)
8108 return;
8109
8110 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
8111 link_info);
8112}
8113
47beaa6a
RS		 8114/* Reserve space for COUNT dynamic relocations in relocation selection
8115 SRELOC. */
8116
8117static void
8118elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
8119 bfd_size_type count)
8120{
8121 struct elf32_arm_link_hash_table *htab;
8122
8123 htab = elf32_arm_hash_table (info);
8124 BFD_ASSERT (htab->root.dynamic_sections_created);
8125 if (sreloc == NULL)
8126 abort ();
8127 sreloc->size += RELOC_SIZE (htab) * count;
8128}
8129
34e77a92
RS		 8130/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8131 dynamic, the relocations should go in SRELOC, otherwise they should
8132 go in the special .rel.iplt section. */
8133
8134static void
8135elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
8136 bfd_size_type count)
8137{
8138 struct elf32_arm_link_hash_table *htab;
8139
8140 htab = elf32_arm_hash_table (info);
8141 if (!htab->root.dynamic_sections_created)
8142 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
8143 else
8144 {
8145 BFD_ASSERT (sreloc != NULL);
8146 sreloc->size += RELOC_SIZE (htab) * count;
8147 }
8148}
8149
47beaa6a
RS		 8150/* Add relocation REL to the end of relocation section SRELOC. */
8151
8152static void
8153elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
8154 asection *sreloc, Elf_Internal_Rela *rel)
8155{
8156 bfd_byte *loc;
8157 struct elf32_arm_link_hash_table *htab;
8158
8159 htab = elf32_arm_hash_table (info);
34e77a92
RS		 8160 if (!htab->root.dynamic_sections_created
8161 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
8162 sreloc = htab->root.irelplt;
47beaa6a
RS		 8163 if (sreloc == NULL)
8164 abort ();
8165 loc = sreloc->contents;
8166 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
8167 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
8168 abort ();
8169 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
8170}
8171
34e77a92
RS		 8172/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8173 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8174 to .plt. */
8175
8176static void
8177elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
8178 bfd_boolean is_iplt_entry,
8179 union gotplt_union *root_plt,
8180 struct arm_plt_info *arm_plt)
8181{
8182 struct elf32_arm_link_hash_table *htab;
8183 asection *splt;
8184 asection *sgotplt;
8185
8186 htab = elf32_arm_hash_table (info);
8187
8188 if (is_iplt_entry)
8189 {
8190 splt = htab->root.iplt;
8191 sgotplt = htab->root.igotplt;
8192
99059e56
RM		 8193 /* NaCl uses a special first entry in .iplt too. */
8194 if (htab->nacl_p && splt->size == 0)
8195 splt->size += htab->plt_header_size;
8196
34e77a92
RS		 8197 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8198 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
8199 }
8200 else
8201 {
8202 splt = htab->root.splt;
8203 sgotplt = htab->root.sgotplt;
8204
8205 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8206 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
8207
8208 /* If this is the first .plt entry, make room for the special
8209 first entry. */
8210 if (splt->size == 0)
8211 splt->size += htab->plt_header_size;
9f19ab6d
WN		 8212
8213 htab->next_tls_desc_index++;
34e77a92
RS		 8214 }
8215
8216 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8217 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8218 splt->size += PLT_THUMB_STUB_SIZE;
8219 root_plt->offset = splt->size;
8220 splt->size += htab->plt_entry_size;
8221
8222 if (!htab->symbian_p)
8223 {
8224 /* We also need to make an entry in the .got.plt section, which
8225 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 8226 if (is_iplt_entry)
8227 arm_plt->got_offset = sgotplt->size;
8228 else
8229 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 8230 sgotplt->size += 4;
8231 }
8232}
8233
b38cadfb
NC		 8234static bfd_vma
8235arm_movw_immediate (bfd_vma value)
8236{
8237 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
8238}
8239
8240static bfd_vma
8241arm_movt_immediate (bfd_vma value)
8242{
8243 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
8244}
8245
34e77a92
RS		 8246/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8247 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8248 Otherwise, DYNINDX is the index of the symbol in the dynamic
8249 symbol table and SYM_VALUE is undefined.
8250
8251 ROOT_PLT points to the offset of the PLT entry from the start of its
8252 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 8253 bookkeeping information.
34e77a92 8254
57460bcf
NC		 8255 Returns FALSE if there was a problem. */
8256
8257static bfd_boolean
34e77a92
RS		 8258elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
8259 union gotplt_union *root_plt,
8260 struct arm_plt_info *arm_plt,
8261 int dynindx, bfd_vma sym_value)
8262{
8263 struct elf32_arm_link_hash_table *htab;
8264 asection *sgot;
8265 asection *splt;
8266 asection *srel;
8267 bfd_byte *loc;
8268 bfd_vma plt_index;
8269 Elf_Internal_Rela rel;
8270 bfd_vma plt_header_size;
8271 bfd_vma got_header_size;
8272
8273 htab = elf32_arm_hash_table (info);
8274
8275 /* Pick the appropriate sections and sizes. */
8276 if (dynindx == -1)
8277 {
8278 splt = htab->root.iplt;
8279 sgot = htab->root.igotplt;
8280 srel = htab->root.irelplt;
8281
8282 /* There are no reserved entries in .igot.plt, and no special
8283 first entry in .iplt. */
8284 got_header_size = 0;
8285 plt_header_size = 0;
8286 }
8287 else
8288 {
8289 splt = htab->root.splt;
8290 sgot = htab->root.sgotplt;
8291 srel = htab->root.srelplt;
8292
8293 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
8294 plt_header_size = htab->plt_header_size;
8295 }
8296 BFD_ASSERT (splt != NULL && srel != NULL);
8297
8298 /* Fill in the entry in the procedure linkage table. */
8299 if (htab->symbian_p)
8300 {
8301 BFD_ASSERT (dynindx >= 0);
8302 put_arm_insn (htab, output_bfd,
8303 elf32_arm_symbian_plt_entry[0],
8304 splt->contents + root_plt->offset);
8305 bfd_put_32 (output_bfd,
8306 elf32_arm_symbian_plt_entry[1],
8307 splt->contents + root_plt->offset + 4);
8308
8309 /* Fill in the entry in the .rel.plt section. */
8310 rel.r_offset = (splt->output_section->vma
8311 + splt->output_offset
8312 + root_plt->offset + 4);
8313 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
8314
8315 /* Get the index in the procedure linkage table which
8316 corresponds to this symbol. This is the index of this symbol
8317 in all the symbols for which we are making plt entries. The
8318 first entry in the procedure linkage table is reserved. */
8319 plt_index = ((root_plt->offset - plt_header_size)
8320 / htab->plt_entry_size);
8321 }
8322 else
8323 {
8324 bfd_vma got_offset, got_address, plt_address;
8325 bfd_vma got_displacement, initial_got_entry;
8326 bfd_byte * ptr;
8327
8328 BFD_ASSERT (sgot != NULL);
8329
8330 /* Get the offset into the .(i)got.plt table of the entry that
8331 corresponds to this function. */
8332 got_offset = (arm_plt->got_offset & -2);
8333
8334 /* Get the index in the procedure linkage table which
8335 corresponds to this symbol. This is the index of this symbol
8336 in all the symbols for which we are making plt entries.
8337 After the reserved .got.plt entries, all symbols appear in
8338 the same order as in .plt. */
8339 plt_index = (got_offset - got_header_size) / 4;
8340
8341 /* Calculate the address of the GOT entry. */
8342 got_address = (sgot->output_section->vma
8343 + sgot->output_offset
8344 + got_offset);
8345
8346 /* ...and the address of the PLT entry. */
8347 plt_address = (splt->output_section->vma
8348 + splt->output_offset
8349 + root_plt->offset);
8350
8351 ptr = splt->contents + root_plt->offset;
0e1862bb 8352 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 8353 {
8354 unsigned int i;
8355 bfd_vma val;
8356
8357 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8358 {
8359 val = elf32_arm_vxworks_shared_plt_entry[i];
8360 if (i == 2)
8361 val |= got_address - sgot->output_section->vma;
8362 if (i == 5)
8363 val |= plt_index * RELOC_SIZE (htab);
8364 if (i == 2 || i == 5)
8365 bfd_put_32 (output_bfd, val, ptr);
8366 else
8367 put_arm_insn (htab, output_bfd, val, ptr);
8368 }
8369 }
8370 else if (htab->vxworks_p)
8371 {
8372 unsigned int i;
8373 bfd_vma val;
8374
8375 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8376 {
8377 val = elf32_arm_vxworks_exec_plt_entry[i];
8378 if (i == 2)
8379 val |= got_address;
8380 if (i == 4)
8381 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
8382 if (i == 5)
8383 val |= plt_index * RELOC_SIZE (htab);
8384 if (i == 2 || i == 5)
8385 bfd_put_32 (output_bfd, val, ptr);
8386 else
8387 put_arm_insn (htab, output_bfd, val, ptr);
8388 }
8389
8390 loc = (htab->srelplt2->contents
8391 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
8392
8393 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
8394 referencing the GOT for this PLT entry. */
8395 rel.r_offset = plt_address + 8;
8396 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
8397 rel.r_addend = got_offset;
8398 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8399 loc += RELOC_SIZE (htab);
8400
8401 /* Create the R_ARM_ABS32 relocation referencing the
8402 beginning of the PLT for this GOT entry. */
8403 rel.r_offset = got_address;
8404 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
8405 rel.r_addend = 0;
8406 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8407 }
b38cadfb
NC		 8408 else if (htab->nacl_p)
8409 {
8410 /* Calculate the displacement between the PLT slot and the
8411 common tail that's part of the special initial PLT slot. */
6034aab8 8412 int32_t tail_displacement
b38cadfb
NC		 8413 = ((splt->output_section->vma + splt->output_offset
8414 + ARM_NACL_PLT_TAIL_OFFSET)
8415 - (plt_address + htab->plt_entry_size + 4));
8416 BFD_ASSERT ((tail_displacement & 3) == 0);
8417 tail_displacement >>= 2;
8418
8419 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
8420 || (-tail_displacement & 0xff000000) == 0);
8421
8422 /* Calculate the displacement between the PLT slot and the entry
8423 in the GOT. The offset accounts for the value produced by
8424 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 8425 got_displacement = (got_address
99059e56 8426 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 8427
8428 /* NaCl does not support interworking at all. */
8429 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
8430
8431 put_arm_insn (htab, output_bfd,
8432 elf32_arm_nacl_plt_entry[0]
8433 | arm_movw_immediate (got_displacement),
8434 ptr + 0);
8435 put_arm_insn (htab, output_bfd,
8436 elf32_arm_nacl_plt_entry[1]
8437 | arm_movt_immediate (got_displacement),
8438 ptr + 4);
8439 put_arm_insn (htab, output_bfd,
8440 elf32_arm_nacl_plt_entry[2],
8441 ptr + 8);
8442 put_arm_insn (htab, output_bfd,
8443 elf32_arm_nacl_plt_entry[3]
8444 | (tail_displacement & 0x00ffffff),
8445 ptr + 12);
8446 }
57460bcf
NC		 8447 else if (using_thumb_only (htab))
8448 {
eed94f8f 8449 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 8450 if (!using_thumb2 (htab))
eed94f8f
NC		 8451 {
8452 /* FIXME: We ought to be able to generate thumb-1 PLT
8453 instructions... */
8454 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
8455 output_bfd);
8456 return FALSE;
8457 }
57460bcf 8458
eed94f8f
NC		 8459 /* Calculate the displacement between the PLT slot and the entry in
8460 the GOT. The 12-byte offset accounts for the value produced by
8461 adding to pc in the 3rd instruction of the PLT stub. */
8462 got_displacement = got_address - (plt_address + 12);
8463
8464 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
8465 instead of 'put_thumb_insn'. */
8466 put_arm_insn (htab, output_bfd,
8467 elf32_thumb2_plt_entry[0]
8468 | ((got_displacement & 0x000000ff) << 16)
8469 | ((got_displacement & 0x00000700) << 20)
8470 | ((got_displacement & 0x00000800) >> 1)
8471 | ((got_displacement & 0x0000f000) >> 12),
8472 ptr + 0);
8473 put_arm_insn (htab, output_bfd,
8474 elf32_thumb2_plt_entry[1]
8475 | ((got_displacement & 0x00ff0000) )
8476 | ((got_displacement & 0x07000000) << 4)
8477 | ((got_displacement & 0x08000000) >> 17)
8478 | ((got_displacement & 0xf0000000) >> 28),
8479 ptr + 4);
8480 put_arm_insn (htab, output_bfd,
8481 elf32_thumb2_plt_entry[2],
8482 ptr + 8);
8483 put_arm_insn (htab, output_bfd,
8484 elf32_thumb2_plt_entry[3],
8485 ptr + 12);
57460bcf 8486 }
34e77a92
RS		 8487 else
8488 {
8489 /* Calculate the displacement between the PLT slot and the
8490 entry in the GOT. The eight-byte offset accounts for the
8491 value produced by adding to pc in the first instruction
8492 of the PLT stub. */
8493 got_displacement = got_address - (plt_address + 8);
8494
34e77a92
RS		 8495 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8496 {
8497 put_thumb_insn (htab, output_bfd,
8498 elf32_arm_plt_thumb_stub[0], ptr - 4);
8499 put_thumb_insn (htab, output_bfd,
8500 elf32_arm_plt_thumb_stub[1], ptr - 2);
8501 }
8502
1db37fe6
YG		 8503 if (!elf32_arm_use_long_plt_entry)
8504 {
8505 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
8506
8507 put_arm_insn (htab, output_bfd,
8508 elf32_arm_plt_entry_short[0]
8509 | ((got_displacement & 0x0ff00000) >> 20),
8510 ptr + 0);
8511 put_arm_insn (htab, output_bfd,
8512 elf32_arm_plt_entry_short[1]
8513 | ((got_displacement & 0x000ff000) >> 12),
8514 ptr+ 4);
8515 put_arm_insn (htab, output_bfd,
8516 elf32_arm_plt_entry_short[2]
8517 | (got_displacement & 0x00000fff),
8518 ptr + 8);
34e77a92 8519#ifdef FOUR_WORD_PLT
1db37fe6 8520 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 8521#endif
1db37fe6
YG		 8522 }
8523 else
8524 {
8525 put_arm_insn (htab, output_bfd,
8526 elf32_arm_plt_entry_long[0]
8527 | ((got_displacement & 0xf0000000) >> 28),
8528 ptr + 0);
8529 put_arm_insn (htab, output_bfd,
8530 elf32_arm_plt_entry_long[1]
8531 | ((got_displacement & 0x0ff00000) >> 20),
8532 ptr + 4);
8533 put_arm_insn (htab, output_bfd,
8534 elf32_arm_plt_entry_long[2]
8535 | ((got_displacement & 0x000ff000) >> 12),
8536 ptr+ 8);
8537 put_arm_insn (htab, output_bfd,
8538 elf32_arm_plt_entry_long[3]
8539 | (got_displacement & 0x00000fff),
8540 ptr + 12);
8541 }
34e77a92
RS		 8542 }
8543
8544 /* Fill in the entry in the .rel(a).(i)plt section. */
8545 rel.r_offset = got_address;
8546 rel.r_addend = 0;
8547 if (dynindx == -1)
8548 {
8549 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
8550 The dynamic linker or static executable then calls SYM_VALUE
8551 to determine the correct run-time value of the .igot.plt entry. */
8552 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
8553 initial_got_entry = sym_value;
8554 }
8555 else
8556 {
8557 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
8558 initial_got_entry = (splt->output_section->vma
8559 + splt->output_offset);
8560 }
8561
8562 /* Fill in the entry in the global offset table. */
8563 bfd_put_32 (output_bfd, initial_got_entry,
8564 sgot->contents + got_offset);
8565 }
8566
aba8c3de
WN		 8567 if (dynindx == -1)
8568 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
8569 else
8570 {
8571 loc = srel->contents + plt_index * RELOC_SIZE (htab);
8572 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8573 }
57460bcf
NC		 8574
8575 return TRUE;
34e77a92
RS		 8576}
8577
eb043451
PB		 8578/* Some relocations map to different relocations depending on the
8579 target. Return the real relocation. */
8029a119 8580
eb043451
PB		 8581static int
8582arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
8583 int r_type)
8584{
8585 switch (r_type)
8586 {
8587 case R_ARM_TARGET1:
8588 if (globals->target1_is_rel)
8589 return R_ARM_REL32;
8590 else
8591 return R_ARM_ABS32;
8592
8593 case R_ARM_TARGET2:
8594 return globals->target2_reloc;
8595
8596 default:
8597 return r_type;
8598 }
8599}
eb043451 8600
ba93b8ac
DJ		 8601/* Return the base VMA address which should be subtracted from real addresses
8602 when resolving @dtpoff relocation.
8603 This is PT_TLS segment p_vaddr. */
8604
8605static bfd_vma
8606dtpoff_base (struct bfd_link_info *info)
8607{
8608 /* If tls_sec is NULL, we should have signalled an error already. */
8609 if (elf_hash_table (info)->tls_sec == NULL)
8610 return 0;
8611 return elf_hash_table (info)->tls_sec->vma;
8612}
8613
8614/* Return the relocation value for @tpoff relocation
8615 if STT_TLS virtual address is ADDRESS. */
8616
8617static bfd_vma
8618tpoff (struct bfd_link_info *info, bfd_vma address)
8619{
8620 struct elf_link_hash_table *htab = elf_hash_table (info);
8621 bfd_vma base;
8622
8623 /* If tls_sec is NULL, we should have signalled an error already. */
8624 if (htab->tls_sec == NULL)
8625 return 0;
8626 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
8627 return address - htab->tls_sec->vma + base;
8628}
8629
00a97672
RS		 8630/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
8631 VALUE is the relocation value. */
8632
8633static bfd_reloc_status_type
8634elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
8635{
8636 if (value > 0xfff)
8637 return bfd_reloc_overflow;
8638
8639 value |= bfd_get_32 (abfd, data) & 0xfffff000;
8640 bfd_put_32 (abfd, value, data);
8641 return bfd_reloc_ok;
8642}
8643
0855e32b
NS		 8644/* Handle TLS relaxations. Relaxing is possible for symbols that use
8645 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
8646 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
8647
8648 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
8649 is to then call final_link_relocate. Return other values in the
62672b10
NS		 8650 case of error.
8651
8652 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
8653 the pre-relaxed code. It would be nice if the relocs were updated
8654 to match the optimization. */
0855e32b 8655
b38cadfb 8656static bfd_reloc_status_type
0855e32b 8657elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 8658 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 8659 Elf_Internal_Rela *rel, unsigned long is_local)
8660{
8661 unsigned long insn;
b38cadfb 8662
0855e32b
NS		 8663 switch (ELF32_R_TYPE (rel->r_info))
8664 {
8665 default:
8666 return bfd_reloc_notsupported;
b38cadfb 8667
0855e32b
NS		 8668 case R_ARM_TLS_GOTDESC:
8669 if (is_local)
8670 insn = 0;
8671 else
8672 {
8673 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8674 if (insn & 1)
8675 insn -= 5; /* THUMB */
8676 else
8677 insn -= 8; /* ARM */
8678 }
8679 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8680 return bfd_reloc_continue;
8681
8682 case R_ARM_THM_TLS_DESCSEQ:
8683 /* Thumb insn. */
8684 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
8685 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
8686 {
8687 if (is_local)
8688 /* nop */
8689 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8690 }
8691 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
8692 {
8693 if (is_local)
8694 /* nop */
8695 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8696 else
8697 /* ldr rx,[ry] */
8698 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
8699 }
8700 else if ((insn & 0xff87) == 0x4780) /* blx rx */
8701 {
8702 if (is_local)
8703 /* nop */
8704 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8705 else
8706 /* mov r0, rx */
8707 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
8708 contents + rel->r_offset);
8709 }
8710 else
8711 {
8712 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
8713 /* It's a 32 bit instruction, fetch the rest of it for
8714 error generation. */
8715 insn = (insn << 16)
8716 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
8717 (*_bfd_error_handler)
8718 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
8719 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8720 return bfd_reloc_notsupported;
8721 }
8722 break;
b38cadfb 8723
0855e32b
NS		 8724 case R_ARM_TLS_DESCSEQ:
8725 /* arm insn. */
8726 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8727 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
8728 {
8729 if (is_local)
8730 /* mov rx, ry */
8731 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
8732 contents + rel->r_offset);
8733 }
8734 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
8735 {
8736 if (is_local)
8737 /* nop */
8738 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8739 else
8740 /* ldr rx,[ry] */
8741 bfd_put_32 (input_bfd, insn & 0xfffff000,
8742 contents + rel->r_offset);
8743 }
8744 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
8745 {
8746 if (is_local)
8747 /* nop */
8748 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8749 else
8750 /* mov r0, rx */
8751 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
8752 contents + rel->r_offset);
8753 }
8754 else
8755 {
8756 (*_bfd_error_handler)
8757 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
8758 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8759 return bfd_reloc_notsupported;
8760 }
8761 break;
8762
8763 case R_ARM_TLS_CALL:
8764 /* GD->IE relaxation, turn the instruction into 'nop' or
8765 'ldr r0, [pc,r0]' */
8766 insn = is_local ? 0xe1a00000 : 0xe79f0000;
8767 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8768 break;
b38cadfb 8769
0855e32b 8770 case R_ARM_THM_TLS_CALL:
6a631e86 8771 /* GD->IE relaxation. */
0855e32b
NS		 8772 if (!is_local)
8773 /* add r0,pc; ldr r0, [r0] */
8774 insn = 0x44786800;
8775 else if (arch_has_thumb2_nop (globals))
8776 /* nop.w */
8777 insn = 0xf3af8000;
8778 else
8779 /* nop; nop */
8780 insn = 0xbf00bf00;
b38cadfb 8781
0855e32b
NS		 8782 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
8783 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
8784 break;
8785 }
8786 return bfd_reloc_ok;
8787}
8788
4962c51a
MS		 8789/* For a given value of n, calculate the value of G_n as required to
8790 deal with group relocations. We return it in the form of an
8791 encoded constant-and-rotation, together with the final residual. If n is
8792 specified as less than zero, then final_residual is filled with the
8793 input value and no further action is performed. */
8794
8795static bfd_vma
8796calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
8797{
8798 int current_n;
8799 bfd_vma g_n;
8800 bfd_vma encoded_g_n = 0;
8801 bfd_vma residual = value; /* Also known as Y_n. */
8802
8803 for (current_n = 0; current_n <= n; current_n++)
8804 {
8805 int shift;
8806
8807 /* Calculate which part of the value to mask. */
8808 if (residual == 0)
99059e56 8809 shift = 0;
4962c51a 8810 else
99059e56
RM		 8811 {
8812 int msb;
8813
8814 /* Determine the most significant bit in the residual and
8815 align the resulting value to a 2-bit boundary. */
8816 for (msb = 30; msb >= 0; msb -= 2)
8817 if (residual & (3 << msb))
8818 break;
8819
8820 /* The desired shift is now (msb - 6), or zero, whichever
8821 is the greater. */
8822 shift = msb - 6;
8823 if (shift < 0)
8824 shift = 0;
8825 }
4962c51a
MS		 8826
8827 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
8828 g_n = residual & (0xff << shift);
8829 encoded_g_n = (g_n >> shift)
99059e56 8830 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 8831
8832 /* Calculate the residual for the next time around. */
8833 residual &= ~g_n;
8834 }
8835
8836 *final_residual = residual;
8837
8838 return encoded_g_n;
8839}
8840
8841/* Given an ARM instruction, determine whether it is an ADD or a SUB.
8842 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 8843
4962c51a 8844static int
906e58ca 8845identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 8846{
8847 int opcode = insn & 0x1e00000;
8848
8849 if (opcode == 1 << 23) /* ADD */
8850 return 1;
8851
8852 if (opcode == 1 << 22) /* SUB */
8853 return -1;
8854
8855 return 0;
8856}
8857
252b5132 8858/* Perform a relocation as part of a final link. */
9b485d32 8859
252b5132 8860static bfd_reloc_status_type
57e8b36a
NC		 8861elf32_arm_final_link_relocate (reloc_howto_type * howto,
8862 bfd * input_bfd,
8863 bfd * output_bfd,
8864 asection * input_section,
8865 bfd_byte * contents,
8866 Elf_Internal_Rela * rel,
8867 bfd_vma value,
8868 struct bfd_link_info * info,
8869 asection * sym_sec,
8870 const char * sym_name,
34e77a92
RS		 8871 unsigned char st_type,
8872 enum arm_st_branch_type branch_type,
0945cdfd 8873 struct elf_link_hash_entry * h,
f2a9dd69 8874 bfd_boolean * unresolved_reloc_p,
8029a119 8875 char ** error_message)
252b5132
RH		 8876{
8877 unsigned long r_type = howto->type;
8878 unsigned long r_symndx;
8879 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 8880 bfd_vma * local_got_offsets;
0855e32b 8881 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 8882 asection * sgot;
8883 asection * splt;
252b5132 8884 asection * sreloc = NULL;
362d30a1 8885 asection * srelgot;
252b5132 8886 bfd_vma addend;
ba96a88f 8887 bfd_signed_vma signed_addend;
34e77a92
RS		 8888 unsigned char dynreloc_st_type;
8889 bfd_vma dynreloc_value;
ba96a88f 8890 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 8891 struct elf32_arm_link_hash_entry *eh;
8892 union gotplt_union *root_plt;
8893 struct arm_plt_info *arm_plt;
8894 bfd_vma plt_offset;
8895 bfd_vma gotplt_offset;
8896 bfd_boolean has_iplt_entry;
f21f3fe0 8897
9c504268 8898 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 8899 if (globals == NULL)
8900 return bfd_reloc_notsupported;
9c504268 8901
0ffa91dd
NC		 8902 BFD_ASSERT (is_arm_elf (input_bfd));
8903
8904 /* Some relocation types map to different relocations depending on the
9c504268 8905 target. We pick the right one here. */
eb043451 8906 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 8907
8908 /* It is possible to have linker relaxations on some TLS access
8909 models. Update our information here. */
8910 r_type = elf32_arm_tls_transition (info, r_type, h);
8911
eb043451
PB		 8912 if (r_type != howto->type)
8913 howto = elf32_arm_howto_from_type (r_type);
9c504268 8914
34e77a92 8915 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 8916 sgot = globals->root.sgot;
252b5132 8917 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 8918 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
8919
34e77a92
RS		 8920 if (globals->root.dynamic_sections_created)
8921 srelgot = globals->root.srelgot;
8922 else
8923 srelgot = NULL;
8924
252b5132
RH		 8925 r_symndx = ELF32_R_SYM (rel->r_info);
8926
4e7fd91e 8927 if (globals->use_rel)
ba96a88f 8928 {
4e7fd91e
PB		 8929 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
8930
8931 if (addend & ((howto->src_mask + 1) >> 1))
8932 {
8933 signed_addend = -1;
8934 signed_addend &= ~ howto->src_mask;
8935 signed_addend |= addend;
8936 }
8937 else
8938 signed_addend = addend;
ba96a88f
NC		 8939 }
8940 else
4e7fd91e 8941 addend = signed_addend = rel->r_addend;
f21f3fe0 8942
39f21624
NC		 8943 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
8944 are resolving a function call relocation. */
8945 if (using_thumb_only (globals)
8946 && (r_type == R_ARM_THM_CALL
8947 || r_type == R_ARM_THM_JUMP24)
8948 && branch_type == ST_BRANCH_TO_ARM)
8949 branch_type = ST_BRANCH_TO_THUMB;
8950
34e77a92
RS		 8951 /* Record the symbol information that should be used in dynamic
8952 relocations. */
8953 dynreloc_st_type = st_type;
8954 dynreloc_value = value;
8955 if (branch_type == ST_BRANCH_TO_THUMB)
8956 dynreloc_value |= 1;
8957
8958 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8959 VALUE appropriately for relocations that we resolve at link time. */
8960 has_iplt_entry = FALSE;
8961 if (elf32_arm_get_plt_info (input_bfd, eh, r_symndx, &root_plt, &arm_plt)
8962 && root_plt->offset != (bfd_vma) -1)
8963 {
8964 plt_offset = root_plt->offset;
8965 gotplt_offset = arm_plt->got_offset;
8966
8967 if (h == NULL || eh->is_iplt)
8968 {
8969 has_iplt_entry = TRUE;
8970 splt = globals->root.iplt;
8971
8972 /* Populate .iplt entries here, because not all of them will
8973 be seen by finish_dynamic_symbol. The lower bit is set if
8974 we have already populated the entry. */
8975 if (plt_offset & 1)
8976 plt_offset--;
8977 else
8978 {
57460bcf
NC		 8979 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
8980 -1, dynreloc_value))
8981 root_plt->offset |= 1;
8982 else
8983 return bfd_reloc_notsupported;
34e77a92
RS		 8984 }
8985
8986 /* Static relocations always resolve to the .iplt entry. */
8987 st_type = STT_FUNC;
8988 value = (splt->output_section->vma
8989 + splt->output_offset
8990 + plt_offset);
8991 branch_type = ST_BRANCH_TO_ARM;
8992
8993 /* If there are non-call relocations that resolve to the .iplt
8994 entry, then all dynamic ones must too. */
8995 if (arm_plt->noncall_refcount != 0)
8996 {
8997 dynreloc_st_type = st_type;
8998 dynreloc_value = value;
8999 }
9000 }
9001 else
9002 /* We populate the .plt entry in finish_dynamic_symbol. */
9003 splt = globals->root.splt;
9004 }
9005 else
9006 {
9007 splt = NULL;
9008 plt_offset = (bfd_vma) -1;
9009 gotplt_offset = (bfd_vma) -1;
9010 }
9011
252b5132
RH		 9012 switch (r_type)
9013 {
9014 case R_ARM_NONE:
28a094c2
DJ		 9015 /* We don't need to find a value for this symbol. It's just a
9016 marker. */
9017 *unresolved_reloc_p = FALSE;
252b5132
RH		 9018 return bfd_reloc_ok;
9019
00a97672
RS		 9020 case R_ARM_ABS12:
9021 if (!globals->vxworks_p)
9022 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9023
252b5132
RH		 9024 case R_ARM_PC24:
9025 case R_ARM_ABS32:
bb224fc3 9026 case R_ARM_ABS32_NOI:
252b5132 9027 case R_ARM_REL32:
bb224fc3 9028 case R_ARM_REL32_NOI:
5b5bb741
PB		 9029 case R_ARM_CALL:
9030 case R_ARM_JUMP24:
dfc5f959 9031 case R_ARM_XPC25:
eb043451 9032 case R_ARM_PREL31:
7359ea65 9033 case R_ARM_PLT32:
7359ea65
DJ		 9034 /* Handle relocations which should use the PLT entry. ABS32/REL32
9035 will use the symbol's value, which may point to a PLT entry, but we
9036 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 9037 branches in this object should go to it, except if the PLT is too
9038 far away, in which case a long branch stub should be inserted. */
bb224fc3 9039 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 9040 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 9041 && r_type != R_ARM_CALL
9042 && r_type != R_ARM_JUMP24
9043 && r_type != R_ARM_PLT32)
34e77a92 9044 && plt_offset != (bfd_vma) -1)
7359ea65 9045 {
34e77a92
RS		 9046 /* If we've created a .plt section, and assigned a PLT entry
9047 to this function, it must either be a STT_GNU_IFUNC reference
9048 or not be known to bind locally. In other cases, we should
9049 have cleared the PLT entry by now. */
9050 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 9051
9052 value = (splt->output_section->vma
9053 + splt->output_offset
34e77a92 9054 + plt_offset);
0945cdfd 9055 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 9056 return _bfd_final_link_relocate (howto, input_bfd, input_section,
9057 contents, rel->r_offset, value,
00a97672 9058 rel->r_addend);
7359ea65
DJ		 9059 }
9060
67687978
PB		 9061 /* When generating a shared object or relocatable executable, these
9062 relocations are copied into the output file to be resolved at
9063 run time. */
0e1862bb
L		 9064 if ((bfd_link_pic (info)
9065 || globals->root.is_relocatable_executable)
7359ea65 9066 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 9067 && !(globals->vxworks_p
3348747a
NS		 9068 && strcmp (input_section->output_section->name,
9069 ".tls_vars") == 0)
bb224fc3 9070 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 9071 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 9072 && !(input_bfd == globals->stub_bfd
9073 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 9074 && (h == NULL
9075 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
9076 || h->root.type != bfd_link_hash_undefweak)
9077 && r_type != R_ARM_PC24
5b5bb741
PB		 9078 && r_type != R_ARM_CALL
9079 && r_type != R_ARM_JUMP24
ee06dc07 9080 && r_type != R_ARM_PREL31
7359ea65 9081 && r_type != R_ARM_PLT32)
252b5132 9082 {
947216bf 9083 Elf_Internal_Rela outrel;
b34976b6 9084 bfd_boolean skip, relocate;
f21f3fe0 9085
52db4ec2
JW		 9086 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
9087 && !h->def_regular)
9088 {
9089 char *v = _("shared object");
9090
0e1862bb 9091 if (bfd_link_executable (info))
52db4ec2
JW		 9092 v = _("PIE executable");
9093
9094 (*_bfd_error_handler)
9095 (_("%B: relocation %s against external or undefined symbol `%s'"
9096 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
9097 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
9098 return bfd_reloc_notsupported;
9099 }
9100
0945cdfd
DJ		 9101 *unresolved_reloc_p = FALSE;
9102
34e77a92 9103 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 9104 {
83bac4b0
NC		 9105 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
9106 ! globals->use_rel);
f21f3fe0 9107
83bac4b0 9108 if (sreloc == NULL)
252b5132 9109 return bfd_reloc_notsupported;
252b5132 9110 }
f21f3fe0 9111
b34976b6
AM		 9112 skip = FALSE;
9113 relocate = FALSE;
f21f3fe0 9114
00a97672 9115 outrel.r_addend = addend;
c629eae0
JJ		 9116 outrel.r_offset =
9117 _bfd_elf_section_offset (output_bfd, info, input_section,
9118 rel->r_offset);
9119 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 9120 skip = TRUE;
0bb2d96a 9121 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 9122 skip = TRUE, relocate = TRUE;
252b5132
RH		 9123 outrel.r_offset += (input_section->output_section->vma
9124 + input_section->output_offset);
f21f3fe0 9125
252b5132 9126 if (skip)
0bb2d96a 9127 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 9128 else if (h != NULL
9129 && h->dynindx != -1
0e1862bb 9130 && (!bfd_link_pic (info)
a496fbc8 9131 || !SYMBOLIC_BIND (info, h)
f5385ebf 9132 || !h->def_regular))
5e681ec4 9133 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 9134 else
9135 {
a16385dc
MM		 9136 int symbol;
9137
5e681ec4 9138 /* This symbol is local, or marked to become local. */
34e77a92 9139 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 9140 if (globals->symbian_p)
6366ff1e 9141 {
74541ad4
AM		 9142 asection *osec;
9143
6366ff1e
MM		 9144 /* On Symbian OS, the data segment and text segement
9145 can be relocated independently. Therefore, we
9146 must indicate the segment to which this
9147 relocation is relative. The BPABI allows us to
9148 use any symbol in the right segment; we just use
9149 the section symbol as it is convenient. (We
9150 cannot use the symbol given by "h" directly as it
74541ad4
AM		 9151 will not appear in the dynamic symbol table.)
9152
9153 Note that the dynamic linker ignores the section
9154 symbol value, so we don't subtract osec->vma
9155 from the emitted reloc addend. */
10dbd1f3 9156 if (sym_sec)
74541ad4 9157 osec = sym_sec->output_section;
10dbd1f3 9158 else
74541ad4
AM		 9159 osec = input_section->output_section;
9160 symbol = elf_section_data (osec)->dynindx;
9161 if (symbol == 0)
9162 {
9163 struct elf_link_hash_table *htab = elf_hash_table (info);
9164
9165 if ((osec->flags & SEC_READONLY) == 0
9166 && htab->data_index_section != NULL)
9167 osec = htab->data_index_section;
9168 else
9169 osec = htab->text_index_section;
9170 symbol = elf_section_data (osec)->dynindx;
9171 }
6366ff1e
MM		 9172 BFD_ASSERT (symbol != 0);
9173 }
a16385dc
MM		 9174 else
9175 /* On SVR4-ish systems, the dynamic loader cannot
9176 relocate the text and data segments independently,
9177 so the symbol does not matter. */
9178 symbol = 0;
34e77a92
RS		 9179 if (dynreloc_st_type == STT_GNU_IFUNC)
9180 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9181 to the .iplt entry. Instead, every non-call reference
9182 must use an R_ARM_IRELATIVE relocation to obtain the
9183 correct run-time address. */
9184 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
9185 else
9186 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 9187 if (globals->use_rel)
9188 relocate = TRUE;
9189 else
34e77a92 9190 outrel.r_addend += dynreloc_value;
252b5132 9191 }
f21f3fe0 9192
47beaa6a 9193 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 9194
f21f3fe0 9195 /* If this reloc is against an external symbol, we do not want to
252b5132 9196 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 9197 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 9198 if (! relocate)
9199 return bfd_reloc_ok;
9a5aca8c 9200
f21f3fe0 9201 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 9202 contents, rel->r_offset,
9203 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 9204 }
9205 else switch (r_type)
9206 {
00a97672
RS		 9207 case R_ARM_ABS12:
9208 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9209
dfc5f959 9210 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 9211 case R_ARM_CALL:
9212 case R_ARM_JUMP24:
8029a119 9213 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 9214 case R_ARM_PLT32:
906e58ca 9215 {
906e58ca
NC		 9216 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
9217
dfc5f959 9218 if (r_type == R_ARM_XPC25)
252b5132 9219 {
dfc5f959
NC		 9220 /* Check for Arm calling Arm function. */
9221 /* FIXME: Should we translate the instruction into a BL
9222 instruction instead ? */
35fc36a8 9223 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 9224 (*_bfd_error_handler)
9225 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
9226 input_bfd,
9227 h ? h->root.root.string : "(local)");
dfc5f959 9228 }
155d87d7 9229 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 9230 {
9231 /* Check for Arm calling Thumb function. */
35fc36a8 9232 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 9233 {
f2a9dd69
DJ		 9234 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
9235 output_bfd, input_section,
9236 hit_data, sym_sec, rel->r_offset,
9237 signed_addend, value,
9238 error_message))
9239 return bfd_reloc_ok;
9240 else
9241 return bfd_reloc_dangerous;
dfc5f959 9242 }
252b5132 9243 }
ba96a88f 9244
906e58ca 9245 /* Check if a stub has to be inserted because the
8029a119 9246 destination is too far or we are changing mode. */
155d87d7
CL		 9247 if ( r_type == R_ARM_CALL
9248 || r_type == R_ARM_JUMP24
9249 || r_type == R_ARM_PLT32)
906e58ca 9250 {
fe33d2fa
CL		 9251 enum elf32_arm_stub_type stub_type = arm_stub_none;
9252 struct elf32_arm_link_hash_entry *hash;
9253
9254 hash = (struct elf32_arm_link_hash_entry *) h;
9255 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9256 st_type, &branch_type,
9257 hash, value, sym_sec,
fe33d2fa 9258 input_bfd, sym_name);
5fa9e92f 9259
fe33d2fa 9260 if (stub_type != arm_stub_none)
906e58ca
NC		 9261 {
9262 /* The target is out of reach, so redirect the
9263 branch to the local stub for this function. */
906e58ca
NC		 9264 stub_entry = elf32_arm_get_stub_entry (input_section,
9265 sym_sec, h,
fe33d2fa
CL		 9266 rel, globals,
9267 stub_type);
9cd3e4e5
NC		 9268 {
9269 if (stub_entry != NULL)
9270 value = (stub_entry->stub_offset
9271 + stub_entry->stub_sec->output_offset
9272 + stub_entry->stub_sec->output_section->vma);
9273
9274 if (plt_offset != (bfd_vma) -1)
9275 *unresolved_reloc_p = FALSE;
9276 }
906e58ca 9277 }
fe33d2fa
CL		 9278 else
9279 {
9280 /* If the call goes through a PLT entry, make sure to
9281 check distance to the right destination address. */
34e77a92 9282 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9283 {
9284 value = (splt->output_section->vma
9285 + splt->output_offset
34e77a92 9286 + plt_offset);
fe33d2fa
CL		 9287 *unresolved_reloc_p = FALSE;
9288 /* The PLT entry is in ARM mode, regardless of the
9289 target function. */
35fc36a8 9290 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9291 }
9292 }
906e58ca
NC		 9293 }
9294
dea514f5
PB		 9295 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9296 where:
9297 S is the address of the symbol in the relocation.
9298 P is address of the instruction being relocated.
9299 A is the addend (extracted from the instruction) in bytes.
9300
9301 S is held in 'value'.
9302 P is the base address of the section containing the
9303 instruction plus the offset of the reloc into that
9304 section, ie:
9305 (input_section->output_section->vma +
9306 input_section->output_offset +
9307 rel->r_offset).
9308 A is the addend, converted into bytes, ie:
9309 (signed_addend * 4)
9310
9311 Note: None of these operations have knowledge of the pipeline
9312 size of the processor, thus it is up to the assembler to
9313 encode this information into the addend. */
9314 value -= (input_section->output_section->vma
9315 + input_section->output_offset);
9316 value -= rel->r_offset;
4e7fd91e
PB		 9317 if (globals->use_rel)
9318 value += (signed_addend << howto->size);
9319 else
9320 /* RELA addends do not have to be adjusted by howto->size. */
9321 value += signed_addend;
23080146 9322
dcb5e6e6
NC		 9323 signed_addend = value;
9324 signed_addend >>= howto->rightshift;
9a5aca8c 9325
5ab79981 9326 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 9327 the next instruction unless a PLT entry will be created.
77b4f08f 9328 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 9329 The jump to the next instruction is optimized as a NOP depending
9330 on the architecture. */
ffcb4889 9331 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 9332 && plt_offset == (bfd_vma) -1)
77b4f08f 9333 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 9334 {
cd1dac3d
DG		 9335 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
9336
9337 if (arch_has_arm_nop (globals))
9338 value |= 0x0320f000;
9339 else
9340 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 9341 }
9342 else
59f2c4e7 9343 {
9b485d32 9344 /* Perform a signed range check. */
dcb5e6e6 9345 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 9346 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
9347 return bfd_reloc_overflow;
9a5aca8c 9348
5ab79981 9349 addend = (value & 2);
39b41c9c 9350
5ab79981
PB		 9351 value = (signed_addend & howto->dst_mask)
9352 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 9353
5ab79981
PB		 9354 if (r_type == R_ARM_CALL)
9355 {
155d87d7 9356 /* Set the H bit in the BLX instruction. */
35fc36a8 9357 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 9358 {
9359 if (addend)
9360 value |= (1 << 24);
9361 else
9362 value &= ~(bfd_vma)(1 << 24);
9363 }
9364
5ab79981 9365 /* Select the correct instruction (BL or BLX). */
906e58ca 9366 /* Only if we are not handling a BL to a stub. In this
8029a119 9367 case, mode switching is performed by the stub. */
35fc36a8 9368 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 9369 value |= (1 << 28);
63e1a0fc 9370 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 9371 {
9372 value &= ~(bfd_vma)(1 << 28);
9373 value |= (1 << 24);
9374 }
39b41c9c
PB		 9375 }
9376 }
906e58ca 9377 }
252b5132 9378 break;
f21f3fe0 9379
252b5132
RH		 9380 case R_ARM_ABS32:
9381 value += addend;
35fc36a8 9382 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 9383 value |= 1;
9384 break;
f21f3fe0 9385
bb224fc3
MS		 9386 case R_ARM_ABS32_NOI:
9387 value += addend;
9388 break;
9389
252b5132 9390 case R_ARM_REL32:
a8bc6c78 9391 value += addend;
35fc36a8 9392 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 9393 value |= 1;
252b5132 9394 value -= (input_section->output_section->vma
62efb346 9395 + input_section->output_offset + rel->r_offset);
252b5132 9396 break;
eb043451 9397
bb224fc3
MS		 9398 case R_ARM_REL32_NOI:
9399 value += addend;
9400 value -= (input_section->output_section->vma
9401 + input_section->output_offset + rel->r_offset);
9402 break;
9403
eb043451
PB		 9404 case R_ARM_PREL31:
9405 value -= (input_section->output_section->vma
9406 + input_section->output_offset + rel->r_offset);
9407 value += signed_addend;
9408 if (! h || h->root.type != bfd_link_hash_undefweak)
9409 {
8029a119 9410 /* Check for overflow. */
eb043451
PB		 9411 if ((value ^ (value >> 1)) & (1 << 30))
9412 return bfd_reloc_overflow;
9413 }
9414 value &= 0x7fffffff;
9415 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 9416 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 9417 value |= 1;
9418 break;
252b5132 9419 }
f21f3fe0 9420
252b5132
RH		 9421 bfd_put_32 (input_bfd, value, hit_data);
9422 return bfd_reloc_ok;
9423
9424 case R_ARM_ABS8:
fd0fd00c
MJ		 9425 /* PR 16202: Refectch the addend using the correct size. */
9426 if (globals->use_rel)
9427 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 9428 value += addend;
4e67d4ca
DG		 9429
9430 /* There is no way to tell whether the user intended to use a signed or
9431 unsigned addend. When checking for overflow we accept either,
9432 as specified by the AAELF. */
9433 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 9434 return bfd_reloc_overflow;
9435
9436 bfd_put_8 (input_bfd, value, hit_data);
9437 return bfd_reloc_ok;
9438
9439 case R_ARM_ABS16:
fd0fd00c
MJ		 9440 /* PR 16202: Refectch the addend using the correct size. */
9441 if (globals->use_rel)
9442 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 9443 value += addend;
9444
4e67d4ca
DG		 9445 /* See comment for R_ARM_ABS8. */
9446 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 9447 return bfd_reloc_overflow;
9448
9449 bfd_put_16 (input_bfd, value, hit_data);
9450 return bfd_reloc_ok;
9451
252b5132 9452 case R_ARM_THM_ABS5:
9b485d32 9453 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 9454 if (globals->use_rel)
9455 {
9456 /* Need to refetch addend. */
9457 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9458 /* ??? Need to determine shift amount from operand size. */
9459 addend >>= howto->rightshift;
9460 }
252b5132
RH		 9461 value += addend;
9462
9463 /* ??? Isn't value unsigned? */
9464 if ((long) value > 0x1f || (long) value < -0x10)
9465 return bfd_reloc_overflow;
9466
9467 /* ??? Value needs to be properly shifted into place first. */
9468 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
9469 bfd_put_16 (input_bfd, value, hit_data);
9470 return bfd_reloc_ok;
9471
2cab6cc3
MS		 9472 case R_ARM_THM_ALU_PREL_11_0:
9473 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
9474 {
9475 bfd_vma insn;
9476 bfd_signed_vma relocation;
9477
9478 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9479 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9480
99059e56
RM		 9481 if (globals->use_rel)
9482 {
9483 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
9484 | ((insn & (1 << 26)) >> 15);
9485 if (insn & 0xf00000)
9486 signed_addend = -signed_addend;
9487 }
2cab6cc3
MS		 9488
9489 relocation = value + signed_addend;
79f08007 9490 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9491 + input_section->output_offset
9492 + rel->r_offset);
2cab6cc3 9493
b6518b38 9494 value = relocation;
2cab6cc3 9495
99059e56
RM		 9496 if (value >= 0x1000)
9497 return bfd_reloc_overflow;
2cab6cc3
MS		 9498
9499 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 9500 | ((value & 0x700) << 4)
9501 | ((value & 0x800) << 15);
9502 if (relocation < 0)
9503 insn |= 0xa00000;
2cab6cc3
MS		 9504
9505 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9506 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9507
99059e56 9508 return bfd_reloc_ok;
2cab6cc3
MS		 9509 }
9510
e1ec24c6
NC		 9511 case R_ARM_THM_PC8:
9512 /* PR 10073: This reloc is not generated by the GNU toolchain,
9513 but it is supported for compatibility with third party libraries
9514 generated by other compilers, specifically the ARM/IAR. */
9515 {
9516 bfd_vma insn;
9517 bfd_signed_vma relocation;
9518
9519 insn = bfd_get_16 (input_bfd, hit_data);
9520
99059e56 9521 if (globals->use_rel)
79f08007 9522 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 9523
9524 relocation = value + addend;
79f08007 9525 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9526 + input_section->output_offset
9527 + rel->r_offset);
e1ec24c6 9528
b6518b38 9529 value = relocation;
e1ec24c6
NC		 9530
9531 /* We do not check for overflow of this reloc. Although strictly
9532 speaking this is incorrect, it appears to be necessary in order
9533 to work with IAR generated relocs. Since GCC and GAS do not
9534 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
9535 a problem for them. */
9536 value &= 0x3fc;
9537
9538 insn = (insn & 0xff00) | (value >> 2);
9539
9540 bfd_put_16 (input_bfd, insn, hit_data);
9541
99059e56 9542 return bfd_reloc_ok;
e1ec24c6
NC		 9543 }
9544
2cab6cc3
MS		 9545 case R_ARM_THM_PC12:
9546 /* Corresponds to: ldr.w reg, [pc, #offset]. */
9547 {
9548 bfd_vma insn;
9549 bfd_signed_vma relocation;
9550
9551 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9552 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9553
99059e56
RM		 9554 if (globals->use_rel)
9555 {
9556 signed_addend = insn & 0xfff;
9557 if (!(insn & (1 << 23)))
9558 signed_addend = -signed_addend;
9559 }
2cab6cc3
MS		 9560
9561 relocation = value + signed_addend;
79f08007 9562 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9563 + input_section->output_offset
9564 + rel->r_offset);
2cab6cc3 9565
b6518b38 9566 value = relocation;
2cab6cc3 9567
99059e56
RM		 9568 if (value >= 0x1000)
9569 return bfd_reloc_overflow;
2cab6cc3
MS		 9570
9571 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 9572 if (relocation >= 0)
9573 insn |= (1 << 23);
2cab6cc3
MS		 9574
9575 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9576 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9577
99059e56 9578 return bfd_reloc_ok;
2cab6cc3
MS		 9579 }
9580
dfc5f959 9581 case R_ARM_THM_XPC22:
c19d1205 9582 case R_ARM_THM_CALL:
bd97cb95 9583 case R_ARM_THM_JUMP24:
dfc5f959 9584 /* Thumb BL (branch long instruction). */
252b5132 9585 {
b34976b6 9586 bfd_vma relocation;
99059e56 9587 bfd_vma reloc_sign;
b34976b6
AM		 9588 bfd_boolean overflow = FALSE;
9589 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9590 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 9591 bfd_signed_vma reloc_signed_max;
9592 bfd_signed_vma reloc_signed_min;
b34976b6 9593 bfd_vma check;
252b5132 9594 bfd_signed_vma signed_check;
e95de063 9595 int bitsize;
cd1dac3d 9596 const int thumb2 = using_thumb2 (globals);
252b5132 9597
5ab79981 9598 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 9599 the next instruction unless a PLT entry will be created.
9600 The jump to the next instruction is optimized as a NOP.W for
9601 Thumb-2 enabled architectures. */
19540007 9602 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 9603 && plt_offset == (bfd_vma) -1)
5ab79981 9604 {
cd1dac3d
DG		 9605 if (arch_has_thumb2_nop (globals))
9606 {
9607 bfd_put_16 (input_bfd, 0xf3af, hit_data);
9608 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
9609 }
9610 else
9611 {
9612 bfd_put_16 (input_bfd, 0xe000, hit_data);
9613 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
9614 }
5ab79981
PB		 9615 return bfd_reloc_ok;
9616 }
9617
e95de063 9618 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 9619 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 9620 if (globals->use_rel)
9621 {
99059e56
RM		 9622 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
9623 bfd_vma upper = upper_insn & 0x3ff;
9624 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 9625 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
9626 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 9627 bfd_vma i1 = j1 ^ s ? 0 : 1;
9628 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 9629
99059e56
RM		 9630 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
9631 /* Sign extend. */
9632 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 9633
4e7fd91e
PB		 9634 signed_addend = addend;
9635 }
cb1afa5c 9636
dfc5f959
NC		 9637 if (r_type == R_ARM_THM_XPC22)
9638 {
9639 /* Check for Thumb to Thumb call. */
9640 /* FIXME: Should we translate the instruction into a BL
9641 instruction instead ? */
35fc36a8 9642 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 9643 (*_bfd_error_handler)
9644 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
9645 input_bfd,
9646 h ? h->root.root.string : "(local)");
dfc5f959
NC		 9647 }
9648 else
252b5132 9649 {
dfc5f959
NC		 9650 /* If it is not a call to Thumb, assume call to Arm.
9651 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 9652 function call at all, but rather a long jump. Calls through
9653 the PLT do not require stubs. */
34e77a92 9654 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 9655 {
bd97cb95 9656 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9657 {
9658 /* Convert BL to BLX. */
9659 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9660 }
155d87d7
CL		 9661 else if (( r_type != R_ARM_THM_CALL)
9662 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 9663 {
9664 if (elf32_thumb_to_arm_stub
9665 (info, sym_name, input_bfd, output_bfd, input_section,
9666 hit_data, sym_sec, rel->r_offset, signed_addend, value,
9667 error_message))
9668 return bfd_reloc_ok;
9669 else
9670 return bfd_reloc_dangerous;
9671 }
da5938a2 9672 }
35fc36a8
RS		 9673 else if (branch_type == ST_BRANCH_TO_THUMB
9674 && globals->use_blx
bd97cb95 9675 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9676 {
9677 /* Make sure this is a BL. */
9678 lower_insn |= 0x1800;
9679 }
252b5132 9680 }
f21f3fe0 9681
fe33d2fa 9682 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 9683 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 9684 {
9685 /* Check if a stub has to be inserted because the destination
8029a119 9686 is too far. */
fe33d2fa
CL		 9687 struct elf32_arm_stub_hash_entry *stub_entry;
9688 struct elf32_arm_link_hash_entry *hash;
9689
9690 hash = (struct elf32_arm_link_hash_entry *) h;
9691
9692 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9693 st_type, &branch_type,
9694 hash, value, sym_sec,
fe33d2fa
CL		 9695 input_bfd, sym_name);
9696
9697 if (stub_type != arm_stub_none)
906e58ca
NC		 9698 {
9699 /* The target is out of reach or we are changing modes, so
9700 redirect the branch to the local stub for this
9701 function. */
9702 stub_entry = elf32_arm_get_stub_entry (input_section,
9703 sym_sec, h,
fe33d2fa
CL		 9704 rel, globals,
9705 stub_type);
906e58ca 9706 if (stub_entry != NULL)
9cd3e4e5
NC		 9707 {
9708 value = (stub_entry->stub_offset
9709 + stub_entry->stub_sec->output_offset
9710 + stub_entry->stub_sec->output_section->vma);
9711
9712 if (plt_offset != (bfd_vma) -1)
9713 *unresolved_reloc_p = FALSE;
9714 }
906e58ca 9715
f4ac8484 9716 /* If this call becomes a call to Arm, force BLX. */
155d87d7 9717 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 9718 {
9719 if ((stub_entry
9720 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 9721 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 9722 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9723 }
906e58ca
NC		 9724 }
9725 }
9726
fe33d2fa 9727 /* Handle calls via the PLT. */
34e77a92 9728 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9729 {
9730 value = (splt->output_section->vma
9731 + splt->output_offset
34e77a92 9732 + plt_offset);
fe33d2fa 9733
eed94f8f
NC		 9734 if (globals->use_blx
9735 && r_type == R_ARM_THM_CALL
9736 && ! using_thumb_only (globals))
fe33d2fa
CL		 9737 {
9738 /* If the Thumb BLX instruction is available, convert
9739 the BL to a BLX instruction to call the ARM-mode
9740 PLT entry. */
9741 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 9742 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9743 }
9744 else
9745 {
eed94f8f
NC		 9746 if (! using_thumb_only (globals))
9747 /* Target the Thumb stub before the ARM PLT entry. */
9748 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 9749 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 9750 }
9751 *unresolved_reloc_p = FALSE;
9752 }
9753
ba96a88f 9754 relocation = value + signed_addend;
f21f3fe0 9755
252b5132 9756 relocation -= (input_section->output_section->vma
ba96a88f
NC		 9757 + input_section->output_offset
9758 + rel->r_offset);
9a5aca8c 9759
252b5132
RH		 9760 check = relocation >> howto->rightshift;
9761
9762 /* If this is a signed value, the rightshift just dropped
9763 leading 1 bits (assuming twos complement). */
9764 if ((bfd_signed_vma) relocation >= 0)
9765 signed_check = check;
9766 else
9767 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
9768
e95de063
MS		 9769 /* Calculate the permissable maximum and minimum values for
9770 this relocation according to whether we're relocating for
9771 Thumb-2 or not. */
9772 bitsize = howto->bitsize;
9773 if (!thumb2)
9774 bitsize -= 2;
f6ebfac0 9775 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 9776 reloc_signed_min = ~reloc_signed_max;
9777
252b5132 9778 /* Assumes two's complement. */
ba96a88f 9779 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 9780 overflow = TRUE;
252b5132 9781
bd97cb95 9782 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 9783 /* For a BLX instruction, make sure that the relocation is rounded up
9784 to a word boundary. This follows the semantics of the instruction
9785 which specifies that bit 1 of the target address will come from bit
9786 1 of the base address. */
9787 relocation = (relocation + 2) & ~ 3;
cb1afa5c 9788
e95de063
MS		 9789 /* Put RELOCATION back into the insn. Assumes two's complement.
9790 We use the Thumb-2 encoding, which is safe even if dealing with
9791 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 9792 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 9793 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 9794 | ((relocation >> 12) & 0x3ff)
9795 | (reloc_sign << 10);
906e58ca 9796 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 9797 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
9798 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
9799 | ((relocation >> 1) & 0x7ff);
c62e1cc3 9800
252b5132
RH		 9801 /* Put the relocated value back in the object file: */
9802 bfd_put_16 (input_bfd, upper_insn, hit_data);
9803 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9804
9805 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9806 }
9807 break;
9808
c19d1205
ZW		 9809 case R_ARM_THM_JUMP19:
9810 /* Thumb32 conditional branch instruction. */
9811 {
9812 bfd_vma relocation;
9813 bfd_boolean overflow = FALSE;
9814 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9815 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 9816 bfd_signed_vma reloc_signed_max = 0xffffe;
9817 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 9818 bfd_signed_vma signed_check;
c5423981
TG		 9819 enum elf32_arm_stub_type stub_type = arm_stub_none;
9820 struct elf32_arm_stub_hash_entry *stub_entry;
9821 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 9822
9823 /* Need to refetch the addend, reconstruct the top three bits,
9824 and squish the two 11 bit pieces together. */
9825 if (globals->use_rel)
9826 {
9827 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 9828 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 9829 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
9830 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
9831 bfd_vma lower = (lower_insn & 0x07ff);
9832
a00a1f35
MS		 9833 upper |= J1 << 6;
9834 upper |= J2 << 7;
9835 upper |= (!S) << 8;
c19d1205
ZW		 9836 upper -= 0x0100; /* Sign extend. */
9837
9838 addend = (upper << 12) | (lower << 1);
9839 signed_addend = addend;
9840 }
9841
bd97cb95 9842 /* Handle calls via the PLT. */
34e77a92 9843 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 9844 {
9845 value = (splt->output_section->vma
9846 + splt->output_offset
34e77a92 9847 + plt_offset);
bd97cb95
DJ		 9848 /* Target the Thumb stub before the ARM PLT entry. */
9849 value -= PLT_THUMB_STUB_SIZE;
9850 *unresolved_reloc_p = FALSE;
9851 }
9852
c5423981
TG		 9853 hash = (struct elf32_arm_link_hash_entry *)h;
9854
9855 stub_type = arm_type_of_stub (info, input_section, rel,
9856 st_type, &branch_type,
9857 hash, value, sym_sec,
9858 input_bfd, sym_name);
9859 if (stub_type != arm_stub_none)
9860 {
9861 stub_entry = elf32_arm_get_stub_entry (input_section,
9862 sym_sec, h,
9863 rel, globals,
9864 stub_type);
9865 if (stub_entry != NULL)
9866 {
9867 value = (stub_entry->stub_offset
9868 + stub_entry->stub_sec->output_offset
9869 + stub_entry->stub_sec->output_section->vma);
9870 }
9871 }
c19d1205 9872
99059e56 9873 relocation = value + signed_addend;
c19d1205
ZW		 9874 relocation -= (input_section->output_section->vma
9875 + input_section->output_offset
9876 + rel->r_offset);
a00a1f35 9877 signed_check = (bfd_signed_vma) relocation;
c19d1205 9878
c19d1205
ZW		 9879 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9880 overflow = TRUE;
9881
9882 /* Put RELOCATION back into the insn. */
9883 {
9884 bfd_vma S = (relocation & 0x00100000) >> 20;
9885 bfd_vma J2 = (relocation & 0x00080000) >> 19;
9886 bfd_vma J1 = (relocation & 0x00040000) >> 18;
9887 bfd_vma hi = (relocation & 0x0003f000) >> 12;
9888 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
9889
a00a1f35 9890 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 9891 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
9892 }
9893
9894 /* Put the relocated value back in the object file: */
9895 bfd_put_16 (input_bfd, upper_insn, hit_data);
9896 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9897
9898 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9899 }
9900
9901 case R_ARM_THM_JUMP11:
9902 case R_ARM_THM_JUMP8:
9903 case R_ARM_THM_JUMP6:
51c5503b
NC		 9904 /* Thumb B (branch) instruction). */
9905 {
6cf9e9fe 9906 bfd_signed_vma relocation;
51c5503b
NC		 9907 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
9908 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 9909 bfd_signed_vma signed_check;
9910
c19d1205
ZW		 9911 /* CZB cannot jump backward. */
9912 if (r_type == R_ARM_THM_JUMP6)
9913 reloc_signed_min = 0;
9914
4e7fd91e 9915 if (globals->use_rel)
6cf9e9fe 9916 {
4e7fd91e
PB		 9917 /* Need to refetch addend. */
9918 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9919 if (addend & ((howto->src_mask + 1) >> 1))
9920 {
9921 signed_addend = -1;
9922 signed_addend &= ~ howto->src_mask;
9923 signed_addend |= addend;
9924 }
9925 else
9926 signed_addend = addend;
9927 /* The value in the insn has been right shifted. We need to
9928 undo this, so that we can perform the address calculation
9929 in terms of bytes. */
9930 signed_addend <<= howto->rightshift;
6cf9e9fe 9931 }
6cf9e9fe 9932 relocation = value + signed_addend;
51c5503b
NC		 9933
9934 relocation -= (input_section->output_section->vma
9935 + input_section->output_offset
9936 + rel->r_offset);
9937
6cf9e9fe
NC		 9938 relocation >>= howto->rightshift;
9939 signed_check = relocation;
c19d1205
ZW		 9940
9941 if (r_type == R_ARM_THM_JUMP6)
9942 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
9943 else
9944 relocation &= howto->dst_mask;
51c5503b 9945 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 9946
51c5503b
NC		 9947 bfd_put_16 (input_bfd, relocation, hit_data);
9948
9949 /* Assumes two's complement. */
9950 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9951 return bfd_reloc_overflow;
9952
9953 return bfd_reloc_ok;
9954 }
cedb70c5 9955
8375c36b
PB		 9956 case R_ARM_ALU_PCREL7_0:
9957 case R_ARM_ALU_PCREL15_8:
9958 case R_ARM_ALU_PCREL23_15:
9959 {
9960 bfd_vma insn;
9961 bfd_vma relocation;
9962
9963 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 9964 if (globals->use_rel)
9965 {
9966 /* Extract the addend. */
9967 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
9968 signed_addend = addend;
9969 }
8375c36b
PB		 9970 relocation = value + signed_addend;
9971
9972 relocation -= (input_section->output_section->vma
9973 + input_section->output_offset
9974 + rel->r_offset);
9975 insn = (insn & ~0xfff)
9976 | ((howto->bitpos << 7) & 0xf00)
9977 | ((relocation >> howto->bitpos) & 0xff);
9978 bfd_put_32 (input_bfd, value, hit_data);
9979 }
9980 return bfd_reloc_ok;
9981
252b5132
RH		 9982 case R_ARM_GNU_VTINHERIT:
9983 case R_ARM_GNU_VTENTRY:
9984 return bfd_reloc_ok;
9985
c19d1205 9986 case R_ARM_GOTOFF32:
252b5132 9987 /* Relocation is relative to the start of the
99059e56 9988 global offset table. */
252b5132
RH		 9989
9990 BFD_ASSERT (sgot != NULL);
9991 if (sgot == NULL)
99059e56 9992 return bfd_reloc_notsupported;
9a5aca8c 9993
cedb70c5 9994 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 9995 address by one, so that attempts to call the function pointer will
9996 correctly interpret it as Thumb code. */
35fc36a8 9997 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 9998 value += 1;
9999
252b5132 10000 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 10001 calculation. We always want the start of .got. If we
10002 define _GLOBAL_OFFSET_TABLE in a different way, as is
10003 permitted by the ABI, we might have to change this
10004 calculation. */
252b5132 10005 value -= sgot->output_section->vma;
f21f3fe0 10006 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10007 contents, rel->r_offset, value,
00a97672 10008 rel->r_addend);
252b5132
RH		 10009
10010 case R_ARM_GOTPC:
a7c10850 10011 /* Use global offset table as symbol value. */
252b5132 10012 BFD_ASSERT (sgot != NULL);
f21f3fe0 10013
252b5132 10014 if (sgot == NULL)
99059e56 10015 return bfd_reloc_notsupported;
252b5132 10016
0945cdfd 10017 *unresolved_reloc_p = FALSE;
252b5132 10018 value = sgot->output_section->vma;
f21f3fe0 10019 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10020 contents, rel->r_offset, value,
00a97672 10021 rel->r_addend);
f21f3fe0 10022
252b5132 10023 case R_ARM_GOT32:
eb043451 10024 case R_ARM_GOT_PREL:
252b5132 10025 /* Relocation is to the entry for this symbol in the
99059e56 10026 global offset table. */
252b5132
RH		 10027 if (sgot == NULL)
10028 return bfd_reloc_notsupported;
f21f3fe0 10029
34e77a92
RS		 10030 if (dynreloc_st_type == STT_GNU_IFUNC
10031 && plt_offset != (bfd_vma) -1
10032 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
10033 {
10034 /* We have a relocation against a locally-binding STT_GNU_IFUNC
10035 symbol, and the relocation resolves directly to the runtime
10036 target rather than to the .iplt entry. This means that any
10037 .got entry would be the same value as the .igot.plt entry,
10038 so there's no point creating both. */
10039 sgot = globals->root.igotplt;
10040 value = sgot->output_offset + gotplt_offset;
10041 }
10042 else if (h != NULL)
252b5132
RH		 10043 {
10044 bfd_vma off;
f21f3fe0 10045
252b5132
RH		 10046 off = h->got.offset;
10047 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 10048 if ((off & 1) != 0)
252b5132 10049 {
b436d854
RS		 10050 /* We have already processsed one GOT relocation against
10051 this symbol. */
10052 off &= ~1;
10053 if (globals->root.dynamic_sections_created
10054 && !SYMBOL_REFERENCES_LOCAL (info, h))
10055 *unresolved_reloc_p = FALSE;
10056 }
10057 else
10058 {
10059 Elf_Internal_Rela outrel;
10060
6f820c85 10061 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 10062 {
10063 /* If the symbol doesn't resolve locally in a static
10064 object, we have an undefined reference. If the
10065 symbol doesn't resolve locally in a dynamic object,
10066 it should be resolved by the dynamic linker. */
10067 if (globals->root.dynamic_sections_created)
10068 {
10069 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
10070 *unresolved_reloc_p = FALSE;
10071 }
10072 else
10073 outrel.r_info = 0;
10074 outrel.r_addend = 0;
10075 }
252b5132
RH		 10076 else
10077 {
34e77a92 10078 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10079 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 10080 else if (bfd_link_pic (info) &&
31943882
WN		 10081 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10082 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 10083 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
10084 else
10085 outrel.r_info = 0;
34e77a92 10086 outrel.r_addend = dynreloc_value;
b436d854 10087 }
ee29b9fb 10088
b436d854
RS		 10089 /* The GOT entry is initialized to zero by default.
10090 See if we should install a different value. */
10091 if (outrel.r_addend != 0
10092 && (outrel.r_info == 0 || globals->use_rel))
10093 {
10094 bfd_put_32 (output_bfd, outrel.r_addend,
10095 sgot->contents + off);
10096 outrel.r_addend = 0;
252b5132 10097 }
f21f3fe0 10098
b436d854
RS		 10099 if (outrel.r_info != 0)
10100 {
10101 outrel.r_offset = (sgot->output_section->vma
10102 + sgot->output_offset
10103 + off);
10104 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
10105 }
10106 h->got.offset |= 1;
10107 }
252b5132
RH		 10108 value = sgot->output_offset + off;
10109 }
10110 else
10111 {
10112 bfd_vma off;
f21f3fe0 10113
252b5132
RH		 10114 BFD_ASSERT (local_got_offsets != NULL &&
10115 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 10116
252b5132 10117 off = local_got_offsets[r_symndx];
f21f3fe0 10118
252b5132
RH		 10119 /* The offset must always be a multiple of 4. We use the
10120 least significant bit to record whether we have already
9b485d32 10121 generated the necessary reloc. */
252b5132
RH		 10122 if ((off & 1) != 0)
10123 off &= ~1;
10124 else
10125 {
00a97672 10126 if (globals->use_rel)
34e77a92 10127 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 10128
0e1862bb 10129 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 10130 {
947216bf 10131 Elf_Internal_Rela outrel;
f21f3fe0 10132
34e77a92 10133 outrel.r_addend = addend + dynreloc_value;
252b5132 10134 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 10135 + sgot->output_offset
252b5132 10136 + off);
34e77a92 10137 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10138 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 10139 else
10140 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 10141 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 10142 }
f21f3fe0 10143
252b5132
RH		 10144 local_got_offsets[r_symndx] |= 1;
10145 }
f21f3fe0 10146
252b5132
RH		 10147 value = sgot->output_offset + off;
10148 }
eb043451
PB		 10149 if (r_type != R_ARM_GOT32)
10150 value += sgot->output_section->vma;
9a5aca8c 10151
f21f3fe0 10152 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10153 contents, rel->r_offset, value,
00a97672 10154 rel->r_addend);
f21f3fe0 10155
ba93b8ac
DJ		 10156 case R_ARM_TLS_LDO32:
10157 value = value - dtpoff_base (info);
10158
10159 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10160 contents, rel->r_offset, value,
10161 rel->r_addend);
ba93b8ac
DJ		 10162
10163 case R_ARM_TLS_LDM32:
10164 {
10165 bfd_vma off;
10166
362d30a1 10167 if (sgot == NULL)
ba93b8ac
DJ		 10168 abort ();
10169
10170 off = globals->tls_ldm_got.offset;
10171
10172 if ((off & 1) != 0)
10173 off &= ~1;
10174 else
10175 {
10176 /* If we don't know the module number, create a relocation
10177 for it. */
0e1862bb 10178 if (bfd_link_pic (info))
ba93b8ac
DJ		 10179 {
10180 Elf_Internal_Rela outrel;
ba93b8ac 10181
362d30a1 10182 if (srelgot == NULL)
ba93b8ac
DJ		 10183 abort ();
10184
00a97672 10185 outrel.r_addend = 0;
362d30a1
RS		 10186 outrel.r_offset = (sgot->output_section->vma
10187 + sgot->output_offset + off);
ba93b8ac
DJ		 10188 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
10189
00a97672
RS		 10190 if (globals->use_rel)
10191 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10192 sgot->contents + off);
ba93b8ac 10193
47beaa6a 10194 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10195 }
10196 else
362d30a1 10197 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 10198
10199 globals->tls_ldm_got.offset |= 1;
10200 }
10201
362d30a1 10202 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 10203 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
10204
10205 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10206 contents, rel->r_offset, value,
00a97672 10207 rel->r_addend);
ba93b8ac
DJ		 10208 }
10209
0855e32b
NS		 10210 case R_ARM_TLS_CALL:
10211 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 10212 case R_ARM_TLS_GD32:
10213 case R_ARM_TLS_IE32:
0855e32b
NS		 10214 case R_ARM_TLS_GOTDESC:
10215 case R_ARM_TLS_DESCSEQ:
10216 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 10217 {
0855e32b
NS		 10218 bfd_vma off, offplt;
10219 int indx = 0;
ba93b8ac
DJ		 10220 char tls_type;
10221
0855e32b 10222 BFD_ASSERT (sgot != NULL);
ba93b8ac 10223
ba93b8ac
DJ		 10224 if (h != NULL)
10225 {
10226 bfd_boolean dyn;
10227 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 10228 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
10229 bfd_link_pic (info),
10230 h)
10231 && (!bfd_link_pic (info)
ba93b8ac
DJ		 10232 || !SYMBOL_REFERENCES_LOCAL (info, h)))
10233 {
10234 *unresolved_reloc_p = FALSE;
10235 indx = h->dynindx;
10236 }
10237 off = h->got.offset;
0855e32b 10238 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 10239 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
10240 }
10241 else
10242 {
0855e32b 10243 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 10244 off = local_got_offsets[r_symndx];
0855e32b 10245 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 10246 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
10247 }
10248
0855e32b 10249 /* Linker relaxations happens from one of the
b38cadfb 10250 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 10251 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 10252 tls_type = GOT_TLS_IE;
0855e32b
NS		 10253
10254 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 10255
10256 if ((off & 1) != 0)
10257 off &= ~1;
10258 else
10259 {
10260 bfd_boolean need_relocs = FALSE;
10261 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 10262 int cur_off = off;
10263
10264 /* The GOT entries have not been initialized yet. Do it
10265 now, and emit any relocations. If both an IE GOT and a
10266 GD GOT are necessary, we emit the GD first. */
10267
0e1862bb 10268 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 10269 && (h == NULL
10270 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10271 || h->root.type != bfd_link_hash_undefweak))
10272 {
10273 need_relocs = TRUE;
0855e32b 10274 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 10275 }
10276
0855e32b
NS		 10277 if (tls_type & GOT_TLS_GDESC)
10278 {
47beaa6a
RS		 10279 bfd_byte *loc;
10280
0855e32b
NS		 10281 /* We should have relaxed, unless this is an undefined
10282 weak symbol. */
10283 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 10284 || bfd_link_pic (info));
0855e32b 10285 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 10286 <= globals->root.sgotplt->size);
0855e32b
NS		 10287
10288 outrel.r_addend = 0;
10289 outrel.r_offset = (globals->root.sgotplt->output_section->vma
10290 + globals->root.sgotplt->output_offset
10291 + offplt
10292 + globals->sgotplt_jump_table_size);
b38cadfb 10293
0855e32b
NS		 10294 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
10295 sreloc = globals->root.srelplt;
10296 loc = sreloc->contents;
10297 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
10298 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 10299 <= sreloc->contents + sreloc->size);
0855e32b
NS		 10300
10301 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
10302
10303 /* For globals, the first word in the relocation gets
10304 the relocation index and the top bit set, or zero,
10305 if we're binding now. For locals, it gets the
10306 symbol's offset in the tls section. */
99059e56 10307 bfd_put_32 (output_bfd,
0855e32b
NS		 10308 !h ? value - elf_hash_table (info)->tls_sec->vma
10309 : info->flags & DF_BIND_NOW ? 0
10310 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 10311 globals->root.sgotplt->contents + offplt
10312 + globals->sgotplt_jump_table_size);
10313
0855e32b 10314 /* Second word in the relocation is always zero. */
99059e56 10315 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 10316 globals->root.sgotplt->contents + offplt
10317 + globals->sgotplt_jump_table_size + 4);
0855e32b 10318 }
ba93b8ac
DJ		 10319 if (tls_type & GOT_TLS_GD)
10320 {
10321 if (need_relocs)
10322 {
00a97672 10323 outrel.r_addend = 0;
362d30a1
RS		 10324 outrel.r_offset = (sgot->output_section->vma
10325 + sgot->output_offset
00a97672 10326 + cur_off);
ba93b8ac 10327 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 10328
00a97672
RS		 10329 if (globals->use_rel)
10330 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10331 sgot->contents + cur_off);
00a97672 10332
47beaa6a 10333 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10334
10335 if (indx == 0)
10336 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10337 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10338 else
10339 {
00a97672 10340 outrel.r_addend = 0;
ba93b8ac
DJ		 10341 outrel.r_info = ELF32_R_INFO (indx,
10342 R_ARM_TLS_DTPOFF32);
10343 outrel.r_offset += 4;
00a97672
RS		 10344
10345 if (globals->use_rel)
10346 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10347 sgot->contents + cur_off + 4);
00a97672 10348
47beaa6a
RS		 10349 elf32_arm_add_dynreloc (output_bfd, info,
10350 srelgot, &outrel);
ba93b8ac
DJ		 10351 }
10352 }
10353 else
10354 {
10355 /* If we are not emitting relocations for a
10356 general dynamic reference, then we must be in a
10357 static link or an executable link with the
10358 symbol binding locally. Mark it as belonging
10359 to module 1, the executable. */
10360 bfd_put_32 (output_bfd, 1,
362d30a1 10361 sgot->contents + cur_off);
ba93b8ac 10362 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10363 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10364 }
10365
10366 cur_off += 8;
10367 }
10368
10369 if (tls_type & GOT_TLS_IE)
10370 {
10371 if (need_relocs)
10372 {
00a97672
RS		 10373 if (indx == 0)
10374 outrel.r_addend = value - dtpoff_base (info);
10375 else
10376 outrel.r_addend = 0;
362d30a1
RS		 10377 outrel.r_offset = (sgot->output_section->vma
10378 + sgot->output_offset
ba93b8ac
DJ		 10379 + cur_off);
10380 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
10381
00a97672
RS		 10382 if (globals->use_rel)
10383 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10384 sgot->contents + cur_off);
ba93b8ac 10385
47beaa6a 10386 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10387 }
10388 else
10389 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 10390 sgot->contents + cur_off);
ba93b8ac
DJ		 10391 cur_off += 4;
10392 }
10393
10394 if (h != NULL)
10395 h->got.offset |= 1;
10396 else
10397 local_got_offsets[r_symndx] |= 1;
10398 }
10399
10400 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
10401 off += 8;
0855e32b
NS		 10402 else if (tls_type & GOT_TLS_GDESC)
10403 off = offplt;
10404
10405 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
10406 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
10407 {
10408 bfd_signed_vma offset;
12352d3f
PB		 10409 /* TLS stubs are arm mode. The original symbol is a
10410 data object, so branch_type is bogus. */
10411 branch_type = ST_BRANCH_TO_ARM;
0855e32b 10412 enum elf32_arm_stub_type stub_type
34e77a92
RS		 10413 = arm_type_of_stub (info, input_section, rel,
10414 st_type, &branch_type,
0855e32b
NS		 10415 (struct elf32_arm_link_hash_entry *)h,
10416 globals->tls_trampoline, globals->root.splt,
10417 input_bfd, sym_name);
10418
10419 if (stub_type != arm_stub_none)
10420 {
10421 struct elf32_arm_stub_hash_entry *stub_entry
10422 = elf32_arm_get_stub_entry
10423 (input_section, globals->root.splt, 0, rel,
10424 globals, stub_type);
10425 offset = (stub_entry->stub_offset
10426 + stub_entry->stub_sec->output_offset
10427 + stub_entry->stub_sec->output_section->vma);
10428 }
10429 else
10430 offset = (globals->root.splt->output_section->vma
10431 + globals->root.splt->output_offset
10432 + globals->tls_trampoline);
10433
10434 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
10435 {
10436 unsigned long inst;
b38cadfb
NC		 10437
10438 offset -= (input_section->output_section->vma
10439 + input_section->output_offset
10440 + rel->r_offset + 8);
0855e32b
NS		 10441
10442 inst = offset >> 2;
10443 inst &= 0x00ffffff;
10444 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
10445 }
10446 else
10447 {
10448 /* Thumb blx encodes the offset in a complicated
10449 fashion. */
10450 unsigned upper_insn, lower_insn;
10451 unsigned neg;
10452
b38cadfb
NC		 10453 offset -= (input_section->output_section->vma
10454 + input_section->output_offset
0855e32b 10455 + rel->r_offset + 4);
b38cadfb 10456
12352d3f
PB		 10457 if (stub_type != arm_stub_none
10458 && arm_stub_is_thumb (stub_type))
10459 {
10460 lower_insn = 0xd000;
10461 }
10462 else
10463 {
10464 lower_insn = 0xc000;
6a631e86 10465 /* Round up the offset to a word boundary. */
12352d3f
PB		 10466 offset = (offset + 2) & ~2;
10467 }
10468
0855e32b
NS		 10469 neg = offset < 0;
10470 upper_insn = (0xf000
10471 | ((offset >> 12) & 0x3ff)
10472 | (neg << 10));
12352d3f 10473 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 10474 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 10475 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 10476 bfd_put_16 (input_bfd, upper_insn, hit_data);
10477 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10478 return bfd_reloc_ok;
10479 }
10480 }
10481 /* These relocations needs special care, as besides the fact
10482 they point somewhere in .gotplt, the addend must be
10483 adjusted accordingly depending on the type of instruction
6a631e86 10484 we refer to. */
0855e32b
NS		 10485 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
10486 {
10487 unsigned long data, insn;
10488 unsigned thumb;
b38cadfb 10489
0855e32b
NS		 10490 data = bfd_get_32 (input_bfd, hit_data);
10491 thumb = data & 1;
10492 data &= ~1u;
b38cadfb 10493
0855e32b
NS		 10494 if (thumb)
10495 {
10496 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
10497 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10498 insn = (insn << 16)
10499 | bfd_get_16 (input_bfd,
10500 contents + rel->r_offset - data + 2);
10501 if ((insn & 0xf800c000) == 0xf000c000)
10502 /* bl/blx */
10503 value = -6;
10504 else if ((insn & 0xffffff00) == 0x4400)
10505 /* add */
10506 value = -5;
10507 else
10508 {
10509 (*_bfd_error_handler)
10510 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
10511 input_bfd, input_section,
10512 (unsigned long)rel->r_offset, insn);
10513 return bfd_reloc_notsupported;
10514 }
10515 }
10516 else
10517 {
10518 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
10519
10520 switch (insn >> 24)
10521 {
10522 case 0xeb: /* bl */
10523 case 0xfa: /* blx */
10524 value = -4;
10525 break;
10526
10527 case 0xe0: /* add */
10528 value = -8;
10529 break;
b38cadfb 10530
0855e32b
NS		 10531 default:
10532 (*_bfd_error_handler)
10533 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
10534 input_bfd, input_section,
10535 (unsigned long)rel->r_offset, insn);
10536 return bfd_reloc_notsupported;
10537 }
10538 }
b38cadfb 10539
0855e32b
NS		 10540 value += ((globals->root.sgotplt->output_section->vma
10541 + globals->root.sgotplt->output_offset + off)
10542 - (input_section->output_section->vma
10543 + input_section->output_offset
10544 + rel->r_offset)
10545 + globals->sgotplt_jump_table_size);
10546 }
10547 else
10548 value = ((globals->root.sgot->output_section->vma
10549 + globals->root.sgot->output_offset + off)
10550 - (input_section->output_section->vma
10551 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 10552
10553 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10554 contents, rel->r_offset, value,
00a97672 10555 rel->r_addend);
ba93b8ac
DJ		 10556 }
10557
10558 case R_ARM_TLS_LE32:
3cbc1e5e 10559 if (bfd_link_dll (info))
ba93b8ac
DJ		 10560 {
10561 (*_bfd_error_handler)
10562 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
10563 input_bfd, input_section,
10564 (long) rel->r_offset, howto->name);
46691134 10565 return bfd_reloc_notsupported;
ba93b8ac
DJ		 10566 }
10567 else
10568 value = tpoff (info, value);
906e58ca 10569
ba93b8ac 10570 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10571 contents, rel->r_offset, value,
10572 rel->r_addend);
ba93b8ac 10573
319850b4
JB		 10574 case R_ARM_V4BX:
10575 if (globals->fix_v4bx)
845b51d6
PB		 10576 {
10577 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 10578
845b51d6
PB		 10579 /* Ensure that we have a BX instruction. */
10580 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 10581
845b51d6
PB		 10582 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
10583 {
10584 /* Branch to veneer. */
10585 bfd_vma glue_addr;
10586 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
10587 glue_addr -= input_section->output_section->vma
10588 + input_section->output_offset
10589 + rel->r_offset + 8;
10590 insn = (insn & 0xf0000000) | 0x0a000000
10591 | ((glue_addr >> 2) & 0x00ffffff);
10592 }
10593 else
10594 {
10595 /* Preserve Rm (lowest four bits) and the condition code
10596 (highest four bits). Other bits encode MOV PC,Rm. */
10597 insn = (insn & 0xf000000f) | 0x01a0f000;
10598 }
319850b4 10599
845b51d6
PB		 10600 bfd_put_32 (input_bfd, insn, hit_data);
10601 }
319850b4
JB		 10602 return bfd_reloc_ok;
10603
b6895b4f
PB		 10604 case R_ARM_MOVW_ABS_NC:
10605 case R_ARM_MOVT_ABS:
10606 case R_ARM_MOVW_PREL_NC:
10607 case R_ARM_MOVT_PREL:
92f5d02b
MS		 10608 /* Until we properly support segment-base-relative addressing then
10609 we assume the segment base to be zero, as for the group relocations.
10610 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
10611 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
10612 case R_ARM_MOVW_BREL_NC:
10613 case R_ARM_MOVW_BREL:
10614 case R_ARM_MOVT_BREL:
b6895b4f
PB		 10615 {
10616 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
10617
10618 if (globals->use_rel)
10619 {
10620 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 10621 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10622 }
92f5d02b 10623
b6895b4f 10624 value += signed_addend;
b6895b4f
PB		 10625
10626 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
10627 value -= (input_section->output_section->vma
10628 + input_section->output_offset + rel->r_offset);
10629
92f5d02b 10630 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 10631 return bfd_reloc_overflow;
92f5d02b 10632
35fc36a8 10633 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10634 value |= 1;
10635
10636 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 10637 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 10638 value >>= 16;
10639
10640 insn &= 0xfff0f000;
10641 insn |= value & 0xfff;
10642 insn |= (value & 0xf000) << 4;
10643 bfd_put_32 (input_bfd, insn, hit_data);
10644 }
10645 return bfd_reloc_ok;
10646
10647 case R_ARM_THM_MOVW_ABS_NC:
10648 case R_ARM_THM_MOVT_ABS:
10649 case R_ARM_THM_MOVW_PREL_NC:
10650 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 10651 /* Until we properly support segment-base-relative addressing then
10652 we assume the segment base to be zero, as for the above relocations.
10653 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
10654 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
10655 as R_ARM_THM_MOVT_ABS. */
10656 case R_ARM_THM_MOVW_BREL_NC:
10657 case R_ARM_THM_MOVW_BREL:
10658 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 10659 {
10660 bfd_vma insn;
906e58ca 10661
b6895b4f
PB		 10662 insn = bfd_get_16 (input_bfd, hit_data) << 16;
10663 insn |= bfd_get_16 (input_bfd, hit_data + 2);
10664
10665 if (globals->use_rel)
10666 {
10667 addend = ((insn >> 4) & 0xf000)
10668 | ((insn >> 15) & 0x0800)
10669 | ((insn >> 4) & 0x0700)
10670 | (insn & 0x00ff);
39623e12 10671 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10672 }
92f5d02b 10673
b6895b4f 10674 value += signed_addend;
b6895b4f
PB		 10675
10676 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
10677 value -= (input_section->output_section->vma
10678 + input_section->output_offset + rel->r_offset);
10679
92f5d02b 10680 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 10681 return bfd_reloc_overflow;
92f5d02b 10682
35fc36a8 10683 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10684 value |= 1;
10685
10686 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 10687 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 10688 value >>= 16;
10689
10690 insn &= 0xfbf08f00;
10691 insn |= (value & 0xf000) << 4;
10692 insn |= (value & 0x0800) << 15;
10693 insn |= (value & 0x0700) << 4;
10694 insn |= (value & 0x00ff);
10695
10696 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10697 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10698 }
10699 return bfd_reloc_ok;
10700
4962c51a
MS		 10701 case R_ARM_ALU_PC_G0_NC:
10702 case R_ARM_ALU_PC_G1_NC:
10703 case R_ARM_ALU_PC_G0:
10704 case R_ARM_ALU_PC_G1:
10705 case R_ARM_ALU_PC_G2:
10706 case R_ARM_ALU_SB_G0_NC:
10707 case R_ARM_ALU_SB_G1_NC:
10708 case R_ARM_ALU_SB_G0:
10709 case R_ARM_ALU_SB_G1:
10710 case R_ARM_ALU_SB_G2:
10711 {
10712 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10713 bfd_vma pc = input_section->output_section->vma
4962c51a 10714 + input_section->output_offset + rel->r_offset;
31a91d61 10715 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10716 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 10717 bfd_vma residual;
10718 bfd_vma g_n;
4962c51a 10719 bfd_signed_vma signed_value;
99059e56
RM		 10720 int group = 0;
10721
10722 /* Determine which group of bits to select. */
10723 switch (r_type)
10724 {
10725 case R_ARM_ALU_PC_G0_NC:
10726 case R_ARM_ALU_PC_G0:
10727 case R_ARM_ALU_SB_G0_NC:
10728 case R_ARM_ALU_SB_G0:
10729 group = 0;
10730 break;
10731
10732 case R_ARM_ALU_PC_G1_NC:
10733 case R_ARM_ALU_PC_G1:
10734 case R_ARM_ALU_SB_G1_NC:
10735 case R_ARM_ALU_SB_G1:
10736 group = 1;
10737 break;
10738
10739 case R_ARM_ALU_PC_G2:
10740 case R_ARM_ALU_SB_G2:
10741 group = 2;
10742 break;
10743
10744 default:
10745 abort ();
10746 }
10747
10748 /* If REL, extract the addend from the insn. If RELA, it will
10749 have already been fetched for us. */
4962c51a 10750 if (globals->use_rel)
99059e56
RM		 10751 {
10752 int negative;
10753 bfd_vma constant = insn & 0xff;
10754 bfd_vma rotation = (insn & 0xf00) >> 8;
10755
10756 if (rotation == 0)
10757 signed_addend = constant;
10758 else
10759 {
10760 /* Compensate for the fact that in the instruction, the
10761 rotation is stored in multiples of 2 bits. */
10762 rotation *= 2;
10763
10764 /* Rotate "constant" right by "rotation" bits. */
10765 signed_addend = (constant >> rotation) |
10766 (constant << (8 * sizeof (bfd_vma) - rotation));
10767 }
10768
10769 /* Determine if the instruction is an ADD or a SUB.
10770 (For REL, this determines the sign of the addend.) */
10771 negative = identify_add_or_sub (insn);
10772 if (negative == 0)
10773 {
10774 (*_bfd_error_handler)
10775 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
10776 input_bfd, input_section,
10777 (long) rel->r_offset, howto->name);
10778 return bfd_reloc_overflow;
10779 }
10780
10781 signed_addend *= negative;
10782 }
4962c51a
MS		 10783
10784 /* Compute the value (X) to go in the place. */
99059e56
RM		 10785 if (r_type == R_ARM_ALU_PC_G0_NC
10786 || r_type == R_ARM_ALU_PC_G1_NC
10787 || r_type == R_ARM_ALU_PC_G0
10788 || r_type == R_ARM_ALU_PC_G1
10789 || r_type == R_ARM_ALU_PC_G2)
10790 /* PC relative. */
10791 signed_value = value - pc + signed_addend;
10792 else
10793 /* Section base relative. */
10794 signed_value = value - sb + signed_addend;
10795
10796 /* If the target symbol is a Thumb function, then set the
10797 Thumb bit in the address. */
35fc36a8 10798 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 10799 signed_value |= 1;
10800
99059e56
RM		 10801 /* Calculate the value of the relevant G_n, in encoded
10802 constant-with-rotation format. */
b6518b38
NC		 10803 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10804 group, &residual);
99059e56
RM		 10805
10806 /* Check for overflow if required. */
10807 if ((r_type == R_ARM_ALU_PC_G0
10808 || r_type == R_ARM_ALU_PC_G1
10809 || r_type == R_ARM_ALU_PC_G2
10810 || r_type == R_ARM_ALU_SB_G0
10811 || r_type == R_ARM_ALU_SB_G1
10812 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
10813 {
10814 (*_bfd_error_handler)
10815 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
10816 input_bfd, input_section,
b6518b38
NC		 10817 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
10818 howto->name);
99059e56
RM		 10819 return bfd_reloc_overflow;
10820 }
10821
10822 /* Mask out the value and the ADD/SUB part of the opcode; take care
10823 not to destroy the S bit. */
10824 insn &= 0xff1ff000;
10825
10826 /* Set the opcode according to whether the value to go in the
10827 place is negative. */
10828 if (signed_value < 0)
10829 insn |= 1 << 22;
10830 else
10831 insn |= 1 << 23;
10832
10833 /* Encode the offset. */
10834 insn |= g_n;
4962c51a
MS		 10835
10836 bfd_put_32 (input_bfd, insn, hit_data);
10837 }
10838 return bfd_reloc_ok;
10839
10840 case R_ARM_LDR_PC_G0:
10841 case R_ARM_LDR_PC_G1:
10842 case R_ARM_LDR_PC_G2:
10843 case R_ARM_LDR_SB_G0:
10844 case R_ARM_LDR_SB_G1:
10845 case R_ARM_LDR_SB_G2:
10846 {
10847 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10848 bfd_vma pc = input_section->output_section->vma
4962c51a 10849 + input_section->output_offset + rel->r_offset;
31a91d61 10850 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10851 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10852 bfd_vma residual;
4962c51a 10853 bfd_signed_vma signed_value;
99059e56
RM		 10854 int group = 0;
10855
10856 /* Determine which groups of bits to calculate. */
10857 switch (r_type)
10858 {
10859 case R_ARM_LDR_PC_G0:
10860 case R_ARM_LDR_SB_G0:
10861 group = 0;
10862 break;
10863
10864 case R_ARM_LDR_PC_G1:
10865 case R_ARM_LDR_SB_G1:
10866 group = 1;
10867 break;
10868
10869 case R_ARM_LDR_PC_G2:
10870 case R_ARM_LDR_SB_G2:
10871 group = 2;
10872 break;
10873
10874 default:
10875 abort ();
10876 }
10877
10878 /* If REL, extract the addend from the insn. If RELA, it will
10879 have already been fetched for us. */
4962c51a 10880 if (globals->use_rel)
99059e56
RM		 10881 {
10882 int negative = (insn & (1 << 23)) ? 1 : -1;
10883 signed_addend = negative * (insn & 0xfff);
10884 }
4962c51a
MS		 10885
10886 /* Compute the value (X) to go in the place. */
99059e56
RM		 10887 if (r_type == R_ARM_LDR_PC_G0
10888 || r_type == R_ARM_LDR_PC_G1
10889 || r_type == R_ARM_LDR_PC_G2)
10890 /* PC relative. */
10891 signed_value = value - pc + signed_addend;
10892 else
10893 /* Section base relative. */
10894 signed_value = value - sb + signed_addend;
10895
10896 /* Calculate the value of the relevant G_{n-1} to obtain
10897 the residual at that stage. */
b6518b38
NC		 10898 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10899 group - 1, &residual);
99059e56
RM		 10900
10901 /* Check for overflow. */
10902 if (residual >= 0x1000)
10903 {
10904 (*_bfd_error_handler)
10905 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10906 input_bfd, input_section,
10907 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10908 return bfd_reloc_overflow;
10909 }
10910
10911 /* Mask out the value and U bit. */
10912 insn &= 0xff7ff000;
10913
10914 /* Set the U bit if the value to go in the place is non-negative. */
10915 if (signed_value >= 0)
10916 insn |= 1 << 23;
10917
10918 /* Encode the offset. */
10919 insn |= residual;
4962c51a
MS		 10920
10921 bfd_put_32 (input_bfd, insn, hit_data);
10922 }
10923 return bfd_reloc_ok;
10924
10925 case R_ARM_LDRS_PC_G0:
10926 case R_ARM_LDRS_PC_G1:
10927 case R_ARM_LDRS_PC_G2:
10928 case R_ARM_LDRS_SB_G0:
10929 case R_ARM_LDRS_SB_G1:
10930 case R_ARM_LDRS_SB_G2:
10931 {
10932 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10933 bfd_vma pc = input_section->output_section->vma
4962c51a 10934 + input_section->output_offset + rel->r_offset;
31a91d61 10935 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10936 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10937 bfd_vma residual;
4962c51a 10938 bfd_signed_vma signed_value;
99059e56
RM		 10939 int group = 0;
10940
10941 /* Determine which groups of bits to calculate. */
10942 switch (r_type)
10943 {
10944 case R_ARM_LDRS_PC_G0:
10945 case R_ARM_LDRS_SB_G0:
10946 group = 0;
10947 break;
10948
10949 case R_ARM_LDRS_PC_G1:
10950 case R_ARM_LDRS_SB_G1:
10951 group = 1;
10952 break;
10953
10954 case R_ARM_LDRS_PC_G2:
10955 case R_ARM_LDRS_SB_G2:
10956 group = 2;
10957 break;
10958
10959 default:
10960 abort ();
10961 }
10962
10963 /* If REL, extract the addend from the insn. If RELA, it will
10964 have already been fetched for us. */
4962c51a 10965 if (globals->use_rel)
99059e56
RM		 10966 {
10967 int negative = (insn & (1 << 23)) ? 1 : -1;
10968 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
10969 }
4962c51a
MS		 10970
10971 /* Compute the value (X) to go in the place. */
99059e56
RM		 10972 if (r_type == R_ARM_LDRS_PC_G0
10973 || r_type == R_ARM_LDRS_PC_G1
10974 || r_type == R_ARM_LDRS_PC_G2)
10975 /* PC relative. */
10976 signed_value = value - pc + signed_addend;
10977 else
10978 /* Section base relative. */
10979 signed_value = value - sb + signed_addend;
10980
10981 /* Calculate the value of the relevant G_{n-1} to obtain
10982 the residual at that stage. */
b6518b38
NC		 10983 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10984 group - 1, &residual);
99059e56
RM		 10985
10986 /* Check for overflow. */
10987 if (residual >= 0x100)
10988 {
10989 (*_bfd_error_handler)
10990 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10991 input_bfd, input_section,
10992 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10993 return bfd_reloc_overflow;
10994 }
10995
10996 /* Mask out the value and U bit. */
10997 insn &= 0xff7ff0f0;
10998
10999 /* Set the U bit if the value to go in the place is non-negative. */
11000 if (signed_value >= 0)
11001 insn |= 1 << 23;
11002
11003 /* Encode the offset. */
11004 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 11005
11006 bfd_put_32 (input_bfd, insn, hit_data);
11007 }
11008 return bfd_reloc_ok;
11009
11010 case R_ARM_LDC_PC_G0:
11011 case R_ARM_LDC_PC_G1:
11012 case R_ARM_LDC_PC_G2:
11013 case R_ARM_LDC_SB_G0:
11014 case R_ARM_LDC_SB_G1:
11015 case R_ARM_LDC_SB_G2:
11016 {
11017 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11018 bfd_vma pc = input_section->output_section->vma
4962c51a 11019 + input_section->output_offset + rel->r_offset;
31a91d61 11020 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11021 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11022 bfd_vma residual;
4962c51a 11023 bfd_signed_vma signed_value;
99059e56
RM		 11024 int group = 0;
11025
11026 /* Determine which groups of bits to calculate. */
11027 switch (r_type)
11028 {
11029 case R_ARM_LDC_PC_G0:
11030 case R_ARM_LDC_SB_G0:
11031 group = 0;
11032 break;
11033
11034 case R_ARM_LDC_PC_G1:
11035 case R_ARM_LDC_SB_G1:
11036 group = 1;
11037 break;
11038
11039 case R_ARM_LDC_PC_G2:
11040 case R_ARM_LDC_SB_G2:
11041 group = 2;
11042 break;
11043
11044 default:
11045 abort ();
11046 }
11047
11048 /* If REL, extract the addend from the insn. If RELA, it will
11049 have already been fetched for us. */
4962c51a 11050 if (globals->use_rel)
99059e56
RM		 11051 {
11052 int negative = (insn & (1 << 23)) ? 1 : -1;
11053 signed_addend = negative * ((insn & 0xff) << 2);
11054 }
4962c51a
MS		 11055
11056 /* Compute the value (X) to go in the place. */
99059e56
RM		 11057 if (r_type == R_ARM_LDC_PC_G0
11058 || r_type == R_ARM_LDC_PC_G1
11059 || r_type == R_ARM_LDC_PC_G2)
11060 /* PC relative. */
11061 signed_value = value - pc + signed_addend;
11062 else
11063 /* Section base relative. */
11064 signed_value = value - sb + signed_addend;
11065
11066 /* Calculate the value of the relevant G_{n-1} to obtain
11067 the residual at that stage. */
b6518b38
NC		 11068 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11069 group - 1, &residual);
99059e56
RM		 11070
11071 /* Check for overflow. (The absolute value to go in the place must be
11072 divisible by four and, after having been divided by four, must
11073 fit in eight bits.) */
11074 if ((residual & 0x3) != 0 || residual >= 0x400)
11075 {
11076 (*_bfd_error_handler)
11077 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11078 input_bfd, input_section,
b6518b38 11079 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11080 return bfd_reloc_overflow;
11081 }
11082
11083 /* Mask out the value and U bit. */
11084 insn &= 0xff7fff00;
11085
11086 /* Set the U bit if the value to go in the place is non-negative. */
11087 if (signed_value >= 0)
11088 insn |= 1 << 23;
11089
11090 /* Encode the offset. */
11091 insn |= residual >> 2;
4962c51a
MS		 11092
11093 bfd_put_32 (input_bfd, insn, hit_data);
11094 }
11095 return bfd_reloc_ok;
11096
72d98d16
MG		 11097 case R_ARM_THM_ALU_ABS_G0_NC:
11098 case R_ARM_THM_ALU_ABS_G1_NC:
11099 case R_ARM_THM_ALU_ABS_G2_NC:
11100 case R_ARM_THM_ALU_ABS_G3_NC:
11101 {
11102 const int shift_array[4] = {0, 8, 16, 24};
11103 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
11104 bfd_vma addr = value;
11105 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
11106
11107 /* Compute address. */
11108 if (globals->use_rel)
11109 signed_addend = insn & 0xff;
11110 addr += signed_addend;
11111 if (branch_type == ST_BRANCH_TO_THUMB)
11112 addr |= 1;
11113 /* Clean imm8 insn. */
11114 insn &= 0xff00;
11115 /* And update with correct part of address. */
11116 insn |= (addr >> shift) & 0xff;
11117 /* Update insn. */
11118 bfd_put_16 (input_bfd, insn, hit_data);
11119 }
11120
11121 *unresolved_reloc_p = FALSE;
11122 return bfd_reloc_ok;
11123
252b5132
RH		 11124 default:
11125 return bfd_reloc_notsupported;
11126 }
11127}
11128
98c1d4aa
NC		 11129/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11130static void
57e8b36a
NC		 11131arm_add_to_rel (bfd * abfd,
11132 bfd_byte * address,
11133 reloc_howto_type * howto,
11134 bfd_signed_vma increment)
98c1d4aa 11135{
98c1d4aa
NC		 11136 bfd_signed_vma addend;
11137
bd97cb95
DJ		 11138 if (howto->type == R_ARM_THM_CALL
11139 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 11140 {
9a5aca8c
AM		 11141 int upper_insn, lower_insn;
11142 int upper, lower;
98c1d4aa 11143
9a5aca8c
AM		 11144 upper_insn = bfd_get_16 (abfd, address);
11145 lower_insn = bfd_get_16 (abfd, address + 2);
11146 upper = upper_insn & 0x7ff;
11147 lower = lower_insn & 0x7ff;
11148
11149 addend = (upper << 12) | (lower << 1);
ddda4409 11150 addend += increment;
9a5aca8c 11151 addend >>= 1;
98c1d4aa 11152
9a5aca8c
AM		 11153 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
11154 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
11155
dc810e39
AM		 11156 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
11157 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 11158 }
11159 else
11160 {
11161 bfd_vma contents;
11162
11163 contents = bfd_get_32 (abfd, address);
11164
11165 /* Get the (signed) value from the instruction. */
11166 addend = contents & howto->src_mask;
11167 if (addend & ((howto->src_mask + 1) >> 1))
11168 {
11169 bfd_signed_vma mask;
11170
11171 mask = -1;
11172 mask &= ~ howto->src_mask;
11173 addend |= mask;
11174 }
11175
11176 /* Add in the increment, (which is a byte value). */
11177 switch (howto->type)
11178 {
11179 default:
11180 addend += increment;
11181 break;
11182
11183 case R_ARM_PC24:
c6596c5e 11184 case R_ARM_PLT32:
5b5bb741
PB		 11185 case R_ARM_CALL:
11186 case R_ARM_JUMP24:
9a5aca8c 11187 addend <<= howto->size;
dc810e39 11188 addend += increment;
9a5aca8c
AM		 11189
11190 /* Should we check for overflow here ? */
11191
11192 /* Drop any undesired bits. */
11193 addend >>= howto->rightshift;
11194 break;
11195 }
11196
11197 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
11198
11199 bfd_put_32 (abfd, contents, address);
ddda4409 11200 }
98c1d4aa 11201}
252b5132 11202
ba93b8ac
DJ		 11203#define IS_ARM_TLS_RELOC(R_TYPE) \
11204 ((R_TYPE) == R_ARM_TLS_GD32 \
11205 || (R_TYPE) == R_ARM_TLS_LDO32 \
11206 || (R_TYPE) == R_ARM_TLS_LDM32 \
11207 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11208 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11209 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11210 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 11211 || (R_TYPE) == R_ARM_TLS_IE32 \
11212 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11213
11214/* Specific set of relocations for the gnu tls dialect. */
11215#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11216 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11217 || (R_TYPE) == R_ARM_TLS_CALL \
11218 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11219 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11220 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 11221
252b5132 11222/* Relocate an ARM ELF section. */
906e58ca 11223
b34976b6 11224static bfd_boolean
57e8b36a
NC		 11225elf32_arm_relocate_section (bfd * output_bfd,
11226 struct bfd_link_info * info,
11227 bfd * input_bfd,
11228 asection * input_section,
11229 bfd_byte * contents,
11230 Elf_Internal_Rela * relocs,
11231 Elf_Internal_Sym * local_syms,
11232 asection ** local_sections)
252b5132 11233{
b34976b6
AM		 11234 Elf_Internal_Shdr *symtab_hdr;
11235 struct elf_link_hash_entry **sym_hashes;
11236 Elf_Internal_Rela *rel;
11237 Elf_Internal_Rela *relend;
11238 const char *name;
b32d3aa2 11239 struct elf32_arm_link_hash_table * globals;
252b5132 11240
4e7fd91e 11241 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 11242 if (globals == NULL)
11243 return FALSE;
b491616a 11244
0ffa91dd 11245 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 11246 sym_hashes = elf_sym_hashes (input_bfd);
11247
11248 rel = relocs;
11249 relend = relocs + input_section->reloc_count;
11250 for (; rel < relend; rel++)
11251 {
ba96a88f
NC		 11252 int r_type;
11253 reloc_howto_type * howto;
11254 unsigned long r_symndx;
11255 Elf_Internal_Sym * sym;
11256 asection * sec;
252b5132 11257 struct elf_link_hash_entry * h;
ba96a88f
NC		 11258 bfd_vma relocation;
11259 bfd_reloc_status_type r;
11260 arelent bfd_reloc;
ba93b8ac 11261 char sym_type;
0945cdfd 11262 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 11263 char *error_message = NULL;
f21f3fe0 11264
252b5132 11265 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 11266 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 11267 r_type = arm_real_reloc_type (globals, r_type);
252b5132 11268
ba96a88f 11269 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 11270 || r_type == R_ARM_GNU_VTINHERIT)
11271 continue;
252b5132 11272
b32d3aa2 11273 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 11274 howto = bfd_reloc.howto;
252b5132 11275
252b5132
RH		 11276 h = NULL;
11277 sym = NULL;
11278 sec = NULL;
9b485d32 11279
252b5132
RH		 11280 if (r_symndx < symtab_hdr->sh_info)
11281 {
11282 sym = local_syms + r_symndx;
ba93b8ac 11283 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 11284 sec = local_sections[r_symndx];
ffcb4889
NS		 11285
11286 /* An object file might have a reference to a local
11287 undefined symbol. This is a daft object file, but we
11288 should at least do something about it. V4BX & NONE
11289 relocations do not use the symbol and are explicitly
77b4f08f
TS		 11290 allowed to use the undefined symbol, so allow those.
11291 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 11292 if (r_type != R_ARM_V4BX
11293 && r_type != R_ARM_NONE
77b4f08f 11294 && r_symndx != STN_UNDEF
ffcb4889
NS		 11295 && bfd_is_und_section (sec)
11296 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
11297 {
11298 if (!info->callbacks->undefined_symbol
11299 (info, bfd_elf_string_from_elf_section
11300 (input_bfd, symtab_hdr->sh_link, sym->st_name),
11301 input_bfd, input_section,
11302 rel->r_offset, TRUE))
11303 return FALSE;
11304 }
b38cadfb 11305
4e7fd91e 11306 if (globals->use_rel)
f8df10f4 11307 {
4e7fd91e
PB		 11308 relocation = (sec->output_section->vma
11309 + sec->output_offset
11310 + sym->st_value);
0e1862bb 11311 if (!bfd_link_relocatable (info)
ab96bf03
AM		 11312 && (sec->flags & SEC_MERGE)
11313 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 11314 {
4e7fd91e
PB		 11315 asection *msec;
11316 bfd_vma addend, value;
11317
39623e12 11318 switch (r_type)
4e7fd91e 11319 {
39623e12
PB		 11320 case R_ARM_MOVW_ABS_NC:
11321 case R_ARM_MOVT_ABS:
11322 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11323 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
11324 addend = (addend ^ 0x8000) - 0x8000;
11325 break;
f8df10f4 11326
39623e12
PB		 11327 case R_ARM_THM_MOVW_ABS_NC:
11328 case R_ARM_THM_MOVT_ABS:
11329 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
11330 << 16;
11331 value |= bfd_get_16 (input_bfd,
11332 contents + rel->r_offset + 2);
11333 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
11334 | ((value & 0x04000000) >> 15);
11335 addend = (addend ^ 0x8000) - 0x8000;
11336 break;
f8df10f4 11337
39623e12
PB		 11338 default:
11339 if (howto->rightshift
11340 || (howto->src_mask & (howto->src_mask + 1)))
11341 {
11342 (*_bfd_error_handler)
11343 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
11344 input_bfd, input_section,
11345 (long) rel->r_offset, howto->name);
11346 return FALSE;
11347 }
11348
11349 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11350
11351 /* Get the (signed) value from the instruction. */
11352 addend = value & howto->src_mask;
11353 if (addend & ((howto->src_mask + 1) >> 1))
11354 {
11355 bfd_signed_vma mask;
11356
11357 mask = -1;
11358 mask &= ~ howto->src_mask;
11359 addend |= mask;
11360 }
11361 break;
4e7fd91e 11362 }
39623e12 11363
4e7fd91e
PB		 11364 msec = sec;
11365 addend =
11366 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
11367 - relocation;
11368 addend += msec->output_section->vma + msec->output_offset;
39623e12 11369
cc643b88 11370 /* Cases here must match those in the preceding
39623e12
PB		 11371 switch statement. */
11372 switch (r_type)
11373 {
11374 case R_ARM_MOVW_ABS_NC:
11375 case R_ARM_MOVT_ABS:
11376 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
11377 | (addend & 0xfff);
11378 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11379 break;
11380
11381 case R_ARM_THM_MOVW_ABS_NC:
11382 case R_ARM_THM_MOVT_ABS:
11383 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
11384 | (addend & 0xff) | ((addend & 0x0800) << 15);
11385 bfd_put_16 (input_bfd, value >> 16,
11386 contents + rel->r_offset);
11387 bfd_put_16 (input_bfd, value,
11388 contents + rel->r_offset + 2);
11389 break;
11390
11391 default:
11392 value = (value & ~ howto->dst_mask)
11393 | (addend & howto->dst_mask);
11394 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11395 break;
11396 }
f8df10f4 11397 }
f8df10f4 11398 }
4e7fd91e
PB		 11399 else
11400 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 11401 }
11402 else
11403 {
62d887d4 11404 bfd_boolean warned, ignored;
560e09e9 11405
b2a8e766
AM		 11406 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
11407 r_symndx, symtab_hdr, sym_hashes,
11408 h, sec, relocation,
62d887d4 11409 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 11410
11411 sym_type = h->type;
252b5132
RH		 11412 }
11413
dbaa2011 11414 if (sec != NULL && discarded_section (sec))
e4067dbb 11415 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 11416 rel, 1, relend, howto, 0, contents);
ab96bf03 11417
0e1862bb 11418 if (bfd_link_relocatable (info))
ab96bf03
AM		 11419 {
11420 /* This is a relocatable link. We don't have to change
11421 anything, unless the reloc is against a section symbol,
11422 in which case we have to adjust according to where the
11423 section symbol winds up in the output section. */
11424 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
11425 {
11426 if (globals->use_rel)
11427 arm_add_to_rel (input_bfd, contents + rel->r_offset,
11428 howto, (bfd_signed_vma) sec->output_offset);
11429 else
11430 rel->r_addend += sec->output_offset;
11431 }
11432 continue;
11433 }
11434
252b5132
RH		 11435 if (h != NULL)
11436 name = h->root.root.string;
11437 else
11438 {
11439 name = (bfd_elf_string_from_elf_section
11440 (input_bfd, symtab_hdr->sh_link, sym->st_name));
11441 if (name == NULL || *name == '\0')
11442 name = bfd_section_name (input_bfd, sec);
11443 }
f21f3fe0 11444
cf35638d 11445 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 11446 && r_type != R_ARM_NONE
11447 && (h == NULL
11448 || h->root.type == bfd_link_hash_defined
11449 || h->root.type == bfd_link_hash_defweak)
11450 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
11451 {
11452 (*_bfd_error_handler)
11453 ((sym_type == STT_TLS
11454 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
11455 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
11456 input_bfd,
11457 input_section,
11458 (long) rel->r_offset,
11459 howto->name,
11460 name);
11461 }
11462
0855e32b 11463 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 11464 done, i.e., the relaxation produced the final output we want,
11465 and we won't let anybody mess with it. Also, we have to do
11466 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 11467 both in relaxed and non-relaxed cases. */
0855e32b
NS		 11468 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
11469 || (IS_ARM_TLS_GNU_RELOC (r_type)
b38cadfb 11470 && !((h ? elf32_arm_hash_entry (h)->tls_type :
0855e32b
NS		 11471 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
11472 & GOT_TLS_GDESC)))
11473 {
11474 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
11475 contents, rel, h == NULL);
11476 /* This may have been marked unresolved because it came from
11477 a shared library. But we've just dealt with that. */
11478 unresolved_reloc = 0;
11479 }
11480 else
11481 r = bfd_reloc_continue;
b38cadfb 11482
0855e32b
NS		 11483 if (r == bfd_reloc_continue)
11484 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
11485 input_section, contents, rel,
34e77a92 11486 relocation, info, sec, name, sym_type,
35fc36a8
RS		 11487 (h ? h->target_internal
11488 : ARM_SYM_BRANCH_TYPE (sym)), h,
0855e32b 11489 &unresolved_reloc, &error_message);
0945cdfd
DJ		 11490
11491 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
11492 because such sections are not SEC_ALLOC and thus ld.so will
11493 not process them. */
11494 if (unresolved_reloc
99059e56
RM		 11495 && !((input_section->flags & SEC_DEBUGGING) != 0
11496 && h->def_dynamic)
1d5316ab
AM		 11497 && _bfd_elf_section_offset (output_bfd, info, input_section,
11498 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 11499 {
11500 (*_bfd_error_handler)
843fe662
L		 11501 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
11502 input_bfd,
11503 input_section,
11504 (long) rel->r_offset,
11505 howto->name,
11506 h->root.root.string);
0945cdfd
DJ		 11507 return FALSE;
11508 }
252b5132
RH		 11509
11510 if (r != bfd_reloc_ok)
11511 {
252b5132
RH		 11512 switch (r)
11513 {
11514 case bfd_reloc_overflow:
cf919dfd
PB		 11515 /* If the overflowing reloc was to an undefined symbol,
11516 we have already printed one error message and there
11517 is no point complaining again. */
11518 if ((! h ||
11519 h->root.type != bfd_link_hash_undefined)
11520 && (!((*info->callbacks->reloc_overflow)
dfeffb9f
L		 11521 (info, (h ? &h->root : NULL), name, howto->name,
11522 (bfd_vma) 0, input_bfd, input_section,
11523 rel->r_offset))))
b34976b6 11524 return FALSE;
252b5132
RH		 11525 break;
11526
11527 case bfd_reloc_undefined:
11528 if (!((*info->callbacks->undefined_symbol)
11529 (info, name, input_bfd, input_section,
b34976b6
AM		 11530 rel->r_offset, TRUE)))
11531 return FALSE;
252b5132
RH		 11532 break;
11533
11534 case bfd_reloc_outofrange:
f2a9dd69 11535 error_message = _("out of range");
252b5132
RH		 11536 goto common_error;
11537
11538 case bfd_reloc_notsupported:
f2a9dd69 11539 error_message = _("unsupported relocation");
252b5132
RH		 11540 goto common_error;
11541
11542 case bfd_reloc_dangerous:
f2a9dd69 11543 /* error_message should already be set. */
252b5132
RH		 11544 goto common_error;
11545
11546 default:
f2a9dd69 11547 error_message = _("unknown error");
8029a119 11548 /* Fall through. */
252b5132
RH		 11549
11550 common_error:
f2a9dd69
DJ		 11551 BFD_ASSERT (error_message != NULL);
11552 if (!((*info->callbacks->reloc_dangerous)
11553 (info, error_message, input_bfd, input_section,
252b5132 11554 rel->r_offset)))
b34976b6 11555 return FALSE;
252b5132
RH		 11556 break;
11557 }
11558 }
11559 }
11560
b34976b6 11561 return TRUE;
252b5132
RH		 11562}
11563
91d6fa6a 11564/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 11565 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 11566 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 11567 maintaining that condition). */
11568
11569static void
11570add_unwind_table_edit (arm_unwind_table_edit **head,
11571 arm_unwind_table_edit **tail,
11572 arm_unwind_edit_type type,
11573 asection *linked_section,
91d6fa6a 11574 unsigned int tindex)
2468f9c9 11575{
21d799b5
NC		 11576 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
11577 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 11578
2468f9c9
PB		 11579 new_edit->type = type;
11580 new_edit->linked_section = linked_section;
91d6fa6a 11581 new_edit->index = tindex;
b38cadfb 11582
91d6fa6a 11583 if (tindex > 0)
2468f9c9
PB		 11584 {
11585 new_edit->next = NULL;
11586
11587 if (*tail)
11588 (*tail)->next = new_edit;
11589
11590 (*tail) = new_edit;
11591
11592 if (!*head)
11593 (*head) = new_edit;
11594 }
11595 else
11596 {
11597 new_edit->next = *head;
11598
11599 if (!*tail)
11600 *tail = new_edit;
11601
11602 *head = new_edit;
11603 }
11604}
11605
11606static _arm_elf_section_data *get_arm_elf_section_data (asection *);
11607
11608/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
11609static void
11610adjust_exidx_size(asection *exidx_sec, int adjust)
11611{
11612 asection *out_sec;
11613
11614 if (!exidx_sec->rawsize)
11615 exidx_sec->rawsize = exidx_sec->size;
11616
11617 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
11618 out_sec = exidx_sec->output_section;
11619 /* Adjust size of output section. */
11620 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
11621}
11622
11623/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
11624static void
11625insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
11626{
11627 struct _arm_elf_section_data *exidx_arm_data;
11628
11629 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11630 add_unwind_table_edit (
11631 &exidx_arm_data->u.exidx.unwind_edit_list,
11632 &exidx_arm_data->u.exidx.unwind_edit_tail,
11633 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
11634
491d01d3
YU		 11635 exidx_arm_data->additional_reloc_count++;
11636
2468f9c9
PB		 11637 adjust_exidx_size(exidx_sec, 8);
11638}
11639
11640/* Scan .ARM.exidx tables, and create a list describing edits which should be
11641 made to those tables, such that:
b38cadfb 11642
2468f9c9
PB		 11643 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
11644 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 11645 codes which have been inlined into the index).
2468f9c9 11646
85fdf906
AH		 11647 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
11648
2468f9c9 11649 The edits are applied when the tables are written
b38cadfb 11650 (in elf32_arm_write_section). */
2468f9c9
PB		 11651
11652bfd_boolean
11653elf32_arm_fix_exidx_coverage (asection **text_section_order,
11654 unsigned int num_text_sections,
85fdf906
AH		 11655 struct bfd_link_info *info,
11656 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 11657{
11658 bfd *inp;
11659 unsigned int last_second_word = 0, i;
11660 asection *last_exidx_sec = NULL;
11661 asection *last_text_sec = NULL;
11662 int last_unwind_type = -1;
11663
11664 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
11665 text sections. */
c72f2fb2 11666 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 11667 {
11668 asection *sec;
b38cadfb 11669
2468f9c9 11670 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 11671 {
2468f9c9
PB		 11672 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
11673 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 11674
dec9d5df 11675 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 11676 continue;
b38cadfb 11677
2468f9c9
PB		 11678 if (elf_sec->linked_to)
11679 {
11680 Elf_Internal_Shdr *linked_hdr
99059e56 11681 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 11682 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 11683 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 11684
11685 if (linked_sec_arm_data == NULL)
99059e56 11686 continue;
2468f9c9
PB		 11687
11688 /* Link this .ARM.exidx section back from the text section it
99059e56 11689 describes. */
2468f9c9
PB		 11690 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
11691 }
11692 }
11693 }
11694
11695 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
11696 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 11697 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 11698
11699 for (i = 0; i < num_text_sections; i++)
11700 {
11701 asection *sec = text_section_order[i];
11702 asection *exidx_sec;
11703 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
11704 struct _arm_elf_section_data *exidx_arm_data;
11705 bfd_byte *contents = NULL;
11706 int deleted_exidx_bytes = 0;
11707 bfd_vma j;
11708 arm_unwind_table_edit *unwind_edit_head = NULL;
11709 arm_unwind_table_edit *unwind_edit_tail = NULL;
11710 Elf_Internal_Shdr *hdr;
11711 bfd *ibfd;
11712
11713 if (arm_data == NULL)
99059e56 11714 continue;
2468f9c9
PB		 11715
11716 exidx_sec = arm_data->u.text.arm_exidx_sec;
11717 if (exidx_sec == NULL)
11718 {
11719 /* Section has no unwind data. */
11720 if (last_unwind_type == 0 || !last_exidx_sec)
11721 continue;
11722
11723 /* Ignore zero sized sections. */
11724 if (sec->size == 0)
11725 continue;
11726
11727 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11728 last_unwind_type = 0;
11729 continue;
11730 }
11731
22a8f80e
PB		 11732 /* Skip /DISCARD/ sections. */
11733 if (bfd_is_abs_section (exidx_sec->output_section))
11734 continue;
11735
2468f9c9
PB		 11736 hdr = &elf_section_data (exidx_sec)->this_hdr;
11737 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 11738 continue;
b38cadfb 11739
2468f9c9
PB		 11740 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11741 if (exidx_arm_data == NULL)
99059e56 11742 continue;
b38cadfb 11743
2468f9c9 11744 ibfd = exidx_sec->owner;
b38cadfb 11745
2468f9c9
PB		 11746 if (hdr->contents != NULL)
11747 contents = hdr->contents;
11748 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
11749 /* An error? */
11750 continue;
11751
ac06903d
YU		 11752 if (last_unwind_type > 0)
11753 {
11754 unsigned int first_word = bfd_get_32 (ibfd, contents);
11755 /* Add cantunwind if first unwind item does not match section
11756 start. */
11757 if (first_word != sec->vma)
11758 {
11759 insert_cantunwind_after (last_text_sec, last_exidx_sec);
11760 last_unwind_type = 0;
11761 }
11762 }
11763
2468f9c9
PB		 11764 for (j = 0; j < hdr->sh_size; j += 8)
11765 {
11766 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
11767 int unwind_type;
11768 int elide = 0;
11769
11770 /* An EXIDX_CANTUNWIND entry. */
11771 if (second_word == 1)
11772 {
11773 if (last_unwind_type == 0)
11774 elide = 1;
11775 unwind_type = 0;
11776 }
11777 /* Inlined unwinding data. Merge if equal to previous. */
11778 else if ((second_word & 0x80000000) != 0)
11779 {
85fdf906
AH		 11780 if (merge_exidx_entries
11781 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 11782 elide = 1;
11783 unwind_type = 1;
11784 last_second_word = second_word;
11785 }
11786 /* Normal table entry. In theory we could merge these too,
11787 but duplicate entries are likely to be much less common. */
11788 else
11789 unwind_type = 2;
11790
491d01d3 11791 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 11792 {
11793 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
11794 DELETE_EXIDX_ENTRY, NULL, j / 8);
11795
11796 deleted_exidx_bytes += 8;
11797 }
11798
11799 last_unwind_type = unwind_type;
11800 }
11801
11802 /* Free contents if we allocated it ourselves. */
11803 if (contents != hdr->contents)
99059e56 11804 free (contents);
2468f9c9
PB		 11805
11806 /* Record edits to be applied later (in elf32_arm_write_section). */
11807 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
11808 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 11809
2468f9c9
PB		 11810 if (deleted_exidx_bytes > 0)
11811 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
11812
11813 last_exidx_sec = exidx_sec;
11814 last_text_sec = sec;
11815 }
11816
11817 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 11818 if (!bfd_link_relocatable (info) && last_exidx_sec
11819 && last_unwind_type != 0)
2468f9c9
PB		 11820 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11821
11822 return TRUE;
11823}
11824
3e6b1042
DJ		 11825static bfd_boolean
11826elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
11827 bfd *ibfd, const char *name)
11828{
11829 asection *sec, *osec;
11830
3d4d4302 11831 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 11832 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
11833 return TRUE;
11834
11835 osec = sec->output_section;
11836 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
11837 return TRUE;
11838
11839 if (! bfd_set_section_contents (obfd, osec, sec->contents,
11840 sec->output_offset, sec->size))
11841 return FALSE;
11842
11843 return TRUE;
11844}
11845
11846static bfd_boolean
11847elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
11848{
11849 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 11850 asection *sec, *osec;
3e6b1042 11851
4dfe6ac6
NC		 11852 if (globals == NULL)
11853 return FALSE;
11854
3e6b1042
DJ		 11855 /* Invoke the regular ELF backend linker to do all the work. */
11856 if (!bfd_elf_final_link (abfd, info))
11857 return FALSE;
11858
fe33d2fa
CL		 11859 /* Process stub sections (eg BE8 encoding, ...). */
11860 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 11861 unsigned int i;
cdb21a0a
NS		 11862 for (i=0; i<htab->top_id; i++)
11863 {
11864 sec = htab->stub_group[i].stub_sec;
11865 /* Only process it once, in its link_sec slot. */
11866 if (sec && i == htab->stub_group[i].link_sec->id)
11867 {
11868 osec = sec->output_section;
11869 elf32_arm_write_section (abfd, info, sec, sec->contents);
11870 if (! bfd_set_section_contents (abfd, osec, sec->contents,
11871 sec->output_offset, sec->size))
11872 return FALSE;
11873 }
fe33d2fa 11874 }
fe33d2fa 11875
3e6b1042
DJ		 11876 /* Write out any glue sections now that we have created all the
11877 stubs. */
11878 if (globals->bfd_of_glue_owner != NULL)
11879 {
11880 if (! elf32_arm_output_glue_section (info, abfd,
11881 globals->bfd_of_glue_owner,
11882 ARM2THUMB_GLUE_SECTION_NAME))
11883 return FALSE;
11884
11885 if (! elf32_arm_output_glue_section (info, abfd,
11886 globals->bfd_of_glue_owner,
11887 THUMB2ARM_GLUE_SECTION_NAME))
11888 return FALSE;
11889
11890 if (! elf32_arm_output_glue_section (info, abfd,
11891 globals->bfd_of_glue_owner,
11892 VFP11_ERRATUM_VENEER_SECTION_NAME))
11893 return FALSE;
11894
a504d23a
LA		 11895 if (! elf32_arm_output_glue_section (info, abfd,
11896 globals->bfd_of_glue_owner,
11897 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
11898 return FALSE;
11899
3e6b1042
DJ		 11900 if (! elf32_arm_output_glue_section (info, abfd,
11901 globals->bfd_of_glue_owner,
11902 ARM_BX_GLUE_SECTION_NAME))
11903 return FALSE;
11904 }
11905
11906 return TRUE;
11907}
11908
5968a7b8
NC		 11909/* Return a best guess for the machine number based on the attributes. */
11910
11911static unsigned int
11912bfd_arm_get_mach_from_attributes (bfd * abfd)
11913{
11914 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
11915
11916 switch (arch)
11917 {
11918 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
11919 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
11920 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
11921
11922 case TAG_CPU_ARCH_V5TE:
11923 {
11924 char * name;
11925
11926 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
11927 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
11928
11929 if (name)
11930 {
11931 if (strcmp (name, "IWMMXT2") == 0)
11932 return bfd_mach_arm_iWMMXt2;
11933
11934 if (strcmp (name, "IWMMXT") == 0)
6034aab8 11935 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 11936
11937 if (strcmp (name, "XSCALE") == 0)
11938 {
11939 int wmmx;
11940
11941 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
11942 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
11943 switch (wmmx)
11944 {
11945 case 1: return bfd_mach_arm_iWMMXt;
11946 case 2: return bfd_mach_arm_iWMMXt2;
11947 default: return bfd_mach_arm_XScale;
11948 }
11949 }
5968a7b8
NC		 11950 }
11951
11952 return bfd_mach_arm_5TE;
11953 }
11954
11955 default:
11956 return bfd_mach_arm_unknown;
11957 }
11958}
11959
c178919b
NC		 11960/* Set the right machine number. */
11961
11962static bfd_boolean
57e8b36a 11963elf32_arm_object_p (bfd *abfd)
c178919b 11964{
5a6c6817 11965 unsigned int mach;
57e8b36a 11966
5a6c6817 11967 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 11968
5968a7b8
NC		 11969 if (mach == bfd_mach_arm_unknown)
11970 {
11971 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
11972 mach = bfd_mach_arm_ep9312;
11973 else
11974 mach = bfd_arm_get_mach_from_attributes (abfd);
11975 }
c178919b 11976
5968a7b8 11977 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 11978 return TRUE;
11979}
11980
fc830a83 11981/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 11982
b34976b6 11983static bfd_boolean
57e8b36a 11984elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 11985{
11986 if (elf_flags_init (abfd)
11987 && elf_elfheader (abfd)->e_flags != flags)
11988 {
fc830a83
NC		 11989 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
11990 {
fd2ec330 11991 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 11992 (*_bfd_error_handler)
11993 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
11994 abfd);
fc830a83 11995 else
d003868e
AM		 11996 _bfd_error_handler
11997 (_("Warning: Clearing the interworking flag of %B due to outside request"),
11998 abfd);
fc830a83 11999 }
252b5132
RH		 12000 }
12001 else
12002 {
12003 elf_elfheader (abfd)->e_flags = flags;
b34976b6 12004 elf_flags_init (abfd) = TRUE;
252b5132
RH		 12005 }
12006
b34976b6 12007 return TRUE;
252b5132
RH		 12008}
12009
fc830a83 12010/* Copy backend specific data from one object module to another. */
9b485d32 12011
b34976b6 12012static bfd_boolean
57e8b36a 12013elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 12014{
12015 flagword in_flags;
12016 flagword out_flags;
12017
0ffa91dd 12018 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 12019 return TRUE;
252b5132 12020
fc830a83 12021 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 12022 out_flags = elf_elfheader (obfd)->e_flags;
12023
fc830a83
NC		 12024 if (elf_flags_init (obfd)
12025 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
12026 && in_flags != out_flags)
252b5132 12027 {
252b5132 12028 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 12029 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 12030 return FALSE;
252b5132
RH		 12031
12032 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 12033 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 12034 return FALSE;
252b5132
RH		 12035
12036 /* If the src and dest have different interworking flags
99059e56 12037 then turn off the interworking bit. */
fd2ec330 12038 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 12039 {
fd2ec330 12040 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 12041 _bfd_error_handler
12042 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
12043 obfd, ibfd);
252b5132 12044
fd2ec330 12045 in_flags &= ~EF_ARM_INTERWORK;
252b5132 12046 }
1006ba19
PB		 12047
12048 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 12049 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
12050 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 12051 }
12052
12053 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 12054 elf_flags_init (obfd) = TRUE;
252b5132 12055
e2349352 12056 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 12057}
12058
12059/* Values for Tag_ABI_PCS_R9_use. */
12060enum
12061{
12062 AEABI_R9_V6,
12063 AEABI_R9_SB,
12064 AEABI_R9_TLS,
12065 AEABI_R9_unused
12066};
12067
12068/* Values for Tag_ABI_PCS_RW_data. */
12069enum
12070{
12071 AEABI_PCS_RW_data_absolute,
12072 AEABI_PCS_RW_data_PCrel,
12073 AEABI_PCS_RW_data_SBrel,
12074 AEABI_PCS_RW_data_unused
12075};
12076
12077/* Values for Tag_ABI_enum_size. */
12078enum
12079{
12080 AEABI_enum_unused,
12081 AEABI_enum_short,
12082 AEABI_enum_wide,
12083 AEABI_enum_forced_wide
12084};
12085
104d59d1
JM		 12086/* Determine whether an object attribute tag takes an integer, a
12087 string or both. */
906e58ca 12088
104d59d1
JM		 12089static int
12090elf32_arm_obj_attrs_arg_type (int tag)
12091{
12092 if (tag == Tag_compatibility)
3483fe2e 12093 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 12094 else if (tag == Tag_nodefaults)
3483fe2e
AS		 12095 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
12096 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
12097 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 12098 else if (tag < 32)
3483fe2e 12099 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 12100 else
3483fe2e 12101 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 12102}
12103
5aa6ff7c
AS		 12104/* The ABI defines that Tag_conformance should be emitted first, and that
12105 Tag_nodefaults should be second (if either is defined). This sets those
12106 two positions, and bumps up the position of all the remaining tags to
12107 compensate. */
12108static int
12109elf32_arm_obj_attrs_order (int num)
12110{
3de4a297 12111 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 12112 return Tag_conformance;
3de4a297 12113 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 12114 return Tag_nodefaults;
12115 if ((num - 2) < Tag_nodefaults)
12116 return num - 2;
12117 if ((num - 1) < Tag_conformance)
12118 return num - 1;
12119 return num;
12120}
12121
e8b36cd1
JM		 12122/* Attribute numbers >=64 (mod 128) can be safely ignored. */
12123static bfd_boolean
12124elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
12125{
12126 if ((tag & 127) < 64)
12127 {
12128 _bfd_error_handler
12129 (_("%B: Unknown mandatory EABI object attribute %d"),
12130 abfd, tag);
12131 bfd_set_error (bfd_error_bad_value);
12132 return FALSE;
12133 }
12134 else
12135 {
12136 _bfd_error_handler
12137 (_("Warning: %B: Unknown EABI object attribute %d"),
12138 abfd, tag);
12139 return TRUE;
12140 }
12141}
12142
91e22acd
AS		 12143/* Read the architecture from the Tag_also_compatible_with attribute, if any.
12144 Returns -1 if no architecture could be read. */
12145
12146static int
12147get_secondary_compatible_arch (bfd *abfd)
12148{
12149 obj_attribute *attr =
12150 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
12151
12152 /* Note: the tag and its argument below are uleb128 values, though
12153 currently-defined values fit in one byte for each. */
12154 if (attr->s
12155 && attr->s[0] == Tag_CPU_arch
12156 && (attr->s[1] & 128) != 128
12157 && attr->s[2] == 0)
12158 return attr->s[1];
12159
12160 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12161 return -1;
12162}
12163
12164/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12165 The tag is removed if ARCH is -1. */
12166
8e79c3df 12167static void
91e22acd 12168set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 12169{
91e22acd
AS		 12170 obj_attribute *attr =
12171 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 12172
91e22acd
AS		 12173 if (arch == -1)
12174 {
12175 attr->s = NULL;
12176 return;
8e79c3df 12177 }
91e22acd
AS		 12178
12179 /* Note: the tag and its argument below are uleb128 values, though
12180 currently-defined values fit in one byte for each. */
12181 if (!attr->s)
21d799b5 12182 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 12183 attr->s[0] = Tag_CPU_arch;
12184 attr->s[1] = arch;
12185 attr->s[2] = '\0';
8e79c3df
CM		 12186}
12187
91e22acd
AS		 12188/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12189 into account. */
12190
12191static int
12192tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
12193 int newtag, int secondary_compat)
8e79c3df 12194{
91e22acd
AS		 12195#define T(X) TAG_CPU_ARCH_##X
12196 int tagl, tagh, result;
12197 const int v6t2[] =
12198 {
12199 T(V6T2), /* PRE_V4. */
12200 T(V6T2), /* V4. */
12201 T(V6T2), /* V4T. */
12202 T(V6T2), /* V5T. */
12203 T(V6T2), /* V5TE. */
12204 T(V6T2), /* V5TEJ. */
12205 T(V6T2), /* V6. */
12206 T(V7), /* V6KZ. */
12207 T(V6T2) /* V6T2. */
12208 };
12209 const int v6k[] =
12210 {
12211 T(V6K), /* PRE_V4. */
12212 T(V6K), /* V4. */
12213 T(V6K), /* V4T. */
12214 T(V6K), /* V5T. */
12215 T(V6K), /* V5TE. */
12216 T(V6K), /* V5TEJ. */
12217 T(V6K), /* V6. */
12218 T(V6KZ), /* V6KZ. */
12219 T(V7), /* V6T2. */
12220 T(V6K) /* V6K. */
12221 };
12222 const int v7[] =
12223 {
12224 T(V7), /* PRE_V4. */
12225 T(V7), /* V4. */
12226 T(V7), /* V4T. */
12227 T(V7), /* V5T. */
12228 T(V7), /* V5TE. */
12229 T(V7), /* V5TEJ. */
12230 T(V7), /* V6. */
12231 T(V7), /* V6KZ. */
12232 T(V7), /* V6T2. */
12233 T(V7), /* V6K. */
12234 T(V7) /* V7. */
12235 };
12236 const int v6_m[] =
12237 {
12238 -1, /* PRE_V4. */
12239 -1, /* V4. */
12240 T(V6K), /* V4T. */
12241 T(V6K), /* V5T. */
12242 T(V6K), /* V5TE. */
12243 T(V6K), /* V5TEJ. */
12244 T(V6K), /* V6. */
12245 T(V6KZ), /* V6KZ. */
12246 T(V7), /* V6T2. */
12247 T(V6K), /* V6K. */
12248 T(V7), /* V7. */
12249 T(V6_M) /* V6_M. */
12250 };
12251 const int v6s_m[] =
12252 {
12253 -1, /* PRE_V4. */
12254 -1, /* V4. */
12255 T(V6K), /* V4T. */
12256 T(V6K), /* V5T. */
12257 T(V6K), /* V5TE. */
12258 T(V6K), /* V5TEJ. */
12259 T(V6K), /* V6. */
12260 T(V6KZ), /* V6KZ. */
12261 T(V7), /* V6T2. */
12262 T(V6K), /* V6K. */
12263 T(V7), /* V7. */
12264 T(V6S_M), /* V6_M. */
12265 T(V6S_M) /* V6S_M. */
12266 };
9e3c6df6
PB		 12267 const int v7e_m[] =
12268 {
12269 -1, /* PRE_V4. */
12270 -1, /* V4. */
12271 T(V7E_M), /* V4T. */
12272 T(V7E_M), /* V5T. */
12273 T(V7E_M), /* V5TE. */
12274 T(V7E_M), /* V5TEJ. */
12275 T(V7E_M), /* V6. */
12276 T(V7E_M), /* V6KZ. */
12277 T(V7E_M), /* V6T2. */
12278 T(V7E_M), /* V6K. */
12279 T(V7E_M), /* V7. */
12280 T(V7E_M), /* V6_M. */
12281 T(V7E_M), /* V6S_M. */
12282 T(V7E_M) /* V7E_M. */
12283 };
bca38921
MGD		 12284 const int v8[] =
12285 {
12286 T(V8), /* PRE_V4. */
12287 T(V8), /* V4. */
12288 T(V8), /* V4T. */
12289 T(V8), /* V5T. */
12290 T(V8), /* V5TE. */
12291 T(V8), /* V5TEJ. */
12292 T(V8), /* V6. */
12293 T(V8), /* V6KZ. */
12294 T(V8), /* V6T2. */
12295 T(V8), /* V6K. */
12296 T(V8), /* V7. */
12297 T(V8), /* V6_M. */
12298 T(V8), /* V6S_M. */
12299 T(V8), /* V7E_M. */
12300 T(V8) /* V8. */
12301 };
2fd158eb
TP		 12302 const int v8m_baseline[] =
12303 {
12304 -1, /* PRE_V4. */
12305 -1, /* V4. */
12306 -1, /* V4T. */
12307 -1, /* V5T. */
12308 -1, /* V5TE. */
12309 -1, /* V5TEJ. */
12310 -1, /* V6. */
12311 -1, /* V6KZ. */
12312 -1, /* V6T2. */
12313 -1, /* V6K. */
12314 -1, /* V7. */
12315 T(V8M_BASE), /* V6_M. */
12316 T(V8M_BASE), /* V6S_M. */
12317 -1, /* V7E_M. */
12318 -1, /* V8. */
12319 -1,
12320 T(V8M_BASE) /* V8-M BASELINE. */
12321 };
12322 const int v8m_mainline[] =
12323 {
12324 -1, /* PRE_V4. */
12325 -1, /* V4. */
12326 -1, /* V4T. */
12327 -1, /* V5T. */
12328 -1, /* V5TE. */
12329 -1, /* V5TEJ. */
12330 -1, /* V6. */
12331 -1, /* V6KZ. */
12332 -1, /* V6T2. */
12333 -1, /* V6K. */
12334 T(V8M_MAIN), /* V7. */
12335 T(V8M_MAIN), /* V6_M. */
12336 T(V8M_MAIN), /* V6S_M. */
12337 T(V8M_MAIN), /* V7E_M. */
12338 -1, /* V8. */
12339 -1,
12340 T(V8M_MAIN), /* V8-M BASELINE. */
12341 T(V8M_MAIN) /* V8-M MAINLINE. */
12342 };
91e22acd
AS		 12343 const int v4t_plus_v6_m[] =
12344 {
12345 -1, /* PRE_V4. */
12346 -1, /* V4. */
12347 T(V4T), /* V4T. */
12348 T(V5T), /* V5T. */
12349 T(V5TE), /* V5TE. */
12350 T(V5TEJ), /* V5TEJ. */
12351 T(V6), /* V6. */
12352 T(V6KZ), /* V6KZ. */
12353 T(V6T2), /* V6T2. */
12354 T(V6K), /* V6K. */
12355 T(V7), /* V7. */
12356 T(V6_M), /* V6_M. */
12357 T(V6S_M), /* V6S_M. */
9e3c6df6 12358 T(V7E_M), /* V7E_M. */
bca38921 12359 T(V8), /* V8. */
4ed7ed8d 12360 -1, /* Unused. */
2fd158eb
TP		 12361 T(V8M_BASE), /* V8-M BASELINE. */
12362 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 12363 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
12364 };
12365 const int *comb[] =
12366 {
12367 v6t2,
12368 v6k,
12369 v7,
12370 v6_m,
12371 v6s_m,
9e3c6df6 12372 v7e_m,
bca38921 12373 v8,
4ed7ed8d 12374 NULL,
2fd158eb
TP		 12375 v8m_baseline,
12376 v8m_mainline,
91e22acd
AS		 12377 /* Pseudo-architecture. */
12378 v4t_plus_v6_m
12379 };
12380
12381 /* Check we've not got a higher architecture than we know about. */
12382
9e3c6df6 12383 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 12384 {
3895f852 12385 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 12386 return -1;
12387 }
12388
12389 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12390
12391 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
12392 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
12393 oldtag = T(V4T_PLUS_V6_M);
12394
12395 /* And override the new tag if we have a Tag_also_compatible_with on the
12396 input. */
12397
12398 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
12399 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
12400 newtag = T(V4T_PLUS_V6_M);
12401
12402 tagl = (oldtag < newtag) ? oldtag : newtag;
12403 result = tagh = (oldtag > newtag) ? oldtag : newtag;
12404
12405 /* Architectures before V6KZ add features monotonically. */
12406 if (tagh <= TAG_CPU_ARCH_V6KZ)
12407 return result;
12408
4ed7ed8d 12409 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 12410
12411 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
12412 as the canonical version. */
12413 if (result == T(V4T_PLUS_V6_M))
12414 {
12415 result = T(V4T);
12416 *secondary_compat_out = T(V6_M);
12417 }
12418 else
12419 *secondary_compat_out = -1;
12420
12421 if (result == -1)
12422 {
3895f852 12423 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 12424 ibfd, oldtag, newtag);
12425 return -1;
12426 }
12427
12428 return result;
12429#undef T
8e79c3df
CM		 12430}
12431
ac56ee8f
MGD		 12432/* Query attributes object to see if integer divide instructions may be
12433 present in an object. */
12434static bfd_boolean
12435elf32_arm_attributes_accept_div (const obj_attribute *attr)
12436{
12437 int arch = attr[Tag_CPU_arch].i;
12438 int profile = attr[Tag_CPU_arch_profile].i;
12439
12440 switch (attr[Tag_DIV_use].i)
12441 {
12442 case 0:
12443 /* Integer divide allowed if instruction contained in archetecture. */
12444 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
12445 return TRUE;
12446 else if (arch >= TAG_CPU_ARCH_V7E_M)
12447 return TRUE;
12448 else
12449 return FALSE;
12450
12451 case 1:
12452 /* Integer divide explicitly prohibited. */
12453 return FALSE;
12454
12455 default:
12456 /* Unrecognised case - treat as allowing divide everywhere. */
12457 case 2:
12458 /* Integer divide allowed in ARM state. */
12459 return TRUE;
12460 }
12461}
12462
12463/* Query attributes object to see if integer divide instructions are
12464 forbidden to be in the object. This is not the inverse of
12465 elf32_arm_attributes_accept_div. */
12466static bfd_boolean
12467elf32_arm_attributes_forbid_div (const obj_attribute *attr)
12468{
12469 return attr[Tag_DIV_use].i == 1;
12470}
12471
ee065d83
PB		 12472/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
12473 are conflicting attributes. */
906e58ca 12474
ee065d83
PB		 12475static bfd_boolean
12476elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
12477{
104d59d1
JM		 12478 obj_attribute *in_attr;
12479 obj_attribute *out_attr;
ee065d83
PB		 12480 /* Some tags have 0 = don't care, 1 = strong requirement,
12481 2 = weak requirement. */
91e22acd 12482 static const int order_021[3] = {0, 2, 1};
ee065d83 12483 int i;
91e22acd 12484 bfd_boolean result = TRUE;
9274e9de 12485 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 12486
3e6b1042
DJ		 12487 /* Skip the linker stubs file. This preserves previous behavior
12488 of accepting unknown attributes in the first input file - but
12489 is that a bug? */
12490 if (ibfd->flags & BFD_LINKER_CREATED)
12491 return TRUE;
12492
9274e9de
TG		 12493 /* Skip any input that hasn't attribute section.
12494 This enables to link object files without attribute section with
12495 any others. */
12496 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
12497 return TRUE;
12498
104d59d1 12499 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 12500 {
12501 /* This is the first object. Copy the attributes. */
104d59d1 12502 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 12503
cd21e546
MGD		 12504 out_attr = elf_known_obj_attributes_proc (obfd);
12505
004ae526
PB		 12506 /* Use the Tag_null value to indicate the attributes have been
12507 initialized. */
cd21e546 12508 out_attr[0].i = 1;
004ae526 12509
cd21e546
MGD		 12510 /* We do not output objects with Tag_MPextension_use_legacy - we move
12511 the attribute's value to Tag_MPextension_use. */
12512 if (out_attr[Tag_MPextension_use_legacy].i != 0)
12513 {
12514 if (out_attr[Tag_MPextension_use].i != 0
12515 && out_attr[Tag_MPextension_use_legacy].i
99059e56 12516 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 12517 {
12518 _bfd_error_handler
12519 (_("Error: %B has both the current and legacy "
12520 "Tag_MPextension_use attributes"), ibfd);
12521 result = FALSE;
12522 }
12523
12524 out_attr[Tag_MPextension_use] =
12525 out_attr[Tag_MPextension_use_legacy];
12526 out_attr[Tag_MPextension_use_legacy].type = 0;
12527 out_attr[Tag_MPextension_use_legacy].i = 0;
12528 }
12529
12530 return result;
ee065d83
PB		 12531 }
12532
104d59d1
JM		 12533 in_attr = elf_known_obj_attributes_proc (ibfd);
12534 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 12535 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
12536 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
12537 {
5c294fee
TG		 12538 /* Ignore mismatches if the object doesn't use floating point or is
12539 floating point ABI independent. */
12540 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
12541 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12542 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 12543 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 12544 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12545 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 12546 {
12547 _bfd_error_handler
3895f852 12548 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 12549 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
12550 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 12551 result = FALSE;
ee065d83
PB		 12552 }
12553 }
12554
3de4a297 12555 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 12556 {
12557 /* Merge this attribute with existing attributes. */
12558 switch (i)
12559 {
12560 case Tag_CPU_raw_name:
12561 case Tag_CPU_name:
6a631e86 12562 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 12563 break;
12564
12565 case Tag_ABI_optimization_goals:
12566 case Tag_ABI_FP_optimization_goals:
12567 /* Use the first value seen. */
12568 break;
12569
12570 case Tag_CPU_arch:
91e22acd
AS		 12571 {
12572 int secondary_compat = -1, secondary_compat_out = -1;
12573 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 12574 int arch_attr;
12575 static const char *name_table[] =
12576 {
91e22acd
AS		 12577 /* These aren't real CPU names, but we can't guess
12578 that from the architecture version alone. */
12579 "Pre v4",
12580 "ARM v4",
12581 "ARM v4T",
12582 "ARM v5T",
12583 "ARM v5TE",
12584 "ARM v5TEJ",
12585 "ARM v6",
12586 "ARM v6KZ",
12587 "ARM v6T2",
12588 "ARM v6K",
12589 "ARM v7",
12590 "ARM v6-M",
bca38921 12591 "ARM v6S-M",
2fd158eb
TP		 12592 "ARM v8",
12593 "",
12594 "ARM v8-M.baseline",
12595 "ARM v8-M.mainline",
91e22acd
AS		 12596 };
12597
12598 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
12599 secondary_compat = get_secondary_compatible_arch (ibfd);
12600 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 12601 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
12602 &secondary_compat_out,
12603 in_attr[i].i,
12604 secondary_compat);
12605
12606 /* Return with error if failed to merge. */
12607 if (arch_attr == -1)
12608 return FALSE;
12609
12610 out_attr[i].i = arch_attr;
12611
91e22acd
AS		 12612 set_secondary_compatible_arch (obfd, secondary_compat_out);
12613
12614 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
12615 if (out_attr[i].i == saved_out_attr)
12616 ; /* Leave the names alone. */
12617 else if (out_attr[i].i == in_attr[i].i)
12618 {
12619 /* The output architecture has been changed to match the
12620 input architecture. Use the input names. */
12621 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
12622 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
12623 : NULL;
12624 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
12625 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
12626 : NULL;
12627 }
12628 else
12629 {
12630 out_attr[Tag_CPU_name].s = NULL;
12631 out_attr[Tag_CPU_raw_name].s = NULL;
12632 }
12633
12634 /* If we still don't have a value for Tag_CPU_name,
12635 make one up now. Tag_CPU_raw_name remains blank. */
12636 if (out_attr[Tag_CPU_name].s == NULL
12637 && out_attr[i].i < ARRAY_SIZE (name_table))
12638 out_attr[Tag_CPU_name].s =
12639 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
12640 }
12641 break;
12642
ee065d83
PB		 12643 case Tag_ARM_ISA_use:
12644 case Tag_THUMB_ISA_use:
ee065d83 12645 case Tag_WMMX_arch:
91e22acd
AS		 12646 case Tag_Advanced_SIMD_arch:
12647 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 12648 case Tag_ABI_FP_rounding:
ee065d83
PB		 12649 case Tag_ABI_FP_exceptions:
12650 case Tag_ABI_FP_user_exceptions:
12651 case Tag_ABI_FP_number_model:
75375b3e 12652 case Tag_FP_HP_extension:
91e22acd
AS		 12653 case Tag_CPU_unaligned_access:
12654 case Tag_T2EE_use:
91e22acd 12655 case Tag_MPextension_use:
ee065d83
PB		 12656 /* Use the largest value specified. */
12657 if (in_attr[i].i > out_attr[i].i)
12658 out_attr[i].i = in_attr[i].i;
12659 break;
12660
75375b3e 12661 case Tag_ABI_align_preserved:
91e22acd
AS		 12662 case Tag_ABI_PCS_RO_data:
12663 /* Use the smallest value specified. */
12664 if (in_attr[i].i < out_attr[i].i)
12665 out_attr[i].i = in_attr[i].i;
12666 break;
12667
75375b3e 12668 case Tag_ABI_align_needed:
91e22acd 12669 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 12670 && (in_attr[Tag_ABI_align_preserved].i == 0
12671 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 12672 {
91e22acd
AS		 12673 /* This error message should be enabled once all non-conformant
12674 binaries in the toolchain have had the attributes set
12675 properly.
ee065d83 12676 _bfd_error_handler
3895f852 12677 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 12678 obfd, ibfd);
12679 result = FALSE; */
ee065d83 12680 }
91e22acd
AS		 12681 /* Fall through. */
12682 case Tag_ABI_FP_denormal:
12683 case Tag_ABI_PCS_GOT_use:
12684 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
12685 value if greater than 2 (for future-proofing). */
12686 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
12687 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
12688 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 12689 out_attr[i].i = in_attr[i].i;
12690 break;
91e22acd 12691
75375b3e
MGD		 12692 case Tag_Virtualization_use:
12693 /* The virtualization tag effectively stores two bits of
12694 information: the intended use of TrustZone (in bit 0), and the
12695 intended use of Virtualization (in bit 1). */
12696 if (out_attr[i].i == 0)
12697 out_attr[i].i = in_attr[i].i;
12698 else if (in_attr[i].i != 0
12699 && in_attr[i].i != out_attr[i].i)
12700 {
12701 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
12702 out_attr[i].i = 3;
12703 else
12704 {
12705 _bfd_error_handler
12706 (_("error: %B: unable to merge virtualization attributes "
12707 "with %B"),
12708 obfd, ibfd);
12709 result = FALSE;
12710 }
12711 }
12712 break;
91e22acd
AS		 12713
12714 case Tag_CPU_arch_profile:
12715 if (out_attr[i].i != in_attr[i].i)
12716 {
12717 /* 0 will merge with anything.
12718 'A' and 'S' merge to 'A'.
12719 'R' and 'S' merge to 'R'.
99059e56 12720 'M' and 'A|R|S' is an error. */
91e22acd
AS		 12721 if (out_attr[i].i == 0
12722 || (out_attr[i].i == 'S'
12723 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
12724 out_attr[i].i = in_attr[i].i;
12725 else if (in_attr[i].i == 0
12726 || (in_attr[i].i == 'S'
12727 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 12728 ; /* Do nothing. */
91e22acd
AS		 12729 else
12730 {
12731 _bfd_error_handler
3895f852 12732 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 12733 ibfd,
12734 in_attr[i].i ? in_attr[i].i : '0',
12735 out_attr[i].i ? out_attr[i].i : '0');
12736 result = FALSE;
12737 }
12738 }
12739 break;
15afaa63
TP		 12740
12741 case Tag_DSP_extension:
12742 /* No need to change output value if any of:
12743 - pre (<=) ARMv5T input architecture (do not have DSP)
12744 - M input profile not ARMv7E-M and do not have DSP. */
12745 if (in_attr[Tag_CPU_arch].i <= 3
12746 || (in_attr[Tag_CPU_arch_profile].i == 'M'
12747 && in_attr[Tag_CPU_arch].i != 13
12748 && in_attr[i].i == 0))
12749 ; /* Do nothing. */
12750 /* Output value should be 0 if DSP part of architecture, ie.
12751 - post (>=) ARMv5te architecture output
12752 - A, R or S profile output or ARMv7E-M output architecture. */
12753 else if (out_attr[Tag_CPU_arch].i >= 4
12754 && (out_attr[Tag_CPU_arch_profile].i == 'A'
12755 || out_attr[Tag_CPU_arch_profile].i == 'R'
12756 || out_attr[Tag_CPU_arch_profile].i == 'S'
12757 || out_attr[Tag_CPU_arch].i == 13))
12758 out_attr[i].i = 0;
12759 /* Otherwise, DSP instructions are added and not part of output
12760 architecture. */
12761 else
12762 out_attr[i].i = 1;
12763 break;
12764
75375b3e 12765 case Tag_FP_arch:
62f3b8c8 12766 {
4547cb56
NC		 12767 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
12768 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
12769 when it's 0. It might mean absence of FP hardware if
99654aaf 12770 Tag_FP_arch is zero. */
4547cb56 12771
a715796b 12772#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 12773 static const struct
12774 {
12775 int ver;
12776 int regs;
bca38921 12777 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 12778 {
12779 {0, 0},
12780 {1, 16},
12781 {2, 16},
12782 {3, 32},
12783 {3, 16},
12784 {4, 32},
bca38921 12785 {4, 16},
a715796b
TG		 12786 {8, 32},
12787 {8, 16}
62f3b8c8
PB		 12788 };
12789 int ver;
12790 int regs;
12791 int newval;
12792
4547cb56
NC		 12793 /* If the output has no requirement about FP hardware,
12794 follow the requirement of the input. */
12795 if (out_attr[i].i == 0)
12796 {
12797 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
12798 out_attr[i].i = in_attr[i].i;
12799 out_attr[Tag_ABI_HardFP_use].i
12800 = in_attr[Tag_ABI_HardFP_use].i;
12801 break;
12802 }
12803 /* If the input has no requirement about FP hardware, do
12804 nothing. */
12805 else if (in_attr[i].i == 0)
12806 {
12807 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
12808 break;
12809 }
12810
12811 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 12812 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 12813
12814 /* If both the input and the output have zero Tag_ABI_HardFP_use,
12815 do nothing. */
12816 if (in_attr[Tag_ABI_HardFP_use].i == 0
12817 && out_attr[Tag_ABI_HardFP_use].i == 0)
12818 ;
12819 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 12820 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 12821 else if (in_attr[Tag_ABI_HardFP_use].i
12822 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 12823 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 12824
12825 /* Now we can handle Tag_FP_arch. */
12826
bca38921
MGD		 12827 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
12828 pick the biggest. */
12829 if (in_attr[i].i >= VFP_VERSION_COUNT
12830 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 12831 {
12832 out_attr[i] = in_attr[i];
12833 break;
12834 }
12835 /* The output uses the superset of input features
12836 (ISA version) and registers. */
12837 ver = vfp_versions[in_attr[i].i].ver;
12838 if (ver < vfp_versions[out_attr[i].i].ver)
12839 ver = vfp_versions[out_attr[i].i].ver;
12840 regs = vfp_versions[in_attr[i].i].regs;
12841 if (regs < vfp_versions[out_attr[i].i].regs)
12842 regs = vfp_versions[out_attr[i].i].regs;
12843 /* This assumes all possible supersets are also a valid
99059e56 12844 options. */
bca38921 12845 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 12846 {
12847 if (regs == vfp_versions[newval].regs
12848 && ver == vfp_versions[newval].ver)
12849 break;
12850 }
12851 out_attr[i].i = newval;
12852 }
b1cc4aeb 12853 break;
ee065d83
PB		 12854 case Tag_PCS_config:
12855 if (out_attr[i].i == 0)
12856 out_attr[i].i = in_attr[i].i;
b6009aca 12857 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 12858 {
12859 /* It's sometimes ok to mix different configs, so this is only
99059e56 12860 a warning. */
ee065d83
PB		 12861 _bfd_error_handler
12862 (_("Warning: %B: Conflicting platform configuration"), ibfd);
12863 }
12864 break;
12865 case Tag_ABI_PCS_R9_use:
004ae526
PB		 12866 if (in_attr[i].i != out_attr[i].i
12867 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 12868 && in_attr[i].i != AEABI_R9_unused)
12869 {
12870 _bfd_error_handler
3895f852 12871 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 12872 result = FALSE;
ee065d83
PB		 12873 }
12874 if (out_attr[i].i == AEABI_R9_unused)
12875 out_attr[i].i = in_attr[i].i;
12876 break;
12877 case Tag_ABI_PCS_RW_data:
12878 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
12879 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
12880 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
12881 {
12882 _bfd_error_handler
3895f852 12883 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 12884 ibfd);
91e22acd 12885 result = FALSE;
ee065d83
PB		 12886 }
12887 /* Use the smallest value specified. */
12888 if (in_attr[i].i < out_attr[i].i)
12889 out_attr[i].i = in_attr[i].i;
12890 break;
ee065d83 12891 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 12892 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
12893 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 12894 {
12895 _bfd_error_handler
a9dc9481
JM		 12896 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
12897 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 12898 }
a9dc9481 12899 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 12900 out_attr[i].i = in_attr[i].i;
12901 break;
ee065d83
PB		 12902 case Tag_ABI_enum_size:
12903 if (in_attr[i].i != AEABI_enum_unused)
12904 {
12905 if (out_attr[i].i == AEABI_enum_unused
12906 || out_attr[i].i == AEABI_enum_forced_wide)
12907 {
12908 /* The existing object is compatible with anything.
12909 Use whatever requirements the new object has. */
12910 out_attr[i].i = in_attr[i].i;
12911 }
12912 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 12913 && out_attr[i].i != in_attr[i].i
0ffa91dd 12914 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 12915 {
91e22acd 12916 static const char *aeabi_enum_names[] =
bf21ed78 12917 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 12918 const char *in_name =
12919 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12920 ? aeabi_enum_names[in_attr[i].i]
12921 : "<unknown>";
12922 const char *out_name =
12923 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12924 ? aeabi_enum_names[out_attr[i].i]
12925 : "<unknown>";
ee065d83 12926 _bfd_error_handler
bf21ed78 12927 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 12928 ibfd, in_name, out_name);
ee065d83
PB		 12929 }
12930 }
12931 break;
12932 case Tag_ABI_VFP_args:
12933 /* Aready done. */
12934 break;
12935 case Tag_ABI_WMMX_args:
12936 if (in_attr[i].i != out_attr[i].i)
12937 {
12938 _bfd_error_handler
3895f852 12939 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 12940 ibfd, obfd);
91e22acd 12941 result = FALSE;
ee065d83
PB		 12942 }
12943 break;
7b86a9fa
AS		 12944 case Tag_compatibility:
12945 /* Merged in target-independent code. */
12946 break;
91e22acd 12947 case Tag_ABI_HardFP_use:
4547cb56 12948 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 12949 break;
12950 case Tag_ABI_FP_16bit_format:
12951 if (in_attr[i].i != 0 && out_attr[i].i != 0)
12952 {
12953 if (in_attr[i].i != out_attr[i].i)
12954 {
12955 _bfd_error_handler
3895f852 12956 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 12957 ibfd, obfd);
12958 result = FALSE;
12959 }
12960 }
12961 if (in_attr[i].i != 0)
12962 out_attr[i].i = in_attr[i].i;
12963 break;
7b86a9fa 12964
cd21e546 12965 case Tag_DIV_use:
ac56ee8f
MGD		 12966 /* A value of zero on input means that the divide instruction may
12967 be used if available in the base architecture as specified via
12968 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
12969 the user did not want divide instructions. A value of 2
12970 explicitly means that divide instructions were allowed in ARM
12971 and Thumb state. */
12972 if (in_attr[i].i == out_attr[i].i)
12973 /* Do nothing. */ ;
12974 else if (elf32_arm_attributes_forbid_div (in_attr)
12975 && !elf32_arm_attributes_accept_div (out_attr))
12976 out_attr[i].i = 1;
12977 else if (elf32_arm_attributes_forbid_div (out_attr)
12978 && elf32_arm_attributes_accept_div (in_attr))
12979 out_attr[i].i = in_attr[i].i;
12980 else if (in_attr[i].i == 2)
12981 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 12982 break;
12983
12984 case Tag_MPextension_use_legacy:
12985 /* We don't output objects with Tag_MPextension_use_legacy - we
12986 move the value to Tag_MPextension_use. */
12987 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
12988 {
12989 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
12990 {
12991 _bfd_error_handler
12992 (_("%B has has both the current and legacy "
b38cadfb 12993 "Tag_MPextension_use attributes"),
cd21e546
MGD		 12994 ibfd);
12995 result = FALSE;
12996 }
12997 }
12998
12999 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
13000 out_attr[Tag_MPextension_use] = in_attr[i];
13001
13002 break;
13003
91e22acd 13004 case Tag_nodefaults:
2d0bb761
AS		 13005 /* This tag is set if it exists, but the value is unused (and is
13006 typically zero). We don't actually need to do anything here -
13007 the merge happens automatically when the type flags are merged
13008 below. */
91e22acd
AS		 13009 break;
13010 case Tag_also_compatible_with:
13011 /* Already done in Tag_CPU_arch. */
13012 break;
13013 case Tag_conformance:
13014 /* Keep the attribute if it matches. Throw it away otherwise.
13015 No attribute means no claim to conform. */
13016 if (!in_attr[i].s || !out_attr[i].s
13017 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
13018 out_attr[i].s = NULL;
13019 break;
3cfad14c 13020
91e22acd 13021 default:
e8b36cd1
JM		 13022 result
13023 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 13024 }
13025
13026 /* If out_attr was copied from in_attr then it won't have a type yet. */
13027 if (in_attr[i].type && !out_attr[i].type)
13028 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 13029 }
13030
104d59d1 13031 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 13032 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
13033 return FALSE;
ee065d83 13034
104d59d1 13035 /* Check for any attributes not known on ARM. */
e8b36cd1 13036 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 13037
91e22acd 13038 return result;
252b5132
RH		 13039}
13040
3a4a14e9
PB		 13041
13042/* Return TRUE if the two EABI versions are incompatible. */
13043
13044static bfd_boolean
13045elf32_arm_versions_compatible (unsigned iver, unsigned over)
13046{
13047 /* v4 and v5 are the same spec before and after it was released,
13048 so allow mixing them. */
13049 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
13050 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
13051 return TRUE;
13052
13053 return (iver == over);
13054}
13055
252b5132
RH		 13056/* Merge backend specific data from an object file to the output
13057 object file when linking. */
9b485d32 13058
b34976b6 13059static bfd_boolean
21d799b5 13060elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 13061
9b485d32
NC		 13062/* Display the flags field. */
13063
b34976b6 13064static bfd_boolean
57e8b36a 13065elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 13066{
fc830a83
NC		 13067 FILE * file = (FILE *) ptr;
13068 unsigned long flags;
252b5132
RH		 13069
13070 BFD_ASSERT (abfd != NULL && ptr != NULL);
13071
13072 /* Print normal ELF private data. */
13073 _bfd_elf_print_private_bfd_data (abfd, ptr);
13074
fc830a83 13075 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 13076 /* Ignore init flag - it may not be set, despite the flags field
13077 containing valid data. */
252b5132
RH		 13078
13079 /* xgettext:c-format */
9b485d32 13080 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 13081
fc830a83
NC		 13082 switch (EF_ARM_EABI_VERSION (flags))
13083 {
13084 case EF_ARM_EABI_UNKNOWN:
4cc11e76 13085 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 13086 official ARM ELF extended ABI. Hence they are only decoded if
13087 the EABI version is not set. */
fd2ec330 13088 if (flags & EF_ARM_INTERWORK)
9b485d32 13089 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 13090
fd2ec330 13091 if (flags & EF_ARM_APCS_26)
6c571f00 13092 fprintf (file, " [APCS-26]");
fc830a83 13093 else
6c571f00 13094 fprintf (file, " [APCS-32]");
9a5aca8c 13095
96a846ea
RE		 13096 if (flags & EF_ARM_VFP_FLOAT)
13097 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 13098 else if (flags & EF_ARM_MAVERICK_FLOAT)
13099 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 13100 else
13101 fprintf (file, _(" [FPA float format]"));
13102
fd2ec330 13103 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 13104 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 13105
fd2ec330 13106 if (flags & EF_ARM_PIC)
9b485d32 13107 fprintf (file, _(" [position independent]"));
fc830a83 13108
fd2ec330 13109 if (flags & EF_ARM_NEW_ABI)
9b485d32 13110 fprintf (file, _(" [new ABI]"));
9a5aca8c 13111
fd2ec330 13112 if (flags & EF_ARM_OLD_ABI)
9b485d32 13113 fprintf (file, _(" [old ABI]"));
9a5aca8c 13114
fd2ec330 13115 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 13116 fprintf (file, _(" [software FP]"));
9a5aca8c 13117
96a846ea
RE		 13118 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
13119 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 13120 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
13121 | EF_ARM_MAVERICK_FLOAT);
fc830a83 13122 break;
9a5aca8c 13123
fc830a83 13124 case EF_ARM_EABI_VER1:
9b485d32 13125 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 13126
fc830a83 13127 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 13128 fprintf (file, _(" [sorted symbol table]"));
fc830a83 13129 else
9b485d32 13130 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 13131
fc830a83
NC		 13132 flags &= ~ EF_ARM_SYMSARESORTED;
13133 break;
9a5aca8c 13134
fd2ec330
PB		 13135 case EF_ARM_EABI_VER2:
13136 fprintf (file, _(" [Version2 EABI]"));
13137
13138 if (flags & EF_ARM_SYMSARESORTED)
13139 fprintf (file, _(" [sorted symbol table]"));
13140 else
13141 fprintf (file, _(" [unsorted symbol table]"));
13142
13143 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
13144 fprintf (file, _(" [dynamic symbols use segment index]"));
13145
13146 if (flags & EF_ARM_MAPSYMSFIRST)
13147 fprintf (file, _(" [mapping symbols precede others]"));
13148
99e4ae17 13149 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 13150 | EF_ARM_MAPSYMSFIRST);
13151 break;
13152
d507cf36
PB		 13153 case EF_ARM_EABI_VER3:
13154 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 13155 break;
13156
13157 case EF_ARM_EABI_VER4:
13158 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 13159 goto eabi;
d507cf36 13160
3a4a14e9
PB		 13161 case EF_ARM_EABI_VER5:
13162 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 13163
13164 if (flags & EF_ARM_ABI_FLOAT_SOFT)
13165 fprintf (file, _(" [soft-float ABI]"));
13166
13167 if (flags & EF_ARM_ABI_FLOAT_HARD)
13168 fprintf (file, _(" [hard-float ABI]"));
13169
13170 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
13171
3a4a14e9 13172 eabi:
d507cf36
PB		 13173 if (flags & EF_ARM_BE8)
13174 fprintf (file, _(" [BE8]"));
13175
13176 if (flags & EF_ARM_LE8)
13177 fprintf (file, _(" [LE8]"));
13178
13179 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
13180 break;
13181
fc830a83 13182 default:
9b485d32 13183 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 13184 break;
13185 }
252b5132 13186
fc830a83 13187 flags &= ~ EF_ARM_EABIMASK;
252b5132 13188
fc830a83 13189 if (flags & EF_ARM_RELEXEC)
9b485d32 13190 fprintf (file, _(" [relocatable executable]"));
252b5132 13191
a5721edd 13192 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 13193
13194 if (flags)
9b485d32 13195 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 13196
252b5132
RH		 13197 fputc ('\n', file);
13198
b34976b6 13199 return TRUE;
252b5132
RH		 13200}
13201
13202static int
57e8b36a 13203elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 13204{
2f0ca46a
NC		 13205 switch (ELF_ST_TYPE (elf_sym->st_info))
13206 {
13207 case STT_ARM_TFUNC:
13208 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 13209
2f0ca46a
NC		 13210 case STT_ARM_16BIT:
13211 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13212 This allows us to distinguish between data used by Thumb instructions
13213 and non-data (which is probably code) inside Thumb regions of an
13214 executable. */
1a0eb693 13215 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 13216 return ELF_ST_TYPE (elf_sym->st_info);
13217 break;
9a5aca8c 13218
ce855c42
NC		 13219 default:
13220 break;
2f0ca46a
NC		 13221 }
13222
13223 return type;
252b5132 13224}
f21f3fe0 13225
252b5132 13226static asection *
07adf181
AM		 13227elf32_arm_gc_mark_hook (asection *sec,
13228 struct bfd_link_info *info,
13229 Elf_Internal_Rela *rel,
13230 struct elf_link_hash_entry *h,
13231 Elf_Internal_Sym *sym)
252b5132
RH		 13232{
13233 if (h != NULL)
07adf181 13234 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 13235 {
13236 case R_ARM_GNU_VTINHERIT:
13237 case R_ARM_GNU_VTENTRY:
07adf181
AM		 13238 return NULL;
13239 }
9ad5cbcf 13240
07adf181 13241 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 13242}
13243
780a67af
NC		 13244/* Update the got entry reference counts for the section being removed. */
13245
b34976b6 13246static bfd_boolean
ba93b8ac
DJ		 13247elf32_arm_gc_sweep_hook (bfd * abfd,
13248 struct bfd_link_info * info,
13249 asection * sec,
13250 const Elf_Internal_Rela * relocs)
252b5132 13251{
5e681ec4
PB		 13252 Elf_Internal_Shdr *symtab_hdr;
13253 struct elf_link_hash_entry **sym_hashes;
13254 bfd_signed_vma *local_got_refcounts;
13255 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 13256 struct elf32_arm_link_hash_table * globals;
13257
0e1862bb 13258 if (bfd_link_relocatable (info))
7dda2462
TG		 13259 return TRUE;
13260
eb043451 13261 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13262 if (globals == NULL)
13263 return FALSE;
5e681ec4
PB		 13264
13265 elf_section_data (sec)->local_dynrel = NULL;
13266
0ffa91dd 13267 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 13268 sym_hashes = elf_sym_hashes (abfd);
13269 local_got_refcounts = elf_local_got_refcounts (abfd);
13270
906e58ca 13271 check_use_blx (globals);
bd97cb95 13272
5e681ec4
PB		 13273 relend = relocs + sec->reloc_count;
13274 for (rel = relocs; rel < relend; rel++)
eb043451 13275 {
3eb128b2
AM		 13276 unsigned long r_symndx;
13277 struct elf_link_hash_entry *h = NULL;
f6e32f6d 13278 struct elf32_arm_link_hash_entry *eh;
eb043451 13279 int r_type;
34e77a92 13280 bfd_boolean call_reloc_p;
f6e32f6d
RS		 13281 bfd_boolean may_become_dynamic_p;
13282 bfd_boolean may_need_local_target_p;
34e77a92
RS		 13283 union gotplt_union *root_plt;
13284 struct arm_plt_info *arm_plt;
5e681ec4 13285
3eb128b2
AM		 13286 r_symndx = ELF32_R_SYM (rel->r_info);
13287 if (r_symndx >= symtab_hdr->sh_info)
13288 {
13289 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13290 while (h->root.type == bfd_link_hash_indirect
13291 || h->root.type == bfd_link_hash_warning)
13292 h = (struct elf_link_hash_entry *) h->root.u.i.link;
13293 }
f6e32f6d
RS		 13294 eh = (struct elf32_arm_link_hash_entry *) h;
13295
34e77a92 13296 call_reloc_p = FALSE;
f6e32f6d
RS		 13297 may_become_dynamic_p = FALSE;
13298 may_need_local_target_p = FALSE;
3eb128b2 13299
eb043451 13300 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13301 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 13302 switch (r_type)
13303 {
13304 case R_ARM_GOT32:
eb043451 13305 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13306 case R_ARM_TLS_GD32:
13307 case R_ARM_TLS_IE32:
3eb128b2 13308 if (h != NULL)
eb043451 13309 {
eb043451
PB		 13310 if (h->got.refcount > 0)
13311 h->got.refcount -= 1;
13312 }
13313 else if (local_got_refcounts != NULL)
13314 {
13315 if (local_got_refcounts[r_symndx] > 0)
13316 local_got_refcounts[r_symndx] -= 1;
13317 }
13318 break;
13319
ba93b8ac 13320 case R_ARM_TLS_LDM32:
4dfe6ac6 13321 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 13322 break;
13323
eb043451
PB		 13324 case R_ARM_PC24:
13325 case R_ARM_PLT32:
5b5bb741
PB		 13326 case R_ARM_CALL:
13327 case R_ARM_JUMP24:
eb043451 13328 case R_ARM_PREL31:
c19d1205 13329 case R_ARM_THM_CALL:
bd97cb95
DJ		 13330 case R_ARM_THM_JUMP24:
13331 case R_ARM_THM_JUMP19:
34e77a92 13332 call_reloc_p = TRUE;
f6e32f6d
RS		 13333 may_need_local_target_p = TRUE;
13334 break;
13335
13336 case R_ARM_ABS12:
13337 if (!globals->vxworks_p)
13338 {
13339 may_need_local_target_p = TRUE;
13340 break;
13341 }
13342 /* Fall through. */
13343 case R_ARM_ABS32:
13344 case R_ARM_ABS32_NOI:
13345 case R_ARM_REL32:
13346 case R_ARM_REL32_NOI:
b6895b4f
PB		 13347 case R_ARM_MOVW_ABS_NC:
13348 case R_ARM_MOVT_ABS:
13349 case R_ARM_MOVW_PREL_NC:
13350 case R_ARM_MOVT_PREL:
13351 case R_ARM_THM_MOVW_ABS_NC:
13352 case R_ARM_THM_MOVT_ABS:
13353 case R_ARM_THM_MOVW_PREL_NC:
13354 case R_ARM_THM_MOVT_PREL:
b7693d02 13355 /* Should the interworking branches be here also? */
0e1862bb 13356 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 13357 && (sec->flags & SEC_ALLOC) != 0)
13358 {
13359 if (h == NULL
469a3493 13360 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13361 {
13362 call_reloc_p = TRUE;
13363 may_need_local_target_p = TRUE;
13364 }
13365 else
13366 may_become_dynamic_p = TRUE;
13367 }
f6e32f6d
RS		 13368 else
13369 may_need_local_target_p = TRUE;
13370 break;
b7693d02 13371
f6e32f6d
RS		 13372 default:
13373 break;
13374 }
5e681ec4 13375
34e77a92
RS		 13376 if (may_need_local_target_p
13377 && elf32_arm_get_plt_info (abfd, eh, r_symndx, &root_plt, &arm_plt))
f6e32f6d 13378 {
27586251
HPN		 13379 /* If PLT refcount book-keeping is wrong and too low, we'll
13380 see a zero value (going to -1) for the root PLT reference
13381 count. */
13382 if (root_plt->refcount >= 0)
13383 {
13384 BFD_ASSERT (root_plt->refcount != 0);
13385 root_plt->refcount -= 1;
13386 }
13387 else
13388 /* A value of -1 means the symbol has become local, forced
13389 or seeing a hidden definition. Any other negative value
13390 is an error. */
13391 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 13392
13393 if (!call_reloc_p)
13394 arm_plt->noncall_refcount--;
5e681ec4 13395
f6e32f6d 13396 if (r_type == R_ARM_THM_CALL)
34e77a92 13397 arm_plt->maybe_thumb_refcount--;
bd97cb95 13398
f6e32f6d
RS		 13399 if (r_type == R_ARM_THM_JUMP24
13400 || r_type == R_ARM_THM_JUMP19)
34e77a92 13401 arm_plt->thumb_refcount--;
f6e32f6d 13402 }
5e681ec4 13403
34e77a92 13404 if (may_become_dynamic_p)
f6e32f6d
RS		 13405 {
13406 struct elf_dyn_relocs **pp;
13407 struct elf_dyn_relocs *p;
5e681ec4 13408
34e77a92 13409 if (h != NULL)
9c489990 13410 pp = &(eh->dyn_relocs);
34e77a92
RS		 13411 else
13412 {
13413 Elf_Internal_Sym *isym;
13414
13415 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
13416 abfd, r_symndx);
13417 if (isym == NULL)
13418 return FALSE;
13419 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13420 if (pp == NULL)
13421 return FALSE;
13422 }
9c489990 13423 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 13424 if (p->sec == sec)
13425 {
13426 /* Everything must go for SEC. */
13427 *pp = p->next;
13428 break;
13429 }
eb043451
PB		 13430 }
13431 }
5e681ec4 13432
b34976b6 13433 return TRUE;
252b5132
RH		 13434}
13435
780a67af
NC		 13436/* Look through the relocs for a section during the first phase. */
13437
b34976b6 13438static bfd_boolean
57e8b36a
NC		 13439elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
13440 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 13441{
b34976b6
AM		 13442 Elf_Internal_Shdr *symtab_hdr;
13443 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 13444 const Elf_Internal_Rela *rel;
13445 const Elf_Internal_Rela *rel_end;
13446 bfd *dynobj;
5e681ec4 13447 asection *sreloc;
5e681ec4 13448 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 13449 bfd_boolean call_reloc_p;
13450 bfd_boolean may_become_dynamic_p;
13451 bfd_boolean may_need_local_target_p;
ce98a316 13452 unsigned long nsyms;
9a5aca8c 13453
0e1862bb 13454 if (bfd_link_relocatable (info))
b34976b6 13455 return TRUE;
9a5aca8c 13456
0ffa91dd
NC		 13457 BFD_ASSERT (is_arm_elf (abfd));
13458
5e681ec4 13459 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13460 if (htab == NULL)
13461 return FALSE;
13462
5e681ec4 13463 sreloc = NULL;
9a5aca8c 13464
67687978
PB		 13465 /* Create dynamic sections for relocatable executables so that we can
13466 copy relocations. */
13467 if (htab->root.is_relocatable_executable
13468 && ! htab->root.dynamic_sections_created)
13469 {
13470 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
13471 return FALSE;
13472 }
13473
cbc704f3
RS		 13474 if (htab->root.dynobj == NULL)
13475 htab->root.dynobj = abfd;
34e77a92
RS		 13476 if (!create_ifunc_sections (info))
13477 return FALSE;
cbc704f3
RS		 13478
13479 dynobj = htab->root.dynobj;
13480
0ffa91dd 13481 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 13482 sym_hashes = elf_sym_hashes (abfd);
ce98a316 13483 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 13484
252b5132
RH		 13485 rel_end = relocs + sec->reloc_count;
13486 for (rel = relocs; rel < rel_end; rel++)
13487 {
34e77a92 13488 Elf_Internal_Sym *isym;
252b5132 13489 struct elf_link_hash_entry *h;
b7693d02 13490 struct elf32_arm_link_hash_entry *eh;
252b5132 13491 unsigned long r_symndx;
eb043451 13492 int r_type;
9a5aca8c 13493
252b5132 13494 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 13495 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13496 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 13497
ce98a316
NC		 13498 if (r_symndx >= nsyms
13499 /* PR 9934: It is possible to have relocations that do not
13500 refer to symbols, thus it is also possible to have an
13501 object file containing relocations but no symbol table. */
cf35638d 13502 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 13503 {
13504 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 13505 r_symndx);
ba93b8ac
DJ		 13506 return FALSE;
13507 }
13508
34e77a92
RS		 13509 h = NULL;
13510 isym = NULL;
13511 if (nsyms > 0)
973a3492 13512 {
34e77a92
RS		 13513 if (r_symndx < symtab_hdr->sh_info)
13514 {
13515 /* A local symbol. */
13516 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
13517 abfd, r_symndx);
13518 if (isym == NULL)
13519 return FALSE;
13520 }
13521 else
13522 {
13523 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13524 while (h->root.type == bfd_link_hash_indirect
13525 || h->root.type == bfd_link_hash_warning)
13526 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 13527
13528 /* PR15323, ref flags aren't set for references in the
13529 same object. */
13530 h->root.non_ir_ref = 1;
34e77a92 13531 }
973a3492 13532 }
9a5aca8c 13533
b7693d02
DJ		 13534 eh = (struct elf32_arm_link_hash_entry *) h;
13535
f6e32f6d
RS		 13536 call_reloc_p = FALSE;
13537 may_become_dynamic_p = FALSE;
13538 may_need_local_target_p = FALSE;
13539
0855e32b
NS		 13540 /* Could be done earlier, if h were already available. */
13541 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 13542 switch (r_type)
99059e56 13543 {
5e681ec4 13544 case R_ARM_GOT32:
eb043451 13545 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13546 case R_ARM_TLS_GD32:
13547 case R_ARM_TLS_IE32:
0855e32b
NS		 13548 case R_ARM_TLS_GOTDESC:
13549 case R_ARM_TLS_DESCSEQ:
13550 case R_ARM_THM_TLS_DESCSEQ:
13551 case R_ARM_TLS_CALL:
13552 case R_ARM_THM_TLS_CALL:
5e681ec4 13553 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 13554 {
13555 int tls_type, old_tls_type;
5e681ec4 13556
ba93b8ac
DJ		 13557 switch (r_type)
13558 {
13559 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 13560
ba93b8ac 13561 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 13562
0855e32b
NS		 13563 case R_ARM_TLS_GOTDESC:
13564 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
13565 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
13566 tls_type = GOT_TLS_GDESC; break;
b38cadfb 13567
ba93b8ac
DJ		 13568 default: tls_type = GOT_NORMAL; break;
13569 }
252b5132 13570
0e1862bb 13571 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 13572 info->flags |= DF_STATIC_TLS;
13573
ba93b8ac
DJ		 13574 if (h != NULL)
13575 {
13576 h->got.refcount++;
13577 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
13578 }
13579 else
13580 {
ba93b8ac 13581 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 13582 if (!elf32_arm_allocate_local_sym_info (abfd))
13583 return FALSE;
13584 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 13585 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
13586 }
13587
0855e32b 13588 /* If a variable is accessed with both tls methods, two
99059e56 13589 slots may be created. */
0855e32b
NS		 13590 if (GOT_TLS_GD_ANY_P (old_tls_type)
13591 && GOT_TLS_GD_ANY_P (tls_type))
13592 tls_type |= old_tls_type;
13593
13594 /* We will already have issued an error message if there
13595 is a TLS/non-TLS mismatch, based on the symbol
13596 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 13597 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
13598 && tls_type != GOT_NORMAL)
13599 tls_type |= old_tls_type;
13600
0855e32b 13601 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 13602 method, we're able to relax. Turn off the GDESC flag,
13603 without messing up with any other kind of tls types
6a631e86 13604 that may be involved. */
0855e32b
NS		 13605 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
13606 tls_type &= ~GOT_TLS_GDESC;
13607
ba93b8ac
DJ		 13608 if (old_tls_type != tls_type)
13609 {
13610 if (h != NULL)
13611 elf32_arm_hash_entry (h)->tls_type = tls_type;
13612 else
13613 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
13614 }
13615 }
8029a119 13616 /* Fall through. */
ba93b8ac
DJ		 13617
13618 case R_ARM_TLS_LDM32:
13619 if (r_type == R_ARM_TLS_LDM32)
13620 htab->tls_ldm_got.refcount++;
8029a119 13621 /* Fall through. */
252b5132 13622
c19d1205 13623 case R_ARM_GOTOFF32:
5e681ec4 13624 case R_ARM_GOTPC:
cbc704f3
RS		 13625 if (htab->root.sgot == NULL
13626 && !create_got_section (htab->root.dynobj, info))
13627 return FALSE;
252b5132
RH		 13628 break;
13629
252b5132 13630 case R_ARM_PC24:
7359ea65 13631 case R_ARM_PLT32:
5b5bb741
PB		 13632 case R_ARM_CALL:
13633 case R_ARM_JUMP24:
eb043451 13634 case R_ARM_PREL31:
c19d1205 13635 case R_ARM_THM_CALL:
bd97cb95
DJ		 13636 case R_ARM_THM_JUMP24:
13637 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 13638 call_reloc_p = TRUE;
13639 may_need_local_target_p = TRUE;
13640 break;
13641
13642 case R_ARM_ABS12:
13643 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
13644 ldr __GOTT_INDEX__ offsets. */
13645 if (!htab->vxworks_p)
13646 {
13647 may_need_local_target_p = TRUE;
13648 break;
13649 }
aebf9be7
NC		 13650 else goto jump_over;
13651
f6e32f6d 13652 /* Fall through. */
39623e12 13653
96c23d59
JM		 13654 case R_ARM_MOVW_ABS_NC:
13655 case R_ARM_MOVT_ABS:
13656 case R_ARM_THM_MOVW_ABS_NC:
13657 case R_ARM_THM_MOVT_ABS:
0e1862bb 13658 if (bfd_link_pic (info))
96c23d59
JM		 13659 {
13660 (*_bfd_error_handler)
13661 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
13662 abfd, elf32_arm_howto_table_1[r_type].name,
13663 (h) ? h->root.root.string : "a local symbol");
13664 bfd_set_error (bfd_error_bad_value);
13665 return FALSE;
13666 }
13667
13668 /* Fall through. */
39623e12
PB		 13669 case R_ARM_ABS32:
13670 case R_ARM_ABS32_NOI:
aebf9be7 13671 jump_over:
0e1862bb 13672 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 13673 {
13674 h->pointer_equality_needed = 1;
13675 }
13676 /* Fall through. */
39623e12
PB		 13677 case R_ARM_REL32:
13678 case R_ARM_REL32_NOI:
b6895b4f
PB		 13679 case R_ARM_MOVW_PREL_NC:
13680 case R_ARM_MOVT_PREL:
b6895b4f
PB		 13681 case R_ARM_THM_MOVW_PREL_NC:
13682 case R_ARM_THM_MOVT_PREL:
39623e12 13683
b7693d02 13684 /* Should the interworking branches be listed here? */
0e1862bb 13685 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 13686 && (sec->flags & SEC_ALLOC) != 0)
13687 {
13688 if (h == NULL
469a3493 13689 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13690 {
13691 /* In shared libraries and relocatable executables,
13692 we treat local relative references as calls;
13693 see the related SYMBOL_CALLS_LOCAL code in
13694 allocate_dynrelocs. */
13695 call_reloc_p = TRUE;
13696 may_need_local_target_p = TRUE;
13697 }
13698 else
13699 /* We are creating a shared library or relocatable
13700 executable, and this is a reloc against a global symbol,
13701 or a non-PC-relative reloc against a local symbol.
13702 We may need to copy the reloc into the output. */
13703 may_become_dynamic_p = TRUE;
13704 }
f6e32f6d
RS		 13705 else
13706 may_need_local_target_p = TRUE;
252b5132
RH		 13707 break;
13708
99059e56
RM		 13709 /* This relocation describes the C++ object vtable hierarchy.
13710 Reconstruct it for later use during GC. */
13711 case R_ARM_GNU_VTINHERIT:
13712 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
13713 return FALSE;
13714 break;
13715
13716 /* This relocation describes which C++ vtable entries are actually
13717 used. Record for later use during GC. */
13718 case R_ARM_GNU_VTENTRY:
13719 BFD_ASSERT (h != NULL);
13720 if (h != NULL
13721 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
13722 return FALSE;
13723 break;
13724 }
f6e32f6d
RS		 13725
13726 if (h != NULL)
13727 {
13728 if (call_reloc_p)
13729 /* We may need a .plt entry if the function this reloc
13730 refers to is in a different object, regardless of the
13731 symbol's type. We can't tell for sure yet, because
13732 something later might force the symbol local. */
13733 h->needs_plt = 1;
13734 else if (may_need_local_target_p)
13735 /* If this reloc is in a read-only section, we might
13736 need a copy reloc. We can't check reliably at this
13737 stage whether the section is read-only, as input
13738 sections have not yet been mapped to output sections.
13739 Tentatively set the flag for now, and correct in
13740 adjust_dynamic_symbol. */
13741 h->non_got_ref = 1;
13742 }
13743
34e77a92
RS		 13744 if (may_need_local_target_p
13745 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 13746 {
34e77a92
RS		 13747 union gotplt_union *root_plt;
13748 struct arm_plt_info *arm_plt;
13749 struct arm_local_iplt_info *local_iplt;
13750
13751 if (h != NULL)
13752 {
13753 root_plt = &h->plt;
13754 arm_plt = &eh->plt;
13755 }
13756 else
13757 {
13758 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
13759 if (local_iplt == NULL)
13760 return FALSE;
13761 root_plt = &local_iplt->root;
13762 arm_plt = &local_iplt->arm;
13763 }
13764
f6e32f6d
RS		 13765 /* If the symbol is a function that doesn't bind locally,
13766 this relocation will need a PLT entry. */
a8c887dd
NC		 13767 if (root_plt->refcount != -1)
13768 root_plt->refcount += 1;
34e77a92
RS		 13769
13770 if (!call_reloc_p)
13771 arm_plt->noncall_refcount++;
f6e32f6d
RS		 13772
13773 /* It's too early to use htab->use_blx here, so we have to
13774 record possible blx references separately from
13775 relocs that definitely need a thumb stub. */
13776
13777 if (r_type == R_ARM_THM_CALL)
34e77a92 13778 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 13779
13780 if (r_type == R_ARM_THM_JUMP24
13781 || r_type == R_ARM_THM_JUMP19)
34e77a92 13782 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 13783 }
13784
13785 if (may_become_dynamic_p)
13786 {
13787 struct elf_dyn_relocs *p, **head;
13788
13789 /* Create a reloc section in dynobj. */
13790 if (sreloc == NULL)
13791 {
13792 sreloc = _bfd_elf_make_dynamic_reloc_section
13793 (sec, dynobj, 2, abfd, ! htab->use_rel);
13794
13795 if (sreloc == NULL)
13796 return FALSE;
13797
13798 /* BPABI objects never have dynamic relocations mapped. */
13799 if (htab->symbian_p)
13800 {
13801 flagword flags;
13802
13803 flags = bfd_get_section_flags (dynobj, sreloc);
13804 flags &= ~(SEC_LOAD | SEC_ALLOC);
13805 bfd_set_section_flags (dynobj, sreloc, flags);
13806 }
13807 }
13808
13809 /* If this is a global symbol, count the number of
13810 relocations we need for this symbol. */
13811 if (h != NULL)
13812 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
13813 else
13814 {
34e77a92
RS		 13815 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13816 if (head == NULL)
f6e32f6d 13817 return FALSE;
f6e32f6d
RS		 13818 }
13819
13820 p = *head;
13821 if (p == NULL || p->sec != sec)
13822 {
13823 bfd_size_type amt = sizeof *p;
13824
13825 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
13826 if (p == NULL)
13827 return FALSE;
13828 p->next = *head;
13829 *head = p;
13830 p->sec = sec;
13831 p->count = 0;
13832 p->pc_count = 0;
13833 }
13834
469a3493 13835 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 13836 p->pc_count += 1;
13837 p->count += 1;
13838 }
252b5132 13839 }
f21f3fe0 13840
b34976b6 13841 return TRUE;
252b5132
RH		 13842}
13843
6a5bb875
PB		 13844/* Unwinding tables are not referenced directly. This pass marks them as
13845 required if the corresponding code section is marked. */
13846
13847static bfd_boolean
906e58ca
NC		 13848elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
13849 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 13850{
13851 bfd *sub;
13852 Elf_Internal_Shdr **elf_shdrp;
13853 bfd_boolean again;
13854
7f6ab9f8
AM		 13855 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
13856
6a5bb875
PB		 13857 /* Marking EH data may cause additional code sections to be marked,
13858 requiring multiple passes. */
13859 again = TRUE;
13860 while (again)
13861 {
13862 again = FALSE;
c72f2fb2 13863 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 13864 {
13865 asection *o;
13866
0ffa91dd 13867 if (! is_arm_elf (sub))
6a5bb875
PB		 13868 continue;
13869
13870 elf_shdrp = elf_elfsections (sub);
13871 for (o = sub->sections; o != NULL; o = o->next)
13872 {
13873 Elf_Internal_Shdr *hdr;
0ffa91dd 13874
6a5bb875 13875 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 13876 if (hdr->sh_type == SHT_ARM_EXIDX
13877 && hdr->sh_link
13878 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 13879 && !o->gc_mark
13880 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
13881 {
13882 again = TRUE;
13883 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
13884 return FALSE;
13885 }
13886 }
13887 }
13888 }
13889
13890 return TRUE;
13891}
13892
3c9458e9
NC		 13893/* Treat mapping symbols as special target symbols. */
13894
13895static bfd_boolean
13896elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
13897{
b0796911
PB		 13898 return bfd_is_arm_special_symbol_name (sym->name,
13899 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 13900}
13901
0367ecfb
NC		 13902/* This is a copy of elf_find_function() from elf.c except that
13903 ARM mapping symbols are ignored when looking for function names
13904 and STT_ARM_TFUNC is considered to a function type. */
252b5132 13905
0367ecfb
NC		 13906static bfd_boolean
13907arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 13908 asymbol ** symbols,
fb167eb2 13909 asection * section,
0367ecfb
NC		 13910 bfd_vma offset,
13911 const char ** filename_ptr,
13912 const char ** functionname_ptr)
13913{
13914 const char * filename = NULL;
13915 asymbol * func = NULL;
13916 bfd_vma low_func = 0;
13917 asymbol ** p;
252b5132
RH		 13918
13919 for (p = symbols; *p != NULL; p++)
13920 {
13921 elf_symbol_type *q;
13922
13923 q = (elf_symbol_type *) *p;
13924
252b5132
RH		 13925 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
13926 {
13927 default:
13928 break;
13929 case STT_FILE:
13930 filename = bfd_asymbol_name (&q->symbol);
13931 break;
252b5132
RH		 13932 case STT_FUNC:
13933 case STT_ARM_TFUNC:
9d2da7ca 13934 case STT_NOTYPE:
b0796911 13935 /* Skip mapping symbols. */
0367ecfb 13936 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 13937 && bfd_is_arm_special_symbol_name (q->symbol.name,
13938 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 13939 continue;
13940 /* Fall through. */
6b40fcba 13941 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 13942 && q->symbol.value >= low_func
13943 && q->symbol.value <= offset)
13944 {
13945 func = (asymbol *) q;
13946 low_func = q->symbol.value;
13947 }
13948 break;
13949 }
13950 }
13951
13952 if (func == NULL)
b34976b6 13953 return FALSE;
252b5132 13954
0367ecfb
NC		 13955 if (filename_ptr)
13956 *filename_ptr = filename;
13957 if (functionname_ptr)
13958 *functionname_ptr = bfd_asymbol_name (func);
13959
13960 return TRUE;
906e58ca 13961}
0367ecfb
NC		 13962
13963
13964/* Find the nearest line to a particular section and offset, for error
13965 reporting. This code is a duplicate of the code in elf.c, except
13966 that it uses arm_elf_find_function. */
13967
13968static bfd_boolean
13969elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 13970 asymbol ** symbols,
fb167eb2 13971 asection * section,
0367ecfb
NC		 13972 bfd_vma offset,
13973 const char ** filename_ptr,
13974 const char ** functionname_ptr,
fb167eb2
AM		 13975 unsigned int * line_ptr,
13976 unsigned int * discriminator_ptr)
0367ecfb
NC		 13977{
13978 bfd_boolean found = FALSE;
13979
fb167eb2 13980 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 13981 filename_ptr, functionname_ptr,
fb167eb2
AM		 13982 line_ptr, discriminator_ptr,
13983 dwarf_debug_sections, 0,
0367ecfb
NC		 13984 & elf_tdata (abfd)->dwarf2_find_line_info))
13985 {
13986 if (!*functionname_ptr)
fb167eb2 13987 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 13988 *filename_ptr ? NULL : filename_ptr,
13989 functionname_ptr);
f21f3fe0 13990
0367ecfb
NC		 13991 return TRUE;
13992 }
13993
fb167eb2
AM		 13994 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
13995 uses DWARF1. */
13996
0367ecfb
NC		 13997 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
13998 & found, filename_ptr,
13999 functionname_ptr, line_ptr,
14000 & elf_tdata (abfd)->line_info))
14001 return FALSE;
14002
14003 if (found && (*functionname_ptr || *line_ptr))
14004 return TRUE;
14005
14006 if (symbols == NULL)
14007 return FALSE;
14008
fb167eb2 14009 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14010 filename_ptr, functionname_ptr))
14011 return FALSE;
14012
14013 *line_ptr = 0;
b34976b6 14014 return TRUE;
252b5132
RH		 14015}
14016
4ab527b0
FF		 14017static bfd_boolean
14018elf32_arm_find_inliner_info (bfd * abfd,
14019 const char ** filename_ptr,
14020 const char ** functionname_ptr,
14021 unsigned int * line_ptr)
14022{
14023 bfd_boolean found;
14024 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
14025 functionname_ptr, line_ptr,
14026 & elf_tdata (abfd)->dwarf2_find_line_info);
14027 return found;
14028}
14029
252b5132
RH		 14030/* Adjust a symbol defined by a dynamic object and referenced by a
14031 regular object. The current definition is in some section of the
14032 dynamic object, but we're not including those sections. We have to
14033 change the definition to something the rest of the link can
14034 understand. */
14035
b34976b6 14036static bfd_boolean
57e8b36a
NC		 14037elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
14038 struct elf_link_hash_entry * h)
252b5132
RH		 14039{
14040 bfd * dynobj;
14041 asection * s;
b7693d02 14042 struct elf32_arm_link_hash_entry * eh;
67687978 14043 struct elf32_arm_link_hash_table *globals;
252b5132 14044
67687978 14045 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14046 if (globals == NULL)
14047 return FALSE;
14048
252b5132
RH		 14049 dynobj = elf_hash_table (info)->dynobj;
14050
14051 /* Make sure we know what is going on here. */
14052 BFD_ASSERT (dynobj != NULL
f5385ebf 14053 && (h->needs_plt
34e77a92 14054 || h->type == STT_GNU_IFUNC
f6e332e6 14055 || h->u.weakdef != NULL
f5385ebf
AM		 14056 || (h->def_dynamic
14057 && h->ref_regular
14058 && !h->def_regular)));
252b5132 14059
b7693d02
DJ		 14060 eh = (struct elf32_arm_link_hash_entry *) h;
14061
252b5132
RH		 14062 /* If this is a function, put it in the procedure linkage table. We
14063 will fill in the contents of the procedure linkage table later,
14064 when we know the address of the .got section. */
34e77a92 14065 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 14066 {
34e77a92
RS		 14067 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
14068 symbol binds locally. */
5e681ec4 14069 if (h->plt.refcount <= 0
34e77a92
RS		 14070 || (h->type != STT_GNU_IFUNC
14071 && (SYMBOL_CALLS_LOCAL (info, h)
14072 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
14073 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 14074 {
14075 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 14076 file, but the symbol was never referred to by a dynamic
14077 object, or if all references were garbage collected. In
14078 such a case, we don't actually need to build a procedure
14079 linkage table, and we can just do a PC24 reloc instead. */
14080 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14081 eh->plt.thumb_refcount = 0;
14082 eh->plt.maybe_thumb_refcount = 0;
14083 eh->plt.noncall_refcount = 0;
f5385ebf 14084 h->needs_plt = 0;
252b5132
RH		 14085 }
14086
b34976b6 14087 return TRUE;
252b5132 14088 }
5e681ec4 14089 else
b7693d02
DJ		 14090 {
14091 /* It's possible that we incorrectly decided a .plt reloc was
14092 needed for an R_ARM_PC24 or similar reloc to a non-function sym
14093 in check_relocs. We can't decide accurately between function
14094 and non-function syms in check-relocs; Objects loaded later in
14095 the link may change h->type. So fix it now. */
14096 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14097 eh->plt.thumb_refcount = 0;
14098 eh->plt.maybe_thumb_refcount = 0;
14099 eh->plt.noncall_refcount = 0;
b7693d02 14100 }
252b5132
RH		 14101
14102 /* If this is a weak symbol, and there is a real definition, the
14103 processor independent code will have arranged for us to see the
14104 real definition first, and we can just use the same value. */
f6e332e6 14105 if (h->u.weakdef != NULL)
252b5132 14106 {
f6e332e6
AM		 14107 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
14108 || h->u.weakdef->root.type == bfd_link_hash_defweak);
14109 h->root.u.def.section = h->u.weakdef->root.u.def.section;
14110 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 14111 return TRUE;
252b5132
RH		 14112 }
14113
ba93b8ac
DJ		 14114 /* If there are no non-GOT references, we do not need a copy
14115 relocation. */
14116 if (!h->non_got_ref)
14117 return TRUE;
14118
252b5132
RH		 14119 /* This is a reference to a symbol defined by a dynamic object which
14120 is not a function. */
14121
14122 /* If we are creating a shared library, we must presume that the
14123 only references to the symbol are via the global offset table.
14124 For such cases we need not do anything here; the relocations will
67687978
PB		 14125 be handled correctly by relocate_section. Relocatable executables
14126 can reference data in shared objects directly, so we don't need to
14127 do anything here. */
0e1862bb 14128 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 14129 return TRUE;
252b5132
RH		 14130
14131 /* We must allocate the symbol in our .dynbss section, which will
14132 become part of the .bss section of the executable. There will be
14133 an entry for this symbol in the .dynsym section. The dynamic
14134 object will contain position independent code, so all references
14135 from the dynamic object to this symbol will go through the global
14136 offset table. The dynamic linker will use the .dynsym entry to
14137 determine the address it must put in the global offset table, so
14138 both the dynamic object and the regular object will refer to the
14139 same memory location for the variable. */
3d4d4302 14140 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 14141 BFD_ASSERT (s != NULL);
14142
5522f910
NC		 14143 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
14144 linker to copy the initial value out of the dynamic object and into
14145 the runtime process image. We need to remember the offset into the
00a97672 14146 .rel(a).bss section we are going to use. */
5522f910
NC		 14147 if (info->nocopyreloc == 0
14148 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 14149 && h->size != 0)
252b5132
RH		 14150 {
14151 asection *srel;
14152
3d4d4302 14153 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 14154 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 14155 h->needs_copy = 1;
252b5132
RH		 14156 }
14157
6cabe1ea 14158 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 14159}
14160
5e681ec4
PB		 14161/* Allocate space in .plt, .got and associated reloc sections for
14162 dynamic relocs. */
14163
14164static bfd_boolean
47beaa6a 14165allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 14166{
14167 struct bfd_link_info *info;
14168 struct elf32_arm_link_hash_table *htab;
14169 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 14170 struct elf_dyn_relocs *p;
5e681ec4
PB		 14171
14172 if (h->root.type == bfd_link_hash_indirect)
14173 return TRUE;
14174
e6a6bb22
AM		 14175 eh = (struct elf32_arm_link_hash_entry *) h;
14176
5e681ec4
PB		 14177 info = (struct bfd_link_info *) inf;
14178 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14179 if (htab == NULL)
14180 return FALSE;
5e681ec4 14181
34e77a92 14182 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 14183 && h->plt.refcount > 0)
14184 {
14185 /* Make sure this symbol is output as a dynamic symbol.
14186 Undefined weak syms won't yet be marked as dynamic. */
14187 if (h->dynindx == -1
f5385ebf 14188 && !h->forced_local)
5e681ec4 14189 {
c152c796 14190 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14191 return FALSE;
14192 }
14193
34e77a92
RS		 14194 /* If the call in the PLT entry binds locally, the associated
14195 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14196 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14197 than the .plt section. */
14198 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
14199 {
14200 eh->is_iplt = 1;
14201 if (eh->plt.noncall_refcount == 0
14202 && SYMBOL_REFERENCES_LOCAL (info, h))
14203 /* All non-call references can be resolved directly.
14204 This means that they can (and in some cases, must)
14205 resolve directly to the run-time target, rather than
14206 to the PLT. That in turns means that any .got entry
14207 would be equal to the .igot.plt entry, so there's
14208 no point having both. */
14209 h->got.refcount = 0;
14210 }
14211
0e1862bb 14212 if (bfd_link_pic (info)
34e77a92 14213 || eh->is_iplt
7359ea65 14214 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 14215 {
34e77a92 14216 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 14217
5e681ec4
PB		 14218 /* If this symbol is not defined in a regular file, and we are
14219 not generating a shared library, then set the symbol to this
14220 location in the .plt. This is required to make function
14221 pointers compare as equal between the normal executable and
14222 the shared library. */
0e1862bb 14223 if (! bfd_link_pic (info)
f5385ebf 14224 && !h->def_regular)
5e681ec4 14225 {
34e77a92 14226 h->root.u.def.section = htab->root.splt;
5e681ec4 14227 h->root.u.def.value = h->plt.offset;
5e681ec4 14228
67d74e43
DJ		 14229 /* Make sure the function is not marked as Thumb, in case
14230 it is the target of an ABS32 relocation, which will
14231 point to the PLT entry. */
35fc36a8 14232 h->target_internal = ST_BRANCH_TO_ARM;
67d74e43 14233 }
022f8312 14234
00a97672
RS		 14235 /* VxWorks executables have a second set of relocations for
14236 each PLT entry. They go in a separate relocation section,
14237 which is processed by the kernel loader. */
0e1862bb 14238 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 14239 {
14240 /* There is a relocation for the initial PLT entry:
14241 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14242 if (h->plt.offset == htab->plt_header_size)
47beaa6a 14243 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 14244
14245 /* There are two extra relocations for each subsequent
14246 PLT entry: an R_ARM_32 relocation for the GOT entry,
14247 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 14248 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 14249 }
5e681ec4
PB		 14250 }
14251 else
14252 {
14253 h->plt.offset = (bfd_vma) -1;
f5385ebf 14254 h->needs_plt = 0;
5e681ec4
PB		 14255 }
14256 }
14257 else
14258 {
14259 h->plt.offset = (bfd_vma) -1;
f5385ebf 14260 h->needs_plt = 0;
5e681ec4
PB		 14261 }
14262
0855e32b
NS		 14263 eh = (struct elf32_arm_link_hash_entry *) h;
14264 eh->tlsdesc_got = (bfd_vma) -1;
14265
5e681ec4
PB		 14266 if (h->got.refcount > 0)
14267 {
14268 asection *s;
14269 bfd_boolean dyn;
ba93b8ac
DJ		 14270 int tls_type = elf32_arm_hash_entry (h)->tls_type;
14271 int indx;
5e681ec4
PB		 14272
14273 /* Make sure this symbol is output as a dynamic symbol.
14274 Undefined weak syms won't yet be marked as dynamic. */
14275 if (h->dynindx == -1
f5385ebf 14276 && !h->forced_local)
5e681ec4 14277 {
c152c796 14278 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14279 return FALSE;
14280 }
14281
e5a52504
MM		 14282 if (!htab->symbian_p)
14283 {
362d30a1 14284 s = htab->root.sgot;
e5a52504 14285 h->got.offset = s->size;
ba93b8ac
DJ		 14286
14287 if (tls_type == GOT_UNKNOWN)
14288 abort ();
14289
14290 if (tls_type == GOT_NORMAL)
14291 /* Non-TLS symbols need one GOT slot. */
14292 s->size += 4;
14293 else
14294 {
99059e56
RM		 14295 if (tls_type & GOT_TLS_GDESC)
14296 {
0855e32b 14297 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 14298 eh->tlsdesc_got
0855e32b
NS		 14299 = (htab->root.sgotplt->size
14300 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 14301 htab->root.sgotplt->size += 8;
14302 h->got.offset = (bfd_vma) -2;
34e77a92 14303 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14304 reloc in the middle of .got.plt. */
99059e56
RM		 14305 htab->num_tls_desc++;
14306 }
0855e32b 14307
ba93b8ac 14308 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 14309 {
14310 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14311 the symbol is both GD and GDESC, got.offset may
14312 have been overwritten. */
14313 h->got.offset = s->size;
14314 s->size += 8;
14315 }
14316
ba93b8ac
DJ		 14317 if (tls_type & GOT_TLS_IE)
14318 /* R_ARM_TLS_IE32 needs one GOT slot. */
14319 s->size += 4;
14320 }
14321
e5a52504 14322 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 14323
14324 indx = 0;
0e1862bb
L		 14325 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
14326 bfd_link_pic (info),
14327 h)
14328 && (!bfd_link_pic (info)
ba93b8ac
DJ		 14329 || !SYMBOL_REFERENCES_LOCAL (info, h)))
14330 indx = h->dynindx;
14331
14332 if (tls_type != GOT_NORMAL
0e1862bb 14333 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 14334 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14335 || h->root.type != bfd_link_hash_undefweak))
14336 {
14337 if (tls_type & GOT_TLS_IE)
47beaa6a 14338 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14339
14340 if (tls_type & GOT_TLS_GD)
47beaa6a 14341 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14342
b38cadfb 14343 if (tls_type & GOT_TLS_GDESC)
0855e32b 14344 {
47beaa6a 14345 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 14346 /* GDESC needs a trampoline to jump to. */
14347 htab->tls_trampoline = -1;
14348 }
14349
14350 /* Only GD needs it. GDESC just emits one relocation per
14351 2 entries. */
b38cadfb 14352 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 14353 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14354 }
6f820c85 14355 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 14356 {
14357 if (htab->root.dynamic_sections_created)
14358 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
14359 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
14360 }
34e77a92
RS		 14361 else if (h->type == STT_GNU_IFUNC
14362 && eh->plt.noncall_refcount == 0)
14363 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
14364 they all resolve dynamically instead. Reserve room for the
14365 GOT entry's R_ARM_IRELATIVE relocation. */
14366 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 14367 else if (bfd_link_pic (info)
14368 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14369 || h->root.type != bfd_link_hash_undefweak))
b436d854 14370 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 14371 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 14372 }
5e681ec4
PB		 14373 }
14374 else
14375 h->got.offset = (bfd_vma) -1;
14376
a4fd1a8e
PB		 14377 /* Allocate stubs for exported Thumb functions on v4t. */
14378 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 14379 && h->def_regular
35fc36a8 14380 && h->target_internal == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 14381 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
14382 {
14383 struct elf_link_hash_entry * th;
14384 struct bfd_link_hash_entry * bh;
14385 struct elf_link_hash_entry * myh;
14386 char name[1024];
14387 asection *s;
14388 bh = NULL;
14389 /* Create a new symbol to regist the real location of the function. */
14390 s = h->root.u.def.section;
906e58ca 14391 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 14392 _bfd_generic_link_add_one_symbol (info, s->owner,
14393 name, BSF_GLOBAL, s,
14394 h->root.u.def.value,
14395 NULL, TRUE, FALSE, &bh);
14396
14397 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 14398 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 14399 myh->forced_local = 1;
35fc36a8 14400 myh->target_internal = ST_BRANCH_TO_THUMB;
a4fd1a8e
PB		 14401 eh->export_glue = myh;
14402 th = record_arm_to_thumb_glue (info, h);
14403 /* Point the symbol at the stub. */
14404 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
35fc36a8 14405 h->target_internal = ST_BRANCH_TO_ARM;
a4fd1a8e
PB		 14406 h->root.u.def.section = th->root.u.def.section;
14407 h->root.u.def.value = th->root.u.def.value & ~1;
14408 }
14409
0bdcacaf 14410 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 14411 return TRUE;
14412
14413 /* In the shared -Bsymbolic case, discard space allocated for
14414 dynamic pc-relative relocs against symbols which turn out to be
14415 defined in regular objects. For the normal shared case, discard
14416 space for pc-relative relocs that have become local due to symbol
14417 visibility changes. */
14418
0e1862bb 14419 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 14420 {
469a3493
RM		 14421 /* Relocs that use pc_count are PC-relative forms, which will appear
14422 on something like ".long foo - ." or "movw REG, foo - .". We want
14423 calls to protected symbols to resolve directly to the function
14424 rather than going via the plt. If people want function pointer
14425 comparisons to work as expected then they should avoid writing
14426 assembly like ".long foo - .". */
ba93b8ac
DJ		 14427 if (SYMBOL_CALLS_LOCAL (info, h))
14428 {
0bdcacaf 14429 struct elf_dyn_relocs **pp;
ba93b8ac 14430
0bdcacaf 14431 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 14432 {
14433 p->count -= p->pc_count;
14434 p->pc_count = 0;
14435 if (p->count == 0)
14436 *pp = p->next;
14437 else
14438 pp = &p->next;
14439 }
14440 }
14441
4dfe6ac6 14442 if (htab->vxworks_p)
3348747a 14443 {
0bdcacaf 14444 struct elf_dyn_relocs **pp;
3348747a 14445
0bdcacaf 14446 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 14447 {
0bdcacaf 14448 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 14449 *pp = p->next;
14450 else
14451 pp = &p->next;
14452 }
14453 }
14454
ba93b8ac 14455 /* Also discard relocs on undefined weak syms with non-default
99059e56 14456 visibility. */
0bdcacaf 14457 if (eh->dyn_relocs != NULL
5e681ec4 14458 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 14459 {
14460 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 14461 eh->dyn_relocs = NULL;
22d606e9
AM		 14462
14463 /* Make sure undefined weak symbols are output as a dynamic
14464 symbol in PIEs. */
14465 else if (h->dynindx == -1
14466 && !h->forced_local)
14467 {
14468 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14469 return FALSE;
14470 }
14471 }
14472
67687978
PB		 14473 else if (htab->root.is_relocatable_executable && h->dynindx == -1
14474 && h->root.type == bfd_link_hash_new)
14475 {
14476 /* Output absolute symbols so that we can create relocations
14477 against them. For normal symbols we output a relocation
14478 against the section that contains them. */
14479 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14480 return FALSE;
14481 }
14482
5e681ec4
PB		 14483 }
14484 else
14485 {
14486 /* For the non-shared case, discard space for relocs against
14487 symbols which turn out to need copy relocs or are not
14488 dynamic. */
14489
f5385ebf
AM		 14490 if (!h->non_got_ref
14491 && ((h->def_dynamic
14492 && !h->def_regular)
5e681ec4
PB		 14493 || (htab->root.dynamic_sections_created
14494 && (h->root.type == bfd_link_hash_undefweak
14495 || h->root.type == bfd_link_hash_undefined))))
14496 {
14497 /* Make sure this symbol is output as a dynamic symbol.
14498 Undefined weak syms won't yet be marked as dynamic. */
14499 if (h->dynindx == -1
f5385ebf 14500 && !h->forced_local)
5e681ec4 14501 {
c152c796 14502 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14503 return FALSE;
14504 }
14505
14506 /* If that succeeded, we know we'll be keeping all the
14507 relocs. */
14508 if (h->dynindx != -1)
14509 goto keep;
14510 }
14511
0bdcacaf 14512 eh->dyn_relocs = NULL;
5e681ec4
PB		 14513
14514 keep: ;
14515 }
14516
14517 /* Finally, allocate space. */
0bdcacaf 14518 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 14519 {
0bdcacaf 14520 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 14521 if (h->type == STT_GNU_IFUNC
14522 && eh->plt.noncall_refcount == 0
14523 && SYMBOL_REFERENCES_LOCAL (info, h))
14524 elf32_arm_allocate_irelocs (info, sreloc, p->count);
14525 else
14526 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 14527 }
14528
14529 return TRUE;
14530}
14531
08d1f311
DJ		 14532/* Find any dynamic relocs that apply to read-only sections. */
14533
14534static bfd_boolean
8029a119 14535elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 14536{
8029a119 14537 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 14538 struct elf_dyn_relocs * p;
08d1f311 14539
08d1f311 14540 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 14541 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 14542 {
0bdcacaf 14543 asection *s = p->sec;
08d1f311
DJ		 14544
14545 if (s != NULL && (s->flags & SEC_READONLY) != 0)
14546 {
14547 struct bfd_link_info *info = (struct bfd_link_info *) inf;
14548
14549 info->flags |= DF_TEXTREL;
14550
14551 /* Not an error, just cut short the traversal. */
14552 return FALSE;
14553 }
14554 }
14555 return TRUE;
14556}
14557
d504ffc8
DJ		 14558void
14559bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
14560 int byteswap_code)
14561{
14562 struct elf32_arm_link_hash_table *globals;
14563
14564 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14565 if (globals == NULL)
14566 return;
14567
d504ffc8
DJ		 14568 globals->byteswap_code = byteswap_code;
14569}
14570
252b5132
RH		 14571/* Set the sizes of the dynamic sections. */
14572
b34976b6 14573static bfd_boolean
57e8b36a
NC		 14574elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
14575 struct bfd_link_info * info)
252b5132
RH		 14576{
14577 bfd * dynobj;
14578 asection * s;
b34976b6
AM		 14579 bfd_boolean plt;
14580 bfd_boolean relocs;
5e681ec4
PB		 14581 bfd *ibfd;
14582 struct elf32_arm_link_hash_table *htab;
252b5132 14583
5e681ec4 14584 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14585 if (htab == NULL)
14586 return FALSE;
14587
252b5132
RH		 14588 dynobj = elf_hash_table (info)->dynobj;
14589 BFD_ASSERT (dynobj != NULL);
39b41c9c 14590 check_use_blx (htab);
252b5132
RH		 14591
14592 if (elf_hash_table (info)->dynamic_sections_created)
14593 {
14594 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 14595 if (bfd_link_executable (info) && !info->nointerp)
252b5132 14596 {
3d4d4302 14597 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 14598 BFD_ASSERT (s != NULL);
eea6121a 14599 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 14600 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
14601 }
14602 }
5e681ec4
PB		 14603
14604 /* Set up .got offsets for local syms, and space for local dynamic
14605 relocs. */
c72f2fb2 14606 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 14607 {
5e681ec4
PB		 14608 bfd_signed_vma *local_got;
14609 bfd_signed_vma *end_local_got;
34e77a92 14610 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 14611 char *local_tls_type;
0855e32b 14612 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 14613 bfd_size_type locsymcount;
14614 Elf_Internal_Shdr *symtab_hdr;
14615 asection *srel;
4dfe6ac6 14616 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 14617 unsigned int symndx;
5e681ec4 14618
0ffa91dd 14619 if (! is_arm_elf (ibfd))
5e681ec4
PB		 14620 continue;
14621
14622 for (s = ibfd->sections; s != NULL; s = s->next)
14623 {
0bdcacaf 14624 struct elf_dyn_relocs *p;
5e681ec4 14625
0bdcacaf 14626 for (p = (struct elf_dyn_relocs *)
99059e56 14627 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 14628 {
0bdcacaf
RS		 14629 if (!bfd_is_abs_section (p->sec)
14630 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 14631 {
14632 /* Input section has been discarded, either because
14633 it is a copy of a linkonce section or due to
14634 linker script /DISCARD/, so we'll be discarding
14635 the relocs too. */
14636 }
3348747a 14637 else if (is_vxworks
0bdcacaf 14638 && strcmp (p->sec->output_section->name,
3348747a
NS		 14639 ".tls_vars") == 0)
14640 {
14641 /* Relocations in vxworks .tls_vars sections are
14642 handled specially by the loader. */
14643 }
5e681ec4
PB		 14644 else if (p->count != 0)
14645 {
0bdcacaf 14646 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 14647 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 14648 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 14649 info->flags |= DF_TEXTREL;
14650 }
14651 }
14652 }
14653
14654 local_got = elf_local_got_refcounts (ibfd);
14655 if (!local_got)
14656 continue;
14657
0ffa91dd 14658 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 14659 locsymcount = symtab_hdr->sh_info;
14660 end_local_got = local_got + locsymcount;
34e77a92 14661 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 14662 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 14663 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 14664 symndx = 0;
362d30a1
RS		 14665 s = htab->root.sgot;
14666 srel = htab->root.srelgot;
0855e32b 14667 for (; local_got < end_local_got;
34e77a92
RS		 14668 ++local_got, ++local_iplt_ptr, ++local_tls_type,
14669 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 14670 {
0855e32b 14671 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 14672 local_iplt = *local_iplt_ptr;
14673 if (local_iplt != NULL)
14674 {
14675 struct elf_dyn_relocs *p;
14676
14677 if (local_iplt->root.refcount > 0)
14678 {
14679 elf32_arm_allocate_plt_entry (info, TRUE,
14680 &local_iplt->root,
14681 &local_iplt->arm);
14682 if (local_iplt->arm.noncall_refcount == 0)
14683 /* All references to the PLT are calls, so all
14684 non-call references can resolve directly to the
14685 run-time target. This means that the .got entry
14686 would be the same as the .igot.plt entry, so there's
14687 no point creating both. */
14688 *local_got = 0;
14689 }
14690 else
14691 {
14692 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
14693 local_iplt->root.offset = (bfd_vma) -1;
14694 }
14695
14696 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
14697 {
14698 asection *psrel;
14699
14700 psrel = elf_section_data (p->sec)->sreloc;
14701 if (local_iplt->arm.noncall_refcount == 0)
14702 elf32_arm_allocate_irelocs (info, psrel, p->count);
14703 else
14704 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
14705 }
14706 }
5e681ec4
PB		 14707 if (*local_got > 0)
14708 {
34e77a92
RS		 14709 Elf_Internal_Sym *isym;
14710
eea6121a 14711 *local_got = s->size;
ba93b8ac
DJ		 14712 if (*local_tls_type & GOT_TLS_GD)
14713 /* TLS_GD relocs need an 8-byte structure in the GOT. */
14714 s->size += 8;
0855e32b
NS		 14715 if (*local_tls_type & GOT_TLS_GDESC)
14716 {
14717 *local_tlsdesc_gotent = htab->root.sgotplt->size
14718 - elf32_arm_compute_jump_table_size (htab);
14719 htab->root.sgotplt->size += 8;
14720 *local_got = (bfd_vma) -2;
34e77a92 14721 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14722 reloc in the middle of .got.plt. */
99059e56 14723 htab->num_tls_desc++;
0855e32b 14724 }
ba93b8ac
DJ		 14725 if (*local_tls_type & GOT_TLS_IE)
14726 s->size += 4;
ba93b8ac 14727
0855e32b
NS		 14728 if (*local_tls_type & GOT_NORMAL)
14729 {
14730 /* If the symbol is both GD and GDESC, *local_got
14731 may have been overwritten. */
14732 *local_got = s->size;
14733 s->size += 4;
14734 }
14735
34e77a92
RS		 14736 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
14737 if (isym == NULL)
14738 return FALSE;
14739
14740 /* If all references to an STT_GNU_IFUNC PLT are calls,
14741 then all non-call references, including this GOT entry,
14742 resolve directly to the run-time target. */
14743 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
14744 && (local_iplt == NULL
14745 || local_iplt->arm.noncall_refcount == 0))
14746 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 14747 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 14748 {
0e1862bb 14749 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 14750 || *local_tls_type & GOT_TLS_GD)
14751 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 14752
0e1862bb 14753 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 14754 {
14755 elf32_arm_allocate_dynrelocs (info,
14756 htab->root.srelplt, 1);
14757 htab->tls_trampoline = -1;
14758 }
0855e32b 14759 }
5e681ec4
PB		 14760 }
14761 else
14762 *local_got = (bfd_vma) -1;
14763 }
252b5132
RH		 14764 }
14765
ba93b8ac
DJ		 14766 if (htab->tls_ldm_got.refcount > 0)
14767 {
14768 /* Allocate two GOT entries and one dynamic relocation (if necessary)
14769 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 14770 htab->tls_ldm_got.offset = htab->root.sgot->size;
14771 htab->root.sgot->size += 8;
0e1862bb 14772 if (bfd_link_pic (info))
47beaa6a 14773 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14774 }
14775 else
14776 htab->tls_ldm_got.offset = -1;
14777
5e681ec4
PB		 14778 /* Allocate global sym .plt and .got entries, and space for global
14779 sym dynamic relocs. */
47beaa6a 14780 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 14781
d504ffc8 14782 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 14783 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 14784 {
0ffa91dd 14785 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 14786 continue;
14787
c7b8f16e
JB		 14788 /* Initialise mapping tables for code/data. */
14789 bfd_elf32_arm_init_maps (ibfd);
906e58ca 14790
c7b8f16e 14791 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 14792 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
14793 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 14794 /* xgettext:c-format */
14795 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 14796 ibfd->filename);
14797 }
d504ffc8 14798
3e6b1042
DJ		 14799 /* Allocate space for the glue sections now that we've sized them. */
14800 bfd_elf32_arm_allocate_interworking_sections (info);
14801
0855e32b
NS		 14802 /* For every jump slot reserved in the sgotplt, reloc_count is
14803 incremented. However, when we reserve space for TLS descriptors,
14804 it's not incremented, so in order to compute the space reserved
14805 for them, it suffices to multiply the reloc count by the jump
14806 slot size. */
14807 if (htab->root.srelplt)
14808 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
14809
14810 if (htab->tls_trampoline)
14811 {
14812 if (htab->root.splt->size == 0)
14813 htab->root.splt->size += htab->plt_header_size;
b38cadfb 14814
0855e32b
NS		 14815 htab->tls_trampoline = htab->root.splt->size;
14816 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 14817
0855e32b 14818 /* If we're not using lazy TLS relocations, don't generate the
99059e56 14819 PLT and GOT entries they require. */
0855e32b
NS		 14820 if (!(info->flags & DF_BIND_NOW))
14821 {
14822 htab->dt_tlsdesc_got = htab->root.sgot->size;
14823 htab->root.sgot->size += 4;
14824
14825 htab->dt_tlsdesc_plt = htab->root.splt->size;
14826 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
14827 }
14828 }
14829
252b5132
RH		 14830 /* The check_relocs and adjust_dynamic_symbol entry points have
14831 determined the sizes of the various dynamic sections. Allocate
14832 memory for them. */
b34976b6
AM		 14833 plt = FALSE;
14834 relocs = FALSE;
252b5132
RH		 14835 for (s = dynobj->sections; s != NULL; s = s->next)
14836 {
14837 const char * name;
252b5132
RH		 14838
14839 if ((s->flags & SEC_LINKER_CREATED) == 0)
14840 continue;
14841
14842 /* It's OK to base decisions on the section name, because none
14843 of the dynobj section names depend upon the input files. */
14844 name = bfd_get_section_name (dynobj, s);
14845
34e77a92 14846 if (s == htab->root.splt)
252b5132 14847 {
c456f082
AM		 14848 /* Remember whether there is a PLT. */
14849 plt = s->size != 0;
252b5132 14850 }
0112cd26 14851 else if (CONST_STRNEQ (name, ".rel"))
252b5132 14852 {
c456f082 14853 if (s->size != 0)
252b5132 14854 {
252b5132 14855 /* Remember whether there are any reloc sections other
00a97672 14856 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 14857 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 14858 relocs = TRUE;
252b5132
RH		 14859
14860 /* We use the reloc_count field as a counter if we need
14861 to copy relocs into the output file. */
14862 s->reloc_count = 0;
14863 }
14864 }
34e77a92
RS		 14865 else if (s != htab->root.sgot
14866 && s != htab->root.sgotplt
14867 && s != htab->root.iplt
14868 && s != htab->root.igotplt
14869 && s != htab->sdynbss)
252b5132
RH		 14870 {
14871 /* It's not one of our sections, so don't allocate space. */
14872 continue;
14873 }
14874
c456f082 14875 if (s->size == 0)
252b5132 14876 {
c456f082 14877 /* If we don't need this section, strip it from the
00a97672
RS		 14878 output file. This is mostly to handle .rel(a).bss and
14879 .rel(a).plt. We must create both sections in
c456f082
AM		 14880 create_dynamic_sections, because they must be created
14881 before the linker maps input sections to output
14882 sections. The linker does that before
14883 adjust_dynamic_symbol is called, and it is that
14884 function which decides whether anything needs to go
14885 into these sections. */
8423293d 14886 s->flags |= SEC_EXCLUDE;
252b5132
RH		 14887 continue;
14888 }
14889
c456f082
AM		 14890 if ((s->flags & SEC_HAS_CONTENTS) == 0)
14891 continue;
14892
252b5132 14893 /* Allocate memory for the section contents. */
21d799b5 14894 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 14895 if (s->contents == NULL)
b34976b6 14896 return FALSE;
252b5132
RH		 14897 }
14898
14899 if (elf_hash_table (info)->dynamic_sections_created)
14900 {
14901 /* Add some entries to the .dynamic section. We fill in the
14902 values later, in elf32_arm_finish_dynamic_sections, but we
14903 must add the entries now so that we get the correct size for
14904 the .dynamic section. The DT_DEBUG entry is filled in by the
14905 dynamic linker and used by the debugger. */
dc810e39 14906#define add_dynamic_entry(TAG, VAL) \
5a580b3a 14907 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 14908
0e1862bb 14909 if (bfd_link_executable (info))
252b5132 14910 {
dc810e39 14911 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 14912 return FALSE;
252b5132
RH		 14913 }
14914
14915 if (plt)
14916 {
dc810e39
AM		 14917 if ( !add_dynamic_entry (DT_PLTGOT, 0)
14918 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 14919 || !add_dynamic_entry (DT_PLTREL,
14920 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 14921 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 14922 return FALSE;
0855e32b
NS		 14923
14924 if (htab->dt_tlsdesc_plt &&
b38cadfb 14925 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 14926 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 14927 return FALSE;
252b5132
RH		 14928 }
14929
14930 if (relocs)
14931 {
00a97672
RS		 14932 if (htab->use_rel)
14933 {
14934 if (!add_dynamic_entry (DT_REL, 0)
14935 || !add_dynamic_entry (DT_RELSZ, 0)
14936 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
14937 return FALSE;
14938 }
14939 else
14940 {
14941 if (!add_dynamic_entry (DT_RELA, 0)
14942 || !add_dynamic_entry (DT_RELASZ, 0)
14943 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
14944 return FALSE;
14945 }
252b5132
RH		 14946 }
14947
08d1f311
DJ		 14948 /* If any dynamic relocs apply to a read-only section,
14949 then we need a DT_TEXTREL entry. */
14950 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 14951 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
14952 info);
08d1f311 14953
99e4ae17 14954 if ((info->flags & DF_TEXTREL) != 0)
252b5132 14955 {
dc810e39 14956 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 14957 return FALSE;
252b5132 14958 }
7a2b07ff
NS		 14959 if (htab->vxworks_p
14960 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
14961 return FALSE;
252b5132 14962 }
8532796c 14963#undef add_dynamic_entry
252b5132 14964
b34976b6 14965 return TRUE;
252b5132
RH		 14966}
14967
0855e32b
NS		 14968/* Size sections even though they're not dynamic. We use it to setup
14969 _TLS_MODULE_BASE_, if needed. */
14970
14971static bfd_boolean
14972elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 14973 struct bfd_link_info *info)
0855e32b
NS		 14974{
14975 asection *tls_sec;
14976
0e1862bb 14977 if (bfd_link_relocatable (info))
0855e32b
NS		 14978 return TRUE;
14979
14980 tls_sec = elf_hash_table (info)->tls_sec;
14981
14982 if (tls_sec)
14983 {
14984 struct elf_link_hash_entry *tlsbase;
14985
14986 tlsbase = elf_link_hash_lookup
14987 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
14988
14989 if (tlsbase)
99059e56
RM		 14990 {
14991 struct bfd_link_hash_entry *bh = NULL;
0855e32b 14992 const struct elf_backend_data *bed
99059e56 14993 = get_elf_backend_data (output_bfd);
0855e32b 14994
99059e56 14995 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 14996 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
14997 tls_sec, 0, NULL, FALSE,
14998 bed->collect, &bh)))
14999 return FALSE;
b38cadfb 15000
99059e56
RM		 15001 tlsbase->type = STT_TLS;
15002 tlsbase = (struct elf_link_hash_entry *)bh;
15003 tlsbase->def_regular = 1;
15004 tlsbase->other = STV_HIDDEN;
15005 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 15006 }
15007 }
15008 return TRUE;
15009}
15010
252b5132
RH		 15011/* Finish up dynamic symbol handling. We set the contents of various
15012 dynamic sections here. */
15013
b34976b6 15014static bfd_boolean
906e58ca
NC		 15015elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
15016 struct bfd_link_info * info,
15017 struct elf_link_hash_entry * h,
15018 Elf_Internal_Sym * sym)
252b5132 15019{
e5a52504 15020 struct elf32_arm_link_hash_table *htab;
b7693d02 15021 struct elf32_arm_link_hash_entry *eh;
252b5132 15022
e5a52504 15023 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15024 if (htab == NULL)
15025 return FALSE;
15026
b7693d02 15027 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 15028
15029 if (h->plt.offset != (bfd_vma) -1)
15030 {
34e77a92 15031 if (!eh->is_iplt)
e5a52504 15032 {
34e77a92 15033 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 15034 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
15035 h->dynindx, 0))
15036 return FALSE;
e5a52504 15037 }
57e8b36a 15038
f5385ebf 15039 if (!h->def_regular)
252b5132
RH		 15040 {
15041 /* Mark the symbol as undefined, rather than as defined in
3a635617 15042 the .plt section. */
252b5132 15043 sym->st_shndx = SHN_UNDEF;
3a635617 15044 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 15045 Otherwise, the PLT entry would provide a definition for
15046 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 15047 and so the symbol would never be NULL. Leave the value if
15048 there were any relocations where pointer equality matters
15049 (this is a clue for the dynamic linker, to make function
15050 pointer comparisons work between an application and shared
15051 library). */
97323ad1 15052 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 15053 sym->st_value = 0;
252b5132 15054 }
34e77a92
RS		 15055 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
15056 {
15057 /* At least one non-call relocation references this .iplt entry,
15058 so the .iplt entry is the function's canonical address. */
15059 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
15060 sym->st_target_internal = ST_BRANCH_TO_ARM;
15061 sym->st_shndx = (_bfd_elf_section_from_bfd_section
15062 (output_bfd, htab->root.iplt->output_section));
15063 sym->st_value = (h->plt.offset
15064 + htab->root.iplt->output_section->vma
15065 + htab->root.iplt->output_offset);
15066 }
252b5132
RH		 15067 }
15068
f5385ebf 15069 if (h->needs_copy)
252b5132
RH		 15070 {
15071 asection * s;
947216bf 15072 Elf_Internal_Rela rel;
252b5132
RH		 15073
15074 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 15075 BFD_ASSERT (h->dynindx != -1
15076 && (h->root.type == bfd_link_hash_defined
15077 || h->root.type == bfd_link_hash_defweak));
15078
362d30a1 15079 s = htab->srelbss;
252b5132
RH		 15080 BFD_ASSERT (s != NULL);
15081
00a97672 15082 rel.r_addend = 0;
252b5132
RH		 15083 rel.r_offset = (h->root.u.def.value
15084 + h->root.u.def.section->output_section->vma
15085 + h->root.u.def.section->output_offset);
15086 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 15087 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 15088 }
15089
00a97672
RS		 15090 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
15091 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
15092 to the ".got" section. */
9637f6ef 15093 if (h == htab->root.hdynamic
00a97672 15094 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 15095 sym->st_shndx = SHN_ABS;
15096
b34976b6 15097 return TRUE;
252b5132
RH		 15098}
15099
0855e32b
NS		 15100static void
15101arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15102 void *contents,
15103 const unsigned long *template, unsigned count)
15104{
15105 unsigned ix;
b38cadfb 15106
0855e32b
NS		 15107 for (ix = 0; ix != count; ix++)
15108 {
15109 unsigned long insn = template[ix];
15110
15111 /* Emit mov pc,rx if bx is not permitted. */
15112 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
15113 insn = (insn & 0xf000000f) | 0x01a0f000;
15114 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
15115 }
15116}
15117
99059e56
RM		 15118/* Install the special first PLT entry for elf32-arm-nacl. Unlike
15119 other variants, NaCl needs this entry in a static executable's
15120 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
15121 zero. For .iplt really only the last bundle is useful, and .iplt
15122 could have a shorter first entry, with each individual PLT entry's
15123 relative branch calculated differently so it targets the last
15124 bundle instead of the instruction before it (labelled .Lplt_tail
15125 above). But it's simpler to keep the size and layout of PLT0
15126 consistent with the dynamic case, at the cost of some dead code at
15127 the start of .iplt and the one dead store to the stack at the start
15128 of .Lplt_tail. */
15129static void
15130arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15131 asection *plt, bfd_vma got_displacement)
15132{
15133 unsigned int i;
15134
15135 put_arm_insn (htab, output_bfd,
15136 elf32_arm_nacl_plt0_entry[0]
15137 | arm_movw_immediate (got_displacement),
15138 plt->contents + 0);
15139 put_arm_insn (htab, output_bfd,
15140 elf32_arm_nacl_plt0_entry[1]
15141 | arm_movt_immediate (got_displacement),
15142 plt->contents + 4);
15143
15144 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
15145 put_arm_insn (htab, output_bfd,
15146 elf32_arm_nacl_plt0_entry[i],
15147 plt->contents + (i * 4));
15148}
15149
252b5132
RH		 15150/* Finish up the dynamic sections. */
15151
b34976b6 15152static bfd_boolean
57e8b36a 15153elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 15154{
15155 bfd * dynobj;
15156 asection * sgot;
15157 asection * sdyn;
4dfe6ac6
NC		 15158 struct elf32_arm_link_hash_table *htab;
15159
15160 htab = elf32_arm_hash_table (info);
15161 if (htab == NULL)
15162 return FALSE;
252b5132
RH		 15163
15164 dynobj = elf_hash_table (info)->dynobj;
15165
362d30a1 15166 sgot = htab->root.sgotplt;
894891db
NC		 15167 /* A broken linker script might have discarded the dynamic sections.
15168 Catch this here so that we do not seg-fault later on. */
15169 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
15170 return FALSE;
3d4d4302 15171 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 15172
15173 if (elf_hash_table (info)->dynamic_sections_created)
15174 {
15175 asection *splt;
15176 Elf32_External_Dyn *dyncon, *dynconend;
15177
362d30a1 15178 splt = htab->root.splt;
24a1ba0f 15179 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 15180 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 15181
15182 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 15183 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 15184
252b5132
RH		 15185 for (; dyncon < dynconend; dyncon++)
15186 {
15187 Elf_Internal_Dyn dyn;
15188 const char * name;
15189 asection * s;
15190
15191 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
15192
15193 switch (dyn.d_tag)
15194 {
229fcec5
MM		 15195 unsigned int type;
15196
252b5132 15197 default:
7a2b07ff
NS		 15198 if (htab->vxworks_p
15199 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
15200 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 15201 break;
15202
229fcec5
MM		 15203 case DT_HASH:
15204 name = ".hash";
15205 goto get_vma_if_bpabi;
15206 case DT_STRTAB:
15207 name = ".dynstr";
15208 goto get_vma_if_bpabi;
15209 case DT_SYMTAB:
15210 name = ".dynsym";
15211 goto get_vma_if_bpabi;
c0042f5d
MM		 15212 case DT_VERSYM:
15213 name = ".gnu.version";
15214 goto get_vma_if_bpabi;
15215 case DT_VERDEF:
15216 name = ".gnu.version_d";
15217 goto get_vma_if_bpabi;
15218 case DT_VERNEED:
15219 name = ".gnu.version_r";
15220 goto get_vma_if_bpabi;
15221
252b5132
RH		 15222 case DT_PLTGOT:
15223 name = ".got";
15224 goto get_vma;
15225 case DT_JMPREL:
00a97672 15226 name = RELOC_SECTION (htab, ".plt");
252b5132
RH		 15227 get_vma:
15228 s = bfd_get_section_by_name (output_bfd, name);
05456594
NC		 15229 if (s == NULL)
15230 {
15231 /* PR ld/14397: Issue an error message if a required section is missing. */
15232 (*_bfd_error_handler)
15233 (_("error: required section '%s' not found in the linker script"), name);
15234 bfd_set_error (bfd_error_invalid_operation);
15235 return FALSE;
15236 }
229fcec5
MM		 15237 if (!htab->symbian_p)
15238 dyn.d_un.d_ptr = s->vma;
15239 else
15240 /* In the BPABI, tags in the PT_DYNAMIC section point
15241 at the file offset, not the memory address, for the
15242 convenience of the post linker. */
15243 dyn.d_un.d_ptr = s->filepos;
252b5132
RH		 15244 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15245 break;
15246
229fcec5
MM		 15247 get_vma_if_bpabi:
15248 if (htab->symbian_p)
15249 goto get_vma;
15250 break;
15251
252b5132 15252 case DT_PLTRELSZ:
362d30a1 15253 s = htab->root.srelplt;
252b5132 15254 BFD_ASSERT (s != NULL);
eea6121a 15255 dyn.d_un.d_val = s->size;
252b5132
RH		 15256 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15257 break;
906e58ca 15258
252b5132 15259 case DT_RELSZ:
00a97672 15260 case DT_RELASZ:
229fcec5
MM		 15261 if (!htab->symbian_p)
15262 {
15263 /* My reading of the SVR4 ABI indicates that the
15264 procedure linkage table relocs (DT_JMPREL) should be
15265 included in the overall relocs (DT_REL). This is
15266 what Solaris does. However, UnixWare can not handle
15267 that case. Therefore, we override the DT_RELSZ entry
15268 here to make it not include the JMPREL relocs. Since
00a97672 15269 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 15270 other relocation sections, we don't have to worry
15271 about changing the DT_REL entry. */
362d30a1 15272 s = htab->root.srelplt;
229fcec5
MM		 15273 if (s != NULL)
15274 dyn.d_un.d_val -= s->size;
15275 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15276 break;
15277 }
8029a119 15278 /* Fall through. */
229fcec5
MM		 15279
15280 case DT_REL:
15281 case DT_RELA:
229fcec5
MM		 15282 /* In the BPABI, the DT_REL tag must point at the file
15283 offset, not the VMA, of the first relocation
15284 section. So, we use code similar to that in
15285 elflink.c, but do not check for SHF_ALLOC on the
15286 relcoation section, since relocations sections are
15287 never allocated under the BPABI. The comments above
15288 about Unixware notwithstanding, we include all of the
15289 relocations here. */
15290 if (htab->symbian_p)
15291 {
15292 unsigned int i;
15293 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
15294 ? SHT_REL : SHT_RELA);
15295 dyn.d_un.d_val = 0;
15296 for (i = 1; i < elf_numsections (output_bfd); i++)
15297 {
906e58ca 15298 Elf_Internal_Shdr *hdr
229fcec5
MM		 15299 = elf_elfsections (output_bfd)[i];
15300 if (hdr->sh_type == type)
15301 {
906e58ca 15302 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 15303 || dyn.d_tag == DT_RELASZ)
15304 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 15305 else if ((ufile_ptr) hdr->sh_offset
15306 <= dyn.d_un.d_val - 1)
229fcec5
MM		 15307 dyn.d_un.d_val = hdr->sh_offset;
15308 }
15309 }
15310 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15311 }
252b5132 15312 break;
88f7bcd5 15313
0855e32b 15314 case DT_TLSDESC_PLT:
99059e56 15315 s = htab->root.splt;
0855e32b
NS		 15316 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
15317 + htab->dt_tlsdesc_plt);
15318 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15319 break;
15320
15321 case DT_TLSDESC_GOT:
99059e56 15322 s = htab->root.sgot;
0855e32b 15323 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 15324 + htab->dt_tlsdesc_got);
0855e32b
NS		 15325 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15326 break;
15327
88f7bcd5
NC		 15328 /* Set the bottom bit of DT_INIT/FINI if the
15329 corresponding function is Thumb. */
15330 case DT_INIT:
15331 name = info->init_function;
15332 goto get_sym;
15333 case DT_FINI:
15334 name = info->fini_function;
15335 get_sym:
15336 /* If it wasn't set by elf_bfd_final_link
4cc11e76 15337 then there is nothing to adjust. */
88f7bcd5
NC		 15338 if (dyn.d_un.d_val != 0)
15339 {
15340 struct elf_link_hash_entry * eh;
15341
15342 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 15343 FALSE, FALSE, TRUE);
35fc36a8 15344 if (eh != NULL && eh->target_internal == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 15345 {
15346 dyn.d_un.d_val |= 1;
b34976b6 15347 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 15348 }
15349 }
15350 break;
252b5132
RH		 15351 }
15352 }
15353
24a1ba0f 15354 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 15355 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 15356 {
00a97672
RS		 15357 const bfd_vma *plt0_entry;
15358 bfd_vma got_address, plt_address, got_displacement;
15359
15360 /* Calculate the addresses of the GOT and PLT. */
15361 got_address = sgot->output_section->vma + sgot->output_offset;
15362 plt_address = splt->output_section->vma + splt->output_offset;
15363
15364 if (htab->vxworks_p)
15365 {
15366 /* The VxWorks GOT is relocated by the dynamic linker.
15367 Therefore, we must emit relocations rather than simply
15368 computing the values now. */
15369 Elf_Internal_Rela rel;
15370
15371 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 15372 put_arm_insn (htab, output_bfd, plt0_entry[0],
15373 splt->contents + 0);
15374 put_arm_insn (htab, output_bfd, plt0_entry[1],
15375 splt->contents + 4);
15376 put_arm_insn (htab, output_bfd, plt0_entry[2],
15377 splt->contents + 8);
00a97672
RS		 15378 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
15379
8029a119 15380 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 15381 rel.r_offset = plt_address + 12;
15382 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15383 rel.r_addend = 0;
15384 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
15385 htab->srelplt2->contents);
15386 }
b38cadfb 15387 else if (htab->nacl_p)
99059e56
RM		 15388 arm_nacl_put_plt0 (htab, output_bfd, splt,
15389 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 15390 else if (using_thumb_only (htab))
15391 {
15392 got_displacement = got_address - (plt_address + 12);
15393
15394 plt0_entry = elf32_thumb2_plt0_entry;
15395 put_arm_insn (htab, output_bfd, plt0_entry[0],
15396 splt->contents + 0);
15397 put_arm_insn (htab, output_bfd, plt0_entry[1],
15398 splt->contents + 4);
15399 put_arm_insn (htab, output_bfd, plt0_entry[2],
15400 splt->contents + 8);
15401
15402 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
15403 }
00a97672
RS		 15404 else
15405 {
15406 got_displacement = got_address - (plt_address + 16);
15407
15408 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 15409 put_arm_insn (htab, output_bfd, plt0_entry[0],
15410 splt->contents + 0);
15411 put_arm_insn (htab, output_bfd, plt0_entry[1],
15412 splt->contents + 4);
15413 put_arm_insn (htab, output_bfd, plt0_entry[2],
15414 splt->contents + 8);
15415 put_arm_insn (htab, output_bfd, plt0_entry[3],
15416 splt->contents + 12);
5e681ec4 15417
5e681ec4 15418#ifdef FOUR_WORD_PLT
00a97672
RS		 15419 /* The displacement value goes in the otherwise-unused
15420 last word of the second entry. */
15421 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 15422#else
00a97672 15423 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 15424#endif
00a97672 15425 }
f7a74f8c 15426 }
252b5132
RH		 15427
15428 /* UnixWare sets the entsize of .plt to 4, although that doesn't
15429 really seem like the right value. */
74541ad4
AM		 15430 if (splt->output_section->owner == output_bfd)
15431 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 15432
0855e32b
NS		 15433 if (htab->dt_tlsdesc_plt)
15434 {
15435 bfd_vma got_address
15436 = sgot->output_section->vma + sgot->output_offset;
15437 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
15438 + htab->root.sgot->output_offset);
15439 bfd_vma plt_address
15440 = splt->output_section->vma + splt->output_offset;
15441
b38cadfb 15442 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15443 splt->contents + htab->dt_tlsdesc_plt,
15444 dl_tlsdesc_lazy_trampoline, 6);
15445
15446 bfd_put_32 (output_bfd,
15447 gotplt_address + htab->dt_tlsdesc_got
15448 - (plt_address + htab->dt_tlsdesc_plt)
15449 - dl_tlsdesc_lazy_trampoline[6],
15450 splt->contents + htab->dt_tlsdesc_plt + 24);
15451 bfd_put_32 (output_bfd,
15452 got_address - (plt_address + htab->dt_tlsdesc_plt)
15453 - dl_tlsdesc_lazy_trampoline[7],
15454 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
15455 }
15456
15457 if (htab->tls_trampoline)
15458 {
b38cadfb 15459 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15460 splt->contents + htab->tls_trampoline,
15461 tls_trampoline, 3);
15462#ifdef FOUR_WORD_PLT
15463 bfd_put_32 (output_bfd, 0x00000000,
15464 splt->contents + htab->tls_trampoline + 12);
b38cadfb 15465#endif
0855e32b
NS		 15466 }
15467
0e1862bb
L		 15468 if (htab->vxworks_p
15469 && !bfd_link_pic (info)
15470 && htab->root.splt->size > 0)
00a97672
RS		 15471 {
15472 /* Correct the .rel(a).plt.unloaded relocations. They will have
15473 incorrect symbol indexes. */
15474 int num_plts;
eed62c48 15475 unsigned char *p;
00a97672 15476
362d30a1 15477 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 15478 / htab->plt_entry_size);
15479 p = htab->srelplt2->contents + RELOC_SIZE (htab);
15480
15481 for (; num_plts; num_plts--)
15482 {
15483 Elf_Internal_Rela rel;
15484
15485 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15486 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15487 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15488 p += RELOC_SIZE (htab);
15489
15490 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15491 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
15492 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15493 p += RELOC_SIZE (htab);
15494 }
15495 }
252b5132
RH		 15496 }
15497
99059e56
RM		 15498 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
15499 /* NaCl uses a special first entry in .iplt too. */
15500 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
15501
252b5132 15502 /* Fill in the first three entries in the global offset table. */
229fcec5 15503 if (sgot)
252b5132 15504 {
229fcec5
MM		 15505 if (sgot->size > 0)
15506 {
15507 if (sdyn == NULL)
15508 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
15509 else
15510 bfd_put_32 (output_bfd,
15511 sdyn->output_section->vma + sdyn->output_offset,
15512 sgot->contents);
15513 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
15514 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
15515 }
252b5132 15516
229fcec5
MM		 15517 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
15518 }
252b5132 15519
b34976b6 15520 return TRUE;
252b5132
RH		 15521}
15522
ba96a88f 15523static void
57e8b36a 15524elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 15525{
9b485d32 15526 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 15527 struct elf32_arm_link_hash_table *globals;
ac4c9b04 15528 struct elf_segment_map *m;
ba96a88f
NC		 15529
15530 i_ehdrp = elf_elfheader (abfd);
15531
94a3258f
PB		 15532 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
15533 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
15534 else
7394f108 15535 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 15536 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 15537
93204d3a
PB		 15538 if (link_info)
15539 {
15540 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 15541 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 15542 i_ehdrp->e_flags |= EF_ARM_BE8;
15543 }
3bfcb652
NC		 15544
15545 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
15546 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
15547 {
15548 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 15549 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 15550 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
15551 else
15552 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
15553 }
ac4c9b04
MG		 15554
15555 /* Scan segment to set p_flags attribute if it contains only sections with
15556 SHF_ARM_NOREAD flag. */
15557 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
15558 {
15559 unsigned int j;
15560
15561 if (m->count == 0)
15562 continue;
15563 for (j = 0; j < m->count; j++)
15564 {
15565 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_NOREAD))
15566 break;
15567 }
15568 if (j == m->count)
15569 {
15570 m->p_flags = PF_X;
15571 m->p_flags_valid = 1;
15572 }
15573 }
ba96a88f
NC		 15574}
15575
99e4ae17 15576static enum elf_reloc_type_class
7e612e98
AM		 15577elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
15578 const asection *rel_sec ATTRIBUTE_UNUSED,
15579 const Elf_Internal_Rela *rela)
99e4ae17 15580{
f51e552e 15581 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 15582 {
15583 case R_ARM_RELATIVE:
15584 return reloc_class_relative;
15585 case R_ARM_JUMP_SLOT:
15586 return reloc_class_plt;
15587 case R_ARM_COPY:
15588 return reloc_class_copy;
109575d7
JW		 15589 case R_ARM_IRELATIVE:
15590 return reloc_class_ifunc;
99e4ae17
AJ		 15591 default:
15592 return reloc_class_normal;
15593 }
15594}
15595
e489d0ae 15596static void
57e8b36a 15597elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 15598{
5a6c6817 15599 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 15600}
15601
40a18ebd
NC		 15602/* Return TRUE if this is an unwinding table entry. */
15603
15604static bfd_boolean
15605is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
15606{
0112cd26
NC		 15607 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
15608 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 15609}
15610
15611
15612/* Set the type and flags for an ARM section. We do this by
15613 the section name, which is a hack, but ought to work. */
15614
15615static bfd_boolean
15616elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
15617{
15618 const char * name;
15619
15620 name = bfd_get_section_name (abfd, sec);
15621
15622 if (is_arm_elf_unwind_section_name (abfd, name))
15623 {
15624 hdr->sh_type = SHT_ARM_EXIDX;
15625 hdr->sh_flags |= SHF_LINK_ORDER;
15626 }
ac4c9b04
MG		 15627
15628 if (sec->flags & SEC_ELF_NOREAD)
15629 hdr->sh_flags |= SHF_ARM_NOREAD;
15630
40a18ebd
NC		 15631 return TRUE;
15632}
15633
6dc132d9
L		 15634/* Handle an ARM specific section when reading an object file. This is
15635 called when bfd_section_from_shdr finds a section with an unknown
15636 type. */
40a18ebd
NC		 15637
15638static bfd_boolean
15639elf32_arm_section_from_shdr (bfd *abfd,
15640 Elf_Internal_Shdr * hdr,
6dc132d9
L		 15641 const char *name,
15642 int shindex)
40a18ebd
NC		 15643{
15644 /* There ought to be a place to keep ELF backend specific flags, but
15645 at the moment there isn't one. We just keep track of the
15646 sections by their name, instead. Fortunately, the ABI gives
15647 names for all the ARM specific sections, so we will probably get
15648 away with this. */
15649 switch (hdr->sh_type)
15650 {
15651 case SHT_ARM_EXIDX:
0951f019
RE		 15652 case SHT_ARM_PREEMPTMAP:
15653 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 15654 break;
15655
15656 default:
15657 return FALSE;
15658 }
15659
6dc132d9 15660 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 15661 return FALSE;
15662
15663 return TRUE;
15664}
e489d0ae 15665
44444f50
NC		 15666static _arm_elf_section_data *
15667get_arm_elf_section_data (asection * sec)
15668{
47b2e99c
JZ		 15669 if (sec && sec->owner && is_arm_elf (sec->owner))
15670 return elf32_arm_section_data (sec);
44444f50
NC		 15671 else
15672 return NULL;
8e3de13a
NC		 15673}
15674
4e617b1e
PB		 15675typedef struct
15676{
57402f1e 15677 void *flaginfo;
4e617b1e 15678 struct bfd_link_info *info;
91a5743d
PB		 15679 asection *sec;
15680 int sec_shndx;
6e0b88f1
AM		 15681 int (*func) (void *, const char *, Elf_Internal_Sym *,
15682 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 15683} output_arch_syminfo;
15684
15685enum map_symbol_type
15686{
15687 ARM_MAP_ARM,
15688 ARM_MAP_THUMB,
15689 ARM_MAP_DATA
15690};
15691
15692
7413f23f 15693/* Output a single mapping symbol. */
4e617b1e
PB		 15694
15695static bfd_boolean
7413f23f
DJ		 15696elf32_arm_output_map_sym (output_arch_syminfo *osi,
15697 enum map_symbol_type type,
15698 bfd_vma offset)
4e617b1e
PB		 15699{
15700 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 15701 Elf_Internal_Sym sym;
15702
91a5743d
PB		 15703 sym.st_value = osi->sec->output_section->vma
15704 + osi->sec->output_offset
15705 + offset;
4e617b1e
PB		 15706 sym.st_size = 0;
15707 sym.st_other = 0;
15708 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 15709 sym.st_shndx = osi->sec_shndx;
35fc36a8 15710 sym.st_target_internal = 0;
fe33d2fa 15711 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 15712 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 15713}
15714
34e77a92
RS		 15715/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
15716 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 15717
15718static bfd_boolean
34e77a92
RS		 15719elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
15720 bfd_boolean is_iplt_entry_p,
15721 union gotplt_union *root_plt,
15722 struct arm_plt_info *arm_plt)
4e617b1e 15723{
4e617b1e 15724 struct elf32_arm_link_hash_table *htab;
34e77a92 15725 bfd_vma addr, plt_header_size;
4e617b1e 15726
34e77a92 15727 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 15728 return TRUE;
15729
4dfe6ac6
NC		 15730 htab = elf32_arm_hash_table (osi->info);
15731 if (htab == NULL)
15732 return FALSE;
15733
34e77a92
RS		 15734 if (is_iplt_entry_p)
15735 {
15736 osi->sec = htab->root.iplt;
15737 plt_header_size = 0;
15738 }
15739 else
15740 {
15741 osi->sec = htab->root.splt;
15742 plt_header_size = htab->plt_header_size;
15743 }
15744 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
15745 (osi->info->output_bfd, osi->sec->output_section));
15746
15747 addr = root_plt->offset & -2;
4e617b1e
PB		 15748 if (htab->symbian_p)
15749 {
7413f23f 15750 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15751 return FALSE;
7413f23f 15752 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 15753 return FALSE;
15754 }
15755 else if (htab->vxworks_p)
15756 {
7413f23f 15757 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15758 return FALSE;
7413f23f 15759 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 15760 return FALSE;
7413f23f 15761 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 15762 return FALSE;
7413f23f 15763 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 15764 return FALSE;
15765 }
b38cadfb
NC		 15766 else if (htab->nacl_p)
15767 {
15768 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
15769 return FALSE;
15770 }
eed94f8f
NC		 15771 else if (using_thumb_only (htab))
15772 {
15773 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
15774 return FALSE;
6a631e86 15775 }
4e617b1e
PB		 15776 else
15777 {
34e77a92 15778 bfd_boolean thumb_stub_p;
bd97cb95 15779
34e77a92
RS		 15780 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
15781 if (thumb_stub_p)
4e617b1e 15782 {
7413f23f 15783 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 15784 return FALSE;
15785 }
15786#ifdef FOUR_WORD_PLT
7413f23f 15787 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15788 return FALSE;
7413f23f 15789 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 15790 return FALSE;
15791#else
906e58ca 15792 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 15793 so only need to output a mapping symbol for the first PLT entry and
15794 entries with thumb thunks. */
34e77a92 15795 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 15796 {
7413f23f 15797 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 15798 return FALSE;
15799 }
15800#endif
15801 }
15802
15803 return TRUE;
15804}
15805
34e77a92
RS		 15806/* Output mapping symbols for PLT entries associated with H. */
15807
15808static bfd_boolean
15809elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
15810{
15811 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
15812 struct elf32_arm_link_hash_entry *eh;
15813
15814 if (h->root.type == bfd_link_hash_indirect)
15815 return TRUE;
15816
15817 if (h->root.type == bfd_link_hash_warning)
15818 /* When warning symbols are created, they **replace** the "real"
15819 entry in the hash table, thus we never get to see the real
15820 symbol in a hash traversal. So look at it now. */
15821 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15822
15823 eh = (struct elf32_arm_link_hash_entry *) h;
15824 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
15825 &h->plt, &eh->plt);
15826}
15827
7413f23f
DJ		 15828/* Output a single local symbol for a generated stub. */
15829
15830static bfd_boolean
15831elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
15832 bfd_vma offset, bfd_vma size)
15833{
7413f23f
DJ		 15834 Elf_Internal_Sym sym;
15835
7413f23f
DJ		 15836 sym.st_value = osi->sec->output_section->vma
15837 + osi->sec->output_offset
15838 + offset;
15839 sym.st_size = size;
15840 sym.st_other = 0;
15841 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
15842 sym.st_shndx = osi->sec_shndx;
35fc36a8 15843 sym.st_target_internal = 0;
57402f1e 15844 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 15845}
4e617b1e 15846
da5938a2 15847static bfd_boolean
8029a119
NC		 15848arm_map_one_stub (struct bfd_hash_entry * gen_entry,
15849 void * in_arg)
da5938a2
NC		 15850{
15851 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 15852 asection *stub_sec;
15853 bfd_vma addr;
7413f23f 15854 char *stub_name;
9a008db3 15855 output_arch_syminfo *osi;
d3ce72d0 15856 const insn_sequence *template_sequence;
461a49ca
DJ		 15857 enum stub_insn_type prev_type;
15858 int size;
15859 int i;
15860 enum map_symbol_type sym_type;
da5938a2
NC		 15861
15862 /* Massage our args to the form they really have. */
15863 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 15864 osi = (output_arch_syminfo *) in_arg;
da5938a2 15865
da5938a2
NC		 15866 stub_sec = stub_entry->stub_sec;
15867
15868 /* Ensure this stub is attached to the current section being
7413f23f 15869 processed. */
da5938a2
NC		 15870 if (stub_sec != osi->sec)
15871 return TRUE;
15872
7413f23f
DJ		 15873 addr = (bfd_vma) stub_entry->stub_offset;
15874 stub_name = stub_entry->output_name;
da5938a2 15875
d3ce72d0
NC		 15876 template_sequence = stub_entry->stub_template;
15877 switch (template_sequence[0].type)
7413f23f 15878 {
461a49ca
DJ		 15879 case ARM_TYPE:
15880 if (!elf32_arm_output_stub_sym (osi, stub_name, addr, stub_entry->stub_size))
da5938a2
NC		 15881 return FALSE;
15882 break;
461a49ca 15883 case THUMB16_TYPE:
48229727 15884 case THUMB32_TYPE:
461a49ca
DJ		 15885 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
15886 stub_entry->stub_size))
da5938a2
NC		 15887 return FALSE;
15888 break;
15889 default:
15890 BFD_FAIL ();
48229727 15891 return 0;
7413f23f 15892 }
da5938a2 15893
461a49ca
DJ		 15894 prev_type = DATA_TYPE;
15895 size = 0;
15896 for (i = 0; i < stub_entry->stub_template_size; i++)
15897 {
d3ce72d0 15898 switch (template_sequence[i].type)
461a49ca
DJ		 15899 {
15900 case ARM_TYPE:
15901 sym_type = ARM_MAP_ARM;
15902 break;
15903
15904 case THUMB16_TYPE:
48229727 15905 case THUMB32_TYPE:
461a49ca
DJ		 15906 sym_type = ARM_MAP_THUMB;
15907 break;
15908
15909 case DATA_TYPE:
15910 sym_type = ARM_MAP_DATA;
15911 break;
15912
15913 default:
15914 BFD_FAIL ();
4e31c731 15915 return FALSE;
461a49ca
DJ		 15916 }
15917
d3ce72d0 15918 if (template_sequence[i].type != prev_type)
461a49ca 15919 {
d3ce72d0 15920 prev_type = template_sequence[i].type;
461a49ca
DJ		 15921 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
15922 return FALSE;
15923 }
15924
d3ce72d0 15925 switch (template_sequence[i].type)
461a49ca
DJ		 15926 {
15927 case ARM_TYPE:
48229727 15928 case THUMB32_TYPE:
461a49ca
DJ		 15929 size += 4;
15930 break;
15931
15932 case THUMB16_TYPE:
15933 size += 2;
15934 break;
15935
15936 case DATA_TYPE:
15937 size += 4;
15938 break;
15939
15940 default:
15941 BFD_FAIL ();
4e31c731 15942 return FALSE;
461a49ca
DJ		 15943 }
15944 }
15945
da5938a2
NC		 15946 return TRUE;
15947}
15948
33811162
DG		 15949/* Output mapping symbols for linker generated sections,
15950 and for those data-only sections that do not have a
15951 $d. */
4e617b1e
PB		 15952
15953static bfd_boolean
15954elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 15955 struct bfd_link_info *info,
57402f1e 15956 void *flaginfo,
6e0b88f1
AM		 15957 int (*func) (void *, const char *,
15958 Elf_Internal_Sym *,
15959 asection *,
15960 struct elf_link_hash_entry *))
4e617b1e
PB		 15961{
15962 output_arch_syminfo osi;
15963 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 15964 bfd_vma offset;
15965 bfd_size_type size;
33811162 15966 bfd *input_bfd;
4e617b1e
PB		 15967
15968 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15969 if (htab == NULL)
15970 return FALSE;
15971
906e58ca 15972 check_use_blx (htab);
91a5743d 15973
57402f1e 15974 osi.flaginfo = flaginfo;
4e617b1e
PB		 15975 osi.info = info;
15976 osi.func = func;
906e58ca 15977
33811162
DG		 15978 /* Add a $d mapping symbol to data-only sections that
15979 don't have any mapping symbol. This may result in (harmless) redundant
15980 mapping symbols. */
15981 for (input_bfd = info->input_bfds;
15982 input_bfd != NULL;
c72f2fb2 15983 input_bfd = input_bfd->link.next)
33811162
DG		 15984 {
15985 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
15986 for (osi.sec = input_bfd->sections;
15987 osi.sec != NULL;
15988 osi.sec = osi.sec->next)
15989 {
15990 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 15991 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
15992 != 0)
33811162
DG		 15993 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
15994 == SEC_HAS_CONTENTS
15995 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 15996 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 15997 && osi.sec->size > 0
15998 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 15999 {
16000 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16001 (output_bfd, osi.sec->output_section);
16002 if (osi.sec_shndx != (int)SHN_BAD)
16003 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
16004 }
16005 }
16006 }
16007
91a5743d
PB		 16008 /* ARM->Thumb glue. */
16009 if (htab->arm_glue_size > 0)
16010 {
3d4d4302
AM		 16011 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16012 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 16013
16014 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16015 (output_bfd, osi.sec->output_section);
0e1862bb 16016 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 16017 || htab->pic_veneer)
16018 size = ARM2THUMB_PIC_GLUE_SIZE;
16019 else if (htab->use_blx)
16020 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
16021 else
16022 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 16023
91a5743d
PB		 16024 for (offset = 0; offset < htab->arm_glue_size; offset += size)
16025 {
7413f23f
DJ		 16026 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
16027 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 16028 }
16029 }
16030
16031 /* Thumb->ARM glue. */
16032 if (htab->thumb_glue_size > 0)
16033 {
3d4d4302
AM		 16034 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16035 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 16036
16037 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16038 (output_bfd, osi.sec->output_section);
16039 size = THUMB2ARM_GLUE_SIZE;
16040
16041 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
16042 {
7413f23f
DJ		 16043 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
16044 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 16045 }
16046 }
16047
845b51d6
PB		 16048 /* ARMv4 BX veneers. */
16049 if (htab->bx_glue_size > 0)
16050 {
3d4d4302
AM		 16051 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16052 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 16053
16054 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16055 (output_bfd, osi.sec->output_section);
16056
7413f23f 16057 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 16058 }
16059
8029a119
NC		 16060 /* Long calls stubs. */
16061 if (htab->stub_bfd && htab->stub_bfd->sections)
16062 {
da5938a2 16063 asection* stub_sec;
8029a119 16064
da5938a2
NC		 16065 for (stub_sec = htab->stub_bfd->sections;
16066 stub_sec != NULL;
8029a119
NC		 16067 stub_sec = stub_sec->next)
16068 {
16069 /* Ignore non-stub sections. */
16070 if (!strstr (stub_sec->name, STUB_SUFFIX))
16071 continue;
da5938a2 16072
8029a119 16073 osi.sec = stub_sec;
da5938a2 16074
8029a119
NC		 16075 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16076 (output_bfd, osi.sec->output_section);
da5938a2 16077
8029a119
NC		 16078 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
16079 }
16080 }
da5938a2 16081
91a5743d 16082 /* Finally, output mapping symbols for the PLT. */
34e77a92 16083 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 16084 {
34e77a92
RS		 16085 osi.sec = htab->root.splt;
16086 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16087 (output_bfd, osi.sec->output_section));
16088
16089 /* Output mapping symbols for the plt header. SymbianOS does not have a
16090 plt header. */
16091 if (htab->vxworks_p)
16092 {
16093 /* VxWorks shared libraries have no PLT header. */
0e1862bb 16094 if (!bfd_link_pic (info))
34e77a92
RS		 16095 {
16096 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16097 return FALSE;
16098 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16099 return FALSE;
16100 }
16101 }
b38cadfb
NC		 16102 else if (htab->nacl_p)
16103 {
16104 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16105 return FALSE;
16106 }
eed94f8f
NC		 16107 else if (using_thumb_only (htab))
16108 {
16109 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
16110 return FALSE;
16111 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16112 return FALSE;
16113 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
16114 return FALSE;
16115 }
34e77a92 16116 else if (!htab->symbian_p)
4e617b1e 16117 {
7413f23f 16118 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 16119 return FALSE;
34e77a92
RS		 16120#ifndef FOUR_WORD_PLT
16121 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 16122 return FALSE;
34e77a92 16123#endif
4e617b1e
PB		 16124 }
16125 }
99059e56
RM		 16126 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
16127 {
16128 /* NaCl uses a special first entry in .iplt too. */
16129 osi.sec = htab->root.iplt;
16130 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16131 (output_bfd, osi.sec->output_section));
16132 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16133 return FALSE;
16134 }
34e77a92
RS		 16135 if ((htab->root.splt && htab->root.splt->size > 0)
16136 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 16137 {
34e77a92
RS		 16138 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
16139 for (input_bfd = info->input_bfds;
16140 input_bfd != NULL;
c72f2fb2 16141 input_bfd = input_bfd->link.next)
34e77a92
RS		 16142 {
16143 struct arm_local_iplt_info **local_iplt;
16144 unsigned int i, num_syms;
4e617b1e 16145
34e77a92
RS		 16146 local_iplt = elf32_arm_local_iplt (input_bfd);
16147 if (local_iplt != NULL)
16148 {
16149 num_syms = elf_symtab_hdr (input_bfd).sh_info;
16150 for (i = 0; i < num_syms; i++)
16151 if (local_iplt[i] != NULL
16152 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
16153 &local_iplt[i]->root,
16154 &local_iplt[i]->arm))
16155 return FALSE;
16156 }
16157 }
16158 }
0855e32b
NS		 16159 if (htab->dt_tlsdesc_plt != 0)
16160 {
16161 /* Mapping symbols for the lazy tls trampoline. */
16162 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
16163 return FALSE;
b38cadfb 16164
0855e32b
NS		 16165 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16166 htab->dt_tlsdesc_plt + 24))
16167 return FALSE;
16168 }
16169 if (htab->tls_trampoline != 0)
16170 {
16171 /* Mapping symbols for the tls trampoline. */
16172 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
16173 return FALSE;
16174#ifdef FOUR_WORD_PLT
16175 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16176 htab->tls_trampoline + 12))
16177 return FALSE;
b38cadfb 16178#endif
0855e32b 16179 }
b38cadfb 16180
4e617b1e
PB		 16181 return TRUE;
16182}
16183
e489d0ae
PB		 16184/* Allocate target specific section data. */
16185
16186static bfd_boolean
16187elf32_arm_new_section_hook (bfd *abfd, asection *sec)
16188{
f592407e
AM		 16189 if (!sec->used_by_bfd)
16190 {
16191 _arm_elf_section_data *sdata;
16192 bfd_size_type amt = sizeof (*sdata);
e489d0ae 16193
21d799b5 16194 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 16195 if (sdata == NULL)
16196 return FALSE;
16197 sec->used_by_bfd = sdata;
16198 }
e489d0ae
PB		 16199
16200 return _bfd_elf_new_section_hook (abfd, sec);
16201}
16202
16203
16204/* Used to order a list of mapping symbols by address. */
16205
16206static int
16207elf32_arm_compare_mapping (const void * a, const void * b)
16208{
7f6a71ff
JM		 16209 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
16210 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
16211
16212 if (amap->vma > bmap->vma)
16213 return 1;
16214 else if (amap->vma < bmap->vma)
16215 return -1;
16216 else if (amap->type > bmap->type)
16217 /* Ensure results do not depend on the host qsort for objects with
16218 multiple mapping symbols at the same address by sorting on type
16219 after vma. */
16220 return 1;
16221 else if (amap->type < bmap->type)
16222 return -1;
16223 else
16224 return 0;
e489d0ae
PB		 16225}
16226
2468f9c9
PB		 16227/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16228
16229static unsigned long
16230offset_prel31 (unsigned long addr, bfd_vma offset)
16231{
16232 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
16233}
16234
16235/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16236 relocations. */
16237
16238static void
16239copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
16240{
16241 unsigned long first_word = bfd_get_32 (output_bfd, from);
16242 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 16243
2468f9c9
PB		 16244 /* High bit of first word is supposed to be zero. */
16245 if ((first_word & 0x80000000ul) == 0)
16246 first_word = offset_prel31 (first_word, offset);
b38cadfb 16247
2468f9c9
PB		 16248 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16249 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16250 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
16251 second_word = offset_prel31 (second_word, offset);
b38cadfb 16252
2468f9c9
PB		 16253 bfd_put_32 (output_bfd, first_word, to);
16254 bfd_put_32 (output_bfd, second_word, to + 4);
16255}
e489d0ae 16256
48229727
JB		 16257/* Data for make_branch_to_a8_stub(). */
16258
b38cadfb
NC		 16259struct a8_branch_to_stub_data
16260{
48229727
JB		 16261 asection *writing_section;
16262 bfd_byte *contents;
16263};
16264
16265
16266/* Helper to insert branches to Cortex-A8 erratum stubs in the right
16267 places for a particular section. */
16268
16269static bfd_boolean
16270make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 16271 void *in_arg)
48229727
JB		 16272{
16273 struct elf32_arm_stub_hash_entry *stub_entry;
16274 struct a8_branch_to_stub_data *data;
16275 bfd_byte *contents;
16276 unsigned long branch_insn;
16277 bfd_vma veneered_insn_loc, veneer_entry_loc;
16278 bfd_signed_vma branch_offset;
16279 bfd *abfd;
91d6fa6a 16280 unsigned int target;
48229727
JB		 16281
16282 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
16283 data = (struct a8_branch_to_stub_data *) in_arg;
16284
16285 if (stub_entry->target_section != data->writing_section
4563a860 16286 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 16287 return TRUE;
16288
16289 contents = data->contents;
16290
16291 veneered_insn_loc = stub_entry->target_section->output_section->vma
16292 + stub_entry->target_section->output_offset
16293 + stub_entry->target_value;
16294
16295 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
16296 + stub_entry->stub_sec->output_offset
16297 + stub_entry->stub_offset;
16298
16299 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
16300 veneered_insn_loc &= ~3u;
16301
16302 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
16303
16304 abfd = stub_entry->target_section->owner;
91d6fa6a 16305 target = stub_entry->target_value;
48229727
JB		 16306
16307 /* We attempt to avoid this condition by setting stubs_always_after_branch
16308 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16309 This check is just to be on the safe side... */
16310 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
16311 {
16312 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
16313 "allocated in unsafe location"), abfd);
16314 return FALSE;
16315 }
16316
16317 switch (stub_entry->stub_type)
16318 {
16319 case arm_stub_a8_veneer_b:
16320 case arm_stub_a8_veneer_b_cond:
16321 branch_insn = 0xf0009000;
16322 goto jump24;
16323
16324 case arm_stub_a8_veneer_blx:
16325 branch_insn = 0xf000e800;
16326 goto jump24;
16327
16328 case arm_stub_a8_veneer_bl:
16329 {
16330 unsigned int i1, j1, i2, j2, s;
16331
16332 branch_insn = 0xf000d000;
16333
16334 jump24:
16335 if (branch_offset < -16777216 || branch_offset > 16777214)
16336 {
16337 /* There's not much we can do apart from complain if this
16338 happens. */
16339 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
16340 "of range (input file too large)"), abfd);
16341 return FALSE;
16342 }
16343
16344 /* i1 = not(j1 eor s), so:
16345 not i1 = j1 eor s
16346 j1 = (not i1) eor s. */
16347
16348 branch_insn |= (branch_offset >> 1) & 0x7ff;
16349 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
16350 i2 = (branch_offset >> 22) & 1;
16351 i1 = (branch_offset >> 23) & 1;
16352 s = (branch_offset >> 24) & 1;
16353 j1 = (!i1) ^ s;
16354 j2 = (!i2) ^ s;
16355 branch_insn |= j2 << 11;
16356 branch_insn |= j1 << 13;
16357 branch_insn |= s << 26;
16358 }
16359 break;
16360
16361 default:
16362 BFD_FAIL ();
16363 return FALSE;
16364 }
16365
91d6fa6a
NC		 16366 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[target]);
16367 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[target + 2]);
48229727
JB		 16368
16369 return TRUE;
16370}
16371
a504d23a
LA		 16372/* Beginning of stm32l4xx work-around. */
16373
16374/* Functions encoding instructions necessary for the emission of the
16375 fix-stm32l4xx-629360.
16376 Encoding is extracted from the
16377 ARM (C) Architecture Reference Manual
16378 ARMv7-A and ARMv7-R edition
16379 ARM DDI 0406C.b (ID072512). */
16380
16381static inline bfd_vma
82188b29 16382create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 16383{
16384 /* A8.8.18 B (A8-334)
16385 B target_address (Encoding T4). */
16386 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
16387 /* jump offset is: S:I1:I2:imm10:imm11:0. */
16388 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
16389
a504d23a
LA		 16390 int s = ((branch_offset & 0x1000000) >> 24);
16391 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
16392 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
16393
16394 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
16395 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
16396
16397 bfd_vma patched_inst = 0xf0009000
16398 | s << 26 /* S. */
16399 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
16400 | j1 << 13 /* J1. */
16401 | j2 << 11 /* J2. */
16402 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
16403
16404 return patched_inst;
16405}
16406
16407static inline bfd_vma
16408create_instruction_ldmia (int base_reg, int wback, int reg_mask)
16409{
16410 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
16411 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
16412 bfd_vma patched_inst = 0xe8900000
16413 | (/*W=*/wback << 21)
16414 | (base_reg << 16)
16415 | (reg_mask & 0x0000ffff);
16416
16417 return patched_inst;
16418}
16419
16420static inline bfd_vma
16421create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
16422{
16423 /* A8.8.60 LDMDB/LDMEA (A8-402)
16424 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
16425 bfd_vma patched_inst = 0xe9100000
16426 | (/*W=*/wback << 21)
16427 | (base_reg << 16)
16428 | (reg_mask & 0x0000ffff);
16429
16430 return patched_inst;
16431}
16432
16433static inline bfd_vma
16434create_instruction_mov (int target_reg, int source_reg)
16435{
16436 /* A8.8.103 MOV (register) (A8-486)
16437 MOV Rd, Rm (Encoding T1). */
16438 bfd_vma patched_inst = 0x4600
16439 | (target_reg & 0x7)
16440 | ((target_reg & 0x8) >> 3) << 7
16441 | (source_reg << 3);
16442
16443 return patched_inst;
16444}
16445
16446static inline bfd_vma
16447create_instruction_sub (int target_reg, int source_reg, int value)
16448{
16449 /* A8.8.221 SUB (immediate) (A8-708)
16450 SUB Rd, Rn, #value (Encoding T3). */
16451 bfd_vma patched_inst = 0xf1a00000
16452 | (target_reg << 8)
16453 | (source_reg << 16)
16454 | (/*S=*/0 << 20)
16455 | ((value & 0x800) >> 11) << 26
16456 | ((value & 0x700) >> 8) << 12
16457 | (value & 0x0ff);
16458
16459 return patched_inst;
16460}
16461
16462static inline bfd_vma
9239bbd3 16463create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 16464 int first_reg)
16465{
16466 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16467 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
16468 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 16469 | (/*W=*/wback << 21)
16470 | (base_reg << 16)
9239bbd3
CM		 16471 | (num_words & 0x000000ff)
16472 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 16473 | (first_reg & 0x00000001) << 22;
16474
16475 return patched_inst;
16476}
16477
16478static inline bfd_vma
9239bbd3
CM		 16479create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
16480 int first_reg)
a504d23a
LA		 16481{
16482 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16483 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
16484 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 16485 | (base_reg << 16)
9239bbd3
CM		 16486 | (num_words & 0x000000ff)
16487 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 16488 | (first_reg & 0x00000001) << 22;
16489
16490 return patched_inst;
16491}
16492
16493static inline bfd_vma
16494create_instruction_udf_w (int value)
16495{
16496 /* A8.8.247 UDF (A8-758)
16497 Undefined (Encoding T2). */
16498 bfd_vma patched_inst = 0xf7f0a000
16499 | (value & 0x00000fff)
16500 | (value & 0x000f0000) << 16;
16501
16502 return patched_inst;
16503}
16504
16505static inline bfd_vma
16506create_instruction_udf (int value)
16507{
16508 /* A8.8.247 UDF (A8-758)
16509 Undefined (Encoding T1). */
16510 bfd_vma patched_inst = 0xde00
16511 | (value & 0xff);
16512
16513 return patched_inst;
16514}
16515
16516/* Functions writing an instruction in memory, returning the next
16517 memory position to write to. */
16518
16519static inline bfd_byte *
16520push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
16521 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16522{
16523 put_thumb2_insn (htab, output_bfd, insn, pt);
16524 return pt + 4;
16525}
16526
16527static inline bfd_byte *
16528push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
16529 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16530{
16531 put_thumb_insn (htab, output_bfd, insn, pt);
16532 return pt + 2;
16533}
16534
16535/* Function filling up a region in memory with T1 and T2 UDFs taking
16536 care of alignment. */
16537
16538static bfd_byte *
16539stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
16540 bfd * output_bfd,
16541 const bfd_byte * const base_stub_contents,
16542 bfd_byte * const from_stub_contents,
16543 const bfd_byte * const end_stub_contents)
16544{
16545 bfd_byte *current_stub_contents = from_stub_contents;
16546
16547 /* Fill the remaining of the stub with deterministic contents : UDF
16548 instructions.
16549 Check if realignment is needed on modulo 4 frontier using T1, to
16550 further use T2. */
16551 if ((current_stub_contents < end_stub_contents)
16552 && !((current_stub_contents - base_stub_contents) % 2)
16553 && ((current_stub_contents - base_stub_contents) % 4))
16554 current_stub_contents =
16555 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16556 create_instruction_udf (0));
16557
16558 for (; current_stub_contents < end_stub_contents;)
16559 current_stub_contents =
16560 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16561 create_instruction_udf_w (0));
16562
16563 return current_stub_contents;
16564}
16565
16566/* Functions writing the stream of instructions equivalent to the
16567 derived sequence for ldmia, ldmdb, vldm respectively. */
16568
16569static void
16570stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
16571 bfd * output_bfd,
16572 const insn32 initial_insn,
16573 const bfd_byte *const initial_insn_addr,
16574 bfd_byte *const base_stub_contents)
16575{
16576 int wback = (initial_insn & 0x00200000) >> 21;
16577 int ri, rn = (initial_insn & 0x000F0000) >> 16;
16578 int insn_all_registers = initial_insn & 0x0000ffff;
16579 int insn_low_registers, insn_high_registers;
16580 int usable_register_mask;
16581 int nb_registers = popcount (insn_all_registers);
16582 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16583 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16584 bfd_byte *current_stub_contents = base_stub_contents;
16585
16586 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
16587
16588 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16589 smaller than 8 registers load sequences that do not cause the
16590 hardware issue. */
16591 if (nb_registers <= 8)
16592 {
16593 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16594 current_stub_contents =
16595 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16596 initial_insn);
16597
16598 /* B initial_insn_addr+4. */
16599 if (!restore_pc)
16600 current_stub_contents =
16601 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16602 create_instruction_branch_absolute
82188b29
NC		 16603 (initial_insn_addr - current_stub_contents));
16604
a504d23a
LA		 16605
16606 /* Fill the remaining of the stub with deterministic contents. */
16607 current_stub_contents =
16608 stm32l4xx_fill_stub_udf (htab, output_bfd,
16609 base_stub_contents, current_stub_contents,
16610 base_stub_contents +
16611 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16612
16613 return;
16614 }
16615
16616 /* - reg_list[13] == 0. */
16617 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
16618
16619 /* - reg_list[14] & reg_list[15] != 1. */
16620 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16621
16622 /* - if (wback==1) reg_list[rn] == 0. */
16623 BFD_ASSERT (!wback || !restore_rn);
16624
16625 /* - nb_registers > 8. */
16626 BFD_ASSERT (popcount (insn_all_registers) > 8);
16627
16628 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16629
16630 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
16631 - One with the 7 lowest registers (register mask 0x007F)
16632 This LDM will finally contain between 2 and 7 registers
16633 - One with the 7 highest registers (register mask 0xDF80)
16634 This ldm will finally contain between 2 and 7 registers. */
16635 insn_low_registers = insn_all_registers & 0x007F;
16636 insn_high_registers = insn_all_registers & 0xDF80;
16637
16638 /* A spare register may be needed during this veneer to temporarily
16639 handle the base register. This register will be restored with the
16640 last LDM operation.
16641 The usable register may be any general purpose register (that
16642 excludes PC, SP, LR : register mask is 0x1FFF). */
16643 usable_register_mask = 0x1FFF;
16644
16645 /* Generate the stub function. */
16646 if (wback)
16647 {
16648 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
16649 current_stub_contents =
16650 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16651 create_instruction_ldmia
16652 (rn, /*wback=*/1, insn_low_registers));
16653
16654 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
16655 current_stub_contents =
16656 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16657 create_instruction_ldmia
16658 (rn, /*wback=*/1, insn_high_registers));
16659 if (!restore_pc)
16660 {
16661 /* B initial_insn_addr+4. */
16662 current_stub_contents =
16663 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16664 create_instruction_branch_absolute
82188b29 16665 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16666 }
16667 }
16668 else /* if (!wback). */
16669 {
16670 ri = rn;
16671
16672 /* If Rn is not part of the high-register-list, move it there. */
16673 if (!(insn_high_registers & (1 << rn)))
16674 {
16675 /* Choose a Ri in the high-register-list that will be restored. */
16676 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16677
16678 /* MOV Ri, Rn. */
16679 current_stub_contents =
16680 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16681 create_instruction_mov (ri, rn));
16682 }
16683
16684 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
16685 current_stub_contents =
16686 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16687 create_instruction_ldmia
16688 (ri, /*wback=*/1, insn_low_registers));
16689
16690 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
16691 current_stub_contents =
16692 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16693 create_instruction_ldmia
16694 (ri, /*wback=*/0, insn_high_registers));
16695
16696 if (!restore_pc)
16697 {
16698 /* B initial_insn_addr+4. */
16699 current_stub_contents =
16700 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16701 create_instruction_branch_absolute
82188b29 16702 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16703 }
16704 }
16705
16706 /* Fill the remaining of the stub with deterministic contents. */
16707 current_stub_contents =
16708 stm32l4xx_fill_stub_udf (htab, output_bfd,
16709 base_stub_contents, current_stub_contents,
16710 base_stub_contents +
16711 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16712}
16713
16714static void
16715stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
16716 bfd * output_bfd,
16717 const insn32 initial_insn,
16718 const bfd_byte *const initial_insn_addr,
16719 bfd_byte *const base_stub_contents)
16720{
16721 int wback = (initial_insn & 0x00200000) >> 21;
16722 int ri, rn = (initial_insn & 0x000f0000) >> 16;
16723 int insn_all_registers = initial_insn & 0x0000ffff;
16724 int insn_low_registers, insn_high_registers;
16725 int usable_register_mask;
16726 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16727 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16728 int nb_registers = popcount (insn_all_registers);
16729 bfd_byte *current_stub_contents = base_stub_contents;
16730
16731 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
16732
16733 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16734 smaller than 8 registers load sequences that do not cause the
16735 hardware issue. */
16736 if (nb_registers <= 8)
16737 {
16738 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16739 current_stub_contents =
16740 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16741 initial_insn);
16742
16743 /* B initial_insn_addr+4. */
16744 current_stub_contents =
16745 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16746 create_instruction_branch_absolute
82188b29 16747 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16748
16749 /* Fill the remaining of the stub with deterministic contents. */
16750 current_stub_contents =
16751 stm32l4xx_fill_stub_udf (htab, output_bfd,
16752 base_stub_contents, current_stub_contents,
16753 base_stub_contents +
16754 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16755
16756 return;
16757 }
16758
16759 /* - reg_list[13] == 0. */
16760 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
16761
16762 /* - reg_list[14] & reg_list[15] != 1. */
16763 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16764
16765 /* - if (wback==1) reg_list[rn] == 0. */
16766 BFD_ASSERT (!wback || !restore_rn);
16767
16768 /* - nb_registers > 8. */
16769 BFD_ASSERT (popcount (insn_all_registers) > 8);
16770
16771 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16772
16773 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
16774 - One with the 7 lowest registers (register mask 0x007F)
16775 This LDM will finally contain between 2 and 7 registers
16776 - One with the 7 highest registers (register mask 0xDF80)
16777 This ldm will finally contain between 2 and 7 registers. */
16778 insn_low_registers = insn_all_registers & 0x007F;
16779 insn_high_registers = insn_all_registers & 0xDF80;
16780
16781 /* A spare register may be needed during this veneer to temporarily
16782 handle the base register. This register will be restored with
16783 the last LDM operation.
16784 The usable register may be any general purpose register (that excludes
16785 PC, SP, LR : register mask is 0x1FFF). */
16786 usable_register_mask = 0x1FFF;
16787
16788 /* Generate the stub function. */
16789 if (!wback && !restore_pc && !restore_rn)
16790 {
16791 /* Choose a Ri in the low-register-list that will be restored. */
16792 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16793
16794 /* MOV Ri, Rn. */
16795 current_stub_contents =
16796 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16797 create_instruction_mov (ri, rn));
16798
16799 /* LDMDB Ri!, {R-high-register-list}. */
16800 current_stub_contents =
16801 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16802 create_instruction_ldmdb
16803 (ri, /*wback=*/1, insn_high_registers));
16804
16805 /* LDMDB Ri, {R-low-register-list}. */
16806 current_stub_contents =
16807 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16808 create_instruction_ldmdb
16809 (ri, /*wback=*/0, insn_low_registers));
16810
16811 /* B initial_insn_addr+4. */
16812 current_stub_contents =
16813 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16814 create_instruction_branch_absolute
82188b29 16815 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16816 }
16817 else if (wback && !restore_pc && !restore_rn)
16818 {
16819 /* LDMDB Rn!, {R-high-register-list}. */
16820 current_stub_contents =
16821 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16822 create_instruction_ldmdb
16823 (rn, /*wback=*/1, insn_high_registers));
16824
16825 /* LDMDB Rn!, {R-low-register-list}. */
16826 current_stub_contents =
16827 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16828 create_instruction_ldmdb
16829 (rn, /*wback=*/1, insn_low_registers));
16830
16831 /* B initial_insn_addr+4. */
16832 current_stub_contents =
16833 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16834 create_instruction_branch_absolute
82188b29 16835 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16836 }
16837 else if (!wback && restore_pc && !restore_rn)
16838 {
16839 /* Choose a Ri in the high-register-list that will be restored. */
16840 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16841
16842 /* SUB Ri, Rn, #(4*nb_registers). */
16843 current_stub_contents =
16844 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16845 create_instruction_sub (ri, rn, (4 * nb_registers)));
16846
16847 /* LDMIA Ri!, {R-low-register-list}. */
16848 current_stub_contents =
16849 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16850 create_instruction_ldmia
16851 (ri, /*wback=*/1, insn_low_registers));
16852
16853 /* LDMIA Ri, {R-high-register-list}. */
16854 current_stub_contents =
16855 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16856 create_instruction_ldmia
16857 (ri, /*wback=*/0, insn_high_registers));
16858 }
16859 else if (wback && restore_pc && !restore_rn)
16860 {
16861 /* Choose a Ri in the high-register-list that will be restored. */
16862 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16863
16864 /* SUB Rn, Rn, #(4*nb_registers) */
16865 current_stub_contents =
16866 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16867 create_instruction_sub (rn, rn, (4 * nb_registers)));
16868
16869 /* MOV Ri, Rn. */
16870 current_stub_contents =
16871 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16872 create_instruction_mov (ri, rn));
16873
16874 /* LDMIA Ri!, {R-low-register-list}. */
16875 current_stub_contents =
16876 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16877 create_instruction_ldmia
16878 (ri, /*wback=*/1, insn_low_registers));
16879
16880 /* LDMIA Ri, {R-high-register-list}. */
16881 current_stub_contents =
16882 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16883 create_instruction_ldmia
16884 (ri, /*wback=*/0, insn_high_registers));
16885 }
16886 else if (!wback && !restore_pc && restore_rn)
16887 {
16888 ri = rn;
16889 if (!(insn_low_registers & (1 << rn)))
16890 {
16891 /* Choose a Ri in the low-register-list that will be restored. */
16892 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16893
16894 /* MOV Ri, Rn. */
16895 current_stub_contents =
16896 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16897 create_instruction_mov (ri, rn));
16898 }
16899
16900 /* LDMDB Ri!, {R-high-register-list}. */
16901 current_stub_contents =
16902 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16903 create_instruction_ldmdb
16904 (ri, /*wback=*/1, insn_high_registers));
16905
16906 /* LDMDB Ri, {R-low-register-list}. */
16907 current_stub_contents =
16908 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16909 create_instruction_ldmdb
16910 (ri, /*wback=*/0, insn_low_registers));
16911
16912 /* B initial_insn_addr+4. */
16913 current_stub_contents =
16914 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16915 create_instruction_branch_absolute
82188b29 16916 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16917 }
16918 else if (!wback && restore_pc && restore_rn)
16919 {
16920 ri = rn;
16921 if (!(insn_high_registers & (1 << rn)))
16922 {
16923 /* Choose a Ri in the high-register-list that will be restored. */
16924 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16925 }
16926
16927 /* SUB Ri, Rn, #(4*nb_registers). */
16928 current_stub_contents =
16929 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16930 create_instruction_sub (ri, rn, (4 * nb_registers)));
16931
16932 /* LDMIA Ri!, {R-low-register-list}. */
16933 current_stub_contents =
16934 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16935 create_instruction_ldmia
16936 (ri, /*wback=*/1, insn_low_registers));
16937
16938 /* LDMIA Ri, {R-high-register-list}. */
16939 current_stub_contents =
16940 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16941 create_instruction_ldmia
16942 (ri, /*wback=*/0, insn_high_registers));
16943 }
16944 else if (wback && restore_rn)
16945 {
16946 /* The assembler should not have accepted to encode this. */
16947 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
16948 "undefined behavior.\n");
16949 }
16950
16951 /* Fill the remaining of the stub with deterministic contents. */
16952 current_stub_contents =
16953 stm32l4xx_fill_stub_udf (htab, output_bfd,
16954 base_stub_contents, current_stub_contents,
16955 base_stub_contents +
16956 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16957
16958}
16959
16960static void
16961stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
16962 bfd * output_bfd,
16963 const insn32 initial_insn,
16964 const bfd_byte *const initial_insn_addr,
16965 bfd_byte *const base_stub_contents)
16966{
9239bbd3 16967 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 16968 bfd_byte *current_stub_contents = base_stub_contents;
16969
16970 BFD_ASSERT (is_thumb2_vldm (initial_insn));
16971
16972 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 16973 smaller than 8 words load sequences that do not cause the
a504d23a 16974 hardware issue. */
9239bbd3 16975 if (num_words <= 8)
a504d23a
LA		 16976 {
16977 /* Untouched instruction. */
16978 current_stub_contents =
16979 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16980 initial_insn);
16981
16982 /* B initial_insn_addr+4. */
16983 current_stub_contents =
16984 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16985 create_instruction_branch_absolute
82188b29 16986 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16987 }
16988 else
16989 {
9239bbd3
CM		 16990 bfd_boolean is_dp = /* DP encoding. */
16991 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 16992 bfd_boolean is_ia_nobang = /* (IA without !). */
16993 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
16994 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
16995 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
16996 bfd_boolean is_db_bang = /* (DB with !). */
16997 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 16998 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 16999 /* d = UInt (Vd:D);. */
9239bbd3 17000 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 17001 | (((unsigned int)initial_insn << 9) >> 31);
17002
9239bbd3
CM		 17003 /* Compute the number of 8-words chunks needed to split. */
17004 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 17005 int chunk;
17006
17007 /* The test coverage has been done assuming the following
17008 hypothesis that exactly one of the previous is_ predicates is
17009 true. */
9239bbd3
CM		 17010 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
17011 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 17012
9239bbd3 17013 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 17014 cases, then we emit the adjustments:
17015
17016 vldm rx, {...}
17017 -> vldm rx!, {8_words_or_less} for each needed 8_word
17018 -> sub rx, rx, #size (list)
17019
17020 vldm rx!, {...}
17021 -> vldm rx!, {8_words_or_less} for each needed 8_word
17022 This also handles vpop instruction (when rx is sp)
17023
17024 vldmd rx!, {...}
17025 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 17026 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 17027 {
9239bbd3
CM		 17028 bfd_vma new_insn = 0;
17029
a504d23a
LA		 17030 if (is_ia_nobang || is_ia_bang)
17031 {
9239bbd3
CM		 17032 new_insn = create_instruction_vldmia
17033 (base_reg,
17034 is_dp,
17035 /*wback= . */1,
17036 chunks - (chunk + 1) ?
17037 8 : num_words - chunk * 8,
17038 first_reg + chunk * 8);
a504d23a
LA		 17039 }
17040 else if (is_db_bang)
17041 {
9239bbd3
CM		 17042 new_insn = create_instruction_vldmdb
17043 (base_reg,
17044 is_dp,
17045 chunks - (chunk + 1) ?
17046 8 : num_words - chunk * 8,
17047 first_reg + chunk * 8);
a504d23a 17048 }
9239bbd3
CM		 17049
17050 if (new_insn)
17051 current_stub_contents =
17052 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17053 new_insn);
a504d23a
LA		 17054 }
17055
17056 /* Only this case requires the base register compensation
17057 subtract. */
17058 if (is_ia_nobang)
17059 {
17060 current_stub_contents =
17061 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17062 create_instruction_sub
9239bbd3 17063 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 17064 }
17065
17066 /* B initial_insn_addr+4. */
17067 current_stub_contents =
17068 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17069 create_instruction_branch_absolute
82188b29 17070 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17071 }
17072
17073 /* Fill the remaining of the stub with deterministic contents. */
17074 current_stub_contents =
17075 stm32l4xx_fill_stub_udf (htab, output_bfd,
17076 base_stub_contents, current_stub_contents,
17077 base_stub_contents +
17078 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
17079}
17080
17081static void
17082stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
17083 bfd * output_bfd,
17084 const insn32 wrong_insn,
17085 const bfd_byte *const wrong_insn_addr,
17086 bfd_byte *const stub_contents)
17087{
17088 if (is_thumb2_ldmia (wrong_insn))
17089 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
17090 wrong_insn, wrong_insn_addr,
17091 stub_contents);
17092 else if (is_thumb2_ldmdb (wrong_insn))
17093 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
17094 wrong_insn, wrong_insn_addr,
17095 stub_contents);
17096 else if (is_thumb2_vldm (wrong_insn))
17097 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
17098 wrong_insn, wrong_insn_addr,
17099 stub_contents);
17100}
17101
17102/* End of stm32l4xx work-around. */
17103
17104
491d01d3
YU		 17105static void
17106elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
17107 asection *output_sec, Elf_Internal_Rela *rel)
17108{
17109 BFD_ASSERT (output_sec && rel);
17110 struct bfd_elf_section_reloc_data *output_reldata;
17111 struct elf32_arm_link_hash_table *htab;
17112 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
17113 Elf_Internal_Shdr *rel_hdr;
17114
17115
17116 if (oesd->rel.hdr)
17117 {
17118 rel_hdr = oesd->rel.hdr;
17119 output_reldata = &(oesd->rel);
17120 }
17121 else if (oesd->rela.hdr)
17122 {
17123 rel_hdr = oesd->rela.hdr;
17124 output_reldata = &(oesd->rela);
17125 }
17126 else
17127 {
17128 abort ();
17129 }
17130
17131 bfd_byte *erel = rel_hdr->contents;
17132 erel += output_reldata->count * rel_hdr->sh_entsize;
17133 htab = elf32_arm_hash_table (info);
17134 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
17135 output_reldata->count++;
17136}
17137
e489d0ae
PB		 17138/* Do code byteswapping. Return FALSE afterwards so that the section is
17139 written out as normal. */
17140
17141static bfd_boolean
c7b8f16e 17142elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 17143 struct bfd_link_info *link_info,
17144 asection *sec,
e489d0ae
PB		 17145 bfd_byte *contents)
17146{
48229727 17147 unsigned int mapcount, errcount;
8e3de13a 17148 _arm_elf_section_data *arm_data;
c7b8f16e 17149 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 17150 elf32_arm_section_map *map;
c7b8f16e 17151 elf32_vfp11_erratum_list *errnode;
a504d23a 17152 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 17153 bfd_vma ptr;
17154 bfd_vma end;
c7b8f16e 17155 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 17156 bfd_byte tmp;
48229727 17157 unsigned int i;
57e8b36a 17158
4dfe6ac6
NC		 17159 if (globals == NULL)
17160 return FALSE;
17161
8e3de13a
NC		 17162 /* If this section has not been allocated an _arm_elf_section_data
17163 structure then we cannot record anything. */
17164 arm_data = get_arm_elf_section_data (sec);
17165 if (arm_data == NULL)
17166 return FALSE;
17167
17168 mapcount = arm_data->mapcount;
17169 map = arm_data->map;
c7b8f16e
JB		 17170 errcount = arm_data->erratumcount;
17171
17172 if (errcount != 0)
17173 {
17174 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
17175
17176 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 17177 errnode = errnode->next)
17178 {
17179 bfd_vma target = errnode->vma - offset;
17180
17181 switch (errnode->type)
17182 {
17183 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
17184 {
17185 bfd_vma branch_to_veneer;
17186 /* Original condition code of instruction, plus bit mask for
17187 ARM B instruction. */
17188 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
17189 | 0x0a000000;
c7b8f16e
JB		 17190
17191 /* The instruction is before the label. */
91d6fa6a 17192 target -= 4;
c7b8f16e
JB		 17193
17194 /* Above offset included in -4 below. */
17195 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 17196 - errnode->vma - 4;
c7b8f16e
JB		 17197
17198 if ((signed) branch_to_veneer < -(1 << 25)
17199 || (signed) branch_to_veneer >= (1 << 25))
17200 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17201 "range"), output_bfd);
17202
99059e56
RM		 17203 insn |= (branch_to_veneer >> 2) & 0xffffff;
17204 contents[endianflip ^ target] = insn & 0xff;
17205 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17206 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17207 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17208 }
17209 break;
c7b8f16e
JB		 17210
17211 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 17212 {
17213 bfd_vma branch_from_veneer;
17214 unsigned int insn;
c7b8f16e 17215
99059e56
RM		 17216 /* Take size of veneer into account. */
17217 branch_from_veneer = errnode->u.v.branch->vma
17218 - errnode->vma - 12;
c7b8f16e
JB		 17219
17220 if ((signed) branch_from_veneer < -(1 << 25)
17221 || (signed) branch_from_veneer >= (1 << 25))
17222 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17223 "range"), output_bfd);
17224
99059e56
RM		 17225 /* Original instruction. */
17226 insn = errnode->u.v.branch->u.b.vfp_insn;
17227 contents[endianflip ^ target] = insn & 0xff;
17228 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17229 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17230 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17231
17232 /* Branch back to insn after original insn. */
17233 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
17234 contents[endianflip ^ (target + 4)] = insn & 0xff;
17235 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
17236 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
17237 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
17238 }
17239 break;
c7b8f16e 17240
99059e56
RM		 17241 default:
17242 abort ();
17243 }
17244 }
c7b8f16e 17245 }
e489d0ae 17246
a504d23a
LA		 17247 if (arm_data->stm32l4xx_erratumcount != 0)
17248 {
17249 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
17250 stm32l4xx_errnode != 0;
17251 stm32l4xx_errnode = stm32l4xx_errnode->next)
17252 {
17253 bfd_vma target = stm32l4xx_errnode->vma - offset;
17254
17255 switch (stm32l4xx_errnode->type)
17256 {
17257 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
17258 {
17259 unsigned int insn;
17260 bfd_vma branch_to_veneer =
17261 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
17262
17263 if ((signed) branch_to_veneer < -(1 << 24)
17264 || (signed) branch_to_veneer >= (1 << 24))
17265 {
17266 bfd_vma out_of_range =
17267 ((signed) branch_to_veneer < -(1 << 24)) ?
17268 - branch_to_veneer - (1 << 24) :
17269 ((signed) branch_to_veneer >= (1 << 24)) ?
17270 branch_to_veneer - (1 << 24) : 0;
17271
17272 (*_bfd_error_handler)
17273 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 17274 "Jump out of range by %ld bytes. "
a504d23a
LA		 17275 "Cannot encode branch instruction. "),
17276 output_bfd,
eee926f2 17277 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 17278 out_of_range);
17279 continue;
17280 }
17281
17282 insn = create_instruction_branch_absolute
82188b29 17283 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 17284
17285 /* The instruction is before the label. */
17286 target -= 4;
17287
17288 put_thumb2_insn (globals, output_bfd,
17289 (bfd_vma) insn, contents + target);
17290 }
17291 break;
17292
17293 case STM32L4XX_ERRATUM_VENEER:
17294 {
82188b29
NC		 17295 bfd_byte * veneer;
17296 bfd_byte * veneer_r;
a504d23a
LA		 17297 unsigned int insn;
17298
82188b29
NC		 17299 veneer = contents + target;
17300 veneer_r = veneer
17301 + stm32l4xx_errnode->u.b.veneer->vma
17302 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 17303
17304 if ((signed) (veneer_r - veneer -
17305 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17306 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17307 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17308 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
17309 || (signed) (veneer_r - veneer) >= (1 << 24))
17310 {
17311 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
17312 "veneer."), output_bfd);
17313 continue;
17314 }
17315
17316 /* Original instruction. */
17317 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
17318
17319 stm32l4xx_create_replacing_stub
17320 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
17321 }
17322 break;
17323
17324 default:
17325 abort ();
17326 }
17327 }
17328 }
17329
2468f9c9
PB		 17330 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
17331 {
17332 arm_unwind_table_edit *edit_node
99059e56 17333 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 17334 /* Now, sec->size is the size of the section we will write. The original
99059e56 17335 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 17336 markers) was sec->rawsize. (This isn't the case if we perform no
17337 edits, then rawsize will be zero and we should use size). */
21d799b5 17338 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 17339 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
17340 unsigned int in_index, out_index;
17341 bfd_vma add_to_offsets = 0;
17342
17343 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 17344 {
2468f9c9
PB		 17345 if (edit_node)
17346 {
17347 unsigned int edit_index = edit_node->index;
b38cadfb 17348
2468f9c9 17349 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 17350 {
2468f9c9
PB		 17351 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17352 contents + in_index * 8, add_to_offsets);
17353 out_index++;
17354 in_index++;
17355 }
17356 else if (in_index == edit_index
17357 || (in_index * 8 >= input_size
17358 && edit_index == UINT_MAX))
99059e56 17359 {
2468f9c9
PB		 17360 switch (edit_node->type)
17361 {
17362 case DELETE_EXIDX_ENTRY:
17363 in_index++;
17364 add_to_offsets += 8;
17365 break;
b38cadfb 17366
2468f9c9
PB		 17367 case INSERT_EXIDX_CANTUNWIND_AT_END:
17368 {
99059e56 17369 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 17370 bfd_vma text_offset = text_sec->output_section->vma
17371 + text_sec->output_offset
17372 + text_sec->size;
17373 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 17374 unsigned long prel31_offset;
2468f9c9
PB		 17375
17376 /* Note: this is meant to be equivalent to an
17377 R_ARM_PREL31 relocation. These synthetic
17378 EXIDX_CANTUNWIND markers are not relocated by the
17379 usual BFD method. */
17380 prel31_offset = (text_offset - exidx_offset)
17381 & 0x7ffffffful;
491d01d3
YU		 17382 if (bfd_link_relocatable (link_info))
17383 {
17384 /* Here relocation for new EXIDX_CANTUNWIND is
17385 created, so there is no need to
17386 adjust offset by hand. */
17387 prel31_offset = text_sec->output_offset
17388 + text_sec->size;
17389
17390 /* New relocation entity. */
17391 asection *text_out = text_sec->output_section;
17392 Elf_Internal_Rela rel;
17393 rel.r_addend = 0;
17394 rel.r_offset = exidx_offset;
17395 rel.r_info = ELF32_R_INFO (text_out->target_index,
17396 R_ARM_PREL31);
17397
17398 elf32_arm_add_relocation (output_bfd, link_info,
17399 sec->output_section,
17400 &rel);
17401 }
2468f9c9
PB		 17402
17403 /* First address we can't unwind. */
17404 bfd_put_32 (output_bfd, prel31_offset,
17405 &edited_contents[out_index * 8]);
17406
17407 /* Code for EXIDX_CANTUNWIND. */
17408 bfd_put_32 (output_bfd, 0x1,
17409 &edited_contents[out_index * 8 + 4]);
17410
17411 out_index++;
17412 add_to_offsets -= 8;
17413 }
17414 break;
17415 }
b38cadfb 17416
2468f9c9
PB		 17417 edit_node = edit_node->next;
17418 }
17419 }
17420 else
17421 {
17422 /* No more edits, copy remaining entries verbatim. */
17423 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17424 contents + in_index * 8, add_to_offsets);
17425 out_index++;
17426 in_index++;
17427 }
17428 }
17429
17430 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
17431 bfd_set_section_contents (output_bfd, sec->output_section,
17432 edited_contents,
17433 (file_ptr) sec->output_offset, sec->size);
17434
17435 return TRUE;
17436 }
17437
48229727
JB		 17438 /* Fix code to point to Cortex-A8 erratum stubs. */
17439 if (globals->fix_cortex_a8)
17440 {
17441 struct a8_branch_to_stub_data data;
17442
17443 data.writing_section = sec;
17444 data.contents = contents;
17445
a504d23a
LA		 17446 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
17447 & data);
48229727
JB		 17448 }
17449
e489d0ae
PB		 17450 if (mapcount == 0)
17451 return FALSE;
17452
c7b8f16e 17453 if (globals->byteswap_code)
e489d0ae 17454 {
c7b8f16e 17455 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 17456
c7b8f16e
JB		 17457 ptr = map[0].vma;
17458 for (i = 0; i < mapcount; i++)
99059e56
RM		 17459 {
17460 if (i == mapcount - 1)
c7b8f16e 17461 end = sec->size;
99059e56
RM		 17462 else
17463 end = map[i + 1].vma;
e489d0ae 17464
99059e56 17465 switch (map[i].type)
e489d0ae 17466 {
c7b8f16e
JB		 17467 case 'a':
17468 /* Byte swap code words. */
17469 while (ptr + 3 < end)
99059e56
RM		 17470 {
17471 tmp = contents[ptr];
17472 contents[ptr] = contents[ptr + 3];
17473 contents[ptr + 3] = tmp;
17474 tmp = contents[ptr + 1];
17475 contents[ptr + 1] = contents[ptr + 2];
17476 contents[ptr + 2] = tmp;
17477 ptr += 4;
17478 }
c7b8f16e 17479 break;
e489d0ae 17480
c7b8f16e
JB		 17481 case 't':
17482 /* Byte swap code halfwords. */
17483 while (ptr + 1 < end)
99059e56
RM		 17484 {
17485 tmp = contents[ptr];
17486 contents[ptr] = contents[ptr + 1];
17487 contents[ptr + 1] = tmp;
17488 ptr += 2;
17489 }
c7b8f16e
JB		 17490 break;
17491
17492 case 'd':
17493 /* Leave data alone. */
17494 break;
17495 }
99059e56
RM		 17496 ptr = end;
17497 }
e489d0ae 17498 }
8e3de13a 17499
93204d3a 17500 free (map);
47b2e99c 17501 arm_data->mapcount = -1;
c7b8f16e 17502 arm_data->mapsize = 0;
8e3de13a 17503 arm_data->map = NULL;
8e3de13a 17504
e489d0ae
PB		 17505 return FALSE;
17506}
17507
0beaef2b
PB		 17508/* Mangle thumb function symbols as we read them in. */
17509
8384fb8f 17510static bfd_boolean
0beaef2b
PB		 17511elf32_arm_swap_symbol_in (bfd * abfd,
17512 const void *psrc,
17513 const void *pshn,
17514 Elf_Internal_Sym *dst)
17515{
8384fb8f
AM		 17516 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
17517 return FALSE;
0beaef2b
PB		 17518
17519 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 17520 the address. */
63e1a0fc
PB		 17521 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
17522 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 17523 {
63e1a0fc
PB		 17524 if (dst->st_value & 1)
17525 {
17526 dst->st_value &= ~(bfd_vma) 1;
17527 dst->st_target_internal = ST_BRANCH_TO_THUMB;
17528 }
17529 else
17530 dst->st_target_internal = ST_BRANCH_TO_ARM;
35fc36a8
RS		 17531 }
17532 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
17533 {
17534 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
17535 dst->st_target_internal = ST_BRANCH_TO_THUMB;
0beaef2b 17536 }
35fc36a8
RS		 17537 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
17538 dst->st_target_internal = ST_BRANCH_LONG;
17539 else
63e1a0fc 17540 dst->st_target_internal = ST_BRANCH_UNKNOWN;
35fc36a8 17541
8384fb8f 17542 return TRUE;
0beaef2b
PB		 17543}
17544
17545
17546/* Mangle thumb function symbols as we write them out. */
17547
17548static void
17549elf32_arm_swap_symbol_out (bfd *abfd,
17550 const Elf_Internal_Sym *src,
17551 void *cdst,
17552 void *shndx)
17553{
17554 Elf_Internal_Sym newsym;
17555
17556 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
17557 of the address set, as per the new EABI. We do this unconditionally
17558 because objcopy does not set the elf header flags until after
17559 it writes out the symbol table. */
35fc36a8 17560 if (src->st_target_internal == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 17561 {
17562 newsym = *src;
34e77a92
RS		 17563 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
17564 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 17565 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 17566 {
17567 /* Do this only for defined symbols. At link type, the static
17568 linker will simulate the work of dynamic linker of resolving
17569 symbols and will carry over the thumbness of found symbols to
17570 the output symbol table. It's not clear how it happens, but
17571 the thumbness of undefined symbols can well be different at
17572 runtime, and writing '1' for them will be confusing for users
17573 and possibly for dynamic linker itself.
17574 */
17575 newsym.st_value |= 1;
17576 }
906e58ca 17577
0beaef2b
PB		 17578 src = &newsym;
17579 }
17580 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
17581}
17582
b294bdf8
MM		 17583/* Add the PT_ARM_EXIDX program header. */
17584
17585static bfd_boolean
906e58ca 17586elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 17587 struct bfd_link_info *info ATTRIBUTE_UNUSED)
17588{
17589 struct elf_segment_map *m;
17590 asection *sec;
17591
17592 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17593 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17594 {
17595 /* If there is already a PT_ARM_EXIDX header, then we do not
17596 want to add another one. This situation arises when running
17597 "strip"; the input binary already has the header. */
12bd6957 17598 m = elf_seg_map (abfd);
b294bdf8
MM		 17599 while (m && m->p_type != PT_ARM_EXIDX)
17600 m = m->next;
17601 if (!m)
17602 {
21d799b5 17603 m = (struct elf_segment_map *)
99059e56 17604 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 17605 if (m == NULL)
17606 return FALSE;
17607 m->p_type = PT_ARM_EXIDX;
17608 m->count = 1;
17609 m->sections[0] = sec;
17610
12bd6957
AM		 17611 m->next = elf_seg_map (abfd);
17612 elf_seg_map (abfd) = m;
b294bdf8
MM		 17613 }
17614 }
17615
17616 return TRUE;
17617}
17618
17619/* We may add a PT_ARM_EXIDX program header. */
17620
17621static int
a6b96beb
AM		 17622elf32_arm_additional_program_headers (bfd *abfd,
17623 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 17624{
17625 asection *sec;
17626
17627 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17628 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17629 return 1;
17630 else
17631 return 0;
17632}
17633
34e77a92
RS		 17634/* Hook called by the linker routine which adds symbols from an object
17635 file. */
17636
17637static bfd_boolean
17638elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
17639 Elf_Internal_Sym *sym, const char **namep,
17640 flagword *flagsp, asection **secp, bfd_vma *valp)
17641{
f1885d1e
AM		 17642 if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
17643 || ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE)
17644 && (abfd->flags & DYNAMIC) == 0
17645 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
13a2df29 17646 elf_tdata (info->output_bfd)->has_gnu_symbols = elf_gnu_symbol_any;
34e77a92 17647
c792917c
NC		 17648 if (elf32_arm_hash_table (info) == NULL)
17649 return FALSE;
17650
34e77a92
RS		 17651 if (elf32_arm_hash_table (info)->vxworks_p
17652 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
17653 flagsp, secp, valp))
17654 return FALSE;
17655
17656 return TRUE;
17657}
17658
0beaef2b 17659/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 17660const struct elf_size_info elf32_arm_size_info =
17661{
0beaef2b
PB		 17662 sizeof (Elf32_External_Ehdr),
17663 sizeof (Elf32_External_Phdr),
17664 sizeof (Elf32_External_Shdr),
17665 sizeof (Elf32_External_Rel),
17666 sizeof (Elf32_External_Rela),
17667 sizeof (Elf32_External_Sym),
17668 sizeof (Elf32_External_Dyn),
17669 sizeof (Elf_External_Note),
17670 4,
17671 1,
17672 32, 2,
17673 ELFCLASS32, EV_CURRENT,
17674 bfd_elf32_write_out_phdrs,
17675 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 17676 bfd_elf32_checksum_contents,
0beaef2b
PB		 17677 bfd_elf32_write_relocs,
17678 elf32_arm_swap_symbol_in,
17679 elf32_arm_swap_symbol_out,
17680 bfd_elf32_slurp_reloc_table,
17681 bfd_elf32_slurp_symbol_table,
17682 bfd_elf32_swap_dyn_in,
17683 bfd_elf32_swap_dyn_out,
17684 bfd_elf32_swap_reloc_in,
17685 bfd_elf32_swap_reloc_out,
17686 bfd_elf32_swap_reloca_in,
17687 bfd_elf32_swap_reloca_out
17688};
17689
685e70ae
VK		 17690static bfd_vma
17691read_code32 (const bfd *abfd, const bfd_byte *addr)
17692{
17693 /* V7 BE8 code is always little endian. */
17694 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17695 return bfd_getl32 (addr);
17696
17697 return bfd_get_32 (abfd, addr);
17698}
17699
17700static bfd_vma
17701read_code16 (const bfd *abfd, const bfd_byte *addr)
17702{
17703 /* V7 BE8 code is always little endian. */
17704 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17705 return bfd_getl16 (addr);
17706
17707 return bfd_get_16 (abfd, addr);
17708}
17709
6a631e86
YG		 17710/* Return size of plt0 entry starting at ADDR
17711 or (bfd_vma) -1 if size can not be determined. */
17712
17713static bfd_vma
17714elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
17715{
17716 bfd_vma first_word;
17717 bfd_vma plt0_size;
17718
685e70ae 17719 first_word = read_code32 (abfd, addr);
6a631e86
YG		 17720
17721 if (first_word == elf32_arm_plt0_entry[0])
17722 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
17723 else if (first_word == elf32_thumb2_plt0_entry[0])
17724 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
17725 else
17726 /* We don't yet handle this PLT format. */
17727 return (bfd_vma) -1;
17728
17729 return plt0_size;
17730}
17731
17732/* Return size of plt entry starting at offset OFFSET
17733 of plt section located at address START
17734 or (bfd_vma) -1 if size can not be determined. */
17735
17736static bfd_vma
17737elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
17738{
17739 bfd_vma first_insn;
17740 bfd_vma plt_size = 0;
17741 const bfd_byte *addr = start + offset;
17742
17743 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 17744 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 17745 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
17746
17747 /* Respect Thumb stub if necessary. */
685e70ae 17748 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 17749 {
17750 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
17751 }
17752
17753 /* Strip immediate from first add. */
685e70ae 17754 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 17755
17756#ifdef FOUR_WORD_PLT
17757 if (first_insn == elf32_arm_plt_entry[0])
17758 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
17759#else
17760 if (first_insn == elf32_arm_plt_entry_long[0])
17761 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
17762 else if (first_insn == elf32_arm_plt_entry_short[0])
17763 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
17764#endif
17765 else
17766 /* We don't yet handle this PLT format. */
17767 return (bfd_vma) -1;
17768
17769 return plt_size;
17770}
17771
17772/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
17773
17774static long
17775elf32_arm_get_synthetic_symtab (bfd *abfd,
17776 long symcount ATTRIBUTE_UNUSED,
17777 asymbol **syms ATTRIBUTE_UNUSED,
17778 long dynsymcount,
17779 asymbol **dynsyms,
17780 asymbol **ret)
17781{
17782 asection *relplt;
17783 asymbol *s;
17784 arelent *p;
17785 long count, i, n;
17786 size_t size;
17787 Elf_Internal_Shdr *hdr;
17788 char *names;
17789 asection *plt;
17790 bfd_vma offset;
17791 bfd_byte *data;
17792
17793 *ret = NULL;
17794
17795 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
17796 return 0;
17797
17798 if (dynsymcount <= 0)
17799 return 0;
17800
17801 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
17802 if (relplt == NULL)
17803 return 0;
17804
17805 hdr = &elf_section_data (relplt)->this_hdr;
17806 if (hdr->sh_link != elf_dynsymtab (abfd)
17807 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
17808 return 0;
17809
17810 plt = bfd_get_section_by_name (abfd, ".plt");
17811 if (plt == NULL)
17812 return 0;
17813
17814 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
17815 return -1;
17816
17817 data = plt->contents;
17818 if (data == NULL)
17819 {
17820 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
17821 return -1;
17822 bfd_cache_section_contents((asection *) plt, data);
17823 }
17824
17825 count = relplt->size / hdr->sh_entsize;
17826 size = count * sizeof (asymbol);
17827 p = relplt->relocation;
17828 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17829 {
17830 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
17831 if (p->addend != 0)
17832 size += sizeof ("+0x") - 1 + 8;
17833 }
17834
17835 s = *ret = (asymbol *) bfd_malloc (size);
17836 if (s == NULL)
17837 return -1;
17838
17839 offset = elf32_arm_plt0_size (abfd, data);
17840 if (offset == (bfd_vma) -1)
17841 return -1;
17842
17843 names = (char *) (s + count);
17844 p = relplt->relocation;
17845 n = 0;
17846 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17847 {
17848 size_t len;
17849
17850 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
17851 if (plt_size == (bfd_vma) -1)
17852 break;
17853
17854 *s = **p->sym_ptr_ptr;
17855 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
17856 we are defining a symbol, ensure one of them is set. */
17857 if ((s->flags & BSF_LOCAL) == 0)
17858 s->flags |= BSF_GLOBAL;
17859 s->flags |= BSF_SYNTHETIC;
17860 s->section = plt;
17861 s->value = offset;
17862 s->name = names;
17863 s->udata.p = NULL;
17864 len = strlen ((*p->sym_ptr_ptr)->name);
17865 memcpy (names, (*p->sym_ptr_ptr)->name, len);
17866 names += len;
17867 if (p->addend != 0)
17868 {
17869 char buf[30], *a;
17870
17871 memcpy (names, "+0x", sizeof ("+0x") - 1);
17872 names += sizeof ("+0x") - 1;
17873 bfd_sprintf_vma (abfd, buf, p->addend);
17874 for (a = buf; *a == '0'; ++a)
17875 ;
17876 len = strlen (a);
17877 memcpy (names, a, len);
17878 names += len;
17879 }
17880 memcpy (names, "@plt", sizeof ("@plt"));
17881 names += sizeof ("@plt");
17882 ++s, ++n;
17883 offset += plt_size;
17884 }
17885
17886 return n;
17887}
17888
ac4c9b04
MG		 17889static bfd_boolean
17890elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
17891{
17892 if (hdr->sh_flags & SHF_ARM_NOREAD)
17893 *flags |= SEC_ELF_NOREAD;
17894 return TRUE;
17895}
17896
17897static flagword
17898elf32_arm_lookup_section_flags (char *flag_name)
17899{
17900 if (!strcmp (flag_name, "SHF_ARM_NOREAD"))
17901 return SHF_ARM_NOREAD;
17902
17903 return SEC_NO_FLAGS;
17904}
17905
491d01d3
YU		 17906static unsigned int
17907elf32_arm_count_additional_relocs (asection *sec)
17908{
17909 struct _arm_elf_section_data *arm_data;
17910 arm_data = get_arm_elf_section_data (sec);
17911 return arm_data->additional_reloc_count;
17912}
17913
5522f910
NC		 17914/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
17915 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
17916 FALSE otherwise. ISECTION is the best guess matching section from the
17917 input bfd IBFD, but it might be NULL. */
17918
17919static bfd_boolean
17920elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
17921 bfd *obfd ATTRIBUTE_UNUSED,
17922 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
17923 Elf_Internal_Shdr *osection)
17924{
17925 switch (osection->sh_type)
17926 {
17927 case SHT_ARM_EXIDX:
17928 {
17929 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
17930 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
17931 unsigned i = 0;
17932
17933 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
17934 osection->sh_info = 0;
17935
17936 /* The sh_link field must be set to the text section associated with
17937 this index section. Unfortunately the ARM EHABI does not specify
17938 exactly how to determine this association. Our caller does try
17939 to match up OSECTION with its corresponding input section however
17940 so that is a good first guess. */
17941 if (isection != NULL
17942 && osection->bfd_section != NULL
17943 && isection->bfd_section != NULL
17944 && isection->bfd_section->output_section != NULL
17945 && isection->bfd_section->output_section == osection->bfd_section
17946 && iheaders != NULL
17947 && isection->sh_link > 0
17948 && isection->sh_link < elf_numsections (ibfd)
17949 && iheaders[isection->sh_link]->bfd_section != NULL
17950 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
17951 )
17952 {
17953 for (i = elf_numsections (obfd); i-- > 0;)
17954 if (oheaders[i]->bfd_section
17955 == iheaders[isection->sh_link]->bfd_section->output_section)
17956 break;
17957 }
17958
17959 if (i == 0)
17960 {
17961 /* Failing that we have to find a matching section ourselves. If
17962 we had the output section name available we could compare that
17963 with input section names. Unfortunately we don't. So instead
17964 we use a simple heuristic and look for the nearest executable
17965 section before this one. */
17966 for (i = elf_numsections (obfd); i-- > 0;)
17967 if (oheaders[i] == osection)
17968 break;
17969 if (i == 0)
17970 break;
17971
17972 while (i-- > 0)
17973 if (oheaders[i]->sh_type == SHT_PROGBITS
17974 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
17975 == (SHF_ALLOC | SHF_EXECINSTR))
17976 break;
17977 }
17978
17979 if (i)
17980 {
17981 osection->sh_link = i;
17982 /* If the text section was part of a group
17983 then the index section should be too. */
17984 if (oheaders[i]->sh_flags & SHF_GROUP)
17985 osection->sh_flags |= SHF_GROUP;
17986 return TRUE;
17987 }
17988 }
17989 break;
17990
17991 case SHT_ARM_PREEMPTMAP:
17992 osection->sh_flags = SHF_ALLOC;
17993 break;
17994
17995 case SHT_ARM_ATTRIBUTES:
17996 case SHT_ARM_DEBUGOVERLAY:
17997 case SHT_ARM_OVERLAYSECTION:
17998 default:
17999 break;
18000 }
18001
18002 return FALSE;
18003}
18004
18005#undef elf_backend_copy_special_section_fields
18006#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
18007
252b5132 18008#define ELF_ARCH bfd_arch_arm
ae95ffa6 18009#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 18010#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 18011#ifdef __QNXTARGET__
18012#define ELF_MAXPAGESIZE 0x1000
18013#else
7572ca89 18014#define ELF_MAXPAGESIZE 0x10000
d0facd1b 18015#endif
b1342370 18016#define ELF_MINPAGESIZE 0x1000
24718e3b 18017#define ELF_COMMONPAGESIZE 0x1000
252b5132 18018
ba93b8ac
DJ		 18019#define bfd_elf32_mkobject elf32_arm_mkobject
18020
99e4ae17
AJ		 18021#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
18022#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 18023#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
18024#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
18025#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 18026#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 18027#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 18028#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 18029#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 18030#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 18031#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 18032#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 18033#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 18034
18035#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
18036#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 18037#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 18038#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
18039#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 18040#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 18041#define elf_backend_write_section elf32_arm_write_section
252b5132 18042#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 18043#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 18044#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
18045#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
18046#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 18047#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 18048#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 18049#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 18050#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 18051#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 18052#define elf_backend_fake_sections elf32_arm_fake_sections
18053#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 18054#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 18055#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 18056#define elf_backend_size_info elf32_arm_size_info
b294bdf8 18057#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 18058#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
18059#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
18060#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 18061#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 18062#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
906e58ca
NC		 18063
18064#define elf_backend_can_refcount 1
18065#define elf_backend_can_gc_sections 1
18066#define elf_backend_plt_readonly 1
18067#define elf_backend_want_got_plt 1
18068#define elf_backend_want_plt_sym 0
18069#define elf_backend_may_use_rel_p 1
18070#define elf_backend_may_use_rela_p 0
4e7fd91e 18071#define elf_backend_default_use_rela_p 0
252b5132 18072
04f7c78d 18073#define elf_backend_got_header_size 12
b68a20d6 18074#define elf_backend_extern_protected_data 1
04f7c78d 18075
906e58ca
NC		 18076#undef elf_backend_obj_attrs_vendor
18077#define elf_backend_obj_attrs_vendor "aeabi"
18078#undef elf_backend_obj_attrs_section
18079#define elf_backend_obj_attrs_section ".ARM.attributes"
18080#undef elf_backend_obj_attrs_arg_type
18081#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
18082#undef elf_backend_obj_attrs_section_type
104d59d1 18083#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 18084#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
18085#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 18086
ac4c9b04
MG		 18087#undef elf_backend_section_flags
18088#define elf_backend_section_flags elf32_arm_section_flags
18089#undef elf_backend_lookup_section_flags_hook
18090#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
18091
252b5132 18092#include "elf32-target.h"
7f266840 18093
b38cadfb
NC		 18094/* Native Client targets. */
18095
18096#undef TARGET_LITTLE_SYM
6d00b590 18097#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 18098#undef TARGET_LITTLE_NAME
18099#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
18100#undef TARGET_BIG_SYM
6d00b590 18101#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 18102#undef TARGET_BIG_NAME
18103#define TARGET_BIG_NAME "elf32-bigarm-nacl"
18104
18105/* Like elf32_arm_link_hash_table_create -- but overrides
18106 appropriately for NaCl. */
18107
18108static struct bfd_link_hash_table *
18109elf32_arm_nacl_link_hash_table_create (bfd *abfd)
18110{
18111 struct bfd_link_hash_table *ret;
18112
18113 ret = elf32_arm_link_hash_table_create (abfd);
18114 if (ret)
18115 {
18116 struct elf32_arm_link_hash_table *htab
18117 = (struct elf32_arm_link_hash_table *) ret;
18118
18119 htab->nacl_p = 1;
18120
18121 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
18122 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
18123 }
18124 return ret;
18125}
18126
18127/* Since NaCl doesn't use the ARM-specific unwind format, we don't
18128 really need to use elf32_arm_modify_segment_map. But we do it
18129 anyway just to reduce gratuitous differences with the stock ARM backend. */
18130
18131static bfd_boolean
18132elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
18133{
18134 return (elf32_arm_modify_segment_map (abfd, info)
18135 && nacl_modify_segment_map (abfd, info));
18136}
18137
887badb3
RM		 18138static void
18139elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
18140{
18141 elf32_arm_final_write_processing (abfd, linker);
18142 nacl_final_write_processing (abfd, linker);
18143}
18144
6a631e86
YG		 18145static bfd_vma
18146elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
18147 const arelent *rel ATTRIBUTE_UNUSED)
18148{
18149 return plt->vma
18150 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
18151 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
18152}
887badb3 18153
b38cadfb 18154#undef elf32_bed
6a631e86 18155#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 18156#undef bfd_elf32_bfd_link_hash_table_create
18157#define bfd_elf32_bfd_link_hash_table_create \
18158 elf32_arm_nacl_link_hash_table_create
18159#undef elf_backend_plt_alignment
6a631e86 18160#define elf_backend_plt_alignment 4
b38cadfb
NC		 18161#undef elf_backend_modify_segment_map
18162#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
18163#undef elf_backend_modify_program_headers
18164#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 18165#undef elf_backend_final_write_processing
18166#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 18167#undef bfd_elf32_get_synthetic_symtab
18168#undef elf_backend_plt_sym_val
18169#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 18170#undef elf_backend_copy_special_section_fields
b38cadfb 18171
887badb3
RM		 18172#undef ELF_MINPAGESIZE
18173#undef ELF_COMMONPAGESIZE
18174
b38cadfb
NC		 18175
18176#include "elf32-target.h"
18177
18178/* Reset to defaults. */
18179#undef elf_backend_plt_alignment
18180#undef elf_backend_modify_segment_map
18181#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
18182#undef elf_backend_modify_program_headers
887badb3
RM		 18183#undef elf_backend_final_write_processing
18184#define elf_backend_final_write_processing elf32_arm_final_write_processing
18185#undef ELF_MINPAGESIZE
18186#define ELF_MINPAGESIZE 0x1000
18187#undef ELF_COMMONPAGESIZE
18188#define ELF_COMMONPAGESIZE 0x1000
18189
b38cadfb 18190
906e58ca 18191/* VxWorks Targets. */
4e7fd91e 18192
906e58ca 18193#undef TARGET_LITTLE_SYM
6d00b590 18194#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 18195#undef TARGET_LITTLE_NAME
4e7fd91e 18196#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 18197#undef TARGET_BIG_SYM
6d00b590 18198#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 18199#undef TARGET_BIG_NAME
4e7fd91e
PB		 18200#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
18201
18202/* Like elf32_arm_link_hash_table_create -- but overrides
18203 appropriately for VxWorks. */
906e58ca 18204
4e7fd91e
PB		 18205static struct bfd_link_hash_table *
18206elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
18207{
18208 struct bfd_link_hash_table *ret;
18209
18210 ret = elf32_arm_link_hash_table_create (abfd);
18211 if (ret)
18212 {
18213 struct elf32_arm_link_hash_table *htab
00a97672 18214 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 18215 htab->use_rel = 0;
00a97672 18216 htab->vxworks_p = 1;
4e7fd91e
PB		 18217 }
18218 return ret;
906e58ca 18219}
4e7fd91e 18220
00a97672
RS		 18221static void
18222elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
18223{
18224 elf32_arm_final_write_processing (abfd, linker);
18225 elf_vxworks_final_write_processing (abfd, linker);
18226}
18227
906e58ca 18228#undef elf32_bed
4e7fd91e
PB		 18229#define elf32_bed elf32_arm_vxworks_bed
18230
906e58ca
NC		 18231#undef bfd_elf32_bfd_link_hash_table_create
18232#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 18233#undef elf_backend_final_write_processing
18234#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
18235#undef elf_backend_emit_relocs
18236#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 18237
906e58ca 18238#undef elf_backend_may_use_rel_p
00a97672 18239#define elf_backend_may_use_rel_p 0
906e58ca 18240#undef elf_backend_may_use_rela_p
00a97672 18241#define elf_backend_may_use_rela_p 1
906e58ca 18242#undef elf_backend_default_use_rela_p
00a97672 18243#define elf_backend_default_use_rela_p 1
906e58ca 18244#undef elf_backend_want_plt_sym
00a97672 18245#define elf_backend_want_plt_sym 1
906e58ca 18246#undef ELF_MAXPAGESIZE
00a97672 18247#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 18248
18249#include "elf32-target.h"
18250
18251
21d799b5
NC		 18252/* Merge backend specific data from an object file to the output
18253 object file when linking. */
18254
18255static bfd_boolean
18256elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
18257{
18258 flagword out_flags;
18259 flagword in_flags;
18260 bfd_boolean flags_compatible = TRUE;
18261 asection *sec;
18262
cc643b88 18263 /* Check if we have the same endianness. */
21d799b5
NC		 18264 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
18265 return FALSE;
18266
18267 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
18268 return TRUE;
18269
18270 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
18271 return FALSE;
18272
18273 /* The input BFD must have had its flags initialised. */
18274 /* The following seems bogus to me -- The flags are initialized in
18275 the assembler but I don't think an elf_flags_init field is
18276 written into the object. */
18277 /* BFD_ASSERT (elf_flags_init (ibfd)); */
18278
18279 in_flags = elf_elfheader (ibfd)->e_flags;
18280 out_flags = elf_elfheader (obfd)->e_flags;
18281
18282 /* In theory there is no reason why we couldn't handle this. However
18283 in practice it isn't even close to working and there is no real
18284 reason to want it. */
18285 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
18286 && !(ibfd->flags & DYNAMIC)
18287 && (in_flags & EF_ARM_BE8))
18288 {
18289 _bfd_error_handler (_("error: %B is already in final BE8 format"),
18290 ibfd);
18291 return FALSE;
18292 }
18293
18294 if (!elf_flags_init (obfd))
18295 {
18296 /* If the input is the default architecture and had the default
18297 flags then do not bother setting the flags for the output
18298 architecture, instead allow future merges to do this. If no
18299 future merges ever set these flags then they will retain their
99059e56
RM		 18300 uninitialised values, which surprise surprise, correspond
18301 to the default values. */
21d799b5
NC		 18302 if (bfd_get_arch_info (ibfd)->the_default
18303 && elf_elfheader (ibfd)->e_flags == 0)
18304 return TRUE;
18305
18306 elf_flags_init (obfd) = TRUE;
18307 elf_elfheader (obfd)->e_flags = in_flags;
18308
18309 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
18310 && bfd_get_arch_info (obfd)->the_default)
18311 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
18312
18313 return TRUE;
18314 }
18315
18316 /* Determine what should happen if the input ARM architecture
18317 does not match the output ARM architecture. */
18318 if (! bfd_arm_merge_machines (ibfd, obfd))
18319 return FALSE;
18320
18321 /* Identical flags must be compatible. */
18322 if (in_flags == out_flags)
18323 return TRUE;
18324
18325 /* Check to see if the input BFD actually contains any sections. If
18326 not, its flags may not have been initialised either, but it
18327 cannot actually cause any incompatiblity. Do not short-circuit
18328 dynamic objects; their section list may be emptied by
18329 elf_link_add_object_symbols.
18330
18331 Also check to see if there are no code sections in the input.
18332 In this case there is no need to check for code specific flags.
18333 XXX - do we need to worry about floating-point format compatability
18334 in data sections ? */
18335 if (!(ibfd->flags & DYNAMIC))
18336 {
18337 bfd_boolean null_input_bfd = TRUE;
18338 bfd_boolean only_data_sections = TRUE;
18339
18340 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
18341 {
18342 /* Ignore synthetic glue sections. */
18343 if (strcmp (sec->name, ".glue_7")
18344 && strcmp (sec->name, ".glue_7t"))
18345 {
18346 if ((bfd_get_section_flags (ibfd, sec)
18347 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
18348 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 18349 only_data_sections = FALSE;
21d799b5
NC		 18350
18351 null_input_bfd = FALSE;
18352 break;
18353 }
18354 }
18355
18356 if (null_input_bfd || only_data_sections)
18357 return TRUE;
18358 }
18359
18360 /* Complain about various flag mismatches. */
18361 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
18362 EF_ARM_EABI_VERSION (out_flags)))
18363 {
18364 _bfd_error_handler
18365 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
18366 ibfd, obfd,
18367 (in_flags & EF_ARM_EABIMASK) >> 24,
18368 (out_flags & EF_ARM_EABIMASK) >> 24);
18369 return FALSE;
18370 }
18371
18372 /* Not sure what needs to be checked for EABI versions >= 1. */
18373 /* VxWorks libraries do not use these flags. */
18374 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
18375 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
18376 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
18377 {
18378 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
18379 {
18380 _bfd_error_handler
18381 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
18382 ibfd, obfd,
18383 in_flags & EF_ARM_APCS_26 ? 26 : 32,
18384 out_flags & EF_ARM_APCS_26 ? 26 : 32);
18385 flags_compatible = FALSE;
18386 }
18387
18388 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
18389 {
18390 if (in_flags & EF_ARM_APCS_FLOAT)
18391 _bfd_error_handler
18392 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
18393 ibfd, obfd);
18394 else
18395 _bfd_error_handler
18396 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
18397 ibfd, obfd);
18398
18399 flags_compatible = FALSE;
18400 }
18401
18402 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
18403 {
18404 if (in_flags & EF_ARM_VFP_FLOAT)
18405 _bfd_error_handler
18406 (_("error: %B uses VFP instructions, whereas %B does not"),
18407 ibfd, obfd);
18408 else
18409 _bfd_error_handler
18410 (_("error: %B uses FPA instructions, whereas %B does not"),
18411 ibfd, obfd);
18412
18413 flags_compatible = FALSE;
18414 }
18415
18416 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
18417 {
18418 if (in_flags & EF_ARM_MAVERICK_FLOAT)
18419 _bfd_error_handler
18420 (_("error: %B uses Maverick instructions, whereas %B does not"),
18421 ibfd, obfd);
18422 else
18423 _bfd_error_handler
18424 (_("error: %B does not use Maverick instructions, whereas %B does"),
18425 ibfd, obfd);
18426
18427 flags_compatible = FALSE;
18428 }
18429
18430#ifdef EF_ARM_SOFT_FLOAT
18431 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
18432 {
18433 /* We can allow interworking between code that is VFP format
18434 layout, and uses either soft float or integer regs for
18435 passing floating point arguments and results. We already
18436 know that the APCS_FLOAT flags match; similarly for VFP
18437 flags. */
18438 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
18439 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
18440 {
18441 if (in_flags & EF_ARM_SOFT_FLOAT)
18442 _bfd_error_handler
18443 (_("error: %B uses software FP, whereas %B uses hardware FP"),
18444 ibfd, obfd);
18445 else
18446 _bfd_error_handler
18447 (_("error: %B uses hardware FP, whereas %B uses software FP"),
18448 ibfd, obfd);
18449
18450 flags_compatible = FALSE;
18451 }
18452 }
18453#endif
18454
18455 /* Interworking mismatch is only a warning. */
18456 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
18457 {
18458 if (in_flags & EF_ARM_INTERWORK)
18459 {
18460 _bfd_error_handler
18461 (_("Warning: %B supports interworking, whereas %B does not"),
18462 ibfd, obfd);
18463 }
18464 else
18465 {
18466 _bfd_error_handler
18467 (_("Warning: %B does not support interworking, whereas %B does"),
18468 ibfd, obfd);
18469 }
18470 }
18471 }
18472
18473 return flags_compatible;
18474}
18475
18476
906e58ca 18477/* Symbian OS Targets. */
7f266840 18478
906e58ca 18479#undef TARGET_LITTLE_SYM
6d00b590 18480#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 18481#undef TARGET_LITTLE_NAME
7f266840 18482#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 18483#undef TARGET_BIG_SYM
6d00b590 18484#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 18485#undef TARGET_BIG_NAME
7f266840
DJ		 18486#define TARGET_BIG_NAME "elf32-bigarm-symbian"
18487
18488/* Like elf32_arm_link_hash_table_create -- but overrides
18489 appropriately for Symbian OS. */
906e58ca 18490
7f266840
DJ		 18491static struct bfd_link_hash_table *
18492elf32_arm_symbian_link_hash_table_create (bfd *abfd)
18493{
18494 struct bfd_link_hash_table *ret;
18495
18496 ret = elf32_arm_link_hash_table_create (abfd);
18497 if (ret)
18498 {
18499 struct elf32_arm_link_hash_table *htab
18500 = (struct elf32_arm_link_hash_table *)ret;
18501 /* There is no PLT header for Symbian OS. */
18502 htab->plt_header_size = 0;
95720a86
DJ		 18503 /* The PLT entries are each one instruction and one word. */
18504 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 18505 htab->symbian_p = 1;
33bfe774
JB		 18506 /* Symbian uses armv5t or above, so use_blx is always true. */
18507 htab->use_blx = 1;
67687978 18508 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 18509 }
18510 return ret;
906e58ca 18511}
7f266840 18512
b35d266b 18513static const struct bfd_elf_special_section
551b43fd 18514elf32_arm_symbian_special_sections[] =
7f266840 18515{
5cd3778d
MM		 18516 /* In a BPABI executable, the dynamic linking sections do not go in
18517 the loadable read-only segment. The post-linker may wish to
18518 refer to these sections, but they are not part of the final
18519 program image. */
0112cd26
NC		 18520 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
18521 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
18522 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
18523 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
18524 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 18525 /* These sections do not need to be writable as the SymbianOS
18526 postlinker will arrange things so that no dynamic relocation is
18527 required. */
0112cd26
NC		 18528 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
18529 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
18530 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
18531 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 18532};
18533
c3c76620 18534static void
906e58ca 18535elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 18536 struct bfd_link_info *link_info)
c3c76620
MM		 18537{
18538 /* BPABI objects are never loaded directly by an OS kernel; they are
18539 processed by a postlinker first, into an OS-specific format. If
18540 the D_PAGED bit is set on the file, BFD will align segments on
18541 page boundaries, so that an OS can directly map the file. With
18542 BPABI objects, that just results in wasted space. In addition,
18543 because we clear the D_PAGED bit, map_sections_to_segments will
18544 recognize that the program headers should not be mapped into any
18545 loadable segment. */
18546 abfd->flags &= ~D_PAGED;
906e58ca 18547 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 18548}
7f266840
DJ		 18549
18550static bfd_boolean
906e58ca 18551elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 18552 struct bfd_link_info *info)
7f266840
DJ		 18553{
18554 struct elf_segment_map *m;
18555 asection *dynsec;
18556
7f266840
DJ		 18557 /* BPABI shared libraries and executables should have a PT_DYNAMIC
18558 segment. However, because the .dynamic section is not marked
18559 with SEC_LOAD, the generic ELF code will not create such a
18560 segment. */
18561 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
18562 if (dynsec)
18563 {
12bd6957 18564 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 18565 if (m->p_type == PT_DYNAMIC)
18566 break;
18567
18568 if (m == NULL)
18569 {
18570 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 18571 m->next = elf_seg_map (abfd);
18572 elf_seg_map (abfd) = m;
8ded5a0f 18573 }
7f266840
DJ		 18574 }
18575
b294bdf8
MM		 18576 /* Also call the generic arm routine. */
18577 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 18578}
18579
95720a86
DJ		 18580/* Return address for Ith PLT stub in section PLT, for relocation REL
18581 or (bfd_vma) -1 if it should not be included. */
18582
18583static bfd_vma
18584elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
18585 const arelent *rel ATTRIBUTE_UNUSED)
18586{
18587 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
18588}
18589
8029a119 18590#undef elf32_bed
7f266840
DJ		 18591#define elf32_bed elf32_arm_symbian_bed
18592
18593/* The dynamic sections are not allocated on SymbianOS; the postlinker
18594 will process them and then discard them. */
906e58ca 18595#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 18596#define ELF_DYNAMIC_SEC_FLAGS \
18597 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
18598
00a97672 18599#undef elf_backend_emit_relocs
c3c76620 18600
906e58ca
NC		 18601#undef bfd_elf32_bfd_link_hash_table_create
18602#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
18603#undef elf_backend_special_sections
18604#define elf_backend_special_sections elf32_arm_symbian_special_sections
18605#undef elf_backend_begin_write_processing
18606#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
18607#undef elf_backend_final_write_processing
18608#define elf_backend_final_write_processing elf32_arm_final_write_processing
18609
18610#undef elf_backend_modify_segment_map
7f266840
DJ		 18611#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
18612
18613/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 18614#undef elf_backend_got_header_size
7f266840
DJ		 18615#define elf_backend_got_header_size 0
18616
18617/* Similarly, there is no .got.plt section. */
906e58ca 18618#undef elf_backend_want_got_plt
7f266840
DJ		 18619#define elf_backend_want_got_plt 0
18620
906e58ca 18621#undef elf_backend_plt_sym_val
95720a86
DJ		 18622#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
18623
906e58ca 18624#undef elf_backend_may_use_rel_p
00a97672 18625#define elf_backend_may_use_rel_p 1
906e58ca 18626#undef elf_backend_may_use_rela_p
00a97672 18627#define elf_backend_may_use_rela_p 0
906e58ca 18628#undef elf_backend_default_use_rela_p
00a97672 18629#define elf_backend_default_use_rela_p 0
906e58ca 18630#undef elf_backend_want_plt_sym
00a97672 18631#define elf_backend_want_plt_sym 0
906e58ca 18632#undef ELF_MAXPAGESIZE
00a97672 18633#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 18634
7f266840 18635#include "elf32-target.h"
GDB Binutils - Deliverables
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