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[ARM] Add FDPIC relocations definitions
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
219d1afa 2 Copyright (C) 1998-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
f3185997 59#define elf_info_to_howto NULL
07d6d2b8 60#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
07d6d2b8 240 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
99059e56
RM		 334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
07d6d2b8 340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
99059e56
RM		 348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
07d6d2b8 354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
99059e56
RM		 362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
07d6d2b8 368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
99059e56
RM		 378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
07d6d2b8 384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
99059e56
RM		 392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
07d6d2b8 398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
99059e56
RM		 406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
07d6d2b8 412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
99059e56
RM		 420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
07d6d2b8 426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
99059e56
RM		 434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
07d6d2b8 440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
99059e56 446 TRUE, /* pc_relative */
07d6d2b8 447 0, /* bitpos */
99059e56
RM		 448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
99059e56 460 FALSE, /* pc_relative */
07d6d2b8 461 0, /* bitpos */
99059e56
RM		 462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
99059e56 474 TRUE, /* pc_relative */
07d6d2b8 475 0, /* bitpos */
99059e56
RM		 476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
07d6d2b8 909 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 917 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
07d6d2b8 937 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 945 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
07d6d2b8 951 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 959 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
07d6d2b8 965 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 973 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
07d6d2b8 979 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 987 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
07d6d2b8 993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1001 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
07d6d2b8 1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1015 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
07d6d2b8 1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1029 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
07d6d2b8 1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1043 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
07d6d2b8 1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1057 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
07d6d2b8 1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1071 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
07d6d2b8 1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1085 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
07d6d2b8 1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1099 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
07d6d2b8 1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1113 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
07d6d2b8 1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1127 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
07d6d2b8 1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1141 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
07d6d2b8 1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1155 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
07d6d2b8 1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1169 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
07d6d2b8 1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1183 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
07d6d2b8 1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1197 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
07d6d2b8 1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1211 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
07d6d2b8 1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1225 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
07d6d2b8 1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1239 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
07d6d2b8 1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1253 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
07d6d2b8 1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1267 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
07d6d2b8 1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1486
1487 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
99059e56 1494 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
99059e56 1509 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1510 NULL, /* special_function */
99059e56 1511 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
99059e56
RM		 1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
07d6d2b8 1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
99059e56
RM		 1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
07d6d2b8 1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
99059e56
RM		 1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
07d6d2b8 1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
99059e56
RM		 1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
07d6d2b8 1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
99059e56 1608 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
07d6d2b8 1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92 1748/* 160 onwards: */
188fd7ae 1749static reloc_howto_type elf32_arm_howto_table_2[5] =
34e77a92
RS		 1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
99059e56
RM		 1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
188fd7ae
CL		 1763 FALSE), /* pcrel_offset */
1764 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1765 0, /* rightshift */
1766 2, /* size (0 = byte, 1 = short, 2 = long) */
1767 32, /* bitsize */
1768 FALSE, /* pc_relative */
1769 0, /* bitpos */
1770 complain_overflow_bitfield,/* complain_on_overflow */
1771 bfd_elf_generic_reloc, /* special_function */
1772 "R_ARM_GOTFUNCDESC", /* name */
1773 FALSE, /* partial_inplace */
1774 0, /* src_mask */
1775 0xffffffff, /* dst_mask */
1776 FALSE), /* pcrel_offset */
1777 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1778 0, /* rightshift */
1779 2, /* size (0 = byte, 1 = short, 2 = long) */
1780 32, /* bitsize */
1781 FALSE, /* pc_relative */
1782 0, /* bitpos */
1783 complain_overflow_bitfield,/* complain_on_overflow */
1784 bfd_elf_generic_reloc, /* special_function */
1785 "R_ARM_GOTOFFFUNCDESC",/* name */
1786 FALSE, /* partial_inplace */
1787 0, /* src_mask */
1788 0xffffffff, /* dst_mask */
1789 FALSE), /* pcrel_offset */
1790 HOWTO (R_ARM_FUNCDESC, /* type */
1791 0, /* rightshift */
1792 2, /* size (0 = byte, 1 = short, 2 = long) */
1793 32, /* bitsize */
1794 FALSE, /* pc_relative */
1795 0, /* bitpos */
1796 complain_overflow_bitfield,/* complain_on_overflow */
1797 bfd_elf_generic_reloc, /* special_function */
1798 "R_ARM_FUNCDESC", /* name */
1799 FALSE, /* partial_inplace */
1800 0, /* src_mask */
1801 0xffffffff, /* dst_mask */
1802 FALSE), /* pcrel_offset */
1803 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1804 0, /* rightshift */
1805 2, /* size (0 = byte, 1 = short, 2 = long) */
1806 64, /* bitsize */
1807 FALSE, /* pc_relative */
1808 0, /* bitpos */
1809 complain_overflow_bitfield,/* complain_on_overflow */
1810 bfd_elf_generic_reloc, /* special_function */
1811 "R_ARM_FUNCDESC_VALUE",/* name */
1812 FALSE, /* partial_inplace */
1813 0, /* src_mask */
1814 0xffffffff, /* dst_mask */
1815 FALSE), /* pcrel_offset */
34e77a92 1816};
c19d1205 1817
34e77a92
RS		 1818/* 249-255 extended, currently unused, relocations: */
1819static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1820{
1821 HOWTO (R_ARM_RREL32, /* type */
1822 0, /* rightshift */
1823 0, /* size (0 = byte, 1 = short, 2 = long) */
1824 0, /* bitsize */
1825 FALSE, /* pc_relative */
1826 0, /* bitpos */
1827 complain_overflow_dont,/* complain_on_overflow */
1828 bfd_elf_generic_reloc, /* special_function */
1829 "R_ARM_RREL32", /* name */
1830 FALSE, /* partial_inplace */
1831 0, /* src_mask */
1832 0, /* dst_mask */
1833 FALSE), /* pcrel_offset */
1834
1835 HOWTO (R_ARM_RABS32, /* type */
1836 0, /* rightshift */
1837 0, /* size (0 = byte, 1 = short, 2 = long) */
1838 0, /* bitsize */
1839 FALSE, /* pc_relative */
1840 0, /* bitpos */
1841 complain_overflow_dont,/* complain_on_overflow */
1842 bfd_elf_generic_reloc, /* special_function */
1843 "R_ARM_RABS32", /* name */
1844 FALSE, /* partial_inplace */
1845 0, /* src_mask */
1846 0, /* dst_mask */
1847 FALSE), /* pcrel_offset */
1848
1849 HOWTO (R_ARM_RPC24, /* type */
1850 0, /* rightshift */
1851 0, /* size (0 = byte, 1 = short, 2 = long) */
1852 0, /* bitsize */
1853 FALSE, /* pc_relative */
1854 0, /* bitpos */
1855 complain_overflow_dont,/* complain_on_overflow */
1856 bfd_elf_generic_reloc, /* special_function */
1857 "R_ARM_RPC24", /* name */
1858 FALSE, /* partial_inplace */
1859 0, /* src_mask */
1860 0, /* dst_mask */
1861 FALSE), /* pcrel_offset */
1862
1863 HOWTO (R_ARM_RBASE, /* type */
1864 0, /* rightshift */
1865 0, /* size (0 = byte, 1 = short, 2 = long) */
1866 0, /* bitsize */
1867 FALSE, /* pc_relative */
1868 0, /* bitpos */
1869 complain_overflow_dont,/* complain_on_overflow */
1870 bfd_elf_generic_reloc, /* special_function */
1871 "R_ARM_RBASE", /* name */
1872 FALSE, /* partial_inplace */
1873 0, /* src_mask */
1874 0, /* dst_mask */
1875 FALSE) /* pcrel_offset */
1876};
1877
1878static reloc_howto_type *
1879elf32_arm_howto_from_type (unsigned int r_type)
1880{
906e58ca 1881 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1882 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1883
188fd7ae
CL		 1884 if (r_type >= R_ARM_IRELATIVE
1885 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1886 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1887
c19d1205 1888 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1889 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1890 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1891
c19d1205 1892 return NULL;
7f266840
DJ		 1893}
1894
f3185997
NC		 1895static bfd_boolean
1896elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1897 Elf_Internal_Rela * elf_reloc)
1898{
1899 unsigned int r_type;
1900
1901 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1902 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1903 {
1904 /* xgettext:c-format */
1905 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1906 abfd, r_type);
1907 bfd_set_error (bfd_error_bad_value);
1908 return FALSE;
1909 }
1910 return TRUE;
7f266840
DJ		 1911}
1912
1913struct elf32_arm_reloc_map
1914 {
1915 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1916 unsigned char elf_reloc_val;
7f266840
DJ		 1917 };
1918
1919/* All entries in this list must also be present in elf32_arm_howto_table. */
1920static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1921 {
07d6d2b8 1922 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 1923 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1924 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1925 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 1926 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1927 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1928 {BFD_RELOC_32, R_ARM_ABS32},
1929 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1930 {BFD_RELOC_8, R_ARM_ABS8},
1931 {BFD_RELOC_16, R_ARM_ABS16},
1932 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 1933 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1934 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1935 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1936 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1937 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1938 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1939 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 1940 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1941 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1942 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
1943 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
1944 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
1945 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
1946 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1947 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 1948 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1949 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1950 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1951 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 1952 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 1953 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1954 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1955 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 1956 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 1957 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 1958 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 1959 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1960 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1961 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1962 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1963 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1964 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 1965 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1966 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1967 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
1968 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 1969 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
1970 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
1971 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
1972 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
c19d1205
ZW		 1973 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1974 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1975 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1976 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1977 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1978 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1979 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1980 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1981 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1982 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1983 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1984 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1985 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1986 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1987 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1988 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1989 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1990 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1991 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1992 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1993 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1994 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1995 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1996 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1997 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1998 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1999 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2000 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2001 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2002 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2003 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2004 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2005 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2006 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2007 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2008 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2009 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2010 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2011 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2012 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2013 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2014 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
2015 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 2016 };
2017
2018static reloc_howto_type *
f1c71a59
ZW		 2019elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2020 bfd_reloc_code_real_type code)
7f266840
DJ		 2021{
2022 unsigned int i;
8029a119 2023
906e58ca 2024 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2025 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2026 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2027
c19d1205 2028 return NULL;
7f266840
DJ		 2029}
2030
157090f7
AM		 2031static reloc_howto_type *
2032elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2033 const char *r_name)
2034{
2035 unsigned int i;
2036
906e58ca 2037 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2038 if (elf32_arm_howto_table_1[i].name != NULL
2039 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2040 return &elf32_arm_howto_table_1[i];
2041
906e58ca 2042 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2043 if (elf32_arm_howto_table_2[i].name != NULL
2044 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2045 return &elf32_arm_howto_table_2[i];
2046
34e77a92
RS		 2047 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2048 if (elf32_arm_howto_table_3[i].name != NULL
2049 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2050 return &elf32_arm_howto_table_3[i];
2051
157090f7
AM		 2052 return NULL;
2053}
2054
906e58ca
NC		 2055/* Support for core dump NOTE sections. */
2056
7f266840 2057static bfd_boolean
f1c71a59 2058elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2059{
2060 int offset;
2061 size_t size;
2062
2063 switch (note->descsz)
2064 {
2065 default:
2066 return FALSE;
2067
8029a119 2068 case 148: /* Linux/ARM 32-bit. */
7f266840 2069 /* pr_cursig */
228e534f 2070 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2071
2072 /* pr_pid */
228e534f 2073 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2074
2075 /* pr_reg */
2076 offset = 72;
2077 size = 72;
2078
2079 break;
2080 }
2081
2082 /* Make a ".reg/999" section. */
2083 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2084 size, note->descpos + offset);
2085}
2086
2087static bfd_boolean
f1c71a59 2088elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2089{
2090 switch (note->descsz)
2091 {
2092 default:
2093 return FALSE;
2094
8029a119 2095 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2096 elf_tdata (abfd)->core->pid
4395ee08 2097 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2098 elf_tdata (abfd)->core->program
7f266840 2099 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2100 elf_tdata (abfd)->core->command
7f266840
DJ		 2101 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2102 }
2103
2104 /* Note that for some reason, a spurious space is tacked
2105 onto the end of the args in some (at least one anyway)
2106 implementations, so strip it off if it exists. */
7f266840 2107 {
228e534f 2108 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2109 int n = strlen (command);
2110
2111 if (0 < n && command[n - 1] == ' ')
2112 command[n - 1] = '\0';
2113 }
2114
2115 return TRUE;
2116}
2117
1f20dca5
UW		 2118static char *
2119elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2120 int note_type, ...)
2121{
2122 switch (note_type)
2123 {
2124 default:
2125 return NULL;
2126
2127 case NT_PRPSINFO:
2128 {
2129 char data[124];
2130 va_list ap;
2131
2132 va_start (ap, note_type);
2133 memset (data, 0, sizeof (data));
2134 strncpy (data + 28, va_arg (ap, const char *), 16);
2135 strncpy (data + 44, va_arg (ap, const char *), 80);
2136 va_end (ap);
2137
2138 return elfcore_write_note (abfd, buf, bufsiz,
2139 "CORE", note_type, data, sizeof (data));
2140 }
2141
2142 case NT_PRSTATUS:
2143 {
2144 char data[148];
2145 va_list ap;
2146 long pid;
2147 int cursig;
2148 const void *greg;
2149
2150 va_start (ap, note_type);
2151 memset (data, 0, sizeof (data));
2152 pid = va_arg (ap, long);
2153 bfd_put_32 (abfd, pid, data + 24);
2154 cursig = va_arg (ap, int);
2155 bfd_put_16 (abfd, cursig, data + 12);
2156 greg = va_arg (ap, const void *);
2157 memcpy (data + 72, greg, 72);
2158 va_end (ap);
2159
2160 return elfcore_write_note (abfd, buf, bufsiz,
2161 "CORE", note_type, data, sizeof (data));
2162 }
2163 }
2164}
2165
07d6d2b8
AM		 2166#define TARGET_LITTLE_SYM arm_elf32_le_vec
2167#define TARGET_LITTLE_NAME "elf32-littlearm"
2168#define TARGET_BIG_SYM arm_elf32_be_vec
2169#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2170
2171#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2172#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2173#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2174
252b5132
RH		 2175typedef unsigned long int insn32;
2176typedef unsigned short int insn16;
2177
3a4a14e9
PB		 2178/* In lieu of proper flags, assume all EABIv4 or later objects are
2179 interworkable. */
57e8b36a 2180#define INTERWORK_FLAG(abfd) \
3a4a14e9 2181 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2182 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2183 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2184
252b5132
RH		 2185/* The linker script knows the section names for placement.
2186 The entry_names are used to do simple name mangling on the stubs.
2187 Given a function name, and its type, the stub can be found. The
9b485d32 2188 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2189#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2190#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2191
2192#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2193#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2194
c7b8f16e
JB		 2195#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2196#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2197
a504d23a
LA		 2198#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2199#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2200
845b51d6
PB		 2201#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2202#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2203
7413f23f
DJ		 2204#define STUB_ENTRY_NAME "__%s_veneer"
2205
4ba2ef8f
TP		 2206#define CMSE_PREFIX "__acle_se_"
2207
252b5132
RH		 2208/* The name of the dynamic interpreter. This is put in the .interp
2209 section. */
2210#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2211
0855e32b 2212static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2213{
2214 0xe08e0000, /* add r0, lr, r0 */
2215 0xe5901004, /* ldr r1, [r0,#4] */
2216 0xe12fff11, /* bx r1 */
2217};
0855e32b
NS		 2218
2219static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2220{
2221 0xe52d2004, /* push {r2} */
2222 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2223 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2224 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2225 0xe081100f, /* 2: add r1, pc */
2226 0xe12fff12, /* bx r2 */
2227 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2228 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2229 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2230};
0855e32b 2231
5e681ec4
PB		 2232#ifdef FOUR_WORD_PLT
2233
252b5132
RH		 2234/* The first entry in a procedure linkage table looks like
2235 this. It is set up so that any shared library function that is
59f2c4e7 2236 called before the relocation has been set up calls the dynamic
9b485d32 2237 linker first. */
e5a52504 2238static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2239{
2240 0xe52de004, /* str lr, [sp, #-4]! */
2241 0xe59fe010, /* ldr lr, [pc, #16] */
2242 0xe08fe00e, /* add lr, pc, lr */
2243 0xe5bef008, /* ldr pc, [lr, #8]! */
2244};
5e681ec4
PB		 2245
2246/* Subsequent entries in a procedure linkage table look like
2247 this. */
e5a52504 2248static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2249{
2250 0xe28fc600, /* add ip, pc, #NN */
2251 0xe28cca00, /* add ip, ip, #NN */
2252 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2253 0x00000000, /* unused */
2254};
5e681ec4 2255
eed94f8f 2256#else /* not FOUR_WORD_PLT */
5e681ec4 2257
5e681ec4
PB		 2258/* The first entry in a procedure linkage table looks like
2259 this. It is set up so that any shared library function that is
2260 called before the relocation has been set up calls the dynamic
2261 linker first. */
e5a52504 2262static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2263{
07d6d2b8
AM		 2264 0xe52de004, /* str lr, [sp, #-4]! */
2265 0xe59fe004, /* ldr lr, [pc, #4] */
2266 0xe08fe00e, /* add lr, pc, lr */
2267 0xe5bef008, /* ldr pc, [lr, #8]! */
2268 0x00000000, /* &GOT[0] - . */
b38cadfb 2269};
252b5132 2270
1db37fe6
YG		 2271/* By default subsequent entries in a procedure linkage table look like
2272 this. Offsets that don't fit into 28 bits will cause link error. */
2273static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2274{
2275 0xe28fc600, /* add ip, pc, #0xNN00000 */
2276 0xe28cca00, /* add ip, ip, #0xNN000 */
2277 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2278};
5e681ec4 2279
1db37fe6
YG		 2280/* When explicitly asked, we'll use this "long" entry format
2281 which can cope with arbitrary displacements. */
2282static const bfd_vma elf32_arm_plt_entry_long [] =
2283{
07d6d2b8
AM		 2284 0xe28fc200, /* add ip, pc, #0xN0000000 */
2285 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2286 0xe28cca00, /* add ip, ip, #0xNN000 */
2287 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2288};
2289
2290static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2291
eed94f8f
NC		 2292#endif /* not FOUR_WORD_PLT */
2293
2294/* The first entry in a procedure linkage table looks like this.
2295 It is set up so that any shared library function that is called before the
2296 relocation has been set up calls the dynamic linker first. */
2297static const bfd_vma elf32_thumb2_plt0_entry [] =
2298{
2299 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2300 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2301 0xf8dfb500, /* push {lr} */
2302 0x44fee008, /* ldr.w lr, [pc, #8] */
2303 /* add lr, pc */
eed94f8f 2304 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2305 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2306};
2307
2308/* Subsequent entries in a procedure linkage table for thumb only target
2309 look like this. */
2310static const bfd_vma elf32_thumb2_plt_entry [] =
2311{
2312 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2313 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2314 0x0c00f240, /* movw ip, #0xNNNN */
2315 0x0c00f2c0, /* movt ip, #0xNNNN */
2316 0xf8dc44fc, /* add ip, pc */
2317 0xbf00f000 /* ldr.w pc, [ip] */
2318 /* nop */
eed94f8f 2319};
252b5132 2320
00a97672
RS		 2321/* The format of the first entry in the procedure linkage table
2322 for a VxWorks executable. */
2323static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2324{
07d6d2b8
AM		 2325 0xe52dc008, /* str ip,[sp,#-8]! */
2326 0xe59fc000, /* ldr ip,[pc] */
2327 0xe59cf008, /* ldr pc,[ip,#8] */
2328 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2329};
00a97672
RS		 2330
2331/* The format of subsequent entries in a VxWorks executable. */
2332static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2333{
07d6d2b8
AM		 2334 0xe59fc000, /* ldr ip,[pc] */
2335 0xe59cf000, /* ldr pc,[ip] */
2336 0x00000000, /* .long @got */
2337 0xe59fc000, /* ldr ip,[pc] */
2338 0xea000000, /* b _PLT */
2339 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2340};
00a97672
RS		 2341
2342/* The format of entries in a VxWorks shared library. */
2343static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2344{
07d6d2b8
AM		 2345 0xe59fc000, /* ldr ip,[pc] */
2346 0xe79cf009, /* ldr pc,[ip,r9] */
2347 0x00000000, /* .long @got */
2348 0xe59fc000, /* ldr ip,[pc] */
2349 0xe599f008, /* ldr pc,[r9,#8] */
2350 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2351};
00a97672 2352
b7693d02
DJ		 2353/* An initial stub used if the PLT entry is referenced from Thumb code. */
2354#define PLT_THUMB_STUB_SIZE 4
2355static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2356{
2357 0x4778, /* bx pc */
2358 0x46c0 /* nop */
2359};
b7693d02 2360
e5a52504
MM		 2361/* The entries in a PLT when using a DLL-based target with multiple
2362 address spaces. */
906e58ca 2363static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2364{
07d6d2b8
AM		 2365 0xe51ff004, /* ldr pc, [pc, #-4] */
2366 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2367};
2368
2369/* The first entry in a procedure linkage table looks like
2370 this. It is set up so that any shared library function that is
2371 called before the relocation has been set up calls the dynamic
2372 linker first. */
2373static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2374{
2375 /* First bundle: */
2376 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2377 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2378 0xe08cc00f, /* add ip, ip, pc */
2379 0xe52dc008, /* str ip, [sp, #-8]! */
2380 /* Second bundle: */
edccdf7c
RM		 2381 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2382 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2383 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2384 0xe12fff1c, /* bx ip */
b38cadfb 2385 /* Third bundle: */
edccdf7c
RM		 2386 0xe320f000, /* nop */
2387 0xe320f000, /* nop */
2388 0xe320f000, /* nop */
b38cadfb
NC		 2389 /* .Lplt_tail: */
2390 0xe50dc004, /* str ip, [sp, #-4] */
2391 /* Fourth bundle: */
edccdf7c
RM		 2392 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2393 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2394 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2395 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2396};
2397#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2398
2399/* Subsequent entries in a procedure linkage table look like this. */
2400static const bfd_vma elf32_arm_nacl_plt_entry [] =
2401{
2402 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2403 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2404 0xe08cc00f, /* add ip, ip, pc */
2405 0xea000000, /* b .Lplt_tail */
2406};
e5a52504 2407
906e58ca
NC		 2408#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2409#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2410#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2411#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2412#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2413#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2414#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2415#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2416
461a49ca 2417enum stub_insn_type
b38cadfb
NC		 2418{
2419 THUMB16_TYPE = 1,
2420 THUMB32_TYPE,
2421 ARM_TYPE,
2422 DATA_TYPE
2423};
461a49ca 2424
48229727
JB		 2425#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2426/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2427 is inserted in arm_build_one_stub(). */
2428#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2429#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2430#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2431#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2432#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2433#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2434#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2435#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2436
2437typedef struct
2438{
07d6d2b8 2439 bfd_vma data;
b38cadfb 2440 enum stub_insn_type type;
07d6d2b8
AM		 2441 unsigned int r_type;
2442 int reloc_addend;
461a49ca
DJ		 2443} insn_sequence;
2444
fea2b4d6
CL		 2445/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2446 to reach the stub if necessary. */
461a49ca 2447static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2448{
07d6d2b8 2449 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2450 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2451};
906e58ca 2452
fea2b4d6
CL		 2453/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2454 available. */
461a49ca 2455static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2456{
07d6d2b8
AM		 2457 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2458 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2459 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2460};
906e58ca 2461
d3626fb0 2462/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2463static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2464{
07d6d2b8
AM		 2465 THUMB16_INSN (0xb401), /* push {r0} */
2466 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2467 THUMB16_INSN (0x4684), /* mov ip, r0 */
2468 THUMB16_INSN (0xbc01), /* pop {r0} */
2469 THUMB16_INSN (0x4760), /* bx ip */
2470 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2471 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2472};
906e58ca 2473
80c135e5
TP		 2474/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2475static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2476{
07d6d2b8 2477 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2478 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2479};
2480
d5a67c02
AV		 2481/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2482 M-profile architectures. */
2483static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2484{
2485 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2486 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2487 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2488};
2489
d3626fb0
CL		 2490/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2491 allowed. */
2492static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2493{
07d6d2b8
AM		 2494 THUMB16_INSN (0x4778), /* bx pc */
2495 THUMB16_INSN (0x46c0), /* nop */
2496 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2497 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2498 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2499};
d3626fb0 2500
fea2b4d6
CL		 2501/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2502 available. */
461a49ca 2503static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2504{
07d6d2b8
AM		 2505 THUMB16_INSN (0x4778), /* bx pc */
2506 THUMB16_INSN (0x46c0), /* nop */
2507 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2508 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2509};
906e58ca 2510
fea2b4d6
CL		 2511/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2512 one, when the destination is close enough. */
461a49ca 2513static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2514{
07d6d2b8
AM		 2515 THUMB16_INSN (0x4778), /* bx pc */
2516 THUMB16_INSN (0x46c0), /* nop */
b38cadfb
NC		 2517 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2518};
c820be07 2519
cf3eccff 2520/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2521 blx to reach the stub if necessary. */
cf3eccff 2522static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2523{
07d6d2b8
AM		 2524 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2525 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2527};
906e58ca 2528
cf3eccff
DJ		 2529/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2530 blx to reach the stub if necessary. We can not add into pc;
2531 it is not guaranteed to mode switch (different in ARMv6 and
2532 ARMv7). */
2533static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2534{
07d6d2b8
AM		 2535 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2536 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2537 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2538 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2539};
cf3eccff 2540
ebe24dd4
CL		 2541/* V4T ARM -> ARM long branch stub, PIC. */
2542static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2543{
07d6d2b8
AM		 2544 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2545 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2546 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2547 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2548};
ebe24dd4
CL		 2549
2550/* V4T Thumb -> ARM long branch stub, PIC. */
2551static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2552{
07d6d2b8
AM		 2553 THUMB16_INSN (0x4778), /* bx pc */
2554 THUMB16_INSN (0x46c0), /* nop */
2555 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2556 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2557 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2558};
ebe24dd4 2559
d3626fb0
CL		 2560/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2561 architectures. */
ebe24dd4 2562static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2563{
07d6d2b8
AM		 2564 THUMB16_INSN (0xb401), /* push {r0} */
2565 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2566 THUMB16_INSN (0x46fc), /* mov ip, pc */
2567 THUMB16_INSN (0x4484), /* add ip, r0 */
2568 THUMB16_INSN (0xbc01), /* pop {r0} */
2569 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2570 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2571};
ebe24dd4 2572
d3626fb0
CL		 2573/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2574 allowed. */
2575static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2576{
07d6d2b8
AM		 2577 THUMB16_INSN (0x4778), /* bx pc */
2578 THUMB16_INSN (0x46c0), /* nop */
2579 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2580 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2581 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2582 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2583};
d3626fb0 2584
0855e32b
NS		 2585/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2586 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2587static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2588{
07d6d2b8
AM		 2589 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2590 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2591 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2592};
2593
2594/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2595 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2596static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2597{
07d6d2b8
AM		 2598 THUMB16_INSN (0x4778), /* bx pc */
2599 THUMB16_INSN (0x46c0), /* nop */
2600 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2601 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2602 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2603};
2604
7a89b94e
NC		 2605/* NaCl ARM -> ARM long branch stub. */
2606static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2607{
2608 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2609 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2610 ARM_INSN (0xe12fff1c), /* bx ip */
2611 ARM_INSN (0xe320f000), /* nop */
2612 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2613 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2614 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2615 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2616};
2617
2618/* NaCl ARM -> ARM long branch stub, PIC. */
2619static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2620{
2621 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2622 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2623 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2624 ARM_INSN (0xe12fff1c), /* bx ip */
2625 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2626 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2627 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2628 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2629};
2630
4ba2ef8f
TP		 2631/* Stub used for transition to secure state (aka SG veneer). */
2632static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2633{
2634 THUMB32_INSN (0xe97fe97f), /* sg. */
2635 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2636};
2637
7a89b94e 2638
48229727
JB		 2639/* Cortex-A8 erratum-workaround stubs. */
2640
2641/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2642 can't use a conditional branch to reach this stub). */
2643
2644static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2645{
07d6d2b8 2646 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2647 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2648 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2649};
48229727
JB		 2650
2651/* Stub used for b.w and bl.w instructions. */
2652
2653static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2654{
2655 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2656};
48229727
JB		 2657
2658static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2659{
2660 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2661};
48229727
JB		 2662
2663/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2664 instruction (which switches to ARM mode) to point to this stub. Jump to the
2665 real destination using an ARM-mode branch. */
2666
2667static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2668{
2669 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2670};
48229727 2671
9553db3c
NC		 2672/* For each section group there can be a specially created linker section
2673 to hold the stubs for that group. The name of the stub section is based
2674 upon the name of another section within that group with the suffix below
2675 applied.
2676
2677 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2678 create what appeared to be a linker stub section when it actually
2679 contained user code/data. For example, consider this fragment:
b38cadfb 2680
9553db3c
NC		 2681 const char * stubborn_problems[] = { "np" };
2682
2683 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2684 section called:
2685
2686 .data.rel.local.stubborn_problems
2687
2688 This then causes problems in arm32_arm_build_stubs() as it triggers:
2689
2690 // Ignore non-stub sections.
2691 if (!strstr (stub_sec->name, STUB_SUFFIX))
2692 continue;
2693
2694 And so the section would be ignored instead of being processed. Hence
2695 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2696 C identifier. */
2697#define STUB_SUFFIX ".__stub"
906e58ca 2698
738a79f6
CL		 2699/* One entry per long/short branch stub defined above. */
2700#define DEF_STUBS \
2701 DEF_STUB(long_branch_any_any) \
2702 DEF_STUB(long_branch_v4t_arm_thumb) \
2703 DEF_STUB(long_branch_thumb_only) \
2704 DEF_STUB(long_branch_v4t_thumb_thumb) \
2705 DEF_STUB(long_branch_v4t_thumb_arm) \
2706 DEF_STUB(short_branch_v4t_thumb_arm) \
2707 DEF_STUB(long_branch_any_arm_pic) \
2708 DEF_STUB(long_branch_any_thumb_pic) \
2709 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2710 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2711 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2712 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2713 DEF_STUB(long_branch_any_tls_pic) \
2714 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2715 DEF_STUB(long_branch_arm_nacl) \
2716 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2717 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2718 DEF_STUB(a8_veneer_b_cond) \
2719 DEF_STUB(a8_veneer_b) \
2720 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2721 DEF_STUB(a8_veneer_blx) \
2722 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2723 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2724
2725#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2726enum elf32_arm_stub_type
2727{
906e58ca 2728 arm_stub_none,
738a79f6 2729 DEF_STUBS
4f4faa4d 2730 max_stub_type
738a79f6
CL		 2731};
2732#undef DEF_STUB
2733
8d9d9490
TP		 2734/* Note the first a8_veneer type. */
2735const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2736
738a79f6
CL		 2737typedef struct
2738{
d3ce72d0 2739 const insn_sequence* template_sequence;
738a79f6
CL		 2740 int template_size;
2741} stub_def;
2742
2743#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2744static const stub_def stub_definitions[] =
2745{
738a79f6
CL		 2746 {NULL, 0},
2747 DEF_STUBS
906e58ca
NC		 2748};
2749
2750struct elf32_arm_stub_hash_entry
2751{
2752 /* Base hash table entry structure. */
2753 struct bfd_hash_entry root;
2754
2755 /* The stub section. */
2756 asection *stub_sec;
2757
2758 /* Offset within stub_sec of the beginning of this stub. */
2759 bfd_vma stub_offset;
2760
2761 /* Given the symbol's value and its section we can determine its final
2762 value when building the stubs (so the stub knows where to jump). */
2763 bfd_vma target_value;
2764 asection *target_section;
2765
8d9d9490
TP		 2766 /* Same as above but for the source of the branch to the stub. Used for
2767 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2768 such, source section does not need to be recorded since Cortex-A8 erratum
2769 workaround stubs are only generated when both source and target are in the
2770 same section. */
2771 bfd_vma source_value;
48229727
JB		 2772
2773 /* The instruction which caused this stub to be generated (only valid for
2774 Cortex-A8 erratum workaround stubs at present). */
2775 unsigned long orig_insn;
2776
461a49ca 2777 /* The stub type. */
906e58ca 2778 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2779 /* Its encoding size in bytes. */
2780 int stub_size;
2781 /* Its template. */
2782 const insn_sequence *stub_template;
2783 /* The size of the template (number of entries). */
2784 int stub_template_size;
906e58ca
NC		 2785
2786 /* The symbol table entry, if any, that this was derived from. */
2787 struct elf32_arm_link_hash_entry *h;
2788
35fc36a8
RS		 2789 /* Type of branch. */
2790 enum arm_st_branch_type branch_type;
906e58ca
NC		 2791
2792 /* Where this stub is being called from, or, in the case of combined
2793 stub sections, the first input section in the group. */
2794 asection *id_sec;
7413f23f
DJ		 2795
2796 /* The name for the local symbol at the start of this stub. The
2797 stub name in the hash table has to be unique; this does not, so
2798 it can be friendlier. */
2799 char *output_name;
906e58ca
NC		 2800};
2801
e489d0ae
PB		 2802/* Used to build a map of a section. This is required for mixed-endian
2803 code/data. */
2804
2805typedef struct elf32_elf_section_map
2806{
2807 bfd_vma vma;
2808 char type;
2809}
2810elf32_arm_section_map;
2811
c7b8f16e
JB		 2812/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2813
2814typedef enum
2815{
2816 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2817 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2818 VFP11_ERRATUM_ARM_VENEER,
2819 VFP11_ERRATUM_THUMB_VENEER
2820}
2821elf32_vfp11_erratum_type;
2822
2823typedef struct elf32_vfp11_erratum_list
2824{
2825 struct elf32_vfp11_erratum_list *next;
2826 bfd_vma vma;
2827 union
2828 {
2829 struct
2830 {
2831 struct elf32_vfp11_erratum_list *veneer;
2832 unsigned int vfp_insn;
2833 } b;
2834 struct
2835 {
2836 struct elf32_vfp11_erratum_list *branch;
2837 unsigned int id;
2838 } v;
2839 } u;
2840 elf32_vfp11_erratum_type type;
2841}
2842elf32_vfp11_erratum_list;
2843
a504d23a
LA		 2844/* Information about a STM32L4XX erratum veneer, or a branch to such a
2845 veneer. */
2846typedef enum
2847{
2848 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2849 STM32L4XX_ERRATUM_VENEER
2850}
2851elf32_stm32l4xx_erratum_type;
2852
2853typedef struct elf32_stm32l4xx_erratum_list
2854{
2855 struct elf32_stm32l4xx_erratum_list *next;
2856 bfd_vma vma;
2857 union
2858 {
2859 struct
2860 {
2861 struct elf32_stm32l4xx_erratum_list *veneer;
2862 unsigned int insn;
2863 } b;
2864 struct
2865 {
2866 struct elf32_stm32l4xx_erratum_list *branch;
2867 unsigned int id;
2868 } v;
2869 } u;
2870 elf32_stm32l4xx_erratum_type type;
2871}
2872elf32_stm32l4xx_erratum_list;
2873
2468f9c9
PB		 2874typedef enum
2875{
2876 DELETE_EXIDX_ENTRY,
2877 INSERT_EXIDX_CANTUNWIND_AT_END
2878}
2879arm_unwind_edit_type;
2880
2881/* A (sorted) list of edits to apply to an unwind table. */
2882typedef struct arm_unwind_table_edit
2883{
2884 arm_unwind_edit_type type;
2885 /* Note: we sometimes want to insert an unwind entry corresponding to a
2886 section different from the one we're currently writing out, so record the
2887 (text) section this edit relates to here. */
2888 asection *linked_section;
2889 unsigned int index;
2890 struct arm_unwind_table_edit *next;
2891}
2892arm_unwind_table_edit;
2893
8e3de13a 2894typedef struct _arm_elf_section_data
e489d0ae 2895{
2468f9c9 2896 /* Information about mapping symbols. */
e489d0ae 2897 struct bfd_elf_section_data elf;
8e3de13a 2898 unsigned int mapcount;
c7b8f16e 2899 unsigned int mapsize;
e489d0ae 2900 elf32_arm_section_map *map;
2468f9c9 2901 /* Information about CPU errata. */
c7b8f16e
JB		 2902 unsigned int erratumcount;
2903 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2904 unsigned int stm32l4xx_erratumcount;
2905 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2906 unsigned int additional_reloc_count;
2468f9c9
PB		 2907 /* Information about unwind tables. */
2908 union
2909 {
2910 /* Unwind info attached to a text section. */
2911 struct
2912 {
2913 asection *arm_exidx_sec;
2914 } text;
2915
2916 /* Unwind info attached to an .ARM.exidx section. */
2917 struct
2918 {
2919 arm_unwind_table_edit *unwind_edit_list;
2920 arm_unwind_table_edit *unwind_edit_tail;
2921 } exidx;
2922 } u;
8e3de13a
NC		 2923}
2924_arm_elf_section_data;
e489d0ae
PB		 2925
2926#define elf32_arm_section_data(sec) \
8e3de13a 2927 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2928
48229727
JB		 2929/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2930 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2931 so may be created multiple times: we use an array of these entries whilst
2932 relaxing which we can refresh easily, then create stubs for each potentially
2933 erratum-triggering instruction once we've settled on a solution. */
2934
b38cadfb
NC		 2935struct a8_erratum_fix
2936{
48229727
JB		 2937 bfd *input_bfd;
2938 asection *section;
2939 bfd_vma offset;
8d9d9490 2940 bfd_vma target_offset;
48229727
JB		 2941 unsigned long orig_insn;
2942 char *stub_name;
2943 enum elf32_arm_stub_type stub_type;
35fc36a8 2944 enum arm_st_branch_type branch_type;
48229727
JB		 2945};
2946
2947/* A table of relocs applied to branches which might trigger Cortex-A8
2948 erratum. */
2949
b38cadfb
NC		 2950struct a8_erratum_reloc
2951{
48229727
JB		 2952 bfd_vma from;
2953 bfd_vma destination;
92750f34
DJ		 2954 struct elf32_arm_link_hash_entry *hash;
2955 const char *sym_name;
48229727 2956 unsigned int r_type;
35fc36a8 2957 enum arm_st_branch_type branch_type;
48229727
JB		 2958 bfd_boolean non_a8_stub;
2959};
2960
ba93b8ac
DJ		 2961/* The size of the thread control block. */
2962#define TCB_SIZE 8
2963
34e77a92
RS		 2964/* ARM-specific information about a PLT entry, over and above the usual
2965 gotplt_union. */
b38cadfb
NC		 2966struct arm_plt_info
2967{
34e77a92
RS		 2968 /* We reference count Thumb references to a PLT entry separately,
2969 so that we can emit the Thumb trampoline only if needed. */
2970 bfd_signed_vma thumb_refcount;
2971
2972 /* Some references from Thumb code may be eliminated by BL->BLX
2973 conversion, so record them separately. */
2974 bfd_signed_vma maybe_thumb_refcount;
2975
2976 /* How many of the recorded PLT accesses were from non-call relocations.
2977 This information is useful when deciding whether anything takes the
2978 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2979 non-call references to the function should resolve directly to the
2980 real runtime target. */
2981 unsigned int noncall_refcount;
2982
2983 /* Since PLT entries have variable size if the Thumb prologue is
2984 used, we need to record the index into .got.plt instead of
2985 recomputing it from the PLT offset. */
2986 bfd_signed_vma got_offset;
2987};
2988
2989/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2990struct arm_local_iplt_info
2991{
34e77a92
RS		 2992 /* The information that is usually found in the generic ELF part of
2993 the hash table entry. */
2994 union gotplt_union root;
2995
2996 /* The information that is usually found in the ARM-specific part of
2997 the hash table entry. */
2998 struct arm_plt_info arm;
2999
3000 /* A list of all potential dynamic relocations against this symbol. */
3001 struct elf_dyn_relocs *dyn_relocs;
3002};
3003
0ffa91dd 3004struct elf_arm_obj_tdata
ba93b8ac
DJ		 3005{
3006 struct elf_obj_tdata root;
3007
3008 /* tls_type for each local got entry. */
3009 char *local_got_tls_type;
ee065d83 3010
0855e32b
NS		 3011 /* GOTPLT entries for TLS descriptors. */
3012 bfd_vma *local_tlsdesc_gotent;
3013
34e77a92
RS		 3014 /* Information for local symbols that need entries in .iplt. */
3015 struct arm_local_iplt_info **local_iplt;
3016
bf21ed78
MS		 3017 /* Zero to warn when linking objects with incompatible enum sizes. */
3018 int no_enum_size_warning;
a9dc9481
JM		 3019
3020 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3021 int no_wchar_size_warning;
ba93b8ac
DJ		 3022};
3023
0ffa91dd
NC		 3024#define elf_arm_tdata(bfd) \
3025 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3026
0ffa91dd
NC		 3027#define elf32_arm_local_got_tls_type(bfd) \
3028 (elf_arm_tdata (bfd)->local_got_tls_type)
3029
0855e32b
NS		 3030#define elf32_arm_local_tlsdesc_gotent(bfd) \
3031 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3032
34e77a92
RS		 3033#define elf32_arm_local_iplt(bfd) \
3034 (elf_arm_tdata (bfd)->local_iplt)
3035
0ffa91dd
NC		 3036#define is_arm_elf(bfd) \
3037 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3038 && elf_tdata (bfd) != NULL \
4dfe6ac6 3039 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3040
3041static bfd_boolean
3042elf32_arm_mkobject (bfd *abfd)
3043{
0ffa91dd 3044 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3045 ARM_ELF_DATA);
ba93b8ac
DJ		 3046}
3047
ba93b8ac
DJ		 3048#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3049
ba96a88f 3050/* Arm ELF linker hash entry. */
252b5132 3051struct elf32_arm_link_hash_entry
b38cadfb
NC		 3052{
3053 struct elf_link_hash_entry root;
252b5132 3054
b38cadfb
NC		 3055 /* Track dynamic relocs copied for this symbol. */
3056 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3057
b38cadfb
NC		 3058 /* ARM-specific PLT information. */
3059 struct arm_plt_info plt;
ba93b8ac
DJ		 3060
3061#define GOT_UNKNOWN 0
3062#define GOT_NORMAL 1
3063#define GOT_TLS_GD 2
3064#define GOT_TLS_IE 4
0855e32b
NS		 3065#define GOT_TLS_GDESC 8
3066#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3067 unsigned int tls_type : 8;
34e77a92 3068
b38cadfb
NC		 3069 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3070 unsigned int is_iplt : 1;
34e77a92 3071
b38cadfb 3072 unsigned int unused : 23;
a4fd1a8e 3073
b38cadfb
NC		 3074 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3075 starting at the end of the jump table. */
3076 bfd_vma tlsdesc_got;
0855e32b 3077
b38cadfb
NC		 3078 /* The symbol marking the real symbol location for exported thumb
3079 symbols with Arm stubs. */
3080 struct elf_link_hash_entry *export_glue;
906e58ca 3081
b38cadfb 3082 /* A pointer to the most recently used stub hash entry against this
8029a119 3083 symbol. */
b38cadfb
NC		 3084 struct elf32_arm_stub_hash_entry *stub_cache;
3085};
252b5132 3086
252b5132 3087/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3088#define elf32_arm_link_hash_traverse(table, func, info) \
3089 (elf_link_hash_traverse \
3090 (&(table)->root, \
b7693d02 3091 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3092 (info)))
3093
3094/* Get the ARM elf linker hash table from a link_info structure. */
3095#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3096 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3097 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3098
906e58ca
NC		 3099#define arm_stub_hash_lookup(table, string, create, copy) \
3100 ((struct elf32_arm_stub_hash_entry *) \
3101 bfd_hash_lookup ((table), (string), (create), (copy)))
3102
21d799b5
NC		 3103/* Array to keep track of which stub sections have been created, and
3104 information on stub grouping. */
3105struct map_stub
3106{
3107 /* This is the section to which stubs in the group will be
3108 attached. */
3109 asection *link_sec;
3110 /* The stub section. */
3111 asection *stub_sec;
3112};
3113
0855e32b
NS		 3114#define elf32_arm_compute_jump_table_size(htab) \
3115 ((htab)->next_tls_desc_index * 4)
3116
9b485d32 3117/* ARM ELF linker hash table. */
252b5132 3118struct elf32_arm_link_hash_table
906e58ca
NC		 3119{
3120 /* The main hash table. */
3121 struct elf_link_hash_table root;
252b5132 3122
906e58ca
NC		 3123 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3124 bfd_size_type thumb_glue_size;
252b5132 3125
906e58ca
NC		 3126 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3127 bfd_size_type arm_glue_size;
252b5132 3128
906e58ca
NC		 3129 /* The size in bytes of section containing the ARMv4 BX veneers. */
3130 bfd_size_type bx_glue_size;
845b51d6 3131
906e58ca
NC		 3132 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3133 veneer has been populated. */
3134 bfd_vma bx_glue_offset[15];
845b51d6 3135
906e58ca
NC		 3136 /* The size in bytes of the section containing glue for VFP11 erratum
3137 veneers. */
3138 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3139
a504d23a
LA		 3140 /* The size in bytes of the section containing glue for STM32L4XX erratum
3141 veneers. */
3142 bfd_size_type stm32l4xx_erratum_glue_size;
3143
48229727
JB		 3144 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3145 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3146 elf32_arm_write_section(). */
3147 struct a8_erratum_fix *a8_erratum_fixes;
3148 unsigned int num_a8_erratum_fixes;
3149
906e58ca
NC		 3150 /* An arbitrary input BFD chosen to hold the glue sections. */
3151 bfd * bfd_of_glue_owner;
ba96a88f 3152
906e58ca
NC		 3153 /* Nonzero to output a BE8 image. */
3154 int byteswap_code;
e489d0ae 3155
906e58ca
NC		 3156 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3157 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3158 int target1_is_rel;
9c504268 3159
906e58ca
NC		 3160 /* The relocation to use for R_ARM_TARGET2 relocations. */
3161 int target2_reloc;
eb043451 3162
906e58ca
NC		 3163 /* 0 = Ignore R_ARM_V4BX.
3164 1 = Convert BX to MOV PC.
3165 2 = Generate v4 interworing stubs. */
3166 int fix_v4bx;
319850b4 3167
48229727
JB		 3168 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3169 int fix_cortex_a8;
3170
2de70689
MGD		 3171 /* Whether we should fix the ARM1176 BLX immediate issue. */
3172 int fix_arm1176;
3173
906e58ca
NC		 3174 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3175 int use_blx;
33bfe774 3176
906e58ca
NC		 3177 /* What sort of code sequences we should look for which may trigger the
3178 VFP11 denorm erratum. */
3179 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3180
906e58ca
NC		 3181 /* Global counter for the number of fixes we have emitted. */
3182 int num_vfp11_fixes;
c7b8f16e 3183
a504d23a
LA		 3184 /* What sort of code sequences we should look for which may trigger the
3185 STM32L4XX erratum. */
3186 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3187
3188 /* Global counter for the number of fixes we have emitted. */
3189 int num_stm32l4xx_fixes;
3190
906e58ca
NC		 3191 /* Nonzero to force PIC branch veneers. */
3192 int pic_veneer;
27e55c4d 3193
906e58ca
NC		 3194 /* The number of bytes in the initial entry in the PLT. */
3195 bfd_size_type plt_header_size;
e5a52504 3196
906e58ca
NC		 3197 /* The number of bytes in the subsequent PLT etries. */
3198 bfd_size_type plt_entry_size;
e5a52504 3199
906e58ca
NC		 3200 /* True if the target system is VxWorks. */
3201 int vxworks_p;
00a97672 3202
906e58ca
NC		 3203 /* True if the target system is Symbian OS. */
3204 int symbian_p;
e5a52504 3205
b38cadfb
NC		 3206 /* True if the target system is Native Client. */
3207 int nacl_p;
3208
906e58ca 3209 /* True if the target uses REL relocations. */
f3185997 3210 bfd_boolean use_rel;
4e7fd91e 3211
54ddd295
TP		 3212 /* Nonzero if import library must be a secure gateway import library
3213 as per ARMv8-M Security Extensions. */
3214 int cmse_implib;
3215
0955507f
TP		 3216 /* The import library whose symbols' address must remain stable in
3217 the import library generated. */
3218 bfd *in_implib_bfd;
3219
0855e32b
NS		 3220 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3221 bfd_vma next_tls_desc_index;
3222
3223 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3224 bfd_vma num_tls_desc;
3225
906e58ca
NC		 3226 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3227 asection *srelplt2;
00a97672 3228
0855e32b
NS		 3229 /* The offset into splt of the PLT entry for the TLS descriptor
3230 resolver. Special values are 0, if not necessary (or not found
3231 to be necessary yet), and -1 if needed but not determined
3232 yet. */
3233 bfd_vma dt_tlsdesc_plt;
3234
3235 /* The offset into sgot of the GOT entry used by the PLT entry
3236 above. */
b38cadfb 3237 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3238
3239 /* Offset in .plt section of tls_arm_trampoline. */
3240 bfd_vma tls_trampoline;
3241
906e58ca
NC		 3242 /* Data for R_ARM_TLS_LDM32 relocations. */
3243 union
3244 {
3245 bfd_signed_vma refcount;
3246 bfd_vma offset;
3247 } tls_ldm_got;
b7693d02 3248
87d72d41
AM		 3249 /* Small local sym cache. */
3250 struct sym_cache sym_cache;
906e58ca
NC		 3251
3252 /* For convenience in allocate_dynrelocs. */
3253 bfd * obfd;
3254
0855e32b
NS		 3255 /* The amount of space used by the reserved portion of the sgotplt
3256 section, plus whatever space is used by the jump slots. */
3257 bfd_vma sgotplt_jump_table_size;
3258
906e58ca
NC		 3259 /* The stub hash table. */
3260 struct bfd_hash_table stub_hash_table;
3261
3262 /* Linker stub bfd. */
3263 bfd *stub_bfd;
3264
3265 /* Linker call-backs. */
6bde4c52
TP		 3266 asection * (*add_stub_section) (const char *, asection *, asection *,
3267 unsigned int);
906e58ca
NC		 3268 void (*layout_sections_again) (void);
3269
3270 /* Array to keep track of which stub sections have been created, and
3271 information on stub grouping. */
21d799b5 3272 struct map_stub *stub_group;
906e58ca 3273
4ba2ef8f
TP		 3274 /* Input stub section holding secure gateway veneers. */
3275 asection *cmse_stub_sec;
3276
0955507f
TP		 3277 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3278 start to be allocated. */
3279 bfd_vma new_cmse_stub_offset;
3280
fe33d2fa 3281 /* Number of elements in stub_group. */
7292b3ac 3282 unsigned int top_id;
fe33d2fa 3283
906e58ca
NC		 3284 /* Assorted information used by elf32_arm_size_stubs. */
3285 unsigned int bfd_count;
7292b3ac 3286 unsigned int top_index;
906e58ca 3287 asection **input_list;
617a5ada
CL		 3288
3289 /* True if the target system uses FDPIC. */
3290 int fdpic_p;
906e58ca 3291};
252b5132 3292
a504d23a
LA		 3293static inline int
3294ctz (unsigned int mask)
3295{
3296#if GCC_VERSION >= 3004
3297 return __builtin_ctz (mask);
3298#else
3299 unsigned int i;
3300
3301 for (i = 0; i < 8 * sizeof (mask); i++)
3302 {
3303 if (mask & 0x1)
3304 break;
3305 mask = (mask >> 1);
3306 }
3307 return i;
3308#endif
3309}
3310
3311static inline int
b25e998d 3312elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3313{
3314#if GCC_VERSION >= 3004
3315 return __builtin_popcount (mask);
3316#else
b25e998d
CG		 3317 unsigned int i;
3318 int sum = 0;
a504d23a
LA		 3319
3320 for (i = 0; i < 8 * sizeof (mask); i++)
3321 {
3322 if (mask & 0x1)
3323 sum++;
3324 mask = (mask >> 1);
3325 }
3326 return sum;
3327#endif
3328}
3329
780a67af
NC		 3330/* Create an entry in an ARM ELF linker hash table. */
3331
3332static struct bfd_hash_entry *
57e8b36a 3333elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3334 struct bfd_hash_table * table,
3335 const char * string)
780a67af
NC		 3336{
3337 struct elf32_arm_link_hash_entry * ret =
3338 (struct elf32_arm_link_hash_entry *) entry;
3339
3340 /* Allocate the structure if it has not already been allocated by a
3341 subclass. */
906e58ca 3342 if (ret == NULL)
21d799b5 3343 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3344 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3345 if (ret == NULL)
780a67af
NC		 3346 return (struct bfd_hash_entry *) ret;
3347
3348 /* Call the allocation method of the superclass. */
3349 ret = ((struct elf32_arm_link_hash_entry *)
3350 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3351 table, string));
57e8b36a 3352 if (ret != NULL)
b7693d02 3353 {
0bdcacaf 3354 ret->dyn_relocs = NULL;
ba93b8ac 3355 ret->tls_type = GOT_UNKNOWN;
0855e32b 3356 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3357 ret->plt.thumb_refcount = 0;
3358 ret->plt.maybe_thumb_refcount = 0;
3359 ret->plt.noncall_refcount = 0;
3360 ret->plt.got_offset = -1;
3361 ret->is_iplt = FALSE;
a4fd1a8e 3362 ret->export_glue = NULL;
906e58ca
NC		 3363
3364 ret->stub_cache = NULL;
b7693d02 3365 }
780a67af
NC		 3366
3367 return (struct bfd_hash_entry *) ret;
3368}
3369
34e77a92
RS		 3370/* Ensure that we have allocated bookkeeping structures for ABFD's local
3371 symbols. */
3372
3373static bfd_boolean
3374elf32_arm_allocate_local_sym_info (bfd *abfd)
3375{
3376 if (elf_local_got_refcounts (abfd) == NULL)
3377 {
3378 bfd_size_type num_syms;
3379 bfd_size_type size;
3380 char *data;
3381
3382 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3383 size = num_syms * (sizeof (bfd_signed_vma)
3384 + sizeof (struct arm_local_iplt_info *)
3385 + sizeof (bfd_vma)
3386 + sizeof (char));
3387 data = bfd_zalloc (abfd, size);
3388 if (data == NULL)
3389 return FALSE;
3390
3391 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3392 data += num_syms * sizeof (bfd_signed_vma);
3393
3394 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3395 data += num_syms * sizeof (struct arm_local_iplt_info *);
3396
3397 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3398 data += num_syms * sizeof (bfd_vma);
3399
3400 elf32_arm_local_got_tls_type (abfd) = data;
3401 }
3402 return TRUE;
3403}
3404
3405/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3406 to input bfd ABFD. Create the information if it doesn't already exist.
3407 Return null if an allocation fails. */
3408
3409static struct arm_local_iplt_info *
3410elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3411{
3412 struct arm_local_iplt_info **ptr;
3413
3414 if (!elf32_arm_allocate_local_sym_info (abfd))
3415 return NULL;
3416
3417 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3418 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3419 if (*ptr == NULL)
3420 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3421 return *ptr;
3422}
3423
3424/* Try to obtain PLT information for the symbol with index R_SYMNDX
3425 in ABFD's symbol table. If the symbol is global, H points to its
3426 hash table entry, otherwise H is null.
3427
3428 Return true if the symbol does have PLT information. When returning
3429 true, point *ROOT_PLT at the target-independent reference count/offset
3430 union and *ARM_PLT at the ARM-specific information. */
3431
3432static bfd_boolean
4ba2ef8f
TP		 3433elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3434 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3435 unsigned long r_symndx, union gotplt_union **root_plt,
3436 struct arm_plt_info **arm_plt)
3437{
3438 struct arm_local_iplt_info *local_iplt;
3439
4ba2ef8f
TP		 3440 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3441 return FALSE;
3442
34e77a92
RS		 3443 if (h != NULL)
3444 {
3445 *root_plt = &h->root.plt;
3446 *arm_plt = &h->plt;
3447 return TRUE;
3448 }
3449
3450 if (elf32_arm_local_iplt (abfd) == NULL)
3451 return FALSE;
3452
3453 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3454 if (local_iplt == NULL)
3455 return FALSE;
3456
3457 *root_plt = &local_iplt->root;
3458 *arm_plt = &local_iplt->arm;
3459 return TRUE;
3460}
3461
3462/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3463 before it. */
3464
3465static bfd_boolean
3466elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3467 struct arm_plt_info *arm_plt)
3468{
3469 struct elf32_arm_link_hash_table *htab;
3470
3471 htab = elf32_arm_hash_table (info);
3472 return (arm_plt->thumb_refcount != 0
3473 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3474}
3475
3476/* Return a pointer to the head of the dynamic reloc list that should
3477 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3478 ABFD's symbol table. Return null if an error occurs. */
3479
3480static struct elf_dyn_relocs **
3481elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3482 Elf_Internal_Sym *isym)
3483{
3484 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3485 {
3486 struct arm_local_iplt_info *local_iplt;
3487
3488 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3489 if (local_iplt == NULL)
3490 return NULL;
3491 return &local_iplt->dyn_relocs;
3492 }
3493 else
3494 {
3495 /* Track dynamic relocs needed for local syms too.
3496 We really need local syms available to do this
3497 easily. Oh well. */
3498 asection *s;
3499 void *vpp;
3500
3501 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3502 if (s == NULL)
3503 abort ();
3504
3505 vpp = &elf_section_data (s)->local_dynrel;
3506 return (struct elf_dyn_relocs **) vpp;
3507 }
3508}
3509
906e58ca
NC		 3510/* Initialize an entry in the stub hash table. */
3511
3512static struct bfd_hash_entry *
3513stub_hash_newfunc (struct bfd_hash_entry *entry,
3514 struct bfd_hash_table *table,
3515 const char *string)
3516{
3517 /* Allocate the structure if it has not already been allocated by a
3518 subclass. */
3519 if (entry == NULL)
3520 {
21d799b5 3521 entry = (struct bfd_hash_entry *)
99059e56 3522 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3523 if (entry == NULL)
3524 return entry;
3525 }
3526
3527 /* Call the allocation method of the superclass. */
3528 entry = bfd_hash_newfunc (entry, table, string);
3529 if (entry != NULL)
3530 {
3531 struct elf32_arm_stub_hash_entry *eh;
3532
3533 /* Initialize the local fields. */
3534 eh = (struct elf32_arm_stub_hash_entry *) entry;
3535 eh->stub_sec = NULL;
0955507f 3536 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3537 eh->source_value = 0;
906e58ca
NC		 3538 eh->target_value = 0;
3539 eh->target_section = NULL;
cedfb179 3540 eh->orig_insn = 0;
906e58ca 3541 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3542 eh->stub_size = 0;
3543 eh->stub_template = NULL;
0955507f 3544 eh->stub_template_size = -1;
906e58ca
NC		 3545 eh->h = NULL;
3546 eh->id_sec = NULL;
d8d2f433 3547 eh->output_name = NULL;
906e58ca
NC		 3548 }
3549
3550 return entry;
3551}
3552
00a97672 3553/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3554 shortcuts to them in our hash table. */
3555
3556static bfd_boolean
57e8b36a 3557create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3558{
3559 struct elf32_arm_link_hash_table *htab;
3560
e5a52504 3561 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3562 if (htab == NULL)
3563 return FALSE;
3564
e5a52504
MM		 3565 /* BPABI objects never have a GOT, or associated sections. */
3566 if (htab->symbian_p)
3567 return TRUE;
3568
5e681ec4
PB		 3569 if (! _bfd_elf_create_got_section (dynobj, info))
3570 return FALSE;
3571
5e681ec4
PB		 3572 return TRUE;
3573}
3574
34e77a92
RS		 3575/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3576
3577static bfd_boolean
3578create_ifunc_sections (struct bfd_link_info *info)
3579{
3580 struct elf32_arm_link_hash_table *htab;
3581 const struct elf_backend_data *bed;
3582 bfd *dynobj;
3583 asection *s;
3584 flagword flags;
b38cadfb 3585
34e77a92
RS		 3586 htab = elf32_arm_hash_table (info);
3587 dynobj = htab->root.dynobj;
3588 bed = get_elf_backend_data (dynobj);
3589 flags = bed->dynamic_sec_flags;
3590
3591 if (htab->root.iplt == NULL)
3592 {
3d4d4302
AM		 3593 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3594 flags | SEC_READONLY | SEC_CODE);
34e77a92 3595 if (s == NULL
a0f49396 3596 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3597 return FALSE;
3598 htab->root.iplt = s;
3599 }
3600
3601 if (htab->root.irelplt == NULL)
3602 {
3d4d4302
AM		 3603 s = bfd_make_section_anyway_with_flags (dynobj,
3604 RELOC_SECTION (htab, ".iplt"),
3605 flags | SEC_READONLY);
34e77a92 3606 if (s == NULL
a0f49396 3607 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3608 return FALSE;
3609 htab->root.irelplt = s;
3610 }
3611
3612 if (htab->root.igotplt == NULL)
3613 {
3d4d4302 3614 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3615 if (s == NULL
3616 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3617 return FALSE;
3618 htab->root.igotplt = s;
3619 }
3620 return TRUE;
3621}
3622
eed94f8f
NC		 3623/* Determine if we're dealing with a Thumb only architecture. */
3624
3625static bfd_boolean
3626using_thumb_only (struct elf32_arm_link_hash_table *globals)
3627{
2fd158eb
TP		 3628 int arch;
3629 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3630 Tag_CPU_arch_profile);
eed94f8f 3631
2fd158eb
TP		 3632 if (profile)
3633 return profile == 'M';
eed94f8f 3634
2fd158eb 3635 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3636
60a019a0 3637 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3638 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0 3639
2fd158eb
TP		 3640 if (arch == TAG_CPU_ARCH_V6_M
3641 || arch == TAG_CPU_ARCH_V6S_M
3642 || arch == TAG_CPU_ARCH_V7E_M
3643 || arch == TAG_CPU_ARCH_V8M_BASE
3644 || arch == TAG_CPU_ARCH_V8M_MAIN)
3645 return TRUE;
eed94f8f 3646
2fd158eb 3647 return FALSE;
eed94f8f
NC		 3648}
3649
3650/* Determine if we're dealing with a Thumb-2 object. */
3651
3652static bfd_boolean
3653using_thumb2 (struct elf32_arm_link_hash_table *globals)
3654{
60a019a0
TP		 3655 int arch;
3656 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3657 Tag_THUMB_ISA_use);
3658
3659 if (thumb_isa)
3660 return thumb_isa == 2;
3661
3662 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3663
3664 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3665 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3666
3667 return (arch == TAG_CPU_ARCH_V6T2
3668 || arch == TAG_CPU_ARCH_V7
3669 || arch == TAG_CPU_ARCH_V7E_M
3670 || arch == TAG_CPU_ARCH_V8
bff0500d 3671 || arch == TAG_CPU_ARCH_V8R
60a019a0 3672 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3673}
3674
5e866f5a
TP		 3675/* Determine whether Thumb-2 BL instruction is available. */
3676
3677static bfd_boolean
3678using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3679{
3680 int arch =
3681 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3682
3683 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3684 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
5e866f5a
TP		 3685
3686 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3687 return (arch == TAG_CPU_ARCH_V6T2
3688 || arch >= TAG_CPU_ARCH_V7);
3689}
3690
00a97672
RS		 3691/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3692 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3693 hash table. */
3694
3695static bfd_boolean
57e8b36a 3696elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3697{
3698 struct elf32_arm_link_hash_table *htab;
3699
3700 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3701 if (htab == NULL)
3702 return FALSE;
3703
362d30a1 3704 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3705 return FALSE;
3706
3707 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3708 return FALSE;
3709
00a97672
RS		 3710 if (htab->vxworks_p)
3711 {
3712 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3713 return FALSE;
3714
0e1862bb 3715 if (bfd_link_pic (info))
00a97672
RS		 3716 {
3717 htab->plt_header_size = 0;
3718 htab->plt_entry_size
3719 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3720 }
3721 else
3722 {
3723 htab->plt_header_size
3724 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3725 htab->plt_entry_size
3726 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3727 }
aebf9be7
NC		 3728
3729 if (elf_elfheader (dynobj))
3730 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3731 }
eed94f8f
NC		 3732 else
3733 {
3734 /* PR ld/16017
3735 Test for thumb only architectures. Note - we cannot just call
3736 using_thumb_only() as the attributes in the output bfd have not been
3737 initialised at this point, so instead we use the input bfd. */
3738 bfd * saved_obfd = htab->obfd;
3739
3740 htab->obfd = dynobj;
3741 if (using_thumb_only (htab))
3742 {
3743 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3744 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3745 }
3746 htab->obfd = saved_obfd;
3747 }
5e681ec4 3748
362d30a1
RS		 3749 if (!htab->root.splt
3750 || !htab->root.srelplt
9d19e4fd
AM		 3751 || !htab->root.sdynbss
3752 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3753 abort ();
3754
3755 return TRUE;
3756}
3757
906e58ca
NC		 3758/* Copy the extra info we tack onto an elf_link_hash_entry. */
3759
3760static void
3761elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3762 struct elf_link_hash_entry *dir,
3763 struct elf_link_hash_entry *ind)
3764{
3765 struct elf32_arm_link_hash_entry *edir, *eind;
3766
3767 edir = (struct elf32_arm_link_hash_entry *) dir;
3768 eind = (struct elf32_arm_link_hash_entry *) ind;
3769
0bdcacaf 3770 if (eind->dyn_relocs != NULL)
906e58ca 3771 {
0bdcacaf 3772 if (edir->dyn_relocs != NULL)
906e58ca 3773 {
0bdcacaf
RS		 3774 struct elf_dyn_relocs **pp;
3775 struct elf_dyn_relocs *p;
906e58ca
NC		 3776
3777 /* Add reloc counts against the indirect sym to the direct sym
3778 list. Merge any entries against the same section. */
0bdcacaf 3779 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3780 {
0bdcacaf 3781 struct elf_dyn_relocs *q;
906e58ca 3782
0bdcacaf
RS		 3783 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3784 if (q->sec == p->sec)
906e58ca
NC		 3785 {
3786 q->pc_count += p->pc_count;
3787 q->count += p->count;
3788 *pp = p->next;
3789 break;
3790 }
3791 if (q == NULL)
3792 pp = &p->next;
3793 }
0bdcacaf 3794 *pp = edir->dyn_relocs;
906e58ca
NC		 3795 }
3796
0bdcacaf
RS		 3797 edir->dyn_relocs = eind->dyn_relocs;
3798 eind->dyn_relocs = NULL;
906e58ca
NC		 3799 }
3800
3801 if (ind->root.type == bfd_link_hash_indirect)
3802 {
3803 /* Copy over PLT info. */
34e77a92
RS		 3804 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3805 eind->plt.thumb_refcount = 0;
3806 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3807 eind->plt.maybe_thumb_refcount = 0;
3808 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3809 eind->plt.noncall_refcount = 0;
3810
3811 /* We should only allocate a function to .iplt once the final
3812 symbol information is known. */
3813 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3814
3815 if (dir->got.refcount <= 0)
3816 {
3817 edir->tls_type = eind->tls_type;
3818 eind->tls_type = GOT_UNKNOWN;
3819 }
3820 }
3821
3822 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3823}
3824
68faa637
AM		 3825/* Destroy an ARM elf linker hash table. */
3826
3827static void
d495ab0d 3828elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3829{
3830 struct elf32_arm_link_hash_table *ret
d495ab0d 3831 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3832
3833 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3834 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3835}
3836
906e58ca
NC		 3837/* Create an ARM elf linker hash table. */
3838
3839static struct bfd_link_hash_table *
3840elf32_arm_link_hash_table_create (bfd *abfd)
3841{
3842 struct elf32_arm_link_hash_table *ret;
3843 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3844
7bf52ea2 3845 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3846 if (ret == NULL)
3847 return NULL;
3848
3849 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3850 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3851 sizeof (struct elf32_arm_link_hash_entry),
3852 ARM_ELF_DATA))
906e58ca
NC		 3853 {
3854 free (ret);
3855 return NULL;
3856 }
3857
906e58ca 3858 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3859 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3860#ifdef FOUR_WORD_PLT
3861 ret->plt_header_size = 16;
3862 ret->plt_entry_size = 16;
3863#else
3864 ret->plt_header_size = 20;
1db37fe6 3865 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3866#endif
f3185997 3867 ret->use_rel = TRUE;
906e58ca 3868 ret->obfd = abfd;
617a5ada 3869 ret->fdpic_p = 0;
906e58ca
NC		 3870
3871 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3872 sizeof (struct elf32_arm_stub_hash_entry)))
3873 {
d495ab0d 3874 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3875 return NULL;
3876 }
d495ab0d 3877 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3878
3879 return &ret->root.root;
3880}
3881
cd1dac3d
DG		 3882/* Determine what kind of NOPs are available. */
3883
3884static bfd_boolean
3885arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3886{
3887 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3888 Tag_CPU_arch);
cd1dac3d 3889
60a019a0 3890 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3891 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3892
3893 return (arch == TAG_CPU_ARCH_V6T2
3894 || arch == TAG_CPU_ARCH_V6K
3895 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 3896 || arch == TAG_CPU_ARCH_V8
3897 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 3898}
3899
f4ac8484
DJ		 3900static bfd_boolean
3901arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3902{
3903 switch (stub_type)
3904 {
fea2b4d6 3905 case arm_stub_long_branch_thumb_only:
80c135e5 3906 case arm_stub_long_branch_thumb2_only:
d5a67c02 3907 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3908 case arm_stub_long_branch_v4t_thumb_arm:
3909 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3910 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3911 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3912 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3913 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3914 return TRUE;
3915 case arm_stub_none:
3916 BFD_FAIL ();
3917 return FALSE;
3918 break;
3919 default:
3920 return FALSE;
3921 }
3922}
3923
906e58ca
NC		 3924/* Determine the type of stub needed, if any, for a call. */
3925
3926static enum elf32_arm_stub_type
3927arm_type_of_stub (struct bfd_link_info *info,
3928 asection *input_sec,
3929 const Elf_Internal_Rela *rel,
34e77a92 3930 unsigned char st_type,
35fc36a8 3931 enum arm_st_branch_type *actual_branch_type,
906e58ca 3932 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3933 bfd_vma destination,
3934 asection *sym_sec,
3935 bfd *input_bfd,
3936 const char *name)
906e58ca
NC		 3937{
3938 bfd_vma location;
3939 bfd_signed_vma branch_offset;
3940 unsigned int r_type;
3941 struct elf32_arm_link_hash_table * globals;
5e866f5a 3942 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3943 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3944 int use_plt = 0;
35fc36a8 3945 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3946 union gotplt_union *root_plt;
3947 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3948 int arch;
3949 int thumb2_movw;
906e58ca 3950
35fc36a8 3951 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3952 return stub_type;
3953
906e58ca 3954 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3955 if (globals == NULL)
3956 return stub_type;
906e58ca
NC		 3957
3958 thumb_only = using_thumb_only (globals);
906e58ca 3959 thumb2 = using_thumb2 (globals);
5e866f5a 3960 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3961
d5a67c02
AV		 3962 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3963
3964 /* True for architectures that implement the thumb2 movw instruction. */
3965 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3966
906e58ca
NC		 3967 /* Determine where the call point is. */
3968 location = (input_sec->output_offset
3969 + input_sec->output_section->vma
3970 + rel->r_offset);
3971
906e58ca
NC		 3972 r_type = ELF32_R_TYPE (rel->r_info);
3973
39f21624
NC		 3974 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3975 are considering a function call relocation. */
c5423981 3976 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 3977 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3978 && branch_type == ST_BRANCH_TO_ARM)
3979 branch_type = ST_BRANCH_TO_THUMB;
3980
34e77a92
RS		 3981 /* For TLS call relocs, it is the caller's responsibility to provide
3982 the address of the appropriate trampoline. */
3983 if (r_type != R_ARM_TLS_CALL
3984 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3985 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3986 ELF32_R_SYM (rel->r_info), &root_plt,
3987 &arm_plt)
34e77a92 3988 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3989 {
34e77a92 3990 asection *splt;
fe33d2fa 3991
34e77a92
RS		 3992 if (hash == NULL || hash->is_iplt)
3993 splt = globals->root.iplt;
3994 else
3995 splt = globals->root.splt;
3996 if (splt != NULL)
b38cadfb 3997 {
34e77a92
RS		 3998 use_plt = 1;
3999
4000 /* Note when dealing with PLT entries: the main PLT stub is in
4001 ARM mode, so if the branch is in Thumb mode, another
4002 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4003 PLT stub. If a long branch stub is needed, we'll add a
4004 Thumb->Arm one and branch directly to the ARM PLT entry.
4005 Here, we have to check if a pre-PLT Thumb->ARM stub
4006 is needed and if it will be close enough. */
34e77a92
RS		 4007
4008 destination = (splt->output_section->vma
4009 + splt->output_offset
4010 + root_plt->offset);
4011 st_type = STT_FUNC;
2df2751d
CL		 4012
4013 /* Thumb branch/call to PLT: it can become a branch to ARM
4014 or to Thumb. We must perform the same checks and
4015 corrections as in elf32_arm_final_link_relocate. */
4016 if ((r_type == R_ARM_THM_CALL)
4017 || (r_type == R_ARM_THM_JUMP24))
4018 {
4019 if (globals->use_blx
4020 && r_type == R_ARM_THM_CALL
4021 && !thumb_only)
4022 {
4023 /* If the Thumb BLX instruction is available, convert
4024 the BL to a BLX instruction to call the ARM-mode
4025 PLT entry. */
4026 branch_type = ST_BRANCH_TO_ARM;
4027 }
4028 else
4029 {
4030 if (!thumb_only)
4031 /* Target the Thumb stub before the ARM PLT entry. */
4032 destination -= PLT_THUMB_STUB_SIZE;
4033 branch_type = ST_BRANCH_TO_THUMB;
4034 }
4035 }
4036 else
4037 {
4038 branch_type = ST_BRANCH_TO_ARM;
4039 }
34e77a92 4040 }
5fa9e92f 4041 }
34e77a92
RS		 4042 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4043 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4044
fe33d2fa
CL		 4045 branch_offset = (bfd_signed_vma)(destination - location);
4046
0855e32b 4047 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4048 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4049 {
5fa9e92f
CL		 4050 /* Handle cases where:
4051 - this call goes too far (different Thumb/Thumb2 max
99059e56 4052 distance)
155d87d7 4053 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4054 Thumb->Arm branch (not bl). A stub is needed in this case,
4055 but only if this call is not through a PLT entry. Indeed,
695344c0 4056 PLT stubs handle mode switching already. */
5e866f5a 4057 if ((!thumb2_bl
906e58ca
NC		 4058 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4059 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4060 || (thumb2_bl
906e58ca
NC		 4061 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4062 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4063 || (thumb2
4064 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4065 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4066 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4067 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4068 && (((r_type == R_ARM_THM_CALL
4069 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4070 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4071 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4072 && !use_plt))
906e58ca 4073 {
2df2751d
CL		 4074 /* If we need to insert a Thumb-Thumb long branch stub to a
4075 PLT, use one that branches directly to the ARM PLT
4076 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4077 stub, undo this now. */
695344c0
NC		 4078 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4079 {
4080 branch_type = ST_BRANCH_TO_ARM;
4081 branch_offset += PLT_THUMB_STUB_SIZE;
4082 }
2df2751d 4083
35fc36a8 4084 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4085 {
4086 /* Thumb to thumb. */
4087 if (!thumb_only)
4088 {
d5a67c02 4089 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4090 _bfd_error_handler
871b3ab2 4091 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4092 " section with SHF_ARM_PURECODE section"
4093 " attribute is only supported for M-profile"
90b6238f 4094 " targets that implement the movw instruction"),
10463f39 4095 input_bfd, input_sec);
d5a67c02 4096
0e1862bb 4097 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4098 /* PIC stubs. */
155d87d7 4099 ? ((globals->use_blx
9553db3c 4100 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4101 /* V5T and above. Stub starts with ARM code, so
4102 we must be able to switch mode before
4103 reaching it, which is only possible for 'bl'
4104 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4105 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4106 /* On V4T, use Thumb code only. */
d3626fb0 4107 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4108
4109 /* non-PIC stubs. */
155d87d7 4110 : ((globals->use_blx
9553db3c 4111 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4112 /* V5T and above. */
4113 ? arm_stub_long_branch_any_any
4114 /* V4T. */
d3626fb0 4115 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4116 }
4117 else
4118 {
d5a67c02
AV		 4119 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4120 stub_type = arm_stub_long_branch_thumb2_only_pure;
4121 else
4122 {
4123 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4124 _bfd_error_handler
871b3ab2 4125 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4126 " section with SHF_ARM_PURECODE section"
4127 " attribute is only supported for M-profile"
90b6238f 4128 " targets that implement the movw instruction"),
10463f39 4129 input_bfd, input_sec);
d5a67c02
AV		 4130
4131 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4132 /* PIC stub. */
4133 ? arm_stub_long_branch_thumb_only_pic
4134 /* non-PIC stub. */
4135 : (thumb2 ? arm_stub_long_branch_thumb2_only
4136 : arm_stub_long_branch_thumb_only);
4137 }
906e58ca
NC		 4138 }
4139 }
4140 else
4141 {
d5a67c02 4142 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4143 _bfd_error_handler
871b3ab2 4144 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4145 " section with SHF_ARM_PURECODE section"
4146 " attribute is only supported" " for M-profile"
90b6238f 4147 " targets that implement the movw instruction"),
10463f39 4148 input_bfd, input_sec);
d5a67c02 4149
906e58ca 4150 /* Thumb to arm. */
c820be07
NC		 4151 if (sym_sec != NULL
4152 && sym_sec->owner != NULL
4153 && !INTERWORK_FLAG (sym_sec->owner))
4154 {
4eca0228 4155 _bfd_error_handler
90b6238f
AM		 4156 (_("%pB(%s): warning: interworking not enabled;"
4157 " first occurrence: %pB: %s call to %s"),
4158 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4159 }
4160
0855e32b 4161 stub_type =
0e1862bb 4162 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4163 /* PIC stubs. */
0855e32b 4164 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4165 /* TLS PIC stubs. */
0855e32b
NS		 4166 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4167 : arm_stub_long_branch_v4t_thumb_tls_pic)
4168 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4169 /* V5T PIC and above. */
4170 ? arm_stub_long_branch_any_arm_pic
4171 /* V4T PIC stub. */
4172 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4173
4174 /* non-PIC stubs. */
0855e32b 4175 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4176 /* V5T and above. */
4177 ? arm_stub_long_branch_any_any
4178 /* V4T. */
4179 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4180
4181 /* Handle v4t short branches. */
fea2b4d6 4182 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4183 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4184 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4185 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4186 }
4187 }
4188 }
fe33d2fa
CL		 4189 else if (r_type == R_ARM_CALL
4190 || r_type == R_ARM_JUMP24
0855e32b
NS		 4191 || r_type == R_ARM_PLT32
4192 || r_type == R_ARM_TLS_CALL)
906e58ca 4193 {
d5a67c02 4194 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4195 _bfd_error_handler
871b3ab2 4196 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4197 " section with SHF_ARM_PURECODE section"
4198 " attribute is only supported for M-profile"
90b6238f 4199 " targets that implement the movw instruction"),
10463f39 4200 input_bfd, input_sec);
35fc36a8 4201 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4202 {
4203 /* Arm to thumb. */
c820be07
NC		 4204
4205 if (sym_sec != NULL
4206 && sym_sec->owner != NULL
4207 && !INTERWORK_FLAG (sym_sec->owner))
4208 {
4eca0228 4209 _bfd_error_handler
90b6238f
AM		 4210 (_("%pB(%s): warning: interworking not enabled;"
4211 " first occurrence: %pB: %s call to %s"),
4212 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4213 }
4214
4215 /* We have an extra 2-bytes reach because of
4216 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4217 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4218 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4219 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4220 || (r_type == R_ARM_JUMP24)
4221 || (r_type == R_ARM_PLT32))
906e58ca 4222 {
0e1862bb 4223 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4224 /* PIC stubs. */
ebe24dd4
CL		 4225 ? ((globals->use_blx)
4226 /* V5T and above. */
4227 ? arm_stub_long_branch_any_thumb_pic
4228 /* V4T stub. */
4229 : arm_stub_long_branch_v4t_arm_thumb_pic)
4230
c2b4a39d
CL		 4231 /* non-PIC stubs. */
4232 : ((globals->use_blx)
4233 /* V5T and above. */
4234 ? arm_stub_long_branch_any_any
4235 /* V4T. */
4236 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4237 }
4238 }
4239 else
4240 {
4241 /* Arm to arm. */
4242 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4243 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4244 {
0855e32b 4245 stub_type =
0e1862bb 4246 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4247 /* PIC stubs. */
0855e32b 4248 ? (r_type == R_ARM_TLS_CALL
6a631e86 4249 /* TLS PIC Stub. */
0855e32b 4250 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4251 : (globals->nacl_p
4252 ? arm_stub_long_branch_arm_nacl_pic
4253 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4254 /* non-PIC stubs. */
7a89b94e
NC		 4255 : (globals->nacl_p
4256 ? arm_stub_long_branch_arm_nacl
4257 : arm_stub_long_branch_any_any);
906e58ca
NC		 4258 }
4259 }
4260 }
4261
fe33d2fa
CL		 4262 /* If a stub is needed, record the actual destination type. */
4263 if (stub_type != arm_stub_none)
35fc36a8 4264 *actual_branch_type = branch_type;
fe33d2fa 4265
906e58ca
NC		 4266 return stub_type;
4267}
4268
4269/* Build a name for an entry in the stub hash table. */
4270
4271static char *
4272elf32_arm_stub_name (const asection *input_section,
4273 const asection *sym_sec,
4274 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4275 const Elf_Internal_Rela *rel,
4276 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4277{
4278 char *stub_name;
4279 bfd_size_type len;
4280
4281 if (hash)
4282 {
fe33d2fa 4283 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4284 stub_name = (char *) bfd_malloc (len);
906e58ca 4285 if (stub_name != NULL)
fe33d2fa 4286 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4287 input_section->id & 0xffffffff,
4288 hash->root.root.root.string,
fe33d2fa
CL		 4289 (int) rel->r_addend & 0xffffffff,
4290 (int) stub_type);
906e58ca
NC		 4291 }
4292 else
4293 {
fe33d2fa 4294 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4295 stub_name = (char *) bfd_malloc (len);
906e58ca 4296 if (stub_name != NULL)
fe33d2fa 4297 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4298 input_section->id & 0xffffffff,
4299 sym_sec->id & 0xffffffff,
0855e32b
NS		 4300 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4301 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4302 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4303 (int) rel->r_addend & 0xffffffff,
4304 (int) stub_type);
906e58ca
NC		 4305 }
4306
4307 return stub_name;
4308}
4309
4310/* Look up an entry in the stub hash. Stub entries are cached because
4311 creating the stub name takes a bit of time. */
4312
4313static struct elf32_arm_stub_hash_entry *
4314elf32_arm_get_stub_entry (const asection *input_section,
4315 const asection *sym_sec,
4316 struct elf_link_hash_entry *hash,
4317 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4318 struct elf32_arm_link_hash_table *htab,
4319 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4320{
4321 struct elf32_arm_stub_hash_entry *stub_entry;
4322 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4323 const asection *id_sec;
4324
4325 if ((input_section->flags & SEC_CODE) == 0)
4326 return NULL;
4327
4328 /* If this input section is part of a group of sections sharing one
4329 stub section, then use the id of the first section in the group.
4330 Stub names need to include a section id, as there may well be
4331 more than one stub used to reach say, printf, and we need to
4332 distinguish between them. */
c2abbbeb 4333 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4334 id_sec = htab->stub_group[input_section->id].link_sec;
4335
4336 if (h != NULL && h->stub_cache != NULL
4337 && h->stub_cache->h == h
fe33d2fa
CL		 4338 && h->stub_cache->id_sec == id_sec
4339 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4340 {
4341 stub_entry = h->stub_cache;
4342 }
4343 else
4344 {
4345 char *stub_name;
4346
fe33d2fa 4347 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4348 if (stub_name == NULL)
4349 return NULL;
4350
4351 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4352 stub_name, FALSE, FALSE);
4353 if (h != NULL)
4354 h->stub_cache = stub_entry;
4355
4356 free (stub_name);
4357 }
4358
4359 return stub_entry;
4360}
4361
daa4adae
TP		 4362/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4363 section. */
4364
4365static bfd_boolean
4366arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4367{
4368 if (stub_type >= max_stub_type)
4369 abort (); /* Should be unreachable. */
4370
4ba2ef8f
TP		 4371 switch (stub_type)
4372 {
4373 case arm_stub_cmse_branch_thumb_only:
4374 return TRUE;
4375
4376 default:
4377 return FALSE;
4378 }
4379
4380 abort (); /* Should be unreachable. */
daa4adae
TP		 4381}
4382
4383/* Required alignment (as a power of 2) for the dedicated section holding
4384 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4385 with input sections. */
4386
4387static int
4388arm_dedicated_stub_output_section_required_alignment
4389 (enum elf32_arm_stub_type stub_type)
4390{
4391 if (stub_type >= max_stub_type)
4392 abort (); /* Should be unreachable. */
4393
4ba2ef8f
TP		 4394 switch (stub_type)
4395 {
4396 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4397 boundary. */
4398 case arm_stub_cmse_branch_thumb_only:
4399 return 5;
4400
4401 default:
4402 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4403 return 0;
4404 }
4405
4406 abort (); /* Should be unreachable. */
daa4adae
TP		 4407}
4408
4409/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4410 NULL if veneers of this type are interspersed with input sections. */
4411
4412static const char *
4413arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4414{
4415 if (stub_type >= max_stub_type)
4416 abort (); /* Should be unreachable. */
4417
4ba2ef8f
TP		 4418 switch (stub_type)
4419 {
4420 case arm_stub_cmse_branch_thumb_only:
4421 return ".gnu.sgstubs";
4422
4423 default:
4424 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4425 return NULL;
4426 }
4427
4428 abort (); /* Should be unreachable. */
daa4adae
TP		 4429}
4430
4431/* If veneers of type STUB_TYPE should go in a dedicated output section,
4432 returns the address of the hash table field in HTAB holding a pointer to the
4433 corresponding input section. Otherwise, returns NULL. */
4434
4435static asection **
4ba2ef8f
TP		 4436arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4437 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4438{
4439 if (stub_type >= max_stub_type)
4440 abort (); /* Should be unreachable. */
4441
4ba2ef8f
TP		 4442 switch (stub_type)
4443 {
4444 case arm_stub_cmse_branch_thumb_only:
4445 return &htab->cmse_stub_sec;
4446
4447 default:
4448 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4449 return NULL;
4450 }
4451
4452 abort (); /* Should be unreachable. */
daa4adae
TP		 4453}
4454
4455/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4456 is the section that branch into veneer and can be NULL if stub should go in
4457 a dedicated output section. Returns a pointer to the stub section, and the
4458 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4459 LINK_SEC_P may be NULL. */
906e58ca 4460
48229727
JB		 4461static asection *
4462elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4463 struct elf32_arm_link_hash_table *htab,
4464 enum elf32_arm_stub_type stub_type)
906e58ca 4465{
daa4adae
TP		 4466 asection *link_sec, *out_sec, **stub_sec_p;
4467 const char *stub_sec_prefix;
4468 bfd_boolean dedicated_output_section =
4469 arm_dedicated_stub_output_section_required (stub_type);
4470 int align;
906e58ca 4471
daa4adae 4472 if (dedicated_output_section)
906e58ca 4473 {
daa4adae
TP		 4474 bfd *output_bfd = htab->obfd;
4475 const char *out_sec_name =
4476 arm_dedicated_stub_output_section_name (stub_type);
4477 link_sec = NULL;
4478 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4479 stub_sec_prefix = out_sec_name;
4480 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4481 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4482 if (out_sec == NULL)
906e58ca 4483 {
90b6238f 4484 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4485 "section %s"), out_sec_name);
daa4adae 4486 return NULL;
906e58ca 4487 }
daa4adae
TP		 4488 }
4489 else
4490 {
c2abbbeb 4491 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4492 link_sec = htab->stub_group[section->id].link_sec;
4493 BFD_ASSERT (link_sec != NULL);
4494 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4495 if (*stub_sec_p == NULL)
4496 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4497 stub_sec_prefix = link_sec->name;
4498 out_sec = link_sec->output_section;
4499 align = htab->nacl_p ? 4 : 3;
906e58ca 4500 }
b38cadfb 4501
daa4adae
TP		 4502 if (*stub_sec_p == NULL)
4503 {
4504 size_t namelen;
4505 bfd_size_type len;
4506 char *s_name;
4507
4508 namelen = strlen (stub_sec_prefix);
4509 len = namelen + sizeof (STUB_SUFFIX);
4510 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4511 if (s_name == NULL)
4512 return NULL;
4513
4514 memcpy (s_name, stub_sec_prefix, namelen);
4515 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4516 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4517 align);
4518 if (*stub_sec_p == NULL)
4519 return NULL;
4520
4521 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4522 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4523 | SEC_KEEP;
4524 }
4525
4526 if (!dedicated_output_section)
4527 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4528
48229727
JB		 4529 if (link_sec_p)
4530 *link_sec_p = link_sec;
b38cadfb 4531
daa4adae 4532 return *stub_sec_p;
48229727
JB		 4533}
4534
4535/* Add a new stub entry to the stub hash. Not all fields of the new
4536 stub entry are initialised. */
4537
4538static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4539elf32_arm_add_stub (const char *stub_name, asection *section,
4540 struct elf32_arm_link_hash_table *htab,
4541 enum elf32_arm_stub_type stub_type)
48229727
JB		 4542{
4543 asection *link_sec;
4544 asection *stub_sec;
4545 struct elf32_arm_stub_hash_entry *stub_entry;
4546
daa4adae
TP		 4547 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4548 stub_type);
48229727
JB		 4549 if (stub_sec == NULL)
4550 return NULL;
906e58ca
NC		 4551
4552 /* Enter this entry into the linker stub hash table. */
4553 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4554 TRUE, FALSE);
4555 if (stub_entry == NULL)
4556 {
6bde4c52
TP		 4557 if (section == NULL)
4558 section = stub_sec;
871b3ab2 4559 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4560 section->owner, stub_name);
906e58ca
NC		 4561 return NULL;
4562 }
4563
4564 stub_entry->stub_sec = stub_sec;
0955507f 4565 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4566 stub_entry->id_sec = link_sec;
4567
906e58ca
NC		 4568 return stub_entry;
4569}
4570
4571/* Store an Arm insn into an output section not processed by
4572 elf32_arm_write_section. */
4573
4574static void
8029a119
NC		 4575put_arm_insn (struct elf32_arm_link_hash_table * htab,
4576 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4577{
4578 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4579 bfd_putl32 (val, ptr);
4580 else
4581 bfd_putb32 (val, ptr);
4582}
4583
4584/* Store a 16-bit Thumb insn into an output section not processed by
4585 elf32_arm_write_section. */
4586
4587static void
8029a119
NC		 4588put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4589 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4590{
4591 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4592 bfd_putl16 (val, ptr);
4593 else
4594 bfd_putb16 (val, ptr);
4595}
4596
a504d23a
LA		 4597/* Store a Thumb2 insn into an output section not processed by
4598 elf32_arm_write_section. */
4599
4600static void
4601put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4602 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4603{
4604 /* T2 instructions are 16-bit streamed. */
4605 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4606 {
4607 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4608 bfd_putl16 ((val & 0xffff), ptr + 2);
4609 }
4610 else
4611 {
4612 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4613 bfd_putb16 ((val & 0xffff), ptr + 2);
4614 }
4615}
4616
0855e32b
NS		 4617/* If it's possible to change R_TYPE to a more efficient access
4618 model, return the new reloc type. */
4619
4620static unsigned
b38cadfb 4621elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4622 struct elf_link_hash_entry *h)
4623{
4624 int is_local = (h == NULL);
4625
0e1862bb
L		 4626 if (bfd_link_pic (info)
4627 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4628 return r_type;
4629
b38cadfb 4630 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4631 switch (r_type)
4632 {
4633 case R_ARM_TLS_GOTDESC:
4634 case R_ARM_TLS_CALL:
4635 case R_ARM_THM_TLS_CALL:
4636 case R_ARM_TLS_DESCSEQ:
4637 case R_ARM_THM_TLS_DESCSEQ:
4638 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4639 }
4640
4641 return r_type;
4642}
4643
48229727
JB		 4644static bfd_reloc_status_type elf32_arm_final_link_relocate
4645 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4646 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4647 const char *, unsigned char, enum arm_st_branch_type,
4648 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4649
4563a860
JB		 4650static unsigned int
4651arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4652{
4653 switch (stub_type)
4654 {
4655 case arm_stub_a8_veneer_b_cond:
4656 case arm_stub_a8_veneer_b:
4657 case arm_stub_a8_veneer_bl:
4658 return 2;
4659
4660 case arm_stub_long_branch_any_any:
4661 case arm_stub_long_branch_v4t_arm_thumb:
4662 case arm_stub_long_branch_thumb_only:
80c135e5 4663 case arm_stub_long_branch_thumb2_only:
d5a67c02 4664 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4665 case arm_stub_long_branch_v4t_thumb_thumb:
4666 case arm_stub_long_branch_v4t_thumb_arm:
4667 case arm_stub_short_branch_v4t_thumb_arm:
4668 case arm_stub_long_branch_any_arm_pic:
4669 case arm_stub_long_branch_any_thumb_pic:
4670 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4671 case arm_stub_long_branch_v4t_arm_thumb_pic:
4672 case arm_stub_long_branch_v4t_thumb_arm_pic:
4673 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4674 case arm_stub_long_branch_any_tls_pic:
4675 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4676 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4677 case arm_stub_a8_veneer_blx:
4678 return 4;
b38cadfb 4679
7a89b94e
NC		 4680 case arm_stub_long_branch_arm_nacl:
4681 case arm_stub_long_branch_arm_nacl_pic:
4682 return 16;
4683
4563a860
JB		 4684 default:
4685 abort (); /* Should be unreachable. */
4686 }
4687}
4688
4f4faa4d
TP		 4689/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4690 veneering (TRUE) or have their own symbol (FALSE). */
4691
4692static bfd_boolean
4693arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4694{
4695 if (stub_type >= max_stub_type)
4696 abort (); /* Should be unreachable. */
4697
4ba2ef8f
TP		 4698 switch (stub_type)
4699 {
4700 case arm_stub_cmse_branch_thumb_only:
4701 return TRUE;
4702
4703 default:
4704 return FALSE;
4705 }
4706
4707 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4708}
4709
d7c5bd02
TP		 4710/* Returns the padding needed for the dedicated section used stubs of type
4711 STUB_TYPE. */
4712
4713static int
4714arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4715{
4716 if (stub_type >= max_stub_type)
4717 abort (); /* Should be unreachable. */
4718
4ba2ef8f
TP		 4719 switch (stub_type)
4720 {
4721 case arm_stub_cmse_branch_thumb_only:
4722 return 32;
4723
4724 default:
4725 return 0;
4726 }
4727
4728 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4729}
4730
0955507f
TP		 4731/* If veneers of type STUB_TYPE should go in a dedicated output section,
4732 returns the address of the hash table field in HTAB holding the offset at
4733 which new veneers should be layed out in the stub section. */
4734
4735static bfd_vma*
4736arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4737 enum elf32_arm_stub_type stub_type)
4738{
4739 switch (stub_type)
4740 {
4741 case arm_stub_cmse_branch_thumb_only:
4742 return &htab->new_cmse_stub_offset;
4743
4744 default:
4745 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4746 return NULL;
4747 }
4748}
4749
906e58ca
NC		 4750static bfd_boolean
4751arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4752 void * in_arg)
4753{
7a89b94e 4754#define MAXRELOCS 3
0955507f 4755 bfd_boolean removed_sg_veneer;
906e58ca 4756 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4757 struct elf32_arm_link_hash_table *globals;
906e58ca 4758 struct bfd_link_info *info;
906e58ca
NC		 4759 asection *stub_sec;
4760 bfd *stub_bfd;
906e58ca
NC		 4761 bfd_byte *loc;
4762 bfd_vma sym_value;
4763 int template_size;
4764 int size;
d3ce72d0 4765 const insn_sequence *template_sequence;
906e58ca 4766 int i;
48229727
JB		 4767 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4768 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4769 int nrelocs = 0;
0955507f 4770 int just_allocated = 0;
906e58ca
NC		 4771
4772 /* Massage our args to the form they really have. */
4773 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4774 info = (struct bfd_link_info *) in_arg;
4775
4776 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4777 if (globals == NULL)
4778 return FALSE;
906e58ca 4779
906e58ca
NC		 4780 stub_sec = stub_entry->stub_sec;
4781
4dfe6ac6 4782 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4783 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4784 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4785 return TRUE;
fe33d2fa 4786
0955507f
TP		 4787 /* Assign a slot at the end of section if none assigned yet. */
4788 if (stub_entry->stub_offset == (bfd_vma) -1)
4789 {
4790 stub_entry->stub_offset = stub_sec->size;
4791 just_allocated = 1;
4792 }
906e58ca
NC		 4793 loc = stub_sec->contents + stub_entry->stub_offset;
4794
4795 stub_bfd = stub_sec->owner;
4796
906e58ca
NC		 4797 /* This is the address of the stub destination. */
4798 sym_value = (stub_entry->target_value
4799 + stub_entry->target_section->output_offset
4800 + stub_entry->target_section->output_section->vma);
4801
d3ce72d0 4802 template_sequence = stub_entry->stub_template;
461a49ca 4803 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4804
4805 size = 0;
461a49ca 4806 for (i = 0; i < template_size; i++)
906e58ca 4807 {
d3ce72d0 4808 switch (template_sequence[i].type)
461a49ca
DJ		 4809 {
4810 case THUMB16_TYPE:
48229727 4811 {
d3ce72d0
NC		 4812 bfd_vma data = (bfd_vma) template_sequence[i].data;
4813 if (template_sequence[i].reloc_addend != 0)
48229727 4814 {
99059e56
RM		 4815 /* We've borrowed the reloc_addend field to mean we should
4816 insert a condition code into this (Thumb-1 branch)
4817 instruction. See THUMB16_BCOND_INSN. */
4818 BFD_ASSERT ((data & 0xff00) == 0xd000);
4819 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4820 }
fe33d2fa 4821 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4822 size += 2;
4823 }
461a49ca 4824 break;
906e58ca 4825
48229727 4826 case THUMB32_TYPE:
fe33d2fa
CL		 4827 bfd_put_16 (stub_bfd,
4828 (template_sequence[i].data >> 16) & 0xffff,
4829 loc + size);
4830 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4831 loc + size + 2);
99059e56
RM		 4832 if (template_sequence[i].r_type != R_ARM_NONE)
4833 {
4834 stub_reloc_idx[nrelocs] = i;
4835 stub_reloc_offset[nrelocs++] = size;
4836 }
4837 size += 4;
4838 break;
48229727 4839
461a49ca 4840 case ARM_TYPE:
fe33d2fa
CL		 4841 bfd_put_32 (stub_bfd, template_sequence[i].data,
4842 loc + size);
461a49ca
DJ		 4843 /* Handle cases where the target is encoded within the
4844 instruction. */
d3ce72d0 4845 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4846 {
48229727
JB		 4847 stub_reloc_idx[nrelocs] = i;
4848 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4849 }
4850 size += 4;
4851 break;
4852
4853 case DATA_TYPE:
d3ce72d0 4854 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4855 stub_reloc_idx[nrelocs] = i;
4856 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4857 size += 4;
4858 break;
4859
4860 default:
4861 BFD_FAIL ();
4862 return FALSE;
4863 }
906e58ca 4864 }
461a49ca 4865
0955507f
TP		 4866 if (just_allocated)
4867 stub_sec->size += size;
906e58ca 4868
461a49ca
DJ		 4869 /* Stub size has already been computed in arm_size_one_stub. Check
4870 consistency. */
4871 BFD_ASSERT (size == stub_entry->stub_size);
4872
906e58ca 4873 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4874 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4875 sym_value |= 1;
4876
0955507f
TP		 4877 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4878 to relocate in each stub. */
4879 removed_sg_veneer =
4880 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4881 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4882
48229727 4883 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4884 {
4885 Elf_Internal_Rela rel;
4886 bfd_boolean unresolved_reloc;
4887 char *error_message;
4888 bfd_vma points_to =
4889 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4890
4891 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4892 rel.r_info = ELF32_R_INFO (0,
4893 template_sequence[stub_reloc_idx[i]].r_type);
4894 rel.r_addend = 0;
4895
4896 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4897 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4898 template should refer back to the instruction after the original
4899 branch. We use target_section as Cortex-A8 erratum workaround stubs
4900 are only generated when both source and target are in the same
4901 section. */
4902 points_to = stub_entry->target_section->output_section->vma
4903 + stub_entry->target_section->output_offset
4904 + stub_entry->source_value;
4905
4906 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4907 (template_sequence[stub_reloc_idx[i]].r_type),
4908 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4909 points_to, info, stub_entry->target_section, "", STT_FUNC,
4910 stub_entry->branch_type,
4911 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4912 &error_message);
4913 }
906e58ca
NC		 4914
4915 return TRUE;
48229727 4916#undef MAXRELOCS
906e58ca
NC		 4917}
4918
48229727
JB		 4919/* Calculate the template, template size and instruction size for a stub.
4920 Return value is the instruction size. */
906e58ca 4921
48229727
JB		 4922static unsigned int
4923find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4924 const insn_sequence **stub_template,
4925 int *stub_template_size)
906e58ca 4926{
d3ce72d0 4927 const insn_sequence *template_sequence = NULL;
48229727
JB		 4928 int template_size = 0, i;
4929 unsigned int size;
906e58ca 4930
d3ce72d0 4931 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4932 if (stub_template)
4933 *stub_template = template_sequence;
4934
48229727 4935 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4936 if (stub_template_size)
4937 *stub_template_size = template_size;
906e58ca
NC		 4938
4939 size = 0;
461a49ca
DJ		 4940 for (i = 0; i < template_size; i++)
4941 {
d3ce72d0 4942 switch (template_sequence[i].type)
461a49ca
DJ		 4943 {
4944 case THUMB16_TYPE:
4945 size += 2;
4946 break;
4947
4948 case ARM_TYPE:
48229727 4949 case THUMB32_TYPE:
461a49ca
DJ		 4950 case DATA_TYPE:
4951 size += 4;
4952 break;
4953
4954 default:
4955 BFD_FAIL ();
2a229407 4956 return 0;
461a49ca
DJ		 4957 }
4958 }
4959
48229727
JB		 4960 return size;
4961}
4962
4963/* As above, but don't actually build the stub. Just bump offset so
4964 we know stub section sizes. */
4965
4966static bfd_boolean
4967arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4968 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4969{
4970 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4971 const insn_sequence *template_sequence;
48229727
JB		 4972 int template_size, size;
4973
4974 /* Massage our args to the form they really have. */
4975 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4976
4977 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4978 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4979
d3ce72d0 4980 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4981 &template_size);
4982
0955507f
TP		 4983 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4984 if (stub_entry->stub_template_size)
4985 {
4986 stub_entry->stub_size = size;
4987 stub_entry->stub_template = template_sequence;
4988 stub_entry->stub_template_size = template_size;
4989 }
4990
4991 /* Already accounted for. */
4992 if (stub_entry->stub_offset != (bfd_vma) -1)
4993 return TRUE;
461a49ca 4994
906e58ca
NC		 4995 size = (size + 7) & ~7;
4996 stub_entry->stub_sec->size += size;
461a49ca 4997
906e58ca
NC		 4998 return TRUE;
4999}
5000
5001/* External entry points for sizing and building linker stubs. */
5002
5003/* Set up various things so that we can make a list of input sections
5004 for each output section included in the link. Returns -1 on error,
5005 0 when no stubs will be needed, and 1 on success. */
5006
5007int
5008elf32_arm_setup_section_lists (bfd *output_bfd,
5009 struct bfd_link_info *info)
5010{
5011 bfd *input_bfd;
5012 unsigned int bfd_count;
7292b3ac 5013 unsigned int top_id, top_index;
906e58ca
NC		 5014 asection *section;
5015 asection **input_list, **list;
5016 bfd_size_type amt;
5017 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5018
4dfe6ac6
NC		 5019 if (htab == NULL)
5020 return 0;
906e58ca
NC		 5021 if (! is_elf_hash_table (htab))
5022 return 0;
5023
5024 /* Count the number of input BFDs and find the top input section id. */
5025 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5026 input_bfd != NULL;
c72f2fb2 5027 input_bfd = input_bfd->link.next)
906e58ca
NC		 5028 {
5029 bfd_count += 1;
5030 for (section = input_bfd->sections;
5031 section != NULL;
5032 section = section->next)
5033 {
5034 if (top_id < section->id)
5035 top_id = section->id;
5036 }
5037 }
5038 htab->bfd_count = bfd_count;
5039
5040 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5041 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5042 if (htab->stub_group == NULL)
5043 return -1;
fe33d2fa 5044 htab->top_id = top_id;
906e58ca
NC		 5045
5046 /* We can't use output_bfd->section_count here to find the top output
5047 section index as some sections may have been removed, and
5048 _bfd_strip_section_from_output doesn't renumber the indices. */
5049 for (section = output_bfd->sections, top_index = 0;
5050 section != NULL;
5051 section = section->next)
5052 {
5053 if (top_index < section->index)
5054 top_index = section->index;
5055 }
5056
5057 htab->top_index = top_index;
5058 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5059 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5060 htab->input_list = input_list;
5061 if (input_list == NULL)
5062 return -1;
5063
5064 /* For sections we aren't interested in, mark their entries with a
5065 value we can check later. */
5066 list = input_list + top_index;
5067 do
5068 *list = bfd_abs_section_ptr;
5069 while (list-- != input_list);
5070
5071 for (section = output_bfd->sections;
5072 section != NULL;
5073 section = section->next)
5074 {
5075 if ((section->flags & SEC_CODE) != 0)
5076 input_list[section->index] = NULL;
5077 }
5078
5079 return 1;
5080}
5081
5082/* The linker repeatedly calls this function for each input section,
5083 in the order that input sections are linked into output sections.
5084 Build lists of input sections to determine groupings between which
5085 we may insert linker stubs. */
5086
5087void
5088elf32_arm_next_input_section (struct bfd_link_info *info,
5089 asection *isec)
5090{
5091 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5092
4dfe6ac6
NC		 5093 if (htab == NULL)
5094 return;
5095
906e58ca
NC		 5096 if (isec->output_section->index <= htab->top_index)
5097 {
5098 asection **list = htab->input_list + isec->output_section->index;
5099
a7470592 5100 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5101 {
5102 /* Steal the link_sec pointer for our list. */
5103#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5104 /* This happens to make the list in reverse order,
07d72278 5105 which we reverse later. */
906e58ca
NC		 5106 PREV_SEC (isec) = *list;
5107 *list = isec;
5108 }
5109 }
5110}
5111
5112/* See whether we can group stub sections together. Grouping stub
5113 sections may result in fewer stubs. More importantly, we need to
07d72278 5114 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5115 .fini output sections respectively, because glibc splits the
5116 _init and _fini functions into multiple parts. Putting a stub in
5117 the middle of a function is not a good idea. */
5118
5119static void
5120group_sections (struct elf32_arm_link_hash_table *htab,
5121 bfd_size_type stub_group_size,
07d72278 5122 bfd_boolean stubs_always_after_branch)
906e58ca 5123{
07d72278 5124 asection **list = htab->input_list;
906e58ca
NC		 5125
5126 do
5127 {
5128 asection *tail = *list;
07d72278 5129 asection *head;
906e58ca
NC		 5130
5131 if (tail == bfd_abs_section_ptr)
5132 continue;
5133
07d72278
DJ		 5134 /* Reverse the list: we must avoid placing stubs at the
5135 beginning of the section because the beginning of the text
5136 section may be required for an interrupt vector in bare metal
5137 code. */
5138#define NEXT_SEC PREV_SEC
e780aef2
CL		 5139 head = NULL;
5140 while (tail != NULL)
99059e56
RM		 5141 {
5142 /* Pop from tail. */
5143 asection *item = tail;
5144 tail = PREV_SEC (item);
e780aef2 5145
99059e56
RM		 5146 /* Push on head. */
5147 NEXT_SEC (item) = head;
5148 head = item;
5149 }
07d72278
DJ		 5150
5151 while (head != NULL)
906e58ca
NC		 5152 {
5153 asection *curr;
07d72278 5154 asection *next;
e780aef2
CL		 5155 bfd_vma stub_group_start = head->output_offset;
5156 bfd_vma end_of_next;
906e58ca 5157
07d72278 5158 curr = head;
e780aef2 5159 while (NEXT_SEC (curr) != NULL)
8cd931b7 5160 {
e780aef2
CL		 5161 next = NEXT_SEC (curr);
5162 end_of_next = next->output_offset + next->size;
5163 if (end_of_next - stub_group_start >= stub_group_size)
5164 /* End of NEXT is too far from start, so stop. */
8cd931b7 5165 break;
e780aef2
CL		 5166 /* Add NEXT to the group. */
5167 curr = next;
8cd931b7 5168 }
906e58ca 5169
07d72278 5170 /* OK, the size from the start to the start of CURR is less
906e58ca 5171 than stub_group_size and thus can be handled by one stub
07d72278 5172 section. (Or the head section is itself larger than
906e58ca
NC		 5173 stub_group_size, in which case we may be toast.)
5174 We should really be keeping track of the total size of
5175 stubs added here, as stubs contribute to the final output
7fb9f789 5176 section size. */
906e58ca
NC		 5177 do
5178 {
07d72278 5179 next = NEXT_SEC (head);
906e58ca 5180 /* Set up this stub group. */
07d72278 5181 htab->stub_group[head->id].link_sec = curr;
906e58ca 5182 }
07d72278 5183 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5184
5185 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5186 bytes after the stub section can be handled by it too. */
5187 if (!stubs_always_after_branch)
906e58ca 5188 {
e780aef2
CL		 5189 stub_group_start = curr->output_offset + curr->size;
5190
8cd931b7 5191 while (next != NULL)
906e58ca 5192 {
e780aef2
CL		 5193 end_of_next = next->output_offset + next->size;
5194 if (end_of_next - stub_group_start >= stub_group_size)
5195 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5196 break;
e780aef2 5197 /* Add NEXT to the stub group. */
07d72278
DJ		 5198 head = next;
5199 next = NEXT_SEC (head);
5200 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5201 }
5202 }
07d72278 5203 head = next;
906e58ca
NC		 5204 }
5205 }
07d72278 5206 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5207
5208 free (htab->input_list);
5209#undef PREV_SEC
07d72278 5210#undef NEXT_SEC
906e58ca
NC		 5211}
5212
48229727
JB		 5213/* Comparison function for sorting/searching relocations relating to Cortex-A8
5214 erratum fix. */
5215
5216static int
5217a8_reloc_compare (const void *a, const void *b)
5218{
21d799b5
NC		 5219 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5220 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5221
5222 if (ra->from < rb->from)
5223 return -1;
5224 else if (ra->from > rb->from)
5225 return 1;
5226 else
5227 return 0;
5228}
5229
5230static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5231 const char *, char **);
5232
5233/* Helper function to scan code for sequences which might trigger the Cortex-A8
5234 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5235 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5236 otherwise. */
5237
81694485
NC		 5238static bfd_boolean
5239cortex_a8_erratum_scan (bfd *input_bfd,
5240 struct bfd_link_info *info,
48229727
JB		 5241 struct a8_erratum_fix **a8_fixes_p,
5242 unsigned int *num_a8_fixes_p,
5243 unsigned int *a8_fix_table_size_p,
5244 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5245 unsigned int num_a8_relocs,
5246 unsigned prev_num_a8_fixes,
5247 bfd_boolean *stub_changed_p)
48229727
JB		 5248{
5249 asection *section;
5250 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5251 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5252 unsigned int num_a8_fixes = *num_a8_fixes_p;
5253 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5254
4dfe6ac6
NC		 5255 if (htab == NULL)
5256 return FALSE;
5257
48229727
JB		 5258 for (section = input_bfd->sections;
5259 section != NULL;
5260 section = section->next)
5261 {
5262 bfd_byte *contents = NULL;
5263 struct _arm_elf_section_data *sec_data;
5264 unsigned int span;
5265 bfd_vma base_vma;
5266
5267 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5268 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5269 || (section->flags & SEC_EXCLUDE) != 0
5270 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5271 || (section->output_section == bfd_abs_section_ptr))
5272 continue;
48229727
JB		 5273
5274 base_vma = section->output_section->vma + section->output_offset;
5275
5276 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5277 contents = elf_section_data (section)->this_hdr.contents;
48229727 5278 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5279 return TRUE;
48229727
JB		 5280
5281 sec_data = elf32_arm_section_data (section);
5282
5283 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5284 {
5285 unsigned int span_start = sec_data->map[span].vma;
5286 unsigned int span_end = (span == sec_data->mapcount - 1)
5287 ? section->size : sec_data->map[span + 1].vma;
5288 unsigned int i;
5289 char span_type = sec_data->map[span].type;
5290 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5291
5292 if (span_type != 't')
5293 continue;
5294
5295 /* Span is entirely within a single 4KB region: skip scanning. */
5296 if (((base_vma + span_start) & ~0xfff)
48229727 5297 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5298 continue;
5299
5300 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5301
5302 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5303 * The branch target is in the same 4KB region as the
5304 first half of the branch.
5305 * The instruction before the branch is a 32-bit
5306 length non-branch instruction. */
5307 for (i = span_start; i < span_end;)
5308 {
5309 unsigned int insn = bfd_getl16 (&contents[i]);
5310 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5311 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5312
99059e56
RM		 5313 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5314 insn_32bit = TRUE;
48229727
JB		 5315
5316 if (insn_32bit)
99059e56
RM		 5317 {
5318 /* Load the rest of the insn (in manual-friendly order). */
5319 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5320
5321 /* Encoding T4: B<c>.W. */
5322 is_b = (insn & 0xf800d000) == 0xf0009000;
5323 /* Encoding T1: BL<c>.W. */
5324 is_bl = (insn & 0xf800d000) == 0xf000d000;
5325 /* Encoding T2: BLX<c>.W. */
5326 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5327 /* Encoding T3: B<c>.W (not permitted in IT block). */
5328 is_bcc = (insn & 0xf800d000) == 0xf0008000
5329 && (insn & 0x07f00000) != 0x03800000;
5330 }
5331
5332 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5333
99059e56 5334 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5335 && insn_32bit
5336 && is_32bit_branch
5337 && last_was_32bit
5338 && ! last_was_branch)
99059e56
RM		 5339 {
5340 bfd_signed_vma offset = 0;
5341 bfd_boolean force_target_arm = FALSE;
48229727 5342 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5343 bfd_vma target;
5344 enum elf32_arm_stub_type stub_type = arm_stub_none;
5345 struct a8_erratum_reloc key, *found;
5346 bfd_boolean use_plt = FALSE;
48229727 5347
99059e56
RM		 5348 key.from = base_vma + i;
5349 found = (struct a8_erratum_reloc *)
5350 bsearch (&key, a8_relocs, num_a8_relocs,
5351 sizeof (struct a8_erratum_reloc),
5352 &a8_reloc_compare);
48229727
JB		 5353
5354 if (found)
5355 {
5356 char *error_message = NULL;
5357 struct elf_link_hash_entry *entry;
5358
5359 /* We don't care about the error returned from this
99059e56 5360 function, only if there is glue or not. */
48229727
JB		 5361 entry = find_thumb_glue (info, found->sym_name,
5362 &error_message);
5363
5364 if (entry)
5365 found->non_a8_stub = TRUE;
5366
92750f34 5367 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5368 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5369 && found->hash->root.plt.offset != (bfd_vma) -1)
5370 use_plt = TRUE;
5371
5372 if (found->r_type == R_ARM_THM_CALL)
5373 {
35fc36a8
RS		 5374 if (found->branch_type == ST_BRANCH_TO_ARM
5375 || use_plt)
92750f34
DJ		 5376 force_target_arm = TRUE;
5377 else
5378 force_target_thumb = TRUE;
5379 }
48229727
JB		 5380 }
5381
99059e56 5382 /* Check if we have an offending branch instruction. */
48229727
JB		 5383
5384 if (found && found->non_a8_stub)
5385 /* We've already made a stub for this instruction, e.g.
5386 it's a long branch or a Thumb->ARM stub. Assume that
5387 stub will suffice to work around the A8 erratum (see
5388 setting of always_after_branch above). */
5389 ;
99059e56
RM		 5390 else if (is_bcc)
5391 {
5392 offset = (insn & 0x7ff) << 1;
5393 offset |= (insn & 0x3f0000) >> 4;
5394 offset |= (insn & 0x2000) ? 0x40000 : 0;
5395 offset |= (insn & 0x800) ? 0x80000 : 0;
5396 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5397 if (offset & 0x100000)
5398 offset |= ~ ((bfd_signed_vma) 0xfffff);
5399 stub_type = arm_stub_a8_veneer_b_cond;
5400 }
5401 else if (is_b || is_bl || is_blx)
5402 {
5403 int s = (insn & 0x4000000) != 0;
5404 int j1 = (insn & 0x2000) != 0;
5405 int j2 = (insn & 0x800) != 0;
5406 int i1 = !(j1 ^ s);
5407 int i2 = !(j2 ^ s);
5408
5409 offset = (insn & 0x7ff) << 1;
5410 offset |= (insn & 0x3ff0000) >> 4;
5411 offset |= i2 << 22;
5412 offset |= i1 << 23;
5413 offset |= s << 24;
5414 if (offset & 0x1000000)
5415 offset |= ~ ((bfd_signed_vma) 0xffffff);
5416
5417 if (is_blx)
5418 offset &= ~ ((bfd_signed_vma) 3);
5419
5420 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5421 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5422 }
5423
5424 if (stub_type != arm_stub_none)
5425 {
5426 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5427
5428 /* The original instruction is a BL, but the target is
99059e56 5429 an ARM instruction. If we were not making a stub,
48229727
JB		 5430 the BL would have been converted to a BLX. Use the
5431 BLX stub instead in that case. */
5432 if (htab->use_blx && force_target_arm
5433 && stub_type == arm_stub_a8_veneer_bl)
5434 {
5435 stub_type = arm_stub_a8_veneer_blx;
5436 is_blx = TRUE;
5437 is_bl = FALSE;
5438 }
5439 /* Conversely, if the original instruction was
5440 BLX but the target is Thumb mode, use the BL
5441 stub. */
5442 else if (force_target_thumb
5443 && stub_type == arm_stub_a8_veneer_blx)
5444 {
5445 stub_type = arm_stub_a8_veneer_bl;
5446 is_blx = FALSE;
5447 is_bl = TRUE;
5448 }
5449
99059e56
RM		 5450 if (is_blx)
5451 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5452
99059e56
RM		 5453 /* If we found a relocation, use the proper destination,
5454 not the offset in the (unrelocated) instruction.
48229727
JB		 5455 Note this is always done if we switched the stub type
5456 above. */
99059e56
RM		 5457 if (found)
5458 offset =
81694485 5459 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5460
99059e56
RM		 5461 /* If the stub will use a Thumb-mode branch to a
5462 PLT target, redirect it to the preceding Thumb
5463 entry point. */
5464 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5465 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5466
99059e56 5467 target = pc_for_insn + offset;
48229727 5468
99059e56
RM		 5469 /* The BLX stub is ARM-mode code. Adjust the offset to
5470 take the different PC value (+8 instead of +4) into
48229727 5471 account. */
99059e56
RM		 5472 if (stub_type == arm_stub_a8_veneer_blx)
5473 offset += 4;
5474
5475 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5476 {
5477 char *stub_name = NULL;
5478
5479 if (num_a8_fixes == a8_fix_table_size)
5480 {
5481 a8_fix_table_size *= 2;
5482 a8_fixes = (struct a8_erratum_fix *)
5483 bfd_realloc (a8_fixes,
5484 sizeof (struct a8_erratum_fix)
5485 * a8_fix_table_size);
5486 }
48229727 5487
eb7c4339
NS		 5488 if (num_a8_fixes < prev_num_a8_fixes)
5489 {
5490 /* If we're doing a subsequent scan,
5491 check if we've found the same fix as
5492 before, and try and reuse the stub
5493 name. */
5494 stub_name = a8_fixes[num_a8_fixes].stub_name;
5495 if ((a8_fixes[num_a8_fixes].section != section)
5496 || (a8_fixes[num_a8_fixes].offset != i))
5497 {
5498 free (stub_name);
5499 stub_name = NULL;
5500 *stub_changed_p = TRUE;
5501 }
5502 }
5503
5504 if (!stub_name)
5505 {
21d799b5 5506 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5507 if (stub_name != NULL)
5508 sprintf (stub_name, "%x:%x", section->id, i);
5509 }
48229727 5510
99059e56
RM		 5511 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5512 a8_fixes[num_a8_fixes].section = section;
5513 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5514 a8_fixes[num_a8_fixes].target_offset =
5515 target - base_vma;
99059e56
RM		 5516 a8_fixes[num_a8_fixes].orig_insn = insn;
5517 a8_fixes[num_a8_fixes].stub_name = stub_name;
5518 a8_fixes[num_a8_fixes].stub_type = stub_type;
5519 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5520 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5521
99059e56
RM		 5522 num_a8_fixes++;
5523 }
5524 }
5525 }
48229727 5526
99059e56
RM		 5527 i += insn_32bit ? 4 : 2;
5528 last_was_32bit = insn_32bit;
48229727 5529 last_was_branch = is_32bit_branch;
99059e56
RM		 5530 }
5531 }
48229727
JB		 5532
5533 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5534 free (contents);
48229727 5535 }
fe33d2fa 5536
48229727
JB		 5537 *a8_fixes_p = a8_fixes;
5538 *num_a8_fixes_p = num_a8_fixes;
5539 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5540
81694485 5541 return FALSE;
48229727
JB		 5542}
5543
b715f643
TP		 5544/* Create or update a stub entry depending on whether the stub can already be
5545 found in HTAB. The stub is identified by:
5546 - its type STUB_TYPE
5547 - its source branch (note that several can share the same stub) whose
5548 section and relocation (if any) are given by SECTION and IRELA
5549 respectively
5550 - its target symbol whose input section, hash, name, value and branch type
5551 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5552 respectively
5553
5554 If found, the value of the stub's target symbol is updated from SYM_VALUE
5555 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5556 TRUE and the stub entry is initialized.
5557
0955507f
TP		 5558 Returns the stub that was created or updated, or NULL if an error
5559 occurred. */
b715f643 5560
0955507f 5561static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5562elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5563 enum elf32_arm_stub_type stub_type, asection *section,
5564 Elf_Internal_Rela *irela, asection *sym_sec,
5565 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5566 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5567 bfd_boolean *new_stub)
5568{
5569 const asection *id_sec;
5570 char *stub_name;
5571 struct elf32_arm_stub_hash_entry *stub_entry;
5572 unsigned int r_type;
4f4faa4d 5573 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5574
5575 BFD_ASSERT (stub_type != arm_stub_none);
5576 *new_stub = FALSE;
5577
4f4faa4d
TP		 5578 if (sym_claimed)
5579 stub_name = sym_name;
5580 else
5581 {
5582 BFD_ASSERT (irela);
5583 BFD_ASSERT (section);
c2abbbeb 5584 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5585
4f4faa4d
TP		 5586 /* Support for grouping stub sections. */
5587 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5588
4f4faa4d
TP		 5589 /* Get the name of this stub. */
5590 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5591 stub_type);
5592 if (!stub_name)
0955507f 5593 return NULL;
4f4faa4d 5594 }
b715f643
TP		 5595
5596 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5597 FALSE);
5598 /* The proper stub has already been created, just update its value. */
5599 if (stub_entry != NULL)
5600 {
4f4faa4d
TP		 5601 if (!sym_claimed)
5602 free (stub_name);
b715f643 5603 stub_entry->target_value = sym_value;
0955507f 5604 return stub_entry;
b715f643
TP		 5605 }
5606
daa4adae 5607 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5608 if (stub_entry == NULL)
5609 {
4f4faa4d
TP		 5610 if (!sym_claimed)
5611 free (stub_name);
0955507f 5612 return NULL;
b715f643
TP		 5613 }
5614
5615 stub_entry->target_value = sym_value;
5616 stub_entry->target_section = sym_sec;
5617 stub_entry->stub_type = stub_type;
5618 stub_entry->h = hash;
5619 stub_entry->branch_type = branch_type;
5620
4f4faa4d
TP		 5621 if (sym_claimed)
5622 stub_entry->output_name = sym_name;
5623 else
b715f643 5624 {
4f4faa4d
TP		 5625 if (sym_name == NULL)
5626 sym_name = "unnamed";
5627 stub_entry->output_name = (char *)
5628 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5629 + strlen (sym_name));
5630 if (stub_entry->output_name == NULL)
5631 {
5632 free (stub_name);
0955507f 5633 return NULL;
4f4faa4d 5634 }
b715f643 5635
4f4faa4d
TP		 5636 /* For historical reasons, use the existing names for ARM-to-Thumb and
5637 Thumb-to-ARM stubs. */
5638 r_type = ELF32_R_TYPE (irela->r_info);
5639 if ((r_type == (unsigned int) R_ARM_THM_CALL
5640 || r_type == (unsigned int) R_ARM_THM_JUMP24
5641 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5642 && branch_type == ST_BRANCH_TO_ARM)
5643 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5644 else if ((r_type == (unsigned int) R_ARM_CALL
5645 || r_type == (unsigned int) R_ARM_JUMP24)
5646 && branch_type == ST_BRANCH_TO_THUMB)
5647 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5648 else
5649 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5650 }
b715f643
TP		 5651
5652 *new_stub = TRUE;
0955507f 5653 return stub_entry;
b715f643
TP		 5654}
5655
4ba2ef8f
TP		 5656/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5657 gateway veneer to transition from non secure to secure state and create them
5658 accordingly.
5659
5660 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5661 defines the conditions that govern Secure Gateway veneer creation for a
5662 given symbol <SYM> as follows:
5663 - it has function type
5664 - it has non local binding
5665 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5666 same type, binding and value as <SYM> (called normal symbol).
5667 An entry function can handle secure state transition itself in which case
5668 its special symbol would have a different value from the normal symbol.
5669
5670 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5671 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5672 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5673 created.
4ba2ef8f 5674
0955507f 5675 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5676
5677static bfd_boolean
5678cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5679 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5680 int *cmse_stub_created)
4ba2ef8f
TP		 5681{
5682 const struct elf_backend_data *bed;
5683 Elf_Internal_Shdr *symtab_hdr;
5684 unsigned i, j, sym_count, ext_start;
5685 Elf_Internal_Sym *cmse_sym, *local_syms;
5686 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5687 enum arm_st_branch_type branch_type;
5688 char *sym_name, *lsym_name;
5689 bfd_vma sym_value;
5690 asection *section;
0955507f
TP		 5691 struct elf32_arm_stub_hash_entry *stub_entry;
5692 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5693
5694 bed = get_elf_backend_data (input_bfd);
5695 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5696 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5697 ext_start = symtab_hdr->sh_info;
5698 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5699 && out_attr[Tag_CPU_arch_profile].i == 'M');
5700
5701 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5702 if (local_syms == NULL)
5703 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5704 symtab_hdr->sh_info, 0, NULL, NULL,
5705 NULL);
5706 if (symtab_hdr->sh_info && local_syms == NULL)
5707 return FALSE;
5708
5709 /* Scan symbols. */
5710 for (i = 0; i < sym_count; i++)
5711 {
5712 cmse_invalid = FALSE;
5713
5714 if (i < ext_start)
5715 {
5716 cmse_sym = &local_syms[i];
5717 /* Not a special symbol. */
5718 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5719 continue;
5720 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5721 symtab_hdr->sh_link,
5722 cmse_sym->st_name);
5723 /* Special symbol with local binding. */
5724 cmse_invalid = TRUE;
5725 }
5726 else
5727 {
5728 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5729 sym_name = (char *) cmse_hash->root.root.root.string;
5730
5731 /* Not a special symbol. */
5732 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5733 continue;
5734
5735 /* Special symbol has incorrect binding or type. */
5736 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5737 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5738 || cmse_hash->root.type != STT_FUNC)
5739 cmse_invalid = TRUE;
5740 }
5741
5742 if (!is_v8m)
5743 {
90b6238f
AM		 5744 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5745 "ARMv8-M architecture or later"),
4eca0228 5746 input_bfd, sym_name);
4ba2ef8f
TP		 5747 is_v8m = TRUE; /* Avoid multiple warning. */
5748 ret = FALSE;
5749 }
5750
5751 if (cmse_invalid)
5752 {
90b6238f
AM		 5753 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
5754 " a global or weak function symbol"),
4eca0228 5755 input_bfd, sym_name);
4ba2ef8f
TP		 5756 ret = FALSE;
5757 if (i < ext_start)
5758 continue;
5759 }
5760
5761 sym_name += strlen (CMSE_PREFIX);
5762 hash = (struct elf32_arm_link_hash_entry *)
5763 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5764
5765 /* No associated normal symbol or it is neither global nor weak. */
5766 if (!hash
5767 || (hash->root.root.type != bfd_link_hash_defined
5768 && hash->root.root.type != bfd_link_hash_defweak)
5769 || hash->root.type != STT_FUNC)
5770 {
5771 /* Initialize here to avoid warning about use of possibly
5772 uninitialized variable. */
5773 j = 0;
5774
5775 if (!hash)
5776 {
5777 /* Searching for a normal symbol with local binding. */
5778 for (; j < ext_start; j++)
5779 {
5780 lsym_name =
5781 bfd_elf_string_from_elf_section (input_bfd,
5782 symtab_hdr->sh_link,
5783 local_syms[j].st_name);
5784 if (!strcmp (sym_name, lsym_name))
5785 break;
5786 }
5787 }
5788
5789 if (hash || j < ext_start)
5790 {
4eca0228 5791 _bfd_error_handler
90b6238f
AM		 5792 (_("%pB: invalid standard symbol `%s'; it must be "
5793 "a global or weak function symbol"),
5794 input_bfd, sym_name);
4ba2ef8f
TP		 5795 }
5796 else
4eca0228 5797 _bfd_error_handler
90b6238f 5798 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 5799 ret = FALSE;
5800 if (!hash)
5801 continue;
5802 }
5803
5804 sym_value = hash->root.root.u.def.value;
5805 section = hash->root.root.u.def.section;
5806
5807 if (cmse_hash->root.root.u.def.section != section)
5808 {
4eca0228 5809 _bfd_error_handler
90b6238f 5810 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 5811 input_bfd, sym_name);
5812 ret = FALSE;
5813 }
5814 if (cmse_hash->root.root.u.def.value != sym_value)
5815 continue; /* Ignore: could be an entry function starting with SG. */
5816
5817 /* If this section is a link-once section that will be discarded, then
5818 don't create any stubs. */
5819 if (section->output_section == NULL)
5820 {
4eca0228 5821 _bfd_error_handler
90b6238f 5822 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 5823 continue;
5824 }
5825
5826 if (hash->root.size == 0)
5827 {
4eca0228 5828 _bfd_error_handler
90b6238f 5829 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 5830 ret = FALSE;
5831 }
5832
5833 if (!ret)
5834 continue;
5835 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5836 stub_entry
4ba2ef8f
TP		 5837 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5838 NULL, NULL, section, hash, sym_name,
5839 sym_value, branch_type, &new_stub);
5840
0955507f 5841 if (stub_entry == NULL)
4ba2ef8f
TP		 5842 ret = FALSE;
5843 else
5844 {
5845 BFD_ASSERT (new_stub);
0955507f 5846 (*cmse_stub_created)++;
4ba2ef8f
TP		 5847 }
5848 }
5849
5850 if (!symtab_hdr->contents)
5851 free (local_syms);
5852 return ret;
5853}
5854
0955507f
TP		 5855/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5856 code entry function, ie can be called from non secure code without using a
5857 veneer. */
5858
5859static bfd_boolean
5860cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5861{
42484486 5862 bfd_byte contents[4];
0955507f
TP		 5863 uint32_t first_insn;
5864 asection *section;
5865 file_ptr offset;
5866 bfd *abfd;
5867
5868 /* Defined symbol of function type. */
5869 if (hash->root.root.type != bfd_link_hash_defined
5870 && hash->root.root.type != bfd_link_hash_defweak)
5871 return FALSE;
5872 if (hash->root.type != STT_FUNC)
5873 return FALSE;
5874
5875 /* Read first instruction. */
5876 section = hash->root.root.u.def.section;
5877 abfd = section->owner;
5878 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5879 if (!bfd_get_section_contents (abfd, section, contents, offset,
5880 sizeof (contents)))
0955507f
TP		 5881 return FALSE;
5882
42484486
TP		 5883 first_insn = bfd_get_32 (abfd, contents);
5884
5885 /* Starts by SG instruction. */
0955507f
TP		 5886 return first_insn == 0xe97fe97f;
5887}
5888
5889/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5890 secure gateway veneers (ie. the veneers was not in the input import library)
5891 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5892
5893static bfd_boolean
5894arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5895{
5896 struct elf32_arm_stub_hash_entry *stub_entry;
5897 struct bfd_link_info *info;
5898
5899 /* Massage our args to the form they really have. */
5900 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5901 info = (struct bfd_link_info *) gen_info;
5902
5903 if (info->out_implib_bfd)
5904 return TRUE;
5905
5906 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5907 return TRUE;
5908
5909 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5910 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5911
5912 return TRUE;
5913}
5914
5915/* Set offset of each secure gateway veneers so that its address remain
5916 identical to the one in the input import library referred by
5917 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5918 (present in input import library but absent from the executable being
5919 linked) or if new veneers appeared and there is no output import library
5920 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5921 number of secure gateway veneers found in the input import library.
5922
5923 The function returns whether an error occurred. If no error occurred,
5924 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5925 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5926 veneer observed set for new veneers to be layed out after. */
5927
5928static bfd_boolean
5929set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5930 struct elf32_arm_link_hash_table *htab,
5931 int *cmse_stub_created)
5932{
5933 long symsize;
5934 char *sym_name;
5935 flagword flags;
5936 long i, symcount;
5937 bfd *in_implib_bfd;
5938 asection *stub_out_sec;
5939 bfd_boolean ret = TRUE;
5940 Elf_Internal_Sym *intsym;
5941 const char *out_sec_name;
5942 bfd_size_type cmse_stub_size;
5943 asymbol **sympp = NULL, *sym;
5944 struct elf32_arm_link_hash_entry *hash;
5945 const insn_sequence *cmse_stub_template;
5946 struct elf32_arm_stub_hash_entry *stub_entry;
5947 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5948 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5949 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5950
5951 /* No input secure gateway import library. */
5952 if (!htab->in_implib_bfd)
5953 return TRUE;
5954
5955 in_implib_bfd = htab->in_implib_bfd;
5956 if (!htab->cmse_implib)
5957 {
871b3ab2 5958 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 5959 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 5960 return FALSE;
5961 }
5962
5963 /* Get symbol table size. */
5964 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5965 if (symsize < 0)
5966 return FALSE;
5967
5968 /* Read in the input secure gateway import library's symbol table. */
5969 sympp = (asymbol **) xmalloc (symsize);
5970 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5971 if (symcount < 0)
5972 {
5973 ret = FALSE;
5974 goto free_sym_buf;
5975 }
5976
5977 htab->new_cmse_stub_offset = 0;
5978 cmse_stub_size =
5979 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5980 &cmse_stub_template,
5981 &cmse_stub_template_size);
5982 out_sec_name =
5983 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5984 stub_out_sec =
5985 bfd_get_section_by_name (htab->obfd, out_sec_name);
5986 if (stub_out_sec != NULL)
5987 cmse_stub_sec_vma = stub_out_sec->vma;
5988
5989 /* Set addresses of veneers mentionned in input secure gateway import
5990 library's symbol table. */
5991 for (i = 0; i < symcount; i++)
5992 {
5993 sym = sympp[i];
5994 flags = sym->flags;
5995 sym_name = (char *) bfd_asymbol_name (sym);
5996 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5997
5998 if (sym->section != bfd_abs_section_ptr
5999 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6000 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6001 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6002 != ST_BRANCH_TO_THUMB))
6003 {
90b6238f
AM		 6004 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6005 "symbol should be absolute, global and "
6006 "refer to Thumb functions"),
4eca0228 6007 in_implib_bfd, sym_name);
0955507f
TP		 6008 ret = FALSE;
6009 continue;
6010 }
6011
6012 veneer_value = bfd_asymbol_value (sym);
6013 stub_offset = veneer_value - cmse_stub_sec_vma;
6014 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6015 FALSE, FALSE);
6016 hash = (struct elf32_arm_link_hash_entry *)
6017 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6018
6019 /* Stub entry should have been created by cmse_scan or the symbol be of
6020 a secure function callable from non secure code. */
6021 if (!stub_entry && !hash)
6022 {
6023 bfd_boolean new_stub;
6024
4eca0228 6025 _bfd_error_handler
90b6238f 6026 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6027 hash = (struct elf32_arm_link_hash_entry *)
6028 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6029 stub_entry
6030 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6031 NULL, NULL, bfd_abs_section_ptr, hash,
6032 sym_name, veneer_value,
6033 ST_BRANCH_TO_THUMB, &new_stub);
6034 if (stub_entry == NULL)
6035 ret = FALSE;
6036 else
6037 {
6038 BFD_ASSERT (new_stub);
6039 new_cmse_stubs_created++;
6040 (*cmse_stub_created)++;
6041 }
6042 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6043 stub_entry->stub_offset = stub_offset;
6044 }
6045 /* Symbol found is not callable from non secure code. */
6046 else if (!stub_entry)
6047 {
6048 if (!cmse_entry_fct_p (hash))
6049 {
90b6238f 6050 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6051 sym_name);
0955507f
TP		 6052 ret = FALSE;
6053 }
6054 continue;
6055 }
6056 else
6057 {
6058 /* Only stubs for SG veneers should have been created. */
6059 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6060
6061 /* Check visibility hasn't changed. */
6062 if (!!(flags & BSF_GLOBAL)
6063 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6064 _bfd_error_handler
90b6238f 6065 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6066 sym_name);
6067
6068 stub_entry->stub_offset = stub_offset;
6069 }
6070
6071 /* Size should match that of a SG veneer. */
6072 if (intsym->st_size != cmse_stub_size)
6073 {
90b6238f 6074 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6075 in_implib_bfd, sym_name);
0955507f
TP		 6076 ret = FALSE;
6077 }
6078
6079 /* Previous veneer address is before current SG veneer section. */
6080 if (veneer_value < cmse_stub_sec_vma)
6081 {
6082 /* Avoid offset underflow. */
6083 if (stub_entry)
6084 stub_entry->stub_offset = 0;
6085 stub_offset = 0;
6086 ret = FALSE;
6087 }
6088
6089 /* Complain if stub offset not a multiple of stub size. */
6090 if (stub_offset % cmse_stub_size)
6091 {
4eca0228 6092 _bfd_error_handler
90b6238f
AM		 6093 (_("offset of veneer for entry function `%s' not a multiple of "
6094 "its size"), sym_name);
0955507f
TP		 6095 ret = FALSE;
6096 }
6097
6098 if (!ret)
6099 continue;
6100
6101 new_cmse_stubs_created--;
6102 if (veneer_value < cmse_stub_array_start)
6103 cmse_stub_array_start = veneer_value;
6104 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6105 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6106 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6107 }
6108
6109 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6110 {
6111 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6112 _bfd_error_handler
0955507f
TP		 6113 (_("new entry function(s) introduced but no output import library "
6114 "specified:"));
6115 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6116 }
6117
6118 if (cmse_stub_array_start != cmse_stub_sec_vma)
6119 {
4eca0228 6120 _bfd_error_handler
90b6238f 6121 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6122 out_sec_name);
6123 ret = FALSE;
6124 }
6125
6126free_sym_buf:
6127 free (sympp);
6128 return ret;
6129}
6130
906e58ca
NC		 6131/* Determine and set the size of the stub section for a final link.
6132
6133 The basic idea here is to examine all the relocations looking for
6134 PC-relative calls to a target that is unreachable with a "bl"
6135 instruction. */
6136
6137bfd_boolean
6138elf32_arm_size_stubs (bfd *output_bfd,
6139 bfd *stub_bfd,
6140 struct bfd_link_info *info,
6141 bfd_signed_vma group_size,
7a89b94e 6142 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6143 asection *,
7a89b94e 6144 unsigned int),
906e58ca
NC		 6145 void (*layout_sections_again) (void))
6146{
0955507f 6147 bfd_boolean ret = TRUE;
4ba2ef8f 6148 obj_attribute *out_attr;
0955507f 6149 int cmse_stub_created = 0;
906e58ca 6150 bfd_size_type stub_group_size;
4ba2ef8f 6151 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6152 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6153 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6154 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6155 struct a8_erratum_reloc *a8_relocs = NULL;
6156 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6157
4dfe6ac6
NC		 6158 if (htab == NULL)
6159 return FALSE;
6160
48229727
JB		 6161 if (htab->fix_cortex_a8)
6162 {
21d799b5 6163 a8_fixes = (struct a8_erratum_fix *)
99059e56 6164 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6165 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6166 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6167 }
906e58ca
NC		 6168
6169 /* Propagate mach to stub bfd, because it may not have been
6170 finalized when we created stub_bfd. */
6171 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6172 bfd_get_mach (output_bfd));
6173
6174 /* Stash our params away. */
6175 htab->stub_bfd = stub_bfd;
6176 htab->add_stub_section = add_stub_section;
6177 htab->layout_sections_again = layout_sections_again;
07d72278 6178 stubs_always_after_branch = group_size < 0;
48229727 6179
4ba2ef8f
TP		 6180 out_attr = elf_known_obj_attributes_proc (output_bfd);
6181 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6182
48229727
JB		 6183 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6184 as the first half of a 32-bit branch straddling two 4K pages. This is a
6185 crude way of enforcing that. */
6186 if (htab->fix_cortex_a8)
6187 stubs_always_after_branch = 1;
6188
906e58ca
NC		 6189 if (group_size < 0)
6190 stub_group_size = -group_size;
6191 else
6192 stub_group_size = group_size;
6193
6194 if (stub_group_size == 1)
6195 {
6196 /* Default values. */
6197 /* Thumb branch range is +-4MB has to be used as the default
6198 maximum size (a given section can contain both ARM and Thumb
6199 code, so the worst case has to be taken into account).
6200
6201 This value is 24K less than that, which allows for 2025
6202 12-byte stubs. If we exceed that, then we will fail to link.
6203 The user will have to relink with an explicit group size
6204 option. */
6205 stub_group_size = 4170000;
6206 }
6207
07d72278 6208 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6209
3ae046cc
NS		 6210 /* If we're applying the cortex A8 fix, we need to determine the
6211 program header size now, because we cannot change it later --
6212 that could alter section placements. Notice the A8 erratum fix
6213 ends up requiring the section addresses to remain unchanged
6214 modulo the page size. That's something we cannot represent
6215 inside BFD, and we don't want to force the section alignment to
6216 be the page size. */
6217 if (htab->fix_cortex_a8)
6218 (*htab->layout_sections_again) ();
6219
906e58ca
NC		 6220 while (1)
6221 {
6222 bfd *input_bfd;
6223 unsigned int bfd_indx;
6224 asection *stub_sec;
d7c5bd02 6225 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6226 bfd_boolean stub_changed = FALSE;
6227 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6228
48229727 6229 num_a8_fixes = 0;
906e58ca
NC		 6230 for (input_bfd = info->input_bfds, bfd_indx = 0;
6231 input_bfd != NULL;
c72f2fb2 6232 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6233 {
6234 Elf_Internal_Shdr *symtab_hdr;
6235 asection *section;
6236 Elf_Internal_Sym *local_syms = NULL;
6237
99059e56
RM		 6238 if (!is_arm_elf (input_bfd))
6239 continue;
adbcc655 6240
48229727
JB		 6241 num_a8_relocs = 0;
6242
906e58ca
NC		 6243 /* We'll need the symbol table in a second. */
6244 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6245 if (symtab_hdr->sh_info == 0)
6246 continue;
6247
4ba2ef8f
TP		 6248 /* Limit scan of symbols to object file whose profile is
6249 Microcontroller to not hinder performance in the general case. */
6250 if (m_profile && first_veneer_scan)
6251 {
6252 struct elf_link_hash_entry **sym_hashes;
6253
6254 sym_hashes = elf_sym_hashes (input_bfd);
6255 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6256 &cmse_stub_created))
4ba2ef8f 6257 goto error_ret_free_local;
0955507f
TP		 6258
6259 if (cmse_stub_created != 0)
6260 stub_changed = TRUE;
4ba2ef8f
TP		 6261 }
6262
906e58ca
NC		 6263 /* Walk over each section attached to the input bfd. */
6264 for (section = input_bfd->sections;
6265 section != NULL;
6266 section = section->next)
6267 {
6268 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6269
6270 /* If there aren't any relocs, then there's nothing more
6271 to do. */
6272 if ((section->flags & SEC_RELOC) == 0
6273 || section->reloc_count == 0
6274 || (section->flags & SEC_CODE) == 0)
6275 continue;
6276
6277 /* If this section is a link-once section that will be
6278 discarded, then don't create any stubs. */
6279 if (section->output_section == NULL
6280 || section->output_section->owner != output_bfd)
6281 continue;
6282
6283 /* Get the relocs. */
6284 internal_relocs
6285 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6286 NULL, info->keep_memory);
6287 if (internal_relocs == NULL)
6288 goto error_ret_free_local;
6289
6290 /* Now examine each relocation. */
6291 irela = internal_relocs;
6292 irelaend = irela + section->reloc_count;
6293 for (; irela < irelaend; irela++)
6294 {
6295 unsigned int r_type, r_indx;
906e58ca
NC		 6296 asection *sym_sec;
6297 bfd_vma sym_value;
6298 bfd_vma destination;
6299 struct elf32_arm_link_hash_entry *hash;
7413f23f 6300 const char *sym_name;
34e77a92 6301 unsigned char st_type;
35fc36a8 6302 enum arm_st_branch_type branch_type;
48229727 6303 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6304
6305 r_type = ELF32_R_TYPE (irela->r_info);
6306 r_indx = ELF32_R_SYM (irela->r_info);
6307
6308 if (r_type >= (unsigned int) R_ARM_max)
6309 {
6310 bfd_set_error (bfd_error_bad_value);
6311 error_ret_free_internal:
6312 if (elf_section_data (section)->relocs == NULL)
6313 free (internal_relocs);
15dd01b1
TP		 6314 /* Fall through. */
6315 error_ret_free_local:
6316 if (local_syms != NULL
6317 && (symtab_hdr->contents
6318 != (unsigned char *) local_syms))
6319 free (local_syms);
6320 return FALSE;
906e58ca 6321 }
b38cadfb 6322
0855e32b
NS		 6323 hash = NULL;
6324 if (r_indx >= symtab_hdr->sh_info)
6325 hash = elf32_arm_hash_entry
6326 (elf_sym_hashes (input_bfd)
6327 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6328
0855e32b
NS		 6329 /* Only look for stubs on branch instructions, or
6330 non-relaxed TLSCALL */
906e58ca 6331 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6332 && (r_type != (unsigned int) R_ARM_THM_CALL)
6333 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6334 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6335 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6336 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6337 && (r_type != (unsigned int) R_ARM_PLT32)
6338 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6339 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6340 && r_type == elf32_arm_tls_transition
6341 (info, r_type, &hash->root)
6342 && ((hash ? hash->tls_type
6343 : (elf32_arm_local_got_tls_type
6344 (input_bfd)[r_indx]))
6345 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6346 continue;
6347
6348 /* Now determine the call target, its name, value,
6349 section. */
6350 sym_sec = NULL;
6351 sym_value = 0;
6352 destination = 0;
7413f23f 6353 sym_name = NULL;
b38cadfb 6354
0855e32b
NS		 6355 if (r_type == (unsigned int) R_ARM_TLS_CALL
6356 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6357 {
6358 /* A non-relaxed TLS call. The target is the
6359 plt-resident trampoline and nothing to do
6360 with the symbol. */
6361 BFD_ASSERT (htab->tls_trampoline > 0);
6362 sym_sec = htab->root.splt;
6363 sym_value = htab->tls_trampoline;
6364 hash = 0;
34e77a92 6365 st_type = STT_FUNC;
35fc36a8 6366 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6367 }
6368 else if (!hash)
906e58ca
NC		 6369 {
6370 /* It's a local symbol. */
6371 Elf_Internal_Sym *sym;
906e58ca
NC		 6372
6373 if (local_syms == NULL)
6374 {
6375 local_syms
6376 = (Elf_Internal_Sym *) symtab_hdr->contents;
6377 if (local_syms == NULL)
6378 local_syms
6379 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6380 symtab_hdr->sh_info, 0,
6381 NULL, NULL, NULL);
6382 if (local_syms == NULL)
6383 goto error_ret_free_internal;
6384 }
6385
6386 sym = local_syms + r_indx;
f6d250ce
TS		 6387 if (sym->st_shndx == SHN_UNDEF)
6388 sym_sec = bfd_und_section_ptr;
6389 else if (sym->st_shndx == SHN_ABS)
6390 sym_sec = bfd_abs_section_ptr;
6391 else if (sym->st_shndx == SHN_COMMON)
6392 sym_sec = bfd_com_section_ptr;
6393 else
6394 sym_sec =
6395 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6396
ffcb4889
NS		 6397 if (!sym_sec)
6398 /* This is an undefined symbol. It can never
6a631e86 6399 be resolved. */
ffcb4889 6400 continue;
fe33d2fa 6401
906e58ca
NC		 6402 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6403 sym_value = sym->st_value;
6404 destination = (sym_value + irela->r_addend
6405 + sym_sec->output_offset
6406 + sym_sec->output_section->vma);
34e77a92 6407 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6408 branch_type =
6409 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6410 sym_name
6411 = bfd_elf_string_from_elf_section (input_bfd,
6412 symtab_hdr->sh_link,
6413 sym->st_name);
906e58ca
NC		 6414 }
6415 else
6416 {
6417 /* It's an external symbol. */
906e58ca
NC		 6418 while (hash->root.root.type == bfd_link_hash_indirect
6419 || hash->root.root.type == bfd_link_hash_warning)
6420 hash = ((struct elf32_arm_link_hash_entry *)
6421 hash->root.root.u.i.link);
6422
6423 if (hash->root.root.type == bfd_link_hash_defined
6424 || hash->root.root.type == bfd_link_hash_defweak)
6425 {
6426 sym_sec = hash->root.root.u.def.section;
6427 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6428
6429 struct elf32_arm_link_hash_table *globals =
6430 elf32_arm_hash_table (info);
6431
6432 /* For a destination in a shared library,
6433 use the PLT stub as target address to
6434 decide whether a branch stub is
6435 needed. */
4dfe6ac6 6436 if (globals != NULL
362d30a1 6437 && globals->root.splt != NULL
4dfe6ac6 6438 && hash != NULL
022f8312
CL		 6439 && hash->root.plt.offset != (bfd_vma) -1)
6440 {
362d30a1 6441 sym_sec = globals->root.splt;
022f8312
CL		 6442 sym_value = hash->root.plt.offset;
6443 if (sym_sec->output_section != NULL)
6444 destination = (sym_value
6445 + sym_sec->output_offset
6446 + sym_sec->output_section->vma);
6447 }
6448 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6449 destination = (sym_value + irela->r_addend
6450 + sym_sec->output_offset
6451 + sym_sec->output_section->vma);
6452 }
69c5861e
CL		 6453 else if ((hash->root.root.type == bfd_link_hash_undefined)
6454 || (hash->root.root.type == bfd_link_hash_undefweak))
6455 {
6456 /* For a shared library, use the PLT stub as
6457 target address to decide whether a long
6458 branch stub is needed.
6459 For absolute code, they cannot be handled. */
6460 struct elf32_arm_link_hash_table *globals =
6461 elf32_arm_hash_table (info);
6462
4dfe6ac6 6463 if (globals != NULL
362d30a1 6464 && globals->root.splt != NULL
4dfe6ac6 6465 && hash != NULL
69c5861e
CL		 6466 && hash->root.plt.offset != (bfd_vma) -1)
6467 {
362d30a1 6468 sym_sec = globals->root.splt;
69c5861e
CL		 6469 sym_value = hash->root.plt.offset;
6470 if (sym_sec->output_section != NULL)
6471 destination = (sym_value
6472 + sym_sec->output_offset
6473 + sym_sec->output_section->vma);
6474 }
6475 else
6476 continue;
6477 }
906e58ca
NC		 6478 else
6479 {
6480 bfd_set_error (bfd_error_bad_value);
6481 goto error_ret_free_internal;
6482 }
34e77a92 6483 st_type = hash->root.type;
39d911fc
TP		 6484 branch_type =
6485 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6486 sym_name = hash->root.root.root.string;
906e58ca
NC		 6487 }
6488
48229727 6489 do
7413f23f 6490 {
b715f643 6491 bfd_boolean new_stub;
0955507f 6492 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6493
48229727
JB		 6494 /* Determine what (if any) linker stub is needed. */
6495 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6496 st_type, &branch_type,
6497 hash, destination, sym_sec,
48229727
JB		 6498 input_bfd, sym_name);
6499 if (stub_type == arm_stub_none)
6500 break;
6501
48229727
JB		 6502 /* We've either created a stub for this reloc already,
6503 or we are about to. */
0955507f 6504 stub_entry =
b715f643
TP		 6505 elf32_arm_create_stub (htab, stub_type, section, irela,
6506 sym_sec, hash,
6507 (char *) sym_name, sym_value,
6508 branch_type, &new_stub);
7413f23f 6509
0955507f 6510 created_stub = stub_entry != NULL;
b715f643
TP		 6511 if (!created_stub)
6512 goto error_ret_free_internal;
6513 else if (!new_stub)
6514 break;
99059e56 6515 else
b715f643 6516 stub_changed = TRUE;
99059e56
RM		 6517 }
6518 while (0);
6519
6520 /* Look for relocations which might trigger Cortex-A8
6521 erratum. */
6522 if (htab->fix_cortex_a8
6523 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6524 || r_type == (unsigned int) R_ARM_THM_JUMP19
6525 || r_type == (unsigned int) R_ARM_THM_CALL
6526 || r_type == (unsigned int) R_ARM_THM_XPC22))
6527 {
6528 bfd_vma from = section->output_section->vma
6529 + section->output_offset
6530 + irela->r_offset;
6531
6532 if ((from & 0xfff) == 0xffe)
6533 {
6534 /* Found a candidate. Note we haven't checked the
6535 destination is within 4K here: if we do so (and
6536 don't create an entry in a8_relocs) we can't tell
6537 that a branch should have been relocated when
6538 scanning later. */
6539 if (num_a8_relocs == a8_reloc_table_size)
6540 {
6541 a8_reloc_table_size *= 2;
6542 a8_relocs = (struct a8_erratum_reloc *)
6543 bfd_realloc (a8_relocs,
6544 sizeof (struct a8_erratum_reloc)
6545 * a8_reloc_table_size);
6546 }
6547
6548 a8_relocs[num_a8_relocs].from = from;
6549 a8_relocs[num_a8_relocs].destination = destination;
6550 a8_relocs[num_a8_relocs].r_type = r_type;
6551 a8_relocs[num_a8_relocs].branch_type = branch_type;
6552 a8_relocs[num_a8_relocs].sym_name = sym_name;
6553 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6554 a8_relocs[num_a8_relocs].hash = hash;
6555
6556 num_a8_relocs++;
6557 }
6558 }
906e58ca
NC		 6559 }
6560
99059e56
RM		 6561 /* We're done with the internal relocs, free them. */
6562 if (elf_section_data (section)->relocs == NULL)
6563 free (internal_relocs);
6564 }
48229727 6565
99059e56 6566 if (htab->fix_cortex_a8)
48229727 6567 {
99059e56
RM		 6568 /* Sort relocs which might apply to Cortex-A8 erratum. */
6569 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6570 sizeof (struct a8_erratum_reloc),
99059e56 6571 &a8_reloc_compare);
48229727 6572
99059e56
RM		 6573 /* Scan for branches which might trigger Cortex-A8 erratum. */
6574 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6575 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6576 a8_relocs, num_a8_relocs,
6577 prev_num_a8_fixes, &stub_changed)
6578 != 0)
48229727 6579 goto error_ret_free_local;
5e681ec4 6580 }
7f991970
AM		 6581
6582 if (local_syms != NULL
6583 && symtab_hdr->contents != (unsigned char *) local_syms)
6584 {
6585 if (!info->keep_memory)
6586 free (local_syms);
6587 else
6588 symtab_hdr->contents = (unsigned char *) local_syms;
6589 }
5e681ec4
PB		 6590 }
6591
0955507f
TP		 6592 if (first_veneer_scan
6593 && !set_cmse_veneer_addr_from_implib (info, htab,
6594 &cmse_stub_created))
6595 ret = FALSE;
6596
eb7c4339 6597 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6598 stub_changed = TRUE;
48229727 6599
906e58ca
NC		 6600 if (!stub_changed)
6601 break;
5e681ec4 6602
906e58ca
NC		 6603 /* OK, we've added some stubs. Find out the new size of the
6604 stub sections. */
6605 for (stub_sec = htab->stub_bfd->sections;
6606 stub_sec != NULL;
6607 stub_sec = stub_sec->next)
3e6b1042
DJ		 6608 {
6609 /* Ignore non-stub sections. */
6610 if (!strstr (stub_sec->name, STUB_SUFFIX))
6611 continue;
6612
6613 stub_sec->size = 0;
6614 }
b34b2d70 6615
0955507f
TP		 6616 /* Add new SG veneers after those already in the input import
6617 library. */
6618 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6619 stub_type++)
6620 {
6621 bfd_vma *start_offset_p;
6622 asection **stub_sec_p;
6623
6624 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6625 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6626 if (start_offset_p == NULL)
6627 continue;
6628
6629 BFD_ASSERT (stub_sec_p != NULL);
6630 if (*stub_sec_p != NULL)
6631 (*stub_sec_p)->size = *start_offset_p;
6632 }
6633
d7c5bd02 6634 /* Compute stub section size, considering padding. */
906e58ca 6635 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6636 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6637 stub_type++)
6638 {
6639 int size, padding;
6640 asection **stub_sec_p;
6641
6642 padding = arm_dedicated_stub_section_padding (stub_type);
6643 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6644 /* Skip if no stub input section or no stub section padding
6645 required. */
6646 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6647 continue;
6648 /* Stub section padding required but no dedicated section. */
6649 BFD_ASSERT (stub_sec_p);
6650
6651 size = (*stub_sec_p)->size;
6652 size = (size + padding - 1) & ~(padding - 1);
6653 (*stub_sec_p)->size = size;
6654 }
906e58ca 6655
48229727
JB		 6656 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6657 if (htab->fix_cortex_a8)
99059e56
RM		 6658 for (i = 0; i < num_a8_fixes; i++)
6659 {
48229727 6660 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6661 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6662
6663 if (stub_sec == NULL)
7f991970 6664 return FALSE;
48229727 6665
99059e56
RM		 6666 stub_sec->size
6667 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6668 NULL);
6669 }
48229727
JB		 6670
6671
906e58ca
NC		 6672 /* Ask the linker to do its stuff. */
6673 (*htab->layout_sections_again) ();
4ba2ef8f 6674 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6675 }
6676
48229727
JB		 6677 /* Add stubs for Cortex-A8 erratum fixes now. */
6678 if (htab->fix_cortex_a8)
6679 {
6680 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6681 {
6682 struct elf32_arm_stub_hash_entry *stub_entry;
6683 char *stub_name = a8_fixes[i].stub_name;
6684 asection *section = a8_fixes[i].section;
6685 unsigned int section_id = a8_fixes[i].section->id;
6686 asection *link_sec = htab->stub_group[section_id].link_sec;
6687 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6688 const insn_sequence *template_sequence;
6689 int template_size, size = 0;
6690
6691 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6692 TRUE, FALSE);
6693 if (stub_entry == NULL)
6694 {
871b3ab2 6695 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6696 section->owner, stub_name);
99059e56
RM		 6697 return FALSE;
6698 }
6699
6700 stub_entry->stub_sec = stub_sec;
0955507f 6701 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6702 stub_entry->id_sec = link_sec;
6703 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6704 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6705 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6706 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6707 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6708 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6709
99059e56
RM		 6710 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6711 &template_sequence,
6712 &template_size);
48229727 6713
99059e56
RM		 6714 stub_entry->stub_size = size;
6715 stub_entry->stub_template = template_sequence;
6716 stub_entry->stub_template_size = template_size;
6717 }
48229727
JB		 6718
6719 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6720 elf32_arm_write_section(). */
48229727
JB		 6721 htab->a8_erratum_fixes = a8_fixes;
6722 htab->num_a8_erratum_fixes = num_a8_fixes;
6723 }
6724 else
6725 {
6726 htab->a8_erratum_fixes = NULL;
6727 htab->num_a8_erratum_fixes = 0;
6728 }
0955507f 6729 return ret;
5e681ec4
PB		 6730}
6731
906e58ca
NC		 6732/* Build all the stubs associated with the current output file. The
6733 stubs are kept in a hash table attached to the main linker hash
6734 table. We also set up the .plt entries for statically linked PIC
6735 functions here. This function is called via arm_elf_finish in the
6736 linker. */
252b5132 6737
906e58ca
NC		 6738bfd_boolean
6739elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6740{
906e58ca
NC		 6741 asection *stub_sec;
6742 struct bfd_hash_table *table;
0955507f 6743 enum elf32_arm_stub_type stub_type;
906e58ca 6744 struct elf32_arm_link_hash_table *htab;
252b5132 6745
906e58ca 6746 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6747 if (htab == NULL)
6748 return FALSE;
252b5132 6749
906e58ca
NC		 6750 for (stub_sec = htab->stub_bfd->sections;
6751 stub_sec != NULL;
6752 stub_sec = stub_sec->next)
252b5132 6753 {
906e58ca
NC		 6754 bfd_size_type size;
6755
8029a119 6756 /* Ignore non-stub sections. */
906e58ca
NC		 6757 if (!strstr (stub_sec->name, STUB_SUFFIX))
6758 continue;
6759
d7c5bd02 6760 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6761 must at least be done for stub section requiring padding and for SG
6762 veneers to ensure that a non secure code branching to a removed SG
6763 veneer causes an error. */
906e58ca 6764 size = stub_sec->size;
21d799b5 6765 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6766 if (stub_sec->contents == NULL && size != 0)
6767 return FALSE;
0955507f 6768
906e58ca 6769 stub_sec->size = 0;
252b5132
RH		 6770 }
6771
0955507f
TP		 6772 /* Add new SG veneers after those already in the input import library. */
6773 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6774 {
6775 bfd_vma *start_offset_p;
6776 asection **stub_sec_p;
6777
6778 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6779 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6780 if (start_offset_p == NULL)
6781 continue;
6782
6783 BFD_ASSERT (stub_sec_p != NULL);
6784 if (*stub_sec_p != NULL)
6785 (*stub_sec_p)->size = *start_offset_p;
6786 }
6787
906e58ca
NC		 6788 /* Build the stubs as directed by the stub hash table. */
6789 table = &htab->stub_hash_table;
6790 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6791 if (htab->fix_cortex_a8)
6792 {
6793 /* Place the cortex a8 stubs last. */
6794 htab->fix_cortex_a8 = -1;
6795 bfd_hash_traverse (table, arm_build_one_stub, info);
6796 }
252b5132 6797
906e58ca 6798 return TRUE;
252b5132
RH		 6799}
6800
9b485d32
NC		 6801/* Locate the Thumb encoded calling stub for NAME. */
6802
252b5132 6803static struct elf_link_hash_entry *
57e8b36a
NC		 6804find_thumb_glue (struct bfd_link_info *link_info,
6805 const char *name,
f2a9dd69 6806 char **error_message)
252b5132
RH		 6807{
6808 char *tmp_name;
6809 struct elf_link_hash_entry *hash;
6810 struct elf32_arm_link_hash_table *hash_table;
6811
6812 /* We need a pointer to the armelf specific hash table. */
6813 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6814 if (hash_table == NULL)
6815 return NULL;
252b5132 6816
21d799b5 6817 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6818 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6819
6820 BFD_ASSERT (tmp_name);
6821
6822 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6823
6824 hash = elf_link_hash_lookup
b34976b6 6825 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6826
b1657152 6827 if (hash == NULL
90b6238f
AM		 6828 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
6829 "Thumb", tmp_name, name) == -1)
b1657152 6830 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6831
6832 free (tmp_name);
6833
6834 return hash;
6835}
6836
9b485d32
NC		 6837/* Locate the ARM encoded calling stub for NAME. */
6838
252b5132 6839static struct elf_link_hash_entry *
57e8b36a
NC		 6840find_arm_glue (struct bfd_link_info *link_info,
6841 const char *name,
f2a9dd69 6842 char **error_message)
252b5132
RH		 6843{
6844 char *tmp_name;
6845 struct elf_link_hash_entry *myh;
6846 struct elf32_arm_link_hash_table *hash_table;
6847
6848 /* We need a pointer to the elfarm specific hash table. */
6849 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6850 if (hash_table == NULL)
6851 return NULL;
252b5132 6852
21d799b5 6853 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6854 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6855
6856 BFD_ASSERT (tmp_name);
6857
6858 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6859
6860 myh = elf_link_hash_lookup
b34976b6 6861 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6862
b1657152 6863 if (myh == NULL
90b6238f
AM		 6864 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
6865 "ARM", tmp_name, name) == -1)
b1657152 6866 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6867
6868 free (tmp_name);
6869
6870 return myh;
6871}
6872
8f6277f5 6873/* ARM->Thumb glue (static images):
252b5132
RH		 6874
6875 .arm
6876 __func_from_arm:
6877 ldr r12, __func_addr
6878 bx r12
6879 __func_addr:
906e58ca 6880 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6881
26079076
PB		 6882 (v5t static images)
6883 .arm
6884 __func_from_arm:
6885 ldr pc, __func_addr
6886 __func_addr:
906e58ca 6887 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6888
8f6277f5
PB		 6889 (relocatable images)
6890 .arm
6891 __func_from_arm:
6892 ldr r12, __func_offset
6893 add r12, r12, pc
6894 bx r12
6895 __func_offset:
8029a119 6896 .word func - . */
8f6277f5
PB		 6897
6898#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6899static const insn32 a2t1_ldr_insn = 0xe59fc000;
6900static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6901static const insn32 a2t3_func_addr_insn = 0x00000001;
6902
26079076
PB		 6903#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6904static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6905static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6906
8f6277f5
PB		 6907#define ARM2THUMB_PIC_GLUE_SIZE 16
6908static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6909static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6910static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6911
07d6d2b8 6912/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6913
07d6d2b8
AM		 6914 .thumb .thumb
6915 .align 2 .align 2
6916 __func_from_thumb: __func_from_thumb:
6917 bx pc push {r6, lr}
6918 nop ldr r6, __func_addr
6919 .arm mov lr, pc
6920 b func bx r6
99059e56
RM		 6921 .arm
6922 ;; back_to_thumb
6923 ldmia r13! {r6, lr}
6924 bx lr
6925 __func_addr:
07d6d2b8 6926 .word func */
252b5132
RH		 6927
6928#define THUMB2ARM_GLUE_SIZE 8
6929static const insn16 t2a1_bx_pc_insn = 0x4778;
6930static const insn16 t2a2_noop_insn = 0x46c0;
6931static const insn32 t2a3_b_insn = 0xea000000;
6932
c7b8f16e 6933#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6934#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6935#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6936
845b51d6
PB		 6937#define ARM_BX_VENEER_SIZE 12
6938static const insn32 armbx1_tst_insn = 0xe3100001;
6939static const insn32 armbx2_moveq_insn = 0x01a0f000;
6940static const insn32 armbx3_bx_insn = 0xe12fff10;
6941
7e392df6 6942#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6943static void
6944arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6945{
6946 asection * s;
8029a119 6947 bfd_byte * contents;
252b5132 6948
8029a119 6949 if (size == 0)
3e6b1042
DJ		 6950 {
6951 /* Do not include empty glue sections in the output. */
6952 if (abfd != NULL)
6953 {
3d4d4302 6954 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6955 if (s != NULL)
6956 s->flags |= SEC_EXCLUDE;
6957 }
6958 return;
6959 }
252b5132 6960
8029a119 6961 BFD_ASSERT (abfd != NULL);
252b5132 6962
3d4d4302 6963 s = bfd_get_linker_section (abfd, name);
8029a119 6964 BFD_ASSERT (s != NULL);
252b5132 6965
21d799b5 6966 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6967
8029a119
NC		 6968 BFD_ASSERT (s->size == size);
6969 s->contents = contents;
6970}
906e58ca 6971
8029a119
NC		 6972bfd_boolean
6973bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6974{
6975 struct elf32_arm_link_hash_table * globals;
906e58ca 6976
8029a119
NC		 6977 globals = elf32_arm_hash_table (info);
6978 BFD_ASSERT (globals != NULL);
906e58ca 6979
8029a119
NC		 6980 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6981 globals->arm_glue_size,
6982 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6983
8029a119
NC		 6984 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6985 globals->thumb_glue_size,
6986 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6987
8029a119
NC		 6988 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6989 globals->vfp11_erratum_glue_size,
6990 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6991
a504d23a
LA		 6992 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6993 globals->stm32l4xx_erratum_glue_size,
6994 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6995
8029a119
NC		 6996 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6997 globals->bx_glue_size,
845b51d6
PB		 6998 ARM_BX_GLUE_SECTION_NAME);
6999
b34976b6 7000 return TRUE;
252b5132
RH		 7001}
7002
a4fd1a8e 7003/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7004 returns the symbol identifying the stub. */
7005
a4fd1a8e 7006static struct elf_link_hash_entry *
57e8b36a
NC		 7007record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7008 struct elf_link_hash_entry * h)
252b5132
RH		 7009{
7010 const char * name = h->root.root.string;
63b0f745 7011 asection * s;
252b5132
RH		 7012 char * tmp_name;
7013 struct elf_link_hash_entry * myh;
14a793b2 7014 struct bfd_link_hash_entry * bh;
252b5132 7015 struct elf32_arm_link_hash_table * globals;
dc810e39 7016 bfd_vma val;
2f475487 7017 bfd_size_type size;
252b5132
RH		 7018
7019 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7020 BFD_ASSERT (globals != NULL);
7021 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7022
3d4d4302 7023 s = bfd_get_linker_section
252b5132
RH		 7024 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7025
252b5132
RH		 7026 BFD_ASSERT (s != NULL);
7027
21d799b5 7028 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7029 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7030
7031 BFD_ASSERT (tmp_name);
7032
7033 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7034
7035 myh = elf_link_hash_lookup
b34976b6 7036 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7037
7038 if (myh != NULL)
7039 {
9b485d32 7040 /* We've already seen this guy. */
252b5132 7041 free (tmp_name);
a4fd1a8e 7042 return myh;
252b5132
RH		 7043 }
7044
57e8b36a
NC		 7045 /* The only trick here is using hash_table->arm_glue_size as the value.
7046 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7047 putting it. The +1 on the value marks that the stub has not been
7048 output yet - not that it is a Thumb function. */
14a793b2 7049 bh = NULL;
dc810e39
AM		 7050 val = globals->arm_glue_size + 1;
7051 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7052 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7053 NULL, TRUE, FALSE, &bh);
252b5132 7054
b7693d02
DJ		 7055 myh = (struct elf_link_hash_entry *) bh;
7056 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7057 myh->forced_local = 1;
7058
252b5132
RH		 7059 free (tmp_name);
7060
0e1862bb
L		 7061 if (bfd_link_pic (link_info)
7062 || globals->root.is_relocatable_executable
27e55c4d 7063 || globals->pic_veneer)
2f475487 7064 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7065 else if (globals->use_blx)
7066 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7067 else
2f475487
AM		 7068 size = ARM2THUMB_STATIC_GLUE_SIZE;
7069
7070 s->size += size;
7071 globals->arm_glue_size += size;
252b5132 7072
a4fd1a8e 7073 return myh;
252b5132
RH		 7074}
7075
845b51d6
PB		 7076/* Allocate space for ARMv4 BX veneers. */
7077
7078static void
7079record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7080{
7081 asection * s;
7082 struct elf32_arm_link_hash_table *globals;
7083 char *tmp_name;
7084 struct elf_link_hash_entry *myh;
7085 struct bfd_link_hash_entry *bh;
7086 bfd_vma val;
7087
7088 /* BX PC does not need a veneer. */
7089 if (reg == 15)
7090 return;
7091
7092 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7093 BFD_ASSERT (globals != NULL);
7094 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7095
7096 /* Check if this veneer has already been allocated. */
7097 if (globals->bx_glue_offset[reg])
7098 return;
7099
3d4d4302 7100 s = bfd_get_linker_section
845b51d6
PB		 7101 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7102
7103 BFD_ASSERT (s != NULL);
7104
7105 /* Add symbol for veneer. */
21d799b5
NC		 7106 tmp_name = (char *)
7107 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7108
845b51d6 7109 BFD_ASSERT (tmp_name);
906e58ca 7110
845b51d6 7111 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7112
845b51d6
PB		 7113 myh = elf_link_hash_lookup
7114 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7115
845b51d6 7116 BFD_ASSERT (myh == NULL);
906e58ca 7117
845b51d6
PB		 7118 bh = NULL;
7119 val = globals->bx_glue_size;
7120 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7121 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7122 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7123
7124 myh = (struct elf_link_hash_entry *) bh;
7125 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7126 myh->forced_local = 1;
7127
7128 s->size += ARM_BX_VENEER_SIZE;
7129 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7130 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7131}
7132
7133
c7b8f16e
JB		 7134/* Add an entry to the code/data map for section SEC. */
7135
7136static void
7137elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7138{
7139 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7140 unsigned int newidx;
906e58ca 7141
c7b8f16e
JB		 7142 if (sec_data->map == NULL)
7143 {
21d799b5 7144 sec_data->map = (elf32_arm_section_map *)
99059e56 7145 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7146 sec_data->mapcount = 0;
7147 sec_data->mapsize = 1;
7148 }
906e58ca 7149
c7b8f16e 7150 newidx = sec_data->mapcount++;
906e58ca 7151
c7b8f16e
JB		 7152 if (sec_data->mapcount > sec_data->mapsize)
7153 {
7154 sec_data->mapsize *= 2;
21d799b5 7155 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7156 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7157 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7158 }
7159
7160 if (sec_data->map)
7161 {
7162 sec_data->map[newidx].vma = vma;
7163 sec_data->map[newidx].type = type;
c7b8f16e 7164 }
c7b8f16e
JB		 7165}
7166
7167
7168/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7169 veneers are handled for now. */
7170
7171static bfd_vma
7172record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7173 elf32_vfp11_erratum_list *branch,
7174 bfd *branch_bfd,
7175 asection *branch_sec,
7176 unsigned int offset)
c7b8f16e
JB		 7177{
7178 asection *s;
7179 struct elf32_arm_link_hash_table *hash_table;
7180 char *tmp_name;
7181 struct elf_link_hash_entry *myh;
7182 struct bfd_link_hash_entry *bh;
7183 bfd_vma val;
7184 struct _arm_elf_section_data *sec_data;
c7b8f16e 7185 elf32_vfp11_erratum_list *newerr;
906e58ca 7186
c7b8f16e 7187 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7188 BFD_ASSERT (hash_table != NULL);
7189 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7190
3d4d4302 7191 s = bfd_get_linker_section
c7b8f16e 7192 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7193
c7b8f16e 7194 sec_data = elf32_arm_section_data (s);
906e58ca 7195
c7b8f16e 7196 BFD_ASSERT (s != NULL);
906e58ca 7197
21d799b5 7198 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7199 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7200
c7b8f16e 7201 BFD_ASSERT (tmp_name);
906e58ca 7202
c7b8f16e
JB		 7203 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7204 hash_table->num_vfp11_fixes);
906e58ca 7205
c7b8f16e
JB		 7206 myh = elf_link_hash_lookup
7207 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7208
c7b8f16e 7209 BFD_ASSERT (myh == NULL);
906e58ca 7210
c7b8f16e
JB		 7211 bh = NULL;
7212 val = hash_table->vfp11_erratum_glue_size;
7213 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7214 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7215 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7216
7217 myh = (struct elf_link_hash_entry *) bh;
7218 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7219 myh->forced_local = 1;
7220
7221 /* Link veneer back to calling location. */
c7e2358a 7222 sec_data->erratumcount += 1;
21d799b5
NC		 7223 newerr = (elf32_vfp11_erratum_list *)
7224 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7225
c7b8f16e
JB		 7226 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7227 newerr->vma = -1;
7228 newerr->u.v.branch = branch;
7229 newerr->u.v.id = hash_table->num_vfp11_fixes;
7230 branch->u.b.veneer = newerr;
7231
7232 newerr->next = sec_data->erratumlist;
7233 sec_data->erratumlist = newerr;
7234
7235 /* A symbol for the return from the veneer. */
7236 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7237 hash_table->num_vfp11_fixes);
7238
7239 myh = elf_link_hash_lookup
7240 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7241
c7b8f16e
JB		 7242 if (myh != NULL)
7243 abort ();
7244
7245 bh = NULL;
7246 val = offset + 4;
7247 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7248 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7249
c7b8f16e
JB		 7250 myh = (struct elf_link_hash_entry *) bh;
7251 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7252 myh->forced_local = 1;
7253
7254 free (tmp_name);
906e58ca 7255
c7b8f16e
JB		 7256 /* Generate a mapping symbol for the veneer section, and explicitly add an
7257 entry for that symbol to the code/data map for the section. */
7258 if (hash_table->vfp11_erratum_glue_size == 0)
7259 {
7260 bh = NULL;
7261 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7262 ever requires this erratum fix. */
c7b8f16e
JB		 7263 _bfd_generic_link_add_one_symbol (link_info,
7264 hash_table->bfd_of_glue_owner, "$a",
7265 BSF_LOCAL, s, 0, NULL,
99059e56 7266 TRUE, FALSE, &bh);
c7b8f16e
JB		 7267
7268 myh = (struct elf_link_hash_entry *) bh;
7269 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7270 myh->forced_local = 1;
906e58ca 7271
c7b8f16e 7272 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7273 BFDs. We must make a note of this generated mapping symbol
7274 ourselves so that code byteswapping works properly in
7275 elf32_arm_write_section. */
c7b8f16e
JB		 7276 elf32_arm_section_map_add (s, 'a', 0);
7277 }
906e58ca 7278
c7b8f16e
JB		 7279 s->size += VFP11_ERRATUM_VENEER_SIZE;
7280 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7281 hash_table->num_vfp11_fixes++;
906e58ca 7282
c7b8f16e
JB		 7283 /* The offset of the veneer. */
7284 return val;
7285}
7286
a504d23a
LA		 7287/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7288 veneers need to be handled because used only in Cortex-M. */
7289
7290static bfd_vma
7291record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7292 elf32_stm32l4xx_erratum_list *branch,
7293 bfd *branch_bfd,
7294 asection *branch_sec,
7295 unsigned int offset,
7296 bfd_size_type veneer_size)
7297{
7298 asection *s;
7299 struct elf32_arm_link_hash_table *hash_table;
7300 char *tmp_name;
7301 struct elf_link_hash_entry *myh;
7302 struct bfd_link_hash_entry *bh;
7303 bfd_vma val;
7304 struct _arm_elf_section_data *sec_data;
7305 elf32_stm32l4xx_erratum_list *newerr;
7306
7307 hash_table = elf32_arm_hash_table (link_info);
7308 BFD_ASSERT (hash_table != NULL);
7309 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7310
7311 s = bfd_get_linker_section
7312 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7313
7314 BFD_ASSERT (s != NULL);
7315
7316 sec_data = elf32_arm_section_data (s);
7317
7318 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7319 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7320
7321 BFD_ASSERT (tmp_name);
7322
7323 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7324 hash_table->num_stm32l4xx_fixes);
7325
7326 myh = elf_link_hash_lookup
7327 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7328
7329 BFD_ASSERT (myh == NULL);
7330
7331 bh = NULL;
7332 val = hash_table->stm32l4xx_erratum_glue_size;
7333 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7334 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7335 NULL, TRUE, FALSE, &bh);
7336
7337 myh = (struct elf_link_hash_entry *) bh;
7338 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7339 myh->forced_local = 1;
7340
7341 /* Link veneer back to calling location. */
7342 sec_data->stm32l4xx_erratumcount += 1;
7343 newerr = (elf32_stm32l4xx_erratum_list *)
7344 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7345
7346 newerr->type = STM32L4XX_ERRATUM_VENEER;
7347 newerr->vma = -1;
7348 newerr->u.v.branch = branch;
7349 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7350 branch->u.b.veneer = newerr;
7351
7352 newerr->next = sec_data->stm32l4xx_erratumlist;
7353 sec_data->stm32l4xx_erratumlist = newerr;
7354
7355 /* A symbol for the return from the veneer. */
7356 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7357 hash_table->num_stm32l4xx_fixes);
7358
7359 myh = elf_link_hash_lookup
7360 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7361
7362 if (myh != NULL)
7363 abort ();
7364
7365 bh = NULL;
7366 val = offset + 4;
7367 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7368 branch_sec, val, NULL, TRUE, FALSE, &bh);
7369
7370 myh = (struct elf_link_hash_entry *) bh;
7371 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7372 myh->forced_local = 1;
7373
7374 free (tmp_name);
7375
7376 /* Generate a mapping symbol for the veneer section, and explicitly add an
7377 entry for that symbol to the code/data map for the section. */
7378 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7379 {
7380 bh = NULL;
7381 /* Creates a THUMB symbol since there is no other choice. */
7382 _bfd_generic_link_add_one_symbol (link_info,
7383 hash_table->bfd_of_glue_owner, "$t",
7384 BSF_LOCAL, s, 0, NULL,
7385 TRUE, FALSE, &bh);
7386
7387 myh = (struct elf_link_hash_entry *) bh;
7388 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7389 myh->forced_local = 1;
7390
7391 /* The elf32_arm_init_maps function only cares about symbols from input
7392 BFDs. We must make a note of this generated mapping symbol
7393 ourselves so that code byteswapping works properly in
7394 elf32_arm_write_section. */
7395 elf32_arm_section_map_add (s, 't', 0);
7396 }
7397
7398 s->size += veneer_size;
7399 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7400 hash_table->num_stm32l4xx_fixes++;
7401
7402 /* The offset of the veneer. */
7403 return val;
7404}
7405
8029a119 7406#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7407 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7408 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7409
7410/* Create a fake section for use by the ARM backend of the linker. */
7411
7412static bfd_boolean
7413arm_make_glue_section (bfd * abfd, const char * name)
7414{
7415 asection * sec;
7416
3d4d4302 7417 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7418 if (sec != NULL)
7419 /* Already made. */
7420 return TRUE;
7421
3d4d4302 7422 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7423
7424 if (sec == NULL
7425 || !bfd_set_section_alignment (abfd, sec, 2))
7426 return FALSE;
7427
7428 /* Set the gc mark to prevent the section from being removed by garbage
7429 collection, despite the fact that no relocs refer to this section. */
7430 sec->gc_mark = 1;
7431
7432 return TRUE;
7433}
7434
1db37fe6
YG		 7435/* Set size of .plt entries. This function is called from the
7436 linker scripts in ld/emultempl/{armelf}.em. */
7437
7438void
7439bfd_elf32_arm_use_long_plt (void)
7440{
7441 elf32_arm_use_long_plt_entry = TRUE;
7442}
7443
8afb0e02
NC		 7444/* Add the glue sections to ABFD. This function is called from the
7445 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7446
b34976b6 7447bfd_boolean
57e8b36a
NC		 7448bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7449 struct bfd_link_info *info)
252b5132 7450{
a504d23a
LA		 7451 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7452 bfd_boolean dostm32l4xx = globals
7453 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7454 bfd_boolean addglue;
7455
8afb0e02
NC		 7456 /* If we are only performing a partial
7457 link do not bother adding the glue. */
0e1862bb 7458 if (bfd_link_relocatable (info))
b34976b6 7459 return TRUE;
252b5132 7460
a504d23a 7461 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7462 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7463 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7464 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7465
7466 if (!dostm32l4xx)
7467 return addglue;
7468
7469 return addglue
7470 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7471}
7472
daa4adae
TP		 7473/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7474 ensures they are not marked for deletion by
7475 strip_excluded_output_sections () when veneers are going to be created
7476 later. Not doing so would trigger assert on empty section size in
7477 lang_size_sections_1 (). */
7478
7479void
7480bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7481{
7482 enum elf32_arm_stub_type stub_type;
7483
7484 /* If we are only performing a partial
7485 link do not bother adding the glue. */
7486 if (bfd_link_relocatable (info))
7487 return;
7488
7489 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7490 {
7491 asection *out_sec;
7492 const char *out_sec_name;
7493
7494 if (!arm_dedicated_stub_output_section_required (stub_type))
7495 continue;
7496
7497 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7498 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7499 if (out_sec != NULL)
7500 out_sec->flags |= SEC_KEEP;
7501 }
7502}
7503
8afb0e02
NC		 7504/* Select a BFD to be used to hold the sections used by the glue code.
7505 This function is called from the linker scripts in ld/emultempl/
8029a119 7506 {armelf/pe}.em. */
8afb0e02 7507
b34976b6 7508bfd_boolean
57e8b36a 7509bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7510{
7511 struct elf32_arm_link_hash_table *globals;
7512
7513 /* If we are only performing a partial link
7514 do not bother getting a bfd to hold the glue. */
0e1862bb 7515 if (bfd_link_relocatable (info))
b34976b6 7516 return TRUE;
8afb0e02 7517
b7693d02
DJ		 7518 /* Make sure we don't attach the glue sections to a dynamic object. */
7519 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7520
8afb0e02 7521 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7522 BFD_ASSERT (globals != NULL);
7523
7524 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7525 return TRUE;
8afb0e02 7526
252b5132
RH		 7527 /* Save the bfd for later use. */
7528 globals->bfd_of_glue_owner = abfd;
cedb70c5 7529
b34976b6 7530 return TRUE;
252b5132
RH		 7531}
7532
906e58ca
NC		 7533static void
7534check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7535{
2de70689
MGD		 7536 int cpu_arch;
7537
b38cadfb 7538 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7539 Tag_CPU_arch);
7540
7541 if (globals->fix_arm1176)
7542 {
7543 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7544 globals->use_blx = 1;
7545 }
7546 else
7547 {
7548 if (cpu_arch > TAG_CPU_ARCH_V4T)
7549 globals->use_blx = 1;
7550 }
39b41c9c
PB		 7551}
7552
b34976b6 7553bfd_boolean
57e8b36a 7554bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7555 struct bfd_link_info *link_info)
252b5132
RH		 7556{
7557 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7558 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7559 Elf_Internal_Rela *irel, *irelend;
7560 bfd_byte *contents = NULL;
252b5132
RH		 7561
7562 asection *sec;
7563 struct elf32_arm_link_hash_table *globals;
7564
7565 /* If we are only performing a partial link do not bother
7566 to construct any glue. */
0e1862bb 7567 if (bfd_link_relocatable (link_info))
b34976b6 7568 return TRUE;
252b5132 7569
39ce1a6a
NC		 7570 /* Here we have a bfd that is to be included on the link. We have a
7571 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7572 globals = elf32_arm_hash_table (link_info);
252b5132 7573 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7574
7575 check_use_blx (globals);
252b5132 7576
d504ffc8 7577 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7578 {
90b6238f 7579 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7580 abfd);
e489d0ae
PB		 7581 return FALSE;
7582 }
f21f3fe0 7583
39ce1a6a
NC		 7584 /* PR 5398: If we have not decided to include any loadable sections in
7585 the output then we will not have a glue owner bfd. This is OK, it
7586 just means that there is nothing else for us to do here. */
7587 if (globals->bfd_of_glue_owner == NULL)
7588 return TRUE;
7589
252b5132
RH		 7590 /* Rummage around all the relocs and map the glue vectors. */
7591 sec = abfd->sections;
7592
7593 if (sec == NULL)
b34976b6 7594 return TRUE;
252b5132
RH		 7595
7596 for (; sec != NULL; sec = sec->next)
7597 {
7598 if (sec->reloc_count == 0)
7599 continue;
7600
2f475487
AM		 7601 if ((sec->flags & SEC_EXCLUDE) != 0)
7602 continue;
7603
0ffa91dd 7604 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7605
9b485d32 7606 /* Load the relocs. */
6cdc0ccc 7607 internal_relocs
906e58ca 7608 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7609
6cdc0ccc
AM		 7610 if (internal_relocs == NULL)
7611 goto error_return;
252b5132 7612
6cdc0ccc
AM		 7613 irelend = internal_relocs + sec->reloc_count;
7614 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7615 {
7616 long r_type;
7617 unsigned long r_index;
252b5132
RH		 7618
7619 struct elf_link_hash_entry *h;
7620
7621 r_type = ELF32_R_TYPE (irel->r_info);
7622 r_index = ELF32_R_SYM (irel->r_info);
7623
9b485d32 7624 /* These are the only relocation types we care about. */
ba96a88f 7625 if ( r_type != R_ARM_PC24
845b51d6 7626 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7627 continue;
7628
7629 /* Get the section contents if we haven't done so already. */
7630 if (contents == NULL)
7631 {
7632 /* Get cached copy if it exists. */
7633 if (elf_section_data (sec)->this_hdr.contents != NULL)
7634 contents = elf_section_data (sec)->this_hdr.contents;
7635 else
7636 {
7637 /* Go get them off disk. */
57e8b36a 7638 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7639 goto error_return;
7640 }
7641 }
7642
845b51d6
PB		 7643 if (r_type == R_ARM_V4BX)
7644 {
7645 int reg;
7646
7647 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7648 record_arm_bx_glue (link_info, reg);
7649 continue;
7650 }
7651
a7c10850 7652 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7653 h = NULL;
7654
9b485d32 7655 /* We don't care about local symbols. */
252b5132
RH		 7656 if (r_index < symtab_hdr->sh_info)
7657 continue;
7658
9b485d32 7659 /* This is an external symbol. */
252b5132
RH		 7660 r_index -= symtab_hdr->sh_info;
7661 h = (struct elf_link_hash_entry *)
7662 elf_sym_hashes (abfd)[r_index];
7663
7664 /* If the relocation is against a static symbol it must be within
7665 the current section and so cannot be a cross ARM/Thumb relocation. */
7666 if (h == NULL)
7667 continue;
7668
d504ffc8
DJ		 7669 /* If the call will go through a PLT entry then we do not need
7670 glue. */
362d30a1 7671 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7672 continue;
7673
252b5132
RH		 7674 switch (r_type)
7675 {
7676 case R_ARM_PC24:
7677 /* This one is a call from arm code. We need to look up
99059e56
RM		 7678 the target of the call. If it is a thumb target, we
7679 insert glue. */
39d911fc
TP		 7680 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7681 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7682 record_arm_to_thumb_glue (link_info, h);
7683 break;
7684
252b5132 7685 default:
c6596c5e 7686 abort ();
252b5132
RH		 7687 }
7688 }
6cdc0ccc
AM		 7689
7690 if (contents != NULL
7691 && elf_section_data (sec)->this_hdr.contents != contents)
7692 free (contents);
7693 contents = NULL;
7694
7695 if (internal_relocs != NULL
7696 && elf_section_data (sec)->relocs != internal_relocs)
7697 free (internal_relocs);
7698 internal_relocs = NULL;
252b5132
RH		 7699 }
7700
b34976b6 7701 return TRUE;
9a5aca8c 7702
252b5132 7703error_return:
6cdc0ccc
AM		 7704 if (contents != NULL
7705 && elf_section_data (sec)->this_hdr.contents != contents)
7706 free (contents);
7707 if (internal_relocs != NULL
7708 && elf_section_data (sec)->relocs != internal_relocs)
7709 free (internal_relocs);
9a5aca8c 7710
b34976b6 7711 return FALSE;
252b5132 7712}
7e392df6 7713#endif
252b5132 7714
eb043451 7715
c7b8f16e
JB		 7716/* Initialise maps of ARM/Thumb/data for input BFDs. */
7717
7718void
7719bfd_elf32_arm_init_maps (bfd *abfd)
7720{
7721 Elf_Internal_Sym *isymbuf;
7722 Elf_Internal_Shdr *hdr;
7723 unsigned int i, localsyms;
7724
af1f4419
NC		 7725 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7726 if (! is_arm_elf (abfd))
7727 return;
7728
c7b8f16e
JB		 7729 if ((abfd->flags & DYNAMIC) != 0)
7730 return;
7731
0ffa91dd 7732 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7733 localsyms = hdr->sh_info;
7734
7735 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7736 should contain the number of local symbols, which should come before any
7737 global symbols. Mapping symbols are always local. */
7738 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7739 NULL);
7740
7741 /* No internal symbols read? Skip this BFD. */
7742 if (isymbuf == NULL)
7743 return;
7744
7745 for (i = 0; i < localsyms; i++)
7746 {
7747 Elf_Internal_Sym *isym = &isymbuf[i];
7748 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7749 const char *name;
906e58ca 7750
c7b8f16e 7751 if (sec != NULL
99059e56
RM		 7752 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7753 {
7754 name = bfd_elf_string_from_elf_section (abfd,
7755 hdr->sh_link, isym->st_name);
906e58ca 7756
99059e56 7757 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7758 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7759 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7760 }
c7b8f16e
JB		 7761 }
7762}
7763
7764
48229727
JB		 7765/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7766 say what they wanted. */
7767
7768void
7769bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7770{
7771 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7772 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7773
4dfe6ac6
NC		 7774 if (globals == NULL)
7775 return;
7776
48229727
JB		 7777 if (globals->fix_cortex_a8 == -1)
7778 {
7779 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7780 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7781 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7782 || out_attr[Tag_CPU_arch_profile].i == 0))
7783 globals->fix_cortex_a8 = 1;
7784 else
7785 globals->fix_cortex_a8 = 0;
7786 }
7787}
7788
7789
c7b8f16e
JB		 7790void
7791bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7792{
7793 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7794 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7795
4dfe6ac6
NC		 7796 if (globals == NULL)
7797 return;
c7b8f16e
JB		 7798 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7799 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7800 {
7801 switch (globals->vfp11_fix)
99059e56
RM		 7802 {
7803 case BFD_ARM_VFP11_FIX_DEFAULT:
7804 case BFD_ARM_VFP11_FIX_NONE:
7805 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7806 break;
7807
7808 default:
7809 /* Give a warning, but do as the user requests anyway. */
871b3ab2 7810 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 7811 "workaround is not necessary for target architecture"), obfd);
7812 }
c7b8f16e
JB		 7813 }
7814 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7815 /* For earlier architectures, we might need the workaround, but do not
7816 enable it by default. If users is running with broken hardware, they
7817 must enable the erratum fix explicitly. */
7818 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7819}
7820
a504d23a
LA		 7821void
7822bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7823{
7824 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7825 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7826
7827 if (globals == NULL)
7828 return;
7829
7830 /* We assume only Cortex-M4 may require the fix. */
7831 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7832 || out_attr[Tag_CPU_arch_profile].i != 'M')
7833 {
7834 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7835 /* Give a warning, but do as the user requests anyway. */
4eca0228 7836 _bfd_error_handler
871b3ab2 7837 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 7838 "workaround is not necessary for target architecture"), obfd);
7839 }
7840}
c7b8f16e 7841
906e58ca
NC		 7842enum bfd_arm_vfp11_pipe
7843{
c7b8f16e
JB		 7844 VFP11_FMAC,
7845 VFP11_LS,
7846 VFP11_DS,
7847 VFP11_BAD
7848};
7849
7850/* Return a VFP register number. This is encoded as RX:X for single-precision
7851 registers, or X:RX for double-precision registers, where RX is the group of
7852 four bits in the instruction encoding and X is the single extension bit.
7853 RX and X fields are specified using their lowest (starting) bit. The return
7854 value is:
7855
7856 0...31: single-precision registers s0...s31
7857 32...63: double-precision registers d0...d31.
906e58ca 7858
c7b8f16e
JB		 7859 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7860 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7861
c7b8f16e
JB		 7862static unsigned int
7863bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7864 unsigned int x)
c7b8f16e
JB		 7865{
7866 if (is_double)
7867 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7868 else
7869 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7870}
7871
7872/* Set bits in *WMASK according to a register number REG as encoded by
7873 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7874
7875static void
7876bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7877{
7878 if (reg < 32)
7879 *wmask |= 1 << reg;
7880 else if (reg < 48)
7881 *wmask |= 3 << ((reg - 32) * 2);
7882}
7883
7884/* Return TRUE if WMASK overwrites anything in REGS. */
7885
7886static bfd_boolean
7887bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7888{
7889 int i;
906e58ca 7890
c7b8f16e
JB		 7891 for (i = 0; i < numregs; i++)
7892 {
7893 unsigned int reg = regs[i];
7894
7895 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7896 return TRUE;
906e58ca 7897
c7b8f16e
JB		 7898 reg -= 32;
7899
7900 if (reg >= 16)
99059e56 7901 continue;
906e58ca 7902
c7b8f16e 7903 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7904 return TRUE;
c7b8f16e 7905 }
906e58ca 7906
c7b8f16e
JB		 7907 return FALSE;
7908}
7909
7910/* In this function, we're interested in two things: finding input registers
7911 for VFP data-processing instructions, and finding the set of registers which
7912 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7913 hold the written set, so FLDM etc. are easy to deal with (we're only
7914 interested in 32 SP registers or 16 dp registers, due to the VFP version
7915 implemented by the chip in question). DP registers are marked by setting
7916 both SP registers in the write mask). */
7917
7918static enum bfd_arm_vfp11_pipe
7919bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7920 int *numregs)
c7b8f16e 7921{
91d6fa6a 7922 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7923 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7924
7925 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7926 {
7927 unsigned int pqrs;
7928 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7929 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7930
7931 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7932 | ((insn & 0x00300000) >> 19)
7933 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7934
7935 switch (pqrs)
99059e56
RM		 7936 {
7937 case 0: /* fmac[sd]. */
7938 case 1: /* fnmac[sd]. */
7939 case 2: /* fmsc[sd]. */
7940 case 3: /* fnmsc[sd]. */
7941 vpipe = VFP11_FMAC;
7942 bfd_arm_vfp11_write_mask (destmask, fd);
7943 regs[0] = fd;
7944 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7945 regs[2] = fm;
7946 *numregs = 3;
7947 break;
7948
7949 case 4: /* fmul[sd]. */
7950 case 5: /* fnmul[sd]. */
7951 case 6: /* fadd[sd]. */
7952 case 7: /* fsub[sd]. */
7953 vpipe = VFP11_FMAC;
7954 goto vfp_binop;
7955
7956 case 8: /* fdiv[sd]. */
7957 vpipe = VFP11_DS;
7958 vfp_binop:
7959 bfd_arm_vfp11_write_mask (destmask, fd);
7960 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7961 regs[1] = fm;
7962 *numregs = 2;
7963 break;
7964
7965 case 15: /* extended opcode. */
7966 {
7967 unsigned int extn = ((insn >> 15) & 0x1e)
7968 | ((insn >> 7) & 1);
7969
7970 switch (extn)
7971 {
7972 case 0: /* fcpy[sd]. */
7973 case 1: /* fabs[sd]. */
7974 case 2: /* fneg[sd]. */
7975 case 8: /* fcmp[sd]. */
7976 case 9: /* fcmpe[sd]. */
7977 case 10: /* fcmpz[sd]. */
7978 case 11: /* fcmpez[sd]. */
7979 case 16: /* fuito[sd]. */
7980 case 17: /* fsito[sd]. */
7981 case 24: /* ftoui[sd]. */
7982 case 25: /* ftouiz[sd]. */
7983 case 26: /* ftosi[sd]. */
7984 case 27: /* ftosiz[sd]. */
7985 /* These instructions will not bounce due to underflow. */
7986 *numregs = 0;
7987 vpipe = VFP11_FMAC;
7988 break;
7989
7990 case 3: /* fsqrt[sd]. */
7991 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7992 registers to cause the erratum in previous instructions. */
7993 bfd_arm_vfp11_write_mask (destmask, fd);
7994 vpipe = VFP11_DS;
7995 break;
7996
7997 case 15: /* fcvt{ds,sd}. */
7998 {
7999 int rnum = 0;
8000
8001 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8002
8003 /* Only FCVTSD can underflow. */
99059e56
RM		 8004 if ((insn & 0x100) != 0)
8005 regs[rnum++] = fm;
c7b8f16e 8006
99059e56 8007 *numregs = rnum;
c7b8f16e 8008
99059e56
RM		 8009 vpipe = VFP11_FMAC;
8010 }
8011 break;
c7b8f16e 8012
99059e56
RM		 8013 default:
8014 return VFP11_BAD;
8015 }
8016 }
8017 break;
c7b8f16e 8018
99059e56
RM		 8019 default:
8020 return VFP11_BAD;
8021 }
c7b8f16e
JB		 8022 }
8023 /* Two-register transfer. */
8024 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8025 {
8026 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8027
c7b8f16e
JB		 8028 if ((insn & 0x100000) == 0)
8029 {
99059e56
RM		 8030 if (is_double)
8031 bfd_arm_vfp11_write_mask (destmask, fm);
8032 else
8033 {
8034 bfd_arm_vfp11_write_mask (destmask, fm);
8035 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8036 }
c7b8f16e
JB		 8037 }
8038
91d6fa6a 8039 vpipe = VFP11_LS;
c7b8f16e
JB		 8040 }
8041 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8042 {
8043 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8044 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8045
c7b8f16e 8046 switch (puw)
99059e56
RM		 8047 {
8048 case 0: /* Two-reg transfer. We should catch these above. */
8049 abort ();
906e58ca 8050
99059e56
RM		 8051 case 2: /* fldm[sdx]. */
8052 case 3:
8053 case 5:
8054 {
8055 unsigned int i, offset = insn & 0xff;
c7b8f16e 8056
99059e56
RM		 8057 if (is_double)
8058 offset >>= 1;
c7b8f16e 8059
99059e56
RM		 8060 for (i = fd; i < fd + offset; i++)
8061 bfd_arm_vfp11_write_mask (destmask, i);
8062 }
8063 break;
906e58ca 8064
99059e56
RM		 8065 case 4: /* fld[sd]. */
8066 case 6:
8067 bfd_arm_vfp11_write_mask (destmask, fd);
8068 break;
906e58ca 8069
99059e56
RM		 8070 default:
8071 return VFP11_BAD;
8072 }
c7b8f16e 8073
91d6fa6a 8074 vpipe = VFP11_LS;
c7b8f16e
JB		 8075 }
8076 /* Single-register transfer. Note L==0. */
8077 else if ((insn & 0x0f100e10) == 0x0e000a10)
8078 {
8079 unsigned int opcode = (insn >> 21) & 7;
8080 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8081
8082 switch (opcode)
99059e56
RM		 8083 {
8084 case 0: /* fmsr/fmdlr. */
8085 case 1: /* fmdhr. */
8086 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8087 destination register. I don't know if this is exactly right,
8088 but it is the conservative choice. */
8089 bfd_arm_vfp11_write_mask (destmask, fn);
8090 break;
8091
8092 case 7: /* fmxr. */
8093 break;
8094 }
c7b8f16e 8095
91d6fa6a 8096 vpipe = VFP11_LS;
c7b8f16e
JB		 8097 }
8098
91d6fa6a 8099 return vpipe;
c7b8f16e
JB		 8100}
8101
8102
8103static int elf32_arm_compare_mapping (const void * a, const void * b);
8104
8105
8106/* Look for potentially-troublesome code sequences which might trigger the
8107 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8108 (available from ARM) for details of the erratum. A short version is
8109 described in ld.texinfo. */
8110
8111bfd_boolean
8112bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8113{
8114 asection *sec;
8115 bfd_byte *contents = NULL;
8116 int state = 0;
8117 int regs[3], numregs = 0;
8118 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8119 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8120
4dfe6ac6
NC		 8121 if (globals == NULL)
8122 return FALSE;
8123
c7b8f16e
JB		 8124 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8125 The states transition as follows:
906e58ca 8126
c7b8f16e 8127 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8128 A VFP FMAC-pipeline instruction has been seen. Fill
8129 regs[0]..regs[numregs-1] with its input operands. Remember this
8130 instruction in 'first_fmac'.
c7b8f16e
JB		 8131
8132 1 -> 2
99059e56
RM		 8133 Any instruction, except for a VFP instruction which overwrites
8134 regs[*].
906e58ca 8135
c7b8f16e
JB		 8136 1 -> 3 [ -> 0 ] or
8137 2 -> 3 [ -> 0 ]
99059e56
RM		 8138 A VFP instruction has been seen which overwrites any of regs[*].
8139 We must make a veneer! Reset state to 0 before examining next
8140 instruction.
906e58ca 8141
c7b8f16e 8142 2 -> 0
99059e56
RM		 8143 If we fail to match anything in state 2, reset to state 0 and reset
8144 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8145
8146 If the VFP11 vector mode is in use, there must be at least two unrelated
8147 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8148 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8149
8150 /* If we are only performing a partial link do not bother
8151 to construct any glue. */
0e1862bb 8152 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8153 return TRUE;
8154
0ffa91dd
NC		 8155 /* Skip if this bfd does not correspond to an ELF image. */
8156 if (! is_arm_elf (abfd))
8157 return TRUE;
906e58ca 8158
c7b8f16e
JB		 8159 /* We should have chosen a fix type by the time we get here. */
8160 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8161
8162 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8163 return TRUE;
2e6030b9 8164
33a7ffc2
JM		 8165 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8166 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8167 return TRUE;
8168
c7b8f16e
JB		 8169 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8170 {
8171 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8172 struct _arm_elf_section_data *sec_data;
8173
8174 /* If we don't have executable progbits, we're not interested in this
99059e56 8175 section. Also skip if section is to be excluded. */
c7b8f16e 8176 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8177 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8178 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8179 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8180 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8181 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8182 continue;
c7b8f16e
JB		 8183
8184 sec_data = elf32_arm_section_data (sec);
906e58ca 8185
c7b8f16e 8186 if (sec_data->mapcount == 0)
99059e56 8187 continue;
906e58ca 8188
c7b8f16e
JB		 8189 if (elf_section_data (sec)->this_hdr.contents != NULL)
8190 contents = elf_section_data (sec)->this_hdr.contents;
8191 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8192 goto error_return;
8193
8194 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8195 elf32_arm_compare_mapping);
8196
8197 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8198 {
8199 unsigned int span_start = sec_data->map[span].vma;
8200 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8201 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8202 char span_type = sec_data->map[span].type;
8203
8204 /* FIXME: Only ARM mode is supported at present. We may need to
8205 support Thumb-2 mode also at some point. */
8206 if (span_type != 'a')
8207 continue;
8208
8209 for (i = span_start; i < span_end;)
8210 {
8211 unsigned int next_i = i + 4;
8212 unsigned int insn = bfd_big_endian (abfd)
8213 ? (contents[i] << 24)
8214 | (contents[i + 1] << 16)
8215 | (contents[i + 2] << 8)
8216 | contents[i + 3]
8217 : (contents[i + 3] << 24)
8218 | (contents[i + 2] << 16)
8219 | (contents[i + 1] << 8)
8220 | contents[i];
8221 unsigned int writemask = 0;
8222 enum bfd_arm_vfp11_pipe vpipe;
8223
8224 switch (state)
8225 {
8226 case 0:
8227 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8228 &numregs);
8229 /* I'm assuming the VFP11 erratum can trigger with denorm
8230 operands on either the FMAC or the DS pipeline. This might
8231 lead to slightly overenthusiastic veneer insertion. */
8232 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8233 {
8234 state = use_vector ? 1 : 2;
8235 first_fmac = i;
8236 veneer_of_insn = insn;
8237 }
8238 break;
8239
8240 case 1:
8241 {
8242 int other_regs[3], other_numregs;
8243 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8244 other_regs,
99059e56
RM		 8245 &other_numregs);
8246 if (vpipe != VFP11_BAD
8247 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8248 numregs))
99059e56
RM		 8249 state = 3;
8250 else
8251 state = 2;
8252 }
8253 break;
8254
8255 case 2:
8256 {
8257 int other_regs[3], other_numregs;
8258 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8259 other_regs,
99059e56
RM		 8260 &other_numregs);
8261 if (vpipe != VFP11_BAD
8262 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8263 numregs))
99059e56
RM		 8264 state = 3;
8265 else
8266 {
8267 state = 0;
8268 next_i = first_fmac + 4;
8269 }
8270 }
8271 break;
8272
8273 case 3:
8274 abort (); /* Should be unreachable. */
8275 }
8276
8277 if (state == 3)
8278 {
8279 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8280 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8281
8282 elf32_arm_section_data (sec)->erratumcount += 1;
8283
8284 newerr->u.b.vfp_insn = veneer_of_insn;
8285
8286 switch (span_type)
8287 {
8288 case 'a':
8289 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8290 break;
8291
8292 default:
8293 abort ();
8294 }
8295
8296 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8297 first_fmac);
8298
99059e56 8299 newerr->vma = -1;
c7b8f16e 8300
99059e56
RM		 8301 newerr->next = sec_data->erratumlist;
8302 sec_data->erratumlist = newerr;
c7b8f16e 8303
99059e56
RM		 8304 state = 0;
8305 }
c7b8f16e 8306
99059e56
RM		 8307 i = next_i;
8308 }
8309 }
906e58ca 8310
c7b8f16e 8311 if (contents != NULL
99059e56
RM		 8312 && elf_section_data (sec)->this_hdr.contents != contents)
8313 free (contents);
c7b8f16e
JB		 8314 contents = NULL;
8315 }
8316
8317 return TRUE;
8318
8319error_return:
8320 if (contents != NULL
8321 && elf_section_data (sec)->this_hdr.contents != contents)
8322 free (contents);
906e58ca 8323
c7b8f16e
JB		 8324 return FALSE;
8325}
8326
8327/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8328 after sections have been laid out, using specially-named symbols. */
8329
8330void
8331bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8332 struct bfd_link_info *link_info)
8333{
8334 asection *sec;
8335 struct elf32_arm_link_hash_table *globals;
8336 char *tmp_name;
906e58ca 8337
0e1862bb 8338 if (bfd_link_relocatable (link_info))
c7b8f16e 8339 return;
2e6030b9
MS		 8340
8341 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8342 if (! is_arm_elf (abfd))
2e6030b9
MS		 8343 return;
8344
c7b8f16e 8345 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8346 if (globals == NULL)
8347 return;
906e58ca 8348
21d799b5 8349 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8350 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8351
8352 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8353 {
8354 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8355 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8356
c7b8f16e 8357 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8358 {
8359 struct elf_link_hash_entry *myh;
8360 bfd_vma vma;
8361
8362 switch (errnode->type)
8363 {
8364 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8365 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8366 /* Find veneer symbol. */
8367 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8368 errnode->u.b.veneer->u.v.id);
8369
99059e56
RM		 8370 myh = elf_link_hash_lookup
8371 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8372
a504d23a 8373 if (myh == NULL)
90b6238f
AM		 8374 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8375 abfd, "VFP11", tmp_name);
a504d23a
LA		 8376
8377 vma = myh->root.u.def.section->output_section->vma
8378 + myh->root.u.def.section->output_offset
8379 + myh->root.u.def.value;
8380
8381 errnode->u.b.veneer->vma = vma;
8382 break;
8383
8384 case VFP11_ERRATUM_ARM_VENEER:
8385 case VFP11_ERRATUM_THUMB_VENEER:
8386 /* Find return location. */
8387 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8388 errnode->u.v.id);
8389
8390 myh = elf_link_hash_lookup
8391 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8392
8393 if (myh == NULL)
90b6238f
AM		 8394 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8395 abfd, "VFP11", tmp_name);
a504d23a
LA		 8396
8397 vma = myh->root.u.def.section->output_section->vma
8398 + myh->root.u.def.section->output_offset
8399 + myh->root.u.def.value;
8400
8401 errnode->u.v.branch->vma = vma;
8402 break;
8403
8404 default:
8405 abort ();
8406 }
8407 }
8408 }
8409
8410 free (tmp_name);
8411}
8412
8413/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8414 return locations after sections have been laid out, using
8415 specially-named symbols. */
8416
8417void
8418bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8419 struct bfd_link_info *link_info)
8420{
8421 asection *sec;
8422 struct elf32_arm_link_hash_table *globals;
8423 char *tmp_name;
8424
8425 if (bfd_link_relocatable (link_info))
8426 return;
8427
8428 /* Skip if this bfd does not correspond to an ELF image. */
8429 if (! is_arm_elf (abfd))
8430 return;
8431
8432 globals = elf32_arm_hash_table (link_info);
8433 if (globals == NULL)
8434 return;
8435
8436 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8437 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8438
8439 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8440 {
8441 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8442 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8443
8444 for (; errnode != NULL; errnode = errnode->next)
8445 {
8446 struct elf_link_hash_entry *myh;
8447 bfd_vma vma;
8448
8449 switch (errnode->type)
8450 {
8451 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8452 /* Find veneer symbol. */
8453 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8454 errnode->u.b.veneer->u.v.id);
8455
8456 myh = elf_link_hash_lookup
8457 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8458
8459 if (myh == NULL)
90b6238f
AM		 8460 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8461 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8462
8463 vma = myh->root.u.def.section->output_section->vma
8464 + myh->root.u.def.section->output_offset
8465 + myh->root.u.def.value;
8466
8467 errnode->u.b.veneer->vma = vma;
8468 break;
8469
8470 case STM32L4XX_ERRATUM_VENEER:
8471 /* Find return location. */
8472 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8473 errnode->u.v.id);
8474
8475 myh = elf_link_hash_lookup
8476 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8477
8478 if (myh == NULL)
90b6238f
AM		 8479 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8480 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8481
8482 vma = myh->root.u.def.section->output_section->vma
8483 + myh->root.u.def.section->output_offset
8484 + myh->root.u.def.value;
8485
8486 errnode->u.v.branch->vma = vma;
8487 break;
8488
8489 default:
8490 abort ();
8491 }
8492 }
8493 }
8494
8495 free (tmp_name);
8496}
8497
8498static inline bfd_boolean
8499is_thumb2_ldmia (const insn32 insn)
8500{
8501 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8502 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8503 return (insn & 0xffd02000) == 0xe8900000;
8504}
8505
8506static inline bfd_boolean
8507is_thumb2_ldmdb (const insn32 insn)
8508{
8509 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8510 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8511 return (insn & 0xffd02000) == 0xe9100000;
8512}
8513
8514static inline bfd_boolean
8515is_thumb2_vldm (const insn32 insn)
8516{
8517 /* A6.5 Extension register load or store instruction
8518 A7.7.229
9239bbd3
CM		 8519 We look for SP 32-bit and DP 64-bit registers.
8520 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8521 <list> is consecutive 64-bit registers
8522 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8523 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8524 <list> is consecutive 32-bit registers
8525 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8526 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8527 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8528 return
9239bbd3
CM		 8529 (((insn & 0xfe100f00) == 0xec100b00) ||
8530 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8531 && /* (IA without !). */
8532 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8533 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8534 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8535 /* (DB with !). */
8536 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8537}
8538
8539/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8540 VLDM opcode and:
8541 - computes the number and the mode of memory accesses
8542 - decides if the replacement should be done:
8543 . replaces only if > 8-word accesses
8544 . or (testing purposes only) replaces all accesses. */
8545
8546static bfd_boolean
8547stm32l4xx_need_create_replacing_stub (const insn32 insn,
8548 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8549{
9239bbd3 8550 int nb_words = 0;
a504d23a
LA		 8551
8552 /* The field encoding the register list is the same for both LDMIA
8553 and LDMDB encodings. */
8554 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8555 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8556 else if (is_thumb2_vldm (insn))
9239bbd3 8557 nb_words = (insn & 0xff);
a504d23a
LA		 8558
8559 /* DEFAULT mode accounts for the real bug condition situation,
8560 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8561 return
9239bbd3 8562 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8563 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8564}
8565
8566/* Look for potentially-troublesome code sequences which might trigger
8567 the STM STM32L4XX erratum. */
8568
8569bfd_boolean
8570bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8571 struct bfd_link_info *link_info)
8572{
8573 asection *sec;
8574 bfd_byte *contents = NULL;
8575 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8576
8577 if (globals == NULL)
8578 return FALSE;
8579
8580 /* If we are only performing a partial link do not bother
8581 to construct any glue. */
8582 if (bfd_link_relocatable (link_info))
8583 return TRUE;
8584
8585 /* Skip if this bfd does not correspond to an ELF image. */
8586 if (! is_arm_elf (abfd))
8587 return TRUE;
8588
8589 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8590 return TRUE;
8591
8592 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8593 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8594 return TRUE;
8595
8596 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8597 {
8598 unsigned int i, span;
8599 struct _arm_elf_section_data *sec_data;
8600
8601 /* If we don't have executable progbits, we're not interested in this
8602 section. Also skip if section is to be excluded. */
8603 if (elf_section_type (sec) != SHT_PROGBITS
8604 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8605 || (sec->flags & SEC_EXCLUDE) != 0
8606 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8607 || sec->output_section == bfd_abs_section_ptr
8608 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8609 continue;
8610
8611 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8612
a504d23a
LA		 8613 if (sec_data->mapcount == 0)
8614 continue;
c7b8f16e 8615
a504d23a
LA		 8616 if (elf_section_data (sec)->this_hdr.contents != NULL)
8617 contents = elf_section_data (sec)->this_hdr.contents;
8618 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8619 goto error_return;
c7b8f16e 8620
a504d23a
LA		 8621 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8622 elf32_arm_compare_mapping);
c7b8f16e 8623
a504d23a
LA		 8624 for (span = 0; span < sec_data->mapcount; span++)
8625 {
8626 unsigned int span_start = sec_data->map[span].vma;
8627 unsigned int span_end = (span == sec_data->mapcount - 1)
8628 ? sec->size : sec_data->map[span + 1].vma;
8629 char span_type = sec_data->map[span].type;
8630 int itblock_current_pos = 0;
c7b8f16e 8631
a504d23a
LA		 8632 /* Only Thumb2 mode need be supported with this CM4 specific
8633 code, we should not encounter any arm mode eg span_type
8634 != 'a'. */
8635 if (span_type != 't')
8636 continue;
c7b8f16e 8637
a504d23a
LA		 8638 for (i = span_start; i < span_end;)
8639 {
8640 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8641 bfd_boolean insn_32bit = FALSE;
8642 bfd_boolean is_ldm = FALSE;
8643 bfd_boolean is_vldm = FALSE;
8644 bfd_boolean is_not_last_in_it_block = FALSE;
8645
8646 /* The first 16-bits of all 32-bit thumb2 instructions start
8647 with opcode[15..13]=0b111 and the encoded op1 can be anything
8648 except opcode[12..11]!=0b00.
8649 See 32-bit Thumb instruction encoding. */
8650 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8651 insn_32bit = TRUE;
c7b8f16e 8652
a504d23a
LA		 8653 /* Compute the predicate that tells if the instruction
8654 is concerned by the IT block
8655 - Creates an error if there is a ldm that is not
8656 last in the IT block thus cannot be replaced
8657 - Otherwise we can create a branch at the end of the
8658 IT block, it will be controlled naturally by IT
8659 with the proper pseudo-predicate
8660 - So the only interesting predicate is the one that
8661 tells that we are not on the last item of an IT
8662 block. */
8663 if (itblock_current_pos != 0)
8664 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8665
a504d23a
LA		 8666 if (insn_32bit)
8667 {
8668 /* Load the rest of the insn (in manual-friendly order). */
8669 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8670 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8671 is_vldm = is_thumb2_vldm (insn);
8672
8673 /* Veneers are created for (v)ldm depending on
8674 option flags and memory accesses conditions; but
8675 if the instruction is not the last instruction of
8676 an IT block, we cannot create a jump there, so we
8677 bail out. */
5025eb7c
AO		 8678 if ((is_ldm || is_vldm)
8679 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8680 (insn, globals->stm32l4xx_fix))
8681 {
8682 if (is_not_last_in_it_block)
8683 {
4eca0228 8684 _bfd_error_handler
695344c0 8685 /* xgettext:c-format */
871b3ab2 8686 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8687 " in non-last IT block instruction:"
8688 " STM32L4XX veneer cannot be generated; "
8689 "use gcc option -mrestrict-it to generate"
8690 " only one instruction per IT block"),
d42c267e 8691 abfd, sec, i);
a504d23a
LA		 8692 }
8693 else
8694 {
8695 elf32_stm32l4xx_erratum_list *newerr =
8696 (elf32_stm32l4xx_erratum_list *)
8697 bfd_zmalloc
8698 (sizeof (elf32_stm32l4xx_erratum_list));
8699
8700 elf32_arm_section_data (sec)
8701 ->stm32l4xx_erratumcount += 1;
8702 newerr->u.b.insn = insn;
8703 /* We create only thumb branches. */
8704 newerr->type =
8705 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8706 record_stm32l4xx_erratum_veneer
8707 (link_info, newerr, abfd, sec,
8708 i,
8709 is_ldm ?
8710 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8711 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8712 newerr->vma = -1;
8713 newerr->next = sec_data->stm32l4xx_erratumlist;
8714 sec_data->stm32l4xx_erratumlist = newerr;
8715 }
8716 }
8717 }
8718 else
8719 {
8720 /* A7.7.37 IT p208
8721 IT blocks are only encoded in T1
8722 Encoding T1: IT{x{y{z}}} <firstcond>
8723 1 0 1 1 - 1 1 1 1 - firstcond - mask
8724 if mask = '0000' then see 'related encodings'
8725 We don't deal with UNPREDICTABLE, just ignore these.
8726 There can be no nested IT blocks so an IT block
8727 is naturally a new one for which it is worth
8728 computing its size. */
5025eb7c
AO		 8729 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8730 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8731 /* If we have a new IT block we compute its size. */
8732 if (is_newitblock)
8733 {
8734 /* Compute the number of instructions controlled
8735 by the IT block, it will be used to decide
8736 whether we are inside an IT block or not. */
8737 unsigned int mask = insn & 0x000f;
8738 itblock_current_pos = 4 - ctz (mask);
8739 }
8740 }
8741
8742 i += insn_32bit ? 4 : 2;
99059e56
RM		 8743 }
8744 }
a504d23a
LA		 8745
8746 if (contents != NULL
8747 && elf_section_data (sec)->this_hdr.contents != contents)
8748 free (contents);
8749 contents = NULL;
c7b8f16e 8750 }
906e58ca 8751
a504d23a
LA		 8752 return TRUE;
8753
8754error_return:
8755 if (contents != NULL
8756 && elf_section_data (sec)->this_hdr.contents != contents)
8757 free (contents);
c7b8f16e 8758
a504d23a
LA		 8759 return FALSE;
8760}
c7b8f16e 8761
eb043451
PB		 8762/* Set target relocation values needed during linking. */
8763
8764void
68c39892 8765bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8766 struct bfd_link_info *link_info,
68c39892 8767 struct elf32_arm_params *params)
eb043451
PB		 8768{
8769 struct elf32_arm_link_hash_table *globals;
8770
8771 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8772 if (globals == NULL)
8773 return;
eb043451 8774
68c39892
TP		 8775 globals->target1_is_rel = params->target1_is_rel;
8776 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8777 globals->target2_reloc = R_ARM_REL32;
68c39892 8778 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8779 globals->target2_reloc = R_ARM_ABS32;
68c39892 8780 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8781 globals->target2_reloc = R_ARM_GOT_PREL;
8782 else
8783 {
90b6238f 8784 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 8785 params->target2_type);
eb043451 8786 }
68c39892
TP		 8787 globals->fix_v4bx = params->fix_v4bx;
8788 globals->use_blx |= params->use_blx;
8789 globals->vfp11_fix = params->vfp11_denorm_fix;
8790 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8791 globals->pic_veneer = params->pic_veneer;
8792 globals->fix_cortex_a8 = params->fix_cortex_a8;
8793 globals->fix_arm1176 = params->fix_arm1176;
8794 globals->cmse_implib = params->cmse_implib;
8795 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8796
0ffa91dd 8797 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8798 elf_arm_tdata (output_bfd)->no_enum_size_warning
8799 = params->no_enum_size_warning;
8800 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8801 = params->no_wchar_size_warning;
eb043451 8802}
eb043451 8803
12a0a0fd 8804/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8805
12a0a0fd
PB		 8806static void
8807insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8808{
8809 bfd_vma upper;
8810 bfd_vma lower;
8811 int reloc_sign;
8812
8813 BFD_ASSERT ((offset & 1) == 0);
8814
8815 upper = bfd_get_16 (abfd, insn);
8816 lower = bfd_get_16 (abfd, insn + 2);
8817 reloc_sign = (offset < 0) ? 1 : 0;
8818 upper = (upper & ~(bfd_vma) 0x7ff)
8819 | ((offset >> 12) & 0x3ff)
8820 | (reloc_sign << 10);
906e58ca 8821 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8822 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8823 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8824 | ((offset >> 1) & 0x7ff);
8825 bfd_put_16 (abfd, upper, insn);
8826 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8827}
8828
9b485d32
NC		 8829/* Thumb code calling an ARM function. */
8830
252b5132 8831static int
57e8b36a 8832elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 8833 const char * name,
8834 bfd * input_bfd,
8835 bfd * output_bfd,
8836 asection * input_section,
8837 bfd_byte * hit_data,
8838 asection * sym_sec,
8839 bfd_vma offset,
8840 bfd_signed_vma addend,
8841 bfd_vma val,
f2a9dd69 8842 char **error_message)
252b5132 8843{
bcbdc74c 8844 asection * s = 0;
dc810e39 8845 bfd_vma my_offset;
252b5132 8846 long int ret_offset;
bcbdc74c
NC		 8847 struct elf_link_hash_entry * myh;
8848 struct elf32_arm_link_hash_table * globals;
252b5132 8849
f2a9dd69 8850 myh = find_thumb_glue (info, name, error_message);
252b5132 8851 if (myh == NULL)
b34976b6 8852 return FALSE;
252b5132
RH		 8853
8854 globals = elf32_arm_hash_table (info);
252b5132
RH		 8855 BFD_ASSERT (globals != NULL);
8856 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8857
8858 my_offset = myh->root.u.def.value;
8859
3d4d4302
AM		 8860 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8861 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8862
8863 BFD_ASSERT (s != NULL);
8864 BFD_ASSERT (s->contents != NULL);
8865 BFD_ASSERT (s->output_section != NULL);
8866
8867 if ((my_offset & 0x01) == 0x01)
8868 {
8869 if (sym_sec != NULL
8870 && sym_sec->owner != NULL
8871 && !INTERWORK_FLAG (sym_sec->owner))
8872 {
4eca0228 8873 _bfd_error_handler
90b6238f
AM		 8874 (_("%pB(%s): warning: interworking not enabled;"
8875 " first occurrence: %pB: %s call to %s"),
8876 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 8877
b34976b6 8878 return FALSE;
252b5132
RH		 8879 }
8880
8881 --my_offset;
8882 myh->root.u.def.value = my_offset;
8883
52ab56c2
PB		 8884 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8885 s->contents + my_offset);
252b5132 8886
52ab56c2
PB		 8887 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8888 s->contents + my_offset + 2);
252b5132
RH		 8889
8890 ret_offset =
9b485d32
NC		 8891 /* Address of destination of the stub. */
8892 ((bfd_signed_vma) val)
252b5132 8893 - ((bfd_signed_vma)
57e8b36a
NC		 8894 /* Offset from the start of the current section
8895 to the start of the stubs. */
9b485d32
NC		 8896 (s->output_offset
8897 /* Offset of the start of this stub from the start of the stubs. */
8898 + my_offset
8899 /* Address of the start of the current section. */
8900 + s->output_section->vma)
8901 /* The branch instruction is 4 bytes into the stub. */
8902 + 4
8903 /* ARM branches work from the pc of the instruction + 8. */
8904 + 8);
252b5132 8905
52ab56c2
PB		 8906 put_arm_insn (globals, output_bfd,
8907 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8908 s->contents + my_offset + 4);
252b5132
RH		 8909 }
8910
8911 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8912
427bfd90
NC		 8913 /* Now go back and fix up the original BL insn to point to here. */
8914 ret_offset =
8915 /* Address of where the stub is located. */
8916 (s->output_section->vma + s->output_offset + my_offset)
8917 /* Address of where the BL is located. */
57e8b36a
NC		 8918 - (input_section->output_section->vma + input_section->output_offset
8919 + offset)
427bfd90
NC		 8920 /* Addend in the relocation. */
8921 - addend
8922 /* Biassing for PC-relative addressing. */
8923 - 8;
252b5132 8924
12a0a0fd 8925 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8926
b34976b6 8927 return TRUE;
252b5132
RH		 8928}
8929
a4fd1a8e 8930/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8931
a4fd1a8e
PB		 8932static struct elf_link_hash_entry *
8933elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 8934 const char * name,
8935 bfd * input_bfd,
8936 bfd * output_bfd,
8937 asection * sym_sec,
8938 bfd_vma val,
8939 asection * s,
8940 char ** error_message)
252b5132 8941{
dc810e39 8942 bfd_vma my_offset;
252b5132 8943 long int ret_offset;
bcbdc74c
NC		 8944 struct elf_link_hash_entry * myh;
8945 struct elf32_arm_link_hash_table * globals;
252b5132 8946
f2a9dd69 8947 myh = find_arm_glue (info, name, error_message);
252b5132 8948 if (myh == NULL)
a4fd1a8e 8949 return NULL;
252b5132
RH		 8950
8951 globals = elf32_arm_hash_table (info);
252b5132
RH		 8952 BFD_ASSERT (globals != NULL);
8953 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8954
8955 my_offset = myh->root.u.def.value;
252b5132
RH		 8956
8957 if ((my_offset & 0x01) == 0x01)
8958 {
8959 if (sym_sec != NULL
8960 && sym_sec->owner != NULL
8961 && !INTERWORK_FLAG (sym_sec->owner))
8962 {
4eca0228 8963 _bfd_error_handler
90b6238f
AM		 8964 (_("%pB(%s): warning: interworking not enabled;"
8965 " first occurrence: %pB: %s call to %s"),
8966 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 8967 }
9b485d32 8968
252b5132
RH		 8969 --my_offset;
8970 myh->root.u.def.value = my_offset;
8971
0e1862bb
L		 8972 if (bfd_link_pic (info)
8973 || globals->root.is_relocatable_executable
27e55c4d 8974 || globals->pic_veneer)
8f6277f5
PB		 8975 {
8976 /* For relocatable objects we can't use absolute addresses,
8977 so construct the address from a relative offset. */
8978 /* TODO: If the offset is small it's probably worth
8979 constructing the address with adds. */
52ab56c2
PB		 8980 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8981 s->contents + my_offset);
8982 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8983 s->contents + my_offset + 4);
8984 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8985 s->contents + my_offset + 8);
8f6277f5
PB		 8986 /* Adjust the offset by 4 for the position of the add,
8987 and 8 for the pipeline offset. */
8988 ret_offset = (val - (s->output_offset
8989 + s->output_section->vma
8990 + my_offset + 12))
8991 | 1;
8992 bfd_put_32 (output_bfd, ret_offset,
8993 s->contents + my_offset + 12);
8994 }
26079076
PB		 8995 else if (globals->use_blx)
8996 {
8997 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8998 s->contents + my_offset);
8999
9000 /* It's a thumb address. Add the low order bit. */
9001 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9002 s->contents + my_offset + 4);
9003 }
8f6277f5
PB		 9004 else
9005 {
52ab56c2
PB		 9006 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9007 s->contents + my_offset);
252b5132 9008
52ab56c2
PB		 9009 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9010 s->contents + my_offset + 4);
252b5132 9011
8f6277f5
PB		 9012 /* It's a thumb address. Add the low order bit. */
9013 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9014 s->contents + my_offset + 8);
8029a119
NC		 9015
9016 my_offset += 12;
8f6277f5 9017 }
252b5132
RH		 9018 }
9019
9020 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9021
a4fd1a8e
PB		 9022 return myh;
9023}
9024
9025/* Arm code calling a Thumb function. */
9026
9027static int
9028elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9029 const char * name,
9030 bfd * input_bfd,
9031 bfd * output_bfd,
9032 asection * input_section,
9033 bfd_byte * hit_data,
9034 asection * sym_sec,
9035 bfd_vma offset,
9036 bfd_signed_vma addend,
9037 bfd_vma val,
f2a9dd69 9038 char **error_message)
a4fd1a8e
PB		 9039{
9040 unsigned long int tmp;
9041 bfd_vma my_offset;
9042 asection * s;
9043 long int ret_offset;
9044 struct elf_link_hash_entry * myh;
9045 struct elf32_arm_link_hash_table * globals;
9046
9047 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9048 BFD_ASSERT (globals != NULL);
9049 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9050
3d4d4302
AM		 9051 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9052 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9053 BFD_ASSERT (s != NULL);
9054 BFD_ASSERT (s->contents != NULL);
9055 BFD_ASSERT (s->output_section != NULL);
9056
9057 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9058 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9059 if (!myh)
9060 return FALSE;
9061
9062 my_offset = myh->root.u.def.value;
252b5132
RH		 9063 tmp = bfd_get_32 (input_bfd, hit_data);
9064 tmp = tmp & 0xFF000000;
9065
9b485d32 9066 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9067 ret_offset = (s->output_offset
9068 + my_offset
9069 + s->output_section->vma
9070 - (input_section->output_offset
9071 + input_section->output_section->vma
9072 + offset + addend)
9073 - 8);
9a5aca8c 9074
252b5132
RH		 9075 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9076
dc810e39 9077 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9078
b34976b6 9079 return TRUE;
252b5132
RH		 9080}
9081
a4fd1a8e
PB		 9082/* Populate Arm stub for an exported Thumb function. */
9083
9084static bfd_boolean
9085elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9086{
9087 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9088 asection * s;
9089 struct elf_link_hash_entry * myh;
9090 struct elf32_arm_link_hash_entry *eh;
9091 struct elf32_arm_link_hash_table * globals;
9092 asection *sec;
9093 bfd_vma val;
f2a9dd69 9094 char *error_message;
a4fd1a8e 9095
906e58ca 9096 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9097 /* Allocate stubs for exported Thumb functions on v4t. */
9098 if (eh->export_glue == NULL)
9099 return TRUE;
9100
9101 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9102 BFD_ASSERT (globals != NULL);
9103 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9104
3d4d4302
AM		 9105 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9106 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9107 BFD_ASSERT (s != NULL);
9108 BFD_ASSERT (s->contents != NULL);
9109 BFD_ASSERT (s->output_section != NULL);
9110
9111 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9112
9113 BFD_ASSERT (sec->output_section != NULL);
9114
a4fd1a8e
PB		 9115 val = eh->export_glue->root.u.def.value + sec->output_offset
9116 + sec->output_section->vma;
8029a119 9117
a4fd1a8e
PB		 9118 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9119 h->root.u.def.section->owner,
f2a9dd69
DJ		 9120 globals->obfd, sec, val, s,
9121 &error_message);
a4fd1a8e
PB		 9122 BFD_ASSERT (myh);
9123 return TRUE;
9124}
9125
845b51d6
PB		 9126/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9127
9128static bfd_vma
9129elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9130{
9131 bfd_byte *p;
9132 bfd_vma glue_addr;
9133 asection *s;
9134 struct elf32_arm_link_hash_table *globals;
9135
9136 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9137 BFD_ASSERT (globals != NULL);
9138 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9139
3d4d4302
AM		 9140 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9141 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9142 BFD_ASSERT (s != NULL);
9143 BFD_ASSERT (s->contents != NULL);
9144 BFD_ASSERT (s->output_section != NULL);
9145
9146 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9147
9148 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9149
9150 if ((globals->bx_glue_offset[reg] & 1) == 0)
9151 {
9152 p = s->contents + glue_addr;
9153 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9154 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9155 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9156 globals->bx_glue_offset[reg] |= 1;
9157 }
9158
9159 return glue_addr + s->output_section->vma + s->output_offset;
9160}
9161
a4fd1a8e
PB		 9162/* Generate Arm stubs for exported Thumb symbols. */
9163static void
906e58ca 9164elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9165 struct bfd_link_info *link_info)
9166{
9167 struct elf32_arm_link_hash_table * globals;
9168
8029a119
NC		 9169 if (link_info == NULL)
9170 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9171 return;
9172
9173 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9174 if (globals == NULL)
9175 return;
9176
84c08195
PB		 9177 /* If blx is available then exported Thumb symbols are OK and there is
9178 nothing to do. */
a4fd1a8e
PB		 9179 if (globals->use_blx)
9180 return;
9181
9182 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9183 link_info);
9184}
9185
47beaa6a
RS		 9186/* Reserve space for COUNT dynamic relocations in relocation selection
9187 SRELOC. */
9188
9189static void
9190elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9191 bfd_size_type count)
9192{
9193 struct elf32_arm_link_hash_table *htab;
9194
9195 htab = elf32_arm_hash_table (info);
9196 BFD_ASSERT (htab->root.dynamic_sections_created);
9197 if (sreloc == NULL)
9198 abort ();
9199 sreloc->size += RELOC_SIZE (htab) * count;
9200}
9201
34e77a92
RS		 9202/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9203 dynamic, the relocations should go in SRELOC, otherwise they should
9204 go in the special .rel.iplt section. */
9205
9206static void
9207elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9208 bfd_size_type count)
9209{
9210 struct elf32_arm_link_hash_table *htab;
9211
9212 htab = elf32_arm_hash_table (info);
9213 if (!htab->root.dynamic_sections_created)
9214 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9215 else
9216 {
9217 BFD_ASSERT (sreloc != NULL);
9218 sreloc->size += RELOC_SIZE (htab) * count;
9219 }
9220}
9221
47beaa6a
RS		 9222/* Add relocation REL to the end of relocation section SRELOC. */
9223
9224static void
9225elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9226 asection *sreloc, Elf_Internal_Rela *rel)
9227{
9228 bfd_byte *loc;
9229 struct elf32_arm_link_hash_table *htab;
9230
9231 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9232 if (!htab->root.dynamic_sections_created
9233 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9234 sreloc = htab->root.irelplt;
47beaa6a
RS		 9235 if (sreloc == NULL)
9236 abort ();
9237 loc = sreloc->contents;
9238 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9239 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9240 abort ();
9241 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9242}
9243
34e77a92
RS		 9244/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9245 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9246 to .plt. */
9247
9248static void
9249elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9250 bfd_boolean is_iplt_entry,
9251 union gotplt_union *root_plt,
9252 struct arm_plt_info *arm_plt)
9253{
9254 struct elf32_arm_link_hash_table *htab;
9255 asection *splt;
9256 asection *sgotplt;
9257
9258 htab = elf32_arm_hash_table (info);
9259
9260 if (is_iplt_entry)
9261 {
9262 splt = htab->root.iplt;
9263 sgotplt = htab->root.igotplt;
9264
99059e56
RM		 9265 /* NaCl uses a special first entry in .iplt too. */
9266 if (htab->nacl_p && splt->size == 0)
9267 splt->size += htab->plt_header_size;
9268
34e77a92
RS		 9269 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9270 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9271 }
9272 else
9273 {
9274 splt = htab->root.splt;
9275 sgotplt = htab->root.sgotplt;
9276
9277 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9278 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9279
9280 /* If this is the first .plt entry, make room for the special
9281 first entry. */
9282 if (splt->size == 0)
9283 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9284
9285 htab->next_tls_desc_index++;
34e77a92
RS		 9286 }
9287
9288 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9289 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9290 splt->size += PLT_THUMB_STUB_SIZE;
9291 root_plt->offset = splt->size;
9292 splt->size += htab->plt_entry_size;
9293
9294 if (!htab->symbian_p)
9295 {
9296 /* We also need to make an entry in the .got.plt section, which
9297 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9298 if (is_iplt_entry)
9299 arm_plt->got_offset = sgotplt->size;
9300 else
9301 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9302 sgotplt->size += 4;
9303 }
9304}
9305
b38cadfb
NC		 9306static bfd_vma
9307arm_movw_immediate (bfd_vma value)
9308{
9309 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9310}
9311
9312static bfd_vma
9313arm_movt_immediate (bfd_vma value)
9314{
9315 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9316}
9317
34e77a92
RS		 9318/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9319 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9320 Otherwise, DYNINDX is the index of the symbol in the dynamic
9321 symbol table and SYM_VALUE is undefined.
9322
9323 ROOT_PLT points to the offset of the PLT entry from the start of its
9324 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9325 bookkeeping information.
34e77a92 9326
57460bcf
NC		 9327 Returns FALSE if there was a problem. */
9328
9329static bfd_boolean
34e77a92
RS		 9330elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9331 union gotplt_union *root_plt,
9332 struct arm_plt_info *arm_plt,
9333 int dynindx, bfd_vma sym_value)
9334{
9335 struct elf32_arm_link_hash_table *htab;
9336 asection *sgot;
9337 asection *splt;
9338 asection *srel;
9339 bfd_byte *loc;
9340 bfd_vma plt_index;
9341 Elf_Internal_Rela rel;
9342 bfd_vma plt_header_size;
9343 bfd_vma got_header_size;
9344
9345 htab = elf32_arm_hash_table (info);
9346
9347 /* Pick the appropriate sections and sizes. */
9348 if (dynindx == -1)
9349 {
9350 splt = htab->root.iplt;
9351 sgot = htab->root.igotplt;
9352 srel = htab->root.irelplt;
9353
9354 /* There are no reserved entries in .igot.plt, and no special
9355 first entry in .iplt. */
9356 got_header_size = 0;
9357 plt_header_size = 0;
9358 }
9359 else
9360 {
9361 splt = htab->root.splt;
9362 sgot = htab->root.sgotplt;
9363 srel = htab->root.srelplt;
9364
9365 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9366 plt_header_size = htab->plt_header_size;
9367 }
9368 BFD_ASSERT (splt != NULL && srel != NULL);
9369
9370 /* Fill in the entry in the procedure linkage table. */
9371 if (htab->symbian_p)
9372 {
9373 BFD_ASSERT (dynindx >= 0);
9374 put_arm_insn (htab, output_bfd,
9375 elf32_arm_symbian_plt_entry[0],
9376 splt->contents + root_plt->offset);
9377 bfd_put_32 (output_bfd,
9378 elf32_arm_symbian_plt_entry[1],
9379 splt->contents + root_plt->offset + 4);
9380
9381 /* Fill in the entry in the .rel.plt section. */
9382 rel.r_offset = (splt->output_section->vma
9383 + splt->output_offset
9384 + root_plt->offset + 4);
9385 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9386
9387 /* Get the index in the procedure linkage table which
9388 corresponds to this symbol. This is the index of this symbol
9389 in all the symbols for which we are making plt entries. The
9390 first entry in the procedure linkage table is reserved. */
9391 plt_index = ((root_plt->offset - plt_header_size)
9392 / htab->plt_entry_size);
9393 }
9394 else
9395 {
9396 bfd_vma got_offset, got_address, plt_address;
9397 bfd_vma got_displacement, initial_got_entry;
9398 bfd_byte * ptr;
9399
9400 BFD_ASSERT (sgot != NULL);
9401
9402 /* Get the offset into the .(i)got.plt table of the entry that
9403 corresponds to this function. */
9404 got_offset = (arm_plt->got_offset & -2);
9405
9406 /* Get the index in the procedure linkage table which
9407 corresponds to this symbol. This is the index of this symbol
9408 in all the symbols for which we are making plt entries.
9409 After the reserved .got.plt entries, all symbols appear in
9410 the same order as in .plt. */
9411 plt_index = (got_offset - got_header_size) / 4;
9412
9413 /* Calculate the address of the GOT entry. */
9414 got_address = (sgot->output_section->vma
9415 + sgot->output_offset
9416 + got_offset);
9417
9418 /* ...and the address of the PLT entry. */
9419 plt_address = (splt->output_section->vma
9420 + splt->output_offset
9421 + root_plt->offset);
9422
9423 ptr = splt->contents + root_plt->offset;
0e1862bb 9424 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9425 {
9426 unsigned int i;
9427 bfd_vma val;
9428
9429 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9430 {
9431 val = elf32_arm_vxworks_shared_plt_entry[i];
9432 if (i == 2)
9433 val |= got_address - sgot->output_section->vma;
9434 if (i == 5)
9435 val |= plt_index * RELOC_SIZE (htab);
9436 if (i == 2 || i == 5)
9437 bfd_put_32 (output_bfd, val, ptr);
9438 else
9439 put_arm_insn (htab, output_bfd, val, ptr);
9440 }
9441 }
9442 else if (htab->vxworks_p)
9443 {
9444 unsigned int i;
9445 bfd_vma val;
9446
9447 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9448 {
9449 val = elf32_arm_vxworks_exec_plt_entry[i];
9450 if (i == 2)
9451 val |= got_address;
9452 if (i == 4)
9453 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9454 if (i == 5)
9455 val |= plt_index * RELOC_SIZE (htab);
9456 if (i == 2 || i == 5)
9457 bfd_put_32 (output_bfd, val, ptr);
9458 else
9459 put_arm_insn (htab, output_bfd, val, ptr);
9460 }
9461
9462 loc = (htab->srelplt2->contents
9463 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9464
9465 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9466 referencing the GOT for this PLT entry. */
9467 rel.r_offset = plt_address + 8;
9468 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9469 rel.r_addend = got_offset;
9470 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9471 loc += RELOC_SIZE (htab);
9472
9473 /* Create the R_ARM_ABS32 relocation referencing the
9474 beginning of the PLT for this GOT entry. */
9475 rel.r_offset = got_address;
9476 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9477 rel.r_addend = 0;
9478 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9479 }
b38cadfb
NC		 9480 else if (htab->nacl_p)
9481 {
9482 /* Calculate the displacement between the PLT slot and the
9483 common tail that's part of the special initial PLT slot. */
6034aab8 9484 int32_t tail_displacement
b38cadfb
NC		 9485 = ((splt->output_section->vma + splt->output_offset
9486 + ARM_NACL_PLT_TAIL_OFFSET)
9487 - (plt_address + htab->plt_entry_size + 4));
9488 BFD_ASSERT ((tail_displacement & 3) == 0);
9489 tail_displacement >>= 2;
9490
9491 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9492 || (-tail_displacement & 0xff000000) == 0);
9493
9494 /* Calculate the displacement between the PLT slot and the entry
9495 in the GOT. The offset accounts for the value produced by
9496 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9497 got_displacement = (got_address
99059e56 9498 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9499
9500 /* NaCl does not support interworking at all. */
9501 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9502
9503 put_arm_insn (htab, output_bfd,
9504 elf32_arm_nacl_plt_entry[0]
9505 | arm_movw_immediate (got_displacement),
9506 ptr + 0);
9507 put_arm_insn (htab, output_bfd,
9508 elf32_arm_nacl_plt_entry[1]
9509 | arm_movt_immediate (got_displacement),
9510 ptr + 4);
9511 put_arm_insn (htab, output_bfd,
9512 elf32_arm_nacl_plt_entry[2],
9513 ptr + 8);
9514 put_arm_insn (htab, output_bfd,
9515 elf32_arm_nacl_plt_entry[3]
9516 | (tail_displacement & 0x00ffffff),
9517 ptr + 12);
9518 }
57460bcf
NC		 9519 else if (using_thumb_only (htab))
9520 {
eed94f8f 9521 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9522 if (!using_thumb2 (htab))
eed94f8f
NC		 9523 {
9524 /* FIXME: We ought to be able to generate thumb-1 PLT
9525 instructions... */
90b6238f 9526 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9527 output_bfd);
9528 return FALSE;
9529 }
57460bcf 9530
eed94f8f
NC		 9531 /* Calculate the displacement between the PLT slot and the entry in
9532 the GOT. The 12-byte offset accounts for the value produced by
9533 adding to pc in the 3rd instruction of the PLT stub. */
9534 got_displacement = got_address - (plt_address + 12);
9535
9536 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9537 instead of 'put_thumb_insn'. */
9538 put_arm_insn (htab, output_bfd,
9539 elf32_thumb2_plt_entry[0]
9540 | ((got_displacement & 0x000000ff) << 16)
9541 | ((got_displacement & 0x00000700) << 20)
9542 | ((got_displacement & 0x00000800) >> 1)
9543 | ((got_displacement & 0x0000f000) >> 12),
9544 ptr + 0);
9545 put_arm_insn (htab, output_bfd,
9546 elf32_thumb2_plt_entry[1]
9547 | ((got_displacement & 0x00ff0000) )
9548 | ((got_displacement & 0x07000000) << 4)
9549 | ((got_displacement & 0x08000000) >> 17)
9550 | ((got_displacement & 0xf0000000) >> 28),
9551 ptr + 4);
9552 put_arm_insn (htab, output_bfd,
9553 elf32_thumb2_plt_entry[2],
9554 ptr + 8);
9555 put_arm_insn (htab, output_bfd,
9556 elf32_thumb2_plt_entry[3],
9557 ptr + 12);
57460bcf 9558 }
34e77a92
RS		 9559 else
9560 {
9561 /* Calculate the displacement between the PLT slot and the
9562 entry in the GOT. The eight-byte offset accounts for the
9563 value produced by adding to pc in the first instruction
9564 of the PLT stub. */
9565 got_displacement = got_address - (plt_address + 8);
9566
34e77a92
RS		 9567 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9568 {
9569 put_thumb_insn (htab, output_bfd,
9570 elf32_arm_plt_thumb_stub[0], ptr - 4);
9571 put_thumb_insn (htab, output_bfd,
9572 elf32_arm_plt_thumb_stub[1], ptr - 2);
9573 }
9574
1db37fe6
YG		 9575 if (!elf32_arm_use_long_plt_entry)
9576 {
9577 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9578
9579 put_arm_insn (htab, output_bfd,
9580 elf32_arm_plt_entry_short[0]
9581 | ((got_displacement & 0x0ff00000) >> 20),
9582 ptr + 0);
9583 put_arm_insn (htab, output_bfd,
9584 elf32_arm_plt_entry_short[1]
9585 | ((got_displacement & 0x000ff000) >> 12),
9586 ptr+ 4);
9587 put_arm_insn (htab, output_bfd,
9588 elf32_arm_plt_entry_short[2]
9589 | (got_displacement & 0x00000fff),
9590 ptr + 8);
34e77a92 9591#ifdef FOUR_WORD_PLT
1db37fe6 9592 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9593#endif
1db37fe6
YG		 9594 }
9595 else
9596 {
9597 put_arm_insn (htab, output_bfd,
9598 elf32_arm_plt_entry_long[0]
9599 | ((got_displacement & 0xf0000000) >> 28),
9600 ptr + 0);
9601 put_arm_insn (htab, output_bfd,
9602 elf32_arm_plt_entry_long[1]
9603 | ((got_displacement & 0x0ff00000) >> 20),
9604 ptr + 4);
9605 put_arm_insn (htab, output_bfd,
9606 elf32_arm_plt_entry_long[2]
9607 | ((got_displacement & 0x000ff000) >> 12),
9608 ptr+ 8);
9609 put_arm_insn (htab, output_bfd,
9610 elf32_arm_plt_entry_long[3]
9611 | (got_displacement & 0x00000fff),
9612 ptr + 12);
9613 }
34e77a92
RS		 9614 }
9615
9616 /* Fill in the entry in the .rel(a).(i)plt section. */
9617 rel.r_offset = got_address;
9618 rel.r_addend = 0;
9619 if (dynindx == -1)
9620 {
9621 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9622 The dynamic linker or static executable then calls SYM_VALUE
9623 to determine the correct run-time value of the .igot.plt entry. */
9624 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9625 initial_got_entry = sym_value;
9626 }
9627 else
9628 {
9629 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9630 initial_got_entry = (splt->output_section->vma
9631 + splt->output_offset);
9632 }
9633
9634 /* Fill in the entry in the global offset table. */
9635 bfd_put_32 (output_bfd, initial_got_entry,
9636 sgot->contents + got_offset);
9637 }
9638
aba8c3de
WN		 9639 if (dynindx == -1)
9640 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9641 else
9642 {
9643 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9644 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9645 }
57460bcf
NC		 9646
9647 return TRUE;
34e77a92
RS		 9648}
9649
eb043451
PB		 9650/* Some relocations map to different relocations depending on the
9651 target. Return the real relocation. */
8029a119 9652
eb043451
PB		 9653static int
9654arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9655 int r_type)
9656{
9657 switch (r_type)
9658 {
9659 case R_ARM_TARGET1:
9660 if (globals->target1_is_rel)
9661 return R_ARM_REL32;
9662 else
9663 return R_ARM_ABS32;
9664
9665 case R_ARM_TARGET2:
9666 return globals->target2_reloc;
9667
9668 default:
9669 return r_type;
9670 }
9671}
eb043451 9672
ba93b8ac
DJ		 9673/* Return the base VMA address which should be subtracted from real addresses
9674 when resolving @dtpoff relocation.
9675 This is PT_TLS segment p_vaddr. */
9676
9677static bfd_vma
9678dtpoff_base (struct bfd_link_info *info)
9679{
9680 /* If tls_sec is NULL, we should have signalled an error already. */
9681 if (elf_hash_table (info)->tls_sec == NULL)
9682 return 0;
9683 return elf_hash_table (info)->tls_sec->vma;
9684}
9685
9686/* Return the relocation value for @tpoff relocation
9687 if STT_TLS virtual address is ADDRESS. */
9688
9689static bfd_vma
9690tpoff (struct bfd_link_info *info, bfd_vma address)
9691{
9692 struct elf_link_hash_table *htab = elf_hash_table (info);
9693 bfd_vma base;
9694
9695 /* If tls_sec is NULL, we should have signalled an error already. */
9696 if (htab->tls_sec == NULL)
9697 return 0;
9698 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9699 return address - htab->tls_sec->vma + base;
9700}
9701
00a97672
RS		 9702/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9703 VALUE is the relocation value. */
9704
9705static bfd_reloc_status_type
9706elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9707{
9708 if (value > 0xfff)
9709 return bfd_reloc_overflow;
9710
9711 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9712 bfd_put_32 (abfd, value, data);
9713 return bfd_reloc_ok;
9714}
9715
0855e32b
NS		 9716/* Handle TLS relaxations. Relaxing is possible for symbols that use
9717 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9718 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9719
9720 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9721 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9722 case of error.
9723
9724 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9725 the pre-relaxed code. It would be nice if the relocs were updated
9726 to match the optimization. */
0855e32b 9727
b38cadfb 9728static bfd_reloc_status_type
0855e32b 9729elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9730 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9731 Elf_Internal_Rela *rel, unsigned long is_local)
9732{
9733 unsigned long insn;
b38cadfb 9734
0855e32b
NS		 9735 switch (ELF32_R_TYPE (rel->r_info))
9736 {
9737 default:
9738 return bfd_reloc_notsupported;
b38cadfb 9739
0855e32b
NS		 9740 case R_ARM_TLS_GOTDESC:
9741 if (is_local)
9742 insn = 0;
9743 else
9744 {
9745 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9746 if (insn & 1)
9747 insn -= 5; /* THUMB */
9748 else
9749 insn -= 8; /* ARM */
9750 }
9751 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9752 return bfd_reloc_continue;
9753
9754 case R_ARM_THM_TLS_DESCSEQ:
9755 /* Thumb insn. */
9756 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9757 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9758 {
9759 if (is_local)
9760 /* nop */
9761 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9762 }
9763 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9764 {
9765 if (is_local)
9766 /* nop */
9767 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9768 else
9769 /* ldr rx,[ry] */
9770 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9771 }
9772 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9773 {
9774 if (is_local)
9775 /* nop */
9776 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9777 else
9778 /* mov r0, rx */
9779 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9780 contents + rel->r_offset);
9781 }
9782 else
9783 {
9784 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9785 /* It's a 32 bit instruction, fetch the rest of it for
9786 error generation. */
9787 insn = (insn << 16)
9788 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9789 _bfd_error_handler
695344c0 9790 /* xgettext:c-format */
2dcf00ce 9791 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 9792 "unexpected %s instruction '%#lx' in TLS trampoline"),
9793 input_bfd, input_sec, (uint64_t) rel->r_offset,
9794 "Thumb", insn);
0855e32b
NS		 9795 return bfd_reloc_notsupported;
9796 }
9797 break;
b38cadfb 9798
0855e32b
NS		 9799 case R_ARM_TLS_DESCSEQ:
9800 /* arm insn. */
9801 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9802 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9803 {
9804 if (is_local)
9805 /* mov rx, ry */
9806 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9807 contents + rel->r_offset);
9808 }
9809 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9810 {
9811 if (is_local)
9812 /* nop */
9813 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9814 else
9815 /* ldr rx,[ry] */
9816 bfd_put_32 (input_bfd, insn & 0xfffff000,
9817 contents + rel->r_offset);
9818 }
9819 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9820 {
9821 if (is_local)
9822 /* nop */
9823 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9824 else
9825 /* mov r0, rx */
9826 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9827 contents + rel->r_offset);
9828 }
9829 else
9830 {
4eca0228 9831 _bfd_error_handler
695344c0 9832 /* xgettext:c-format */
2dcf00ce 9833 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 9834 "unexpected %s instruction '%#lx' in TLS trampoline"),
9835 input_bfd, input_sec, (uint64_t) rel->r_offset,
9836 "ARM", insn);
0855e32b
NS		 9837 return bfd_reloc_notsupported;
9838 }
9839 break;
9840
9841 case R_ARM_TLS_CALL:
9842 /* GD->IE relaxation, turn the instruction into 'nop' or
9843 'ldr r0, [pc,r0]' */
9844 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9845 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9846 break;
b38cadfb 9847
0855e32b 9848 case R_ARM_THM_TLS_CALL:
6a631e86 9849 /* GD->IE relaxation. */
0855e32b
NS		 9850 if (!is_local)
9851 /* add r0,pc; ldr r0, [r0] */
9852 insn = 0x44786800;
60a019a0 9853 else if (using_thumb2 (globals))
0855e32b
NS		 9854 /* nop.w */
9855 insn = 0xf3af8000;
9856 else
9857 /* nop; nop */
9858 insn = 0xbf00bf00;
b38cadfb 9859
0855e32b
NS		 9860 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9861 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9862 break;
9863 }
9864 return bfd_reloc_ok;
9865}
9866
4962c51a
MS		 9867/* For a given value of n, calculate the value of G_n as required to
9868 deal with group relocations. We return it in the form of an
9869 encoded constant-and-rotation, together with the final residual. If n is
9870 specified as less than zero, then final_residual is filled with the
9871 input value and no further action is performed. */
9872
9873static bfd_vma
9874calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9875{
9876 int current_n;
9877 bfd_vma g_n;
9878 bfd_vma encoded_g_n = 0;
9879 bfd_vma residual = value; /* Also known as Y_n. */
9880
9881 for (current_n = 0; current_n <= n; current_n++)
9882 {
9883 int shift;
9884
9885 /* Calculate which part of the value to mask. */
9886 if (residual == 0)
99059e56 9887 shift = 0;
4962c51a 9888 else
99059e56
RM		 9889 {
9890 int msb;
9891
9892 /* Determine the most significant bit in the residual and
9893 align the resulting value to a 2-bit boundary. */
9894 for (msb = 30; msb >= 0; msb -= 2)
9895 if (residual & (3 << msb))
9896 break;
9897
9898 /* The desired shift is now (msb - 6), or zero, whichever
9899 is the greater. */
9900 shift = msb - 6;
9901 if (shift < 0)
9902 shift = 0;
9903 }
4962c51a
MS		 9904
9905 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9906 g_n = residual & (0xff << shift);
9907 encoded_g_n = (g_n >> shift)
99059e56 9908 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9909
9910 /* Calculate the residual for the next time around. */
9911 residual &= ~g_n;
9912 }
9913
9914 *final_residual = residual;
9915
9916 return encoded_g_n;
9917}
9918
9919/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9920 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9921
4962c51a 9922static int
906e58ca 9923identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9924{
9925 int opcode = insn & 0x1e00000;
9926
9927 if (opcode == 1 << 23) /* ADD */
9928 return 1;
9929
9930 if (opcode == 1 << 22) /* SUB */
9931 return -1;
9932
9933 return 0;
9934}
9935
252b5132 9936/* Perform a relocation as part of a final link. */
9b485d32 9937
252b5132 9938static bfd_reloc_status_type
07d6d2b8
AM		 9939elf32_arm_final_link_relocate (reloc_howto_type * howto,
9940 bfd * input_bfd,
9941 bfd * output_bfd,
9942 asection * input_section,
9943 bfd_byte * contents,
9944 Elf_Internal_Rela * rel,
9945 bfd_vma value,
9946 struct bfd_link_info * info,
9947 asection * sym_sec,
9948 const char * sym_name,
9949 unsigned char st_type,
9950 enum arm_st_branch_type branch_type,
0945cdfd 9951 struct elf_link_hash_entry * h,
07d6d2b8
AM		 9952 bfd_boolean * unresolved_reloc_p,
9953 char ** error_message)
9954{
9955 unsigned long r_type = howto->type;
9956 unsigned long r_symndx;
9957 bfd_byte * hit_data = contents + rel->r_offset;
9958 bfd_vma * local_got_offsets;
9959 bfd_vma * local_tlsdesc_gotents;
9960 asection * sgot;
9961 asection * splt;
9962 asection * sreloc = NULL;
9963 asection * srelgot;
9964 bfd_vma addend;
9965 bfd_signed_vma signed_addend;
9966 unsigned char dynreloc_st_type;
9967 bfd_vma dynreloc_value;
ba96a88f 9968 struct elf32_arm_link_hash_table * globals;
34e77a92 9969 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 9970 union gotplt_union *root_plt;
9971 struct arm_plt_info *arm_plt;
9972 bfd_vma plt_offset;
9973 bfd_vma gotplt_offset;
9974 bfd_boolean has_iplt_entry;
9975 bfd_boolean resolved_to_zero;
f21f3fe0 9976
9c504268 9977 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9978 if (globals == NULL)
9979 return bfd_reloc_notsupported;
9c504268 9980
0ffa91dd 9981 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 9982 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 9983
9984 /* Some relocation types map to different relocations depending on the
9c504268 9985 target. We pick the right one here. */
eb043451 9986 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9987
9988 /* It is possible to have linker relaxations on some TLS access
9989 models. Update our information here. */
9990 r_type = elf32_arm_tls_transition (info, r_type, h);
9991
eb043451
PB		 9992 if (r_type != howto->type)
9993 howto = elf32_arm_howto_from_type (r_type);
9c504268 9994
34e77a92 9995 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9996 sgot = globals->root.sgot;
252b5132 9997 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9998 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9999
34e77a92
RS		 10000 if (globals->root.dynamic_sections_created)
10001 srelgot = globals->root.srelgot;
10002 else
10003 srelgot = NULL;
10004
252b5132
RH		 10005 r_symndx = ELF32_R_SYM (rel->r_info);
10006
4e7fd91e 10007 if (globals->use_rel)
ba96a88f 10008 {
4e7fd91e
PB		 10009 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10010
10011 if (addend & ((howto->src_mask + 1) >> 1))
10012 {
10013 signed_addend = -1;
10014 signed_addend &= ~ howto->src_mask;
10015 signed_addend |= addend;
10016 }
10017 else
10018 signed_addend = addend;
ba96a88f
NC		 10019 }
10020 else
4e7fd91e 10021 addend = signed_addend = rel->r_addend;
f21f3fe0 10022
39f21624
NC		 10023 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10024 are resolving a function call relocation. */
10025 if (using_thumb_only (globals)
10026 && (r_type == R_ARM_THM_CALL
10027 || r_type == R_ARM_THM_JUMP24)
10028 && branch_type == ST_BRANCH_TO_ARM)
10029 branch_type = ST_BRANCH_TO_THUMB;
10030
34e77a92
RS		 10031 /* Record the symbol information that should be used in dynamic
10032 relocations. */
10033 dynreloc_st_type = st_type;
10034 dynreloc_value = value;
10035 if (branch_type == ST_BRANCH_TO_THUMB)
10036 dynreloc_value |= 1;
10037
10038 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10039 VALUE appropriately for relocations that we resolve at link time. */
10040 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10041 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10042 &arm_plt)
34e77a92
RS		 10043 && root_plt->offset != (bfd_vma) -1)
10044 {
10045 plt_offset = root_plt->offset;
10046 gotplt_offset = arm_plt->got_offset;
10047
10048 if (h == NULL || eh->is_iplt)
10049 {
10050 has_iplt_entry = TRUE;
10051 splt = globals->root.iplt;
10052
10053 /* Populate .iplt entries here, because not all of them will
10054 be seen by finish_dynamic_symbol. The lower bit is set if
10055 we have already populated the entry. */
10056 if (plt_offset & 1)
10057 plt_offset--;
10058 else
10059 {
57460bcf
NC		 10060 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10061 -1, dynreloc_value))
10062 root_plt->offset |= 1;
10063 else
10064 return bfd_reloc_notsupported;
34e77a92
RS		 10065 }
10066
10067 /* Static relocations always resolve to the .iplt entry. */
10068 st_type = STT_FUNC;
10069 value = (splt->output_section->vma
10070 + splt->output_offset
10071 + plt_offset);
10072 branch_type = ST_BRANCH_TO_ARM;
10073
10074 /* If there are non-call relocations that resolve to the .iplt
10075 entry, then all dynamic ones must too. */
10076 if (arm_plt->noncall_refcount != 0)
10077 {
10078 dynreloc_st_type = st_type;
10079 dynreloc_value = value;
10080 }
10081 }
10082 else
10083 /* We populate the .plt entry in finish_dynamic_symbol. */
10084 splt = globals->root.splt;
10085 }
10086 else
10087 {
10088 splt = NULL;
10089 plt_offset = (bfd_vma) -1;
10090 gotplt_offset = (bfd_vma) -1;
10091 }
10092
95b03e4a
L		 10093 resolved_to_zero = (h != NULL
10094 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10095
252b5132
RH		 10096 switch (r_type)
10097 {
10098 case R_ARM_NONE:
28a094c2
DJ		 10099 /* We don't need to find a value for this symbol. It's just a
10100 marker. */
10101 *unresolved_reloc_p = FALSE;
252b5132
RH		 10102 return bfd_reloc_ok;
10103
00a97672
RS		 10104 case R_ARM_ABS12:
10105 if (!globals->vxworks_p)
10106 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10107 /* Fall through. */
00a97672 10108
252b5132
RH		 10109 case R_ARM_PC24:
10110 case R_ARM_ABS32:
bb224fc3 10111 case R_ARM_ABS32_NOI:
252b5132 10112 case R_ARM_REL32:
bb224fc3 10113 case R_ARM_REL32_NOI:
5b5bb741
PB		 10114 case R_ARM_CALL:
10115 case R_ARM_JUMP24:
dfc5f959 10116 case R_ARM_XPC25:
eb043451 10117 case R_ARM_PREL31:
7359ea65 10118 case R_ARM_PLT32:
7359ea65
DJ		 10119 /* Handle relocations which should use the PLT entry. ABS32/REL32
10120 will use the symbol's value, which may point to a PLT entry, but we
10121 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10122 branches in this object should go to it, except if the PLT is too
10123 far away, in which case a long branch stub should be inserted. */
bb224fc3 10124 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10125 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10126 && r_type != R_ARM_CALL
10127 && r_type != R_ARM_JUMP24
10128 && r_type != R_ARM_PLT32)
34e77a92 10129 && plt_offset != (bfd_vma) -1)
7359ea65 10130 {
34e77a92
RS		 10131 /* If we've created a .plt section, and assigned a PLT entry
10132 to this function, it must either be a STT_GNU_IFUNC reference
10133 or not be known to bind locally. In other cases, we should
10134 have cleared the PLT entry by now. */
10135 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10136
10137 value = (splt->output_section->vma
10138 + splt->output_offset
34e77a92 10139 + plt_offset);
0945cdfd 10140 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10141 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10142 contents, rel->r_offset, value,
00a97672 10143 rel->r_addend);
7359ea65
DJ		 10144 }
10145
67687978
PB		 10146 /* When generating a shared object or relocatable executable, these
10147 relocations are copied into the output file to be resolved at
10148 run time. */
0e1862bb
L		 10149 if ((bfd_link_pic (info)
10150 || globals->root.is_relocatable_executable)
7359ea65 10151 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10152 && !(globals->vxworks_p
3348747a
NS		 10153 && strcmp (input_section->output_section->name,
10154 ".tls_vars") == 0)
bb224fc3 10155 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10156 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10157 && !(input_bfd == globals->stub_bfd
10158 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10159 && (h == NULL
95b03e4a
L		 10160 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10161 && !resolved_to_zero)
7359ea65
DJ		 10162 || h->root.type != bfd_link_hash_undefweak)
10163 && r_type != R_ARM_PC24
5b5bb741
PB		 10164 && r_type != R_ARM_CALL
10165 && r_type != R_ARM_JUMP24
ee06dc07 10166 && r_type != R_ARM_PREL31
7359ea65 10167 && r_type != R_ARM_PLT32)
252b5132 10168 {
947216bf 10169 Elf_Internal_Rela outrel;
b34976b6 10170 bfd_boolean skip, relocate;
f21f3fe0 10171
52db4ec2
JW		 10172 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10173 && !h->def_regular)
10174 {
10175 char *v = _("shared object");
10176
0e1862bb 10177 if (bfd_link_executable (info))
52db4ec2
JW		 10178 v = _("PIE executable");
10179
4eca0228 10180 _bfd_error_handler
871b3ab2 10181 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10182 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10183 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10184 return bfd_reloc_notsupported;
10185 }
10186
0945cdfd
DJ		 10187 *unresolved_reloc_p = FALSE;
10188
34e77a92 10189 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10190 {
83bac4b0
NC		 10191 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10192 ! globals->use_rel);
f21f3fe0 10193
83bac4b0 10194 if (sreloc == NULL)
252b5132 10195 return bfd_reloc_notsupported;
252b5132 10196 }
f21f3fe0 10197
b34976b6
AM		 10198 skip = FALSE;
10199 relocate = FALSE;
f21f3fe0 10200
00a97672 10201 outrel.r_addend = addend;
c629eae0
JJ		 10202 outrel.r_offset =
10203 _bfd_elf_section_offset (output_bfd, info, input_section,
10204 rel->r_offset);
10205 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10206 skip = TRUE;
0bb2d96a 10207 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10208 skip = TRUE, relocate = TRUE;
252b5132
RH		 10209 outrel.r_offset += (input_section->output_section->vma
10210 + input_section->output_offset);
f21f3fe0 10211
252b5132 10212 if (skip)
0bb2d96a 10213 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10214 else if (h != NULL
10215 && h->dynindx != -1
0e1862bb 10216 && (!bfd_link_pic (info)
1dcb9720
JW		 10217 || !(bfd_link_pie (info)
10218 || SYMBOLIC_BIND (info, h))
f5385ebf 10219 || !h->def_regular))
5e681ec4 10220 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10221 else
10222 {
a16385dc
MM		 10223 int symbol;
10224
5e681ec4 10225 /* This symbol is local, or marked to become local. */
34e77a92 10226 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10227 if (globals->symbian_p)
6366ff1e 10228 {
74541ad4
AM		 10229 asection *osec;
10230
6366ff1e
MM		 10231 /* On Symbian OS, the data segment and text segement
10232 can be relocated independently. Therefore, we
10233 must indicate the segment to which this
10234 relocation is relative. The BPABI allows us to
10235 use any symbol in the right segment; we just use
10236 the section symbol as it is convenient. (We
10237 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10238 will not appear in the dynamic symbol table.)
10239
10240 Note that the dynamic linker ignores the section
10241 symbol value, so we don't subtract osec->vma
10242 from the emitted reloc addend. */
10dbd1f3 10243 if (sym_sec)
74541ad4 10244 osec = sym_sec->output_section;
10dbd1f3 10245 else
74541ad4
AM		 10246 osec = input_section->output_section;
10247 symbol = elf_section_data (osec)->dynindx;
10248 if (symbol == 0)
10249 {
10250 struct elf_link_hash_table *htab = elf_hash_table (info);
10251
10252 if ((osec->flags & SEC_READONLY) == 0
10253 && htab->data_index_section != NULL)
10254 osec = htab->data_index_section;
10255 else
10256 osec = htab->text_index_section;
10257 symbol = elf_section_data (osec)->dynindx;
10258 }
6366ff1e
MM		 10259 BFD_ASSERT (symbol != 0);
10260 }
a16385dc
MM		 10261 else
10262 /* On SVR4-ish systems, the dynamic loader cannot
10263 relocate the text and data segments independently,
10264 so the symbol does not matter. */
10265 symbol = 0;
34e77a92
RS		 10266 if (dynreloc_st_type == STT_GNU_IFUNC)
10267 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10268 to the .iplt entry. Instead, every non-call reference
10269 must use an R_ARM_IRELATIVE relocation to obtain the
10270 correct run-time address. */
10271 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10272 else
10273 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10274 if (globals->use_rel)
10275 relocate = TRUE;
10276 else
34e77a92 10277 outrel.r_addend += dynreloc_value;
252b5132 10278 }
f21f3fe0 10279
47beaa6a 10280 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10281
f21f3fe0 10282 /* If this reloc is against an external symbol, we do not want to
252b5132 10283 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10284 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10285 if (! relocate)
10286 return bfd_reloc_ok;
9a5aca8c 10287
f21f3fe0 10288 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10289 contents, rel->r_offset,
10290 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10291 }
10292 else switch (r_type)
10293 {
00a97672
RS		 10294 case R_ARM_ABS12:
10295 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10296
dfc5f959 10297 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10298 case R_ARM_CALL:
10299 case R_ARM_JUMP24:
8029a119 10300 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10301 case R_ARM_PLT32:
906e58ca 10302 {
906e58ca
NC		 10303 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10304
dfc5f959 10305 if (r_type == R_ARM_XPC25)
252b5132 10306 {
dfc5f959
NC		 10307 /* Check for Arm calling Arm function. */
10308 /* FIXME: Should we translate the instruction into a BL
10309 instruction instead ? */
35fc36a8 10310 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10311 _bfd_error_handler
90b6238f
AM		 10312 (_("\%pB: warning: %s BLX instruction targets"
10313 " %s function '%s'"),
10314 input_bfd, "ARM",
10315 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10316 }
155d87d7 10317 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10318 {
10319 /* Check for Arm calling Thumb function. */
35fc36a8 10320 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10321 {
f2a9dd69
DJ		 10322 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10323 output_bfd, input_section,
10324 hit_data, sym_sec, rel->r_offset,
10325 signed_addend, value,
10326 error_message))
10327 return bfd_reloc_ok;
10328 else
10329 return bfd_reloc_dangerous;
dfc5f959 10330 }
252b5132 10331 }
ba96a88f 10332
906e58ca 10333 /* Check if a stub has to be inserted because the
8029a119 10334 destination is too far or we are changing mode. */
155d87d7
CL		 10335 if ( r_type == R_ARM_CALL
10336 || r_type == R_ARM_JUMP24
10337 || r_type == R_ARM_PLT32)
906e58ca 10338 {
fe33d2fa
CL		 10339 enum elf32_arm_stub_type stub_type = arm_stub_none;
10340 struct elf32_arm_link_hash_entry *hash;
10341
10342 hash = (struct elf32_arm_link_hash_entry *) h;
10343 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10344 st_type, &branch_type,
10345 hash, value, sym_sec,
fe33d2fa 10346 input_bfd, sym_name);
5fa9e92f 10347
fe33d2fa 10348 if (stub_type != arm_stub_none)
906e58ca
NC		 10349 {
10350 /* The target is out of reach, so redirect the
10351 branch to the local stub for this function. */
906e58ca
NC		 10352 stub_entry = elf32_arm_get_stub_entry (input_section,
10353 sym_sec, h,
fe33d2fa
CL		 10354 rel, globals,
10355 stub_type);
9cd3e4e5
NC		 10356 {
10357 if (stub_entry != NULL)
10358 value = (stub_entry->stub_offset
10359 + stub_entry->stub_sec->output_offset
10360 + stub_entry->stub_sec->output_section->vma);
10361
10362 if (plt_offset != (bfd_vma) -1)
10363 *unresolved_reloc_p = FALSE;
10364 }
906e58ca 10365 }
fe33d2fa
CL		 10366 else
10367 {
10368 /* If the call goes through a PLT entry, make sure to
10369 check distance to the right destination address. */
34e77a92 10370 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10371 {
10372 value = (splt->output_section->vma
10373 + splt->output_offset
34e77a92 10374 + plt_offset);
fe33d2fa
CL		 10375 *unresolved_reloc_p = FALSE;
10376 /* The PLT entry is in ARM mode, regardless of the
10377 target function. */
35fc36a8 10378 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10379 }
10380 }
906e58ca
NC		 10381 }
10382
dea514f5
PB		 10383 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10384 where:
10385 S is the address of the symbol in the relocation.
10386 P is address of the instruction being relocated.
10387 A is the addend (extracted from the instruction) in bytes.
10388
10389 S is held in 'value'.
10390 P is the base address of the section containing the
10391 instruction plus the offset of the reloc into that
10392 section, ie:
10393 (input_section->output_section->vma +
10394 input_section->output_offset +
10395 rel->r_offset).
10396 A is the addend, converted into bytes, ie:
10397 (signed_addend * 4)
10398
10399 Note: None of these operations have knowledge of the pipeline
10400 size of the processor, thus it is up to the assembler to
10401 encode this information into the addend. */
10402 value -= (input_section->output_section->vma
10403 + input_section->output_offset);
10404 value -= rel->r_offset;
4e7fd91e
PB		 10405 if (globals->use_rel)
10406 value += (signed_addend << howto->size);
10407 else
10408 /* RELA addends do not have to be adjusted by howto->size. */
10409 value += signed_addend;
23080146 10410
dcb5e6e6
NC		 10411 signed_addend = value;
10412 signed_addend >>= howto->rightshift;
9a5aca8c 10413
5ab79981 10414 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10415 the next instruction unless a PLT entry will be created.
77b4f08f 10416 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10417 The jump to the next instruction is optimized as a NOP depending
10418 on the architecture. */
ffcb4889 10419 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10420 && plt_offset == (bfd_vma) -1)
77b4f08f 10421 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10422 {
cd1dac3d
DG		 10423 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10424
10425 if (arch_has_arm_nop (globals))
10426 value |= 0x0320f000;
10427 else
10428 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10429 }
10430 else
59f2c4e7 10431 {
9b485d32 10432 /* Perform a signed range check. */
dcb5e6e6 10433 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10434 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10435 return bfd_reloc_overflow;
9a5aca8c 10436
5ab79981 10437 addend = (value & 2);
39b41c9c 10438
5ab79981
PB		 10439 value = (signed_addend & howto->dst_mask)
10440 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10441
5ab79981
PB		 10442 if (r_type == R_ARM_CALL)
10443 {
155d87d7 10444 /* Set the H bit in the BLX instruction. */
35fc36a8 10445 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10446 {
10447 if (addend)
10448 value |= (1 << 24);
10449 else
10450 value &= ~(bfd_vma)(1 << 24);
10451 }
10452
5ab79981 10453 /* Select the correct instruction (BL or BLX). */
906e58ca 10454 /* Only if we are not handling a BL to a stub. In this
8029a119 10455 case, mode switching is performed by the stub. */
35fc36a8 10456 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10457 value |= (1 << 28);
63e1a0fc 10458 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10459 {
10460 value &= ~(bfd_vma)(1 << 28);
10461 value |= (1 << 24);
10462 }
39b41c9c
PB		 10463 }
10464 }
906e58ca 10465 }
252b5132 10466 break;
f21f3fe0 10467
252b5132
RH		 10468 case R_ARM_ABS32:
10469 value += addend;
35fc36a8 10470 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10471 value |= 1;
10472 break;
f21f3fe0 10473
bb224fc3
MS		 10474 case R_ARM_ABS32_NOI:
10475 value += addend;
10476 break;
10477
252b5132 10478 case R_ARM_REL32:
a8bc6c78 10479 value += addend;
35fc36a8 10480 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10481 value |= 1;
252b5132 10482 value -= (input_section->output_section->vma
62efb346 10483 + input_section->output_offset + rel->r_offset);
252b5132 10484 break;
eb043451 10485
bb224fc3
MS		 10486 case R_ARM_REL32_NOI:
10487 value += addend;
10488 value -= (input_section->output_section->vma
10489 + input_section->output_offset + rel->r_offset);
10490 break;
10491
eb043451
PB		 10492 case R_ARM_PREL31:
10493 value -= (input_section->output_section->vma
10494 + input_section->output_offset + rel->r_offset);
10495 value += signed_addend;
10496 if (! h || h->root.type != bfd_link_hash_undefweak)
10497 {
8029a119 10498 /* Check for overflow. */
eb043451
PB		 10499 if ((value ^ (value >> 1)) & (1 << 30))
10500 return bfd_reloc_overflow;
10501 }
10502 value &= 0x7fffffff;
10503 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10504 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10505 value |= 1;
10506 break;
252b5132 10507 }
f21f3fe0 10508
252b5132
RH		 10509 bfd_put_32 (input_bfd, value, hit_data);
10510 return bfd_reloc_ok;
10511
10512 case R_ARM_ABS8:
fd0fd00c
MJ		 10513 /* PR 16202: Refectch the addend using the correct size. */
10514 if (globals->use_rel)
10515 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10516 value += addend;
4e67d4ca
DG		 10517
10518 /* There is no way to tell whether the user intended to use a signed or
10519 unsigned addend. When checking for overflow we accept either,
10520 as specified by the AAELF. */
10521 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10522 return bfd_reloc_overflow;
10523
10524 bfd_put_8 (input_bfd, value, hit_data);
10525 return bfd_reloc_ok;
10526
10527 case R_ARM_ABS16:
fd0fd00c
MJ		 10528 /* PR 16202: Refectch the addend using the correct size. */
10529 if (globals->use_rel)
10530 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10531 value += addend;
10532
4e67d4ca
DG		 10533 /* See comment for R_ARM_ABS8. */
10534 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10535 return bfd_reloc_overflow;
10536
10537 bfd_put_16 (input_bfd, value, hit_data);
10538 return bfd_reloc_ok;
10539
252b5132 10540 case R_ARM_THM_ABS5:
9b485d32 10541 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10542 if (globals->use_rel)
10543 {
10544 /* Need to refetch addend. */
10545 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10546 /* ??? Need to determine shift amount from operand size. */
10547 addend >>= howto->rightshift;
10548 }
252b5132
RH		 10549 value += addend;
10550
10551 /* ??? Isn't value unsigned? */
10552 if ((long) value > 0x1f || (long) value < -0x10)
10553 return bfd_reloc_overflow;
10554
10555 /* ??? Value needs to be properly shifted into place first. */
10556 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10557 bfd_put_16 (input_bfd, value, hit_data);
10558 return bfd_reloc_ok;
10559
2cab6cc3
MS		 10560 case R_ARM_THM_ALU_PREL_11_0:
10561 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10562 {
10563 bfd_vma insn;
10564 bfd_signed_vma relocation;
10565
10566 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10567 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10568
99059e56
RM		 10569 if (globals->use_rel)
10570 {
10571 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10572 | ((insn & (1 << 26)) >> 15);
10573 if (insn & 0xf00000)
10574 signed_addend = -signed_addend;
10575 }
2cab6cc3
MS		 10576
10577 relocation = value + signed_addend;
79f08007 10578 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10579 + input_section->output_offset
10580 + rel->r_offset);
2cab6cc3 10581
8c65b54f
CS		 10582 /* PR 21523: Use an absolute value. The user of this reloc will
10583 have already selected an ADD or SUB insn appropriately. */
e652757b 10584 value = labs (relocation);
2cab6cc3 10585
99059e56
RM		 10586 if (value >= 0x1000)
10587 return bfd_reloc_overflow;
2cab6cc3 10588
e645cf40
AG		 10589 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10590 if (branch_type == ST_BRANCH_TO_THUMB)
10591 value |= 1;
10592
2cab6cc3 10593 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10594 | ((value & 0x700) << 4)
10595 | ((value & 0x800) << 15);
10596 if (relocation < 0)
10597 insn |= 0xa00000;
2cab6cc3
MS		 10598
10599 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10600 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10601
99059e56 10602 return bfd_reloc_ok;
2cab6cc3
MS		 10603 }
10604
e1ec24c6
NC		 10605 case R_ARM_THM_PC8:
10606 /* PR 10073: This reloc is not generated by the GNU toolchain,
10607 but it is supported for compatibility with third party libraries
10608 generated by other compilers, specifically the ARM/IAR. */
10609 {
10610 bfd_vma insn;
10611 bfd_signed_vma relocation;
10612
10613 insn = bfd_get_16 (input_bfd, hit_data);
10614
99059e56 10615 if (globals->use_rel)
79f08007 10616 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10617
10618 relocation = value + addend;
79f08007 10619 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10620 + input_section->output_offset
10621 + rel->r_offset);
e1ec24c6 10622
b6518b38 10623 value = relocation;
e1ec24c6
NC		 10624
10625 /* We do not check for overflow of this reloc. Although strictly
10626 speaking this is incorrect, it appears to be necessary in order
10627 to work with IAR generated relocs. Since GCC and GAS do not
10628 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10629 a problem for them. */
10630 value &= 0x3fc;
10631
10632 insn = (insn & 0xff00) | (value >> 2);
10633
10634 bfd_put_16 (input_bfd, insn, hit_data);
10635
99059e56 10636 return bfd_reloc_ok;
e1ec24c6
NC		 10637 }
10638
2cab6cc3
MS		 10639 case R_ARM_THM_PC12:
10640 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10641 {
10642 bfd_vma insn;
10643 bfd_signed_vma relocation;
10644
10645 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10646 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10647
99059e56
RM		 10648 if (globals->use_rel)
10649 {
10650 signed_addend = insn & 0xfff;
10651 if (!(insn & (1 << 23)))
10652 signed_addend = -signed_addend;
10653 }
2cab6cc3
MS		 10654
10655 relocation = value + signed_addend;
79f08007 10656 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10657 + input_section->output_offset
10658 + rel->r_offset);
2cab6cc3 10659
b6518b38 10660 value = relocation;
2cab6cc3 10661
99059e56
RM		 10662 if (value >= 0x1000)
10663 return bfd_reloc_overflow;
2cab6cc3
MS		 10664
10665 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10666 if (relocation >= 0)
10667 insn |= (1 << 23);
2cab6cc3
MS		 10668
10669 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10670 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10671
99059e56 10672 return bfd_reloc_ok;
2cab6cc3
MS		 10673 }
10674
dfc5f959 10675 case R_ARM_THM_XPC22:
c19d1205 10676 case R_ARM_THM_CALL:
bd97cb95 10677 case R_ARM_THM_JUMP24:
dfc5f959 10678 /* Thumb BL (branch long instruction). */
252b5132 10679 {
b34976b6 10680 bfd_vma relocation;
99059e56 10681 bfd_vma reloc_sign;
b34976b6
AM		 10682 bfd_boolean overflow = FALSE;
10683 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10684 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10685 bfd_signed_vma reloc_signed_max;
10686 bfd_signed_vma reloc_signed_min;
b34976b6 10687 bfd_vma check;
252b5132 10688 bfd_signed_vma signed_check;
e95de063 10689 int bitsize;
cd1dac3d 10690 const int thumb2 = using_thumb2 (globals);
5e866f5a 10691 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10692
5ab79981 10693 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10694 the next instruction unless a PLT entry will be created.
10695 The jump to the next instruction is optimized as a NOP.W for
10696 Thumb-2 enabled architectures. */
19540007 10697 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10698 && plt_offset == (bfd_vma) -1)
5ab79981 10699 {
60a019a0 10700 if (thumb2)
cd1dac3d
DG		 10701 {
10702 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10703 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10704 }
10705 else
10706 {
10707 bfd_put_16 (input_bfd, 0xe000, hit_data);
10708 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10709 }
5ab79981
PB		 10710 return bfd_reloc_ok;
10711 }
10712
e95de063 10713 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10714 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10715 if (globals->use_rel)
10716 {
99059e56
RM		 10717 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10718 bfd_vma upper = upper_insn & 0x3ff;
10719 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10720 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10721 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10722 bfd_vma i1 = j1 ^ s ? 0 : 1;
10723 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10724
99059e56
RM		 10725 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10726 /* Sign extend. */
10727 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10728
4e7fd91e
PB		 10729 signed_addend = addend;
10730 }
cb1afa5c 10731
dfc5f959
NC		 10732 if (r_type == R_ARM_THM_XPC22)
10733 {
10734 /* Check for Thumb to Thumb call. */
10735 /* FIXME: Should we translate the instruction into a BL
10736 instruction instead ? */
35fc36a8 10737 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10738 _bfd_error_handler
90b6238f
AM		 10739 (_("%pB: warning: %s BLX instruction targets"
10740 " %s function '%s'"),
10741 input_bfd, "Thumb",
10742 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 10743 }
10744 else
252b5132 10745 {
dfc5f959
NC		 10746 /* If it is not a call to Thumb, assume call to Arm.
10747 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10748 function call at all, but rather a long jump. Calls through
10749 the PLT do not require stubs. */
34e77a92 10750 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10751 {
bd97cb95 10752 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10753 {
10754 /* Convert BL to BLX. */
10755 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10756 }
155d87d7
CL		 10757 else if (( r_type != R_ARM_THM_CALL)
10758 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10759 {
10760 if (elf32_thumb_to_arm_stub
10761 (info, sym_name, input_bfd, output_bfd, input_section,
10762 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10763 error_message))
10764 return bfd_reloc_ok;
10765 else
10766 return bfd_reloc_dangerous;
10767 }
da5938a2 10768 }
35fc36a8
RS		 10769 else if (branch_type == ST_BRANCH_TO_THUMB
10770 && globals->use_blx
bd97cb95 10771 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10772 {
10773 /* Make sure this is a BL. */
10774 lower_insn |= 0x1800;
10775 }
252b5132 10776 }
f21f3fe0 10777
fe33d2fa 10778 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10779 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10780 {
10781 /* Check if a stub has to be inserted because the destination
8029a119 10782 is too far. */
fe33d2fa
CL		 10783 struct elf32_arm_stub_hash_entry *stub_entry;
10784 struct elf32_arm_link_hash_entry *hash;
10785
10786 hash = (struct elf32_arm_link_hash_entry *) h;
10787
10788 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10789 st_type, &branch_type,
10790 hash, value, sym_sec,
fe33d2fa
CL		 10791 input_bfd, sym_name);
10792
10793 if (stub_type != arm_stub_none)
906e58ca
NC		 10794 {
10795 /* The target is out of reach or we are changing modes, so
10796 redirect the branch to the local stub for this
10797 function. */
10798 stub_entry = elf32_arm_get_stub_entry (input_section,
10799 sym_sec, h,
fe33d2fa
CL		 10800 rel, globals,
10801 stub_type);
906e58ca 10802 if (stub_entry != NULL)
9cd3e4e5
NC		 10803 {
10804 value = (stub_entry->stub_offset
10805 + stub_entry->stub_sec->output_offset
10806 + stub_entry->stub_sec->output_section->vma);
10807
10808 if (plt_offset != (bfd_vma) -1)
10809 *unresolved_reloc_p = FALSE;
10810 }
906e58ca 10811
f4ac8484 10812 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10813 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10814 {
10815 if ((stub_entry
10816 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10817 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10818 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10819 }
906e58ca
NC		 10820 }
10821 }
10822
fe33d2fa 10823 /* Handle calls via the PLT. */
34e77a92 10824 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10825 {
10826 value = (splt->output_section->vma
10827 + splt->output_offset
34e77a92 10828 + plt_offset);
fe33d2fa 10829
eed94f8f
NC		 10830 if (globals->use_blx
10831 && r_type == R_ARM_THM_CALL
10832 && ! using_thumb_only (globals))
fe33d2fa
CL		 10833 {
10834 /* If the Thumb BLX instruction is available, convert
10835 the BL to a BLX instruction to call the ARM-mode
10836 PLT entry. */
10837 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10838 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10839 }
10840 else
10841 {
eed94f8f
NC		 10842 if (! using_thumb_only (globals))
10843 /* Target the Thumb stub before the ARM PLT entry. */
10844 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10845 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10846 }
10847 *unresolved_reloc_p = FALSE;
10848 }
10849
ba96a88f 10850 relocation = value + signed_addend;
f21f3fe0 10851
252b5132 10852 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10853 + input_section->output_offset
10854 + rel->r_offset);
9a5aca8c 10855
252b5132
RH		 10856 check = relocation >> howto->rightshift;
10857
10858 /* If this is a signed value, the rightshift just dropped
10859 leading 1 bits (assuming twos complement). */
10860 if ((bfd_signed_vma) relocation >= 0)
10861 signed_check = check;
10862 else
10863 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10864
e95de063
MS		 10865 /* Calculate the permissable maximum and minimum values for
10866 this relocation according to whether we're relocating for
10867 Thumb-2 or not. */
10868 bitsize = howto->bitsize;
5e866f5a 10869 if (!thumb2_bl)
e95de063 10870 bitsize -= 2;
f6ebfac0 10871 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10872 reloc_signed_min = ~reloc_signed_max;
10873
252b5132 10874 /* Assumes two's complement. */
ba96a88f 10875 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10876 overflow = TRUE;
252b5132 10877
bd97cb95 10878 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10879 /* For a BLX instruction, make sure that the relocation is rounded up
10880 to a word boundary. This follows the semantics of the instruction
10881 which specifies that bit 1 of the target address will come from bit
10882 1 of the base address. */
10883 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10884
e95de063
MS		 10885 /* Put RELOCATION back into the insn. Assumes two's complement.
10886 We use the Thumb-2 encoding, which is safe even if dealing with
10887 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10888 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10889 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10890 | ((relocation >> 12) & 0x3ff)
10891 | (reloc_sign << 10);
906e58ca 10892 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10893 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10894 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10895 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10896
252b5132
RH		 10897 /* Put the relocated value back in the object file: */
10898 bfd_put_16 (input_bfd, upper_insn, hit_data);
10899 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10900
10901 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10902 }
10903 break;
10904
c19d1205
ZW		 10905 case R_ARM_THM_JUMP19:
10906 /* Thumb32 conditional branch instruction. */
10907 {
10908 bfd_vma relocation;
10909 bfd_boolean overflow = FALSE;
10910 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10911 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10912 bfd_signed_vma reloc_signed_max = 0xffffe;
10913 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10914 bfd_signed_vma signed_check;
07d6d2b8 10915 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 10916 struct elf32_arm_stub_hash_entry *stub_entry;
10917 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10918
10919 /* Need to refetch the addend, reconstruct the top three bits,
10920 and squish the two 11 bit pieces together. */
10921 if (globals->use_rel)
10922 {
10923 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10924 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10925 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10926 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10927 bfd_vma lower = (lower_insn & 0x07ff);
10928
a00a1f35
MS		 10929 upper |= J1 << 6;
10930 upper |= J2 << 7;
10931 upper |= (!S) << 8;
c19d1205
ZW		 10932 upper -= 0x0100; /* Sign extend. */
10933
10934 addend = (upper << 12) | (lower << 1);
10935 signed_addend = addend;
10936 }
10937
bd97cb95 10938 /* Handle calls via the PLT. */
34e77a92 10939 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10940 {
10941 value = (splt->output_section->vma
10942 + splt->output_offset
34e77a92 10943 + plt_offset);
bd97cb95
DJ		 10944 /* Target the Thumb stub before the ARM PLT entry. */
10945 value -= PLT_THUMB_STUB_SIZE;
10946 *unresolved_reloc_p = FALSE;
10947 }
10948
c5423981
TG		 10949 hash = (struct elf32_arm_link_hash_entry *)h;
10950
10951 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 10952 st_type, &branch_type,
10953 hash, value, sym_sec,
10954 input_bfd, sym_name);
c5423981
TG		 10955 if (stub_type != arm_stub_none)
10956 {
10957 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 10958 sym_sec, h,
10959 rel, globals,
10960 stub_type);
c5423981
TG		 10961 if (stub_entry != NULL)
10962 {
07d6d2b8
AM		 10963 value = (stub_entry->stub_offset
10964 + stub_entry->stub_sec->output_offset
10965 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 10966 }
10967 }
c19d1205 10968
99059e56 10969 relocation = value + signed_addend;
c19d1205
ZW		 10970 relocation -= (input_section->output_section->vma
10971 + input_section->output_offset
10972 + rel->r_offset);
a00a1f35 10973 signed_check = (bfd_signed_vma) relocation;
c19d1205 10974
c19d1205
ZW		 10975 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10976 overflow = TRUE;
10977
10978 /* Put RELOCATION back into the insn. */
10979 {
10980 bfd_vma S = (relocation & 0x00100000) >> 20;
10981 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10982 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10983 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10984 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10985
a00a1f35 10986 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10987 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10988 }
10989
10990 /* Put the relocated value back in the object file: */
10991 bfd_put_16 (input_bfd, upper_insn, hit_data);
10992 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10993
10994 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10995 }
10996
10997 case R_ARM_THM_JUMP11:
10998 case R_ARM_THM_JUMP8:
10999 case R_ARM_THM_JUMP6:
51c5503b
NC		 11000 /* Thumb B (branch) instruction). */
11001 {
6cf9e9fe 11002 bfd_signed_vma relocation;
51c5503b
NC		 11003 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11004 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11005 bfd_signed_vma signed_check;
11006
c19d1205
ZW		 11007 /* CZB cannot jump backward. */
11008 if (r_type == R_ARM_THM_JUMP6)
11009 reloc_signed_min = 0;
11010
4e7fd91e 11011 if (globals->use_rel)
6cf9e9fe 11012 {
4e7fd91e
PB		 11013 /* Need to refetch addend. */
11014 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11015 if (addend & ((howto->src_mask + 1) >> 1))
11016 {
11017 signed_addend = -1;
11018 signed_addend &= ~ howto->src_mask;
11019 signed_addend |= addend;
11020 }
11021 else
11022 signed_addend = addend;
11023 /* The value in the insn has been right shifted. We need to
11024 undo this, so that we can perform the address calculation
11025 in terms of bytes. */
11026 signed_addend <<= howto->rightshift;
6cf9e9fe 11027 }
6cf9e9fe 11028 relocation = value + signed_addend;
51c5503b
NC		 11029
11030 relocation -= (input_section->output_section->vma
11031 + input_section->output_offset
11032 + rel->r_offset);
11033
6cf9e9fe
NC		 11034 relocation >>= howto->rightshift;
11035 signed_check = relocation;
c19d1205
ZW		 11036
11037 if (r_type == R_ARM_THM_JUMP6)
11038 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11039 else
11040 relocation &= howto->dst_mask;
51c5503b 11041 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11042
51c5503b
NC		 11043 bfd_put_16 (input_bfd, relocation, hit_data);
11044
11045 /* Assumes two's complement. */
11046 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11047 return bfd_reloc_overflow;
11048
11049 return bfd_reloc_ok;
11050 }
cedb70c5 11051
8375c36b
PB		 11052 case R_ARM_ALU_PCREL7_0:
11053 case R_ARM_ALU_PCREL15_8:
11054 case R_ARM_ALU_PCREL23_15:
11055 {
11056 bfd_vma insn;
11057 bfd_vma relocation;
11058
11059 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11060 if (globals->use_rel)
11061 {
11062 /* Extract the addend. */
11063 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11064 signed_addend = addend;
11065 }
8375c36b
PB		 11066 relocation = value + signed_addend;
11067
11068 relocation -= (input_section->output_section->vma
11069 + input_section->output_offset
11070 + rel->r_offset);
11071 insn = (insn & ~0xfff)
11072 | ((howto->bitpos << 7) & 0xf00)
11073 | ((relocation >> howto->bitpos) & 0xff);
11074 bfd_put_32 (input_bfd, value, hit_data);
11075 }
11076 return bfd_reloc_ok;
11077
252b5132
RH		 11078 case R_ARM_GNU_VTINHERIT:
11079 case R_ARM_GNU_VTENTRY:
11080 return bfd_reloc_ok;
11081
c19d1205 11082 case R_ARM_GOTOFF32:
252b5132 11083 /* Relocation is relative to the start of the
99059e56 11084 global offset table. */
252b5132
RH		 11085
11086 BFD_ASSERT (sgot != NULL);
11087 if (sgot == NULL)
99059e56 11088 return bfd_reloc_notsupported;
9a5aca8c 11089
cedb70c5 11090 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11091 address by one, so that attempts to call the function pointer will
11092 correctly interpret it as Thumb code. */
35fc36a8 11093 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11094 value += 1;
11095
252b5132 11096 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11097 calculation. We always want the start of .got. If we
11098 define _GLOBAL_OFFSET_TABLE in a different way, as is
11099 permitted by the ABI, we might have to change this
11100 calculation. */
252b5132 11101 value -= sgot->output_section->vma;
f21f3fe0 11102 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11103 contents, rel->r_offset, value,
00a97672 11104 rel->r_addend);
252b5132
RH		 11105
11106 case R_ARM_GOTPC:
a7c10850 11107 /* Use global offset table as symbol value. */
252b5132 11108 BFD_ASSERT (sgot != NULL);
f21f3fe0 11109
252b5132 11110 if (sgot == NULL)
99059e56 11111 return bfd_reloc_notsupported;
252b5132 11112
0945cdfd 11113 *unresolved_reloc_p = FALSE;
252b5132 11114 value = sgot->output_section->vma;
f21f3fe0 11115 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11116 contents, rel->r_offset, value,
00a97672 11117 rel->r_addend);
f21f3fe0 11118
252b5132 11119 case R_ARM_GOT32:
eb043451 11120 case R_ARM_GOT_PREL:
252b5132 11121 /* Relocation is to the entry for this symbol in the
99059e56 11122 global offset table. */
252b5132
RH		 11123 if (sgot == NULL)
11124 return bfd_reloc_notsupported;
f21f3fe0 11125
34e77a92
RS		 11126 if (dynreloc_st_type == STT_GNU_IFUNC
11127 && plt_offset != (bfd_vma) -1
11128 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11129 {
11130 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11131 symbol, and the relocation resolves directly to the runtime
11132 target rather than to the .iplt entry. This means that any
11133 .got entry would be the same value as the .igot.plt entry,
11134 so there's no point creating both. */
11135 sgot = globals->root.igotplt;
11136 value = sgot->output_offset + gotplt_offset;
11137 }
11138 else if (h != NULL)
252b5132
RH		 11139 {
11140 bfd_vma off;
f21f3fe0 11141
252b5132
RH		 11142 off = h->got.offset;
11143 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11144 if ((off & 1) != 0)
252b5132 11145 {
b436d854
RS		 11146 /* We have already processsed one GOT relocation against
11147 this symbol. */
11148 off &= ~1;
11149 if (globals->root.dynamic_sections_created
11150 && !SYMBOL_REFERENCES_LOCAL (info, h))
11151 *unresolved_reloc_p = FALSE;
11152 }
11153 else
11154 {
11155 Elf_Internal_Rela outrel;
11156
6f820c85 11157 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11158 {
11159 /* If the symbol doesn't resolve locally in a static
11160 object, we have an undefined reference. If the
11161 symbol doesn't resolve locally in a dynamic object,
11162 it should be resolved by the dynamic linker. */
11163 if (globals->root.dynamic_sections_created)
11164 {
11165 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11166 *unresolved_reloc_p = FALSE;
11167 }
11168 else
11169 outrel.r_info = 0;
11170 outrel.r_addend = 0;
11171 }
252b5132
RH		 11172 else
11173 {
34e77a92 11174 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11175 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11176 else if (bfd_link_pic (info)
11177 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11178 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11179 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11180 else
11181 outrel.r_info = 0;
34e77a92 11182 outrel.r_addend = dynreloc_value;
b436d854 11183 }
ee29b9fb 11184
b436d854
RS		 11185 /* The GOT entry is initialized to zero by default.
11186 See if we should install a different value. */
11187 if (outrel.r_addend != 0
11188 && (outrel.r_info == 0 || globals->use_rel))
11189 {
11190 bfd_put_32 (output_bfd, outrel.r_addend,
11191 sgot->contents + off);
11192 outrel.r_addend = 0;
252b5132 11193 }
f21f3fe0 11194
b436d854
RS		 11195 if (outrel.r_info != 0)
11196 {
11197 outrel.r_offset = (sgot->output_section->vma
11198 + sgot->output_offset
11199 + off);
11200 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11201 }
11202 h->got.offset |= 1;
11203 }
252b5132
RH		 11204 value = sgot->output_offset + off;
11205 }
11206 else
11207 {
11208 bfd_vma off;
f21f3fe0 11209
5025eb7c
AO		 11210 BFD_ASSERT (local_got_offsets != NULL
11211 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11212
252b5132 11213 off = local_got_offsets[r_symndx];
f21f3fe0 11214
252b5132
RH		 11215 /* The offset must always be a multiple of 4. We use the
11216 least significant bit to record whether we have already
9b485d32 11217 generated the necessary reloc. */
252b5132
RH		 11218 if ((off & 1) != 0)
11219 off &= ~1;
11220 else
11221 {
00a97672 11222 if (globals->use_rel)
34e77a92 11223 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11224
0e1862bb 11225 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11226 {
947216bf 11227 Elf_Internal_Rela outrel;
f21f3fe0 11228
34e77a92 11229 outrel.r_addend = addend + dynreloc_value;
252b5132 11230 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11231 + sgot->output_offset
252b5132 11232 + off);
34e77a92 11233 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11234 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11235 else
11236 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11237 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11238 }
f21f3fe0 11239
252b5132
RH		 11240 local_got_offsets[r_symndx] |= 1;
11241 }
f21f3fe0 11242
252b5132
RH		 11243 value = sgot->output_offset + off;
11244 }
eb043451
PB		 11245 if (r_type != R_ARM_GOT32)
11246 value += sgot->output_section->vma;
9a5aca8c 11247
f21f3fe0 11248 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11249 contents, rel->r_offset, value,
00a97672 11250 rel->r_addend);
f21f3fe0 11251
ba93b8ac
DJ		 11252 case R_ARM_TLS_LDO32:
11253 value = value - dtpoff_base (info);
11254
11255 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11256 contents, rel->r_offset, value,
11257 rel->r_addend);
ba93b8ac
DJ		 11258
11259 case R_ARM_TLS_LDM32:
11260 {
11261 bfd_vma off;
11262
362d30a1 11263 if (sgot == NULL)
ba93b8ac
DJ		 11264 abort ();
11265
11266 off = globals->tls_ldm_got.offset;
11267
11268 if ((off & 1) != 0)
11269 off &= ~1;
11270 else
11271 {
11272 /* If we don't know the module number, create a relocation
11273 for it. */
0e1862bb 11274 if (bfd_link_pic (info))
ba93b8ac
DJ		 11275 {
11276 Elf_Internal_Rela outrel;
ba93b8ac 11277
362d30a1 11278 if (srelgot == NULL)
ba93b8ac
DJ		 11279 abort ();
11280
00a97672 11281 outrel.r_addend = 0;
362d30a1
RS		 11282 outrel.r_offset = (sgot->output_section->vma
11283 + sgot->output_offset + off);
ba93b8ac
DJ		 11284 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11285
00a97672
RS		 11286 if (globals->use_rel)
11287 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11288 sgot->contents + off);
ba93b8ac 11289
47beaa6a 11290 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11291 }
11292 else
362d30a1 11293 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11294
11295 globals->tls_ldm_got.offset |= 1;
11296 }
11297
362d30a1 11298 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11299 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11300
11301 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11302 contents, rel->r_offset, value,
00a97672 11303 rel->r_addend);
ba93b8ac
DJ		 11304 }
11305
0855e32b
NS		 11306 case R_ARM_TLS_CALL:
11307 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11308 case R_ARM_TLS_GD32:
11309 case R_ARM_TLS_IE32:
0855e32b
NS		 11310 case R_ARM_TLS_GOTDESC:
11311 case R_ARM_TLS_DESCSEQ:
11312 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11313 {
0855e32b
NS		 11314 bfd_vma off, offplt;
11315 int indx = 0;
ba93b8ac
DJ		 11316 char tls_type;
11317
0855e32b 11318 BFD_ASSERT (sgot != NULL);
ba93b8ac 11319
ba93b8ac
DJ		 11320 if (h != NULL)
11321 {
11322 bfd_boolean dyn;
11323 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11324 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11325 bfd_link_pic (info),
11326 h)
11327 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11328 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11329 {
11330 *unresolved_reloc_p = FALSE;
11331 indx = h->dynindx;
11332 }
11333 off = h->got.offset;
0855e32b 11334 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11335 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11336 }
11337 else
11338 {
0855e32b 11339 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11340 off = local_got_offsets[r_symndx];
0855e32b 11341 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11342 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11343 }
11344
0855e32b 11345 /* Linker relaxations happens from one of the
b38cadfb 11346 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11347 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11348 tls_type = GOT_TLS_IE;
0855e32b
NS		 11349
11350 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11351
11352 if ((off & 1) != 0)
11353 off &= ~1;
11354 else
11355 {
11356 bfd_boolean need_relocs = FALSE;
11357 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11358 int cur_off = off;
11359
11360 /* The GOT entries have not been initialized yet. Do it
11361 now, and emit any relocations. If both an IE GOT and a
11362 GD GOT are necessary, we emit the GD first. */
11363
0e1862bb 11364 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11365 && (h == NULL
95b03e4a
L		 11366 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11367 && !resolved_to_zero)
ba93b8ac
DJ		 11368 || h->root.type != bfd_link_hash_undefweak))
11369 {
11370 need_relocs = TRUE;
0855e32b 11371 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11372 }
11373
0855e32b
NS		 11374 if (tls_type & GOT_TLS_GDESC)
11375 {
47beaa6a
RS		 11376 bfd_byte *loc;
11377
0855e32b
NS		 11378 /* We should have relaxed, unless this is an undefined
11379 weak symbol. */
11380 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11381 || bfd_link_pic (info));
0855e32b 11382 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11383 <= globals->root.sgotplt->size);
0855e32b
NS		 11384
11385 outrel.r_addend = 0;
11386 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11387 + globals->root.sgotplt->output_offset
11388 + offplt
11389 + globals->sgotplt_jump_table_size);
b38cadfb 11390
0855e32b
NS		 11391 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11392 sreloc = globals->root.srelplt;
11393 loc = sreloc->contents;
11394 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11395 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11396 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11397
11398 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11399
11400 /* For globals, the first word in the relocation gets
11401 the relocation index and the top bit set, or zero,
11402 if we're binding now. For locals, it gets the
11403 symbol's offset in the tls section. */
99059e56 11404 bfd_put_32 (output_bfd,
0855e32b
NS		 11405 !h ? value - elf_hash_table (info)->tls_sec->vma
11406 : info->flags & DF_BIND_NOW ? 0
11407 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11408 globals->root.sgotplt->contents + offplt
11409 + globals->sgotplt_jump_table_size);
11410
0855e32b 11411 /* Second word in the relocation is always zero. */
99059e56 11412 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11413 globals->root.sgotplt->contents + offplt
11414 + globals->sgotplt_jump_table_size + 4);
0855e32b 11415 }
ba93b8ac
DJ		 11416 if (tls_type & GOT_TLS_GD)
11417 {
11418 if (need_relocs)
11419 {
00a97672 11420 outrel.r_addend = 0;
362d30a1
RS		 11421 outrel.r_offset = (sgot->output_section->vma
11422 + sgot->output_offset
00a97672 11423 + cur_off);
ba93b8ac 11424 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11425
00a97672
RS		 11426 if (globals->use_rel)
11427 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11428 sgot->contents + cur_off);
00a97672 11429
47beaa6a 11430 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11431
11432 if (indx == 0)
11433 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11434 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11435 else
11436 {
00a97672 11437 outrel.r_addend = 0;
ba93b8ac
DJ		 11438 outrel.r_info = ELF32_R_INFO (indx,
11439 R_ARM_TLS_DTPOFF32);
11440 outrel.r_offset += 4;
00a97672
RS		 11441
11442 if (globals->use_rel)
11443 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11444 sgot->contents + cur_off + 4);
00a97672 11445
47beaa6a
RS		 11446 elf32_arm_add_dynreloc (output_bfd, info,
11447 srelgot, &outrel);
ba93b8ac
DJ		 11448 }
11449 }
11450 else
11451 {
11452 /* If we are not emitting relocations for a
11453 general dynamic reference, then we must be in a
11454 static link or an executable link with the
11455 symbol binding locally. Mark it as belonging
11456 to module 1, the executable. */
11457 bfd_put_32 (output_bfd, 1,
362d30a1 11458 sgot->contents + cur_off);
ba93b8ac 11459 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11460 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11461 }
11462
11463 cur_off += 8;
11464 }
11465
11466 if (tls_type & GOT_TLS_IE)
11467 {
11468 if (need_relocs)
11469 {
00a97672
RS		 11470 if (indx == 0)
11471 outrel.r_addend = value - dtpoff_base (info);
11472 else
11473 outrel.r_addend = 0;
362d30a1
RS		 11474 outrel.r_offset = (sgot->output_section->vma
11475 + sgot->output_offset
ba93b8ac
DJ		 11476 + cur_off);
11477 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11478
00a97672
RS		 11479 if (globals->use_rel)
11480 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11481 sgot->contents + cur_off);
ba93b8ac 11482
47beaa6a 11483 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11484 }
11485 else
11486 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11487 sgot->contents + cur_off);
ba93b8ac
DJ		 11488 cur_off += 4;
11489 }
11490
11491 if (h != NULL)
11492 h->got.offset |= 1;
11493 else
11494 local_got_offsets[r_symndx] |= 1;
11495 }
11496
11497 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11498 off += 8;
0855e32b
NS		 11499 else if (tls_type & GOT_TLS_GDESC)
11500 off = offplt;
11501
11502 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11503 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11504 {
11505 bfd_signed_vma offset;
12352d3f
PB		 11506 /* TLS stubs are arm mode. The original symbol is a
11507 data object, so branch_type is bogus. */
11508 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11509 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11510 = arm_type_of_stub (info, input_section, rel,
11511 st_type, &branch_type,
0855e32b
NS		 11512 (struct elf32_arm_link_hash_entry *)h,
11513 globals->tls_trampoline, globals->root.splt,
11514 input_bfd, sym_name);
11515
11516 if (stub_type != arm_stub_none)
11517 {
11518 struct elf32_arm_stub_hash_entry *stub_entry
11519 = elf32_arm_get_stub_entry
11520 (input_section, globals->root.splt, 0, rel,
11521 globals, stub_type);
11522 offset = (stub_entry->stub_offset
11523 + stub_entry->stub_sec->output_offset
11524 + stub_entry->stub_sec->output_section->vma);
11525 }
11526 else
11527 offset = (globals->root.splt->output_section->vma
11528 + globals->root.splt->output_offset
11529 + globals->tls_trampoline);
11530
11531 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11532 {
11533 unsigned long inst;
b38cadfb
NC		 11534
11535 offset -= (input_section->output_section->vma
11536 + input_section->output_offset
11537 + rel->r_offset + 8);
0855e32b
NS		 11538
11539 inst = offset >> 2;
11540 inst &= 0x00ffffff;
11541 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11542 }
11543 else
11544 {
11545 /* Thumb blx encodes the offset in a complicated
11546 fashion. */
11547 unsigned upper_insn, lower_insn;
11548 unsigned neg;
11549
b38cadfb
NC		 11550 offset -= (input_section->output_section->vma
11551 + input_section->output_offset
0855e32b 11552 + rel->r_offset + 4);
b38cadfb 11553
12352d3f
PB		 11554 if (stub_type != arm_stub_none
11555 && arm_stub_is_thumb (stub_type))
11556 {
11557 lower_insn = 0xd000;
11558 }
11559 else
11560 {
11561 lower_insn = 0xc000;
6a631e86 11562 /* Round up the offset to a word boundary. */
12352d3f
PB		 11563 offset = (offset + 2) & ~2;
11564 }
11565
0855e32b
NS		 11566 neg = offset < 0;
11567 upper_insn = (0xf000
11568 | ((offset >> 12) & 0x3ff)
11569 | (neg << 10));
12352d3f 11570 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11571 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11572 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11573 bfd_put_16 (input_bfd, upper_insn, hit_data);
11574 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11575 return bfd_reloc_ok;
11576 }
11577 }
11578 /* These relocations needs special care, as besides the fact
11579 they point somewhere in .gotplt, the addend must be
11580 adjusted accordingly depending on the type of instruction
6a631e86 11581 we refer to. */
0855e32b
NS		 11582 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11583 {
11584 unsigned long data, insn;
11585 unsigned thumb;
b38cadfb 11586
0855e32b
NS		 11587 data = bfd_get_32 (input_bfd, hit_data);
11588 thumb = data & 1;
11589 data &= ~1u;
b38cadfb 11590
0855e32b
NS		 11591 if (thumb)
11592 {
11593 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11594 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11595 insn = (insn << 16)
11596 | bfd_get_16 (input_bfd,
11597 contents + rel->r_offset - data + 2);
11598 if ((insn & 0xf800c000) == 0xf000c000)
11599 /* bl/blx */
11600 value = -6;
11601 else if ((insn & 0xffffff00) == 0x4400)
11602 /* add */
11603 value = -5;
11604 else
11605 {
4eca0228 11606 _bfd_error_handler
695344c0 11607 /* xgettext:c-format */
2dcf00ce 11608 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11609 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11610 "referenced by TLS_GOTDESC"),
11611 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11612 "Thumb", insn);
0855e32b
NS		 11613 return bfd_reloc_notsupported;
11614 }
11615 }
11616 else
11617 {
11618 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11619
11620 switch (insn >> 24)
11621 {
11622 case 0xeb: /* bl */
11623 case 0xfa: /* blx */
11624 value = -4;
11625 break;
11626
11627 case 0xe0: /* add */
11628 value = -8;
11629 break;
b38cadfb 11630
0855e32b 11631 default:
4eca0228 11632 _bfd_error_handler
695344c0 11633 /* xgettext:c-format */
2dcf00ce 11634 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11635 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11636 "referenced by TLS_GOTDESC"),
11637 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11638 "ARM", insn);
0855e32b
NS		 11639 return bfd_reloc_notsupported;
11640 }
11641 }
b38cadfb 11642
0855e32b
NS		 11643 value += ((globals->root.sgotplt->output_section->vma
11644 + globals->root.sgotplt->output_offset + off)
11645 - (input_section->output_section->vma
11646 + input_section->output_offset
11647 + rel->r_offset)
11648 + globals->sgotplt_jump_table_size);
11649 }
11650 else
11651 value = ((globals->root.sgot->output_section->vma
11652 + globals->root.sgot->output_offset + off)
11653 - (input_section->output_section->vma
11654 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11655
11656 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11657 contents, rel->r_offset, value,
00a97672 11658 rel->r_addend);
ba93b8ac
DJ		 11659 }
11660
11661 case R_ARM_TLS_LE32:
3cbc1e5e 11662 if (bfd_link_dll (info))
ba93b8ac 11663 {
4eca0228 11664 _bfd_error_handler
695344c0 11665 /* xgettext:c-format */
2dcf00ce
AM		 11666 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
11667 "in shared object"),
11668 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 11669 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11670 }
11671 else
11672 value = tpoff (info, value);
906e58ca 11673
ba93b8ac 11674 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11675 contents, rel->r_offset, value,
11676 rel->r_addend);
ba93b8ac 11677
319850b4
JB		 11678 case R_ARM_V4BX:
11679 if (globals->fix_v4bx)
845b51d6
PB		 11680 {
11681 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11682
845b51d6
PB		 11683 /* Ensure that we have a BX instruction. */
11684 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11685
845b51d6
PB		 11686 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11687 {
11688 /* Branch to veneer. */
11689 bfd_vma glue_addr;
11690 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11691 glue_addr -= input_section->output_section->vma
11692 + input_section->output_offset
11693 + rel->r_offset + 8;
11694 insn = (insn & 0xf0000000) | 0x0a000000
11695 | ((glue_addr >> 2) & 0x00ffffff);
11696 }
11697 else
11698 {
11699 /* Preserve Rm (lowest four bits) and the condition code
11700 (highest four bits). Other bits encode MOV PC,Rm. */
11701 insn = (insn & 0xf000000f) | 0x01a0f000;
11702 }
319850b4 11703
845b51d6
PB		 11704 bfd_put_32 (input_bfd, insn, hit_data);
11705 }
319850b4
JB		 11706 return bfd_reloc_ok;
11707
b6895b4f
PB		 11708 case R_ARM_MOVW_ABS_NC:
11709 case R_ARM_MOVT_ABS:
11710 case R_ARM_MOVW_PREL_NC:
11711 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11712 /* Until we properly support segment-base-relative addressing then
11713 we assume the segment base to be zero, as for the group relocations.
11714 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11715 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11716 case R_ARM_MOVW_BREL_NC:
11717 case R_ARM_MOVW_BREL:
11718 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11719 {
11720 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11721
11722 if (globals->use_rel)
11723 {
11724 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11725 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11726 }
92f5d02b 11727
b6895b4f 11728 value += signed_addend;
b6895b4f
PB		 11729
11730 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11731 value -= (input_section->output_section->vma
11732 + input_section->output_offset + rel->r_offset);
11733
92f5d02b 11734 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11735 return bfd_reloc_overflow;
92f5d02b 11736
35fc36a8 11737 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11738 value |= 1;
11739
11740 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11741 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11742 value >>= 16;
11743
11744 insn &= 0xfff0f000;
11745 insn |= value & 0xfff;
11746 insn |= (value & 0xf000) << 4;
11747 bfd_put_32 (input_bfd, insn, hit_data);
11748 }
11749 return bfd_reloc_ok;
11750
11751 case R_ARM_THM_MOVW_ABS_NC:
11752 case R_ARM_THM_MOVT_ABS:
11753 case R_ARM_THM_MOVW_PREL_NC:
11754 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11755 /* Until we properly support segment-base-relative addressing then
11756 we assume the segment base to be zero, as for the above relocations.
11757 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11758 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11759 as R_ARM_THM_MOVT_ABS. */
11760 case R_ARM_THM_MOVW_BREL_NC:
11761 case R_ARM_THM_MOVW_BREL:
11762 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11763 {
11764 bfd_vma insn;
906e58ca 11765
b6895b4f
PB		 11766 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11767 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11768
11769 if (globals->use_rel)
11770 {
11771 addend = ((insn >> 4) & 0xf000)
11772 | ((insn >> 15) & 0x0800)
11773 | ((insn >> 4) & 0x0700)
07d6d2b8 11774 | (insn & 0x00ff);
39623e12 11775 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11776 }
92f5d02b 11777
b6895b4f 11778 value += signed_addend;
b6895b4f
PB		 11779
11780 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11781 value -= (input_section->output_section->vma
11782 + input_section->output_offset + rel->r_offset);
11783
92f5d02b 11784 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11785 return bfd_reloc_overflow;
92f5d02b 11786
35fc36a8 11787 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11788 value |= 1;
11789
11790 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11791 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11792 value >>= 16;
11793
11794 insn &= 0xfbf08f00;
11795 insn |= (value & 0xf000) << 4;
11796 insn |= (value & 0x0800) << 15;
11797 insn |= (value & 0x0700) << 4;
11798 insn |= (value & 0x00ff);
11799
11800 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11801 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11802 }
11803 return bfd_reloc_ok;
11804
4962c51a
MS		 11805 case R_ARM_ALU_PC_G0_NC:
11806 case R_ARM_ALU_PC_G1_NC:
11807 case R_ARM_ALU_PC_G0:
11808 case R_ARM_ALU_PC_G1:
11809 case R_ARM_ALU_PC_G2:
11810 case R_ARM_ALU_SB_G0_NC:
11811 case R_ARM_ALU_SB_G1_NC:
11812 case R_ARM_ALU_SB_G0:
11813 case R_ARM_ALU_SB_G1:
11814 case R_ARM_ALU_SB_G2:
11815 {
11816 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11817 bfd_vma pc = input_section->output_section->vma
4962c51a 11818 + input_section->output_offset + rel->r_offset;
31a91d61 11819 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11820 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11821 bfd_vma residual;
11822 bfd_vma g_n;
4962c51a 11823 bfd_signed_vma signed_value;
99059e56
RM		 11824 int group = 0;
11825
11826 /* Determine which group of bits to select. */
11827 switch (r_type)
11828 {
11829 case R_ARM_ALU_PC_G0_NC:
11830 case R_ARM_ALU_PC_G0:
11831 case R_ARM_ALU_SB_G0_NC:
11832 case R_ARM_ALU_SB_G0:
11833 group = 0;
11834 break;
11835
11836 case R_ARM_ALU_PC_G1_NC:
11837 case R_ARM_ALU_PC_G1:
11838 case R_ARM_ALU_SB_G1_NC:
11839 case R_ARM_ALU_SB_G1:
11840 group = 1;
11841 break;
11842
11843 case R_ARM_ALU_PC_G2:
11844 case R_ARM_ALU_SB_G2:
11845 group = 2;
11846 break;
11847
11848 default:
11849 abort ();
11850 }
11851
11852 /* If REL, extract the addend from the insn. If RELA, it will
11853 have already been fetched for us. */
4962c51a 11854 if (globals->use_rel)
99059e56
RM		 11855 {
11856 int negative;
11857 bfd_vma constant = insn & 0xff;
11858 bfd_vma rotation = (insn & 0xf00) >> 8;
11859
11860 if (rotation == 0)
11861 signed_addend = constant;
11862 else
11863 {
11864 /* Compensate for the fact that in the instruction, the
11865 rotation is stored in multiples of 2 bits. */
11866 rotation *= 2;
11867
11868 /* Rotate "constant" right by "rotation" bits. */
11869 signed_addend = (constant >> rotation) |
11870 (constant << (8 * sizeof (bfd_vma) - rotation));
11871 }
11872
11873 /* Determine if the instruction is an ADD or a SUB.
11874 (For REL, this determines the sign of the addend.) */
11875 negative = identify_add_or_sub (insn);
11876 if (negative == 0)
11877 {
4eca0228 11878 _bfd_error_handler
695344c0 11879 /* xgettext:c-format */
90b6238f 11880 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 11881 "are allowed for ALU group relocations"),
11882 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 11883 return bfd_reloc_overflow;
11884 }
11885
11886 signed_addend *= negative;
11887 }
4962c51a
MS		 11888
11889 /* Compute the value (X) to go in the place. */
99059e56
RM		 11890 if (r_type == R_ARM_ALU_PC_G0_NC
11891 || r_type == R_ARM_ALU_PC_G1_NC
11892 || r_type == R_ARM_ALU_PC_G0
11893 || r_type == R_ARM_ALU_PC_G1
11894 || r_type == R_ARM_ALU_PC_G2)
11895 /* PC relative. */
11896 signed_value = value - pc + signed_addend;
11897 else
11898 /* Section base relative. */
11899 signed_value = value - sb + signed_addend;
11900
11901 /* If the target symbol is a Thumb function, then set the
11902 Thumb bit in the address. */
35fc36a8 11903 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11904 signed_value |= 1;
11905
99059e56
RM		 11906 /* Calculate the value of the relevant G_n, in encoded
11907 constant-with-rotation format. */
b6518b38
NC		 11908 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11909 group, &residual);
99059e56
RM		 11910
11911 /* Check for overflow if required. */
11912 if ((r_type == R_ARM_ALU_PC_G0
11913 || r_type == R_ARM_ALU_PC_G1
11914 || r_type == R_ARM_ALU_PC_G2
11915 || r_type == R_ARM_ALU_SB_G0
11916 || r_type == R_ARM_ALU_SB_G1
11917 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11918 {
4eca0228 11919 _bfd_error_handler
695344c0 11920 /* xgettext:c-format */
90b6238f 11921 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 11922 "splitting %#" PRIx64 " for group relocation %s"),
11923 input_bfd, input_section, (uint64_t) rel->r_offset,
11924 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
11925 howto->name);
99059e56
RM		 11926 return bfd_reloc_overflow;
11927 }
11928
11929 /* Mask out the value and the ADD/SUB part of the opcode; take care
11930 not to destroy the S bit. */
11931 insn &= 0xff1ff000;
11932
11933 /* Set the opcode according to whether the value to go in the
11934 place is negative. */
11935 if (signed_value < 0)
11936 insn |= 1 << 22;
11937 else
11938 insn |= 1 << 23;
11939
11940 /* Encode the offset. */
11941 insn |= g_n;
4962c51a
MS		 11942
11943 bfd_put_32 (input_bfd, insn, hit_data);
11944 }
11945 return bfd_reloc_ok;
11946
11947 case R_ARM_LDR_PC_G0:
11948 case R_ARM_LDR_PC_G1:
11949 case R_ARM_LDR_PC_G2:
11950 case R_ARM_LDR_SB_G0:
11951 case R_ARM_LDR_SB_G1:
11952 case R_ARM_LDR_SB_G2:
11953 {
11954 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11955 bfd_vma pc = input_section->output_section->vma
4962c51a 11956 + input_section->output_offset + rel->r_offset;
31a91d61 11957 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11958 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11959 bfd_vma residual;
4962c51a 11960 bfd_signed_vma signed_value;
99059e56
RM		 11961 int group = 0;
11962
11963 /* Determine which groups of bits to calculate. */
11964 switch (r_type)
11965 {
11966 case R_ARM_LDR_PC_G0:
11967 case R_ARM_LDR_SB_G0:
11968 group = 0;
11969 break;
11970
11971 case R_ARM_LDR_PC_G1:
11972 case R_ARM_LDR_SB_G1:
11973 group = 1;
11974 break;
11975
11976 case R_ARM_LDR_PC_G2:
11977 case R_ARM_LDR_SB_G2:
11978 group = 2;
11979 break;
11980
11981 default:
11982 abort ();
11983 }
11984
11985 /* If REL, extract the addend from the insn. If RELA, it will
11986 have already been fetched for us. */
4962c51a 11987 if (globals->use_rel)
99059e56
RM		 11988 {
11989 int negative = (insn & (1 << 23)) ? 1 : -1;
11990 signed_addend = negative * (insn & 0xfff);
11991 }
4962c51a
MS		 11992
11993 /* Compute the value (X) to go in the place. */
99059e56
RM		 11994 if (r_type == R_ARM_LDR_PC_G0
11995 || r_type == R_ARM_LDR_PC_G1
11996 || r_type == R_ARM_LDR_PC_G2)
11997 /* PC relative. */
11998 signed_value = value - pc + signed_addend;
11999 else
12000 /* Section base relative. */
12001 signed_value = value - sb + signed_addend;
12002
12003 /* Calculate the value of the relevant G_{n-1} to obtain
12004 the residual at that stage. */
b6518b38
NC		 12005 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12006 group - 1, &residual);
99059e56
RM		 12007
12008 /* Check for overflow. */
12009 if (residual >= 0x1000)
12010 {
4eca0228 12011 _bfd_error_handler
695344c0 12012 /* xgettext:c-format */
90b6238f 12013 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12014 "splitting %#" PRIx64 " for group relocation %s"),
12015 input_bfd, input_section, (uint64_t) rel->r_offset,
12016 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12017 howto->name);
99059e56
RM		 12018 return bfd_reloc_overflow;
12019 }
12020
12021 /* Mask out the value and U bit. */
12022 insn &= 0xff7ff000;
12023
12024 /* Set the U bit if the value to go in the place is non-negative. */
12025 if (signed_value >= 0)
12026 insn |= 1 << 23;
12027
12028 /* Encode the offset. */
12029 insn |= residual;
4962c51a
MS		 12030
12031 bfd_put_32 (input_bfd, insn, hit_data);
12032 }
12033 return bfd_reloc_ok;
12034
12035 case R_ARM_LDRS_PC_G0:
12036 case R_ARM_LDRS_PC_G1:
12037 case R_ARM_LDRS_PC_G2:
12038 case R_ARM_LDRS_SB_G0:
12039 case R_ARM_LDRS_SB_G1:
12040 case R_ARM_LDRS_SB_G2:
12041 {
12042 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12043 bfd_vma pc = input_section->output_section->vma
4962c51a 12044 + input_section->output_offset + rel->r_offset;
31a91d61 12045 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12046 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12047 bfd_vma residual;
4962c51a 12048 bfd_signed_vma signed_value;
99059e56
RM		 12049 int group = 0;
12050
12051 /* Determine which groups of bits to calculate. */
12052 switch (r_type)
12053 {
12054 case R_ARM_LDRS_PC_G0:
12055 case R_ARM_LDRS_SB_G0:
12056 group = 0;
12057 break;
12058
12059 case R_ARM_LDRS_PC_G1:
12060 case R_ARM_LDRS_SB_G1:
12061 group = 1;
12062 break;
12063
12064 case R_ARM_LDRS_PC_G2:
12065 case R_ARM_LDRS_SB_G2:
12066 group = 2;
12067 break;
12068
12069 default:
12070 abort ();
12071 }
12072
12073 /* If REL, extract the addend from the insn. If RELA, it will
12074 have already been fetched for us. */
4962c51a 12075 if (globals->use_rel)
99059e56
RM		 12076 {
12077 int negative = (insn & (1 << 23)) ? 1 : -1;
12078 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12079 }
4962c51a
MS		 12080
12081 /* Compute the value (X) to go in the place. */
99059e56
RM		 12082 if (r_type == R_ARM_LDRS_PC_G0
12083 || r_type == R_ARM_LDRS_PC_G1
12084 || r_type == R_ARM_LDRS_PC_G2)
12085 /* PC relative. */
12086 signed_value = value - pc + signed_addend;
12087 else
12088 /* Section base relative. */
12089 signed_value = value - sb + signed_addend;
12090
12091 /* Calculate the value of the relevant G_{n-1} to obtain
12092 the residual at that stage. */
b6518b38
NC		 12093 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12094 group - 1, &residual);
99059e56
RM		 12095
12096 /* Check for overflow. */
12097 if (residual >= 0x100)
12098 {
4eca0228 12099 _bfd_error_handler
695344c0 12100 /* xgettext:c-format */
90b6238f 12101 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12102 "splitting %#" PRIx64 " for group relocation %s"),
12103 input_bfd, input_section, (uint64_t) rel->r_offset,
12104 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12105 howto->name);
99059e56
RM		 12106 return bfd_reloc_overflow;
12107 }
12108
12109 /* Mask out the value and U bit. */
12110 insn &= 0xff7ff0f0;
12111
12112 /* Set the U bit if the value to go in the place is non-negative. */
12113 if (signed_value >= 0)
12114 insn |= 1 << 23;
12115
12116 /* Encode the offset. */
12117 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12118
12119 bfd_put_32 (input_bfd, insn, hit_data);
12120 }
12121 return bfd_reloc_ok;
12122
12123 case R_ARM_LDC_PC_G0:
12124 case R_ARM_LDC_PC_G1:
12125 case R_ARM_LDC_PC_G2:
12126 case R_ARM_LDC_SB_G0:
12127 case R_ARM_LDC_SB_G1:
12128 case R_ARM_LDC_SB_G2:
12129 {
12130 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12131 bfd_vma pc = input_section->output_section->vma
4962c51a 12132 + input_section->output_offset + rel->r_offset;
31a91d61 12133 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12134 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12135 bfd_vma residual;
4962c51a 12136 bfd_signed_vma signed_value;
99059e56
RM		 12137 int group = 0;
12138
12139 /* Determine which groups of bits to calculate. */
12140 switch (r_type)
12141 {
12142 case R_ARM_LDC_PC_G0:
12143 case R_ARM_LDC_SB_G0:
12144 group = 0;
12145 break;
12146
12147 case R_ARM_LDC_PC_G1:
12148 case R_ARM_LDC_SB_G1:
12149 group = 1;
12150 break;
12151
12152 case R_ARM_LDC_PC_G2:
12153 case R_ARM_LDC_SB_G2:
12154 group = 2;
12155 break;
12156
12157 default:
12158 abort ();
12159 }
12160
12161 /* If REL, extract the addend from the insn. If RELA, it will
12162 have already been fetched for us. */
4962c51a 12163 if (globals->use_rel)
99059e56
RM		 12164 {
12165 int negative = (insn & (1 << 23)) ? 1 : -1;
12166 signed_addend = negative * ((insn & 0xff) << 2);
12167 }
4962c51a
MS		 12168
12169 /* Compute the value (X) to go in the place. */
99059e56
RM		 12170 if (r_type == R_ARM_LDC_PC_G0
12171 || r_type == R_ARM_LDC_PC_G1
12172 || r_type == R_ARM_LDC_PC_G2)
12173 /* PC relative. */
12174 signed_value = value - pc + signed_addend;
12175 else
12176 /* Section base relative. */
12177 signed_value = value - sb + signed_addend;
12178
12179 /* Calculate the value of the relevant G_{n-1} to obtain
12180 the residual at that stage. */
b6518b38
NC		 12181 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12182 group - 1, &residual);
99059e56
RM		 12183
12184 /* Check for overflow. (The absolute value to go in the place must be
12185 divisible by four and, after having been divided by four, must
12186 fit in eight bits.) */
12187 if ((residual & 0x3) != 0 || residual >= 0x400)
12188 {
4eca0228 12189 _bfd_error_handler
695344c0 12190 /* xgettext:c-format */
90b6238f 12191 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12192 "splitting %#" PRIx64 " for group relocation %s"),
12193 input_bfd, input_section, (uint64_t) rel->r_offset,
12194 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12195 howto->name);
99059e56
RM		 12196 return bfd_reloc_overflow;
12197 }
12198
12199 /* Mask out the value and U bit. */
12200 insn &= 0xff7fff00;
12201
12202 /* Set the U bit if the value to go in the place is non-negative. */
12203 if (signed_value >= 0)
12204 insn |= 1 << 23;
12205
12206 /* Encode the offset. */
12207 insn |= residual >> 2;
4962c51a
MS		 12208
12209 bfd_put_32 (input_bfd, insn, hit_data);
12210 }
12211 return bfd_reloc_ok;
12212
72d98d16
MG		 12213 case R_ARM_THM_ALU_ABS_G0_NC:
12214 case R_ARM_THM_ALU_ABS_G1_NC:
12215 case R_ARM_THM_ALU_ABS_G2_NC:
12216 case R_ARM_THM_ALU_ABS_G3_NC:
12217 {
12218 const int shift_array[4] = {0, 8, 16, 24};
12219 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12220 bfd_vma addr = value;
12221 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12222
12223 /* Compute address. */
12224 if (globals->use_rel)
12225 signed_addend = insn & 0xff;
12226 addr += signed_addend;
12227 if (branch_type == ST_BRANCH_TO_THUMB)
12228 addr |= 1;
12229 /* Clean imm8 insn. */
12230 insn &= 0xff00;
12231 /* And update with correct part of address. */
12232 insn |= (addr >> shift) & 0xff;
12233 /* Update insn. */
12234 bfd_put_16 (input_bfd, insn, hit_data);
12235 }
12236
12237 *unresolved_reloc_p = FALSE;
12238 return bfd_reloc_ok;
12239
252b5132
RH		 12240 default:
12241 return bfd_reloc_notsupported;
12242 }
12243}
12244
98c1d4aa
NC		 12245/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12246static void
07d6d2b8
AM		 12247arm_add_to_rel (bfd * abfd,
12248 bfd_byte * address,
57e8b36a 12249 reloc_howto_type * howto,
07d6d2b8 12250 bfd_signed_vma increment)
98c1d4aa 12251{
98c1d4aa
NC		 12252 bfd_signed_vma addend;
12253
bd97cb95
DJ		 12254 if (howto->type == R_ARM_THM_CALL
12255 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12256 {
9a5aca8c
AM		 12257 int upper_insn, lower_insn;
12258 int upper, lower;
98c1d4aa 12259
9a5aca8c
AM		 12260 upper_insn = bfd_get_16 (abfd, address);
12261 lower_insn = bfd_get_16 (abfd, address + 2);
12262 upper = upper_insn & 0x7ff;
12263 lower = lower_insn & 0x7ff;
12264
12265 addend = (upper << 12) | (lower << 1);
ddda4409 12266 addend += increment;
9a5aca8c 12267 addend >>= 1;
98c1d4aa 12268
9a5aca8c
AM		 12269 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12270 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12271
dc810e39
AM		 12272 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12273 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12274 }
12275 else
12276 {
07d6d2b8 12277 bfd_vma contents;
9a5aca8c
AM		 12278
12279 contents = bfd_get_32 (abfd, address);
12280
12281 /* Get the (signed) value from the instruction. */
12282 addend = contents & howto->src_mask;
12283 if (addend & ((howto->src_mask + 1) >> 1))
12284 {
12285 bfd_signed_vma mask;
12286
12287 mask = -1;
12288 mask &= ~ howto->src_mask;
12289 addend |= mask;
12290 }
12291
12292 /* Add in the increment, (which is a byte value). */
12293 switch (howto->type)
12294 {
12295 default:
12296 addend += increment;
12297 break;
12298
12299 case R_ARM_PC24:
c6596c5e 12300 case R_ARM_PLT32:
5b5bb741
PB		 12301 case R_ARM_CALL:
12302 case R_ARM_JUMP24:
9a5aca8c 12303 addend <<= howto->size;
dc810e39 12304 addend += increment;
9a5aca8c
AM		 12305
12306 /* Should we check for overflow here ? */
12307
12308 /* Drop any undesired bits. */
12309 addend >>= howto->rightshift;
12310 break;
12311 }
12312
12313 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12314
12315 bfd_put_32 (abfd, contents, address);
ddda4409 12316 }
98c1d4aa 12317}
252b5132 12318
ba93b8ac
DJ		 12319#define IS_ARM_TLS_RELOC(R_TYPE) \
12320 ((R_TYPE) == R_ARM_TLS_GD32 \
12321 || (R_TYPE) == R_ARM_TLS_LDO32 \
12322 || (R_TYPE) == R_ARM_TLS_LDM32 \
12323 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12324 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12325 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12326 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12327 || (R_TYPE) == R_ARM_TLS_IE32 \
12328 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12329
12330/* Specific set of relocations for the gnu tls dialect. */
12331#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12332 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12333 || (R_TYPE) == R_ARM_TLS_CALL \
12334 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12335 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12336 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12337
252b5132 12338/* Relocate an ARM ELF section. */
906e58ca 12339
b34976b6 12340static bfd_boolean
07d6d2b8 12341elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 12342 struct bfd_link_info * info,
07d6d2b8
AM		 12343 bfd * input_bfd,
12344 asection * input_section,
12345 bfd_byte * contents,
12346 Elf_Internal_Rela * relocs,
12347 Elf_Internal_Sym * local_syms,
12348 asection ** local_sections)
252b5132 12349{
b34976b6
AM		 12350 Elf_Internal_Shdr *symtab_hdr;
12351 struct elf_link_hash_entry **sym_hashes;
12352 Elf_Internal_Rela *rel;
12353 Elf_Internal_Rela *relend;
12354 const char *name;
b32d3aa2 12355 struct elf32_arm_link_hash_table * globals;
252b5132 12356
4e7fd91e 12357 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12358 if (globals == NULL)
12359 return FALSE;
b491616a 12360
0ffa91dd 12361 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12362 sym_hashes = elf_sym_hashes (input_bfd);
12363
12364 rel = relocs;
12365 relend = relocs + input_section->reloc_count;
12366 for (; rel < relend; rel++)
12367 {
07d6d2b8
AM		 12368 int r_type;
12369 reloc_howto_type * howto;
12370 unsigned long r_symndx;
12371 Elf_Internal_Sym * sym;
12372 asection * sec;
252b5132 12373 struct elf_link_hash_entry * h;
07d6d2b8
AM		 12374 bfd_vma relocation;
12375 bfd_reloc_status_type r;
12376 arelent bfd_reloc;
12377 char sym_type;
12378 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12379 char *error_message = NULL;
f21f3fe0 12380
252b5132 12381 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12382 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12383 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12384
ba96a88f 12385 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12386 || r_type == R_ARM_GNU_VTINHERIT)
12387 continue;
252b5132 12388
47aeb64c
NC		 12389 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
12390
12391 if (howto == NULL)
12392 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 12393
252b5132
RH		 12394 h = NULL;
12395 sym = NULL;
12396 sec = NULL;
9b485d32 12397
252b5132
RH		 12398 if (r_symndx < symtab_hdr->sh_info)
12399 {
12400 sym = local_syms + r_symndx;
ba93b8ac 12401 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12402 sec = local_sections[r_symndx];
ffcb4889
NS		 12403
12404 /* An object file might have a reference to a local
12405 undefined symbol. This is a daft object file, but we
12406 should at least do something about it. V4BX & NONE
12407 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12408 allowed to use the undefined symbol, so allow those.
12409 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12410 if (r_type != R_ARM_V4BX
12411 && r_type != R_ARM_NONE
77b4f08f 12412 && r_symndx != STN_UNDEF
ffcb4889
NS		 12413 && bfd_is_und_section (sec)
12414 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12415 (*info->callbacks->undefined_symbol)
12416 (info, bfd_elf_string_from_elf_section
12417 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12418 input_bfd, input_section,
12419 rel->r_offset, TRUE);
b38cadfb 12420
4e7fd91e 12421 if (globals->use_rel)
f8df10f4 12422 {
4e7fd91e
PB		 12423 relocation = (sec->output_section->vma
12424 + sec->output_offset
12425 + sym->st_value);
0e1862bb 12426 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12427 && (sec->flags & SEC_MERGE)
12428 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12429 {
4e7fd91e
PB		 12430 asection *msec;
12431 bfd_vma addend, value;
12432
39623e12 12433 switch (r_type)
4e7fd91e 12434 {
39623e12
PB		 12435 case R_ARM_MOVW_ABS_NC:
12436 case R_ARM_MOVT_ABS:
12437 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12438 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12439 addend = (addend ^ 0x8000) - 0x8000;
12440 break;
f8df10f4 12441
39623e12
PB		 12442 case R_ARM_THM_MOVW_ABS_NC:
12443 case R_ARM_THM_MOVT_ABS:
12444 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12445 << 16;
12446 value |= bfd_get_16 (input_bfd,
12447 contents + rel->r_offset + 2);
12448 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12449 | ((value & 0x04000000) >> 15);
12450 addend = (addend ^ 0x8000) - 0x8000;
12451 break;
f8df10f4 12452
39623e12
PB		 12453 default:
12454 if (howto->rightshift
12455 || (howto->src_mask & (howto->src_mask + 1)))
12456 {
4eca0228 12457 _bfd_error_handler
695344c0 12458 /* xgettext:c-format */
2dcf00ce
AM		 12459 (_("%pB(%pA+%#" PRIx64 "): "
12460 "%s relocation against SEC_MERGE section"),
39623e12 12461 input_bfd, input_section,
2dcf00ce 12462 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 12463 return FALSE;
12464 }
12465
12466 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12467
12468 /* Get the (signed) value from the instruction. */
12469 addend = value & howto->src_mask;
12470 if (addend & ((howto->src_mask + 1) >> 1))
12471 {
12472 bfd_signed_vma mask;
12473
12474 mask = -1;
12475 mask &= ~ howto->src_mask;
12476 addend |= mask;
12477 }
12478 break;
4e7fd91e 12479 }
39623e12 12480
4e7fd91e
PB		 12481 msec = sec;
12482 addend =
12483 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12484 - relocation;
12485 addend += msec->output_section->vma + msec->output_offset;
39623e12 12486
cc643b88 12487 /* Cases here must match those in the preceding
39623e12
PB		 12488 switch statement. */
12489 switch (r_type)
12490 {
12491 case R_ARM_MOVW_ABS_NC:
12492 case R_ARM_MOVT_ABS:
12493 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12494 | (addend & 0xfff);
12495 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12496 break;
12497
12498 case R_ARM_THM_MOVW_ABS_NC:
12499 case R_ARM_THM_MOVT_ABS:
12500 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12501 | (addend & 0xff) | ((addend & 0x0800) << 15);
12502 bfd_put_16 (input_bfd, value >> 16,
12503 contents + rel->r_offset);
12504 bfd_put_16 (input_bfd, value,
12505 contents + rel->r_offset + 2);
12506 break;
12507
12508 default:
12509 value = (value & ~ howto->dst_mask)
12510 | (addend & howto->dst_mask);
12511 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12512 break;
12513 }
f8df10f4 12514 }
f8df10f4 12515 }
4e7fd91e
PB		 12516 else
12517 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12518 }
12519 else
12520 {
62d887d4 12521 bfd_boolean warned, ignored;
560e09e9 12522
b2a8e766
AM		 12523 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12524 r_symndx, symtab_hdr, sym_hashes,
12525 h, sec, relocation,
62d887d4 12526 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12527
12528 sym_type = h->type;
252b5132
RH		 12529 }
12530
dbaa2011 12531 if (sec != NULL && discarded_section (sec))
e4067dbb 12532 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12533 rel, 1, relend, howto, 0, contents);
ab96bf03 12534
0e1862bb 12535 if (bfd_link_relocatable (info))
ab96bf03
AM		 12536 {
12537 /* This is a relocatable link. We don't have to change
12538 anything, unless the reloc is against a section symbol,
12539 in which case we have to adjust according to where the
12540 section symbol winds up in the output section. */
12541 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12542 {
12543 if (globals->use_rel)
12544 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12545 howto, (bfd_signed_vma) sec->output_offset);
12546 else
12547 rel->r_addend += sec->output_offset;
12548 }
12549 continue;
12550 }
12551
252b5132
RH		 12552 if (h != NULL)
12553 name = h->root.root.string;
12554 else
12555 {
12556 name = (bfd_elf_string_from_elf_section
12557 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12558 if (name == NULL || *name == '\0')
12559 name = bfd_section_name (input_bfd, sec);
12560 }
f21f3fe0 12561
cf35638d 12562 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12563 && r_type != R_ARM_NONE
12564 && (h == NULL
12565 || h->root.type == bfd_link_hash_defined
12566 || h->root.type == bfd_link_hash_defweak)
12567 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12568 {
4eca0228 12569 _bfd_error_handler
ba93b8ac 12570 ((sym_type == STT_TLS
695344c0 12571 /* xgettext:c-format */
2dcf00ce 12572 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 12573 /* xgettext:c-format */
2dcf00ce 12574 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 12575 input_bfd,
12576 input_section,
2dcf00ce 12577 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 12578 howto->name,
12579 name);
12580 }
12581
0855e32b 12582 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12583 done, i.e., the relaxation produced the final output we want,
12584 and we won't let anybody mess with it. Also, we have to do
12585 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12586 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12587 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12588 || (IS_ARM_TLS_GNU_RELOC (r_type)
12589 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12590 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12591 & GOT_TLS_GDESC)))
12592 {
12593 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12594 contents, rel, h == NULL);
12595 /* This may have been marked unresolved because it came from
12596 a shared library. But we've just dealt with that. */
12597 unresolved_reloc = 0;
12598 }
12599 else
12600 r = bfd_reloc_continue;
b38cadfb 12601
39d911fc
TP		 12602 if (r == bfd_reloc_continue)
12603 {
12604 unsigned char branch_type =
12605 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12606 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12607
12608 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12609 input_section, contents, rel,
12610 relocation, info, sec, name,
12611 sym_type, branch_type, h,
12612 &unresolved_reloc,
12613 &error_message);
12614 }
0945cdfd
DJ		 12615
12616 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12617 because such sections are not SEC_ALLOC and thus ld.so will
12618 not process them. */
12619 if (unresolved_reloc
99059e56
RM		 12620 && !((input_section->flags & SEC_DEBUGGING) != 0
12621 && h->def_dynamic)
1d5316ab
AM		 12622 && _bfd_elf_section_offset (output_bfd, info, input_section,
12623 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12624 {
4eca0228 12625 _bfd_error_handler
695344c0 12626 /* xgettext:c-format */
2dcf00ce
AM		 12627 (_("%pB(%pA+%#" PRIx64 "): "
12628 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 12629 input_bfd,
12630 input_section,
2dcf00ce 12631 (uint64_t) rel->r_offset,
843fe662
L		 12632 howto->name,
12633 h->root.root.string);
0945cdfd
DJ		 12634 return FALSE;
12635 }
252b5132
RH		 12636
12637 if (r != bfd_reloc_ok)
12638 {
252b5132
RH		 12639 switch (r)
12640 {
12641 case bfd_reloc_overflow:
cf919dfd
PB		 12642 /* If the overflowing reloc was to an undefined symbol,
12643 we have already printed one error message and there
12644 is no point complaining again. */
1a72702b
AM		 12645 if (!h || h->root.type != bfd_link_hash_undefined)
12646 (*info->callbacks->reloc_overflow)
12647 (info, (h ? &h->root : NULL), name, howto->name,
12648 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12649 break;
12650
12651 case bfd_reloc_undefined:
1a72702b
AM		 12652 (*info->callbacks->undefined_symbol)
12653 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12654 break;
12655
12656 case bfd_reloc_outofrange:
f2a9dd69 12657 error_message = _("out of range");
252b5132
RH		 12658 goto common_error;
12659
12660 case bfd_reloc_notsupported:
f2a9dd69 12661 error_message = _("unsupported relocation");
252b5132
RH		 12662 goto common_error;
12663
12664 case bfd_reloc_dangerous:
f2a9dd69 12665 /* error_message should already be set. */
252b5132
RH		 12666 goto common_error;
12667
12668 default:
f2a9dd69 12669 error_message = _("unknown error");
8029a119 12670 /* Fall through. */
252b5132
RH		 12671
12672 common_error:
f2a9dd69 12673 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12674 (*info->callbacks->reloc_dangerous)
12675 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12676 break;
12677 }
12678 }
12679 }
12680
b34976b6 12681 return TRUE;
252b5132
RH		 12682}
12683
91d6fa6a 12684/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12685 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12686 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12687 maintaining that condition). */
12688
12689static void
12690add_unwind_table_edit (arm_unwind_table_edit **head,
12691 arm_unwind_table_edit **tail,
12692 arm_unwind_edit_type type,
12693 asection *linked_section,
91d6fa6a 12694 unsigned int tindex)
2468f9c9 12695{
21d799b5
NC		 12696 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12697 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12698
2468f9c9
PB		 12699 new_edit->type = type;
12700 new_edit->linked_section = linked_section;
91d6fa6a 12701 new_edit->index = tindex;
b38cadfb 12702
91d6fa6a 12703 if (tindex > 0)
2468f9c9
PB		 12704 {
12705 new_edit->next = NULL;
12706
12707 if (*tail)
12708 (*tail)->next = new_edit;
12709
12710 (*tail) = new_edit;
12711
12712 if (!*head)
12713 (*head) = new_edit;
12714 }
12715 else
12716 {
12717 new_edit->next = *head;
12718
12719 if (!*tail)
12720 *tail = new_edit;
12721
12722 *head = new_edit;
12723 }
12724}
12725
12726static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12727
12728/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12729static void
12730adjust_exidx_size(asection *exidx_sec, int adjust)
12731{
12732 asection *out_sec;
12733
12734 if (!exidx_sec->rawsize)
12735 exidx_sec->rawsize = exidx_sec->size;
12736
12737 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12738 out_sec = exidx_sec->output_section;
12739 /* Adjust size of output section. */
12740 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12741}
12742
12743/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12744static void
12745insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12746{
12747 struct _arm_elf_section_data *exidx_arm_data;
12748
12749 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12750 add_unwind_table_edit (
12751 &exidx_arm_data->u.exidx.unwind_edit_list,
12752 &exidx_arm_data->u.exidx.unwind_edit_tail,
12753 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12754
491d01d3
YU		 12755 exidx_arm_data->additional_reloc_count++;
12756
2468f9c9
PB		 12757 adjust_exidx_size(exidx_sec, 8);
12758}
12759
12760/* Scan .ARM.exidx tables, and create a list describing edits which should be
12761 made to those tables, such that:
b38cadfb 12762
2468f9c9
PB		 12763 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12764 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12765 codes which have been inlined into the index).
2468f9c9 12766
85fdf906
AH		 12767 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12768
2468f9c9 12769 The edits are applied when the tables are written
b38cadfb 12770 (in elf32_arm_write_section). */
2468f9c9
PB		 12771
12772bfd_boolean
12773elf32_arm_fix_exidx_coverage (asection **text_section_order,
12774 unsigned int num_text_sections,
85fdf906
AH		 12775 struct bfd_link_info *info,
12776 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12777{
12778 bfd *inp;
12779 unsigned int last_second_word = 0, i;
12780 asection *last_exidx_sec = NULL;
12781 asection *last_text_sec = NULL;
12782 int last_unwind_type = -1;
12783
12784 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12785 text sections. */
c72f2fb2 12786 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12787 {
12788 asection *sec;
b38cadfb 12789
2468f9c9 12790 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12791 {
2468f9c9
PB		 12792 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12793 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12794
dec9d5df 12795 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12796 continue;
b38cadfb 12797
2468f9c9
PB		 12798 if (elf_sec->linked_to)
12799 {
12800 Elf_Internal_Shdr *linked_hdr
99059e56 12801 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12802 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12803 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12804
12805 if (linked_sec_arm_data == NULL)
99059e56 12806 continue;
2468f9c9
PB		 12807
12808 /* Link this .ARM.exidx section back from the text section it
99059e56 12809 describes. */
2468f9c9
PB		 12810 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12811 }
12812 }
12813 }
12814
12815 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12816 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12817 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12818
12819 for (i = 0; i < num_text_sections; i++)
12820 {
12821 asection *sec = text_section_order[i];
12822 asection *exidx_sec;
12823 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12824 struct _arm_elf_section_data *exidx_arm_data;
12825 bfd_byte *contents = NULL;
12826 int deleted_exidx_bytes = 0;
12827 bfd_vma j;
12828 arm_unwind_table_edit *unwind_edit_head = NULL;
12829 arm_unwind_table_edit *unwind_edit_tail = NULL;
12830 Elf_Internal_Shdr *hdr;
12831 bfd *ibfd;
12832
12833 if (arm_data == NULL)
99059e56 12834 continue;
2468f9c9
PB		 12835
12836 exidx_sec = arm_data->u.text.arm_exidx_sec;
12837 if (exidx_sec == NULL)
12838 {
12839 /* Section has no unwind data. */
12840 if (last_unwind_type == 0 || !last_exidx_sec)
12841 continue;
12842
12843 /* Ignore zero sized sections. */
12844 if (sec->size == 0)
12845 continue;
12846
12847 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12848 last_unwind_type = 0;
12849 continue;
12850 }
12851
22a8f80e
PB		 12852 /* Skip /DISCARD/ sections. */
12853 if (bfd_is_abs_section (exidx_sec->output_section))
12854 continue;
12855
2468f9c9
PB		 12856 hdr = &elf_section_data (exidx_sec)->this_hdr;
12857 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12858 continue;
b38cadfb 12859
2468f9c9
PB		 12860 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12861 if (exidx_arm_data == NULL)
99059e56 12862 continue;
b38cadfb 12863
2468f9c9 12864 ibfd = exidx_sec->owner;
b38cadfb 12865
2468f9c9
PB		 12866 if (hdr->contents != NULL)
12867 contents = hdr->contents;
12868 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12869 /* An error? */
12870 continue;
12871
ac06903d
YU		 12872 if (last_unwind_type > 0)
12873 {
12874 unsigned int first_word = bfd_get_32 (ibfd, contents);
12875 /* Add cantunwind if first unwind item does not match section
12876 start. */
12877 if (first_word != sec->vma)
12878 {
12879 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12880 last_unwind_type = 0;
12881 }
12882 }
12883
2468f9c9
PB		 12884 for (j = 0; j < hdr->sh_size; j += 8)
12885 {
12886 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12887 int unwind_type;
12888 int elide = 0;
12889
12890 /* An EXIDX_CANTUNWIND entry. */
12891 if (second_word == 1)
12892 {
12893 if (last_unwind_type == 0)
12894 elide = 1;
12895 unwind_type = 0;
12896 }
12897 /* Inlined unwinding data. Merge if equal to previous. */
12898 else if ((second_word & 0x80000000) != 0)
12899 {
85fdf906
AH		 12900 if (merge_exidx_entries
12901 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12902 elide = 1;
12903 unwind_type = 1;
12904 last_second_word = second_word;
12905 }
12906 /* Normal table entry. In theory we could merge these too,
12907 but duplicate entries are likely to be much less common. */
12908 else
12909 unwind_type = 2;
12910
491d01d3 12911 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12912 {
12913 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12914 DELETE_EXIDX_ENTRY, NULL, j / 8);
12915
12916 deleted_exidx_bytes += 8;
12917 }
12918
12919 last_unwind_type = unwind_type;
12920 }
12921
12922 /* Free contents if we allocated it ourselves. */
12923 if (contents != hdr->contents)
99059e56 12924 free (contents);
2468f9c9
PB		 12925
12926 /* Record edits to be applied later (in elf32_arm_write_section). */
12927 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12928 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12929
2468f9c9
PB		 12930 if (deleted_exidx_bytes > 0)
12931 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12932
12933 last_exidx_sec = exidx_sec;
12934 last_text_sec = sec;
12935 }
12936
12937 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12938 if (!bfd_link_relocatable (info) && last_exidx_sec
12939 && last_unwind_type != 0)
2468f9c9
PB		 12940 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12941
12942 return TRUE;
12943}
12944
3e6b1042
DJ		 12945static bfd_boolean
12946elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12947 bfd *ibfd, const char *name)
12948{
12949 asection *sec, *osec;
12950
3d4d4302 12951 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12952 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12953 return TRUE;
12954
12955 osec = sec->output_section;
12956 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12957 return TRUE;
12958
12959 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12960 sec->output_offset, sec->size))
12961 return FALSE;
12962
12963 return TRUE;
12964}
12965
12966static bfd_boolean
12967elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12968{
12969 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12970 asection *sec, *osec;
3e6b1042 12971
4dfe6ac6
NC		 12972 if (globals == NULL)
12973 return FALSE;
12974
3e6b1042
DJ		 12975 /* Invoke the regular ELF backend linker to do all the work. */
12976 if (!bfd_elf_final_link (abfd, info))
12977 return FALSE;
12978
fe33d2fa
CL		 12979 /* Process stub sections (eg BE8 encoding, ...). */
12980 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12981 unsigned int i;
cdb21a0a
NS		 12982 for (i=0; i<htab->top_id; i++)
12983 {
12984 sec = htab->stub_group[i].stub_sec;
12985 /* Only process it once, in its link_sec slot. */
12986 if (sec && i == htab->stub_group[i].link_sec->id)
12987 {
12988 osec = sec->output_section;
12989 elf32_arm_write_section (abfd, info, sec, sec->contents);
12990 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12991 sec->output_offset, sec->size))
12992 return FALSE;
12993 }
fe33d2fa 12994 }
fe33d2fa 12995
3e6b1042
DJ		 12996 /* Write out any glue sections now that we have created all the
12997 stubs. */
12998 if (globals->bfd_of_glue_owner != NULL)
12999 {
13000 if (! elf32_arm_output_glue_section (info, abfd,
13001 globals->bfd_of_glue_owner,
13002 ARM2THUMB_GLUE_SECTION_NAME))
13003 return FALSE;
13004
13005 if (! elf32_arm_output_glue_section (info, abfd,
13006 globals->bfd_of_glue_owner,
13007 THUMB2ARM_GLUE_SECTION_NAME))
13008 return FALSE;
13009
13010 if (! elf32_arm_output_glue_section (info, abfd,
13011 globals->bfd_of_glue_owner,
13012 VFP11_ERRATUM_VENEER_SECTION_NAME))
13013 return FALSE;
13014
a504d23a
LA		 13015 if (! elf32_arm_output_glue_section (info, abfd,
13016 globals->bfd_of_glue_owner,
13017 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13018 return FALSE;
13019
3e6b1042
DJ		 13020 if (! elf32_arm_output_glue_section (info, abfd,
13021 globals->bfd_of_glue_owner,
13022 ARM_BX_GLUE_SECTION_NAME))
13023 return FALSE;
13024 }
13025
13026 return TRUE;
13027}
13028
5968a7b8
NC		 13029/* Return a best guess for the machine number based on the attributes. */
13030
13031static unsigned int
13032bfd_arm_get_mach_from_attributes (bfd * abfd)
13033{
13034 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13035
13036 switch (arch)
13037 {
13038 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13039 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13040 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13041
13042 case TAG_CPU_ARCH_V5TE:
13043 {
13044 char * name;
13045
13046 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13047 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13048
13049 if (name)
13050 {
13051 if (strcmp (name, "IWMMXT2") == 0)
13052 return bfd_mach_arm_iWMMXt2;
13053
13054 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13055 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13056
13057 if (strcmp (name, "XSCALE") == 0)
13058 {
13059 int wmmx;
13060
13061 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13062 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13063 switch (wmmx)
13064 {
13065 case 1: return bfd_mach_arm_iWMMXt;
13066 case 2: return bfd_mach_arm_iWMMXt2;
13067 default: return bfd_mach_arm_XScale;
13068 }
13069 }
5968a7b8
NC		 13070 }
13071
13072 return bfd_mach_arm_5TE;
13073 }
13074
13075 default:
13076 return bfd_mach_arm_unknown;
13077 }
13078}
13079
c178919b
NC		 13080/* Set the right machine number. */
13081
13082static bfd_boolean
57e8b36a 13083elf32_arm_object_p (bfd *abfd)
c178919b 13084{
5a6c6817 13085 unsigned int mach;
57e8b36a 13086
5a6c6817 13087 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13088
5968a7b8
NC		 13089 if (mach == bfd_mach_arm_unknown)
13090 {
13091 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13092 mach = bfd_mach_arm_ep9312;
13093 else
13094 mach = bfd_arm_get_mach_from_attributes (abfd);
13095 }
c178919b 13096
5968a7b8 13097 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13098 return TRUE;
13099}
13100
fc830a83 13101/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13102
b34976b6 13103static bfd_boolean
57e8b36a 13104elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13105{
13106 if (elf_flags_init (abfd)
13107 && elf_elfheader (abfd)->e_flags != flags)
13108 {
fc830a83
NC		 13109 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13110 {
fd2ec330 13111 if (flags & EF_ARM_INTERWORK)
4eca0228 13112 _bfd_error_handler
90b6238f 13113 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13114 abfd);
fc830a83 13115 else
d003868e 13116 _bfd_error_handler
90b6238f 13117 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13118 abfd);
fc830a83 13119 }
252b5132
RH		 13120 }
13121 else
13122 {
13123 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13124 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13125 }
13126
b34976b6 13127 return TRUE;
252b5132
RH		 13128}
13129
fc830a83 13130/* Copy backend specific data from one object module to another. */
9b485d32 13131
b34976b6 13132static bfd_boolean
57e8b36a 13133elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13134{
13135 flagword in_flags;
13136 flagword out_flags;
13137
0ffa91dd 13138 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13139 return TRUE;
252b5132 13140
fc830a83 13141 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13142 out_flags = elf_elfheader (obfd)->e_flags;
13143
fc830a83
NC		 13144 if (elf_flags_init (obfd)
13145 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13146 && in_flags != out_flags)
252b5132 13147 {
252b5132 13148 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13149 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13150 return FALSE;
252b5132
RH		 13151
13152 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13153 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13154 return FALSE;
252b5132
RH		 13155
13156 /* If the src and dest have different interworking flags
99059e56 13157 then turn off the interworking bit. */
fd2ec330 13158 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13159 {
fd2ec330 13160 if (out_flags & EF_ARM_INTERWORK)
d003868e 13161 _bfd_error_handler
90b6238f 13162 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13163 obfd, ibfd);
252b5132 13164
fd2ec330 13165 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13166 }
1006ba19
PB		 13167
13168 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13169 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13170 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13171 }
13172
13173 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13174 elf_flags_init (obfd) = TRUE;
252b5132 13175
e2349352 13176 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13177}
13178
13179/* Values for Tag_ABI_PCS_R9_use. */
13180enum
13181{
13182 AEABI_R9_V6,
13183 AEABI_R9_SB,
13184 AEABI_R9_TLS,
13185 AEABI_R9_unused
13186};
13187
13188/* Values for Tag_ABI_PCS_RW_data. */
13189enum
13190{
13191 AEABI_PCS_RW_data_absolute,
13192 AEABI_PCS_RW_data_PCrel,
13193 AEABI_PCS_RW_data_SBrel,
13194 AEABI_PCS_RW_data_unused
13195};
13196
13197/* Values for Tag_ABI_enum_size. */
13198enum
13199{
13200 AEABI_enum_unused,
13201 AEABI_enum_short,
13202 AEABI_enum_wide,
13203 AEABI_enum_forced_wide
13204};
13205
104d59d1
JM		 13206/* Determine whether an object attribute tag takes an integer, a
13207 string or both. */
906e58ca 13208
104d59d1
JM		 13209static int
13210elf32_arm_obj_attrs_arg_type (int tag)
13211{
13212 if (tag == Tag_compatibility)
3483fe2e 13213 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13214 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13215 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13216 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13217 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13218 else if (tag < 32)
3483fe2e 13219 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13220 else
3483fe2e 13221 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13222}
13223
5aa6ff7c
AS		 13224/* The ABI defines that Tag_conformance should be emitted first, and that
13225 Tag_nodefaults should be second (if either is defined). This sets those
13226 two positions, and bumps up the position of all the remaining tags to
13227 compensate. */
13228static int
13229elf32_arm_obj_attrs_order (int num)
13230{
3de4a297 13231 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13232 return Tag_conformance;
3de4a297 13233 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13234 return Tag_nodefaults;
13235 if ((num - 2) < Tag_nodefaults)
13236 return num - 2;
13237 if ((num - 1) < Tag_conformance)
13238 return num - 1;
13239 return num;
13240}
13241
e8b36cd1
JM		 13242/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13243static bfd_boolean
13244elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13245{
13246 if ((tag & 127) < 64)
13247 {
13248 _bfd_error_handler
90b6238f 13249 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 13250 abfd, tag);
13251 bfd_set_error (bfd_error_bad_value);
13252 return FALSE;
13253 }
13254 else
13255 {
13256 _bfd_error_handler
90b6238f 13257 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 13258 abfd, tag);
13259 return TRUE;
13260 }
13261}
13262
91e22acd
AS		 13263/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13264 Returns -1 if no architecture could be read. */
13265
13266static int
13267get_secondary_compatible_arch (bfd *abfd)
13268{
13269 obj_attribute *attr =
13270 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13271
13272 /* Note: the tag and its argument below are uleb128 values, though
13273 currently-defined values fit in one byte for each. */
13274 if (attr->s
13275 && attr->s[0] == Tag_CPU_arch
13276 && (attr->s[1] & 128) != 128
13277 && attr->s[2] == 0)
13278 return attr->s[1];
13279
13280 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13281 return -1;
13282}
13283
13284/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13285 The tag is removed if ARCH is -1. */
13286
8e79c3df 13287static void
91e22acd 13288set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13289{
91e22acd
AS		 13290 obj_attribute *attr =
13291 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13292
91e22acd
AS		 13293 if (arch == -1)
13294 {
13295 attr->s = NULL;
13296 return;
8e79c3df 13297 }
91e22acd
AS		 13298
13299 /* Note: the tag and its argument below are uleb128 values, though
13300 currently-defined values fit in one byte for each. */
13301 if (!attr->s)
21d799b5 13302 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13303 attr->s[0] = Tag_CPU_arch;
13304 attr->s[1] = arch;
13305 attr->s[2] = '\0';
8e79c3df
CM		 13306}
13307
91e22acd
AS		 13308/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13309 into account. */
13310
13311static int
13312tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13313 int newtag, int secondary_compat)
8e79c3df 13314{
91e22acd
AS		 13315#define T(X) TAG_CPU_ARCH_##X
13316 int tagl, tagh, result;
13317 const int v6t2[] =
13318 {
13319 T(V6T2), /* PRE_V4. */
13320 T(V6T2), /* V4. */
13321 T(V6T2), /* V4T. */
13322 T(V6T2), /* V5T. */
13323 T(V6T2), /* V5TE. */
13324 T(V6T2), /* V5TEJ. */
13325 T(V6T2), /* V6. */
13326 T(V7), /* V6KZ. */
13327 T(V6T2) /* V6T2. */
13328 };
13329 const int v6k[] =
13330 {
13331 T(V6K), /* PRE_V4. */
13332 T(V6K), /* V4. */
13333 T(V6K), /* V4T. */
13334 T(V6K), /* V5T. */
13335 T(V6K), /* V5TE. */
13336 T(V6K), /* V5TEJ. */
13337 T(V6K), /* V6. */
13338 T(V6KZ), /* V6KZ. */
13339 T(V7), /* V6T2. */
13340 T(V6K) /* V6K. */
13341 };
13342 const int v7[] =
13343 {
13344 T(V7), /* PRE_V4. */
13345 T(V7), /* V4. */
13346 T(V7), /* V4T. */
13347 T(V7), /* V5T. */
13348 T(V7), /* V5TE. */
13349 T(V7), /* V5TEJ. */
13350 T(V7), /* V6. */
13351 T(V7), /* V6KZ. */
13352 T(V7), /* V6T2. */
13353 T(V7), /* V6K. */
13354 T(V7) /* V7. */
13355 };
13356 const int v6_m[] =
13357 {
07d6d2b8
AM		 13358 -1, /* PRE_V4. */
13359 -1, /* V4. */
91e22acd
AS		 13360 T(V6K), /* V4T. */
13361 T(V6K), /* V5T. */
13362 T(V6K), /* V5TE. */
13363 T(V6K), /* V5TEJ. */
13364 T(V6K), /* V6. */
13365 T(V6KZ), /* V6KZ. */
13366 T(V7), /* V6T2. */
13367 T(V6K), /* V6K. */
13368 T(V7), /* V7. */
13369 T(V6_M) /* V6_M. */
13370 };
13371 const int v6s_m[] =
13372 {
07d6d2b8
AM		 13373 -1, /* PRE_V4. */
13374 -1, /* V4. */
91e22acd
AS		 13375 T(V6K), /* V4T. */
13376 T(V6K), /* V5T. */
13377 T(V6K), /* V5TE. */
13378 T(V6K), /* V5TEJ. */
13379 T(V6K), /* V6. */
13380 T(V6KZ), /* V6KZ. */
13381 T(V7), /* V6T2. */
13382 T(V6K), /* V6K. */
13383 T(V7), /* V7. */
13384 T(V6S_M), /* V6_M. */
13385 T(V6S_M) /* V6S_M. */
13386 };
9e3c6df6
PB		 13387 const int v7e_m[] =
13388 {
07d6d2b8
AM		 13389 -1, /* PRE_V4. */
13390 -1, /* V4. */
9e3c6df6
PB		 13391 T(V7E_M), /* V4T. */
13392 T(V7E_M), /* V5T. */
13393 T(V7E_M), /* V5TE. */
13394 T(V7E_M), /* V5TEJ. */
13395 T(V7E_M), /* V6. */
13396 T(V7E_M), /* V6KZ. */
13397 T(V7E_M), /* V6T2. */
13398 T(V7E_M), /* V6K. */
13399 T(V7E_M), /* V7. */
13400 T(V7E_M), /* V6_M. */
13401 T(V7E_M), /* V6S_M. */
13402 T(V7E_M) /* V7E_M. */
13403 };
bca38921
MGD		 13404 const int v8[] =
13405 {
13406 T(V8), /* PRE_V4. */
13407 T(V8), /* V4. */
13408 T(V8), /* V4T. */
13409 T(V8), /* V5T. */
13410 T(V8), /* V5TE. */
13411 T(V8), /* V5TEJ. */
13412 T(V8), /* V6. */
13413 T(V8), /* V6KZ. */
13414 T(V8), /* V6T2. */
13415 T(V8), /* V6K. */
13416 T(V8), /* V7. */
13417 T(V8), /* V6_M. */
13418 T(V8), /* V6S_M. */
13419 T(V8), /* V7E_M. */
13420 T(V8) /* V8. */
13421 };
bff0500d
TP		 13422 const int v8r[] =
13423 {
13424 T(V8R), /* PRE_V4. */
13425 T(V8R), /* V4. */
13426 T(V8R), /* V4T. */
13427 T(V8R), /* V5T. */
13428 T(V8R), /* V5TE. */
13429 T(V8R), /* V5TEJ. */
13430 T(V8R), /* V6. */
13431 T(V8R), /* V6KZ. */
13432 T(V8R), /* V6T2. */
13433 T(V8R), /* V6K. */
13434 T(V8R), /* V7. */
13435 T(V8R), /* V6_M. */
13436 T(V8R), /* V6S_M. */
13437 T(V8R), /* V7E_M. */
13438 T(V8), /* V8. */
13439 T(V8R), /* V8R. */
13440 };
2fd158eb
TP		 13441 const int v8m_baseline[] =
13442 {
13443 -1, /* PRE_V4. */
13444 -1, /* V4. */
13445 -1, /* V4T. */
13446 -1, /* V5T. */
13447 -1, /* V5TE. */
13448 -1, /* V5TEJ. */
13449 -1, /* V6. */
13450 -1, /* V6KZ. */
13451 -1, /* V6T2. */
13452 -1, /* V6K. */
13453 -1, /* V7. */
13454 T(V8M_BASE), /* V6_M. */
13455 T(V8M_BASE), /* V6S_M. */
13456 -1, /* V7E_M. */
13457 -1, /* V8. */
bff0500d 13458 -1, /* V8R. */
2fd158eb
TP		 13459 T(V8M_BASE) /* V8-M BASELINE. */
13460 };
13461 const int v8m_mainline[] =
13462 {
13463 -1, /* PRE_V4. */
13464 -1, /* V4. */
13465 -1, /* V4T. */
13466 -1, /* V5T. */
13467 -1, /* V5TE. */
13468 -1, /* V5TEJ. */
13469 -1, /* V6. */
13470 -1, /* V6KZ. */
13471 -1, /* V6T2. */
13472 -1, /* V6K. */
13473 T(V8M_MAIN), /* V7. */
13474 T(V8M_MAIN), /* V6_M. */
13475 T(V8M_MAIN), /* V6S_M. */
13476 T(V8M_MAIN), /* V7E_M. */
13477 -1, /* V8. */
bff0500d 13478 -1, /* V8R. */
2fd158eb
TP		 13479 T(V8M_MAIN), /* V8-M BASELINE. */
13480 T(V8M_MAIN) /* V8-M MAINLINE. */
13481 };
91e22acd
AS		 13482 const int v4t_plus_v6_m[] =
13483 {
13484 -1, /* PRE_V4. */
13485 -1, /* V4. */
13486 T(V4T), /* V4T. */
13487 T(V5T), /* V5T. */
13488 T(V5TE), /* V5TE. */
13489 T(V5TEJ), /* V5TEJ. */
13490 T(V6), /* V6. */
13491 T(V6KZ), /* V6KZ. */
13492 T(V6T2), /* V6T2. */
13493 T(V6K), /* V6K. */
13494 T(V7), /* V7. */
13495 T(V6_M), /* V6_M. */
13496 T(V6S_M), /* V6S_M. */
9e3c6df6 13497 T(V7E_M), /* V7E_M. */
bca38921 13498 T(V8), /* V8. */
bff0500d 13499 -1, /* V8R. */
2fd158eb
TP		 13500 T(V8M_BASE), /* V8-M BASELINE. */
13501 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13502 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13503 };
13504 const int *comb[] =
13505 {
13506 v6t2,
13507 v6k,
13508 v7,
13509 v6_m,
13510 v6s_m,
9e3c6df6 13511 v7e_m,
bca38921 13512 v8,
bff0500d 13513 v8r,
2fd158eb
TP		 13514 v8m_baseline,
13515 v8m_mainline,
91e22acd
AS		 13516 /* Pseudo-architecture. */
13517 v4t_plus_v6_m
13518 };
13519
13520 /* Check we've not got a higher architecture than we know about. */
13521
9e3c6df6 13522 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13523 {
90b6238f 13524 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 13525 return -1;
13526 }
13527
13528 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13529
13530 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13531 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13532 oldtag = T(V4T_PLUS_V6_M);
13533
13534 /* And override the new tag if we have a Tag_also_compatible_with on the
13535 input. */
13536
13537 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13538 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13539 newtag = T(V4T_PLUS_V6_M);
13540
13541 tagl = (oldtag < newtag) ? oldtag : newtag;
13542 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13543
13544 /* Architectures before V6KZ add features monotonically. */
13545 if (tagh <= TAG_CPU_ARCH_V6KZ)
13546 return result;
13547
4ed7ed8d 13548 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13549
13550 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13551 as the canonical version. */
13552 if (result == T(V4T_PLUS_V6_M))
13553 {
13554 result = T(V4T);
13555 *secondary_compat_out = T(V6_M);
13556 }
13557 else
13558 *secondary_compat_out = -1;
13559
13560 if (result == -1)
13561 {
90b6238f 13562 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 13563 ibfd, oldtag, newtag);
13564 return -1;
13565 }
13566
13567 return result;
13568#undef T
8e79c3df
CM		 13569}
13570
ac56ee8f
MGD		 13571/* Query attributes object to see if integer divide instructions may be
13572 present in an object. */
13573static bfd_boolean
13574elf32_arm_attributes_accept_div (const obj_attribute *attr)
13575{
13576 int arch = attr[Tag_CPU_arch].i;
13577 int profile = attr[Tag_CPU_arch_profile].i;
13578
13579 switch (attr[Tag_DIV_use].i)
13580 {
13581 case 0:
13582 /* Integer divide allowed if instruction contained in archetecture. */
13583 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13584 return TRUE;
13585 else if (arch >= TAG_CPU_ARCH_V7E_M)
13586 return TRUE;
13587 else
13588 return FALSE;
13589
13590 case 1:
13591 /* Integer divide explicitly prohibited. */
13592 return FALSE;
13593
13594 default:
13595 /* Unrecognised case - treat as allowing divide everywhere. */
13596 case 2:
13597 /* Integer divide allowed in ARM state. */
13598 return TRUE;
13599 }
13600}
13601
13602/* Query attributes object to see if integer divide instructions are
13603 forbidden to be in the object. This is not the inverse of
13604 elf32_arm_attributes_accept_div. */
13605static bfd_boolean
13606elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13607{
13608 return attr[Tag_DIV_use].i == 1;
13609}
13610
ee065d83
PB		 13611/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13612 are conflicting attributes. */
906e58ca 13613
ee065d83 13614static bfd_boolean
50e03d47 13615elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 13616{
50e03d47 13617 bfd *obfd = info->output_bfd;
104d59d1
JM		 13618 obj_attribute *in_attr;
13619 obj_attribute *out_attr;
ee065d83
PB		 13620 /* Some tags have 0 = don't care, 1 = strong requirement,
13621 2 = weak requirement. */
91e22acd 13622 static const int order_021[3] = {0, 2, 1};
ee065d83 13623 int i;
91e22acd 13624 bfd_boolean result = TRUE;
9274e9de 13625 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13626
3e6b1042
DJ		 13627 /* Skip the linker stubs file. This preserves previous behavior
13628 of accepting unknown attributes in the first input file - but
13629 is that a bug? */
13630 if (ibfd->flags & BFD_LINKER_CREATED)
13631 return TRUE;
13632
9274e9de
TG		 13633 /* Skip any input that hasn't attribute section.
13634 This enables to link object files without attribute section with
13635 any others. */
13636 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13637 return TRUE;
13638
104d59d1 13639 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13640 {
13641 /* This is the first object. Copy the attributes. */
104d59d1 13642 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13643
cd21e546
MGD		 13644 out_attr = elf_known_obj_attributes_proc (obfd);
13645
004ae526
PB		 13646 /* Use the Tag_null value to indicate the attributes have been
13647 initialized. */
cd21e546 13648 out_attr[0].i = 1;
004ae526 13649
cd21e546
MGD		 13650 /* We do not output objects with Tag_MPextension_use_legacy - we move
13651 the attribute's value to Tag_MPextension_use. */
13652 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13653 {
13654 if (out_attr[Tag_MPextension_use].i != 0
13655 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13656 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13657 {
13658 _bfd_error_handler
871b3ab2 13659 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 13660 "Tag_MPextension_use attributes"), ibfd);
13661 result = FALSE;
13662 }
13663
13664 out_attr[Tag_MPextension_use] =
13665 out_attr[Tag_MPextension_use_legacy];
13666 out_attr[Tag_MPextension_use_legacy].type = 0;
13667 out_attr[Tag_MPextension_use_legacy].i = 0;
13668 }
13669
13670 return result;
ee065d83
PB		 13671 }
13672
104d59d1
JM		 13673 in_attr = elf_known_obj_attributes_proc (ibfd);
13674 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13675 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13676 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13677 {
5c294fee
TG		 13678 /* Ignore mismatches if the object doesn't use floating point or is
13679 floating point ABI independent. */
13680 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13681 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13682 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13683 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13684 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13685 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13686 {
13687 _bfd_error_handler
871b3ab2 13688 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 13689 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13690 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13691 result = FALSE;
ee065d83
PB		 13692 }
13693 }
13694
3de4a297 13695 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13696 {
13697 /* Merge this attribute with existing attributes. */
13698 switch (i)
13699 {
13700 case Tag_CPU_raw_name:
13701 case Tag_CPU_name:
6a631e86 13702 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13703 break;
13704
13705 case Tag_ABI_optimization_goals:
13706 case Tag_ABI_FP_optimization_goals:
13707 /* Use the first value seen. */
13708 break;
13709
13710 case Tag_CPU_arch:
91e22acd
AS		 13711 {
13712 int secondary_compat = -1, secondary_compat_out = -1;
13713 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13714 int arch_attr;
13715 static const char *name_table[] =
13716 {
91e22acd
AS		 13717 /* These aren't real CPU names, but we can't guess
13718 that from the architecture version alone. */
13719 "Pre v4",
13720 "ARM v4",
13721 "ARM v4T",
13722 "ARM v5T",
13723 "ARM v5TE",
13724 "ARM v5TEJ",
13725 "ARM v6",
13726 "ARM v6KZ",
13727 "ARM v6T2",
13728 "ARM v6K",
13729 "ARM v7",
13730 "ARM v6-M",
bca38921 13731 "ARM v6S-M",
2fd158eb
TP		 13732 "ARM v8",
13733 "",
13734 "ARM v8-M.baseline",
13735 "ARM v8-M.mainline",
91e22acd
AS		 13736 };
13737
13738 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13739 secondary_compat = get_secondary_compatible_arch (ibfd);
13740 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13741 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13742 &secondary_compat_out,
13743 in_attr[i].i,
13744 secondary_compat);
13745
13746 /* Return with error if failed to merge. */
13747 if (arch_attr == -1)
13748 return FALSE;
13749
13750 out_attr[i].i = arch_attr;
13751
91e22acd
AS		 13752 set_secondary_compatible_arch (obfd, secondary_compat_out);
13753
13754 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13755 if (out_attr[i].i == saved_out_attr)
13756 ; /* Leave the names alone. */
13757 else if (out_attr[i].i == in_attr[i].i)
13758 {
13759 /* The output architecture has been changed to match the
13760 input architecture. Use the input names. */
13761 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13762 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13763 : NULL;
13764 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13765 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13766 : NULL;
13767 }
13768 else
13769 {
13770 out_attr[Tag_CPU_name].s = NULL;
13771 out_attr[Tag_CPU_raw_name].s = NULL;
13772 }
13773
13774 /* If we still don't have a value for Tag_CPU_name,
13775 make one up now. Tag_CPU_raw_name remains blank. */
13776 if (out_attr[Tag_CPU_name].s == NULL
13777 && out_attr[i].i < ARRAY_SIZE (name_table))
13778 out_attr[Tag_CPU_name].s =
13779 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13780 }
13781 break;
13782
ee065d83
PB		 13783 case Tag_ARM_ISA_use:
13784 case Tag_THUMB_ISA_use:
ee065d83 13785 case Tag_WMMX_arch:
91e22acd
AS		 13786 case Tag_Advanced_SIMD_arch:
13787 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13788 case Tag_ABI_FP_rounding:
ee065d83
PB		 13789 case Tag_ABI_FP_exceptions:
13790 case Tag_ABI_FP_user_exceptions:
13791 case Tag_ABI_FP_number_model:
75375b3e 13792 case Tag_FP_HP_extension:
91e22acd
AS		 13793 case Tag_CPU_unaligned_access:
13794 case Tag_T2EE_use:
91e22acd 13795 case Tag_MPextension_use:
ee065d83
PB		 13796 /* Use the largest value specified. */
13797 if (in_attr[i].i > out_attr[i].i)
13798 out_attr[i].i = in_attr[i].i;
13799 break;
13800
75375b3e 13801 case Tag_ABI_align_preserved:
91e22acd
AS		 13802 case Tag_ABI_PCS_RO_data:
13803 /* Use the smallest value specified. */
13804 if (in_attr[i].i < out_attr[i].i)
13805 out_attr[i].i = in_attr[i].i;
13806 break;
13807
75375b3e 13808 case Tag_ABI_align_needed:
91e22acd 13809 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13810 && (in_attr[Tag_ABI_align_preserved].i == 0
13811 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13812 {
91e22acd
AS		 13813 /* This error message should be enabled once all non-conformant
13814 binaries in the toolchain have had the attributes set
13815 properly.
ee065d83 13816 _bfd_error_handler
871b3ab2 13817 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 13818 obfd, ibfd);
13819 result = FALSE; */
ee065d83 13820 }
91e22acd
AS		 13821 /* Fall through. */
13822 case Tag_ABI_FP_denormal:
13823 case Tag_ABI_PCS_GOT_use:
13824 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13825 value if greater than 2 (for future-proofing). */
13826 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13827 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13828 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13829 out_attr[i].i = in_attr[i].i;
13830 break;
91e22acd 13831
75375b3e
MGD		 13832 case Tag_Virtualization_use:
13833 /* The virtualization tag effectively stores two bits of
13834 information: the intended use of TrustZone (in bit 0), and the
13835 intended use of Virtualization (in bit 1). */
13836 if (out_attr[i].i == 0)
13837 out_attr[i].i = in_attr[i].i;
13838 else if (in_attr[i].i != 0
13839 && in_attr[i].i != out_attr[i].i)
13840 {
13841 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13842 out_attr[i].i = 3;
13843 else
13844 {
13845 _bfd_error_handler
871b3ab2
AM		 13846 (_("error: %pB: unable to merge virtualization attributes "
13847 "with %pB"),
75375b3e
MGD		 13848 obfd, ibfd);
13849 result = FALSE;
13850 }
13851 }
13852 break;
91e22acd
AS		 13853
13854 case Tag_CPU_arch_profile:
13855 if (out_attr[i].i != in_attr[i].i)
13856 {
13857 /* 0 will merge with anything.
13858 'A' and 'S' merge to 'A'.
13859 'R' and 'S' merge to 'R'.
99059e56 13860 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13861 if (out_attr[i].i == 0
13862 || (out_attr[i].i == 'S'
13863 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13864 out_attr[i].i = in_attr[i].i;
13865 else if (in_attr[i].i == 0
13866 || (in_attr[i].i == 'S'
13867 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13868 ; /* Do nothing. */
91e22acd
AS		 13869 else
13870 {
13871 _bfd_error_handler
90b6238f 13872 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 13873 ibfd,
13874 in_attr[i].i ? in_attr[i].i : '0',
13875 out_attr[i].i ? out_attr[i].i : '0');
13876 result = FALSE;
13877 }
13878 }
13879 break;
15afaa63
TP		 13880
13881 case Tag_DSP_extension:
13882 /* No need to change output value if any of:
13883 - pre (<=) ARMv5T input architecture (do not have DSP)
13884 - M input profile not ARMv7E-M and do not have DSP. */
13885 if (in_attr[Tag_CPU_arch].i <= 3
13886 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13887 && in_attr[Tag_CPU_arch].i != 13
13888 && in_attr[i].i == 0))
13889 ; /* Do nothing. */
13890 /* Output value should be 0 if DSP part of architecture, ie.
13891 - post (>=) ARMv5te architecture output
13892 - A, R or S profile output or ARMv7E-M output architecture. */
13893 else if (out_attr[Tag_CPU_arch].i >= 4
13894 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13895 || out_attr[Tag_CPU_arch_profile].i == 'R'
13896 || out_attr[Tag_CPU_arch_profile].i == 'S'
13897 || out_attr[Tag_CPU_arch].i == 13))
13898 out_attr[i].i = 0;
13899 /* Otherwise, DSP instructions are added and not part of output
13900 architecture. */
13901 else
13902 out_attr[i].i = 1;
13903 break;
13904
75375b3e 13905 case Tag_FP_arch:
62f3b8c8 13906 {
4547cb56
NC		 13907 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13908 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13909 when it's 0. It might mean absence of FP hardware if
99654aaf 13910 Tag_FP_arch is zero. */
4547cb56 13911
a715796b 13912#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13913 static const struct
13914 {
13915 int ver;
13916 int regs;
bca38921 13917 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13918 {
13919 {0, 0},
13920 {1, 16},
13921 {2, 16},
13922 {3, 32},
13923 {3, 16},
13924 {4, 32},
bca38921 13925 {4, 16},
a715796b
TG		 13926 {8, 32},
13927 {8, 16}
62f3b8c8
PB		 13928 };
13929 int ver;
13930 int regs;
13931 int newval;
13932
4547cb56
NC		 13933 /* If the output has no requirement about FP hardware,
13934 follow the requirement of the input. */
13935 if (out_attr[i].i == 0)
13936 {
4ec192e6
RE		 13937 /* This assert is still reasonable, we shouldn't
13938 produce the suspicious build attribute
13939 combination (See below for in_attr). */
4547cb56
NC		 13940 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13941 out_attr[i].i = in_attr[i].i;
13942 out_attr[Tag_ABI_HardFP_use].i
13943 = in_attr[Tag_ABI_HardFP_use].i;
13944 break;
13945 }
13946 /* If the input has no requirement about FP hardware, do
13947 nothing. */
13948 else if (in_attr[i].i == 0)
13949 {
4ec192e6
RE		 13950 /* We used to assert that Tag_ABI_HardFP_use was
13951 zero here, but we should never assert when
13952 consuming an object file that has suspicious
13953 build attributes. The single precision variant
13954 of 'no FP architecture' is still 'no FP
13955 architecture', so we just ignore the tag in this
13956 case. */
4547cb56
NC		 13957 break;
13958 }
13959
13960 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13961 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13962
13963 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13964 do nothing. */
13965 if (in_attr[Tag_ABI_HardFP_use].i == 0
13966 && out_attr[Tag_ABI_HardFP_use].i == 0)
13967 ;
13968 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13969 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13970 else if (in_attr[Tag_ABI_HardFP_use].i
13971 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13972 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13973
13974 /* Now we can handle Tag_FP_arch. */
13975
bca38921
MGD		 13976 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13977 pick the biggest. */
13978 if (in_attr[i].i >= VFP_VERSION_COUNT
13979 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13980 {
13981 out_attr[i] = in_attr[i];
13982 break;
13983 }
13984 /* The output uses the superset of input features
13985 (ISA version) and registers. */
13986 ver = vfp_versions[in_attr[i].i].ver;
13987 if (ver < vfp_versions[out_attr[i].i].ver)
13988 ver = vfp_versions[out_attr[i].i].ver;
13989 regs = vfp_versions[in_attr[i].i].regs;
13990 if (regs < vfp_versions[out_attr[i].i].regs)
13991 regs = vfp_versions[out_attr[i].i].regs;
13992 /* This assumes all possible supersets are also a valid
99059e56 13993 options. */
bca38921 13994 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13995 {
13996 if (regs == vfp_versions[newval].regs
13997 && ver == vfp_versions[newval].ver)
13998 break;
13999 }
14000 out_attr[i].i = newval;
14001 }
b1cc4aeb 14002 break;
ee065d83
PB		 14003 case Tag_PCS_config:
14004 if (out_attr[i].i == 0)
14005 out_attr[i].i = in_attr[i].i;
b6009aca 14006 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14007 {
14008 /* It's sometimes ok to mix different configs, so this is only
99059e56 14009 a warning. */
ee065d83 14010 _bfd_error_handler
90b6238f 14011 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14012 }
14013 break;
14014 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14015 if (in_attr[i].i != out_attr[i].i
14016 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14017 && in_attr[i].i != AEABI_R9_unused)
14018 {
14019 _bfd_error_handler
90b6238f 14020 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14021 result = FALSE;
ee065d83
PB		 14022 }
14023 if (out_attr[i].i == AEABI_R9_unused)
14024 out_attr[i].i = in_attr[i].i;
14025 break;
14026 case Tag_ABI_PCS_RW_data:
14027 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14028 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14029 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14030 {
14031 _bfd_error_handler
871b3ab2 14032 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14033 ibfd);
91e22acd 14034 result = FALSE;
ee065d83
PB		 14035 }
14036 /* Use the smallest value specified. */
14037 if (in_attr[i].i < out_attr[i].i)
14038 out_attr[i].i = in_attr[i].i;
14039 break;
ee065d83 14040 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14041 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14042 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14043 {
14044 _bfd_error_handler
871b3ab2 14045 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14046 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14047 }
a9dc9481 14048 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14049 out_attr[i].i = in_attr[i].i;
14050 break;
ee065d83
PB		 14051 case Tag_ABI_enum_size:
14052 if (in_attr[i].i != AEABI_enum_unused)
14053 {
14054 if (out_attr[i].i == AEABI_enum_unused
14055 || out_attr[i].i == AEABI_enum_forced_wide)
14056 {
14057 /* The existing object is compatible with anything.
14058 Use whatever requirements the new object has. */
14059 out_attr[i].i = in_attr[i].i;
14060 }
14061 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14062 && out_attr[i].i != in_attr[i].i
0ffa91dd 14063 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14064 {
91e22acd 14065 static const char *aeabi_enum_names[] =
bf21ed78 14066 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14067 const char *in_name =
14068 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14069 ? aeabi_enum_names[in_attr[i].i]
14070 : "<unknown>";
14071 const char *out_name =
14072 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14073 ? aeabi_enum_names[out_attr[i].i]
14074 : "<unknown>";
ee065d83 14075 _bfd_error_handler
871b3ab2 14076 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14077 ibfd, in_name, out_name);
ee065d83
PB		 14078 }
14079 }
14080 break;
14081 case Tag_ABI_VFP_args:
14082 /* Aready done. */
14083 break;
14084 case Tag_ABI_WMMX_args:
14085 if (in_attr[i].i != out_attr[i].i)
14086 {
14087 _bfd_error_handler
871b3ab2 14088 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14089 ibfd, obfd);
91e22acd 14090 result = FALSE;
ee065d83
PB		 14091 }
14092 break;
7b86a9fa
AS		 14093 case Tag_compatibility:
14094 /* Merged in target-independent code. */
14095 break;
91e22acd 14096 case Tag_ABI_HardFP_use:
4547cb56 14097 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14098 break;
14099 case Tag_ABI_FP_16bit_format:
14100 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14101 {
14102 if (in_attr[i].i != out_attr[i].i)
14103 {
14104 _bfd_error_handler
871b3ab2 14105 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14106 ibfd, obfd);
14107 result = FALSE;
14108 }
14109 }
14110 if (in_attr[i].i != 0)
14111 out_attr[i].i = in_attr[i].i;
14112 break;
7b86a9fa 14113
cd21e546 14114 case Tag_DIV_use:
ac56ee8f
MGD		 14115 /* A value of zero on input means that the divide instruction may
14116 be used if available in the base architecture as specified via
14117 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14118 the user did not want divide instructions. A value of 2
14119 explicitly means that divide instructions were allowed in ARM
14120 and Thumb state. */
14121 if (in_attr[i].i == out_attr[i].i)
14122 /* Do nothing. */ ;
14123 else if (elf32_arm_attributes_forbid_div (in_attr)
14124 && !elf32_arm_attributes_accept_div (out_attr))
14125 out_attr[i].i = 1;
14126 else if (elf32_arm_attributes_forbid_div (out_attr)
14127 && elf32_arm_attributes_accept_div (in_attr))
14128 out_attr[i].i = in_attr[i].i;
14129 else if (in_attr[i].i == 2)
14130 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14131 break;
14132
14133 case Tag_MPextension_use_legacy:
14134 /* We don't output objects with Tag_MPextension_use_legacy - we
14135 move the value to Tag_MPextension_use. */
14136 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14137 {
14138 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14139 {
14140 _bfd_error_handler
871b3ab2 14141 (_("%pB has both the current and legacy "
b38cadfb 14142 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14143 ibfd);
14144 result = FALSE;
14145 }
14146 }
14147
14148 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14149 out_attr[Tag_MPextension_use] = in_attr[i];
14150
14151 break;
14152
91e22acd 14153 case Tag_nodefaults:
2d0bb761
AS		 14154 /* This tag is set if it exists, but the value is unused (and is
14155 typically zero). We don't actually need to do anything here -
14156 the merge happens automatically when the type flags are merged
14157 below. */
91e22acd
AS		 14158 break;
14159 case Tag_also_compatible_with:
14160 /* Already done in Tag_CPU_arch. */
14161 break;
14162 case Tag_conformance:
14163 /* Keep the attribute if it matches. Throw it away otherwise.
14164 No attribute means no claim to conform. */
14165 if (!in_attr[i].s || !out_attr[i].s
14166 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14167 out_attr[i].s = NULL;
14168 break;
3cfad14c 14169
91e22acd 14170 default:
e8b36cd1
JM		 14171 result
14172 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14173 }
14174
14175 /* If out_attr was copied from in_attr then it won't have a type yet. */
14176 if (in_attr[i].type && !out_attr[i].type)
14177 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14178 }
14179
104d59d1 14180 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14181 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14182 return FALSE;
ee065d83 14183
104d59d1 14184 /* Check for any attributes not known on ARM. */
e8b36cd1 14185 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14186
91e22acd 14187 return result;
252b5132
RH		 14188}
14189
3a4a14e9
PB		 14190
14191/* Return TRUE if the two EABI versions are incompatible. */
14192
14193static bfd_boolean
14194elf32_arm_versions_compatible (unsigned iver, unsigned over)
14195{
14196 /* v4 and v5 are the same spec before and after it was released,
14197 so allow mixing them. */
14198 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14199 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14200 return TRUE;
14201
14202 return (iver == over);
14203}
14204
252b5132
RH		 14205/* Merge backend specific data from an object file to the output
14206 object file when linking. */
9b485d32 14207
b34976b6 14208static bfd_boolean
50e03d47 14209elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14210
9b485d32
NC		 14211/* Display the flags field. */
14212
b34976b6 14213static bfd_boolean
57e8b36a 14214elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14215{
fc830a83
NC		 14216 FILE * file = (FILE *) ptr;
14217 unsigned long flags;
252b5132
RH		 14218
14219 BFD_ASSERT (abfd != NULL && ptr != NULL);
14220
14221 /* Print normal ELF private data. */
14222 _bfd_elf_print_private_bfd_data (abfd, ptr);
14223
fc830a83 14224 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14225 /* Ignore init flag - it may not be set, despite the flags field
14226 containing valid data. */
252b5132 14227
9b485d32 14228 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14229
fc830a83
NC		 14230 switch (EF_ARM_EABI_VERSION (flags))
14231 {
14232 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14233 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14234 official ARM ELF extended ABI. Hence they are only decoded if
14235 the EABI version is not set. */
fd2ec330 14236 if (flags & EF_ARM_INTERWORK)
9b485d32 14237 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14238
fd2ec330 14239 if (flags & EF_ARM_APCS_26)
6c571f00 14240 fprintf (file, " [APCS-26]");
fc830a83 14241 else
6c571f00 14242 fprintf (file, " [APCS-32]");
9a5aca8c 14243
96a846ea
RE		 14244 if (flags & EF_ARM_VFP_FLOAT)
14245 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14246 else if (flags & EF_ARM_MAVERICK_FLOAT)
14247 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14248 else
14249 fprintf (file, _(" [FPA float format]"));
14250
fd2ec330 14251 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14252 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14253
fd2ec330 14254 if (flags & EF_ARM_PIC)
9b485d32 14255 fprintf (file, _(" [position independent]"));
fc830a83 14256
fd2ec330 14257 if (flags & EF_ARM_NEW_ABI)
9b485d32 14258 fprintf (file, _(" [new ABI]"));
9a5aca8c 14259
fd2ec330 14260 if (flags & EF_ARM_OLD_ABI)
9b485d32 14261 fprintf (file, _(" [old ABI]"));
9a5aca8c 14262
fd2ec330 14263 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14264 fprintf (file, _(" [software FP]"));
9a5aca8c 14265
96a846ea
RE		 14266 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14267 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14268 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14269 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14270 break;
9a5aca8c 14271
fc830a83 14272 case EF_ARM_EABI_VER1:
9b485d32 14273 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14274
fc830a83 14275 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14276 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14277 else
9b485d32 14278 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14279
fc830a83
NC		 14280 flags &= ~ EF_ARM_SYMSARESORTED;
14281 break;
9a5aca8c 14282
fd2ec330
PB		 14283 case EF_ARM_EABI_VER2:
14284 fprintf (file, _(" [Version2 EABI]"));
14285
14286 if (flags & EF_ARM_SYMSARESORTED)
14287 fprintf (file, _(" [sorted symbol table]"));
14288 else
14289 fprintf (file, _(" [unsorted symbol table]"));
14290
14291 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14292 fprintf (file, _(" [dynamic symbols use segment index]"));
14293
14294 if (flags & EF_ARM_MAPSYMSFIRST)
14295 fprintf (file, _(" [mapping symbols precede others]"));
14296
99e4ae17 14297 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14298 | EF_ARM_MAPSYMSFIRST);
14299 break;
14300
d507cf36
PB		 14301 case EF_ARM_EABI_VER3:
14302 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14303 break;
14304
14305 case EF_ARM_EABI_VER4:
14306 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14307 goto eabi;
d507cf36 14308
3a4a14e9
PB		 14309 case EF_ARM_EABI_VER5:
14310 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14311
14312 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14313 fprintf (file, _(" [soft-float ABI]"));
14314
14315 if (flags & EF_ARM_ABI_FLOAT_HARD)
14316 fprintf (file, _(" [hard-float ABI]"));
14317
14318 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14319
3a4a14e9 14320 eabi:
d507cf36
PB		 14321 if (flags & EF_ARM_BE8)
14322 fprintf (file, _(" [BE8]"));
14323
14324 if (flags & EF_ARM_LE8)
14325 fprintf (file, _(" [LE8]"));
14326
14327 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14328 break;
14329
fc830a83 14330 default:
9b485d32 14331 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14332 break;
14333 }
252b5132 14334
fc830a83 14335 flags &= ~ EF_ARM_EABIMASK;
252b5132 14336
fc830a83 14337 if (flags & EF_ARM_RELEXEC)
9b485d32 14338 fprintf (file, _(" [relocatable executable]"));
252b5132 14339
18a20338
CL		 14340 if (flags & EF_ARM_PIC)
14341 fprintf (file, _(" [position independent]"));
14342
14343 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
14344 fprintf (file, _(" [FDPIC ABI supplement]"));
14345
14346 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 14347
14348 if (flags)
9b485d32 14349 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14350
252b5132
RH		 14351 fputc ('\n', file);
14352
b34976b6 14353 return TRUE;
252b5132
RH		 14354}
14355
14356static int
57e8b36a 14357elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14358{
2f0ca46a
NC		 14359 switch (ELF_ST_TYPE (elf_sym->st_info))
14360 {
14361 case STT_ARM_TFUNC:
14362 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14363
2f0ca46a
NC		 14364 case STT_ARM_16BIT:
14365 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14366 This allows us to distinguish between data used by Thumb instructions
14367 and non-data (which is probably code) inside Thumb regions of an
14368 executable. */
1a0eb693 14369 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14370 return ELF_ST_TYPE (elf_sym->st_info);
14371 break;
9a5aca8c 14372
ce855c42
NC		 14373 default:
14374 break;
2f0ca46a
NC		 14375 }
14376
14377 return type;
252b5132 14378}
f21f3fe0 14379
252b5132 14380static asection *
07adf181
AM		 14381elf32_arm_gc_mark_hook (asection *sec,
14382 struct bfd_link_info *info,
14383 Elf_Internal_Rela *rel,
14384 struct elf_link_hash_entry *h,
14385 Elf_Internal_Sym *sym)
252b5132
RH		 14386{
14387 if (h != NULL)
07adf181 14388 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14389 {
14390 case R_ARM_GNU_VTINHERIT:
14391 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14392 return NULL;
14393 }
9ad5cbcf 14394
07adf181 14395 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14396}
14397
780a67af
NC		 14398/* Look through the relocs for a section during the first phase. */
14399
b34976b6 14400static bfd_boolean
57e8b36a
NC		 14401elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14402 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14403{
b34976b6
AM		 14404 Elf_Internal_Shdr *symtab_hdr;
14405 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14406 const Elf_Internal_Rela *rel;
14407 const Elf_Internal_Rela *rel_end;
14408 bfd *dynobj;
5e681ec4 14409 asection *sreloc;
5e681ec4 14410 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14411 bfd_boolean call_reloc_p;
14412 bfd_boolean may_become_dynamic_p;
14413 bfd_boolean may_need_local_target_p;
ce98a316 14414 unsigned long nsyms;
9a5aca8c 14415
0e1862bb 14416 if (bfd_link_relocatable (info))
b34976b6 14417 return TRUE;
9a5aca8c 14418
0ffa91dd
NC		 14419 BFD_ASSERT (is_arm_elf (abfd));
14420
5e681ec4 14421 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14422 if (htab == NULL)
14423 return FALSE;
14424
5e681ec4 14425 sreloc = NULL;
9a5aca8c 14426
67687978
PB		 14427 /* Create dynamic sections for relocatable executables so that we can
14428 copy relocations. */
14429 if (htab->root.is_relocatable_executable
14430 && ! htab->root.dynamic_sections_created)
14431 {
14432 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14433 return FALSE;
14434 }
14435
cbc704f3
RS		 14436 if (htab->root.dynobj == NULL)
14437 htab->root.dynobj = abfd;
34e77a92
RS		 14438 if (!create_ifunc_sections (info))
14439 return FALSE;
cbc704f3
RS		 14440
14441 dynobj = htab->root.dynobj;
14442
0ffa91dd 14443 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14444 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14445 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14446
252b5132
RH		 14447 rel_end = relocs + sec->reloc_count;
14448 for (rel = relocs; rel < rel_end; rel++)
14449 {
34e77a92 14450 Elf_Internal_Sym *isym;
252b5132 14451 struct elf_link_hash_entry *h;
b7693d02 14452 struct elf32_arm_link_hash_entry *eh;
d42c267e 14453 unsigned int r_symndx;
eb043451 14454 int r_type;
9a5aca8c 14455
252b5132 14456 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14457 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14458 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14459
ce98a316
NC		 14460 if (r_symndx >= nsyms
14461 /* PR 9934: It is possible to have relocations that do not
14462 refer to symbols, thus it is also possible to have an
14463 object file containing relocations but no symbol table. */
cf35638d 14464 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14465 {
871b3ab2 14466 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 14467 r_symndx);
ba93b8ac
DJ		 14468 return FALSE;
14469 }
14470
34e77a92
RS		 14471 h = NULL;
14472 isym = NULL;
14473 if (nsyms > 0)
973a3492 14474 {
34e77a92
RS		 14475 if (r_symndx < symtab_hdr->sh_info)
14476 {
14477 /* A local symbol. */
14478 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14479 abfd, r_symndx);
14480 if (isym == NULL)
14481 return FALSE;
14482 }
14483 else
14484 {
14485 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14486 while (h->root.type == bfd_link_hash_indirect
14487 || h->root.type == bfd_link_hash_warning)
14488 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14489 }
973a3492 14490 }
9a5aca8c 14491
b7693d02
DJ		 14492 eh = (struct elf32_arm_link_hash_entry *) h;
14493
f6e32f6d
RS		 14494 call_reloc_p = FALSE;
14495 may_become_dynamic_p = FALSE;
14496 may_need_local_target_p = FALSE;
14497
0855e32b
NS		 14498 /* Could be done earlier, if h were already available. */
14499 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14500 switch (r_type)
99059e56 14501 {
5e681ec4 14502 case R_ARM_GOT32:
eb043451 14503 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14504 case R_ARM_TLS_GD32:
14505 case R_ARM_TLS_IE32:
0855e32b
NS		 14506 case R_ARM_TLS_GOTDESC:
14507 case R_ARM_TLS_DESCSEQ:
14508 case R_ARM_THM_TLS_DESCSEQ:
14509 case R_ARM_TLS_CALL:
14510 case R_ARM_THM_TLS_CALL:
5e681ec4 14511 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14512 {
14513 int tls_type, old_tls_type;
5e681ec4 14514
ba93b8ac
DJ		 14515 switch (r_type)
14516 {
14517 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14518
ba93b8ac 14519 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14520
0855e32b
NS		 14521 case R_ARM_TLS_GOTDESC:
14522 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14523 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14524 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14525
ba93b8ac
DJ		 14526 default: tls_type = GOT_NORMAL; break;
14527 }
252b5132 14528
0e1862bb 14529 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14530 info->flags |= DF_STATIC_TLS;
14531
ba93b8ac
DJ		 14532 if (h != NULL)
14533 {
14534 h->got.refcount++;
14535 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14536 }
14537 else
14538 {
ba93b8ac 14539 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14540 if (!elf32_arm_allocate_local_sym_info (abfd))
14541 return FALSE;
14542 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14543 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14544 }
14545
0855e32b 14546 /* If a variable is accessed with both tls methods, two
99059e56 14547 slots may be created. */
0855e32b
NS		 14548 if (GOT_TLS_GD_ANY_P (old_tls_type)
14549 && GOT_TLS_GD_ANY_P (tls_type))
14550 tls_type |= old_tls_type;
14551
14552 /* We will already have issued an error message if there
14553 is a TLS/non-TLS mismatch, based on the symbol
14554 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14555 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14556 && tls_type != GOT_NORMAL)
14557 tls_type |= old_tls_type;
14558
0855e32b 14559 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14560 method, we're able to relax. Turn off the GDESC flag,
14561 without messing up with any other kind of tls types
6a631e86 14562 that may be involved. */
0855e32b
NS		 14563 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14564 tls_type &= ~GOT_TLS_GDESC;
14565
ba93b8ac
DJ		 14566 if (old_tls_type != tls_type)
14567 {
14568 if (h != NULL)
14569 elf32_arm_hash_entry (h)->tls_type = tls_type;
14570 else
14571 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14572 }
14573 }
8029a119 14574 /* Fall through. */
ba93b8ac
DJ		 14575
14576 case R_ARM_TLS_LDM32:
14577 if (r_type == R_ARM_TLS_LDM32)
14578 htab->tls_ldm_got.refcount++;
8029a119 14579 /* Fall through. */
252b5132 14580
c19d1205 14581 case R_ARM_GOTOFF32:
5e681ec4 14582 case R_ARM_GOTPC:
cbc704f3
RS		 14583 if (htab->root.sgot == NULL
14584 && !create_got_section (htab->root.dynobj, info))
14585 return FALSE;
252b5132
RH		 14586 break;
14587
252b5132 14588 case R_ARM_PC24:
7359ea65 14589 case R_ARM_PLT32:
5b5bb741
PB		 14590 case R_ARM_CALL:
14591 case R_ARM_JUMP24:
eb043451 14592 case R_ARM_PREL31:
c19d1205 14593 case R_ARM_THM_CALL:
bd97cb95
DJ		 14594 case R_ARM_THM_JUMP24:
14595 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14596 call_reloc_p = TRUE;
14597 may_need_local_target_p = TRUE;
14598 break;
14599
14600 case R_ARM_ABS12:
14601 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14602 ldr __GOTT_INDEX__ offsets. */
14603 if (!htab->vxworks_p)
14604 {
14605 may_need_local_target_p = TRUE;
14606 break;
14607 }
aebf9be7 14608 else goto jump_over;
9eaff861 14609
f6e32f6d 14610 /* Fall through. */
39623e12 14611
96c23d59
JM		 14612 case R_ARM_MOVW_ABS_NC:
14613 case R_ARM_MOVT_ABS:
14614 case R_ARM_THM_MOVW_ABS_NC:
14615 case R_ARM_THM_MOVT_ABS:
0e1862bb 14616 if (bfd_link_pic (info))
96c23d59 14617 {
4eca0228 14618 _bfd_error_handler
871b3ab2 14619 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 14620 abfd, elf32_arm_howto_table_1[r_type].name,
14621 (h) ? h->root.root.string : "a local symbol");
14622 bfd_set_error (bfd_error_bad_value);
14623 return FALSE;
14624 }
14625
14626 /* Fall through. */
39623e12
PB		 14627 case R_ARM_ABS32:
14628 case R_ARM_ABS32_NOI:
aebf9be7 14629 jump_over:
0e1862bb 14630 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14631 {
14632 h->pointer_equality_needed = 1;
14633 }
14634 /* Fall through. */
39623e12
PB		 14635 case R_ARM_REL32:
14636 case R_ARM_REL32_NOI:
b6895b4f
PB		 14637 case R_ARM_MOVW_PREL_NC:
14638 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14639 case R_ARM_THM_MOVW_PREL_NC:
14640 case R_ARM_THM_MOVT_PREL:
39623e12 14641
b7693d02 14642 /* Should the interworking branches be listed here? */
0e1862bb 14643 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14644 && (sec->flags & SEC_ALLOC) != 0)
14645 {
14646 if (h == NULL
469a3493 14647 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14648 {
14649 /* In shared libraries and relocatable executables,
14650 we treat local relative references as calls;
14651 see the related SYMBOL_CALLS_LOCAL code in
14652 allocate_dynrelocs. */
14653 call_reloc_p = TRUE;
14654 may_need_local_target_p = TRUE;
14655 }
14656 else
14657 /* We are creating a shared library or relocatable
14658 executable, and this is a reloc against a global symbol,
14659 or a non-PC-relative reloc against a local symbol.
14660 We may need to copy the reloc into the output. */
14661 may_become_dynamic_p = TRUE;
14662 }
f6e32f6d
RS		 14663 else
14664 may_need_local_target_p = TRUE;
252b5132
RH		 14665 break;
14666
99059e56
RM		 14667 /* This relocation describes the C++ object vtable hierarchy.
14668 Reconstruct it for later use during GC. */
14669 case R_ARM_GNU_VTINHERIT:
14670 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14671 return FALSE;
14672 break;
14673
14674 /* This relocation describes which C++ vtable entries are actually
14675 used. Record for later use during GC. */
14676 case R_ARM_GNU_VTENTRY:
14677 BFD_ASSERT (h != NULL);
14678 if (h != NULL
14679 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14680 return FALSE;
14681 break;
14682 }
f6e32f6d
RS		 14683
14684 if (h != NULL)
14685 {
14686 if (call_reloc_p)
14687 /* We may need a .plt entry if the function this reloc
14688 refers to is in a different object, regardless of the
14689 symbol's type. We can't tell for sure yet, because
14690 something later might force the symbol local. */
14691 h->needs_plt = 1;
14692 else if (may_need_local_target_p)
14693 /* If this reloc is in a read-only section, we might
14694 need a copy reloc. We can't check reliably at this
14695 stage whether the section is read-only, as input
14696 sections have not yet been mapped to output sections.
14697 Tentatively set the flag for now, and correct in
14698 adjust_dynamic_symbol. */
14699 h->non_got_ref = 1;
14700 }
14701
34e77a92
RS		 14702 if (may_need_local_target_p
14703 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14704 {
34e77a92
RS		 14705 union gotplt_union *root_plt;
14706 struct arm_plt_info *arm_plt;
14707 struct arm_local_iplt_info *local_iplt;
14708
14709 if (h != NULL)
14710 {
14711 root_plt = &h->plt;
14712 arm_plt = &eh->plt;
14713 }
14714 else
14715 {
14716 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14717 if (local_iplt == NULL)
14718 return FALSE;
14719 root_plt = &local_iplt->root;
14720 arm_plt = &local_iplt->arm;
14721 }
14722
f6e32f6d
RS		 14723 /* If the symbol is a function that doesn't bind locally,
14724 this relocation will need a PLT entry. */
a8c887dd
NC		 14725 if (root_plt->refcount != -1)
14726 root_plt->refcount += 1;
34e77a92
RS		 14727
14728 if (!call_reloc_p)
14729 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14730
14731 /* It's too early to use htab->use_blx here, so we have to
14732 record possible blx references separately from
14733 relocs that definitely need a thumb stub. */
14734
14735 if (r_type == R_ARM_THM_CALL)
34e77a92 14736 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14737
14738 if (r_type == R_ARM_THM_JUMP24
14739 || r_type == R_ARM_THM_JUMP19)
34e77a92 14740 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14741 }
14742
14743 if (may_become_dynamic_p)
14744 {
14745 struct elf_dyn_relocs *p, **head;
14746
14747 /* Create a reloc section in dynobj. */
14748 if (sreloc == NULL)
14749 {
14750 sreloc = _bfd_elf_make_dynamic_reloc_section
14751 (sec, dynobj, 2, abfd, ! htab->use_rel);
14752
14753 if (sreloc == NULL)
14754 return FALSE;
14755
14756 /* BPABI objects never have dynamic relocations mapped. */
14757 if (htab->symbian_p)
14758 {
14759 flagword flags;
14760
14761 flags = bfd_get_section_flags (dynobj, sreloc);
14762 flags &= ~(SEC_LOAD | SEC_ALLOC);
14763 bfd_set_section_flags (dynobj, sreloc, flags);
14764 }
14765 }
14766
14767 /* If this is a global symbol, count the number of
14768 relocations we need for this symbol. */
14769 if (h != NULL)
14770 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14771 else
14772 {
34e77a92
RS		 14773 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14774 if (head == NULL)
f6e32f6d 14775 return FALSE;
f6e32f6d
RS		 14776 }
14777
14778 p = *head;
14779 if (p == NULL || p->sec != sec)
14780 {
14781 bfd_size_type amt = sizeof *p;
14782
14783 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14784 if (p == NULL)
14785 return FALSE;
14786 p->next = *head;
14787 *head = p;
14788 p->sec = sec;
14789 p->count = 0;
14790 p->pc_count = 0;
14791 }
14792
469a3493 14793 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14794 p->pc_count += 1;
14795 p->count += 1;
14796 }
252b5132 14797 }
f21f3fe0 14798
b34976b6 14799 return TRUE;
252b5132
RH		 14800}
14801
9eaff861
AO		 14802static void
14803elf32_arm_update_relocs (asection *o,
14804 struct bfd_elf_section_reloc_data *reldata)
14805{
14806 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14807 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14808 const struct elf_backend_data *bed;
14809 _arm_elf_section_data *eado;
14810 struct bfd_link_order *p;
14811 bfd_byte *erela_head, *erela;
14812 Elf_Internal_Rela *irela_head, *irela;
14813 Elf_Internal_Shdr *rel_hdr;
14814 bfd *abfd;
14815 unsigned int count;
14816
14817 eado = get_arm_elf_section_data (o);
14818
14819 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14820 return;
14821
14822 abfd = o->owner;
14823 bed = get_elf_backend_data (abfd);
14824 rel_hdr = reldata->hdr;
14825
14826 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14827 {
14828 swap_in = bed->s->swap_reloc_in;
14829 swap_out = bed->s->swap_reloc_out;
14830 }
14831 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14832 {
14833 swap_in = bed->s->swap_reloca_in;
14834 swap_out = bed->s->swap_reloca_out;
14835 }
14836 else
14837 abort ();
14838
14839 erela_head = rel_hdr->contents;
14840 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14841 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14842
14843 erela = erela_head;
14844 irela = irela_head;
14845 count = 0;
14846
14847 for (p = o->map_head.link_order; p; p = p->next)
14848 {
14849 if (p->type == bfd_section_reloc_link_order
14850 || p->type == bfd_symbol_reloc_link_order)
14851 {
14852 (*swap_in) (abfd, erela, irela);
14853 erela += rel_hdr->sh_entsize;
14854 irela++;
14855 count++;
14856 }
14857 else if (p->type == bfd_indirect_link_order)
14858 {
14859 struct bfd_elf_section_reloc_data *input_reldata;
14860 arm_unwind_table_edit *edit_list, *edit_tail;
14861 _arm_elf_section_data *eadi;
14862 bfd_size_type j;
14863 bfd_vma offset;
14864 asection *i;
14865
14866 i = p->u.indirect.section;
14867
14868 eadi = get_arm_elf_section_data (i);
14869 edit_list = eadi->u.exidx.unwind_edit_list;
14870 edit_tail = eadi->u.exidx.unwind_edit_tail;
14871 offset = o->vma + i->output_offset;
14872
14873 if (eadi->elf.rel.hdr &&
14874 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14875 input_reldata = &eadi->elf.rel;
14876 else if (eadi->elf.rela.hdr &&
14877 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14878 input_reldata = &eadi->elf.rela;
14879 else
14880 abort ();
14881
14882 if (edit_list)
14883 {
14884 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14885 {
14886 arm_unwind_table_edit *edit_node, *edit_next;
14887 bfd_vma bias;
c48182bf 14888 bfd_vma reloc_index;
9eaff861
AO		 14889
14890 (*swap_in) (abfd, erela, irela);
c48182bf 14891 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 14892
14893 bias = 0;
14894 edit_node = edit_list;
14895 for (edit_next = edit_list;
c48182bf 14896 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 14897 edit_next = edit_node->next)
14898 {
14899 bias++;
14900 edit_node = edit_next;
14901 }
14902
14903 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 14904 || edit_node->index != reloc_index)
9eaff861
AO		 14905 {
14906 irela->r_offset -= bias * 8;
14907 irela++;
14908 count++;
14909 }
14910
14911 erela += rel_hdr->sh_entsize;
14912 }
14913
14914 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
14915 {
14916 /* New relocation entity. */
14917 asection *text_sec = edit_tail->linked_section;
14918 asection *text_out = text_sec->output_section;
14919 bfd_vma exidx_offset = offset + i->size - 8;
14920
14921 irela->r_addend = 0;
14922 irela->r_offset = exidx_offset;
14923 irela->r_info = ELF32_R_INFO
14924 (text_out->target_index, R_ARM_PREL31);
14925 irela++;
14926 count++;
14927 }
14928 }
14929 else
14930 {
14931 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14932 {
14933 (*swap_in) (abfd, erela, irela);
14934 erela += rel_hdr->sh_entsize;
14935 irela++;
14936 }
14937
14938 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
14939 }
14940 }
14941 }
14942
14943 reldata->count = count;
14944 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
14945
14946 erela = erela_head;
14947 irela = irela_head;
14948 while (count > 0)
14949 {
14950 (*swap_out) (abfd, irela, erela);
14951 erela += rel_hdr->sh_entsize;
14952 irela++;
14953 count--;
14954 }
14955
14956 free (irela_head);
14957
14958 /* Hashes are no longer valid. */
14959 free (reldata->hashes);
14960 reldata->hashes = NULL;
14961}
14962
6a5bb875 14963/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 14964 required if the corresponding code section is marked. Similarly, ARMv8-M
14965 secure entry functions can only be referenced by SG veneers which are
14966 created after the GC process. They need to be marked in case they reside in
14967 their own section (as would be the case if code was compiled with
14968 -ffunction-sections). */
6a5bb875
PB		 14969
14970static bfd_boolean
906e58ca
NC		 14971elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
14972 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 14973{
14974 bfd *sub;
14975 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 14976 asection *cmse_sec;
14977 obj_attribute *out_attr;
14978 Elf_Internal_Shdr *symtab_hdr;
14979 unsigned i, sym_count, ext_start;
14980 const struct elf_backend_data *bed;
14981 struct elf_link_hash_entry **sym_hashes;
14982 struct elf32_arm_link_hash_entry *cmse_hash;
14983 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 14984
7f6ab9f8
AM		 14985 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
14986
4ba2ef8f
TP		 14987 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
14988 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
14989 && out_attr[Tag_CPU_arch_profile].i == 'M';
14990
6a5bb875
PB		 14991 /* Marking EH data may cause additional code sections to be marked,
14992 requiring multiple passes. */
14993 again = TRUE;
14994 while (again)
14995 {
14996 again = FALSE;
c72f2fb2 14997 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 14998 {
14999 asection *o;
15000
0ffa91dd 15001 if (! is_arm_elf (sub))
6a5bb875
PB		 15002 continue;
15003
15004 elf_shdrp = elf_elfsections (sub);
15005 for (o = sub->sections; o != NULL; o = o->next)
15006 {
15007 Elf_Internal_Shdr *hdr;
0ffa91dd 15008
6a5bb875 15009 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15010 if (hdr->sh_type == SHT_ARM_EXIDX
15011 && hdr->sh_link
15012 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15013 && !o->gc_mark
15014 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15015 {
15016 again = TRUE;
15017 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15018 return FALSE;
15019 }
15020 }
4ba2ef8f
TP		 15021
15022 /* Mark section holding ARMv8-M secure entry functions. We mark all
15023 of them so no need for a second browsing. */
15024 if (is_v8m && first_bfd_browse)
15025 {
15026 sym_hashes = elf_sym_hashes (sub);
15027 bed = get_elf_backend_data (sub);
15028 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15029 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15030 ext_start = symtab_hdr->sh_info;
15031
15032 /* Scan symbols. */
15033 for (i = ext_start; i < sym_count; i++)
15034 {
15035 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15036
15037 /* Assume it is a special symbol. If not, cmse_scan will
15038 warn about it and user can do something about it. */
15039 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15040 {
15041 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15042 if (!cmse_sec->gc_mark
15043 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15044 return FALSE;
15045 }
15046 }
15047 }
6a5bb875 15048 }
4ba2ef8f 15049 first_bfd_browse = FALSE;
6a5bb875
PB		 15050 }
15051
15052 return TRUE;
15053}
15054
3c9458e9
NC		 15055/* Treat mapping symbols as special target symbols. */
15056
15057static bfd_boolean
15058elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15059{
b0796911
PB		 15060 return bfd_is_arm_special_symbol_name (sym->name,
15061 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15062}
15063
0367ecfb
NC		 15064/* This is a copy of elf_find_function() from elf.c except that
15065 ARM mapping symbols are ignored when looking for function names
15066 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15067
0367ecfb 15068static bfd_boolean
07d6d2b8 15069arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15070 asymbol ** symbols,
fb167eb2 15071 asection * section,
07d6d2b8 15072 bfd_vma offset,
0367ecfb
NC		 15073 const char ** filename_ptr,
15074 const char ** functionname_ptr)
15075{
15076 const char * filename = NULL;
15077 asymbol * func = NULL;
15078 bfd_vma low_func = 0;
15079 asymbol ** p;
252b5132
RH		 15080
15081 for (p = symbols; *p != NULL; p++)
15082 {
15083 elf_symbol_type *q;
15084
15085 q = (elf_symbol_type *) *p;
15086
252b5132
RH		 15087 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15088 {
15089 default:
15090 break;
15091 case STT_FILE:
15092 filename = bfd_asymbol_name (&q->symbol);
15093 break;
252b5132
RH		 15094 case STT_FUNC:
15095 case STT_ARM_TFUNC:
9d2da7ca 15096 case STT_NOTYPE:
b0796911 15097 /* Skip mapping symbols. */
0367ecfb 15098 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15099 && bfd_is_arm_special_symbol_name (q->symbol.name,
15100 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15101 continue;
15102 /* Fall through. */
6b40fcba 15103 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15104 && q->symbol.value >= low_func
15105 && q->symbol.value <= offset)
15106 {
15107 func = (asymbol *) q;
15108 low_func = q->symbol.value;
15109 }
15110 break;
15111 }
15112 }
15113
15114 if (func == NULL)
b34976b6 15115 return FALSE;
252b5132 15116
0367ecfb
NC		 15117 if (filename_ptr)
15118 *filename_ptr = filename;
15119 if (functionname_ptr)
15120 *functionname_ptr = bfd_asymbol_name (func);
15121
15122 return TRUE;
906e58ca 15123}
0367ecfb
NC		 15124
15125
15126/* Find the nearest line to a particular section and offset, for error
15127 reporting. This code is a duplicate of the code in elf.c, except
15128 that it uses arm_elf_find_function. */
15129
15130static bfd_boolean
07d6d2b8
AM		 15131elf32_arm_find_nearest_line (bfd * abfd,
15132 asymbol ** symbols,
15133 asection * section,
15134 bfd_vma offset,
0367ecfb
NC		 15135 const char ** filename_ptr,
15136 const char ** functionname_ptr,
fb167eb2
AM		 15137 unsigned int * line_ptr,
15138 unsigned int * discriminator_ptr)
0367ecfb
NC		 15139{
15140 bfd_boolean found = FALSE;
15141
fb167eb2 15142 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15143 filename_ptr, functionname_ptr,
fb167eb2
AM		 15144 line_ptr, discriminator_ptr,
15145 dwarf_debug_sections, 0,
0367ecfb
NC		 15146 & elf_tdata (abfd)->dwarf2_find_line_info))
15147 {
15148 if (!*functionname_ptr)
fb167eb2 15149 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15150 *filename_ptr ? NULL : filename_ptr,
15151 functionname_ptr);
f21f3fe0 15152
0367ecfb
NC		 15153 return TRUE;
15154 }
15155
fb167eb2
AM		 15156 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15157 uses DWARF1. */
15158
0367ecfb
NC		 15159 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15160 & found, filename_ptr,
15161 functionname_ptr, line_ptr,
15162 & elf_tdata (abfd)->line_info))
15163 return FALSE;
15164
15165 if (found && (*functionname_ptr || *line_ptr))
15166 return TRUE;
15167
15168 if (symbols == NULL)
15169 return FALSE;
15170
fb167eb2 15171 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15172 filename_ptr, functionname_ptr))
15173 return FALSE;
15174
15175 *line_ptr = 0;
b34976b6 15176 return TRUE;
252b5132
RH		 15177}
15178
4ab527b0 15179static bfd_boolean
07d6d2b8 15180elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 15181 const char ** filename_ptr,
15182 const char ** functionname_ptr,
15183 unsigned int * line_ptr)
15184{
15185 bfd_boolean found;
15186 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15187 functionname_ptr, line_ptr,
15188 & elf_tdata (abfd)->dwarf2_find_line_info);
15189 return found;
15190}
15191
63c1f59d
AM		 15192/* Find dynamic relocs for H that apply to read-only sections. */
15193
15194static asection *
15195readonly_dynrelocs (struct elf_link_hash_entry *h)
15196{
15197 struct elf_dyn_relocs *p;
15198
15199 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
15200 {
15201 asection *s = p->sec->output_section;
15202
15203 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15204 return p->sec;
15205 }
15206 return NULL;
15207}
15208
252b5132
RH		 15209/* Adjust a symbol defined by a dynamic object and referenced by a
15210 regular object. The current definition is in some section of the
15211 dynamic object, but we're not including those sections. We have to
15212 change the definition to something the rest of the link can
15213 understand. */
15214
b34976b6 15215static bfd_boolean
57e8b36a
NC		 15216elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15217 struct elf_link_hash_entry * h)
252b5132
RH		 15218{
15219 bfd * dynobj;
5474d94f 15220 asection *s, *srel;
b7693d02 15221 struct elf32_arm_link_hash_entry * eh;
67687978 15222 struct elf32_arm_link_hash_table *globals;
252b5132 15223
67687978 15224 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15225 if (globals == NULL)
15226 return FALSE;
15227
252b5132
RH		 15228 dynobj = elf_hash_table (info)->dynobj;
15229
15230 /* Make sure we know what is going on here. */
15231 BFD_ASSERT (dynobj != NULL
f5385ebf 15232 && (h->needs_plt
34e77a92 15233 || h->type == STT_GNU_IFUNC
60d67dc8 15234 || h->is_weakalias
f5385ebf
AM		 15235 || (h->def_dynamic
15236 && h->ref_regular
15237 && !h->def_regular)));
252b5132 15238
b7693d02
DJ		 15239 eh = (struct elf32_arm_link_hash_entry *) h;
15240
252b5132
RH		 15241 /* If this is a function, put it in the procedure linkage table. We
15242 will fill in the contents of the procedure linkage table later,
15243 when we know the address of the .got section. */
34e77a92 15244 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15245 {
34e77a92
RS		 15246 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15247 symbol binds locally. */
5e681ec4 15248 if (h->plt.refcount <= 0
34e77a92
RS		 15249 || (h->type != STT_GNU_IFUNC
15250 && (SYMBOL_CALLS_LOCAL (info, h)
15251 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15252 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15253 {
15254 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15255 file, but the symbol was never referred to by a dynamic
15256 object, or if all references were garbage collected. In
15257 such a case, we don't actually need to build a procedure
15258 linkage table, and we can just do a PC24 reloc instead. */
15259 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15260 eh->plt.thumb_refcount = 0;
15261 eh->plt.maybe_thumb_refcount = 0;
15262 eh->plt.noncall_refcount = 0;
f5385ebf 15263 h->needs_plt = 0;
252b5132
RH		 15264 }
15265
b34976b6 15266 return TRUE;
252b5132 15267 }
5e681ec4 15268 else
b7693d02
DJ		 15269 {
15270 /* It's possible that we incorrectly decided a .plt reloc was
15271 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15272 in check_relocs. We can't decide accurately between function
15273 and non-function syms in check-relocs; Objects loaded later in
15274 the link may change h->type. So fix it now. */
15275 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15276 eh->plt.thumb_refcount = 0;
15277 eh->plt.maybe_thumb_refcount = 0;
15278 eh->plt.noncall_refcount = 0;
b7693d02 15279 }
252b5132
RH		 15280
15281 /* If this is a weak symbol, and there is a real definition, the
15282 processor independent code will have arranged for us to see the
15283 real definition first, and we can just use the same value. */
60d67dc8 15284 if (h->is_weakalias)
252b5132 15285 {
60d67dc8
AM		 15286 struct elf_link_hash_entry *def = weakdef (h);
15287 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
15288 h->root.u.def.section = def->root.u.def.section;
15289 h->root.u.def.value = def->root.u.def.value;
b34976b6 15290 return TRUE;
252b5132
RH		 15291 }
15292
ba93b8ac
DJ		 15293 /* If there are no non-GOT references, we do not need a copy
15294 relocation. */
15295 if (!h->non_got_ref)
15296 return TRUE;
15297
252b5132
RH		 15298 /* This is a reference to a symbol defined by a dynamic object which
15299 is not a function. */
15300
15301 /* If we are creating a shared library, we must presume that the
15302 only references to the symbol are via the global offset table.
15303 For such cases we need not do anything here; the relocations will
67687978
PB		 15304 be handled correctly by relocate_section. Relocatable executables
15305 can reference data in shared objects directly, so we don't need to
15306 do anything here. */
0e1862bb 15307 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15308 return TRUE;
252b5132
RH		 15309
15310 /* We must allocate the symbol in our .dynbss section, which will
15311 become part of the .bss section of the executable. There will be
15312 an entry for this symbol in the .dynsym section. The dynamic
15313 object will contain position independent code, so all references
15314 from the dynamic object to this symbol will go through the global
15315 offset table. The dynamic linker will use the .dynsym entry to
15316 determine the address it must put in the global offset table, so
15317 both the dynamic object and the regular object will refer to the
15318 same memory location for the variable. */
5522f910
NC		 15319 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15320 linker to copy the initial value out of the dynamic object and into
15321 the runtime process image. We need to remember the offset into the
00a97672 15322 .rel(a).bss section we are going to use. */
5474d94f
AM		 15323 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
15324 {
15325 s = globals->root.sdynrelro;
15326 srel = globals->root.sreldynrelro;
15327 }
15328 else
15329 {
15330 s = globals->root.sdynbss;
15331 srel = globals->root.srelbss;
15332 }
5522f910
NC		 15333 if (info->nocopyreloc == 0
15334 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15335 && h->size != 0)
252b5132 15336 {
47beaa6a 15337 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15338 h->needs_copy = 1;
252b5132
RH		 15339 }
15340
6cabe1ea 15341 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15342}
15343
5e681ec4
PB		 15344/* Allocate space in .plt, .got and associated reloc sections for
15345 dynamic relocs. */
15346
15347static bfd_boolean
47beaa6a 15348allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15349{
15350 struct bfd_link_info *info;
15351 struct elf32_arm_link_hash_table *htab;
15352 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15353 struct elf_dyn_relocs *p;
5e681ec4
PB		 15354
15355 if (h->root.type == bfd_link_hash_indirect)
15356 return TRUE;
15357
e6a6bb22
AM		 15358 eh = (struct elf32_arm_link_hash_entry *) h;
15359
5e681ec4
PB		 15360 info = (struct bfd_link_info *) inf;
15361 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15362 if (htab == NULL)
15363 return FALSE;
5e681ec4 15364
34e77a92 15365 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15366 && h->plt.refcount > 0)
15367 {
15368 /* Make sure this symbol is output as a dynamic symbol.
15369 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15370 if (h->dynindx == -1 && !h->forced_local
15371 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15372 {
c152c796 15373 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15374 return FALSE;
15375 }
15376
34e77a92
RS		 15377 /* If the call in the PLT entry binds locally, the associated
15378 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15379 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15380 than the .plt section. */
15381 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15382 {
15383 eh->is_iplt = 1;
15384 if (eh->plt.noncall_refcount == 0
15385 && SYMBOL_REFERENCES_LOCAL (info, h))
15386 /* All non-call references can be resolved directly.
15387 This means that they can (and in some cases, must)
15388 resolve directly to the run-time target, rather than
15389 to the PLT. That in turns means that any .got entry
15390 would be equal to the .igot.plt entry, so there's
15391 no point having both. */
15392 h->got.refcount = 0;
15393 }
15394
0e1862bb 15395 if (bfd_link_pic (info)
34e77a92 15396 || eh->is_iplt
7359ea65 15397 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15398 {
34e77a92 15399 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15400
5e681ec4
PB		 15401 /* If this symbol is not defined in a regular file, and we are
15402 not generating a shared library, then set the symbol to this
15403 location in the .plt. This is required to make function
15404 pointers compare as equal between the normal executable and
15405 the shared library. */
0e1862bb 15406 if (! bfd_link_pic (info)
f5385ebf 15407 && !h->def_regular)
5e681ec4 15408 {
34e77a92 15409 h->root.u.def.section = htab->root.splt;
5e681ec4 15410 h->root.u.def.value = h->plt.offset;
5e681ec4 15411
67d74e43
DJ		 15412 /* Make sure the function is not marked as Thumb, in case
15413 it is the target of an ABS32 relocation, which will
15414 point to the PLT entry. */
39d911fc 15415 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15416 }
022f8312 15417
00a97672
RS		 15418 /* VxWorks executables have a second set of relocations for
15419 each PLT entry. They go in a separate relocation section,
15420 which is processed by the kernel loader. */
0e1862bb 15421 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15422 {
15423 /* There is a relocation for the initial PLT entry:
15424 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15425 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15426 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15427
15428 /* There are two extra relocations for each subsequent
15429 PLT entry: an R_ARM_32 relocation for the GOT entry,
15430 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15431 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15432 }
5e681ec4
PB		 15433 }
15434 else
15435 {
15436 h->plt.offset = (bfd_vma) -1;
f5385ebf 15437 h->needs_plt = 0;
5e681ec4
PB		 15438 }
15439 }
15440 else
15441 {
15442 h->plt.offset = (bfd_vma) -1;
f5385ebf 15443 h->needs_plt = 0;
5e681ec4
PB		 15444 }
15445
0855e32b
NS		 15446 eh = (struct elf32_arm_link_hash_entry *) h;
15447 eh->tlsdesc_got = (bfd_vma) -1;
15448
5e681ec4
PB		 15449 if (h->got.refcount > 0)
15450 {
15451 asection *s;
15452 bfd_boolean dyn;
ba93b8ac
DJ		 15453 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15454 int indx;
5e681ec4
PB		 15455
15456 /* Make sure this symbol is output as a dynamic symbol.
15457 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15458 if (h->dynindx == -1 && !h->forced_local
15459 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15460 {
c152c796 15461 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15462 return FALSE;
15463 }
15464
e5a52504
MM		 15465 if (!htab->symbian_p)
15466 {
362d30a1 15467 s = htab->root.sgot;
e5a52504 15468 h->got.offset = s->size;
ba93b8ac
DJ		 15469
15470 if (tls_type == GOT_UNKNOWN)
15471 abort ();
15472
15473 if (tls_type == GOT_NORMAL)
15474 /* Non-TLS symbols need one GOT slot. */
15475 s->size += 4;
15476 else
15477 {
99059e56
RM		 15478 if (tls_type & GOT_TLS_GDESC)
15479 {
0855e32b 15480 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15481 eh->tlsdesc_got
0855e32b
NS		 15482 = (htab->root.sgotplt->size
15483 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15484 htab->root.sgotplt->size += 8;
15485 h->got.offset = (bfd_vma) -2;
34e77a92 15486 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15487 reloc in the middle of .got.plt. */
99059e56
RM		 15488 htab->num_tls_desc++;
15489 }
0855e32b 15490
ba93b8ac 15491 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15492 {
15493 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15494 the symbol is both GD and GDESC, got.offset may
15495 have been overwritten. */
15496 h->got.offset = s->size;
15497 s->size += 8;
15498 }
15499
ba93b8ac
DJ		 15500 if (tls_type & GOT_TLS_IE)
15501 /* R_ARM_TLS_IE32 needs one GOT slot. */
15502 s->size += 4;
15503 }
15504
e5a52504 15505 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15506
15507 indx = 0;
0e1862bb
L		 15508 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15509 bfd_link_pic (info),
15510 h)
15511 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15512 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15513 indx = h->dynindx;
15514
15515 if (tls_type != GOT_NORMAL
0e1862bb 15516 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15517 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15518 || h->root.type != bfd_link_hash_undefweak))
15519 {
15520 if (tls_type & GOT_TLS_IE)
47beaa6a 15521 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15522
15523 if (tls_type & GOT_TLS_GD)
47beaa6a 15524 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15525
b38cadfb 15526 if (tls_type & GOT_TLS_GDESC)
0855e32b 15527 {
47beaa6a 15528 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15529 /* GDESC needs a trampoline to jump to. */
15530 htab->tls_trampoline = -1;
15531 }
15532
15533 /* Only GD needs it. GDESC just emits one relocation per
15534 2 entries. */
b38cadfb 15535 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15536 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15537 }
6f820c85 15538 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15539 {
15540 if (htab->root.dynamic_sections_created)
15541 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15542 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15543 }
34e77a92
RS		 15544 else if (h->type == STT_GNU_IFUNC
15545 && eh->plt.noncall_refcount == 0)
15546 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15547 they all resolve dynamically instead. Reserve room for the
15548 GOT entry's R_ARM_IRELATIVE relocation. */
15549 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15550 else if (bfd_link_pic (info)
15551 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15552 || h->root.type != bfd_link_hash_undefweak))
b436d854 15553 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15554 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15555 }
5e681ec4
PB		 15556 }
15557 else
15558 h->got.offset = (bfd_vma) -1;
15559
a4fd1a8e
PB		 15560 /* Allocate stubs for exported Thumb functions on v4t. */
15561 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15562 && h->def_regular
39d911fc 15563 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15564 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15565 {
15566 struct elf_link_hash_entry * th;
15567 struct bfd_link_hash_entry * bh;
15568 struct elf_link_hash_entry * myh;
15569 char name[1024];
15570 asection *s;
15571 bh = NULL;
15572 /* Create a new symbol to regist the real location of the function. */
15573 s = h->root.u.def.section;
906e58ca 15574 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15575 _bfd_generic_link_add_one_symbol (info, s->owner,
15576 name, BSF_GLOBAL, s,
15577 h->root.u.def.value,
15578 NULL, TRUE, FALSE, &bh);
15579
15580 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15581 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15582 myh->forced_local = 1;
39d911fc 15583 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15584 eh->export_glue = myh;
15585 th = record_arm_to_thumb_glue (info, h);
15586 /* Point the symbol at the stub. */
15587 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15588 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15589 h->root.u.def.section = th->root.u.def.section;
15590 h->root.u.def.value = th->root.u.def.value & ~1;
15591 }
15592
0bdcacaf 15593 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15594 return TRUE;
15595
15596 /* In the shared -Bsymbolic case, discard space allocated for
15597 dynamic pc-relative relocs against symbols which turn out to be
15598 defined in regular objects. For the normal shared case, discard
15599 space for pc-relative relocs that have become local due to symbol
15600 visibility changes. */
15601
0e1862bb 15602 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15603 {
469a3493
RM		 15604 /* Relocs that use pc_count are PC-relative forms, which will appear
15605 on something like ".long foo - ." or "movw REG, foo - .". We want
15606 calls to protected symbols to resolve directly to the function
15607 rather than going via the plt. If people want function pointer
15608 comparisons to work as expected then they should avoid writing
15609 assembly like ".long foo - .". */
ba93b8ac
DJ		 15610 if (SYMBOL_CALLS_LOCAL (info, h))
15611 {
0bdcacaf 15612 struct elf_dyn_relocs **pp;
ba93b8ac 15613
0bdcacaf 15614 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15615 {
15616 p->count -= p->pc_count;
15617 p->pc_count = 0;
15618 if (p->count == 0)
15619 *pp = p->next;
15620 else
15621 pp = &p->next;
15622 }
15623 }
15624
4dfe6ac6 15625 if (htab->vxworks_p)
3348747a 15626 {
0bdcacaf 15627 struct elf_dyn_relocs **pp;
3348747a 15628
0bdcacaf 15629 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15630 {
0bdcacaf 15631 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15632 *pp = p->next;
15633 else
15634 pp = &p->next;
15635 }
15636 }
15637
ba93b8ac 15638 /* Also discard relocs on undefined weak syms with non-default
99059e56 15639 visibility. */
0bdcacaf 15640 if (eh->dyn_relocs != NULL
5e681ec4 15641 && h->root.type == bfd_link_hash_undefweak)
22d606e9 15642 {
95b03e4a
L		 15643 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15644 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 15645 eh->dyn_relocs = NULL;
22d606e9
AM		 15646
15647 /* Make sure undefined weak symbols are output as a dynamic
15648 symbol in PIEs. */
15649 else if (h->dynindx == -1
15650 && !h->forced_local)
15651 {
15652 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15653 return FALSE;
15654 }
15655 }
15656
67687978
PB		 15657 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15658 && h->root.type == bfd_link_hash_new)
15659 {
15660 /* Output absolute symbols so that we can create relocations
15661 against them. For normal symbols we output a relocation
15662 against the section that contains them. */
15663 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15664 return FALSE;
15665 }
15666
5e681ec4
PB		 15667 }
15668 else
15669 {
15670 /* For the non-shared case, discard space for relocs against
15671 symbols which turn out to need copy relocs or are not
15672 dynamic. */
15673
f5385ebf
AM		 15674 if (!h->non_got_ref
15675 && ((h->def_dynamic
15676 && !h->def_regular)
5e681ec4
PB		 15677 || (htab->root.dynamic_sections_created
15678 && (h->root.type == bfd_link_hash_undefweak
15679 || h->root.type == bfd_link_hash_undefined))))
15680 {
15681 /* Make sure this symbol is output as a dynamic symbol.
15682 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15683 if (h->dynindx == -1 && !h->forced_local
15684 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15685 {
c152c796 15686 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15687 return FALSE;
15688 }
15689
15690 /* If that succeeded, we know we'll be keeping all the
15691 relocs. */
15692 if (h->dynindx != -1)
15693 goto keep;
15694 }
15695
0bdcacaf 15696 eh->dyn_relocs = NULL;
5e681ec4
PB		 15697
15698 keep: ;
15699 }
15700
15701 /* Finally, allocate space. */
0bdcacaf 15702 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15703 {
0bdcacaf 15704 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15705 if (h->type == STT_GNU_IFUNC
15706 && eh->plt.noncall_refcount == 0
15707 && SYMBOL_REFERENCES_LOCAL (info, h))
15708 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15709 else
15710 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15711 }
15712
15713 return TRUE;
15714}
15715
63c1f59d
AM		 15716/* Set DF_TEXTREL if we find any dynamic relocs that apply to
15717 read-only sections. */
08d1f311
DJ		 15718
15719static bfd_boolean
63c1f59d 15720maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 15721{
63c1f59d 15722 asection *sec;
08d1f311 15723
63c1f59d
AM		 15724 if (h->root.type == bfd_link_hash_indirect)
15725 return TRUE;
08d1f311 15726
63c1f59d
AM		 15727 sec = readonly_dynrelocs (h);
15728 if (sec != NULL)
15729 {
15730 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 15731
63c1f59d
AM		 15732 info->flags |= DF_TEXTREL;
15733 info->callbacks->minfo
c1c8c1ef 15734 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 15735 sec->owner, h->root.root.string, sec);
08d1f311 15736
63c1f59d
AM		 15737 /* Not an error, just cut short the traversal. */
15738 return FALSE;
08d1f311
DJ		 15739 }
15740 return TRUE;
15741}
15742
d504ffc8
DJ		 15743void
15744bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15745 int byteswap_code)
15746{
15747 struct elf32_arm_link_hash_table *globals;
15748
15749 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15750 if (globals == NULL)
15751 return;
15752
d504ffc8
DJ		 15753 globals->byteswap_code = byteswap_code;
15754}
15755
252b5132
RH		 15756/* Set the sizes of the dynamic sections. */
15757
b34976b6 15758static bfd_boolean
57e8b36a
NC		 15759elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15760 struct bfd_link_info * info)
252b5132
RH		 15761{
15762 bfd * dynobj;
15763 asection * s;
b34976b6
AM		 15764 bfd_boolean plt;
15765 bfd_boolean relocs;
5e681ec4
PB		 15766 bfd *ibfd;
15767 struct elf32_arm_link_hash_table *htab;
252b5132 15768
5e681ec4 15769 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15770 if (htab == NULL)
15771 return FALSE;
15772
252b5132
RH		 15773 dynobj = elf_hash_table (info)->dynobj;
15774 BFD_ASSERT (dynobj != NULL);
39b41c9c 15775 check_use_blx (htab);
252b5132
RH		 15776
15777 if (elf_hash_table (info)->dynamic_sections_created)
15778 {
15779 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15780 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15781 {
3d4d4302 15782 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15783 BFD_ASSERT (s != NULL);
eea6121a 15784 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15785 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15786 }
15787 }
5e681ec4
PB		 15788
15789 /* Set up .got offsets for local syms, and space for local dynamic
15790 relocs. */
c72f2fb2 15791 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15792 {
5e681ec4
PB		 15793 bfd_signed_vma *local_got;
15794 bfd_signed_vma *end_local_got;
34e77a92 15795 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15796 char *local_tls_type;
0855e32b 15797 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15798 bfd_size_type locsymcount;
15799 Elf_Internal_Shdr *symtab_hdr;
15800 asection *srel;
4dfe6ac6 15801 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15802 unsigned int symndx;
5e681ec4 15803
0ffa91dd 15804 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15805 continue;
15806
15807 for (s = ibfd->sections; s != NULL; s = s->next)
15808 {
0bdcacaf 15809 struct elf_dyn_relocs *p;
5e681ec4 15810
0bdcacaf 15811 for (p = (struct elf_dyn_relocs *)
99059e56 15812 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15813 {
0bdcacaf
RS		 15814 if (!bfd_is_abs_section (p->sec)
15815 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15816 {
15817 /* Input section has been discarded, either because
15818 it is a copy of a linkonce section or due to
15819 linker script /DISCARD/, so we'll be discarding
15820 the relocs too. */
15821 }
3348747a 15822 else if (is_vxworks
0bdcacaf 15823 && strcmp (p->sec->output_section->name,
3348747a
NS		 15824 ".tls_vars") == 0)
15825 {
15826 /* Relocations in vxworks .tls_vars sections are
15827 handled specially by the loader. */
15828 }
5e681ec4
PB		 15829 else if (p->count != 0)
15830 {
0bdcacaf 15831 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15832 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15833 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15834 info->flags |= DF_TEXTREL;
15835 }
15836 }
15837 }
15838
15839 local_got = elf_local_got_refcounts (ibfd);
15840 if (!local_got)
15841 continue;
15842
0ffa91dd 15843 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15844 locsymcount = symtab_hdr->sh_info;
15845 end_local_got = local_got + locsymcount;
34e77a92 15846 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15847 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15848 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15849 symndx = 0;
362d30a1
RS		 15850 s = htab->root.sgot;
15851 srel = htab->root.srelgot;
0855e32b 15852 for (; local_got < end_local_got;
34e77a92
RS		 15853 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15854 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15855 {
0855e32b 15856 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15857 local_iplt = *local_iplt_ptr;
15858 if (local_iplt != NULL)
15859 {
15860 struct elf_dyn_relocs *p;
15861
15862 if (local_iplt->root.refcount > 0)
15863 {
15864 elf32_arm_allocate_plt_entry (info, TRUE,
15865 &local_iplt->root,
15866 &local_iplt->arm);
15867 if (local_iplt->arm.noncall_refcount == 0)
15868 /* All references to the PLT are calls, so all
15869 non-call references can resolve directly to the
15870 run-time target. This means that the .got entry
15871 would be the same as the .igot.plt entry, so there's
15872 no point creating both. */
15873 *local_got = 0;
15874 }
15875 else
15876 {
15877 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15878 local_iplt->root.offset = (bfd_vma) -1;
15879 }
15880
15881 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15882 {
15883 asection *psrel;
15884
15885 psrel = elf_section_data (p->sec)->sreloc;
15886 if (local_iplt->arm.noncall_refcount == 0)
15887 elf32_arm_allocate_irelocs (info, psrel, p->count);
15888 else
15889 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15890 }
15891 }
5e681ec4
PB		 15892 if (*local_got > 0)
15893 {
34e77a92
RS		 15894 Elf_Internal_Sym *isym;
15895
eea6121a 15896 *local_got = s->size;
ba93b8ac
DJ		 15897 if (*local_tls_type & GOT_TLS_GD)
15898 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15899 s->size += 8;
0855e32b
NS		 15900 if (*local_tls_type & GOT_TLS_GDESC)
15901 {
15902 *local_tlsdesc_gotent = htab->root.sgotplt->size
15903 - elf32_arm_compute_jump_table_size (htab);
15904 htab->root.sgotplt->size += 8;
15905 *local_got = (bfd_vma) -2;
34e77a92 15906 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15907 reloc in the middle of .got.plt. */
99059e56 15908 htab->num_tls_desc++;
0855e32b 15909 }
ba93b8ac
DJ		 15910 if (*local_tls_type & GOT_TLS_IE)
15911 s->size += 4;
ba93b8ac 15912
0855e32b
NS		 15913 if (*local_tls_type & GOT_NORMAL)
15914 {
15915 /* If the symbol is both GD and GDESC, *local_got
15916 may have been overwritten. */
15917 *local_got = s->size;
15918 s->size += 4;
15919 }
15920
34e77a92
RS		 15921 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15922 if (isym == NULL)
15923 return FALSE;
15924
15925 /* If all references to an STT_GNU_IFUNC PLT are calls,
15926 then all non-call references, including this GOT entry,
15927 resolve directly to the run-time target. */
15928 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15929 && (local_iplt == NULL
15930 || local_iplt->arm.noncall_refcount == 0))
15931 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15932 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15933 {
0e1862bb 15934 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15935 || *local_tls_type & GOT_TLS_GD)
15936 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15937
0e1862bb 15938 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15939 {
15940 elf32_arm_allocate_dynrelocs (info,
15941 htab->root.srelplt, 1);
15942 htab->tls_trampoline = -1;
15943 }
0855e32b 15944 }
5e681ec4
PB		 15945 }
15946 else
15947 *local_got = (bfd_vma) -1;
15948 }
252b5132
RH		 15949 }
15950
ba93b8ac
DJ		 15951 if (htab->tls_ldm_got.refcount > 0)
15952 {
15953 /* Allocate two GOT entries and one dynamic relocation (if necessary)
15954 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 15955 htab->tls_ldm_got.offset = htab->root.sgot->size;
15956 htab->root.sgot->size += 8;
0e1862bb 15957 if (bfd_link_pic (info))
47beaa6a 15958 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15959 }
15960 else
15961 htab->tls_ldm_got.offset = -1;
15962
5e681ec4
PB		 15963 /* Allocate global sym .plt and .got entries, and space for global
15964 sym dynamic relocs. */
47beaa6a 15965 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 15966
d504ffc8 15967 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 15968 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 15969 {
0ffa91dd 15970 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 15971 continue;
15972
c7b8f16e
JB		 15973 /* Initialise mapping tables for code/data. */
15974 bfd_elf32_arm_init_maps (ibfd);
906e58ca 15975
c7b8f16e 15976 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 15977 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
15978 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 15979 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 15980 }
d504ffc8 15981
3e6b1042
DJ		 15982 /* Allocate space for the glue sections now that we've sized them. */
15983 bfd_elf32_arm_allocate_interworking_sections (info);
15984
0855e32b
NS		 15985 /* For every jump slot reserved in the sgotplt, reloc_count is
15986 incremented. However, when we reserve space for TLS descriptors,
15987 it's not incremented, so in order to compute the space reserved
15988 for them, it suffices to multiply the reloc count by the jump
15989 slot size. */
15990 if (htab->root.srelplt)
15991 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
15992
15993 if (htab->tls_trampoline)
15994 {
15995 if (htab->root.splt->size == 0)
15996 htab->root.splt->size += htab->plt_header_size;
b38cadfb 15997
0855e32b
NS		 15998 htab->tls_trampoline = htab->root.splt->size;
15999 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16000
0855e32b 16001 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16002 PLT and GOT entries they require. */
0855e32b
NS		 16003 if (!(info->flags & DF_BIND_NOW))
16004 {
16005 htab->dt_tlsdesc_got = htab->root.sgot->size;
16006 htab->root.sgot->size += 4;
16007
16008 htab->dt_tlsdesc_plt = htab->root.splt->size;
16009 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16010 }
16011 }
16012
252b5132
RH		 16013 /* The check_relocs and adjust_dynamic_symbol entry points have
16014 determined the sizes of the various dynamic sections. Allocate
16015 memory for them. */
b34976b6
AM		 16016 plt = FALSE;
16017 relocs = FALSE;
252b5132
RH		 16018 for (s = dynobj->sections; s != NULL; s = s->next)
16019 {
16020 const char * name;
252b5132
RH		 16021
16022 if ((s->flags & SEC_LINKER_CREATED) == 0)
16023 continue;
16024
16025 /* It's OK to base decisions on the section name, because none
16026 of the dynobj section names depend upon the input files. */
16027 name = bfd_get_section_name (dynobj, s);
16028
34e77a92 16029 if (s == htab->root.splt)
252b5132 16030 {
c456f082
AM		 16031 /* Remember whether there is a PLT. */
16032 plt = s->size != 0;
252b5132 16033 }
0112cd26 16034 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16035 {
c456f082 16036 if (s->size != 0)
252b5132 16037 {
252b5132 16038 /* Remember whether there are any reloc sections other
00a97672 16039 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16040 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16041 relocs = TRUE;
252b5132
RH		 16042
16043 /* We use the reloc_count field as a counter if we need
16044 to copy relocs into the output file. */
16045 s->reloc_count = 0;
16046 }
16047 }
34e77a92
RS		 16048 else if (s != htab->root.sgot
16049 && s != htab->root.sgotplt
16050 && s != htab->root.iplt
16051 && s != htab->root.igotplt
5474d94f
AM		 16052 && s != htab->root.sdynbss
16053 && s != htab->root.sdynrelro)
252b5132
RH		 16054 {
16055 /* It's not one of our sections, so don't allocate space. */
16056 continue;
16057 }
16058
c456f082 16059 if (s->size == 0)
252b5132 16060 {
c456f082 16061 /* If we don't need this section, strip it from the
00a97672
RS		 16062 output file. This is mostly to handle .rel(a).bss and
16063 .rel(a).plt. We must create both sections in
c456f082
AM		 16064 create_dynamic_sections, because they must be created
16065 before the linker maps input sections to output
16066 sections. The linker does that before
16067 adjust_dynamic_symbol is called, and it is that
16068 function which decides whether anything needs to go
16069 into these sections. */
8423293d 16070 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16071 continue;
16072 }
16073
c456f082
AM		 16074 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16075 continue;
16076
252b5132 16077 /* Allocate memory for the section contents. */
21d799b5 16078 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16079 if (s->contents == NULL)
b34976b6 16080 return FALSE;
252b5132
RH		 16081 }
16082
16083 if (elf_hash_table (info)->dynamic_sections_created)
16084 {
16085 /* Add some entries to the .dynamic section. We fill in the
16086 values later, in elf32_arm_finish_dynamic_sections, but we
16087 must add the entries now so that we get the correct size for
16088 the .dynamic section. The DT_DEBUG entry is filled in by the
16089 dynamic linker and used by the debugger. */
dc810e39 16090#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16091 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16092
0e1862bb 16093 if (bfd_link_executable (info))
252b5132 16094 {
dc810e39 16095 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16096 return FALSE;
252b5132
RH		 16097 }
16098
16099 if (plt)
16100 {
dc810e39
AM		 16101 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16102 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16103 || !add_dynamic_entry (DT_PLTREL,
16104 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16105 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16106 return FALSE;
0855e32b 16107
5025eb7c
AO		 16108 if (htab->dt_tlsdesc_plt
16109 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16110 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16111 return FALSE;
252b5132
RH		 16112 }
16113
16114 if (relocs)
16115 {
00a97672
RS		 16116 if (htab->use_rel)
16117 {
16118 if (!add_dynamic_entry (DT_REL, 0)
16119 || !add_dynamic_entry (DT_RELSZ, 0)
16120 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16121 return FALSE;
16122 }
16123 else
16124 {
16125 if (!add_dynamic_entry (DT_RELA, 0)
16126 || !add_dynamic_entry (DT_RELASZ, 0)
16127 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16128 return FALSE;
16129 }
252b5132
RH		 16130 }
16131
08d1f311
DJ		 16132 /* If any dynamic relocs apply to a read-only section,
16133 then we need a DT_TEXTREL entry. */
16134 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 16135 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 16136
99e4ae17 16137 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16138 {
dc810e39 16139 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16140 return FALSE;
252b5132 16141 }
7a2b07ff
NS		 16142 if (htab->vxworks_p
16143 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16144 return FALSE;
252b5132 16145 }
8532796c 16146#undef add_dynamic_entry
252b5132 16147
b34976b6 16148 return TRUE;
252b5132
RH		 16149}
16150
0855e32b
NS		 16151/* Size sections even though they're not dynamic. We use it to setup
16152 _TLS_MODULE_BASE_, if needed. */
16153
16154static bfd_boolean
16155elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16156 struct bfd_link_info *info)
0855e32b
NS		 16157{
16158 asection *tls_sec;
16159
0e1862bb 16160 if (bfd_link_relocatable (info))
0855e32b
NS		 16161 return TRUE;
16162
16163 tls_sec = elf_hash_table (info)->tls_sec;
16164
16165 if (tls_sec)
16166 {
16167 struct elf_link_hash_entry *tlsbase;
16168
16169 tlsbase = elf_link_hash_lookup
16170 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16171
16172 if (tlsbase)
99059e56
RM		 16173 {
16174 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16175 const struct elf_backend_data *bed
99059e56 16176 = get_elf_backend_data (output_bfd);
0855e32b 16177
99059e56 16178 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16179 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16180 tls_sec, 0, NULL, FALSE,
16181 bed->collect, &bh)))
16182 return FALSE;
b38cadfb 16183
99059e56
RM		 16184 tlsbase->type = STT_TLS;
16185 tlsbase = (struct elf_link_hash_entry *)bh;
16186 tlsbase->def_regular = 1;
16187 tlsbase->other = STV_HIDDEN;
16188 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16189 }
16190 }
16191 return TRUE;
16192}
16193
252b5132
RH		 16194/* Finish up dynamic symbol handling. We set the contents of various
16195 dynamic sections here. */
16196
b34976b6 16197static bfd_boolean
906e58ca
NC		 16198elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16199 struct bfd_link_info * info,
16200 struct elf_link_hash_entry * h,
16201 Elf_Internal_Sym * sym)
252b5132 16202{
e5a52504 16203 struct elf32_arm_link_hash_table *htab;
b7693d02 16204 struct elf32_arm_link_hash_entry *eh;
252b5132 16205
e5a52504 16206 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16207 if (htab == NULL)
16208 return FALSE;
16209
b7693d02 16210 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16211
16212 if (h->plt.offset != (bfd_vma) -1)
16213 {
34e77a92 16214 if (!eh->is_iplt)
e5a52504 16215 {
34e77a92 16216 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16217 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16218 h->dynindx, 0))
16219 return FALSE;
e5a52504 16220 }
57e8b36a 16221
f5385ebf 16222 if (!h->def_regular)
252b5132
RH		 16223 {
16224 /* Mark the symbol as undefined, rather than as defined in
3a635617 16225 the .plt section. */
252b5132 16226 sym->st_shndx = SHN_UNDEF;
3a635617 16227 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16228 Otherwise, the PLT entry would provide a definition for
16229 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16230 and so the symbol would never be NULL. Leave the value if
16231 there were any relocations where pointer equality matters
16232 (this is a clue for the dynamic linker, to make function
16233 pointer comparisons work between an application and shared
16234 library). */
97323ad1 16235 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16236 sym->st_value = 0;
252b5132 16237 }
34e77a92
RS		 16238 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16239 {
16240 /* At least one non-call relocation references this .iplt entry,
16241 so the .iplt entry is the function's canonical address. */
16242 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16243 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16244 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16245 (output_bfd, htab->root.iplt->output_section));
16246 sym->st_value = (h->plt.offset
16247 + htab->root.iplt->output_section->vma
16248 + htab->root.iplt->output_offset);
16249 }
252b5132
RH		 16250 }
16251
f5385ebf 16252 if (h->needs_copy)
252b5132
RH		 16253 {
16254 asection * s;
947216bf 16255 Elf_Internal_Rela rel;
252b5132
RH		 16256
16257 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16258 BFD_ASSERT (h->dynindx != -1
16259 && (h->root.type == bfd_link_hash_defined
16260 || h->root.type == bfd_link_hash_defweak));
16261
00a97672 16262 rel.r_addend = 0;
252b5132
RH		 16263 rel.r_offset = (h->root.u.def.value
16264 + h->root.u.def.section->output_section->vma
16265 + h->root.u.def.section->output_offset);
16266 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 16267 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 16268 s = htab->root.sreldynrelro;
16269 else
16270 s = htab->root.srelbss;
47beaa6a 16271 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16272 }
16273
00a97672
RS		 16274 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16275 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16276 to the ".got" section. */
9637f6ef 16277 if (h == htab->root.hdynamic
00a97672 16278 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16279 sym->st_shndx = SHN_ABS;
16280
b34976b6 16281 return TRUE;
252b5132
RH		 16282}
16283
0855e32b
NS		 16284static void
16285arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16286 void *contents,
16287 const unsigned long *template, unsigned count)
16288{
16289 unsigned ix;
b38cadfb 16290
0855e32b
NS		 16291 for (ix = 0; ix != count; ix++)
16292 {
16293 unsigned long insn = template[ix];
16294
16295 /* Emit mov pc,rx if bx is not permitted. */
16296 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16297 insn = (insn & 0xf000000f) | 0x01a0f000;
16298 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16299 }
16300}
16301
99059e56
RM		 16302/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16303 other variants, NaCl needs this entry in a static executable's
16304 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16305 zero. For .iplt really only the last bundle is useful, and .iplt
16306 could have a shorter first entry, with each individual PLT entry's
16307 relative branch calculated differently so it targets the last
16308 bundle instead of the instruction before it (labelled .Lplt_tail
16309 above). But it's simpler to keep the size and layout of PLT0
16310 consistent with the dynamic case, at the cost of some dead code at
16311 the start of .iplt and the one dead store to the stack at the start
16312 of .Lplt_tail. */
16313static void
16314arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16315 asection *plt, bfd_vma got_displacement)
16316{
16317 unsigned int i;
16318
16319 put_arm_insn (htab, output_bfd,
16320 elf32_arm_nacl_plt0_entry[0]
16321 | arm_movw_immediate (got_displacement),
16322 plt->contents + 0);
16323 put_arm_insn (htab, output_bfd,
16324 elf32_arm_nacl_plt0_entry[1]
16325 | arm_movt_immediate (got_displacement),
16326 plt->contents + 4);
16327
16328 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16329 put_arm_insn (htab, output_bfd,
16330 elf32_arm_nacl_plt0_entry[i],
16331 plt->contents + (i * 4));
16332}
16333
252b5132
RH		 16334/* Finish up the dynamic sections. */
16335
b34976b6 16336static bfd_boolean
57e8b36a 16337elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16338{
16339 bfd * dynobj;
16340 asection * sgot;
16341 asection * sdyn;
4dfe6ac6
NC		 16342 struct elf32_arm_link_hash_table *htab;
16343
16344 htab = elf32_arm_hash_table (info);
16345 if (htab == NULL)
16346 return FALSE;
252b5132
RH		 16347
16348 dynobj = elf_hash_table (info)->dynobj;
16349
362d30a1 16350 sgot = htab->root.sgotplt;
894891db
NC		 16351 /* A broken linker script might have discarded the dynamic sections.
16352 Catch this here so that we do not seg-fault later on. */
16353 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16354 return FALSE;
3d4d4302 16355 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16356
16357 if (elf_hash_table (info)->dynamic_sections_created)
16358 {
16359 asection *splt;
16360 Elf32_External_Dyn *dyncon, *dynconend;
16361
362d30a1 16362 splt = htab->root.splt;
24a1ba0f 16363 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16364 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16365
16366 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16367 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16368
252b5132
RH		 16369 for (; dyncon < dynconend; dyncon++)
16370 {
16371 Elf_Internal_Dyn dyn;
16372 const char * name;
16373 asection * s;
16374
16375 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16376
16377 switch (dyn.d_tag)
16378 {
229fcec5
MM		 16379 unsigned int type;
16380
252b5132 16381 default:
7a2b07ff
NS		 16382 if (htab->vxworks_p
16383 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16384 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16385 break;
16386
229fcec5
MM		 16387 case DT_HASH:
16388 name = ".hash";
16389 goto get_vma_if_bpabi;
16390 case DT_STRTAB:
16391 name = ".dynstr";
16392 goto get_vma_if_bpabi;
16393 case DT_SYMTAB:
16394 name = ".dynsym";
16395 goto get_vma_if_bpabi;
c0042f5d
MM		 16396 case DT_VERSYM:
16397 name = ".gnu.version";
16398 goto get_vma_if_bpabi;
16399 case DT_VERDEF:
16400 name = ".gnu.version_d";
16401 goto get_vma_if_bpabi;
16402 case DT_VERNEED:
16403 name = ".gnu.version_r";
16404 goto get_vma_if_bpabi;
16405
252b5132 16406 case DT_PLTGOT:
4ade44b7 16407 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16408 goto get_vma;
16409 case DT_JMPREL:
00a97672 16410 name = RELOC_SECTION (htab, ".plt");
252b5132 16411 get_vma:
4ade44b7 16412 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16413 if (s == NULL)
16414 {
4eca0228 16415 _bfd_error_handler
4ade44b7 16416 (_("could not find section %s"), name);
05456594
NC		 16417 bfd_set_error (bfd_error_invalid_operation);
16418 return FALSE;
16419 }
229fcec5 16420 if (!htab->symbian_p)
4ade44b7 16421 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16422 else
16423 /* In the BPABI, tags in the PT_DYNAMIC section point
16424 at the file offset, not the memory address, for the
16425 convenience of the post linker. */
4ade44b7 16426 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16427 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16428 break;
16429
229fcec5
MM		 16430 get_vma_if_bpabi:
16431 if (htab->symbian_p)
16432 goto get_vma;
16433 break;
16434
252b5132 16435 case DT_PLTRELSZ:
362d30a1 16436 s = htab->root.srelplt;
252b5132 16437 BFD_ASSERT (s != NULL);
eea6121a 16438 dyn.d_un.d_val = s->size;
252b5132
RH		 16439 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16440 break;
906e58ca 16441
252b5132 16442 case DT_RELSZ:
00a97672 16443 case DT_RELASZ:
229fcec5
MM		 16444 case DT_REL:
16445 case DT_RELA:
229fcec5
MM		 16446 /* In the BPABI, the DT_REL tag must point at the file
16447 offset, not the VMA, of the first relocation
16448 section. So, we use code similar to that in
16449 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 16450 relocation section, since relocation sections are
16451 never allocated under the BPABI. PLT relocs are also
16452 included. */
229fcec5
MM		 16453 if (htab->symbian_p)
16454 {
16455 unsigned int i;
16456 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16457 ? SHT_REL : SHT_RELA);
16458 dyn.d_un.d_val = 0;
16459 for (i = 1; i < elf_numsections (output_bfd); i++)
16460 {
906e58ca 16461 Elf_Internal_Shdr *hdr
229fcec5
MM		 16462 = elf_elfsections (output_bfd)[i];
16463 if (hdr->sh_type == type)
16464 {
906e58ca 16465 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16466 || dyn.d_tag == DT_RELASZ)
16467 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16468 else if ((ufile_ptr) hdr->sh_offset
16469 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16470 dyn.d_un.d_val = hdr->sh_offset;
16471 }
16472 }
16473 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16474 }
252b5132 16475 break;
88f7bcd5 16476
0855e32b 16477 case DT_TLSDESC_PLT:
99059e56 16478 s = htab->root.splt;
0855e32b
NS		 16479 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16480 + htab->dt_tlsdesc_plt);
16481 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16482 break;
16483
16484 case DT_TLSDESC_GOT:
99059e56 16485 s = htab->root.sgot;
0855e32b 16486 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16487 + htab->dt_tlsdesc_got);
0855e32b
NS		 16488 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16489 break;
16490
88f7bcd5
NC		 16491 /* Set the bottom bit of DT_INIT/FINI if the
16492 corresponding function is Thumb. */
16493 case DT_INIT:
16494 name = info->init_function;
16495 goto get_sym;
16496 case DT_FINI:
16497 name = info->fini_function;
16498 get_sym:
16499 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16500 then there is nothing to adjust. */
88f7bcd5
NC		 16501 if (dyn.d_un.d_val != 0)
16502 {
16503 struct elf_link_hash_entry * eh;
16504
16505 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16506 FALSE, FALSE, TRUE);
39d911fc
TP		 16507 if (eh != NULL
16508 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16509 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16510 {
16511 dyn.d_un.d_val |= 1;
b34976b6 16512 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16513 }
16514 }
16515 break;
252b5132
RH		 16516 }
16517 }
16518
24a1ba0f 16519 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16520 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16521 {
00a97672
RS		 16522 const bfd_vma *plt0_entry;
16523 bfd_vma got_address, plt_address, got_displacement;
16524
16525 /* Calculate the addresses of the GOT and PLT. */
16526 got_address = sgot->output_section->vma + sgot->output_offset;
16527 plt_address = splt->output_section->vma + splt->output_offset;
16528
16529 if (htab->vxworks_p)
16530 {
16531 /* The VxWorks GOT is relocated by the dynamic linker.
16532 Therefore, we must emit relocations rather than simply
16533 computing the values now. */
16534 Elf_Internal_Rela rel;
16535
16536 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16537 put_arm_insn (htab, output_bfd, plt0_entry[0],
16538 splt->contents + 0);
16539 put_arm_insn (htab, output_bfd, plt0_entry[1],
16540 splt->contents + 4);
16541 put_arm_insn (htab, output_bfd, plt0_entry[2],
16542 splt->contents + 8);
00a97672
RS		 16543 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16544
8029a119 16545 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16546 rel.r_offset = plt_address + 12;
16547 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16548 rel.r_addend = 0;
16549 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16550 htab->srelplt2->contents);
16551 }
b38cadfb 16552 else if (htab->nacl_p)
99059e56
RM		 16553 arm_nacl_put_plt0 (htab, output_bfd, splt,
16554 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16555 else if (using_thumb_only (htab))
16556 {
16557 got_displacement = got_address - (plt_address + 12);
16558
16559 plt0_entry = elf32_thumb2_plt0_entry;
16560 put_arm_insn (htab, output_bfd, plt0_entry[0],
16561 splt->contents + 0);
16562 put_arm_insn (htab, output_bfd, plt0_entry[1],
16563 splt->contents + 4);
16564 put_arm_insn (htab, output_bfd, plt0_entry[2],
16565 splt->contents + 8);
16566
16567 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16568 }
00a97672
RS		 16569 else
16570 {
16571 got_displacement = got_address - (plt_address + 16);
16572
16573 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16574 put_arm_insn (htab, output_bfd, plt0_entry[0],
16575 splt->contents + 0);
16576 put_arm_insn (htab, output_bfd, plt0_entry[1],
16577 splt->contents + 4);
16578 put_arm_insn (htab, output_bfd, plt0_entry[2],
16579 splt->contents + 8);
16580 put_arm_insn (htab, output_bfd, plt0_entry[3],
16581 splt->contents + 12);
5e681ec4 16582
5e681ec4 16583#ifdef FOUR_WORD_PLT
00a97672
RS		 16584 /* The displacement value goes in the otherwise-unused
16585 last word of the second entry. */
16586 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16587#else
00a97672 16588 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16589#endif
00a97672 16590 }
f7a74f8c 16591 }
252b5132
RH		 16592
16593 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16594 really seem like the right value. */
74541ad4
AM		 16595 if (splt->output_section->owner == output_bfd)
16596 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16597
0855e32b
NS		 16598 if (htab->dt_tlsdesc_plt)
16599 {
16600 bfd_vma got_address
16601 = sgot->output_section->vma + sgot->output_offset;
16602 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16603 + htab->root.sgot->output_offset);
16604 bfd_vma plt_address
16605 = splt->output_section->vma + splt->output_offset;
16606
b38cadfb 16607 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16608 splt->contents + htab->dt_tlsdesc_plt,
16609 dl_tlsdesc_lazy_trampoline, 6);
16610
16611 bfd_put_32 (output_bfd,
16612 gotplt_address + htab->dt_tlsdesc_got
16613 - (plt_address + htab->dt_tlsdesc_plt)
16614 - dl_tlsdesc_lazy_trampoline[6],
16615 splt->contents + htab->dt_tlsdesc_plt + 24);
16616 bfd_put_32 (output_bfd,
16617 got_address - (plt_address + htab->dt_tlsdesc_plt)
16618 - dl_tlsdesc_lazy_trampoline[7],
16619 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16620 }
16621
16622 if (htab->tls_trampoline)
16623 {
b38cadfb 16624 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16625 splt->contents + htab->tls_trampoline,
16626 tls_trampoline, 3);
16627#ifdef FOUR_WORD_PLT
16628 bfd_put_32 (output_bfd, 0x00000000,
16629 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16630#endif
0855e32b
NS		 16631 }
16632
0e1862bb
L		 16633 if (htab->vxworks_p
16634 && !bfd_link_pic (info)
16635 && htab->root.splt->size > 0)
00a97672
RS		 16636 {
16637 /* Correct the .rel(a).plt.unloaded relocations. They will have
16638 incorrect symbol indexes. */
16639 int num_plts;
eed62c48 16640 unsigned char *p;
00a97672 16641
362d30a1 16642 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16643 / htab->plt_entry_size);
16644 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16645
16646 for (; num_plts; num_plts--)
16647 {
16648 Elf_Internal_Rela rel;
16649
16650 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16651 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16652 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16653 p += RELOC_SIZE (htab);
16654
16655 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16656 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16657 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16658 p += RELOC_SIZE (htab);
16659 }
16660 }
252b5132
RH		 16661 }
16662
99059e56
RM		 16663 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16664 /* NaCl uses a special first entry in .iplt too. */
16665 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16666
252b5132 16667 /* Fill in the first three entries in the global offset table. */
229fcec5 16668 if (sgot)
252b5132 16669 {
229fcec5
MM		 16670 if (sgot->size > 0)
16671 {
16672 if (sdyn == NULL)
16673 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16674 else
16675 bfd_put_32 (output_bfd,
16676 sdyn->output_section->vma + sdyn->output_offset,
16677 sgot->contents);
16678 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16679 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16680 }
252b5132 16681
229fcec5
MM		 16682 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16683 }
252b5132 16684
b34976b6 16685 return TRUE;
252b5132
RH		 16686}
16687
ba96a88f 16688static void
57e8b36a 16689elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16690{
9b485d32 16691 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16692 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16693 struct elf_segment_map *m;
ba96a88f
NC		 16694
16695 i_ehdrp = elf_elfheader (abfd);
16696
94a3258f
PB		 16697 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16698 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16699 else
7394f108 16700 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16701 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16702
93204d3a
PB		 16703 if (link_info)
16704 {
16705 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16706 if (globals != NULL && globals->byteswap_code)
93204d3a 16707 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 16708
16709 if (globals->fdpic_p)
16710 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 16711 }
3bfcb652
NC		 16712
16713 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16714 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16715 {
16716 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16717 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16718 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16719 else
16720 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16721 }
ac4c9b04
MG		 16722
16723 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16724 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16725 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16726 {
16727 unsigned int j;
16728
16729 if (m->count == 0)
16730 continue;
16731 for (j = 0; j < m->count; j++)
16732 {
f0728ee3 16733 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16734 break;
16735 }
16736 if (j == m->count)
16737 {
16738 m->p_flags = PF_X;
16739 m->p_flags_valid = 1;
16740 }
16741 }
ba96a88f
NC		 16742}
16743
99e4ae17 16744static enum elf_reloc_type_class
7e612e98
AM		 16745elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16746 const asection *rel_sec ATTRIBUTE_UNUSED,
16747 const Elf_Internal_Rela *rela)
99e4ae17 16748{
f51e552e 16749 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16750 {
16751 case R_ARM_RELATIVE:
16752 return reloc_class_relative;
16753 case R_ARM_JUMP_SLOT:
16754 return reloc_class_plt;
16755 case R_ARM_COPY:
16756 return reloc_class_copy;
109575d7
JW		 16757 case R_ARM_IRELATIVE:
16758 return reloc_class_ifunc;
99e4ae17
AJ		 16759 default:
16760 return reloc_class_normal;
16761 }
16762}
16763
e489d0ae 16764static void
57e8b36a 16765elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16766{
5a6c6817 16767 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16768}
16769
40a18ebd
NC		 16770/* Return TRUE if this is an unwinding table entry. */
16771
16772static bfd_boolean
16773is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16774{
0112cd26
NC		 16775 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16776 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16777}
16778
16779
16780/* Set the type and flags for an ARM section. We do this by
16781 the section name, which is a hack, but ought to work. */
16782
16783static bfd_boolean
16784elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16785{
16786 const char * name;
16787
16788 name = bfd_get_section_name (abfd, sec);
16789
16790 if (is_arm_elf_unwind_section_name (abfd, name))
16791 {
16792 hdr->sh_type = SHT_ARM_EXIDX;
16793 hdr->sh_flags |= SHF_LINK_ORDER;
16794 }
ac4c9b04 16795
f0728ee3
AV		 16796 if (sec->flags & SEC_ELF_PURECODE)
16797 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16798
40a18ebd
NC		 16799 return TRUE;
16800}
16801
6dc132d9
L		 16802/* Handle an ARM specific section when reading an object file. This is
16803 called when bfd_section_from_shdr finds a section with an unknown
16804 type. */
40a18ebd
NC		 16805
16806static bfd_boolean
16807elf32_arm_section_from_shdr (bfd *abfd,
16808 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16809 const char *name,
16810 int shindex)
40a18ebd
NC		 16811{
16812 /* There ought to be a place to keep ELF backend specific flags, but
16813 at the moment there isn't one. We just keep track of the
16814 sections by their name, instead. Fortunately, the ABI gives
16815 names for all the ARM specific sections, so we will probably get
16816 away with this. */
16817 switch (hdr->sh_type)
16818 {
16819 case SHT_ARM_EXIDX:
0951f019
RE		 16820 case SHT_ARM_PREEMPTMAP:
16821 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16822 break;
16823
16824 default:
16825 return FALSE;
16826 }
16827
6dc132d9 16828 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16829 return FALSE;
16830
16831 return TRUE;
16832}
e489d0ae 16833
44444f50
NC		 16834static _arm_elf_section_data *
16835get_arm_elf_section_data (asection * sec)
16836{
47b2e99c
JZ		 16837 if (sec && sec->owner && is_arm_elf (sec->owner))
16838 return elf32_arm_section_data (sec);
44444f50
NC		 16839 else
16840 return NULL;
8e3de13a
NC		 16841}
16842
4e617b1e
PB		 16843typedef struct
16844{
57402f1e 16845 void *flaginfo;
4e617b1e 16846 struct bfd_link_info *info;
91a5743d
PB		 16847 asection *sec;
16848 int sec_shndx;
6e0b88f1
AM		 16849 int (*func) (void *, const char *, Elf_Internal_Sym *,
16850 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16851} output_arch_syminfo;
16852
16853enum map_symbol_type
16854{
16855 ARM_MAP_ARM,
16856 ARM_MAP_THUMB,
16857 ARM_MAP_DATA
16858};
16859
16860
7413f23f 16861/* Output a single mapping symbol. */
4e617b1e
PB		 16862
16863static bfd_boolean
7413f23f
DJ		 16864elf32_arm_output_map_sym (output_arch_syminfo *osi,
16865 enum map_symbol_type type,
16866 bfd_vma offset)
4e617b1e
PB		 16867{
16868 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16869 Elf_Internal_Sym sym;
16870
91a5743d
PB		 16871 sym.st_value = osi->sec->output_section->vma
16872 + osi->sec->output_offset
16873 + offset;
4e617b1e
PB		 16874 sym.st_size = 0;
16875 sym.st_other = 0;
16876 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16877 sym.st_shndx = osi->sec_shndx;
35fc36a8 16878 sym.st_target_internal = 0;
fe33d2fa 16879 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16880 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16881}
16882
34e77a92
RS		 16883/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16884 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16885
16886static bfd_boolean
34e77a92
RS		 16887elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16888 bfd_boolean is_iplt_entry_p,
16889 union gotplt_union *root_plt,
16890 struct arm_plt_info *arm_plt)
4e617b1e 16891{
4e617b1e 16892 struct elf32_arm_link_hash_table *htab;
34e77a92 16893 bfd_vma addr, plt_header_size;
4e617b1e 16894
34e77a92 16895 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16896 return TRUE;
16897
4dfe6ac6
NC		 16898 htab = elf32_arm_hash_table (osi->info);
16899 if (htab == NULL)
16900 return FALSE;
16901
34e77a92
RS		 16902 if (is_iplt_entry_p)
16903 {
16904 osi->sec = htab->root.iplt;
16905 plt_header_size = 0;
16906 }
16907 else
16908 {
16909 osi->sec = htab->root.splt;
16910 plt_header_size = htab->plt_header_size;
16911 }
16912 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16913 (osi->info->output_bfd, osi->sec->output_section));
16914
16915 addr = root_plt->offset & -2;
4e617b1e
PB		 16916 if (htab->symbian_p)
16917 {
7413f23f 16918 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16919 return FALSE;
7413f23f 16920 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16921 return FALSE;
16922 }
16923 else if (htab->vxworks_p)
16924 {
7413f23f 16925 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16926 return FALSE;
7413f23f 16927 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16928 return FALSE;
7413f23f 16929 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16930 return FALSE;
7413f23f 16931 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16932 return FALSE;
16933 }
b38cadfb
NC		 16934 else if (htab->nacl_p)
16935 {
16936 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16937 return FALSE;
16938 }
eed94f8f
NC		 16939 else if (using_thumb_only (htab))
16940 {
16941 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16942 return FALSE;
6a631e86 16943 }
4e617b1e
PB		 16944 else
16945 {
34e77a92 16946 bfd_boolean thumb_stub_p;
bd97cb95 16947
34e77a92
RS		 16948 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16949 if (thumb_stub_p)
4e617b1e 16950 {
7413f23f 16951 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16952 return FALSE;
16953 }
16954#ifdef FOUR_WORD_PLT
7413f23f 16955 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16956 return FALSE;
7413f23f 16957 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 16958 return FALSE;
16959#else
906e58ca 16960 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 16961 so only need to output a mapping symbol for the first PLT entry and
16962 entries with thumb thunks. */
34e77a92 16963 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 16964 {
7413f23f 16965 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 16966 return FALSE;
16967 }
16968#endif
16969 }
16970
16971 return TRUE;
16972}
16973
34e77a92
RS		 16974/* Output mapping symbols for PLT entries associated with H. */
16975
16976static bfd_boolean
16977elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
16978{
16979 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
16980 struct elf32_arm_link_hash_entry *eh;
16981
16982 if (h->root.type == bfd_link_hash_indirect)
16983 return TRUE;
16984
16985 if (h->root.type == bfd_link_hash_warning)
16986 /* When warning symbols are created, they **replace** the "real"
16987 entry in the hash table, thus we never get to see the real
16988 symbol in a hash traversal. So look at it now. */
16989 h = (struct elf_link_hash_entry *) h->root.u.i.link;
16990
16991 eh = (struct elf32_arm_link_hash_entry *) h;
16992 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
16993 &h->plt, &eh->plt);
16994}
16995
4f4faa4d
TP		 16996/* Bind a veneered symbol to its veneer identified by its hash entry
16997 STUB_ENTRY. The veneered location thus loose its symbol. */
16998
16999static void
17000arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17001{
17002 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17003
17004 BFD_ASSERT (hash);
17005 hash->root.root.u.def.section = stub_entry->stub_sec;
17006 hash->root.root.u.def.value = stub_entry->stub_offset;
17007 hash->root.size = stub_entry->stub_size;
17008}
17009
7413f23f
DJ		 17010/* Output a single local symbol for a generated stub. */
17011
17012static bfd_boolean
17013elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17014 bfd_vma offset, bfd_vma size)
17015{
7413f23f
DJ		 17016 Elf_Internal_Sym sym;
17017
7413f23f
DJ		 17018 sym.st_value = osi->sec->output_section->vma
17019 + osi->sec->output_offset
17020 + offset;
17021 sym.st_size = size;
17022 sym.st_other = 0;
17023 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17024 sym.st_shndx = osi->sec_shndx;
35fc36a8 17025 sym.st_target_internal = 0;
57402f1e 17026 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17027}
4e617b1e 17028
da5938a2 17029static bfd_boolean
8029a119
NC		 17030arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17031 void * in_arg)
da5938a2
NC		 17032{
17033 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17034 asection *stub_sec;
17035 bfd_vma addr;
7413f23f 17036 char *stub_name;
9a008db3 17037 output_arch_syminfo *osi;
d3ce72d0 17038 const insn_sequence *template_sequence;
461a49ca
DJ		 17039 enum stub_insn_type prev_type;
17040 int size;
17041 int i;
17042 enum map_symbol_type sym_type;
da5938a2
NC		 17043
17044 /* Massage our args to the form they really have. */
17045 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17046 osi = (output_arch_syminfo *) in_arg;
da5938a2 17047
da5938a2
NC		 17048 stub_sec = stub_entry->stub_sec;
17049
17050 /* Ensure this stub is attached to the current section being
7413f23f 17051 processed. */
da5938a2
NC		 17052 if (stub_sec != osi->sec)
17053 return TRUE;
17054
7413f23f 17055 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17056 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17057
17058 if (arm_stub_sym_claimed (stub_entry->stub_type))
17059 arm_stub_claim_sym (stub_entry);
17060 else
7413f23f 17061 {
4f4faa4d
TP		 17062 stub_name = stub_entry->output_name;
17063 switch (template_sequence[0].type)
17064 {
17065 case ARM_TYPE:
17066 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17067 stub_entry->stub_size))
17068 return FALSE;
17069 break;
17070 case THUMB16_TYPE:
17071 case THUMB32_TYPE:
17072 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17073 stub_entry->stub_size))
17074 return FALSE;
17075 break;
17076 default:
17077 BFD_FAIL ();
17078 return 0;
17079 }
7413f23f 17080 }
da5938a2 17081
461a49ca
DJ		 17082 prev_type = DATA_TYPE;
17083 size = 0;
17084 for (i = 0; i < stub_entry->stub_template_size; i++)
17085 {
d3ce72d0 17086 switch (template_sequence[i].type)
461a49ca
DJ		 17087 {
17088 case ARM_TYPE:
17089 sym_type = ARM_MAP_ARM;
17090 break;
17091
17092 case THUMB16_TYPE:
48229727 17093 case THUMB32_TYPE:
461a49ca
DJ		 17094 sym_type = ARM_MAP_THUMB;
17095 break;
17096
17097 case DATA_TYPE:
17098 sym_type = ARM_MAP_DATA;
17099 break;
17100
17101 default:
17102 BFD_FAIL ();
4e31c731 17103 return FALSE;
461a49ca
DJ		 17104 }
17105
d3ce72d0 17106 if (template_sequence[i].type != prev_type)
461a49ca 17107 {
d3ce72d0 17108 prev_type = template_sequence[i].type;
461a49ca
DJ		 17109 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17110 return FALSE;
17111 }
17112
d3ce72d0 17113 switch (template_sequence[i].type)
461a49ca
DJ		 17114 {
17115 case ARM_TYPE:
48229727 17116 case THUMB32_TYPE:
461a49ca
DJ		 17117 size += 4;
17118 break;
17119
17120 case THUMB16_TYPE:
17121 size += 2;
17122 break;
17123
17124 case DATA_TYPE:
17125 size += 4;
17126 break;
17127
17128 default:
17129 BFD_FAIL ();
4e31c731 17130 return FALSE;
461a49ca
DJ		 17131 }
17132 }
17133
da5938a2
NC		 17134 return TRUE;
17135}
17136
33811162
DG		 17137/* Output mapping symbols for linker generated sections,
17138 and for those data-only sections that do not have a
17139 $d. */
4e617b1e
PB		 17140
17141static bfd_boolean
17142elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17143 struct bfd_link_info *info,
57402f1e 17144 void *flaginfo,
6e0b88f1
AM		 17145 int (*func) (void *, const char *,
17146 Elf_Internal_Sym *,
17147 asection *,
17148 struct elf_link_hash_entry *))
4e617b1e
PB		 17149{
17150 output_arch_syminfo osi;
17151 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17152 bfd_vma offset;
17153 bfd_size_type size;
33811162 17154 bfd *input_bfd;
4e617b1e
PB		 17155
17156 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17157 if (htab == NULL)
17158 return FALSE;
17159
906e58ca 17160 check_use_blx (htab);
91a5743d 17161
57402f1e 17162 osi.flaginfo = flaginfo;
4e617b1e
PB		 17163 osi.info = info;
17164 osi.func = func;
906e58ca 17165
33811162
DG		 17166 /* Add a $d mapping symbol to data-only sections that
17167 don't have any mapping symbol. This may result in (harmless) redundant
17168 mapping symbols. */
17169 for (input_bfd = info->input_bfds;
17170 input_bfd != NULL;
c72f2fb2 17171 input_bfd = input_bfd->link.next)
33811162
DG		 17172 {
17173 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17174 for (osi.sec = input_bfd->sections;
17175 osi.sec != NULL;
17176 osi.sec = osi.sec->next)
17177 {
17178 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17179 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17180 != 0)
33811162
DG		 17181 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17182 == SEC_HAS_CONTENTS
17183 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17184 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17185 && osi.sec->size > 0
17186 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17187 {
17188 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17189 (output_bfd, osi.sec->output_section);
17190 if (osi.sec_shndx != (int)SHN_BAD)
17191 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17192 }
17193 }
17194 }
17195
91a5743d
PB		 17196 /* ARM->Thumb glue. */
17197 if (htab->arm_glue_size > 0)
17198 {
3d4d4302
AM		 17199 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17200 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17201
17202 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17203 (output_bfd, osi.sec->output_section);
0e1862bb 17204 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17205 || htab->pic_veneer)
17206 size = ARM2THUMB_PIC_GLUE_SIZE;
17207 else if (htab->use_blx)
17208 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17209 else
17210 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17211
91a5743d
PB		 17212 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17213 {
7413f23f
DJ		 17214 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17215 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17216 }
17217 }
17218
17219 /* Thumb->ARM glue. */
17220 if (htab->thumb_glue_size > 0)
17221 {
3d4d4302
AM		 17222 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17223 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17224
17225 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17226 (output_bfd, osi.sec->output_section);
17227 size = THUMB2ARM_GLUE_SIZE;
17228
17229 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17230 {
7413f23f
DJ		 17231 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17232 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17233 }
17234 }
17235
845b51d6
PB		 17236 /* ARMv4 BX veneers. */
17237 if (htab->bx_glue_size > 0)
17238 {
3d4d4302
AM		 17239 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17240 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17241
17242 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17243 (output_bfd, osi.sec->output_section);
17244
7413f23f 17245 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17246 }
17247
8029a119
NC		 17248 /* Long calls stubs. */
17249 if (htab->stub_bfd && htab->stub_bfd->sections)
17250 {
da5938a2 17251 asection* stub_sec;
8029a119 17252
da5938a2
NC		 17253 for (stub_sec = htab->stub_bfd->sections;
17254 stub_sec != NULL;
8029a119
NC		 17255 stub_sec = stub_sec->next)
17256 {
17257 /* Ignore non-stub sections. */
17258 if (!strstr (stub_sec->name, STUB_SUFFIX))
17259 continue;
da5938a2 17260
8029a119 17261 osi.sec = stub_sec;
da5938a2 17262
8029a119
NC		 17263 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17264 (output_bfd, osi.sec->output_section);
da5938a2 17265
8029a119
NC		 17266 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17267 }
17268 }
da5938a2 17269
91a5743d 17270 /* Finally, output mapping symbols for the PLT. */
34e77a92 17271 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17272 {
34e77a92
RS		 17273 osi.sec = htab->root.splt;
17274 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17275 (output_bfd, osi.sec->output_section));
17276
17277 /* Output mapping symbols for the plt header. SymbianOS does not have a
17278 plt header. */
17279 if (htab->vxworks_p)
17280 {
17281 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17282 if (!bfd_link_pic (info))
34e77a92
RS		 17283 {
17284 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17285 return FALSE;
17286 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17287 return FALSE;
17288 }
17289 }
b38cadfb
NC		 17290 else if (htab->nacl_p)
17291 {
17292 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17293 return FALSE;
17294 }
eed94f8f
NC		 17295 else if (using_thumb_only (htab))
17296 {
17297 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17298 return FALSE;
17299 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17300 return FALSE;
17301 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17302 return FALSE;
17303 }
34e77a92 17304 else if (!htab->symbian_p)
4e617b1e 17305 {
7413f23f 17306 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17307 return FALSE;
34e77a92
RS		 17308#ifndef FOUR_WORD_PLT
17309 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17310 return FALSE;
34e77a92 17311#endif
4e617b1e
PB		 17312 }
17313 }
99059e56
RM		 17314 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17315 {
17316 /* NaCl uses a special first entry in .iplt too. */
17317 osi.sec = htab->root.iplt;
17318 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17319 (output_bfd, osi.sec->output_section));
17320 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17321 return FALSE;
17322 }
34e77a92
RS		 17323 if ((htab->root.splt && htab->root.splt->size > 0)
17324 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17325 {
34e77a92
RS		 17326 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17327 for (input_bfd = info->input_bfds;
17328 input_bfd != NULL;
c72f2fb2 17329 input_bfd = input_bfd->link.next)
34e77a92
RS		 17330 {
17331 struct arm_local_iplt_info **local_iplt;
17332 unsigned int i, num_syms;
4e617b1e 17333
34e77a92
RS		 17334 local_iplt = elf32_arm_local_iplt (input_bfd);
17335 if (local_iplt != NULL)
17336 {
17337 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17338 for (i = 0; i < num_syms; i++)
17339 if (local_iplt[i] != NULL
17340 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17341 &local_iplt[i]->root,
17342 &local_iplt[i]->arm))
17343 return FALSE;
17344 }
17345 }
17346 }
0855e32b
NS		 17347 if (htab->dt_tlsdesc_plt != 0)
17348 {
17349 /* Mapping symbols for the lazy tls trampoline. */
17350 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17351 return FALSE;
b38cadfb 17352
0855e32b
NS		 17353 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17354 htab->dt_tlsdesc_plt + 24))
17355 return FALSE;
17356 }
17357 if (htab->tls_trampoline != 0)
17358 {
17359 /* Mapping symbols for the tls trampoline. */
17360 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17361 return FALSE;
17362#ifdef FOUR_WORD_PLT
17363 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17364 htab->tls_trampoline + 12))
17365 return FALSE;
b38cadfb 17366#endif
0855e32b 17367 }
b38cadfb 17368
4e617b1e
PB		 17369 return TRUE;
17370}
17371
54ddd295
TP		 17372/* Filter normal symbols of CMSE entry functions of ABFD to include in
17373 the import library. All SYMCOUNT symbols of ABFD can be examined
17374 from their pointers in SYMS. Pointers of symbols to keep should be
17375 stored continuously at the beginning of that array.
17376
17377 Returns the number of symbols to keep. */
17378
17379static unsigned int
17380elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17381 struct bfd_link_info *info,
17382 asymbol **syms, long symcount)
17383{
17384 size_t maxnamelen;
17385 char *cmse_name;
17386 long src_count, dst_count = 0;
17387 struct elf32_arm_link_hash_table *htab;
17388
17389 htab = elf32_arm_hash_table (info);
17390 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17391 symcount = 0;
17392
17393 maxnamelen = 128;
17394 cmse_name = (char *) bfd_malloc (maxnamelen);
17395 for (src_count = 0; src_count < symcount; src_count++)
17396 {
17397 struct elf32_arm_link_hash_entry *cmse_hash;
17398 asymbol *sym;
17399 flagword flags;
17400 char *name;
17401 size_t namelen;
17402
17403 sym = syms[src_count];
17404 flags = sym->flags;
17405 name = (char *) bfd_asymbol_name (sym);
17406
17407 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17408 continue;
17409 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17410 continue;
17411
17412 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17413 if (namelen > maxnamelen)
17414 {
17415 cmse_name = (char *)
17416 bfd_realloc (cmse_name, namelen);
17417 maxnamelen = namelen;
17418 }
17419 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17420 cmse_hash = (struct elf32_arm_link_hash_entry *)
17421 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17422
17423 if (!cmse_hash
17424 || (cmse_hash->root.root.type != bfd_link_hash_defined
17425 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17426 || cmse_hash->root.type != STT_FUNC)
17427 continue;
17428
17429 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17430 continue;
17431
17432 syms[dst_count++] = sym;
17433 }
17434 free (cmse_name);
17435
17436 syms[dst_count] = NULL;
17437
17438 return dst_count;
17439}
17440
17441/* Filter symbols of ABFD to include in the import library. All
17442 SYMCOUNT symbols of ABFD can be examined from their pointers in
17443 SYMS. Pointers of symbols to keep should be stored continuously at
17444 the beginning of that array.
17445
17446 Returns the number of symbols to keep. */
17447
17448static unsigned int
17449elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17450 struct bfd_link_info *info,
17451 asymbol **syms, long symcount)
17452{
17453 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17454
046734ff
TP		 17455 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
17456 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
17457 library to be a relocatable object file. */
17458 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 17459 if (globals->cmse_implib)
17460 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17461 else
17462 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17463}
17464
e489d0ae
PB		 17465/* Allocate target specific section data. */
17466
17467static bfd_boolean
17468elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17469{
f592407e
AM		 17470 if (!sec->used_by_bfd)
17471 {
17472 _arm_elf_section_data *sdata;
17473 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17474
21d799b5 17475 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17476 if (sdata == NULL)
17477 return FALSE;
17478 sec->used_by_bfd = sdata;
17479 }
e489d0ae
PB		 17480
17481 return _bfd_elf_new_section_hook (abfd, sec);
17482}
17483
17484
17485/* Used to order a list of mapping symbols by address. */
17486
17487static int
17488elf32_arm_compare_mapping (const void * a, const void * b)
17489{
7f6a71ff
JM		 17490 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17491 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17492
17493 if (amap->vma > bmap->vma)
17494 return 1;
17495 else if (amap->vma < bmap->vma)
17496 return -1;
17497 else if (amap->type > bmap->type)
17498 /* Ensure results do not depend on the host qsort for objects with
17499 multiple mapping symbols at the same address by sorting on type
17500 after vma. */
17501 return 1;
17502 else if (amap->type < bmap->type)
17503 return -1;
17504 else
17505 return 0;
e489d0ae
PB		 17506}
17507
2468f9c9
PB		 17508/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17509
17510static unsigned long
17511offset_prel31 (unsigned long addr, bfd_vma offset)
17512{
17513 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17514}
17515
17516/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17517 relocations. */
17518
17519static void
17520copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17521{
17522 unsigned long first_word = bfd_get_32 (output_bfd, from);
17523 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17524
2468f9c9
PB		 17525 /* High bit of first word is supposed to be zero. */
17526 if ((first_word & 0x80000000ul) == 0)
17527 first_word = offset_prel31 (first_word, offset);
b38cadfb 17528
2468f9c9
PB		 17529 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17530 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17531 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17532 second_word = offset_prel31 (second_word, offset);
b38cadfb 17533
2468f9c9
PB		 17534 bfd_put_32 (output_bfd, first_word, to);
17535 bfd_put_32 (output_bfd, second_word, to + 4);
17536}
e489d0ae 17537
48229727
JB		 17538/* Data for make_branch_to_a8_stub(). */
17539
b38cadfb
NC		 17540struct a8_branch_to_stub_data
17541{
48229727
JB		 17542 asection *writing_section;
17543 bfd_byte *contents;
17544};
17545
17546
17547/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17548 places for a particular section. */
17549
17550static bfd_boolean
17551make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17552 void *in_arg)
48229727
JB		 17553{
17554 struct elf32_arm_stub_hash_entry *stub_entry;
17555 struct a8_branch_to_stub_data *data;
17556 bfd_byte *contents;
17557 unsigned long branch_insn;
17558 bfd_vma veneered_insn_loc, veneer_entry_loc;
17559 bfd_signed_vma branch_offset;
17560 bfd *abfd;
8d9d9490 17561 unsigned int loc;
48229727
JB		 17562
17563 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17564 data = (struct a8_branch_to_stub_data *) in_arg;
17565
17566 if (stub_entry->target_section != data->writing_section
4563a860 17567 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17568 return TRUE;
17569
17570 contents = data->contents;
17571
8d9d9490
TP		 17572 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17573 generated when both source and target are in the same section. */
48229727
JB		 17574 veneered_insn_loc = stub_entry->target_section->output_section->vma
17575 + stub_entry->target_section->output_offset
8d9d9490 17576 + stub_entry->source_value;
48229727
JB		 17577
17578 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17579 + stub_entry->stub_sec->output_offset
17580 + stub_entry->stub_offset;
17581
17582 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17583 veneered_insn_loc &= ~3u;
17584
17585 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17586
17587 abfd = stub_entry->target_section->owner;
8d9d9490 17588 loc = stub_entry->source_value;
48229727
JB		 17589
17590 /* We attempt to avoid this condition by setting stubs_always_after_branch
17591 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17592 This check is just to be on the safe side... */
17593 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17594 {
871b3ab2 17595 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 17596 "allocated in unsafe location"), abfd);
48229727
JB		 17597 return FALSE;
17598 }
17599
17600 switch (stub_entry->stub_type)
17601 {
17602 case arm_stub_a8_veneer_b:
17603 case arm_stub_a8_veneer_b_cond:
17604 branch_insn = 0xf0009000;
17605 goto jump24;
17606
17607 case arm_stub_a8_veneer_blx:
17608 branch_insn = 0xf000e800;
17609 goto jump24;
17610
17611 case arm_stub_a8_veneer_bl:
17612 {
17613 unsigned int i1, j1, i2, j2, s;
17614
17615 branch_insn = 0xf000d000;
17616
17617 jump24:
17618 if (branch_offset < -16777216 || branch_offset > 16777214)
17619 {
17620 /* There's not much we can do apart from complain if this
17621 happens. */
871b3ab2 17622 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 17623 "of range (input file too large)"), abfd);
48229727
JB		 17624 return FALSE;
17625 }
17626
17627 /* i1 = not(j1 eor s), so:
17628 not i1 = j1 eor s
17629 j1 = (not i1) eor s. */
17630
17631 branch_insn |= (branch_offset >> 1) & 0x7ff;
17632 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17633 i2 = (branch_offset >> 22) & 1;
17634 i1 = (branch_offset >> 23) & 1;
17635 s = (branch_offset >> 24) & 1;
17636 j1 = (!i1) ^ s;
17637 j2 = (!i2) ^ s;
17638 branch_insn |= j2 << 11;
17639 branch_insn |= j1 << 13;
17640 branch_insn |= s << 26;
17641 }
17642 break;
17643
17644 default:
17645 BFD_FAIL ();
17646 return FALSE;
17647 }
17648
8d9d9490
TP		 17649 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17650 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17651
17652 return TRUE;
17653}
17654
a504d23a
LA		 17655/* Beginning of stm32l4xx work-around. */
17656
17657/* Functions encoding instructions necessary for the emission of the
17658 fix-stm32l4xx-629360.
17659 Encoding is extracted from the
17660 ARM (C) Architecture Reference Manual
17661 ARMv7-A and ARMv7-R edition
17662 ARM DDI 0406C.b (ID072512). */
17663
17664static inline bfd_vma
82188b29 17665create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17666{
17667 /* A8.8.18 B (A8-334)
17668 B target_address (Encoding T4). */
17669 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17670 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17671 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17672
a504d23a
LA		 17673 int s = ((branch_offset & 0x1000000) >> 24);
17674 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17675 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17676
17677 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17678 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17679
17680 bfd_vma patched_inst = 0xf0009000
17681 | s << 26 /* S. */
17682 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17683 | j1 << 13 /* J1. */
17684 | j2 << 11 /* J2. */
17685 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17686
17687 return patched_inst;
17688}
17689
17690static inline bfd_vma
17691create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17692{
17693 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17694 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17695 bfd_vma patched_inst = 0xe8900000
17696 | (/*W=*/wback << 21)
17697 | (base_reg << 16)
17698 | (reg_mask & 0x0000ffff);
17699
17700 return patched_inst;
17701}
17702
17703static inline bfd_vma
17704create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17705{
17706 /* A8.8.60 LDMDB/LDMEA (A8-402)
17707 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17708 bfd_vma patched_inst = 0xe9100000
17709 | (/*W=*/wback << 21)
17710 | (base_reg << 16)
17711 | (reg_mask & 0x0000ffff);
17712
17713 return patched_inst;
17714}
17715
17716static inline bfd_vma
17717create_instruction_mov (int target_reg, int source_reg)
17718{
17719 /* A8.8.103 MOV (register) (A8-486)
17720 MOV Rd, Rm (Encoding T1). */
17721 bfd_vma patched_inst = 0x4600
17722 | (target_reg & 0x7)
17723 | ((target_reg & 0x8) >> 3) << 7
17724 | (source_reg << 3);
17725
17726 return patched_inst;
17727}
17728
17729static inline bfd_vma
17730create_instruction_sub (int target_reg, int source_reg, int value)
17731{
17732 /* A8.8.221 SUB (immediate) (A8-708)
17733 SUB Rd, Rn, #value (Encoding T3). */
17734 bfd_vma patched_inst = 0xf1a00000
17735 | (target_reg << 8)
17736 | (source_reg << 16)
17737 | (/*S=*/0 << 20)
17738 | ((value & 0x800) >> 11) << 26
17739 | ((value & 0x700) >> 8) << 12
17740 | (value & 0x0ff);
17741
17742 return patched_inst;
17743}
17744
17745static inline bfd_vma
9239bbd3 17746create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17747 int first_reg)
17748{
17749 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17750 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17751 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17752 | (/*W=*/wback << 21)
17753 | (base_reg << 16)
9239bbd3
CM		 17754 | (num_words & 0x000000ff)
17755 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17756 | (first_reg & 0x00000001) << 22;
17757
17758 return patched_inst;
17759}
17760
17761static inline bfd_vma
9239bbd3
CM		 17762create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17763 int first_reg)
a504d23a
LA		 17764{
17765 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17766 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17767 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17768 | (base_reg << 16)
9239bbd3
CM		 17769 | (num_words & 0x000000ff)
17770 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17771 | (first_reg & 0x00000001) << 22;
17772
17773 return patched_inst;
17774}
17775
17776static inline bfd_vma
17777create_instruction_udf_w (int value)
17778{
17779 /* A8.8.247 UDF (A8-758)
17780 Undefined (Encoding T2). */
17781 bfd_vma patched_inst = 0xf7f0a000
17782 | (value & 0x00000fff)
17783 | (value & 0x000f0000) << 16;
17784
17785 return patched_inst;
17786}
17787
17788static inline bfd_vma
17789create_instruction_udf (int value)
17790{
17791 /* A8.8.247 UDF (A8-758)
17792 Undefined (Encoding T1). */
17793 bfd_vma patched_inst = 0xde00
17794 | (value & 0xff);
17795
17796 return patched_inst;
17797}
17798
17799/* Functions writing an instruction in memory, returning the next
17800 memory position to write to. */
17801
17802static inline bfd_byte *
17803push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17804 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17805{
17806 put_thumb2_insn (htab, output_bfd, insn, pt);
17807 return pt + 4;
17808}
17809
17810static inline bfd_byte *
17811push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17812 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17813{
17814 put_thumb_insn (htab, output_bfd, insn, pt);
17815 return pt + 2;
17816}
17817
17818/* Function filling up a region in memory with T1 and T2 UDFs taking
17819 care of alignment. */
17820
17821static bfd_byte *
17822stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 17823 bfd * output_bfd,
17824 const bfd_byte * const base_stub_contents,
17825 bfd_byte * const from_stub_contents,
17826 const bfd_byte * const end_stub_contents)
a504d23a
LA		 17827{
17828 bfd_byte *current_stub_contents = from_stub_contents;
17829
17830 /* Fill the remaining of the stub with deterministic contents : UDF
17831 instructions.
17832 Check if realignment is needed on modulo 4 frontier using T1, to
17833 further use T2. */
17834 if ((current_stub_contents < end_stub_contents)
17835 && !((current_stub_contents - base_stub_contents) % 2)
17836 && ((current_stub_contents - base_stub_contents) % 4))
17837 current_stub_contents =
17838 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17839 create_instruction_udf (0));
17840
17841 for (; current_stub_contents < end_stub_contents;)
17842 current_stub_contents =
17843 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17844 create_instruction_udf_w (0));
17845
17846 return current_stub_contents;
17847}
17848
17849/* Functions writing the stream of instructions equivalent to the
17850 derived sequence for ldmia, ldmdb, vldm respectively. */
17851
17852static void
17853stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17854 bfd * output_bfd,
17855 const insn32 initial_insn,
17856 const bfd_byte *const initial_insn_addr,
17857 bfd_byte *const base_stub_contents)
17858{
17859 int wback = (initial_insn & 0x00200000) >> 21;
17860 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17861 int insn_all_registers = initial_insn & 0x0000ffff;
17862 int insn_low_registers, insn_high_registers;
17863 int usable_register_mask;
b25e998d 17864 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17865 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17866 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17867 bfd_byte *current_stub_contents = base_stub_contents;
17868
17869 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17870
17871 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17872 smaller than 8 registers load sequences that do not cause the
17873 hardware issue. */
17874 if (nb_registers <= 8)
17875 {
17876 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17877 current_stub_contents =
17878 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17879 initial_insn);
17880
17881 /* B initial_insn_addr+4. */
17882 if (!restore_pc)
17883 current_stub_contents =
17884 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17885 create_instruction_branch_absolute
82188b29 17886 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17887
17888 /* Fill the remaining of the stub with deterministic contents. */
17889 current_stub_contents =
17890 stm32l4xx_fill_stub_udf (htab, output_bfd,
17891 base_stub_contents, current_stub_contents,
17892 base_stub_contents +
17893 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17894
17895 return;
17896 }
17897
17898 /* - reg_list[13] == 0. */
17899 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17900
17901 /* - reg_list[14] & reg_list[15] != 1. */
17902 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17903
17904 /* - if (wback==1) reg_list[rn] == 0. */
17905 BFD_ASSERT (!wback || !restore_rn);
17906
17907 /* - nb_registers > 8. */
b25e998d 17908 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17909
17910 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17911
17912 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17913 - One with the 7 lowest registers (register mask 0x007F)
17914 This LDM will finally contain between 2 and 7 registers
17915 - One with the 7 highest registers (register mask 0xDF80)
17916 This ldm will finally contain between 2 and 7 registers. */
17917 insn_low_registers = insn_all_registers & 0x007F;
17918 insn_high_registers = insn_all_registers & 0xDF80;
17919
17920 /* A spare register may be needed during this veneer to temporarily
17921 handle the base register. This register will be restored with the
17922 last LDM operation.
17923 The usable register may be any general purpose register (that
17924 excludes PC, SP, LR : register mask is 0x1FFF). */
17925 usable_register_mask = 0x1FFF;
17926
17927 /* Generate the stub function. */
17928 if (wback)
17929 {
17930 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17931 current_stub_contents =
17932 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17933 create_instruction_ldmia
17934 (rn, /*wback=*/1, insn_low_registers));
17935
17936 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17937 current_stub_contents =
17938 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17939 create_instruction_ldmia
17940 (rn, /*wback=*/1, insn_high_registers));
17941 if (!restore_pc)
17942 {
17943 /* B initial_insn_addr+4. */
17944 current_stub_contents =
17945 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17946 create_instruction_branch_absolute
82188b29 17947 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17948 }
17949 }
17950 else /* if (!wback). */
17951 {
17952 ri = rn;
17953
17954 /* If Rn is not part of the high-register-list, move it there. */
17955 if (!(insn_high_registers & (1 << rn)))
17956 {
17957 /* Choose a Ri in the high-register-list that will be restored. */
17958 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17959
17960 /* MOV Ri, Rn. */
17961 current_stub_contents =
17962 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17963 create_instruction_mov (ri, rn));
17964 }
17965
17966 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
17967 current_stub_contents =
17968 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17969 create_instruction_ldmia
17970 (ri, /*wback=*/1, insn_low_registers));
17971
17972 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
17973 current_stub_contents =
17974 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17975 create_instruction_ldmia
17976 (ri, /*wback=*/0, insn_high_registers));
17977
17978 if (!restore_pc)
17979 {
17980 /* B initial_insn_addr+4. */
17981 current_stub_contents =
17982 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17983 create_instruction_branch_absolute
82188b29 17984 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17985 }
17986 }
17987
17988 /* Fill the remaining of the stub with deterministic contents. */
17989 current_stub_contents =
17990 stm32l4xx_fill_stub_udf (htab, output_bfd,
17991 base_stub_contents, current_stub_contents,
17992 base_stub_contents +
17993 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17994}
17995
17996static void
17997stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
17998 bfd * output_bfd,
17999 const insn32 initial_insn,
18000 const bfd_byte *const initial_insn_addr,
18001 bfd_byte *const base_stub_contents)
18002{
18003 int wback = (initial_insn & 0x00200000) >> 21;
18004 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18005 int insn_all_registers = initial_insn & 0x0000ffff;
18006 int insn_low_registers, insn_high_registers;
18007 int usable_register_mask;
18008 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18009 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18010 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18011 bfd_byte *current_stub_contents = base_stub_contents;
18012
18013 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18014
18015 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18016 smaller than 8 registers load sequences that do not cause the
18017 hardware issue. */
18018 if (nb_registers <= 8)
18019 {
18020 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18021 current_stub_contents =
18022 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18023 initial_insn);
18024
18025 /* B initial_insn_addr+4. */
18026 current_stub_contents =
18027 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18028 create_instruction_branch_absolute
82188b29 18029 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18030
18031 /* Fill the remaining of the stub with deterministic contents. */
18032 current_stub_contents =
18033 stm32l4xx_fill_stub_udf (htab, output_bfd,
18034 base_stub_contents, current_stub_contents,
18035 base_stub_contents +
18036 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18037
18038 return;
18039 }
18040
18041 /* - reg_list[13] == 0. */
18042 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18043
18044 /* - reg_list[14] & reg_list[15] != 1. */
18045 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18046
18047 /* - if (wback==1) reg_list[rn] == 0. */
18048 BFD_ASSERT (!wback || !restore_rn);
18049
18050 /* - nb_registers > 8. */
b25e998d 18051 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18052
18053 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18054
18055 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18056 - One with the 7 lowest registers (register mask 0x007F)
18057 This LDM will finally contain between 2 and 7 registers
18058 - One with the 7 highest registers (register mask 0xDF80)
18059 This ldm will finally contain between 2 and 7 registers. */
18060 insn_low_registers = insn_all_registers & 0x007F;
18061 insn_high_registers = insn_all_registers & 0xDF80;
18062
18063 /* A spare register may be needed during this veneer to temporarily
18064 handle the base register. This register will be restored with
18065 the last LDM operation.
18066 The usable register may be any general purpose register (that excludes
18067 PC, SP, LR : register mask is 0x1FFF). */
18068 usable_register_mask = 0x1FFF;
18069
18070 /* Generate the stub function. */
18071 if (!wback && !restore_pc && !restore_rn)
18072 {
18073 /* Choose a Ri in the low-register-list that will be restored. */
18074 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18075
18076 /* MOV Ri, Rn. */
18077 current_stub_contents =
18078 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18079 create_instruction_mov (ri, rn));
18080
18081 /* LDMDB Ri!, {R-high-register-list}. */
18082 current_stub_contents =
18083 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18084 create_instruction_ldmdb
18085 (ri, /*wback=*/1, insn_high_registers));
18086
18087 /* LDMDB Ri, {R-low-register-list}. */
18088 current_stub_contents =
18089 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18090 create_instruction_ldmdb
18091 (ri, /*wback=*/0, insn_low_registers));
18092
18093 /* B initial_insn_addr+4. */
18094 current_stub_contents =
18095 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18096 create_instruction_branch_absolute
82188b29 18097 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18098 }
18099 else if (wback && !restore_pc && !restore_rn)
18100 {
18101 /* LDMDB Rn!, {R-high-register-list}. */
18102 current_stub_contents =
18103 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18104 create_instruction_ldmdb
18105 (rn, /*wback=*/1, insn_high_registers));
18106
18107 /* LDMDB Rn!, {R-low-register-list}. */
18108 current_stub_contents =
18109 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18110 create_instruction_ldmdb
18111 (rn, /*wback=*/1, insn_low_registers));
18112
18113 /* B initial_insn_addr+4. */
18114 current_stub_contents =
18115 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18116 create_instruction_branch_absolute
82188b29 18117 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18118 }
18119 else if (!wback && restore_pc && !restore_rn)
18120 {
18121 /* Choose a Ri in the high-register-list that will be restored. */
18122 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18123
18124 /* SUB Ri, Rn, #(4*nb_registers). */
18125 current_stub_contents =
18126 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18127 create_instruction_sub (ri, rn, (4 * nb_registers)));
18128
18129 /* LDMIA Ri!, {R-low-register-list}. */
18130 current_stub_contents =
18131 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18132 create_instruction_ldmia
18133 (ri, /*wback=*/1, insn_low_registers));
18134
18135 /* LDMIA Ri, {R-high-register-list}. */
18136 current_stub_contents =
18137 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18138 create_instruction_ldmia
18139 (ri, /*wback=*/0, insn_high_registers));
18140 }
18141 else if (wback && restore_pc && !restore_rn)
18142 {
18143 /* Choose a Ri in the high-register-list that will be restored. */
18144 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18145
18146 /* SUB Rn, Rn, #(4*nb_registers) */
18147 current_stub_contents =
18148 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18149 create_instruction_sub (rn, rn, (4 * nb_registers)));
18150
18151 /* MOV Ri, Rn. */
18152 current_stub_contents =
18153 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18154 create_instruction_mov (ri, rn));
18155
18156 /* LDMIA Ri!, {R-low-register-list}. */
18157 current_stub_contents =
18158 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18159 create_instruction_ldmia
18160 (ri, /*wback=*/1, insn_low_registers));
18161
18162 /* LDMIA Ri, {R-high-register-list}. */
18163 current_stub_contents =
18164 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18165 create_instruction_ldmia
18166 (ri, /*wback=*/0, insn_high_registers));
18167 }
18168 else if (!wback && !restore_pc && restore_rn)
18169 {
18170 ri = rn;
18171 if (!(insn_low_registers & (1 << rn)))
18172 {
18173 /* Choose a Ri in the low-register-list that will be restored. */
18174 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18175
18176 /* MOV Ri, Rn. */
18177 current_stub_contents =
18178 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18179 create_instruction_mov (ri, rn));
18180 }
18181
18182 /* LDMDB Ri!, {R-high-register-list}. */
18183 current_stub_contents =
18184 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18185 create_instruction_ldmdb
18186 (ri, /*wback=*/1, insn_high_registers));
18187
18188 /* LDMDB Ri, {R-low-register-list}. */
18189 current_stub_contents =
18190 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18191 create_instruction_ldmdb
18192 (ri, /*wback=*/0, insn_low_registers));
18193
18194 /* B initial_insn_addr+4. */
18195 current_stub_contents =
18196 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18197 create_instruction_branch_absolute
82188b29 18198 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18199 }
18200 else if (!wback && restore_pc && restore_rn)
18201 {
18202 ri = rn;
18203 if (!(insn_high_registers & (1 << rn)))
18204 {
18205 /* Choose a Ri in the high-register-list that will be restored. */
18206 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18207 }
18208
18209 /* SUB Ri, Rn, #(4*nb_registers). */
18210 current_stub_contents =
18211 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18212 create_instruction_sub (ri, rn, (4 * nb_registers)));
18213
18214 /* LDMIA Ri!, {R-low-register-list}. */
18215 current_stub_contents =
18216 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18217 create_instruction_ldmia
18218 (ri, /*wback=*/1, insn_low_registers));
18219
18220 /* LDMIA Ri, {R-high-register-list}. */
18221 current_stub_contents =
18222 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18223 create_instruction_ldmia
18224 (ri, /*wback=*/0, insn_high_registers));
18225 }
18226 else if (wback && restore_rn)
18227 {
18228 /* The assembler should not have accepted to encode this. */
18229 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18230 "undefined behavior.\n");
18231 }
18232
18233 /* Fill the remaining of the stub with deterministic contents. */
18234 current_stub_contents =
18235 stm32l4xx_fill_stub_udf (htab, output_bfd,
18236 base_stub_contents, current_stub_contents,
18237 base_stub_contents +
18238 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18239
18240}
18241
18242static void
18243stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18244 bfd * output_bfd,
18245 const insn32 initial_insn,
18246 const bfd_byte *const initial_insn_addr,
18247 bfd_byte *const base_stub_contents)
18248{
9239bbd3 18249 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18250 bfd_byte *current_stub_contents = base_stub_contents;
18251
18252 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18253
18254 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18255 smaller than 8 words load sequences that do not cause the
a504d23a 18256 hardware issue. */
9239bbd3 18257 if (num_words <= 8)
a504d23a
LA		 18258 {
18259 /* Untouched instruction. */
18260 current_stub_contents =
18261 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18262 initial_insn);
18263
18264 /* B initial_insn_addr+4. */
18265 current_stub_contents =
18266 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18267 create_instruction_branch_absolute
82188b29 18268 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18269 }
18270 else
18271 {
9eaff861 18272 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18273 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18274 bfd_boolean is_ia_nobang = /* (IA without !). */
18275 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18276 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18277 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18278 bfd_boolean is_db_bang = /* (DB with !). */
18279 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18280 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18281 /* d = UInt (Vd:D);. */
9239bbd3 18282 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18283 | (((unsigned int)initial_insn << 9) >> 31);
18284
9239bbd3
CM		 18285 /* Compute the number of 8-words chunks needed to split. */
18286 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18287 int chunk;
18288
18289 /* The test coverage has been done assuming the following
18290 hypothesis that exactly one of the previous is_ predicates is
18291 true. */
9239bbd3
CM		 18292 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18293 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18294
9239bbd3 18295 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18296 cases, then we emit the adjustments:
18297
18298 vldm rx, {...}
18299 -> vldm rx!, {8_words_or_less} for each needed 8_word
18300 -> sub rx, rx, #size (list)
18301
18302 vldm rx!, {...}
18303 -> vldm rx!, {8_words_or_less} for each needed 8_word
18304 This also handles vpop instruction (when rx is sp)
18305
18306 vldmd rx!, {...}
18307 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18308 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18309 {
9239bbd3
CM		 18310 bfd_vma new_insn = 0;
18311
a504d23a
LA		 18312 if (is_ia_nobang || is_ia_bang)
18313 {
9239bbd3
CM		 18314 new_insn = create_instruction_vldmia
18315 (base_reg,
18316 is_dp,
18317 /*wback= . */1,
18318 chunks - (chunk + 1) ?
18319 8 : num_words - chunk * 8,
18320 first_reg + chunk * 8);
a504d23a
LA		 18321 }
18322 else if (is_db_bang)
18323 {
9239bbd3
CM		 18324 new_insn = create_instruction_vldmdb
18325 (base_reg,
18326 is_dp,
18327 chunks - (chunk + 1) ?
18328 8 : num_words - chunk * 8,
18329 first_reg + chunk * 8);
a504d23a 18330 }
9239bbd3
CM		 18331
18332 if (new_insn)
18333 current_stub_contents =
18334 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18335 new_insn);
a504d23a
LA		 18336 }
18337
18338 /* Only this case requires the base register compensation
18339 subtract. */
18340 if (is_ia_nobang)
18341 {
18342 current_stub_contents =
18343 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18344 create_instruction_sub
9239bbd3 18345 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18346 }
18347
18348 /* B initial_insn_addr+4. */
18349 current_stub_contents =
18350 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18351 create_instruction_branch_absolute
82188b29 18352 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18353 }
18354
18355 /* Fill the remaining of the stub with deterministic contents. */
18356 current_stub_contents =
18357 stm32l4xx_fill_stub_udf (htab, output_bfd,
18358 base_stub_contents, current_stub_contents,
18359 base_stub_contents +
18360 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18361}
18362
18363static void
18364stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18365 bfd * output_bfd,
18366 const insn32 wrong_insn,
18367 const bfd_byte *const wrong_insn_addr,
18368 bfd_byte *const stub_contents)
18369{
18370 if (is_thumb2_ldmia (wrong_insn))
18371 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18372 wrong_insn, wrong_insn_addr,
18373 stub_contents);
18374 else if (is_thumb2_ldmdb (wrong_insn))
18375 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18376 wrong_insn, wrong_insn_addr,
18377 stub_contents);
18378 else if (is_thumb2_vldm (wrong_insn))
18379 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18380 wrong_insn, wrong_insn_addr,
18381 stub_contents);
18382}
18383
18384/* End of stm32l4xx work-around. */
18385
18386
e489d0ae
PB		 18387/* Do code byteswapping. Return FALSE afterwards so that the section is
18388 written out as normal. */
18389
18390static bfd_boolean
c7b8f16e 18391elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18392 struct bfd_link_info *link_info,
18393 asection *sec,
e489d0ae
PB		 18394 bfd_byte *contents)
18395{
48229727 18396 unsigned int mapcount, errcount;
8e3de13a 18397 _arm_elf_section_data *arm_data;
c7b8f16e 18398 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18399 elf32_arm_section_map *map;
c7b8f16e 18400 elf32_vfp11_erratum_list *errnode;
a504d23a 18401 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18402 bfd_vma ptr;
18403 bfd_vma end;
c7b8f16e 18404 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18405 bfd_byte tmp;
48229727 18406 unsigned int i;
57e8b36a 18407
4dfe6ac6
NC		 18408 if (globals == NULL)
18409 return FALSE;
18410
8e3de13a
NC		 18411 /* If this section has not been allocated an _arm_elf_section_data
18412 structure then we cannot record anything. */
18413 arm_data = get_arm_elf_section_data (sec);
18414 if (arm_data == NULL)
18415 return FALSE;
18416
18417 mapcount = arm_data->mapcount;
18418 map = arm_data->map;
c7b8f16e
JB		 18419 errcount = arm_data->erratumcount;
18420
18421 if (errcount != 0)
18422 {
18423 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18424
18425 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18426 errnode = errnode->next)
18427 {
18428 bfd_vma target = errnode->vma - offset;
18429
18430 switch (errnode->type)
18431 {
18432 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18433 {
18434 bfd_vma branch_to_veneer;
18435 /* Original condition code of instruction, plus bit mask for
18436 ARM B instruction. */
18437 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18438 | 0x0a000000;
c7b8f16e
JB		 18439
18440 /* The instruction is before the label. */
91d6fa6a 18441 target -= 4;
c7b8f16e
JB		 18442
18443 /* Above offset included in -4 below. */
18444 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18445 - errnode->vma - 4;
c7b8f16e
JB		 18446
18447 if ((signed) branch_to_veneer < -(1 << 25)
18448 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 18449 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 18450 "range"), output_bfd);
c7b8f16e 18451
99059e56
RM		 18452 insn |= (branch_to_veneer >> 2) & 0xffffff;
18453 contents[endianflip ^ target] = insn & 0xff;
18454 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18455 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18456 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18457 }
18458 break;
c7b8f16e
JB		 18459
18460 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18461 {
18462 bfd_vma branch_from_veneer;
18463 unsigned int insn;
c7b8f16e 18464
99059e56
RM		 18465 /* Take size of veneer into account. */
18466 branch_from_veneer = errnode->u.v.branch->vma
18467 - errnode->vma - 12;
c7b8f16e
JB		 18468
18469 if ((signed) branch_from_veneer < -(1 << 25)
18470 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 18471 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 18472 "range"), output_bfd);
c7b8f16e 18473
99059e56
RM		 18474 /* Original instruction. */
18475 insn = errnode->u.v.branch->u.b.vfp_insn;
18476 contents[endianflip ^ target] = insn & 0xff;
18477 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18478 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18479 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18480
18481 /* Branch back to insn after original insn. */
18482 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18483 contents[endianflip ^ (target + 4)] = insn & 0xff;
18484 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18485 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18486 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18487 }
18488 break;
c7b8f16e 18489
99059e56
RM		 18490 default:
18491 abort ();
18492 }
18493 }
c7b8f16e 18494 }
e489d0ae 18495
a504d23a
LA		 18496 if (arm_data->stm32l4xx_erratumcount != 0)
18497 {
18498 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18499 stm32l4xx_errnode != 0;
18500 stm32l4xx_errnode = stm32l4xx_errnode->next)
18501 {
18502 bfd_vma target = stm32l4xx_errnode->vma - offset;
18503
18504 switch (stm32l4xx_errnode->type)
18505 {
18506 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18507 {
18508 unsigned int insn;
18509 bfd_vma branch_to_veneer =
18510 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18511
18512 if ((signed) branch_to_veneer < -(1 << 24)
18513 || (signed) branch_to_veneer >= (1 << 24))
18514 {
18515 bfd_vma out_of_range =
18516 ((signed) branch_to_veneer < -(1 << 24)) ?
18517 - branch_to_veneer - (1 << 24) :
18518 ((signed) branch_to_veneer >= (1 << 24)) ?
18519 branch_to_veneer - (1 << 24) : 0;
18520
4eca0228 18521 _bfd_error_handler
2dcf00ce 18522 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 18523 "cannot create STM32L4XX veneer; "
18524 "jump out of range by %" PRId64 " bytes; "
18525 "cannot encode branch instruction"),
a504d23a 18526 output_bfd,
2dcf00ce
AM		 18527 (uint64_t) (stm32l4xx_errnode->vma - 4),
18528 (int64_t) out_of_range);
a504d23a
LA		 18529 continue;
18530 }
18531
18532 insn = create_instruction_branch_absolute
82188b29 18533 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18534
18535 /* The instruction is before the label. */
18536 target -= 4;
18537
18538 put_thumb2_insn (globals, output_bfd,
18539 (bfd_vma) insn, contents + target);
18540 }
18541 break;
18542
18543 case STM32L4XX_ERRATUM_VENEER:
18544 {
82188b29
NC		 18545 bfd_byte * veneer;
18546 bfd_byte * veneer_r;
a504d23a
LA		 18547 unsigned int insn;
18548
82188b29
NC		 18549 veneer = contents + target;
18550 veneer_r = veneer
18551 + stm32l4xx_errnode->u.b.veneer->vma
18552 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18553
18554 if ((signed) (veneer_r - veneer -
18555 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18556 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18557 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18558 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18559 || (signed) (veneer_r - veneer) >= (1 << 24))
18560 {
90b6238f
AM		 18561 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
18562 "veneer"), output_bfd);
a504d23a
LA		 18563 continue;
18564 }
18565
18566 /* Original instruction. */
18567 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18568
18569 stm32l4xx_create_replacing_stub
18570 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18571 }
18572 break;
18573
18574 default:
18575 abort ();
18576 }
18577 }
18578 }
18579
2468f9c9
PB		 18580 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18581 {
18582 arm_unwind_table_edit *edit_node
99059e56 18583 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18584 /* Now, sec->size is the size of the section we will write. The original
99059e56 18585 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18586 markers) was sec->rawsize. (This isn't the case if we perform no
18587 edits, then rawsize will be zero and we should use size). */
21d799b5 18588 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18589 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18590 unsigned int in_index, out_index;
18591 bfd_vma add_to_offsets = 0;
18592
18593 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18594 {
2468f9c9
PB		 18595 if (edit_node)
18596 {
18597 unsigned int edit_index = edit_node->index;
b38cadfb 18598
2468f9c9 18599 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18600 {
2468f9c9
PB		 18601 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18602 contents + in_index * 8, add_to_offsets);
18603 out_index++;
18604 in_index++;
18605 }
18606 else if (in_index == edit_index
18607 || (in_index * 8 >= input_size
18608 && edit_index == UINT_MAX))
99059e56 18609 {
2468f9c9
PB		 18610 switch (edit_node->type)
18611 {
18612 case DELETE_EXIDX_ENTRY:
18613 in_index++;
18614 add_to_offsets += 8;
18615 break;
b38cadfb 18616
2468f9c9
PB		 18617 case INSERT_EXIDX_CANTUNWIND_AT_END:
18618 {
99059e56 18619 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18620 bfd_vma text_offset = text_sec->output_section->vma
18621 + text_sec->output_offset
18622 + text_sec->size;
18623 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18624 unsigned long prel31_offset;
2468f9c9
PB		 18625
18626 /* Note: this is meant to be equivalent to an
18627 R_ARM_PREL31 relocation. These synthetic
18628 EXIDX_CANTUNWIND markers are not relocated by the
18629 usual BFD method. */
18630 prel31_offset = (text_offset - exidx_offset)
18631 & 0x7ffffffful;
491d01d3
YU		 18632 if (bfd_link_relocatable (link_info))
18633 {
18634 /* Here relocation for new EXIDX_CANTUNWIND is
18635 created, so there is no need to
18636 adjust offset by hand. */
18637 prel31_offset = text_sec->output_offset
18638 + text_sec->size;
491d01d3 18639 }
2468f9c9
PB		 18640
18641 /* First address we can't unwind. */
18642 bfd_put_32 (output_bfd, prel31_offset,
18643 &edited_contents[out_index * 8]);
18644
18645 /* Code for EXIDX_CANTUNWIND. */
18646 bfd_put_32 (output_bfd, 0x1,
18647 &edited_contents[out_index * 8 + 4]);
18648
18649 out_index++;
18650 add_to_offsets -= 8;
18651 }
18652 break;
18653 }
b38cadfb 18654
2468f9c9
PB		 18655 edit_node = edit_node->next;
18656 }
18657 }
18658 else
18659 {
18660 /* No more edits, copy remaining entries verbatim. */
18661 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18662 contents + in_index * 8, add_to_offsets);
18663 out_index++;
18664 in_index++;
18665 }
18666 }
18667
18668 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18669 bfd_set_section_contents (output_bfd, sec->output_section,
18670 edited_contents,
18671 (file_ptr) sec->output_offset, sec->size);
18672
18673 return TRUE;
18674 }
18675
48229727
JB		 18676 /* Fix code to point to Cortex-A8 erratum stubs. */
18677 if (globals->fix_cortex_a8)
18678 {
18679 struct a8_branch_to_stub_data data;
18680
18681 data.writing_section = sec;
18682 data.contents = contents;
18683
a504d23a
LA		 18684 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18685 & data);
48229727
JB		 18686 }
18687
e489d0ae
PB		 18688 if (mapcount == 0)
18689 return FALSE;
18690
c7b8f16e 18691 if (globals->byteswap_code)
e489d0ae 18692 {
c7b8f16e 18693 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18694
c7b8f16e
JB		 18695 ptr = map[0].vma;
18696 for (i = 0; i < mapcount; i++)
99059e56
RM		 18697 {
18698 if (i == mapcount - 1)
c7b8f16e 18699 end = sec->size;
99059e56
RM		 18700 else
18701 end = map[i + 1].vma;
e489d0ae 18702
99059e56 18703 switch (map[i].type)
e489d0ae 18704 {
c7b8f16e
JB		 18705 case 'a':
18706 /* Byte swap code words. */
18707 while (ptr + 3 < end)
99059e56
RM		 18708 {
18709 tmp = contents[ptr];
18710 contents[ptr] = contents[ptr + 3];
18711 contents[ptr + 3] = tmp;
18712 tmp = contents[ptr + 1];
18713 contents[ptr + 1] = contents[ptr + 2];
18714 contents[ptr + 2] = tmp;
18715 ptr += 4;
18716 }
c7b8f16e 18717 break;
e489d0ae 18718
c7b8f16e
JB		 18719 case 't':
18720 /* Byte swap code halfwords. */
18721 while (ptr + 1 < end)
99059e56
RM		 18722 {
18723 tmp = contents[ptr];
18724 contents[ptr] = contents[ptr + 1];
18725 contents[ptr + 1] = tmp;
18726 ptr += 2;
18727 }
c7b8f16e
JB		 18728 break;
18729
18730 case 'd':
18731 /* Leave data alone. */
18732 break;
18733 }
99059e56
RM		 18734 ptr = end;
18735 }
e489d0ae 18736 }
8e3de13a 18737
93204d3a 18738 free (map);
47b2e99c 18739 arm_data->mapcount = -1;
c7b8f16e 18740 arm_data->mapsize = 0;
8e3de13a 18741 arm_data->map = NULL;
8e3de13a 18742
e489d0ae
PB		 18743 return FALSE;
18744}
18745
0beaef2b
PB		 18746/* Mangle thumb function symbols as we read them in. */
18747
8384fb8f 18748static bfd_boolean
0beaef2b
PB		 18749elf32_arm_swap_symbol_in (bfd * abfd,
18750 const void *psrc,
18751 const void *pshn,
18752 Elf_Internal_Sym *dst)
18753{
4ba2ef8f
TP		 18754 Elf_Internal_Shdr *symtab_hdr;
18755 const char *name = NULL;
18756
8384fb8f
AM		 18757 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18758 return FALSE;
39d911fc 18759 dst->st_target_internal = 0;
0beaef2b
PB		 18760
18761 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18762 the address. */
63e1a0fc
PB		 18763 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18764 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18765 {
63e1a0fc
PB		 18766 if (dst->st_value & 1)
18767 {
18768 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18769 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18770 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18771 }
18772 else
39d911fc 18773 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18774 }
18775 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18776 {
18777 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18778 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18779 }
35fc36a8 18780 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18781 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18782 else
39d911fc 18783 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18784
4ba2ef8f
TP		 18785 /* Mark CMSE special symbols. */
18786 symtab_hdr = & elf_symtab_hdr (abfd);
18787 if (symtab_hdr->sh_size)
18788 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18789 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18790 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18791
8384fb8f 18792 return TRUE;
0beaef2b
PB		 18793}
18794
18795
18796/* Mangle thumb function symbols as we write them out. */
18797
18798static void
18799elf32_arm_swap_symbol_out (bfd *abfd,
18800 const Elf_Internal_Sym *src,
18801 void *cdst,
18802 void *shndx)
18803{
18804 Elf_Internal_Sym newsym;
18805
18806 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18807 of the address set, as per the new EABI. We do this unconditionally
18808 because objcopy does not set the elf header flags until after
18809 it writes out the symbol table. */
39d911fc 18810 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18811 {
18812 newsym = *src;
34e77a92
RS		 18813 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18814 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18815 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18816 {
18817 /* Do this only for defined symbols. At link type, the static
18818 linker will simulate the work of dynamic linker of resolving
18819 symbols and will carry over the thumbness of found symbols to
18820 the output symbol table. It's not clear how it happens, but
18821 the thumbness of undefined symbols can well be different at
18822 runtime, and writing '1' for them will be confusing for users
18823 and possibly for dynamic linker itself.
18824 */
18825 newsym.st_value |= 1;
18826 }
906e58ca 18827
0beaef2b
PB		 18828 src = &newsym;
18829 }
18830 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18831}
18832
b294bdf8
MM		 18833/* Add the PT_ARM_EXIDX program header. */
18834
18835static bfd_boolean
906e58ca 18836elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18837 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18838{
18839 struct elf_segment_map *m;
18840 asection *sec;
18841
18842 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18843 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18844 {
18845 /* If there is already a PT_ARM_EXIDX header, then we do not
18846 want to add another one. This situation arises when running
18847 "strip"; the input binary already has the header. */
12bd6957 18848 m = elf_seg_map (abfd);
b294bdf8
MM		 18849 while (m && m->p_type != PT_ARM_EXIDX)
18850 m = m->next;
18851 if (!m)
18852 {
21d799b5 18853 m = (struct elf_segment_map *)
99059e56 18854 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18855 if (m == NULL)
18856 return FALSE;
18857 m->p_type = PT_ARM_EXIDX;
18858 m->count = 1;
18859 m->sections[0] = sec;
18860
12bd6957
AM		 18861 m->next = elf_seg_map (abfd);
18862 elf_seg_map (abfd) = m;
b294bdf8
MM		 18863 }
18864 }
18865
18866 return TRUE;
18867}
18868
18869/* We may add a PT_ARM_EXIDX program header. */
18870
18871static int
a6b96beb
AM		 18872elf32_arm_additional_program_headers (bfd *abfd,
18873 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18874{
18875 asection *sec;
18876
18877 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18878 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18879 return 1;
18880 else
18881 return 0;
18882}
18883
34e77a92
RS		 18884/* Hook called by the linker routine which adds symbols from an object
18885 file. */
18886
18887static bfd_boolean
18888elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18889 Elf_Internal_Sym *sym, const char **namep,
18890 flagword *flagsp, asection **secp, bfd_vma *valp)
18891{
a43942db 18892 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18893 && (abfd->flags & DYNAMIC) == 0
18894 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18895 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18896
c792917c
NC		 18897 if (elf32_arm_hash_table (info) == NULL)
18898 return FALSE;
18899
34e77a92
RS		 18900 if (elf32_arm_hash_table (info)->vxworks_p
18901 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18902 flagsp, secp, valp))
18903 return FALSE;
18904
18905 return TRUE;
18906}
18907
0beaef2b 18908/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18909const struct elf_size_info elf32_arm_size_info =
18910{
0beaef2b
PB		 18911 sizeof (Elf32_External_Ehdr),
18912 sizeof (Elf32_External_Phdr),
18913 sizeof (Elf32_External_Shdr),
18914 sizeof (Elf32_External_Rel),
18915 sizeof (Elf32_External_Rela),
18916 sizeof (Elf32_External_Sym),
18917 sizeof (Elf32_External_Dyn),
18918 sizeof (Elf_External_Note),
18919 4,
18920 1,
18921 32, 2,
18922 ELFCLASS32, EV_CURRENT,
18923 bfd_elf32_write_out_phdrs,
18924 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18925 bfd_elf32_checksum_contents,
0beaef2b
PB		 18926 bfd_elf32_write_relocs,
18927 elf32_arm_swap_symbol_in,
18928 elf32_arm_swap_symbol_out,
18929 bfd_elf32_slurp_reloc_table,
18930 bfd_elf32_slurp_symbol_table,
18931 bfd_elf32_swap_dyn_in,
18932 bfd_elf32_swap_dyn_out,
18933 bfd_elf32_swap_reloc_in,
18934 bfd_elf32_swap_reloc_out,
18935 bfd_elf32_swap_reloca_in,
18936 bfd_elf32_swap_reloca_out
18937};
18938
685e70ae
VK		 18939static bfd_vma
18940read_code32 (const bfd *abfd, const bfd_byte *addr)
18941{
18942 /* V7 BE8 code is always little endian. */
18943 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18944 return bfd_getl32 (addr);
18945
18946 return bfd_get_32 (abfd, addr);
18947}
18948
18949static bfd_vma
18950read_code16 (const bfd *abfd, const bfd_byte *addr)
18951{
18952 /* V7 BE8 code is always little endian. */
18953 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18954 return bfd_getl16 (addr);
18955
18956 return bfd_get_16 (abfd, addr);
18957}
18958
6a631e86
YG		 18959/* Return size of plt0 entry starting at ADDR
18960 or (bfd_vma) -1 if size can not be determined. */
18961
18962static bfd_vma
18963elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
18964{
18965 bfd_vma first_word;
18966 bfd_vma plt0_size;
18967
685e70ae 18968 first_word = read_code32 (abfd, addr);
6a631e86
YG		 18969
18970 if (first_word == elf32_arm_plt0_entry[0])
18971 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
18972 else if (first_word == elf32_thumb2_plt0_entry[0])
18973 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
18974 else
18975 /* We don't yet handle this PLT format. */
18976 return (bfd_vma) -1;
18977
18978 return plt0_size;
18979}
18980
18981/* Return size of plt entry starting at offset OFFSET
18982 of plt section located at address START
18983 or (bfd_vma) -1 if size can not be determined. */
18984
18985static bfd_vma
18986elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
18987{
18988 bfd_vma first_insn;
18989 bfd_vma plt_size = 0;
18990 const bfd_byte *addr = start + offset;
18991
18992 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 18993 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 18994 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
18995
18996 /* Respect Thumb stub if necessary. */
685e70ae 18997 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 18998 {
18999 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19000 }
19001
19002 /* Strip immediate from first add. */
685e70ae 19003 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19004
19005#ifdef FOUR_WORD_PLT
19006 if (first_insn == elf32_arm_plt_entry[0])
19007 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19008#else
19009 if (first_insn == elf32_arm_plt_entry_long[0])
19010 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19011 else if (first_insn == elf32_arm_plt_entry_short[0])
19012 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19013#endif
19014 else
19015 /* We don't yet handle this PLT format. */
19016 return (bfd_vma) -1;
19017
19018 return plt_size;
19019}
19020
19021/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19022
19023static long
19024elf32_arm_get_synthetic_symtab (bfd *abfd,
19025 long symcount ATTRIBUTE_UNUSED,
19026 asymbol **syms ATTRIBUTE_UNUSED,
19027 long dynsymcount,
19028 asymbol **dynsyms,
19029 asymbol **ret)
19030{
19031 asection *relplt;
19032 asymbol *s;
19033 arelent *p;
19034 long count, i, n;
19035 size_t size;
19036 Elf_Internal_Shdr *hdr;
19037 char *names;
19038 asection *plt;
19039 bfd_vma offset;
19040 bfd_byte *data;
19041
19042 *ret = NULL;
19043
19044 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19045 return 0;
19046
19047 if (dynsymcount <= 0)
19048 return 0;
19049
19050 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19051 if (relplt == NULL)
19052 return 0;
19053
19054 hdr = &elf_section_data (relplt)->this_hdr;
19055 if (hdr->sh_link != elf_dynsymtab (abfd)
19056 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19057 return 0;
19058
19059 plt = bfd_get_section_by_name (abfd, ".plt");
19060 if (plt == NULL)
19061 return 0;
19062
19063 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19064 return -1;
19065
19066 data = plt->contents;
19067 if (data == NULL)
19068 {
19069 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19070 return -1;
19071 bfd_cache_section_contents((asection *) plt, data);
19072 }
19073
19074 count = relplt->size / hdr->sh_entsize;
19075 size = count * sizeof (asymbol);
19076 p = relplt->relocation;
19077 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19078 {
19079 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19080 if (p->addend != 0)
19081 size += sizeof ("+0x") - 1 + 8;
19082 }
19083
19084 s = *ret = (asymbol *) bfd_malloc (size);
19085 if (s == NULL)
19086 return -1;
19087
19088 offset = elf32_arm_plt0_size (abfd, data);
19089 if (offset == (bfd_vma) -1)
19090 return -1;
19091
19092 names = (char *) (s + count);
19093 p = relplt->relocation;
19094 n = 0;
19095 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19096 {
19097 size_t len;
19098
19099 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19100 if (plt_size == (bfd_vma) -1)
19101 break;
19102
19103 *s = **p->sym_ptr_ptr;
19104 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19105 we are defining a symbol, ensure one of them is set. */
19106 if ((s->flags & BSF_LOCAL) == 0)
19107 s->flags |= BSF_GLOBAL;
19108 s->flags |= BSF_SYNTHETIC;
19109 s->section = plt;
19110 s->value = offset;
19111 s->name = names;
19112 s->udata.p = NULL;
19113 len = strlen ((*p->sym_ptr_ptr)->name);
19114 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19115 names += len;
19116 if (p->addend != 0)
19117 {
19118 char buf[30], *a;
19119
19120 memcpy (names, "+0x", sizeof ("+0x") - 1);
19121 names += sizeof ("+0x") - 1;
19122 bfd_sprintf_vma (abfd, buf, p->addend);
19123 for (a = buf; *a == '0'; ++a)
19124 ;
19125 len = strlen (a);
19126 memcpy (names, a, len);
19127 names += len;
19128 }
19129 memcpy (names, "@plt", sizeof ("@plt"));
19130 names += sizeof ("@plt");
19131 ++s, ++n;
19132 offset += plt_size;
19133 }
19134
19135 return n;
19136}
19137
ac4c9b04
MG		 19138static bfd_boolean
19139elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19140{
f0728ee3
AV		 19141 if (hdr->sh_flags & SHF_ARM_PURECODE)
19142 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19143 return TRUE;
19144}
19145
19146static flagword
19147elf32_arm_lookup_section_flags (char *flag_name)
19148{
f0728ee3
AV		 19149 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19150 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19151
19152 return SEC_NO_FLAGS;
19153}
19154
491d01d3
YU		 19155static unsigned int
19156elf32_arm_count_additional_relocs (asection *sec)
19157{
19158 struct _arm_elf_section_data *arm_data;
19159 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19160
6342be70 19161 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19162}
19163
5522f910 19164/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19165 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19166 FALSE otherwise. ISECTION is the best guess matching section from the
19167 input bfd IBFD, but it might be NULL. */
19168
19169static bfd_boolean
19170elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19171 bfd *obfd ATTRIBUTE_UNUSED,
19172 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19173 Elf_Internal_Shdr *osection)
19174{
19175 switch (osection->sh_type)
19176 {
19177 case SHT_ARM_EXIDX:
19178 {
19179 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19180 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19181 unsigned i = 0;
19182
19183 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19184 osection->sh_info = 0;
19185
19186 /* The sh_link field must be set to the text section associated with
19187 this index section. Unfortunately the ARM EHABI does not specify
19188 exactly how to determine this association. Our caller does try
19189 to match up OSECTION with its corresponding input section however
19190 so that is a good first guess. */
19191 if (isection != NULL
19192 && osection->bfd_section != NULL
19193 && isection->bfd_section != NULL
19194 && isection->bfd_section->output_section != NULL
19195 && isection->bfd_section->output_section == osection->bfd_section
19196 && iheaders != NULL
19197 && isection->sh_link > 0
19198 && isection->sh_link < elf_numsections (ibfd)
19199 && iheaders[isection->sh_link]->bfd_section != NULL
19200 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19201 )
19202 {
19203 for (i = elf_numsections (obfd); i-- > 0;)
19204 if (oheaders[i]->bfd_section
19205 == iheaders[isection->sh_link]->bfd_section->output_section)
19206 break;
19207 }
9eaff861 19208
5522f910
NC		 19209 if (i == 0)
19210 {
19211 /* Failing that we have to find a matching section ourselves. If
19212 we had the output section name available we could compare that
19213 with input section names. Unfortunately we don't. So instead
19214 we use a simple heuristic and look for the nearest executable
19215 section before this one. */
19216 for (i = elf_numsections (obfd); i-- > 0;)
19217 if (oheaders[i] == osection)
19218 break;
19219 if (i == 0)
19220 break;
19221
19222 while (i-- > 0)
19223 if (oheaders[i]->sh_type == SHT_PROGBITS
19224 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19225 == (SHF_ALLOC | SHF_EXECINSTR))
19226 break;
19227 }
19228
19229 if (i)
19230 {
19231 osection->sh_link = i;
19232 /* If the text section was part of a group
19233 then the index section should be too. */
19234 if (oheaders[i]->sh_flags & SHF_GROUP)
19235 osection->sh_flags |= SHF_GROUP;
19236 return TRUE;
19237 }
19238 }
19239 break;
19240
19241 case SHT_ARM_PREEMPTMAP:
19242 osection->sh_flags = SHF_ALLOC;
19243 break;
19244
19245 case SHT_ARM_ATTRIBUTES:
19246 case SHT_ARM_DEBUGOVERLAY:
19247 case SHT_ARM_OVERLAYSECTION:
19248 default:
19249 break;
19250 }
19251
19252 return FALSE;
19253}
19254
d691934d
NC		 19255/* Returns TRUE if NAME is an ARM mapping symbol.
19256 Traditionally the symbols $a, $d and $t have been used.
19257 The ARM ELF standard also defines $x (for A64 code). It also allows a
19258 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19259 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19260 not support them here. $t.x indicates the start of ThumbEE instructions. */
19261
19262static bfd_boolean
19263is_arm_mapping_symbol (const char * name)
19264{
19265 return name != NULL /* Paranoia. */
19266 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19267 the mapping symbols could have acquired a prefix.
19268 We do not support this here, since such symbols no
19269 longer conform to the ARM ELF ABI. */
19270 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19271 && (name[2] == 0 || name[2] == '.');
19272 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19273 any characters that follow the period are legal characters for the body
19274 of a symbol's name. For now we just assume that this is the case. */
19275}
19276
fca2a38f
NC		 19277/* Make sure that mapping symbols in object files are not removed via the
19278 "strip --strip-unneeded" tool. These symbols are needed in order to
19279 correctly generate interworking veneers, and for byte swapping code
19280 regions. Once an object file has been linked, it is safe to remove the
19281 symbols as they will no longer be needed. */
19282
19283static void
19284elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19285{
19286 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19287 && sym->section != bfd_abs_section_ptr
d691934d 19288 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19289 sym->flags |= BSF_KEEP;
19290}
19291
5522f910
NC		 19292#undef elf_backend_copy_special_section_fields
19293#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19294
252b5132 19295#define ELF_ARCH bfd_arch_arm
ae95ffa6 19296#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19297#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19298#ifdef __QNXTARGET__
19299#define ELF_MAXPAGESIZE 0x1000
19300#else
7572ca89 19301#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19302#endif
b1342370 19303#define ELF_MINPAGESIZE 0x1000
24718e3b 19304#define ELF_COMMONPAGESIZE 0x1000
252b5132 19305
07d6d2b8 19306#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 19307
99e4ae17
AJ		 19308#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19309#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19310#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19311#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 19312#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19313#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19314#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 19315#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
19316#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19317#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19318#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19319#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 19320#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 19321
07d6d2b8
AM		 19322#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19323#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19324#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 19325#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19326#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19327#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19328#define elf_backend_write_section elf32_arm_write_section
252b5132 19329#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 19330#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19331#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19332#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19333#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19334#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19335#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19336#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19337#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19338#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 19339#define elf_backend_fake_sections elf32_arm_fake_sections
19340#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
19341#define elf_backend_final_write_processing elf32_arm_final_write_processing
19342#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19343#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19344#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 19345#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19346#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19347#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 19348#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19349#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19350#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19351#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19352
19353#define elf_backend_can_refcount 1
19354#define elf_backend_can_gc_sections 1
19355#define elf_backend_plt_readonly 1
19356#define elf_backend_want_got_plt 1
19357#define elf_backend_want_plt_sym 0
5474d94f 19358#define elf_backend_want_dynrelro 1
906e58ca
NC		 19359#define elf_backend_may_use_rel_p 1
19360#define elf_backend_may_use_rela_p 0
4e7fd91e 19361#define elf_backend_default_use_rela_p 0
64f52338 19362#define elf_backend_dtrel_excludes_plt 1
252b5132 19363
04f7c78d 19364#define elf_backend_got_header_size 12
b68a20d6 19365#define elf_backend_extern_protected_data 1
04f7c78d 19366
07d6d2b8 19367#undef elf_backend_obj_attrs_vendor
906e58ca 19368#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 19369#undef elf_backend_obj_attrs_section
906e58ca 19370#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 19371#undef elf_backend_obj_attrs_arg_type
906e58ca 19372#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 19373#undef elf_backend_obj_attrs_section_type
104d59d1 19374#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 19375#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 19376#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19377
07d6d2b8 19378#undef elf_backend_section_flags
ac4c9b04 19379#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 19380#undef elf_backend_lookup_section_flags_hook
19381#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 19382
a2f63b2e
MR		 19383#define elf_backend_linux_prpsinfo32_ugid16 TRUE
19384
252b5132 19385#include "elf32-target.h"
7f266840 19386
b38cadfb
NC		 19387/* Native Client targets. */
19388
19389#undef TARGET_LITTLE_SYM
6d00b590 19390#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19391#undef TARGET_LITTLE_NAME
19392#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19393#undef TARGET_BIG_SYM
6d00b590 19394#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19395#undef TARGET_BIG_NAME
19396#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19397
19398/* Like elf32_arm_link_hash_table_create -- but overrides
19399 appropriately for NaCl. */
19400
19401static struct bfd_link_hash_table *
19402elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19403{
19404 struct bfd_link_hash_table *ret;
19405
19406 ret = elf32_arm_link_hash_table_create (abfd);
19407 if (ret)
19408 {
19409 struct elf32_arm_link_hash_table *htab
19410 = (struct elf32_arm_link_hash_table *) ret;
19411
19412 htab->nacl_p = 1;
19413
19414 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19415 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19416 }
19417 return ret;
19418}
19419
19420/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19421 really need to use elf32_arm_modify_segment_map. But we do it
19422 anyway just to reduce gratuitous differences with the stock ARM backend. */
19423
19424static bfd_boolean
19425elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19426{
19427 return (elf32_arm_modify_segment_map (abfd, info)
19428 && nacl_modify_segment_map (abfd, info));
19429}
19430
887badb3
RM		 19431static void
19432elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19433{
19434 elf32_arm_final_write_processing (abfd, linker);
19435 nacl_final_write_processing (abfd, linker);
19436}
19437
6a631e86
YG		 19438static bfd_vma
19439elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19440 const arelent *rel ATTRIBUTE_UNUSED)
19441{
19442 return plt->vma
19443 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19444 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19445}
887badb3 19446
b38cadfb 19447#undef elf32_bed
6a631e86 19448#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19449#undef bfd_elf32_bfd_link_hash_table_create
19450#define bfd_elf32_bfd_link_hash_table_create \
19451 elf32_arm_nacl_link_hash_table_create
19452#undef elf_backend_plt_alignment
6a631e86 19453#define elf_backend_plt_alignment 4
b38cadfb
NC		 19454#undef elf_backend_modify_segment_map
19455#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19456#undef elf_backend_modify_program_headers
19457#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19458#undef elf_backend_final_write_processing
19459#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19460#undef bfd_elf32_get_synthetic_symtab
19461#undef elf_backend_plt_sym_val
19462#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19463#undef elf_backend_copy_special_section_fields
b38cadfb 19464
887badb3
RM		 19465#undef ELF_MINPAGESIZE
19466#undef ELF_COMMONPAGESIZE
19467
b38cadfb
NC		 19468
19469#include "elf32-target.h"
19470
19471/* Reset to defaults. */
19472#undef elf_backend_plt_alignment
19473#undef elf_backend_modify_segment_map
19474#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19475#undef elf_backend_modify_program_headers
887badb3
RM		 19476#undef elf_backend_final_write_processing
19477#define elf_backend_final_write_processing elf32_arm_final_write_processing
19478#undef ELF_MINPAGESIZE
19479#define ELF_MINPAGESIZE 0x1000
19480#undef ELF_COMMONPAGESIZE
19481#define ELF_COMMONPAGESIZE 0x1000
19482
b38cadfb 19483
617a5ada
CL		 19484/* FDPIC Targets. */
19485
19486#undef TARGET_LITTLE_SYM
19487#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
19488#undef TARGET_LITTLE_NAME
19489#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
19490#undef TARGET_BIG_SYM
19491#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
19492#undef TARGET_BIG_NAME
19493#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
19494#undef elf_match_priority
19495#define elf_match_priority 128
18a20338
CL		 19496#undef ELF_OSABI
19497#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 19498
19499/* Like elf32_arm_link_hash_table_create -- but overrides
19500 appropriately for FDPIC. */
19501
19502static struct bfd_link_hash_table *
19503elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
19504{
19505 struct bfd_link_hash_table *ret;
19506
19507 ret = elf32_arm_link_hash_table_create (abfd);
19508 if (ret)
19509 {
19510 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
19511
19512 htab->fdpic_p = 1;
19513 }
19514 return ret;
19515}
19516
19517#undef elf32_bed
19518#define elf32_bed elf32_arm_fdpic_bed
19519
19520#undef bfd_elf32_bfd_link_hash_table_create
19521#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
19522
19523#include "elf32-target.h"
19524#undef elf_match_priority
18a20338 19525#undef ELF_OSABI
617a5ada 19526
906e58ca 19527/* VxWorks Targets. */
4e7fd91e 19528
07d6d2b8
AM		 19529#undef TARGET_LITTLE_SYM
19530#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
19531#undef TARGET_LITTLE_NAME
19532#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
19533#undef TARGET_BIG_SYM
19534#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
19535#undef TARGET_BIG_NAME
19536#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 19537
19538/* Like elf32_arm_link_hash_table_create -- but overrides
19539 appropriately for VxWorks. */
906e58ca 19540
4e7fd91e
PB		 19541static struct bfd_link_hash_table *
19542elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19543{
19544 struct bfd_link_hash_table *ret;
19545
19546 ret = elf32_arm_link_hash_table_create (abfd);
19547 if (ret)
19548 {
19549 struct elf32_arm_link_hash_table *htab
00a97672 19550 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19551 htab->use_rel = 0;
00a97672 19552 htab->vxworks_p = 1;
4e7fd91e
PB		 19553 }
19554 return ret;
906e58ca 19555}
4e7fd91e 19556
00a97672
RS		 19557static void
19558elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19559{
19560 elf32_arm_final_write_processing (abfd, linker);
19561 elf_vxworks_final_write_processing (abfd, linker);
19562}
19563
906e58ca 19564#undef elf32_bed
4e7fd91e
PB		 19565#define elf32_bed elf32_arm_vxworks_bed
19566
906e58ca
NC		 19567#undef bfd_elf32_bfd_link_hash_table_create
19568#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19569#undef elf_backend_final_write_processing
19570#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19571#undef elf_backend_emit_relocs
9eaff861 19572#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19573
906e58ca 19574#undef elf_backend_may_use_rel_p
00a97672 19575#define elf_backend_may_use_rel_p 0
906e58ca 19576#undef elf_backend_may_use_rela_p
00a97672 19577#define elf_backend_may_use_rela_p 1
906e58ca 19578#undef elf_backend_default_use_rela_p
00a97672 19579#define elf_backend_default_use_rela_p 1
906e58ca 19580#undef elf_backend_want_plt_sym
00a97672 19581#define elf_backend_want_plt_sym 1
906e58ca 19582#undef ELF_MAXPAGESIZE
00a97672 19583#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19584
19585#include "elf32-target.h"
19586
19587
21d799b5
NC		 19588/* Merge backend specific data from an object file to the output
19589 object file when linking. */
19590
19591static bfd_boolean
50e03d47 19592elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 19593{
50e03d47 19594 bfd *obfd = info->output_bfd;
21d799b5
NC		 19595 flagword out_flags;
19596 flagword in_flags;
19597 bfd_boolean flags_compatible = TRUE;
19598 asection *sec;
19599
cc643b88 19600 /* Check if we have the same endianness. */
50e03d47 19601 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 19602 return FALSE;
19603
19604 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19605 return TRUE;
19606
50e03d47 19607 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 19608 return FALSE;
19609
19610 /* The input BFD must have had its flags initialised. */
19611 /* The following seems bogus to me -- The flags are initialized in
19612 the assembler but I don't think an elf_flags_init field is
19613 written into the object. */
19614 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19615
19616 in_flags = elf_elfheader (ibfd)->e_flags;
19617 out_flags = elf_elfheader (obfd)->e_flags;
19618
19619 /* In theory there is no reason why we couldn't handle this. However
19620 in practice it isn't even close to working and there is no real
19621 reason to want it. */
19622 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19623 && !(ibfd->flags & DYNAMIC)
19624 && (in_flags & EF_ARM_BE8))
19625 {
871b3ab2 19626 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 19627 ibfd);
19628 return FALSE;
19629 }
19630
19631 if (!elf_flags_init (obfd))
19632 {
19633 /* If the input is the default architecture and had the default
19634 flags then do not bother setting the flags for the output
19635 architecture, instead allow future merges to do this. If no
19636 future merges ever set these flags then they will retain their
99059e56
RM		 19637 uninitialised values, which surprise surprise, correspond
19638 to the default values. */
21d799b5
NC		 19639 if (bfd_get_arch_info (ibfd)->the_default
19640 && elf_elfheader (ibfd)->e_flags == 0)
19641 return TRUE;
19642
19643 elf_flags_init (obfd) = TRUE;
19644 elf_elfheader (obfd)->e_flags = in_flags;
19645
19646 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19647 && bfd_get_arch_info (obfd)->the_default)
19648 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19649
19650 return TRUE;
19651 }
19652
19653 /* Determine what should happen if the input ARM architecture
19654 does not match the output ARM architecture. */
19655 if (! bfd_arm_merge_machines (ibfd, obfd))
19656 return FALSE;
19657
19658 /* Identical flags must be compatible. */
19659 if (in_flags == out_flags)
19660 return TRUE;
19661
19662 /* Check to see if the input BFD actually contains any sections. If
19663 not, its flags may not have been initialised either, but it
19664 cannot actually cause any incompatiblity. Do not short-circuit
19665 dynamic objects; their section list may be emptied by
19666 elf_link_add_object_symbols.
19667
19668 Also check to see if there are no code sections in the input.
19669 In this case there is no need to check for code specific flags.
19670 XXX - do we need to worry about floating-point format compatability
19671 in data sections ? */
19672 if (!(ibfd->flags & DYNAMIC))
19673 {
19674 bfd_boolean null_input_bfd = TRUE;
19675 bfd_boolean only_data_sections = TRUE;
19676
19677 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19678 {
19679 /* Ignore synthetic glue sections. */
19680 if (strcmp (sec->name, ".glue_7")
19681 && strcmp (sec->name, ".glue_7t"))
19682 {
19683 if ((bfd_get_section_flags (ibfd, sec)
19684 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19685 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19686 only_data_sections = FALSE;
21d799b5
NC		 19687
19688 null_input_bfd = FALSE;
19689 break;
19690 }
19691 }
19692
19693 if (null_input_bfd || only_data_sections)
19694 return TRUE;
19695 }
19696
19697 /* Complain about various flag mismatches. */
19698 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19699 EF_ARM_EABI_VERSION (out_flags)))
19700 {
19701 _bfd_error_handler
90b6238f 19702 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 19703 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
19704 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 19705 return FALSE;
19706 }
19707
19708 /* Not sure what needs to be checked for EABI versions >= 1. */
19709 /* VxWorks libraries do not use these flags. */
19710 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19711 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19712 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19713 {
19714 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19715 {
19716 _bfd_error_handler
871b3ab2 19717 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 19718 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
19719 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 19720 flags_compatible = FALSE;
19721 }
19722
19723 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19724 {
19725 if (in_flags & EF_ARM_APCS_FLOAT)
19726 _bfd_error_handler
871b3ab2 19727 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 19728 ibfd, obfd);
19729 else
19730 _bfd_error_handler
871b3ab2 19731 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 19732 ibfd, obfd);
19733
19734 flags_compatible = FALSE;
19735 }
19736
19737 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19738 {
19739 if (in_flags & EF_ARM_VFP_FLOAT)
19740 _bfd_error_handler
90b6238f
AM		 19741 (_("error: %pB uses %s instructions, whereas %pB does not"),
19742 ibfd, "VFP", obfd);
21d799b5
NC		 19743 else
19744 _bfd_error_handler
90b6238f
AM		 19745 (_("error: %pB uses %s instructions, whereas %pB does not"),
19746 ibfd, "FPA", obfd);
21d799b5
NC		 19747
19748 flags_compatible = FALSE;
19749 }
19750
19751 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19752 {
19753 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19754 _bfd_error_handler
90b6238f
AM		 19755 (_("error: %pB uses %s instructions, whereas %pB does not"),
19756 ibfd, "Maverick", obfd);
21d799b5
NC		 19757 else
19758 _bfd_error_handler
90b6238f
AM		 19759 (_("error: %pB does not use %s instructions, whereas %pB does"),
19760 ibfd, "Maverick", obfd);
21d799b5
NC		 19761
19762 flags_compatible = FALSE;
19763 }
19764
19765#ifdef EF_ARM_SOFT_FLOAT
19766 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19767 {
19768 /* We can allow interworking between code that is VFP format
19769 layout, and uses either soft float or integer regs for
19770 passing floating point arguments and results. We already
19771 know that the APCS_FLOAT flags match; similarly for VFP
19772 flags. */
19773 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19774 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19775 {
19776 if (in_flags & EF_ARM_SOFT_FLOAT)
19777 _bfd_error_handler
871b3ab2 19778 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 19779 ibfd, obfd);
19780 else
19781 _bfd_error_handler
871b3ab2 19782 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 19783 ibfd, obfd);
19784
19785 flags_compatible = FALSE;
19786 }
19787 }
19788#endif
19789
19790 /* Interworking mismatch is only a warning. */
19791 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19792 {
19793 if (in_flags & EF_ARM_INTERWORK)
19794 {
19795 _bfd_error_handler
90b6238f 19796 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 19797 ibfd, obfd);
19798 }
19799 else
19800 {
19801 _bfd_error_handler
90b6238f 19802 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 19803 ibfd, obfd);
19804 }
19805 }
19806 }
19807
19808 return flags_compatible;
19809}
19810
19811
906e58ca 19812/* Symbian OS Targets. */
7f266840 19813
07d6d2b8
AM		 19814#undef TARGET_LITTLE_SYM
19815#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
19816#undef TARGET_LITTLE_NAME
19817#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
19818#undef TARGET_BIG_SYM
19819#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
19820#undef TARGET_BIG_NAME
19821#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 19822
19823/* Like elf32_arm_link_hash_table_create -- but overrides
19824 appropriately for Symbian OS. */
906e58ca 19825
7f266840
DJ		 19826static struct bfd_link_hash_table *
19827elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19828{
19829 struct bfd_link_hash_table *ret;
19830
19831 ret = elf32_arm_link_hash_table_create (abfd);
19832 if (ret)
19833 {
19834 struct elf32_arm_link_hash_table *htab
19835 = (struct elf32_arm_link_hash_table *)ret;
19836 /* There is no PLT header for Symbian OS. */
19837 htab->plt_header_size = 0;
95720a86
DJ		 19838 /* The PLT entries are each one instruction and one word. */
19839 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19840 htab->symbian_p = 1;
33bfe774
JB		 19841 /* Symbian uses armv5t or above, so use_blx is always true. */
19842 htab->use_blx = 1;
67687978 19843 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19844 }
19845 return ret;
906e58ca 19846}
7f266840 19847
b35d266b 19848static const struct bfd_elf_special_section
551b43fd 19849elf32_arm_symbian_special_sections[] =
7f266840 19850{
5cd3778d
MM		 19851 /* In a BPABI executable, the dynamic linking sections do not go in
19852 the loadable read-only segment. The post-linker may wish to
19853 refer to these sections, but they are not part of the final
19854 program image. */
07d6d2b8
AM		 19855 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19856 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19857 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19858 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19859 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19860 /* These sections do not need to be writable as the SymbianOS
19861 postlinker will arrange things so that no dynamic relocation is
19862 required. */
07d6d2b8
AM		 19863 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19864 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 19865 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 19866 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19867};
19868
c3c76620 19869static void
906e58ca 19870elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19871 struct bfd_link_info *link_info)
c3c76620
MM		 19872{
19873 /* BPABI objects are never loaded directly by an OS kernel; they are
19874 processed by a postlinker first, into an OS-specific format. If
19875 the D_PAGED bit is set on the file, BFD will align segments on
19876 page boundaries, so that an OS can directly map the file. With
19877 BPABI objects, that just results in wasted space. In addition,
19878 because we clear the D_PAGED bit, map_sections_to_segments will
19879 recognize that the program headers should not be mapped into any
19880 loadable segment. */
19881 abfd->flags &= ~D_PAGED;
906e58ca 19882 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19883}
7f266840
DJ		 19884
19885static bfd_boolean
906e58ca 19886elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19887 struct bfd_link_info *info)
7f266840
DJ		 19888{
19889 struct elf_segment_map *m;
19890 asection *dynsec;
19891
7f266840
DJ		 19892 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19893 segment. However, because the .dynamic section is not marked
19894 with SEC_LOAD, the generic ELF code will not create such a
19895 segment. */
19896 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19897 if (dynsec)
19898 {
12bd6957 19899 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19900 if (m->p_type == PT_DYNAMIC)
19901 break;
19902
19903 if (m == NULL)
19904 {
19905 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19906 m->next = elf_seg_map (abfd);
19907 elf_seg_map (abfd) = m;
8ded5a0f 19908 }
7f266840
DJ		 19909 }
19910
b294bdf8
MM		 19911 /* Also call the generic arm routine. */
19912 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19913}
19914
95720a86
DJ		 19915/* Return address for Ith PLT stub in section PLT, for relocation REL
19916 or (bfd_vma) -1 if it should not be included. */
19917
19918static bfd_vma
19919elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19920 const arelent *rel ATTRIBUTE_UNUSED)
19921{
19922 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19923}
19924
8029a119 19925#undef elf32_bed
7f266840
DJ		 19926#define elf32_bed elf32_arm_symbian_bed
19927
19928/* The dynamic sections are not allocated on SymbianOS; the postlinker
19929 will process them and then discard them. */
906e58ca 19930#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19931#define ELF_DYNAMIC_SEC_FLAGS \
19932 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19933
9eaff861 19934#undef elf_backend_emit_relocs
c3c76620 19935
906e58ca
NC		 19936#undef bfd_elf32_bfd_link_hash_table_create
19937#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19938#undef elf_backend_special_sections
07d6d2b8 19939#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 19940#undef elf_backend_begin_write_processing
19941#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19942#undef elf_backend_final_write_processing
19943#define elf_backend_final_write_processing elf32_arm_final_write_processing
19944
19945#undef elf_backend_modify_segment_map
7f266840
DJ		 19946#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19947
19948/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19949#undef elf_backend_got_header_size
7f266840
DJ		 19950#define elf_backend_got_header_size 0
19951
19952/* Similarly, there is no .got.plt section. */
906e58ca 19953#undef elf_backend_want_got_plt
7f266840
DJ		 19954#define elf_backend_want_got_plt 0
19955
906e58ca 19956#undef elf_backend_plt_sym_val
95720a86
DJ		 19957#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19958
906e58ca 19959#undef elf_backend_may_use_rel_p
00a97672 19960#define elf_backend_may_use_rel_p 1
906e58ca 19961#undef elf_backend_may_use_rela_p
00a97672 19962#define elf_backend_may_use_rela_p 0
906e58ca 19963#undef elf_backend_default_use_rela_p
00a97672 19964#define elf_backend_default_use_rela_p 0
906e58ca 19965#undef elf_backend_want_plt_sym
00a97672 19966#define elf_backend_want_plt_sym 0
64f52338
AM		 19967#undef elf_backend_dtrel_excludes_plt
19968#define elf_backend_dtrel_excludes_plt 0
906e58ca 19969#undef ELF_MAXPAGESIZE
00a97672 19970#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19971
7f266840 19972#include "elf32-target.h"
GDB Binutils - Deliverables
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