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Fix new inferior events output
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
219d1afa 2 Copyright (C) 1998-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
f3185997 59#define elf_info_to_howto NULL
07d6d2b8 60#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
07d6d2b8 240 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
99059e56
RM		 334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
07d6d2b8 340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
99059e56
RM		 348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
07d6d2b8 354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
99059e56
RM		 362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
07d6d2b8 368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
99059e56
RM		 378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
07d6d2b8 384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
99059e56
RM		 392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
07d6d2b8 398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
99059e56
RM		 406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
07d6d2b8 412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
99059e56
RM		 420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
07d6d2b8 426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
99059e56
RM		 434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
07d6d2b8 440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
99059e56 446 TRUE, /* pc_relative */
07d6d2b8 447 0, /* bitpos */
99059e56
RM		 448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
99059e56 460 FALSE, /* pc_relative */
07d6d2b8 461 0, /* bitpos */
99059e56
RM		 462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
99059e56 474 TRUE, /* pc_relative */
07d6d2b8 475 0, /* bitpos */
99059e56
RM		 476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
07d6d2b8 909 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 917 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
07d6d2b8 937 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 945 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
07d6d2b8 951 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 959 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
07d6d2b8 965 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 973 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
07d6d2b8 979 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 987 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
07d6d2b8 993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1001 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
07d6d2b8 1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1015 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
07d6d2b8 1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1029 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
07d6d2b8 1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1043 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
07d6d2b8 1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1057 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
07d6d2b8 1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1071 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
07d6d2b8 1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1085 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
07d6d2b8 1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1099 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
07d6d2b8 1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1113 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
07d6d2b8 1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1127 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
07d6d2b8 1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1141 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
07d6d2b8 1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1155 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
07d6d2b8 1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1169 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
07d6d2b8 1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1183 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
07d6d2b8 1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1197 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
07d6d2b8 1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1211 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
07d6d2b8 1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1225 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
07d6d2b8 1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1239 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
07d6d2b8 1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1253 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
07d6d2b8 1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1267 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
07d6d2b8 1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1486
1487 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
99059e56 1494 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
99059e56 1509 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1510 NULL, /* special_function */
99059e56 1511 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
99059e56
RM		 1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
07d6d2b8 1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
99059e56
RM		 1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
07d6d2b8 1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
99059e56
RM		 1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
07d6d2b8 1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
99059e56
RM		 1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
07d6d2b8 1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
99059e56 1608 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
07d6d2b8 1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
99059e56
RM		 1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
f3185997
NC		 1842static bfd_boolean
1843elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1849 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1850 {
1851 /* xgettext:c-format */
1852 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1853 abfd, r_type);
1854 bfd_set_error (bfd_error_bad_value);
1855 return FALSE;
1856 }
1857 return TRUE;
7f266840
DJ		 1858}
1859
1860struct elf32_arm_reloc_map
1861 {
1862 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1863 unsigned char elf_reloc_val;
7f266840
DJ		 1864 };
1865
1866/* All entries in this list must also be present in elf32_arm_howto_table. */
1867static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1868 {
07d6d2b8 1869 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 1870 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1871 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1872 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 1873 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1874 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1875 {BFD_RELOC_32, R_ARM_ABS32},
1876 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1877 {BFD_RELOC_8, R_ARM_ABS8},
1878 {BFD_RELOC_16, R_ARM_ABS16},
1879 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 1880 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1881 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1882 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1883 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1884 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1885 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1886 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 1887 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1888 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1889 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
1890 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
1891 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
1892 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
1893 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1894 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 1895 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1896 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1897 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1898 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 1899 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 1900 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1901 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1902 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 1903 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 1904 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 1905 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 1906 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1907 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1908 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1909 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1910 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1911 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 1912 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1913 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1914 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
1915 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1916 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1917 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1918 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1919 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1920 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1921 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1922 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1923 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1924 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1925 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1926 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1927 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1928 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1929 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1930 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1931 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1932 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1933 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1934 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1935 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1936 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1937 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1938 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1939 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1940 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1941 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1942 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1943 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1944 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1945 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1946 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1947 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1948 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1949 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1950 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1951 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1952 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1953 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1954 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1955 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1956 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1957 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1958 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1959 };
1960
1961static reloc_howto_type *
f1c71a59
ZW		 1962elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1963 bfd_reloc_code_real_type code)
7f266840
DJ		 1964{
1965 unsigned int i;
8029a119 1966
906e58ca 1967 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1968 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1969 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1970
c19d1205 1971 return NULL;
7f266840
DJ		 1972}
1973
157090f7
AM		 1974static reloc_howto_type *
1975elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1976 const char *r_name)
1977{
1978 unsigned int i;
1979
906e58ca 1980 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1981 if (elf32_arm_howto_table_1[i].name != NULL
1982 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1983 return &elf32_arm_howto_table_1[i];
1984
906e58ca 1985 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1986 if (elf32_arm_howto_table_2[i].name != NULL
1987 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1988 return &elf32_arm_howto_table_2[i];
1989
34e77a92
RS		 1990 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1991 if (elf32_arm_howto_table_3[i].name != NULL
1992 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1993 return &elf32_arm_howto_table_3[i];
1994
157090f7
AM		 1995 return NULL;
1996}
1997
906e58ca
NC		 1998/* Support for core dump NOTE sections. */
1999
7f266840 2000static bfd_boolean
f1c71a59 2001elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2002{
2003 int offset;
2004 size_t size;
2005
2006 switch (note->descsz)
2007 {
2008 default:
2009 return FALSE;
2010
8029a119 2011 case 148: /* Linux/ARM 32-bit. */
7f266840 2012 /* pr_cursig */
228e534f 2013 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2014
2015 /* pr_pid */
228e534f 2016 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2017
2018 /* pr_reg */
2019 offset = 72;
2020 size = 72;
2021
2022 break;
2023 }
2024
2025 /* Make a ".reg/999" section. */
2026 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2027 size, note->descpos + offset);
2028}
2029
2030static bfd_boolean
f1c71a59 2031elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2032{
2033 switch (note->descsz)
2034 {
2035 default:
2036 return FALSE;
2037
8029a119 2038 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2039 elf_tdata (abfd)->core->pid
4395ee08 2040 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2041 elf_tdata (abfd)->core->program
7f266840 2042 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2043 elf_tdata (abfd)->core->command
7f266840
DJ		 2044 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2045 }
2046
2047 /* Note that for some reason, a spurious space is tacked
2048 onto the end of the args in some (at least one anyway)
2049 implementations, so strip it off if it exists. */
7f266840 2050 {
228e534f 2051 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2052 int n = strlen (command);
2053
2054 if (0 < n && command[n - 1] == ' ')
2055 command[n - 1] = '\0';
2056 }
2057
2058 return TRUE;
2059}
2060
1f20dca5
UW		 2061static char *
2062elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2063 int note_type, ...)
2064{
2065 switch (note_type)
2066 {
2067 default:
2068 return NULL;
2069
2070 case NT_PRPSINFO:
2071 {
2072 char data[124];
2073 va_list ap;
2074
2075 va_start (ap, note_type);
2076 memset (data, 0, sizeof (data));
2077 strncpy (data + 28, va_arg (ap, const char *), 16);
2078 strncpy (data + 44, va_arg (ap, const char *), 80);
2079 va_end (ap);
2080
2081 return elfcore_write_note (abfd, buf, bufsiz,
2082 "CORE", note_type, data, sizeof (data));
2083 }
2084
2085 case NT_PRSTATUS:
2086 {
2087 char data[148];
2088 va_list ap;
2089 long pid;
2090 int cursig;
2091 const void *greg;
2092
2093 va_start (ap, note_type);
2094 memset (data, 0, sizeof (data));
2095 pid = va_arg (ap, long);
2096 bfd_put_32 (abfd, pid, data + 24);
2097 cursig = va_arg (ap, int);
2098 bfd_put_16 (abfd, cursig, data + 12);
2099 greg = va_arg (ap, const void *);
2100 memcpy (data + 72, greg, 72);
2101 va_end (ap);
2102
2103 return elfcore_write_note (abfd, buf, bufsiz,
2104 "CORE", note_type, data, sizeof (data));
2105 }
2106 }
2107}
2108
07d6d2b8
AM		 2109#define TARGET_LITTLE_SYM arm_elf32_le_vec
2110#define TARGET_LITTLE_NAME "elf32-littlearm"
2111#define TARGET_BIG_SYM arm_elf32_be_vec
2112#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2113
2114#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2115#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2116#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2117
252b5132
RH		 2118typedef unsigned long int insn32;
2119typedef unsigned short int insn16;
2120
3a4a14e9
PB		 2121/* In lieu of proper flags, assume all EABIv4 or later objects are
2122 interworkable. */
57e8b36a 2123#define INTERWORK_FLAG(abfd) \
3a4a14e9 2124 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2125 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2126 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2127
252b5132
RH		 2128/* The linker script knows the section names for placement.
2129 The entry_names are used to do simple name mangling on the stubs.
2130 Given a function name, and its type, the stub can be found. The
9b485d32 2131 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2132#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2133#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2134
2135#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2136#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2137
c7b8f16e
JB		 2138#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2139#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2140
a504d23a
LA		 2141#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2142#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2143
845b51d6
PB		 2144#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2145#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2146
7413f23f
DJ		 2147#define STUB_ENTRY_NAME "__%s_veneer"
2148
4ba2ef8f
TP		 2149#define CMSE_PREFIX "__acle_se_"
2150
252b5132
RH		 2151/* The name of the dynamic interpreter. This is put in the .interp
2152 section. */
2153#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2154
0855e32b 2155static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2156{
2157 0xe08e0000, /* add r0, lr, r0 */
2158 0xe5901004, /* ldr r1, [r0,#4] */
2159 0xe12fff11, /* bx r1 */
2160};
0855e32b
NS		 2161
2162static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2163{
2164 0xe52d2004, /* push {r2} */
2165 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2166 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2167 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2168 0xe081100f, /* 2: add r1, pc */
2169 0xe12fff12, /* bx r2 */
2170 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2171 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2172 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2173};
0855e32b 2174
5e681ec4
PB		 2175#ifdef FOUR_WORD_PLT
2176
252b5132
RH		 2177/* The first entry in a procedure linkage table looks like
2178 this. It is set up so that any shared library function that is
59f2c4e7 2179 called before the relocation has been set up calls the dynamic
9b485d32 2180 linker first. */
e5a52504 2181static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2182{
2183 0xe52de004, /* str lr, [sp, #-4]! */
2184 0xe59fe010, /* ldr lr, [pc, #16] */
2185 0xe08fe00e, /* add lr, pc, lr */
2186 0xe5bef008, /* ldr pc, [lr, #8]! */
2187};
5e681ec4
PB		 2188
2189/* Subsequent entries in a procedure linkage table look like
2190 this. */
e5a52504 2191static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2192{
2193 0xe28fc600, /* add ip, pc, #NN */
2194 0xe28cca00, /* add ip, ip, #NN */
2195 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2196 0x00000000, /* unused */
2197};
5e681ec4 2198
eed94f8f 2199#else /* not FOUR_WORD_PLT */
5e681ec4 2200
5e681ec4
PB		 2201/* The first entry in a procedure linkage table looks like
2202 this. It is set up so that any shared library function that is
2203 called before the relocation has been set up calls the dynamic
2204 linker first. */
e5a52504 2205static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2206{
07d6d2b8
AM		 2207 0xe52de004, /* str lr, [sp, #-4]! */
2208 0xe59fe004, /* ldr lr, [pc, #4] */
2209 0xe08fe00e, /* add lr, pc, lr */
2210 0xe5bef008, /* ldr pc, [lr, #8]! */
2211 0x00000000, /* &GOT[0] - . */
b38cadfb 2212};
252b5132 2213
1db37fe6
YG		 2214/* By default subsequent entries in a procedure linkage table look like
2215 this. Offsets that don't fit into 28 bits will cause link error. */
2216static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2217{
2218 0xe28fc600, /* add ip, pc, #0xNN00000 */
2219 0xe28cca00, /* add ip, ip, #0xNN000 */
2220 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2221};
5e681ec4 2222
1db37fe6
YG		 2223/* When explicitly asked, we'll use this "long" entry format
2224 which can cope with arbitrary displacements. */
2225static const bfd_vma elf32_arm_plt_entry_long [] =
2226{
07d6d2b8
AM		 2227 0xe28fc200, /* add ip, pc, #0xN0000000 */
2228 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2229 0xe28cca00, /* add ip, ip, #0xNN000 */
2230 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2231};
2232
2233static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2234
eed94f8f
NC		 2235#endif /* not FOUR_WORD_PLT */
2236
2237/* The first entry in a procedure linkage table looks like this.
2238 It is set up so that any shared library function that is called before the
2239 relocation has been set up calls the dynamic linker first. */
2240static const bfd_vma elf32_thumb2_plt0_entry [] =
2241{
2242 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2243 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2244 0xf8dfb500, /* push {lr} */
2245 0x44fee008, /* ldr.w lr, [pc, #8] */
2246 /* add lr, pc */
eed94f8f 2247 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2248 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2249};
2250
2251/* Subsequent entries in a procedure linkage table for thumb only target
2252 look like this. */
2253static const bfd_vma elf32_thumb2_plt_entry [] =
2254{
2255 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2256 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2257 0x0c00f240, /* movw ip, #0xNNNN */
2258 0x0c00f2c0, /* movt ip, #0xNNNN */
2259 0xf8dc44fc, /* add ip, pc */
2260 0xbf00f000 /* ldr.w pc, [ip] */
2261 /* nop */
eed94f8f 2262};
252b5132 2263
00a97672
RS		 2264/* The format of the first entry in the procedure linkage table
2265 for a VxWorks executable. */
2266static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2267{
07d6d2b8
AM		 2268 0xe52dc008, /* str ip,[sp,#-8]! */
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf008, /* ldr pc,[ip,#8] */
2271 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2272};
00a97672
RS		 2273
2274/* The format of subsequent entries in a VxWorks executable. */
2275static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2276{
07d6d2b8
AM		 2277 0xe59fc000, /* ldr ip,[pc] */
2278 0xe59cf000, /* ldr pc,[ip] */
2279 0x00000000, /* .long @got */
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xea000000, /* b _PLT */
2282 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2283};
00a97672
RS		 2284
2285/* The format of entries in a VxWorks shared library. */
2286static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2287{
07d6d2b8
AM		 2288 0xe59fc000, /* ldr ip,[pc] */
2289 0xe79cf009, /* ldr pc,[ip,r9] */
2290 0x00000000, /* .long @got */
2291 0xe59fc000, /* ldr ip,[pc] */
2292 0xe599f008, /* ldr pc,[r9,#8] */
2293 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2294};
00a97672 2295
b7693d02
DJ		 2296/* An initial stub used if the PLT entry is referenced from Thumb code. */
2297#define PLT_THUMB_STUB_SIZE 4
2298static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2299{
2300 0x4778, /* bx pc */
2301 0x46c0 /* nop */
2302};
b7693d02 2303
e5a52504
MM		 2304/* The entries in a PLT when using a DLL-based target with multiple
2305 address spaces. */
906e58ca 2306static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2307{
07d6d2b8
AM		 2308 0xe51ff004, /* ldr pc, [pc, #-4] */
2309 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2310};
2311
2312/* The first entry in a procedure linkage table looks like
2313 this. It is set up so that any shared library function that is
2314 called before the relocation has been set up calls the dynamic
2315 linker first. */
2316static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2317{
2318 /* First bundle: */
2319 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2320 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2321 0xe08cc00f, /* add ip, ip, pc */
2322 0xe52dc008, /* str ip, [sp, #-8]! */
2323 /* Second bundle: */
edccdf7c
RM		 2324 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2325 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2326 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2327 0xe12fff1c, /* bx ip */
b38cadfb 2328 /* Third bundle: */
edccdf7c
RM		 2329 0xe320f000, /* nop */
2330 0xe320f000, /* nop */
2331 0xe320f000, /* nop */
b38cadfb
NC		 2332 /* .Lplt_tail: */
2333 0xe50dc004, /* str ip, [sp, #-4] */
2334 /* Fourth bundle: */
edccdf7c
RM		 2335 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2336 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2337 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2338 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2339};
2340#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2341
2342/* Subsequent entries in a procedure linkage table look like this. */
2343static const bfd_vma elf32_arm_nacl_plt_entry [] =
2344{
2345 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2346 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2347 0xe08cc00f, /* add ip, ip, pc */
2348 0xea000000, /* b .Lplt_tail */
2349};
e5a52504 2350
906e58ca
NC		 2351#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2352#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2353#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2354#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2355#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2356#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2357#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2358#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2359
461a49ca 2360enum stub_insn_type
b38cadfb
NC		 2361{
2362 THUMB16_TYPE = 1,
2363 THUMB32_TYPE,
2364 ARM_TYPE,
2365 DATA_TYPE
2366};
461a49ca 2367
48229727
JB		 2368#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2369/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2370 is inserted in arm_build_one_stub(). */
2371#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2372#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2373#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2374#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2375#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2376#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2377#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2378#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2379
2380typedef struct
2381{
07d6d2b8 2382 bfd_vma data;
b38cadfb 2383 enum stub_insn_type type;
07d6d2b8
AM		 2384 unsigned int r_type;
2385 int reloc_addend;
461a49ca
DJ		 2386} insn_sequence;
2387
fea2b4d6
CL		 2388/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2389 to reach the stub if necessary. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2391{
07d6d2b8 2392 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2393 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2394};
906e58ca 2395
fea2b4d6
CL		 2396/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2397 available. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2399{
07d6d2b8
AM		 2400 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2401 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2402 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2403};
906e58ca 2404
d3626fb0 2405/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2406static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2407{
07d6d2b8
AM		 2408 THUMB16_INSN (0xb401), /* push {r0} */
2409 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2410 THUMB16_INSN (0x4684), /* mov ip, r0 */
2411 THUMB16_INSN (0xbc01), /* pop {r0} */
2412 THUMB16_INSN (0x4760), /* bx ip */
2413 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2414 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2415};
906e58ca 2416
80c135e5
TP		 2417/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2419{
07d6d2b8 2420 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2421 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2422};
2423
d5a67c02
AV		 2424/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2425 M-profile architectures. */
2426static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2427{
2428 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2429 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2430 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2431};
2432
d3626fb0
CL		 2433/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2434 allowed. */
2435static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2436{
07d6d2b8
AM		 2437 THUMB16_INSN (0x4778), /* bx pc */
2438 THUMB16_INSN (0x46c0), /* nop */
2439 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2440 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2441 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2442};
d3626fb0 2443
fea2b4d6
CL		 2444/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2445 available. */
461a49ca 2446static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2447{
07d6d2b8
AM		 2448 THUMB16_INSN (0x4778), /* bx pc */
2449 THUMB16_INSN (0x46c0), /* nop */
2450 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2451 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2452};
906e58ca 2453
fea2b4d6
CL		 2454/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2455 one, when the destination is close enough. */
461a49ca 2456static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2457{
07d6d2b8
AM		 2458 THUMB16_INSN (0x4778), /* bx pc */
2459 THUMB16_INSN (0x46c0), /* nop */
b38cadfb
NC		 2460 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2461};
c820be07 2462
cf3eccff 2463/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2464 blx to reach the stub if necessary. */
cf3eccff 2465static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2466{
07d6d2b8
AM		 2467 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2468 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2469 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2470};
906e58ca 2471
cf3eccff
DJ		 2472/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2473 blx to reach the stub if necessary. We can not add into pc;
2474 it is not guaranteed to mode switch (different in ARMv6 and
2475 ARMv7). */
2476static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2477{
07d6d2b8
AM		 2478 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2479 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2480 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2481 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2482};
cf3eccff 2483
ebe24dd4
CL		 2484/* V4T ARM -> ARM long branch stub, PIC. */
2485static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2486{
07d6d2b8
AM		 2487 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2488 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2489 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2490 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2491};
ebe24dd4
CL		 2492
2493/* V4T Thumb -> ARM long branch stub, PIC. */
2494static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2495{
07d6d2b8
AM		 2496 THUMB16_INSN (0x4778), /* bx pc */
2497 THUMB16_INSN (0x46c0), /* nop */
2498 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2499 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2500 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2501};
ebe24dd4 2502
d3626fb0
CL		 2503/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2504 architectures. */
ebe24dd4 2505static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2506{
07d6d2b8
AM		 2507 THUMB16_INSN (0xb401), /* push {r0} */
2508 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2509 THUMB16_INSN (0x46fc), /* mov ip, pc */
2510 THUMB16_INSN (0x4484), /* add ip, r0 */
2511 THUMB16_INSN (0xbc01), /* pop {r0} */
2512 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2513 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2514};
ebe24dd4 2515
d3626fb0
CL		 2516/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2517 allowed. */
2518static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2519{
07d6d2b8
AM		 2520 THUMB16_INSN (0x4778), /* bx pc */
2521 THUMB16_INSN (0x46c0), /* nop */
2522 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2523 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2524 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2525 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2526};
d3626fb0 2527
0855e32b
NS		 2528/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2529 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2530static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2531{
07d6d2b8
AM		 2532 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2533 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2534 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2535};
2536
2537/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2538 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2539static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2540{
07d6d2b8
AM		 2541 THUMB16_INSN (0x4778), /* bx pc */
2542 THUMB16_INSN (0x46c0), /* nop */
2543 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2544 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2545 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2546};
2547
7a89b94e
NC		 2548/* NaCl ARM -> ARM long branch stub. */
2549static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2550{
2551 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2552 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2553 ARM_INSN (0xe12fff1c), /* bx ip */
2554 ARM_INSN (0xe320f000), /* nop */
2555 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2556 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2557 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2558 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2559};
2560
2561/* NaCl ARM -> ARM long branch stub, PIC. */
2562static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2563{
2564 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2565 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2566 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2567 ARM_INSN (0xe12fff1c), /* bx ip */
2568 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2569 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2570 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2571 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2572};
2573
4ba2ef8f
TP		 2574/* Stub used for transition to secure state (aka SG veneer). */
2575static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2576{
2577 THUMB32_INSN (0xe97fe97f), /* sg. */
2578 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2579};
2580
7a89b94e 2581
48229727
JB		 2582/* Cortex-A8 erratum-workaround stubs. */
2583
2584/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2585 can't use a conditional branch to reach this stub). */
2586
2587static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2588{
07d6d2b8 2589 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2590 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2591 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2592};
48229727
JB		 2593
2594/* Stub used for b.w and bl.w instructions. */
2595
2596static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2597{
2598 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2599};
48229727
JB		 2600
2601static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2602{
2603 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2604};
48229727
JB		 2605
2606/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2607 instruction (which switches to ARM mode) to point to this stub. Jump to the
2608 real destination using an ARM-mode branch. */
2609
2610static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2611{
2612 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2613};
48229727 2614
9553db3c
NC		 2615/* For each section group there can be a specially created linker section
2616 to hold the stubs for that group. The name of the stub section is based
2617 upon the name of another section within that group with the suffix below
2618 applied.
2619
2620 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2621 create what appeared to be a linker stub section when it actually
2622 contained user code/data. For example, consider this fragment:
b38cadfb 2623
9553db3c
NC		 2624 const char * stubborn_problems[] = { "np" };
2625
2626 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2627 section called:
2628
2629 .data.rel.local.stubborn_problems
2630
2631 This then causes problems in arm32_arm_build_stubs() as it triggers:
2632
2633 // Ignore non-stub sections.
2634 if (!strstr (stub_sec->name, STUB_SUFFIX))
2635 continue;
2636
2637 And so the section would be ignored instead of being processed. Hence
2638 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2639 C identifier. */
2640#define STUB_SUFFIX ".__stub"
906e58ca 2641
738a79f6
CL		 2642/* One entry per long/short branch stub defined above. */
2643#define DEF_STUBS \
2644 DEF_STUB(long_branch_any_any) \
2645 DEF_STUB(long_branch_v4t_arm_thumb) \
2646 DEF_STUB(long_branch_thumb_only) \
2647 DEF_STUB(long_branch_v4t_thumb_thumb) \
2648 DEF_STUB(long_branch_v4t_thumb_arm) \
2649 DEF_STUB(short_branch_v4t_thumb_arm) \
2650 DEF_STUB(long_branch_any_arm_pic) \
2651 DEF_STUB(long_branch_any_thumb_pic) \
2652 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2653 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2654 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2655 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2656 DEF_STUB(long_branch_any_tls_pic) \
2657 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2658 DEF_STUB(long_branch_arm_nacl) \
2659 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2660 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2661 DEF_STUB(a8_veneer_b_cond) \
2662 DEF_STUB(a8_veneer_b) \
2663 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2664 DEF_STUB(a8_veneer_blx) \
2665 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2666 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2667
2668#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2669enum elf32_arm_stub_type
2670{
906e58ca 2671 arm_stub_none,
738a79f6 2672 DEF_STUBS
4f4faa4d 2673 max_stub_type
738a79f6
CL		 2674};
2675#undef DEF_STUB
2676
8d9d9490
TP		 2677/* Note the first a8_veneer type. */
2678const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2679
738a79f6
CL		 2680typedef struct
2681{
d3ce72d0 2682 const insn_sequence* template_sequence;
738a79f6
CL		 2683 int template_size;
2684} stub_def;
2685
2686#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2687static const stub_def stub_definitions[] =
2688{
738a79f6
CL		 2689 {NULL, 0},
2690 DEF_STUBS
906e58ca
NC		 2691};
2692
2693struct elf32_arm_stub_hash_entry
2694{
2695 /* Base hash table entry structure. */
2696 struct bfd_hash_entry root;
2697
2698 /* The stub section. */
2699 asection *stub_sec;
2700
2701 /* Offset within stub_sec of the beginning of this stub. */
2702 bfd_vma stub_offset;
2703
2704 /* Given the symbol's value and its section we can determine its final
2705 value when building the stubs (so the stub knows where to jump). */
2706 bfd_vma target_value;
2707 asection *target_section;
2708
8d9d9490
TP		 2709 /* Same as above but for the source of the branch to the stub. Used for
2710 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2711 such, source section does not need to be recorded since Cortex-A8 erratum
2712 workaround stubs are only generated when both source and target are in the
2713 same section. */
2714 bfd_vma source_value;
48229727
JB		 2715
2716 /* The instruction which caused this stub to be generated (only valid for
2717 Cortex-A8 erratum workaround stubs at present). */
2718 unsigned long orig_insn;
2719
461a49ca 2720 /* The stub type. */
906e58ca 2721 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2722 /* Its encoding size in bytes. */
2723 int stub_size;
2724 /* Its template. */
2725 const insn_sequence *stub_template;
2726 /* The size of the template (number of entries). */
2727 int stub_template_size;
906e58ca
NC		 2728
2729 /* The symbol table entry, if any, that this was derived from. */
2730 struct elf32_arm_link_hash_entry *h;
2731
35fc36a8
RS		 2732 /* Type of branch. */
2733 enum arm_st_branch_type branch_type;
906e58ca
NC		 2734
2735 /* Where this stub is being called from, or, in the case of combined
2736 stub sections, the first input section in the group. */
2737 asection *id_sec;
7413f23f
DJ		 2738
2739 /* The name for the local symbol at the start of this stub. The
2740 stub name in the hash table has to be unique; this does not, so
2741 it can be friendlier. */
2742 char *output_name;
906e58ca
NC		 2743};
2744
e489d0ae
PB		 2745/* Used to build a map of a section. This is required for mixed-endian
2746 code/data. */
2747
2748typedef struct elf32_elf_section_map
2749{
2750 bfd_vma vma;
2751 char type;
2752}
2753elf32_arm_section_map;
2754
c7b8f16e
JB		 2755/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2756
2757typedef enum
2758{
2759 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2760 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2761 VFP11_ERRATUM_ARM_VENEER,
2762 VFP11_ERRATUM_THUMB_VENEER
2763}
2764elf32_vfp11_erratum_type;
2765
2766typedef struct elf32_vfp11_erratum_list
2767{
2768 struct elf32_vfp11_erratum_list *next;
2769 bfd_vma vma;
2770 union
2771 {
2772 struct
2773 {
2774 struct elf32_vfp11_erratum_list *veneer;
2775 unsigned int vfp_insn;
2776 } b;
2777 struct
2778 {
2779 struct elf32_vfp11_erratum_list *branch;
2780 unsigned int id;
2781 } v;
2782 } u;
2783 elf32_vfp11_erratum_type type;
2784}
2785elf32_vfp11_erratum_list;
2786
a504d23a
LA		 2787/* Information about a STM32L4XX erratum veneer, or a branch to such a
2788 veneer. */
2789typedef enum
2790{
2791 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2792 STM32L4XX_ERRATUM_VENEER
2793}
2794elf32_stm32l4xx_erratum_type;
2795
2796typedef struct elf32_stm32l4xx_erratum_list
2797{
2798 struct elf32_stm32l4xx_erratum_list *next;
2799 bfd_vma vma;
2800 union
2801 {
2802 struct
2803 {
2804 struct elf32_stm32l4xx_erratum_list *veneer;
2805 unsigned int insn;
2806 } b;
2807 struct
2808 {
2809 struct elf32_stm32l4xx_erratum_list *branch;
2810 unsigned int id;
2811 } v;
2812 } u;
2813 elf32_stm32l4xx_erratum_type type;
2814}
2815elf32_stm32l4xx_erratum_list;
2816
2468f9c9
PB		 2817typedef enum
2818{
2819 DELETE_EXIDX_ENTRY,
2820 INSERT_EXIDX_CANTUNWIND_AT_END
2821}
2822arm_unwind_edit_type;
2823
2824/* A (sorted) list of edits to apply to an unwind table. */
2825typedef struct arm_unwind_table_edit
2826{
2827 arm_unwind_edit_type type;
2828 /* Note: we sometimes want to insert an unwind entry corresponding to a
2829 section different from the one we're currently writing out, so record the
2830 (text) section this edit relates to here. */
2831 asection *linked_section;
2832 unsigned int index;
2833 struct arm_unwind_table_edit *next;
2834}
2835arm_unwind_table_edit;
2836
8e3de13a 2837typedef struct _arm_elf_section_data
e489d0ae 2838{
2468f9c9 2839 /* Information about mapping symbols. */
e489d0ae 2840 struct bfd_elf_section_data elf;
8e3de13a 2841 unsigned int mapcount;
c7b8f16e 2842 unsigned int mapsize;
e489d0ae 2843 elf32_arm_section_map *map;
2468f9c9 2844 /* Information about CPU errata. */
c7b8f16e
JB		 2845 unsigned int erratumcount;
2846 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2847 unsigned int stm32l4xx_erratumcount;
2848 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2849 unsigned int additional_reloc_count;
2468f9c9
PB		 2850 /* Information about unwind tables. */
2851 union
2852 {
2853 /* Unwind info attached to a text section. */
2854 struct
2855 {
2856 asection *arm_exidx_sec;
2857 } text;
2858
2859 /* Unwind info attached to an .ARM.exidx section. */
2860 struct
2861 {
2862 arm_unwind_table_edit *unwind_edit_list;
2863 arm_unwind_table_edit *unwind_edit_tail;
2864 } exidx;
2865 } u;
8e3de13a
NC		 2866}
2867_arm_elf_section_data;
e489d0ae
PB		 2868
2869#define elf32_arm_section_data(sec) \
8e3de13a 2870 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2871
48229727
JB		 2872/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2873 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2874 so may be created multiple times: we use an array of these entries whilst
2875 relaxing which we can refresh easily, then create stubs for each potentially
2876 erratum-triggering instruction once we've settled on a solution. */
2877
b38cadfb
NC		 2878struct a8_erratum_fix
2879{
48229727
JB		 2880 bfd *input_bfd;
2881 asection *section;
2882 bfd_vma offset;
8d9d9490 2883 bfd_vma target_offset;
48229727
JB		 2884 unsigned long orig_insn;
2885 char *stub_name;
2886 enum elf32_arm_stub_type stub_type;
35fc36a8 2887 enum arm_st_branch_type branch_type;
48229727
JB		 2888};
2889
2890/* A table of relocs applied to branches which might trigger Cortex-A8
2891 erratum. */
2892
b38cadfb
NC		 2893struct a8_erratum_reloc
2894{
48229727
JB		 2895 bfd_vma from;
2896 bfd_vma destination;
92750f34
DJ		 2897 struct elf32_arm_link_hash_entry *hash;
2898 const char *sym_name;
48229727 2899 unsigned int r_type;
35fc36a8 2900 enum arm_st_branch_type branch_type;
48229727
JB		 2901 bfd_boolean non_a8_stub;
2902};
2903
ba93b8ac
DJ		 2904/* The size of the thread control block. */
2905#define TCB_SIZE 8
2906
34e77a92
RS		 2907/* ARM-specific information about a PLT entry, over and above the usual
2908 gotplt_union. */
b38cadfb
NC		 2909struct arm_plt_info
2910{
34e77a92
RS		 2911 /* We reference count Thumb references to a PLT entry separately,
2912 so that we can emit the Thumb trampoline only if needed. */
2913 bfd_signed_vma thumb_refcount;
2914
2915 /* Some references from Thumb code may be eliminated by BL->BLX
2916 conversion, so record them separately. */
2917 bfd_signed_vma maybe_thumb_refcount;
2918
2919 /* How many of the recorded PLT accesses were from non-call relocations.
2920 This information is useful when deciding whether anything takes the
2921 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2922 non-call references to the function should resolve directly to the
2923 real runtime target. */
2924 unsigned int noncall_refcount;
2925
2926 /* Since PLT entries have variable size if the Thumb prologue is
2927 used, we need to record the index into .got.plt instead of
2928 recomputing it from the PLT offset. */
2929 bfd_signed_vma got_offset;
2930};
2931
2932/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2933struct arm_local_iplt_info
2934{
34e77a92
RS		 2935 /* The information that is usually found in the generic ELF part of
2936 the hash table entry. */
2937 union gotplt_union root;
2938
2939 /* The information that is usually found in the ARM-specific part of
2940 the hash table entry. */
2941 struct arm_plt_info arm;
2942
2943 /* A list of all potential dynamic relocations against this symbol. */
2944 struct elf_dyn_relocs *dyn_relocs;
2945};
2946
0ffa91dd 2947struct elf_arm_obj_tdata
ba93b8ac
DJ		 2948{
2949 struct elf_obj_tdata root;
2950
2951 /* tls_type for each local got entry. */
2952 char *local_got_tls_type;
ee065d83 2953
0855e32b
NS		 2954 /* GOTPLT entries for TLS descriptors. */
2955 bfd_vma *local_tlsdesc_gotent;
2956
34e77a92
RS		 2957 /* Information for local symbols that need entries in .iplt. */
2958 struct arm_local_iplt_info **local_iplt;
2959
bf21ed78
MS		 2960 /* Zero to warn when linking objects with incompatible enum sizes. */
2961 int no_enum_size_warning;
a9dc9481
JM		 2962
2963 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2964 int no_wchar_size_warning;
ba93b8ac
DJ		 2965};
2966
0ffa91dd
NC		 2967#define elf_arm_tdata(bfd) \
2968 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2969
0ffa91dd
NC		 2970#define elf32_arm_local_got_tls_type(bfd) \
2971 (elf_arm_tdata (bfd)->local_got_tls_type)
2972
0855e32b
NS		 2973#define elf32_arm_local_tlsdesc_gotent(bfd) \
2974 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2975
34e77a92
RS		 2976#define elf32_arm_local_iplt(bfd) \
2977 (elf_arm_tdata (bfd)->local_iplt)
2978
0ffa91dd
NC		 2979#define is_arm_elf(bfd) \
2980 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2981 && elf_tdata (bfd) != NULL \
4dfe6ac6 2982 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2983
2984static bfd_boolean
2985elf32_arm_mkobject (bfd *abfd)
2986{
0ffa91dd 2987 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2988 ARM_ELF_DATA);
ba93b8ac
DJ		 2989}
2990
ba93b8ac
DJ		 2991#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2992
ba96a88f 2993/* Arm ELF linker hash entry. */
252b5132 2994struct elf32_arm_link_hash_entry
b38cadfb
NC		 2995{
2996 struct elf_link_hash_entry root;
252b5132 2997
b38cadfb
NC		 2998 /* Track dynamic relocs copied for this symbol. */
2999 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3000
b38cadfb
NC		 3001 /* ARM-specific PLT information. */
3002 struct arm_plt_info plt;
ba93b8ac
DJ		 3003
3004#define GOT_UNKNOWN 0
3005#define GOT_NORMAL 1
3006#define GOT_TLS_GD 2
3007#define GOT_TLS_IE 4
0855e32b
NS		 3008#define GOT_TLS_GDESC 8
3009#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3010 unsigned int tls_type : 8;
34e77a92 3011
b38cadfb
NC		 3012 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3013 unsigned int is_iplt : 1;
34e77a92 3014
b38cadfb 3015 unsigned int unused : 23;
a4fd1a8e 3016
b38cadfb
NC		 3017 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3018 starting at the end of the jump table. */
3019 bfd_vma tlsdesc_got;
0855e32b 3020
b38cadfb
NC		 3021 /* The symbol marking the real symbol location for exported thumb
3022 symbols with Arm stubs. */
3023 struct elf_link_hash_entry *export_glue;
906e58ca 3024
b38cadfb 3025 /* A pointer to the most recently used stub hash entry against this
8029a119 3026 symbol. */
b38cadfb
NC		 3027 struct elf32_arm_stub_hash_entry *stub_cache;
3028};
252b5132 3029
252b5132 3030/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3031#define elf32_arm_link_hash_traverse(table, func, info) \
3032 (elf_link_hash_traverse \
3033 (&(table)->root, \
b7693d02 3034 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3035 (info)))
3036
3037/* Get the ARM elf linker hash table from a link_info structure. */
3038#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3039 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3040 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3041
906e58ca
NC		 3042#define arm_stub_hash_lookup(table, string, create, copy) \
3043 ((struct elf32_arm_stub_hash_entry *) \
3044 bfd_hash_lookup ((table), (string), (create), (copy)))
3045
21d799b5
NC		 3046/* Array to keep track of which stub sections have been created, and
3047 information on stub grouping. */
3048struct map_stub
3049{
3050 /* This is the section to which stubs in the group will be
3051 attached. */
3052 asection *link_sec;
3053 /* The stub section. */
3054 asection *stub_sec;
3055};
3056
0855e32b
NS		 3057#define elf32_arm_compute_jump_table_size(htab) \
3058 ((htab)->next_tls_desc_index * 4)
3059
9b485d32 3060/* ARM ELF linker hash table. */
252b5132 3061struct elf32_arm_link_hash_table
906e58ca
NC		 3062{
3063 /* The main hash table. */
3064 struct elf_link_hash_table root;
252b5132 3065
906e58ca
NC		 3066 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3067 bfd_size_type thumb_glue_size;
252b5132 3068
906e58ca
NC		 3069 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3070 bfd_size_type arm_glue_size;
252b5132 3071
906e58ca
NC		 3072 /* The size in bytes of section containing the ARMv4 BX veneers. */
3073 bfd_size_type bx_glue_size;
845b51d6 3074
906e58ca
NC		 3075 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3076 veneer has been populated. */
3077 bfd_vma bx_glue_offset[15];
845b51d6 3078
906e58ca
NC		 3079 /* The size in bytes of the section containing glue for VFP11 erratum
3080 veneers. */
3081 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3082
a504d23a
LA		 3083 /* The size in bytes of the section containing glue for STM32L4XX erratum
3084 veneers. */
3085 bfd_size_type stm32l4xx_erratum_glue_size;
3086
48229727
JB		 3087 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3088 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3089 elf32_arm_write_section(). */
3090 struct a8_erratum_fix *a8_erratum_fixes;
3091 unsigned int num_a8_erratum_fixes;
3092
906e58ca
NC		 3093 /* An arbitrary input BFD chosen to hold the glue sections. */
3094 bfd * bfd_of_glue_owner;
ba96a88f 3095
906e58ca
NC		 3096 /* Nonzero to output a BE8 image. */
3097 int byteswap_code;
e489d0ae 3098
906e58ca
NC		 3099 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3100 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3101 int target1_is_rel;
9c504268 3102
906e58ca
NC		 3103 /* The relocation to use for R_ARM_TARGET2 relocations. */
3104 int target2_reloc;
eb043451 3105
906e58ca
NC		 3106 /* 0 = Ignore R_ARM_V4BX.
3107 1 = Convert BX to MOV PC.
3108 2 = Generate v4 interworing stubs. */
3109 int fix_v4bx;
319850b4 3110
48229727
JB		 3111 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3112 int fix_cortex_a8;
3113
2de70689
MGD		 3114 /* Whether we should fix the ARM1176 BLX immediate issue. */
3115 int fix_arm1176;
3116
906e58ca
NC		 3117 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3118 int use_blx;
33bfe774 3119
906e58ca
NC		 3120 /* What sort of code sequences we should look for which may trigger the
3121 VFP11 denorm erratum. */
3122 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3123
906e58ca
NC		 3124 /* Global counter for the number of fixes we have emitted. */
3125 int num_vfp11_fixes;
c7b8f16e 3126
a504d23a
LA		 3127 /* What sort of code sequences we should look for which may trigger the
3128 STM32L4XX erratum. */
3129 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3130
3131 /* Global counter for the number of fixes we have emitted. */
3132 int num_stm32l4xx_fixes;
3133
906e58ca
NC		 3134 /* Nonzero to force PIC branch veneers. */
3135 int pic_veneer;
27e55c4d 3136
906e58ca
NC		 3137 /* The number of bytes in the initial entry in the PLT. */
3138 bfd_size_type plt_header_size;
e5a52504 3139
906e58ca
NC		 3140 /* The number of bytes in the subsequent PLT etries. */
3141 bfd_size_type plt_entry_size;
e5a52504 3142
906e58ca
NC		 3143 /* True if the target system is VxWorks. */
3144 int vxworks_p;
00a97672 3145
906e58ca
NC		 3146 /* True if the target system is Symbian OS. */
3147 int symbian_p;
e5a52504 3148
b38cadfb
NC		 3149 /* True if the target system is Native Client. */
3150 int nacl_p;
3151
906e58ca 3152 /* True if the target uses REL relocations. */
f3185997 3153 bfd_boolean use_rel;
4e7fd91e 3154
54ddd295
TP		 3155 /* Nonzero if import library must be a secure gateway import library
3156 as per ARMv8-M Security Extensions. */
3157 int cmse_implib;
3158
0955507f
TP		 3159 /* The import library whose symbols' address must remain stable in
3160 the import library generated. */
3161 bfd *in_implib_bfd;
3162
0855e32b
NS		 3163 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3164 bfd_vma next_tls_desc_index;
3165
3166 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3167 bfd_vma num_tls_desc;
3168
906e58ca
NC		 3169 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3170 asection *srelplt2;
00a97672 3171
0855e32b
NS		 3172 /* The offset into splt of the PLT entry for the TLS descriptor
3173 resolver. Special values are 0, if not necessary (or not found
3174 to be necessary yet), and -1 if needed but not determined
3175 yet. */
3176 bfd_vma dt_tlsdesc_plt;
3177
3178 /* The offset into sgot of the GOT entry used by the PLT entry
3179 above. */
b38cadfb 3180 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3181
3182 /* Offset in .plt section of tls_arm_trampoline. */
3183 bfd_vma tls_trampoline;
3184
906e58ca
NC		 3185 /* Data for R_ARM_TLS_LDM32 relocations. */
3186 union
3187 {
3188 bfd_signed_vma refcount;
3189 bfd_vma offset;
3190 } tls_ldm_got;
b7693d02 3191
87d72d41
AM		 3192 /* Small local sym cache. */
3193 struct sym_cache sym_cache;
906e58ca
NC		 3194
3195 /* For convenience in allocate_dynrelocs. */
3196 bfd * obfd;
3197
0855e32b
NS		 3198 /* The amount of space used by the reserved portion of the sgotplt
3199 section, plus whatever space is used by the jump slots. */
3200 bfd_vma sgotplt_jump_table_size;
3201
906e58ca
NC		 3202 /* The stub hash table. */
3203 struct bfd_hash_table stub_hash_table;
3204
3205 /* Linker stub bfd. */
3206 bfd *stub_bfd;
3207
3208 /* Linker call-backs. */
6bde4c52
TP		 3209 asection * (*add_stub_section) (const char *, asection *, asection *,
3210 unsigned int);
906e58ca
NC		 3211 void (*layout_sections_again) (void);
3212
3213 /* Array to keep track of which stub sections have been created, and
3214 information on stub grouping. */
21d799b5 3215 struct map_stub *stub_group;
906e58ca 3216
4ba2ef8f
TP		 3217 /* Input stub section holding secure gateway veneers. */
3218 asection *cmse_stub_sec;
3219
0955507f
TP		 3220 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3221 start to be allocated. */
3222 bfd_vma new_cmse_stub_offset;
3223
fe33d2fa 3224 /* Number of elements in stub_group. */
7292b3ac 3225 unsigned int top_id;
fe33d2fa 3226
906e58ca
NC		 3227 /* Assorted information used by elf32_arm_size_stubs. */
3228 unsigned int bfd_count;
7292b3ac 3229 unsigned int top_index;
906e58ca
NC		 3230 asection **input_list;
3231};
252b5132 3232
a504d23a
LA		 3233static inline int
3234ctz (unsigned int mask)
3235{
3236#if GCC_VERSION >= 3004
3237 return __builtin_ctz (mask);
3238#else
3239 unsigned int i;
3240
3241 for (i = 0; i < 8 * sizeof (mask); i++)
3242 {
3243 if (mask & 0x1)
3244 break;
3245 mask = (mask >> 1);
3246 }
3247 return i;
3248#endif
3249}
3250
3251static inline int
b25e998d 3252elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3253{
3254#if GCC_VERSION >= 3004
3255 return __builtin_popcount (mask);
3256#else
b25e998d
CG		 3257 unsigned int i;
3258 int sum = 0;
a504d23a
LA		 3259
3260 for (i = 0; i < 8 * sizeof (mask); i++)
3261 {
3262 if (mask & 0x1)
3263 sum++;
3264 mask = (mask >> 1);
3265 }
3266 return sum;
3267#endif
3268}
3269
780a67af
NC		 3270/* Create an entry in an ARM ELF linker hash table. */
3271
3272static struct bfd_hash_entry *
57e8b36a 3273elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3274 struct bfd_hash_table * table,
3275 const char * string)
780a67af
NC		 3276{
3277 struct elf32_arm_link_hash_entry * ret =
3278 (struct elf32_arm_link_hash_entry *) entry;
3279
3280 /* Allocate the structure if it has not already been allocated by a
3281 subclass. */
906e58ca 3282 if (ret == NULL)
21d799b5 3283 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3284 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3285 if (ret == NULL)
780a67af
NC		 3286 return (struct bfd_hash_entry *) ret;
3287
3288 /* Call the allocation method of the superclass. */
3289 ret = ((struct elf32_arm_link_hash_entry *)
3290 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3291 table, string));
57e8b36a 3292 if (ret != NULL)
b7693d02 3293 {
0bdcacaf 3294 ret->dyn_relocs = NULL;
ba93b8ac 3295 ret->tls_type = GOT_UNKNOWN;
0855e32b 3296 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3297 ret->plt.thumb_refcount = 0;
3298 ret->plt.maybe_thumb_refcount = 0;
3299 ret->plt.noncall_refcount = 0;
3300 ret->plt.got_offset = -1;
3301 ret->is_iplt = FALSE;
a4fd1a8e 3302 ret->export_glue = NULL;
906e58ca
NC		 3303
3304 ret->stub_cache = NULL;
b7693d02 3305 }
780a67af
NC		 3306
3307 return (struct bfd_hash_entry *) ret;
3308}
3309
34e77a92
RS		 3310/* Ensure that we have allocated bookkeeping structures for ABFD's local
3311 symbols. */
3312
3313static bfd_boolean
3314elf32_arm_allocate_local_sym_info (bfd *abfd)
3315{
3316 if (elf_local_got_refcounts (abfd) == NULL)
3317 {
3318 bfd_size_type num_syms;
3319 bfd_size_type size;
3320 char *data;
3321
3322 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3323 size = num_syms * (sizeof (bfd_signed_vma)
3324 + sizeof (struct arm_local_iplt_info *)
3325 + sizeof (bfd_vma)
3326 + sizeof (char));
3327 data = bfd_zalloc (abfd, size);
3328 if (data == NULL)
3329 return FALSE;
3330
3331 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3332 data += num_syms * sizeof (bfd_signed_vma);
3333
3334 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3335 data += num_syms * sizeof (struct arm_local_iplt_info *);
3336
3337 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3338 data += num_syms * sizeof (bfd_vma);
3339
3340 elf32_arm_local_got_tls_type (abfd) = data;
3341 }
3342 return TRUE;
3343}
3344
3345/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3346 to input bfd ABFD. Create the information if it doesn't already exist.
3347 Return null if an allocation fails. */
3348
3349static struct arm_local_iplt_info *
3350elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3351{
3352 struct arm_local_iplt_info **ptr;
3353
3354 if (!elf32_arm_allocate_local_sym_info (abfd))
3355 return NULL;
3356
3357 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3358 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3359 if (*ptr == NULL)
3360 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3361 return *ptr;
3362}
3363
3364/* Try to obtain PLT information for the symbol with index R_SYMNDX
3365 in ABFD's symbol table. If the symbol is global, H points to its
3366 hash table entry, otherwise H is null.
3367
3368 Return true if the symbol does have PLT information. When returning
3369 true, point *ROOT_PLT at the target-independent reference count/offset
3370 union and *ARM_PLT at the ARM-specific information. */
3371
3372static bfd_boolean
4ba2ef8f
TP		 3373elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3374 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3375 unsigned long r_symndx, union gotplt_union **root_plt,
3376 struct arm_plt_info **arm_plt)
3377{
3378 struct arm_local_iplt_info *local_iplt;
3379
4ba2ef8f
TP		 3380 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3381 return FALSE;
3382
34e77a92
RS		 3383 if (h != NULL)
3384 {
3385 *root_plt = &h->root.plt;
3386 *arm_plt = &h->plt;
3387 return TRUE;
3388 }
3389
3390 if (elf32_arm_local_iplt (abfd) == NULL)
3391 return FALSE;
3392
3393 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3394 if (local_iplt == NULL)
3395 return FALSE;
3396
3397 *root_plt = &local_iplt->root;
3398 *arm_plt = &local_iplt->arm;
3399 return TRUE;
3400}
3401
3402/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3403 before it. */
3404
3405static bfd_boolean
3406elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3407 struct arm_plt_info *arm_plt)
3408{
3409 struct elf32_arm_link_hash_table *htab;
3410
3411 htab = elf32_arm_hash_table (info);
3412 return (arm_plt->thumb_refcount != 0
3413 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3414}
3415
3416/* Return a pointer to the head of the dynamic reloc list that should
3417 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3418 ABFD's symbol table. Return null if an error occurs. */
3419
3420static struct elf_dyn_relocs **
3421elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3422 Elf_Internal_Sym *isym)
3423{
3424 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3425 {
3426 struct arm_local_iplt_info *local_iplt;
3427
3428 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3429 if (local_iplt == NULL)
3430 return NULL;
3431 return &local_iplt->dyn_relocs;
3432 }
3433 else
3434 {
3435 /* Track dynamic relocs needed for local syms too.
3436 We really need local syms available to do this
3437 easily. Oh well. */
3438 asection *s;
3439 void *vpp;
3440
3441 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3442 if (s == NULL)
3443 abort ();
3444
3445 vpp = &elf_section_data (s)->local_dynrel;
3446 return (struct elf_dyn_relocs **) vpp;
3447 }
3448}
3449
906e58ca
NC		 3450/* Initialize an entry in the stub hash table. */
3451
3452static struct bfd_hash_entry *
3453stub_hash_newfunc (struct bfd_hash_entry *entry,
3454 struct bfd_hash_table *table,
3455 const char *string)
3456{
3457 /* Allocate the structure if it has not already been allocated by a
3458 subclass. */
3459 if (entry == NULL)
3460 {
21d799b5 3461 entry = (struct bfd_hash_entry *)
99059e56 3462 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3463 if (entry == NULL)
3464 return entry;
3465 }
3466
3467 /* Call the allocation method of the superclass. */
3468 entry = bfd_hash_newfunc (entry, table, string);
3469 if (entry != NULL)
3470 {
3471 struct elf32_arm_stub_hash_entry *eh;
3472
3473 /* Initialize the local fields. */
3474 eh = (struct elf32_arm_stub_hash_entry *) entry;
3475 eh->stub_sec = NULL;
0955507f 3476 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3477 eh->source_value = 0;
906e58ca
NC		 3478 eh->target_value = 0;
3479 eh->target_section = NULL;
cedfb179 3480 eh->orig_insn = 0;
906e58ca 3481 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3482 eh->stub_size = 0;
3483 eh->stub_template = NULL;
0955507f 3484 eh->stub_template_size = -1;
906e58ca
NC		 3485 eh->h = NULL;
3486 eh->id_sec = NULL;
d8d2f433 3487 eh->output_name = NULL;
906e58ca
NC		 3488 }
3489
3490 return entry;
3491}
3492
00a97672 3493/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3494 shortcuts to them in our hash table. */
3495
3496static bfd_boolean
57e8b36a 3497create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3498{
3499 struct elf32_arm_link_hash_table *htab;
3500
e5a52504 3501 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3502 if (htab == NULL)
3503 return FALSE;
3504
e5a52504
MM		 3505 /* BPABI objects never have a GOT, or associated sections. */
3506 if (htab->symbian_p)
3507 return TRUE;
3508
5e681ec4
PB		 3509 if (! _bfd_elf_create_got_section (dynobj, info))
3510 return FALSE;
3511
5e681ec4
PB		 3512 return TRUE;
3513}
3514
34e77a92
RS		 3515/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3516
3517static bfd_boolean
3518create_ifunc_sections (struct bfd_link_info *info)
3519{
3520 struct elf32_arm_link_hash_table *htab;
3521 const struct elf_backend_data *bed;
3522 bfd *dynobj;
3523 asection *s;
3524 flagword flags;
b38cadfb 3525
34e77a92
RS		 3526 htab = elf32_arm_hash_table (info);
3527 dynobj = htab->root.dynobj;
3528 bed = get_elf_backend_data (dynobj);
3529 flags = bed->dynamic_sec_flags;
3530
3531 if (htab->root.iplt == NULL)
3532 {
3d4d4302
AM		 3533 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3534 flags | SEC_READONLY | SEC_CODE);
34e77a92 3535 if (s == NULL
a0f49396 3536 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3537 return FALSE;
3538 htab->root.iplt = s;
3539 }
3540
3541 if (htab->root.irelplt == NULL)
3542 {
3d4d4302
AM		 3543 s = bfd_make_section_anyway_with_flags (dynobj,
3544 RELOC_SECTION (htab, ".iplt"),
3545 flags | SEC_READONLY);
34e77a92 3546 if (s == NULL
a0f49396 3547 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3548 return FALSE;
3549 htab->root.irelplt = s;
3550 }
3551
3552 if (htab->root.igotplt == NULL)
3553 {
3d4d4302 3554 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3555 if (s == NULL
3556 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3557 return FALSE;
3558 htab->root.igotplt = s;
3559 }
3560 return TRUE;
3561}
3562
eed94f8f
NC		 3563/* Determine if we're dealing with a Thumb only architecture. */
3564
3565static bfd_boolean
3566using_thumb_only (struct elf32_arm_link_hash_table *globals)
3567{
2fd158eb
TP		 3568 int arch;
3569 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3570 Tag_CPU_arch_profile);
eed94f8f 3571
2fd158eb
TP		 3572 if (profile)
3573 return profile == 'M';
eed94f8f 3574
2fd158eb 3575 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3576
60a019a0 3577 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3578 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0 3579
2fd158eb
TP		 3580 if (arch == TAG_CPU_ARCH_V6_M
3581 || arch == TAG_CPU_ARCH_V6S_M
3582 || arch == TAG_CPU_ARCH_V7E_M
3583 || arch == TAG_CPU_ARCH_V8M_BASE
3584 || arch == TAG_CPU_ARCH_V8M_MAIN)
3585 return TRUE;
eed94f8f 3586
2fd158eb 3587 return FALSE;
eed94f8f
NC		 3588}
3589
3590/* Determine if we're dealing with a Thumb-2 object. */
3591
3592static bfd_boolean
3593using_thumb2 (struct elf32_arm_link_hash_table *globals)
3594{
60a019a0
TP		 3595 int arch;
3596 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3597 Tag_THUMB_ISA_use);
3598
3599 if (thumb_isa)
3600 return thumb_isa == 2;
3601
3602 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3603
3604 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3605 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3606
3607 return (arch == TAG_CPU_ARCH_V6T2
3608 || arch == TAG_CPU_ARCH_V7
3609 || arch == TAG_CPU_ARCH_V7E_M
3610 || arch == TAG_CPU_ARCH_V8
bff0500d 3611 || arch == TAG_CPU_ARCH_V8R
60a019a0 3612 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3613}
3614
5e866f5a
TP		 3615/* Determine whether Thumb-2 BL instruction is available. */
3616
3617static bfd_boolean
3618using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3619{
3620 int arch =
3621 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3622
3623 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3624 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
5e866f5a
TP		 3625
3626 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3627 return (arch == TAG_CPU_ARCH_V6T2
3628 || arch >= TAG_CPU_ARCH_V7);
3629}
3630
00a97672
RS		 3631/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3632 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3633 hash table. */
3634
3635static bfd_boolean
57e8b36a 3636elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3637{
3638 struct elf32_arm_link_hash_table *htab;
3639
3640 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3641 if (htab == NULL)
3642 return FALSE;
3643
362d30a1 3644 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3645 return FALSE;
3646
3647 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3648 return FALSE;
3649
00a97672
RS		 3650 if (htab->vxworks_p)
3651 {
3652 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3653 return FALSE;
3654
0e1862bb 3655 if (bfd_link_pic (info))
00a97672
RS		 3656 {
3657 htab->plt_header_size = 0;
3658 htab->plt_entry_size
3659 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3660 }
3661 else
3662 {
3663 htab->plt_header_size
3664 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3665 htab->plt_entry_size
3666 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3667 }
aebf9be7
NC		 3668
3669 if (elf_elfheader (dynobj))
3670 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3671 }
eed94f8f
NC		 3672 else
3673 {
3674 /* PR ld/16017
3675 Test for thumb only architectures. Note - we cannot just call
3676 using_thumb_only() as the attributes in the output bfd have not been
3677 initialised at this point, so instead we use the input bfd. */
3678 bfd * saved_obfd = htab->obfd;
3679
3680 htab->obfd = dynobj;
3681 if (using_thumb_only (htab))
3682 {
3683 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3684 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3685 }
3686 htab->obfd = saved_obfd;
3687 }
5e681ec4 3688
362d30a1
RS		 3689 if (!htab->root.splt
3690 || !htab->root.srelplt
9d19e4fd
AM		 3691 || !htab->root.sdynbss
3692 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3693 abort ();
3694
3695 return TRUE;
3696}
3697
906e58ca
NC		 3698/* Copy the extra info we tack onto an elf_link_hash_entry. */
3699
3700static void
3701elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3702 struct elf_link_hash_entry *dir,
3703 struct elf_link_hash_entry *ind)
3704{
3705 struct elf32_arm_link_hash_entry *edir, *eind;
3706
3707 edir = (struct elf32_arm_link_hash_entry *) dir;
3708 eind = (struct elf32_arm_link_hash_entry *) ind;
3709
0bdcacaf 3710 if (eind->dyn_relocs != NULL)
906e58ca 3711 {
0bdcacaf 3712 if (edir->dyn_relocs != NULL)
906e58ca 3713 {
0bdcacaf
RS		 3714 struct elf_dyn_relocs **pp;
3715 struct elf_dyn_relocs *p;
906e58ca
NC		 3716
3717 /* Add reloc counts against the indirect sym to the direct sym
3718 list. Merge any entries against the same section. */
0bdcacaf 3719 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3720 {
0bdcacaf 3721 struct elf_dyn_relocs *q;
906e58ca 3722
0bdcacaf
RS		 3723 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3724 if (q->sec == p->sec)
906e58ca
NC		 3725 {
3726 q->pc_count += p->pc_count;
3727 q->count += p->count;
3728 *pp = p->next;
3729 break;
3730 }
3731 if (q == NULL)
3732 pp = &p->next;
3733 }
0bdcacaf 3734 *pp = edir->dyn_relocs;
906e58ca
NC		 3735 }
3736
0bdcacaf
RS		 3737 edir->dyn_relocs = eind->dyn_relocs;
3738 eind->dyn_relocs = NULL;
906e58ca
NC		 3739 }
3740
3741 if (ind->root.type == bfd_link_hash_indirect)
3742 {
3743 /* Copy over PLT info. */
34e77a92
RS		 3744 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3745 eind->plt.thumb_refcount = 0;
3746 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3747 eind->plt.maybe_thumb_refcount = 0;
3748 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3749 eind->plt.noncall_refcount = 0;
3750
3751 /* We should only allocate a function to .iplt once the final
3752 symbol information is known. */
3753 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3754
3755 if (dir->got.refcount <= 0)
3756 {
3757 edir->tls_type = eind->tls_type;
3758 eind->tls_type = GOT_UNKNOWN;
3759 }
3760 }
3761
3762 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3763}
3764
68faa637
AM		 3765/* Destroy an ARM elf linker hash table. */
3766
3767static void
d495ab0d 3768elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3769{
3770 struct elf32_arm_link_hash_table *ret
d495ab0d 3771 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3772
3773 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3774 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3775}
3776
906e58ca
NC		 3777/* Create an ARM elf linker hash table. */
3778
3779static struct bfd_link_hash_table *
3780elf32_arm_link_hash_table_create (bfd *abfd)
3781{
3782 struct elf32_arm_link_hash_table *ret;
3783 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3784
7bf52ea2 3785 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3786 if (ret == NULL)
3787 return NULL;
3788
3789 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3790 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3791 sizeof (struct elf32_arm_link_hash_entry),
3792 ARM_ELF_DATA))
906e58ca
NC		 3793 {
3794 free (ret);
3795 return NULL;
3796 }
3797
906e58ca 3798 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3799 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3800#ifdef FOUR_WORD_PLT
3801 ret->plt_header_size = 16;
3802 ret->plt_entry_size = 16;
3803#else
3804 ret->plt_header_size = 20;
1db37fe6 3805 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3806#endif
f3185997 3807 ret->use_rel = TRUE;
906e58ca 3808 ret->obfd = abfd;
906e58ca
NC		 3809
3810 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3811 sizeof (struct elf32_arm_stub_hash_entry)))
3812 {
d495ab0d 3813 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3814 return NULL;
3815 }
d495ab0d 3816 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3817
3818 return &ret->root.root;
3819}
3820
cd1dac3d
DG		 3821/* Determine what kind of NOPs are available. */
3822
3823static bfd_boolean
3824arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3825{
3826 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3827 Tag_CPU_arch);
cd1dac3d 3828
60a019a0 3829 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3830 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3831
3832 return (arch == TAG_CPU_ARCH_V6T2
3833 || arch == TAG_CPU_ARCH_V6K
3834 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 3835 || arch == TAG_CPU_ARCH_V8
3836 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 3837}
3838
f4ac8484
DJ		 3839static bfd_boolean
3840arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3841{
3842 switch (stub_type)
3843 {
fea2b4d6 3844 case arm_stub_long_branch_thumb_only:
80c135e5 3845 case arm_stub_long_branch_thumb2_only:
d5a67c02 3846 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3847 case arm_stub_long_branch_v4t_thumb_arm:
3848 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3849 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3850 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3851 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3852 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3853 return TRUE;
3854 case arm_stub_none:
3855 BFD_FAIL ();
3856 return FALSE;
3857 break;
3858 default:
3859 return FALSE;
3860 }
3861}
3862
906e58ca
NC		 3863/* Determine the type of stub needed, if any, for a call. */
3864
3865static enum elf32_arm_stub_type
3866arm_type_of_stub (struct bfd_link_info *info,
3867 asection *input_sec,
3868 const Elf_Internal_Rela *rel,
34e77a92 3869 unsigned char st_type,
35fc36a8 3870 enum arm_st_branch_type *actual_branch_type,
906e58ca 3871 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3872 bfd_vma destination,
3873 asection *sym_sec,
3874 bfd *input_bfd,
3875 const char *name)
906e58ca
NC		 3876{
3877 bfd_vma location;
3878 bfd_signed_vma branch_offset;
3879 unsigned int r_type;
3880 struct elf32_arm_link_hash_table * globals;
5e866f5a 3881 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3882 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3883 int use_plt = 0;
35fc36a8 3884 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3885 union gotplt_union *root_plt;
3886 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3887 int arch;
3888 int thumb2_movw;
906e58ca 3889
35fc36a8 3890 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3891 return stub_type;
3892
906e58ca 3893 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3894 if (globals == NULL)
3895 return stub_type;
906e58ca
NC		 3896
3897 thumb_only = using_thumb_only (globals);
906e58ca 3898 thumb2 = using_thumb2 (globals);
5e866f5a 3899 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3900
d5a67c02
AV		 3901 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3902
3903 /* True for architectures that implement the thumb2 movw instruction. */
3904 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3905
906e58ca
NC		 3906 /* Determine where the call point is. */
3907 location = (input_sec->output_offset
3908 + input_sec->output_section->vma
3909 + rel->r_offset);
3910
906e58ca
NC		 3911 r_type = ELF32_R_TYPE (rel->r_info);
3912
39f21624
NC		 3913 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3914 are considering a function call relocation. */
c5423981 3915 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 3916 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3917 && branch_type == ST_BRANCH_TO_ARM)
3918 branch_type = ST_BRANCH_TO_THUMB;
3919
34e77a92
RS		 3920 /* For TLS call relocs, it is the caller's responsibility to provide
3921 the address of the appropriate trampoline. */
3922 if (r_type != R_ARM_TLS_CALL
3923 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3924 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3925 ELF32_R_SYM (rel->r_info), &root_plt,
3926 &arm_plt)
34e77a92 3927 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3928 {
34e77a92 3929 asection *splt;
fe33d2fa 3930
34e77a92
RS		 3931 if (hash == NULL || hash->is_iplt)
3932 splt = globals->root.iplt;
3933 else
3934 splt = globals->root.splt;
3935 if (splt != NULL)
b38cadfb 3936 {
34e77a92
RS		 3937 use_plt = 1;
3938
3939 /* Note when dealing with PLT entries: the main PLT stub is in
3940 ARM mode, so if the branch is in Thumb mode, another
3941 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3942 PLT stub. If a long branch stub is needed, we'll add a
3943 Thumb->Arm one and branch directly to the ARM PLT entry.
3944 Here, we have to check if a pre-PLT Thumb->ARM stub
3945 is needed and if it will be close enough. */
34e77a92
RS		 3946
3947 destination = (splt->output_section->vma
3948 + splt->output_offset
3949 + root_plt->offset);
3950 st_type = STT_FUNC;
2df2751d
CL		 3951
3952 /* Thumb branch/call to PLT: it can become a branch to ARM
3953 or to Thumb. We must perform the same checks and
3954 corrections as in elf32_arm_final_link_relocate. */
3955 if ((r_type == R_ARM_THM_CALL)
3956 || (r_type == R_ARM_THM_JUMP24))
3957 {
3958 if (globals->use_blx
3959 && r_type == R_ARM_THM_CALL
3960 && !thumb_only)
3961 {
3962 /* If the Thumb BLX instruction is available, convert
3963 the BL to a BLX instruction to call the ARM-mode
3964 PLT entry. */
3965 branch_type = ST_BRANCH_TO_ARM;
3966 }
3967 else
3968 {
3969 if (!thumb_only)
3970 /* Target the Thumb stub before the ARM PLT entry. */
3971 destination -= PLT_THUMB_STUB_SIZE;
3972 branch_type = ST_BRANCH_TO_THUMB;
3973 }
3974 }
3975 else
3976 {
3977 branch_type = ST_BRANCH_TO_ARM;
3978 }
34e77a92 3979 }
5fa9e92f 3980 }
34e77a92
RS		 3981 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3982 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3983
fe33d2fa
CL		 3984 branch_offset = (bfd_signed_vma)(destination - location);
3985
0855e32b 3986 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3987 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3988 {
5fa9e92f
CL		 3989 /* Handle cases where:
3990 - this call goes too far (different Thumb/Thumb2 max
99059e56 3991 distance)
155d87d7 3992 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3993 Thumb->Arm branch (not bl). A stub is needed in this case,
3994 but only if this call is not through a PLT entry. Indeed,
695344c0 3995 PLT stubs handle mode switching already. */
5e866f5a 3996 if ((!thumb2_bl
906e58ca
NC		 3997 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3998 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 3999 || (thumb2_bl
906e58ca
NC		 4000 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4001 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4002 || (thumb2
4003 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4004 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4005 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4006 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4007 && (((r_type == R_ARM_THM_CALL
4008 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4009 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4010 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4011 && !use_plt))
906e58ca 4012 {
2df2751d
CL		 4013 /* If we need to insert a Thumb-Thumb long branch stub to a
4014 PLT, use one that branches directly to the ARM PLT
4015 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4016 stub, undo this now. */
695344c0
NC		 4017 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4018 {
4019 branch_type = ST_BRANCH_TO_ARM;
4020 branch_offset += PLT_THUMB_STUB_SIZE;
4021 }
2df2751d 4022
35fc36a8 4023 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4024 {
4025 /* Thumb to thumb. */
4026 if (!thumb_only)
4027 {
d5a67c02 4028 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4029 _bfd_error_handler
871b3ab2 4030 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4031 " section with SHF_ARM_PURECODE section"
4032 " attribute is only supported for M-profile"
90b6238f 4033 " targets that implement the movw instruction"),
10463f39 4034 input_bfd, input_sec);
d5a67c02 4035
0e1862bb 4036 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4037 /* PIC stubs. */
155d87d7 4038 ? ((globals->use_blx
9553db3c 4039 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4040 /* V5T and above. Stub starts with ARM code, so
4041 we must be able to switch mode before
4042 reaching it, which is only possible for 'bl'
4043 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4044 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4045 /* On V4T, use Thumb code only. */
d3626fb0 4046 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4047
4048 /* non-PIC stubs. */
155d87d7 4049 : ((globals->use_blx
9553db3c 4050 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4051 /* V5T and above. */
4052 ? arm_stub_long_branch_any_any
4053 /* V4T. */
d3626fb0 4054 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4055 }
4056 else
4057 {
d5a67c02
AV		 4058 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4059 stub_type = arm_stub_long_branch_thumb2_only_pure;
4060 else
4061 {
4062 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4063 _bfd_error_handler
871b3ab2 4064 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4065 " section with SHF_ARM_PURECODE section"
4066 " attribute is only supported for M-profile"
90b6238f 4067 " targets that implement the movw instruction"),
10463f39 4068 input_bfd, input_sec);
d5a67c02
AV		 4069
4070 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4071 /* PIC stub. */
4072 ? arm_stub_long_branch_thumb_only_pic
4073 /* non-PIC stub. */
4074 : (thumb2 ? arm_stub_long_branch_thumb2_only
4075 : arm_stub_long_branch_thumb_only);
4076 }
906e58ca
NC		 4077 }
4078 }
4079 else
4080 {
d5a67c02 4081 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4082 _bfd_error_handler
871b3ab2 4083 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4084 " section with SHF_ARM_PURECODE section"
4085 " attribute is only supported" " for M-profile"
90b6238f 4086 " targets that implement the movw instruction"),
10463f39 4087 input_bfd, input_sec);
d5a67c02 4088
906e58ca 4089 /* Thumb to arm. */
c820be07
NC		 4090 if (sym_sec != NULL
4091 && sym_sec->owner != NULL
4092 && !INTERWORK_FLAG (sym_sec->owner))
4093 {
4eca0228 4094 _bfd_error_handler
90b6238f
AM		 4095 (_("%pB(%s): warning: interworking not enabled;"
4096 " first occurrence: %pB: %s call to %s"),
4097 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4098 }
4099
0855e32b 4100 stub_type =
0e1862bb 4101 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4102 /* PIC stubs. */
0855e32b 4103 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4104 /* TLS PIC stubs. */
0855e32b
NS		 4105 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4106 : arm_stub_long_branch_v4t_thumb_tls_pic)
4107 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4108 /* V5T PIC and above. */
4109 ? arm_stub_long_branch_any_arm_pic
4110 /* V4T PIC stub. */
4111 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4112
4113 /* non-PIC stubs. */
0855e32b 4114 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4115 /* V5T and above. */
4116 ? arm_stub_long_branch_any_any
4117 /* V4T. */
4118 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4119
4120 /* Handle v4t short branches. */
fea2b4d6 4121 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4122 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4123 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4124 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4125 }
4126 }
4127 }
fe33d2fa
CL		 4128 else if (r_type == R_ARM_CALL
4129 || r_type == R_ARM_JUMP24
0855e32b
NS		 4130 || r_type == R_ARM_PLT32
4131 || r_type == R_ARM_TLS_CALL)
906e58ca 4132 {
d5a67c02 4133 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4134 _bfd_error_handler
871b3ab2 4135 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4136 " section with SHF_ARM_PURECODE section"
4137 " attribute is only supported for M-profile"
90b6238f 4138 " targets that implement the movw instruction"),
10463f39 4139 input_bfd, input_sec);
35fc36a8 4140 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4141 {
4142 /* Arm to thumb. */
c820be07
NC		 4143
4144 if (sym_sec != NULL
4145 && sym_sec->owner != NULL
4146 && !INTERWORK_FLAG (sym_sec->owner))
4147 {
4eca0228 4148 _bfd_error_handler
90b6238f
AM		 4149 (_("%pB(%s): warning: interworking not enabled;"
4150 " first occurrence: %pB: %s call to %s"),
4151 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4152 }
4153
4154 /* We have an extra 2-bytes reach because of
4155 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4156 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4157 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4158 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4159 || (r_type == R_ARM_JUMP24)
4160 || (r_type == R_ARM_PLT32))
906e58ca 4161 {
0e1862bb 4162 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4163 /* PIC stubs. */
ebe24dd4
CL		 4164 ? ((globals->use_blx)
4165 /* V5T and above. */
4166 ? arm_stub_long_branch_any_thumb_pic
4167 /* V4T stub. */
4168 : arm_stub_long_branch_v4t_arm_thumb_pic)
4169
c2b4a39d
CL		 4170 /* non-PIC stubs. */
4171 : ((globals->use_blx)
4172 /* V5T and above. */
4173 ? arm_stub_long_branch_any_any
4174 /* V4T. */
4175 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4176 }
4177 }
4178 else
4179 {
4180 /* Arm to arm. */
4181 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4182 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4183 {
0855e32b 4184 stub_type =
0e1862bb 4185 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4186 /* PIC stubs. */
0855e32b 4187 ? (r_type == R_ARM_TLS_CALL
6a631e86 4188 /* TLS PIC Stub. */
0855e32b 4189 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4190 : (globals->nacl_p
4191 ? arm_stub_long_branch_arm_nacl_pic
4192 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4193 /* non-PIC stubs. */
7a89b94e
NC		 4194 : (globals->nacl_p
4195 ? arm_stub_long_branch_arm_nacl
4196 : arm_stub_long_branch_any_any);
906e58ca
NC		 4197 }
4198 }
4199 }
4200
fe33d2fa
CL		 4201 /* If a stub is needed, record the actual destination type. */
4202 if (stub_type != arm_stub_none)
35fc36a8 4203 *actual_branch_type = branch_type;
fe33d2fa 4204
906e58ca
NC		 4205 return stub_type;
4206}
4207
4208/* Build a name for an entry in the stub hash table. */
4209
4210static char *
4211elf32_arm_stub_name (const asection *input_section,
4212 const asection *sym_sec,
4213 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4214 const Elf_Internal_Rela *rel,
4215 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4216{
4217 char *stub_name;
4218 bfd_size_type len;
4219
4220 if (hash)
4221 {
fe33d2fa 4222 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4223 stub_name = (char *) bfd_malloc (len);
906e58ca 4224 if (stub_name != NULL)
fe33d2fa 4225 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4226 input_section->id & 0xffffffff,
4227 hash->root.root.root.string,
fe33d2fa
CL		 4228 (int) rel->r_addend & 0xffffffff,
4229 (int) stub_type);
906e58ca
NC		 4230 }
4231 else
4232 {
fe33d2fa 4233 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4234 stub_name = (char *) bfd_malloc (len);
906e58ca 4235 if (stub_name != NULL)
fe33d2fa 4236 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4237 input_section->id & 0xffffffff,
4238 sym_sec->id & 0xffffffff,
0855e32b
NS		 4239 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4240 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4241 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4242 (int) rel->r_addend & 0xffffffff,
4243 (int) stub_type);
906e58ca
NC		 4244 }
4245
4246 return stub_name;
4247}
4248
4249/* Look up an entry in the stub hash. Stub entries are cached because
4250 creating the stub name takes a bit of time. */
4251
4252static struct elf32_arm_stub_hash_entry *
4253elf32_arm_get_stub_entry (const asection *input_section,
4254 const asection *sym_sec,
4255 struct elf_link_hash_entry *hash,
4256 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4257 struct elf32_arm_link_hash_table *htab,
4258 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4259{
4260 struct elf32_arm_stub_hash_entry *stub_entry;
4261 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4262 const asection *id_sec;
4263
4264 if ((input_section->flags & SEC_CODE) == 0)
4265 return NULL;
4266
4267 /* If this input section is part of a group of sections sharing one
4268 stub section, then use the id of the first section in the group.
4269 Stub names need to include a section id, as there may well be
4270 more than one stub used to reach say, printf, and we need to
4271 distinguish between them. */
c2abbbeb 4272 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4273 id_sec = htab->stub_group[input_section->id].link_sec;
4274
4275 if (h != NULL && h->stub_cache != NULL
4276 && h->stub_cache->h == h
fe33d2fa
CL		 4277 && h->stub_cache->id_sec == id_sec
4278 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4279 {
4280 stub_entry = h->stub_cache;
4281 }
4282 else
4283 {
4284 char *stub_name;
4285
fe33d2fa 4286 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4287 if (stub_name == NULL)
4288 return NULL;
4289
4290 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4291 stub_name, FALSE, FALSE);
4292 if (h != NULL)
4293 h->stub_cache = stub_entry;
4294
4295 free (stub_name);
4296 }
4297
4298 return stub_entry;
4299}
4300
daa4adae
TP		 4301/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4302 section. */
4303
4304static bfd_boolean
4305arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4306{
4307 if (stub_type >= max_stub_type)
4308 abort (); /* Should be unreachable. */
4309
4ba2ef8f
TP		 4310 switch (stub_type)
4311 {
4312 case arm_stub_cmse_branch_thumb_only:
4313 return TRUE;
4314
4315 default:
4316 return FALSE;
4317 }
4318
4319 abort (); /* Should be unreachable. */
daa4adae
TP		 4320}
4321
4322/* Required alignment (as a power of 2) for the dedicated section holding
4323 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4324 with input sections. */
4325
4326static int
4327arm_dedicated_stub_output_section_required_alignment
4328 (enum elf32_arm_stub_type stub_type)
4329{
4330 if (stub_type >= max_stub_type)
4331 abort (); /* Should be unreachable. */
4332
4ba2ef8f
TP		 4333 switch (stub_type)
4334 {
4335 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4336 boundary. */
4337 case arm_stub_cmse_branch_thumb_only:
4338 return 5;
4339
4340 default:
4341 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4342 return 0;
4343 }
4344
4345 abort (); /* Should be unreachable. */
daa4adae
TP		 4346}
4347
4348/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4349 NULL if veneers of this type are interspersed with input sections. */
4350
4351static const char *
4352arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4353{
4354 if (stub_type >= max_stub_type)
4355 abort (); /* Should be unreachable. */
4356
4ba2ef8f
TP		 4357 switch (stub_type)
4358 {
4359 case arm_stub_cmse_branch_thumb_only:
4360 return ".gnu.sgstubs";
4361
4362 default:
4363 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4364 return NULL;
4365 }
4366
4367 abort (); /* Should be unreachable. */
daa4adae
TP		 4368}
4369
4370/* If veneers of type STUB_TYPE should go in a dedicated output section,
4371 returns the address of the hash table field in HTAB holding a pointer to the
4372 corresponding input section. Otherwise, returns NULL. */
4373
4374static asection **
4ba2ef8f
TP		 4375arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4376 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4377{
4378 if (stub_type >= max_stub_type)
4379 abort (); /* Should be unreachable. */
4380
4ba2ef8f
TP		 4381 switch (stub_type)
4382 {
4383 case arm_stub_cmse_branch_thumb_only:
4384 return &htab->cmse_stub_sec;
4385
4386 default:
4387 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4388 return NULL;
4389 }
4390
4391 abort (); /* Should be unreachable. */
daa4adae
TP		 4392}
4393
4394/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4395 is the section that branch into veneer and can be NULL if stub should go in
4396 a dedicated output section. Returns a pointer to the stub section, and the
4397 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4398 LINK_SEC_P may be NULL. */
906e58ca 4399
48229727
JB		 4400static asection *
4401elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4402 struct elf32_arm_link_hash_table *htab,
4403 enum elf32_arm_stub_type stub_type)
906e58ca 4404{
daa4adae
TP		 4405 asection *link_sec, *out_sec, **stub_sec_p;
4406 const char *stub_sec_prefix;
4407 bfd_boolean dedicated_output_section =
4408 arm_dedicated_stub_output_section_required (stub_type);
4409 int align;
906e58ca 4410
daa4adae 4411 if (dedicated_output_section)
906e58ca 4412 {
daa4adae
TP		 4413 bfd *output_bfd = htab->obfd;
4414 const char *out_sec_name =
4415 arm_dedicated_stub_output_section_name (stub_type);
4416 link_sec = NULL;
4417 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4418 stub_sec_prefix = out_sec_name;
4419 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4420 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4421 if (out_sec == NULL)
906e58ca 4422 {
90b6238f 4423 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4424 "section %s"), out_sec_name);
daa4adae 4425 return NULL;
906e58ca 4426 }
daa4adae
TP		 4427 }
4428 else
4429 {
c2abbbeb 4430 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4431 link_sec = htab->stub_group[section->id].link_sec;
4432 BFD_ASSERT (link_sec != NULL);
4433 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4434 if (*stub_sec_p == NULL)
4435 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4436 stub_sec_prefix = link_sec->name;
4437 out_sec = link_sec->output_section;
4438 align = htab->nacl_p ? 4 : 3;
906e58ca 4439 }
b38cadfb 4440
daa4adae
TP		 4441 if (*stub_sec_p == NULL)
4442 {
4443 size_t namelen;
4444 bfd_size_type len;
4445 char *s_name;
4446
4447 namelen = strlen (stub_sec_prefix);
4448 len = namelen + sizeof (STUB_SUFFIX);
4449 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4450 if (s_name == NULL)
4451 return NULL;
4452
4453 memcpy (s_name, stub_sec_prefix, namelen);
4454 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4455 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4456 align);
4457 if (*stub_sec_p == NULL)
4458 return NULL;
4459
4460 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4461 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4462 | SEC_KEEP;
4463 }
4464
4465 if (!dedicated_output_section)
4466 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4467
48229727
JB		 4468 if (link_sec_p)
4469 *link_sec_p = link_sec;
b38cadfb 4470
daa4adae 4471 return *stub_sec_p;
48229727
JB		 4472}
4473
4474/* Add a new stub entry to the stub hash. Not all fields of the new
4475 stub entry are initialised. */
4476
4477static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4478elf32_arm_add_stub (const char *stub_name, asection *section,
4479 struct elf32_arm_link_hash_table *htab,
4480 enum elf32_arm_stub_type stub_type)
48229727
JB		 4481{
4482 asection *link_sec;
4483 asection *stub_sec;
4484 struct elf32_arm_stub_hash_entry *stub_entry;
4485
daa4adae
TP		 4486 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4487 stub_type);
48229727
JB		 4488 if (stub_sec == NULL)
4489 return NULL;
906e58ca
NC		 4490
4491 /* Enter this entry into the linker stub hash table. */
4492 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4493 TRUE, FALSE);
4494 if (stub_entry == NULL)
4495 {
6bde4c52
TP		 4496 if (section == NULL)
4497 section = stub_sec;
871b3ab2 4498 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4499 section->owner, stub_name);
906e58ca
NC		 4500 return NULL;
4501 }
4502
4503 stub_entry->stub_sec = stub_sec;
0955507f 4504 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4505 stub_entry->id_sec = link_sec;
4506
906e58ca
NC		 4507 return stub_entry;
4508}
4509
4510/* Store an Arm insn into an output section not processed by
4511 elf32_arm_write_section. */
4512
4513static void
8029a119
NC		 4514put_arm_insn (struct elf32_arm_link_hash_table * htab,
4515 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4516{
4517 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4518 bfd_putl32 (val, ptr);
4519 else
4520 bfd_putb32 (val, ptr);
4521}
4522
4523/* Store a 16-bit Thumb insn into an output section not processed by
4524 elf32_arm_write_section. */
4525
4526static void
8029a119
NC		 4527put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4528 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4529{
4530 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4531 bfd_putl16 (val, ptr);
4532 else
4533 bfd_putb16 (val, ptr);
4534}
4535
a504d23a
LA		 4536/* Store a Thumb2 insn into an output section not processed by
4537 elf32_arm_write_section. */
4538
4539static void
4540put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4541 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4542{
4543 /* T2 instructions are 16-bit streamed. */
4544 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4545 {
4546 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4547 bfd_putl16 ((val & 0xffff), ptr + 2);
4548 }
4549 else
4550 {
4551 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4552 bfd_putb16 ((val & 0xffff), ptr + 2);
4553 }
4554}
4555
0855e32b
NS		 4556/* If it's possible to change R_TYPE to a more efficient access
4557 model, return the new reloc type. */
4558
4559static unsigned
b38cadfb 4560elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4561 struct elf_link_hash_entry *h)
4562{
4563 int is_local = (h == NULL);
4564
0e1862bb
L		 4565 if (bfd_link_pic (info)
4566 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4567 return r_type;
4568
b38cadfb 4569 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4570 switch (r_type)
4571 {
4572 case R_ARM_TLS_GOTDESC:
4573 case R_ARM_TLS_CALL:
4574 case R_ARM_THM_TLS_CALL:
4575 case R_ARM_TLS_DESCSEQ:
4576 case R_ARM_THM_TLS_DESCSEQ:
4577 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4578 }
4579
4580 return r_type;
4581}
4582
48229727
JB		 4583static bfd_reloc_status_type elf32_arm_final_link_relocate
4584 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4585 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4586 const char *, unsigned char, enum arm_st_branch_type,
4587 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4588
4563a860
JB		 4589static unsigned int
4590arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4591{
4592 switch (stub_type)
4593 {
4594 case arm_stub_a8_veneer_b_cond:
4595 case arm_stub_a8_veneer_b:
4596 case arm_stub_a8_veneer_bl:
4597 return 2;
4598
4599 case arm_stub_long_branch_any_any:
4600 case arm_stub_long_branch_v4t_arm_thumb:
4601 case arm_stub_long_branch_thumb_only:
80c135e5 4602 case arm_stub_long_branch_thumb2_only:
d5a67c02 4603 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4604 case arm_stub_long_branch_v4t_thumb_thumb:
4605 case arm_stub_long_branch_v4t_thumb_arm:
4606 case arm_stub_short_branch_v4t_thumb_arm:
4607 case arm_stub_long_branch_any_arm_pic:
4608 case arm_stub_long_branch_any_thumb_pic:
4609 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4610 case arm_stub_long_branch_v4t_arm_thumb_pic:
4611 case arm_stub_long_branch_v4t_thumb_arm_pic:
4612 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4613 case arm_stub_long_branch_any_tls_pic:
4614 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4615 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4616 case arm_stub_a8_veneer_blx:
4617 return 4;
b38cadfb 4618
7a89b94e
NC		 4619 case arm_stub_long_branch_arm_nacl:
4620 case arm_stub_long_branch_arm_nacl_pic:
4621 return 16;
4622
4563a860
JB		 4623 default:
4624 abort (); /* Should be unreachable. */
4625 }
4626}
4627
4f4faa4d
TP		 4628/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4629 veneering (TRUE) or have their own symbol (FALSE). */
4630
4631static bfd_boolean
4632arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4633{
4634 if (stub_type >= max_stub_type)
4635 abort (); /* Should be unreachable. */
4636
4ba2ef8f
TP		 4637 switch (stub_type)
4638 {
4639 case arm_stub_cmse_branch_thumb_only:
4640 return TRUE;
4641
4642 default:
4643 return FALSE;
4644 }
4645
4646 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4647}
4648
d7c5bd02
TP		 4649/* Returns the padding needed for the dedicated section used stubs of type
4650 STUB_TYPE. */
4651
4652static int
4653arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4654{
4655 if (stub_type >= max_stub_type)
4656 abort (); /* Should be unreachable. */
4657
4ba2ef8f
TP		 4658 switch (stub_type)
4659 {
4660 case arm_stub_cmse_branch_thumb_only:
4661 return 32;
4662
4663 default:
4664 return 0;
4665 }
4666
4667 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4668}
4669
0955507f
TP		 4670/* If veneers of type STUB_TYPE should go in a dedicated output section,
4671 returns the address of the hash table field in HTAB holding the offset at
4672 which new veneers should be layed out in the stub section. */
4673
4674static bfd_vma*
4675arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4676 enum elf32_arm_stub_type stub_type)
4677{
4678 switch (stub_type)
4679 {
4680 case arm_stub_cmse_branch_thumb_only:
4681 return &htab->new_cmse_stub_offset;
4682
4683 default:
4684 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4685 return NULL;
4686 }
4687}
4688
906e58ca
NC		 4689static bfd_boolean
4690arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4691 void * in_arg)
4692{
7a89b94e 4693#define MAXRELOCS 3
0955507f 4694 bfd_boolean removed_sg_veneer;
906e58ca 4695 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4696 struct elf32_arm_link_hash_table *globals;
906e58ca 4697 struct bfd_link_info *info;
906e58ca
NC		 4698 asection *stub_sec;
4699 bfd *stub_bfd;
906e58ca
NC		 4700 bfd_byte *loc;
4701 bfd_vma sym_value;
4702 int template_size;
4703 int size;
d3ce72d0 4704 const insn_sequence *template_sequence;
906e58ca 4705 int i;
48229727
JB		 4706 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4707 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4708 int nrelocs = 0;
0955507f 4709 int just_allocated = 0;
906e58ca
NC		 4710
4711 /* Massage our args to the form they really have. */
4712 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4713 info = (struct bfd_link_info *) in_arg;
4714
4715 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4716 if (globals == NULL)
4717 return FALSE;
906e58ca 4718
906e58ca
NC		 4719 stub_sec = stub_entry->stub_sec;
4720
4dfe6ac6 4721 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4722 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4723 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4724 return TRUE;
fe33d2fa 4725
0955507f
TP		 4726 /* Assign a slot at the end of section if none assigned yet. */
4727 if (stub_entry->stub_offset == (bfd_vma) -1)
4728 {
4729 stub_entry->stub_offset = stub_sec->size;
4730 just_allocated = 1;
4731 }
906e58ca
NC		 4732 loc = stub_sec->contents + stub_entry->stub_offset;
4733
4734 stub_bfd = stub_sec->owner;
4735
906e58ca
NC		 4736 /* This is the address of the stub destination. */
4737 sym_value = (stub_entry->target_value
4738 + stub_entry->target_section->output_offset
4739 + stub_entry->target_section->output_section->vma);
4740
d3ce72d0 4741 template_sequence = stub_entry->stub_template;
461a49ca 4742 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4743
4744 size = 0;
461a49ca 4745 for (i = 0; i < template_size; i++)
906e58ca 4746 {
d3ce72d0 4747 switch (template_sequence[i].type)
461a49ca
DJ		 4748 {
4749 case THUMB16_TYPE:
48229727 4750 {
d3ce72d0
NC		 4751 bfd_vma data = (bfd_vma) template_sequence[i].data;
4752 if (template_sequence[i].reloc_addend != 0)
48229727 4753 {
99059e56
RM		 4754 /* We've borrowed the reloc_addend field to mean we should
4755 insert a condition code into this (Thumb-1 branch)
4756 instruction. See THUMB16_BCOND_INSN. */
4757 BFD_ASSERT ((data & 0xff00) == 0xd000);
4758 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4759 }
fe33d2fa 4760 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4761 size += 2;
4762 }
461a49ca 4763 break;
906e58ca 4764
48229727 4765 case THUMB32_TYPE:
fe33d2fa
CL		 4766 bfd_put_16 (stub_bfd,
4767 (template_sequence[i].data >> 16) & 0xffff,
4768 loc + size);
4769 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4770 loc + size + 2);
99059e56
RM		 4771 if (template_sequence[i].r_type != R_ARM_NONE)
4772 {
4773 stub_reloc_idx[nrelocs] = i;
4774 stub_reloc_offset[nrelocs++] = size;
4775 }
4776 size += 4;
4777 break;
48229727 4778
461a49ca 4779 case ARM_TYPE:
fe33d2fa
CL		 4780 bfd_put_32 (stub_bfd, template_sequence[i].data,
4781 loc + size);
461a49ca
DJ		 4782 /* Handle cases where the target is encoded within the
4783 instruction. */
d3ce72d0 4784 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4785 {
48229727
JB		 4786 stub_reloc_idx[nrelocs] = i;
4787 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4788 }
4789 size += 4;
4790 break;
4791
4792 case DATA_TYPE:
d3ce72d0 4793 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4794 stub_reloc_idx[nrelocs] = i;
4795 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4796 size += 4;
4797 break;
4798
4799 default:
4800 BFD_FAIL ();
4801 return FALSE;
4802 }
906e58ca 4803 }
461a49ca 4804
0955507f
TP		 4805 if (just_allocated)
4806 stub_sec->size += size;
906e58ca 4807
461a49ca
DJ		 4808 /* Stub size has already been computed in arm_size_one_stub. Check
4809 consistency. */
4810 BFD_ASSERT (size == stub_entry->stub_size);
4811
906e58ca 4812 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4813 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4814 sym_value |= 1;
4815
0955507f
TP		 4816 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4817 to relocate in each stub. */
4818 removed_sg_veneer =
4819 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4820 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4821
48229727 4822 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4823 {
4824 Elf_Internal_Rela rel;
4825 bfd_boolean unresolved_reloc;
4826 char *error_message;
4827 bfd_vma points_to =
4828 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4829
4830 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4831 rel.r_info = ELF32_R_INFO (0,
4832 template_sequence[stub_reloc_idx[i]].r_type);
4833 rel.r_addend = 0;
4834
4835 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4836 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4837 template should refer back to the instruction after the original
4838 branch. We use target_section as Cortex-A8 erratum workaround stubs
4839 are only generated when both source and target are in the same
4840 section. */
4841 points_to = stub_entry->target_section->output_section->vma
4842 + stub_entry->target_section->output_offset
4843 + stub_entry->source_value;
4844
4845 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4846 (template_sequence[stub_reloc_idx[i]].r_type),
4847 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4848 points_to, info, stub_entry->target_section, "", STT_FUNC,
4849 stub_entry->branch_type,
4850 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4851 &error_message);
4852 }
906e58ca
NC		 4853
4854 return TRUE;
48229727 4855#undef MAXRELOCS
906e58ca
NC		 4856}
4857
48229727
JB		 4858/* Calculate the template, template size and instruction size for a stub.
4859 Return value is the instruction size. */
906e58ca 4860
48229727
JB		 4861static unsigned int
4862find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4863 const insn_sequence **stub_template,
4864 int *stub_template_size)
906e58ca 4865{
d3ce72d0 4866 const insn_sequence *template_sequence = NULL;
48229727
JB		 4867 int template_size = 0, i;
4868 unsigned int size;
906e58ca 4869
d3ce72d0 4870 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4871 if (stub_template)
4872 *stub_template = template_sequence;
4873
48229727 4874 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4875 if (stub_template_size)
4876 *stub_template_size = template_size;
906e58ca
NC		 4877
4878 size = 0;
461a49ca
DJ		 4879 for (i = 0; i < template_size; i++)
4880 {
d3ce72d0 4881 switch (template_sequence[i].type)
461a49ca
DJ		 4882 {
4883 case THUMB16_TYPE:
4884 size += 2;
4885 break;
4886
4887 case ARM_TYPE:
48229727 4888 case THUMB32_TYPE:
461a49ca
DJ		 4889 case DATA_TYPE:
4890 size += 4;
4891 break;
4892
4893 default:
4894 BFD_FAIL ();
2a229407 4895 return 0;
461a49ca
DJ		 4896 }
4897 }
4898
48229727
JB		 4899 return size;
4900}
4901
4902/* As above, but don't actually build the stub. Just bump offset so
4903 we know stub section sizes. */
4904
4905static bfd_boolean
4906arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4907 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4908{
4909 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4910 const insn_sequence *template_sequence;
48229727
JB		 4911 int template_size, size;
4912
4913 /* Massage our args to the form they really have. */
4914 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4915
4916 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4917 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4918
d3ce72d0 4919 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4920 &template_size);
4921
0955507f
TP		 4922 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4923 if (stub_entry->stub_template_size)
4924 {
4925 stub_entry->stub_size = size;
4926 stub_entry->stub_template = template_sequence;
4927 stub_entry->stub_template_size = template_size;
4928 }
4929
4930 /* Already accounted for. */
4931 if (stub_entry->stub_offset != (bfd_vma) -1)
4932 return TRUE;
461a49ca 4933
906e58ca
NC		 4934 size = (size + 7) & ~7;
4935 stub_entry->stub_sec->size += size;
461a49ca 4936
906e58ca
NC		 4937 return TRUE;
4938}
4939
4940/* External entry points for sizing and building linker stubs. */
4941
4942/* Set up various things so that we can make a list of input sections
4943 for each output section included in the link. Returns -1 on error,
4944 0 when no stubs will be needed, and 1 on success. */
4945
4946int
4947elf32_arm_setup_section_lists (bfd *output_bfd,
4948 struct bfd_link_info *info)
4949{
4950 bfd *input_bfd;
4951 unsigned int bfd_count;
7292b3ac 4952 unsigned int top_id, top_index;
906e58ca
NC		 4953 asection *section;
4954 asection **input_list, **list;
4955 bfd_size_type amt;
4956 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4957
4dfe6ac6
NC		 4958 if (htab == NULL)
4959 return 0;
906e58ca
NC		 4960 if (! is_elf_hash_table (htab))
4961 return 0;
4962
4963 /* Count the number of input BFDs and find the top input section id. */
4964 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4965 input_bfd != NULL;
c72f2fb2 4966 input_bfd = input_bfd->link.next)
906e58ca
NC		 4967 {
4968 bfd_count += 1;
4969 for (section = input_bfd->sections;
4970 section != NULL;
4971 section = section->next)
4972 {
4973 if (top_id < section->id)
4974 top_id = section->id;
4975 }
4976 }
4977 htab->bfd_count = bfd_count;
4978
4979 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4980 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4981 if (htab->stub_group == NULL)
4982 return -1;
fe33d2fa 4983 htab->top_id = top_id;
906e58ca
NC		 4984
4985 /* We can't use output_bfd->section_count here to find the top output
4986 section index as some sections may have been removed, and
4987 _bfd_strip_section_from_output doesn't renumber the indices. */
4988 for (section = output_bfd->sections, top_index = 0;
4989 section != NULL;
4990 section = section->next)
4991 {
4992 if (top_index < section->index)
4993 top_index = section->index;
4994 }
4995
4996 htab->top_index = top_index;
4997 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4998 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4999 htab->input_list = input_list;
5000 if (input_list == NULL)
5001 return -1;
5002
5003 /* For sections we aren't interested in, mark their entries with a
5004 value we can check later. */
5005 list = input_list + top_index;
5006 do
5007 *list = bfd_abs_section_ptr;
5008 while (list-- != input_list);
5009
5010 for (section = output_bfd->sections;
5011 section != NULL;
5012 section = section->next)
5013 {
5014 if ((section->flags & SEC_CODE) != 0)
5015 input_list[section->index] = NULL;
5016 }
5017
5018 return 1;
5019}
5020
5021/* The linker repeatedly calls this function for each input section,
5022 in the order that input sections are linked into output sections.
5023 Build lists of input sections to determine groupings between which
5024 we may insert linker stubs. */
5025
5026void
5027elf32_arm_next_input_section (struct bfd_link_info *info,
5028 asection *isec)
5029{
5030 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5031
4dfe6ac6
NC		 5032 if (htab == NULL)
5033 return;
5034
906e58ca
NC		 5035 if (isec->output_section->index <= htab->top_index)
5036 {
5037 asection **list = htab->input_list + isec->output_section->index;
5038
a7470592 5039 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5040 {
5041 /* Steal the link_sec pointer for our list. */
5042#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5043 /* This happens to make the list in reverse order,
07d72278 5044 which we reverse later. */
906e58ca
NC		 5045 PREV_SEC (isec) = *list;
5046 *list = isec;
5047 }
5048 }
5049}
5050
5051/* See whether we can group stub sections together. Grouping stub
5052 sections may result in fewer stubs. More importantly, we need to
07d72278 5053 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5054 .fini output sections respectively, because glibc splits the
5055 _init and _fini functions into multiple parts. Putting a stub in
5056 the middle of a function is not a good idea. */
5057
5058static void
5059group_sections (struct elf32_arm_link_hash_table *htab,
5060 bfd_size_type stub_group_size,
07d72278 5061 bfd_boolean stubs_always_after_branch)
906e58ca 5062{
07d72278 5063 asection **list = htab->input_list;
906e58ca
NC		 5064
5065 do
5066 {
5067 asection *tail = *list;
07d72278 5068 asection *head;
906e58ca
NC		 5069
5070 if (tail == bfd_abs_section_ptr)
5071 continue;
5072
07d72278
DJ		 5073 /* Reverse the list: we must avoid placing stubs at the
5074 beginning of the section because the beginning of the text
5075 section may be required for an interrupt vector in bare metal
5076 code. */
5077#define NEXT_SEC PREV_SEC
e780aef2
CL		 5078 head = NULL;
5079 while (tail != NULL)
99059e56
RM		 5080 {
5081 /* Pop from tail. */
5082 asection *item = tail;
5083 tail = PREV_SEC (item);
e780aef2 5084
99059e56
RM		 5085 /* Push on head. */
5086 NEXT_SEC (item) = head;
5087 head = item;
5088 }
07d72278
DJ		 5089
5090 while (head != NULL)
906e58ca
NC		 5091 {
5092 asection *curr;
07d72278 5093 asection *next;
e780aef2
CL		 5094 bfd_vma stub_group_start = head->output_offset;
5095 bfd_vma end_of_next;
906e58ca 5096
07d72278 5097 curr = head;
e780aef2 5098 while (NEXT_SEC (curr) != NULL)
8cd931b7 5099 {
e780aef2
CL		 5100 next = NEXT_SEC (curr);
5101 end_of_next = next->output_offset + next->size;
5102 if (end_of_next - stub_group_start >= stub_group_size)
5103 /* End of NEXT is too far from start, so stop. */
8cd931b7 5104 break;
e780aef2
CL		 5105 /* Add NEXT to the group. */
5106 curr = next;
8cd931b7 5107 }
906e58ca 5108
07d72278 5109 /* OK, the size from the start to the start of CURR is less
906e58ca 5110 than stub_group_size and thus can be handled by one stub
07d72278 5111 section. (Or the head section is itself larger than
906e58ca
NC		 5112 stub_group_size, in which case we may be toast.)
5113 We should really be keeping track of the total size of
5114 stubs added here, as stubs contribute to the final output
7fb9f789 5115 section size. */
906e58ca
NC		 5116 do
5117 {
07d72278 5118 next = NEXT_SEC (head);
906e58ca 5119 /* Set up this stub group. */
07d72278 5120 htab->stub_group[head->id].link_sec = curr;
906e58ca 5121 }
07d72278 5122 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5123
5124 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5125 bytes after the stub section can be handled by it too. */
5126 if (!stubs_always_after_branch)
906e58ca 5127 {
e780aef2
CL		 5128 stub_group_start = curr->output_offset + curr->size;
5129
8cd931b7 5130 while (next != NULL)
906e58ca 5131 {
e780aef2
CL		 5132 end_of_next = next->output_offset + next->size;
5133 if (end_of_next - stub_group_start >= stub_group_size)
5134 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5135 break;
e780aef2 5136 /* Add NEXT to the stub group. */
07d72278
DJ		 5137 head = next;
5138 next = NEXT_SEC (head);
5139 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5140 }
5141 }
07d72278 5142 head = next;
906e58ca
NC		 5143 }
5144 }
07d72278 5145 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5146
5147 free (htab->input_list);
5148#undef PREV_SEC
07d72278 5149#undef NEXT_SEC
906e58ca
NC		 5150}
5151
48229727
JB		 5152/* Comparison function for sorting/searching relocations relating to Cortex-A8
5153 erratum fix. */
5154
5155static int
5156a8_reloc_compare (const void *a, const void *b)
5157{
21d799b5
NC		 5158 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5159 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5160
5161 if (ra->from < rb->from)
5162 return -1;
5163 else if (ra->from > rb->from)
5164 return 1;
5165 else
5166 return 0;
5167}
5168
5169static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5170 const char *, char **);
5171
5172/* Helper function to scan code for sequences which might trigger the Cortex-A8
5173 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5174 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5175 otherwise. */
5176
81694485
NC		 5177static bfd_boolean
5178cortex_a8_erratum_scan (bfd *input_bfd,
5179 struct bfd_link_info *info,
48229727
JB		 5180 struct a8_erratum_fix **a8_fixes_p,
5181 unsigned int *num_a8_fixes_p,
5182 unsigned int *a8_fix_table_size_p,
5183 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5184 unsigned int num_a8_relocs,
5185 unsigned prev_num_a8_fixes,
5186 bfd_boolean *stub_changed_p)
48229727
JB		 5187{
5188 asection *section;
5189 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5190 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5191 unsigned int num_a8_fixes = *num_a8_fixes_p;
5192 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5193
4dfe6ac6
NC		 5194 if (htab == NULL)
5195 return FALSE;
5196
48229727
JB		 5197 for (section = input_bfd->sections;
5198 section != NULL;
5199 section = section->next)
5200 {
5201 bfd_byte *contents = NULL;
5202 struct _arm_elf_section_data *sec_data;
5203 unsigned int span;
5204 bfd_vma base_vma;
5205
5206 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5207 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5208 || (section->flags & SEC_EXCLUDE) != 0
5209 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5210 || (section->output_section == bfd_abs_section_ptr))
5211 continue;
48229727
JB		 5212
5213 base_vma = section->output_section->vma + section->output_offset;
5214
5215 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5216 contents = elf_section_data (section)->this_hdr.contents;
48229727 5217 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5218 return TRUE;
48229727
JB		 5219
5220 sec_data = elf32_arm_section_data (section);
5221
5222 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5223 {
5224 unsigned int span_start = sec_data->map[span].vma;
5225 unsigned int span_end = (span == sec_data->mapcount - 1)
5226 ? section->size : sec_data->map[span + 1].vma;
5227 unsigned int i;
5228 char span_type = sec_data->map[span].type;
5229 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5230
5231 if (span_type != 't')
5232 continue;
5233
5234 /* Span is entirely within a single 4KB region: skip scanning. */
5235 if (((base_vma + span_start) & ~0xfff)
48229727 5236 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5237 continue;
5238
5239 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5240
5241 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5242 * The branch target is in the same 4KB region as the
5243 first half of the branch.
5244 * The instruction before the branch is a 32-bit
5245 length non-branch instruction. */
5246 for (i = span_start; i < span_end;)
5247 {
5248 unsigned int insn = bfd_getl16 (&contents[i]);
5249 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5250 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5251
99059e56
RM		 5252 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5253 insn_32bit = TRUE;
48229727
JB		 5254
5255 if (insn_32bit)
99059e56
RM		 5256 {
5257 /* Load the rest of the insn (in manual-friendly order). */
5258 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5259
5260 /* Encoding T4: B<c>.W. */
5261 is_b = (insn & 0xf800d000) == 0xf0009000;
5262 /* Encoding T1: BL<c>.W. */
5263 is_bl = (insn & 0xf800d000) == 0xf000d000;
5264 /* Encoding T2: BLX<c>.W. */
5265 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5266 /* Encoding T3: B<c>.W (not permitted in IT block). */
5267 is_bcc = (insn & 0xf800d000) == 0xf0008000
5268 && (insn & 0x07f00000) != 0x03800000;
5269 }
5270
5271 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5272
99059e56 5273 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5274 && insn_32bit
5275 && is_32bit_branch
5276 && last_was_32bit
5277 && ! last_was_branch)
99059e56
RM		 5278 {
5279 bfd_signed_vma offset = 0;
5280 bfd_boolean force_target_arm = FALSE;
48229727 5281 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5282 bfd_vma target;
5283 enum elf32_arm_stub_type stub_type = arm_stub_none;
5284 struct a8_erratum_reloc key, *found;
5285 bfd_boolean use_plt = FALSE;
48229727 5286
99059e56
RM		 5287 key.from = base_vma + i;
5288 found = (struct a8_erratum_reloc *)
5289 bsearch (&key, a8_relocs, num_a8_relocs,
5290 sizeof (struct a8_erratum_reloc),
5291 &a8_reloc_compare);
48229727
JB		 5292
5293 if (found)
5294 {
5295 char *error_message = NULL;
5296 struct elf_link_hash_entry *entry;
5297
5298 /* We don't care about the error returned from this
99059e56 5299 function, only if there is glue or not. */
48229727
JB		 5300 entry = find_thumb_glue (info, found->sym_name,
5301 &error_message);
5302
5303 if (entry)
5304 found->non_a8_stub = TRUE;
5305
92750f34 5306 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5307 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5308 && found->hash->root.plt.offset != (bfd_vma) -1)
5309 use_plt = TRUE;
5310
5311 if (found->r_type == R_ARM_THM_CALL)
5312 {
35fc36a8
RS		 5313 if (found->branch_type == ST_BRANCH_TO_ARM
5314 || use_plt)
92750f34
DJ		 5315 force_target_arm = TRUE;
5316 else
5317 force_target_thumb = TRUE;
5318 }
48229727
JB		 5319 }
5320
99059e56 5321 /* Check if we have an offending branch instruction. */
48229727
JB		 5322
5323 if (found && found->non_a8_stub)
5324 /* We've already made a stub for this instruction, e.g.
5325 it's a long branch or a Thumb->ARM stub. Assume that
5326 stub will suffice to work around the A8 erratum (see
5327 setting of always_after_branch above). */
5328 ;
99059e56
RM		 5329 else if (is_bcc)
5330 {
5331 offset = (insn & 0x7ff) << 1;
5332 offset |= (insn & 0x3f0000) >> 4;
5333 offset |= (insn & 0x2000) ? 0x40000 : 0;
5334 offset |= (insn & 0x800) ? 0x80000 : 0;
5335 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5336 if (offset & 0x100000)
5337 offset |= ~ ((bfd_signed_vma) 0xfffff);
5338 stub_type = arm_stub_a8_veneer_b_cond;
5339 }
5340 else if (is_b || is_bl || is_blx)
5341 {
5342 int s = (insn & 0x4000000) != 0;
5343 int j1 = (insn & 0x2000) != 0;
5344 int j2 = (insn & 0x800) != 0;
5345 int i1 = !(j1 ^ s);
5346 int i2 = !(j2 ^ s);
5347
5348 offset = (insn & 0x7ff) << 1;
5349 offset |= (insn & 0x3ff0000) >> 4;
5350 offset |= i2 << 22;
5351 offset |= i1 << 23;
5352 offset |= s << 24;
5353 if (offset & 0x1000000)
5354 offset |= ~ ((bfd_signed_vma) 0xffffff);
5355
5356 if (is_blx)
5357 offset &= ~ ((bfd_signed_vma) 3);
5358
5359 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5360 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5361 }
5362
5363 if (stub_type != arm_stub_none)
5364 {
5365 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5366
5367 /* The original instruction is a BL, but the target is
99059e56 5368 an ARM instruction. If we were not making a stub,
48229727
JB		 5369 the BL would have been converted to a BLX. Use the
5370 BLX stub instead in that case. */
5371 if (htab->use_blx && force_target_arm
5372 && stub_type == arm_stub_a8_veneer_bl)
5373 {
5374 stub_type = arm_stub_a8_veneer_blx;
5375 is_blx = TRUE;
5376 is_bl = FALSE;
5377 }
5378 /* Conversely, if the original instruction was
5379 BLX but the target is Thumb mode, use the BL
5380 stub. */
5381 else if (force_target_thumb
5382 && stub_type == arm_stub_a8_veneer_blx)
5383 {
5384 stub_type = arm_stub_a8_veneer_bl;
5385 is_blx = FALSE;
5386 is_bl = TRUE;
5387 }
5388
99059e56
RM		 5389 if (is_blx)
5390 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5391
99059e56
RM		 5392 /* If we found a relocation, use the proper destination,
5393 not the offset in the (unrelocated) instruction.
48229727
JB		 5394 Note this is always done if we switched the stub type
5395 above. */
99059e56
RM		 5396 if (found)
5397 offset =
81694485 5398 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5399
99059e56
RM		 5400 /* If the stub will use a Thumb-mode branch to a
5401 PLT target, redirect it to the preceding Thumb
5402 entry point. */
5403 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5404 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5405
99059e56 5406 target = pc_for_insn + offset;
48229727 5407
99059e56
RM		 5408 /* The BLX stub is ARM-mode code. Adjust the offset to
5409 take the different PC value (+8 instead of +4) into
48229727 5410 account. */
99059e56
RM		 5411 if (stub_type == arm_stub_a8_veneer_blx)
5412 offset += 4;
5413
5414 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5415 {
5416 char *stub_name = NULL;
5417
5418 if (num_a8_fixes == a8_fix_table_size)
5419 {
5420 a8_fix_table_size *= 2;
5421 a8_fixes = (struct a8_erratum_fix *)
5422 bfd_realloc (a8_fixes,
5423 sizeof (struct a8_erratum_fix)
5424 * a8_fix_table_size);
5425 }
48229727 5426
eb7c4339
NS		 5427 if (num_a8_fixes < prev_num_a8_fixes)
5428 {
5429 /* If we're doing a subsequent scan,
5430 check if we've found the same fix as
5431 before, and try and reuse the stub
5432 name. */
5433 stub_name = a8_fixes[num_a8_fixes].stub_name;
5434 if ((a8_fixes[num_a8_fixes].section != section)
5435 || (a8_fixes[num_a8_fixes].offset != i))
5436 {
5437 free (stub_name);
5438 stub_name = NULL;
5439 *stub_changed_p = TRUE;
5440 }
5441 }
5442
5443 if (!stub_name)
5444 {
21d799b5 5445 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5446 if (stub_name != NULL)
5447 sprintf (stub_name, "%x:%x", section->id, i);
5448 }
48229727 5449
99059e56
RM		 5450 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5451 a8_fixes[num_a8_fixes].section = section;
5452 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5453 a8_fixes[num_a8_fixes].target_offset =
5454 target - base_vma;
99059e56
RM		 5455 a8_fixes[num_a8_fixes].orig_insn = insn;
5456 a8_fixes[num_a8_fixes].stub_name = stub_name;
5457 a8_fixes[num_a8_fixes].stub_type = stub_type;
5458 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5459 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5460
99059e56
RM		 5461 num_a8_fixes++;
5462 }
5463 }
5464 }
48229727 5465
99059e56
RM		 5466 i += insn_32bit ? 4 : 2;
5467 last_was_32bit = insn_32bit;
48229727 5468 last_was_branch = is_32bit_branch;
99059e56
RM		 5469 }
5470 }
48229727
JB		 5471
5472 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5473 free (contents);
48229727 5474 }
fe33d2fa 5475
48229727
JB		 5476 *a8_fixes_p = a8_fixes;
5477 *num_a8_fixes_p = num_a8_fixes;
5478 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5479
81694485 5480 return FALSE;
48229727
JB		 5481}
5482
b715f643
TP		 5483/* Create or update a stub entry depending on whether the stub can already be
5484 found in HTAB. The stub is identified by:
5485 - its type STUB_TYPE
5486 - its source branch (note that several can share the same stub) whose
5487 section and relocation (if any) are given by SECTION and IRELA
5488 respectively
5489 - its target symbol whose input section, hash, name, value and branch type
5490 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5491 respectively
5492
5493 If found, the value of the stub's target symbol is updated from SYM_VALUE
5494 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5495 TRUE and the stub entry is initialized.
5496
0955507f
TP		 5497 Returns the stub that was created or updated, or NULL if an error
5498 occurred. */
b715f643 5499
0955507f 5500static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5501elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5502 enum elf32_arm_stub_type stub_type, asection *section,
5503 Elf_Internal_Rela *irela, asection *sym_sec,
5504 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5505 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5506 bfd_boolean *new_stub)
5507{
5508 const asection *id_sec;
5509 char *stub_name;
5510 struct elf32_arm_stub_hash_entry *stub_entry;
5511 unsigned int r_type;
4f4faa4d 5512 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5513
5514 BFD_ASSERT (stub_type != arm_stub_none);
5515 *new_stub = FALSE;
5516
4f4faa4d
TP		 5517 if (sym_claimed)
5518 stub_name = sym_name;
5519 else
5520 {
5521 BFD_ASSERT (irela);
5522 BFD_ASSERT (section);
c2abbbeb 5523 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5524
4f4faa4d
TP		 5525 /* Support for grouping stub sections. */
5526 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5527
4f4faa4d
TP		 5528 /* Get the name of this stub. */
5529 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5530 stub_type);
5531 if (!stub_name)
0955507f 5532 return NULL;
4f4faa4d 5533 }
b715f643
TP		 5534
5535 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5536 FALSE);
5537 /* The proper stub has already been created, just update its value. */
5538 if (stub_entry != NULL)
5539 {
4f4faa4d
TP		 5540 if (!sym_claimed)
5541 free (stub_name);
b715f643 5542 stub_entry->target_value = sym_value;
0955507f 5543 return stub_entry;
b715f643
TP		 5544 }
5545
daa4adae 5546 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5547 if (stub_entry == NULL)
5548 {
4f4faa4d
TP		 5549 if (!sym_claimed)
5550 free (stub_name);
0955507f 5551 return NULL;
b715f643
TP		 5552 }
5553
5554 stub_entry->target_value = sym_value;
5555 stub_entry->target_section = sym_sec;
5556 stub_entry->stub_type = stub_type;
5557 stub_entry->h = hash;
5558 stub_entry->branch_type = branch_type;
5559
4f4faa4d
TP		 5560 if (sym_claimed)
5561 stub_entry->output_name = sym_name;
5562 else
b715f643 5563 {
4f4faa4d
TP		 5564 if (sym_name == NULL)
5565 sym_name = "unnamed";
5566 stub_entry->output_name = (char *)
5567 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5568 + strlen (sym_name));
5569 if (stub_entry->output_name == NULL)
5570 {
5571 free (stub_name);
0955507f 5572 return NULL;
4f4faa4d 5573 }
b715f643 5574
4f4faa4d
TP		 5575 /* For historical reasons, use the existing names for ARM-to-Thumb and
5576 Thumb-to-ARM stubs. */
5577 r_type = ELF32_R_TYPE (irela->r_info);
5578 if ((r_type == (unsigned int) R_ARM_THM_CALL
5579 || r_type == (unsigned int) R_ARM_THM_JUMP24
5580 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5581 && branch_type == ST_BRANCH_TO_ARM)
5582 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5583 else if ((r_type == (unsigned int) R_ARM_CALL
5584 || r_type == (unsigned int) R_ARM_JUMP24)
5585 && branch_type == ST_BRANCH_TO_THUMB)
5586 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5587 else
5588 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5589 }
b715f643
TP		 5590
5591 *new_stub = TRUE;
0955507f 5592 return stub_entry;
b715f643
TP		 5593}
5594
4ba2ef8f
TP		 5595/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5596 gateway veneer to transition from non secure to secure state and create them
5597 accordingly.
5598
5599 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5600 defines the conditions that govern Secure Gateway veneer creation for a
5601 given symbol <SYM> as follows:
5602 - it has function type
5603 - it has non local binding
5604 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5605 same type, binding and value as <SYM> (called normal symbol).
5606 An entry function can handle secure state transition itself in which case
5607 its special symbol would have a different value from the normal symbol.
5608
5609 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5610 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5611 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5612 created.
4ba2ef8f 5613
0955507f 5614 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5615
5616static bfd_boolean
5617cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5618 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5619 int *cmse_stub_created)
4ba2ef8f
TP		 5620{
5621 const struct elf_backend_data *bed;
5622 Elf_Internal_Shdr *symtab_hdr;
5623 unsigned i, j, sym_count, ext_start;
5624 Elf_Internal_Sym *cmse_sym, *local_syms;
5625 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5626 enum arm_st_branch_type branch_type;
5627 char *sym_name, *lsym_name;
5628 bfd_vma sym_value;
5629 asection *section;
0955507f
TP		 5630 struct elf32_arm_stub_hash_entry *stub_entry;
5631 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5632
5633 bed = get_elf_backend_data (input_bfd);
5634 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5635 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5636 ext_start = symtab_hdr->sh_info;
5637 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5638 && out_attr[Tag_CPU_arch_profile].i == 'M');
5639
5640 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5641 if (local_syms == NULL)
5642 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5643 symtab_hdr->sh_info, 0, NULL, NULL,
5644 NULL);
5645 if (symtab_hdr->sh_info && local_syms == NULL)
5646 return FALSE;
5647
5648 /* Scan symbols. */
5649 for (i = 0; i < sym_count; i++)
5650 {
5651 cmse_invalid = FALSE;
5652
5653 if (i < ext_start)
5654 {
5655 cmse_sym = &local_syms[i];
5656 /* Not a special symbol. */
5657 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5658 continue;
5659 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5660 symtab_hdr->sh_link,
5661 cmse_sym->st_name);
5662 /* Special symbol with local binding. */
5663 cmse_invalid = TRUE;
5664 }
5665 else
5666 {
5667 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5668 sym_name = (char *) cmse_hash->root.root.root.string;
5669
5670 /* Not a special symbol. */
5671 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5672 continue;
5673
5674 /* Special symbol has incorrect binding or type. */
5675 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5676 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5677 || cmse_hash->root.type != STT_FUNC)
5678 cmse_invalid = TRUE;
5679 }
5680
5681 if (!is_v8m)
5682 {
90b6238f
AM		 5683 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5684 "ARMv8-M architecture or later"),
4eca0228 5685 input_bfd, sym_name);
4ba2ef8f
TP		 5686 is_v8m = TRUE; /* Avoid multiple warning. */
5687 ret = FALSE;
5688 }
5689
5690 if (cmse_invalid)
5691 {
90b6238f
AM		 5692 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
5693 " a global or weak function symbol"),
4eca0228 5694 input_bfd, sym_name);
4ba2ef8f
TP		 5695 ret = FALSE;
5696 if (i < ext_start)
5697 continue;
5698 }
5699
5700 sym_name += strlen (CMSE_PREFIX);
5701 hash = (struct elf32_arm_link_hash_entry *)
5702 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5703
5704 /* No associated normal symbol or it is neither global nor weak. */
5705 if (!hash
5706 || (hash->root.root.type != bfd_link_hash_defined
5707 && hash->root.root.type != bfd_link_hash_defweak)
5708 || hash->root.type != STT_FUNC)
5709 {
5710 /* Initialize here to avoid warning about use of possibly
5711 uninitialized variable. */
5712 j = 0;
5713
5714 if (!hash)
5715 {
5716 /* Searching for a normal symbol with local binding. */
5717 for (; j < ext_start; j++)
5718 {
5719 lsym_name =
5720 bfd_elf_string_from_elf_section (input_bfd,
5721 symtab_hdr->sh_link,
5722 local_syms[j].st_name);
5723 if (!strcmp (sym_name, lsym_name))
5724 break;
5725 }
5726 }
5727
5728 if (hash || j < ext_start)
5729 {
4eca0228 5730 _bfd_error_handler
90b6238f
AM		 5731 (_("%pB: invalid standard symbol `%s'; it must be "
5732 "a global or weak function symbol"),
5733 input_bfd, sym_name);
4ba2ef8f
TP		 5734 }
5735 else
4eca0228 5736 _bfd_error_handler
90b6238f 5737 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 5738 ret = FALSE;
5739 if (!hash)
5740 continue;
5741 }
5742
5743 sym_value = hash->root.root.u.def.value;
5744 section = hash->root.root.u.def.section;
5745
5746 if (cmse_hash->root.root.u.def.section != section)
5747 {
4eca0228 5748 _bfd_error_handler
90b6238f 5749 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 5750 input_bfd, sym_name);
5751 ret = FALSE;
5752 }
5753 if (cmse_hash->root.root.u.def.value != sym_value)
5754 continue; /* Ignore: could be an entry function starting with SG. */
5755
5756 /* If this section is a link-once section that will be discarded, then
5757 don't create any stubs. */
5758 if (section->output_section == NULL)
5759 {
4eca0228 5760 _bfd_error_handler
90b6238f 5761 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 5762 continue;
5763 }
5764
5765 if (hash->root.size == 0)
5766 {
4eca0228 5767 _bfd_error_handler
90b6238f 5768 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 5769 ret = FALSE;
5770 }
5771
5772 if (!ret)
5773 continue;
5774 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5775 stub_entry
4ba2ef8f
TP		 5776 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5777 NULL, NULL, section, hash, sym_name,
5778 sym_value, branch_type, &new_stub);
5779
0955507f 5780 if (stub_entry == NULL)
4ba2ef8f
TP		 5781 ret = FALSE;
5782 else
5783 {
5784 BFD_ASSERT (new_stub);
0955507f 5785 (*cmse_stub_created)++;
4ba2ef8f
TP		 5786 }
5787 }
5788
5789 if (!symtab_hdr->contents)
5790 free (local_syms);
5791 return ret;
5792}
5793
0955507f
TP		 5794/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5795 code entry function, ie can be called from non secure code without using a
5796 veneer. */
5797
5798static bfd_boolean
5799cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5800{
42484486 5801 bfd_byte contents[4];
0955507f
TP		 5802 uint32_t first_insn;
5803 asection *section;
5804 file_ptr offset;
5805 bfd *abfd;
5806
5807 /* Defined symbol of function type. */
5808 if (hash->root.root.type != bfd_link_hash_defined
5809 && hash->root.root.type != bfd_link_hash_defweak)
5810 return FALSE;
5811 if (hash->root.type != STT_FUNC)
5812 return FALSE;
5813
5814 /* Read first instruction. */
5815 section = hash->root.root.u.def.section;
5816 abfd = section->owner;
5817 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5818 if (!bfd_get_section_contents (abfd, section, contents, offset,
5819 sizeof (contents)))
0955507f
TP		 5820 return FALSE;
5821
42484486
TP		 5822 first_insn = bfd_get_32 (abfd, contents);
5823
5824 /* Starts by SG instruction. */
0955507f
TP		 5825 return first_insn == 0xe97fe97f;
5826}
5827
5828/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5829 secure gateway veneers (ie. the veneers was not in the input import library)
5830 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5831
5832static bfd_boolean
5833arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5834{
5835 struct elf32_arm_stub_hash_entry *stub_entry;
5836 struct bfd_link_info *info;
5837
5838 /* Massage our args to the form they really have. */
5839 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5840 info = (struct bfd_link_info *) gen_info;
5841
5842 if (info->out_implib_bfd)
5843 return TRUE;
5844
5845 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5846 return TRUE;
5847
5848 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5849 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5850
5851 return TRUE;
5852}
5853
5854/* Set offset of each secure gateway veneers so that its address remain
5855 identical to the one in the input import library referred by
5856 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5857 (present in input import library but absent from the executable being
5858 linked) or if new veneers appeared and there is no output import library
5859 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5860 number of secure gateway veneers found in the input import library.
5861
5862 The function returns whether an error occurred. If no error occurred,
5863 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5864 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5865 veneer observed set for new veneers to be layed out after. */
5866
5867static bfd_boolean
5868set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5869 struct elf32_arm_link_hash_table *htab,
5870 int *cmse_stub_created)
5871{
5872 long symsize;
5873 char *sym_name;
5874 flagword flags;
5875 long i, symcount;
5876 bfd *in_implib_bfd;
5877 asection *stub_out_sec;
5878 bfd_boolean ret = TRUE;
5879 Elf_Internal_Sym *intsym;
5880 const char *out_sec_name;
5881 bfd_size_type cmse_stub_size;
5882 asymbol **sympp = NULL, *sym;
5883 struct elf32_arm_link_hash_entry *hash;
5884 const insn_sequence *cmse_stub_template;
5885 struct elf32_arm_stub_hash_entry *stub_entry;
5886 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5887 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5888 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5889
5890 /* No input secure gateway import library. */
5891 if (!htab->in_implib_bfd)
5892 return TRUE;
5893
5894 in_implib_bfd = htab->in_implib_bfd;
5895 if (!htab->cmse_implib)
5896 {
871b3ab2 5897 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 5898 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 5899 return FALSE;
5900 }
5901
5902 /* Get symbol table size. */
5903 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5904 if (symsize < 0)
5905 return FALSE;
5906
5907 /* Read in the input secure gateway import library's symbol table. */
5908 sympp = (asymbol **) xmalloc (symsize);
5909 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5910 if (symcount < 0)
5911 {
5912 ret = FALSE;
5913 goto free_sym_buf;
5914 }
5915
5916 htab->new_cmse_stub_offset = 0;
5917 cmse_stub_size =
5918 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5919 &cmse_stub_template,
5920 &cmse_stub_template_size);
5921 out_sec_name =
5922 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5923 stub_out_sec =
5924 bfd_get_section_by_name (htab->obfd, out_sec_name);
5925 if (stub_out_sec != NULL)
5926 cmse_stub_sec_vma = stub_out_sec->vma;
5927
5928 /* Set addresses of veneers mentionned in input secure gateway import
5929 library's symbol table. */
5930 for (i = 0; i < symcount; i++)
5931 {
5932 sym = sympp[i];
5933 flags = sym->flags;
5934 sym_name = (char *) bfd_asymbol_name (sym);
5935 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5936
5937 if (sym->section != bfd_abs_section_ptr
5938 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5939 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5940 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5941 != ST_BRANCH_TO_THUMB))
5942 {
90b6238f
AM		 5943 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
5944 "symbol should be absolute, global and "
5945 "refer to Thumb functions"),
4eca0228 5946 in_implib_bfd, sym_name);
0955507f
TP		 5947 ret = FALSE;
5948 continue;
5949 }
5950
5951 veneer_value = bfd_asymbol_value (sym);
5952 stub_offset = veneer_value - cmse_stub_sec_vma;
5953 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5954 FALSE, FALSE);
5955 hash = (struct elf32_arm_link_hash_entry *)
5956 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5957
5958 /* Stub entry should have been created by cmse_scan or the symbol be of
5959 a secure function callable from non secure code. */
5960 if (!stub_entry && !hash)
5961 {
5962 bfd_boolean new_stub;
5963
4eca0228 5964 _bfd_error_handler
90b6238f 5965 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 5966 hash = (struct elf32_arm_link_hash_entry *)
5967 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5968 stub_entry
5969 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5970 NULL, NULL, bfd_abs_section_ptr, hash,
5971 sym_name, veneer_value,
5972 ST_BRANCH_TO_THUMB, &new_stub);
5973 if (stub_entry == NULL)
5974 ret = FALSE;
5975 else
5976 {
5977 BFD_ASSERT (new_stub);
5978 new_cmse_stubs_created++;
5979 (*cmse_stub_created)++;
5980 }
5981 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5982 stub_entry->stub_offset = stub_offset;
5983 }
5984 /* Symbol found is not callable from non secure code. */
5985 else if (!stub_entry)
5986 {
5987 if (!cmse_entry_fct_p (hash))
5988 {
90b6238f 5989 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 5990 sym_name);
0955507f
TP		 5991 ret = FALSE;
5992 }
5993 continue;
5994 }
5995 else
5996 {
5997 /* Only stubs for SG veneers should have been created. */
5998 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5999
6000 /* Check visibility hasn't changed. */
6001 if (!!(flags & BSF_GLOBAL)
6002 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6003 _bfd_error_handler
90b6238f 6004 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6005 sym_name);
6006
6007 stub_entry->stub_offset = stub_offset;
6008 }
6009
6010 /* Size should match that of a SG veneer. */
6011 if (intsym->st_size != cmse_stub_size)
6012 {
90b6238f 6013 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6014 in_implib_bfd, sym_name);
0955507f
TP		 6015 ret = FALSE;
6016 }
6017
6018 /* Previous veneer address is before current SG veneer section. */
6019 if (veneer_value < cmse_stub_sec_vma)
6020 {
6021 /* Avoid offset underflow. */
6022 if (stub_entry)
6023 stub_entry->stub_offset = 0;
6024 stub_offset = 0;
6025 ret = FALSE;
6026 }
6027
6028 /* Complain if stub offset not a multiple of stub size. */
6029 if (stub_offset % cmse_stub_size)
6030 {
4eca0228 6031 _bfd_error_handler
90b6238f
AM		 6032 (_("offset of veneer for entry function `%s' not a multiple of "
6033 "its size"), sym_name);
0955507f
TP		 6034 ret = FALSE;
6035 }
6036
6037 if (!ret)
6038 continue;
6039
6040 new_cmse_stubs_created--;
6041 if (veneer_value < cmse_stub_array_start)
6042 cmse_stub_array_start = veneer_value;
6043 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6044 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6045 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6046 }
6047
6048 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6049 {
6050 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6051 _bfd_error_handler
0955507f
TP		 6052 (_("new entry function(s) introduced but no output import library "
6053 "specified:"));
6054 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6055 }
6056
6057 if (cmse_stub_array_start != cmse_stub_sec_vma)
6058 {
4eca0228 6059 _bfd_error_handler
90b6238f 6060 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6061 out_sec_name);
6062 ret = FALSE;
6063 }
6064
6065free_sym_buf:
6066 free (sympp);
6067 return ret;
6068}
6069
906e58ca
NC		 6070/* Determine and set the size of the stub section for a final link.
6071
6072 The basic idea here is to examine all the relocations looking for
6073 PC-relative calls to a target that is unreachable with a "bl"
6074 instruction. */
6075
6076bfd_boolean
6077elf32_arm_size_stubs (bfd *output_bfd,
6078 bfd *stub_bfd,
6079 struct bfd_link_info *info,
6080 bfd_signed_vma group_size,
7a89b94e 6081 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6082 asection *,
7a89b94e 6083 unsigned int),
906e58ca
NC		 6084 void (*layout_sections_again) (void))
6085{
0955507f 6086 bfd_boolean ret = TRUE;
4ba2ef8f 6087 obj_attribute *out_attr;
0955507f 6088 int cmse_stub_created = 0;
906e58ca 6089 bfd_size_type stub_group_size;
4ba2ef8f 6090 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6091 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6092 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6093 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6094 struct a8_erratum_reloc *a8_relocs = NULL;
6095 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6096
4dfe6ac6
NC		 6097 if (htab == NULL)
6098 return FALSE;
6099
48229727
JB		 6100 if (htab->fix_cortex_a8)
6101 {
21d799b5 6102 a8_fixes = (struct a8_erratum_fix *)
99059e56 6103 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6104 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6105 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6106 }
906e58ca
NC		 6107
6108 /* Propagate mach to stub bfd, because it may not have been
6109 finalized when we created stub_bfd. */
6110 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6111 bfd_get_mach (output_bfd));
6112
6113 /* Stash our params away. */
6114 htab->stub_bfd = stub_bfd;
6115 htab->add_stub_section = add_stub_section;
6116 htab->layout_sections_again = layout_sections_again;
07d72278 6117 stubs_always_after_branch = group_size < 0;
48229727 6118
4ba2ef8f
TP		 6119 out_attr = elf_known_obj_attributes_proc (output_bfd);
6120 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6121
48229727
JB		 6122 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6123 as the first half of a 32-bit branch straddling two 4K pages. This is a
6124 crude way of enforcing that. */
6125 if (htab->fix_cortex_a8)
6126 stubs_always_after_branch = 1;
6127
906e58ca
NC		 6128 if (group_size < 0)
6129 stub_group_size = -group_size;
6130 else
6131 stub_group_size = group_size;
6132
6133 if (stub_group_size == 1)
6134 {
6135 /* Default values. */
6136 /* Thumb branch range is +-4MB has to be used as the default
6137 maximum size (a given section can contain both ARM and Thumb
6138 code, so the worst case has to be taken into account).
6139
6140 This value is 24K less than that, which allows for 2025
6141 12-byte stubs. If we exceed that, then we will fail to link.
6142 The user will have to relink with an explicit group size
6143 option. */
6144 stub_group_size = 4170000;
6145 }
6146
07d72278 6147 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6148
3ae046cc
NS		 6149 /* If we're applying the cortex A8 fix, we need to determine the
6150 program header size now, because we cannot change it later --
6151 that could alter section placements. Notice the A8 erratum fix
6152 ends up requiring the section addresses to remain unchanged
6153 modulo the page size. That's something we cannot represent
6154 inside BFD, and we don't want to force the section alignment to
6155 be the page size. */
6156 if (htab->fix_cortex_a8)
6157 (*htab->layout_sections_again) ();
6158
906e58ca
NC		 6159 while (1)
6160 {
6161 bfd *input_bfd;
6162 unsigned int bfd_indx;
6163 asection *stub_sec;
d7c5bd02 6164 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6165 bfd_boolean stub_changed = FALSE;
6166 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6167
48229727 6168 num_a8_fixes = 0;
906e58ca
NC		 6169 for (input_bfd = info->input_bfds, bfd_indx = 0;
6170 input_bfd != NULL;
c72f2fb2 6171 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6172 {
6173 Elf_Internal_Shdr *symtab_hdr;
6174 asection *section;
6175 Elf_Internal_Sym *local_syms = NULL;
6176
99059e56
RM		 6177 if (!is_arm_elf (input_bfd))
6178 continue;
adbcc655 6179
48229727
JB		 6180 num_a8_relocs = 0;
6181
906e58ca
NC		 6182 /* We'll need the symbol table in a second. */
6183 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6184 if (symtab_hdr->sh_info == 0)
6185 continue;
6186
4ba2ef8f
TP		 6187 /* Limit scan of symbols to object file whose profile is
6188 Microcontroller to not hinder performance in the general case. */
6189 if (m_profile && first_veneer_scan)
6190 {
6191 struct elf_link_hash_entry **sym_hashes;
6192
6193 sym_hashes = elf_sym_hashes (input_bfd);
6194 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6195 &cmse_stub_created))
4ba2ef8f 6196 goto error_ret_free_local;
0955507f
TP		 6197
6198 if (cmse_stub_created != 0)
6199 stub_changed = TRUE;
4ba2ef8f
TP		 6200 }
6201
906e58ca
NC		 6202 /* Walk over each section attached to the input bfd. */
6203 for (section = input_bfd->sections;
6204 section != NULL;
6205 section = section->next)
6206 {
6207 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6208
6209 /* If there aren't any relocs, then there's nothing more
6210 to do. */
6211 if ((section->flags & SEC_RELOC) == 0
6212 || section->reloc_count == 0
6213 || (section->flags & SEC_CODE) == 0)
6214 continue;
6215
6216 /* If this section is a link-once section that will be
6217 discarded, then don't create any stubs. */
6218 if (section->output_section == NULL
6219 || section->output_section->owner != output_bfd)
6220 continue;
6221
6222 /* Get the relocs. */
6223 internal_relocs
6224 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6225 NULL, info->keep_memory);
6226 if (internal_relocs == NULL)
6227 goto error_ret_free_local;
6228
6229 /* Now examine each relocation. */
6230 irela = internal_relocs;
6231 irelaend = irela + section->reloc_count;
6232 for (; irela < irelaend; irela++)
6233 {
6234 unsigned int r_type, r_indx;
906e58ca
NC		 6235 asection *sym_sec;
6236 bfd_vma sym_value;
6237 bfd_vma destination;
6238 struct elf32_arm_link_hash_entry *hash;
7413f23f 6239 const char *sym_name;
34e77a92 6240 unsigned char st_type;
35fc36a8 6241 enum arm_st_branch_type branch_type;
48229727 6242 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6243
6244 r_type = ELF32_R_TYPE (irela->r_info);
6245 r_indx = ELF32_R_SYM (irela->r_info);
6246
6247 if (r_type >= (unsigned int) R_ARM_max)
6248 {
6249 bfd_set_error (bfd_error_bad_value);
6250 error_ret_free_internal:
6251 if (elf_section_data (section)->relocs == NULL)
6252 free (internal_relocs);
15dd01b1
TP		 6253 /* Fall through. */
6254 error_ret_free_local:
6255 if (local_syms != NULL
6256 && (symtab_hdr->contents
6257 != (unsigned char *) local_syms))
6258 free (local_syms);
6259 return FALSE;
906e58ca 6260 }
b38cadfb 6261
0855e32b
NS		 6262 hash = NULL;
6263 if (r_indx >= symtab_hdr->sh_info)
6264 hash = elf32_arm_hash_entry
6265 (elf_sym_hashes (input_bfd)
6266 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6267
0855e32b
NS		 6268 /* Only look for stubs on branch instructions, or
6269 non-relaxed TLSCALL */
906e58ca 6270 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6271 && (r_type != (unsigned int) R_ARM_THM_CALL)
6272 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6273 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6274 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6275 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6276 && (r_type != (unsigned int) R_ARM_PLT32)
6277 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6278 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6279 && r_type == elf32_arm_tls_transition
6280 (info, r_type, &hash->root)
6281 && ((hash ? hash->tls_type
6282 : (elf32_arm_local_got_tls_type
6283 (input_bfd)[r_indx]))
6284 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6285 continue;
6286
6287 /* Now determine the call target, its name, value,
6288 section. */
6289 sym_sec = NULL;
6290 sym_value = 0;
6291 destination = 0;
7413f23f 6292 sym_name = NULL;
b38cadfb 6293
0855e32b
NS		 6294 if (r_type == (unsigned int) R_ARM_TLS_CALL
6295 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6296 {
6297 /* A non-relaxed TLS call. The target is the
6298 plt-resident trampoline and nothing to do
6299 with the symbol. */
6300 BFD_ASSERT (htab->tls_trampoline > 0);
6301 sym_sec = htab->root.splt;
6302 sym_value = htab->tls_trampoline;
6303 hash = 0;
34e77a92 6304 st_type = STT_FUNC;
35fc36a8 6305 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6306 }
6307 else if (!hash)
906e58ca
NC		 6308 {
6309 /* It's a local symbol. */
6310 Elf_Internal_Sym *sym;
906e58ca
NC		 6311
6312 if (local_syms == NULL)
6313 {
6314 local_syms
6315 = (Elf_Internal_Sym *) symtab_hdr->contents;
6316 if (local_syms == NULL)
6317 local_syms
6318 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6319 symtab_hdr->sh_info, 0,
6320 NULL, NULL, NULL);
6321 if (local_syms == NULL)
6322 goto error_ret_free_internal;
6323 }
6324
6325 sym = local_syms + r_indx;
f6d250ce
TS		 6326 if (sym->st_shndx == SHN_UNDEF)
6327 sym_sec = bfd_und_section_ptr;
6328 else if (sym->st_shndx == SHN_ABS)
6329 sym_sec = bfd_abs_section_ptr;
6330 else if (sym->st_shndx == SHN_COMMON)
6331 sym_sec = bfd_com_section_ptr;
6332 else
6333 sym_sec =
6334 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6335
ffcb4889
NS		 6336 if (!sym_sec)
6337 /* This is an undefined symbol. It can never
6a631e86 6338 be resolved. */
ffcb4889 6339 continue;
fe33d2fa 6340
906e58ca
NC		 6341 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6342 sym_value = sym->st_value;
6343 destination = (sym_value + irela->r_addend
6344 + sym_sec->output_offset
6345 + sym_sec->output_section->vma);
34e77a92 6346 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6347 branch_type =
6348 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6349 sym_name
6350 = bfd_elf_string_from_elf_section (input_bfd,
6351 symtab_hdr->sh_link,
6352 sym->st_name);
906e58ca
NC		 6353 }
6354 else
6355 {
6356 /* It's an external symbol. */
906e58ca
NC		 6357 while (hash->root.root.type == bfd_link_hash_indirect
6358 || hash->root.root.type == bfd_link_hash_warning)
6359 hash = ((struct elf32_arm_link_hash_entry *)
6360 hash->root.root.u.i.link);
6361
6362 if (hash->root.root.type == bfd_link_hash_defined
6363 || hash->root.root.type == bfd_link_hash_defweak)
6364 {
6365 sym_sec = hash->root.root.u.def.section;
6366 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6367
6368 struct elf32_arm_link_hash_table *globals =
6369 elf32_arm_hash_table (info);
6370
6371 /* For a destination in a shared library,
6372 use the PLT stub as target address to
6373 decide whether a branch stub is
6374 needed. */
4dfe6ac6 6375 if (globals != NULL
362d30a1 6376 && globals->root.splt != NULL
4dfe6ac6 6377 && hash != NULL
022f8312
CL		 6378 && hash->root.plt.offset != (bfd_vma) -1)
6379 {
362d30a1 6380 sym_sec = globals->root.splt;
022f8312
CL		 6381 sym_value = hash->root.plt.offset;
6382 if (sym_sec->output_section != NULL)
6383 destination = (sym_value
6384 + sym_sec->output_offset
6385 + sym_sec->output_section->vma);
6386 }
6387 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6388 destination = (sym_value + irela->r_addend
6389 + sym_sec->output_offset
6390 + sym_sec->output_section->vma);
6391 }
69c5861e
CL		 6392 else if ((hash->root.root.type == bfd_link_hash_undefined)
6393 || (hash->root.root.type == bfd_link_hash_undefweak))
6394 {
6395 /* For a shared library, use the PLT stub as
6396 target address to decide whether a long
6397 branch stub is needed.
6398 For absolute code, they cannot be handled. */
6399 struct elf32_arm_link_hash_table *globals =
6400 elf32_arm_hash_table (info);
6401
4dfe6ac6 6402 if (globals != NULL
362d30a1 6403 && globals->root.splt != NULL
4dfe6ac6 6404 && hash != NULL
69c5861e
CL		 6405 && hash->root.plt.offset != (bfd_vma) -1)
6406 {
362d30a1 6407 sym_sec = globals->root.splt;
69c5861e
CL		 6408 sym_value = hash->root.plt.offset;
6409 if (sym_sec->output_section != NULL)
6410 destination = (sym_value
6411 + sym_sec->output_offset
6412 + sym_sec->output_section->vma);
6413 }
6414 else
6415 continue;
6416 }
906e58ca
NC		 6417 else
6418 {
6419 bfd_set_error (bfd_error_bad_value);
6420 goto error_ret_free_internal;
6421 }
34e77a92 6422 st_type = hash->root.type;
39d911fc
TP		 6423 branch_type =
6424 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6425 sym_name = hash->root.root.root.string;
906e58ca
NC		 6426 }
6427
48229727 6428 do
7413f23f 6429 {
b715f643 6430 bfd_boolean new_stub;
0955507f 6431 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6432
48229727
JB		 6433 /* Determine what (if any) linker stub is needed. */
6434 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6435 st_type, &branch_type,
6436 hash, destination, sym_sec,
48229727
JB		 6437 input_bfd, sym_name);
6438 if (stub_type == arm_stub_none)
6439 break;
6440
48229727
JB		 6441 /* We've either created a stub for this reloc already,
6442 or we are about to. */
0955507f 6443 stub_entry =
b715f643
TP		 6444 elf32_arm_create_stub (htab, stub_type, section, irela,
6445 sym_sec, hash,
6446 (char *) sym_name, sym_value,
6447 branch_type, &new_stub);
7413f23f 6448
0955507f 6449 created_stub = stub_entry != NULL;
b715f643
TP		 6450 if (!created_stub)
6451 goto error_ret_free_internal;
6452 else if (!new_stub)
6453 break;
99059e56 6454 else
b715f643 6455 stub_changed = TRUE;
99059e56
RM		 6456 }
6457 while (0);
6458
6459 /* Look for relocations which might trigger Cortex-A8
6460 erratum. */
6461 if (htab->fix_cortex_a8
6462 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6463 || r_type == (unsigned int) R_ARM_THM_JUMP19
6464 || r_type == (unsigned int) R_ARM_THM_CALL
6465 || r_type == (unsigned int) R_ARM_THM_XPC22))
6466 {
6467 bfd_vma from = section->output_section->vma
6468 + section->output_offset
6469 + irela->r_offset;
6470
6471 if ((from & 0xfff) == 0xffe)
6472 {
6473 /* Found a candidate. Note we haven't checked the
6474 destination is within 4K here: if we do so (and
6475 don't create an entry in a8_relocs) we can't tell
6476 that a branch should have been relocated when
6477 scanning later. */
6478 if (num_a8_relocs == a8_reloc_table_size)
6479 {
6480 a8_reloc_table_size *= 2;
6481 a8_relocs = (struct a8_erratum_reloc *)
6482 bfd_realloc (a8_relocs,
6483 sizeof (struct a8_erratum_reloc)
6484 * a8_reloc_table_size);
6485 }
6486
6487 a8_relocs[num_a8_relocs].from = from;
6488 a8_relocs[num_a8_relocs].destination = destination;
6489 a8_relocs[num_a8_relocs].r_type = r_type;
6490 a8_relocs[num_a8_relocs].branch_type = branch_type;
6491 a8_relocs[num_a8_relocs].sym_name = sym_name;
6492 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6493 a8_relocs[num_a8_relocs].hash = hash;
6494
6495 num_a8_relocs++;
6496 }
6497 }
906e58ca
NC		 6498 }
6499
99059e56
RM		 6500 /* We're done with the internal relocs, free them. */
6501 if (elf_section_data (section)->relocs == NULL)
6502 free (internal_relocs);
6503 }
48229727 6504
99059e56 6505 if (htab->fix_cortex_a8)
48229727 6506 {
99059e56
RM		 6507 /* Sort relocs which might apply to Cortex-A8 erratum. */
6508 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6509 sizeof (struct a8_erratum_reloc),
99059e56 6510 &a8_reloc_compare);
48229727 6511
99059e56
RM		 6512 /* Scan for branches which might trigger Cortex-A8 erratum. */
6513 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6514 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6515 a8_relocs, num_a8_relocs,
6516 prev_num_a8_fixes, &stub_changed)
6517 != 0)
48229727 6518 goto error_ret_free_local;
5e681ec4 6519 }
7f991970
AM		 6520
6521 if (local_syms != NULL
6522 && symtab_hdr->contents != (unsigned char *) local_syms)
6523 {
6524 if (!info->keep_memory)
6525 free (local_syms);
6526 else
6527 symtab_hdr->contents = (unsigned char *) local_syms;
6528 }
5e681ec4
PB		 6529 }
6530
0955507f
TP		 6531 if (first_veneer_scan
6532 && !set_cmse_veneer_addr_from_implib (info, htab,
6533 &cmse_stub_created))
6534 ret = FALSE;
6535
eb7c4339 6536 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6537 stub_changed = TRUE;
48229727 6538
906e58ca
NC		 6539 if (!stub_changed)
6540 break;
5e681ec4 6541
906e58ca
NC		 6542 /* OK, we've added some stubs. Find out the new size of the
6543 stub sections. */
6544 for (stub_sec = htab->stub_bfd->sections;
6545 stub_sec != NULL;
6546 stub_sec = stub_sec->next)
3e6b1042
DJ		 6547 {
6548 /* Ignore non-stub sections. */
6549 if (!strstr (stub_sec->name, STUB_SUFFIX))
6550 continue;
6551
6552 stub_sec->size = 0;
6553 }
b34b2d70 6554
0955507f
TP		 6555 /* Add new SG veneers after those already in the input import
6556 library. */
6557 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6558 stub_type++)
6559 {
6560 bfd_vma *start_offset_p;
6561 asection **stub_sec_p;
6562
6563 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6564 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6565 if (start_offset_p == NULL)
6566 continue;
6567
6568 BFD_ASSERT (stub_sec_p != NULL);
6569 if (*stub_sec_p != NULL)
6570 (*stub_sec_p)->size = *start_offset_p;
6571 }
6572
d7c5bd02 6573 /* Compute stub section size, considering padding. */
906e58ca 6574 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6575 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6576 stub_type++)
6577 {
6578 int size, padding;
6579 asection **stub_sec_p;
6580
6581 padding = arm_dedicated_stub_section_padding (stub_type);
6582 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6583 /* Skip if no stub input section or no stub section padding
6584 required. */
6585 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6586 continue;
6587 /* Stub section padding required but no dedicated section. */
6588 BFD_ASSERT (stub_sec_p);
6589
6590 size = (*stub_sec_p)->size;
6591 size = (size + padding - 1) & ~(padding - 1);
6592 (*stub_sec_p)->size = size;
6593 }
906e58ca 6594
48229727
JB		 6595 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6596 if (htab->fix_cortex_a8)
99059e56
RM		 6597 for (i = 0; i < num_a8_fixes; i++)
6598 {
48229727 6599 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6600 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6601
6602 if (stub_sec == NULL)
7f991970 6603 return FALSE;
48229727 6604
99059e56
RM		 6605 stub_sec->size
6606 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6607 NULL);
6608 }
48229727
JB		 6609
6610
906e58ca
NC		 6611 /* Ask the linker to do its stuff. */
6612 (*htab->layout_sections_again) ();
4ba2ef8f 6613 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6614 }
6615
48229727
JB		 6616 /* Add stubs for Cortex-A8 erratum fixes now. */
6617 if (htab->fix_cortex_a8)
6618 {
6619 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6620 {
6621 struct elf32_arm_stub_hash_entry *stub_entry;
6622 char *stub_name = a8_fixes[i].stub_name;
6623 asection *section = a8_fixes[i].section;
6624 unsigned int section_id = a8_fixes[i].section->id;
6625 asection *link_sec = htab->stub_group[section_id].link_sec;
6626 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6627 const insn_sequence *template_sequence;
6628 int template_size, size = 0;
6629
6630 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6631 TRUE, FALSE);
6632 if (stub_entry == NULL)
6633 {
871b3ab2 6634 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6635 section->owner, stub_name);
99059e56
RM		 6636 return FALSE;
6637 }
6638
6639 stub_entry->stub_sec = stub_sec;
0955507f 6640 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6641 stub_entry->id_sec = link_sec;
6642 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6643 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6644 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6645 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6646 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6647 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6648
99059e56
RM		 6649 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6650 &template_sequence,
6651 &template_size);
48229727 6652
99059e56
RM		 6653 stub_entry->stub_size = size;
6654 stub_entry->stub_template = template_sequence;
6655 stub_entry->stub_template_size = template_size;
6656 }
48229727
JB		 6657
6658 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6659 elf32_arm_write_section(). */
48229727
JB		 6660 htab->a8_erratum_fixes = a8_fixes;
6661 htab->num_a8_erratum_fixes = num_a8_fixes;
6662 }
6663 else
6664 {
6665 htab->a8_erratum_fixes = NULL;
6666 htab->num_a8_erratum_fixes = 0;
6667 }
0955507f 6668 return ret;
5e681ec4
PB		 6669}
6670
906e58ca
NC		 6671/* Build all the stubs associated with the current output file. The
6672 stubs are kept in a hash table attached to the main linker hash
6673 table. We also set up the .plt entries for statically linked PIC
6674 functions here. This function is called via arm_elf_finish in the
6675 linker. */
252b5132 6676
906e58ca
NC		 6677bfd_boolean
6678elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6679{
906e58ca
NC		 6680 asection *stub_sec;
6681 struct bfd_hash_table *table;
0955507f 6682 enum elf32_arm_stub_type stub_type;
906e58ca 6683 struct elf32_arm_link_hash_table *htab;
252b5132 6684
906e58ca 6685 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6686 if (htab == NULL)
6687 return FALSE;
252b5132 6688
906e58ca
NC		 6689 for (stub_sec = htab->stub_bfd->sections;
6690 stub_sec != NULL;
6691 stub_sec = stub_sec->next)
252b5132 6692 {
906e58ca
NC		 6693 bfd_size_type size;
6694
8029a119 6695 /* Ignore non-stub sections. */
906e58ca
NC		 6696 if (!strstr (stub_sec->name, STUB_SUFFIX))
6697 continue;
6698
d7c5bd02 6699 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6700 must at least be done for stub section requiring padding and for SG
6701 veneers to ensure that a non secure code branching to a removed SG
6702 veneer causes an error. */
906e58ca 6703 size = stub_sec->size;
21d799b5 6704 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6705 if (stub_sec->contents == NULL && size != 0)
6706 return FALSE;
0955507f 6707
906e58ca 6708 stub_sec->size = 0;
252b5132
RH		 6709 }
6710
0955507f
TP		 6711 /* Add new SG veneers after those already in the input import library. */
6712 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6713 {
6714 bfd_vma *start_offset_p;
6715 asection **stub_sec_p;
6716
6717 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6718 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6719 if (start_offset_p == NULL)
6720 continue;
6721
6722 BFD_ASSERT (stub_sec_p != NULL);
6723 if (*stub_sec_p != NULL)
6724 (*stub_sec_p)->size = *start_offset_p;
6725 }
6726
906e58ca
NC		 6727 /* Build the stubs as directed by the stub hash table. */
6728 table = &htab->stub_hash_table;
6729 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6730 if (htab->fix_cortex_a8)
6731 {
6732 /* Place the cortex a8 stubs last. */
6733 htab->fix_cortex_a8 = -1;
6734 bfd_hash_traverse (table, arm_build_one_stub, info);
6735 }
252b5132 6736
906e58ca 6737 return TRUE;
252b5132
RH		 6738}
6739
9b485d32
NC		 6740/* Locate the Thumb encoded calling stub for NAME. */
6741
252b5132 6742static struct elf_link_hash_entry *
57e8b36a
NC		 6743find_thumb_glue (struct bfd_link_info *link_info,
6744 const char *name,
f2a9dd69 6745 char **error_message)
252b5132
RH		 6746{
6747 char *tmp_name;
6748 struct elf_link_hash_entry *hash;
6749 struct elf32_arm_link_hash_table *hash_table;
6750
6751 /* We need a pointer to the armelf specific hash table. */
6752 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6753 if (hash_table == NULL)
6754 return NULL;
252b5132 6755
21d799b5 6756 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6757 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6758
6759 BFD_ASSERT (tmp_name);
6760
6761 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6762
6763 hash = elf_link_hash_lookup
b34976b6 6764 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6765
b1657152 6766 if (hash == NULL
90b6238f
AM		 6767 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
6768 "Thumb", tmp_name, name) == -1)
b1657152 6769 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6770
6771 free (tmp_name);
6772
6773 return hash;
6774}
6775
9b485d32
NC		 6776/* Locate the ARM encoded calling stub for NAME. */
6777
252b5132 6778static struct elf_link_hash_entry *
57e8b36a
NC		 6779find_arm_glue (struct bfd_link_info *link_info,
6780 const char *name,
f2a9dd69 6781 char **error_message)
252b5132
RH		 6782{
6783 char *tmp_name;
6784 struct elf_link_hash_entry *myh;
6785 struct elf32_arm_link_hash_table *hash_table;
6786
6787 /* We need a pointer to the elfarm specific hash table. */
6788 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6789 if (hash_table == NULL)
6790 return NULL;
252b5132 6791
21d799b5 6792 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6793 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6794
6795 BFD_ASSERT (tmp_name);
6796
6797 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6798
6799 myh = elf_link_hash_lookup
b34976b6 6800 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6801
b1657152 6802 if (myh == NULL
90b6238f
AM		 6803 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
6804 "ARM", tmp_name, name) == -1)
b1657152 6805 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6806
6807 free (tmp_name);
6808
6809 return myh;
6810}
6811
8f6277f5 6812/* ARM->Thumb glue (static images):
252b5132
RH		 6813
6814 .arm
6815 __func_from_arm:
6816 ldr r12, __func_addr
6817 bx r12
6818 __func_addr:
906e58ca 6819 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6820
26079076
PB		 6821 (v5t static images)
6822 .arm
6823 __func_from_arm:
6824 ldr pc, __func_addr
6825 __func_addr:
906e58ca 6826 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6827
8f6277f5
PB		 6828 (relocatable images)
6829 .arm
6830 __func_from_arm:
6831 ldr r12, __func_offset
6832 add r12, r12, pc
6833 bx r12
6834 __func_offset:
8029a119 6835 .word func - . */
8f6277f5
PB		 6836
6837#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6838static const insn32 a2t1_ldr_insn = 0xe59fc000;
6839static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6840static const insn32 a2t3_func_addr_insn = 0x00000001;
6841
26079076
PB		 6842#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6843static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6844static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6845
8f6277f5
PB		 6846#define ARM2THUMB_PIC_GLUE_SIZE 16
6847static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6848static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6849static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6850
07d6d2b8 6851/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6852
07d6d2b8
AM		 6853 .thumb .thumb
6854 .align 2 .align 2
6855 __func_from_thumb: __func_from_thumb:
6856 bx pc push {r6, lr}
6857 nop ldr r6, __func_addr
6858 .arm mov lr, pc
6859 b func bx r6
99059e56
RM		 6860 .arm
6861 ;; back_to_thumb
6862 ldmia r13! {r6, lr}
6863 bx lr
6864 __func_addr:
07d6d2b8 6865 .word func */
252b5132
RH		 6866
6867#define THUMB2ARM_GLUE_SIZE 8
6868static const insn16 t2a1_bx_pc_insn = 0x4778;
6869static const insn16 t2a2_noop_insn = 0x46c0;
6870static const insn32 t2a3_b_insn = 0xea000000;
6871
c7b8f16e 6872#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6873#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6874#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6875
845b51d6
PB		 6876#define ARM_BX_VENEER_SIZE 12
6877static const insn32 armbx1_tst_insn = 0xe3100001;
6878static const insn32 armbx2_moveq_insn = 0x01a0f000;
6879static const insn32 armbx3_bx_insn = 0xe12fff10;
6880
7e392df6 6881#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6882static void
6883arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6884{
6885 asection * s;
8029a119 6886 bfd_byte * contents;
252b5132 6887
8029a119 6888 if (size == 0)
3e6b1042
DJ		 6889 {
6890 /* Do not include empty glue sections in the output. */
6891 if (abfd != NULL)
6892 {
3d4d4302 6893 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6894 if (s != NULL)
6895 s->flags |= SEC_EXCLUDE;
6896 }
6897 return;
6898 }
252b5132 6899
8029a119 6900 BFD_ASSERT (abfd != NULL);
252b5132 6901
3d4d4302 6902 s = bfd_get_linker_section (abfd, name);
8029a119 6903 BFD_ASSERT (s != NULL);
252b5132 6904
21d799b5 6905 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6906
8029a119
NC		 6907 BFD_ASSERT (s->size == size);
6908 s->contents = contents;
6909}
906e58ca 6910
8029a119
NC		 6911bfd_boolean
6912bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6913{
6914 struct elf32_arm_link_hash_table * globals;
906e58ca 6915
8029a119
NC		 6916 globals = elf32_arm_hash_table (info);
6917 BFD_ASSERT (globals != NULL);
906e58ca 6918
8029a119
NC		 6919 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6920 globals->arm_glue_size,
6921 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6922
8029a119
NC		 6923 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6924 globals->thumb_glue_size,
6925 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6926
8029a119
NC		 6927 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6928 globals->vfp11_erratum_glue_size,
6929 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6930
a504d23a
LA		 6931 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6932 globals->stm32l4xx_erratum_glue_size,
6933 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6934
8029a119
NC		 6935 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6936 globals->bx_glue_size,
845b51d6
PB		 6937 ARM_BX_GLUE_SECTION_NAME);
6938
b34976b6 6939 return TRUE;
252b5132
RH		 6940}
6941
a4fd1a8e 6942/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6943 returns the symbol identifying the stub. */
6944
a4fd1a8e 6945static struct elf_link_hash_entry *
57e8b36a
NC		 6946record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6947 struct elf_link_hash_entry * h)
252b5132
RH		 6948{
6949 const char * name = h->root.root.string;
63b0f745 6950 asection * s;
252b5132
RH		 6951 char * tmp_name;
6952 struct elf_link_hash_entry * myh;
14a793b2 6953 struct bfd_link_hash_entry * bh;
252b5132 6954 struct elf32_arm_link_hash_table * globals;
dc810e39 6955 bfd_vma val;
2f475487 6956 bfd_size_type size;
252b5132
RH		 6957
6958 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6959 BFD_ASSERT (globals != NULL);
6960 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6961
3d4d4302 6962 s = bfd_get_linker_section
252b5132
RH		 6963 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6964
252b5132
RH		 6965 BFD_ASSERT (s != NULL);
6966
21d799b5 6967 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6968 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6969
6970 BFD_ASSERT (tmp_name);
6971
6972 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6973
6974 myh = elf_link_hash_lookup
b34976b6 6975 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6976
6977 if (myh != NULL)
6978 {
9b485d32 6979 /* We've already seen this guy. */
252b5132 6980 free (tmp_name);
a4fd1a8e 6981 return myh;
252b5132
RH		 6982 }
6983
57e8b36a
NC		 6984 /* The only trick here is using hash_table->arm_glue_size as the value.
6985 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6986 putting it. The +1 on the value marks that the stub has not been
6987 output yet - not that it is a Thumb function. */
14a793b2 6988 bh = NULL;
dc810e39
AM		 6989 val = globals->arm_glue_size + 1;
6990 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6991 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6992 NULL, TRUE, FALSE, &bh);
252b5132 6993
b7693d02
DJ		 6994 myh = (struct elf_link_hash_entry *) bh;
6995 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6996 myh->forced_local = 1;
6997
252b5132
RH		 6998 free (tmp_name);
6999
0e1862bb
L		 7000 if (bfd_link_pic (link_info)
7001 || globals->root.is_relocatable_executable
27e55c4d 7002 || globals->pic_veneer)
2f475487 7003 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7004 else if (globals->use_blx)
7005 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7006 else
2f475487
AM		 7007 size = ARM2THUMB_STATIC_GLUE_SIZE;
7008
7009 s->size += size;
7010 globals->arm_glue_size += size;
252b5132 7011
a4fd1a8e 7012 return myh;
252b5132
RH		 7013}
7014
845b51d6
PB		 7015/* Allocate space for ARMv4 BX veneers. */
7016
7017static void
7018record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7019{
7020 asection * s;
7021 struct elf32_arm_link_hash_table *globals;
7022 char *tmp_name;
7023 struct elf_link_hash_entry *myh;
7024 struct bfd_link_hash_entry *bh;
7025 bfd_vma val;
7026
7027 /* BX PC does not need a veneer. */
7028 if (reg == 15)
7029 return;
7030
7031 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7032 BFD_ASSERT (globals != NULL);
7033 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7034
7035 /* Check if this veneer has already been allocated. */
7036 if (globals->bx_glue_offset[reg])
7037 return;
7038
3d4d4302 7039 s = bfd_get_linker_section
845b51d6
PB		 7040 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7041
7042 BFD_ASSERT (s != NULL);
7043
7044 /* Add symbol for veneer. */
21d799b5
NC		 7045 tmp_name = (char *)
7046 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7047
845b51d6 7048 BFD_ASSERT (tmp_name);
906e58ca 7049
845b51d6 7050 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7051
845b51d6
PB		 7052 myh = elf_link_hash_lookup
7053 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7054
845b51d6 7055 BFD_ASSERT (myh == NULL);
906e58ca 7056
845b51d6
PB		 7057 bh = NULL;
7058 val = globals->bx_glue_size;
7059 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7060 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7061 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7062
7063 myh = (struct elf_link_hash_entry *) bh;
7064 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7065 myh->forced_local = 1;
7066
7067 s->size += ARM_BX_VENEER_SIZE;
7068 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7069 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7070}
7071
7072
c7b8f16e
JB		 7073/* Add an entry to the code/data map for section SEC. */
7074
7075static void
7076elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7077{
7078 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7079 unsigned int newidx;
906e58ca 7080
c7b8f16e
JB		 7081 if (sec_data->map == NULL)
7082 {
21d799b5 7083 sec_data->map = (elf32_arm_section_map *)
99059e56 7084 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7085 sec_data->mapcount = 0;
7086 sec_data->mapsize = 1;
7087 }
906e58ca 7088
c7b8f16e 7089 newidx = sec_data->mapcount++;
906e58ca 7090
c7b8f16e
JB		 7091 if (sec_data->mapcount > sec_data->mapsize)
7092 {
7093 sec_data->mapsize *= 2;
21d799b5 7094 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7095 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7096 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7097 }
7098
7099 if (sec_data->map)
7100 {
7101 sec_data->map[newidx].vma = vma;
7102 sec_data->map[newidx].type = type;
c7b8f16e 7103 }
c7b8f16e
JB		 7104}
7105
7106
7107/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7108 veneers are handled for now. */
7109
7110static bfd_vma
7111record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7112 elf32_vfp11_erratum_list *branch,
7113 bfd *branch_bfd,
7114 asection *branch_sec,
7115 unsigned int offset)
c7b8f16e
JB		 7116{
7117 asection *s;
7118 struct elf32_arm_link_hash_table *hash_table;
7119 char *tmp_name;
7120 struct elf_link_hash_entry *myh;
7121 struct bfd_link_hash_entry *bh;
7122 bfd_vma val;
7123 struct _arm_elf_section_data *sec_data;
c7b8f16e 7124 elf32_vfp11_erratum_list *newerr;
906e58ca 7125
c7b8f16e 7126 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7127 BFD_ASSERT (hash_table != NULL);
7128 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7129
3d4d4302 7130 s = bfd_get_linker_section
c7b8f16e 7131 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7132
c7b8f16e 7133 sec_data = elf32_arm_section_data (s);
906e58ca 7134
c7b8f16e 7135 BFD_ASSERT (s != NULL);
906e58ca 7136
21d799b5 7137 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7138 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7139
c7b8f16e 7140 BFD_ASSERT (tmp_name);
906e58ca 7141
c7b8f16e
JB		 7142 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7143 hash_table->num_vfp11_fixes);
906e58ca 7144
c7b8f16e
JB		 7145 myh = elf_link_hash_lookup
7146 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7147
c7b8f16e 7148 BFD_ASSERT (myh == NULL);
906e58ca 7149
c7b8f16e
JB		 7150 bh = NULL;
7151 val = hash_table->vfp11_erratum_glue_size;
7152 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7153 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7154 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7155
7156 myh = (struct elf_link_hash_entry *) bh;
7157 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7158 myh->forced_local = 1;
7159
7160 /* Link veneer back to calling location. */
c7e2358a 7161 sec_data->erratumcount += 1;
21d799b5
NC		 7162 newerr = (elf32_vfp11_erratum_list *)
7163 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7164
c7b8f16e
JB		 7165 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7166 newerr->vma = -1;
7167 newerr->u.v.branch = branch;
7168 newerr->u.v.id = hash_table->num_vfp11_fixes;
7169 branch->u.b.veneer = newerr;
7170
7171 newerr->next = sec_data->erratumlist;
7172 sec_data->erratumlist = newerr;
7173
7174 /* A symbol for the return from the veneer. */
7175 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7176 hash_table->num_vfp11_fixes);
7177
7178 myh = elf_link_hash_lookup
7179 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7180
c7b8f16e
JB		 7181 if (myh != NULL)
7182 abort ();
7183
7184 bh = NULL;
7185 val = offset + 4;
7186 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7187 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7188
c7b8f16e
JB		 7189 myh = (struct elf_link_hash_entry *) bh;
7190 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7191 myh->forced_local = 1;
7192
7193 free (tmp_name);
906e58ca 7194
c7b8f16e
JB		 7195 /* Generate a mapping symbol for the veneer section, and explicitly add an
7196 entry for that symbol to the code/data map for the section. */
7197 if (hash_table->vfp11_erratum_glue_size == 0)
7198 {
7199 bh = NULL;
7200 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7201 ever requires this erratum fix. */
c7b8f16e
JB		 7202 _bfd_generic_link_add_one_symbol (link_info,
7203 hash_table->bfd_of_glue_owner, "$a",
7204 BSF_LOCAL, s, 0, NULL,
99059e56 7205 TRUE, FALSE, &bh);
c7b8f16e
JB		 7206
7207 myh = (struct elf_link_hash_entry *) bh;
7208 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7209 myh->forced_local = 1;
906e58ca 7210
c7b8f16e 7211 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7212 BFDs. We must make a note of this generated mapping symbol
7213 ourselves so that code byteswapping works properly in
7214 elf32_arm_write_section. */
c7b8f16e
JB		 7215 elf32_arm_section_map_add (s, 'a', 0);
7216 }
906e58ca 7217
c7b8f16e
JB		 7218 s->size += VFP11_ERRATUM_VENEER_SIZE;
7219 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7220 hash_table->num_vfp11_fixes++;
906e58ca 7221
c7b8f16e
JB		 7222 /* The offset of the veneer. */
7223 return val;
7224}
7225
a504d23a
LA		 7226/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7227 veneers need to be handled because used only in Cortex-M. */
7228
7229static bfd_vma
7230record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7231 elf32_stm32l4xx_erratum_list *branch,
7232 bfd *branch_bfd,
7233 asection *branch_sec,
7234 unsigned int offset,
7235 bfd_size_type veneer_size)
7236{
7237 asection *s;
7238 struct elf32_arm_link_hash_table *hash_table;
7239 char *tmp_name;
7240 struct elf_link_hash_entry *myh;
7241 struct bfd_link_hash_entry *bh;
7242 bfd_vma val;
7243 struct _arm_elf_section_data *sec_data;
7244 elf32_stm32l4xx_erratum_list *newerr;
7245
7246 hash_table = elf32_arm_hash_table (link_info);
7247 BFD_ASSERT (hash_table != NULL);
7248 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7249
7250 s = bfd_get_linker_section
7251 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7252
7253 BFD_ASSERT (s != NULL);
7254
7255 sec_data = elf32_arm_section_data (s);
7256
7257 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7258 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7259
7260 BFD_ASSERT (tmp_name);
7261
7262 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7263 hash_table->num_stm32l4xx_fixes);
7264
7265 myh = elf_link_hash_lookup
7266 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7267
7268 BFD_ASSERT (myh == NULL);
7269
7270 bh = NULL;
7271 val = hash_table->stm32l4xx_erratum_glue_size;
7272 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7273 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7274 NULL, TRUE, FALSE, &bh);
7275
7276 myh = (struct elf_link_hash_entry *) bh;
7277 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7278 myh->forced_local = 1;
7279
7280 /* Link veneer back to calling location. */
7281 sec_data->stm32l4xx_erratumcount += 1;
7282 newerr = (elf32_stm32l4xx_erratum_list *)
7283 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7284
7285 newerr->type = STM32L4XX_ERRATUM_VENEER;
7286 newerr->vma = -1;
7287 newerr->u.v.branch = branch;
7288 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7289 branch->u.b.veneer = newerr;
7290
7291 newerr->next = sec_data->stm32l4xx_erratumlist;
7292 sec_data->stm32l4xx_erratumlist = newerr;
7293
7294 /* A symbol for the return from the veneer. */
7295 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7296 hash_table->num_stm32l4xx_fixes);
7297
7298 myh = elf_link_hash_lookup
7299 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7300
7301 if (myh != NULL)
7302 abort ();
7303
7304 bh = NULL;
7305 val = offset + 4;
7306 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7307 branch_sec, val, NULL, TRUE, FALSE, &bh);
7308
7309 myh = (struct elf_link_hash_entry *) bh;
7310 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7311 myh->forced_local = 1;
7312
7313 free (tmp_name);
7314
7315 /* Generate a mapping symbol for the veneer section, and explicitly add an
7316 entry for that symbol to the code/data map for the section. */
7317 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7318 {
7319 bh = NULL;
7320 /* Creates a THUMB symbol since there is no other choice. */
7321 _bfd_generic_link_add_one_symbol (link_info,
7322 hash_table->bfd_of_glue_owner, "$t",
7323 BSF_LOCAL, s, 0, NULL,
7324 TRUE, FALSE, &bh);
7325
7326 myh = (struct elf_link_hash_entry *) bh;
7327 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7328 myh->forced_local = 1;
7329
7330 /* The elf32_arm_init_maps function only cares about symbols from input
7331 BFDs. We must make a note of this generated mapping symbol
7332 ourselves so that code byteswapping works properly in
7333 elf32_arm_write_section. */
7334 elf32_arm_section_map_add (s, 't', 0);
7335 }
7336
7337 s->size += veneer_size;
7338 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7339 hash_table->num_stm32l4xx_fixes++;
7340
7341 /* The offset of the veneer. */
7342 return val;
7343}
7344
8029a119 7345#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7346 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7347 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7348
7349/* Create a fake section for use by the ARM backend of the linker. */
7350
7351static bfd_boolean
7352arm_make_glue_section (bfd * abfd, const char * name)
7353{
7354 asection * sec;
7355
3d4d4302 7356 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7357 if (sec != NULL)
7358 /* Already made. */
7359 return TRUE;
7360
3d4d4302 7361 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7362
7363 if (sec == NULL
7364 || !bfd_set_section_alignment (abfd, sec, 2))
7365 return FALSE;
7366
7367 /* Set the gc mark to prevent the section from being removed by garbage
7368 collection, despite the fact that no relocs refer to this section. */
7369 sec->gc_mark = 1;
7370
7371 return TRUE;
7372}
7373
1db37fe6
YG		 7374/* Set size of .plt entries. This function is called from the
7375 linker scripts in ld/emultempl/{armelf}.em. */
7376
7377void
7378bfd_elf32_arm_use_long_plt (void)
7379{
7380 elf32_arm_use_long_plt_entry = TRUE;
7381}
7382
8afb0e02
NC		 7383/* Add the glue sections to ABFD. This function is called from the
7384 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7385
b34976b6 7386bfd_boolean
57e8b36a
NC		 7387bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7388 struct bfd_link_info *info)
252b5132 7389{
a504d23a
LA		 7390 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7391 bfd_boolean dostm32l4xx = globals
7392 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7393 bfd_boolean addglue;
7394
8afb0e02
NC		 7395 /* If we are only performing a partial
7396 link do not bother adding the glue. */
0e1862bb 7397 if (bfd_link_relocatable (info))
b34976b6 7398 return TRUE;
252b5132 7399
a504d23a 7400 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7401 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7402 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7403 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7404
7405 if (!dostm32l4xx)
7406 return addglue;
7407
7408 return addglue
7409 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7410}
7411
daa4adae
TP		 7412/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7413 ensures they are not marked for deletion by
7414 strip_excluded_output_sections () when veneers are going to be created
7415 later. Not doing so would trigger assert on empty section size in
7416 lang_size_sections_1 (). */
7417
7418void
7419bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7420{
7421 enum elf32_arm_stub_type stub_type;
7422
7423 /* If we are only performing a partial
7424 link do not bother adding the glue. */
7425 if (bfd_link_relocatable (info))
7426 return;
7427
7428 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7429 {
7430 asection *out_sec;
7431 const char *out_sec_name;
7432
7433 if (!arm_dedicated_stub_output_section_required (stub_type))
7434 continue;
7435
7436 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7437 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7438 if (out_sec != NULL)
7439 out_sec->flags |= SEC_KEEP;
7440 }
7441}
7442
8afb0e02
NC		 7443/* Select a BFD to be used to hold the sections used by the glue code.
7444 This function is called from the linker scripts in ld/emultempl/
8029a119 7445 {armelf/pe}.em. */
8afb0e02 7446
b34976b6 7447bfd_boolean
57e8b36a 7448bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7449{
7450 struct elf32_arm_link_hash_table *globals;
7451
7452 /* If we are only performing a partial link
7453 do not bother getting a bfd to hold the glue. */
0e1862bb 7454 if (bfd_link_relocatable (info))
b34976b6 7455 return TRUE;
8afb0e02 7456
b7693d02
DJ		 7457 /* Make sure we don't attach the glue sections to a dynamic object. */
7458 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7459
8afb0e02 7460 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7461 BFD_ASSERT (globals != NULL);
7462
7463 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7464 return TRUE;
8afb0e02 7465
252b5132
RH		 7466 /* Save the bfd for later use. */
7467 globals->bfd_of_glue_owner = abfd;
cedb70c5 7468
b34976b6 7469 return TRUE;
252b5132
RH		 7470}
7471
906e58ca
NC		 7472static void
7473check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7474{
2de70689
MGD		 7475 int cpu_arch;
7476
b38cadfb 7477 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7478 Tag_CPU_arch);
7479
7480 if (globals->fix_arm1176)
7481 {
7482 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7483 globals->use_blx = 1;
7484 }
7485 else
7486 {
7487 if (cpu_arch > TAG_CPU_ARCH_V4T)
7488 globals->use_blx = 1;
7489 }
39b41c9c
PB		 7490}
7491
b34976b6 7492bfd_boolean
57e8b36a 7493bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7494 struct bfd_link_info *link_info)
252b5132
RH		 7495{
7496 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7497 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7498 Elf_Internal_Rela *irel, *irelend;
7499 bfd_byte *contents = NULL;
252b5132
RH		 7500
7501 asection *sec;
7502 struct elf32_arm_link_hash_table *globals;
7503
7504 /* If we are only performing a partial link do not bother
7505 to construct any glue. */
0e1862bb 7506 if (bfd_link_relocatable (link_info))
b34976b6 7507 return TRUE;
252b5132 7508
39ce1a6a
NC		 7509 /* Here we have a bfd that is to be included on the link. We have a
7510 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7511 globals = elf32_arm_hash_table (link_info);
252b5132 7512 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7513
7514 check_use_blx (globals);
252b5132 7515
d504ffc8 7516 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7517 {
90b6238f 7518 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7519 abfd);
e489d0ae
PB		 7520 return FALSE;
7521 }
f21f3fe0 7522
39ce1a6a
NC		 7523 /* PR 5398: If we have not decided to include any loadable sections in
7524 the output then we will not have a glue owner bfd. This is OK, it
7525 just means that there is nothing else for us to do here. */
7526 if (globals->bfd_of_glue_owner == NULL)
7527 return TRUE;
7528
252b5132
RH		 7529 /* Rummage around all the relocs and map the glue vectors. */
7530 sec = abfd->sections;
7531
7532 if (sec == NULL)
b34976b6 7533 return TRUE;
252b5132
RH		 7534
7535 for (; sec != NULL; sec = sec->next)
7536 {
7537 if (sec->reloc_count == 0)
7538 continue;
7539
2f475487
AM		 7540 if ((sec->flags & SEC_EXCLUDE) != 0)
7541 continue;
7542
0ffa91dd 7543 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7544
9b485d32 7545 /* Load the relocs. */
6cdc0ccc 7546 internal_relocs
906e58ca 7547 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7548
6cdc0ccc
AM		 7549 if (internal_relocs == NULL)
7550 goto error_return;
252b5132 7551
6cdc0ccc
AM		 7552 irelend = internal_relocs + sec->reloc_count;
7553 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7554 {
7555 long r_type;
7556 unsigned long r_index;
252b5132
RH		 7557
7558 struct elf_link_hash_entry *h;
7559
7560 r_type = ELF32_R_TYPE (irel->r_info);
7561 r_index = ELF32_R_SYM (irel->r_info);
7562
9b485d32 7563 /* These are the only relocation types we care about. */
ba96a88f 7564 if ( r_type != R_ARM_PC24
845b51d6 7565 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7566 continue;
7567
7568 /* Get the section contents if we haven't done so already. */
7569 if (contents == NULL)
7570 {
7571 /* Get cached copy if it exists. */
7572 if (elf_section_data (sec)->this_hdr.contents != NULL)
7573 contents = elf_section_data (sec)->this_hdr.contents;
7574 else
7575 {
7576 /* Go get them off disk. */
57e8b36a 7577 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7578 goto error_return;
7579 }
7580 }
7581
845b51d6
PB		 7582 if (r_type == R_ARM_V4BX)
7583 {
7584 int reg;
7585
7586 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7587 record_arm_bx_glue (link_info, reg);
7588 continue;
7589 }
7590
a7c10850 7591 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7592 h = NULL;
7593
9b485d32 7594 /* We don't care about local symbols. */
252b5132
RH		 7595 if (r_index < symtab_hdr->sh_info)
7596 continue;
7597
9b485d32 7598 /* This is an external symbol. */
252b5132
RH		 7599 r_index -= symtab_hdr->sh_info;
7600 h = (struct elf_link_hash_entry *)
7601 elf_sym_hashes (abfd)[r_index];
7602
7603 /* If the relocation is against a static symbol it must be within
7604 the current section and so cannot be a cross ARM/Thumb relocation. */
7605 if (h == NULL)
7606 continue;
7607
d504ffc8
DJ		 7608 /* If the call will go through a PLT entry then we do not need
7609 glue. */
362d30a1 7610 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7611 continue;
7612
252b5132
RH		 7613 switch (r_type)
7614 {
7615 case R_ARM_PC24:
7616 /* This one is a call from arm code. We need to look up
99059e56
RM		 7617 the target of the call. If it is a thumb target, we
7618 insert glue. */
39d911fc
TP		 7619 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7620 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7621 record_arm_to_thumb_glue (link_info, h);
7622 break;
7623
252b5132 7624 default:
c6596c5e 7625 abort ();
252b5132
RH		 7626 }
7627 }
6cdc0ccc
AM		 7628
7629 if (contents != NULL
7630 && elf_section_data (sec)->this_hdr.contents != contents)
7631 free (contents);
7632 contents = NULL;
7633
7634 if (internal_relocs != NULL
7635 && elf_section_data (sec)->relocs != internal_relocs)
7636 free (internal_relocs);
7637 internal_relocs = NULL;
252b5132
RH		 7638 }
7639
b34976b6 7640 return TRUE;
9a5aca8c 7641
252b5132 7642error_return:
6cdc0ccc
AM		 7643 if (contents != NULL
7644 && elf_section_data (sec)->this_hdr.contents != contents)
7645 free (contents);
7646 if (internal_relocs != NULL
7647 && elf_section_data (sec)->relocs != internal_relocs)
7648 free (internal_relocs);
9a5aca8c 7649
b34976b6 7650 return FALSE;
252b5132 7651}
7e392df6 7652#endif
252b5132 7653
eb043451 7654
c7b8f16e
JB		 7655/* Initialise maps of ARM/Thumb/data for input BFDs. */
7656
7657void
7658bfd_elf32_arm_init_maps (bfd *abfd)
7659{
7660 Elf_Internal_Sym *isymbuf;
7661 Elf_Internal_Shdr *hdr;
7662 unsigned int i, localsyms;
7663
af1f4419
NC		 7664 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7665 if (! is_arm_elf (abfd))
7666 return;
7667
c7b8f16e
JB		 7668 if ((abfd->flags & DYNAMIC) != 0)
7669 return;
7670
0ffa91dd 7671 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7672 localsyms = hdr->sh_info;
7673
7674 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7675 should contain the number of local symbols, which should come before any
7676 global symbols. Mapping symbols are always local. */
7677 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7678 NULL);
7679
7680 /* No internal symbols read? Skip this BFD. */
7681 if (isymbuf == NULL)
7682 return;
7683
7684 for (i = 0; i < localsyms; i++)
7685 {
7686 Elf_Internal_Sym *isym = &isymbuf[i];
7687 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7688 const char *name;
906e58ca 7689
c7b8f16e 7690 if (sec != NULL
99059e56
RM		 7691 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7692 {
7693 name = bfd_elf_string_from_elf_section (abfd,
7694 hdr->sh_link, isym->st_name);
906e58ca 7695
99059e56 7696 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7697 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7698 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7699 }
c7b8f16e
JB		 7700 }
7701}
7702
7703
48229727
JB		 7704/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7705 say what they wanted. */
7706
7707void
7708bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7709{
7710 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7711 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7712
4dfe6ac6
NC		 7713 if (globals == NULL)
7714 return;
7715
48229727
JB		 7716 if (globals->fix_cortex_a8 == -1)
7717 {
7718 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7719 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7720 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7721 || out_attr[Tag_CPU_arch_profile].i == 0))
7722 globals->fix_cortex_a8 = 1;
7723 else
7724 globals->fix_cortex_a8 = 0;
7725 }
7726}
7727
7728
c7b8f16e
JB		 7729void
7730bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7731{
7732 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7733 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7734
4dfe6ac6
NC		 7735 if (globals == NULL)
7736 return;
c7b8f16e
JB		 7737 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7738 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7739 {
7740 switch (globals->vfp11_fix)
99059e56
RM		 7741 {
7742 case BFD_ARM_VFP11_FIX_DEFAULT:
7743 case BFD_ARM_VFP11_FIX_NONE:
7744 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7745 break;
7746
7747 default:
7748 /* Give a warning, but do as the user requests anyway. */
871b3ab2 7749 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 7750 "workaround is not necessary for target architecture"), obfd);
7751 }
c7b8f16e
JB		 7752 }
7753 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7754 /* For earlier architectures, we might need the workaround, but do not
7755 enable it by default. If users is running with broken hardware, they
7756 must enable the erratum fix explicitly. */
7757 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7758}
7759
a504d23a
LA		 7760void
7761bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7762{
7763 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7764 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7765
7766 if (globals == NULL)
7767 return;
7768
7769 /* We assume only Cortex-M4 may require the fix. */
7770 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7771 || out_attr[Tag_CPU_arch_profile].i != 'M')
7772 {
7773 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7774 /* Give a warning, but do as the user requests anyway. */
4eca0228 7775 _bfd_error_handler
871b3ab2 7776 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 7777 "workaround is not necessary for target architecture"), obfd);
7778 }
7779}
c7b8f16e 7780
906e58ca
NC		 7781enum bfd_arm_vfp11_pipe
7782{
c7b8f16e
JB		 7783 VFP11_FMAC,
7784 VFP11_LS,
7785 VFP11_DS,
7786 VFP11_BAD
7787};
7788
7789/* Return a VFP register number. This is encoded as RX:X for single-precision
7790 registers, or X:RX for double-precision registers, where RX is the group of
7791 four bits in the instruction encoding and X is the single extension bit.
7792 RX and X fields are specified using their lowest (starting) bit. The return
7793 value is:
7794
7795 0...31: single-precision registers s0...s31
7796 32...63: double-precision registers d0...d31.
906e58ca 7797
c7b8f16e
JB		 7798 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7799 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7800
c7b8f16e
JB		 7801static unsigned int
7802bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7803 unsigned int x)
c7b8f16e
JB		 7804{
7805 if (is_double)
7806 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7807 else
7808 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7809}
7810
7811/* Set bits in *WMASK according to a register number REG as encoded by
7812 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7813
7814static void
7815bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7816{
7817 if (reg < 32)
7818 *wmask |= 1 << reg;
7819 else if (reg < 48)
7820 *wmask |= 3 << ((reg - 32) * 2);
7821}
7822
7823/* Return TRUE if WMASK overwrites anything in REGS. */
7824
7825static bfd_boolean
7826bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7827{
7828 int i;
906e58ca 7829
c7b8f16e
JB		 7830 for (i = 0; i < numregs; i++)
7831 {
7832 unsigned int reg = regs[i];
7833
7834 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7835 return TRUE;
906e58ca 7836
c7b8f16e
JB		 7837 reg -= 32;
7838
7839 if (reg >= 16)
99059e56 7840 continue;
906e58ca 7841
c7b8f16e 7842 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7843 return TRUE;
c7b8f16e 7844 }
906e58ca 7845
c7b8f16e
JB		 7846 return FALSE;
7847}
7848
7849/* In this function, we're interested in two things: finding input registers
7850 for VFP data-processing instructions, and finding the set of registers which
7851 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7852 hold the written set, so FLDM etc. are easy to deal with (we're only
7853 interested in 32 SP registers or 16 dp registers, due to the VFP version
7854 implemented by the chip in question). DP registers are marked by setting
7855 both SP registers in the write mask). */
7856
7857static enum bfd_arm_vfp11_pipe
7858bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7859 int *numregs)
c7b8f16e 7860{
91d6fa6a 7861 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7862 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7863
7864 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7865 {
7866 unsigned int pqrs;
7867 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7868 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7869
7870 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7871 | ((insn & 0x00300000) >> 19)
7872 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7873
7874 switch (pqrs)
99059e56
RM		 7875 {
7876 case 0: /* fmac[sd]. */
7877 case 1: /* fnmac[sd]. */
7878 case 2: /* fmsc[sd]. */
7879 case 3: /* fnmsc[sd]. */
7880 vpipe = VFP11_FMAC;
7881 bfd_arm_vfp11_write_mask (destmask, fd);
7882 regs[0] = fd;
7883 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7884 regs[2] = fm;
7885 *numregs = 3;
7886 break;
7887
7888 case 4: /* fmul[sd]. */
7889 case 5: /* fnmul[sd]. */
7890 case 6: /* fadd[sd]. */
7891 case 7: /* fsub[sd]. */
7892 vpipe = VFP11_FMAC;
7893 goto vfp_binop;
7894
7895 case 8: /* fdiv[sd]. */
7896 vpipe = VFP11_DS;
7897 vfp_binop:
7898 bfd_arm_vfp11_write_mask (destmask, fd);
7899 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7900 regs[1] = fm;
7901 *numregs = 2;
7902 break;
7903
7904 case 15: /* extended opcode. */
7905 {
7906 unsigned int extn = ((insn >> 15) & 0x1e)
7907 | ((insn >> 7) & 1);
7908
7909 switch (extn)
7910 {
7911 case 0: /* fcpy[sd]. */
7912 case 1: /* fabs[sd]. */
7913 case 2: /* fneg[sd]. */
7914 case 8: /* fcmp[sd]. */
7915 case 9: /* fcmpe[sd]. */
7916 case 10: /* fcmpz[sd]. */
7917 case 11: /* fcmpez[sd]. */
7918 case 16: /* fuito[sd]. */
7919 case 17: /* fsito[sd]. */
7920 case 24: /* ftoui[sd]. */
7921 case 25: /* ftouiz[sd]. */
7922 case 26: /* ftosi[sd]. */
7923 case 27: /* ftosiz[sd]. */
7924 /* These instructions will not bounce due to underflow. */
7925 *numregs = 0;
7926 vpipe = VFP11_FMAC;
7927 break;
7928
7929 case 3: /* fsqrt[sd]. */
7930 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7931 registers to cause the erratum in previous instructions. */
7932 bfd_arm_vfp11_write_mask (destmask, fd);
7933 vpipe = VFP11_DS;
7934 break;
7935
7936 case 15: /* fcvt{ds,sd}. */
7937 {
7938 int rnum = 0;
7939
7940 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7941
7942 /* Only FCVTSD can underflow. */
99059e56
RM		 7943 if ((insn & 0x100) != 0)
7944 regs[rnum++] = fm;
c7b8f16e 7945
99059e56 7946 *numregs = rnum;
c7b8f16e 7947
99059e56
RM		 7948 vpipe = VFP11_FMAC;
7949 }
7950 break;
c7b8f16e 7951
99059e56
RM		 7952 default:
7953 return VFP11_BAD;
7954 }
7955 }
7956 break;
c7b8f16e 7957
99059e56
RM		 7958 default:
7959 return VFP11_BAD;
7960 }
c7b8f16e
JB		 7961 }
7962 /* Two-register transfer. */
7963 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7964 {
7965 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7966
c7b8f16e
JB		 7967 if ((insn & 0x100000) == 0)
7968 {
99059e56
RM		 7969 if (is_double)
7970 bfd_arm_vfp11_write_mask (destmask, fm);
7971 else
7972 {
7973 bfd_arm_vfp11_write_mask (destmask, fm);
7974 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7975 }
c7b8f16e
JB		 7976 }
7977
91d6fa6a 7978 vpipe = VFP11_LS;
c7b8f16e
JB		 7979 }
7980 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7981 {
7982 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7983 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7984
c7b8f16e 7985 switch (puw)
99059e56
RM		 7986 {
7987 case 0: /* Two-reg transfer. We should catch these above. */
7988 abort ();
906e58ca 7989
99059e56
RM		 7990 case 2: /* fldm[sdx]. */
7991 case 3:
7992 case 5:
7993 {
7994 unsigned int i, offset = insn & 0xff;
c7b8f16e 7995
99059e56
RM		 7996 if (is_double)
7997 offset >>= 1;
c7b8f16e 7998
99059e56
RM		 7999 for (i = fd; i < fd + offset; i++)
8000 bfd_arm_vfp11_write_mask (destmask, i);
8001 }
8002 break;
906e58ca 8003
99059e56
RM		 8004 case 4: /* fld[sd]. */
8005 case 6:
8006 bfd_arm_vfp11_write_mask (destmask, fd);
8007 break;
906e58ca 8008
99059e56
RM		 8009 default:
8010 return VFP11_BAD;
8011 }
c7b8f16e 8012
91d6fa6a 8013 vpipe = VFP11_LS;
c7b8f16e
JB		 8014 }
8015 /* Single-register transfer. Note L==0. */
8016 else if ((insn & 0x0f100e10) == 0x0e000a10)
8017 {
8018 unsigned int opcode = (insn >> 21) & 7;
8019 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8020
8021 switch (opcode)
99059e56
RM		 8022 {
8023 case 0: /* fmsr/fmdlr. */
8024 case 1: /* fmdhr. */
8025 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8026 destination register. I don't know if this is exactly right,
8027 but it is the conservative choice. */
8028 bfd_arm_vfp11_write_mask (destmask, fn);
8029 break;
8030
8031 case 7: /* fmxr. */
8032 break;
8033 }
c7b8f16e 8034
91d6fa6a 8035 vpipe = VFP11_LS;
c7b8f16e
JB		 8036 }
8037
91d6fa6a 8038 return vpipe;
c7b8f16e
JB		 8039}
8040
8041
8042static int elf32_arm_compare_mapping (const void * a, const void * b);
8043
8044
8045/* Look for potentially-troublesome code sequences which might trigger the
8046 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8047 (available from ARM) for details of the erratum. A short version is
8048 described in ld.texinfo. */
8049
8050bfd_boolean
8051bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8052{
8053 asection *sec;
8054 bfd_byte *contents = NULL;
8055 int state = 0;
8056 int regs[3], numregs = 0;
8057 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8058 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8059
4dfe6ac6
NC		 8060 if (globals == NULL)
8061 return FALSE;
8062
c7b8f16e
JB		 8063 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8064 The states transition as follows:
906e58ca 8065
c7b8f16e 8066 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8067 A VFP FMAC-pipeline instruction has been seen. Fill
8068 regs[0]..regs[numregs-1] with its input operands. Remember this
8069 instruction in 'first_fmac'.
c7b8f16e
JB		 8070
8071 1 -> 2
99059e56
RM		 8072 Any instruction, except for a VFP instruction which overwrites
8073 regs[*].
906e58ca 8074
c7b8f16e
JB		 8075 1 -> 3 [ -> 0 ] or
8076 2 -> 3 [ -> 0 ]
99059e56
RM		 8077 A VFP instruction has been seen which overwrites any of regs[*].
8078 We must make a veneer! Reset state to 0 before examining next
8079 instruction.
906e58ca 8080
c7b8f16e 8081 2 -> 0
99059e56
RM		 8082 If we fail to match anything in state 2, reset to state 0 and reset
8083 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8084
8085 If the VFP11 vector mode is in use, there must be at least two unrelated
8086 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8087 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8088
8089 /* If we are only performing a partial link do not bother
8090 to construct any glue. */
0e1862bb 8091 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8092 return TRUE;
8093
0ffa91dd
NC		 8094 /* Skip if this bfd does not correspond to an ELF image. */
8095 if (! is_arm_elf (abfd))
8096 return TRUE;
906e58ca 8097
c7b8f16e
JB		 8098 /* We should have chosen a fix type by the time we get here. */
8099 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8100
8101 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8102 return TRUE;
2e6030b9 8103
33a7ffc2
JM		 8104 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8105 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8106 return TRUE;
8107
c7b8f16e
JB		 8108 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8109 {
8110 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8111 struct _arm_elf_section_data *sec_data;
8112
8113 /* If we don't have executable progbits, we're not interested in this
99059e56 8114 section. Also skip if section is to be excluded. */
c7b8f16e 8115 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8116 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8117 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8118 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8119 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8120 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8121 continue;
c7b8f16e
JB		 8122
8123 sec_data = elf32_arm_section_data (sec);
906e58ca 8124
c7b8f16e 8125 if (sec_data->mapcount == 0)
99059e56 8126 continue;
906e58ca 8127
c7b8f16e
JB		 8128 if (elf_section_data (sec)->this_hdr.contents != NULL)
8129 contents = elf_section_data (sec)->this_hdr.contents;
8130 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8131 goto error_return;
8132
8133 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8134 elf32_arm_compare_mapping);
8135
8136 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8137 {
8138 unsigned int span_start = sec_data->map[span].vma;
8139 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8140 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8141 char span_type = sec_data->map[span].type;
8142
8143 /* FIXME: Only ARM mode is supported at present. We may need to
8144 support Thumb-2 mode also at some point. */
8145 if (span_type != 'a')
8146 continue;
8147
8148 for (i = span_start; i < span_end;)
8149 {
8150 unsigned int next_i = i + 4;
8151 unsigned int insn = bfd_big_endian (abfd)
8152 ? (contents[i] << 24)
8153 | (contents[i + 1] << 16)
8154 | (contents[i + 2] << 8)
8155 | contents[i + 3]
8156 : (contents[i + 3] << 24)
8157 | (contents[i + 2] << 16)
8158 | (contents[i + 1] << 8)
8159 | contents[i];
8160 unsigned int writemask = 0;
8161 enum bfd_arm_vfp11_pipe vpipe;
8162
8163 switch (state)
8164 {
8165 case 0:
8166 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8167 &numregs);
8168 /* I'm assuming the VFP11 erratum can trigger with denorm
8169 operands on either the FMAC or the DS pipeline. This might
8170 lead to slightly overenthusiastic veneer insertion. */
8171 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8172 {
8173 state = use_vector ? 1 : 2;
8174 first_fmac = i;
8175 veneer_of_insn = insn;
8176 }
8177 break;
8178
8179 case 1:
8180 {
8181 int other_regs[3], other_numregs;
8182 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8183 other_regs,
99059e56
RM		 8184 &other_numregs);
8185 if (vpipe != VFP11_BAD
8186 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8187 numregs))
99059e56
RM		 8188 state = 3;
8189 else
8190 state = 2;
8191 }
8192 break;
8193
8194 case 2:
8195 {
8196 int other_regs[3], other_numregs;
8197 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8198 other_regs,
99059e56
RM		 8199 &other_numregs);
8200 if (vpipe != VFP11_BAD
8201 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8202 numregs))
99059e56
RM		 8203 state = 3;
8204 else
8205 {
8206 state = 0;
8207 next_i = first_fmac + 4;
8208 }
8209 }
8210 break;
8211
8212 case 3:
8213 abort (); /* Should be unreachable. */
8214 }
8215
8216 if (state == 3)
8217 {
8218 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8219 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8220
8221 elf32_arm_section_data (sec)->erratumcount += 1;
8222
8223 newerr->u.b.vfp_insn = veneer_of_insn;
8224
8225 switch (span_type)
8226 {
8227 case 'a':
8228 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8229 break;
8230
8231 default:
8232 abort ();
8233 }
8234
8235 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8236 first_fmac);
8237
99059e56 8238 newerr->vma = -1;
c7b8f16e 8239
99059e56
RM		 8240 newerr->next = sec_data->erratumlist;
8241 sec_data->erratumlist = newerr;
c7b8f16e 8242
99059e56
RM		 8243 state = 0;
8244 }
c7b8f16e 8245
99059e56
RM		 8246 i = next_i;
8247 }
8248 }
906e58ca 8249
c7b8f16e 8250 if (contents != NULL
99059e56
RM		 8251 && elf_section_data (sec)->this_hdr.contents != contents)
8252 free (contents);
c7b8f16e
JB		 8253 contents = NULL;
8254 }
8255
8256 return TRUE;
8257
8258error_return:
8259 if (contents != NULL
8260 && elf_section_data (sec)->this_hdr.contents != contents)
8261 free (contents);
906e58ca 8262
c7b8f16e
JB		 8263 return FALSE;
8264}
8265
8266/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8267 after sections have been laid out, using specially-named symbols. */
8268
8269void
8270bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8271 struct bfd_link_info *link_info)
8272{
8273 asection *sec;
8274 struct elf32_arm_link_hash_table *globals;
8275 char *tmp_name;
906e58ca 8276
0e1862bb 8277 if (bfd_link_relocatable (link_info))
c7b8f16e 8278 return;
2e6030b9
MS		 8279
8280 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8281 if (! is_arm_elf (abfd))
2e6030b9
MS		 8282 return;
8283
c7b8f16e 8284 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8285 if (globals == NULL)
8286 return;
906e58ca 8287
21d799b5 8288 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8289 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8290
8291 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8292 {
8293 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8294 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8295
c7b8f16e 8296 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8297 {
8298 struct elf_link_hash_entry *myh;
8299 bfd_vma vma;
8300
8301 switch (errnode->type)
8302 {
8303 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8304 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8305 /* Find veneer symbol. */
8306 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8307 errnode->u.b.veneer->u.v.id);
8308
99059e56
RM		 8309 myh = elf_link_hash_lookup
8310 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8311
a504d23a 8312 if (myh == NULL)
90b6238f
AM		 8313 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8314 abfd, "VFP11", tmp_name);
a504d23a
LA		 8315
8316 vma = myh->root.u.def.section->output_section->vma
8317 + myh->root.u.def.section->output_offset
8318 + myh->root.u.def.value;
8319
8320 errnode->u.b.veneer->vma = vma;
8321 break;
8322
8323 case VFP11_ERRATUM_ARM_VENEER:
8324 case VFP11_ERRATUM_THUMB_VENEER:
8325 /* Find return location. */
8326 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8327 errnode->u.v.id);
8328
8329 myh = elf_link_hash_lookup
8330 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8331
8332 if (myh == NULL)
90b6238f
AM		 8333 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8334 abfd, "VFP11", tmp_name);
a504d23a
LA		 8335
8336 vma = myh->root.u.def.section->output_section->vma
8337 + myh->root.u.def.section->output_offset
8338 + myh->root.u.def.value;
8339
8340 errnode->u.v.branch->vma = vma;
8341 break;
8342
8343 default:
8344 abort ();
8345 }
8346 }
8347 }
8348
8349 free (tmp_name);
8350}
8351
8352/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8353 return locations after sections have been laid out, using
8354 specially-named symbols. */
8355
8356void
8357bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8358 struct bfd_link_info *link_info)
8359{
8360 asection *sec;
8361 struct elf32_arm_link_hash_table *globals;
8362 char *tmp_name;
8363
8364 if (bfd_link_relocatable (link_info))
8365 return;
8366
8367 /* Skip if this bfd does not correspond to an ELF image. */
8368 if (! is_arm_elf (abfd))
8369 return;
8370
8371 globals = elf32_arm_hash_table (link_info);
8372 if (globals == NULL)
8373 return;
8374
8375 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8376 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8377
8378 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8379 {
8380 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8381 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8382
8383 for (; errnode != NULL; errnode = errnode->next)
8384 {
8385 struct elf_link_hash_entry *myh;
8386 bfd_vma vma;
8387
8388 switch (errnode->type)
8389 {
8390 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8391 /* Find veneer symbol. */
8392 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8393 errnode->u.b.veneer->u.v.id);
8394
8395 myh = elf_link_hash_lookup
8396 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8397
8398 if (myh == NULL)
90b6238f
AM		 8399 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8400 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8401
8402 vma = myh->root.u.def.section->output_section->vma
8403 + myh->root.u.def.section->output_offset
8404 + myh->root.u.def.value;
8405
8406 errnode->u.b.veneer->vma = vma;
8407 break;
8408
8409 case STM32L4XX_ERRATUM_VENEER:
8410 /* Find return location. */
8411 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8412 errnode->u.v.id);
8413
8414 myh = elf_link_hash_lookup
8415 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8416
8417 if (myh == NULL)
90b6238f
AM		 8418 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8419 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8420
8421 vma = myh->root.u.def.section->output_section->vma
8422 + myh->root.u.def.section->output_offset
8423 + myh->root.u.def.value;
8424
8425 errnode->u.v.branch->vma = vma;
8426 break;
8427
8428 default:
8429 abort ();
8430 }
8431 }
8432 }
8433
8434 free (tmp_name);
8435}
8436
8437static inline bfd_boolean
8438is_thumb2_ldmia (const insn32 insn)
8439{
8440 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8441 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8442 return (insn & 0xffd02000) == 0xe8900000;
8443}
8444
8445static inline bfd_boolean
8446is_thumb2_ldmdb (const insn32 insn)
8447{
8448 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8449 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8450 return (insn & 0xffd02000) == 0xe9100000;
8451}
8452
8453static inline bfd_boolean
8454is_thumb2_vldm (const insn32 insn)
8455{
8456 /* A6.5 Extension register load or store instruction
8457 A7.7.229
9239bbd3
CM		 8458 We look for SP 32-bit and DP 64-bit registers.
8459 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8460 <list> is consecutive 64-bit registers
8461 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8462 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8463 <list> is consecutive 32-bit registers
8464 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8465 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8466 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8467 return
9239bbd3
CM		 8468 (((insn & 0xfe100f00) == 0xec100b00) ||
8469 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8470 && /* (IA without !). */
8471 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8472 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8473 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8474 /* (DB with !). */
8475 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8476}
8477
8478/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8479 VLDM opcode and:
8480 - computes the number and the mode of memory accesses
8481 - decides if the replacement should be done:
8482 . replaces only if > 8-word accesses
8483 . or (testing purposes only) replaces all accesses. */
8484
8485static bfd_boolean
8486stm32l4xx_need_create_replacing_stub (const insn32 insn,
8487 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8488{
9239bbd3 8489 int nb_words = 0;
a504d23a
LA		 8490
8491 /* The field encoding the register list is the same for both LDMIA
8492 and LDMDB encodings. */
8493 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8494 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8495 else if (is_thumb2_vldm (insn))
9239bbd3 8496 nb_words = (insn & 0xff);
a504d23a
LA		 8497
8498 /* DEFAULT mode accounts for the real bug condition situation,
8499 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8500 return
9239bbd3 8501 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8502 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8503}
8504
8505/* Look for potentially-troublesome code sequences which might trigger
8506 the STM STM32L4XX erratum. */
8507
8508bfd_boolean
8509bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8510 struct bfd_link_info *link_info)
8511{
8512 asection *sec;
8513 bfd_byte *contents = NULL;
8514 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8515
8516 if (globals == NULL)
8517 return FALSE;
8518
8519 /* If we are only performing a partial link do not bother
8520 to construct any glue. */
8521 if (bfd_link_relocatable (link_info))
8522 return TRUE;
8523
8524 /* Skip if this bfd does not correspond to an ELF image. */
8525 if (! is_arm_elf (abfd))
8526 return TRUE;
8527
8528 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8529 return TRUE;
8530
8531 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8532 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8533 return TRUE;
8534
8535 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8536 {
8537 unsigned int i, span;
8538 struct _arm_elf_section_data *sec_data;
8539
8540 /* If we don't have executable progbits, we're not interested in this
8541 section. Also skip if section is to be excluded. */
8542 if (elf_section_type (sec) != SHT_PROGBITS
8543 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8544 || (sec->flags & SEC_EXCLUDE) != 0
8545 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8546 || sec->output_section == bfd_abs_section_ptr
8547 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8548 continue;
8549
8550 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8551
a504d23a
LA		 8552 if (sec_data->mapcount == 0)
8553 continue;
c7b8f16e 8554
a504d23a
LA		 8555 if (elf_section_data (sec)->this_hdr.contents != NULL)
8556 contents = elf_section_data (sec)->this_hdr.contents;
8557 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8558 goto error_return;
c7b8f16e 8559
a504d23a
LA		 8560 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8561 elf32_arm_compare_mapping);
c7b8f16e 8562
a504d23a
LA		 8563 for (span = 0; span < sec_data->mapcount; span++)
8564 {
8565 unsigned int span_start = sec_data->map[span].vma;
8566 unsigned int span_end = (span == sec_data->mapcount - 1)
8567 ? sec->size : sec_data->map[span + 1].vma;
8568 char span_type = sec_data->map[span].type;
8569 int itblock_current_pos = 0;
c7b8f16e 8570
a504d23a
LA		 8571 /* Only Thumb2 mode need be supported with this CM4 specific
8572 code, we should not encounter any arm mode eg span_type
8573 != 'a'. */
8574 if (span_type != 't')
8575 continue;
c7b8f16e 8576
a504d23a
LA		 8577 for (i = span_start; i < span_end;)
8578 {
8579 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8580 bfd_boolean insn_32bit = FALSE;
8581 bfd_boolean is_ldm = FALSE;
8582 bfd_boolean is_vldm = FALSE;
8583 bfd_boolean is_not_last_in_it_block = FALSE;
8584
8585 /* The first 16-bits of all 32-bit thumb2 instructions start
8586 with opcode[15..13]=0b111 and the encoded op1 can be anything
8587 except opcode[12..11]!=0b00.
8588 See 32-bit Thumb instruction encoding. */
8589 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8590 insn_32bit = TRUE;
c7b8f16e 8591
a504d23a
LA		 8592 /* Compute the predicate that tells if the instruction
8593 is concerned by the IT block
8594 - Creates an error if there is a ldm that is not
8595 last in the IT block thus cannot be replaced
8596 - Otherwise we can create a branch at the end of the
8597 IT block, it will be controlled naturally by IT
8598 with the proper pseudo-predicate
8599 - So the only interesting predicate is the one that
8600 tells that we are not on the last item of an IT
8601 block. */
8602 if (itblock_current_pos != 0)
8603 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8604
a504d23a
LA		 8605 if (insn_32bit)
8606 {
8607 /* Load the rest of the insn (in manual-friendly order). */
8608 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8609 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8610 is_vldm = is_thumb2_vldm (insn);
8611
8612 /* Veneers are created for (v)ldm depending on
8613 option flags and memory accesses conditions; but
8614 if the instruction is not the last instruction of
8615 an IT block, we cannot create a jump there, so we
8616 bail out. */
5025eb7c
AO		 8617 if ((is_ldm || is_vldm)
8618 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8619 (insn, globals->stm32l4xx_fix))
8620 {
8621 if (is_not_last_in_it_block)
8622 {
4eca0228 8623 _bfd_error_handler
695344c0 8624 /* xgettext:c-format */
871b3ab2 8625 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8626 " in non-last IT block instruction:"
8627 " STM32L4XX veneer cannot be generated; "
8628 "use gcc option -mrestrict-it to generate"
8629 " only one instruction per IT block"),
d42c267e 8630 abfd, sec, i);
a504d23a
LA		 8631 }
8632 else
8633 {
8634 elf32_stm32l4xx_erratum_list *newerr =
8635 (elf32_stm32l4xx_erratum_list *)
8636 bfd_zmalloc
8637 (sizeof (elf32_stm32l4xx_erratum_list));
8638
8639 elf32_arm_section_data (sec)
8640 ->stm32l4xx_erratumcount += 1;
8641 newerr->u.b.insn = insn;
8642 /* We create only thumb branches. */
8643 newerr->type =
8644 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8645 record_stm32l4xx_erratum_veneer
8646 (link_info, newerr, abfd, sec,
8647 i,
8648 is_ldm ?
8649 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8650 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8651 newerr->vma = -1;
8652 newerr->next = sec_data->stm32l4xx_erratumlist;
8653 sec_data->stm32l4xx_erratumlist = newerr;
8654 }
8655 }
8656 }
8657 else
8658 {
8659 /* A7.7.37 IT p208
8660 IT blocks are only encoded in T1
8661 Encoding T1: IT{x{y{z}}} <firstcond>
8662 1 0 1 1 - 1 1 1 1 - firstcond - mask
8663 if mask = '0000' then see 'related encodings'
8664 We don't deal with UNPREDICTABLE, just ignore these.
8665 There can be no nested IT blocks so an IT block
8666 is naturally a new one for which it is worth
8667 computing its size. */
5025eb7c
AO		 8668 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8669 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8670 /* If we have a new IT block we compute its size. */
8671 if (is_newitblock)
8672 {
8673 /* Compute the number of instructions controlled
8674 by the IT block, it will be used to decide
8675 whether we are inside an IT block or not. */
8676 unsigned int mask = insn & 0x000f;
8677 itblock_current_pos = 4 - ctz (mask);
8678 }
8679 }
8680
8681 i += insn_32bit ? 4 : 2;
99059e56
RM		 8682 }
8683 }
a504d23a
LA		 8684
8685 if (contents != NULL
8686 && elf_section_data (sec)->this_hdr.contents != contents)
8687 free (contents);
8688 contents = NULL;
c7b8f16e 8689 }
906e58ca 8690
a504d23a
LA		 8691 return TRUE;
8692
8693error_return:
8694 if (contents != NULL
8695 && elf_section_data (sec)->this_hdr.contents != contents)
8696 free (contents);
c7b8f16e 8697
a504d23a
LA		 8698 return FALSE;
8699}
c7b8f16e 8700
eb043451
PB		 8701/* Set target relocation values needed during linking. */
8702
8703void
68c39892 8704bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8705 struct bfd_link_info *link_info,
68c39892 8706 struct elf32_arm_params *params)
eb043451
PB		 8707{
8708 struct elf32_arm_link_hash_table *globals;
8709
8710 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8711 if (globals == NULL)
8712 return;
eb043451 8713
68c39892
TP		 8714 globals->target1_is_rel = params->target1_is_rel;
8715 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8716 globals->target2_reloc = R_ARM_REL32;
68c39892 8717 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8718 globals->target2_reloc = R_ARM_ABS32;
68c39892 8719 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8720 globals->target2_reloc = R_ARM_GOT_PREL;
8721 else
8722 {
90b6238f 8723 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 8724 params->target2_type);
eb043451 8725 }
68c39892
TP		 8726 globals->fix_v4bx = params->fix_v4bx;
8727 globals->use_blx |= params->use_blx;
8728 globals->vfp11_fix = params->vfp11_denorm_fix;
8729 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8730 globals->pic_veneer = params->pic_veneer;
8731 globals->fix_cortex_a8 = params->fix_cortex_a8;
8732 globals->fix_arm1176 = params->fix_arm1176;
8733 globals->cmse_implib = params->cmse_implib;
8734 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8735
0ffa91dd 8736 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8737 elf_arm_tdata (output_bfd)->no_enum_size_warning
8738 = params->no_enum_size_warning;
8739 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8740 = params->no_wchar_size_warning;
eb043451 8741}
eb043451 8742
12a0a0fd 8743/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8744
12a0a0fd
PB		 8745static void
8746insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8747{
8748 bfd_vma upper;
8749 bfd_vma lower;
8750 int reloc_sign;
8751
8752 BFD_ASSERT ((offset & 1) == 0);
8753
8754 upper = bfd_get_16 (abfd, insn);
8755 lower = bfd_get_16 (abfd, insn + 2);
8756 reloc_sign = (offset < 0) ? 1 : 0;
8757 upper = (upper & ~(bfd_vma) 0x7ff)
8758 | ((offset >> 12) & 0x3ff)
8759 | (reloc_sign << 10);
906e58ca 8760 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8761 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8762 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8763 | ((offset >> 1) & 0x7ff);
8764 bfd_put_16 (abfd, upper, insn);
8765 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8766}
8767
9b485d32
NC		 8768/* Thumb code calling an ARM function. */
8769
252b5132 8770static int
57e8b36a 8771elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 8772 const char * name,
8773 bfd * input_bfd,
8774 bfd * output_bfd,
8775 asection * input_section,
8776 bfd_byte * hit_data,
8777 asection * sym_sec,
8778 bfd_vma offset,
8779 bfd_signed_vma addend,
8780 bfd_vma val,
f2a9dd69 8781 char **error_message)
252b5132 8782{
bcbdc74c 8783 asection * s = 0;
dc810e39 8784 bfd_vma my_offset;
252b5132 8785 long int ret_offset;
bcbdc74c
NC		 8786 struct elf_link_hash_entry * myh;
8787 struct elf32_arm_link_hash_table * globals;
252b5132 8788
f2a9dd69 8789 myh = find_thumb_glue (info, name, error_message);
252b5132 8790 if (myh == NULL)
b34976b6 8791 return FALSE;
252b5132
RH		 8792
8793 globals = elf32_arm_hash_table (info);
252b5132
RH		 8794 BFD_ASSERT (globals != NULL);
8795 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8796
8797 my_offset = myh->root.u.def.value;
8798
3d4d4302
AM		 8799 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8800 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8801
8802 BFD_ASSERT (s != NULL);
8803 BFD_ASSERT (s->contents != NULL);
8804 BFD_ASSERT (s->output_section != NULL);
8805
8806 if ((my_offset & 0x01) == 0x01)
8807 {
8808 if (sym_sec != NULL
8809 && sym_sec->owner != NULL
8810 && !INTERWORK_FLAG (sym_sec->owner))
8811 {
4eca0228 8812 _bfd_error_handler
90b6238f
AM		 8813 (_("%pB(%s): warning: interworking not enabled;"
8814 " first occurrence: %pB: %s call to %s"),
8815 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 8816
b34976b6 8817 return FALSE;
252b5132
RH		 8818 }
8819
8820 --my_offset;
8821 myh->root.u.def.value = my_offset;
8822
52ab56c2
PB		 8823 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8824 s->contents + my_offset);
252b5132 8825
52ab56c2
PB		 8826 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8827 s->contents + my_offset + 2);
252b5132
RH		 8828
8829 ret_offset =
9b485d32
NC		 8830 /* Address of destination of the stub. */
8831 ((bfd_signed_vma) val)
252b5132 8832 - ((bfd_signed_vma)
57e8b36a
NC		 8833 /* Offset from the start of the current section
8834 to the start of the stubs. */
9b485d32
NC		 8835 (s->output_offset
8836 /* Offset of the start of this stub from the start of the stubs. */
8837 + my_offset
8838 /* Address of the start of the current section. */
8839 + s->output_section->vma)
8840 /* The branch instruction is 4 bytes into the stub. */
8841 + 4
8842 /* ARM branches work from the pc of the instruction + 8. */
8843 + 8);
252b5132 8844
52ab56c2
PB		 8845 put_arm_insn (globals, output_bfd,
8846 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8847 s->contents + my_offset + 4);
252b5132
RH		 8848 }
8849
8850 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8851
427bfd90
NC		 8852 /* Now go back and fix up the original BL insn to point to here. */
8853 ret_offset =
8854 /* Address of where the stub is located. */
8855 (s->output_section->vma + s->output_offset + my_offset)
8856 /* Address of where the BL is located. */
57e8b36a
NC		 8857 - (input_section->output_section->vma + input_section->output_offset
8858 + offset)
427bfd90
NC		 8859 /* Addend in the relocation. */
8860 - addend
8861 /* Biassing for PC-relative addressing. */
8862 - 8;
252b5132 8863
12a0a0fd 8864 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8865
b34976b6 8866 return TRUE;
252b5132
RH		 8867}
8868
a4fd1a8e 8869/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8870
a4fd1a8e
PB		 8871static struct elf_link_hash_entry *
8872elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 8873 const char * name,
8874 bfd * input_bfd,
8875 bfd * output_bfd,
8876 asection * sym_sec,
8877 bfd_vma val,
8878 asection * s,
8879 char ** error_message)
252b5132 8880{
dc810e39 8881 bfd_vma my_offset;
252b5132 8882 long int ret_offset;
bcbdc74c
NC		 8883 struct elf_link_hash_entry * myh;
8884 struct elf32_arm_link_hash_table * globals;
252b5132 8885
f2a9dd69 8886 myh = find_arm_glue (info, name, error_message);
252b5132 8887 if (myh == NULL)
a4fd1a8e 8888 return NULL;
252b5132
RH		 8889
8890 globals = elf32_arm_hash_table (info);
252b5132
RH		 8891 BFD_ASSERT (globals != NULL);
8892 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8893
8894 my_offset = myh->root.u.def.value;
252b5132
RH		 8895
8896 if ((my_offset & 0x01) == 0x01)
8897 {
8898 if (sym_sec != NULL
8899 && sym_sec->owner != NULL
8900 && !INTERWORK_FLAG (sym_sec->owner))
8901 {
4eca0228 8902 _bfd_error_handler
90b6238f
AM		 8903 (_("%pB(%s): warning: interworking not enabled;"
8904 " first occurrence: %pB: %s call to %s"),
8905 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 8906 }
9b485d32 8907
252b5132
RH		 8908 --my_offset;
8909 myh->root.u.def.value = my_offset;
8910
0e1862bb
L		 8911 if (bfd_link_pic (info)
8912 || globals->root.is_relocatable_executable
27e55c4d 8913 || globals->pic_veneer)
8f6277f5
PB		 8914 {
8915 /* For relocatable objects we can't use absolute addresses,
8916 so construct the address from a relative offset. */
8917 /* TODO: If the offset is small it's probably worth
8918 constructing the address with adds. */
52ab56c2
PB		 8919 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8920 s->contents + my_offset);
8921 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8922 s->contents + my_offset + 4);
8923 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8924 s->contents + my_offset + 8);
8f6277f5
PB		 8925 /* Adjust the offset by 4 for the position of the add,
8926 and 8 for the pipeline offset. */
8927 ret_offset = (val - (s->output_offset
8928 + s->output_section->vma
8929 + my_offset + 12))
8930 | 1;
8931 bfd_put_32 (output_bfd, ret_offset,
8932 s->contents + my_offset + 12);
8933 }
26079076
PB		 8934 else if (globals->use_blx)
8935 {
8936 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8937 s->contents + my_offset);
8938
8939 /* It's a thumb address. Add the low order bit. */
8940 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8941 s->contents + my_offset + 4);
8942 }
8f6277f5
PB		 8943 else
8944 {
52ab56c2
PB		 8945 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8946 s->contents + my_offset);
252b5132 8947
52ab56c2
PB		 8948 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8949 s->contents + my_offset + 4);
252b5132 8950
8f6277f5
PB		 8951 /* It's a thumb address. Add the low order bit. */
8952 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8953 s->contents + my_offset + 8);
8029a119
NC		 8954
8955 my_offset += 12;
8f6277f5 8956 }
252b5132
RH		 8957 }
8958
8959 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8960
a4fd1a8e
PB		 8961 return myh;
8962}
8963
8964/* Arm code calling a Thumb function. */
8965
8966static int
8967elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 8968 const char * name,
8969 bfd * input_bfd,
8970 bfd * output_bfd,
8971 asection * input_section,
8972 bfd_byte * hit_data,
8973 asection * sym_sec,
8974 bfd_vma offset,
8975 bfd_signed_vma addend,
8976 bfd_vma val,
f2a9dd69 8977 char **error_message)
a4fd1a8e
PB		 8978{
8979 unsigned long int tmp;
8980 bfd_vma my_offset;
8981 asection * s;
8982 long int ret_offset;
8983 struct elf_link_hash_entry * myh;
8984 struct elf32_arm_link_hash_table * globals;
8985
8986 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8987 BFD_ASSERT (globals != NULL);
8988 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8989
3d4d4302
AM		 8990 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8991 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8992 BFD_ASSERT (s != NULL);
8993 BFD_ASSERT (s->contents != NULL);
8994 BFD_ASSERT (s->output_section != NULL);
8995
8996 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8997 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8998 if (!myh)
8999 return FALSE;
9000
9001 my_offset = myh->root.u.def.value;
252b5132
RH		 9002 tmp = bfd_get_32 (input_bfd, hit_data);
9003 tmp = tmp & 0xFF000000;
9004
9b485d32 9005 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9006 ret_offset = (s->output_offset
9007 + my_offset
9008 + s->output_section->vma
9009 - (input_section->output_offset
9010 + input_section->output_section->vma
9011 + offset + addend)
9012 - 8);
9a5aca8c 9013
252b5132
RH		 9014 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9015
dc810e39 9016 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9017
b34976b6 9018 return TRUE;
252b5132
RH		 9019}
9020
a4fd1a8e
PB		 9021/* Populate Arm stub for an exported Thumb function. */
9022
9023static bfd_boolean
9024elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9025{
9026 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9027 asection * s;
9028 struct elf_link_hash_entry * myh;
9029 struct elf32_arm_link_hash_entry *eh;
9030 struct elf32_arm_link_hash_table * globals;
9031 asection *sec;
9032 bfd_vma val;
f2a9dd69 9033 char *error_message;
a4fd1a8e 9034
906e58ca 9035 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9036 /* Allocate stubs for exported Thumb functions on v4t. */
9037 if (eh->export_glue == NULL)
9038 return TRUE;
9039
9040 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9041 BFD_ASSERT (globals != NULL);
9042 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9043
3d4d4302
AM		 9044 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9045 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9046 BFD_ASSERT (s != NULL);
9047 BFD_ASSERT (s->contents != NULL);
9048 BFD_ASSERT (s->output_section != NULL);
9049
9050 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9051
9052 BFD_ASSERT (sec->output_section != NULL);
9053
a4fd1a8e
PB		 9054 val = eh->export_glue->root.u.def.value + sec->output_offset
9055 + sec->output_section->vma;
8029a119 9056
a4fd1a8e
PB		 9057 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9058 h->root.u.def.section->owner,
f2a9dd69
DJ		 9059 globals->obfd, sec, val, s,
9060 &error_message);
a4fd1a8e
PB		 9061 BFD_ASSERT (myh);
9062 return TRUE;
9063}
9064
845b51d6
PB		 9065/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9066
9067static bfd_vma
9068elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9069{
9070 bfd_byte *p;
9071 bfd_vma glue_addr;
9072 asection *s;
9073 struct elf32_arm_link_hash_table *globals;
9074
9075 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9076 BFD_ASSERT (globals != NULL);
9077 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9078
3d4d4302
AM		 9079 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9080 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9081 BFD_ASSERT (s != NULL);
9082 BFD_ASSERT (s->contents != NULL);
9083 BFD_ASSERT (s->output_section != NULL);
9084
9085 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9086
9087 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9088
9089 if ((globals->bx_glue_offset[reg] & 1) == 0)
9090 {
9091 p = s->contents + glue_addr;
9092 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9093 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9094 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9095 globals->bx_glue_offset[reg] |= 1;
9096 }
9097
9098 return glue_addr + s->output_section->vma + s->output_offset;
9099}
9100
a4fd1a8e
PB		 9101/* Generate Arm stubs for exported Thumb symbols. */
9102static void
906e58ca 9103elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9104 struct bfd_link_info *link_info)
9105{
9106 struct elf32_arm_link_hash_table * globals;
9107
8029a119
NC		 9108 if (link_info == NULL)
9109 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9110 return;
9111
9112 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9113 if (globals == NULL)
9114 return;
9115
84c08195
PB		 9116 /* If blx is available then exported Thumb symbols are OK and there is
9117 nothing to do. */
a4fd1a8e
PB		 9118 if (globals->use_blx)
9119 return;
9120
9121 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9122 link_info);
9123}
9124
47beaa6a
RS		 9125/* Reserve space for COUNT dynamic relocations in relocation selection
9126 SRELOC. */
9127
9128static void
9129elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9130 bfd_size_type count)
9131{
9132 struct elf32_arm_link_hash_table *htab;
9133
9134 htab = elf32_arm_hash_table (info);
9135 BFD_ASSERT (htab->root.dynamic_sections_created);
9136 if (sreloc == NULL)
9137 abort ();
9138 sreloc->size += RELOC_SIZE (htab) * count;
9139}
9140
34e77a92
RS		 9141/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9142 dynamic, the relocations should go in SRELOC, otherwise they should
9143 go in the special .rel.iplt section. */
9144
9145static void
9146elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9147 bfd_size_type count)
9148{
9149 struct elf32_arm_link_hash_table *htab;
9150
9151 htab = elf32_arm_hash_table (info);
9152 if (!htab->root.dynamic_sections_created)
9153 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9154 else
9155 {
9156 BFD_ASSERT (sreloc != NULL);
9157 sreloc->size += RELOC_SIZE (htab) * count;
9158 }
9159}
9160
47beaa6a
RS		 9161/* Add relocation REL to the end of relocation section SRELOC. */
9162
9163static void
9164elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9165 asection *sreloc, Elf_Internal_Rela *rel)
9166{
9167 bfd_byte *loc;
9168 struct elf32_arm_link_hash_table *htab;
9169
9170 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9171 if (!htab->root.dynamic_sections_created
9172 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9173 sreloc = htab->root.irelplt;
47beaa6a
RS		 9174 if (sreloc == NULL)
9175 abort ();
9176 loc = sreloc->contents;
9177 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9178 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9179 abort ();
9180 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9181}
9182
34e77a92
RS		 9183/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9184 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9185 to .plt. */
9186
9187static void
9188elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9189 bfd_boolean is_iplt_entry,
9190 union gotplt_union *root_plt,
9191 struct arm_plt_info *arm_plt)
9192{
9193 struct elf32_arm_link_hash_table *htab;
9194 asection *splt;
9195 asection *sgotplt;
9196
9197 htab = elf32_arm_hash_table (info);
9198
9199 if (is_iplt_entry)
9200 {
9201 splt = htab->root.iplt;
9202 sgotplt = htab->root.igotplt;
9203
99059e56
RM		 9204 /* NaCl uses a special first entry in .iplt too. */
9205 if (htab->nacl_p && splt->size == 0)
9206 splt->size += htab->plt_header_size;
9207
34e77a92
RS		 9208 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9209 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9210 }
9211 else
9212 {
9213 splt = htab->root.splt;
9214 sgotplt = htab->root.sgotplt;
9215
9216 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9217 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9218
9219 /* If this is the first .plt entry, make room for the special
9220 first entry. */
9221 if (splt->size == 0)
9222 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9223
9224 htab->next_tls_desc_index++;
34e77a92
RS		 9225 }
9226
9227 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9228 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9229 splt->size += PLT_THUMB_STUB_SIZE;
9230 root_plt->offset = splt->size;
9231 splt->size += htab->plt_entry_size;
9232
9233 if (!htab->symbian_p)
9234 {
9235 /* We also need to make an entry in the .got.plt section, which
9236 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9237 if (is_iplt_entry)
9238 arm_plt->got_offset = sgotplt->size;
9239 else
9240 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9241 sgotplt->size += 4;
9242 }
9243}
9244
b38cadfb
NC		 9245static bfd_vma
9246arm_movw_immediate (bfd_vma value)
9247{
9248 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9249}
9250
9251static bfd_vma
9252arm_movt_immediate (bfd_vma value)
9253{
9254 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9255}
9256
34e77a92
RS		 9257/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9258 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9259 Otherwise, DYNINDX is the index of the symbol in the dynamic
9260 symbol table and SYM_VALUE is undefined.
9261
9262 ROOT_PLT points to the offset of the PLT entry from the start of its
9263 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9264 bookkeeping information.
34e77a92 9265
57460bcf
NC		 9266 Returns FALSE if there was a problem. */
9267
9268static bfd_boolean
34e77a92
RS		 9269elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9270 union gotplt_union *root_plt,
9271 struct arm_plt_info *arm_plt,
9272 int dynindx, bfd_vma sym_value)
9273{
9274 struct elf32_arm_link_hash_table *htab;
9275 asection *sgot;
9276 asection *splt;
9277 asection *srel;
9278 bfd_byte *loc;
9279 bfd_vma plt_index;
9280 Elf_Internal_Rela rel;
9281 bfd_vma plt_header_size;
9282 bfd_vma got_header_size;
9283
9284 htab = elf32_arm_hash_table (info);
9285
9286 /* Pick the appropriate sections and sizes. */
9287 if (dynindx == -1)
9288 {
9289 splt = htab->root.iplt;
9290 sgot = htab->root.igotplt;
9291 srel = htab->root.irelplt;
9292
9293 /* There are no reserved entries in .igot.plt, and no special
9294 first entry in .iplt. */
9295 got_header_size = 0;
9296 plt_header_size = 0;
9297 }
9298 else
9299 {
9300 splt = htab->root.splt;
9301 sgot = htab->root.sgotplt;
9302 srel = htab->root.srelplt;
9303
9304 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9305 plt_header_size = htab->plt_header_size;
9306 }
9307 BFD_ASSERT (splt != NULL && srel != NULL);
9308
9309 /* Fill in the entry in the procedure linkage table. */
9310 if (htab->symbian_p)
9311 {
9312 BFD_ASSERT (dynindx >= 0);
9313 put_arm_insn (htab, output_bfd,
9314 elf32_arm_symbian_plt_entry[0],
9315 splt->contents + root_plt->offset);
9316 bfd_put_32 (output_bfd,
9317 elf32_arm_symbian_plt_entry[1],
9318 splt->contents + root_plt->offset + 4);
9319
9320 /* Fill in the entry in the .rel.plt section. */
9321 rel.r_offset = (splt->output_section->vma
9322 + splt->output_offset
9323 + root_plt->offset + 4);
9324 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9325
9326 /* Get the index in the procedure linkage table which
9327 corresponds to this symbol. This is the index of this symbol
9328 in all the symbols for which we are making plt entries. The
9329 first entry in the procedure linkage table is reserved. */
9330 plt_index = ((root_plt->offset - plt_header_size)
9331 / htab->plt_entry_size);
9332 }
9333 else
9334 {
9335 bfd_vma got_offset, got_address, plt_address;
9336 bfd_vma got_displacement, initial_got_entry;
9337 bfd_byte * ptr;
9338
9339 BFD_ASSERT (sgot != NULL);
9340
9341 /* Get the offset into the .(i)got.plt table of the entry that
9342 corresponds to this function. */
9343 got_offset = (arm_plt->got_offset & -2);
9344
9345 /* Get the index in the procedure linkage table which
9346 corresponds to this symbol. This is the index of this symbol
9347 in all the symbols for which we are making plt entries.
9348 After the reserved .got.plt entries, all symbols appear in
9349 the same order as in .plt. */
9350 plt_index = (got_offset - got_header_size) / 4;
9351
9352 /* Calculate the address of the GOT entry. */
9353 got_address = (sgot->output_section->vma
9354 + sgot->output_offset
9355 + got_offset);
9356
9357 /* ...and the address of the PLT entry. */
9358 plt_address = (splt->output_section->vma
9359 + splt->output_offset
9360 + root_plt->offset);
9361
9362 ptr = splt->contents + root_plt->offset;
0e1862bb 9363 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9364 {
9365 unsigned int i;
9366 bfd_vma val;
9367
9368 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9369 {
9370 val = elf32_arm_vxworks_shared_plt_entry[i];
9371 if (i == 2)
9372 val |= got_address - sgot->output_section->vma;
9373 if (i == 5)
9374 val |= plt_index * RELOC_SIZE (htab);
9375 if (i == 2 || i == 5)
9376 bfd_put_32 (output_bfd, val, ptr);
9377 else
9378 put_arm_insn (htab, output_bfd, val, ptr);
9379 }
9380 }
9381 else if (htab->vxworks_p)
9382 {
9383 unsigned int i;
9384 bfd_vma val;
9385
9386 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9387 {
9388 val = elf32_arm_vxworks_exec_plt_entry[i];
9389 if (i == 2)
9390 val |= got_address;
9391 if (i == 4)
9392 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9393 if (i == 5)
9394 val |= plt_index * RELOC_SIZE (htab);
9395 if (i == 2 || i == 5)
9396 bfd_put_32 (output_bfd, val, ptr);
9397 else
9398 put_arm_insn (htab, output_bfd, val, ptr);
9399 }
9400
9401 loc = (htab->srelplt2->contents
9402 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9403
9404 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9405 referencing the GOT for this PLT entry. */
9406 rel.r_offset = plt_address + 8;
9407 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9408 rel.r_addend = got_offset;
9409 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9410 loc += RELOC_SIZE (htab);
9411
9412 /* Create the R_ARM_ABS32 relocation referencing the
9413 beginning of the PLT for this GOT entry. */
9414 rel.r_offset = got_address;
9415 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9416 rel.r_addend = 0;
9417 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9418 }
b38cadfb
NC		 9419 else if (htab->nacl_p)
9420 {
9421 /* Calculate the displacement between the PLT slot and the
9422 common tail that's part of the special initial PLT slot. */
6034aab8 9423 int32_t tail_displacement
b38cadfb
NC		 9424 = ((splt->output_section->vma + splt->output_offset
9425 + ARM_NACL_PLT_TAIL_OFFSET)
9426 - (plt_address + htab->plt_entry_size + 4));
9427 BFD_ASSERT ((tail_displacement & 3) == 0);
9428 tail_displacement >>= 2;
9429
9430 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9431 || (-tail_displacement & 0xff000000) == 0);
9432
9433 /* Calculate the displacement between the PLT slot and the entry
9434 in the GOT. The offset accounts for the value produced by
9435 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9436 got_displacement = (got_address
99059e56 9437 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9438
9439 /* NaCl does not support interworking at all. */
9440 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9441
9442 put_arm_insn (htab, output_bfd,
9443 elf32_arm_nacl_plt_entry[0]
9444 | arm_movw_immediate (got_displacement),
9445 ptr + 0);
9446 put_arm_insn (htab, output_bfd,
9447 elf32_arm_nacl_plt_entry[1]
9448 | arm_movt_immediate (got_displacement),
9449 ptr + 4);
9450 put_arm_insn (htab, output_bfd,
9451 elf32_arm_nacl_plt_entry[2],
9452 ptr + 8);
9453 put_arm_insn (htab, output_bfd,
9454 elf32_arm_nacl_plt_entry[3]
9455 | (tail_displacement & 0x00ffffff),
9456 ptr + 12);
9457 }
57460bcf
NC		 9458 else if (using_thumb_only (htab))
9459 {
eed94f8f 9460 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9461 if (!using_thumb2 (htab))
eed94f8f
NC		 9462 {
9463 /* FIXME: We ought to be able to generate thumb-1 PLT
9464 instructions... */
90b6238f 9465 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9466 output_bfd);
9467 return FALSE;
9468 }
57460bcf 9469
eed94f8f
NC		 9470 /* Calculate the displacement between the PLT slot and the entry in
9471 the GOT. The 12-byte offset accounts for the value produced by
9472 adding to pc in the 3rd instruction of the PLT stub. */
9473 got_displacement = got_address - (plt_address + 12);
9474
9475 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9476 instead of 'put_thumb_insn'. */
9477 put_arm_insn (htab, output_bfd,
9478 elf32_thumb2_plt_entry[0]
9479 | ((got_displacement & 0x000000ff) << 16)
9480 | ((got_displacement & 0x00000700) << 20)
9481 | ((got_displacement & 0x00000800) >> 1)
9482 | ((got_displacement & 0x0000f000) >> 12),
9483 ptr + 0);
9484 put_arm_insn (htab, output_bfd,
9485 elf32_thumb2_plt_entry[1]
9486 | ((got_displacement & 0x00ff0000) )
9487 | ((got_displacement & 0x07000000) << 4)
9488 | ((got_displacement & 0x08000000) >> 17)
9489 | ((got_displacement & 0xf0000000) >> 28),
9490 ptr + 4);
9491 put_arm_insn (htab, output_bfd,
9492 elf32_thumb2_plt_entry[2],
9493 ptr + 8);
9494 put_arm_insn (htab, output_bfd,
9495 elf32_thumb2_plt_entry[3],
9496 ptr + 12);
57460bcf 9497 }
34e77a92
RS		 9498 else
9499 {
9500 /* Calculate the displacement between the PLT slot and the
9501 entry in the GOT. The eight-byte offset accounts for the
9502 value produced by adding to pc in the first instruction
9503 of the PLT stub. */
9504 got_displacement = got_address - (plt_address + 8);
9505
34e77a92
RS		 9506 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9507 {
9508 put_thumb_insn (htab, output_bfd,
9509 elf32_arm_plt_thumb_stub[0], ptr - 4);
9510 put_thumb_insn (htab, output_bfd,
9511 elf32_arm_plt_thumb_stub[1], ptr - 2);
9512 }
9513
1db37fe6
YG		 9514 if (!elf32_arm_use_long_plt_entry)
9515 {
9516 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9517
9518 put_arm_insn (htab, output_bfd,
9519 elf32_arm_plt_entry_short[0]
9520 | ((got_displacement & 0x0ff00000) >> 20),
9521 ptr + 0);
9522 put_arm_insn (htab, output_bfd,
9523 elf32_arm_plt_entry_short[1]
9524 | ((got_displacement & 0x000ff000) >> 12),
9525 ptr+ 4);
9526 put_arm_insn (htab, output_bfd,
9527 elf32_arm_plt_entry_short[2]
9528 | (got_displacement & 0x00000fff),
9529 ptr + 8);
34e77a92 9530#ifdef FOUR_WORD_PLT
1db37fe6 9531 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9532#endif
1db37fe6
YG		 9533 }
9534 else
9535 {
9536 put_arm_insn (htab, output_bfd,
9537 elf32_arm_plt_entry_long[0]
9538 | ((got_displacement & 0xf0000000) >> 28),
9539 ptr + 0);
9540 put_arm_insn (htab, output_bfd,
9541 elf32_arm_plt_entry_long[1]
9542 | ((got_displacement & 0x0ff00000) >> 20),
9543 ptr + 4);
9544 put_arm_insn (htab, output_bfd,
9545 elf32_arm_plt_entry_long[2]
9546 | ((got_displacement & 0x000ff000) >> 12),
9547 ptr+ 8);
9548 put_arm_insn (htab, output_bfd,
9549 elf32_arm_plt_entry_long[3]
9550 | (got_displacement & 0x00000fff),
9551 ptr + 12);
9552 }
34e77a92
RS		 9553 }
9554
9555 /* Fill in the entry in the .rel(a).(i)plt section. */
9556 rel.r_offset = got_address;
9557 rel.r_addend = 0;
9558 if (dynindx == -1)
9559 {
9560 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9561 The dynamic linker or static executable then calls SYM_VALUE
9562 to determine the correct run-time value of the .igot.plt entry. */
9563 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9564 initial_got_entry = sym_value;
9565 }
9566 else
9567 {
9568 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9569 initial_got_entry = (splt->output_section->vma
9570 + splt->output_offset);
9571 }
9572
9573 /* Fill in the entry in the global offset table. */
9574 bfd_put_32 (output_bfd, initial_got_entry,
9575 sgot->contents + got_offset);
9576 }
9577
aba8c3de
WN		 9578 if (dynindx == -1)
9579 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9580 else
9581 {
9582 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9583 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9584 }
57460bcf
NC		 9585
9586 return TRUE;
34e77a92
RS		 9587}
9588
eb043451
PB		 9589/* Some relocations map to different relocations depending on the
9590 target. Return the real relocation. */
8029a119 9591
eb043451
PB		 9592static int
9593arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9594 int r_type)
9595{
9596 switch (r_type)
9597 {
9598 case R_ARM_TARGET1:
9599 if (globals->target1_is_rel)
9600 return R_ARM_REL32;
9601 else
9602 return R_ARM_ABS32;
9603
9604 case R_ARM_TARGET2:
9605 return globals->target2_reloc;
9606
9607 default:
9608 return r_type;
9609 }
9610}
eb043451 9611
ba93b8ac
DJ		 9612/* Return the base VMA address which should be subtracted from real addresses
9613 when resolving @dtpoff relocation.
9614 This is PT_TLS segment p_vaddr. */
9615
9616static bfd_vma
9617dtpoff_base (struct bfd_link_info *info)
9618{
9619 /* If tls_sec is NULL, we should have signalled an error already. */
9620 if (elf_hash_table (info)->tls_sec == NULL)
9621 return 0;
9622 return elf_hash_table (info)->tls_sec->vma;
9623}
9624
9625/* Return the relocation value for @tpoff relocation
9626 if STT_TLS virtual address is ADDRESS. */
9627
9628static bfd_vma
9629tpoff (struct bfd_link_info *info, bfd_vma address)
9630{
9631 struct elf_link_hash_table *htab = elf_hash_table (info);
9632 bfd_vma base;
9633
9634 /* If tls_sec is NULL, we should have signalled an error already. */
9635 if (htab->tls_sec == NULL)
9636 return 0;
9637 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9638 return address - htab->tls_sec->vma + base;
9639}
9640
00a97672
RS		 9641/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9642 VALUE is the relocation value. */
9643
9644static bfd_reloc_status_type
9645elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9646{
9647 if (value > 0xfff)
9648 return bfd_reloc_overflow;
9649
9650 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9651 bfd_put_32 (abfd, value, data);
9652 return bfd_reloc_ok;
9653}
9654
0855e32b
NS		 9655/* Handle TLS relaxations. Relaxing is possible for symbols that use
9656 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9657 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9658
9659 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9660 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9661 case of error.
9662
9663 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9664 the pre-relaxed code. It would be nice if the relocs were updated
9665 to match the optimization. */
0855e32b 9666
b38cadfb 9667static bfd_reloc_status_type
0855e32b 9668elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9669 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9670 Elf_Internal_Rela *rel, unsigned long is_local)
9671{
9672 unsigned long insn;
b38cadfb 9673
0855e32b
NS		 9674 switch (ELF32_R_TYPE (rel->r_info))
9675 {
9676 default:
9677 return bfd_reloc_notsupported;
b38cadfb 9678
0855e32b
NS		 9679 case R_ARM_TLS_GOTDESC:
9680 if (is_local)
9681 insn = 0;
9682 else
9683 {
9684 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9685 if (insn & 1)
9686 insn -= 5; /* THUMB */
9687 else
9688 insn -= 8; /* ARM */
9689 }
9690 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9691 return bfd_reloc_continue;
9692
9693 case R_ARM_THM_TLS_DESCSEQ:
9694 /* Thumb insn. */
9695 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9696 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9697 {
9698 if (is_local)
9699 /* nop */
9700 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9701 }
9702 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9703 {
9704 if (is_local)
9705 /* nop */
9706 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9707 else
9708 /* ldr rx,[ry] */
9709 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9710 }
9711 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9712 {
9713 if (is_local)
9714 /* nop */
9715 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9716 else
9717 /* mov r0, rx */
9718 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9719 contents + rel->r_offset);
9720 }
9721 else
9722 {
9723 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9724 /* It's a 32 bit instruction, fetch the rest of it for
9725 error generation. */
9726 insn = (insn << 16)
9727 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9728 _bfd_error_handler
695344c0 9729 /* xgettext:c-format */
2dcf00ce 9730 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 9731 "unexpected %s instruction '%#lx' in TLS trampoline"),
9732 input_bfd, input_sec, (uint64_t) rel->r_offset,
9733 "Thumb", insn);
0855e32b
NS		 9734 return bfd_reloc_notsupported;
9735 }
9736 break;
b38cadfb 9737
0855e32b
NS		 9738 case R_ARM_TLS_DESCSEQ:
9739 /* arm insn. */
9740 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9741 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9742 {
9743 if (is_local)
9744 /* mov rx, ry */
9745 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9746 contents + rel->r_offset);
9747 }
9748 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9749 {
9750 if (is_local)
9751 /* nop */
9752 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9753 else
9754 /* ldr rx,[ry] */
9755 bfd_put_32 (input_bfd, insn & 0xfffff000,
9756 contents + rel->r_offset);
9757 }
9758 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9759 {
9760 if (is_local)
9761 /* nop */
9762 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9763 else
9764 /* mov r0, rx */
9765 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9766 contents + rel->r_offset);
9767 }
9768 else
9769 {
4eca0228 9770 _bfd_error_handler
695344c0 9771 /* xgettext:c-format */
2dcf00ce 9772 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 9773 "unexpected %s instruction '%#lx' in TLS trampoline"),
9774 input_bfd, input_sec, (uint64_t) rel->r_offset,
9775 "ARM", insn);
0855e32b
NS		 9776 return bfd_reloc_notsupported;
9777 }
9778 break;
9779
9780 case R_ARM_TLS_CALL:
9781 /* GD->IE relaxation, turn the instruction into 'nop' or
9782 'ldr r0, [pc,r0]' */
9783 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9784 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9785 break;
b38cadfb 9786
0855e32b 9787 case R_ARM_THM_TLS_CALL:
6a631e86 9788 /* GD->IE relaxation. */
0855e32b
NS		 9789 if (!is_local)
9790 /* add r0,pc; ldr r0, [r0] */
9791 insn = 0x44786800;
60a019a0 9792 else if (using_thumb2 (globals))
0855e32b
NS		 9793 /* nop.w */
9794 insn = 0xf3af8000;
9795 else
9796 /* nop; nop */
9797 insn = 0xbf00bf00;
b38cadfb 9798
0855e32b
NS		 9799 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9800 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9801 break;
9802 }
9803 return bfd_reloc_ok;
9804}
9805
4962c51a
MS		 9806/* For a given value of n, calculate the value of G_n as required to
9807 deal with group relocations. We return it in the form of an
9808 encoded constant-and-rotation, together with the final residual. If n is
9809 specified as less than zero, then final_residual is filled with the
9810 input value and no further action is performed. */
9811
9812static bfd_vma
9813calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9814{
9815 int current_n;
9816 bfd_vma g_n;
9817 bfd_vma encoded_g_n = 0;
9818 bfd_vma residual = value; /* Also known as Y_n. */
9819
9820 for (current_n = 0; current_n <= n; current_n++)
9821 {
9822 int shift;
9823
9824 /* Calculate which part of the value to mask. */
9825 if (residual == 0)
99059e56 9826 shift = 0;
4962c51a 9827 else
99059e56
RM		 9828 {
9829 int msb;
9830
9831 /* Determine the most significant bit in the residual and
9832 align the resulting value to a 2-bit boundary. */
9833 for (msb = 30; msb >= 0; msb -= 2)
9834 if (residual & (3 << msb))
9835 break;
9836
9837 /* The desired shift is now (msb - 6), or zero, whichever
9838 is the greater. */
9839 shift = msb - 6;
9840 if (shift < 0)
9841 shift = 0;
9842 }
4962c51a
MS		 9843
9844 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9845 g_n = residual & (0xff << shift);
9846 encoded_g_n = (g_n >> shift)
99059e56 9847 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9848
9849 /* Calculate the residual for the next time around. */
9850 residual &= ~g_n;
9851 }
9852
9853 *final_residual = residual;
9854
9855 return encoded_g_n;
9856}
9857
9858/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9859 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9860
4962c51a 9861static int
906e58ca 9862identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9863{
9864 int opcode = insn & 0x1e00000;
9865
9866 if (opcode == 1 << 23) /* ADD */
9867 return 1;
9868
9869 if (opcode == 1 << 22) /* SUB */
9870 return -1;
9871
9872 return 0;
9873}
9874
252b5132 9875/* Perform a relocation as part of a final link. */
9b485d32 9876
252b5132 9877static bfd_reloc_status_type
07d6d2b8
AM		 9878elf32_arm_final_link_relocate (reloc_howto_type * howto,
9879 bfd * input_bfd,
9880 bfd * output_bfd,
9881 asection * input_section,
9882 bfd_byte * contents,
9883 Elf_Internal_Rela * rel,
9884 bfd_vma value,
9885 struct bfd_link_info * info,
9886 asection * sym_sec,
9887 const char * sym_name,
9888 unsigned char st_type,
9889 enum arm_st_branch_type branch_type,
0945cdfd 9890 struct elf_link_hash_entry * h,
07d6d2b8
AM		 9891 bfd_boolean * unresolved_reloc_p,
9892 char ** error_message)
9893{
9894 unsigned long r_type = howto->type;
9895 unsigned long r_symndx;
9896 bfd_byte * hit_data = contents + rel->r_offset;
9897 bfd_vma * local_got_offsets;
9898 bfd_vma * local_tlsdesc_gotents;
9899 asection * sgot;
9900 asection * splt;
9901 asection * sreloc = NULL;
9902 asection * srelgot;
9903 bfd_vma addend;
9904 bfd_signed_vma signed_addend;
9905 unsigned char dynreloc_st_type;
9906 bfd_vma dynreloc_value;
ba96a88f 9907 struct elf32_arm_link_hash_table * globals;
34e77a92 9908 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 9909 union gotplt_union *root_plt;
9910 struct arm_plt_info *arm_plt;
9911 bfd_vma plt_offset;
9912 bfd_vma gotplt_offset;
9913 bfd_boolean has_iplt_entry;
9914 bfd_boolean resolved_to_zero;
f21f3fe0 9915
9c504268 9916 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9917 if (globals == NULL)
9918 return bfd_reloc_notsupported;
9c504268 9919
0ffa91dd 9920 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 9921 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 9922
9923 /* Some relocation types map to different relocations depending on the
9c504268 9924 target. We pick the right one here. */
eb043451 9925 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9926
9927 /* It is possible to have linker relaxations on some TLS access
9928 models. Update our information here. */
9929 r_type = elf32_arm_tls_transition (info, r_type, h);
9930
eb043451
PB		 9931 if (r_type != howto->type)
9932 howto = elf32_arm_howto_from_type (r_type);
9c504268 9933
34e77a92 9934 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9935 sgot = globals->root.sgot;
252b5132 9936 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9937 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9938
34e77a92
RS		 9939 if (globals->root.dynamic_sections_created)
9940 srelgot = globals->root.srelgot;
9941 else
9942 srelgot = NULL;
9943
252b5132
RH		 9944 r_symndx = ELF32_R_SYM (rel->r_info);
9945
4e7fd91e 9946 if (globals->use_rel)
ba96a88f 9947 {
4e7fd91e
PB		 9948 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9949
9950 if (addend & ((howto->src_mask + 1) >> 1))
9951 {
9952 signed_addend = -1;
9953 signed_addend &= ~ howto->src_mask;
9954 signed_addend |= addend;
9955 }
9956 else
9957 signed_addend = addend;
ba96a88f
NC		 9958 }
9959 else
4e7fd91e 9960 addend = signed_addend = rel->r_addend;
f21f3fe0 9961
39f21624
NC		 9962 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9963 are resolving a function call relocation. */
9964 if (using_thumb_only (globals)
9965 && (r_type == R_ARM_THM_CALL
9966 || r_type == R_ARM_THM_JUMP24)
9967 && branch_type == ST_BRANCH_TO_ARM)
9968 branch_type = ST_BRANCH_TO_THUMB;
9969
34e77a92
RS		 9970 /* Record the symbol information that should be used in dynamic
9971 relocations. */
9972 dynreloc_st_type = st_type;
9973 dynreloc_value = value;
9974 if (branch_type == ST_BRANCH_TO_THUMB)
9975 dynreloc_value |= 1;
9976
9977 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9978 VALUE appropriately for relocations that we resolve at link time. */
9979 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9980 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9981 &arm_plt)
34e77a92
RS		 9982 && root_plt->offset != (bfd_vma) -1)
9983 {
9984 plt_offset = root_plt->offset;
9985 gotplt_offset = arm_plt->got_offset;
9986
9987 if (h == NULL || eh->is_iplt)
9988 {
9989 has_iplt_entry = TRUE;
9990 splt = globals->root.iplt;
9991
9992 /* Populate .iplt entries here, because not all of them will
9993 be seen by finish_dynamic_symbol. The lower bit is set if
9994 we have already populated the entry. */
9995 if (plt_offset & 1)
9996 plt_offset--;
9997 else
9998 {
57460bcf
NC		 9999 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10000 -1, dynreloc_value))
10001 root_plt->offset |= 1;
10002 else
10003 return bfd_reloc_notsupported;
34e77a92
RS		 10004 }
10005
10006 /* Static relocations always resolve to the .iplt entry. */
10007 st_type = STT_FUNC;
10008 value = (splt->output_section->vma
10009 + splt->output_offset
10010 + plt_offset);
10011 branch_type = ST_BRANCH_TO_ARM;
10012
10013 /* If there are non-call relocations that resolve to the .iplt
10014 entry, then all dynamic ones must too. */
10015 if (arm_plt->noncall_refcount != 0)
10016 {
10017 dynreloc_st_type = st_type;
10018 dynreloc_value = value;
10019 }
10020 }
10021 else
10022 /* We populate the .plt entry in finish_dynamic_symbol. */
10023 splt = globals->root.splt;
10024 }
10025 else
10026 {
10027 splt = NULL;
10028 plt_offset = (bfd_vma) -1;
10029 gotplt_offset = (bfd_vma) -1;
10030 }
10031
95b03e4a
L		 10032 resolved_to_zero = (h != NULL
10033 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10034
252b5132
RH		 10035 switch (r_type)
10036 {
10037 case R_ARM_NONE:
28a094c2
DJ		 10038 /* We don't need to find a value for this symbol. It's just a
10039 marker. */
10040 *unresolved_reloc_p = FALSE;
252b5132
RH		 10041 return bfd_reloc_ok;
10042
00a97672
RS		 10043 case R_ARM_ABS12:
10044 if (!globals->vxworks_p)
10045 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10046 /* Fall through. */
00a97672 10047
252b5132
RH		 10048 case R_ARM_PC24:
10049 case R_ARM_ABS32:
bb224fc3 10050 case R_ARM_ABS32_NOI:
252b5132 10051 case R_ARM_REL32:
bb224fc3 10052 case R_ARM_REL32_NOI:
5b5bb741
PB		 10053 case R_ARM_CALL:
10054 case R_ARM_JUMP24:
dfc5f959 10055 case R_ARM_XPC25:
eb043451 10056 case R_ARM_PREL31:
7359ea65 10057 case R_ARM_PLT32:
7359ea65
DJ		 10058 /* Handle relocations which should use the PLT entry. ABS32/REL32
10059 will use the symbol's value, which may point to a PLT entry, but we
10060 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10061 branches in this object should go to it, except if the PLT is too
10062 far away, in which case a long branch stub should be inserted. */
bb224fc3 10063 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10064 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10065 && r_type != R_ARM_CALL
10066 && r_type != R_ARM_JUMP24
10067 && r_type != R_ARM_PLT32)
34e77a92 10068 && plt_offset != (bfd_vma) -1)
7359ea65 10069 {
34e77a92
RS		 10070 /* If we've created a .plt section, and assigned a PLT entry
10071 to this function, it must either be a STT_GNU_IFUNC reference
10072 or not be known to bind locally. In other cases, we should
10073 have cleared the PLT entry by now. */
10074 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10075
10076 value = (splt->output_section->vma
10077 + splt->output_offset
34e77a92 10078 + plt_offset);
0945cdfd 10079 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10080 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10081 contents, rel->r_offset, value,
00a97672 10082 rel->r_addend);
7359ea65
DJ		 10083 }
10084
67687978
PB		 10085 /* When generating a shared object or relocatable executable, these
10086 relocations are copied into the output file to be resolved at
10087 run time. */
0e1862bb
L		 10088 if ((bfd_link_pic (info)
10089 || globals->root.is_relocatable_executable)
7359ea65 10090 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10091 && !(globals->vxworks_p
3348747a
NS		 10092 && strcmp (input_section->output_section->name,
10093 ".tls_vars") == 0)
bb224fc3 10094 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10095 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10096 && !(input_bfd == globals->stub_bfd
10097 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10098 && (h == NULL
95b03e4a
L		 10099 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10100 && !resolved_to_zero)
7359ea65
DJ		 10101 || h->root.type != bfd_link_hash_undefweak)
10102 && r_type != R_ARM_PC24
5b5bb741
PB		 10103 && r_type != R_ARM_CALL
10104 && r_type != R_ARM_JUMP24
ee06dc07 10105 && r_type != R_ARM_PREL31
7359ea65 10106 && r_type != R_ARM_PLT32)
252b5132 10107 {
947216bf 10108 Elf_Internal_Rela outrel;
b34976b6 10109 bfd_boolean skip, relocate;
f21f3fe0 10110
52db4ec2
JW		 10111 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10112 && !h->def_regular)
10113 {
10114 char *v = _("shared object");
10115
0e1862bb 10116 if (bfd_link_executable (info))
52db4ec2
JW		 10117 v = _("PIE executable");
10118
4eca0228 10119 _bfd_error_handler
871b3ab2 10120 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10121 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10122 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10123 return bfd_reloc_notsupported;
10124 }
10125
0945cdfd
DJ		 10126 *unresolved_reloc_p = FALSE;
10127
34e77a92 10128 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10129 {
83bac4b0
NC		 10130 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10131 ! globals->use_rel);
f21f3fe0 10132
83bac4b0 10133 if (sreloc == NULL)
252b5132 10134 return bfd_reloc_notsupported;
252b5132 10135 }
f21f3fe0 10136
b34976b6
AM		 10137 skip = FALSE;
10138 relocate = FALSE;
f21f3fe0 10139
00a97672 10140 outrel.r_addend = addend;
c629eae0
JJ		 10141 outrel.r_offset =
10142 _bfd_elf_section_offset (output_bfd, info, input_section,
10143 rel->r_offset);
10144 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10145 skip = TRUE;
0bb2d96a 10146 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10147 skip = TRUE, relocate = TRUE;
252b5132
RH		 10148 outrel.r_offset += (input_section->output_section->vma
10149 + input_section->output_offset);
f21f3fe0 10150
252b5132 10151 if (skip)
0bb2d96a 10152 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10153 else if (h != NULL
10154 && h->dynindx != -1
0e1862bb 10155 && (!bfd_link_pic (info)
1dcb9720
JW		 10156 || !(bfd_link_pie (info)
10157 || SYMBOLIC_BIND (info, h))
f5385ebf 10158 || !h->def_regular))
5e681ec4 10159 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10160 else
10161 {
a16385dc
MM		 10162 int symbol;
10163
5e681ec4 10164 /* This symbol is local, or marked to become local. */
34e77a92 10165 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10166 if (globals->symbian_p)
6366ff1e 10167 {
74541ad4
AM		 10168 asection *osec;
10169
6366ff1e
MM		 10170 /* On Symbian OS, the data segment and text segement
10171 can be relocated independently. Therefore, we
10172 must indicate the segment to which this
10173 relocation is relative. The BPABI allows us to
10174 use any symbol in the right segment; we just use
10175 the section symbol as it is convenient. (We
10176 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10177 will not appear in the dynamic symbol table.)
10178
10179 Note that the dynamic linker ignores the section
10180 symbol value, so we don't subtract osec->vma
10181 from the emitted reloc addend. */
10dbd1f3 10182 if (sym_sec)
74541ad4 10183 osec = sym_sec->output_section;
10dbd1f3 10184 else
74541ad4
AM		 10185 osec = input_section->output_section;
10186 symbol = elf_section_data (osec)->dynindx;
10187 if (symbol == 0)
10188 {
10189 struct elf_link_hash_table *htab = elf_hash_table (info);
10190
10191 if ((osec->flags & SEC_READONLY) == 0
10192 && htab->data_index_section != NULL)
10193 osec = htab->data_index_section;
10194 else
10195 osec = htab->text_index_section;
10196 symbol = elf_section_data (osec)->dynindx;
10197 }
6366ff1e
MM		 10198 BFD_ASSERT (symbol != 0);
10199 }
a16385dc
MM		 10200 else
10201 /* On SVR4-ish systems, the dynamic loader cannot
10202 relocate the text and data segments independently,
10203 so the symbol does not matter. */
10204 symbol = 0;
34e77a92
RS		 10205 if (dynreloc_st_type == STT_GNU_IFUNC)
10206 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10207 to the .iplt entry. Instead, every non-call reference
10208 must use an R_ARM_IRELATIVE relocation to obtain the
10209 correct run-time address. */
10210 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10211 else
10212 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10213 if (globals->use_rel)
10214 relocate = TRUE;
10215 else
34e77a92 10216 outrel.r_addend += dynreloc_value;
252b5132 10217 }
f21f3fe0 10218
47beaa6a 10219 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10220
f21f3fe0 10221 /* If this reloc is against an external symbol, we do not want to
252b5132 10222 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10223 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10224 if (! relocate)
10225 return bfd_reloc_ok;
9a5aca8c 10226
f21f3fe0 10227 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10228 contents, rel->r_offset,
10229 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10230 }
10231 else switch (r_type)
10232 {
00a97672
RS		 10233 case R_ARM_ABS12:
10234 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10235
dfc5f959 10236 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10237 case R_ARM_CALL:
10238 case R_ARM_JUMP24:
8029a119 10239 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10240 case R_ARM_PLT32:
906e58ca 10241 {
906e58ca
NC		 10242 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10243
dfc5f959 10244 if (r_type == R_ARM_XPC25)
252b5132 10245 {
dfc5f959
NC		 10246 /* Check for Arm calling Arm function. */
10247 /* FIXME: Should we translate the instruction into a BL
10248 instruction instead ? */
35fc36a8 10249 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10250 _bfd_error_handler
90b6238f
AM		 10251 (_("\%pB: warning: %s BLX instruction targets"
10252 " %s function '%s'"),
10253 input_bfd, "ARM",
10254 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10255 }
155d87d7 10256 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10257 {
10258 /* Check for Arm calling Thumb function. */
35fc36a8 10259 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10260 {
f2a9dd69
DJ		 10261 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10262 output_bfd, input_section,
10263 hit_data, sym_sec, rel->r_offset,
10264 signed_addend, value,
10265 error_message))
10266 return bfd_reloc_ok;
10267 else
10268 return bfd_reloc_dangerous;
dfc5f959 10269 }
252b5132 10270 }
ba96a88f 10271
906e58ca 10272 /* Check if a stub has to be inserted because the
8029a119 10273 destination is too far or we are changing mode. */
155d87d7
CL		 10274 if ( r_type == R_ARM_CALL
10275 || r_type == R_ARM_JUMP24
10276 || r_type == R_ARM_PLT32)
906e58ca 10277 {
fe33d2fa
CL		 10278 enum elf32_arm_stub_type stub_type = arm_stub_none;
10279 struct elf32_arm_link_hash_entry *hash;
10280
10281 hash = (struct elf32_arm_link_hash_entry *) h;
10282 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10283 st_type, &branch_type,
10284 hash, value, sym_sec,
fe33d2fa 10285 input_bfd, sym_name);
5fa9e92f 10286
fe33d2fa 10287 if (stub_type != arm_stub_none)
906e58ca
NC		 10288 {
10289 /* The target is out of reach, so redirect the
10290 branch to the local stub for this function. */
906e58ca
NC		 10291 stub_entry = elf32_arm_get_stub_entry (input_section,
10292 sym_sec, h,
fe33d2fa
CL		 10293 rel, globals,
10294 stub_type);
9cd3e4e5
NC		 10295 {
10296 if (stub_entry != NULL)
10297 value = (stub_entry->stub_offset
10298 + stub_entry->stub_sec->output_offset
10299 + stub_entry->stub_sec->output_section->vma);
10300
10301 if (plt_offset != (bfd_vma) -1)
10302 *unresolved_reloc_p = FALSE;
10303 }
906e58ca 10304 }
fe33d2fa
CL		 10305 else
10306 {
10307 /* If the call goes through a PLT entry, make sure to
10308 check distance to the right destination address. */
34e77a92 10309 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10310 {
10311 value = (splt->output_section->vma
10312 + splt->output_offset
34e77a92 10313 + plt_offset);
fe33d2fa
CL		 10314 *unresolved_reloc_p = FALSE;
10315 /* The PLT entry is in ARM mode, regardless of the
10316 target function. */
35fc36a8 10317 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10318 }
10319 }
906e58ca
NC		 10320 }
10321
dea514f5
PB		 10322 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10323 where:
10324 S is the address of the symbol in the relocation.
10325 P is address of the instruction being relocated.
10326 A is the addend (extracted from the instruction) in bytes.
10327
10328 S is held in 'value'.
10329 P is the base address of the section containing the
10330 instruction plus the offset of the reloc into that
10331 section, ie:
10332 (input_section->output_section->vma +
10333 input_section->output_offset +
10334 rel->r_offset).
10335 A is the addend, converted into bytes, ie:
10336 (signed_addend * 4)
10337
10338 Note: None of these operations have knowledge of the pipeline
10339 size of the processor, thus it is up to the assembler to
10340 encode this information into the addend. */
10341 value -= (input_section->output_section->vma
10342 + input_section->output_offset);
10343 value -= rel->r_offset;
4e7fd91e
PB		 10344 if (globals->use_rel)
10345 value += (signed_addend << howto->size);
10346 else
10347 /* RELA addends do not have to be adjusted by howto->size. */
10348 value += signed_addend;
23080146 10349
dcb5e6e6
NC		 10350 signed_addend = value;
10351 signed_addend >>= howto->rightshift;
9a5aca8c 10352
5ab79981 10353 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10354 the next instruction unless a PLT entry will be created.
77b4f08f 10355 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10356 The jump to the next instruction is optimized as a NOP depending
10357 on the architecture. */
ffcb4889 10358 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10359 && plt_offset == (bfd_vma) -1)
77b4f08f 10360 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10361 {
cd1dac3d
DG		 10362 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10363
10364 if (arch_has_arm_nop (globals))
10365 value |= 0x0320f000;
10366 else
10367 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10368 }
10369 else
59f2c4e7 10370 {
9b485d32 10371 /* Perform a signed range check. */
dcb5e6e6 10372 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10373 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10374 return bfd_reloc_overflow;
9a5aca8c 10375
5ab79981 10376 addend = (value & 2);
39b41c9c 10377
5ab79981
PB		 10378 value = (signed_addend & howto->dst_mask)
10379 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10380
5ab79981
PB		 10381 if (r_type == R_ARM_CALL)
10382 {
155d87d7 10383 /* Set the H bit in the BLX instruction. */
35fc36a8 10384 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10385 {
10386 if (addend)
10387 value |= (1 << 24);
10388 else
10389 value &= ~(bfd_vma)(1 << 24);
10390 }
10391
5ab79981 10392 /* Select the correct instruction (BL or BLX). */
906e58ca 10393 /* Only if we are not handling a BL to a stub. In this
8029a119 10394 case, mode switching is performed by the stub. */
35fc36a8 10395 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10396 value |= (1 << 28);
63e1a0fc 10397 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10398 {
10399 value &= ~(bfd_vma)(1 << 28);
10400 value |= (1 << 24);
10401 }
39b41c9c
PB		 10402 }
10403 }
906e58ca 10404 }
252b5132 10405 break;
f21f3fe0 10406
252b5132
RH		 10407 case R_ARM_ABS32:
10408 value += addend;
35fc36a8 10409 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10410 value |= 1;
10411 break;
f21f3fe0 10412
bb224fc3
MS		 10413 case R_ARM_ABS32_NOI:
10414 value += addend;
10415 break;
10416
252b5132 10417 case R_ARM_REL32:
a8bc6c78 10418 value += addend;
35fc36a8 10419 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10420 value |= 1;
252b5132 10421 value -= (input_section->output_section->vma
62efb346 10422 + input_section->output_offset + rel->r_offset);
252b5132 10423 break;
eb043451 10424
bb224fc3
MS		 10425 case R_ARM_REL32_NOI:
10426 value += addend;
10427 value -= (input_section->output_section->vma
10428 + input_section->output_offset + rel->r_offset);
10429 break;
10430
eb043451
PB		 10431 case R_ARM_PREL31:
10432 value -= (input_section->output_section->vma
10433 + input_section->output_offset + rel->r_offset);
10434 value += signed_addend;
10435 if (! h || h->root.type != bfd_link_hash_undefweak)
10436 {
8029a119 10437 /* Check for overflow. */
eb043451
PB		 10438 if ((value ^ (value >> 1)) & (1 << 30))
10439 return bfd_reloc_overflow;
10440 }
10441 value &= 0x7fffffff;
10442 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10443 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10444 value |= 1;
10445 break;
252b5132 10446 }
f21f3fe0 10447
252b5132
RH		 10448 bfd_put_32 (input_bfd, value, hit_data);
10449 return bfd_reloc_ok;
10450
10451 case R_ARM_ABS8:
fd0fd00c
MJ		 10452 /* PR 16202: Refectch the addend using the correct size. */
10453 if (globals->use_rel)
10454 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10455 value += addend;
4e67d4ca
DG		 10456
10457 /* There is no way to tell whether the user intended to use a signed or
10458 unsigned addend. When checking for overflow we accept either,
10459 as specified by the AAELF. */
10460 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10461 return bfd_reloc_overflow;
10462
10463 bfd_put_8 (input_bfd, value, hit_data);
10464 return bfd_reloc_ok;
10465
10466 case R_ARM_ABS16:
fd0fd00c
MJ		 10467 /* PR 16202: Refectch the addend using the correct size. */
10468 if (globals->use_rel)
10469 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10470 value += addend;
10471
4e67d4ca
DG		 10472 /* See comment for R_ARM_ABS8. */
10473 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10474 return bfd_reloc_overflow;
10475
10476 bfd_put_16 (input_bfd, value, hit_data);
10477 return bfd_reloc_ok;
10478
252b5132 10479 case R_ARM_THM_ABS5:
9b485d32 10480 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10481 if (globals->use_rel)
10482 {
10483 /* Need to refetch addend. */
10484 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10485 /* ??? Need to determine shift amount from operand size. */
10486 addend >>= howto->rightshift;
10487 }
252b5132
RH		 10488 value += addend;
10489
10490 /* ??? Isn't value unsigned? */
10491 if ((long) value > 0x1f || (long) value < -0x10)
10492 return bfd_reloc_overflow;
10493
10494 /* ??? Value needs to be properly shifted into place first. */
10495 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10496 bfd_put_16 (input_bfd, value, hit_data);
10497 return bfd_reloc_ok;
10498
2cab6cc3
MS		 10499 case R_ARM_THM_ALU_PREL_11_0:
10500 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10501 {
10502 bfd_vma insn;
10503 bfd_signed_vma relocation;
10504
10505 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10506 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10507
99059e56
RM		 10508 if (globals->use_rel)
10509 {
10510 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10511 | ((insn & (1 << 26)) >> 15);
10512 if (insn & 0xf00000)
10513 signed_addend = -signed_addend;
10514 }
2cab6cc3
MS		 10515
10516 relocation = value + signed_addend;
79f08007 10517 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10518 + input_section->output_offset
10519 + rel->r_offset);
2cab6cc3 10520
8c65b54f
CS		 10521 /* PR 21523: Use an absolute value. The user of this reloc will
10522 have already selected an ADD or SUB insn appropriately. */
e652757b 10523 value = labs (relocation);
2cab6cc3 10524
99059e56
RM		 10525 if (value >= 0x1000)
10526 return bfd_reloc_overflow;
2cab6cc3 10527
e645cf40
AG		 10528 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10529 if (branch_type == ST_BRANCH_TO_THUMB)
10530 value |= 1;
10531
2cab6cc3 10532 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10533 | ((value & 0x700) << 4)
10534 | ((value & 0x800) << 15);
10535 if (relocation < 0)
10536 insn |= 0xa00000;
2cab6cc3
MS		 10537
10538 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10539 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10540
99059e56 10541 return bfd_reloc_ok;
2cab6cc3
MS		 10542 }
10543
e1ec24c6
NC		 10544 case R_ARM_THM_PC8:
10545 /* PR 10073: This reloc is not generated by the GNU toolchain,
10546 but it is supported for compatibility with third party libraries
10547 generated by other compilers, specifically the ARM/IAR. */
10548 {
10549 bfd_vma insn;
10550 bfd_signed_vma relocation;
10551
10552 insn = bfd_get_16 (input_bfd, hit_data);
10553
99059e56 10554 if (globals->use_rel)
79f08007 10555 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10556
10557 relocation = value + addend;
79f08007 10558 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10559 + input_section->output_offset
10560 + rel->r_offset);
e1ec24c6 10561
b6518b38 10562 value = relocation;
e1ec24c6
NC		 10563
10564 /* We do not check for overflow of this reloc. Although strictly
10565 speaking this is incorrect, it appears to be necessary in order
10566 to work with IAR generated relocs. Since GCC and GAS do not
10567 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10568 a problem for them. */
10569 value &= 0x3fc;
10570
10571 insn = (insn & 0xff00) | (value >> 2);
10572
10573 bfd_put_16 (input_bfd, insn, hit_data);
10574
99059e56 10575 return bfd_reloc_ok;
e1ec24c6
NC		 10576 }
10577
2cab6cc3
MS		 10578 case R_ARM_THM_PC12:
10579 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10580 {
10581 bfd_vma insn;
10582 bfd_signed_vma relocation;
10583
10584 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10585 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10586
99059e56
RM		 10587 if (globals->use_rel)
10588 {
10589 signed_addend = insn & 0xfff;
10590 if (!(insn & (1 << 23)))
10591 signed_addend = -signed_addend;
10592 }
2cab6cc3
MS		 10593
10594 relocation = value + signed_addend;
79f08007 10595 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10596 + input_section->output_offset
10597 + rel->r_offset);
2cab6cc3 10598
b6518b38 10599 value = relocation;
2cab6cc3 10600
99059e56
RM		 10601 if (value >= 0x1000)
10602 return bfd_reloc_overflow;
2cab6cc3
MS		 10603
10604 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10605 if (relocation >= 0)
10606 insn |= (1 << 23);
2cab6cc3
MS		 10607
10608 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10609 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10610
99059e56 10611 return bfd_reloc_ok;
2cab6cc3
MS		 10612 }
10613
dfc5f959 10614 case R_ARM_THM_XPC22:
c19d1205 10615 case R_ARM_THM_CALL:
bd97cb95 10616 case R_ARM_THM_JUMP24:
dfc5f959 10617 /* Thumb BL (branch long instruction). */
252b5132 10618 {
b34976b6 10619 bfd_vma relocation;
99059e56 10620 bfd_vma reloc_sign;
b34976b6
AM		 10621 bfd_boolean overflow = FALSE;
10622 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10623 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10624 bfd_signed_vma reloc_signed_max;
10625 bfd_signed_vma reloc_signed_min;
b34976b6 10626 bfd_vma check;
252b5132 10627 bfd_signed_vma signed_check;
e95de063 10628 int bitsize;
cd1dac3d 10629 const int thumb2 = using_thumb2 (globals);
5e866f5a 10630 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10631
5ab79981 10632 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10633 the next instruction unless a PLT entry will be created.
10634 The jump to the next instruction is optimized as a NOP.W for
10635 Thumb-2 enabled architectures. */
19540007 10636 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10637 && plt_offset == (bfd_vma) -1)
5ab79981 10638 {
60a019a0 10639 if (thumb2)
cd1dac3d
DG		 10640 {
10641 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10642 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10643 }
10644 else
10645 {
10646 bfd_put_16 (input_bfd, 0xe000, hit_data);
10647 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10648 }
5ab79981
PB		 10649 return bfd_reloc_ok;
10650 }
10651
e95de063 10652 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10653 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10654 if (globals->use_rel)
10655 {
99059e56
RM		 10656 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10657 bfd_vma upper = upper_insn & 0x3ff;
10658 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10659 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10660 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10661 bfd_vma i1 = j1 ^ s ? 0 : 1;
10662 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10663
99059e56
RM		 10664 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10665 /* Sign extend. */
10666 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10667
4e7fd91e
PB		 10668 signed_addend = addend;
10669 }
cb1afa5c 10670
dfc5f959
NC		 10671 if (r_type == R_ARM_THM_XPC22)
10672 {
10673 /* Check for Thumb to Thumb call. */
10674 /* FIXME: Should we translate the instruction into a BL
10675 instruction instead ? */
35fc36a8 10676 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10677 _bfd_error_handler
90b6238f
AM		 10678 (_("%pB: warning: %s BLX instruction targets"
10679 " %s function '%s'"),
10680 input_bfd, "Thumb",
10681 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 10682 }
10683 else
252b5132 10684 {
dfc5f959
NC		 10685 /* If it is not a call to Thumb, assume call to Arm.
10686 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10687 function call at all, but rather a long jump. Calls through
10688 the PLT do not require stubs. */
34e77a92 10689 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10690 {
bd97cb95 10691 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10692 {
10693 /* Convert BL to BLX. */
10694 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10695 }
155d87d7
CL		 10696 else if (( r_type != R_ARM_THM_CALL)
10697 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10698 {
10699 if (elf32_thumb_to_arm_stub
10700 (info, sym_name, input_bfd, output_bfd, input_section,
10701 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10702 error_message))
10703 return bfd_reloc_ok;
10704 else
10705 return bfd_reloc_dangerous;
10706 }
da5938a2 10707 }
35fc36a8
RS		 10708 else if (branch_type == ST_BRANCH_TO_THUMB
10709 && globals->use_blx
bd97cb95 10710 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10711 {
10712 /* Make sure this is a BL. */
10713 lower_insn |= 0x1800;
10714 }
252b5132 10715 }
f21f3fe0 10716
fe33d2fa 10717 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10718 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10719 {
10720 /* Check if a stub has to be inserted because the destination
8029a119 10721 is too far. */
fe33d2fa
CL		 10722 struct elf32_arm_stub_hash_entry *stub_entry;
10723 struct elf32_arm_link_hash_entry *hash;
10724
10725 hash = (struct elf32_arm_link_hash_entry *) h;
10726
10727 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10728 st_type, &branch_type,
10729 hash, value, sym_sec,
fe33d2fa
CL		 10730 input_bfd, sym_name);
10731
10732 if (stub_type != arm_stub_none)
906e58ca
NC		 10733 {
10734 /* The target is out of reach or we are changing modes, so
10735 redirect the branch to the local stub for this
10736 function. */
10737 stub_entry = elf32_arm_get_stub_entry (input_section,
10738 sym_sec, h,
fe33d2fa
CL		 10739 rel, globals,
10740 stub_type);
906e58ca 10741 if (stub_entry != NULL)
9cd3e4e5
NC		 10742 {
10743 value = (stub_entry->stub_offset
10744 + stub_entry->stub_sec->output_offset
10745 + stub_entry->stub_sec->output_section->vma);
10746
10747 if (plt_offset != (bfd_vma) -1)
10748 *unresolved_reloc_p = FALSE;
10749 }
906e58ca 10750
f4ac8484 10751 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10752 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10753 {
10754 if ((stub_entry
10755 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10756 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10757 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10758 }
906e58ca
NC		 10759 }
10760 }
10761
fe33d2fa 10762 /* Handle calls via the PLT. */
34e77a92 10763 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10764 {
10765 value = (splt->output_section->vma
10766 + splt->output_offset
34e77a92 10767 + plt_offset);
fe33d2fa 10768
eed94f8f
NC		 10769 if (globals->use_blx
10770 && r_type == R_ARM_THM_CALL
10771 && ! using_thumb_only (globals))
fe33d2fa
CL		 10772 {
10773 /* If the Thumb BLX instruction is available, convert
10774 the BL to a BLX instruction to call the ARM-mode
10775 PLT entry. */
10776 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10777 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10778 }
10779 else
10780 {
eed94f8f
NC		 10781 if (! using_thumb_only (globals))
10782 /* Target the Thumb stub before the ARM PLT entry. */
10783 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10784 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10785 }
10786 *unresolved_reloc_p = FALSE;
10787 }
10788
ba96a88f 10789 relocation = value + signed_addend;
f21f3fe0 10790
252b5132 10791 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10792 + input_section->output_offset
10793 + rel->r_offset);
9a5aca8c 10794
252b5132
RH		 10795 check = relocation >> howto->rightshift;
10796
10797 /* If this is a signed value, the rightshift just dropped
10798 leading 1 bits (assuming twos complement). */
10799 if ((bfd_signed_vma) relocation >= 0)
10800 signed_check = check;
10801 else
10802 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10803
e95de063
MS		 10804 /* Calculate the permissable maximum and minimum values for
10805 this relocation according to whether we're relocating for
10806 Thumb-2 or not. */
10807 bitsize = howto->bitsize;
5e866f5a 10808 if (!thumb2_bl)
e95de063 10809 bitsize -= 2;
f6ebfac0 10810 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10811 reloc_signed_min = ~reloc_signed_max;
10812
252b5132 10813 /* Assumes two's complement. */
ba96a88f 10814 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10815 overflow = TRUE;
252b5132 10816
bd97cb95 10817 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10818 /* For a BLX instruction, make sure that the relocation is rounded up
10819 to a word boundary. This follows the semantics of the instruction
10820 which specifies that bit 1 of the target address will come from bit
10821 1 of the base address. */
10822 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10823
e95de063
MS		 10824 /* Put RELOCATION back into the insn. Assumes two's complement.
10825 We use the Thumb-2 encoding, which is safe even if dealing with
10826 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10827 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10828 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10829 | ((relocation >> 12) & 0x3ff)
10830 | (reloc_sign << 10);
906e58ca 10831 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10832 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10833 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10834 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10835
252b5132
RH		 10836 /* Put the relocated value back in the object file: */
10837 bfd_put_16 (input_bfd, upper_insn, hit_data);
10838 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10839
10840 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10841 }
10842 break;
10843
c19d1205
ZW		 10844 case R_ARM_THM_JUMP19:
10845 /* Thumb32 conditional branch instruction. */
10846 {
10847 bfd_vma relocation;
10848 bfd_boolean overflow = FALSE;
10849 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10850 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10851 bfd_signed_vma reloc_signed_max = 0xffffe;
10852 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10853 bfd_signed_vma signed_check;
07d6d2b8 10854 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 10855 struct elf32_arm_stub_hash_entry *stub_entry;
10856 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10857
10858 /* Need to refetch the addend, reconstruct the top three bits,
10859 and squish the two 11 bit pieces together. */
10860 if (globals->use_rel)
10861 {
10862 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10863 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10864 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10865 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10866 bfd_vma lower = (lower_insn & 0x07ff);
10867
a00a1f35
MS		 10868 upper |= J1 << 6;
10869 upper |= J2 << 7;
10870 upper |= (!S) << 8;
c19d1205
ZW		 10871 upper -= 0x0100; /* Sign extend. */
10872
10873 addend = (upper << 12) | (lower << 1);
10874 signed_addend = addend;
10875 }
10876
bd97cb95 10877 /* Handle calls via the PLT. */
34e77a92 10878 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10879 {
10880 value = (splt->output_section->vma
10881 + splt->output_offset
34e77a92 10882 + plt_offset);
bd97cb95
DJ		 10883 /* Target the Thumb stub before the ARM PLT entry. */
10884 value -= PLT_THUMB_STUB_SIZE;
10885 *unresolved_reloc_p = FALSE;
10886 }
10887
c5423981
TG		 10888 hash = (struct elf32_arm_link_hash_entry *)h;
10889
10890 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 10891 st_type, &branch_type,
10892 hash, value, sym_sec,
10893 input_bfd, sym_name);
c5423981
TG		 10894 if (stub_type != arm_stub_none)
10895 {
10896 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 10897 sym_sec, h,
10898 rel, globals,
10899 stub_type);
c5423981
TG		 10900 if (stub_entry != NULL)
10901 {
07d6d2b8
AM		 10902 value = (stub_entry->stub_offset
10903 + stub_entry->stub_sec->output_offset
10904 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 10905 }
10906 }
c19d1205 10907
99059e56 10908 relocation = value + signed_addend;
c19d1205
ZW		 10909 relocation -= (input_section->output_section->vma
10910 + input_section->output_offset
10911 + rel->r_offset);
a00a1f35 10912 signed_check = (bfd_signed_vma) relocation;
c19d1205 10913
c19d1205
ZW		 10914 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10915 overflow = TRUE;
10916
10917 /* Put RELOCATION back into the insn. */
10918 {
10919 bfd_vma S = (relocation & 0x00100000) >> 20;
10920 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10921 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10922 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10923 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10924
a00a1f35 10925 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10926 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10927 }
10928
10929 /* Put the relocated value back in the object file: */
10930 bfd_put_16 (input_bfd, upper_insn, hit_data);
10931 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10932
10933 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10934 }
10935
10936 case R_ARM_THM_JUMP11:
10937 case R_ARM_THM_JUMP8:
10938 case R_ARM_THM_JUMP6:
51c5503b
NC		 10939 /* Thumb B (branch) instruction). */
10940 {
6cf9e9fe 10941 bfd_signed_vma relocation;
51c5503b
NC		 10942 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10943 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10944 bfd_signed_vma signed_check;
10945
c19d1205
ZW		 10946 /* CZB cannot jump backward. */
10947 if (r_type == R_ARM_THM_JUMP6)
10948 reloc_signed_min = 0;
10949
4e7fd91e 10950 if (globals->use_rel)
6cf9e9fe 10951 {
4e7fd91e
PB		 10952 /* Need to refetch addend. */
10953 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10954 if (addend & ((howto->src_mask + 1) >> 1))
10955 {
10956 signed_addend = -1;
10957 signed_addend &= ~ howto->src_mask;
10958 signed_addend |= addend;
10959 }
10960 else
10961 signed_addend = addend;
10962 /* The value in the insn has been right shifted. We need to
10963 undo this, so that we can perform the address calculation
10964 in terms of bytes. */
10965 signed_addend <<= howto->rightshift;
6cf9e9fe 10966 }
6cf9e9fe 10967 relocation = value + signed_addend;
51c5503b
NC		 10968
10969 relocation -= (input_section->output_section->vma
10970 + input_section->output_offset
10971 + rel->r_offset);
10972
6cf9e9fe
NC		 10973 relocation >>= howto->rightshift;
10974 signed_check = relocation;
c19d1205
ZW		 10975
10976 if (r_type == R_ARM_THM_JUMP6)
10977 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10978 else
10979 relocation &= howto->dst_mask;
51c5503b 10980 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10981
51c5503b
NC		 10982 bfd_put_16 (input_bfd, relocation, hit_data);
10983
10984 /* Assumes two's complement. */
10985 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10986 return bfd_reloc_overflow;
10987
10988 return bfd_reloc_ok;
10989 }
cedb70c5 10990
8375c36b
PB		 10991 case R_ARM_ALU_PCREL7_0:
10992 case R_ARM_ALU_PCREL15_8:
10993 case R_ARM_ALU_PCREL23_15:
10994 {
10995 bfd_vma insn;
10996 bfd_vma relocation;
10997
10998 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10999 if (globals->use_rel)
11000 {
11001 /* Extract the addend. */
11002 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11003 signed_addend = addend;
11004 }
8375c36b
PB		 11005 relocation = value + signed_addend;
11006
11007 relocation -= (input_section->output_section->vma
11008 + input_section->output_offset
11009 + rel->r_offset);
11010 insn = (insn & ~0xfff)
11011 | ((howto->bitpos << 7) & 0xf00)
11012 | ((relocation >> howto->bitpos) & 0xff);
11013 bfd_put_32 (input_bfd, value, hit_data);
11014 }
11015 return bfd_reloc_ok;
11016
252b5132
RH		 11017 case R_ARM_GNU_VTINHERIT:
11018 case R_ARM_GNU_VTENTRY:
11019 return bfd_reloc_ok;
11020
c19d1205 11021 case R_ARM_GOTOFF32:
252b5132 11022 /* Relocation is relative to the start of the
99059e56 11023 global offset table. */
252b5132
RH		 11024
11025 BFD_ASSERT (sgot != NULL);
11026 if (sgot == NULL)
99059e56 11027 return bfd_reloc_notsupported;
9a5aca8c 11028
cedb70c5 11029 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11030 address by one, so that attempts to call the function pointer will
11031 correctly interpret it as Thumb code. */
35fc36a8 11032 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11033 value += 1;
11034
252b5132 11035 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11036 calculation. We always want the start of .got. If we
11037 define _GLOBAL_OFFSET_TABLE in a different way, as is
11038 permitted by the ABI, we might have to change this
11039 calculation. */
252b5132 11040 value -= sgot->output_section->vma;
f21f3fe0 11041 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11042 contents, rel->r_offset, value,
00a97672 11043 rel->r_addend);
252b5132
RH		 11044
11045 case R_ARM_GOTPC:
a7c10850 11046 /* Use global offset table as symbol value. */
252b5132 11047 BFD_ASSERT (sgot != NULL);
f21f3fe0 11048
252b5132 11049 if (sgot == NULL)
99059e56 11050 return bfd_reloc_notsupported;
252b5132 11051
0945cdfd 11052 *unresolved_reloc_p = FALSE;
252b5132 11053 value = sgot->output_section->vma;
f21f3fe0 11054 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11055 contents, rel->r_offset, value,
00a97672 11056 rel->r_addend);
f21f3fe0 11057
252b5132 11058 case R_ARM_GOT32:
eb043451 11059 case R_ARM_GOT_PREL:
252b5132 11060 /* Relocation is to the entry for this symbol in the
99059e56 11061 global offset table. */
252b5132
RH		 11062 if (sgot == NULL)
11063 return bfd_reloc_notsupported;
f21f3fe0 11064
34e77a92
RS		 11065 if (dynreloc_st_type == STT_GNU_IFUNC
11066 && plt_offset != (bfd_vma) -1
11067 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11068 {
11069 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11070 symbol, and the relocation resolves directly to the runtime
11071 target rather than to the .iplt entry. This means that any
11072 .got entry would be the same value as the .igot.plt entry,
11073 so there's no point creating both. */
11074 sgot = globals->root.igotplt;
11075 value = sgot->output_offset + gotplt_offset;
11076 }
11077 else if (h != NULL)
252b5132
RH		 11078 {
11079 bfd_vma off;
f21f3fe0 11080
252b5132
RH		 11081 off = h->got.offset;
11082 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11083 if ((off & 1) != 0)
252b5132 11084 {
b436d854
RS		 11085 /* We have already processsed one GOT relocation against
11086 this symbol. */
11087 off &= ~1;
11088 if (globals->root.dynamic_sections_created
11089 && !SYMBOL_REFERENCES_LOCAL (info, h))
11090 *unresolved_reloc_p = FALSE;
11091 }
11092 else
11093 {
11094 Elf_Internal_Rela outrel;
11095
6f820c85 11096 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11097 {
11098 /* If the symbol doesn't resolve locally in a static
11099 object, we have an undefined reference. If the
11100 symbol doesn't resolve locally in a dynamic object,
11101 it should be resolved by the dynamic linker. */
11102 if (globals->root.dynamic_sections_created)
11103 {
11104 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11105 *unresolved_reloc_p = FALSE;
11106 }
11107 else
11108 outrel.r_info = 0;
11109 outrel.r_addend = 0;
11110 }
252b5132
RH		 11111 else
11112 {
34e77a92 11113 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11114 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11115 else if (bfd_link_pic (info)
11116 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11117 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11118 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11119 else
11120 outrel.r_info = 0;
34e77a92 11121 outrel.r_addend = dynreloc_value;
b436d854 11122 }
ee29b9fb 11123
b436d854
RS		 11124 /* The GOT entry is initialized to zero by default.
11125 See if we should install a different value. */
11126 if (outrel.r_addend != 0
11127 && (outrel.r_info == 0 || globals->use_rel))
11128 {
11129 bfd_put_32 (output_bfd, outrel.r_addend,
11130 sgot->contents + off);
11131 outrel.r_addend = 0;
252b5132 11132 }
f21f3fe0 11133
b436d854
RS		 11134 if (outrel.r_info != 0)
11135 {
11136 outrel.r_offset = (sgot->output_section->vma
11137 + sgot->output_offset
11138 + off);
11139 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11140 }
11141 h->got.offset |= 1;
11142 }
252b5132
RH		 11143 value = sgot->output_offset + off;
11144 }
11145 else
11146 {
11147 bfd_vma off;
f21f3fe0 11148
5025eb7c
AO		 11149 BFD_ASSERT (local_got_offsets != NULL
11150 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11151
252b5132 11152 off = local_got_offsets[r_symndx];
f21f3fe0 11153
252b5132
RH		 11154 /* The offset must always be a multiple of 4. We use the
11155 least significant bit to record whether we have already
9b485d32 11156 generated the necessary reloc. */
252b5132
RH		 11157 if ((off & 1) != 0)
11158 off &= ~1;
11159 else
11160 {
00a97672 11161 if (globals->use_rel)
34e77a92 11162 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11163
0e1862bb 11164 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11165 {
947216bf 11166 Elf_Internal_Rela outrel;
f21f3fe0 11167
34e77a92 11168 outrel.r_addend = addend + dynreloc_value;
252b5132 11169 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11170 + sgot->output_offset
252b5132 11171 + off);
34e77a92 11172 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11173 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11174 else
11175 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11176 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11177 }
f21f3fe0 11178
252b5132
RH		 11179 local_got_offsets[r_symndx] |= 1;
11180 }
f21f3fe0 11181
252b5132
RH		 11182 value = sgot->output_offset + off;
11183 }
eb043451
PB		 11184 if (r_type != R_ARM_GOT32)
11185 value += sgot->output_section->vma;
9a5aca8c 11186
f21f3fe0 11187 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11188 contents, rel->r_offset, value,
00a97672 11189 rel->r_addend);
f21f3fe0 11190
ba93b8ac
DJ		 11191 case R_ARM_TLS_LDO32:
11192 value = value - dtpoff_base (info);
11193
11194 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11195 contents, rel->r_offset, value,
11196 rel->r_addend);
ba93b8ac
DJ		 11197
11198 case R_ARM_TLS_LDM32:
11199 {
11200 bfd_vma off;
11201
362d30a1 11202 if (sgot == NULL)
ba93b8ac
DJ		 11203 abort ();
11204
11205 off = globals->tls_ldm_got.offset;
11206
11207 if ((off & 1) != 0)
11208 off &= ~1;
11209 else
11210 {
11211 /* If we don't know the module number, create a relocation
11212 for it. */
0e1862bb 11213 if (bfd_link_pic (info))
ba93b8ac
DJ		 11214 {
11215 Elf_Internal_Rela outrel;
ba93b8ac 11216
362d30a1 11217 if (srelgot == NULL)
ba93b8ac
DJ		 11218 abort ();
11219
00a97672 11220 outrel.r_addend = 0;
362d30a1
RS		 11221 outrel.r_offset = (sgot->output_section->vma
11222 + sgot->output_offset + off);
ba93b8ac
DJ		 11223 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11224
00a97672
RS		 11225 if (globals->use_rel)
11226 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11227 sgot->contents + off);
ba93b8ac 11228
47beaa6a 11229 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11230 }
11231 else
362d30a1 11232 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11233
11234 globals->tls_ldm_got.offset |= 1;
11235 }
11236
362d30a1 11237 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11238 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11239
11240 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11241 contents, rel->r_offset, value,
00a97672 11242 rel->r_addend);
ba93b8ac
DJ		 11243 }
11244
0855e32b
NS		 11245 case R_ARM_TLS_CALL:
11246 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11247 case R_ARM_TLS_GD32:
11248 case R_ARM_TLS_IE32:
0855e32b
NS		 11249 case R_ARM_TLS_GOTDESC:
11250 case R_ARM_TLS_DESCSEQ:
11251 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11252 {
0855e32b
NS		 11253 bfd_vma off, offplt;
11254 int indx = 0;
ba93b8ac
DJ		 11255 char tls_type;
11256
0855e32b 11257 BFD_ASSERT (sgot != NULL);
ba93b8ac 11258
ba93b8ac
DJ		 11259 if (h != NULL)
11260 {
11261 bfd_boolean dyn;
11262 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11263 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11264 bfd_link_pic (info),
11265 h)
11266 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11267 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11268 {
11269 *unresolved_reloc_p = FALSE;
11270 indx = h->dynindx;
11271 }
11272 off = h->got.offset;
0855e32b 11273 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11274 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11275 }
11276 else
11277 {
0855e32b 11278 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11279 off = local_got_offsets[r_symndx];
0855e32b 11280 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11281 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11282 }
11283
0855e32b 11284 /* Linker relaxations happens from one of the
b38cadfb 11285 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11286 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11287 tls_type = GOT_TLS_IE;
0855e32b
NS		 11288
11289 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11290
11291 if ((off & 1) != 0)
11292 off &= ~1;
11293 else
11294 {
11295 bfd_boolean need_relocs = FALSE;
11296 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11297 int cur_off = off;
11298
11299 /* The GOT entries have not been initialized yet. Do it
11300 now, and emit any relocations. If both an IE GOT and a
11301 GD GOT are necessary, we emit the GD first. */
11302
0e1862bb 11303 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11304 && (h == NULL
95b03e4a
L		 11305 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11306 && !resolved_to_zero)
ba93b8ac
DJ		 11307 || h->root.type != bfd_link_hash_undefweak))
11308 {
11309 need_relocs = TRUE;
0855e32b 11310 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11311 }
11312
0855e32b
NS		 11313 if (tls_type & GOT_TLS_GDESC)
11314 {
47beaa6a
RS		 11315 bfd_byte *loc;
11316
0855e32b
NS		 11317 /* We should have relaxed, unless this is an undefined
11318 weak symbol. */
11319 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11320 || bfd_link_pic (info));
0855e32b 11321 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11322 <= globals->root.sgotplt->size);
0855e32b
NS		 11323
11324 outrel.r_addend = 0;
11325 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11326 + globals->root.sgotplt->output_offset
11327 + offplt
11328 + globals->sgotplt_jump_table_size);
b38cadfb 11329
0855e32b
NS		 11330 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11331 sreloc = globals->root.srelplt;
11332 loc = sreloc->contents;
11333 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11334 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11335 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11336
11337 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11338
11339 /* For globals, the first word in the relocation gets
11340 the relocation index and the top bit set, or zero,
11341 if we're binding now. For locals, it gets the
11342 symbol's offset in the tls section. */
99059e56 11343 bfd_put_32 (output_bfd,
0855e32b
NS		 11344 !h ? value - elf_hash_table (info)->tls_sec->vma
11345 : info->flags & DF_BIND_NOW ? 0
11346 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11347 globals->root.sgotplt->contents + offplt
11348 + globals->sgotplt_jump_table_size);
11349
0855e32b 11350 /* Second word in the relocation is always zero. */
99059e56 11351 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11352 globals->root.sgotplt->contents + offplt
11353 + globals->sgotplt_jump_table_size + 4);
0855e32b 11354 }
ba93b8ac
DJ		 11355 if (tls_type & GOT_TLS_GD)
11356 {
11357 if (need_relocs)
11358 {
00a97672 11359 outrel.r_addend = 0;
362d30a1
RS		 11360 outrel.r_offset = (sgot->output_section->vma
11361 + sgot->output_offset
00a97672 11362 + cur_off);
ba93b8ac 11363 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11364
00a97672
RS		 11365 if (globals->use_rel)
11366 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11367 sgot->contents + cur_off);
00a97672 11368
47beaa6a 11369 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11370
11371 if (indx == 0)
11372 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11373 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11374 else
11375 {
00a97672 11376 outrel.r_addend = 0;
ba93b8ac
DJ		 11377 outrel.r_info = ELF32_R_INFO (indx,
11378 R_ARM_TLS_DTPOFF32);
11379 outrel.r_offset += 4;
00a97672
RS		 11380
11381 if (globals->use_rel)
11382 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11383 sgot->contents + cur_off + 4);
00a97672 11384
47beaa6a
RS		 11385 elf32_arm_add_dynreloc (output_bfd, info,
11386 srelgot, &outrel);
ba93b8ac
DJ		 11387 }
11388 }
11389 else
11390 {
11391 /* If we are not emitting relocations for a
11392 general dynamic reference, then we must be in a
11393 static link or an executable link with the
11394 symbol binding locally. Mark it as belonging
11395 to module 1, the executable. */
11396 bfd_put_32 (output_bfd, 1,
362d30a1 11397 sgot->contents + cur_off);
ba93b8ac 11398 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11399 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11400 }
11401
11402 cur_off += 8;
11403 }
11404
11405 if (tls_type & GOT_TLS_IE)
11406 {
11407 if (need_relocs)
11408 {
00a97672
RS		 11409 if (indx == 0)
11410 outrel.r_addend = value - dtpoff_base (info);
11411 else
11412 outrel.r_addend = 0;
362d30a1
RS		 11413 outrel.r_offset = (sgot->output_section->vma
11414 + sgot->output_offset
ba93b8ac
DJ		 11415 + cur_off);
11416 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11417
00a97672
RS		 11418 if (globals->use_rel)
11419 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11420 sgot->contents + cur_off);
ba93b8ac 11421
47beaa6a 11422 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11423 }
11424 else
11425 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11426 sgot->contents + cur_off);
ba93b8ac
DJ		 11427 cur_off += 4;
11428 }
11429
11430 if (h != NULL)
11431 h->got.offset |= 1;
11432 else
11433 local_got_offsets[r_symndx] |= 1;
11434 }
11435
11436 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11437 off += 8;
0855e32b
NS		 11438 else if (tls_type & GOT_TLS_GDESC)
11439 off = offplt;
11440
11441 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11442 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11443 {
11444 bfd_signed_vma offset;
12352d3f
PB		 11445 /* TLS stubs are arm mode. The original symbol is a
11446 data object, so branch_type is bogus. */
11447 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11448 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11449 = arm_type_of_stub (info, input_section, rel,
11450 st_type, &branch_type,
0855e32b
NS		 11451 (struct elf32_arm_link_hash_entry *)h,
11452 globals->tls_trampoline, globals->root.splt,
11453 input_bfd, sym_name);
11454
11455 if (stub_type != arm_stub_none)
11456 {
11457 struct elf32_arm_stub_hash_entry *stub_entry
11458 = elf32_arm_get_stub_entry
11459 (input_section, globals->root.splt, 0, rel,
11460 globals, stub_type);
11461 offset = (stub_entry->stub_offset
11462 + stub_entry->stub_sec->output_offset
11463 + stub_entry->stub_sec->output_section->vma);
11464 }
11465 else
11466 offset = (globals->root.splt->output_section->vma
11467 + globals->root.splt->output_offset
11468 + globals->tls_trampoline);
11469
11470 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11471 {
11472 unsigned long inst;
b38cadfb
NC		 11473
11474 offset -= (input_section->output_section->vma
11475 + input_section->output_offset
11476 + rel->r_offset + 8);
0855e32b
NS		 11477
11478 inst = offset >> 2;
11479 inst &= 0x00ffffff;
11480 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11481 }
11482 else
11483 {
11484 /* Thumb blx encodes the offset in a complicated
11485 fashion. */
11486 unsigned upper_insn, lower_insn;
11487 unsigned neg;
11488
b38cadfb
NC		 11489 offset -= (input_section->output_section->vma
11490 + input_section->output_offset
0855e32b 11491 + rel->r_offset + 4);
b38cadfb 11492
12352d3f
PB		 11493 if (stub_type != arm_stub_none
11494 && arm_stub_is_thumb (stub_type))
11495 {
11496 lower_insn = 0xd000;
11497 }
11498 else
11499 {
11500 lower_insn = 0xc000;
6a631e86 11501 /* Round up the offset to a word boundary. */
12352d3f
PB		 11502 offset = (offset + 2) & ~2;
11503 }
11504
0855e32b
NS		 11505 neg = offset < 0;
11506 upper_insn = (0xf000
11507 | ((offset >> 12) & 0x3ff)
11508 | (neg << 10));
12352d3f 11509 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11510 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11511 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11512 bfd_put_16 (input_bfd, upper_insn, hit_data);
11513 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11514 return bfd_reloc_ok;
11515 }
11516 }
11517 /* These relocations needs special care, as besides the fact
11518 they point somewhere in .gotplt, the addend must be
11519 adjusted accordingly depending on the type of instruction
6a631e86 11520 we refer to. */
0855e32b
NS		 11521 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11522 {
11523 unsigned long data, insn;
11524 unsigned thumb;
b38cadfb 11525
0855e32b
NS		 11526 data = bfd_get_32 (input_bfd, hit_data);
11527 thumb = data & 1;
11528 data &= ~1u;
b38cadfb 11529
0855e32b
NS		 11530 if (thumb)
11531 {
11532 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11533 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11534 insn = (insn << 16)
11535 | bfd_get_16 (input_bfd,
11536 contents + rel->r_offset - data + 2);
11537 if ((insn & 0xf800c000) == 0xf000c000)
11538 /* bl/blx */
11539 value = -6;
11540 else if ((insn & 0xffffff00) == 0x4400)
11541 /* add */
11542 value = -5;
11543 else
11544 {
4eca0228 11545 _bfd_error_handler
695344c0 11546 /* xgettext:c-format */
2dcf00ce 11547 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11548 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11549 "referenced by TLS_GOTDESC"),
11550 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11551 "Thumb", insn);
0855e32b
NS		 11552 return bfd_reloc_notsupported;
11553 }
11554 }
11555 else
11556 {
11557 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11558
11559 switch (insn >> 24)
11560 {
11561 case 0xeb: /* bl */
11562 case 0xfa: /* blx */
11563 value = -4;
11564 break;
11565
11566 case 0xe0: /* add */
11567 value = -8;
11568 break;
b38cadfb 11569
0855e32b 11570 default:
4eca0228 11571 _bfd_error_handler
695344c0 11572 /* xgettext:c-format */
2dcf00ce 11573 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11574 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11575 "referenced by TLS_GOTDESC"),
11576 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11577 "ARM", insn);
0855e32b
NS		 11578 return bfd_reloc_notsupported;
11579 }
11580 }
b38cadfb 11581
0855e32b
NS		 11582 value += ((globals->root.sgotplt->output_section->vma
11583 + globals->root.sgotplt->output_offset + off)
11584 - (input_section->output_section->vma
11585 + input_section->output_offset
11586 + rel->r_offset)
11587 + globals->sgotplt_jump_table_size);
11588 }
11589 else
11590 value = ((globals->root.sgot->output_section->vma
11591 + globals->root.sgot->output_offset + off)
11592 - (input_section->output_section->vma
11593 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11594
11595 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11596 contents, rel->r_offset, value,
00a97672 11597 rel->r_addend);
ba93b8ac
DJ		 11598 }
11599
11600 case R_ARM_TLS_LE32:
3cbc1e5e 11601 if (bfd_link_dll (info))
ba93b8ac 11602 {
4eca0228 11603 _bfd_error_handler
695344c0 11604 /* xgettext:c-format */
2dcf00ce
AM		 11605 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
11606 "in shared object"),
11607 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 11608 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11609 }
11610 else
11611 value = tpoff (info, value);
906e58ca 11612
ba93b8ac 11613 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11614 contents, rel->r_offset, value,
11615 rel->r_addend);
ba93b8ac 11616
319850b4
JB		 11617 case R_ARM_V4BX:
11618 if (globals->fix_v4bx)
845b51d6
PB		 11619 {
11620 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11621
845b51d6
PB		 11622 /* Ensure that we have a BX instruction. */
11623 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11624
845b51d6
PB		 11625 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11626 {
11627 /* Branch to veneer. */
11628 bfd_vma glue_addr;
11629 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11630 glue_addr -= input_section->output_section->vma
11631 + input_section->output_offset
11632 + rel->r_offset + 8;
11633 insn = (insn & 0xf0000000) | 0x0a000000
11634 | ((glue_addr >> 2) & 0x00ffffff);
11635 }
11636 else
11637 {
11638 /* Preserve Rm (lowest four bits) and the condition code
11639 (highest four bits). Other bits encode MOV PC,Rm. */
11640 insn = (insn & 0xf000000f) | 0x01a0f000;
11641 }
319850b4 11642
845b51d6
PB		 11643 bfd_put_32 (input_bfd, insn, hit_data);
11644 }
319850b4
JB		 11645 return bfd_reloc_ok;
11646
b6895b4f
PB		 11647 case R_ARM_MOVW_ABS_NC:
11648 case R_ARM_MOVT_ABS:
11649 case R_ARM_MOVW_PREL_NC:
11650 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11651 /* Until we properly support segment-base-relative addressing then
11652 we assume the segment base to be zero, as for the group relocations.
11653 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11654 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11655 case R_ARM_MOVW_BREL_NC:
11656 case R_ARM_MOVW_BREL:
11657 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11658 {
11659 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11660
11661 if (globals->use_rel)
11662 {
11663 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11664 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11665 }
92f5d02b 11666
b6895b4f 11667 value += signed_addend;
b6895b4f
PB		 11668
11669 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11670 value -= (input_section->output_section->vma
11671 + input_section->output_offset + rel->r_offset);
11672
92f5d02b 11673 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11674 return bfd_reloc_overflow;
92f5d02b 11675
35fc36a8 11676 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11677 value |= 1;
11678
11679 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11680 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11681 value >>= 16;
11682
11683 insn &= 0xfff0f000;
11684 insn |= value & 0xfff;
11685 insn |= (value & 0xf000) << 4;
11686 bfd_put_32 (input_bfd, insn, hit_data);
11687 }
11688 return bfd_reloc_ok;
11689
11690 case R_ARM_THM_MOVW_ABS_NC:
11691 case R_ARM_THM_MOVT_ABS:
11692 case R_ARM_THM_MOVW_PREL_NC:
11693 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11694 /* Until we properly support segment-base-relative addressing then
11695 we assume the segment base to be zero, as for the above relocations.
11696 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11697 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11698 as R_ARM_THM_MOVT_ABS. */
11699 case R_ARM_THM_MOVW_BREL_NC:
11700 case R_ARM_THM_MOVW_BREL:
11701 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11702 {
11703 bfd_vma insn;
906e58ca 11704
b6895b4f
PB		 11705 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11706 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11707
11708 if (globals->use_rel)
11709 {
11710 addend = ((insn >> 4) & 0xf000)
11711 | ((insn >> 15) & 0x0800)
11712 | ((insn >> 4) & 0x0700)
07d6d2b8 11713 | (insn & 0x00ff);
39623e12 11714 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11715 }
92f5d02b 11716
b6895b4f 11717 value += signed_addend;
b6895b4f
PB		 11718
11719 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11720 value -= (input_section->output_section->vma
11721 + input_section->output_offset + rel->r_offset);
11722
92f5d02b 11723 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11724 return bfd_reloc_overflow;
92f5d02b 11725
35fc36a8 11726 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11727 value |= 1;
11728
11729 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11730 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11731 value >>= 16;
11732
11733 insn &= 0xfbf08f00;
11734 insn |= (value & 0xf000) << 4;
11735 insn |= (value & 0x0800) << 15;
11736 insn |= (value & 0x0700) << 4;
11737 insn |= (value & 0x00ff);
11738
11739 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11740 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11741 }
11742 return bfd_reloc_ok;
11743
4962c51a
MS		 11744 case R_ARM_ALU_PC_G0_NC:
11745 case R_ARM_ALU_PC_G1_NC:
11746 case R_ARM_ALU_PC_G0:
11747 case R_ARM_ALU_PC_G1:
11748 case R_ARM_ALU_PC_G2:
11749 case R_ARM_ALU_SB_G0_NC:
11750 case R_ARM_ALU_SB_G1_NC:
11751 case R_ARM_ALU_SB_G0:
11752 case R_ARM_ALU_SB_G1:
11753 case R_ARM_ALU_SB_G2:
11754 {
11755 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11756 bfd_vma pc = input_section->output_section->vma
4962c51a 11757 + input_section->output_offset + rel->r_offset;
31a91d61 11758 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11759 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11760 bfd_vma residual;
11761 bfd_vma g_n;
4962c51a 11762 bfd_signed_vma signed_value;
99059e56
RM		 11763 int group = 0;
11764
11765 /* Determine which group of bits to select. */
11766 switch (r_type)
11767 {
11768 case R_ARM_ALU_PC_G0_NC:
11769 case R_ARM_ALU_PC_G0:
11770 case R_ARM_ALU_SB_G0_NC:
11771 case R_ARM_ALU_SB_G0:
11772 group = 0;
11773 break;
11774
11775 case R_ARM_ALU_PC_G1_NC:
11776 case R_ARM_ALU_PC_G1:
11777 case R_ARM_ALU_SB_G1_NC:
11778 case R_ARM_ALU_SB_G1:
11779 group = 1;
11780 break;
11781
11782 case R_ARM_ALU_PC_G2:
11783 case R_ARM_ALU_SB_G2:
11784 group = 2;
11785 break;
11786
11787 default:
11788 abort ();
11789 }
11790
11791 /* If REL, extract the addend from the insn. If RELA, it will
11792 have already been fetched for us. */
4962c51a 11793 if (globals->use_rel)
99059e56
RM		 11794 {
11795 int negative;
11796 bfd_vma constant = insn & 0xff;
11797 bfd_vma rotation = (insn & 0xf00) >> 8;
11798
11799 if (rotation == 0)
11800 signed_addend = constant;
11801 else
11802 {
11803 /* Compensate for the fact that in the instruction, the
11804 rotation is stored in multiples of 2 bits. */
11805 rotation *= 2;
11806
11807 /* Rotate "constant" right by "rotation" bits. */
11808 signed_addend = (constant >> rotation) |
11809 (constant << (8 * sizeof (bfd_vma) - rotation));
11810 }
11811
11812 /* Determine if the instruction is an ADD or a SUB.
11813 (For REL, this determines the sign of the addend.) */
11814 negative = identify_add_or_sub (insn);
11815 if (negative == 0)
11816 {
4eca0228 11817 _bfd_error_handler
695344c0 11818 /* xgettext:c-format */
90b6238f 11819 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 11820 "are allowed for ALU group relocations"),
11821 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 11822 return bfd_reloc_overflow;
11823 }
11824
11825 signed_addend *= negative;
11826 }
4962c51a
MS		 11827
11828 /* Compute the value (X) to go in the place. */
99059e56
RM		 11829 if (r_type == R_ARM_ALU_PC_G0_NC
11830 || r_type == R_ARM_ALU_PC_G1_NC
11831 || r_type == R_ARM_ALU_PC_G0
11832 || r_type == R_ARM_ALU_PC_G1
11833 || r_type == R_ARM_ALU_PC_G2)
11834 /* PC relative. */
11835 signed_value = value - pc + signed_addend;
11836 else
11837 /* Section base relative. */
11838 signed_value = value - sb + signed_addend;
11839
11840 /* If the target symbol is a Thumb function, then set the
11841 Thumb bit in the address. */
35fc36a8 11842 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11843 signed_value |= 1;
11844
99059e56
RM		 11845 /* Calculate the value of the relevant G_n, in encoded
11846 constant-with-rotation format. */
b6518b38
NC		 11847 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11848 group, &residual);
99059e56
RM		 11849
11850 /* Check for overflow if required. */
11851 if ((r_type == R_ARM_ALU_PC_G0
11852 || r_type == R_ARM_ALU_PC_G1
11853 || r_type == R_ARM_ALU_PC_G2
11854 || r_type == R_ARM_ALU_SB_G0
11855 || r_type == R_ARM_ALU_SB_G1
11856 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11857 {
4eca0228 11858 _bfd_error_handler
695344c0 11859 /* xgettext:c-format */
90b6238f 11860 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 11861 "splitting %#" PRIx64 " for group relocation %s"),
11862 input_bfd, input_section, (uint64_t) rel->r_offset,
11863 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
11864 howto->name);
99059e56
RM		 11865 return bfd_reloc_overflow;
11866 }
11867
11868 /* Mask out the value and the ADD/SUB part of the opcode; take care
11869 not to destroy the S bit. */
11870 insn &= 0xff1ff000;
11871
11872 /* Set the opcode according to whether the value to go in the
11873 place is negative. */
11874 if (signed_value < 0)
11875 insn |= 1 << 22;
11876 else
11877 insn |= 1 << 23;
11878
11879 /* Encode the offset. */
11880 insn |= g_n;
4962c51a
MS		 11881
11882 bfd_put_32 (input_bfd, insn, hit_data);
11883 }
11884 return bfd_reloc_ok;
11885
11886 case R_ARM_LDR_PC_G0:
11887 case R_ARM_LDR_PC_G1:
11888 case R_ARM_LDR_PC_G2:
11889 case R_ARM_LDR_SB_G0:
11890 case R_ARM_LDR_SB_G1:
11891 case R_ARM_LDR_SB_G2:
11892 {
11893 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11894 bfd_vma pc = input_section->output_section->vma
4962c51a 11895 + input_section->output_offset + rel->r_offset;
31a91d61 11896 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11897 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11898 bfd_vma residual;
4962c51a 11899 bfd_signed_vma signed_value;
99059e56
RM		 11900 int group = 0;
11901
11902 /* Determine which groups of bits to calculate. */
11903 switch (r_type)
11904 {
11905 case R_ARM_LDR_PC_G0:
11906 case R_ARM_LDR_SB_G0:
11907 group = 0;
11908 break;
11909
11910 case R_ARM_LDR_PC_G1:
11911 case R_ARM_LDR_SB_G1:
11912 group = 1;
11913 break;
11914
11915 case R_ARM_LDR_PC_G2:
11916 case R_ARM_LDR_SB_G2:
11917 group = 2;
11918 break;
11919
11920 default:
11921 abort ();
11922 }
11923
11924 /* If REL, extract the addend from the insn. If RELA, it will
11925 have already been fetched for us. */
4962c51a 11926 if (globals->use_rel)
99059e56
RM		 11927 {
11928 int negative = (insn & (1 << 23)) ? 1 : -1;
11929 signed_addend = negative * (insn & 0xfff);
11930 }
4962c51a
MS		 11931
11932 /* Compute the value (X) to go in the place. */
99059e56
RM		 11933 if (r_type == R_ARM_LDR_PC_G0
11934 || r_type == R_ARM_LDR_PC_G1
11935 || r_type == R_ARM_LDR_PC_G2)
11936 /* PC relative. */
11937 signed_value = value - pc + signed_addend;
11938 else
11939 /* Section base relative. */
11940 signed_value = value - sb + signed_addend;
11941
11942 /* Calculate the value of the relevant G_{n-1} to obtain
11943 the residual at that stage. */
b6518b38
NC		 11944 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11945 group - 1, &residual);
99059e56
RM		 11946
11947 /* Check for overflow. */
11948 if (residual >= 0x1000)
11949 {
4eca0228 11950 _bfd_error_handler
695344c0 11951 /* xgettext:c-format */
90b6238f 11952 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 11953 "splitting %#" PRIx64 " for group relocation %s"),
11954 input_bfd, input_section, (uint64_t) rel->r_offset,
11955 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
11956 howto->name);
99059e56
RM		 11957 return bfd_reloc_overflow;
11958 }
11959
11960 /* Mask out the value and U bit. */
11961 insn &= 0xff7ff000;
11962
11963 /* Set the U bit if the value to go in the place is non-negative. */
11964 if (signed_value >= 0)
11965 insn |= 1 << 23;
11966
11967 /* Encode the offset. */
11968 insn |= residual;
4962c51a
MS		 11969
11970 bfd_put_32 (input_bfd, insn, hit_data);
11971 }
11972 return bfd_reloc_ok;
11973
11974 case R_ARM_LDRS_PC_G0:
11975 case R_ARM_LDRS_PC_G1:
11976 case R_ARM_LDRS_PC_G2:
11977 case R_ARM_LDRS_SB_G0:
11978 case R_ARM_LDRS_SB_G1:
11979 case R_ARM_LDRS_SB_G2:
11980 {
11981 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11982 bfd_vma pc = input_section->output_section->vma
4962c51a 11983 + input_section->output_offset + rel->r_offset;
31a91d61 11984 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11985 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11986 bfd_vma residual;
4962c51a 11987 bfd_signed_vma signed_value;
99059e56
RM		 11988 int group = 0;
11989
11990 /* Determine which groups of bits to calculate. */
11991 switch (r_type)
11992 {
11993 case R_ARM_LDRS_PC_G0:
11994 case R_ARM_LDRS_SB_G0:
11995 group = 0;
11996 break;
11997
11998 case R_ARM_LDRS_PC_G1:
11999 case R_ARM_LDRS_SB_G1:
12000 group = 1;
12001 break;
12002
12003 case R_ARM_LDRS_PC_G2:
12004 case R_ARM_LDRS_SB_G2:
12005 group = 2;
12006 break;
12007
12008 default:
12009 abort ();
12010 }
12011
12012 /* If REL, extract the addend from the insn. If RELA, it will
12013 have already been fetched for us. */
4962c51a 12014 if (globals->use_rel)
99059e56
RM		 12015 {
12016 int negative = (insn & (1 << 23)) ? 1 : -1;
12017 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12018 }
4962c51a
MS		 12019
12020 /* Compute the value (X) to go in the place. */
99059e56
RM		 12021 if (r_type == R_ARM_LDRS_PC_G0
12022 || r_type == R_ARM_LDRS_PC_G1
12023 || r_type == R_ARM_LDRS_PC_G2)
12024 /* PC relative. */
12025 signed_value = value - pc + signed_addend;
12026 else
12027 /* Section base relative. */
12028 signed_value = value - sb + signed_addend;
12029
12030 /* Calculate the value of the relevant G_{n-1} to obtain
12031 the residual at that stage. */
b6518b38
NC		 12032 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12033 group - 1, &residual);
99059e56
RM		 12034
12035 /* Check for overflow. */
12036 if (residual >= 0x100)
12037 {
4eca0228 12038 _bfd_error_handler
695344c0 12039 /* xgettext:c-format */
90b6238f 12040 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12041 "splitting %#" PRIx64 " for group relocation %s"),
12042 input_bfd, input_section, (uint64_t) rel->r_offset,
12043 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12044 howto->name);
99059e56
RM		 12045 return bfd_reloc_overflow;
12046 }
12047
12048 /* Mask out the value and U bit. */
12049 insn &= 0xff7ff0f0;
12050
12051 /* Set the U bit if the value to go in the place is non-negative. */
12052 if (signed_value >= 0)
12053 insn |= 1 << 23;
12054
12055 /* Encode the offset. */
12056 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12057
12058 bfd_put_32 (input_bfd, insn, hit_data);
12059 }
12060 return bfd_reloc_ok;
12061
12062 case R_ARM_LDC_PC_G0:
12063 case R_ARM_LDC_PC_G1:
12064 case R_ARM_LDC_PC_G2:
12065 case R_ARM_LDC_SB_G0:
12066 case R_ARM_LDC_SB_G1:
12067 case R_ARM_LDC_SB_G2:
12068 {
12069 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12070 bfd_vma pc = input_section->output_section->vma
4962c51a 12071 + input_section->output_offset + rel->r_offset;
31a91d61 12072 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12073 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12074 bfd_vma residual;
4962c51a 12075 bfd_signed_vma signed_value;
99059e56
RM		 12076 int group = 0;
12077
12078 /* Determine which groups of bits to calculate. */
12079 switch (r_type)
12080 {
12081 case R_ARM_LDC_PC_G0:
12082 case R_ARM_LDC_SB_G0:
12083 group = 0;
12084 break;
12085
12086 case R_ARM_LDC_PC_G1:
12087 case R_ARM_LDC_SB_G1:
12088 group = 1;
12089 break;
12090
12091 case R_ARM_LDC_PC_G2:
12092 case R_ARM_LDC_SB_G2:
12093 group = 2;
12094 break;
12095
12096 default:
12097 abort ();
12098 }
12099
12100 /* If REL, extract the addend from the insn. If RELA, it will
12101 have already been fetched for us. */
4962c51a 12102 if (globals->use_rel)
99059e56
RM		 12103 {
12104 int negative = (insn & (1 << 23)) ? 1 : -1;
12105 signed_addend = negative * ((insn & 0xff) << 2);
12106 }
4962c51a
MS		 12107
12108 /* Compute the value (X) to go in the place. */
99059e56
RM		 12109 if (r_type == R_ARM_LDC_PC_G0
12110 || r_type == R_ARM_LDC_PC_G1
12111 || r_type == R_ARM_LDC_PC_G2)
12112 /* PC relative. */
12113 signed_value = value - pc + signed_addend;
12114 else
12115 /* Section base relative. */
12116 signed_value = value - sb + signed_addend;
12117
12118 /* Calculate the value of the relevant G_{n-1} to obtain
12119 the residual at that stage. */
b6518b38
NC		 12120 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12121 group - 1, &residual);
99059e56
RM		 12122
12123 /* Check for overflow. (The absolute value to go in the place must be
12124 divisible by four and, after having been divided by four, must
12125 fit in eight bits.) */
12126 if ((residual & 0x3) != 0 || residual >= 0x400)
12127 {
4eca0228 12128 _bfd_error_handler
695344c0 12129 /* xgettext:c-format */
90b6238f 12130 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12131 "splitting %#" PRIx64 " for group relocation %s"),
12132 input_bfd, input_section, (uint64_t) rel->r_offset,
12133 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12134 howto->name);
99059e56
RM		 12135 return bfd_reloc_overflow;
12136 }
12137
12138 /* Mask out the value and U bit. */
12139 insn &= 0xff7fff00;
12140
12141 /* Set the U bit if the value to go in the place is non-negative. */
12142 if (signed_value >= 0)
12143 insn |= 1 << 23;
12144
12145 /* Encode the offset. */
12146 insn |= residual >> 2;
4962c51a
MS		 12147
12148 bfd_put_32 (input_bfd, insn, hit_data);
12149 }
12150 return bfd_reloc_ok;
12151
72d98d16
MG		 12152 case R_ARM_THM_ALU_ABS_G0_NC:
12153 case R_ARM_THM_ALU_ABS_G1_NC:
12154 case R_ARM_THM_ALU_ABS_G2_NC:
12155 case R_ARM_THM_ALU_ABS_G3_NC:
12156 {
12157 const int shift_array[4] = {0, 8, 16, 24};
12158 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12159 bfd_vma addr = value;
12160 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12161
12162 /* Compute address. */
12163 if (globals->use_rel)
12164 signed_addend = insn & 0xff;
12165 addr += signed_addend;
12166 if (branch_type == ST_BRANCH_TO_THUMB)
12167 addr |= 1;
12168 /* Clean imm8 insn. */
12169 insn &= 0xff00;
12170 /* And update with correct part of address. */
12171 insn |= (addr >> shift) & 0xff;
12172 /* Update insn. */
12173 bfd_put_16 (input_bfd, insn, hit_data);
12174 }
12175
12176 *unresolved_reloc_p = FALSE;
12177 return bfd_reloc_ok;
12178
252b5132
RH		 12179 default:
12180 return bfd_reloc_notsupported;
12181 }
12182}
12183
98c1d4aa
NC		 12184/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12185static void
07d6d2b8
AM		 12186arm_add_to_rel (bfd * abfd,
12187 bfd_byte * address,
57e8b36a 12188 reloc_howto_type * howto,
07d6d2b8 12189 bfd_signed_vma increment)
98c1d4aa 12190{
98c1d4aa
NC		 12191 bfd_signed_vma addend;
12192
bd97cb95
DJ		 12193 if (howto->type == R_ARM_THM_CALL
12194 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12195 {
9a5aca8c
AM		 12196 int upper_insn, lower_insn;
12197 int upper, lower;
98c1d4aa 12198
9a5aca8c
AM		 12199 upper_insn = bfd_get_16 (abfd, address);
12200 lower_insn = bfd_get_16 (abfd, address + 2);
12201 upper = upper_insn & 0x7ff;
12202 lower = lower_insn & 0x7ff;
12203
12204 addend = (upper << 12) | (lower << 1);
ddda4409 12205 addend += increment;
9a5aca8c 12206 addend >>= 1;
98c1d4aa 12207
9a5aca8c
AM		 12208 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12209 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12210
dc810e39
AM		 12211 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12212 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12213 }
12214 else
12215 {
07d6d2b8 12216 bfd_vma contents;
9a5aca8c
AM		 12217
12218 contents = bfd_get_32 (abfd, address);
12219
12220 /* Get the (signed) value from the instruction. */
12221 addend = contents & howto->src_mask;
12222 if (addend & ((howto->src_mask + 1) >> 1))
12223 {
12224 bfd_signed_vma mask;
12225
12226 mask = -1;
12227 mask &= ~ howto->src_mask;
12228 addend |= mask;
12229 }
12230
12231 /* Add in the increment, (which is a byte value). */
12232 switch (howto->type)
12233 {
12234 default:
12235 addend += increment;
12236 break;
12237
12238 case R_ARM_PC24:
c6596c5e 12239 case R_ARM_PLT32:
5b5bb741
PB		 12240 case R_ARM_CALL:
12241 case R_ARM_JUMP24:
9a5aca8c 12242 addend <<= howto->size;
dc810e39 12243 addend += increment;
9a5aca8c
AM		 12244
12245 /* Should we check for overflow here ? */
12246
12247 /* Drop any undesired bits. */
12248 addend >>= howto->rightshift;
12249 break;
12250 }
12251
12252 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12253
12254 bfd_put_32 (abfd, contents, address);
ddda4409 12255 }
98c1d4aa 12256}
252b5132 12257
ba93b8ac
DJ		 12258#define IS_ARM_TLS_RELOC(R_TYPE) \
12259 ((R_TYPE) == R_ARM_TLS_GD32 \
12260 || (R_TYPE) == R_ARM_TLS_LDO32 \
12261 || (R_TYPE) == R_ARM_TLS_LDM32 \
12262 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12263 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12264 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12265 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12266 || (R_TYPE) == R_ARM_TLS_IE32 \
12267 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12268
12269/* Specific set of relocations for the gnu tls dialect. */
12270#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12271 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12272 || (R_TYPE) == R_ARM_TLS_CALL \
12273 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12274 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12275 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12276
252b5132 12277/* Relocate an ARM ELF section. */
906e58ca 12278
b34976b6 12279static bfd_boolean
07d6d2b8 12280elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 12281 struct bfd_link_info * info,
07d6d2b8
AM		 12282 bfd * input_bfd,
12283 asection * input_section,
12284 bfd_byte * contents,
12285 Elf_Internal_Rela * relocs,
12286 Elf_Internal_Sym * local_syms,
12287 asection ** local_sections)
252b5132 12288{
b34976b6
AM		 12289 Elf_Internal_Shdr *symtab_hdr;
12290 struct elf_link_hash_entry **sym_hashes;
12291 Elf_Internal_Rela *rel;
12292 Elf_Internal_Rela *relend;
12293 const char *name;
b32d3aa2 12294 struct elf32_arm_link_hash_table * globals;
252b5132 12295
4e7fd91e 12296 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12297 if (globals == NULL)
12298 return FALSE;
b491616a 12299
0ffa91dd 12300 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12301 sym_hashes = elf_sym_hashes (input_bfd);
12302
12303 rel = relocs;
12304 relend = relocs + input_section->reloc_count;
12305 for (; rel < relend; rel++)
12306 {
07d6d2b8
AM		 12307 int r_type;
12308 reloc_howto_type * howto;
12309 unsigned long r_symndx;
12310 Elf_Internal_Sym * sym;
12311 asection * sec;
252b5132 12312 struct elf_link_hash_entry * h;
07d6d2b8
AM		 12313 bfd_vma relocation;
12314 bfd_reloc_status_type r;
12315 arelent bfd_reloc;
12316 char sym_type;
12317 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12318 char *error_message = NULL;
f21f3fe0 12319
252b5132 12320 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12321 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12322 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12323
ba96a88f 12324 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12325 || r_type == R_ARM_GNU_VTINHERIT)
12326 continue;
252b5132 12327
47aeb64c
NC		 12328 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
12329
12330 if (howto == NULL)
12331 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 12332
252b5132
RH		 12333 h = NULL;
12334 sym = NULL;
12335 sec = NULL;
9b485d32 12336
252b5132
RH		 12337 if (r_symndx < symtab_hdr->sh_info)
12338 {
12339 sym = local_syms + r_symndx;
ba93b8ac 12340 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12341 sec = local_sections[r_symndx];
ffcb4889
NS		 12342
12343 /* An object file might have a reference to a local
12344 undefined symbol. This is a daft object file, but we
12345 should at least do something about it. V4BX & NONE
12346 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12347 allowed to use the undefined symbol, so allow those.
12348 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12349 if (r_type != R_ARM_V4BX
12350 && r_type != R_ARM_NONE
77b4f08f 12351 && r_symndx != STN_UNDEF
ffcb4889
NS		 12352 && bfd_is_und_section (sec)
12353 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12354 (*info->callbacks->undefined_symbol)
12355 (info, bfd_elf_string_from_elf_section
12356 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12357 input_bfd, input_section,
12358 rel->r_offset, TRUE);
b38cadfb 12359
4e7fd91e 12360 if (globals->use_rel)
f8df10f4 12361 {
4e7fd91e
PB		 12362 relocation = (sec->output_section->vma
12363 + sec->output_offset
12364 + sym->st_value);
0e1862bb 12365 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12366 && (sec->flags & SEC_MERGE)
12367 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12368 {
4e7fd91e
PB		 12369 asection *msec;
12370 bfd_vma addend, value;
12371
39623e12 12372 switch (r_type)
4e7fd91e 12373 {
39623e12
PB		 12374 case R_ARM_MOVW_ABS_NC:
12375 case R_ARM_MOVT_ABS:
12376 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12377 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12378 addend = (addend ^ 0x8000) - 0x8000;
12379 break;
f8df10f4 12380
39623e12
PB		 12381 case R_ARM_THM_MOVW_ABS_NC:
12382 case R_ARM_THM_MOVT_ABS:
12383 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12384 << 16;
12385 value |= bfd_get_16 (input_bfd,
12386 contents + rel->r_offset + 2);
12387 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12388 | ((value & 0x04000000) >> 15);
12389 addend = (addend ^ 0x8000) - 0x8000;
12390 break;
f8df10f4 12391
39623e12
PB		 12392 default:
12393 if (howto->rightshift
12394 || (howto->src_mask & (howto->src_mask + 1)))
12395 {
4eca0228 12396 _bfd_error_handler
695344c0 12397 /* xgettext:c-format */
2dcf00ce
AM		 12398 (_("%pB(%pA+%#" PRIx64 "): "
12399 "%s relocation against SEC_MERGE section"),
39623e12 12400 input_bfd, input_section,
2dcf00ce 12401 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 12402 return FALSE;
12403 }
12404
12405 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12406
12407 /* Get the (signed) value from the instruction. */
12408 addend = value & howto->src_mask;
12409 if (addend & ((howto->src_mask + 1) >> 1))
12410 {
12411 bfd_signed_vma mask;
12412
12413 mask = -1;
12414 mask &= ~ howto->src_mask;
12415 addend |= mask;
12416 }
12417 break;
4e7fd91e 12418 }
39623e12 12419
4e7fd91e
PB		 12420 msec = sec;
12421 addend =
12422 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12423 - relocation;
12424 addend += msec->output_section->vma + msec->output_offset;
39623e12 12425
cc643b88 12426 /* Cases here must match those in the preceding
39623e12
PB		 12427 switch statement. */
12428 switch (r_type)
12429 {
12430 case R_ARM_MOVW_ABS_NC:
12431 case R_ARM_MOVT_ABS:
12432 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12433 | (addend & 0xfff);
12434 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12435 break;
12436
12437 case R_ARM_THM_MOVW_ABS_NC:
12438 case R_ARM_THM_MOVT_ABS:
12439 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12440 | (addend & 0xff) | ((addend & 0x0800) << 15);
12441 bfd_put_16 (input_bfd, value >> 16,
12442 contents + rel->r_offset);
12443 bfd_put_16 (input_bfd, value,
12444 contents + rel->r_offset + 2);
12445 break;
12446
12447 default:
12448 value = (value & ~ howto->dst_mask)
12449 | (addend & howto->dst_mask);
12450 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12451 break;
12452 }
f8df10f4 12453 }
f8df10f4 12454 }
4e7fd91e
PB		 12455 else
12456 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12457 }
12458 else
12459 {
62d887d4 12460 bfd_boolean warned, ignored;
560e09e9 12461
b2a8e766
AM		 12462 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12463 r_symndx, symtab_hdr, sym_hashes,
12464 h, sec, relocation,
62d887d4 12465 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12466
12467 sym_type = h->type;
252b5132
RH		 12468 }
12469
dbaa2011 12470 if (sec != NULL && discarded_section (sec))
e4067dbb 12471 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12472 rel, 1, relend, howto, 0, contents);
ab96bf03 12473
0e1862bb 12474 if (bfd_link_relocatable (info))
ab96bf03
AM		 12475 {
12476 /* This is a relocatable link. We don't have to change
12477 anything, unless the reloc is against a section symbol,
12478 in which case we have to adjust according to where the
12479 section symbol winds up in the output section. */
12480 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12481 {
12482 if (globals->use_rel)
12483 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12484 howto, (bfd_signed_vma) sec->output_offset);
12485 else
12486 rel->r_addend += sec->output_offset;
12487 }
12488 continue;
12489 }
12490
252b5132
RH		 12491 if (h != NULL)
12492 name = h->root.root.string;
12493 else
12494 {
12495 name = (bfd_elf_string_from_elf_section
12496 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12497 if (name == NULL || *name == '\0')
12498 name = bfd_section_name (input_bfd, sec);
12499 }
f21f3fe0 12500
cf35638d 12501 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12502 && r_type != R_ARM_NONE
12503 && (h == NULL
12504 || h->root.type == bfd_link_hash_defined
12505 || h->root.type == bfd_link_hash_defweak)
12506 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12507 {
4eca0228 12508 _bfd_error_handler
ba93b8ac 12509 ((sym_type == STT_TLS
695344c0 12510 /* xgettext:c-format */
2dcf00ce 12511 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 12512 /* xgettext:c-format */
2dcf00ce 12513 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 12514 input_bfd,
12515 input_section,
2dcf00ce 12516 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 12517 howto->name,
12518 name);
12519 }
12520
0855e32b 12521 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12522 done, i.e., the relaxation produced the final output we want,
12523 and we won't let anybody mess with it. Also, we have to do
12524 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12525 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12526 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12527 || (IS_ARM_TLS_GNU_RELOC (r_type)
12528 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12529 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12530 & GOT_TLS_GDESC)))
12531 {
12532 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12533 contents, rel, h == NULL);
12534 /* This may have been marked unresolved because it came from
12535 a shared library. But we've just dealt with that. */
12536 unresolved_reloc = 0;
12537 }
12538 else
12539 r = bfd_reloc_continue;
b38cadfb 12540
39d911fc
TP		 12541 if (r == bfd_reloc_continue)
12542 {
12543 unsigned char branch_type =
12544 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12545 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12546
12547 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12548 input_section, contents, rel,
12549 relocation, info, sec, name,
12550 sym_type, branch_type, h,
12551 &unresolved_reloc,
12552 &error_message);
12553 }
0945cdfd
DJ		 12554
12555 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12556 because such sections are not SEC_ALLOC and thus ld.so will
12557 not process them. */
12558 if (unresolved_reloc
99059e56
RM		 12559 && !((input_section->flags & SEC_DEBUGGING) != 0
12560 && h->def_dynamic)
1d5316ab
AM		 12561 && _bfd_elf_section_offset (output_bfd, info, input_section,
12562 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12563 {
4eca0228 12564 _bfd_error_handler
695344c0 12565 /* xgettext:c-format */
2dcf00ce
AM		 12566 (_("%pB(%pA+%#" PRIx64 "): "
12567 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 12568 input_bfd,
12569 input_section,
2dcf00ce 12570 (uint64_t) rel->r_offset,
843fe662
L		 12571 howto->name,
12572 h->root.root.string);
0945cdfd
DJ		 12573 return FALSE;
12574 }
252b5132
RH		 12575
12576 if (r != bfd_reloc_ok)
12577 {
252b5132
RH		 12578 switch (r)
12579 {
12580 case bfd_reloc_overflow:
cf919dfd
PB		 12581 /* If the overflowing reloc was to an undefined symbol,
12582 we have already printed one error message and there
12583 is no point complaining again. */
1a72702b
AM		 12584 if (!h || h->root.type != bfd_link_hash_undefined)
12585 (*info->callbacks->reloc_overflow)
12586 (info, (h ? &h->root : NULL), name, howto->name,
12587 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12588 break;
12589
12590 case bfd_reloc_undefined:
1a72702b
AM		 12591 (*info->callbacks->undefined_symbol)
12592 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12593 break;
12594
12595 case bfd_reloc_outofrange:
f2a9dd69 12596 error_message = _("out of range");
252b5132
RH		 12597 goto common_error;
12598
12599 case bfd_reloc_notsupported:
f2a9dd69 12600 error_message = _("unsupported relocation");
252b5132
RH		 12601 goto common_error;
12602
12603 case bfd_reloc_dangerous:
f2a9dd69 12604 /* error_message should already be set. */
252b5132
RH		 12605 goto common_error;
12606
12607 default:
f2a9dd69 12608 error_message = _("unknown error");
8029a119 12609 /* Fall through. */
252b5132
RH		 12610
12611 common_error:
f2a9dd69 12612 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12613 (*info->callbacks->reloc_dangerous)
12614 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12615 break;
12616 }
12617 }
12618 }
12619
b34976b6 12620 return TRUE;
252b5132
RH		 12621}
12622
91d6fa6a 12623/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12624 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12625 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12626 maintaining that condition). */
12627
12628static void
12629add_unwind_table_edit (arm_unwind_table_edit **head,
12630 arm_unwind_table_edit **tail,
12631 arm_unwind_edit_type type,
12632 asection *linked_section,
91d6fa6a 12633 unsigned int tindex)
2468f9c9 12634{
21d799b5
NC		 12635 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12636 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12637
2468f9c9
PB		 12638 new_edit->type = type;
12639 new_edit->linked_section = linked_section;
91d6fa6a 12640 new_edit->index = tindex;
b38cadfb 12641
91d6fa6a 12642 if (tindex > 0)
2468f9c9
PB		 12643 {
12644 new_edit->next = NULL;
12645
12646 if (*tail)
12647 (*tail)->next = new_edit;
12648
12649 (*tail) = new_edit;
12650
12651 if (!*head)
12652 (*head) = new_edit;
12653 }
12654 else
12655 {
12656 new_edit->next = *head;
12657
12658 if (!*tail)
12659 *tail = new_edit;
12660
12661 *head = new_edit;
12662 }
12663}
12664
12665static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12666
12667/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12668static void
12669adjust_exidx_size(asection *exidx_sec, int adjust)
12670{
12671 asection *out_sec;
12672
12673 if (!exidx_sec->rawsize)
12674 exidx_sec->rawsize = exidx_sec->size;
12675
12676 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12677 out_sec = exidx_sec->output_section;
12678 /* Adjust size of output section. */
12679 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12680}
12681
12682/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12683static void
12684insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12685{
12686 struct _arm_elf_section_data *exidx_arm_data;
12687
12688 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12689 add_unwind_table_edit (
12690 &exidx_arm_data->u.exidx.unwind_edit_list,
12691 &exidx_arm_data->u.exidx.unwind_edit_tail,
12692 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12693
491d01d3
YU		 12694 exidx_arm_data->additional_reloc_count++;
12695
2468f9c9
PB		 12696 adjust_exidx_size(exidx_sec, 8);
12697}
12698
12699/* Scan .ARM.exidx tables, and create a list describing edits which should be
12700 made to those tables, such that:
b38cadfb 12701
2468f9c9
PB		 12702 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12703 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12704 codes which have been inlined into the index).
2468f9c9 12705
85fdf906
AH		 12706 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12707
2468f9c9 12708 The edits are applied when the tables are written
b38cadfb 12709 (in elf32_arm_write_section). */
2468f9c9
PB		 12710
12711bfd_boolean
12712elf32_arm_fix_exidx_coverage (asection **text_section_order,
12713 unsigned int num_text_sections,
85fdf906
AH		 12714 struct bfd_link_info *info,
12715 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12716{
12717 bfd *inp;
12718 unsigned int last_second_word = 0, i;
12719 asection *last_exidx_sec = NULL;
12720 asection *last_text_sec = NULL;
12721 int last_unwind_type = -1;
12722
12723 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12724 text sections. */
c72f2fb2 12725 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12726 {
12727 asection *sec;
b38cadfb 12728
2468f9c9 12729 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12730 {
2468f9c9
PB		 12731 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12732 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12733
dec9d5df 12734 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12735 continue;
b38cadfb 12736
2468f9c9
PB		 12737 if (elf_sec->linked_to)
12738 {
12739 Elf_Internal_Shdr *linked_hdr
99059e56 12740 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12741 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12742 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12743
12744 if (linked_sec_arm_data == NULL)
99059e56 12745 continue;
2468f9c9
PB		 12746
12747 /* Link this .ARM.exidx section back from the text section it
99059e56 12748 describes. */
2468f9c9
PB		 12749 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12750 }
12751 }
12752 }
12753
12754 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12755 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12756 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12757
12758 for (i = 0; i < num_text_sections; i++)
12759 {
12760 asection *sec = text_section_order[i];
12761 asection *exidx_sec;
12762 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12763 struct _arm_elf_section_data *exidx_arm_data;
12764 bfd_byte *contents = NULL;
12765 int deleted_exidx_bytes = 0;
12766 bfd_vma j;
12767 arm_unwind_table_edit *unwind_edit_head = NULL;
12768 arm_unwind_table_edit *unwind_edit_tail = NULL;
12769 Elf_Internal_Shdr *hdr;
12770 bfd *ibfd;
12771
12772 if (arm_data == NULL)
99059e56 12773 continue;
2468f9c9
PB		 12774
12775 exidx_sec = arm_data->u.text.arm_exidx_sec;
12776 if (exidx_sec == NULL)
12777 {
12778 /* Section has no unwind data. */
12779 if (last_unwind_type == 0 || !last_exidx_sec)
12780 continue;
12781
12782 /* Ignore zero sized sections. */
12783 if (sec->size == 0)
12784 continue;
12785
12786 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12787 last_unwind_type = 0;
12788 continue;
12789 }
12790
22a8f80e
PB		 12791 /* Skip /DISCARD/ sections. */
12792 if (bfd_is_abs_section (exidx_sec->output_section))
12793 continue;
12794
2468f9c9
PB		 12795 hdr = &elf_section_data (exidx_sec)->this_hdr;
12796 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12797 continue;
b38cadfb 12798
2468f9c9
PB		 12799 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12800 if (exidx_arm_data == NULL)
99059e56 12801 continue;
b38cadfb 12802
2468f9c9 12803 ibfd = exidx_sec->owner;
b38cadfb 12804
2468f9c9
PB		 12805 if (hdr->contents != NULL)
12806 contents = hdr->contents;
12807 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12808 /* An error? */
12809 continue;
12810
ac06903d
YU		 12811 if (last_unwind_type > 0)
12812 {
12813 unsigned int first_word = bfd_get_32 (ibfd, contents);
12814 /* Add cantunwind if first unwind item does not match section
12815 start. */
12816 if (first_word != sec->vma)
12817 {
12818 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12819 last_unwind_type = 0;
12820 }
12821 }
12822
2468f9c9
PB		 12823 for (j = 0; j < hdr->sh_size; j += 8)
12824 {
12825 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12826 int unwind_type;
12827 int elide = 0;
12828
12829 /* An EXIDX_CANTUNWIND entry. */
12830 if (second_word == 1)
12831 {
12832 if (last_unwind_type == 0)
12833 elide = 1;
12834 unwind_type = 0;
12835 }
12836 /* Inlined unwinding data. Merge if equal to previous. */
12837 else if ((second_word & 0x80000000) != 0)
12838 {
85fdf906
AH		 12839 if (merge_exidx_entries
12840 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12841 elide = 1;
12842 unwind_type = 1;
12843 last_second_word = second_word;
12844 }
12845 /* Normal table entry. In theory we could merge these too,
12846 but duplicate entries are likely to be much less common. */
12847 else
12848 unwind_type = 2;
12849
491d01d3 12850 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12851 {
12852 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12853 DELETE_EXIDX_ENTRY, NULL, j / 8);
12854
12855 deleted_exidx_bytes += 8;
12856 }
12857
12858 last_unwind_type = unwind_type;
12859 }
12860
12861 /* Free contents if we allocated it ourselves. */
12862 if (contents != hdr->contents)
99059e56 12863 free (contents);
2468f9c9
PB		 12864
12865 /* Record edits to be applied later (in elf32_arm_write_section). */
12866 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12867 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12868
2468f9c9
PB		 12869 if (deleted_exidx_bytes > 0)
12870 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12871
12872 last_exidx_sec = exidx_sec;
12873 last_text_sec = sec;
12874 }
12875
12876 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12877 if (!bfd_link_relocatable (info) && last_exidx_sec
12878 && last_unwind_type != 0)
2468f9c9
PB		 12879 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12880
12881 return TRUE;
12882}
12883
3e6b1042
DJ		 12884static bfd_boolean
12885elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12886 bfd *ibfd, const char *name)
12887{
12888 asection *sec, *osec;
12889
3d4d4302 12890 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12891 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12892 return TRUE;
12893
12894 osec = sec->output_section;
12895 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12896 return TRUE;
12897
12898 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12899 sec->output_offset, sec->size))
12900 return FALSE;
12901
12902 return TRUE;
12903}
12904
12905static bfd_boolean
12906elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12907{
12908 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12909 asection *sec, *osec;
3e6b1042 12910
4dfe6ac6
NC		 12911 if (globals == NULL)
12912 return FALSE;
12913
3e6b1042
DJ		 12914 /* Invoke the regular ELF backend linker to do all the work. */
12915 if (!bfd_elf_final_link (abfd, info))
12916 return FALSE;
12917
fe33d2fa
CL		 12918 /* Process stub sections (eg BE8 encoding, ...). */
12919 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12920 unsigned int i;
cdb21a0a
NS		 12921 for (i=0; i<htab->top_id; i++)
12922 {
12923 sec = htab->stub_group[i].stub_sec;
12924 /* Only process it once, in its link_sec slot. */
12925 if (sec && i == htab->stub_group[i].link_sec->id)
12926 {
12927 osec = sec->output_section;
12928 elf32_arm_write_section (abfd, info, sec, sec->contents);
12929 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12930 sec->output_offset, sec->size))
12931 return FALSE;
12932 }
fe33d2fa 12933 }
fe33d2fa 12934
3e6b1042
DJ		 12935 /* Write out any glue sections now that we have created all the
12936 stubs. */
12937 if (globals->bfd_of_glue_owner != NULL)
12938 {
12939 if (! elf32_arm_output_glue_section (info, abfd,
12940 globals->bfd_of_glue_owner,
12941 ARM2THUMB_GLUE_SECTION_NAME))
12942 return FALSE;
12943
12944 if (! elf32_arm_output_glue_section (info, abfd,
12945 globals->bfd_of_glue_owner,
12946 THUMB2ARM_GLUE_SECTION_NAME))
12947 return FALSE;
12948
12949 if (! elf32_arm_output_glue_section (info, abfd,
12950 globals->bfd_of_glue_owner,
12951 VFP11_ERRATUM_VENEER_SECTION_NAME))
12952 return FALSE;
12953
a504d23a
LA		 12954 if (! elf32_arm_output_glue_section (info, abfd,
12955 globals->bfd_of_glue_owner,
12956 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12957 return FALSE;
12958
3e6b1042
DJ		 12959 if (! elf32_arm_output_glue_section (info, abfd,
12960 globals->bfd_of_glue_owner,
12961 ARM_BX_GLUE_SECTION_NAME))
12962 return FALSE;
12963 }
12964
12965 return TRUE;
12966}
12967
5968a7b8
NC		 12968/* Return a best guess for the machine number based on the attributes. */
12969
12970static unsigned int
12971bfd_arm_get_mach_from_attributes (bfd * abfd)
12972{
12973 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12974
12975 switch (arch)
12976 {
12977 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12978 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12979 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12980
12981 case TAG_CPU_ARCH_V5TE:
12982 {
12983 char * name;
12984
12985 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12986 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12987
12988 if (name)
12989 {
12990 if (strcmp (name, "IWMMXT2") == 0)
12991 return bfd_mach_arm_iWMMXt2;
12992
12993 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12994 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12995
12996 if (strcmp (name, "XSCALE") == 0)
12997 {
12998 int wmmx;
12999
13000 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13001 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13002 switch (wmmx)
13003 {
13004 case 1: return bfd_mach_arm_iWMMXt;
13005 case 2: return bfd_mach_arm_iWMMXt2;
13006 default: return bfd_mach_arm_XScale;
13007 }
13008 }
5968a7b8
NC		 13009 }
13010
13011 return bfd_mach_arm_5TE;
13012 }
13013
13014 default:
13015 return bfd_mach_arm_unknown;
13016 }
13017}
13018
c178919b
NC		 13019/* Set the right machine number. */
13020
13021static bfd_boolean
57e8b36a 13022elf32_arm_object_p (bfd *abfd)
c178919b 13023{
5a6c6817 13024 unsigned int mach;
57e8b36a 13025
5a6c6817 13026 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13027
5968a7b8
NC		 13028 if (mach == bfd_mach_arm_unknown)
13029 {
13030 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13031 mach = bfd_mach_arm_ep9312;
13032 else
13033 mach = bfd_arm_get_mach_from_attributes (abfd);
13034 }
c178919b 13035
5968a7b8 13036 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13037 return TRUE;
13038}
13039
fc830a83 13040/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13041
b34976b6 13042static bfd_boolean
57e8b36a 13043elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13044{
13045 if (elf_flags_init (abfd)
13046 && elf_elfheader (abfd)->e_flags != flags)
13047 {
fc830a83
NC		 13048 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13049 {
fd2ec330 13050 if (flags & EF_ARM_INTERWORK)
4eca0228 13051 _bfd_error_handler
90b6238f 13052 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13053 abfd);
fc830a83 13054 else
d003868e 13055 _bfd_error_handler
90b6238f 13056 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13057 abfd);
fc830a83 13058 }
252b5132
RH		 13059 }
13060 else
13061 {
13062 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13063 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13064 }
13065
b34976b6 13066 return TRUE;
252b5132
RH		 13067}
13068
fc830a83 13069/* Copy backend specific data from one object module to another. */
9b485d32 13070
b34976b6 13071static bfd_boolean
57e8b36a 13072elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13073{
13074 flagword in_flags;
13075 flagword out_flags;
13076
0ffa91dd 13077 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13078 return TRUE;
252b5132 13079
fc830a83 13080 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13081 out_flags = elf_elfheader (obfd)->e_flags;
13082
fc830a83
NC		 13083 if (elf_flags_init (obfd)
13084 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13085 && in_flags != out_flags)
252b5132 13086 {
252b5132 13087 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13088 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13089 return FALSE;
252b5132
RH		 13090
13091 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13092 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13093 return FALSE;
252b5132
RH		 13094
13095 /* If the src and dest have different interworking flags
99059e56 13096 then turn off the interworking bit. */
fd2ec330 13097 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13098 {
fd2ec330 13099 if (out_flags & EF_ARM_INTERWORK)
d003868e 13100 _bfd_error_handler
90b6238f 13101 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13102 obfd, ibfd);
252b5132 13103
fd2ec330 13104 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13105 }
1006ba19
PB		 13106
13107 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13108 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13109 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13110 }
13111
13112 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13113 elf_flags_init (obfd) = TRUE;
252b5132 13114
e2349352 13115 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13116}
13117
13118/* Values for Tag_ABI_PCS_R9_use. */
13119enum
13120{
13121 AEABI_R9_V6,
13122 AEABI_R9_SB,
13123 AEABI_R9_TLS,
13124 AEABI_R9_unused
13125};
13126
13127/* Values for Tag_ABI_PCS_RW_data. */
13128enum
13129{
13130 AEABI_PCS_RW_data_absolute,
13131 AEABI_PCS_RW_data_PCrel,
13132 AEABI_PCS_RW_data_SBrel,
13133 AEABI_PCS_RW_data_unused
13134};
13135
13136/* Values for Tag_ABI_enum_size. */
13137enum
13138{
13139 AEABI_enum_unused,
13140 AEABI_enum_short,
13141 AEABI_enum_wide,
13142 AEABI_enum_forced_wide
13143};
13144
104d59d1
JM		 13145/* Determine whether an object attribute tag takes an integer, a
13146 string or both. */
906e58ca 13147
104d59d1
JM		 13148static int
13149elf32_arm_obj_attrs_arg_type (int tag)
13150{
13151 if (tag == Tag_compatibility)
3483fe2e 13152 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13153 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13154 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13155 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13156 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13157 else if (tag < 32)
3483fe2e 13158 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13159 else
3483fe2e 13160 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13161}
13162
5aa6ff7c
AS		 13163/* The ABI defines that Tag_conformance should be emitted first, and that
13164 Tag_nodefaults should be second (if either is defined). This sets those
13165 two positions, and bumps up the position of all the remaining tags to
13166 compensate. */
13167static int
13168elf32_arm_obj_attrs_order (int num)
13169{
3de4a297 13170 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13171 return Tag_conformance;
3de4a297 13172 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13173 return Tag_nodefaults;
13174 if ((num - 2) < Tag_nodefaults)
13175 return num - 2;
13176 if ((num - 1) < Tag_conformance)
13177 return num - 1;
13178 return num;
13179}
13180
e8b36cd1
JM		 13181/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13182static bfd_boolean
13183elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13184{
13185 if ((tag & 127) < 64)
13186 {
13187 _bfd_error_handler
90b6238f 13188 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 13189 abfd, tag);
13190 bfd_set_error (bfd_error_bad_value);
13191 return FALSE;
13192 }
13193 else
13194 {
13195 _bfd_error_handler
90b6238f 13196 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 13197 abfd, tag);
13198 return TRUE;
13199 }
13200}
13201
91e22acd
AS		 13202/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13203 Returns -1 if no architecture could be read. */
13204
13205static int
13206get_secondary_compatible_arch (bfd *abfd)
13207{
13208 obj_attribute *attr =
13209 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13210
13211 /* Note: the tag and its argument below are uleb128 values, though
13212 currently-defined values fit in one byte for each. */
13213 if (attr->s
13214 && attr->s[0] == Tag_CPU_arch
13215 && (attr->s[1] & 128) != 128
13216 && attr->s[2] == 0)
13217 return attr->s[1];
13218
13219 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13220 return -1;
13221}
13222
13223/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13224 The tag is removed if ARCH is -1. */
13225
8e79c3df 13226static void
91e22acd 13227set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13228{
91e22acd
AS		 13229 obj_attribute *attr =
13230 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13231
91e22acd
AS		 13232 if (arch == -1)
13233 {
13234 attr->s = NULL;
13235 return;
8e79c3df 13236 }
91e22acd
AS		 13237
13238 /* Note: the tag and its argument below are uleb128 values, though
13239 currently-defined values fit in one byte for each. */
13240 if (!attr->s)
21d799b5 13241 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13242 attr->s[0] = Tag_CPU_arch;
13243 attr->s[1] = arch;
13244 attr->s[2] = '\0';
8e79c3df
CM		 13245}
13246
91e22acd
AS		 13247/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13248 into account. */
13249
13250static int
13251tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13252 int newtag, int secondary_compat)
8e79c3df 13253{
91e22acd
AS		 13254#define T(X) TAG_CPU_ARCH_##X
13255 int tagl, tagh, result;
13256 const int v6t2[] =
13257 {
13258 T(V6T2), /* PRE_V4. */
13259 T(V6T2), /* V4. */
13260 T(V6T2), /* V4T. */
13261 T(V6T2), /* V5T. */
13262 T(V6T2), /* V5TE. */
13263 T(V6T2), /* V5TEJ. */
13264 T(V6T2), /* V6. */
13265 T(V7), /* V6KZ. */
13266 T(V6T2) /* V6T2. */
13267 };
13268 const int v6k[] =
13269 {
13270 T(V6K), /* PRE_V4. */
13271 T(V6K), /* V4. */
13272 T(V6K), /* V4T. */
13273 T(V6K), /* V5T. */
13274 T(V6K), /* V5TE. */
13275 T(V6K), /* V5TEJ. */
13276 T(V6K), /* V6. */
13277 T(V6KZ), /* V6KZ. */
13278 T(V7), /* V6T2. */
13279 T(V6K) /* V6K. */
13280 };
13281 const int v7[] =
13282 {
13283 T(V7), /* PRE_V4. */
13284 T(V7), /* V4. */
13285 T(V7), /* V4T. */
13286 T(V7), /* V5T. */
13287 T(V7), /* V5TE. */
13288 T(V7), /* V5TEJ. */
13289 T(V7), /* V6. */
13290 T(V7), /* V6KZ. */
13291 T(V7), /* V6T2. */
13292 T(V7), /* V6K. */
13293 T(V7) /* V7. */
13294 };
13295 const int v6_m[] =
13296 {
07d6d2b8
AM		 13297 -1, /* PRE_V4. */
13298 -1, /* V4. */
91e22acd
AS		 13299 T(V6K), /* V4T. */
13300 T(V6K), /* V5T. */
13301 T(V6K), /* V5TE. */
13302 T(V6K), /* V5TEJ. */
13303 T(V6K), /* V6. */
13304 T(V6KZ), /* V6KZ. */
13305 T(V7), /* V6T2. */
13306 T(V6K), /* V6K. */
13307 T(V7), /* V7. */
13308 T(V6_M) /* V6_M. */
13309 };
13310 const int v6s_m[] =
13311 {
07d6d2b8
AM		 13312 -1, /* PRE_V4. */
13313 -1, /* V4. */
91e22acd
AS		 13314 T(V6K), /* V4T. */
13315 T(V6K), /* V5T. */
13316 T(V6K), /* V5TE. */
13317 T(V6K), /* V5TEJ. */
13318 T(V6K), /* V6. */
13319 T(V6KZ), /* V6KZ. */
13320 T(V7), /* V6T2. */
13321 T(V6K), /* V6K. */
13322 T(V7), /* V7. */
13323 T(V6S_M), /* V6_M. */
13324 T(V6S_M) /* V6S_M. */
13325 };
9e3c6df6
PB		 13326 const int v7e_m[] =
13327 {
07d6d2b8
AM		 13328 -1, /* PRE_V4. */
13329 -1, /* V4. */
9e3c6df6
PB		 13330 T(V7E_M), /* V4T. */
13331 T(V7E_M), /* V5T. */
13332 T(V7E_M), /* V5TE. */
13333 T(V7E_M), /* V5TEJ. */
13334 T(V7E_M), /* V6. */
13335 T(V7E_M), /* V6KZ. */
13336 T(V7E_M), /* V6T2. */
13337 T(V7E_M), /* V6K. */
13338 T(V7E_M), /* V7. */
13339 T(V7E_M), /* V6_M. */
13340 T(V7E_M), /* V6S_M. */
13341 T(V7E_M) /* V7E_M. */
13342 };
bca38921
MGD		 13343 const int v8[] =
13344 {
13345 T(V8), /* PRE_V4. */
13346 T(V8), /* V4. */
13347 T(V8), /* V4T. */
13348 T(V8), /* V5T. */
13349 T(V8), /* V5TE. */
13350 T(V8), /* V5TEJ. */
13351 T(V8), /* V6. */
13352 T(V8), /* V6KZ. */
13353 T(V8), /* V6T2. */
13354 T(V8), /* V6K. */
13355 T(V8), /* V7. */
13356 T(V8), /* V6_M. */
13357 T(V8), /* V6S_M. */
13358 T(V8), /* V7E_M. */
13359 T(V8) /* V8. */
13360 };
bff0500d
TP		 13361 const int v8r[] =
13362 {
13363 T(V8R), /* PRE_V4. */
13364 T(V8R), /* V4. */
13365 T(V8R), /* V4T. */
13366 T(V8R), /* V5T. */
13367 T(V8R), /* V5TE. */
13368 T(V8R), /* V5TEJ. */
13369 T(V8R), /* V6. */
13370 T(V8R), /* V6KZ. */
13371 T(V8R), /* V6T2. */
13372 T(V8R), /* V6K. */
13373 T(V8R), /* V7. */
13374 T(V8R), /* V6_M. */
13375 T(V8R), /* V6S_M. */
13376 T(V8R), /* V7E_M. */
13377 T(V8), /* V8. */
13378 T(V8R), /* V8R. */
13379 };
2fd158eb
TP		 13380 const int v8m_baseline[] =
13381 {
13382 -1, /* PRE_V4. */
13383 -1, /* V4. */
13384 -1, /* V4T. */
13385 -1, /* V5T. */
13386 -1, /* V5TE. */
13387 -1, /* V5TEJ. */
13388 -1, /* V6. */
13389 -1, /* V6KZ. */
13390 -1, /* V6T2. */
13391 -1, /* V6K. */
13392 -1, /* V7. */
13393 T(V8M_BASE), /* V6_M. */
13394 T(V8M_BASE), /* V6S_M. */
13395 -1, /* V7E_M. */
13396 -1, /* V8. */
bff0500d 13397 -1, /* V8R. */
2fd158eb
TP		 13398 T(V8M_BASE) /* V8-M BASELINE. */
13399 };
13400 const int v8m_mainline[] =
13401 {
13402 -1, /* PRE_V4. */
13403 -1, /* V4. */
13404 -1, /* V4T. */
13405 -1, /* V5T. */
13406 -1, /* V5TE. */
13407 -1, /* V5TEJ. */
13408 -1, /* V6. */
13409 -1, /* V6KZ. */
13410 -1, /* V6T2. */
13411 -1, /* V6K. */
13412 T(V8M_MAIN), /* V7. */
13413 T(V8M_MAIN), /* V6_M. */
13414 T(V8M_MAIN), /* V6S_M. */
13415 T(V8M_MAIN), /* V7E_M. */
13416 -1, /* V8. */
bff0500d 13417 -1, /* V8R. */
2fd158eb
TP		 13418 T(V8M_MAIN), /* V8-M BASELINE. */
13419 T(V8M_MAIN) /* V8-M MAINLINE. */
13420 };
91e22acd
AS		 13421 const int v4t_plus_v6_m[] =
13422 {
13423 -1, /* PRE_V4. */
13424 -1, /* V4. */
13425 T(V4T), /* V4T. */
13426 T(V5T), /* V5T. */
13427 T(V5TE), /* V5TE. */
13428 T(V5TEJ), /* V5TEJ. */
13429 T(V6), /* V6. */
13430 T(V6KZ), /* V6KZ. */
13431 T(V6T2), /* V6T2. */
13432 T(V6K), /* V6K. */
13433 T(V7), /* V7. */
13434 T(V6_M), /* V6_M. */
13435 T(V6S_M), /* V6S_M. */
9e3c6df6 13436 T(V7E_M), /* V7E_M. */
bca38921 13437 T(V8), /* V8. */
bff0500d 13438 -1, /* V8R. */
2fd158eb
TP		 13439 T(V8M_BASE), /* V8-M BASELINE. */
13440 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13441 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13442 };
13443 const int *comb[] =
13444 {
13445 v6t2,
13446 v6k,
13447 v7,
13448 v6_m,
13449 v6s_m,
9e3c6df6 13450 v7e_m,
bca38921 13451 v8,
bff0500d 13452 v8r,
2fd158eb
TP		 13453 v8m_baseline,
13454 v8m_mainline,
91e22acd
AS		 13455 /* Pseudo-architecture. */
13456 v4t_plus_v6_m
13457 };
13458
13459 /* Check we've not got a higher architecture than we know about. */
13460
9e3c6df6 13461 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13462 {
90b6238f 13463 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 13464 return -1;
13465 }
13466
13467 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13468
13469 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13470 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13471 oldtag = T(V4T_PLUS_V6_M);
13472
13473 /* And override the new tag if we have a Tag_also_compatible_with on the
13474 input. */
13475
13476 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13477 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13478 newtag = T(V4T_PLUS_V6_M);
13479
13480 tagl = (oldtag < newtag) ? oldtag : newtag;
13481 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13482
13483 /* Architectures before V6KZ add features monotonically. */
13484 if (tagh <= TAG_CPU_ARCH_V6KZ)
13485 return result;
13486
4ed7ed8d 13487 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13488
13489 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13490 as the canonical version. */
13491 if (result == T(V4T_PLUS_V6_M))
13492 {
13493 result = T(V4T);
13494 *secondary_compat_out = T(V6_M);
13495 }
13496 else
13497 *secondary_compat_out = -1;
13498
13499 if (result == -1)
13500 {
90b6238f 13501 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 13502 ibfd, oldtag, newtag);
13503 return -1;
13504 }
13505
13506 return result;
13507#undef T
8e79c3df
CM		 13508}
13509
ac56ee8f
MGD		 13510/* Query attributes object to see if integer divide instructions may be
13511 present in an object. */
13512static bfd_boolean
13513elf32_arm_attributes_accept_div (const obj_attribute *attr)
13514{
13515 int arch = attr[Tag_CPU_arch].i;
13516 int profile = attr[Tag_CPU_arch_profile].i;
13517
13518 switch (attr[Tag_DIV_use].i)
13519 {
13520 case 0:
13521 /* Integer divide allowed if instruction contained in archetecture. */
13522 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13523 return TRUE;
13524 else if (arch >= TAG_CPU_ARCH_V7E_M)
13525 return TRUE;
13526 else
13527 return FALSE;
13528
13529 case 1:
13530 /* Integer divide explicitly prohibited. */
13531 return FALSE;
13532
13533 default:
13534 /* Unrecognised case - treat as allowing divide everywhere. */
13535 case 2:
13536 /* Integer divide allowed in ARM state. */
13537 return TRUE;
13538 }
13539}
13540
13541/* Query attributes object to see if integer divide instructions are
13542 forbidden to be in the object. This is not the inverse of
13543 elf32_arm_attributes_accept_div. */
13544static bfd_boolean
13545elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13546{
13547 return attr[Tag_DIV_use].i == 1;
13548}
13549
ee065d83
PB		 13550/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13551 are conflicting attributes. */
906e58ca 13552
ee065d83 13553static bfd_boolean
50e03d47 13554elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 13555{
50e03d47 13556 bfd *obfd = info->output_bfd;
104d59d1
JM		 13557 obj_attribute *in_attr;
13558 obj_attribute *out_attr;
ee065d83
PB		 13559 /* Some tags have 0 = don't care, 1 = strong requirement,
13560 2 = weak requirement. */
91e22acd 13561 static const int order_021[3] = {0, 2, 1};
ee065d83 13562 int i;
91e22acd 13563 bfd_boolean result = TRUE;
9274e9de 13564 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13565
3e6b1042
DJ		 13566 /* Skip the linker stubs file. This preserves previous behavior
13567 of accepting unknown attributes in the first input file - but
13568 is that a bug? */
13569 if (ibfd->flags & BFD_LINKER_CREATED)
13570 return TRUE;
13571
9274e9de
TG		 13572 /* Skip any input that hasn't attribute section.
13573 This enables to link object files without attribute section with
13574 any others. */
13575 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13576 return TRUE;
13577
104d59d1 13578 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13579 {
13580 /* This is the first object. Copy the attributes. */
104d59d1 13581 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13582
cd21e546
MGD		 13583 out_attr = elf_known_obj_attributes_proc (obfd);
13584
004ae526
PB		 13585 /* Use the Tag_null value to indicate the attributes have been
13586 initialized. */
cd21e546 13587 out_attr[0].i = 1;
004ae526 13588
cd21e546
MGD		 13589 /* We do not output objects with Tag_MPextension_use_legacy - we move
13590 the attribute's value to Tag_MPextension_use. */
13591 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13592 {
13593 if (out_attr[Tag_MPextension_use].i != 0
13594 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13595 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13596 {
13597 _bfd_error_handler
871b3ab2 13598 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 13599 "Tag_MPextension_use attributes"), ibfd);
13600 result = FALSE;
13601 }
13602
13603 out_attr[Tag_MPextension_use] =
13604 out_attr[Tag_MPextension_use_legacy];
13605 out_attr[Tag_MPextension_use_legacy].type = 0;
13606 out_attr[Tag_MPextension_use_legacy].i = 0;
13607 }
13608
13609 return result;
ee065d83
PB		 13610 }
13611
104d59d1
JM		 13612 in_attr = elf_known_obj_attributes_proc (ibfd);
13613 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13614 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13615 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13616 {
5c294fee
TG		 13617 /* Ignore mismatches if the object doesn't use floating point or is
13618 floating point ABI independent. */
13619 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13620 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13621 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13622 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13623 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13624 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13625 {
13626 _bfd_error_handler
871b3ab2 13627 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 13628 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13629 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13630 result = FALSE;
ee065d83
PB		 13631 }
13632 }
13633
3de4a297 13634 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13635 {
13636 /* Merge this attribute with existing attributes. */
13637 switch (i)
13638 {
13639 case Tag_CPU_raw_name:
13640 case Tag_CPU_name:
6a631e86 13641 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13642 break;
13643
13644 case Tag_ABI_optimization_goals:
13645 case Tag_ABI_FP_optimization_goals:
13646 /* Use the first value seen. */
13647 break;
13648
13649 case Tag_CPU_arch:
91e22acd
AS		 13650 {
13651 int secondary_compat = -1, secondary_compat_out = -1;
13652 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13653 int arch_attr;
13654 static const char *name_table[] =
13655 {
91e22acd
AS		 13656 /* These aren't real CPU names, but we can't guess
13657 that from the architecture version alone. */
13658 "Pre v4",
13659 "ARM v4",
13660 "ARM v4T",
13661 "ARM v5T",
13662 "ARM v5TE",
13663 "ARM v5TEJ",
13664 "ARM v6",
13665 "ARM v6KZ",
13666 "ARM v6T2",
13667 "ARM v6K",
13668 "ARM v7",
13669 "ARM v6-M",
bca38921 13670 "ARM v6S-M",
2fd158eb
TP		 13671 "ARM v8",
13672 "",
13673 "ARM v8-M.baseline",
13674 "ARM v8-M.mainline",
91e22acd
AS		 13675 };
13676
13677 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13678 secondary_compat = get_secondary_compatible_arch (ibfd);
13679 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13680 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13681 &secondary_compat_out,
13682 in_attr[i].i,
13683 secondary_compat);
13684
13685 /* Return with error if failed to merge. */
13686 if (arch_attr == -1)
13687 return FALSE;
13688
13689 out_attr[i].i = arch_attr;
13690
91e22acd
AS		 13691 set_secondary_compatible_arch (obfd, secondary_compat_out);
13692
13693 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13694 if (out_attr[i].i == saved_out_attr)
13695 ; /* Leave the names alone. */
13696 else if (out_attr[i].i == in_attr[i].i)
13697 {
13698 /* The output architecture has been changed to match the
13699 input architecture. Use the input names. */
13700 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13701 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13702 : NULL;
13703 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13704 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13705 : NULL;
13706 }
13707 else
13708 {
13709 out_attr[Tag_CPU_name].s = NULL;
13710 out_attr[Tag_CPU_raw_name].s = NULL;
13711 }
13712
13713 /* If we still don't have a value for Tag_CPU_name,
13714 make one up now. Tag_CPU_raw_name remains blank. */
13715 if (out_attr[Tag_CPU_name].s == NULL
13716 && out_attr[i].i < ARRAY_SIZE (name_table))
13717 out_attr[Tag_CPU_name].s =
13718 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13719 }
13720 break;
13721
ee065d83
PB		 13722 case Tag_ARM_ISA_use:
13723 case Tag_THUMB_ISA_use:
ee065d83 13724 case Tag_WMMX_arch:
91e22acd
AS		 13725 case Tag_Advanced_SIMD_arch:
13726 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13727 case Tag_ABI_FP_rounding:
ee065d83
PB		 13728 case Tag_ABI_FP_exceptions:
13729 case Tag_ABI_FP_user_exceptions:
13730 case Tag_ABI_FP_number_model:
75375b3e 13731 case Tag_FP_HP_extension:
91e22acd
AS		 13732 case Tag_CPU_unaligned_access:
13733 case Tag_T2EE_use:
91e22acd 13734 case Tag_MPextension_use:
ee065d83
PB		 13735 /* Use the largest value specified. */
13736 if (in_attr[i].i > out_attr[i].i)
13737 out_attr[i].i = in_attr[i].i;
13738 break;
13739
75375b3e 13740 case Tag_ABI_align_preserved:
91e22acd
AS		 13741 case Tag_ABI_PCS_RO_data:
13742 /* Use the smallest value specified. */
13743 if (in_attr[i].i < out_attr[i].i)
13744 out_attr[i].i = in_attr[i].i;
13745 break;
13746
75375b3e 13747 case Tag_ABI_align_needed:
91e22acd 13748 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13749 && (in_attr[Tag_ABI_align_preserved].i == 0
13750 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13751 {
91e22acd
AS		 13752 /* This error message should be enabled once all non-conformant
13753 binaries in the toolchain have had the attributes set
13754 properly.
ee065d83 13755 _bfd_error_handler
871b3ab2 13756 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 13757 obfd, ibfd);
13758 result = FALSE; */
ee065d83 13759 }
91e22acd
AS		 13760 /* Fall through. */
13761 case Tag_ABI_FP_denormal:
13762 case Tag_ABI_PCS_GOT_use:
13763 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13764 value if greater than 2 (for future-proofing). */
13765 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13766 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13767 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13768 out_attr[i].i = in_attr[i].i;
13769 break;
91e22acd 13770
75375b3e
MGD		 13771 case Tag_Virtualization_use:
13772 /* The virtualization tag effectively stores two bits of
13773 information: the intended use of TrustZone (in bit 0), and the
13774 intended use of Virtualization (in bit 1). */
13775 if (out_attr[i].i == 0)
13776 out_attr[i].i = in_attr[i].i;
13777 else if (in_attr[i].i != 0
13778 && in_attr[i].i != out_attr[i].i)
13779 {
13780 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13781 out_attr[i].i = 3;
13782 else
13783 {
13784 _bfd_error_handler
871b3ab2
AM		 13785 (_("error: %pB: unable to merge virtualization attributes "
13786 "with %pB"),
75375b3e
MGD		 13787 obfd, ibfd);
13788 result = FALSE;
13789 }
13790 }
13791 break;
91e22acd
AS		 13792
13793 case Tag_CPU_arch_profile:
13794 if (out_attr[i].i != in_attr[i].i)
13795 {
13796 /* 0 will merge with anything.
13797 'A' and 'S' merge to 'A'.
13798 'R' and 'S' merge to 'R'.
99059e56 13799 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13800 if (out_attr[i].i == 0
13801 || (out_attr[i].i == 'S'
13802 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13803 out_attr[i].i = in_attr[i].i;
13804 else if (in_attr[i].i == 0
13805 || (in_attr[i].i == 'S'
13806 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13807 ; /* Do nothing. */
91e22acd
AS		 13808 else
13809 {
13810 _bfd_error_handler
90b6238f 13811 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 13812 ibfd,
13813 in_attr[i].i ? in_attr[i].i : '0',
13814 out_attr[i].i ? out_attr[i].i : '0');
13815 result = FALSE;
13816 }
13817 }
13818 break;
15afaa63
TP		 13819
13820 case Tag_DSP_extension:
13821 /* No need to change output value if any of:
13822 - pre (<=) ARMv5T input architecture (do not have DSP)
13823 - M input profile not ARMv7E-M and do not have DSP. */
13824 if (in_attr[Tag_CPU_arch].i <= 3
13825 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13826 && in_attr[Tag_CPU_arch].i != 13
13827 && in_attr[i].i == 0))
13828 ; /* Do nothing. */
13829 /* Output value should be 0 if DSP part of architecture, ie.
13830 - post (>=) ARMv5te architecture output
13831 - A, R or S profile output or ARMv7E-M output architecture. */
13832 else if (out_attr[Tag_CPU_arch].i >= 4
13833 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13834 || out_attr[Tag_CPU_arch_profile].i == 'R'
13835 || out_attr[Tag_CPU_arch_profile].i == 'S'
13836 || out_attr[Tag_CPU_arch].i == 13))
13837 out_attr[i].i = 0;
13838 /* Otherwise, DSP instructions are added and not part of output
13839 architecture. */
13840 else
13841 out_attr[i].i = 1;
13842 break;
13843
75375b3e 13844 case Tag_FP_arch:
62f3b8c8 13845 {
4547cb56
NC		 13846 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13847 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13848 when it's 0. It might mean absence of FP hardware if
99654aaf 13849 Tag_FP_arch is zero. */
4547cb56 13850
a715796b 13851#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13852 static const struct
13853 {
13854 int ver;
13855 int regs;
bca38921 13856 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13857 {
13858 {0, 0},
13859 {1, 16},
13860 {2, 16},
13861 {3, 32},
13862 {3, 16},
13863 {4, 32},
bca38921 13864 {4, 16},
a715796b
TG		 13865 {8, 32},
13866 {8, 16}
62f3b8c8
PB		 13867 };
13868 int ver;
13869 int regs;
13870 int newval;
13871
4547cb56
NC		 13872 /* If the output has no requirement about FP hardware,
13873 follow the requirement of the input. */
13874 if (out_attr[i].i == 0)
13875 {
4ec192e6
RE		 13876 /* This assert is still reasonable, we shouldn't
13877 produce the suspicious build attribute
13878 combination (See below for in_attr). */
4547cb56
NC		 13879 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13880 out_attr[i].i = in_attr[i].i;
13881 out_attr[Tag_ABI_HardFP_use].i
13882 = in_attr[Tag_ABI_HardFP_use].i;
13883 break;
13884 }
13885 /* If the input has no requirement about FP hardware, do
13886 nothing. */
13887 else if (in_attr[i].i == 0)
13888 {
4ec192e6
RE		 13889 /* We used to assert that Tag_ABI_HardFP_use was
13890 zero here, but we should never assert when
13891 consuming an object file that has suspicious
13892 build attributes. The single precision variant
13893 of 'no FP architecture' is still 'no FP
13894 architecture', so we just ignore the tag in this
13895 case. */
4547cb56
NC		 13896 break;
13897 }
13898
13899 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13900 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13901
13902 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13903 do nothing. */
13904 if (in_attr[Tag_ABI_HardFP_use].i == 0
13905 && out_attr[Tag_ABI_HardFP_use].i == 0)
13906 ;
13907 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13908 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13909 else if (in_attr[Tag_ABI_HardFP_use].i
13910 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13911 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13912
13913 /* Now we can handle Tag_FP_arch. */
13914
bca38921
MGD		 13915 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13916 pick the biggest. */
13917 if (in_attr[i].i >= VFP_VERSION_COUNT
13918 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13919 {
13920 out_attr[i] = in_attr[i];
13921 break;
13922 }
13923 /* The output uses the superset of input features
13924 (ISA version) and registers. */
13925 ver = vfp_versions[in_attr[i].i].ver;
13926 if (ver < vfp_versions[out_attr[i].i].ver)
13927 ver = vfp_versions[out_attr[i].i].ver;
13928 regs = vfp_versions[in_attr[i].i].regs;
13929 if (regs < vfp_versions[out_attr[i].i].regs)
13930 regs = vfp_versions[out_attr[i].i].regs;
13931 /* This assumes all possible supersets are also a valid
99059e56 13932 options. */
bca38921 13933 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13934 {
13935 if (regs == vfp_versions[newval].regs
13936 && ver == vfp_versions[newval].ver)
13937 break;
13938 }
13939 out_attr[i].i = newval;
13940 }
b1cc4aeb 13941 break;
ee065d83
PB		 13942 case Tag_PCS_config:
13943 if (out_attr[i].i == 0)
13944 out_attr[i].i = in_attr[i].i;
b6009aca 13945 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13946 {
13947 /* It's sometimes ok to mix different configs, so this is only
99059e56 13948 a warning. */
ee065d83 13949 _bfd_error_handler
90b6238f 13950 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 13951 }
13952 break;
13953 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13954 if (in_attr[i].i != out_attr[i].i
13955 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13956 && in_attr[i].i != AEABI_R9_unused)
13957 {
13958 _bfd_error_handler
90b6238f 13959 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 13960 result = FALSE;
ee065d83
PB		 13961 }
13962 if (out_attr[i].i == AEABI_R9_unused)
13963 out_attr[i].i = in_attr[i].i;
13964 break;
13965 case Tag_ABI_PCS_RW_data:
13966 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13967 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13968 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13969 {
13970 _bfd_error_handler
871b3ab2 13971 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 13972 ibfd);
91e22acd 13973 result = FALSE;
ee065d83
PB		 13974 }
13975 /* Use the smallest value specified. */
13976 if (in_attr[i].i < out_attr[i].i)
13977 out_attr[i].i = in_attr[i].i;
13978 break;
ee065d83 13979 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13980 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13981 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13982 {
13983 _bfd_error_handler
871b3ab2 13984 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 13985 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13986 }
a9dc9481 13987 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13988 out_attr[i].i = in_attr[i].i;
13989 break;
ee065d83
PB		 13990 case Tag_ABI_enum_size:
13991 if (in_attr[i].i != AEABI_enum_unused)
13992 {
13993 if (out_attr[i].i == AEABI_enum_unused
13994 || out_attr[i].i == AEABI_enum_forced_wide)
13995 {
13996 /* The existing object is compatible with anything.
13997 Use whatever requirements the new object has. */
13998 out_attr[i].i = in_attr[i].i;
13999 }
14000 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14001 && out_attr[i].i != in_attr[i].i
0ffa91dd 14002 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14003 {
91e22acd 14004 static const char *aeabi_enum_names[] =
bf21ed78 14005 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14006 const char *in_name =
14007 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14008 ? aeabi_enum_names[in_attr[i].i]
14009 : "<unknown>";
14010 const char *out_name =
14011 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14012 ? aeabi_enum_names[out_attr[i].i]
14013 : "<unknown>";
ee065d83 14014 _bfd_error_handler
871b3ab2 14015 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14016 ibfd, in_name, out_name);
ee065d83
PB		 14017 }
14018 }
14019 break;
14020 case Tag_ABI_VFP_args:
14021 /* Aready done. */
14022 break;
14023 case Tag_ABI_WMMX_args:
14024 if (in_attr[i].i != out_attr[i].i)
14025 {
14026 _bfd_error_handler
871b3ab2 14027 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14028 ibfd, obfd);
91e22acd 14029 result = FALSE;
ee065d83
PB		 14030 }
14031 break;
7b86a9fa
AS		 14032 case Tag_compatibility:
14033 /* Merged in target-independent code. */
14034 break;
91e22acd 14035 case Tag_ABI_HardFP_use:
4547cb56 14036 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14037 break;
14038 case Tag_ABI_FP_16bit_format:
14039 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14040 {
14041 if (in_attr[i].i != out_attr[i].i)
14042 {
14043 _bfd_error_handler
871b3ab2 14044 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14045 ibfd, obfd);
14046 result = FALSE;
14047 }
14048 }
14049 if (in_attr[i].i != 0)
14050 out_attr[i].i = in_attr[i].i;
14051 break;
7b86a9fa 14052
cd21e546 14053 case Tag_DIV_use:
ac56ee8f
MGD		 14054 /* A value of zero on input means that the divide instruction may
14055 be used if available in the base architecture as specified via
14056 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14057 the user did not want divide instructions. A value of 2
14058 explicitly means that divide instructions were allowed in ARM
14059 and Thumb state. */
14060 if (in_attr[i].i == out_attr[i].i)
14061 /* Do nothing. */ ;
14062 else if (elf32_arm_attributes_forbid_div (in_attr)
14063 && !elf32_arm_attributes_accept_div (out_attr))
14064 out_attr[i].i = 1;
14065 else if (elf32_arm_attributes_forbid_div (out_attr)
14066 && elf32_arm_attributes_accept_div (in_attr))
14067 out_attr[i].i = in_attr[i].i;
14068 else if (in_attr[i].i == 2)
14069 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14070 break;
14071
14072 case Tag_MPextension_use_legacy:
14073 /* We don't output objects with Tag_MPextension_use_legacy - we
14074 move the value to Tag_MPextension_use. */
14075 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14076 {
14077 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14078 {
14079 _bfd_error_handler
871b3ab2 14080 (_("%pB has both the current and legacy "
b38cadfb 14081 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14082 ibfd);
14083 result = FALSE;
14084 }
14085 }
14086
14087 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14088 out_attr[Tag_MPextension_use] = in_attr[i];
14089
14090 break;
14091
91e22acd 14092 case Tag_nodefaults:
2d0bb761
AS		 14093 /* This tag is set if it exists, but the value is unused (and is
14094 typically zero). We don't actually need to do anything here -
14095 the merge happens automatically when the type flags are merged
14096 below. */
91e22acd
AS		 14097 break;
14098 case Tag_also_compatible_with:
14099 /* Already done in Tag_CPU_arch. */
14100 break;
14101 case Tag_conformance:
14102 /* Keep the attribute if it matches. Throw it away otherwise.
14103 No attribute means no claim to conform. */
14104 if (!in_attr[i].s || !out_attr[i].s
14105 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14106 out_attr[i].s = NULL;
14107 break;
3cfad14c 14108
91e22acd 14109 default:
e8b36cd1
JM		 14110 result
14111 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14112 }
14113
14114 /* If out_attr was copied from in_attr then it won't have a type yet. */
14115 if (in_attr[i].type && !out_attr[i].type)
14116 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14117 }
14118
104d59d1 14119 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14120 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14121 return FALSE;
ee065d83 14122
104d59d1 14123 /* Check for any attributes not known on ARM. */
e8b36cd1 14124 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14125
91e22acd 14126 return result;
252b5132
RH		 14127}
14128
3a4a14e9
PB		 14129
14130/* Return TRUE if the two EABI versions are incompatible. */
14131
14132static bfd_boolean
14133elf32_arm_versions_compatible (unsigned iver, unsigned over)
14134{
14135 /* v4 and v5 are the same spec before and after it was released,
14136 so allow mixing them. */
14137 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14138 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14139 return TRUE;
14140
14141 return (iver == over);
14142}
14143
252b5132
RH		 14144/* Merge backend specific data from an object file to the output
14145 object file when linking. */
9b485d32 14146
b34976b6 14147static bfd_boolean
50e03d47 14148elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14149
9b485d32
NC		 14150/* Display the flags field. */
14151
b34976b6 14152static bfd_boolean
57e8b36a 14153elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14154{
fc830a83
NC		 14155 FILE * file = (FILE *) ptr;
14156 unsigned long flags;
252b5132
RH		 14157
14158 BFD_ASSERT (abfd != NULL && ptr != NULL);
14159
14160 /* Print normal ELF private data. */
14161 _bfd_elf_print_private_bfd_data (abfd, ptr);
14162
fc830a83 14163 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14164 /* Ignore init flag - it may not be set, despite the flags field
14165 containing valid data. */
252b5132 14166
9b485d32 14167 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14168
fc830a83
NC		 14169 switch (EF_ARM_EABI_VERSION (flags))
14170 {
14171 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14172 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14173 official ARM ELF extended ABI. Hence they are only decoded if
14174 the EABI version is not set. */
fd2ec330 14175 if (flags & EF_ARM_INTERWORK)
9b485d32 14176 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14177
fd2ec330 14178 if (flags & EF_ARM_APCS_26)
6c571f00 14179 fprintf (file, " [APCS-26]");
fc830a83 14180 else
6c571f00 14181 fprintf (file, " [APCS-32]");
9a5aca8c 14182
96a846ea
RE		 14183 if (flags & EF_ARM_VFP_FLOAT)
14184 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14185 else if (flags & EF_ARM_MAVERICK_FLOAT)
14186 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14187 else
14188 fprintf (file, _(" [FPA float format]"));
14189
fd2ec330 14190 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14191 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14192
fd2ec330 14193 if (flags & EF_ARM_PIC)
9b485d32 14194 fprintf (file, _(" [position independent]"));
fc830a83 14195
fd2ec330 14196 if (flags & EF_ARM_NEW_ABI)
9b485d32 14197 fprintf (file, _(" [new ABI]"));
9a5aca8c 14198
fd2ec330 14199 if (flags & EF_ARM_OLD_ABI)
9b485d32 14200 fprintf (file, _(" [old ABI]"));
9a5aca8c 14201
fd2ec330 14202 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14203 fprintf (file, _(" [software FP]"));
9a5aca8c 14204
96a846ea
RE		 14205 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14206 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14207 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14208 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14209 break;
9a5aca8c 14210
fc830a83 14211 case EF_ARM_EABI_VER1:
9b485d32 14212 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14213
fc830a83 14214 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14215 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14216 else
9b485d32 14217 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14218
fc830a83
NC		 14219 flags &= ~ EF_ARM_SYMSARESORTED;
14220 break;
9a5aca8c 14221
fd2ec330
PB		 14222 case EF_ARM_EABI_VER2:
14223 fprintf (file, _(" [Version2 EABI]"));
14224
14225 if (flags & EF_ARM_SYMSARESORTED)
14226 fprintf (file, _(" [sorted symbol table]"));
14227 else
14228 fprintf (file, _(" [unsorted symbol table]"));
14229
14230 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14231 fprintf (file, _(" [dynamic symbols use segment index]"));
14232
14233 if (flags & EF_ARM_MAPSYMSFIRST)
14234 fprintf (file, _(" [mapping symbols precede others]"));
14235
99e4ae17 14236 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14237 | EF_ARM_MAPSYMSFIRST);
14238 break;
14239
d507cf36
PB		 14240 case EF_ARM_EABI_VER3:
14241 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14242 break;
14243
14244 case EF_ARM_EABI_VER4:
14245 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14246 goto eabi;
d507cf36 14247
3a4a14e9
PB		 14248 case EF_ARM_EABI_VER5:
14249 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14250
14251 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14252 fprintf (file, _(" [soft-float ABI]"));
14253
14254 if (flags & EF_ARM_ABI_FLOAT_HARD)
14255 fprintf (file, _(" [hard-float ABI]"));
14256
14257 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14258
3a4a14e9 14259 eabi:
d507cf36
PB		 14260 if (flags & EF_ARM_BE8)
14261 fprintf (file, _(" [BE8]"));
14262
14263 if (flags & EF_ARM_LE8)
14264 fprintf (file, _(" [LE8]"));
14265
14266 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14267 break;
14268
fc830a83 14269 default:
9b485d32 14270 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14271 break;
14272 }
252b5132 14273
fc830a83 14274 flags &= ~ EF_ARM_EABIMASK;
252b5132 14275
fc830a83 14276 if (flags & EF_ARM_RELEXEC)
9b485d32 14277 fprintf (file, _(" [relocatable executable]"));
252b5132 14278
a5721edd 14279 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14280
14281 if (flags)
9b485d32 14282 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14283
252b5132
RH		 14284 fputc ('\n', file);
14285
b34976b6 14286 return TRUE;
252b5132
RH		 14287}
14288
14289static int
57e8b36a 14290elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14291{
2f0ca46a
NC		 14292 switch (ELF_ST_TYPE (elf_sym->st_info))
14293 {
14294 case STT_ARM_TFUNC:
14295 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14296
2f0ca46a
NC		 14297 case STT_ARM_16BIT:
14298 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14299 This allows us to distinguish between data used by Thumb instructions
14300 and non-data (which is probably code) inside Thumb regions of an
14301 executable. */
1a0eb693 14302 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14303 return ELF_ST_TYPE (elf_sym->st_info);
14304 break;
9a5aca8c 14305
ce855c42
NC		 14306 default:
14307 break;
2f0ca46a
NC		 14308 }
14309
14310 return type;
252b5132 14311}
f21f3fe0 14312
252b5132 14313static asection *
07adf181
AM		 14314elf32_arm_gc_mark_hook (asection *sec,
14315 struct bfd_link_info *info,
14316 Elf_Internal_Rela *rel,
14317 struct elf_link_hash_entry *h,
14318 Elf_Internal_Sym *sym)
252b5132
RH		 14319{
14320 if (h != NULL)
07adf181 14321 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14322 {
14323 case R_ARM_GNU_VTINHERIT:
14324 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14325 return NULL;
14326 }
9ad5cbcf 14327
07adf181 14328 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14329}
14330
780a67af
NC		 14331/* Look through the relocs for a section during the first phase. */
14332
b34976b6 14333static bfd_boolean
57e8b36a
NC		 14334elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14335 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14336{
b34976b6
AM		 14337 Elf_Internal_Shdr *symtab_hdr;
14338 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14339 const Elf_Internal_Rela *rel;
14340 const Elf_Internal_Rela *rel_end;
14341 bfd *dynobj;
5e681ec4 14342 asection *sreloc;
5e681ec4 14343 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14344 bfd_boolean call_reloc_p;
14345 bfd_boolean may_become_dynamic_p;
14346 bfd_boolean may_need_local_target_p;
ce98a316 14347 unsigned long nsyms;
9a5aca8c 14348
0e1862bb 14349 if (bfd_link_relocatable (info))
b34976b6 14350 return TRUE;
9a5aca8c 14351
0ffa91dd
NC		 14352 BFD_ASSERT (is_arm_elf (abfd));
14353
5e681ec4 14354 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14355 if (htab == NULL)
14356 return FALSE;
14357
5e681ec4 14358 sreloc = NULL;
9a5aca8c 14359
67687978
PB		 14360 /* Create dynamic sections for relocatable executables so that we can
14361 copy relocations. */
14362 if (htab->root.is_relocatable_executable
14363 && ! htab->root.dynamic_sections_created)
14364 {
14365 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14366 return FALSE;
14367 }
14368
cbc704f3
RS		 14369 if (htab->root.dynobj == NULL)
14370 htab->root.dynobj = abfd;
34e77a92
RS		 14371 if (!create_ifunc_sections (info))
14372 return FALSE;
cbc704f3
RS		 14373
14374 dynobj = htab->root.dynobj;
14375
0ffa91dd 14376 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14377 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14378 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14379
252b5132
RH		 14380 rel_end = relocs + sec->reloc_count;
14381 for (rel = relocs; rel < rel_end; rel++)
14382 {
34e77a92 14383 Elf_Internal_Sym *isym;
252b5132 14384 struct elf_link_hash_entry *h;
b7693d02 14385 struct elf32_arm_link_hash_entry *eh;
d42c267e 14386 unsigned int r_symndx;
eb043451 14387 int r_type;
9a5aca8c 14388
252b5132 14389 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14390 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14391 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14392
ce98a316
NC		 14393 if (r_symndx >= nsyms
14394 /* PR 9934: It is possible to have relocations that do not
14395 refer to symbols, thus it is also possible to have an
14396 object file containing relocations but no symbol table. */
cf35638d 14397 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14398 {
871b3ab2 14399 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 14400 r_symndx);
ba93b8ac
DJ		 14401 return FALSE;
14402 }
14403
34e77a92
RS		 14404 h = NULL;
14405 isym = NULL;
14406 if (nsyms > 0)
973a3492 14407 {
34e77a92
RS		 14408 if (r_symndx < symtab_hdr->sh_info)
14409 {
14410 /* A local symbol. */
14411 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14412 abfd, r_symndx);
14413 if (isym == NULL)
14414 return FALSE;
14415 }
14416 else
14417 {
14418 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14419 while (h->root.type == bfd_link_hash_indirect
14420 || h->root.type == bfd_link_hash_warning)
14421 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14422 }
973a3492 14423 }
9a5aca8c 14424
b7693d02
DJ		 14425 eh = (struct elf32_arm_link_hash_entry *) h;
14426
f6e32f6d
RS		 14427 call_reloc_p = FALSE;
14428 may_become_dynamic_p = FALSE;
14429 may_need_local_target_p = FALSE;
14430
0855e32b
NS		 14431 /* Could be done earlier, if h were already available. */
14432 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14433 switch (r_type)
99059e56 14434 {
5e681ec4 14435 case R_ARM_GOT32:
eb043451 14436 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14437 case R_ARM_TLS_GD32:
14438 case R_ARM_TLS_IE32:
0855e32b
NS		 14439 case R_ARM_TLS_GOTDESC:
14440 case R_ARM_TLS_DESCSEQ:
14441 case R_ARM_THM_TLS_DESCSEQ:
14442 case R_ARM_TLS_CALL:
14443 case R_ARM_THM_TLS_CALL:
5e681ec4 14444 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14445 {
14446 int tls_type, old_tls_type;
5e681ec4 14447
ba93b8ac
DJ		 14448 switch (r_type)
14449 {
14450 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14451
ba93b8ac 14452 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14453
0855e32b
NS		 14454 case R_ARM_TLS_GOTDESC:
14455 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14456 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14457 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14458
ba93b8ac
DJ		 14459 default: tls_type = GOT_NORMAL; break;
14460 }
252b5132 14461
0e1862bb 14462 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14463 info->flags |= DF_STATIC_TLS;
14464
ba93b8ac
DJ		 14465 if (h != NULL)
14466 {
14467 h->got.refcount++;
14468 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14469 }
14470 else
14471 {
ba93b8ac 14472 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14473 if (!elf32_arm_allocate_local_sym_info (abfd))
14474 return FALSE;
14475 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14476 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14477 }
14478
0855e32b 14479 /* If a variable is accessed with both tls methods, two
99059e56 14480 slots may be created. */
0855e32b
NS		 14481 if (GOT_TLS_GD_ANY_P (old_tls_type)
14482 && GOT_TLS_GD_ANY_P (tls_type))
14483 tls_type |= old_tls_type;
14484
14485 /* We will already have issued an error message if there
14486 is a TLS/non-TLS mismatch, based on the symbol
14487 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14488 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14489 && tls_type != GOT_NORMAL)
14490 tls_type |= old_tls_type;
14491
0855e32b 14492 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14493 method, we're able to relax. Turn off the GDESC flag,
14494 without messing up with any other kind of tls types
6a631e86 14495 that may be involved. */
0855e32b
NS		 14496 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14497 tls_type &= ~GOT_TLS_GDESC;
14498
ba93b8ac
DJ		 14499 if (old_tls_type != tls_type)
14500 {
14501 if (h != NULL)
14502 elf32_arm_hash_entry (h)->tls_type = tls_type;
14503 else
14504 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14505 }
14506 }
8029a119 14507 /* Fall through. */
ba93b8ac
DJ		 14508
14509 case R_ARM_TLS_LDM32:
14510 if (r_type == R_ARM_TLS_LDM32)
14511 htab->tls_ldm_got.refcount++;
8029a119 14512 /* Fall through. */
252b5132 14513
c19d1205 14514 case R_ARM_GOTOFF32:
5e681ec4 14515 case R_ARM_GOTPC:
cbc704f3
RS		 14516 if (htab->root.sgot == NULL
14517 && !create_got_section (htab->root.dynobj, info))
14518 return FALSE;
252b5132
RH		 14519 break;
14520
252b5132 14521 case R_ARM_PC24:
7359ea65 14522 case R_ARM_PLT32:
5b5bb741
PB		 14523 case R_ARM_CALL:
14524 case R_ARM_JUMP24:
eb043451 14525 case R_ARM_PREL31:
c19d1205 14526 case R_ARM_THM_CALL:
bd97cb95
DJ		 14527 case R_ARM_THM_JUMP24:
14528 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14529 call_reloc_p = TRUE;
14530 may_need_local_target_p = TRUE;
14531 break;
14532
14533 case R_ARM_ABS12:
14534 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14535 ldr __GOTT_INDEX__ offsets. */
14536 if (!htab->vxworks_p)
14537 {
14538 may_need_local_target_p = TRUE;
14539 break;
14540 }
aebf9be7 14541 else goto jump_over;
9eaff861 14542
f6e32f6d 14543 /* Fall through. */
39623e12 14544
96c23d59
JM		 14545 case R_ARM_MOVW_ABS_NC:
14546 case R_ARM_MOVT_ABS:
14547 case R_ARM_THM_MOVW_ABS_NC:
14548 case R_ARM_THM_MOVT_ABS:
0e1862bb 14549 if (bfd_link_pic (info))
96c23d59 14550 {
4eca0228 14551 _bfd_error_handler
871b3ab2 14552 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 14553 abfd, elf32_arm_howto_table_1[r_type].name,
14554 (h) ? h->root.root.string : "a local symbol");
14555 bfd_set_error (bfd_error_bad_value);
14556 return FALSE;
14557 }
14558
14559 /* Fall through. */
39623e12
PB		 14560 case R_ARM_ABS32:
14561 case R_ARM_ABS32_NOI:
aebf9be7 14562 jump_over:
0e1862bb 14563 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14564 {
14565 h->pointer_equality_needed = 1;
14566 }
14567 /* Fall through. */
39623e12
PB		 14568 case R_ARM_REL32:
14569 case R_ARM_REL32_NOI:
b6895b4f
PB		 14570 case R_ARM_MOVW_PREL_NC:
14571 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14572 case R_ARM_THM_MOVW_PREL_NC:
14573 case R_ARM_THM_MOVT_PREL:
39623e12 14574
b7693d02 14575 /* Should the interworking branches be listed here? */
0e1862bb 14576 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14577 && (sec->flags & SEC_ALLOC) != 0)
14578 {
14579 if (h == NULL
469a3493 14580 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14581 {
14582 /* In shared libraries and relocatable executables,
14583 we treat local relative references as calls;
14584 see the related SYMBOL_CALLS_LOCAL code in
14585 allocate_dynrelocs. */
14586 call_reloc_p = TRUE;
14587 may_need_local_target_p = TRUE;
14588 }
14589 else
14590 /* We are creating a shared library or relocatable
14591 executable, and this is a reloc against a global symbol,
14592 or a non-PC-relative reloc against a local symbol.
14593 We may need to copy the reloc into the output. */
14594 may_become_dynamic_p = TRUE;
14595 }
f6e32f6d
RS		 14596 else
14597 may_need_local_target_p = TRUE;
252b5132
RH		 14598 break;
14599
99059e56
RM		 14600 /* This relocation describes the C++ object vtable hierarchy.
14601 Reconstruct it for later use during GC. */
14602 case R_ARM_GNU_VTINHERIT:
14603 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14604 return FALSE;
14605 break;
14606
14607 /* This relocation describes which C++ vtable entries are actually
14608 used. Record for later use during GC. */
14609 case R_ARM_GNU_VTENTRY:
14610 BFD_ASSERT (h != NULL);
14611 if (h != NULL
14612 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14613 return FALSE;
14614 break;
14615 }
f6e32f6d
RS		 14616
14617 if (h != NULL)
14618 {
14619 if (call_reloc_p)
14620 /* We may need a .plt entry if the function this reloc
14621 refers to is in a different object, regardless of the
14622 symbol's type. We can't tell for sure yet, because
14623 something later might force the symbol local. */
14624 h->needs_plt = 1;
14625 else if (may_need_local_target_p)
14626 /* If this reloc is in a read-only section, we might
14627 need a copy reloc. We can't check reliably at this
14628 stage whether the section is read-only, as input
14629 sections have not yet been mapped to output sections.
14630 Tentatively set the flag for now, and correct in
14631 adjust_dynamic_symbol. */
14632 h->non_got_ref = 1;
14633 }
14634
34e77a92
RS		 14635 if (may_need_local_target_p
14636 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14637 {
34e77a92
RS		 14638 union gotplt_union *root_plt;
14639 struct arm_plt_info *arm_plt;
14640 struct arm_local_iplt_info *local_iplt;
14641
14642 if (h != NULL)
14643 {
14644 root_plt = &h->plt;
14645 arm_plt = &eh->plt;
14646 }
14647 else
14648 {
14649 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14650 if (local_iplt == NULL)
14651 return FALSE;
14652 root_plt = &local_iplt->root;
14653 arm_plt = &local_iplt->arm;
14654 }
14655
f6e32f6d
RS		 14656 /* If the symbol is a function that doesn't bind locally,
14657 this relocation will need a PLT entry. */
a8c887dd
NC		 14658 if (root_plt->refcount != -1)
14659 root_plt->refcount += 1;
34e77a92
RS		 14660
14661 if (!call_reloc_p)
14662 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14663
14664 /* It's too early to use htab->use_blx here, so we have to
14665 record possible blx references separately from
14666 relocs that definitely need a thumb stub. */
14667
14668 if (r_type == R_ARM_THM_CALL)
34e77a92 14669 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14670
14671 if (r_type == R_ARM_THM_JUMP24
14672 || r_type == R_ARM_THM_JUMP19)
34e77a92 14673 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14674 }
14675
14676 if (may_become_dynamic_p)
14677 {
14678 struct elf_dyn_relocs *p, **head;
14679
14680 /* Create a reloc section in dynobj. */
14681 if (sreloc == NULL)
14682 {
14683 sreloc = _bfd_elf_make_dynamic_reloc_section
14684 (sec, dynobj, 2, abfd, ! htab->use_rel);
14685
14686 if (sreloc == NULL)
14687 return FALSE;
14688
14689 /* BPABI objects never have dynamic relocations mapped. */
14690 if (htab->symbian_p)
14691 {
14692 flagword flags;
14693
14694 flags = bfd_get_section_flags (dynobj, sreloc);
14695 flags &= ~(SEC_LOAD | SEC_ALLOC);
14696 bfd_set_section_flags (dynobj, sreloc, flags);
14697 }
14698 }
14699
14700 /* If this is a global symbol, count the number of
14701 relocations we need for this symbol. */
14702 if (h != NULL)
14703 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14704 else
14705 {
34e77a92
RS		 14706 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14707 if (head == NULL)
f6e32f6d 14708 return FALSE;
f6e32f6d
RS		 14709 }
14710
14711 p = *head;
14712 if (p == NULL || p->sec != sec)
14713 {
14714 bfd_size_type amt = sizeof *p;
14715
14716 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14717 if (p == NULL)
14718 return FALSE;
14719 p->next = *head;
14720 *head = p;
14721 p->sec = sec;
14722 p->count = 0;
14723 p->pc_count = 0;
14724 }
14725
469a3493 14726 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14727 p->pc_count += 1;
14728 p->count += 1;
14729 }
252b5132 14730 }
f21f3fe0 14731
b34976b6 14732 return TRUE;
252b5132
RH		 14733}
14734
9eaff861
AO		 14735static void
14736elf32_arm_update_relocs (asection *o,
14737 struct bfd_elf_section_reloc_data *reldata)
14738{
14739 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14740 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14741 const struct elf_backend_data *bed;
14742 _arm_elf_section_data *eado;
14743 struct bfd_link_order *p;
14744 bfd_byte *erela_head, *erela;
14745 Elf_Internal_Rela *irela_head, *irela;
14746 Elf_Internal_Shdr *rel_hdr;
14747 bfd *abfd;
14748 unsigned int count;
14749
14750 eado = get_arm_elf_section_data (o);
14751
14752 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14753 return;
14754
14755 abfd = o->owner;
14756 bed = get_elf_backend_data (abfd);
14757 rel_hdr = reldata->hdr;
14758
14759 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14760 {
14761 swap_in = bed->s->swap_reloc_in;
14762 swap_out = bed->s->swap_reloc_out;
14763 }
14764 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14765 {
14766 swap_in = bed->s->swap_reloca_in;
14767 swap_out = bed->s->swap_reloca_out;
14768 }
14769 else
14770 abort ();
14771
14772 erela_head = rel_hdr->contents;
14773 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14774 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14775
14776 erela = erela_head;
14777 irela = irela_head;
14778 count = 0;
14779
14780 for (p = o->map_head.link_order; p; p = p->next)
14781 {
14782 if (p->type == bfd_section_reloc_link_order
14783 || p->type == bfd_symbol_reloc_link_order)
14784 {
14785 (*swap_in) (abfd, erela, irela);
14786 erela += rel_hdr->sh_entsize;
14787 irela++;
14788 count++;
14789 }
14790 else if (p->type == bfd_indirect_link_order)
14791 {
14792 struct bfd_elf_section_reloc_data *input_reldata;
14793 arm_unwind_table_edit *edit_list, *edit_tail;
14794 _arm_elf_section_data *eadi;
14795 bfd_size_type j;
14796 bfd_vma offset;
14797 asection *i;
14798
14799 i = p->u.indirect.section;
14800
14801 eadi = get_arm_elf_section_data (i);
14802 edit_list = eadi->u.exidx.unwind_edit_list;
14803 edit_tail = eadi->u.exidx.unwind_edit_tail;
14804 offset = o->vma + i->output_offset;
14805
14806 if (eadi->elf.rel.hdr &&
14807 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14808 input_reldata = &eadi->elf.rel;
14809 else if (eadi->elf.rela.hdr &&
14810 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14811 input_reldata = &eadi->elf.rela;
14812 else
14813 abort ();
14814
14815 if (edit_list)
14816 {
14817 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14818 {
14819 arm_unwind_table_edit *edit_node, *edit_next;
14820 bfd_vma bias;
c48182bf 14821 bfd_vma reloc_index;
9eaff861
AO		 14822
14823 (*swap_in) (abfd, erela, irela);
c48182bf 14824 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 14825
14826 bias = 0;
14827 edit_node = edit_list;
14828 for (edit_next = edit_list;
c48182bf 14829 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 14830 edit_next = edit_node->next)
14831 {
14832 bias++;
14833 edit_node = edit_next;
14834 }
14835
14836 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 14837 || edit_node->index != reloc_index)
9eaff861
AO		 14838 {
14839 irela->r_offset -= bias * 8;
14840 irela++;
14841 count++;
14842 }
14843
14844 erela += rel_hdr->sh_entsize;
14845 }
14846
14847 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
14848 {
14849 /* New relocation entity. */
14850 asection *text_sec = edit_tail->linked_section;
14851 asection *text_out = text_sec->output_section;
14852 bfd_vma exidx_offset = offset + i->size - 8;
14853
14854 irela->r_addend = 0;
14855 irela->r_offset = exidx_offset;
14856 irela->r_info = ELF32_R_INFO
14857 (text_out->target_index, R_ARM_PREL31);
14858 irela++;
14859 count++;
14860 }
14861 }
14862 else
14863 {
14864 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14865 {
14866 (*swap_in) (abfd, erela, irela);
14867 erela += rel_hdr->sh_entsize;
14868 irela++;
14869 }
14870
14871 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
14872 }
14873 }
14874 }
14875
14876 reldata->count = count;
14877 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
14878
14879 erela = erela_head;
14880 irela = irela_head;
14881 while (count > 0)
14882 {
14883 (*swap_out) (abfd, irela, erela);
14884 erela += rel_hdr->sh_entsize;
14885 irela++;
14886 count--;
14887 }
14888
14889 free (irela_head);
14890
14891 /* Hashes are no longer valid. */
14892 free (reldata->hashes);
14893 reldata->hashes = NULL;
14894}
14895
6a5bb875 14896/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 14897 required if the corresponding code section is marked. Similarly, ARMv8-M
14898 secure entry functions can only be referenced by SG veneers which are
14899 created after the GC process. They need to be marked in case they reside in
14900 their own section (as would be the case if code was compiled with
14901 -ffunction-sections). */
6a5bb875
PB		 14902
14903static bfd_boolean
906e58ca
NC		 14904elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
14905 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 14906{
14907 bfd *sub;
14908 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 14909 asection *cmse_sec;
14910 obj_attribute *out_attr;
14911 Elf_Internal_Shdr *symtab_hdr;
14912 unsigned i, sym_count, ext_start;
14913 const struct elf_backend_data *bed;
14914 struct elf_link_hash_entry **sym_hashes;
14915 struct elf32_arm_link_hash_entry *cmse_hash;
14916 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 14917
7f6ab9f8
AM		 14918 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
14919
4ba2ef8f
TP		 14920 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
14921 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
14922 && out_attr[Tag_CPU_arch_profile].i == 'M';
14923
6a5bb875
PB		 14924 /* Marking EH data may cause additional code sections to be marked,
14925 requiring multiple passes. */
14926 again = TRUE;
14927 while (again)
14928 {
14929 again = FALSE;
c72f2fb2 14930 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 14931 {
14932 asection *o;
14933
0ffa91dd 14934 if (! is_arm_elf (sub))
6a5bb875
PB		 14935 continue;
14936
14937 elf_shdrp = elf_elfsections (sub);
14938 for (o = sub->sections; o != NULL; o = o->next)
14939 {
14940 Elf_Internal_Shdr *hdr;
0ffa91dd 14941
6a5bb875 14942 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 14943 if (hdr->sh_type == SHT_ARM_EXIDX
14944 && hdr->sh_link
14945 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 14946 && !o->gc_mark
14947 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
14948 {
14949 again = TRUE;
14950 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
14951 return FALSE;
14952 }
14953 }
4ba2ef8f
TP		 14954
14955 /* Mark section holding ARMv8-M secure entry functions. We mark all
14956 of them so no need for a second browsing. */
14957 if (is_v8m && first_bfd_browse)
14958 {
14959 sym_hashes = elf_sym_hashes (sub);
14960 bed = get_elf_backend_data (sub);
14961 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
14962 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
14963 ext_start = symtab_hdr->sh_info;
14964
14965 /* Scan symbols. */
14966 for (i = ext_start; i < sym_count; i++)
14967 {
14968 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
14969
14970 /* Assume it is a special symbol. If not, cmse_scan will
14971 warn about it and user can do something about it. */
14972 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
14973 {
14974 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 14975 if (!cmse_sec->gc_mark
14976 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 14977 return FALSE;
14978 }
14979 }
14980 }
6a5bb875 14981 }
4ba2ef8f 14982 first_bfd_browse = FALSE;
6a5bb875
PB		 14983 }
14984
14985 return TRUE;
14986}
14987
3c9458e9
NC		 14988/* Treat mapping symbols as special target symbols. */
14989
14990static bfd_boolean
14991elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
14992{
b0796911
PB		 14993 return bfd_is_arm_special_symbol_name (sym->name,
14994 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 14995}
14996
0367ecfb
NC		 14997/* This is a copy of elf_find_function() from elf.c except that
14998 ARM mapping symbols are ignored when looking for function names
14999 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15000
0367ecfb 15001static bfd_boolean
07d6d2b8 15002arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15003 asymbol ** symbols,
fb167eb2 15004 asection * section,
07d6d2b8 15005 bfd_vma offset,
0367ecfb
NC		 15006 const char ** filename_ptr,
15007 const char ** functionname_ptr)
15008{
15009 const char * filename = NULL;
15010 asymbol * func = NULL;
15011 bfd_vma low_func = 0;
15012 asymbol ** p;
252b5132
RH		 15013
15014 for (p = symbols; *p != NULL; p++)
15015 {
15016 elf_symbol_type *q;
15017
15018 q = (elf_symbol_type *) *p;
15019
252b5132
RH		 15020 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15021 {
15022 default:
15023 break;
15024 case STT_FILE:
15025 filename = bfd_asymbol_name (&q->symbol);
15026 break;
252b5132
RH		 15027 case STT_FUNC:
15028 case STT_ARM_TFUNC:
9d2da7ca 15029 case STT_NOTYPE:
b0796911 15030 /* Skip mapping symbols. */
0367ecfb 15031 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15032 && bfd_is_arm_special_symbol_name (q->symbol.name,
15033 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15034 continue;
15035 /* Fall through. */
6b40fcba 15036 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15037 && q->symbol.value >= low_func
15038 && q->symbol.value <= offset)
15039 {
15040 func = (asymbol *) q;
15041 low_func = q->symbol.value;
15042 }
15043 break;
15044 }
15045 }
15046
15047 if (func == NULL)
b34976b6 15048 return FALSE;
252b5132 15049
0367ecfb
NC		 15050 if (filename_ptr)
15051 *filename_ptr = filename;
15052 if (functionname_ptr)
15053 *functionname_ptr = bfd_asymbol_name (func);
15054
15055 return TRUE;
906e58ca 15056}
0367ecfb
NC		 15057
15058
15059/* Find the nearest line to a particular section and offset, for error
15060 reporting. This code is a duplicate of the code in elf.c, except
15061 that it uses arm_elf_find_function. */
15062
15063static bfd_boolean
07d6d2b8
AM		 15064elf32_arm_find_nearest_line (bfd * abfd,
15065 asymbol ** symbols,
15066 asection * section,
15067 bfd_vma offset,
0367ecfb
NC		 15068 const char ** filename_ptr,
15069 const char ** functionname_ptr,
fb167eb2
AM		 15070 unsigned int * line_ptr,
15071 unsigned int * discriminator_ptr)
0367ecfb
NC		 15072{
15073 bfd_boolean found = FALSE;
15074
fb167eb2 15075 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15076 filename_ptr, functionname_ptr,
fb167eb2
AM		 15077 line_ptr, discriminator_ptr,
15078 dwarf_debug_sections, 0,
0367ecfb
NC		 15079 & elf_tdata (abfd)->dwarf2_find_line_info))
15080 {
15081 if (!*functionname_ptr)
fb167eb2 15082 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15083 *filename_ptr ? NULL : filename_ptr,
15084 functionname_ptr);
f21f3fe0 15085
0367ecfb
NC		 15086 return TRUE;
15087 }
15088
fb167eb2
AM		 15089 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15090 uses DWARF1. */
15091
0367ecfb
NC		 15092 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15093 & found, filename_ptr,
15094 functionname_ptr, line_ptr,
15095 & elf_tdata (abfd)->line_info))
15096 return FALSE;
15097
15098 if (found && (*functionname_ptr || *line_ptr))
15099 return TRUE;
15100
15101 if (symbols == NULL)
15102 return FALSE;
15103
fb167eb2 15104 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15105 filename_ptr, functionname_ptr))
15106 return FALSE;
15107
15108 *line_ptr = 0;
b34976b6 15109 return TRUE;
252b5132
RH		 15110}
15111
4ab527b0 15112static bfd_boolean
07d6d2b8 15113elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 15114 const char ** filename_ptr,
15115 const char ** functionname_ptr,
15116 unsigned int * line_ptr)
15117{
15118 bfd_boolean found;
15119 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15120 functionname_ptr, line_ptr,
15121 & elf_tdata (abfd)->dwarf2_find_line_info);
15122 return found;
15123}
15124
63c1f59d
AM		 15125/* Find dynamic relocs for H that apply to read-only sections. */
15126
15127static asection *
15128readonly_dynrelocs (struct elf_link_hash_entry *h)
15129{
15130 struct elf_dyn_relocs *p;
15131
15132 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
15133 {
15134 asection *s = p->sec->output_section;
15135
15136 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15137 return p->sec;
15138 }
15139 return NULL;
15140}
15141
252b5132
RH		 15142/* Adjust a symbol defined by a dynamic object and referenced by a
15143 regular object. The current definition is in some section of the
15144 dynamic object, but we're not including those sections. We have to
15145 change the definition to something the rest of the link can
15146 understand. */
15147
b34976b6 15148static bfd_boolean
57e8b36a
NC		 15149elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15150 struct elf_link_hash_entry * h)
252b5132
RH		 15151{
15152 bfd * dynobj;
5474d94f 15153 asection *s, *srel;
b7693d02 15154 struct elf32_arm_link_hash_entry * eh;
67687978 15155 struct elf32_arm_link_hash_table *globals;
252b5132 15156
67687978 15157 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15158 if (globals == NULL)
15159 return FALSE;
15160
252b5132
RH		 15161 dynobj = elf_hash_table (info)->dynobj;
15162
15163 /* Make sure we know what is going on here. */
15164 BFD_ASSERT (dynobj != NULL
f5385ebf 15165 && (h->needs_plt
34e77a92 15166 || h->type == STT_GNU_IFUNC
60d67dc8 15167 || h->is_weakalias
f5385ebf
AM		 15168 || (h->def_dynamic
15169 && h->ref_regular
15170 && !h->def_regular)));
252b5132 15171
b7693d02
DJ		 15172 eh = (struct elf32_arm_link_hash_entry *) h;
15173
252b5132
RH		 15174 /* If this is a function, put it in the procedure linkage table. We
15175 will fill in the contents of the procedure linkage table later,
15176 when we know the address of the .got section. */
34e77a92 15177 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15178 {
34e77a92
RS		 15179 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15180 symbol binds locally. */
5e681ec4 15181 if (h->plt.refcount <= 0
34e77a92
RS		 15182 || (h->type != STT_GNU_IFUNC
15183 && (SYMBOL_CALLS_LOCAL (info, h)
15184 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15185 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15186 {
15187 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15188 file, but the symbol was never referred to by a dynamic
15189 object, or if all references were garbage collected. In
15190 such a case, we don't actually need to build a procedure
15191 linkage table, and we can just do a PC24 reloc instead. */
15192 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15193 eh->plt.thumb_refcount = 0;
15194 eh->plt.maybe_thumb_refcount = 0;
15195 eh->plt.noncall_refcount = 0;
f5385ebf 15196 h->needs_plt = 0;
252b5132
RH		 15197 }
15198
b34976b6 15199 return TRUE;
252b5132 15200 }
5e681ec4 15201 else
b7693d02
DJ		 15202 {
15203 /* It's possible that we incorrectly decided a .plt reloc was
15204 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15205 in check_relocs. We can't decide accurately between function
15206 and non-function syms in check-relocs; Objects loaded later in
15207 the link may change h->type. So fix it now. */
15208 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15209 eh->plt.thumb_refcount = 0;
15210 eh->plt.maybe_thumb_refcount = 0;
15211 eh->plt.noncall_refcount = 0;
b7693d02 15212 }
252b5132
RH		 15213
15214 /* If this is a weak symbol, and there is a real definition, the
15215 processor independent code will have arranged for us to see the
15216 real definition first, and we can just use the same value. */
60d67dc8 15217 if (h->is_weakalias)
252b5132 15218 {
60d67dc8
AM		 15219 struct elf_link_hash_entry *def = weakdef (h);
15220 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
15221 h->root.u.def.section = def->root.u.def.section;
15222 h->root.u.def.value = def->root.u.def.value;
b34976b6 15223 return TRUE;
252b5132
RH		 15224 }
15225
ba93b8ac
DJ		 15226 /* If there are no non-GOT references, we do not need a copy
15227 relocation. */
15228 if (!h->non_got_ref)
15229 return TRUE;
15230
252b5132
RH		 15231 /* This is a reference to a symbol defined by a dynamic object which
15232 is not a function. */
15233
15234 /* If we are creating a shared library, we must presume that the
15235 only references to the symbol are via the global offset table.
15236 For such cases we need not do anything here; the relocations will
67687978
PB		 15237 be handled correctly by relocate_section. Relocatable executables
15238 can reference data in shared objects directly, so we don't need to
15239 do anything here. */
0e1862bb 15240 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15241 return TRUE;
252b5132
RH		 15242
15243 /* We must allocate the symbol in our .dynbss section, which will
15244 become part of the .bss section of the executable. There will be
15245 an entry for this symbol in the .dynsym section. The dynamic
15246 object will contain position independent code, so all references
15247 from the dynamic object to this symbol will go through the global
15248 offset table. The dynamic linker will use the .dynsym entry to
15249 determine the address it must put in the global offset table, so
15250 both the dynamic object and the regular object will refer to the
15251 same memory location for the variable. */
5522f910
NC		 15252 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15253 linker to copy the initial value out of the dynamic object and into
15254 the runtime process image. We need to remember the offset into the
00a97672 15255 .rel(a).bss section we are going to use. */
5474d94f
AM		 15256 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
15257 {
15258 s = globals->root.sdynrelro;
15259 srel = globals->root.sreldynrelro;
15260 }
15261 else
15262 {
15263 s = globals->root.sdynbss;
15264 srel = globals->root.srelbss;
15265 }
5522f910
NC		 15266 if (info->nocopyreloc == 0
15267 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15268 && h->size != 0)
252b5132 15269 {
47beaa6a 15270 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15271 h->needs_copy = 1;
252b5132
RH		 15272 }
15273
6cabe1ea 15274 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15275}
15276
5e681ec4
PB		 15277/* Allocate space in .plt, .got and associated reloc sections for
15278 dynamic relocs. */
15279
15280static bfd_boolean
47beaa6a 15281allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15282{
15283 struct bfd_link_info *info;
15284 struct elf32_arm_link_hash_table *htab;
15285 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15286 struct elf_dyn_relocs *p;
5e681ec4
PB		 15287
15288 if (h->root.type == bfd_link_hash_indirect)
15289 return TRUE;
15290
e6a6bb22
AM		 15291 eh = (struct elf32_arm_link_hash_entry *) h;
15292
5e681ec4
PB		 15293 info = (struct bfd_link_info *) inf;
15294 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15295 if (htab == NULL)
15296 return FALSE;
5e681ec4 15297
34e77a92 15298 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15299 && h->plt.refcount > 0)
15300 {
15301 /* Make sure this symbol is output as a dynamic symbol.
15302 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15303 if (h->dynindx == -1 && !h->forced_local
15304 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15305 {
c152c796 15306 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15307 return FALSE;
15308 }
15309
34e77a92
RS		 15310 /* If the call in the PLT entry binds locally, the associated
15311 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15312 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15313 than the .plt section. */
15314 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15315 {
15316 eh->is_iplt = 1;
15317 if (eh->plt.noncall_refcount == 0
15318 && SYMBOL_REFERENCES_LOCAL (info, h))
15319 /* All non-call references can be resolved directly.
15320 This means that they can (and in some cases, must)
15321 resolve directly to the run-time target, rather than
15322 to the PLT. That in turns means that any .got entry
15323 would be equal to the .igot.plt entry, so there's
15324 no point having both. */
15325 h->got.refcount = 0;
15326 }
15327
0e1862bb 15328 if (bfd_link_pic (info)
34e77a92 15329 || eh->is_iplt
7359ea65 15330 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15331 {
34e77a92 15332 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15333
5e681ec4
PB		 15334 /* If this symbol is not defined in a regular file, and we are
15335 not generating a shared library, then set the symbol to this
15336 location in the .plt. This is required to make function
15337 pointers compare as equal between the normal executable and
15338 the shared library. */
0e1862bb 15339 if (! bfd_link_pic (info)
f5385ebf 15340 && !h->def_regular)
5e681ec4 15341 {
34e77a92 15342 h->root.u.def.section = htab->root.splt;
5e681ec4 15343 h->root.u.def.value = h->plt.offset;
5e681ec4 15344
67d74e43
DJ		 15345 /* Make sure the function is not marked as Thumb, in case
15346 it is the target of an ABS32 relocation, which will
15347 point to the PLT entry. */
39d911fc 15348 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15349 }
022f8312 15350
00a97672
RS		 15351 /* VxWorks executables have a second set of relocations for
15352 each PLT entry. They go in a separate relocation section,
15353 which is processed by the kernel loader. */
0e1862bb 15354 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15355 {
15356 /* There is a relocation for the initial PLT entry:
15357 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15358 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15359 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15360
15361 /* There are two extra relocations for each subsequent
15362 PLT entry: an R_ARM_32 relocation for the GOT entry,
15363 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15364 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15365 }
5e681ec4
PB		 15366 }
15367 else
15368 {
15369 h->plt.offset = (bfd_vma) -1;
f5385ebf 15370 h->needs_plt = 0;
5e681ec4
PB		 15371 }
15372 }
15373 else
15374 {
15375 h->plt.offset = (bfd_vma) -1;
f5385ebf 15376 h->needs_plt = 0;
5e681ec4
PB		 15377 }
15378
0855e32b
NS		 15379 eh = (struct elf32_arm_link_hash_entry *) h;
15380 eh->tlsdesc_got = (bfd_vma) -1;
15381
5e681ec4
PB		 15382 if (h->got.refcount > 0)
15383 {
15384 asection *s;
15385 bfd_boolean dyn;
ba93b8ac
DJ		 15386 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15387 int indx;
5e681ec4
PB		 15388
15389 /* Make sure this symbol is output as a dynamic symbol.
15390 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15391 if (h->dynindx == -1 && !h->forced_local
15392 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15393 {
c152c796 15394 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15395 return FALSE;
15396 }
15397
e5a52504
MM		 15398 if (!htab->symbian_p)
15399 {
362d30a1 15400 s = htab->root.sgot;
e5a52504 15401 h->got.offset = s->size;
ba93b8ac
DJ		 15402
15403 if (tls_type == GOT_UNKNOWN)
15404 abort ();
15405
15406 if (tls_type == GOT_NORMAL)
15407 /* Non-TLS symbols need one GOT slot. */
15408 s->size += 4;
15409 else
15410 {
99059e56
RM		 15411 if (tls_type & GOT_TLS_GDESC)
15412 {
0855e32b 15413 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15414 eh->tlsdesc_got
0855e32b
NS		 15415 = (htab->root.sgotplt->size
15416 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15417 htab->root.sgotplt->size += 8;
15418 h->got.offset = (bfd_vma) -2;
34e77a92 15419 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15420 reloc in the middle of .got.plt. */
99059e56
RM		 15421 htab->num_tls_desc++;
15422 }
0855e32b 15423
ba93b8ac 15424 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15425 {
15426 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15427 the symbol is both GD and GDESC, got.offset may
15428 have been overwritten. */
15429 h->got.offset = s->size;
15430 s->size += 8;
15431 }
15432
ba93b8ac
DJ		 15433 if (tls_type & GOT_TLS_IE)
15434 /* R_ARM_TLS_IE32 needs one GOT slot. */
15435 s->size += 4;
15436 }
15437
e5a52504 15438 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15439
15440 indx = 0;
0e1862bb
L		 15441 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15442 bfd_link_pic (info),
15443 h)
15444 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15445 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15446 indx = h->dynindx;
15447
15448 if (tls_type != GOT_NORMAL
0e1862bb 15449 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15450 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15451 || h->root.type != bfd_link_hash_undefweak))
15452 {
15453 if (tls_type & GOT_TLS_IE)
47beaa6a 15454 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15455
15456 if (tls_type & GOT_TLS_GD)
47beaa6a 15457 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15458
b38cadfb 15459 if (tls_type & GOT_TLS_GDESC)
0855e32b 15460 {
47beaa6a 15461 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15462 /* GDESC needs a trampoline to jump to. */
15463 htab->tls_trampoline = -1;
15464 }
15465
15466 /* Only GD needs it. GDESC just emits one relocation per
15467 2 entries. */
b38cadfb 15468 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15469 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15470 }
6f820c85 15471 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15472 {
15473 if (htab->root.dynamic_sections_created)
15474 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15475 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15476 }
34e77a92
RS		 15477 else if (h->type == STT_GNU_IFUNC
15478 && eh->plt.noncall_refcount == 0)
15479 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15480 they all resolve dynamically instead. Reserve room for the
15481 GOT entry's R_ARM_IRELATIVE relocation. */
15482 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15483 else if (bfd_link_pic (info)
15484 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15485 || h->root.type != bfd_link_hash_undefweak))
b436d854 15486 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15487 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15488 }
5e681ec4
PB		 15489 }
15490 else
15491 h->got.offset = (bfd_vma) -1;
15492
a4fd1a8e
PB		 15493 /* Allocate stubs for exported Thumb functions on v4t. */
15494 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15495 && h->def_regular
39d911fc 15496 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15497 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15498 {
15499 struct elf_link_hash_entry * th;
15500 struct bfd_link_hash_entry * bh;
15501 struct elf_link_hash_entry * myh;
15502 char name[1024];
15503 asection *s;
15504 bh = NULL;
15505 /* Create a new symbol to regist the real location of the function. */
15506 s = h->root.u.def.section;
906e58ca 15507 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15508 _bfd_generic_link_add_one_symbol (info, s->owner,
15509 name, BSF_GLOBAL, s,
15510 h->root.u.def.value,
15511 NULL, TRUE, FALSE, &bh);
15512
15513 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15514 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15515 myh->forced_local = 1;
39d911fc 15516 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15517 eh->export_glue = myh;
15518 th = record_arm_to_thumb_glue (info, h);
15519 /* Point the symbol at the stub. */
15520 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15521 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15522 h->root.u.def.section = th->root.u.def.section;
15523 h->root.u.def.value = th->root.u.def.value & ~1;
15524 }
15525
0bdcacaf 15526 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15527 return TRUE;
15528
15529 /* In the shared -Bsymbolic case, discard space allocated for
15530 dynamic pc-relative relocs against symbols which turn out to be
15531 defined in regular objects. For the normal shared case, discard
15532 space for pc-relative relocs that have become local due to symbol
15533 visibility changes. */
15534
0e1862bb 15535 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15536 {
469a3493
RM		 15537 /* Relocs that use pc_count are PC-relative forms, which will appear
15538 on something like ".long foo - ." or "movw REG, foo - .". We want
15539 calls to protected symbols to resolve directly to the function
15540 rather than going via the plt. If people want function pointer
15541 comparisons to work as expected then they should avoid writing
15542 assembly like ".long foo - .". */
ba93b8ac
DJ		 15543 if (SYMBOL_CALLS_LOCAL (info, h))
15544 {
0bdcacaf 15545 struct elf_dyn_relocs **pp;
ba93b8ac 15546
0bdcacaf 15547 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15548 {
15549 p->count -= p->pc_count;
15550 p->pc_count = 0;
15551 if (p->count == 0)
15552 *pp = p->next;
15553 else
15554 pp = &p->next;
15555 }
15556 }
15557
4dfe6ac6 15558 if (htab->vxworks_p)
3348747a 15559 {
0bdcacaf 15560 struct elf_dyn_relocs **pp;
3348747a 15561
0bdcacaf 15562 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15563 {
0bdcacaf 15564 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15565 *pp = p->next;
15566 else
15567 pp = &p->next;
15568 }
15569 }
15570
ba93b8ac 15571 /* Also discard relocs on undefined weak syms with non-default
99059e56 15572 visibility. */
0bdcacaf 15573 if (eh->dyn_relocs != NULL
5e681ec4 15574 && h->root.type == bfd_link_hash_undefweak)
22d606e9 15575 {
95b03e4a
L		 15576 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15577 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 15578 eh->dyn_relocs = NULL;
22d606e9
AM		 15579
15580 /* Make sure undefined weak symbols are output as a dynamic
15581 symbol in PIEs. */
15582 else if (h->dynindx == -1
15583 && !h->forced_local)
15584 {
15585 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15586 return FALSE;
15587 }
15588 }
15589
67687978
PB		 15590 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15591 && h->root.type == bfd_link_hash_new)
15592 {
15593 /* Output absolute symbols so that we can create relocations
15594 against them. For normal symbols we output a relocation
15595 against the section that contains them. */
15596 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15597 return FALSE;
15598 }
15599
5e681ec4
PB		 15600 }
15601 else
15602 {
15603 /* For the non-shared case, discard space for relocs against
15604 symbols which turn out to need copy relocs or are not
15605 dynamic. */
15606
f5385ebf
AM		 15607 if (!h->non_got_ref
15608 && ((h->def_dynamic
15609 && !h->def_regular)
5e681ec4
PB		 15610 || (htab->root.dynamic_sections_created
15611 && (h->root.type == bfd_link_hash_undefweak
15612 || h->root.type == bfd_link_hash_undefined))))
15613 {
15614 /* Make sure this symbol is output as a dynamic symbol.
15615 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15616 if (h->dynindx == -1 && !h->forced_local
15617 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15618 {
c152c796 15619 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15620 return FALSE;
15621 }
15622
15623 /* If that succeeded, we know we'll be keeping all the
15624 relocs. */
15625 if (h->dynindx != -1)
15626 goto keep;
15627 }
15628
0bdcacaf 15629 eh->dyn_relocs = NULL;
5e681ec4
PB		 15630
15631 keep: ;
15632 }
15633
15634 /* Finally, allocate space. */
0bdcacaf 15635 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15636 {
0bdcacaf 15637 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15638 if (h->type == STT_GNU_IFUNC
15639 && eh->plt.noncall_refcount == 0
15640 && SYMBOL_REFERENCES_LOCAL (info, h))
15641 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15642 else
15643 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15644 }
15645
15646 return TRUE;
15647}
15648
63c1f59d
AM		 15649/* Set DF_TEXTREL if we find any dynamic relocs that apply to
15650 read-only sections. */
08d1f311
DJ		 15651
15652static bfd_boolean
63c1f59d 15653maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 15654{
63c1f59d 15655 asection *sec;
08d1f311 15656
63c1f59d
AM		 15657 if (h->root.type == bfd_link_hash_indirect)
15658 return TRUE;
08d1f311 15659
63c1f59d
AM		 15660 sec = readonly_dynrelocs (h);
15661 if (sec != NULL)
15662 {
15663 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 15664
63c1f59d
AM		 15665 info->flags |= DF_TEXTREL;
15666 info->callbacks->minfo
c1c8c1ef 15667 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 15668 sec->owner, h->root.root.string, sec);
08d1f311 15669
63c1f59d
AM		 15670 /* Not an error, just cut short the traversal. */
15671 return FALSE;
08d1f311
DJ		 15672 }
15673 return TRUE;
15674}
15675
d504ffc8
DJ		 15676void
15677bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15678 int byteswap_code)
15679{
15680 struct elf32_arm_link_hash_table *globals;
15681
15682 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15683 if (globals == NULL)
15684 return;
15685
d504ffc8
DJ		 15686 globals->byteswap_code = byteswap_code;
15687}
15688
252b5132
RH		 15689/* Set the sizes of the dynamic sections. */
15690
b34976b6 15691static bfd_boolean
57e8b36a
NC		 15692elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15693 struct bfd_link_info * info)
252b5132
RH		 15694{
15695 bfd * dynobj;
15696 asection * s;
b34976b6
AM		 15697 bfd_boolean plt;
15698 bfd_boolean relocs;
5e681ec4
PB		 15699 bfd *ibfd;
15700 struct elf32_arm_link_hash_table *htab;
252b5132 15701
5e681ec4 15702 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15703 if (htab == NULL)
15704 return FALSE;
15705
252b5132
RH		 15706 dynobj = elf_hash_table (info)->dynobj;
15707 BFD_ASSERT (dynobj != NULL);
39b41c9c 15708 check_use_blx (htab);
252b5132
RH		 15709
15710 if (elf_hash_table (info)->dynamic_sections_created)
15711 {
15712 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15713 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15714 {
3d4d4302 15715 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15716 BFD_ASSERT (s != NULL);
eea6121a 15717 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15718 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15719 }
15720 }
5e681ec4
PB		 15721
15722 /* Set up .got offsets for local syms, and space for local dynamic
15723 relocs. */
c72f2fb2 15724 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15725 {
5e681ec4
PB		 15726 bfd_signed_vma *local_got;
15727 bfd_signed_vma *end_local_got;
34e77a92 15728 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15729 char *local_tls_type;
0855e32b 15730 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15731 bfd_size_type locsymcount;
15732 Elf_Internal_Shdr *symtab_hdr;
15733 asection *srel;
4dfe6ac6 15734 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15735 unsigned int symndx;
5e681ec4 15736
0ffa91dd 15737 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15738 continue;
15739
15740 for (s = ibfd->sections; s != NULL; s = s->next)
15741 {
0bdcacaf 15742 struct elf_dyn_relocs *p;
5e681ec4 15743
0bdcacaf 15744 for (p = (struct elf_dyn_relocs *)
99059e56 15745 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15746 {
0bdcacaf
RS		 15747 if (!bfd_is_abs_section (p->sec)
15748 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15749 {
15750 /* Input section has been discarded, either because
15751 it is a copy of a linkonce section or due to
15752 linker script /DISCARD/, so we'll be discarding
15753 the relocs too. */
15754 }
3348747a 15755 else if (is_vxworks
0bdcacaf 15756 && strcmp (p->sec->output_section->name,
3348747a
NS		 15757 ".tls_vars") == 0)
15758 {
15759 /* Relocations in vxworks .tls_vars sections are
15760 handled specially by the loader. */
15761 }
5e681ec4
PB		 15762 else if (p->count != 0)
15763 {
0bdcacaf 15764 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15765 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15766 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15767 info->flags |= DF_TEXTREL;
15768 }
15769 }
15770 }
15771
15772 local_got = elf_local_got_refcounts (ibfd);
15773 if (!local_got)
15774 continue;
15775
0ffa91dd 15776 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15777 locsymcount = symtab_hdr->sh_info;
15778 end_local_got = local_got + locsymcount;
34e77a92 15779 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15780 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15781 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15782 symndx = 0;
362d30a1
RS		 15783 s = htab->root.sgot;
15784 srel = htab->root.srelgot;
0855e32b 15785 for (; local_got < end_local_got;
34e77a92
RS		 15786 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15787 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15788 {
0855e32b 15789 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15790 local_iplt = *local_iplt_ptr;
15791 if (local_iplt != NULL)
15792 {
15793 struct elf_dyn_relocs *p;
15794
15795 if (local_iplt->root.refcount > 0)
15796 {
15797 elf32_arm_allocate_plt_entry (info, TRUE,
15798 &local_iplt->root,
15799 &local_iplt->arm);
15800 if (local_iplt->arm.noncall_refcount == 0)
15801 /* All references to the PLT are calls, so all
15802 non-call references can resolve directly to the
15803 run-time target. This means that the .got entry
15804 would be the same as the .igot.plt entry, so there's
15805 no point creating both. */
15806 *local_got = 0;
15807 }
15808 else
15809 {
15810 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15811 local_iplt->root.offset = (bfd_vma) -1;
15812 }
15813
15814 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15815 {
15816 asection *psrel;
15817
15818 psrel = elf_section_data (p->sec)->sreloc;
15819 if (local_iplt->arm.noncall_refcount == 0)
15820 elf32_arm_allocate_irelocs (info, psrel, p->count);
15821 else
15822 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15823 }
15824 }
5e681ec4
PB		 15825 if (*local_got > 0)
15826 {
34e77a92
RS		 15827 Elf_Internal_Sym *isym;
15828
eea6121a 15829 *local_got = s->size;
ba93b8ac
DJ		 15830 if (*local_tls_type & GOT_TLS_GD)
15831 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15832 s->size += 8;
0855e32b
NS		 15833 if (*local_tls_type & GOT_TLS_GDESC)
15834 {
15835 *local_tlsdesc_gotent = htab->root.sgotplt->size
15836 - elf32_arm_compute_jump_table_size (htab);
15837 htab->root.sgotplt->size += 8;
15838 *local_got = (bfd_vma) -2;
34e77a92 15839 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15840 reloc in the middle of .got.plt. */
99059e56 15841 htab->num_tls_desc++;
0855e32b 15842 }
ba93b8ac
DJ		 15843 if (*local_tls_type & GOT_TLS_IE)
15844 s->size += 4;
ba93b8ac 15845
0855e32b
NS		 15846 if (*local_tls_type & GOT_NORMAL)
15847 {
15848 /* If the symbol is both GD and GDESC, *local_got
15849 may have been overwritten. */
15850 *local_got = s->size;
15851 s->size += 4;
15852 }
15853
34e77a92
RS		 15854 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15855 if (isym == NULL)
15856 return FALSE;
15857
15858 /* If all references to an STT_GNU_IFUNC PLT are calls,
15859 then all non-call references, including this GOT entry,
15860 resolve directly to the run-time target. */
15861 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15862 && (local_iplt == NULL
15863 || local_iplt->arm.noncall_refcount == 0))
15864 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15865 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15866 {
0e1862bb 15867 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15868 || *local_tls_type & GOT_TLS_GD)
15869 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15870
0e1862bb 15871 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15872 {
15873 elf32_arm_allocate_dynrelocs (info,
15874 htab->root.srelplt, 1);
15875 htab->tls_trampoline = -1;
15876 }
0855e32b 15877 }
5e681ec4
PB		 15878 }
15879 else
15880 *local_got = (bfd_vma) -1;
15881 }
252b5132
RH		 15882 }
15883
ba93b8ac
DJ		 15884 if (htab->tls_ldm_got.refcount > 0)
15885 {
15886 /* Allocate two GOT entries and one dynamic relocation (if necessary)
15887 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 15888 htab->tls_ldm_got.offset = htab->root.sgot->size;
15889 htab->root.sgot->size += 8;
0e1862bb 15890 if (bfd_link_pic (info))
47beaa6a 15891 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15892 }
15893 else
15894 htab->tls_ldm_got.offset = -1;
15895
5e681ec4
PB		 15896 /* Allocate global sym .plt and .got entries, and space for global
15897 sym dynamic relocs. */
47beaa6a 15898 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 15899
d504ffc8 15900 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 15901 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 15902 {
0ffa91dd 15903 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 15904 continue;
15905
c7b8f16e
JB		 15906 /* Initialise mapping tables for code/data. */
15907 bfd_elf32_arm_init_maps (ibfd);
906e58ca 15908
c7b8f16e 15909 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 15910 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
15911 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 15912 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 15913 }
d504ffc8 15914
3e6b1042
DJ		 15915 /* Allocate space for the glue sections now that we've sized them. */
15916 bfd_elf32_arm_allocate_interworking_sections (info);
15917
0855e32b
NS		 15918 /* For every jump slot reserved in the sgotplt, reloc_count is
15919 incremented. However, when we reserve space for TLS descriptors,
15920 it's not incremented, so in order to compute the space reserved
15921 for them, it suffices to multiply the reloc count by the jump
15922 slot size. */
15923 if (htab->root.srelplt)
15924 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
15925
15926 if (htab->tls_trampoline)
15927 {
15928 if (htab->root.splt->size == 0)
15929 htab->root.splt->size += htab->plt_header_size;
b38cadfb 15930
0855e32b
NS		 15931 htab->tls_trampoline = htab->root.splt->size;
15932 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 15933
0855e32b 15934 /* If we're not using lazy TLS relocations, don't generate the
99059e56 15935 PLT and GOT entries they require. */
0855e32b
NS		 15936 if (!(info->flags & DF_BIND_NOW))
15937 {
15938 htab->dt_tlsdesc_got = htab->root.sgot->size;
15939 htab->root.sgot->size += 4;
15940
15941 htab->dt_tlsdesc_plt = htab->root.splt->size;
15942 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
15943 }
15944 }
15945
252b5132
RH		 15946 /* The check_relocs and adjust_dynamic_symbol entry points have
15947 determined the sizes of the various dynamic sections. Allocate
15948 memory for them. */
b34976b6
AM		 15949 plt = FALSE;
15950 relocs = FALSE;
252b5132
RH		 15951 for (s = dynobj->sections; s != NULL; s = s->next)
15952 {
15953 const char * name;
252b5132
RH		 15954
15955 if ((s->flags & SEC_LINKER_CREATED) == 0)
15956 continue;
15957
15958 /* It's OK to base decisions on the section name, because none
15959 of the dynobj section names depend upon the input files. */
15960 name = bfd_get_section_name (dynobj, s);
15961
34e77a92 15962 if (s == htab->root.splt)
252b5132 15963 {
c456f082
AM		 15964 /* Remember whether there is a PLT. */
15965 plt = s->size != 0;
252b5132 15966 }
0112cd26 15967 else if (CONST_STRNEQ (name, ".rel"))
252b5132 15968 {
c456f082 15969 if (s->size != 0)
252b5132 15970 {
252b5132 15971 /* Remember whether there are any reloc sections other
00a97672 15972 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 15973 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 15974 relocs = TRUE;
252b5132
RH		 15975
15976 /* We use the reloc_count field as a counter if we need
15977 to copy relocs into the output file. */
15978 s->reloc_count = 0;
15979 }
15980 }
34e77a92
RS		 15981 else if (s != htab->root.sgot
15982 && s != htab->root.sgotplt
15983 && s != htab->root.iplt
15984 && s != htab->root.igotplt
5474d94f
AM		 15985 && s != htab->root.sdynbss
15986 && s != htab->root.sdynrelro)
252b5132
RH		 15987 {
15988 /* It's not one of our sections, so don't allocate space. */
15989 continue;
15990 }
15991
c456f082 15992 if (s->size == 0)
252b5132 15993 {
c456f082 15994 /* If we don't need this section, strip it from the
00a97672
RS		 15995 output file. This is mostly to handle .rel(a).bss and
15996 .rel(a).plt. We must create both sections in
c456f082
AM		 15997 create_dynamic_sections, because they must be created
15998 before the linker maps input sections to output
15999 sections. The linker does that before
16000 adjust_dynamic_symbol is called, and it is that
16001 function which decides whether anything needs to go
16002 into these sections. */
8423293d 16003 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16004 continue;
16005 }
16006
c456f082
AM		 16007 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16008 continue;
16009
252b5132 16010 /* Allocate memory for the section contents. */
21d799b5 16011 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16012 if (s->contents == NULL)
b34976b6 16013 return FALSE;
252b5132
RH		 16014 }
16015
16016 if (elf_hash_table (info)->dynamic_sections_created)
16017 {
16018 /* Add some entries to the .dynamic section. We fill in the
16019 values later, in elf32_arm_finish_dynamic_sections, but we
16020 must add the entries now so that we get the correct size for
16021 the .dynamic section. The DT_DEBUG entry is filled in by the
16022 dynamic linker and used by the debugger. */
dc810e39 16023#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16024 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16025
0e1862bb 16026 if (bfd_link_executable (info))
252b5132 16027 {
dc810e39 16028 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16029 return FALSE;
252b5132
RH		 16030 }
16031
16032 if (plt)
16033 {
dc810e39
AM		 16034 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16035 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16036 || !add_dynamic_entry (DT_PLTREL,
16037 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16038 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16039 return FALSE;
0855e32b 16040
5025eb7c
AO		 16041 if (htab->dt_tlsdesc_plt
16042 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16043 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16044 return FALSE;
252b5132
RH		 16045 }
16046
16047 if (relocs)
16048 {
00a97672
RS		 16049 if (htab->use_rel)
16050 {
16051 if (!add_dynamic_entry (DT_REL, 0)
16052 || !add_dynamic_entry (DT_RELSZ, 0)
16053 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16054 return FALSE;
16055 }
16056 else
16057 {
16058 if (!add_dynamic_entry (DT_RELA, 0)
16059 || !add_dynamic_entry (DT_RELASZ, 0)
16060 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16061 return FALSE;
16062 }
252b5132
RH		 16063 }
16064
08d1f311
DJ		 16065 /* If any dynamic relocs apply to a read-only section,
16066 then we need a DT_TEXTREL entry. */
16067 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 16068 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 16069
99e4ae17 16070 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16071 {
dc810e39 16072 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16073 return FALSE;
252b5132 16074 }
7a2b07ff
NS		 16075 if (htab->vxworks_p
16076 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16077 return FALSE;
252b5132 16078 }
8532796c 16079#undef add_dynamic_entry
252b5132 16080
b34976b6 16081 return TRUE;
252b5132
RH		 16082}
16083
0855e32b
NS		 16084/* Size sections even though they're not dynamic. We use it to setup
16085 _TLS_MODULE_BASE_, if needed. */
16086
16087static bfd_boolean
16088elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16089 struct bfd_link_info *info)
0855e32b
NS		 16090{
16091 asection *tls_sec;
16092
0e1862bb 16093 if (bfd_link_relocatable (info))
0855e32b
NS		 16094 return TRUE;
16095
16096 tls_sec = elf_hash_table (info)->tls_sec;
16097
16098 if (tls_sec)
16099 {
16100 struct elf_link_hash_entry *tlsbase;
16101
16102 tlsbase = elf_link_hash_lookup
16103 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16104
16105 if (tlsbase)
99059e56
RM		 16106 {
16107 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16108 const struct elf_backend_data *bed
99059e56 16109 = get_elf_backend_data (output_bfd);
0855e32b 16110
99059e56 16111 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16112 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16113 tls_sec, 0, NULL, FALSE,
16114 bed->collect, &bh)))
16115 return FALSE;
b38cadfb 16116
99059e56
RM		 16117 tlsbase->type = STT_TLS;
16118 tlsbase = (struct elf_link_hash_entry *)bh;
16119 tlsbase->def_regular = 1;
16120 tlsbase->other = STV_HIDDEN;
16121 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16122 }
16123 }
16124 return TRUE;
16125}
16126
252b5132
RH		 16127/* Finish up dynamic symbol handling. We set the contents of various
16128 dynamic sections here. */
16129
b34976b6 16130static bfd_boolean
906e58ca
NC		 16131elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16132 struct bfd_link_info * info,
16133 struct elf_link_hash_entry * h,
16134 Elf_Internal_Sym * sym)
252b5132 16135{
e5a52504 16136 struct elf32_arm_link_hash_table *htab;
b7693d02 16137 struct elf32_arm_link_hash_entry *eh;
252b5132 16138
e5a52504 16139 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16140 if (htab == NULL)
16141 return FALSE;
16142
b7693d02 16143 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16144
16145 if (h->plt.offset != (bfd_vma) -1)
16146 {
34e77a92 16147 if (!eh->is_iplt)
e5a52504 16148 {
34e77a92 16149 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16150 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16151 h->dynindx, 0))
16152 return FALSE;
e5a52504 16153 }
57e8b36a 16154
f5385ebf 16155 if (!h->def_regular)
252b5132
RH		 16156 {
16157 /* Mark the symbol as undefined, rather than as defined in
3a635617 16158 the .plt section. */
252b5132 16159 sym->st_shndx = SHN_UNDEF;
3a635617 16160 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16161 Otherwise, the PLT entry would provide a definition for
16162 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16163 and so the symbol would never be NULL. Leave the value if
16164 there were any relocations where pointer equality matters
16165 (this is a clue for the dynamic linker, to make function
16166 pointer comparisons work between an application and shared
16167 library). */
97323ad1 16168 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16169 sym->st_value = 0;
252b5132 16170 }
34e77a92
RS		 16171 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16172 {
16173 /* At least one non-call relocation references this .iplt entry,
16174 so the .iplt entry is the function's canonical address. */
16175 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16176 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16177 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16178 (output_bfd, htab->root.iplt->output_section));
16179 sym->st_value = (h->plt.offset
16180 + htab->root.iplt->output_section->vma
16181 + htab->root.iplt->output_offset);
16182 }
252b5132
RH		 16183 }
16184
f5385ebf 16185 if (h->needs_copy)
252b5132
RH		 16186 {
16187 asection * s;
947216bf 16188 Elf_Internal_Rela rel;
252b5132
RH		 16189
16190 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16191 BFD_ASSERT (h->dynindx != -1
16192 && (h->root.type == bfd_link_hash_defined
16193 || h->root.type == bfd_link_hash_defweak));
16194
00a97672 16195 rel.r_addend = 0;
252b5132
RH		 16196 rel.r_offset = (h->root.u.def.value
16197 + h->root.u.def.section->output_section->vma
16198 + h->root.u.def.section->output_offset);
16199 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 16200 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 16201 s = htab->root.sreldynrelro;
16202 else
16203 s = htab->root.srelbss;
47beaa6a 16204 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16205 }
16206
00a97672
RS		 16207 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16208 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16209 to the ".got" section. */
9637f6ef 16210 if (h == htab->root.hdynamic
00a97672 16211 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16212 sym->st_shndx = SHN_ABS;
16213
b34976b6 16214 return TRUE;
252b5132
RH		 16215}
16216
0855e32b
NS		 16217static void
16218arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16219 void *contents,
16220 const unsigned long *template, unsigned count)
16221{
16222 unsigned ix;
b38cadfb 16223
0855e32b
NS		 16224 for (ix = 0; ix != count; ix++)
16225 {
16226 unsigned long insn = template[ix];
16227
16228 /* Emit mov pc,rx if bx is not permitted. */
16229 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16230 insn = (insn & 0xf000000f) | 0x01a0f000;
16231 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16232 }
16233}
16234
99059e56
RM		 16235/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16236 other variants, NaCl needs this entry in a static executable's
16237 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16238 zero. For .iplt really only the last bundle is useful, and .iplt
16239 could have a shorter first entry, with each individual PLT entry's
16240 relative branch calculated differently so it targets the last
16241 bundle instead of the instruction before it (labelled .Lplt_tail
16242 above). But it's simpler to keep the size and layout of PLT0
16243 consistent with the dynamic case, at the cost of some dead code at
16244 the start of .iplt and the one dead store to the stack at the start
16245 of .Lplt_tail. */
16246static void
16247arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16248 asection *plt, bfd_vma got_displacement)
16249{
16250 unsigned int i;
16251
16252 put_arm_insn (htab, output_bfd,
16253 elf32_arm_nacl_plt0_entry[0]
16254 | arm_movw_immediate (got_displacement),
16255 plt->contents + 0);
16256 put_arm_insn (htab, output_bfd,
16257 elf32_arm_nacl_plt0_entry[1]
16258 | arm_movt_immediate (got_displacement),
16259 plt->contents + 4);
16260
16261 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16262 put_arm_insn (htab, output_bfd,
16263 elf32_arm_nacl_plt0_entry[i],
16264 plt->contents + (i * 4));
16265}
16266
252b5132
RH		 16267/* Finish up the dynamic sections. */
16268
b34976b6 16269static bfd_boolean
57e8b36a 16270elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16271{
16272 bfd * dynobj;
16273 asection * sgot;
16274 asection * sdyn;
4dfe6ac6
NC		 16275 struct elf32_arm_link_hash_table *htab;
16276
16277 htab = elf32_arm_hash_table (info);
16278 if (htab == NULL)
16279 return FALSE;
252b5132
RH		 16280
16281 dynobj = elf_hash_table (info)->dynobj;
16282
362d30a1 16283 sgot = htab->root.sgotplt;
894891db
NC		 16284 /* A broken linker script might have discarded the dynamic sections.
16285 Catch this here so that we do not seg-fault later on. */
16286 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16287 return FALSE;
3d4d4302 16288 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16289
16290 if (elf_hash_table (info)->dynamic_sections_created)
16291 {
16292 asection *splt;
16293 Elf32_External_Dyn *dyncon, *dynconend;
16294
362d30a1 16295 splt = htab->root.splt;
24a1ba0f 16296 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16297 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16298
16299 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16300 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16301
252b5132
RH		 16302 for (; dyncon < dynconend; dyncon++)
16303 {
16304 Elf_Internal_Dyn dyn;
16305 const char * name;
16306 asection * s;
16307
16308 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16309
16310 switch (dyn.d_tag)
16311 {
229fcec5
MM		 16312 unsigned int type;
16313
252b5132 16314 default:
7a2b07ff
NS		 16315 if (htab->vxworks_p
16316 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16317 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16318 break;
16319
229fcec5
MM		 16320 case DT_HASH:
16321 name = ".hash";
16322 goto get_vma_if_bpabi;
16323 case DT_STRTAB:
16324 name = ".dynstr";
16325 goto get_vma_if_bpabi;
16326 case DT_SYMTAB:
16327 name = ".dynsym";
16328 goto get_vma_if_bpabi;
c0042f5d
MM		 16329 case DT_VERSYM:
16330 name = ".gnu.version";
16331 goto get_vma_if_bpabi;
16332 case DT_VERDEF:
16333 name = ".gnu.version_d";
16334 goto get_vma_if_bpabi;
16335 case DT_VERNEED:
16336 name = ".gnu.version_r";
16337 goto get_vma_if_bpabi;
16338
252b5132 16339 case DT_PLTGOT:
4ade44b7 16340 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16341 goto get_vma;
16342 case DT_JMPREL:
00a97672 16343 name = RELOC_SECTION (htab, ".plt");
252b5132 16344 get_vma:
4ade44b7 16345 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16346 if (s == NULL)
16347 {
4eca0228 16348 _bfd_error_handler
4ade44b7 16349 (_("could not find section %s"), name);
05456594
NC		 16350 bfd_set_error (bfd_error_invalid_operation);
16351 return FALSE;
16352 }
229fcec5 16353 if (!htab->symbian_p)
4ade44b7 16354 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16355 else
16356 /* In the BPABI, tags in the PT_DYNAMIC section point
16357 at the file offset, not the memory address, for the
16358 convenience of the post linker. */
4ade44b7 16359 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16360 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16361 break;
16362
229fcec5
MM		 16363 get_vma_if_bpabi:
16364 if (htab->symbian_p)
16365 goto get_vma;
16366 break;
16367
252b5132 16368 case DT_PLTRELSZ:
362d30a1 16369 s = htab->root.srelplt;
252b5132 16370 BFD_ASSERT (s != NULL);
eea6121a 16371 dyn.d_un.d_val = s->size;
252b5132
RH		 16372 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16373 break;
906e58ca 16374
252b5132 16375 case DT_RELSZ:
00a97672 16376 case DT_RELASZ:
229fcec5
MM		 16377 case DT_REL:
16378 case DT_RELA:
229fcec5
MM		 16379 /* In the BPABI, the DT_REL tag must point at the file
16380 offset, not the VMA, of the first relocation
16381 section. So, we use code similar to that in
16382 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 16383 relocation section, since relocation sections are
16384 never allocated under the BPABI. PLT relocs are also
16385 included. */
229fcec5
MM		 16386 if (htab->symbian_p)
16387 {
16388 unsigned int i;
16389 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16390 ? SHT_REL : SHT_RELA);
16391 dyn.d_un.d_val = 0;
16392 for (i = 1; i < elf_numsections (output_bfd); i++)
16393 {
906e58ca 16394 Elf_Internal_Shdr *hdr
229fcec5
MM		 16395 = elf_elfsections (output_bfd)[i];
16396 if (hdr->sh_type == type)
16397 {
906e58ca 16398 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16399 || dyn.d_tag == DT_RELASZ)
16400 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16401 else if ((ufile_ptr) hdr->sh_offset
16402 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16403 dyn.d_un.d_val = hdr->sh_offset;
16404 }
16405 }
16406 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16407 }
252b5132 16408 break;
88f7bcd5 16409
0855e32b 16410 case DT_TLSDESC_PLT:
99059e56 16411 s = htab->root.splt;
0855e32b
NS		 16412 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16413 + htab->dt_tlsdesc_plt);
16414 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16415 break;
16416
16417 case DT_TLSDESC_GOT:
99059e56 16418 s = htab->root.sgot;
0855e32b 16419 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16420 + htab->dt_tlsdesc_got);
0855e32b
NS		 16421 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16422 break;
16423
88f7bcd5
NC		 16424 /* Set the bottom bit of DT_INIT/FINI if the
16425 corresponding function is Thumb. */
16426 case DT_INIT:
16427 name = info->init_function;
16428 goto get_sym;
16429 case DT_FINI:
16430 name = info->fini_function;
16431 get_sym:
16432 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16433 then there is nothing to adjust. */
88f7bcd5
NC		 16434 if (dyn.d_un.d_val != 0)
16435 {
16436 struct elf_link_hash_entry * eh;
16437
16438 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16439 FALSE, FALSE, TRUE);
39d911fc
TP		 16440 if (eh != NULL
16441 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16442 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16443 {
16444 dyn.d_un.d_val |= 1;
b34976b6 16445 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16446 }
16447 }
16448 break;
252b5132
RH		 16449 }
16450 }
16451
24a1ba0f 16452 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16453 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16454 {
00a97672
RS		 16455 const bfd_vma *plt0_entry;
16456 bfd_vma got_address, plt_address, got_displacement;
16457
16458 /* Calculate the addresses of the GOT and PLT. */
16459 got_address = sgot->output_section->vma + sgot->output_offset;
16460 plt_address = splt->output_section->vma + splt->output_offset;
16461
16462 if (htab->vxworks_p)
16463 {
16464 /* The VxWorks GOT is relocated by the dynamic linker.
16465 Therefore, we must emit relocations rather than simply
16466 computing the values now. */
16467 Elf_Internal_Rela rel;
16468
16469 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16470 put_arm_insn (htab, output_bfd, plt0_entry[0],
16471 splt->contents + 0);
16472 put_arm_insn (htab, output_bfd, plt0_entry[1],
16473 splt->contents + 4);
16474 put_arm_insn (htab, output_bfd, plt0_entry[2],
16475 splt->contents + 8);
00a97672
RS		 16476 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16477
8029a119 16478 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16479 rel.r_offset = plt_address + 12;
16480 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16481 rel.r_addend = 0;
16482 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16483 htab->srelplt2->contents);
16484 }
b38cadfb 16485 else if (htab->nacl_p)
99059e56
RM		 16486 arm_nacl_put_plt0 (htab, output_bfd, splt,
16487 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16488 else if (using_thumb_only (htab))
16489 {
16490 got_displacement = got_address - (plt_address + 12);
16491
16492 plt0_entry = elf32_thumb2_plt0_entry;
16493 put_arm_insn (htab, output_bfd, plt0_entry[0],
16494 splt->contents + 0);
16495 put_arm_insn (htab, output_bfd, plt0_entry[1],
16496 splt->contents + 4);
16497 put_arm_insn (htab, output_bfd, plt0_entry[2],
16498 splt->contents + 8);
16499
16500 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16501 }
00a97672
RS		 16502 else
16503 {
16504 got_displacement = got_address - (plt_address + 16);
16505
16506 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16507 put_arm_insn (htab, output_bfd, plt0_entry[0],
16508 splt->contents + 0);
16509 put_arm_insn (htab, output_bfd, plt0_entry[1],
16510 splt->contents + 4);
16511 put_arm_insn (htab, output_bfd, plt0_entry[2],
16512 splt->contents + 8);
16513 put_arm_insn (htab, output_bfd, plt0_entry[3],
16514 splt->contents + 12);
5e681ec4 16515
5e681ec4 16516#ifdef FOUR_WORD_PLT
00a97672
RS		 16517 /* The displacement value goes in the otherwise-unused
16518 last word of the second entry. */
16519 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16520#else
00a97672 16521 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16522#endif
00a97672 16523 }
f7a74f8c 16524 }
252b5132
RH		 16525
16526 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16527 really seem like the right value. */
74541ad4
AM		 16528 if (splt->output_section->owner == output_bfd)
16529 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16530
0855e32b
NS		 16531 if (htab->dt_tlsdesc_plt)
16532 {
16533 bfd_vma got_address
16534 = sgot->output_section->vma + sgot->output_offset;
16535 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16536 + htab->root.sgot->output_offset);
16537 bfd_vma plt_address
16538 = splt->output_section->vma + splt->output_offset;
16539
b38cadfb 16540 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16541 splt->contents + htab->dt_tlsdesc_plt,
16542 dl_tlsdesc_lazy_trampoline, 6);
16543
16544 bfd_put_32 (output_bfd,
16545 gotplt_address + htab->dt_tlsdesc_got
16546 - (plt_address + htab->dt_tlsdesc_plt)
16547 - dl_tlsdesc_lazy_trampoline[6],
16548 splt->contents + htab->dt_tlsdesc_plt + 24);
16549 bfd_put_32 (output_bfd,
16550 got_address - (plt_address + htab->dt_tlsdesc_plt)
16551 - dl_tlsdesc_lazy_trampoline[7],
16552 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16553 }
16554
16555 if (htab->tls_trampoline)
16556 {
b38cadfb 16557 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16558 splt->contents + htab->tls_trampoline,
16559 tls_trampoline, 3);
16560#ifdef FOUR_WORD_PLT
16561 bfd_put_32 (output_bfd, 0x00000000,
16562 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16563#endif
0855e32b
NS		 16564 }
16565
0e1862bb
L		 16566 if (htab->vxworks_p
16567 && !bfd_link_pic (info)
16568 && htab->root.splt->size > 0)
00a97672
RS		 16569 {
16570 /* Correct the .rel(a).plt.unloaded relocations. They will have
16571 incorrect symbol indexes. */
16572 int num_plts;
eed62c48 16573 unsigned char *p;
00a97672 16574
362d30a1 16575 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16576 / htab->plt_entry_size);
16577 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16578
16579 for (; num_plts; num_plts--)
16580 {
16581 Elf_Internal_Rela rel;
16582
16583 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16584 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16585 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16586 p += RELOC_SIZE (htab);
16587
16588 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16589 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16590 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16591 p += RELOC_SIZE (htab);
16592 }
16593 }
252b5132
RH		 16594 }
16595
99059e56
RM		 16596 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16597 /* NaCl uses a special first entry in .iplt too. */
16598 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16599
252b5132 16600 /* Fill in the first three entries in the global offset table. */
229fcec5 16601 if (sgot)
252b5132 16602 {
229fcec5
MM		 16603 if (sgot->size > 0)
16604 {
16605 if (sdyn == NULL)
16606 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16607 else
16608 bfd_put_32 (output_bfd,
16609 sdyn->output_section->vma + sdyn->output_offset,
16610 sgot->contents);
16611 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16612 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16613 }
252b5132 16614
229fcec5
MM		 16615 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16616 }
252b5132 16617
b34976b6 16618 return TRUE;
252b5132
RH		 16619}
16620
ba96a88f 16621static void
57e8b36a 16622elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16623{
9b485d32 16624 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16625 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16626 struct elf_segment_map *m;
ba96a88f
NC		 16627
16628 i_ehdrp = elf_elfheader (abfd);
16629
94a3258f
PB		 16630 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16631 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16632 else
7394f108 16633 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16634 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16635
93204d3a
PB		 16636 if (link_info)
16637 {
16638 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16639 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16640 i_ehdrp->e_flags |= EF_ARM_BE8;
16641 }
3bfcb652
NC		 16642
16643 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16644 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16645 {
16646 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16647 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16648 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16649 else
16650 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16651 }
ac4c9b04
MG		 16652
16653 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16654 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16655 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16656 {
16657 unsigned int j;
16658
16659 if (m->count == 0)
16660 continue;
16661 for (j = 0; j < m->count; j++)
16662 {
f0728ee3 16663 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16664 break;
16665 }
16666 if (j == m->count)
16667 {
16668 m->p_flags = PF_X;
16669 m->p_flags_valid = 1;
16670 }
16671 }
ba96a88f
NC		 16672}
16673
99e4ae17 16674static enum elf_reloc_type_class
7e612e98
AM		 16675elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16676 const asection *rel_sec ATTRIBUTE_UNUSED,
16677 const Elf_Internal_Rela *rela)
99e4ae17 16678{
f51e552e 16679 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16680 {
16681 case R_ARM_RELATIVE:
16682 return reloc_class_relative;
16683 case R_ARM_JUMP_SLOT:
16684 return reloc_class_plt;
16685 case R_ARM_COPY:
16686 return reloc_class_copy;
109575d7
JW		 16687 case R_ARM_IRELATIVE:
16688 return reloc_class_ifunc;
99e4ae17
AJ		 16689 default:
16690 return reloc_class_normal;
16691 }
16692}
16693
e489d0ae 16694static void
57e8b36a 16695elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16696{
5a6c6817 16697 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16698}
16699
40a18ebd
NC		 16700/* Return TRUE if this is an unwinding table entry. */
16701
16702static bfd_boolean
16703is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16704{
0112cd26
NC		 16705 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16706 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16707}
16708
16709
16710/* Set the type and flags for an ARM section. We do this by
16711 the section name, which is a hack, but ought to work. */
16712
16713static bfd_boolean
16714elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16715{
16716 const char * name;
16717
16718 name = bfd_get_section_name (abfd, sec);
16719
16720 if (is_arm_elf_unwind_section_name (abfd, name))
16721 {
16722 hdr->sh_type = SHT_ARM_EXIDX;
16723 hdr->sh_flags |= SHF_LINK_ORDER;
16724 }
ac4c9b04 16725
f0728ee3
AV		 16726 if (sec->flags & SEC_ELF_PURECODE)
16727 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16728
40a18ebd
NC		 16729 return TRUE;
16730}
16731
6dc132d9
L		 16732/* Handle an ARM specific section when reading an object file. This is
16733 called when bfd_section_from_shdr finds a section with an unknown
16734 type. */
40a18ebd
NC		 16735
16736static bfd_boolean
16737elf32_arm_section_from_shdr (bfd *abfd,
16738 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16739 const char *name,
16740 int shindex)
40a18ebd
NC		 16741{
16742 /* There ought to be a place to keep ELF backend specific flags, but
16743 at the moment there isn't one. We just keep track of the
16744 sections by their name, instead. Fortunately, the ABI gives
16745 names for all the ARM specific sections, so we will probably get
16746 away with this. */
16747 switch (hdr->sh_type)
16748 {
16749 case SHT_ARM_EXIDX:
0951f019
RE		 16750 case SHT_ARM_PREEMPTMAP:
16751 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16752 break;
16753
16754 default:
16755 return FALSE;
16756 }
16757
6dc132d9 16758 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16759 return FALSE;
16760
16761 return TRUE;
16762}
e489d0ae 16763
44444f50
NC		 16764static _arm_elf_section_data *
16765get_arm_elf_section_data (asection * sec)
16766{
47b2e99c
JZ		 16767 if (sec && sec->owner && is_arm_elf (sec->owner))
16768 return elf32_arm_section_data (sec);
44444f50
NC		 16769 else
16770 return NULL;
8e3de13a
NC		 16771}
16772
4e617b1e
PB		 16773typedef struct
16774{
57402f1e 16775 void *flaginfo;
4e617b1e 16776 struct bfd_link_info *info;
91a5743d
PB		 16777 asection *sec;
16778 int sec_shndx;
6e0b88f1
AM		 16779 int (*func) (void *, const char *, Elf_Internal_Sym *,
16780 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16781} output_arch_syminfo;
16782
16783enum map_symbol_type
16784{
16785 ARM_MAP_ARM,
16786 ARM_MAP_THUMB,
16787 ARM_MAP_DATA
16788};
16789
16790
7413f23f 16791/* Output a single mapping symbol. */
4e617b1e
PB		 16792
16793static bfd_boolean
7413f23f
DJ		 16794elf32_arm_output_map_sym (output_arch_syminfo *osi,
16795 enum map_symbol_type type,
16796 bfd_vma offset)
4e617b1e
PB		 16797{
16798 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16799 Elf_Internal_Sym sym;
16800
91a5743d
PB		 16801 sym.st_value = osi->sec->output_section->vma
16802 + osi->sec->output_offset
16803 + offset;
4e617b1e
PB		 16804 sym.st_size = 0;
16805 sym.st_other = 0;
16806 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16807 sym.st_shndx = osi->sec_shndx;
35fc36a8 16808 sym.st_target_internal = 0;
fe33d2fa 16809 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16810 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16811}
16812
34e77a92
RS		 16813/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16814 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16815
16816static bfd_boolean
34e77a92
RS		 16817elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16818 bfd_boolean is_iplt_entry_p,
16819 union gotplt_union *root_plt,
16820 struct arm_plt_info *arm_plt)
4e617b1e 16821{
4e617b1e 16822 struct elf32_arm_link_hash_table *htab;
34e77a92 16823 bfd_vma addr, plt_header_size;
4e617b1e 16824
34e77a92 16825 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16826 return TRUE;
16827
4dfe6ac6
NC		 16828 htab = elf32_arm_hash_table (osi->info);
16829 if (htab == NULL)
16830 return FALSE;
16831
34e77a92
RS		 16832 if (is_iplt_entry_p)
16833 {
16834 osi->sec = htab->root.iplt;
16835 plt_header_size = 0;
16836 }
16837 else
16838 {
16839 osi->sec = htab->root.splt;
16840 plt_header_size = htab->plt_header_size;
16841 }
16842 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16843 (osi->info->output_bfd, osi->sec->output_section));
16844
16845 addr = root_plt->offset & -2;
4e617b1e
PB		 16846 if (htab->symbian_p)
16847 {
7413f23f 16848 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16849 return FALSE;
7413f23f 16850 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16851 return FALSE;
16852 }
16853 else if (htab->vxworks_p)
16854 {
7413f23f 16855 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16856 return FALSE;
7413f23f 16857 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16858 return FALSE;
7413f23f 16859 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16860 return FALSE;
7413f23f 16861 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16862 return FALSE;
16863 }
b38cadfb
NC		 16864 else if (htab->nacl_p)
16865 {
16866 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16867 return FALSE;
16868 }
eed94f8f
NC		 16869 else if (using_thumb_only (htab))
16870 {
16871 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16872 return FALSE;
6a631e86 16873 }
4e617b1e
PB		 16874 else
16875 {
34e77a92 16876 bfd_boolean thumb_stub_p;
bd97cb95 16877
34e77a92
RS		 16878 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16879 if (thumb_stub_p)
4e617b1e 16880 {
7413f23f 16881 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16882 return FALSE;
16883 }
16884#ifdef FOUR_WORD_PLT
7413f23f 16885 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16886 return FALSE;
7413f23f 16887 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 16888 return FALSE;
16889#else
906e58ca 16890 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 16891 so only need to output a mapping symbol for the first PLT entry and
16892 entries with thumb thunks. */
34e77a92 16893 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 16894 {
7413f23f 16895 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 16896 return FALSE;
16897 }
16898#endif
16899 }
16900
16901 return TRUE;
16902}
16903
34e77a92
RS		 16904/* Output mapping symbols for PLT entries associated with H. */
16905
16906static bfd_boolean
16907elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
16908{
16909 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
16910 struct elf32_arm_link_hash_entry *eh;
16911
16912 if (h->root.type == bfd_link_hash_indirect)
16913 return TRUE;
16914
16915 if (h->root.type == bfd_link_hash_warning)
16916 /* When warning symbols are created, they **replace** the "real"
16917 entry in the hash table, thus we never get to see the real
16918 symbol in a hash traversal. So look at it now. */
16919 h = (struct elf_link_hash_entry *) h->root.u.i.link;
16920
16921 eh = (struct elf32_arm_link_hash_entry *) h;
16922 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
16923 &h->plt, &eh->plt);
16924}
16925
4f4faa4d
TP		 16926/* Bind a veneered symbol to its veneer identified by its hash entry
16927 STUB_ENTRY. The veneered location thus loose its symbol. */
16928
16929static void
16930arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
16931{
16932 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
16933
16934 BFD_ASSERT (hash);
16935 hash->root.root.u.def.section = stub_entry->stub_sec;
16936 hash->root.root.u.def.value = stub_entry->stub_offset;
16937 hash->root.size = stub_entry->stub_size;
16938}
16939
7413f23f
DJ		 16940/* Output a single local symbol for a generated stub. */
16941
16942static bfd_boolean
16943elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
16944 bfd_vma offset, bfd_vma size)
16945{
7413f23f
DJ		 16946 Elf_Internal_Sym sym;
16947
7413f23f
DJ		 16948 sym.st_value = osi->sec->output_section->vma
16949 + osi->sec->output_offset
16950 + offset;
16951 sym.st_size = size;
16952 sym.st_other = 0;
16953 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
16954 sym.st_shndx = osi->sec_shndx;
35fc36a8 16955 sym.st_target_internal = 0;
57402f1e 16956 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 16957}
4e617b1e 16958
da5938a2 16959static bfd_boolean
8029a119
NC		 16960arm_map_one_stub (struct bfd_hash_entry * gen_entry,
16961 void * in_arg)
da5938a2
NC		 16962{
16963 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 16964 asection *stub_sec;
16965 bfd_vma addr;
7413f23f 16966 char *stub_name;
9a008db3 16967 output_arch_syminfo *osi;
d3ce72d0 16968 const insn_sequence *template_sequence;
461a49ca
DJ		 16969 enum stub_insn_type prev_type;
16970 int size;
16971 int i;
16972 enum map_symbol_type sym_type;
da5938a2
NC		 16973
16974 /* Massage our args to the form they really have. */
16975 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 16976 osi = (output_arch_syminfo *) in_arg;
da5938a2 16977
da5938a2
NC		 16978 stub_sec = stub_entry->stub_sec;
16979
16980 /* Ensure this stub is attached to the current section being
7413f23f 16981 processed. */
da5938a2
NC		 16982 if (stub_sec != osi->sec)
16983 return TRUE;
16984
7413f23f 16985 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 16986 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 16987
16988 if (arm_stub_sym_claimed (stub_entry->stub_type))
16989 arm_stub_claim_sym (stub_entry);
16990 else
7413f23f 16991 {
4f4faa4d
TP		 16992 stub_name = stub_entry->output_name;
16993 switch (template_sequence[0].type)
16994 {
16995 case ARM_TYPE:
16996 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
16997 stub_entry->stub_size))
16998 return FALSE;
16999 break;
17000 case THUMB16_TYPE:
17001 case THUMB32_TYPE:
17002 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17003 stub_entry->stub_size))
17004 return FALSE;
17005 break;
17006 default:
17007 BFD_FAIL ();
17008 return 0;
17009 }
7413f23f 17010 }
da5938a2 17011
461a49ca
DJ		 17012 prev_type = DATA_TYPE;
17013 size = 0;
17014 for (i = 0; i < stub_entry->stub_template_size; i++)
17015 {
d3ce72d0 17016 switch (template_sequence[i].type)
461a49ca
DJ		 17017 {
17018 case ARM_TYPE:
17019 sym_type = ARM_MAP_ARM;
17020 break;
17021
17022 case THUMB16_TYPE:
48229727 17023 case THUMB32_TYPE:
461a49ca
DJ		 17024 sym_type = ARM_MAP_THUMB;
17025 break;
17026
17027 case DATA_TYPE:
17028 sym_type = ARM_MAP_DATA;
17029 break;
17030
17031 default:
17032 BFD_FAIL ();
4e31c731 17033 return FALSE;
461a49ca
DJ		 17034 }
17035
d3ce72d0 17036 if (template_sequence[i].type != prev_type)
461a49ca 17037 {
d3ce72d0 17038 prev_type = template_sequence[i].type;
461a49ca
DJ		 17039 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17040 return FALSE;
17041 }
17042
d3ce72d0 17043 switch (template_sequence[i].type)
461a49ca
DJ		 17044 {
17045 case ARM_TYPE:
48229727 17046 case THUMB32_TYPE:
461a49ca
DJ		 17047 size += 4;
17048 break;
17049
17050 case THUMB16_TYPE:
17051 size += 2;
17052 break;
17053
17054 case DATA_TYPE:
17055 size += 4;
17056 break;
17057
17058 default:
17059 BFD_FAIL ();
4e31c731 17060 return FALSE;
461a49ca
DJ		 17061 }
17062 }
17063
da5938a2
NC		 17064 return TRUE;
17065}
17066
33811162
DG		 17067/* Output mapping symbols for linker generated sections,
17068 and for those data-only sections that do not have a
17069 $d. */
4e617b1e
PB		 17070
17071static bfd_boolean
17072elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17073 struct bfd_link_info *info,
57402f1e 17074 void *flaginfo,
6e0b88f1
AM		 17075 int (*func) (void *, const char *,
17076 Elf_Internal_Sym *,
17077 asection *,
17078 struct elf_link_hash_entry *))
4e617b1e
PB		 17079{
17080 output_arch_syminfo osi;
17081 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17082 bfd_vma offset;
17083 bfd_size_type size;
33811162 17084 bfd *input_bfd;
4e617b1e
PB		 17085
17086 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17087 if (htab == NULL)
17088 return FALSE;
17089
906e58ca 17090 check_use_blx (htab);
91a5743d 17091
57402f1e 17092 osi.flaginfo = flaginfo;
4e617b1e
PB		 17093 osi.info = info;
17094 osi.func = func;
906e58ca 17095
33811162
DG		 17096 /* Add a $d mapping symbol to data-only sections that
17097 don't have any mapping symbol. This may result in (harmless) redundant
17098 mapping symbols. */
17099 for (input_bfd = info->input_bfds;
17100 input_bfd != NULL;
c72f2fb2 17101 input_bfd = input_bfd->link.next)
33811162
DG		 17102 {
17103 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17104 for (osi.sec = input_bfd->sections;
17105 osi.sec != NULL;
17106 osi.sec = osi.sec->next)
17107 {
17108 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17109 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17110 != 0)
33811162
DG		 17111 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17112 == SEC_HAS_CONTENTS
17113 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17114 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17115 && osi.sec->size > 0
17116 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17117 {
17118 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17119 (output_bfd, osi.sec->output_section);
17120 if (osi.sec_shndx != (int)SHN_BAD)
17121 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17122 }
17123 }
17124 }
17125
91a5743d
PB		 17126 /* ARM->Thumb glue. */
17127 if (htab->arm_glue_size > 0)
17128 {
3d4d4302
AM		 17129 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17130 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17131
17132 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17133 (output_bfd, osi.sec->output_section);
0e1862bb 17134 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17135 || htab->pic_veneer)
17136 size = ARM2THUMB_PIC_GLUE_SIZE;
17137 else if (htab->use_blx)
17138 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17139 else
17140 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17141
91a5743d
PB		 17142 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17143 {
7413f23f
DJ		 17144 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17145 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17146 }
17147 }
17148
17149 /* Thumb->ARM glue. */
17150 if (htab->thumb_glue_size > 0)
17151 {
3d4d4302
AM		 17152 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17153 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17154
17155 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17156 (output_bfd, osi.sec->output_section);
17157 size = THUMB2ARM_GLUE_SIZE;
17158
17159 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17160 {
7413f23f
DJ		 17161 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17162 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17163 }
17164 }
17165
845b51d6
PB		 17166 /* ARMv4 BX veneers. */
17167 if (htab->bx_glue_size > 0)
17168 {
3d4d4302
AM		 17169 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17170 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17171
17172 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17173 (output_bfd, osi.sec->output_section);
17174
7413f23f 17175 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17176 }
17177
8029a119
NC		 17178 /* Long calls stubs. */
17179 if (htab->stub_bfd && htab->stub_bfd->sections)
17180 {
da5938a2 17181 asection* stub_sec;
8029a119 17182
da5938a2
NC		 17183 for (stub_sec = htab->stub_bfd->sections;
17184 stub_sec != NULL;
8029a119
NC		 17185 stub_sec = stub_sec->next)
17186 {
17187 /* Ignore non-stub sections. */
17188 if (!strstr (stub_sec->name, STUB_SUFFIX))
17189 continue;
da5938a2 17190
8029a119 17191 osi.sec = stub_sec;
da5938a2 17192
8029a119
NC		 17193 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17194 (output_bfd, osi.sec->output_section);
da5938a2 17195
8029a119
NC		 17196 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17197 }
17198 }
da5938a2 17199
91a5743d 17200 /* Finally, output mapping symbols for the PLT. */
34e77a92 17201 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17202 {
34e77a92
RS		 17203 osi.sec = htab->root.splt;
17204 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17205 (output_bfd, osi.sec->output_section));
17206
17207 /* Output mapping symbols for the plt header. SymbianOS does not have a
17208 plt header. */
17209 if (htab->vxworks_p)
17210 {
17211 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17212 if (!bfd_link_pic (info))
34e77a92
RS		 17213 {
17214 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17215 return FALSE;
17216 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17217 return FALSE;
17218 }
17219 }
b38cadfb
NC		 17220 else if (htab->nacl_p)
17221 {
17222 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17223 return FALSE;
17224 }
eed94f8f
NC		 17225 else if (using_thumb_only (htab))
17226 {
17227 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17228 return FALSE;
17229 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17230 return FALSE;
17231 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17232 return FALSE;
17233 }
34e77a92 17234 else if (!htab->symbian_p)
4e617b1e 17235 {
7413f23f 17236 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17237 return FALSE;
34e77a92
RS		 17238#ifndef FOUR_WORD_PLT
17239 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17240 return FALSE;
34e77a92 17241#endif
4e617b1e
PB		 17242 }
17243 }
99059e56
RM		 17244 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17245 {
17246 /* NaCl uses a special first entry in .iplt too. */
17247 osi.sec = htab->root.iplt;
17248 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17249 (output_bfd, osi.sec->output_section));
17250 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17251 return FALSE;
17252 }
34e77a92
RS		 17253 if ((htab->root.splt && htab->root.splt->size > 0)
17254 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17255 {
34e77a92
RS		 17256 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17257 for (input_bfd = info->input_bfds;
17258 input_bfd != NULL;
c72f2fb2 17259 input_bfd = input_bfd->link.next)
34e77a92
RS		 17260 {
17261 struct arm_local_iplt_info **local_iplt;
17262 unsigned int i, num_syms;
4e617b1e 17263
34e77a92
RS		 17264 local_iplt = elf32_arm_local_iplt (input_bfd);
17265 if (local_iplt != NULL)
17266 {
17267 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17268 for (i = 0; i < num_syms; i++)
17269 if (local_iplt[i] != NULL
17270 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17271 &local_iplt[i]->root,
17272 &local_iplt[i]->arm))
17273 return FALSE;
17274 }
17275 }
17276 }
0855e32b
NS		 17277 if (htab->dt_tlsdesc_plt != 0)
17278 {
17279 /* Mapping symbols for the lazy tls trampoline. */
17280 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17281 return FALSE;
b38cadfb 17282
0855e32b
NS		 17283 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17284 htab->dt_tlsdesc_plt + 24))
17285 return FALSE;
17286 }
17287 if (htab->tls_trampoline != 0)
17288 {
17289 /* Mapping symbols for the tls trampoline. */
17290 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17291 return FALSE;
17292#ifdef FOUR_WORD_PLT
17293 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17294 htab->tls_trampoline + 12))
17295 return FALSE;
b38cadfb 17296#endif
0855e32b 17297 }
b38cadfb 17298
4e617b1e
PB		 17299 return TRUE;
17300}
17301
54ddd295
TP		 17302/* Filter normal symbols of CMSE entry functions of ABFD to include in
17303 the import library. All SYMCOUNT symbols of ABFD can be examined
17304 from their pointers in SYMS. Pointers of symbols to keep should be
17305 stored continuously at the beginning of that array.
17306
17307 Returns the number of symbols to keep. */
17308
17309static unsigned int
17310elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17311 struct bfd_link_info *info,
17312 asymbol **syms, long symcount)
17313{
17314 size_t maxnamelen;
17315 char *cmse_name;
17316 long src_count, dst_count = 0;
17317 struct elf32_arm_link_hash_table *htab;
17318
17319 htab = elf32_arm_hash_table (info);
17320 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17321 symcount = 0;
17322
17323 maxnamelen = 128;
17324 cmse_name = (char *) bfd_malloc (maxnamelen);
17325 for (src_count = 0; src_count < symcount; src_count++)
17326 {
17327 struct elf32_arm_link_hash_entry *cmse_hash;
17328 asymbol *sym;
17329 flagword flags;
17330 char *name;
17331 size_t namelen;
17332
17333 sym = syms[src_count];
17334 flags = sym->flags;
17335 name = (char *) bfd_asymbol_name (sym);
17336
17337 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17338 continue;
17339 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17340 continue;
17341
17342 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17343 if (namelen > maxnamelen)
17344 {
17345 cmse_name = (char *)
17346 bfd_realloc (cmse_name, namelen);
17347 maxnamelen = namelen;
17348 }
17349 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17350 cmse_hash = (struct elf32_arm_link_hash_entry *)
17351 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17352
17353 if (!cmse_hash
17354 || (cmse_hash->root.root.type != bfd_link_hash_defined
17355 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17356 || cmse_hash->root.type != STT_FUNC)
17357 continue;
17358
17359 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17360 continue;
17361
17362 syms[dst_count++] = sym;
17363 }
17364 free (cmse_name);
17365
17366 syms[dst_count] = NULL;
17367
17368 return dst_count;
17369}
17370
17371/* Filter symbols of ABFD to include in the import library. All
17372 SYMCOUNT symbols of ABFD can be examined from their pointers in
17373 SYMS. Pointers of symbols to keep should be stored continuously at
17374 the beginning of that array.
17375
17376 Returns the number of symbols to keep. */
17377
17378static unsigned int
17379elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17380 struct bfd_link_info *info,
17381 asymbol **syms, long symcount)
17382{
17383 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17384
046734ff
TP		 17385 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
17386 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
17387 library to be a relocatable object file. */
17388 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 17389 if (globals->cmse_implib)
17390 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17391 else
17392 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17393}
17394
e489d0ae
PB		 17395/* Allocate target specific section data. */
17396
17397static bfd_boolean
17398elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17399{
f592407e
AM		 17400 if (!sec->used_by_bfd)
17401 {
17402 _arm_elf_section_data *sdata;
17403 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17404
21d799b5 17405 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17406 if (sdata == NULL)
17407 return FALSE;
17408 sec->used_by_bfd = sdata;
17409 }
e489d0ae
PB		 17410
17411 return _bfd_elf_new_section_hook (abfd, sec);
17412}
17413
17414
17415/* Used to order a list of mapping symbols by address. */
17416
17417static int
17418elf32_arm_compare_mapping (const void * a, const void * b)
17419{
7f6a71ff
JM		 17420 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17421 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17422
17423 if (amap->vma > bmap->vma)
17424 return 1;
17425 else if (amap->vma < bmap->vma)
17426 return -1;
17427 else if (amap->type > bmap->type)
17428 /* Ensure results do not depend on the host qsort for objects with
17429 multiple mapping symbols at the same address by sorting on type
17430 after vma. */
17431 return 1;
17432 else if (amap->type < bmap->type)
17433 return -1;
17434 else
17435 return 0;
e489d0ae
PB		 17436}
17437
2468f9c9
PB		 17438/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17439
17440static unsigned long
17441offset_prel31 (unsigned long addr, bfd_vma offset)
17442{
17443 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17444}
17445
17446/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17447 relocations. */
17448
17449static void
17450copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17451{
17452 unsigned long first_word = bfd_get_32 (output_bfd, from);
17453 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17454
2468f9c9
PB		 17455 /* High bit of first word is supposed to be zero. */
17456 if ((first_word & 0x80000000ul) == 0)
17457 first_word = offset_prel31 (first_word, offset);
b38cadfb 17458
2468f9c9
PB		 17459 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17460 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17461 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17462 second_word = offset_prel31 (second_word, offset);
b38cadfb 17463
2468f9c9
PB		 17464 bfd_put_32 (output_bfd, first_word, to);
17465 bfd_put_32 (output_bfd, second_word, to + 4);
17466}
e489d0ae 17467
48229727
JB		 17468/* Data for make_branch_to_a8_stub(). */
17469
b38cadfb
NC		 17470struct a8_branch_to_stub_data
17471{
48229727
JB		 17472 asection *writing_section;
17473 bfd_byte *contents;
17474};
17475
17476
17477/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17478 places for a particular section. */
17479
17480static bfd_boolean
17481make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17482 void *in_arg)
48229727
JB		 17483{
17484 struct elf32_arm_stub_hash_entry *stub_entry;
17485 struct a8_branch_to_stub_data *data;
17486 bfd_byte *contents;
17487 unsigned long branch_insn;
17488 bfd_vma veneered_insn_loc, veneer_entry_loc;
17489 bfd_signed_vma branch_offset;
17490 bfd *abfd;
8d9d9490 17491 unsigned int loc;
48229727
JB		 17492
17493 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17494 data = (struct a8_branch_to_stub_data *) in_arg;
17495
17496 if (stub_entry->target_section != data->writing_section
4563a860 17497 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17498 return TRUE;
17499
17500 contents = data->contents;
17501
8d9d9490
TP		 17502 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17503 generated when both source and target are in the same section. */
48229727
JB		 17504 veneered_insn_loc = stub_entry->target_section->output_section->vma
17505 + stub_entry->target_section->output_offset
8d9d9490 17506 + stub_entry->source_value;
48229727
JB		 17507
17508 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17509 + stub_entry->stub_sec->output_offset
17510 + stub_entry->stub_offset;
17511
17512 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17513 veneered_insn_loc &= ~3u;
17514
17515 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17516
17517 abfd = stub_entry->target_section->owner;
8d9d9490 17518 loc = stub_entry->source_value;
48229727
JB		 17519
17520 /* We attempt to avoid this condition by setting stubs_always_after_branch
17521 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17522 This check is just to be on the safe side... */
17523 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17524 {
871b3ab2 17525 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 17526 "allocated in unsafe location"), abfd);
48229727
JB		 17527 return FALSE;
17528 }
17529
17530 switch (stub_entry->stub_type)
17531 {
17532 case arm_stub_a8_veneer_b:
17533 case arm_stub_a8_veneer_b_cond:
17534 branch_insn = 0xf0009000;
17535 goto jump24;
17536
17537 case arm_stub_a8_veneer_blx:
17538 branch_insn = 0xf000e800;
17539 goto jump24;
17540
17541 case arm_stub_a8_veneer_bl:
17542 {
17543 unsigned int i1, j1, i2, j2, s;
17544
17545 branch_insn = 0xf000d000;
17546
17547 jump24:
17548 if (branch_offset < -16777216 || branch_offset > 16777214)
17549 {
17550 /* There's not much we can do apart from complain if this
17551 happens. */
871b3ab2 17552 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 17553 "of range (input file too large)"), abfd);
48229727
JB		 17554 return FALSE;
17555 }
17556
17557 /* i1 = not(j1 eor s), so:
17558 not i1 = j1 eor s
17559 j1 = (not i1) eor s. */
17560
17561 branch_insn |= (branch_offset >> 1) & 0x7ff;
17562 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17563 i2 = (branch_offset >> 22) & 1;
17564 i1 = (branch_offset >> 23) & 1;
17565 s = (branch_offset >> 24) & 1;
17566 j1 = (!i1) ^ s;
17567 j2 = (!i2) ^ s;
17568 branch_insn |= j2 << 11;
17569 branch_insn |= j1 << 13;
17570 branch_insn |= s << 26;
17571 }
17572 break;
17573
17574 default:
17575 BFD_FAIL ();
17576 return FALSE;
17577 }
17578
8d9d9490
TP		 17579 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17580 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17581
17582 return TRUE;
17583}
17584
a504d23a
LA		 17585/* Beginning of stm32l4xx work-around. */
17586
17587/* Functions encoding instructions necessary for the emission of the
17588 fix-stm32l4xx-629360.
17589 Encoding is extracted from the
17590 ARM (C) Architecture Reference Manual
17591 ARMv7-A and ARMv7-R edition
17592 ARM DDI 0406C.b (ID072512). */
17593
17594static inline bfd_vma
82188b29 17595create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17596{
17597 /* A8.8.18 B (A8-334)
17598 B target_address (Encoding T4). */
17599 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17600 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17601 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17602
a504d23a
LA		 17603 int s = ((branch_offset & 0x1000000) >> 24);
17604 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17605 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17606
17607 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17608 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17609
17610 bfd_vma patched_inst = 0xf0009000
17611 | s << 26 /* S. */
17612 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17613 | j1 << 13 /* J1. */
17614 | j2 << 11 /* J2. */
17615 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17616
17617 return patched_inst;
17618}
17619
17620static inline bfd_vma
17621create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17622{
17623 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17624 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17625 bfd_vma patched_inst = 0xe8900000
17626 | (/*W=*/wback << 21)
17627 | (base_reg << 16)
17628 | (reg_mask & 0x0000ffff);
17629
17630 return patched_inst;
17631}
17632
17633static inline bfd_vma
17634create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17635{
17636 /* A8.8.60 LDMDB/LDMEA (A8-402)
17637 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17638 bfd_vma patched_inst = 0xe9100000
17639 | (/*W=*/wback << 21)
17640 | (base_reg << 16)
17641 | (reg_mask & 0x0000ffff);
17642
17643 return patched_inst;
17644}
17645
17646static inline bfd_vma
17647create_instruction_mov (int target_reg, int source_reg)
17648{
17649 /* A8.8.103 MOV (register) (A8-486)
17650 MOV Rd, Rm (Encoding T1). */
17651 bfd_vma patched_inst = 0x4600
17652 | (target_reg & 0x7)
17653 | ((target_reg & 0x8) >> 3) << 7
17654 | (source_reg << 3);
17655
17656 return patched_inst;
17657}
17658
17659static inline bfd_vma
17660create_instruction_sub (int target_reg, int source_reg, int value)
17661{
17662 /* A8.8.221 SUB (immediate) (A8-708)
17663 SUB Rd, Rn, #value (Encoding T3). */
17664 bfd_vma patched_inst = 0xf1a00000
17665 | (target_reg << 8)
17666 | (source_reg << 16)
17667 | (/*S=*/0 << 20)
17668 | ((value & 0x800) >> 11) << 26
17669 | ((value & 0x700) >> 8) << 12
17670 | (value & 0x0ff);
17671
17672 return patched_inst;
17673}
17674
17675static inline bfd_vma
9239bbd3 17676create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17677 int first_reg)
17678{
17679 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17680 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17681 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17682 | (/*W=*/wback << 21)
17683 | (base_reg << 16)
9239bbd3
CM		 17684 | (num_words & 0x000000ff)
17685 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17686 | (first_reg & 0x00000001) << 22;
17687
17688 return patched_inst;
17689}
17690
17691static inline bfd_vma
9239bbd3
CM		 17692create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17693 int first_reg)
a504d23a
LA		 17694{
17695 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17696 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17697 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17698 | (base_reg << 16)
9239bbd3
CM		 17699 | (num_words & 0x000000ff)
17700 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17701 | (first_reg & 0x00000001) << 22;
17702
17703 return patched_inst;
17704}
17705
17706static inline bfd_vma
17707create_instruction_udf_w (int value)
17708{
17709 /* A8.8.247 UDF (A8-758)
17710 Undefined (Encoding T2). */
17711 bfd_vma patched_inst = 0xf7f0a000
17712 | (value & 0x00000fff)
17713 | (value & 0x000f0000) << 16;
17714
17715 return patched_inst;
17716}
17717
17718static inline bfd_vma
17719create_instruction_udf (int value)
17720{
17721 /* A8.8.247 UDF (A8-758)
17722 Undefined (Encoding T1). */
17723 bfd_vma patched_inst = 0xde00
17724 | (value & 0xff);
17725
17726 return patched_inst;
17727}
17728
17729/* Functions writing an instruction in memory, returning the next
17730 memory position to write to. */
17731
17732static inline bfd_byte *
17733push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17734 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17735{
17736 put_thumb2_insn (htab, output_bfd, insn, pt);
17737 return pt + 4;
17738}
17739
17740static inline bfd_byte *
17741push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17742 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17743{
17744 put_thumb_insn (htab, output_bfd, insn, pt);
17745 return pt + 2;
17746}
17747
17748/* Function filling up a region in memory with T1 and T2 UDFs taking
17749 care of alignment. */
17750
17751static bfd_byte *
17752stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 17753 bfd * output_bfd,
17754 const bfd_byte * const base_stub_contents,
17755 bfd_byte * const from_stub_contents,
17756 const bfd_byte * const end_stub_contents)
a504d23a
LA		 17757{
17758 bfd_byte *current_stub_contents = from_stub_contents;
17759
17760 /* Fill the remaining of the stub with deterministic contents : UDF
17761 instructions.
17762 Check if realignment is needed on modulo 4 frontier using T1, to
17763 further use T2. */
17764 if ((current_stub_contents < end_stub_contents)
17765 && !((current_stub_contents - base_stub_contents) % 2)
17766 && ((current_stub_contents - base_stub_contents) % 4))
17767 current_stub_contents =
17768 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17769 create_instruction_udf (0));
17770
17771 for (; current_stub_contents < end_stub_contents;)
17772 current_stub_contents =
17773 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17774 create_instruction_udf_w (0));
17775
17776 return current_stub_contents;
17777}
17778
17779/* Functions writing the stream of instructions equivalent to the
17780 derived sequence for ldmia, ldmdb, vldm respectively. */
17781
17782static void
17783stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17784 bfd * output_bfd,
17785 const insn32 initial_insn,
17786 const bfd_byte *const initial_insn_addr,
17787 bfd_byte *const base_stub_contents)
17788{
17789 int wback = (initial_insn & 0x00200000) >> 21;
17790 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17791 int insn_all_registers = initial_insn & 0x0000ffff;
17792 int insn_low_registers, insn_high_registers;
17793 int usable_register_mask;
b25e998d 17794 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17795 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17796 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17797 bfd_byte *current_stub_contents = base_stub_contents;
17798
17799 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17800
17801 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17802 smaller than 8 registers load sequences that do not cause the
17803 hardware issue. */
17804 if (nb_registers <= 8)
17805 {
17806 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17807 current_stub_contents =
17808 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17809 initial_insn);
17810
17811 /* B initial_insn_addr+4. */
17812 if (!restore_pc)
17813 current_stub_contents =
17814 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17815 create_instruction_branch_absolute
82188b29 17816 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17817
17818 /* Fill the remaining of the stub with deterministic contents. */
17819 current_stub_contents =
17820 stm32l4xx_fill_stub_udf (htab, output_bfd,
17821 base_stub_contents, current_stub_contents,
17822 base_stub_contents +
17823 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17824
17825 return;
17826 }
17827
17828 /* - reg_list[13] == 0. */
17829 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17830
17831 /* - reg_list[14] & reg_list[15] != 1. */
17832 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17833
17834 /* - if (wback==1) reg_list[rn] == 0. */
17835 BFD_ASSERT (!wback || !restore_rn);
17836
17837 /* - nb_registers > 8. */
b25e998d 17838 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17839
17840 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17841
17842 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17843 - One with the 7 lowest registers (register mask 0x007F)
17844 This LDM will finally contain between 2 and 7 registers
17845 - One with the 7 highest registers (register mask 0xDF80)
17846 This ldm will finally contain between 2 and 7 registers. */
17847 insn_low_registers = insn_all_registers & 0x007F;
17848 insn_high_registers = insn_all_registers & 0xDF80;
17849
17850 /* A spare register may be needed during this veneer to temporarily
17851 handle the base register. This register will be restored with the
17852 last LDM operation.
17853 The usable register may be any general purpose register (that
17854 excludes PC, SP, LR : register mask is 0x1FFF). */
17855 usable_register_mask = 0x1FFF;
17856
17857 /* Generate the stub function. */
17858 if (wback)
17859 {
17860 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17861 current_stub_contents =
17862 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17863 create_instruction_ldmia
17864 (rn, /*wback=*/1, insn_low_registers));
17865
17866 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17867 current_stub_contents =
17868 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17869 create_instruction_ldmia
17870 (rn, /*wback=*/1, insn_high_registers));
17871 if (!restore_pc)
17872 {
17873 /* B initial_insn_addr+4. */
17874 current_stub_contents =
17875 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17876 create_instruction_branch_absolute
82188b29 17877 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17878 }
17879 }
17880 else /* if (!wback). */
17881 {
17882 ri = rn;
17883
17884 /* If Rn is not part of the high-register-list, move it there. */
17885 if (!(insn_high_registers & (1 << rn)))
17886 {
17887 /* Choose a Ri in the high-register-list that will be restored. */
17888 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17889
17890 /* MOV Ri, Rn. */
17891 current_stub_contents =
17892 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17893 create_instruction_mov (ri, rn));
17894 }
17895
17896 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
17897 current_stub_contents =
17898 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17899 create_instruction_ldmia
17900 (ri, /*wback=*/1, insn_low_registers));
17901
17902 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
17903 current_stub_contents =
17904 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17905 create_instruction_ldmia
17906 (ri, /*wback=*/0, insn_high_registers));
17907
17908 if (!restore_pc)
17909 {
17910 /* B initial_insn_addr+4. */
17911 current_stub_contents =
17912 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17913 create_instruction_branch_absolute
82188b29 17914 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17915 }
17916 }
17917
17918 /* Fill the remaining of the stub with deterministic contents. */
17919 current_stub_contents =
17920 stm32l4xx_fill_stub_udf (htab, output_bfd,
17921 base_stub_contents, current_stub_contents,
17922 base_stub_contents +
17923 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17924}
17925
17926static void
17927stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
17928 bfd * output_bfd,
17929 const insn32 initial_insn,
17930 const bfd_byte *const initial_insn_addr,
17931 bfd_byte *const base_stub_contents)
17932{
17933 int wback = (initial_insn & 0x00200000) >> 21;
17934 int ri, rn = (initial_insn & 0x000f0000) >> 16;
17935 int insn_all_registers = initial_insn & 0x0000ffff;
17936 int insn_low_registers, insn_high_registers;
17937 int usable_register_mask;
17938 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17939 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 17940 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17941 bfd_byte *current_stub_contents = base_stub_contents;
17942
17943 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
17944
17945 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17946 smaller than 8 registers load sequences that do not cause the
17947 hardware issue. */
17948 if (nb_registers <= 8)
17949 {
17950 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17951 current_stub_contents =
17952 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17953 initial_insn);
17954
17955 /* B initial_insn_addr+4. */
17956 current_stub_contents =
17957 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17958 create_instruction_branch_absolute
82188b29 17959 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17960
17961 /* Fill the remaining of the stub with deterministic contents. */
17962 current_stub_contents =
17963 stm32l4xx_fill_stub_udf (htab, output_bfd,
17964 base_stub_contents, current_stub_contents,
17965 base_stub_contents +
17966 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17967
17968 return;
17969 }
17970
17971 /* - reg_list[13] == 0. */
17972 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
17973
17974 /* - reg_list[14] & reg_list[15] != 1. */
17975 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17976
17977 /* - if (wback==1) reg_list[rn] == 0. */
17978 BFD_ASSERT (!wback || !restore_rn);
17979
17980 /* - nb_registers > 8. */
b25e998d 17981 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17982
17983 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17984
17985 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
17986 - One with the 7 lowest registers (register mask 0x007F)
17987 This LDM will finally contain between 2 and 7 registers
17988 - One with the 7 highest registers (register mask 0xDF80)
17989 This ldm will finally contain between 2 and 7 registers. */
17990 insn_low_registers = insn_all_registers & 0x007F;
17991 insn_high_registers = insn_all_registers & 0xDF80;
17992
17993 /* A spare register may be needed during this veneer to temporarily
17994 handle the base register. This register will be restored with
17995 the last LDM operation.
17996 The usable register may be any general purpose register (that excludes
17997 PC, SP, LR : register mask is 0x1FFF). */
17998 usable_register_mask = 0x1FFF;
17999
18000 /* Generate the stub function. */
18001 if (!wback && !restore_pc && !restore_rn)
18002 {
18003 /* Choose a Ri in the low-register-list that will be restored. */
18004 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18005
18006 /* MOV Ri, Rn. */
18007 current_stub_contents =
18008 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18009 create_instruction_mov (ri, rn));
18010
18011 /* LDMDB Ri!, {R-high-register-list}. */
18012 current_stub_contents =
18013 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18014 create_instruction_ldmdb
18015 (ri, /*wback=*/1, insn_high_registers));
18016
18017 /* LDMDB Ri, {R-low-register-list}. */
18018 current_stub_contents =
18019 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18020 create_instruction_ldmdb
18021 (ri, /*wback=*/0, insn_low_registers));
18022
18023 /* B initial_insn_addr+4. */
18024 current_stub_contents =
18025 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18026 create_instruction_branch_absolute
82188b29 18027 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18028 }
18029 else if (wback && !restore_pc && !restore_rn)
18030 {
18031 /* LDMDB Rn!, {R-high-register-list}. */
18032 current_stub_contents =
18033 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18034 create_instruction_ldmdb
18035 (rn, /*wback=*/1, insn_high_registers));
18036
18037 /* LDMDB Rn!, {R-low-register-list}. */
18038 current_stub_contents =
18039 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18040 create_instruction_ldmdb
18041 (rn, /*wback=*/1, insn_low_registers));
18042
18043 /* B initial_insn_addr+4. */
18044 current_stub_contents =
18045 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18046 create_instruction_branch_absolute
82188b29 18047 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18048 }
18049 else if (!wback && restore_pc && !restore_rn)
18050 {
18051 /* Choose a Ri in the high-register-list that will be restored. */
18052 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18053
18054 /* SUB Ri, Rn, #(4*nb_registers). */
18055 current_stub_contents =
18056 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18057 create_instruction_sub (ri, rn, (4 * nb_registers)));
18058
18059 /* LDMIA Ri!, {R-low-register-list}. */
18060 current_stub_contents =
18061 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18062 create_instruction_ldmia
18063 (ri, /*wback=*/1, insn_low_registers));
18064
18065 /* LDMIA Ri, {R-high-register-list}. */
18066 current_stub_contents =
18067 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18068 create_instruction_ldmia
18069 (ri, /*wback=*/0, insn_high_registers));
18070 }
18071 else if (wback && restore_pc && !restore_rn)
18072 {
18073 /* Choose a Ri in the high-register-list that will be restored. */
18074 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18075
18076 /* SUB Rn, Rn, #(4*nb_registers) */
18077 current_stub_contents =
18078 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18079 create_instruction_sub (rn, rn, (4 * nb_registers)));
18080
18081 /* MOV Ri, Rn. */
18082 current_stub_contents =
18083 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18084 create_instruction_mov (ri, rn));
18085
18086 /* LDMIA Ri!, {R-low-register-list}. */
18087 current_stub_contents =
18088 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18089 create_instruction_ldmia
18090 (ri, /*wback=*/1, insn_low_registers));
18091
18092 /* LDMIA Ri, {R-high-register-list}. */
18093 current_stub_contents =
18094 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18095 create_instruction_ldmia
18096 (ri, /*wback=*/0, insn_high_registers));
18097 }
18098 else if (!wback && !restore_pc && restore_rn)
18099 {
18100 ri = rn;
18101 if (!(insn_low_registers & (1 << rn)))
18102 {
18103 /* Choose a Ri in the low-register-list that will be restored. */
18104 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18105
18106 /* MOV Ri, Rn. */
18107 current_stub_contents =
18108 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18109 create_instruction_mov (ri, rn));
18110 }
18111
18112 /* LDMDB Ri!, {R-high-register-list}. */
18113 current_stub_contents =
18114 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18115 create_instruction_ldmdb
18116 (ri, /*wback=*/1, insn_high_registers));
18117
18118 /* LDMDB Ri, {R-low-register-list}. */
18119 current_stub_contents =
18120 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18121 create_instruction_ldmdb
18122 (ri, /*wback=*/0, insn_low_registers));
18123
18124 /* B initial_insn_addr+4. */
18125 current_stub_contents =
18126 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18127 create_instruction_branch_absolute
82188b29 18128 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18129 }
18130 else if (!wback && restore_pc && restore_rn)
18131 {
18132 ri = rn;
18133 if (!(insn_high_registers & (1 << rn)))
18134 {
18135 /* Choose a Ri in the high-register-list that will be restored. */
18136 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18137 }
18138
18139 /* SUB Ri, Rn, #(4*nb_registers). */
18140 current_stub_contents =
18141 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18142 create_instruction_sub (ri, rn, (4 * nb_registers)));
18143
18144 /* LDMIA Ri!, {R-low-register-list}. */
18145 current_stub_contents =
18146 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18147 create_instruction_ldmia
18148 (ri, /*wback=*/1, insn_low_registers));
18149
18150 /* LDMIA Ri, {R-high-register-list}. */
18151 current_stub_contents =
18152 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18153 create_instruction_ldmia
18154 (ri, /*wback=*/0, insn_high_registers));
18155 }
18156 else if (wback && restore_rn)
18157 {
18158 /* The assembler should not have accepted to encode this. */
18159 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18160 "undefined behavior.\n");
18161 }
18162
18163 /* Fill the remaining of the stub with deterministic contents. */
18164 current_stub_contents =
18165 stm32l4xx_fill_stub_udf (htab, output_bfd,
18166 base_stub_contents, current_stub_contents,
18167 base_stub_contents +
18168 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18169
18170}
18171
18172static void
18173stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18174 bfd * output_bfd,
18175 const insn32 initial_insn,
18176 const bfd_byte *const initial_insn_addr,
18177 bfd_byte *const base_stub_contents)
18178{
9239bbd3 18179 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18180 bfd_byte *current_stub_contents = base_stub_contents;
18181
18182 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18183
18184 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18185 smaller than 8 words load sequences that do not cause the
a504d23a 18186 hardware issue. */
9239bbd3 18187 if (num_words <= 8)
a504d23a
LA		 18188 {
18189 /* Untouched instruction. */
18190 current_stub_contents =
18191 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18192 initial_insn);
18193
18194 /* B initial_insn_addr+4. */
18195 current_stub_contents =
18196 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18197 create_instruction_branch_absolute
82188b29 18198 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18199 }
18200 else
18201 {
9eaff861 18202 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18203 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18204 bfd_boolean is_ia_nobang = /* (IA without !). */
18205 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18206 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18207 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18208 bfd_boolean is_db_bang = /* (DB with !). */
18209 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18210 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18211 /* d = UInt (Vd:D);. */
9239bbd3 18212 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18213 | (((unsigned int)initial_insn << 9) >> 31);
18214
9239bbd3
CM		 18215 /* Compute the number of 8-words chunks needed to split. */
18216 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18217 int chunk;
18218
18219 /* The test coverage has been done assuming the following
18220 hypothesis that exactly one of the previous is_ predicates is
18221 true. */
9239bbd3
CM		 18222 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18223 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18224
9239bbd3 18225 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18226 cases, then we emit the adjustments:
18227
18228 vldm rx, {...}
18229 -> vldm rx!, {8_words_or_less} for each needed 8_word
18230 -> sub rx, rx, #size (list)
18231
18232 vldm rx!, {...}
18233 -> vldm rx!, {8_words_or_less} for each needed 8_word
18234 This also handles vpop instruction (when rx is sp)
18235
18236 vldmd rx!, {...}
18237 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18238 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18239 {
9239bbd3
CM		 18240 bfd_vma new_insn = 0;
18241
a504d23a
LA		 18242 if (is_ia_nobang || is_ia_bang)
18243 {
9239bbd3
CM		 18244 new_insn = create_instruction_vldmia
18245 (base_reg,
18246 is_dp,
18247 /*wback= . */1,
18248 chunks - (chunk + 1) ?
18249 8 : num_words - chunk * 8,
18250 first_reg + chunk * 8);
a504d23a
LA		 18251 }
18252 else if (is_db_bang)
18253 {
9239bbd3
CM		 18254 new_insn = create_instruction_vldmdb
18255 (base_reg,
18256 is_dp,
18257 chunks - (chunk + 1) ?
18258 8 : num_words - chunk * 8,
18259 first_reg + chunk * 8);
a504d23a 18260 }
9239bbd3
CM		 18261
18262 if (new_insn)
18263 current_stub_contents =
18264 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18265 new_insn);
a504d23a
LA		 18266 }
18267
18268 /* Only this case requires the base register compensation
18269 subtract. */
18270 if (is_ia_nobang)
18271 {
18272 current_stub_contents =
18273 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18274 create_instruction_sub
9239bbd3 18275 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18276 }
18277
18278 /* B initial_insn_addr+4. */
18279 current_stub_contents =
18280 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18281 create_instruction_branch_absolute
82188b29 18282 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18283 }
18284
18285 /* Fill the remaining of the stub with deterministic contents. */
18286 current_stub_contents =
18287 stm32l4xx_fill_stub_udf (htab, output_bfd,
18288 base_stub_contents, current_stub_contents,
18289 base_stub_contents +
18290 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18291}
18292
18293static void
18294stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18295 bfd * output_bfd,
18296 const insn32 wrong_insn,
18297 const bfd_byte *const wrong_insn_addr,
18298 bfd_byte *const stub_contents)
18299{
18300 if (is_thumb2_ldmia (wrong_insn))
18301 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18302 wrong_insn, wrong_insn_addr,
18303 stub_contents);
18304 else if (is_thumb2_ldmdb (wrong_insn))
18305 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18306 wrong_insn, wrong_insn_addr,
18307 stub_contents);
18308 else if (is_thumb2_vldm (wrong_insn))
18309 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18310 wrong_insn, wrong_insn_addr,
18311 stub_contents);
18312}
18313
18314/* End of stm32l4xx work-around. */
18315
18316
e489d0ae
PB		 18317/* Do code byteswapping. Return FALSE afterwards so that the section is
18318 written out as normal. */
18319
18320static bfd_boolean
c7b8f16e 18321elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18322 struct bfd_link_info *link_info,
18323 asection *sec,
e489d0ae
PB		 18324 bfd_byte *contents)
18325{
48229727 18326 unsigned int mapcount, errcount;
8e3de13a 18327 _arm_elf_section_data *arm_data;
c7b8f16e 18328 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18329 elf32_arm_section_map *map;
c7b8f16e 18330 elf32_vfp11_erratum_list *errnode;
a504d23a 18331 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18332 bfd_vma ptr;
18333 bfd_vma end;
c7b8f16e 18334 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18335 bfd_byte tmp;
48229727 18336 unsigned int i;
57e8b36a 18337
4dfe6ac6
NC		 18338 if (globals == NULL)
18339 return FALSE;
18340
8e3de13a
NC		 18341 /* If this section has not been allocated an _arm_elf_section_data
18342 structure then we cannot record anything. */
18343 arm_data = get_arm_elf_section_data (sec);
18344 if (arm_data == NULL)
18345 return FALSE;
18346
18347 mapcount = arm_data->mapcount;
18348 map = arm_data->map;
c7b8f16e
JB		 18349 errcount = arm_data->erratumcount;
18350
18351 if (errcount != 0)
18352 {
18353 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18354
18355 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18356 errnode = errnode->next)
18357 {
18358 bfd_vma target = errnode->vma - offset;
18359
18360 switch (errnode->type)
18361 {
18362 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18363 {
18364 bfd_vma branch_to_veneer;
18365 /* Original condition code of instruction, plus bit mask for
18366 ARM B instruction. */
18367 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18368 | 0x0a000000;
c7b8f16e
JB		 18369
18370 /* The instruction is before the label. */
91d6fa6a 18371 target -= 4;
c7b8f16e
JB		 18372
18373 /* Above offset included in -4 below. */
18374 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18375 - errnode->vma - 4;
c7b8f16e
JB		 18376
18377 if ((signed) branch_to_veneer < -(1 << 25)
18378 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 18379 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 18380 "range"), output_bfd);
c7b8f16e 18381
99059e56
RM		 18382 insn |= (branch_to_veneer >> 2) & 0xffffff;
18383 contents[endianflip ^ target] = insn & 0xff;
18384 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18385 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18386 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18387 }
18388 break;
c7b8f16e
JB		 18389
18390 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18391 {
18392 bfd_vma branch_from_veneer;
18393 unsigned int insn;
c7b8f16e 18394
99059e56
RM		 18395 /* Take size of veneer into account. */
18396 branch_from_veneer = errnode->u.v.branch->vma
18397 - errnode->vma - 12;
c7b8f16e
JB		 18398
18399 if ((signed) branch_from_veneer < -(1 << 25)
18400 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 18401 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 18402 "range"), output_bfd);
c7b8f16e 18403
99059e56
RM		 18404 /* Original instruction. */
18405 insn = errnode->u.v.branch->u.b.vfp_insn;
18406 contents[endianflip ^ target] = insn & 0xff;
18407 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18408 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18409 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18410
18411 /* Branch back to insn after original insn. */
18412 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18413 contents[endianflip ^ (target + 4)] = insn & 0xff;
18414 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18415 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18416 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18417 }
18418 break;
c7b8f16e 18419
99059e56
RM		 18420 default:
18421 abort ();
18422 }
18423 }
c7b8f16e 18424 }
e489d0ae 18425
a504d23a
LA		 18426 if (arm_data->stm32l4xx_erratumcount != 0)
18427 {
18428 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18429 stm32l4xx_errnode != 0;
18430 stm32l4xx_errnode = stm32l4xx_errnode->next)
18431 {
18432 bfd_vma target = stm32l4xx_errnode->vma - offset;
18433
18434 switch (stm32l4xx_errnode->type)
18435 {
18436 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18437 {
18438 unsigned int insn;
18439 bfd_vma branch_to_veneer =
18440 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18441
18442 if ((signed) branch_to_veneer < -(1 << 24)
18443 || (signed) branch_to_veneer >= (1 << 24))
18444 {
18445 bfd_vma out_of_range =
18446 ((signed) branch_to_veneer < -(1 << 24)) ?
18447 - branch_to_veneer - (1 << 24) :
18448 ((signed) branch_to_veneer >= (1 << 24)) ?
18449 branch_to_veneer - (1 << 24) : 0;
18450
4eca0228 18451 _bfd_error_handler
2dcf00ce 18452 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 18453 "cannot create STM32L4XX veneer; "
18454 "jump out of range by %" PRId64 " bytes; "
18455 "cannot encode branch instruction"),
a504d23a 18456 output_bfd,
2dcf00ce
AM		 18457 (uint64_t) (stm32l4xx_errnode->vma - 4),
18458 (int64_t) out_of_range);
a504d23a
LA		 18459 continue;
18460 }
18461
18462 insn = create_instruction_branch_absolute
82188b29 18463 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18464
18465 /* The instruction is before the label. */
18466 target -= 4;
18467
18468 put_thumb2_insn (globals, output_bfd,
18469 (bfd_vma) insn, contents + target);
18470 }
18471 break;
18472
18473 case STM32L4XX_ERRATUM_VENEER:
18474 {
82188b29
NC		 18475 bfd_byte * veneer;
18476 bfd_byte * veneer_r;
a504d23a
LA		 18477 unsigned int insn;
18478
82188b29
NC		 18479 veneer = contents + target;
18480 veneer_r = veneer
18481 + stm32l4xx_errnode->u.b.veneer->vma
18482 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18483
18484 if ((signed) (veneer_r - veneer -
18485 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18486 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18487 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18488 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18489 || (signed) (veneer_r - veneer) >= (1 << 24))
18490 {
90b6238f
AM		 18491 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
18492 "veneer"), output_bfd);
a504d23a
LA		 18493 continue;
18494 }
18495
18496 /* Original instruction. */
18497 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18498
18499 stm32l4xx_create_replacing_stub
18500 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18501 }
18502 break;
18503
18504 default:
18505 abort ();
18506 }
18507 }
18508 }
18509
2468f9c9
PB		 18510 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18511 {
18512 arm_unwind_table_edit *edit_node
99059e56 18513 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18514 /* Now, sec->size is the size of the section we will write. The original
99059e56 18515 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18516 markers) was sec->rawsize. (This isn't the case if we perform no
18517 edits, then rawsize will be zero and we should use size). */
21d799b5 18518 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18519 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18520 unsigned int in_index, out_index;
18521 bfd_vma add_to_offsets = 0;
18522
18523 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18524 {
2468f9c9
PB		 18525 if (edit_node)
18526 {
18527 unsigned int edit_index = edit_node->index;
b38cadfb 18528
2468f9c9 18529 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18530 {
2468f9c9
PB		 18531 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18532 contents + in_index * 8, add_to_offsets);
18533 out_index++;
18534 in_index++;
18535 }
18536 else if (in_index == edit_index
18537 || (in_index * 8 >= input_size
18538 && edit_index == UINT_MAX))
99059e56 18539 {
2468f9c9
PB		 18540 switch (edit_node->type)
18541 {
18542 case DELETE_EXIDX_ENTRY:
18543 in_index++;
18544 add_to_offsets += 8;
18545 break;
b38cadfb 18546
2468f9c9
PB		 18547 case INSERT_EXIDX_CANTUNWIND_AT_END:
18548 {
99059e56 18549 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18550 bfd_vma text_offset = text_sec->output_section->vma
18551 + text_sec->output_offset
18552 + text_sec->size;
18553 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18554 unsigned long prel31_offset;
2468f9c9
PB		 18555
18556 /* Note: this is meant to be equivalent to an
18557 R_ARM_PREL31 relocation. These synthetic
18558 EXIDX_CANTUNWIND markers are not relocated by the
18559 usual BFD method. */
18560 prel31_offset = (text_offset - exidx_offset)
18561 & 0x7ffffffful;
491d01d3
YU		 18562 if (bfd_link_relocatable (link_info))
18563 {
18564 /* Here relocation for new EXIDX_CANTUNWIND is
18565 created, so there is no need to
18566 adjust offset by hand. */
18567 prel31_offset = text_sec->output_offset
18568 + text_sec->size;
491d01d3 18569 }
2468f9c9
PB		 18570
18571 /* First address we can't unwind. */
18572 bfd_put_32 (output_bfd, prel31_offset,
18573 &edited_contents[out_index * 8]);
18574
18575 /* Code for EXIDX_CANTUNWIND. */
18576 bfd_put_32 (output_bfd, 0x1,
18577 &edited_contents[out_index * 8 + 4]);
18578
18579 out_index++;
18580 add_to_offsets -= 8;
18581 }
18582 break;
18583 }
b38cadfb 18584
2468f9c9
PB		 18585 edit_node = edit_node->next;
18586 }
18587 }
18588 else
18589 {
18590 /* No more edits, copy remaining entries verbatim. */
18591 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18592 contents + in_index * 8, add_to_offsets);
18593 out_index++;
18594 in_index++;
18595 }
18596 }
18597
18598 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18599 bfd_set_section_contents (output_bfd, sec->output_section,
18600 edited_contents,
18601 (file_ptr) sec->output_offset, sec->size);
18602
18603 return TRUE;
18604 }
18605
48229727
JB		 18606 /* Fix code to point to Cortex-A8 erratum stubs. */
18607 if (globals->fix_cortex_a8)
18608 {
18609 struct a8_branch_to_stub_data data;
18610
18611 data.writing_section = sec;
18612 data.contents = contents;
18613
a504d23a
LA		 18614 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18615 & data);
48229727
JB		 18616 }
18617
e489d0ae
PB		 18618 if (mapcount == 0)
18619 return FALSE;
18620
c7b8f16e 18621 if (globals->byteswap_code)
e489d0ae 18622 {
c7b8f16e 18623 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18624
c7b8f16e
JB		 18625 ptr = map[0].vma;
18626 for (i = 0; i < mapcount; i++)
99059e56
RM		 18627 {
18628 if (i == mapcount - 1)
c7b8f16e 18629 end = sec->size;
99059e56
RM		 18630 else
18631 end = map[i + 1].vma;
e489d0ae 18632
99059e56 18633 switch (map[i].type)
e489d0ae 18634 {
c7b8f16e
JB		 18635 case 'a':
18636 /* Byte swap code words. */
18637 while (ptr + 3 < end)
99059e56
RM		 18638 {
18639 tmp = contents[ptr];
18640 contents[ptr] = contents[ptr + 3];
18641 contents[ptr + 3] = tmp;
18642 tmp = contents[ptr + 1];
18643 contents[ptr + 1] = contents[ptr + 2];
18644 contents[ptr + 2] = tmp;
18645 ptr += 4;
18646 }
c7b8f16e 18647 break;
e489d0ae 18648
c7b8f16e
JB		 18649 case 't':
18650 /* Byte swap code halfwords. */
18651 while (ptr + 1 < end)
99059e56
RM		 18652 {
18653 tmp = contents[ptr];
18654 contents[ptr] = contents[ptr + 1];
18655 contents[ptr + 1] = tmp;
18656 ptr += 2;
18657 }
c7b8f16e
JB		 18658 break;
18659
18660 case 'd':
18661 /* Leave data alone. */
18662 break;
18663 }
99059e56
RM		 18664 ptr = end;
18665 }
e489d0ae 18666 }
8e3de13a 18667
93204d3a 18668 free (map);
47b2e99c 18669 arm_data->mapcount = -1;
c7b8f16e 18670 arm_data->mapsize = 0;
8e3de13a 18671 arm_data->map = NULL;
8e3de13a 18672
e489d0ae
PB		 18673 return FALSE;
18674}
18675
0beaef2b
PB		 18676/* Mangle thumb function symbols as we read them in. */
18677
8384fb8f 18678static bfd_boolean
0beaef2b
PB		 18679elf32_arm_swap_symbol_in (bfd * abfd,
18680 const void *psrc,
18681 const void *pshn,
18682 Elf_Internal_Sym *dst)
18683{
4ba2ef8f
TP		 18684 Elf_Internal_Shdr *symtab_hdr;
18685 const char *name = NULL;
18686
8384fb8f
AM		 18687 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18688 return FALSE;
39d911fc 18689 dst->st_target_internal = 0;
0beaef2b
PB		 18690
18691 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18692 the address. */
63e1a0fc
PB		 18693 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18694 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18695 {
63e1a0fc
PB		 18696 if (dst->st_value & 1)
18697 {
18698 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18699 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18700 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18701 }
18702 else
39d911fc 18703 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18704 }
18705 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18706 {
18707 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18708 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18709 }
35fc36a8 18710 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18711 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18712 else
39d911fc 18713 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18714
4ba2ef8f
TP		 18715 /* Mark CMSE special symbols. */
18716 symtab_hdr = & elf_symtab_hdr (abfd);
18717 if (symtab_hdr->sh_size)
18718 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18719 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18720 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18721
8384fb8f 18722 return TRUE;
0beaef2b
PB		 18723}
18724
18725
18726/* Mangle thumb function symbols as we write them out. */
18727
18728static void
18729elf32_arm_swap_symbol_out (bfd *abfd,
18730 const Elf_Internal_Sym *src,
18731 void *cdst,
18732 void *shndx)
18733{
18734 Elf_Internal_Sym newsym;
18735
18736 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18737 of the address set, as per the new EABI. We do this unconditionally
18738 because objcopy does not set the elf header flags until after
18739 it writes out the symbol table. */
39d911fc 18740 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18741 {
18742 newsym = *src;
34e77a92
RS		 18743 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18744 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18745 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18746 {
18747 /* Do this only for defined symbols. At link type, the static
18748 linker will simulate the work of dynamic linker of resolving
18749 symbols and will carry over the thumbness of found symbols to
18750 the output symbol table. It's not clear how it happens, but
18751 the thumbness of undefined symbols can well be different at
18752 runtime, and writing '1' for them will be confusing for users
18753 and possibly for dynamic linker itself.
18754 */
18755 newsym.st_value |= 1;
18756 }
906e58ca 18757
0beaef2b
PB		 18758 src = &newsym;
18759 }
18760 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18761}
18762
b294bdf8
MM		 18763/* Add the PT_ARM_EXIDX program header. */
18764
18765static bfd_boolean
906e58ca 18766elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18767 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18768{
18769 struct elf_segment_map *m;
18770 asection *sec;
18771
18772 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18773 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18774 {
18775 /* If there is already a PT_ARM_EXIDX header, then we do not
18776 want to add another one. This situation arises when running
18777 "strip"; the input binary already has the header. */
12bd6957 18778 m = elf_seg_map (abfd);
b294bdf8
MM		 18779 while (m && m->p_type != PT_ARM_EXIDX)
18780 m = m->next;
18781 if (!m)
18782 {
21d799b5 18783 m = (struct elf_segment_map *)
99059e56 18784 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18785 if (m == NULL)
18786 return FALSE;
18787 m->p_type = PT_ARM_EXIDX;
18788 m->count = 1;
18789 m->sections[0] = sec;
18790
12bd6957
AM		 18791 m->next = elf_seg_map (abfd);
18792 elf_seg_map (abfd) = m;
b294bdf8
MM		 18793 }
18794 }
18795
18796 return TRUE;
18797}
18798
18799/* We may add a PT_ARM_EXIDX program header. */
18800
18801static int
a6b96beb
AM		 18802elf32_arm_additional_program_headers (bfd *abfd,
18803 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18804{
18805 asection *sec;
18806
18807 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18808 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18809 return 1;
18810 else
18811 return 0;
18812}
18813
34e77a92
RS		 18814/* Hook called by the linker routine which adds symbols from an object
18815 file. */
18816
18817static bfd_boolean
18818elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18819 Elf_Internal_Sym *sym, const char **namep,
18820 flagword *flagsp, asection **secp, bfd_vma *valp)
18821{
a43942db 18822 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18823 && (abfd->flags & DYNAMIC) == 0
18824 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18825 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18826
c792917c
NC		 18827 if (elf32_arm_hash_table (info) == NULL)
18828 return FALSE;
18829
34e77a92
RS		 18830 if (elf32_arm_hash_table (info)->vxworks_p
18831 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18832 flagsp, secp, valp))
18833 return FALSE;
18834
18835 return TRUE;
18836}
18837
0beaef2b 18838/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18839const struct elf_size_info elf32_arm_size_info =
18840{
0beaef2b
PB		 18841 sizeof (Elf32_External_Ehdr),
18842 sizeof (Elf32_External_Phdr),
18843 sizeof (Elf32_External_Shdr),
18844 sizeof (Elf32_External_Rel),
18845 sizeof (Elf32_External_Rela),
18846 sizeof (Elf32_External_Sym),
18847 sizeof (Elf32_External_Dyn),
18848 sizeof (Elf_External_Note),
18849 4,
18850 1,
18851 32, 2,
18852 ELFCLASS32, EV_CURRENT,
18853 bfd_elf32_write_out_phdrs,
18854 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18855 bfd_elf32_checksum_contents,
0beaef2b
PB		 18856 bfd_elf32_write_relocs,
18857 elf32_arm_swap_symbol_in,
18858 elf32_arm_swap_symbol_out,
18859 bfd_elf32_slurp_reloc_table,
18860 bfd_elf32_slurp_symbol_table,
18861 bfd_elf32_swap_dyn_in,
18862 bfd_elf32_swap_dyn_out,
18863 bfd_elf32_swap_reloc_in,
18864 bfd_elf32_swap_reloc_out,
18865 bfd_elf32_swap_reloca_in,
18866 bfd_elf32_swap_reloca_out
18867};
18868
685e70ae
VK		 18869static bfd_vma
18870read_code32 (const bfd *abfd, const bfd_byte *addr)
18871{
18872 /* V7 BE8 code is always little endian. */
18873 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18874 return bfd_getl32 (addr);
18875
18876 return bfd_get_32 (abfd, addr);
18877}
18878
18879static bfd_vma
18880read_code16 (const bfd *abfd, const bfd_byte *addr)
18881{
18882 /* V7 BE8 code is always little endian. */
18883 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18884 return bfd_getl16 (addr);
18885
18886 return bfd_get_16 (abfd, addr);
18887}
18888
6a631e86
YG		 18889/* Return size of plt0 entry starting at ADDR
18890 or (bfd_vma) -1 if size can not be determined. */
18891
18892static bfd_vma
18893elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
18894{
18895 bfd_vma first_word;
18896 bfd_vma plt0_size;
18897
685e70ae 18898 first_word = read_code32 (abfd, addr);
6a631e86
YG		 18899
18900 if (first_word == elf32_arm_plt0_entry[0])
18901 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
18902 else if (first_word == elf32_thumb2_plt0_entry[0])
18903 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
18904 else
18905 /* We don't yet handle this PLT format. */
18906 return (bfd_vma) -1;
18907
18908 return plt0_size;
18909}
18910
18911/* Return size of plt entry starting at offset OFFSET
18912 of plt section located at address START
18913 or (bfd_vma) -1 if size can not be determined. */
18914
18915static bfd_vma
18916elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
18917{
18918 bfd_vma first_insn;
18919 bfd_vma plt_size = 0;
18920 const bfd_byte *addr = start + offset;
18921
18922 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 18923 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 18924 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
18925
18926 /* Respect Thumb stub if necessary. */
685e70ae 18927 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 18928 {
18929 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
18930 }
18931
18932 /* Strip immediate from first add. */
685e70ae 18933 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 18934
18935#ifdef FOUR_WORD_PLT
18936 if (first_insn == elf32_arm_plt_entry[0])
18937 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
18938#else
18939 if (first_insn == elf32_arm_plt_entry_long[0])
18940 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
18941 else if (first_insn == elf32_arm_plt_entry_short[0])
18942 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
18943#endif
18944 else
18945 /* We don't yet handle this PLT format. */
18946 return (bfd_vma) -1;
18947
18948 return plt_size;
18949}
18950
18951/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
18952
18953static long
18954elf32_arm_get_synthetic_symtab (bfd *abfd,
18955 long symcount ATTRIBUTE_UNUSED,
18956 asymbol **syms ATTRIBUTE_UNUSED,
18957 long dynsymcount,
18958 asymbol **dynsyms,
18959 asymbol **ret)
18960{
18961 asection *relplt;
18962 asymbol *s;
18963 arelent *p;
18964 long count, i, n;
18965 size_t size;
18966 Elf_Internal_Shdr *hdr;
18967 char *names;
18968 asection *plt;
18969 bfd_vma offset;
18970 bfd_byte *data;
18971
18972 *ret = NULL;
18973
18974 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
18975 return 0;
18976
18977 if (dynsymcount <= 0)
18978 return 0;
18979
18980 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
18981 if (relplt == NULL)
18982 return 0;
18983
18984 hdr = &elf_section_data (relplt)->this_hdr;
18985 if (hdr->sh_link != elf_dynsymtab (abfd)
18986 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
18987 return 0;
18988
18989 plt = bfd_get_section_by_name (abfd, ".plt");
18990 if (plt == NULL)
18991 return 0;
18992
18993 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
18994 return -1;
18995
18996 data = plt->contents;
18997 if (data == NULL)
18998 {
18999 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19000 return -1;
19001 bfd_cache_section_contents((asection *) plt, data);
19002 }
19003
19004 count = relplt->size / hdr->sh_entsize;
19005 size = count * sizeof (asymbol);
19006 p = relplt->relocation;
19007 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19008 {
19009 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19010 if (p->addend != 0)
19011 size += sizeof ("+0x") - 1 + 8;
19012 }
19013
19014 s = *ret = (asymbol *) bfd_malloc (size);
19015 if (s == NULL)
19016 return -1;
19017
19018 offset = elf32_arm_plt0_size (abfd, data);
19019 if (offset == (bfd_vma) -1)
19020 return -1;
19021
19022 names = (char *) (s + count);
19023 p = relplt->relocation;
19024 n = 0;
19025 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19026 {
19027 size_t len;
19028
19029 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19030 if (plt_size == (bfd_vma) -1)
19031 break;
19032
19033 *s = **p->sym_ptr_ptr;
19034 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19035 we are defining a symbol, ensure one of them is set. */
19036 if ((s->flags & BSF_LOCAL) == 0)
19037 s->flags |= BSF_GLOBAL;
19038 s->flags |= BSF_SYNTHETIC;
19039 s->section = plt;
19040 s->value = offset;
19041 s->name = names;
19042 s->udata.p = NULL;
19043 len = strlen ((*p->sym_ptr_ptr)->name);
19044 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19045 names += len;
19046 if (p->addend != 0)
19047 {
19048 char buf[30], *a;
19049
19050 memcpy (names, "+0x", sizeof ("+0x") - 1);
19051 names += sizeof ("+0x") - 1;
19052 bfd_sprintf_vma (abfd, buf, p->addend);
19053 for (a = buf; *a == '0'; ++a)
19054 ;
19055 len = strlen (a);
19056 memcpy (names, a, len);
19057 names += len;
19058 }
19059 memcpy (names, "@plt", sizeof ("@plt"));
19060 names += sizeof ("@plt");
19061 ++s, ++n;
19062 offset += plt_size;
19063 }
19064
19065 return n;
19066}
19067
ac4c9b04
MG		 19068static bfd_boolean
19069elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19070{
f0728ee3
AV		 19071 if (hdr->sh_flags & SHF_ARM_PURECODE)
19072 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19073 return TRUE;
19074}
19075
19076static flagword
19077elf32_arm_lookup_section_flags (char *flag_name)
19078{
f0728ee3
AV		 19079 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19080 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19081
19082 return SEC_NO_FLAGS;
19083}
19084
491d01d3
YU		 19085static unsigned int
19086elf32_arm_count_additional_relocs (asection *sec)
19087{
19088 struct _arm_elf_section_data *arm_data;
19089 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19090
6342be70 19091 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19092}
19093
5522f910 19094/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19095 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19096 FALSE otherwise. ISECTION is the best guess matching section from the
19097 input bfd IBFD, but it might be NULL. */
19098
19099static bfd_boolean
19100elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19101 bfd *obfd ATTRIBUTE_UNUSED,
19102 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19103 Elf_Internal_Shdr *osection)
19104{
19105 switch (osection->sh_type)
19106 {
19107 case SHT_ARM_EXIDX:
19108 {
19109 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19110 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19111 unsigned i = 0;
19112
19113 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19114 osection->sh_info = 0;
19115
19116 /* The sh_link field must be set to the text section associated with
19117 this index section. Unfortunately the ARM EHABI does not specify
19118 exactly how to determine this association. Our caller does try
19119 to match up OSECTION with its corresponding input section however
19120 so that is a good first guess. */
19121 if (isection != NULL
19122 && osection->bfd_section != NULL
19123 && isection->bfd_section != NULL
19124 && isection->bfd_section->output_section != NULL
19125 && isection->bfd_section->output_section == osection->bfd_section
19126 && iheaders != NULL
19127 && isection->sh_link > 0
19128 && isection->sh_link < elf_numsections (ibfd)
19129 && iheaders[isection->sh_link]->bfd_section != NULL
19130 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19131 )
19132 {
19133 for (i = elf_numsections (obfd); i-- > 0;)
19134 if (oheaders[i]->bfd_section
19135 == iheaders[isection->sh_link]->bfd_section->output_section)
19136 break;
19137 }
9eaff861 19138
5522f910
NC		 19139 if (i == 0)
19140 {
19141 /* Failing that we have to find a matching section ourselves. If
19142 we had the output section name available we could compare that
19143 with input section names. Unfortunately we don't. So instead
19144 we use a simple heuristic and look for the nearest executable
19145 section before this one. */
19146 for (i = elf_numsections (obfd); i-- > 0;)
19147 if (oheaders[i] == osection)
19148 break;
19149 if (i == 0)
19150 break;
19151
19152 while (i-- > 0)
19153 if (oheaders[i]->sh_type == SHT_PROGBITS
19154 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19155 == (SHF_ALLOC | SHF_EXECINSTR))
19156 break;
19157 }
19158
19159 if (i)
19160 {
19161 osection->sh_link = i;
19162 /* If the text section was part of a group
19163 then the index section should be too. */
19164 if (oheaders[i]->sh_flags & SHF_GROUP)
19165 osection->sh_flags |= SHF_GROUP;
19166 return TRUE;
19167 }
19168 }
19169 break;
19170
19171 case SHT_ARM_PREEMPTMAP:
19172 osection->sh_flags = SHF_ALLOC;
19173 break;
19174
19175 case SHT_ARM_ATTRIBUTES:
19176 case SHT_ARM_DEBUGOVERLAY:
19177 case SHT_ARM_OVERLAYSECTION:
19178 default:
19179 break;
19180 }
19181
19182 return FALSE;
19183}
19184
d691934d
NC		 19185/* Returns TRUE if NAME is an ARM mapping symbol.
19186 Traditionally the symbols $a, $d and $t have been used.
19187 The ARM ELF standard also defines $x (for A64 code). It also allows a
19188 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19189 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19190 not support them here. $t.x indicates the start of ThumbEE instructions. */
19191
19192static bfd_boolean
19193is_arm_mapping_symbol (const char * name)
19194{
19195 return name != NULL /* Paranoia. */
19196 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19197 the mapping symbols could have acquired a prefix.
19198 We do not support this here, since such symbols no
19199 longer conform to the ARM ELF ABI. */
19200 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19201 && (name[2] == 0 || name[2] == '.');
19202 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19203 any characters that follow the period are legal characters for the body
19204 of a symbol's name. For now we just assume that this is the case. */
19205}
19206
fca2a38f
NC		 19207/* Make sure that mapping symbols in object files are not removed via the
19208 "strip --strip-unneeded" tool. These symbols are needed in order to
19209 correctly generate interworking veneers, and for byte swapping code
19210 regions. Once an object file has been linked, it is safe to remove the
19211 symbols as they will no longer be needed. */
19212
19213static void
19214elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19215{
19216 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19217 && sym->section != bfd_abs_section_ptr
d691934d 19218 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19219 sym->flags |= BSF_KEEP;
19220}
19221
5522f910
NC		 19222#undef elf_backend_copy_special_section_fields
19223#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19224
252b5132 19225#define ELF_ARCH bfd_arch_arm
ae95ffa6 19226#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19227#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19228#ifdef __QNXTARGET__
19229#define ELF_MAXPAGESIZE 0x1000
19230#else
7572ca89 19231#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19232#endif
b1342370 19233#define ELF_MINPAGESIZE 0x1000
24718e3b 19234#define ELF_COMMONPAGESIZE 0x1000
252b5132 19235
07d6d2b8 19236#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 19237
99e4ae17
AJ		 19238#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19239#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19240#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19241#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 19242#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19243#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19244#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 19245#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
19246#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19247#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19248#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19249#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 19250#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 19251
07d6d2b8
AM		 19252#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19253#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19254#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 19255#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19256#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19257#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19258#define elf_backend_write_section elf32_arm_write_section
252b5132 19259#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 19260#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19261#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19262#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19263#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19264#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19265#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19266#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19267#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19268#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 19269#define elf_backend_fake_sections elf32_arm_fake_sections
19270#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
19271#define elf_backend_final_write_processing elf32_arm_final_write_processing
19272#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19273#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19274#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 19275#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19276#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19277#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 19278#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19279#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19280#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19281#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19282
19283#define elf_backend_can_refcount 1
19284#define elf_backend_can_gc_sections 1
19285#define elf_backend_plt_readonly 1
19286#define elf_backend_want_got_plt 1
19287#define elf_backend_want_plt_sym 0
5474d94f 19288#define elf_backend_want_dynrelro 1
906e58ca
NC		 19289#define elf_backend_may_use_rel_p 1
19290#define elf_backend_may_use_rela_p 0
4e7fd91e 19291#define elf_backend_default_use_rela_p 0
64f52338 19292#define elf_backend_dtrel_excludes_plt 1
252b5132 19293
04f7c78d 19294#define elf_backend_got_header_size 12
b68a20d6 19295#define elf_backend_extern_protected_data 1
04f7c78d 19296
07d6d2b8 19297#undef elf_backend_obj_attrs_vendor
906e58ca 19298#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 19299#undef elf_backend_obj_attrs_section
906e58ca 19300#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 19301#undef elf_backend_obj_attrs_arg_type
906e58ca 19302#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 19303#undef elf_backend_obj_attrs_section_type
104d59d1 19304#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 19305#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 19306#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19307
07d6d2b8 19308#undef elf_backend_section_flags
ac4c9b04 19309#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 19310#undef elf_backend_lookup_section_flags_hook
19311#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 19312
a2f63b2e
MR		 19313#define elf_backend_linux_prpsinfo32_ugid16 TRUE
19314
252b5132 19315#include "elf32-target.h"
7f266840 19316
b38cadfb
NC		 19317/* Native Client targets. */
19318
19319#undef TARGET_LITTLE_SYM
6d00b590 19320#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19321#undef TARGET_LITTLE_NAME
19322#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19323#undef TARGET_BIG_SYM
6d00b590 19324#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19325#undef TARGET_BIG_NAME
19326#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19327
19328/* Like elf32_arm_link_hash_table_create -- but overrides
19329 appropriately for NaCl. */
19330
19331static struct bfd_link_hash_table *
19332elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19333{
19334 struct bfd_link_hash_table *ret;
19335
19336 ret = elf32_arm_link_hash_table_create (abfd);
19337 if (ret)
19338 {
19339 struct elf32_arm_link_hash_table *htab
19340 = (struct elf32_arm_link_hash_table *) ret;
19341
19342 htab->nacl_p = 1;
19343
19344 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19345 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19346 }
19347 return ret;
19348}
19349
19350/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19351 really need to use elf32_arm_modify_segment_map. But we do it
19352 anyway just to reduce gratuitous differences with the stock ARM backend. */
19353
19354static bfd_boolean
19355elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19356{
19357 return (elf32_arm_modify_segment_map (abfd, info)
19358 && nacl_modify_segment_map (abfd, info));
19359}
19360
887badb3
RM		 19361static void
19362elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19363{
19364 elf32_arm_final_write_processing (abfd, linker);
19365 nacl_final_write_processing (abfd, linker);
19366}
19367
6a631e86
YG		 19368static bfd_vma
19369elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19370 const arelent *rel ATTRIBUTE_UNUSED)
19371{
19372 return plt->vma
19373 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19374 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19375}
887badb3 19376
b38cadfb 19377#undef elf32_bed
6a631e86 19378#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19379#undef bfd_elf32_bfd_link_hash_table_create
19380#define bfd_elf32_bfd_link_hash_table_create \
19381 elf32_arm_nacl_link_hash_table_create
19382#undef elf_backend_plt_alignment
6a631e86 19383#define elf_backend_plt_alignment 4
b38cadfb
NC		 19384#undef elf_backend_modify_segment_map
19385#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19386#undef elf_backend_modify_program_headers
19387#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19388#undef elf_backend_final_write_processing
19389#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19390#undef bfd_elf32_get_synthetic_symtab
19391#undef elf_backend_plt_sym_val
19392#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19393#undef elf_backend_copy_special_section_fields
b38cadfb 19394
887badb3
RM		 19395#undef ELF_MINPAGESIZE
19396#undef ELF_COMMONPAGESIZE
19397
b38cadfb
NC		 19398
19399#include "elf32-target.h"
19400
19401/* Reset to defaults. */
19402#undef elf_backend_plt_alignment
19403#undef elf_backend_modify_segment_map
19404#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19405#undef elf_backend_modify_program_headers
887badb3
RM		 19406#undef elf_backend_final_write_processing
19407#define elf_backend_final_write_processing elf32_arm_final_write_processing
19408#undef ELF_MINPAGESIZE
19409#define ELF_MINPAGESIZE 0x1000
19410#undef ELF_COMMONPAGESIZE
19411#define ELF_COMMONPAGESIZE 0x1000
19412
b38cadfb 19413
906e58ca 19414/* VxWorks Targets. */
4e7fd91e 19415
07d6d2b8
AM		 19416#undef TARGET_LITTLE_SYM
19417#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
19418#undef TARGET_LITTLE_NAME
19419#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
19420#undef TARGET_BIG_SYM
19421#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
19422#undef TARGET_BIG_NAME
19423#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 19424
19425/* Like elf32_arm_link_hash_table_create -- but overrides
19426 appropriately for VxWorks. */
906e58ca 19427
4e7fd91e
PB		 19428static struct bfd_link_hash_table *
19429elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19430{
19431 struct bfd_link_hash_table *ret;
19432
19433 ret = elf32_arm_link_hash_table_create (abfd);
19434 if (ret)
19435 {
19436 struct elf32_arm_link_hash_table *htab
00a97672 19437 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19438 htab->use_rel = 0;
00a97672 19439 htab->vxworks_p = 1;
4e7fd91e
PB		 19440 }
19441 return ret;
906e58ca 19442}
4e7fd91e 19443
00a97672
RS		 19444static void
19445elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19446{
19447 elf32_arm_final_write_processing (abfd, linker);
19448 elf_vxworks_final_write_processing (abfd, linker);
19449}
19450
906e58ca 19451#undef elf32_bed
4e7fd91e
PB		 19452#define elf32_bed elf32_arm_vxworks_bed
19453
906e58ca
NC		 19454#undef bfd_elf32_bfd_link_hash_table_create
19455#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19456#undef elf_backend_final_write_processing
19457#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19458#undef elf_backend_emit_relocs
9eaff861 19459#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19460
906e58ca 19461#undef elf_backend_may_use_rel_p
00a97672 19462#define elf_backend_may_use_rel_p 0
906e58ca 19463#undef elf_backend_may_use_rela_p
00a97672 19464#define elf_backend_may_use_rela_p 1
906e58ca 19465#undef elf_backend_default_use_rela_p
00a97672 19466#define elf_backend_default_use_rela_p 1
906e58ca 19467#undef elf_backend_want_plt_sym
00a97672 19468#define elf_backend_want_plt_sym 1
906e58ca 19469#undef ELF_MAXPAGESIZE
00a97672 19470#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19471
19472#include "elf32-target.h"
19473
19474
21d799b5
NC		 19475/* Merge backend specific data from an object file to the output
19476 object file when linking. */
19477
19478static bfd_boolean
50e03d47 19479elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 19480{
50e03d47 19481 bfd *obfd = info->output_bfd;
21d799b5
NC		 19482 flagword out_flags;
19483 flagword in_flags;
19484 bfd_boolean flags_compatible = TRUE;
19485 asection *sec;
19486
cc643b88 19487 /* Check if we have the same endianness. */
50e03d47 19488 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 19489 return FALSE;
19490
19491 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19492 return TRUE;
19493
50e03d47 19494 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 19495 return FALSE;
19496
19497 /* The input BFD must have had its flags initialised. */
19498 /* The following seems bogus to me -- The flags are initialized in
19499 the assembler but I don't think an elf_flags_init field is
19500 written into the object. */
19501 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19502
19503 in_flags = elf_elfheader (ibfd)->e_flags;
19504 out_flags = elf_elfheader (obfd)->e_flags;
19505
19506 /* In theory there is no reason why we couldn't handle this. However
19507 in practice it isn't even close to working and there is no real
19508 reason to want it. */
19509 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19510 && !(ibfd->flags & DYNAMIC)
19511 && (in_flags & EF_ARM_BE8))
19512 {
871b3ab2 19513 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 19514 ibfd);
19515 return FALSE;
19516 }
19517
19518 if (!elf_flags_init (obfd))
19519 {
19520 /* If the input is the default architecture and had the default
19521 flags then do not bother setting the flags for the output
19522 architecture, instead allow future merges to do this. If no
19523 future merges ever set these flags then they will retain their
99059e56
RM		 19524 uninitialised values, which surprise surprise, correspond
19525 to the default values. */
21d799b5
NC		 19526 if (bfd_get_arch_info (ibfd)->the_default
19527 && elf_elfheader (ibfd)->e_flags == 0)
19528 return TRUE;
19529
19530 elf_flags_init (obfd) = TRUE;
19531 elf_elfheader (obfd)->e_flags = in_flags;
19532
19533 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19534 && bfd_get_arch_info (obfd)->the_default)
19535 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19536
19537 return TRUE;
19538 }
19539
19540 /* Determine what should happen if the input ARM architecture
19541 does not match the output ARM architecture. */
19542 if (! bfd_arm_merge_machines (ibfd, obfd))
19543 return FALSE;
19544
19545 /* Identical flags must be compatible. */
19546 if (in_flags == out_flags)
19547 return TRUE;
19548
19549 /* Check to see if the input BFD actually contains any sections. If
19550 not, its flags may not have been initialised either, but it
19551 cannot actually cause any incompatiblity. Do not short-circuit
19552 dynamic objects; their section list may be emptied by
19553 elf_link_add_object_symbols.
19554
19555 Also check to see if there are no code sections in the input.
19556 In this case there is no need to check for code specific flags.
19557 XXX - do we need to worry about floating-point format compatability
19558 in data sections ? */
19559 if (!(ibfd->flags & DYNAMIC))
19560 {
19561 bfd_boolean null_input_bfd = TRUE;
19562 bfd_boolean only_data_sections = TRUE;
19563
19564 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19565 {
19566 /* Ignore synthetic glue sections. */
19567 if (strcmp (sec->name, ".glue_7")
19568 && strcmp (sec->name, ".glue_7t"))
19569 {
19570 if ((bfd_get_section_flags (ibfd, sec)
19571 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19572 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19573 only_data_sections = FALSE;
21d799b5
NC		 19574
19575 null_input_bfd = FALSE;
19576 break;
19577 }
19578 }
19579
19580 if (null_input_bfd || only_data_sections)
19581 return TRUE;
19582 }
19583
19584 /* Complain about various flag mismatches. */
19585 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19586 EF_ARM_EABI_VERSION (out_flags)))
19587 {
19588 _bfd_error_handler
90b6238f 19589 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 19590 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
19591 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 19592 return FALSE;
19593 }
19594
19595 /* Not sure what needs to be checked for EABI versions >= 1. */
19596 /* VxWorks libraries do not use these flags. */
19597 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19598 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19599 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19600 {
19601 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19602 {
19603 _bfd_error_handler
871b3ab2 19604 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 19605 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
19606 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 19607 flags_compatible = FALSE;
19608 }
19609
19610 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19611 {
19612 if (in_flags & EF_ARM_APCS_FLOAT)
19613 _bfd_error_handler
871b3ab2 19614 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 19615 ibfd, obfd);
19616 else
19617 _bfd_error_handler
871b3ab2 19618 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 19619 ibfd, obfd);
19620
19621 flags_compatible = FALSE;
19622 }
19623
19624 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19625 {
19626 if (in_flags & EF_ARM_VFP_FLOAT)
19627 _bfd_error_handler
90b6238f
AM		 19628 (_("error: %pB uses %s instructions, whereas %pB does not"),
19629 ibfd, "VFP", obfd);
21d799b5
NC		 19630 else
19631 _bfd_error_handler
90b6238f
AM		 19632 (_("error: %pB uses %s instructions, whereas %pB does not"),
19633 ibfd, "FPA", obfd);
21d799b5
NC		 19634
19635 flags_compatible = FALSE;
19636 }
19637
19638 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19639 {
19640 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19641 _bfd_error_handler
90b6238f
AM		 19642 (_("error: %pB uses %s instructions, whereas %pB does not"),
19643 ibfd, "Maverick", obfd);
21d799b5
NC		 19644 else
19645 _bfd_error_handler
90b6238f
AM		 19646 (_("error: %pB does not use %s instructions, whereas %pB does"),
19647 ibfd, "Maverick", obfd);
21d799b5
NC		 19648
19649 flags_compatible = FALSE;
19650 }
19651
19652#ifdef EF_ARM_SOFT_FLOAT
19653 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19654 {
19655 /* We can allow interworking between code that is VFP format
19656 layout, and uses either soft float or integer regs for
19657 passing floating point arguments and results. We already
19658 know that the APCS_FLOAT flags match; similarly for VFP
19659 flags. */
19660 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19661 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19662 {
19663 if (in_flags & EF_ARM_SOFT_FLOAT)
19664 _bfd_error_handler
871b3ab2 19665 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 19666 ibfd, obfd);
19667 else
19668 _bfd_error_handler
871b3ab2 19669 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 19670 ibfd, obfd);
19671
19672 flags_compatible = FALSE;
19673 }
19674 }
19675#endif
19676
19677 /* Interworking mismatch is only a warning. */
19678 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19679 {
19680 if (in_flags & EF_ARM_INTERWORK)
19681 {
19682 _bfd_error_handler
90b6238f 19683 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 19684 ibfd, obfd);
19685 }
19686 else
19687 {
19688 _bfd_error_handler
90b6238f 19689 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 19690 ibfd, obfd);
19691 }
19692 }
19693 }
19694
19695 return flags_compatible;
19696}
19697
19698
906e58ca 19699/* Symbian OS Targets. */
7f266840 19700
07d6d2b8
AM		 19701#undef TARGET_LITTLE_SYM
19702#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
19703#undef TARGET_LITTLE_NAME
19704#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
19705#undef TARGET_BIG_SYM
19706#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
19707#undef TARGET_BIG_NAME
19708#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 19709
19710/* Like elf32_arm_link_hash_table_create -- but overrides
19711 appropriately for Symbian OS. */
906e58ca 19712
7f266840
DJ		 19713static struct bfd_link_hash_table *
19714elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19715{
19716 struct bfd_link_hash_table *ret;
19717
19718 ret = elf32_arm_link_hash_table_create (abfd);
19719 if (ret)
19720 {
19721 struct elf32_arm_link_hash_table *htab
19722 = (struct elf32_arm_link_hash_table *)ret;
19723 /* There is no PLT header for Symbian OS. */
19724 htab->plt_header_size = 0;
95720a86
DJ		 19725 /* The PLT entries are each one instruction and one word. */
19726 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19727 htab->symbian_p = 1;
33bfe774
JB		 19728 /* Symbian uses armv5t or above, so use_blx is always true. */
19729 htab->use_blx = 1;
67687978 19730 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19731 }
19732 return ret;
906e58ca 19733}
7f266840 19734
b35d266b 19735static const struct bfd_elf_special_section
551b43fd 19736elf32_arm_symbian_special_sections[] =
7f266840 19737{
5cd3778d
MM		 19738 /* In a BPABI executable, the dynamic linking sections do not go in
19739 the loadable read-only segment. The post-linker may wish to
19740 refer to these sections, but they are not part of the final
19741 program image. */
07d6d2b8
AM		 19742 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19743 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19744 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19745 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19746 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19747 /* These sections do not need to be writable as the SymbianOS
19748 postlinker will arrange things so that no dynamic relocation is
19749 required. */
07d6d2b8
AM		 19750 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19751 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 19752 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 19753 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19754};
19755
c3c76620 19756static void
906e58ca 19757elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19758 struct bfd_link_info *link_info)
c3c76620
MM		 19759{
19760 /* BPABI objects are never loaded directly by an OS kernel; they are
19761 processed by a postlinker first, into an OS-specific format. If
19762 the D_PAGED bit is set on the file, BFD will align segments on
19763 page boundaries, so that an OS can directly map the file. With
19764 BPABI objects, that just results in wasted space. In addition,
19765 because we clear the D_PAGED bit, map_sections_to_segments will
19766 recognize that the program headers should not be mapped into any
19767 loadable segment. */
19768 abfd->flags &= ~D_PAGED;
906e58ca 19769 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19770}
7f266840
DJ		 19771
19772static bfd_boolean
906e58ca 19773elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19774 struct bfd_link_info *info)
7f266840
DJ		 19775{
19776 struct elf_segment_map *m;
19777 asection *dynsec;
19778
7f266840
DJ		 19779 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19780 segment. However, because the .dynamic section is not marked
19781 with SEC_LOAD, the generic ELF code will not create such a
19782 segment. */
19783 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19784 if (dynsec)
19785 {
12bd6957 19786 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19787 if (m->p_type == PT_DYNAMIC)
19788 break;
19789
19790 if (m == NULL)
19791 {
19792 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19793 m->next = elf_seg_map (abfd);
19794 elf_seg_map (abfd) = m;
8ded5a0f 19795 }
7f266840
DJ		 19796 }
19797
b294bdf8
MM		 19798 /* Also call the generic arm routine. */
19799 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19800}
19801
95720a86
DJ		 19802/* Return address for Ith PLT stub in section PLT, for relocation REL
19803 or (bfd_vma) -1 if it should not be included. */
19804
19805static bfd_vma
19806elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19807 const arelent *rel ATTRIBUTE_UNUSED)
19808{
19809 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19810}
19811
8029a119 19812#undef elf32_bed
7f266840
DJ		 19813#define elf32_bed elf32_arm_symbian_bed
19814
19815/* The dynamic sections are not allocated on SymbianOS; the postlinker
19816 will process them and then discard them. */
906e58ca 19817#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19818#define ELF_DYNAMIC_SEC_FLAGS \
19819 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19820
9eaff861 19821#undef elf_backend_emit_relocs
c3c76620 19822
906e58ca
NC		 19823#undef bfd_elf32_bfd_link_hash_table_create
19824#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19825#undef elf_backend_special_sections
07d6d2b8 19826#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 19827#undef elf_backend_begin_write_processing
19828#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19829#undef elf_backend_final_write_processing
19830#define elf_backend_final_write_processing elf32_arm_final_write_processing
19831
19832#undef elf_backend_modify_segment_map
7f266840
DJ		 19833#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19834
19835/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19836#undef elf_backend_got_header_size
7f266840
DJ		 19837#define elf_backend_got_header_size 0
19838
19839/* Similarly, there is no .got.plt section. */
906e58ca 19840#undef elf_backend_want_got_plt
7f266840
DJ		 19841#define elf_backend_want_got_plt 0
19842
906e58ca 19843#undef elf_backend_plt_sym_val
95720a86
DJ		 19844#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19845
906e58ca 19846#undef elf_backend_may_use_rel_p
00a97672 19847#define elf_backend_may_use_rel_p 1
906e58ca 19848#undef elf_backend_may_use_rela_p
00a97672 19849#define elf_backend_may_use_rela_p 0
906e58ca 19850#undef elf_backend_default_use_rela_p
00a97672 19851#define elf_backend_default_use_rela_p 0
906e58ca 19852#undef elf_backend_want_plt_sym
00a97672 19853#define elf_backend_want_plt_sym 0
64f52338
AM		 19854#undef elf_backend_dtrel_excludes_plt
19855#define elf_backend_dtrel_excludes_plt 0
906e58ca 19856#undef ELF_MAXPAGESIZE
00a97672 19857#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19858
7f266840 19859#include "elf32-target.h"
GDB Binutils - Deliverables
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