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gas/doc/arc: Add nps400 references into the documentation
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
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252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
252b5132
RH		 2141/* The name of the dynamic interpreter. This is put in the .interp
2142 section. */
2143#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2144
0855e32b 2145static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2146{
2147 0xe08e0000, /* add r0, lr, r0 */
2148 0xe5901004, /* ldr r1, [r0,#4] */
2149 0xe12fff11, /* bx r1 */
2150};
0855e32b
NS		 2151
2152static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2153{
2154 0xe52d2004, /* push {r2} */
2155 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2156 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2157 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2158 0xe081100f, /* 2: add r1, pc */
2159 0xe12fff12, /* bx r2 */
2160 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2161 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2162 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2163};
0855e32b 2164
5e681ec4
PB		 2165#ifdef FOUR_WORD_PLT
2166
252b5132
RH		 2167/* The first entry in a procedure linkage table looks like
2168 this. It is set up so that any shared library function that is
59f2c4e7 2169 called before the relocation has been set up calls the dynamic
9b485d32 2170 linker first. */
e5a52504 2171static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2172{
2173 0xe52de004, /* str lr, [sp, #-4]! */
2174 0xe59fe010, /* ldr lr, [pc, #16] */
2175 0xe08fe00e, /* add lr, pc, lr */
2176 0xe5bef008, /* ldr pc, [lr, #8]! */
2177};
5e681ec4
PB		 2178
2179/* Subsequent entries in a procedure linkage table look like
2180 this. */
e5a52504 2181static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2182{
2183 0xe28fc600, /* add ip, pc, #NN */
2184 0xe28cca00, /* add ip, ip, #NN */
2185 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2186 0x00000000, /* unused */
2187};
5e681ec4 2188
eed94f8f 2189#else /* not FOUR_WORD_PLT */
5e681ec4 2190
5e681ec4
PB		 2191/* The first entry in a procedure linkage table looks like
2192 this. It is set up so that any shared library function that is
2193 called before the relocation has been set up calls the dynamic
2194 linker first. */
e5a52504 2195static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2196{
2197 0xe52de004, /* str lr, [sp, #-4]! */
2198 0xe59fe004, /* ldr lr, [pc, #4] */
2199 0xe08fe00e, /* add lr, pc, lr */
2200 0xe5bef008, /* ldr pc, [lr, #8]! */
2201 0x00000000, /* &GOT[0] - . */
2202};
252b5132 2203
1db37fe6
YG		 2204/* By default subsequent entries in a procedure linkage table look like
2205 this. Offsets that don't fit into 28 bits will cause link error. */
2206static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2207{
2208 0xe28fc600, /* add ip, pc, #0xNN00000 */
2209 0xe28cca00, /* add ip, ip, #0xNN000 */
2210 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2211};
5e681ec4 2212
1db37fe6
YG		 2213/* When explicitly asked, we'll use this "long" entry format
2214 which can cope with arbitrary displacements. */
2215static const bfd_vma elf32_arm_plt_entry_long [] =
2216{
2217 0xe28fc200, /* add ip, pc, #0xN0000000 */
2218 0xe28cc600, /* add ip, ip, #0xNN00000 */
2219 0xe28cca00, /* add ip, ip, #0xNN000 */
2220 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2221};
2222
2223static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2224
eed94f8f
NC		 2225#endif /* not FOUR_WORD_PLT */
2226
2227/* The first entry in a procedure linkage table looks like this.
2228 It is set up so that any shared library function that is called before the
2229 relocation has been set up calls the dynamic linker first. */
2230static const bfd_vma elf32_thumb2_plt0_entry [] =
2231{
2232 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2233 an instruction maybe encoded to one or two array elements. */
2234 0xf8dfb500, /* push {lr} */
2235 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2236 /* add lr, pc */
eed94f8f
NC		 2237 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2238 0x00000000, /* &GOT[0] - . */
2239};
2240
2241/* Subsequent entries in a procedure linkage table for thumb only target
2242 look like this. */
2243static const bfd_vma elf32_thumb2_plt_entry [] =
2244{
2245 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2246 an instruction maybe encoded to one or two array elements. */
2247 0x0c00f240, /* movw ip, #0xNNNN */
2248 0x0c00f2c0, /* movt ip, #0xNNNN */
2249 0xf8dc44fc, /* add ip, pc */
2250 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2251 /* nop */
eed94f8f 2252};
252b5132 2253
00a97672
RS		 2254/* The format of the first entry in the procedure linkage table
2255 for a VxWorks executable. */
2256static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2257{
2258 0xe52dc008, /* str ip,[sp,#-8]! */
2259 0xe59fc000, /* ldr ip,[pc] */
2260 0xe59cf008, /* ldr pc,[ip,#8] */
2261 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2262};
00a97672
RS		 2263
2264/* The format of subsequent entries in a VxWorks executable. */
2265static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2266{
2267 0xe59fc000, /* ldr ip,[pc] */
2268 0xe59cf000, /* ldr pc,[ip] */
2269 0x00000000, /* .long @got */
2270 0xe59fc000, /* ldr ip,[pc] */
2271 0xea000000, /* b _PLT */
2272 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2273};
00a97672
RS		 2274
2275/* The format of entries in a VxWorks shared library. */
2276static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2277{
2278 0xe59fc000, /* ldr ip,[pc] */
2279 0xe79cf009, /* ldr pc,[ip,r9] */
2280 0x00000000, /* .long @got */
2281 0xe59fc000, /* ldr ip,[pc] */
2282 0xe599f008, /* ldr pc,[r9,#8] */
2283 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2284};
00a97672 2285
b7693d02
DJ		 2286/* An initial stub used if the PLT entry is referenced from Thumb code. */
2287#define PLT_THUMB_STUB_SIZE 4
2288static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2289{
2290 0x4778, /* bx pc */
2291 0x46c0 /* nop */
2292};
b7693d02 2293
e5a52504
MM		 2294/* The entries in a PLT when using a DLL-based target with multiple
2295 address spaces. */
906e58ca 2296static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2297{
2298 0xe51ff004, /* ldr pc, [pc, #-4] */
2299 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2300};
2301
2302/* The first entry in a procedure linkage table looks like
2303 this. It is set up so that any shared library function that is
2304 called before the relocation has been set up calls the dynamic
2305 linker first. */
2306static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2307{
2308 /* First bundle: */
2309 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2310 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2311 0xe08cc00f, /* add ip, ip, pc */
2312 0xe52dc008, /* str ip, [sp, #-8]! */
2313 /* Second bundle: */
edccdf7c
RM		 2314 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2315 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2316 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2317 0xe12fff1c, /* bx ip */
b38cadfb 2318 /* Third bundle: */
edccdf7c
RM		 2319 0xe320f000, /* nop */
2320 0xe320f000, /* nop */
2321 0xe320f000, /* nop */
b38cadfb
NC		 2322 /* .Lplt_tail: */
2323 0xe50dc004, /* str ip, [sp, #-4] */
2324 /* Fourth bundle: */
edccdf7c
RM		 2325 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2326 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2327 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2328 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2329};
2330#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2331
2332/* Subsequent entries in a procedure linkage table look like this. */
2333static const bfd_vma elf32_arm_nacl_plt_entry [] =
2334{
2335 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2336 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2337 0xe08cc00f, /* add ip, ip, pc */
2338 0xea000000, /* b .Lplt_tail */
2339};
e5a52504 2340
906e58ca
NC		 2341#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2342#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2343#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2344#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2345#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2346#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2347#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2348#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2349
461a49ca 2350enum stub_insn_type
b38cadfb
NC		 2351{
2352 THUMB16_TYPE = 1,
2353 THUMB32_TYPE,
2354 ARM_TYPE,
2355 DATA_TYPE
2356};
461a49ca 2357
48229727
JB		 2358#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2359/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2360 is inserted in arm_build_one_stub(). */
2361#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2362#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2363#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2364#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2365#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2366#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2367
2368typedef struct
2369{
b38cadfb
NC		 2370 bfd_vma data;
2371 enum stub_insn_type type;
2372 unsigned int r_type;
2373 int reloc_addend;
461a49ca
DJ		 2374} insn_sequence;
2375
fea2b4d6
CL		 2376/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2377 to reach the stub if necessary. */
461a49ca 2378static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2379{
2380 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2381 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2382};
906e58ca 2383
fea2b4d6
CL		 2384/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2385 available. */
461a49ca 2386static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2387{
2388 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2389 ARM_INSN (0xe12fff1c), /* bx ip */
2390 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2391};
906e58ca 2392
d3626fb0 2393/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2394static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2395{
2396 THUMB16_INSN (0xb401), /* push {r0} */
2397 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2398 THUMB16_INSN (0x4684), /* mov ip, r0 */
2399 THUMB16_INSN (0xbc01), /* pop {r0} */
2400 THUMB16_INSN (0x4760), /* bx ip */
2401 THUMB16_INSN (0xbf00), /* nop */
2402 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2403};
906e58ca 2404
d3626fb0
CL		 2405/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2406 allowed. */
2407static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2408{
2409 THUMB16_INSN (0x4778), /* bx pc */
2410 THUMB16_INSN (0x46c0), /* nop */
2411 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2412 ARM_INSN (0xe12fff1c), /* bx ip */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2414};
d3626fb0 2415
fea2b4d6
CL		 2416/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2417 available. */
461a49ca 2418static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2419{
2420 THUMB16_INSN (0x4778), /* bx pc */
2421 THUMB16_INSN (0x46c0), /* nop */
2422 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2423 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2424};
906e58ca 2425
fea2b4d6
CL		 2426/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2427 one, when the destination is close enough. */
461a49ca 2428static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2429{
2430 THUMB16_INSN (0x4778), /* bx pc */
2431 THUMB16_INSN (0x46c0), /* nop */
2432 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2433};
c820be07 2434
cf3eccff 2435/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2436 blx to reach the stub if necessary. */
cf3eccff 2437static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2438{
2439 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2440 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2441 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2442};
906e58ca 2443
cf3eccff
DJ		 2444/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2445 blx to reach the stub if necessary. We can not add into pc;
2446 it is not guaranteed to mode switch (different in ARMv6 and
2447 ARMv7). */
2448static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2449{
2450 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2451 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2452 ARM_INSN (0xe12fff1c), /* bx ip */
2453 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2454};
cf3eccff 2455
ebe24dd4
CL		 2456/* V4T ARM -> ARM long branch stub, PIC. */
2457static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2460 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2461 ARM_INSN (0xe12fff1c), /* bx ip */
2462 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2463};
ebe24dd4
CL		 2464
2465/* V4T Thumb -> ARM long branch stub, PIC. */
2466static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2467{
2468 THUMB16_INSN (0x4778), /* bx pc */
2469 THUMB16_INSN (0x46c0), /* nop */
2470 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2471 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2472 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2473};
ebe24dd4 2474
d3626fb0
CL		 2475/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2476 architectures. */
ebe24dd4 2477static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2478{
2479 THUMB16_INSN (0xb401), /* push {r0} */
2480 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2481 THUMB16_INSN (0x46fc), /* mov ip, pc */
2482 THUMB16_INSN (0x4484), /* add ip, r0 */
2483 THUMB16_INSN (0xbc01), /* pop {r0} */
2484 THUMB16_INSN (0x4760), /* bx ip */
2485 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2486};
ebe24dd4 2487
d3626fb0
CL		 2488/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2489 allowed. */
2490static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2491{
2492 THUMB16_INSN (0x4778), /* bx pc */
2493 THUMB16_INSN (0x46c0), /* nop */
2494 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2495 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2496 ARM_INSN (0xe12fff1c), /* bx ip */
2497 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2498};
d3626fb0 2499
0855e32b
NS		 2500/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2501 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2502static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2503{
b38cadfb
NC		 2504 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2505 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2506 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2507};
2508
2509/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2510 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2511static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2512{
b38cadfb
NC		 2513 THUMB16_INSN (0x4778), /* bx pc */
2514 THUMB16_INSN (0x46c0), /* nop */
2515 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2516 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2517 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2518};
2519
7a89b94e
NC		 2520/* NaCl ARM -> ARM long branch stub. */
2521static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2522{
2523 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2524 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2525 ARM_INSN (0xe12fff1c), /* bx ip */
2526 ARM_INSN (0xe320f000), /* nop */
2527 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2528 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2529 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2530 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2531};
2532
2533/* NaCl ARM -> ARM long branch stub, PIC. */
2534static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2535{
2536 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2537 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2538 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2539 ARM_INSN (0xe12fff1c), /* bx ip */
2540 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2541 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2542 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2543 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2544};
2545
2546
48229727
JB		 2547/* Cortex-A8 erratum-workaround stubs. */
2548
2549/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2550 can't use a conditional branch to reach this stub). */
2551
2552static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2553{
2554 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2555 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2556 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2557};
48229727
JB		 2558
2559/* Stub used for b.w and bl.w instructions. */
2560
2561static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2562{
2563 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2564};
48229727
JB		 2565
2566static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2567{
2568 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2569};
48229727
JB		 2570
2571/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2572 instruction (which switches to ARM mode) to point to this stub. Jump to the
2573 real destination using an ARM-mode branch. */
2574
2575static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2576{
2577 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2578};
48229727 2579
9553db3c
NC		 2580/* For each section group there can be a specially created linker section
2581 to hold the stubs for that group. The name of the stub section is based
2582 upon the name of another section within that group with the suffix below
2583 applied.
2584
2585 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2586 create what appeared to be a linker stub section when it actually
2587 contained user code/data. For example, consider this fragment:
b38cadfb 2588
9553db3c
NC		 2589 const char * stubborn_problems[] = { "np" };
2590
2591 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2592 section called:
2593
2594 .data.rel.local.stubborn_problems
2595
2596 This then causes problems in arm32_arm_build_stubs() as it triggers:
2597
2598 // Ignore non-stub sections.
2599 if (!strstr (stub_sec->name, STUB_SUFFIX))
2600 continue;
2601
2602 And so the section would be ignored instead of being processed. Hence
2603 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2604 C identifier. */
2605#define STUB_SUFFIX ".__stub"
906e58ca 2606
738a79f6
CL		 2607/* One entry per long/short branch stub defined above. */
2608#define DEF_STUBS \
2609 DEF_STUB(long_branch_any_any) \
2610 DEF_STUB(long_branch_v4t_arm_thumb) \
2611 DEF_STUB(long_branch_thumb_only) \
2612 DEF_STUB(long_branch_v4t_thumb_thumb) \
2613 DEF_STUB(long_branch_v4t_thumb_arm) \
2614 DEF_STUB(short_branch_v4t_thumb_arm) \
2615 DEF_STUB(long_branch_any_arm_pic) \
2616 DEF_STUB(long_branch_any_thumb_pic) \
2617 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2618 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2619 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2620 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2621 DEF_STUB(long_branch_any_tls_pic) \
2622 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2623 DEF_STUB(long_branch_arm_nacl) \
2624 DEF_STUB(long_branch_arm_nacl_pic) \
48229727
JB		 2625 DEF_STUB(a8_veneer_b_cond) \
2626 DEF_STUB(a8_veneer_b) \
2627 DEF_STUB(a8_veneer_bl) \
2628 DEF_STUB(a8_veneer_blx)
738a79f6
CL		 2629
2630#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2631enum elf32_arm_stub_type
2632{
906e58ca 2633 arm_stub_none,
738a79f6 2634 DEF_STUBS
6a631e86 2635 /* Note the first a8_veneer type. */
eb7c4339 2636 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
738a79f6
CL		 2637};
2638#undef DEF_STUB
2639
2640typedef struct
2641{
d3ce72d0 2642 const insn_sequence* template_sequence;
738a79f6
CL		 2643 int template_size;
2644} stub_def;
2645
2646#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2647static const stub_def stub_definitions[] =
2648{
738a79f6
CL		 2649 {NULL, 0},
2650 DEF_STUBS
906e58ca
NC		 2651};
2652
2653struct elf32_arm_stub_hash_entry
2654{
2655 /* Base hash table entry structure. */
2656 struct bfd_hash_entry root;
2657
2658 /* The stub section. */
2659 asection *stub_sec;
2660
2661 /* Offset within stub_sec of the beginning of this stub. */
2662 bfd_vma stub_offset;
2663
2664 /* Given the symbol's value and its section we can determine its final
2665 value when building the stubs (so the stub knows where to jump). */
2666 bfd_vma target_value;
2667 asection *target_section;
2668
48229727
JB		 2669 /* Offset to apply to relocation referencing target_value. */
2670 bfd_vma target_addend;
2671
2672 /* The instruction which caused this stub to be generated (only valid for
2673 Cortex-A8 erratum workaround stubs at present). */
2674 unsigned long orig_insn;
2675
461a49ca 2676 /* The stub type. */
906e58ca 2677 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2678 /* Its encoding size in bytes. */
2679 int stub_size;
2680 /* Its template. */
2681 const insn_sequence *stub_template;
2682 /* The size of the template (number of entries). */
2683 int stub_template_size;
906e58ca
NC		 2684
2685 /* The symbol table entry, if any, that this was derived from. */
2686 struct elf32_arm_link_hash_entry *h;
2687
35fc36a8
RS		 2688 /* Type of branch. */
2689 enum arm_st_branch_type branch_type;
906e58ca
NC		 2690
2691 /* Where this stub is being called from, or, in the case of combined
2692 stub sections, the first input section in the group. */
2693 asection *id_sec;
7413f23f
DJ		 2694
2695 /* The name for the local symbol at the start of this stub. The
2696 stub name in the hash table has to be unique; this does not, so
2697 it can be friendlier. */
2698 char *output_name;
906e58ca
NC		 2699};
2700
e489d0ae
PB		 2701/* Used to build a map of a section. This is required for mixed-endian
2702 code/data. */
2703
2704typedef struct elf32_elf_section_map
2705{
2706 bfd_vma vma;
2707 char type;
2708}
2709elf32_arm_section_map;
2710
c7b8f16e
JB		 2711/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2712
2713typedef enum
2714{
2715 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2716 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2717 VFP11_ERRATUM_ARM_VENEER,
2718 VFP11_ERRATUM_THUMB_VENEER
2719}
2720elf32_vfp11_erratum_type;
2721
2722typedef struct elf32_vfp11_erratum_list
2723{
2724 struct elf32_vfp11_erratum_list *next;
2725 bfd_vma vma;
2726 union
2727 {
2728 struct
2729 {
2730 struct elf32_vfp11_erratum_list *veneer;
2731 unsigned int vfp_insn;
2732 } b;
2733 struct
2734 {
2735 struct elf32_vfp11_erratum_list *branch;
2736 unsigned int id;
2737 } v;
2738 } u;
2739 elf32_vfp11_erratum_type type;
2740}
2741elf32_vfp11_erratum_list;
2742
a504d23a
LA		 2743/* Information about a STM32L4XX erratum veneer, or a branch to such a
2744 veneer. */
2745typedef enum
2746{
2747 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2748 STM32L4XX_ERRATUM_VENEER
2749}
2750elf32_stm32l4xx_erratum_type;
2751
2752typedef struct elf32_stm32l4xx_erratum_list
2753{
2754 struct elf32_stm32l4xx_erratum_list *next;
2755 bfd_vma vma;
2756 union
2757 {
2758 struct
2759 {
2760 struct elf32_stm32l4xx_erratum_list *veneer;
2761 unsigned int insn;
2762 } b;
2763 struct
2764 {
2765 struct elf32_stm32l4xx_erratum_list *branch;
2766 unsigned int id;
2767 } v;
2768 } u;
2769 elf32_stm32l4xx_erratum_type type;
2770}
2771elf32_stm32l4xx_erratum_list;
2772
2468f9c9
PB		 2773typedef enum
2774{
2775 DELETE_EXIDX_ENTRY,
2776 INSERT_EXIDX_CANTUNWIND_AT_END
2777}
2778arm_unwind_edit_type;
2779
2780/* A (sorted) list of edits to apply to an unwind table. */
2781typedef struct arm_unwind_table_edit
2782{
2783 arm_unwind_edit_type type;
2784 /* Note: we sometimes want to insert an unwind entry corresponding to a
2785 section different from the one we're currently writing out, so record the
2786 (text) section this edit relates to here. */
2787 asection *linked_section;
2788 unsigned int index;
2789 struct arm_unwind_table_edit *next;
2790}
2791arm_unwind_table_edit;
2792
8e3de13a 2793typedef struct _arm_elf_section_data
e489d0ae 2794{
2468f9c9 2795 /* Information about mapping symbols. */
e489d0ae 2796 struct bfd_elf_section_data elf;
8e3de13a 2797 unsigned int mapcount;
c7b8f16e 2798 unsigned int mapsize;
e489d0ae 2799 elf32_arm_section_map *map;
2468f9c9 2800 /* Information about CPU errata. */
c7b8f16e
JB		 2801 unsigned int erratumcount;
2802 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2803 unsigned int stm32l4xx_erratumcount;
2804 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2805 unsigned int additional_reloc_count;
2468f9c9
PB		 2806 /* Information about unwind tables. */
2807 union
2808 {
2809 /* Unwind info attached to a text section. */
2810 struct
2811 {
2812 asection *arm_exidx_sec;
2813 } text;
2814
2815 /* Unwind info attached to an .ARM.exidx section. */
2816 struct
2817 {
2818 arm_unwind_table_edit *unwind_edit_list;
2819 arm_unwind_table_edit *unwind_edit_tail;
2820 } exidx;
2821 } u;
8e3de13a
NC		 2822}
2823_arm_elf_section_data;
e489d0ae
PB		 2824
2825#define elf32_arm_section_data(sec) \
8e3de13a 2826 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2827
48229727
JB		 2828/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2829 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2830 so may be created multiple times: we use an array of these entries whilst
2831 relaxing which we can refresh easily, then create stubs for each potentially
2832 erratum-triggering instruction once we've settled on a solution. */
2833
b38cadfb
NC		 2834struct a8_erratum_fix
2835{
48229727
JB		 2836 bfd *input_bfd;
2837 asection *section;
2838 bfd_vma offset;
2839 bfd_vma addend;
2840 unsigned long orig_insn;
2841 char *stub_name;
2842 enum elf32_arm_stub_type stub_type;
35fc36a8 2843 enum arm_st_branch_type branch_type;
48229727
JB		 2844};
2845
2846/* A table of relocs applied to branches which might trigger Cortex-A8
2847 erratum. */
2848
b38cadfb
NC		 2849struct a8_erratum_reloc
2850{
48229727
JB		 2851 bfd_vma from;
2852 bfd_vma destination;
92750f34
DJ		 2853 struct elf32_arm_link_hash_entry *hash;
2854 const char *sym_name;
48229727 2855 unsigned int r_type;
35fc36a8 2856 enum arm_st_branch_type branch_type;
48229727
JB		 2857 bfd_boolean non_a8_stub;
2858};
2859
ba93b8ac
DJ		 2860/* The size of the thread control block. */
2861#define TCB_SIZE 8
2862
34e77a92
RS		 2863/* ARM-specific information about a PLT entry, over and above the usual
2864 gotplt_union. */
b38cadfb
NC		 2865struct arm_plt_info
2866{
34e77a92
RS		 2867 /* We reference count Thumb references to a PLT entry separately,
2868 so that we can emit the Thumb trampoline only if needed. */
2869 bfd_signed_vma thumb_refcount;
2870
2871 /* Some references from Thumb code may be eliminated by BL->BLX
2872 conversion, so record them separately. */
2873 bfd_signed_vma maybe_thumb_refcount;
2874
2875 /* How many of the recorded PLT accesses were from non-call relocations.
2876 This information is useful when deciding whether anything takes the
2877 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2878 non-call references to the function should resolve directly to the
2879 real runtime target. */
2880 unsigned int noncall_refcount;
2881
2882 /* Since PLT entries have variable size if the Thumb prologue is
2883 used, we need to record the index into .got.plt instead of
2884 recomputing it from the PLT offset. */
2885 bfd_signed_vma got_offset;
2886};
2887
2888/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2889struct arm_local_iplt_info
2890{
34e77a92
RS		 2891 /* The information that is usually found in the generic ELF part of
2892 the hash table entry. */
2893 union gotplt_union root;
2894
2895 /* The information that is usually found in the ARM-specific part of
2896 the hash table entry. */
2897 struct arm_plt_info arm;
2898
2899 /* A list of all potential dynamic relocations against this symbol. */
2900 struct elf_dyn_relocs *dyn_relocs;
2901};
2902
0ffa91dd 2903struct elf_arm_obj_tdata
ba93b8ac
DJ		 2904{
2905 struct elf_obj_tdata root;
2906
2907 /* tls_type for each local got entry. */
2908 char *local_got_tls_type;
ee065d83 2909
0855e32b
NS		 2910 /* GOTPLT entries for TLS descriptors. */
2911 bfd_vma *local_tlsdesc_gotent;
2912
34e77a92
RS		 2913 /* Information for local symbols that need entries in .iplt. */
2914 struct arm_local_iplt_info **local_iplt;
2915
bf21ed78
MS		 2916 /* Zero to warn when linking objects with incompatible enum sizes. */
2917 int no_enum_size_warning;
a9dc9481
JM		 2918
2919 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2920 int no_wchar_size_warning;
ba93b8ac
DJ		 2921};
2922
0ffa91dd
NC		 2923#define elf_arm_tdata(bfd) \
2924 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2925
0ffa91dd
NC		 2926#define elf32_arm_local_got_tls_type(bfd) \
2927 (elf_arm_tdata (bfd)->local_got_tls_type)
2928
0855e32b
NS		 2929#define elf32_arm_local_tlsdesc_gotent(bfd) \
2930 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2931
34e77a92
RS		 2932#define elf32_arm_local_iplt(bfd) \
2933 (elf_arm_tdata (bfd)->local_iplt)
2934
0ffa91dd
NC		 2935#define is_arm_elf(bfd) \
2936 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2937 && elf_tdata (bfd) != NULL \
4dfe6ac6 2938 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2939
2940static bfd_boolean
2941elf32_arm_mkobject (bfd *abfd)
2942{
0ffa91dd 2943 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2944 ARM_ELF_DATA);
ba93b8ac
DJ		 2945}
2946
ba93b8ac
DJ		 2947#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2948
ba96a88f 2949/* Arm ELF linker hash entry. */
252b5132 2950struct elf32_arm_link_hash_entry
b38cadfb
NC		 2951{
2952 struct elf_link_hash_entry root;
252b5132 2953
b38cadfb
NC		 2954 /* Track dynamic relocs copied for this symbol. */
2955 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2956
b38cadfb
NC		 2957 /* ARM-specific PLT information. */
2958 struct arm_plt_info plt;
ba93b8ac
DJ		 2959
2960#define GOT_UNKNOWN 0
2961#define GOT_NORMAL 1
2962#define GOT_TLS_GD 2
2963#define GOT_TLS_IE 4
0855e32b
NS		 2964#define GOT_TLS_GDESC 8
2965#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 2966 unsigned int tls_type : 8;
34e77a92 2967
b38cadfb
NC		 2968 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2969 unsigned int is_iplt : 1;
34e77a92 2970
b38cadfb 2971 unsigned int unused : 23;
a4fd1a8e 2972
b38cadfb
NC		 2973 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2974 starting at the end of the jump table. */
2975 bfd_vma tlsdesc_got;
0855e32b 2976
b38cadfb
NC		 2977 /* The symbol marking the real symbol location for exported thumb
2978 symbols with Arm stubs. */
2979 struct elf_link_hash_entry *export_glue;
906e58ca 2980
b38cadfb 2981 /* A pointer to the most recently used stub hash entry against this
8029a119 2982 symbol. */
b38cadfb
NC		 2983 struct elf32_arm_stub_hash_entry *stub_cache;
2984};
252b5132 2985
252b5132 2986/* Traverse an arm ELF linker hash table. */
252b5132
RH		 2987#define elf32_arm_link_hash_traverse(table, func, info) \
2988 (elf_link_hash_traverse \
2989 (&(table)->root, \
b7693d02 2990 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 2991 (info)))
2992
2993/* Get the ARM elf linker hash table from a link_info structure. */
2994#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 2995 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2996 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 2997
906e58ca
NC		 2998#define arm_stub_hash_lookup(table, string, create, copy) \
2999 ((struct elf32_arm_stub_hash_entry *) \
3000 bfd_hash_lookup ((table), (string), (create), (copy)))
3001
21d799b5
NC		 3002/* Array to keep track of which stub sections have been created, and
3003 information on stub grouping. */
3004struct map_stub
3005{
3006 /* This is the section to which stubs in the group will be
3007 attached. */
3008 asection *link_sec;
3009 /* The stub section. */
3010 asection *stub_sec;
3011};
3012
0855e32b
NS		 3013#define elf32_arm_compute_jump_table_size(htab) \
3014 ((htab)->next_tls_desc_index * 4)
3015
9b485d32 3016/* ARM ELF linker hash table. */
252b5132 3017struct elf32_arm_link_hash_table
906e58ca
NC		 3018{
3019 /* The main hash table. */
3020 struct elf_link_hash_table root;
252b5132 3021
906e58ca
NC		 3022 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3023 bfd_size_type thumb_glue_size;
252b5132 3024
906e58ca
NC		 3025 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3026 bfd_size_type arm_glue_size;
252b5132 3027
906e58ca
NC		 3028 /* The size in bytes of section containing the ARMv4 BX veneers. */
3029 bfd_size_type bx_glue_size;
845b51d6 3030
906e58ca
NC		 3031 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3032 veneer has been populated. */
3033 bfd_vma bx_glue_offset[15];
845b51d6 3034
906e58ca
NC		 3035 /* The size in bytes of the section containing glue for VFP11 erratum
3036 veneers. */
3037 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3038
a504d23a
LA		 3039 /* The size in bytes of the section containing glue for STM32L4XX erratum
3040 veneers. */
3041 bfd_size_type stm32l4xx_erratum_glue_size;
3042
48229727
JB		 3043 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3044 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3045 elf32_arm_write_section(). */
3046 struct a8_erratum_fix *a8_erratum_fixes;
3047 unsigned int num_a8_erratum_fixes;
3048
906e58ca
NC		 3049 /* An arbitrary input BFD chosen to hold the glue sections. */
3050 bfd * bfd_of_glue_owner;
ba96a88f 3051
906e58ca
NC		 3052 /* Nonzero to output a BE8 image. */
3053 int byteswap_code;
e489d0ae 3054
906e58ca
NC		 3055 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3056 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3057 int target1_is_rel;
9c504268 3058
906e58ca
NC		 3059 /* The relocation to use for R_ARM_TARGET2 relocations. */
3060 int target2_reloc;
eb043451 3061
906e58ca
NC		 3062 /* 0 = Ignore R_ARM_V4BX.
3063 1 = Convert BX to MOV PC.
3064 2 = Generate v4 interworing stubs. */
3065 int fix_v4bx;
319850b4 3066
48229727
JB		 3067 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3068 int fix_cortex_a8;
3069
2de70689
MGD		 3070 /* Whether we should fix the ARM1176 BLX immediate issue. */
3071 int fix_arm1176;
3072
906e58ca
NC		 3073 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3074 int use_blx;
33bfe774 3075
906e58ca
NC		 3076 /* What sort of code sequences we should look for which may trigger the
3077 VFP11 denorm erratum. */
3078 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3079
906e58ca
NC		 3080 /* Global counter for the number of fixes we have emitted. */
3081 int num_vfp11_fixes;
c7b8f16e 3082
a504d23a
LA		 3083 /* What sort of code sequences we should look for which may trigger the
3084 STM32L4XX erratum. */
3085 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3086
3087 /* Global counter for the number of fixes we have emitted. */
3088 int num_stm32l4xx_fixes;
3089
906e58ca
NC		 3090 /* Nonzero to force PIC branch veneers. */
3091 int pic_veneer;
27e55c4d 3092
906e58ca
NC		 3093 /* The number of bytes in the initial entry in the PLT. */
3094 bfd_size_type plt_header_size;
e5a52504 3095
906e58ca
NC		 3096 /* The number of bytes in the subsequent PLT etries. */
3097 bfd_size_type plt_entry_size;
e5a52504 3098
906e58ca
NC		 3099 /* True if the target system is VxWorks. */
3100 int vxworks_p;
00a97672 3101
906e58ca
NC		 3102 /* True if the target system is Symbian OS. */
3103 int symbian_p;
e5a52504 3104
b38cadfb
NC		 3105 /* True if the target system is Native Client. */
3106 int nacl_p;
3107
906e58ca
NC		 3108 /* True if the target uses REL relocations. */
3109 int use_rel;
4e7fd91e 3110
0855e32b
NS		 3111 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3112 bfd_vma next_tls_desc_index;
3113
3114 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3115 bfd_vma num_tls_desc;
3116
906e58ca 3117 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3118 asection *sdynbss;
3119 asection *srelbss;
5e681ec4 3120
906e58ca
NC		 3121 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3122 asection *srelplt2;
00a97672 3123
0855e32b
NS		 3124 /* The offset into splt of the PLT entry for the TLS descriptor
3125 resolver. Special values are 0, if not necessary (or not found
3126 to be necessary yet), and -1 if needed but not determined
3127 yet. */
3128 bfd_vma dt_tlsdesc_plt;
3129
3130 /* The offset into sgot of the GOT entry used by the PLT entry
3131 above. */
b38cadfb 3132 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3133
3134 /* Offset in .plt section of tls_arm_trampoline. */
3135 bfd_vma tls_trampoline;
3136
906e58ca
NC		 3137 /* Data for R_ARM_TLS_LDM32 relocations. */
3138 union
3139 {
3140 bfd_signed_vma refcount;
3141 bfd_vma offset;
3142 } tls_ldm_got;
b7693d02 3143
87d72d41
AM		 3144 /* Small local sym cache. */
3145 struct sym_cache sym_cache;
906e58ca
NC		 3146
3147 /* For convenience in allocate_dynrelocs. */
3148 bfd * obfd;
3149
0855e32b
NS		 3150 /* The amount of space used by the reserved portion of the sgotplt
3151 section, plus whatever space is used by the jump slots. */
3152 bfd_vma sgotplt_jump_table_size;
3153
906e58ca
NC		 3154 /* The stub hash table. */
3155 struct bfd_hash_table stub_hash_table;
3156
3157 /* Linker stub bfd. */
3158 bfd *stub_bfd;
3159
3160 /* Linker call-backs. */
7a89b94e 3161 asection * (*add_stub_section) (const char *, asection *, unsigned int);
906e58ca
NC		 3162 void (*layout_sections_again) (void);
3163
3164 /* Array to keep track of which stub sections have been created, and
3165 information on stub grouping. */
21d799b5 3166 struct map_stub *stub_group;
906e58ca 3167
fe33d2fa 3168 /* Number of elements in stub_group. */
7292b3ac 3169 unsigned int top_id;
fe33d2fa 3170
906e58ca
NC		 3171 /* Assorted information used by elf32_arm_size_stubs. */
3172 unsigned int bfd_count;
7292b3ac 3173 unsigned int top_index;
906e58ca
NC		 3174 asection **input_list;
3175};
252b5132 3176
a504d23a
LA		 3177static inline int
3178ctz (unsigned int mask)
3179{
3180#if GCC_VERSION >= 3004
3181 return __builtin_ctz (mask);
3182#else
3183 unsigned int i;
3184
3185 for (i = 0; i < 8 * sizeof (mask); i++)
3186 {
3187 if (mask & 0x1)
3188 break;
3189 mask = (mask >> 1);
3190 }
3191 return i;
3192#endif
3193}
3194
3195static inline int
3196popcount (unsigned int mask)
3197{
3198#if GCC_VERSION >= 3004
3199 return __builtin_popcount (mask);
3200#else
3201 unsigned int i, sum = 0;
3202
3203 for (i = 0; i < 8 * sizeof (mask); i++)
3204 {
3205 if (mask & 0x1)
3206 sum++;
3207 mask = (mask >> 1);
3208 }
3209 return sum;
3210#endif
3211}
3212
780a67af
NC		 3213/* Create an entry in an ARM ELF linker hash table. */
3214
3215static struct bfd_hash_entry *
57e8b36a 3216elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3217 struct bfd_hash_table * table,
3218 const char * string)
780a67af
NC		 3219{
3220 struct elf32_arm_link_hash_entry * ret =
3221 (struct elf32_arm_link_hash_entry *) entry;
3222
3223 /* Allocate the structure if it has not already been allocated by a
3224 subclass. */
906e58ca 3225 if (ret == NULL)
21d799b5 3226 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3227 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3228 if (ret == NULL)
780a67af
NC		 3229 return (struct bfd_hash_entry *) ret;
3230
3231 /* Call the allocation method of the superclass. */
3232 ret = ((struct elf32_arm_link_hash_entry *)
3233 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3234 table, string));
57e8b36a 3235 if (ret != NULL)
b7693d02 3236 {
0bdcacaf 3237 ret->dyn_relocs = NULL;
ba93b8ac 3238 ret->tls_type = GOT_UNKNOWN;
0855e32b 3239 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3240 ret->plt.thumb_refcount = 0;
3241 ret->plt.maybe_thumb_refcount = 0;
3242 ret->plt.noncall_refcount = 0;
3243 ret->plt.got_offset = -1;
3244 ret->is_iplt = FALSE;
a4fd1a8e 3245 ret->export_glue = NULL;
906e58ca
NC		 3246
3247 ret->stub_cache = NULL;
b7693d02 3248 }
780a67af
NC		 3249
3250 return (struct bfd_hash_entry *) ret;
3251}
3252
34e77a92
RS		 3253/* Ensure that we have allocated bookkeeping structures for ABFD's local
3254 symbols. */
3255
3256static bfd_boolean
3257elf32_arm_allocate_local_sym_info (bfd *abfd)
3258{
3259 if (elf_local_got_refcounts (abfd) == NULL)
3260 {
3261 bfd_size_type num_syms;
3262 bfd_size_type size;
3263 char *data;
3264
3265 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3266 size = num_syms * (sizeof (bfd_signed_vma)
3267 + sizeof (struct arm_local_iplt_info *)
3268 + sizeof (bfd_vma)
3269 + sizeof (char));
3270 data = bfd_zalloc (abfd, size);
3271 if (data == NULL)
3272 return FALSE;
3273
3274 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3275 data += num_syms * sizeof (bfd_signed_vma);
3276
3277 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3278 data += num_syms * sizeof (struct arm_local_iplt_info *);
3279
3280 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3281 data += num_syms * sizeof (bfd_vma);
3282
3283 elf32_arm_local_got_tls_type (abfd) = data;
3284 }
3285 return TRUE;
3286}
3287
3288/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3289 to input bfd ABFD. Create the information if it doesn't already exist.
3290 Return null if an allocation fails. */
3291
3292static struct arm_local_iplt_info *
3293elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3294{
3295 struct arm_local_iplt_info **ptr;
3296
3297 if (!elf32_arm_allocate_local_sym_info (abfd))
3298 return NULL;
3299
3300 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3301 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3302 if (*ptr == NULL)
3303 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3304 return *ptr;
3305}
3306
3307/* Try to obtain PLT information for the symbol with index R_SYMNDX
3308 in ABFD's symbol table. If the symbol is global, H points to its
3309 hash table entry, otherwise H is null.
3310
3311 Return true if the symbol does have PLT information. When returning
3312 true, point *ROOT_PLT at the target-independent reference count/offset
3313 union and *ARM_PLT at the ARM-specific information. */
3314
3315static bfd_boolean
3316elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_entry *h,
3317 unsigned long r_symndx, union gotplt_union **root_plt,
3318 struct arm_plt_info **arm_plt)
3319{
3320 struct arm_local_iplt_info *local_iplt;
3321
3322 if (h != NULL)
3323 {
3324 *root_plt = &h->root.plt;
3325 *arm_plt = &h->plt;
3326 return TRUE;
3327 }
3328
3329 if (elf32_arm_local_iplt (abfd) == NULL)
3330 return FALSE;
3331
3332 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3333 if (local_iplt == NULL)
3334 return FALSE;
3335
3336 *root_plt = &local_iplt->root;
3337 *arm_plt = &local_iplt->arm;
3338 return TRUE;
3339}
3340
3341/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3342 before it. */
3343
3344static bfd_boolean
3345elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3346 struct arm_plt_info *arm_plt)
3347{
3348 struct elf32_arm_link_hash_table *htab;
3349
3350 htab = elf32_arm_hash_table (info);
3351 return (arm_plt->thumb_refcount != 0
3352 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3353}
3354
3355/* Return a pointer to the head of the dynamic reloc list that should
3356 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3357 ABFD's symbol table. Return null if an error occurs. */
3358
3359static struct elf_dyn_relocs **
3360elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3361 Elf_Internal_Sym *isym)
3362{
3363 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3364 {
3365 struct arm_local_iplt_info *local_iplt;
3366
3367 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3368 if (local_iplt == NULL)
3369 return NULL;
3370 return &local_iplt->dyn_relocs;
3371 }
3372 else
3373 {
3374 /* Track dynamic relocs needed for local syms too.
3375 We really need local syms available to do this
3376 easily. Oh well. */
3377 asection *s;
3378 void *vpp;
3379
3380 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3381 if (s == NULL)
3382 abort ();
3383
3384 vpp = &elf_section_data (s)->local_dynrel;
3385 return (struct elf_dyn_relocs **) vpp;
3386 }
3387}
3388
906e58ca
NC		 3389/* Initialize an entry in the stub hash table. */
3390
3391static struct bfd_hash_entry *
3392stub_hash_newfunc (struct bfd_hash_entry *entry,
3393 struct bfd_hash_table *table,
3394 const char *string)
3395{
3396 /* Allocate the structure if it has not already been allocated by a
3397 subclass. */
3398 if (entry == NULL)
3399 {
21d799b5 3400 entry = (struct bfd_hash_entry *)
99059e56 3401 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3402 if (entry == NULL)
3403 return entry;
3404 }
3405
3406 /* Call the allocation method of the superclass. */
3407 entry = bfd_hash_newfunc (entry, table, string);
3408 if (entry != NULL)
3409 {
3410 struct elf32_arm_stub_hash_entry *eh;
3411
3412 /* Initialize the local fields. */
3413 eh = (struct elf32_arm_stub_hash_entry *) entry;
3414 eh->stub_sec = NULL;
3415 eh->stub_offset = 0;
3416 eh->target_value = 0;
3417 eh->target_section = NULL;
cedfb179
DK		 3418 eh->target_addend = 0;
3419 eh->orig_insn = 0;
906e58ca 3420 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3421 eh->stub_size = 0;
3422 eh->stub_template = NULL;
3423 eh->stub_template_size = 0;
906e58ca
NC		 3424 eh->h = NULL;
3425 eh->id_sec = NULL;
d8d2f433 3426 eh->output_name = NULL;
906e58ca
NC		 3427 }
3428
3429 return entry;
3430}
3431
00a97672 3432/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3433 shortcuts to them in our hash table. */
3434
3435static bfd_boolean
57e8b36a 3436create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3437{
3438 struct elf32_arm_link_hash_table *htab;
3439
e5a52504 3440 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3441 if (htab == NULL)
3442 return FALSE;
3443
e5a52504
MM		 3444 /* BPABI objects never have a GOT, or associated sections. */
3445 if (htab->symbian_p)
3446 return TRUE;
3447
5e681ec4
PB		 3448 if (! _bfd_elf_create_got_section (dynobj, info))
3449 return FALSE;
3450
5e681ec4
PB		 3451 return TRUE;
3452}
3453
34e77a92
RS		 3454/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3455
3456static bfd_boolean
3457create_ifunc_sections (struct bfd_link_info *info)
3458{
3459 struct elf32_arm_link_hash_table *htab;
3460 const struct elf_backend_data *bed;
3461 bfd *dynobj;
3462 asection *s;
3463 flagword flags;
b38cadfb 3464
34e77a92
RS		 3465 htab = elf32_arm_hash_table (info);
3466 dynobj = htab->root.dynobj;
3467 bed = get_elf_backend_data (dynobj);
3468 flags = bed->dynamic_sec_flags;
3469
3470 if (htab->root.iplt == NULL)
3471 {
3d4d4302
AM		 3472 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3473 flags | SEC_READONLY | SEC_CODE);
34e77a92 3474 if (s == NULL
a0f49396 3475 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3476 return FALSE;
3477 htab->root.iplt = s;
3478 }
3479
3480 if (htab->root.irelplt == NULL)
3481 {
3d4d4302
AM		 3482 s = bfd_make_section_anyway_with_flags (dynobj,
3483 RELOC_SECTION (htab, ".iplt"),
3484 flags | SEC_READONLY);
34e77a92 3485 if (s == NULL
a0f49396 3486 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3487 return FALSE;
3488 htab->root.irelplt = s;
3489 }
3490
3491 if (htab->root.igotplt == NULL)
3492 {
3d4d4302 3493 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3494 if (s == NULL
3495 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3496 return FALSE;
3497 htab->root.igotplt = s;
3498 }
3499 return TRUE;
3500}
3501
eed94f8f
NC		 3502/* Determine if we're dealing with a Thumb only architecture. */
3503
3504static bfd_boolean
3505using_thumb_only (struct elf32_arm_link_hash_table *globals)
3506{
2fd158eb
TP		 3507 int arch;
3508 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3509 Tag_CPU_arch_profile);
eed94f8f 3510
2fd158eb
TP		 3511 if (profile)
3512 return profile == 'M';
eed94f8f 3513
2fd158eb 3514 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3515
2fd158eb
TP		 3516 if (arch == TAG_CPU_ARCH_V6_M
3517 || arch == TAG_CPU_ARCH_V6S_M
3518 || arch == TAG_CPU_ARCH_V7E_M
3519 || arch == TAG_CPU_ARCH_V8M_BASE
3520 || arch == TAG_CPU_ARCH_V8M_MAIN)
3521 return TRUE;
eed94f8f 3522
2fd158eb 3523 return FALSE;
eed94f8f
NC		 3524}
3525
3526/* Determine if we're dealing with a Thumb-2 object. */
3527
3528static bfd_boolean
3529using_thumb2 (struct elf32_arm_link_hash_table *globals)
3530{
3531 int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3532 Tag_CPU_arch);
3533 return arch == TAG_CPU_ARCH_V6T2 || arch >= TAG_CPU_ARCH_V7;
3534}
3535
00a97672
RS		 3536/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3537 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3538 hash table. */
3539
3540static bfd_boolean
57e8b36a 3541elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3542{
3543 struct elf32_arm_link_hash_table *htab;
3544
3545 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3546 if (htab == NULL)
3547 return FALSE;
3548
362d30a1 3549 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3550 return FALSE;
3551
3552 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3553 return FALSE;
3554
3d4d4302 3555 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3556 if (!bfd_link_pic (info))
3d4d4302
AM		 3557 htab->srelbss = bfd_get_linker_section (dynobj,
3558 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3559
3560 if (htab->vxworks_p)
3561 {
3562 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3563 return FALSE;
3564
0e1862bb 3565 if (bfd_link_pic (info))
00a97672
RS		 3566 {
3567 htab->plt_header_size = 0;
3568 htab->plt_entry_size
3569 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3570 }
3571 else
3572 {
3573 htab->plt_header_size
3574 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3575 htab->plt_entry_size
3576 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3577 }
aebf9be7
NC		 3578
3579 if (elf_elfheader (dynobj))
3580 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3581 }
eed94f8f
NC		 3582 else
3583 {
3584 /* PR ld/16017
3585 Test for thumb only architectures. Note - we cannot just call
3586 using_thumb_only() as the attributes in the output bfd have not been
3587 initialised at this point, so instead we use the input bfd. */
3588 bfd * saved_obfd = htab->obfd;
3589
3590 htab->obfd = dynobj;
3591 if (using_thumb_only (htab))
3592 {
3593 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3594 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3595 }
3596 htab->obfd = saved_obfd;
3597 }
5e681ec4 3598
362d30a1
RS		 3599 if (!htab->root.splt
3600 || !htab->root.srelplt
e5a52504 3601 || !htab->sdynbss
0e1862bb 3602 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3603 abort ();
3604
3605 return TRUE;
3606}
3607
906e58ca
NC		 3608/* Copy the extra info we tack onto an elf_link_hash_entry. */
3609
3610static void
3611elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3612 struct elf_link_hash_entry *dir,
3613 struct elf_link_hash_entry *ind)
3614{
3615 struct elf32_arm_link_hash_entry *edir, *eind;
3616
3617 edir = (struct elf32_arm_link_hash_entry *) dir;
3618 eind = (struct elf32_arm_link_hash_entry *) ind;
3619
0bdcacaf 3620 if (eind->dyn_relocs != NULL)
906e58ca 3621 {
0bdcacaf 3622 if (edir->dyn_relocs != NULL)
906e58ca 3623 {
0bdcacaf
RS		 3624 struct elf_dyn_relocs **pp;
3625 struct elf_dyn_relocs *p;
906e58ca
NC		 3626
3627 /* Add reloc counts against the indirect sym to the direct sym
3628 list. Merge any entries against the same section. */
0bdcacaf 3629 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3630 {
0bdcacaf 3631 struct elf_dyn_relocs *q;
906e58ca 3632
0bdcacaf
RS		 3633 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3634 if (q->sec == p->sec)
906e58ca
NC		 3635 {
3636 q->pc_count += p->pc_count;
3637 q->count += p->count;
3638 *pp = p->next;
3639 break;
3640 }
3641 if (q == NULL)
3642 pp = &p->next;
3643 }
0bdcacaf 3644 *pp = edir->dyn_relocs;
906e58ca
NC		 3645 }
3646
0bdcacaf
RS		 3647 edir->dyn_relocs = eind->dyn_relocs;
3648 eind->dyn_relocs = NULL;
906e58ca
NC		 3649 }
3650
3651 if (ind->root.type == bfd_link_hash_indirect)
3652 {
3653 /* Copy over PLT info. */
34e77a92
RS		 3654 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3655 eind->plt.thumb_refcount = 0;
3656 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3657 eind->plt.maybe_thumb_refcount = 0;
3658 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3659 eind->plt.noncall_refcount = 0;
3660
3661 /* We should only allocate a function to .iplt once the final
3662 symbol information is known. */
3663 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3664
3665 if (dir->got.refcount <= 0)
3666 {
3667 edir->tls_type = eind->tls_type;
3668 eind->tls_type = GOT_UNKNOWN;
3669 }
3670 }
3671
3672 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3673}
3674
68faa637
AM		 3675/* Destroy an ARM elf linker hash table. */
3676
3677static void
d495ab0d 3678elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3679{
3680 struct elf32_arm_link_hash_table *ret
d495ab0d 3681 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3682
3683 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3684 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3685}
3686
906e58ca
NC		 3687/* Create an ARM elf linker hash table. */
3688
3689static struct bfd_link_hash_table *
3690elf32_arm_link_hash_table_create (bfd *abfd)
3691{
3692 struct elf32_arm_link_hash_table *ret;
3693 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3694
7bf52ea2 3695 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3696 if (ret == NULL)
3697 return NULL;
3698
3699 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3700 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3701 sizeof (struct elf32_arm_link_hash_entry),
3702 ARM_ELF_DATA))
906e58ca
NC		 3703 {
3704 free (ret);
3705 return NULL;
3706 }
3707
906e58ca 3708 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3709 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3710#ifdef FOUR_WORD_PLT
3711 ret->plt_header_size = 16;
3712 ret->plt_entry_size = 16;
3713#else
3714 ret->plt_header_size = 20;
1db37fe6 3715 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3716#endif
906e58ca 3717 ret->use_rel = 1;
906e58ca 3718 ret->obfd = abfd;
906e58ca
NC		 3719
3720 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3721 sizeof (struct elf32_arm_stub_hash_entry)))
3722 {
d495ab0d 3723 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3724 return NULL;
3725 }
d495ab0d 3726 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3727
3728 return &ret->root.root;
3729}
3730
cd1dac3d
DG		 3731/* Determine what kind of NOPs are available. */
3732
3733static bfd_boolean
3734arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3735{
3736 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3737 Tag_CPU_arch);
3738 return arch == TAG_CPU_ARCH_V6T2
3739 || arch == TAG_CPU_ARCH_V6K
9e3c6df6
PB		 3740 || arch == TAG_CPU_ARCH_V7
3741 || arch == TAG_CPU_ARCH_V7E_M;
cd1dac3d
DG		 3742}
3743
3744static bfd_boolean
3745arch_has_thumb2_nop (struct elf32_arm_link_hash_table *globals)
3746{
3747 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3748 Tag_CPU_arch);
9e3c6df6
PB		 3749 return (arch == TAG_CPU_ARCH_V6T2 || arch == TAG_CPU_ARCH_V7
3750 || arch == TAG_CPU_ARCH_V7E_M);
cd1dac3d
DG		 3751}
3752
f4ac8484
DJ		 3753static bfd_boolean
3754arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3755{
3756 switch (stub_type)
3757 {
fea2b4d6
CL		 3758 case arm_stub_long_branch_thumb_only:
3759 case arm_stub_long_branch_v4t_thumb_arm:
3760 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3761 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3762 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3763 case arm_stub_long_branch_thumb_only_pic:
f4ac8484
DJ		 3764 return TRUE;
3765 case arm_stub_none:
3766 BFD_FAIL ();
3767 return FALSE;
3768 break;
3769 default:
3770 return FALSE;
3771 }
3772}
3773
906e58ca
NC		 3774/* Determine the type of stub needed, if any, for a call. */
3775
3776static enum elf32_arm_stub_type
3777arm_type_of_stub (struct bfd_link_info *info,
3778 asection *input_sec,
3779 const Elf_Internal_Rela *rel,
34e77a92 3780 unsigned char st_type,
35fc36a8 3781 enum arm_st_branch_type *actual_branch_type,
906e58ca 3782 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3783 bfd_vma destination,
3784 asection *sym_sec,
3785 bfd *input_bfd,
3786 const char *name)
906e58ca
NC		 3787{
3788 bfd_vma location;
3789 bfd_signed_vma branch_offset;
3790 unsigned int r_type;
3791 struct elf32_arm_link_hash_table * globals;
3792 int thumb2;
3793 int thumb_only;
3794 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3795 int use_plt = 0;
35fc36a8 3796 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3797 union gotplt_union *root_plt;
3798 struct arm_plt_info *arm_plt;
906e58ca 3799
35fc36a8 3800 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3801 return stub_type;
3802
906e58ca 3803 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3804 if (globals == NULL)
3805 return stub_type;
906e58ca
NC		 3806
3807 thumb_only = using_thumb_only (globals);
3808
3809 thumb2 = using_thumb2 (globals);
3810
3811 /* Determine where the call point is. */
3812 location = (input_sec->output_offset
3813 + input_sec->output_section->vma
3814 + rel->r_offset);
3815
906e58ca
NC		 3816 r_type = ELF32_R_TYPE (rel->r_info);
3817
39f21624
NC		 3818 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3819 are considering a function call relocation. */
c5423981
TG		 3820 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3821 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3822 && branch_type == ST_BRANCH_TO_ARM)
3823 branch_type = ST_BRANCH_TO_THUMB;
3824
34e77a92
RS		 3825 /* For TLS call relocs, it is the caller's responsibility to provide
3826 the address of the appropriate trampoline. */
3827 if (r_type != R_ARM_TLS_CALL
3828 && r_type != R_ARM_THM_TLS_CALL
3829 && elf32_arm_get_plt_info (input_bfd, hash, ELF32_R_SYM (rel->r_info),
3830 &root_plt, &arm_plt)
3831 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3832 {
34e77a92 3833 asection *splt;
fe33d2fa 3834
34e77a92
RS		 3835 if (hash == NULL || hash->is_iplt)
3836 splt = globals->root.iplt;
3837 else
3838 splt = globals->root.splt;
3839 if (splt != NULL)
b38cadfb 3840 {
34e77a92
RS		 3841 use_plt = 1;
3842
3843 /* Note when dealing with PLT entries: the main PLT stub is in
3844 ARM mode, so if the branch is in Thumb mode, another
3845 Thumb->ARM stub will be inserted later just before the ARM
3846 PLT stub. We don't take this extra distance into account
3847 here, because if a long branch stub is needed, we'll add a
3848 Thumb->Arm one and branch directly to the ARM PLT entry
3849 because it avoids spreading offset corrections in several
3850 places. */
3851
3852 destination = (splt->output_section->vma
3853 + splt->output_offset
3854 + root_plt->offset);
3855 st_type = STT_FUNC;
3856 branch_type = ST_BRANCH_TO_ARM;
3857 }
5fa9e92f 3858 }
34e77a92
RS		 3859 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3860 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3861
fe33d2fa
CL		 3862 branch_offset = (bfd_signed_vma)(destination - location);
3863
0855e32b 3864 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3865 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3866 {
5fa9e92f
CL		 3867 /* Handle cases where:
3868 - this call goes too far (different Thumb/Thumb2 max
99059e56 3869 distance)
155d87d7 3870 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3871 Thumb->Arm branch (not bl). A stub is needed in this case,
3872 but only if this call is not through a PLT entry. Indeed,
3873 PLT stubs handle mode switching already.
5fa9e92f 3874 */
906e58ca
NC		 3875 if ((!thumb2
3876 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3877 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
3878 || (thumb2
3879 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3880 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3881 || (thumb2
3882 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3883 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3884 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3885 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3886 && (((r_type == R_ARM_THM_CALL
3887 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3888 || (r_type == R_ARM_THM_JUMP24)
3889 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3890 && !use_plt))
906e58ca 3891 {
35fc36a8 3892 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3893 {
3894 /* Thumb to thumb. */
3895 if (!thumb_only)
3896 {
0e1862bb 3897 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3898 /* PIC stubs. */
155d87d7 3899 ? ((globals->use_blx
9553db3c 3900 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 3901 /* V5T and above. Stub starts with ARM code, so
3902 we must be able to switch mode before
3903 reaching it, which is only possible for 'bl'
3904 (ie R_ARM_THM_CALL relocation). */
cf3eccff 3905 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 3906 /* On V4T, use Thumb code only. */
d3626fb0 3907 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 3908
3909 /* non-PIC stubs. */
155d87d7 3910 : ((globals->use_blx
9553db3c 3911 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 3912 /* V5T and above. */
3913 ? arm_stub_long_branch_any_any
3914 /* V4T. */
d3626fb0 3915 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 3916 }
3917 else
3918 {
0e1862bb 3919 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
ebe24dd4
CL		 3920 /* PIC stub. */
3921 ? arm_stub_long_branch_thumb_only_pic
c2b4a39d
CL		 3922 /* non-PIC stub. */
3923 : arm_stub_long_branch_thumb_only;
906e58ca
NC		 3924 }
3925 }
3926 else
3927 {
3928 /* Thumb to arm. */
c820be07
NC		 3929 if (sym_sec != NULL
3930 && sym_sec->owner != NULL
3931 && !INTERWORK_FLAG (sym_sec->owner))
3932 {
3933 (*_bfd_error_handler)
3934 (_("%B(%s): warning: interworking not enabled.\n"
3935 " first occurrence: %B: Thumb call to ARM"),
3936 sym_sec->owner, input_bfd, name);
3937 }
3938
0855e32b 3939 stub_type =
0e1862bb 3940 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3941 /* PIC stubs. */
0855e32b 3942 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 3943 /* TLS PIC stubs. */
0855e32b
NS		 3944 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
3945 : arm_stub_long_branch_v4t_thumb_tls_pic)
3946 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
3947 /* V5T PIC and above. */
3948 ? arm_stub_long_branch_any_arm_pic
3949 /* V4T PIC stub. */
3950 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 3951
3952 /* non-PIC stubs. */
0855e32b 3953 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 3954 /* V5T and above. */
3955 ? arm_stub_long_branch_any_any
3956 /* V4T. */
3957 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 3958
3959 /* Handle v4t short branches. */
fea2b4d6 3960 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 3961 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
3962 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 3963 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 3964 }
3965 }
3966 }
fe33d2fa
CL		 3967 else if (r_type == R_ARM_CALL
3968 || r_type == R_ARM_JUMP24
0855e32b
NS		 3969 || r_type == R_ARM_PLT32
3970 || r_type == R_ARM_TLS_CALL)
906e58ca 3971 {
35fc36a8 3972 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3973 {
3974 /* Arm to thumb. */
c820be07
NC		 3975
3976 if (sym_sec != NULL
3977 && sym_sec->owner != NULL
3978 && !INTERWORK_FLAG (sym_sec->owner))
3979 {
3980 (*_bfd_error_handler)
3981 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 3982 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 3983 sym_sec->owner, input_bfd, name);
3984 }
3985
3986 /* We have an extra 2-bytes reach because of
3987 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 3988 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
3989 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 3990 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 3991 || (r_type == R_ARM_JUMP24)
3992 || (r_type == R_ARM_PLT32))
906e58ca 3993 {
0e1862bb 3994 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3995 /* PIC stubs. */
ebe24dd4
CL		 3996 ? ((globals->use_blx)
3997 /* V5T and above. */
3998 ? arm_stub_long_branch_any_thumb_pic
3999 /* V4T stub. */
4000 : arm_stub_long_branch_v4t_arm_thumb_pic)
4001
c2b4a39d
CL		 4002 /* non-PIC stubs. */
4003 : ((globals->use_blx)
4004 /* V5T and above. */
4005 ? arm_stub_long_branch_any_any
4006 /* V4T. */
4007 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4008 }
4009 }
4010 else
4011 {
4012 /* Arm to arm. */
4013 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4014 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4015 {
0855e32b 4016 stub_type =
0e1862bb 4017 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4018 /* PIC stubs. */
0855e32b 4019 ? (r_type == R_ARM_TLS_CALL
6a631e86 4020 /* TLS PIC Stub. */
0855e32b 4021 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4022 : (globals->nacl_p
4023 ? arm_stub_long_branch_arm_nacl_pic
4024 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4025 /* non-PIC stubs. */
7a89b94e
NC		 4026 : (globals->nacl_p
4027 ? arm_stub_long_branch_arm_nacl
4028 : arm_stub_long_branch_any_any);
906e58ca
NC		 4029 }
4030 }
4031 }
4032
fe33d2fa
CL		 4033 /* If a stub is needed, record the actual destination type. */
4034 if (stub_type != arm_stub_none)
35fc36a8 4035 *actual_branch_type = branch_type;
fe33d2fa 4036
906e58ca
NC		 4037 return stub_type;
4038}
4039
4040/* Build a name for an entry in the stub hash table. */
4041
4042static char *
4043elf32_arm_stub_name (const asection *input_section,
4044 const asection *sym_sec,
4045 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4046 const Elf_Internal_Rela *rel,
4047 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4048{
4049 char *stub_name;
4050 bfd_size_type len;
4051
4052 if (hash)
4053 {
fe33d2fa 4054 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4055 stub_name = (char *) bfd_malloc (len);
906e58ca 4056 if (stub_name != NULL)
fe33d2fa 4057 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4058 input_section->id & 0xffffffff,
4059 hash->root.root.root.string,
fe33d2fa
CL		 4060 (int) rel->r_addend & 0xffffffff,
4061 (int) stub_type);
906e58ca
NC		 4062 }
4063 else
4064 {
fe33d2fa 4065 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4066 stub_name = (char *) bfd_malloc (len);
906e58ca 4067 if (stub_name != NULL)
fe33d2fa 4068 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4069 input_section->id & 0xffffffff,
4070 sym_sec->id & 0xffffffff,
0855e32b
NS		 4071 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4072 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4073 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4074 (int) rel->r_addend & 0xffffffff,
4075 (int) stub_type);
906e58ca
NC		 4076 }
4077
4078 return stub_name;
4079}
4080
4081/* Look up an entry in the stub hash. Stub entries are cached because
4082 creating the stub name takes a bit of time. */
4083
4084static struct elf32_arm_stub_hash_entry *
4085elf32_arm_get_stub_entry (const asection *input_section,
4086 const asection *sym_sec,
4087 struct elf_link_hash_entry *hash,
4088 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4089 struct elf32_arm_link_hash_table *htab,
4090 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4091{
4092 struct elf32_arm_stub_hash_entry *stub_entry;
4093 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4094 const asection *id_sec;
4095
4096 if ((input_section->flags & SEC_CODE) == 0)
4097 return NULL;
4098
4099 /* If this input section is part of a group of sections sharing one
4100 stub section, then use the id of the first section in the group.
4101 Stub names need to include a section id, as there may well be
4102 more than one stub used to reach say, printf, and we need to
4103 distinguish between them. */
4104 id_sec = htab->stub_group[input_section->id].link_sec;
4105
4106 if (h != NULL && h->stub_cache != NULL
4107 && h->stub_cache->h == h
fe33d2fa
CL		 4108 && h->stub_cache->id_sec == id_sec
4109 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4110 {
4111 stub_entry = h->stub_cache;
4112 }
4113 else
4114 {
4115 char *stub_name;
4116
fe33d2fa 4117 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4118 if (stub_name == NULL)
4119 return NULL;
4120
4121 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4122 stub_name, FALSE, FALSE);
4123 if (h != NULL)
4124 h->stub_cache = stub_entry;
4125
4126 free (stub_name);
4127 }
4128
4129 return stub_entry;
4130}
4131
48229727 4132/* Find or create a stub section. Returns a pointer to the stub section, and
b38cadfb 4133 the section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4134 LINK_SEC_P may be NULL. */
906e58ca 4135
48229727
JB		 4136static asection *
4137elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
4138 struct elf32_arm_link_hash_table *htab)
906e58ca
NC		 4139{
4140 asection *link_sec;
4141 asection *stub_sec;
906e58ca
NC		 4142
4143 link_sec = htab->stub_group[section->id].link_sec;
9553db3c 4144 BFD_ASSERT (link_sec != NULL);
906e58ca 4145 stub_sec = htab->stub_group[section->id].stub_sec;
9553db3c 4146
906e58ca
NC		 4147 if (stub_sec == NULL)
4148 {
4149 stub_sec = htab->stub_group[link_sec->id].stub_sec;
4150 if (stub_sec == NULL)
4151 {
4152 size_t namelen;
4153 bfd_size_type len;
4154 char *s_name;
4155
4156 namelen = strlen (link_sec->name);
4157 len = namelen + sizeof (STUB_SUFFIX);
21d799b5 4158 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
906e58ca
NC		 4159 if (s_name == NULL)
4160 return NULL;
4161
4162 memcpy (s_name, link_sec->name, namelen);
4163 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
7a89b94e
NC		 4164 stub_sec = (*htab->add_stub_section) (s_name, link_sec,
4165 htab->nacl_p ? 4 : 3);
906e58ca
NC		 4166 if (stub_sec == NULL)
4167 return NULL;
4168 htab->stub_group[link_sec->id].stub_sec = stub_sec;
4169 }
4170 htab->stub_group[section->id].stub_sec = stub_sec;
4171 }
b38cadfb 4172
48229727
JB		 4173 if (link_sec_p)
4174 *link_sec_p = link_sec;
b38cadfb 4175
48229727
JB		 4176 return stub_sec;
4177}
4178
4179/* Add a new stub entry to the stub hash. Not all fields of the new
4180 stub entry are initialised. */
4181
4182static struct elf32_arm_stub_hash_entry *
4183elf32_arm_add_stub (const char *stub_name,
4184 asection *section,
4185 struct elf32_arm_link_hash_table *htab)
4186{
4187 asection *link_sec;
4188 asection *stub_sec;
4189 struct elf32_arm_stub_hash_entry *stub_entry;
4190
4191 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab);
4192 if (stub_sec == NULL)
4193 return NULL;
906e58ca
NC		 4194
4195 /* Enter this entry into the linker stub hash table. */
4196 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4197 TRUE, FALSE);
4198 if (stub_entry == NULL)
4199 {
4200 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4201 section->owner,
4202 stub_name);
4203 return NULL;
4204 }
4205
4206 stub_entry->stub_sec = stub_sec;
4207 stub_entry->stub_offset = 0;
4208 stub_entry->id_sec = link_sec;
4209
906e58ca
NC		 4210 return stub_entry;
4211}
4212
4213/* Store an Arm insn into an output section not processed by
4214 elf32_arm_write_section. */
4215
4216static void
8029a119
NC		 4217put_arm_insn (struct elf32_arm_link_hash_table * htab,
4218 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4219{
4220 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4221 bfd_putl32 (val, ptr);
4222 else
4223 bfd_putb32 (val, ptr);
4224}
4225
4226/* Store a 16-bit Thumb insn into an output section not processed by
4227 elf32_arm_write_section. */
4228
4229static void
8029a119
NC		 4230put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4231 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4232{
4233 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4234 bfd_putl16 (val, ptr);
4235 else
4236 bfd_putb16 (val, ptr);
4237}
4238
a504d23a
LA		 4239/* Store a Thumb2 insn into an output section not processed by
4240 elf32_arm_write_section. */
4241
4242static void
4243put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
4244 bfd * output_bfd, bfd_vma val, void * ptr)
4245{
4246 /* T2 instructions are 16-bit streamed. */
4247 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4248 {
4249 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4250 bfd_putl16 ((val & 0xffff), ptr + 2);
4251 }
4252 else
4253 {
4254 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4255 bfd_putb16 ((val & 0xffff), ptr + 2);
4256 }
4257}
4258
0855e32b
NS		 4259/* If it's possible to change R_TYPE to a more efficient access
4260 model, return the new reloc type. */
4261
4262static unsigned
b38cadfb 4263elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4264 struct elf_link_hash_entry *h)
4265{
4266 int is_local = (h == NULL);
4267
0e1862bb
L		 4268 if (bfd_link_pic (info)
4269 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4270 return r_type;
4271
b38cadfb 4272 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4273 switch (r_type)
4274 {
4275 case R_ARM_TLS_GOTDESC:
4276 case R_ARM_TLS_CALL:
4277 case R_ARM_THM_TLS_CALL:
4278 case R_ARM_TLS_DESCSEQ:
4279 case R_ARM_THM_TLS_DESCSEQ:
4280 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4281 }
4282
4283 return r_type;
4284}
4285
48229727
JB		 4286static bfd_reloc_status_type elf32_arm_final_link_relocate
4287 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4288 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4289 const char *, unsigned char, enum arm_st_branch_type,
4290 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4291
4563a860
JB		 4292static unsigned int
4293arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4294{
4295 switch (stub_type)
4296 {
4297 case arm_stub_a8_veneer_b_cond:
4298 case arm_stub_a8_veneer_b:
4299 case arm_stub_a8_veneer_bl:
4300 return 2;
4301
4302 case arm_stub_long_branch_any_any:
4303 case arm_stub_long_branch_v4t_arm_thumb:
4304 case arm_stub_long_branch_thumb_only:
4305 case arm_stub_long_branch_v4t_thumb_thumb:
4306 case arm_stub_long_branch_v4t_thumb_arm:
4307 case arm_stub_short_branch_v4t_thumb_arm:
4308 case arm_stub_long_branch_any_arm_pic:
4309 case arm_stub_long_branch_any_thumb_pic:
4310 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4311 case arm_stub_long_branch_v4t_arm_thumb_pic:
4312 case arm_stub_long_branch_v4t_thumb_arm_pic:
4313 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4314 case arm_stub_long_branch_any_tls_pic:
4315 case arm_stub_long_branch_v4t_thumb_tls_pic:
4563a860
JB		 4316 case arm_stub_a8_veneer_blx:
4317 return 4;
b38cadfb 4318
7a89b94e
NC		 4319 case arm_stub_long_branch_arm_nacl:
4320 case arm_stub_long_branch_arm_nacl_pic:
4321 return 16;
4322
4563a860
JB		 4323 default:
4324 abort (); /* Should be unreachable. */
4325 }
4326}
4327
906e58ca
NC		 4328static bfd_boolean
4329arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4330 void * in_arg)
4331{
7a89b94e 4332#define MAXRELOCS 3
906e58ca 4333 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4334 struct elf32_arm_link_hash_table *globals;
906e58ca 4335 struct bfd_link_info *info;
906e58ca
NC		 4336 asection *stub_sec;
4337 bfd *stub_bfd;
906e58ca
NC		 4338 bfd_byte *loc;
4339 bfd_vma sym_value;
4340 int template_size;
4341 int size;
d3ce72d0 4342 const insn_sequence *template_sequence;
906e58ca 4343 int i;
48229727
JB		 4344 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4345 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4346 int nrelocs = 0;
906e58ca
NC		 4347
4348 /* Massage our args to the form they really have. */
4349 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4350 info = (struct bfd_link_info *) in_arg;
4351
4352 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4353 if (globals == NULL)
4354 return FALSE;
906e58ca 4355
906e58ca
NC		 4356 stub_sec = stub_entry->stub_sec;
4357
4dfe6ac6 4358 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4359 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4360 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4361 return TRUE;
fe33d2fa 4362
906e58ca
NC		 4363 /* Make a note of the offset within the stubs for this entry. */
4364 stub_entry->stub_offset = stub_sec->size;
4365 loc = stub_sec->contents + stub_entry->stub_offset;
4366
4367 stub_bfd = stub_sec->owner;
4368
906e58ca
NC		 4369 /* This is the address of the stub destination. */
4370 sym_value = (stub_entry->target_value
4371 + stub_entry->target_section->output_offset
4372 + stub_entry->target_section->output_section->vma);
4373
d3ce72d0 4374 template_sequence = stub_entry->stub_template;
461a49ca 4375 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4376
4377 size = 0;
461a49ca 4378 for (i = 0; i < template_size; i++)
906e58ca 4379 {
d3ce72d0 4380 switch (template_sequence[i].type)
461a49ca
DJ		 4381 {
4382 case THUMB16_TYPE:
48229727 4383 {
d3ce72d0
NC		 4384 bfd_vma data = (bfd_vma) template_sequence[i].data;
4385 if (template_sequence[i].reloc_addend != 0)
48229727 4386 {
99059e56
RM		 4387 /* We've borrowed the reloc_addend field to mean we should
4388 insert a condition code into this (Thumb-1 branch)
4389 instruction. See THUMB16_BCOND_INSN. */
4390 BFD_ASSERT ((data & 0xff00) == 0xd000);
4391 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4392 }
fe33d2fa 4393 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4394 size += 2;
4395 }
461a49ca 4396 break;
906e58ca 4397
48229727 4398 case THUMB32_TYPE:
fe33d2fa
CL		 4399 bfd_put_16 (stub_bfd,
4400 (template_sequence[i].data >> 16) & 0xffff,
4401 loc + size);
4402 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4403 loc + size + 2);
99059e56
RM		 4404 if (template_sequence[i].r_type != R_ARM_NONE)
4405 {
4406 stub_reloc_idx[nrelocs] = i;
4407 stub_reloc_offset[nrelocs++] = size;
4408 }
4409 size += 4;
4410 break;
48229727 4411
461a49ca 4412 case ARM_TYPE:
fe33d2fa
CL		 4413 bfd_put_32 (stub_bfd, template_sequence[i].data,
4414 loc + size);
461a49ca
DJ		 4415 /* Handle cases where the target is encoded within the
4416 instruction. */
d3ce72d0 4417 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4418 {
48229727
JB		 4419 stub_reloc_idx[nrelocs] = i;
4420 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4421 }
4422 size += 4;
4423 break;
4424
4425 case DATA_TYPE:
d3ce72d0 4426 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4427 stub_reloc_idx[nrelocs] = i;
4428 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4429 size += 4;
4430 break;
4431
4432 default:
4433 BFD_FAIL ();
4434 return FALSE;
4435 }
906e58ca 4436 }
461a49ca 4437
906e58ca
NC		 4438 stub_sec->size += size;
4439
461a49ca
DJ		 4440 /* Stub size has already been computed in arm_size_one_stub. Check
4441 consistency. */
4442 BFD_ASSERT (size == stub_entry->stub_size);
4443
906e58ca 4444 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4445 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4446 sym_value |= 1;
4447
48229727
JB		 4448 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4449 in each stub. */
4450 BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS);
c820be07 4451
48229727 4452 for (i = 0; i < nrelocs; i++)
d3ce72d0
NC		 4453 if (template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_JUMP24
4454 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_JUMP19
4455 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_CALL
4456 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_XPC22)
48229727
JB		 4457 {
4458 Elf_Internal_Rela rel;
4459 bfd_boolean unresolved_reloc;
4460 char *error_message;
35fc36a8
RS		 4461 enum arm_st_branch_type branch_type
4462 = (template_sequence[stub_reloc_idx[i]].r_type != R_ARM_THM_XPC22
4463 ? ST_BRANCH_TO_THUMB : ST_BRANCH_TO_ARM);
48229727
JB		 4464 bfd_vma points_to = sym_value + stub_entry->target_addend;
4465
4466 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
d3ce72d0 4467 rel.r_info = ELF32_R_INFO (0,
99059e56 4468 template_sequence[stub_reloc_idx[i]].r_type);
d3ce72d0 4469 rel.r_addend = template_sequence[stub_reloc_idx[i]].reloc_addend;
48229727
JB		 4470
4471 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4472 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4473 template should refer back to the instruction after the original
4474 branch. */
4475 points_to = sym_value;
4476
33c6a8fc
JB		 4477 /* There may be unintended consequences if this is not true. */
4478 BFD_ASSERT (stub_entry->h == NULL);
4479
48229727
JB		 4480 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4481 properly. We should probably use this function unconditionally,
4482 rather than only for certain relocations listed in the enclosing
4483 conditional, for the sake of consistency. */
4484 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
d3ce72d0 4485 (template_sequence[stub_reloc_idx[i]].r_type),
48229727 4486 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
34e77a92
RS		 4487 points_to, info, stub_entry->target_section, "", STT_FUNC,
4488 branch_type, (struct elf_link_hash_entry *) stub_entry->h,
4489 &unresolved_reloc, &error_message);
48229727
JB		 4490 }
4491 else
4492 {
fe33d2fa
CL		 4493 Elf_Internal_Rela rel;
4494 bfd_boolean unresolved_reloc;
4495 char *error_message;
4496 bfd_vma points_to = sym_value + stub_entry->target_addend
4497 + template_sequence[stub_reloc_idx[i]].reloc_addend;
4498
4499 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4500 rel.r_info = ELF32_R_INFO (0,
99059e56 4501 template_sequence[stub_reloc_idx[i]].r_type);
fe33d2fa
CL		 4502 rel.r_addend = 0;
4503
4504 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4505 (template_sequence[stub_reloc_idx[i]].r_type),
4506 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
34e77a92 4507 points_to, info, stub_entry->target_section, "", STT_FUNC,
35fc36a8 4508 stub_entry->branch_type,
fe33d2fa
CL		 4509 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4510 &error_message);
48229727 4511 }
906e58ca
NC		 4512
4513 return TRUE;
48229727 4514#undef MAXRELOCS
906e58ca
NC		 4515}
4516
48229727
JB		 4517/* Calculate the template, template size and instruction size for a stub.
4518 Return value is the instruction size. */
906e58ca 4519
48229727
JB		 4520static unsigned int
4521find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4522 const insn_sequence **stub_template,
4523 int *stub_template_size)
906e58ca 4524{
d3ce72d0 4525 const insn_sequence *template_sequence = NULL;
48229727
JB		 4526 int template_size = 0, i;
4527 unsigned int size;
906e58ca 4528
d3ce72d0 4529 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4530 if (stub_template)
4531 *stub_template = template_sequence;
4532
48229727 4533 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4534 if (stub_template_size)
4535 *stub_template_size = template_size;
906e58ca
NC		 4536
4537 size = 0;
461a49ca
DJ		 4538 for (i = 0; i < template_size; i++)
4539 {
d3ce72d0 4540 switch (template_sequence[i].type)
461a49ca
DJ		 4541 {
4542 case THUMB16_TYPE:
4543 size += 2;
4544 break;
4545
4546 case ARM_TYPE:
48229727 4547 case THUMB32_TYPE:
461a49ca
DJ		 4548 case DATA_TYPE:
4549 size += 4;
4550 break;
4551
4552 default:
4553 BFD_FAIL ();
2a229407 4554 return 0;
461a49ca
DJ		 4555 }
4556 }
4557
48229727
JB		 4558 return size;
4559}
4560
4561/* As above, but don't actually build the stub. Just bump offset so
4562 we know stub section sizes. */
4563
4564static bfd_boolean
4565arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4566 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4567{
4568 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4569 const insn_sequence *template_sequence;
48229727
JB		 4570 int template_size, size;
4571
4572 /* Massage our args to the form they really have. */
4573 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4574
4575 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4576 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4577
d3ce72d0 4578 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4579 &template_size);
4580
461a49ca 4581 stub_entry->stub_size = size;
d3ce72d0 4582 stub_entry->stub_template = template_sequence;
461a49ca
DJ		 4583 stub_entry->stub_template_size = template_size;
4584
906e58ca
NC		 4585 size = (size + 7) & ~7;
4586 stub_entry->stub_sec->size += size;
461a49ca 4587
906e58ca
NC		 4588 return TRUE;
4589}
4590
4591/* External entry points for sizing and building linker stubs. */
4592
4593/* Set up various things so that we can make a list of input sections
4594 for each output section included in the link. Returns -1 on error,
4595 0 when no stubs will be needed, and 1 on success. */
4596
4597int
4598elf32_arm_setup_section_lists (bfd *output_bfd,
4599 struct bfd_link_info *info)
4600{
4601 bfd *input_bfd;
4602 unsigned int bfd_count;
7292b3ac 4603 unsigned int top_id, top_index;
906e58ca
NC		 4604 asection *section;
4605 asection **input_list, **list;
4606 bfd_size_type amt;
4607 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4608
4dfe6ac6
NC		 4609 if (htab == NULL)
4610 return 0;
906e58ca
NC		 4611 if (! is_elf_hash_table (htab))
4612 return 0;
4613
4614 /* Count the number of input BFDs and find the top input section id. */
4615 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4616 input_bfd != NULL;
c72f2fb2 4617 input_bfd = input_bfd->link.next)
906e58ca
NC		 4618 {
4619 bfd_count += 1;
4620 for (section = input_bfd->sections;
4621 section != NULL;
4622 section = section->next)
4623 {
4624 if (top_id < section->id)
4625 top_id = section->id;
4626 }
4627 }
4628 htab->bfd_count = bfd_count;
4629
4630 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4631 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4632 if (htab->stub_group == NULL)
4633 return -1;
fe33d2fa 4634 htab->top_id = top_id;
906e58ca
NC		 4635
4636 /* We can't use output_bfd->section_count here to find the top output
4637 section index as some sections may have been removed, and
4638 _bfd_strip_section_from_output doesn't renumber the indices. */
4639 for (section = output_bfd->sections, top_index = 0;
4640 section != NULL;
4641 section = section->next)
4642 {
4643 if (top_index < section->index)
4644 top_index = section->index;
4645 }
4646
4647 htab->top_index = top_index;
4648 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4649 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4650 htab->input_list = input_list;
4651 if (input_list == NULL)
4652 return -1;
4653
4654 /* For sections we aren't interested in, mark their entries with a
4655 value we can check later. */
4656 list = input_list + top_index;
4657 do
4658 *list = bfd_abs_section_ptr;
4659 while (list-- != input_list);
4660
4661 for (section = output_bfd->sections;
4662 section != NULL;
4663 section = section->next)
4664 {
4665 if ((section->flags & SEC_CODE) != 0)
4666 input_list[section->index] = NULL;
4667 }
4668
4669 return 1;
4670}
4671
4672/* The linker repeatedly calls this function for each input section,
4673 in the order that input sections are linked into output sections.
4674 Build lists of input sections to determine groupings between which
4675 we may insert linker stubs. */
4676
4677void
4678elf32_arm_next_input_section (struct bfd_link_info *info,
4679 asection *isec)
4680{
4681 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4682
4dfe6ac6
NC		 4683 if (htab == NULL)
4684 return;
4685
906e58ca
NC		 4686 if (isec->output_section->index <= htab->top_index)
4687 {
4688 asection **list = htab->input_list + isec->output_section->index;
4689
a7470592 4690 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 4691 {
4692 /* Steal the link_sec pointer for our list. */
4693#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4694 /* This happens to make the list in reverse order,
07d72278 4695 which we reverse later. */
906e58ca
NC		 4696 PREV_SEC (isec) = *list;
4697 *list = isec;
4698 }
4699 }
4700}
4701
4702/* See whether we can group stub sections together. Grouping stub
4703 sections may result in fewer stubs. More importantly, we need to
07d72278 4704 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 4705 .fini output sections respectively, because glibc splits the
4706 _init and _fini functions into multiple parts. Putting a stub in
4707 the middle of a function is not a good idea. */
4708
4709static void
4710group_sections (struct elf32_arm_link_hash_table *htab,
4711 bfd_size_type stub_group_size,
07d72278 4712 bfd_boolean stubs_always_after_branch)
906e58ca 4713{
07d72278 4714 asection **list = htab->input_list;
906e58ca
NC		 4715
4716 do
4717 {
4718 asection *tail = *list;
07d72278 4719 asection *head;
906e58ca
NC		 4720
4721 if (tail == bfd_abs_section_ptr)
4722 continue;
4723
07d72278
DJ		 4724 /* Reverse the list: we must avoid placing stubs at the
4725 beginning of the section because the beginning of the text
4726 section may be required for an interrupt vector in bare metal
4727 code. */
4728#define NEXT_SEC PREV_SEC
e780aef2
CL		 4729 head = NULL;
4730 while (tail != NULL)
99059e56
RM		 4731 {
4732 /* Pop from tail. */
4733 asection *item = tail;
4734 tail = PREV_SEC (item);
e780aef2 4735
99059e56
RM		 4736 /* Push on head. */
4737 NEXT_SEC (item) = head;
4738 head = item;
4739 }
07d72278
DJ		 4740
4741 while (head != NULL)
906e58ca
NC		 4742 {
4743 asection *curr;
07d72278 4744 asection *next;
e780aef2
CL		 4745 bfd_vma stub_group_start = head->output_offset;
4746 bfd_vma end_of_next;
906e58ca 4747
07d72278 4748 curr = head;
e780aef2 4749 while (NEXT_SEC (curr) != NULL)
8cd931b7 4750 {
e780aef2
CL		 4751 next = NEXT_SEC (curr);
4752 end_of_next = next->output_offset + next->size;
4753 if (end_of_next - stub_group_start >= stub_group_size)
4754 /* End of NEXT is too far from start, so stop. */
8cd931b7 4755 break;
e780aef2
CL		 4756 /* Add NEXT to the group. */
4757 curr = next;
8cd931b7 4758 }
906e58ca 4759
07d72278 4760 /* OK, the size from the start to the start of CURR is less
906e58ca 4761 than stub_group_size and thus can be handled by one stub
07d72278 4762 section. (Or the head section is itself larger than
906e58ca
NC		 4763 stub_group_size, in which case we may be toast.)
4764 We should really be keeping track of the total size of
4765 stubs added here, as stubs contribute to the final output
7fb9f789 4766 section size. */
906e58ca
NC		 4767 do
4768 {
07d72278 4769 next = NEXT_SEC (head);
906e58ca 4770 /* Set up this stub group. */
07d72278 4771 htab->stub_group[head->id].link_sec = curr;
906e58ca 4772 }
07d72278 4773 while (head != curr && (head = next) != NULL);
906e58ca
NC		 4774
4775 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 4776 bytes after the stub section can be handled by it too. */
4777 if (!stubs_always_after_branch)
906e58ca 4778 {
e780aef2
CL		 4779 stub_group_start = curr->output_offset + curr->size;
4780
8cd931b7 4781 while (next != NULL)
906e58ca 4782 {
e780aef2
CL		 4783 end_of_next = next->output_offset + next->size;
4784 if (end_of_next - stub_group_start >= stub_group_size)
4785 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 4786 break;
e780aef2 4787 /* Add NEXT to the stub group. */
07d72278
DJ		 4788 head = next;
4789 next = NEXT_SEC (head);
4790 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 4791 }
4792 }
07d72278 4793 head = next;
906e58ca
NC		 4794 }
4795 }
07d72278 4796 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 4797
4798 free (htab->input_list);
4799#undef PREV_SEC
07d72278 4800#undef NEXT_SEC
906e58ca
NC		 4801}
4802
48229727
JB		 4803/* Comparison function for sorting/searching relocations relating to Cortex-A8
4804 erratum fix. */
4805
4806static int
4807a8_reloc_compare (const void *a, const void *b)
4808{
21d799b5
NC		 4809 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
4810 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 4811
4812 if (ra->from < rb->from)
4813 return -1;
4814 else if (ra->from > rb->from)
4815 return 1;
4816 else
4817 return 0;
4818}
4819
4820static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
4821 const char *, char **);
4822
4823/* Helper function to scan code for sequences which might trigger the Cortex-A8
4824 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 4825 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 4826 otherwise. */
4827
81694485
NC		 4828static bfd_boolean
4829cortex_a8_erratum_scan (bfd *input_bfd,
4830 struct bfd_link_info *info,
48229727
JB		 4831 struct a8_erratum_fix **a8_fixes_p,
4832 unsigned int *num_a8_fixes_p,
4833 unsigned int *a8_fix_table_size_p,
4834 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 4835 unsigned int num_a8_relocs,
4836 unsigned prev_num_a8_fixes,
4837 bfd_boolean *stub_changed_p)
48229727
JB		 4838{
4839 asection *section;
4840 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4841 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
4842 unsigned int num_a8_fixes = *num_a8_fixes_p;
4843 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
4844
4dfe6ac6
NC		 4845 if (htab == NULL)
4846 return FALSE;
4847
48229727
JB		 4848 for (section = input_bfd->sections;
4849 section != NULL;
4850 section = section->next)
4851 {
4852 bfd_byte *contents = NULL;
4853 struct _arm_elf_section_data *sec_data;
4854 unsigned int span;
4855 bfd_vma base_vma;
4856
4857 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 4858 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
4859 || (section->flags & SEC_EXCLUDE) != 0
4860 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
4861 || (section->output_section == bfd_abs_section_ptr))
4862 continue;
48229727
JB		 4863
4864 base_vma = section->output_section->vma + section->output_offset;
4865
4866 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 4867 contents = elf_section_data (section)->this_hdr.contents;
48229727 4868 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 4869 return TRUE;
48229727
JB		 4870
4871 sec_data = elf32_arm_section_data (section);
4872
4873 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 4874 {
4875 unsigned int span_start = sec_data->map[span].vma;
4876 unsigned int span_end = (span == sec_data->mapcount - 1)
4877 ? section->size : sec_data->map[span + 1].vma;
4878 unsigned int i;
4879 char span_type = sec_data->map[span].type;
4880 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
4881
4882 if (span_type != 't')
4883 continue;
4884
4885 /* Span is entirely within a single 4KB region: skip scanning. */
4886 if (((base_vma + span_start) & ~0xfff)
48229727 4887 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 4888 continue;
4889
4890 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4891
4892 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4893 * The branch target is in the same 4KB region as the
4894 first half of the branch.
4895 * The instruction before the branch is a 32-bit
4896 length non-branch instruction. */
4897 for (i = span_start; i < span_end;)
4898 {
4899 unsigned int insn = bfd_getl16 (&contents[i]);
4900 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 4901 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
4902
99059e56
RM		 4903 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
4904 insn_32bit = TRUE;
48229727
JB		 4905
4906 if (insn_32bit)
99059e56
RM		 4907 {
4908 /* Load the rest of the insn (in manual-friendly order). */
4909 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
4910
4911 /* Encoding T4: B<c>.W. */
4912 is_b = (insn & 0xf800d000) == 0xf0009000;
4913 /* Encoding T1: BL<c>.W. */
4914 is_bl = (insn & 0xf800d000) == 0xf000d000;
4915 /* Encoding T2: BLX<c>.W. */
4916 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 4917 /* Encoding T3: B<c>.W (not permitted in IT block). */
4918 is_bcc = (insn & 0xf800d000) == 0xf0008000
4919 && (insn & 0x07f00000) != 0x03800000;
4920 }
4921
4922 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 4923
99059e56 4924 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 4925 && insn_32bit
4926 && is_32bit_branch
4927 && last_was_32bit
4928 && ! last_was_branch)
99059e56
RM		 4929 {
4930 bfd_signed_vma offset = 0;
4931 bfd_boolean force_target_arm = FALSE;
48229727 4932 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 4933 bfd_vma target;
4934 enum elf32_arm_stub_type stub_type = arm_stub_none;
4935 struct a8_erratum_reloc key, *found;
4936 bfd_boolean use_plt = FALSE;
48229727 4937
99059e56
RM		 4938 key.from = base_vma + i;
4939 found = (struct a8_erratum_reloc *)
4940 bsearch (&key, a8_relocs, num_a8_relocs,
4941 sizeof (struct a8_erratum_reloc),
4942 &a8_reloc_compare);
48229727
JB		 4943
4944 if (found)
4945 {
4946 char *error_message = NULL;
4947 struct elf_link_hash_entry *entry;
4948
4949 /* We don't care about the error returned from this
99059e56 4950 function, only if there is glue or not. */
48229727
JB		 4951 entry = find_thumb_glue (info, found->sym_name,
4952 &error_message);
4953
4954 if (entry)
4955 found->non_a8_stub = TRUE;
4956
92750f34 4957 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 4958 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 4959 && found->hash->root.plt.offset != (bfd_vma) -1)
4960 use_plt = TRUE;
4961
4962 if (found->r_type == R_ARM_THM_CALL)
4963 {
35fc36a8
RS		 4964 if (found->branch_type == ST_BRANCH_TO_ARM
4965 || use_plt)
92750f34
DJ		 4966 force_target_arm = TRUE;
4967 else
4968 force_target_thumb = TRUE;
4969 }
48229727
JB		 4970 }
4971
99059e56 4972 /* Check if we have an offending branch instruction. */
48229727
JB		 4973
4974 if (found && found->non_a8_stub)
4975 /* We've already made a stub for this instruction, e.g.
4976 it's a long branch or a Thumb->ARM stub. Assume that
4977 stub will suffice to work around the A8 erratum (see
4978 setting of always_after_branch above). */
4979 ;
99059e56
RM		 4980 else if (is_bcc)
4981 {
4982 offset = (insn & 0x7ff) << 1;
4983 offset |= (insn & 0x3f0000) >> 4;
4984 offset |= (insn & 0x2000) ? 0x40000 : 0;
4985 offset |= (insn & 0x800) ? 0x80000 : 0;
4986 offset |= (insn & 0x4000000) ? 0x100000 : 0;
4987 if (offset & 0x100000)
4988 offset |= ~ ((bfd_signed_vma) 0xfffff);
4989 stub_type = arm_stub_a8_veneer_b_cond;
4990 }
4991 else if (is_b || is_bl || is_blx)
4992 {
4993 int s = (insn & 0x4000000) != 0;
4994 int j1 = (insn & 0x2000) != 0;
4995 int j2 = (insn & 0x800) != 0;
4996 int i1 = !(j1 ^ s);
4997 int i2 = !(j2 ^ s);
4998
4999 offset = (insn & 0x7ff) << 1;
5000 offset |= (insn & 0x3ff0000) >> 4;
5001 offset |= i2 << 22;
5002 offset |= i1 << 23;
5003 offset |= s << 24;
5004 if (offset & 0x1000000)
5005 offset |= ~ ((bfd_signed_vma) 0xffffff);
5006
5007 if (is_blx)
5008 offset &= ~ ((bfd_signed_vma) 3);
5009
5010 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5011 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5012 }
5013
5014 if (stub_type != arm_stub_none)
5015 {
5016 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5017
5018 /* The original instruction is a BL, but the target is
99059e56 5019 an ARM instruction. If we were not making a stub,
48229727
JB		 5020 the BL would have been converted to a BLX. Use the
5021 BLX stub instead in that case. */
5022 if (htab->use_blx && force_target_arm
5023 && stub_type == arm_stub_a8_veneer_bl)
5024 {
5025 stub_type = arm_stub_a8_veneer_blx;
5026 is_blx = TRUE;
5027 is_bl = FALSE;
5028 }
5029 /* Conversely, if the original instruction was
5030 BLX but the target is Thumb mode, use the BL
5031 stub. */
5032 else if (force_target_thumb
5033 && stub_type == arm_stub_a8_veneer_blx)
5034 {
5035 stub_type = arm_stub_a8_veneer_bl;
5036 is_blx = FALSE;
5037 is_bl = TRUE;
5038 }
5039
99059e56
RM		 5040 if (is_blx)
5041 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5042
99059e56
RM		 5043 /* If we found a relocation, use the proper destination,
5044 not the offset in the (unrelocated) instruction.
48229727
JB		 5045 Note this is always done if we switched the stub type
5046 above. */
99059e56
RM		 5047 if (found)
5048 offset =
81694485 5049 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5050
99059e56
RM		 5051 /* If the stub will use a Thumb-mode branch to a
5052 PLT target, redirect it to the preceding Thumb
5053 entry point. */
5054 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5055 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5056
99059e56 5057 target = pc_for_insn + offset;
48229727 5058
99059e56
RM		 5059 /* The BLX stub is ARM-mode code. Adjust the offset to
5060 take the different PC value (+8 instead of +4) into
48229727 5061 account. */
99059e56
RM		 5062 if (stub_type == arm_stub_a8_veneer_blx)
5063 offset += 4;
5064
5065 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5066 {
5067 char *stub_name = NULL;
5068
5069 if (num_a8_fixes == a8_fix_table_size)
5070 {
5071 a8_fix_table_size *= 2;
5072 a8_fixes = (struct a8_erratum_fix *)
5073 bfd_realloc (a8_fixes,
5074 sizeof (struct a8_erratum_fix)
5075 * a8_fix_table_size);
5076 }
48229727 5077
eb7c4339
NS		 5078 if (num_a8_fixes < prev_num_a8_fixes)
5079 {
5080 /* If we're doing a subsequent scan,
5081 check if we've found the same fix as
5082 before, and try and reuse the stub
5083 name. */
5084 stub_name = a8_fixes[num_a8_fixes].stub_name;
5085 if ((a8_fixes[num_a8_fixes].section != section)
5086 || (a8_fixes[num_a8_fixes].offset != i))
5087 {
5088 free (stub_name);
5089 stub_name = NULL;
5090 *stub_changed_p = TRUE;
5091 }
5092 }
5093
5094 if (!stub_name)
5095 {
21d799b5 5096 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5097 if (stub_name != NULL)
5098 sprintf (stub_name, "%x:%x", section->id, i);
5099 }
48229727 5100
99059e56
RM		 5101 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5102 a8_fixes[num_a8_fixes].section = section;
5103 a8_fixes[num_a8_fixes].offset = i;
5104 a8_fixes[num_a8_fixes].addend = offset;
5105 a8_fixes[num_a8_fixes].orig_insn = insn;
5106 a8_fixes[num_a8_fixes].stub_name = stub_name;
5107 a8_fixes[num_a8_fixes].stub_type = stub_type;
5108 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5109 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5110
99059e56
RM		 5111 num_a8_fixes++;
5112 }
5113 }
5114 }
48229727 5115
99059e56
RM		 5116 i += insn_32bit ? 4 : 2;
5117 last_was_32bit = insn_32bit;
48229727 5118 last_was_branch = is_32bit_branch;
99059e56
RM		 5119 }
5120 }
48229727
JB		 5121
5122 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5123 free (contents);
48229727 5124 }
fe33d2fa 5125
48229727
JB		 5126 *a8_fixes_p = a8_fixes;
5127 *num_a8_fixes_p = num_a8_fixes;
5128 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5129
81694485 5130 return FALSE;
48229727
JB		 5131}
5132
906e58ca
NC		 5133/* Determine and set the size of the stub section for a final link.
5134
5135 The basic idea here is to examine all the relocations looking for
5136 PC-relative calls to a target that is unreachable with a "bl"
5137 instruction. */
5138
5139bfd_boolean
5140elf32_arm_size_stubs (bfd *output_bfd,
5141 bfd *stub_bfd,
5142 struct bfd_link_info *info,
5143 bfd_signed_vma group_size,
7a89b94e
NC		 5144 asection * (*add_stub_section) (const char *, asection *,
5145 unsigned int),
906e58ca
NC		 5146 void (*layout_sections_again) (void))
5147{
5148 bfd_size_type stub_group_size;
07d72278 5149 bfd_boolean stubs_always_after_branch;
906e58ca 5150 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 5151 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 5152 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 5153 struct a8_erratum_reloc *a8_relocs = NULL;
5154 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
5155
4dfe6ac6
NC		 5156 if (htab == NULL)
5157 return FALSE;
5158
48229727
JB		 5159 if (htab->fix_cortex_a8)
5160 {
21d799b5 5161 a8_fixes = (struct a8_erratum_fix *)
99059e56 5162 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 5163 a8_relocs = (struct a8_erratum_reloc *)
99059e56 5164 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 5165 }
906e58ca
NC		 5166
5167 /* Propagate mach to stub bfd, because it may not have been
5168 finalized when we created stub_bfd. */
5169 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
5170 bfd_get_mach (output_bfd));
5171
5172 /* Stash our params away. */
5173 htab->stub_bfd = stub_bfd;
5174 htab->add_stub_section = add_stub_section;
5175 htab->layout_sections_again = layout_sections_again;
07d72278 5176 stubs_always_after_branch = group_size < 0;
48229727
JB		 5177
5178 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5179 as the first half of a 32-bit branch straddling two 4K pages. This is a
5180 crude way of enforcing that. */
5181 if (htab->fix_cortex_a8)
5182 stubs_always_after_branch = 1;
5183
906e58ca
NC		 5184 if (group_size < 0)
5185 stub_group_size = -group_size;
5186 else
5187 stub_group_size = group_size;
5188
5189 if (stub_group_size == 1)
5190 {
5191 /* Default values. */
5192 /* Thumb branch range is +-4MB has to be used as the default
5193 maximum size (a given section can contain both ARM and Thumb
5194 code, so the worst case has to be taken into account).
5195
5196 This value is 24K less than that, which allows for 2025
5197 12-byte stubs. If we exceed that, then we will fail to link.
5198 The user will have to relink with an explicit group size
5199 option. */
5200 stub_group_size = 4170000;
5201 }
5202
07d72278 5203 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 5204
3ae046cc
NS		 5205 /* If we're applying the cortex A8 fix, we need to determine the
5206 program header size now, because we cannot change it later --
5207 that could alter section placements. Notice the A8 erratum fix
5208 ends up requiring the section addresses to remain unchanged
5209 modulo the page size. That's something we cannot represent
5210 inside BFD, and we don't want to force the section alignment to
5211 be the page size. */
5212 if (htab->fix_cortex_a8)
5213 (*htab->layout_sections_again) ();
5214
906e58ca
NC		 5215 while (1)
5216 {
5217 bfd *input_bfd;
5218 unsigned int bfd_indx;
5219 asection *stub_sec;
eb7c4339
NS		 5220 bfd_boolean stub_changed = FALSE;
5221 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 5222
48229727 5223 num_a8_fixes = 0;
906e58ca
NC		 5224 for (input_bfd = info->input_bfds, bfd_indx = 0;
5225 input_bfd != NULL;
c72f2fb2 5226 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 5227 {
5228 Elf_Internal_Shdr *symtab_hdr;
5229 asection *section;
5230 Elf_Internal_Sym *local_syms = NULL;
5231
99059e56
RM		 5232 if (!is_arm_elf (input_bfd))
5233 continue;
adbcc655 5234
48229727
JB		 5235 num_a8_relocs = 0;
5236
906e58ca
NC		 5237 /* We'll need the symbol table in a second. */
5238 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5239 if (symtab_hdr->sh_info == 0)
5240 continue;
5241
5242 /* Walk over each section attached to the input bfd. */
5243 for (section = input_bfd->sections;
5244 section != NULL;
5245 section = section->next)
5246 {
5247 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
5248
5249 /* If there aren't any relocs, then there's nothing more
5250 to do. */
5251 if ((section->flags & SEC_RELOC) == 0
5252 || section->reloc_count == 0
5253 || (section->flags & SEC_CODE) == 0)
5254 continue;
5255
5256 /* If this section is a link-once section that will be
5257 discarded, then don't create any stubs. */
5258 if (section->output_section == NULL
5259 || section->output_section->owner != output_bfd)
5260 continue;
5261
5262 /* Get the relocs. */
5263 internal_relocs
5264 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
5265 NULL, info->keep_memory);
5266 if (internal_relocs == NULL)
5267 goto error_ret_free_local;
5268
5269 /* Now examine each relocation. */
5270 irela = internal_relocs;
5271 irelaend = irela + section->reloc_count;
5272 for (; irela < irelaend; irela++)
5273 {
5274 unsigned int r_type, r_indx;
5275 enum elf32_arm_stub_type stub_type;
5276 struct elf32_arm_stub_hash_entry *stub_entry;
5277 asection *sym_sec;
5278 bfd_vma sym_value;
5279 bfd_vma destination;
5280 struct elf32_arm_link_hash_entry *hash;
7413f23f 5281 const char *sym_name;
906e58ca
NC		 5282 char *stub_name;
5283 const asection *id_sec;
34e77a92 5284 unsigned char st_type;
35fc36a8 5285 enum arm_st_branch_type branch_type;
48229727 5286 bfd_boolean created_stub = FALSE;
906e58ca
NC		 5287
5288 r_type = ELF32_R_TYPE (irela->r_info);
5289 r_indx = ELF32_R_SYM (irela->r_info);
5290
5291 if (r_type >= (unsigned int) R_ARM_max)
5292 {
5293 bfd_set_error (bfd_error_bad_value);
5294 error_ret_free_internal:
5295 if (elf_section_data (section)->relocs == NULL)
5296 free (internal_relocs);
15dd01b1
TP		 5297 /* Fall through. */
5298 error_ret_free_local:
5299 if (local_syms != NULL
5300 && (symtab_hdr->contents
5301 != (unsigned char *) local_syms))
5302 free (local_syms);
5303 return FALSE;
906e58ca 5304 }
b38cadfb 5305
0855e32b
NS		 5306 hash = NULL;
5307 if (r_indx >= symtab_hdr->sh_info)
5308 hash = elf32_arm_hash_entry
5309 (elf_sym_hashes (input_bfd)
5310 [r_indx - symtab_hdr->sh_info]);
b38cadfb 5311
0855e32b
NS		 5312 /* Only look for stubs on branch instructions, or
5313 non-relaxed TLSCALL */
906e58ca 5314 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 5315 && (r_type != (unsigned int) R_ARM_THM_CALL)
5316 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 5317 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
5318 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 5319 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 5320 && (r_type != (unsigned int) R_ARM_PLT32)
5321 && !((r_type == (unsigned int) R_ARM_TLS_CALL
5322 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5323 && r_type == elf32_arm_tls_transition
5324 (info, r_type, &hash->root)
5325 && ((hash ? hash->tls_type
5326 : (elf32_arm_local_got_tls_type
5327 (input_bfd)[r_indx]))
5328 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 5329 continue;
5330
5331 /* Now determine the call target, its name, value,
5332 section. */
5333 sym_sec = NULL;
5334 sym_value = 0;
5335 destination = 0;
7413f23f 5336 sym_name = NULL;
b38cadfb 5337
0855e32b
NS		 5338 if (r_type == (unsigned int) R_ARM_TLS_CALL
5339 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5340 {
5341 /* A non-relaxed TLS call. The target is the
5342 plt-resident trampoline and nothing to do
5343 with the symbol. */
5344 BFD_ASSERT (htab->tls_trampoline > 0);
5345 sym_sec = htab->root.splt;
5346 sym_value = htab->tls_trampoline;
5347 hash = 0;
34e77a92 5348 st_type = STT_FUNC;
35fc36a8 5349 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 5350 }
5351 else if (!hash)
906e58ca
NC		 5352 {
5353 /* It's a local symbol. */
5354 Elf_Internal_Sym *sym;
906e58ca
NC		 5355
5356 if (local_syms == NULL)
5357 {
5358 local_syms
5359 = (Elf_Internal_Sym *) symtab_hdr->contents;
5360 if (local_syms == NULL)
5361 local_syms
5362 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5363 symtab_hdr->sh_info, 0,
5364 NULL, NULL, NULL);
5365 if (local_syms == NULL)
5366 goto error_ret_free_internal;
5367 }
5368
5369 sym = local_syms + r_indx;
f6d250ce
TS		 5370 if (sym->st_shndx == SHN_UNDEF)
5371 sym_sec = bfd_und_section_ptr;
5372 else if (sym->st_shndx == SHN_ABS)
5373 sym_sec = bfd_abs_section_ptr;
5374 else if (sym->st_shndx == SHN_COMMON)
5375 sym_sec = bfd_com_section_ptr;
5376 else
5377 sym_sec =
5378 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
5379
ffcb4889
NS		 5380 if (!sym_sec)
5381 /* This is an undefined symbol. It can never
6a631e86 5382 be resolved. */
ffcb4889 5383 continue;
fe33d2fa 5384
906e58ca
NC		 5385 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
5386 sym_value = sym->st_value;
5387 destination = (sym_value + irela->r_addend
5388 + sym_sec->output_offset
5389 + sym_sec->output_section->vma);
34e77a92 5390 st_type = ELF_ST_TYPE (sym->st_info);
35fc36a8 5391 branch_type = ARM_SYM_BRANCH_TYPE (sym);
7413f23f
DJ		 5392 sym_name
5393 = bfd_elf_string_from_elf_section (input_bfd,
5394 symtab_hdr->sh_link,
5395 sym->st_name);
906e58ca
NC		 5396 }
5397 else
5398 {
5399 /* It's an external symbol. */
906e58ca
NC		 5400 while (hash->root.root.type == bfd_link_hash_indirect
5401 || hash->root.root.type == bfd_link_hash_warning)
5402 hash = ((struct elf32_arm_link_hash_entry *)
5403 hash->root.root.u.i.link);
5404
5405 if (hash->root.root.type == bfd_link_hash_defined
5406 || hash->root.root.type == bfd_link_hash_defweak)
5407 {
5408 sym_sec = hash->root.root.u.def.section;
5409 sym_value = hash->root.root.u.def.value;
022f8312
CL		 5410
5411 struct elf32_arm_link_hash_table *globals =
5412 elf32_arm_hash_table (info);
5413
5414 /* For a destination in a shared library,
5415 use the PLT stub as target address to
5416 decide whether a branch stub is
5417 needed. */
4dfe6ac6 5418 if (globals != NULL
362d30a1 5419 && globals->root.splt != NULL
4dfe6ac6 5420 && hash != NULL
022f8312
CL		 5421 && hash->root.plt.offset != (bfd_vma) -1)
5422 {
362d30a1 5423 sym_sec = globals->root.splt;
022f8312
CL		 5424 sym_value = hash->root.plt.offset;
5425 if (sym_sec->output_section != NULL)
5426 destination = (sym_value
5427 + sym_sec->output_offset
5428 + sym_sec->output_section->vma);
5429 }
5430 else if (sym_sec->output_section != NULL)
906e58ca
NC		 5431 destination = (sym_value + irela->r_addend
5432 + sym_sec->output_offset
5433 + sym_sec->output_section->vma);
5434 }
69c5861e
CL		 5435 else if ((hash->root.root.type == bfd_link_hash_undefined)
5436 || (hash->root.root.type == bfd_link_hash_undefweak))
5437 {
5438 /* For a shared library, use the PLT stub as
5439 target address to decide whether a long
5440 branch stub is needed.
5441 For absolute code, they cannot be handled. */
5442 struct elf32_arm_link_hash_table *globals =
5443 elf32_arm_hash_table (info);
5444
4dfe6ac6 5445 if (globals != NULL
362d30a1 5446 && globals->root.splt != NULL
4dfe6ac6 5447 && hash != NULL
69c5861e
CL		 5448 && hash->root.plt.offset != (bfd_vma) -1)
5449 {
362d30a1 5450 sym_sec = globals->root.splt;
69c5861e
CL		 5451 sym_value = hash->root.plt.offset;
5452 if (sym_sec->output_section != NULL)
5453 destination = (sym_value
5454 + sym_sec->output_offset
5455 + sym_sec->output_section->vma);
5456 }
5457 else
5458 continue;
5459 }
906e58ca
NC		 5460 else
5461 {
5462 bfd_set_error (bfd_error_bad_value);
5463 goto error_ret_free_internal;
5464 }
34e77a92 5465 st_type = hash->root.type;
35fc36a8 5466 branch_type = hash->root.target_internal;
7413f23f 5467 sym_name = hash->root.root.root.string;
906e58ca
NC		 5468 }
5469
48229727 5470 do
7413f23f 5471 {
48229727
JB		 5472 /* Determine what (if any) linker stub is needed. */
5473 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 5474 st_type, &branch_type,
5475 hash, destination, sym_sec,
48229727
JB		 5476 input_bfd, sym_name);
5477 if (stub_type == arm_stub_none)
5478 break;
5479
5480 /* Support for grouping stub sections. */
5481 id_sec = htab->stub_group[section->id].link_sec;
5482
5483 /* Get the name of this stub. */
5484 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash,
fe33d2fa 5485 irela, stub_type);
48229727
JB		 5486 if (!stub_name)
5487 goto error_ret_free_internal;
5488
5489 /* We've either created a stub for this reloc already,
5490 or we are about to. */
5491 created_stub = TRUE;
5492
5493 stub_entry = arm_stub_hash_lookup
5494 (&htab->stub_hash_table, stub_name,
5495 FALSE, FALSE);
5496 if (stub_entry != NULL)
5497 {
5498 /* The proper stub has already been created. */
5499 free (stub_name);
eb7c4339 5500 stub_entry->target_value = sym_value;
48229727
JB		 5501 break;
5502 }
7413f23f 5503
48229727
JB		 5504 stub_entry = elf32_arm_add_stub (stub_name, section,
5505 htab);
5506 if (stub_entry == NULL)
5507 {
5508 free (stub_name);
5509 goto error_ret_free_internal;
5510 }
7413f23f 5511
99059e56
RM		 5512 stub_entry->target_value = sym_value;
5513 stub_entry->target_section = sym_sec;
5514 stub_entry->stub_type = stub_type;
5515 stub_entry->h = hash;
5516 stub_entry->branch_type = branch_type;
5517
5518 if (sym_name == NULL)
5519 sym_name = "unnamed";
5520 stub_entry->output_name = (char *)
5521 bfd_alloc (htab->stub_bfd,
5522 sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5523 + strlen (sym_name));
5524 if (stub_entry->output_name == NULL)
5525 {
5526 free (stub_name);
5527 goto error_ret_free_internal;
5528 }
5529
5530 /* For historical reasons, use the existing names for
5531 ARM-to-Thumb and Thumb-to-ARM stubs. */
5532 if ((r_type == (unsigned int) R_ARM_THM_CALL
c5423981
TG		 5533 || r_type == (unsigned int) R_ARM_THM_JUMP24
5534 || r_type == (unsigned int) R_ARM_THM_JUMP19)
35fc36a8 5535 && branch_type == ST_BRANCH_TO_ARM)
99059e56
RM		 5536 sprintf (stub_entry->output_name,
5537 THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5538 else if ((r_type == (unsigned int) R_ARM_CALL
35fc36a8
RS		 5539 || r_type == (unsigned int) R_ARM_JUMP24)
5540 && branch_type == ST_BRANCH_TO_THUMB)
99059e56
RM		 5541 sprintf (stub_entry->output_name,
5542 ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5543 else
5544 sprintf (stub_entry->output_name, STUB_ENTRY_NAME,
5545 sym_name);
5546
5547 stub_changed = TRUE;
5548 }
5549 while (0);
5550
5551 /* Look for relocations which might trigger Cortex-A8
5552 erratum. */
5553 if (htab->fix_cortex_a8
5554 && (r_type == (unsigned int) R_ARM_THM_JUMP24
5555 || r_type == (unsigned int) R_ARM_THM_JUMP19
5556 || r_type == (unsigned int) R_ARM_THM_CALL
5557 || r_type == (unsigned int) R_ARM_THM_XPC22))
5558 {
5559 bfd_vma from = section->output_section->vma
5560 + section->output_offset
5561 + irela->r_offset;
5562
5563 if ((from & 0xfff) == 0xffe)
5564 {
5565 /* Found a candidate. Note we haven't checked the
5566 destination is within 4K here: if we do so (and
5567 don't create an entry in a8_relocs) we can't tell
5568 that a branch should have been relocated when
5569 scanning later. */
5570 if (num_a8_relocs == a8_reloc_table_size)
5571 {
5572 a8_reloc_table_size *= 2;
5573 a8_relocs = (struct a8_erratum_reloc *)
5574 bfd_realloc (a8_relocs,
5575 sizeof (struct a8_erratum_reloc)
5576 * a8_reloc_table_size);
5577 }
5578
5579 a8_relocs[num_a8_relocs].from = from;
5580 a8_relocs[num_a8_relocs].destination = destination;
5581 a8_relocs[num_a8_relocs].r_type = r_type;
5582 a8_relocs[num_a8_relocs].branch_type = branch_type;
5583 a8_relocs[num_a8_relocs].sym_name = sym_name;
5584 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
5585 a8_relocs[num_a8_relocs].hash = hash;
5586
5587 num_a8_relocs++;
5588 }
5589 }
906e58ca
NC		 5590 }
5591
99059e56
RM		 5592 /* We're done with the internal relocs, free them. */
5593 if (elf_section_data (section)->relocs == NULL)
5594 free (internal_relocs);
5595 }
48229727 5596
99059e56 5597 if (htab->fix_cortex_a8)
48229727 5598 {
99059e56
RM		 5599 /* Sort relocs which might apply to Cortex-A8 erratum. */
5600 qsort (a8_relocs, num_a8_relocs,
eb7c4339 5601 sizeof (struct a8_erratum_reloc),
99059e56 5602 &a8_reloc_compare);
48229727 5603
99059e56
RM		 5604 /* Scan for branches which might trigger Cortex-A8 erratum. */
5605 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 5606 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 5607 a8_relocs, num_a8_relocs,
5608 prev_num_a8_fixes, &stub_changed)
5609 != 0)
48229727 5610 goto error_ret_free_local;
5e681ec4 5611 }
5e681ec4
PB		 5612 }
5613
eb7c4339 5614 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 5615 stub_changed = TRUE;
48229727 5616
906e58ca
NC		 5617 if (!stub_changed)
5618 break;
5e681ec4 5619
906e58ca
NC		 5620 /* OK, we've added some stubs. Find out the new size of the
5621 stub sections. */
5622 for (stub_sec = htab->stub_bfd->sections;
5623 stub_sec != NULL;
5624 stub_sec = stub_sec->next)
3e6b1042
DJ		 5625 {
5626 /* Ignore non-stub sections. */
5627 if (!strstr (stub_sec->name, STUB_SUFFIX))
5628 continue;
5629
5630 stub_sec->size = 0;
5631 }
b34b2d70 5632
906e58ca
NC		 5633 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
5634
48229727
JB		 5635 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5636 if (htab->fix_cortex_a8)
99059e56
RM		 5637 for (i = 0; i < num_a8_fixes; i++)
5638 {
48229727
JB		 5639 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
5640 a8_fixes[i].section, htab);
5641
5642 if (stub_sec == NULL)
5643 goto error_ret_free_local;
5644
99059e56
RM		 5645 stub_sec->size
5646 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
5647 NULL);
5648 }
48229727
JB		 5649
5650
906e58ca
NC		 5651 /* Ask the linker to do its stuff. */
5652 (*htab->layout_sections_again) ();
ba93b8ac
DJ		 5653 }
5654
48229727
JB		 5655 /* Add stubs for Cortex-A8 erratum fixes now. */
5656 if (htab->fix_cortex_a8)
5657 {
5658 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 5659 {
5660 struct elf32_arm_stub_hash_entry *stub_entry;
5661 char *stub_name = a8_fixes[i].stub_name;
5662 asection *section = a8_fixes[i].section;
5663 unsigned int section_id = a8_fixes[i].section->id;
5664 asection *link_sec = htab->stub_group[section_id].link_sec;
5665 asection *stub_sec = htab->stub_group[section_id].stub_sec;
5666 const insn_sequence *template_sequence;
5667 int template_size, size = 0;
5668
5669 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
5670 TRUE, FALSE);
5671 if (stub_entry == NULL)
5672 {
5673 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
5674 section->owner,
5675 stub_name);
5676 return FALSE;
5677 }
5678
5679 stub_entry->stub_sec = stub_sec;
5680 stub_entry->stub_offset = 0;
5681 stub_entry->id_sec = link_sec;
5682 stub_entry->stub_type = a8_fixes[i].stub_type;
5683 stub_entry->target_section = a8_fixes[i].section;
5684 stub_entry->target_value = a8_fixes[i].offset;
5685 stub_entry->target_addend = a8_fixes[i].addend;
5686 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 5687 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 5688
99059e56
RM		 5689 size = find_stub_size_and_template (a8_fixes[i].stub_type,
5690 &template_sequence,
5691 &template_size);
48229727 5692
99059e56
RM		 5693 stub_entry->stub_size = size;
5694 stub_entry->stub_template = template_sequence;
5695 stub_entry->stub_template_size = template_size;
5696 }
48229727
JB		 5697
5698 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 5699 elf32_arm_write_section(). */
48229727
JB		 5700 htab->a8_erratum_fixes = a8_fixes;
5701 htab->num_a8_erratum_fixes = num_a8_fixes;
5702 }
5703 else
5704 {
5705 htab->a8_erratum_fixes = NULL;
5706 htab->num_a8_erratum_fixes = 0;
5707 }
906e58ca 5708 return TRUE;
5e681ec4
PB		 5709}
5710
906e58ca
NC		 5711/* Build all the stubs associated with the current output file. The
5712 stubs are kept in a hash table attached to the main linker hash
5713 table. We also set up the .plt entries for statically linked PIC
5714 functions here. This function is called via arm_elf_finish in the
5715 linker. */
252b5132 5716
906e58ca
NC		 5717bfd_boolean
5718elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 5719{
906e58ca
NC		 5720 asection *stub_sec;
5721 struct bfd_hash_table *table;
5722 struct elf32_arm_link_hash_table *htab;
252b5132 5723
906e58ca 5724 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5725 if (htab == NULL)
5726 return FALSE;
252b5132 5727
906e58ca
NC		 5728 for (stub_sec = htab->stub_bfd->sections;
5729 stub_sec != NULL;
5730 stub_sec = stub_sec->next)
252b5132 5731 {
906e58ca
NC		 5732 bfd_size_type size;
5733
8029a119 5734 /* Ignore non-stub sections. */
906e58ca
NC		 5735 if (!strstr (stub_sec->name, STUB_SUFFIX))
5736 continue;
5737
5738 /* Allocate memory to hold the linker stubs. */
5739 size = stub_sec->size;
21d799b5 5740 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 5741 if (stub_sec->contents == NULL && size != 0)
5742 return FALSE;
5743 stub_sec->size = 0;
252b5132
RH		 5744 }
5745
906e58ca
NC		 5746 /* Build the stubs as directed by the stub hash table. */
5747 table = &htab->stub_hash_table;
5748 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 5749 if (htab->fix_cortex_a8)
5750 {
5751 /* Place the cortex a8 stubs last. */
5752 htab->fix_cortex_a8 = -1;
5753 bfd_hash_traverse (table, arm_build_one_stub, info);
5754 }
252b5132 5755
906e58ca 5756 return TRUE;
252b5132
RH		 5757}
5758
9b485d32
NC		 5759/* Locate the Thumb encoded calling stub for NAME. */
5760
252b5132 5761static struct elf_link_hash_entry *
57e8b36a
NC		 5762find_thumb_glue (struct bfd_link_info *link_info,
5763 const char *name,
f2a9dd69 5764 char **error_message)
252b5132
RH		 5765{
5766 char *tmp_name;
5767 struct elf_link_hash_entry *hash;
5768 struct elf32_arm_link_hash_table *hash_table;
5769
5770 /* We need a pointer to the armelf specific hash table. */
5771 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5772 if (hash_table == NULL)
5773 return NULL;
252b5132 5774
21d799b5 5775 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5776 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5777
5778 BFD_ASSERT (tmp_name);
5779
5780 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
5781
5782 hash = elf_link_hash_lookup
b34976b6 5783 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5784
b1657152
AM		 5785 if (hash == NULL
5786 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
5787 tmp_name, name) == -1)
5788 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5789
5790 free (tmp_name);
5791
5792 return hash;
5793}
5794
9b485d32
NC		 5795/* Locate the ARM encoded calling stub for NAME. */
5796
252b5132 5797static struct elf_link_hash_entry *
57e8b36a
NC		 5798find_arm_glue (struct bfd_link_info *link_info,
5799 const char *name,
f2a9dd69 5800 char **error_message)
252b5132
RH		 5801{
5802 char *tmp_name;
5803 struct elf_link_hash_entry *myh;
5804 struct elf32_arm_link_hash_table *hash_table;
5805
5806 /* We need a pointer to the elfarm specific hash table. */
5807 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5808 if (hash_table == NULL)
5809 return NULL;
252b5132 5810
21d799b5 5811 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5812 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5813
5814 BFD_ASSERT (tmp_name);
5815
5816 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5817
5818 myh = elf_link_hash_lookup
b34976b6 5819 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5820
b1657152
AM		 5821 if (myh == NULL
5822 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
5823 tmp_name, name) == -1)
5824 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5825
5826 free (tmp_name);
5827
5828 return myh;
5829}
5830
8f6277f5 5831/* ARM->Thumb glue (static images):
252b5132
RH		 5832
5833 .arm
5834 __func_from_arm:
5835 ldr r12, __func_addr
5836 bx r12
5837 __func_addr:
906e58ca 5838 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 5839
26079076
PB		 5840 (v5t static images)
5841 .arm
5842 __func_from_arm:
5843 ldr pc, __func_addr
5844 __func_addr:
906e58ca 5845 .word func @ behave as if you saw a ARM_32 reloc.
26079076 5846
8f6277f5
PB		 5847 (relocatable images)
5848 .arm
5849 __func_from_arm:
5850 ldr r12, __func_offset
5851 add r12, r12, pc
5852 bx r12
5853 __func_offset:
8029a119 5854 .word func - . */
8f6277f5
PB		 5855
5856#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 5857static const insn32 a2t1_ldr_insn = 0xe59fc000;
5858static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
5859static const insn32 a2t3_func_addr_insn = 0x00000001;
5860
26079076
PB		 5861#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5862static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
5863static const insn32 a2t2v5_func_addr_insn = 0x00000001;
5864
8f6277f5
PB		 5865#define ARM2THUMB_PIC_GLUE_SIZE 16
5866static const insn32 a2t1p_ldr_insn = 0xe59fc004;
5867static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
5868static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
5869
9b485d32 5870/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 5871
8029a119
NC		 5872 .thumb .thumb
5873 .align 2 .align 2
5874 __func_from_thumb: __func_from_thumb:
5875 bx pc push {r6, lr}
5876 nop ldr r6, __func_addr
5877 .arm mov lr, pc
5878 b func bx r6
99059e56
RM		 5879 .arm
5880 ;; back_to_thumb
5881 ldmia r13! {r6, lr}
5882 bx lr
5883 __func_addr:
5884 .word func */
252b5132
RH		 5885
5886#define THUMB2ARM_GLUE_SIZE 8
5887static const insn16 t2a1_bx_pc_insn = 0x4778;
5888static const insn16 t2a2_noop_insn = 0x46c0;
5889static const insn32 t2a3_b_insn = 0xea000000;
5890
c7b8f16e 5891#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 5892#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
5893#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 5894
845b51d6
PB		 5895#define ARM_BX_VENEER_SIZE 12
5896static const insn32 armbx1_tst_insn = 0xe3100001;
5897static const insn32 armbx2_moveq_insn = 0x01a0f000;
5898static const insn32 armbx3_bx_insn = 0xe12fff10;
5899
7e392df6 5900#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 5901static void
5902arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 5903{
5904 asection * s;
8029a119 5905 bfd_byte * contents;
252b5132 5906
8029a119 5907 if (size == 0)
3e6b1042
DJ		 5908 {
5909 /* Do not include empty glue sections in the output. */
5910 if (abfd != NULL)
5911 {
3d4d4302 5912 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 5913 if (s != NULL)
5914 s->flags |= SEC_EXCLUDE;
5915 }
5916 return;
5917 }
252b5132 5918
8029a119 5919 BFD_ASSERT (abfd != NULL);
252b5132 5920
3d4d4302 5921 s = bfd_get_linker_section (abfd, name);
8029a119 5922 BFD_ASSERT (s != NULL);
252b5132 5923
21d799b5 5924 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 5925
8029a119
NC		 5926 BFD_ASSERT (s->size == size);
5927 s->contents = contents;
5928}
906e58ca 5929
8029a119
NC		 5930bfd_boolean
5931bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
5932{
5933 struct elf32_arm_link_hash_table * globals;
906e58ca 5934
8029a119
NC		 5935 globals = elf32_arm_hash_table (info);
5936 BFD_ASSERT (globals != NULL);
906e58ca 5937
8029a119
NC		 5938 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5939 globals->arm_glue_size,
5940 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 5941
8029a119
NC		 5942 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5943 globals->thumb_glue_size,
5944 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 5945
8029a119
NC		 5946 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5947 globals->vfp11_erratum_glue_size,
5948 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 5949
a504d23a
LA		 5950 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5951 globals->stm32l4xx_erratum_glue_size,
5952 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
5953
8029a119
NC		 5954 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5955 globals->bx_glue_size,
845b51d6
PB		 5956 ARM_BX_GLUE_SECTION_NAME);
5957
b34976b6 5958 return TRUE;
252b5132
RH		 5959}
5960
a4fd1a8e 5961/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 5962 returns the symbol identifying the stub. */
5963
a4fd1a8e 5964static struct elf_link_hash_entry *
57e8b36a
NC		 5965record_arm_to_thumb_glue (struct bfd_link_info * link_info,
5966 struct elf_link_hash_entry * h)
252b5132
RH		 5967{
5968 const char * name = h->root.root.string;
63b0f745 5969 asection * s;
252b5132
RH		 5970 char * tmp_name;
5971 struct elf_link_hash_entry * myh;
14a793b2 5972 struct bfd_link_hash_entry * bh;
252b5132 5973 struct elf32_arm_link_hash_table * globals;
dc810e39 5974 bfd_vma val;
2f475487 5975 bfd_size_type size;
252b5132
RH		 5976
5977 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 5978 BFD_ASSERT (globals != NULL);
5979 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
5980
3d4d4302 5981 s = bfd_get_linker_section
252b5132
RH		 5982 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
5983
252b5132
RH		 5984 BFD_ASSERT (s != NULL);
5985
21d799b5 5986 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5987 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5988
5989 BFD_ASSERT (tmp_name);
5990
5991 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5992
5993 myh = elf_link_hash_lookup
b34976b6 5994 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 5995
5996 if (myh != NULL)
5997 {
9b485d32 5998 /* We've already seen this guy. */
252b5132 5999 free (tmp_name);
a4fd1a8e 6000 return myh;
252b5132
RH		 6001 }
6002
57e8b36a
NC		 6003 /* The only trick here is using hash_table->arm_glue_size as the value.
6004 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6005 putting it. The +1 on the value marks that the stub has not been
6006 output yet - not that it is a Thumb function. */
14a793b2 6007 bh = NULL;
dc810e39
AM		 6008 val = globals->arm_glue_size + 1;
6009 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6010 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6011 NULL, TRUE, FALSE, &bh);
252b5132 6012
b7693d02
DJ		 6013 myh = (struct elf_link_hash_entry *) bh;
6014 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6015 myh->forced_local = 1;
6016
252b5132
RH		 6017 free (tmp_name);
6018
0e1862bb
L		 6019 if (bfd_link_pic (link_info)
6020 || globals->root.is_relocatable_executable
27e55c4d 6021 || globals->pic_veneer)
2f475487 6022 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6023 else if (globals->use_blx)
6024 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6025 else
2f475487
AM		 6026 size = ARM2THUMB_STATIC_GLUE_SIZE;
6027
6028 s->size += size;
6029 globals->arm_glue_size += size;
252b5132 6030
a4fd1a8e 6031 return myh;
252b5132
RH		 6032}
6033
845b51d6
PB		 6034/* Allocate space for ARMv4 BX veneers. */
6035
6036static void
6037record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6038{
6039 asection * s;
6040 struct elf32_arm_link_hash_table *globals;
6041 char *tmp_name;
6042 struct elf_link_hash_entry *myh;
6043 struct bfd_link_hash_entry *bh;
6044 bfd_vma val;
6045
6046 /* BX PC does not need a veneer. */
6047 if (reg == 15)
6048 return;
6049
6050 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 6051 BFD_ASSERT (globals != NULL);
6052 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6053
6054 /* Check if this veneer has already been allocated. */
6055 if (globals->bx_glue_offset[reg])
6056 return;
6057
3d4d4302 6058 s = bfd_get_linker_section
845b51d6
PB		 6059 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
6060
6061 BFD_ASSERT (s != NULL);
6062
6063 /* Add symbol for veneer. */
21d799b5
NC		 6064 tmp_name = (char *)
6065 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 6066
845b51d6 6067 BFD_ASSERT (tmp_name);
906e58ca 6068
845b51d6 6069 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 6070
845b51d6
PB		 6071 myh = elf_link_hash_lookup
6072 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6073
845b51d6 6074 BFD_ASSERT (myh == NULL);
906e58ca 6075
845b51d6
PB		 6076 bh = NULL;
6077 val = globals->bx_glue_size;
6078 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 6079 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6080 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 6081
6082 myh = (struct elf_link_hash_entry *) bh;
6083 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6084 myh->forced_local = 1;
6085
6086 s->size += ARM_BX_VENEER_SIZE;
6087 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
6088 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
6089}
6090
6091
c7b8f16e
JB		 6092/* Add an entry to the code/data map for section SEC. */
6093
6094static void
6095elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
6096{
6097 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
6098 unsigned int newidx;
906e58ca 6099
c7b8f16e
JB		 6100 if (sec_data->map == NULL)
6101 {
21d799b5 6102 sec_data->map = (elf32_arm_section_map *)
99059e56 6103 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 6104 sec_data->mapcount = 0;
6105 sec_data->mapsize = 1;
6106 }
906e58ca 6107
c7b8f16e 6108 newidx = sec_data->mapcount++;
906e58ca 6109
c7b8f16e
JB		 6110 if (sec_data->mapcount > sec_data->mapsize)
6111 {
6112 sec_data->mapsize *= 2;
21d799b5 6113 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 6114 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
6115 * sizeof (elf32_arm_section_map));
515ef31d
NC		 6116 }
6117
6118 if (sec_data->map)
6119 {
6120 sec_data->map[newidx].vma = vma;
6121 sec_data->map[newidx].type = type;
c7b8f16e 6122 }
c7b8f16e
JB		 6123}
6124
6125
6126/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6127 veneers are handled for now. */
6128
6129static bfd_vma
6130record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 6131 elf32_vfp11_erratum_list *branch,
6132 bfd *branch_bfd,
6133 asection *branch_sec,
6134 unsigned int offset)
c7b8f16e
JB		 6135{
6136 asection *s;
6137 struct elf32_arm_link_hash_table *hash_table;
6138 char *tmp_name;
6139 struct elf_link_hash_entry *myh;
6140 struct bfd_link_hash_entry *bh;
6141 bfd_vma val;
6142 struct _arm_elf_section_data *sec_data;
c7b8f16e 6143 elf32_vfp11_erratum_list *newerr;
906e58ca 6144
c7b8f16e 6145 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 6146 BFD_ASSERT (hash_table != NULL);
6147 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 6148
3d4d4302 6149 s = bfd_get_linker_section
c7b8f16e 6150 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 6151
c7b8f16e 6152 sec_data = elf32_arm_section_data (s);
906e58ca 6153
c7b8f16e 6154 BFD_ASSERT (s != NULL);
906e58ca 6155
21d799b5 6156 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 6157 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 6158
c7b8f16e 6159 BFD_ASSERT (tmp_name);
906e58ca 6160
c7b8f16e
JB		 6161 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
6162 hash_table->num_vfp11_fixes);
906e58ca 6163
c7b8f16e
JB		 6164 myh = elf_link_hash_lookup
6165 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6166
c7b8f16e 6167 BFD_ASSERT (myh == NULL);
906e58ca 6168
c7b8f16e
JB		 6169 bh = NULL;
6170 val = hash_table->vfp11_erratum_glue_size;
6171 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 6172 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6173 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 6174
6175 myh = (struct elf_link_hash_entry *) bh;
6176 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6177 myh->forced_local = 1;
6178
6179 /* Link veneer back to calling location. */
c7e2358a 6180 sec_data->erratumcount += 1;
21d799b5
NC		 6181 newerr = (elf32_vfp11_erratum_list *)
6182 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 6183
c7b8f16e
JB		 6184 newerr->type = VFP11_ERRATUM_ARM_VENEER;
6185 newerr->vma = -1;
6186 newerr->u.v.branch = branch;
6187 newerr->u.v.id = hash_table->num_vfp11_fixes;
6188 branch->u.b.veneer = newerr;
6189
6190 newerr->next = sec_data->erratumlist;
6191 sec_data->erratumlist = newerr;
6192
6193 /* A symbol for the return from the veneer. */
6194 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
6195 hash_table->num_vfp11_fixes);
6196
6197 myh = elf_link_hash_lookup
6198 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6199
c7b8f16e
JB		 6200 if (myh != NULL)
6201 abort ();
6202
6203 bh = NULL;
6204 val = offset + 4;
6205 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6206 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 6207
c7b8f16e
JB		 6208 myh = (struct elf_link_hash_entry *) bh;
6209 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6210 myh->forced_local = 1;
6211
6212 free (tmp_name);
906e58ca 6213
c7b8f16e
JB		 6214 /* Generate a mapping symbol for the veneer section, and explicitly add an
6215 entry for that symbol to the code/data map for the section. */
6216 if (hash_table->vfp11_erratum_glue_size == 0)
6217 {
6218 bh = NULL;
6219 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 6220 ever requires this erratum fix. */
c7b8f16e
JB		 6221 _bfd_generic_link_add_one_symbol (link_info,
6222 hash_table->bfd_of_glue_owner, "$a",
6223 BSF_LOCAL, s, 0, NULL,
99059e56 6224 TRUE, FALSE, &bh);
c7b8f16e
JB		 6225
6226 myh = (struct elf_link_hash_entry *) bh;
6227 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6228 myh->forced_local = 1;
906e58ca 6229
c7b8f16e 6230 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 6231 BFDs. We must make a note of this generated mapping symbol
6232 ourselves so that code byteswapping works properly in
6233 elf32_arm_write_section. */
c7b8f16e
JB		 6234 elf32_arm_section_map_add (s, 'a', 0);
6235 }
906e58ca 6236
c7b8f16e
JB		 6237 s->size += VFP11_ERRATUM_VENEER_SIZE;
6238 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
6239 hash_table->num_vfp11_fixes++;
906e58ca 6240
c7b8f16e
JB		 6241 /* The offset of the veneer. */
6242 return val;
6243}
6244
a504d23a
LA		 6245/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6246 veneers need to be handled because used only in Cortex-M. */
6247
6248static bfd_vma
6249record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
6250 elf32_stm32l4xx_erratum_list *branch,
6251 bfd *branch_bfd,
6252 asection *branch_sec,
6253 unsigned int offset,
6254 bfd_size_type veneer_size)
6255{
6256 asection *s;
6257 struct elf32_arm_link_hash_table *hash_table;
6258 char *tmp_name;
6259 struct elf_link_hash_entry *myh;
6260 struct bfd_link_hash_entry *bh;
6261 bfd_vma val;
6262 struct _arm_elf_section_data *sec_data;
6263 elf32_stm32l4xx_erratum_list *newerr;
6264
6265 hash_table = elf32_arm_hash_table (link_info);
6266 BFD_ASSERT (hash_table != NULL);
6267 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
6268
6269 s = bfd_get_linker_section
6270 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6271
6272 BFD_ASSERT (s != NULL);
6273
6274 sec_data = elf32_arm_section_data (s);
6275
6276 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
6277 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
6278
6279 BFD_ASSERT (tmp_name);
6280
6281 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
6282 hash_table->num_stm32l4xx_fixes);
6283
6284 myh = elf_link_hash_lookup
6285 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6286
6287 BFD_ASSERT (myh == NULL);
6288
6289 bh = NULL;
6290 val = hash_table->stm32l4xx_erratum_glue_size;
6291 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
6292 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6293 NULL, TRUE, FALSE, &bh);
6294
6295 myh = (struct elf_link_hash_entry *) bh;
6296 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6297 myh->forced_local = 1;
6298
6299 /* Link veneer back to calling location. */
6300 sec_data->stm32l4xx_erratumcount += 1;
6301 newerr = (elf32_stm32l4xx_erratum_list *)
6302 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
6303
6304 newerr->type = STM32L4XX_ERRATUM_VENEER;
6305 newerr->vma = -1;
6306 newerr->u.v.branch = branch;
6307 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
6308 branch->u.b.veneer = newerr;
6309
6310 newerr->next = sec_data->stm32l4xx_erratumlist;
6311 sec_data->stm32l4xx_erratumlist = newerr;
6312
6313 /* A symbol for the return from the veneer. */
6314 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
6315 hash_table->num_stm32l4xx_fixes);
6316
6317 myh = elf_link_hash_lookup
6318 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6319
6320 if (myh != NULL)
6321 abort ();
6322
6323 bh = NULL;
6324 val = offset + 4;
6325 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6326 branch_sec, val, NULL, TRUE, FALSE, &bh);
6327
6328 myh = (struct elf_link_hash_entry *) bh;
6329 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6330 myh->forced_local = 1;
6331
6332 free (tmp_name);
6333
6334 /* Generate a mapping symbol for the veneer section, and explicitly add an
6335 entry for that symbol to the code/data map for the section. */
6336 if (hash_table->stm32l4xx_erratum_glue_size == 0)
6337 {
6338 bh = NULL;
6339 /* Creates a THUMB symbol since there is no other choice. */
6340 _bfd_generic_link_add_one_symbol (link_info,
6341 hash_table->bfd_of_glue_owner, "$t",
6342 BSF_LOCAL, s, 0, NULL,
6343 TRUE, FALSE, &bh);
6344
6345 myh = (struct elf_link_hash_entry *) bh;
6346 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6347 myh->forced_local = 1;
6348
6349 /* The elf32_arm_init_maps function only cares about symbols from input
6350 BFDs. We must make a note of this generated mapping symbol
6351 ourselves so that code byteswapping works properly in
6352 elf32_arm_write_section. */
6353 elf32_arm_section_map_add (s, 't', 0);
6354 }
6355
6356 s->size += veneer_size;
6357 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
6358 hash_table->num_stm32l4xx_fixes++;
6359
6360 /* The offset of the veneer. */
6361 return val;
6362}
6363
8029a119 6364#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 6365 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6366 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 6367
6368/* Create a fake section for use by the ARM backend of the linker. */
6369
6370static bfd_boolean
6371arm_make_glue_section (bfd * abfd, const char * name)
6372{
6373 asection * sec;
6374
3d4d4302 6375 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 6376 if (sec != NULL)
6377 /* Already made. */
6378 return TRUE;
6379
3d4d4302 6380 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 6381
6382 if (sec == NULL
6383 || !bfd_set_section_alignment (abfd, sec, 2))
6384 return FALSE;
6385
6386 /* Set the gc mark to prevent the section from being removed by garbage
6387 collection, despite the fact that no relocs refer to this section. */
6388 sec->gc_mark = 1;
6389
6390 return TRUE;
6391}
6392
1db37fe6
YG		 6393/* Set size of .plt entries. This function is called from the
6394 linker scripts in ld/emultempl/{armelf}.em. */
6395
6396void
6397bfd_elf32_arm_use_long_plt (void)
6398{
6399 elf32_arm_use_long_plt_entry = TRUE;
6400}
6401
8afb0e02
NC		 6402/* Add the glue sections to ABFD. This function is called from the
6403 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 6404
b34976b6 6405bfd_boolean
57e8b36a
NC		 6406bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
6407 struct bfd_link_info *info)
252b5132 6408{
a504d23a
LA		 6409 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
6410 bfd_boolean dostm32l4xx = globals
6411 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
6412 bfd_boolean addglue;
6413
8afb0e02
NC		 6414 /* If we are only performing a partial
6415 link do not bother adding the glue. */
0e1862bb 6416 if (bfd_link_relocatable (info))
b34976b6 6417 return TRUE;
252b5132 6418
a504d23a 6419 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 6420 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
6421 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
6422 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 6423
6424 if (!dostm32l4xx)
6425 return addglue;
6426
6427 return addglue
6428 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 6429}
6430
6431/* Select a BFD to be used to hold the sections used by the glue code.
6432 This function is called from the linker scripts in ld/emultempl/
8029a119 6433 {armelf/pe}.em. */
8afb0e02 6434
b34976b6 6435bfd_boolean
57e8b36a 6436bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 6437{
6438 struct elf32_arm_link_hash_table *globals;
6439
6440 /* If we are only performing a partial link
6441 do not bother getting a bfd to hold the glue. */
0e1862bb 6442 if (bfd_link_relocatable (info))
b34976b6 6443 return TRUE;
8afb0e02 6444
b7693d02
DJ		 6445 /* Make sure we don't attach the glue sections to a dynamic object. */
6446 BFD_ASSERT (!(abfd->flags & DYNAMIC));
6447
8afb0e02 6448 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 6449 BFD_ASSERT (globals != NULL);
6450
6451 if (globals->bfd_of_glue_owner != NULL)
b34976b6 6452 return TRUE;
8afb0e02 6453
252b5132
RH		 6454 /* Save the bfd for later use. */
6455 globals->bfd_of_glue_owner = abfd;
cedb70c5 6456
b34976b6 6457 return TRUE;
252b5132
RH		 6458}
6459
906e58ca
NC		 6460static void
6461check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 6462{
2de70689
MGD		 6463 int cpu_arch;
6464
b38cadfb 6465 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 6466 Tag_CPU_arch);
6467
6468 if (globals->fix_arm1176)
6469 {
6470 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
6471 globals->use_blx = 1;
6472 }
6473 else
6474 {
6475 if (cpu_arch > TAG_CPU_ARCH_V4T)
6476 globals->use_blx = 1;
6477 }
39b41c9c
PB		 6478}
6479
b34976b6 6480bfd_boolean
57e8b36a 6481bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 6482 struct bfd_link_info *link_info)
252b5132
RH		 6483{
6484 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 6485 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 6486 Elf_Internal_Rela *irel, *irelend;
6487 bfd_byte *contents = NULL;
252b5132
RH		 6488
6489 asection *sec;
6490 struct elf32_arm_link_hash_table *globals;
6491
6492 /* If we are only performing a partial link do not bother
6493 to construct any glue. */
0e1862bb 6494 if (bfd_link_relocatable (link_info))
b34976b6 6495 return TRUE;
252b5132 6496
39ce1a6a
NC		 6497 /* Here we have a bfd that is to be included on the link. We have a
6498 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 6499 globals = elf32_arm_hash_table (link_info);
252b5132 6500 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 6501
6502 check_use_blx (globals);
252b5132 6503
d504ffc8 6504 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 6505 {
d003868e
AM		 6506 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
6507 abfd);
e489d0ae
PB		 6508 return FALSE;
6509 }
f21f3fe0 6510
39ce1a6a
NC		 6511 /* PR 5398: If we have not decided to include any loadable sections in
6512 the output then we will not have a glue owner bfd. This is OK, it
6513 just means that there is nothing else for us to do here. */
6514 if (globals->bfd_of_glue_owner == NULL)
6515 return TRUE;
6516
252b5132
RH		 6517 /* Rummage around all the relocs and map the glue vectors. */
6518 sec = abfd->sections;
6519
6520 if (sec == NULL)
b34976b6 6521 return TRUE;
252b5132
RH		 6522
6523 for (; sec != NULL; sec = sec->next)
6524 {
6525 if (sec->reloc_count == 0)
6526 continue;
6527
2f475487
AM		 6528 if ((sec->flags & SEC_EXCLUDE) != 0)
6529 continue;
6530
0ffa91dd 6531 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 6532
9b485d32 6533 /* Load the relocs. */
6cdc0ccc 6534 internal_relocs
906e58ca 6535 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 6536
6cdc0ccc
AM		 6537 if (internal_relocs == NULL)
6538 goto error_return;
252b5132 6539
6cdc0ccc
AM		 6540 irelend = internal_relocs + sec->reloc_count;
6541 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 6542 {
6543 long r_type;
6544 unsigned long r_index;
252b5132
RH		 6545
6546 struct elf_link_hash_entry *h;
6547
6548 r_type = ELF32_R_TYPE (irel->r_info);
6549 r_index = ELF32_R_SYM (irel->r_info);
6550
9b485d32 6551 /* These are the only relocation types we care about. */
ba96a88f 6552 if ( r_type != R_ARM_PC24
845b51d6 6553 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 6554 continue;
6555
6556 /* Get the section contents if we haven't done so already. */
6557 if (contents == NULL)
6558 {
6559 /* Get cached copy if it exists. */
6560 if (elf_section_data (sec)->this_hdr.contents != NULL)
6561 contents = elf_section_data (sec)->this_hdr.contents;
6562 else
6563 {
6564 /* Go get them off disk. */
57e8b36a 6565 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 6566 goto error_return;
6567 }
6568 }
6569
845b51d6
PB		 6570 if (r_type == R_ARM_V4BX)
6571 {
6572 int reg;
6573
6574 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
6575 record_arm_bx_glue (link_info, reg);
6576 continue;
6577 }
6578
a7c10850 6579 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 6580 h = NULL;
6581
9b485d32 6582 /* We don't care about local symbols. */
252b5132
RH		 6583 if (r_index < symtab_hdr->sh_info)
6584 continue;
6585
9b485d32 6586 /* This is an external symbol. */
252b5132
RH		 6587 r_index -= symtab_hdr->sh_info;
6588 h = (struct elf_link_hash_entry *)
6589 elf_sym_hashes (abfd)[r_index];
6590
6591 /* If the relocation is against a static symbol it must be within
6592 the current section and so cannot be a cross ARM/Thumb relocation. */
6593 if (h == NULL)
6594 continue;
6595
d504ffc8
DJ		 6596 /* If the call will go through a PLT entry then we do not need
6597 glue. */
362d30a1 6598 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 6599 continue;
6600
252b5132
RH		 6601 switch (r_type)
6602 {
6603 case R_ARM_PC24:
6604 /* This one is a call from arm code. We need to look up
99059e56
RM		 6605 the target of the call. If it is a thumb target, we
6606 insert glue. */
35fc36a8 6607 if (h->target_internal == ST_BRANCH_TO_THUMB)
252b5132
RH		 6608 record_arm_to_thumb_glue (link_info, h);
6609 break;
6610
252b5132 6611 default:
c6596c5e 6612 abort ();
252b5132
RH		 6613 }
6614 }
6cdc0ccc
AM		 6615
6616 if (contents != NULL
6617 && elf_section_data (sec)->this_hdr.contents != contents)
6618 free (contents);
6619 contents = NULL;
6620
6621 if (internal_relocs != NULL
6622 && elf_section_data (sec)->relocs != internal_relocs)
6623 free (internal_relocs);
6624 internal_relocs = NULL;
252b5132
RH		 6625 }
6626
b34976b6 6627 return TRUE;
9a5aca8c 6628
252b5132 6629error_return:
6cdc0ccc
AM		 6630 if (contents != NULL
6631 && elf_section_data (sec)->this_hdr.contents != contents)
6632 free (contents);
6633 if (internal_relocs != NULL
6634 && elf_section_data (sec)->relocs != internal_relocs)
6635 free (internal_relocs);
9a5aca8c 6636
b34976b6 6637 return FALSE;
252b5132 6638}
7e392df6 6639#endif
252b5132 6640
eb043451 6641
c7b8f16e
JB		 6642/* Initialise maps of ARM/Thumb/data for input BFDs. */
6643
6644void
6645bfd_elf32_arm_init_maps (bfd *abfd)
6646{
6647 Elf_Internal_Sym *isymbuf;
6648 Elf_Internal_Shdr *hdr;
6649 unsigned int i, localsyms;
6650
af1f4419
NC		 6651 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6652 if (! is_arm_elf (abfd))
6653 return;
6654
c7b8f16e
JB		 6655 if ((abfd->flags & DYNAMIC) != 0)
6656 return;
6657
0ffa91dd 6658 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 6659 localsyms = hdr->sh_info;
6660
6661 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6662 should contain the number of local symbols, which should come before any
6663 global symbols. Mapping symbols are always local. */
6664 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
6665 NULL);
6666
6667 /* No internal symbols read? Skip this BFD. */
6668 if (isymbuf == NULL)
6669 return;
6670
6671 for (i = 0; i < localsyms; i++)
6672 {
6673 Elf_Internal_Sym *isym = &isymbuf[i];
6674 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
6675 const char *name;
906e58ca 6676
c7b8f16e 6677 if (sec != NULL
99059e56
RM		 6678 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
6679 {
6680 name = bfd_elf_string_from_elf_section (abfd,
6681 hdr->sh_link, isym->st_name);
906e58ca 6682
99059e56 6683 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 6684 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 6685 elf32_arm_section_map_add (sec, name[1], isym->st_value);
6686 }
c7b8f16e
JB		 6687 }
6688}
6689
6690
48229727
JB		 6691/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6692 say what they wanted. */
6693
6694void
6695bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
6696{
6697 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6698 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6699
4dfe6ac6
NC		 6700 if (globals == NULL)
6701 return;
6702
48229727
JB		 6703 if (globals->fix_cortex_a8 == -1)
6704 {
6705 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6706 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
6707 && (out_attr[Tag_CPU_arch_profile].i == 'A'
6708 || out_attr[Tag_CPU_arch_profile].i == 0))
6709 globals->fix_cortex_a8 = 1;
6710 else
6711 globals->fix_cortex_a8 = 0;
6712 }
6713}
6714
6715
c7b8f16e
JB		 6716void
6717bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
6718{
6719 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 6720 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 6721
4dfe6ac6
NC		 6722 if (globals == NULL)
6723 return;
c7b8f16e
JB		 6724 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6725 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
6726 {
6727 switch (globals->vfp11_fix)
99059e56
RM		 6728 {
6729 case BFD_ARM_VFP11_FIX_DEFAULT:
6730 case BFD_ARM_VFP11_FIX_NONE:
6731 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6732 break;
6733
6734 default:
6735 /* Give a warning, but do as the user requests anyway. */
6736 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
6737 "workaround is not necessary for target architecture"), obfd);
6738 }
c7b8f16e
JB		 6739 }
6740 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
6741 /* For earlier architectures, we might need the workaround, but do not
6742 enable it by default. If users is running with broken hardware, they
6743 must enable the erratum fix explicitly. */
6744 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6745}
6746
a504d23a
LA		 6747void
6748bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
6749{
6750 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6751 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6752
6753 if (globals == NULL)
6754 return;
6755
6756 /* We assume only Cortex-M4 may require the fix. */
6757 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
6758 || out_attr[Tag_CPU_arch_profile].i != 'M')
6759 {
6760 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
6761 /* Give a warning, but do as the user requests anyway. */
6762 (*_bfd_error_handler)
6763 (_("%B: warning: selected STM32L4XX erratum "
6764 "workaround is not necessary for target architecture"), obfd);
6765 }
6766}
c7b8f16e 6767
906e58ca
NC		 6768enum bfd_arm_vfp11_pipe
6769{
c7b8f16e
JB		 6770 VFP11_FMAC,
6771 VFP11_LS,
6772 VFP11_DS,
6773 VFP11_BAD
6774};
6775
6776/* Return a VFP register number. This is encoded as RX:X for single-precision
6777 registers, or X:RX for double-precision registers, where RX is the group of
6778 four bits in the instruction encoding and X is the single extension bit.
6779 RX and X fields are specified using their lowest (starting) bit. The return
6780 value is:
6781
6782 0...31: single-precision registers s0...s31
6783 32...63: double-precision registers d0...d31.
906e58ca 6784
c7b8f16e
JB		 6785 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6786 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 6787
c7b8f16e
JB		 6788static unsigned int
6789bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 6790 unsigned int x)
c7b8f16e
JB		 6791{
6792 if (is_double)
6793 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
6794 else
6795 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
6796}
6797
6798/* Set bits in *WMASK according to a register number REG as encoded by
6799 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6800
6801static void
6802bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
6803{
6804 if (reg < 32)
6805 *wmask |= 1 << reg;
6806 else if (reg < 48)
6807 *wmask |= 3 << ((reg - 32) * 2);
6808}
6809
6810/* Return TRUE if WMASK overwrites anything in REGS. */
6811
6812static bfd_boolean
6813bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
6814{
6815 int i;
906e58ca 6816
c7b8f16e
JB		 6817 for (i = 0; i < numregs; i++)
6818 {
6819 unsigned int reg = regs[i];
6820
6821 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 6822 return TRUE;
906e58ca 6823
c7b8f16e
JB		 6824 reg -= 32;
6825
6826 if (reg >= 16)
99059e56 6827 continue;
906e58ca 6828
c7b8f16e 6829 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 6830 return TRUE;
c7b8f16e 6831 }
906e58ca 6832
c7b8f16e
JB		 6833 return FALSE;
6834}
6835
6836/* In this function, we're interested in two things: finding input registers
6837 for VFP data-processing instructions, and finding the set of registers which
6838 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6839 hold the written set, so FLDM etc. are easy to deal with (we're only
6840 interested in 32 SP registers or 16 dp registers, due to the VFP version
6841 implemented by the chip in question). DP registers are marked by setting
6842 both SP registers in the write mask). */
6843
6844static enum bfd_arm_vfp11_pipe
6845bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 6846 int *numregs)
c7b8f16e 6847{
91d6fa6a 6848 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 6849 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
6850
6851 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
6852 {
6853 unsigned int pqrs;
6854 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6855 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
6856
6857 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 6858 | ((insn & 0x00300000) >> 19)
6859 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 6860
6861 switch (pqrs)
99059e56
RM		 6862 {
6863 case 0: /* fmac[sd]. */
6864 case 1: /* fnmac[sd]. */
6865 case 2: /* fmsc[sd]. */
6866 case 3: /* fnmsc[sd]. */
6867 vpipe = VFP11_FMAC;
6868 bfd_arm_vfp11_write_mask (destmask, fd);
6869 regs[0] = fd;
6870 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6871 regs[2] = fm;
6872 *numregs = 3;
6873 break;
6874
6875 case 4: /* fmul[sd]. */
6876 case 5: /* fnmul[sd]. */
6877 case 6: /* fadd[sd]. */
6878 case 7: /* fsub[sd]. */
6879 vpipe = VFP11_FMAC;
6880 goto vfp_binop;
6881
6882 case 8: /* fdiv[sd]. */
6883 vpipe = VFP11_DS;
6884 vfp_binop:
6885 bfd_arm_vfp11_write_mask (destmask, fd);
6886 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6887 regs[1] = fm;
6888 *numregs = 2;
6889 break;
6890
6891 case 15: /* extended opcode. */
6892 {
6893 unsigned int extn = ((insn >> 15) & 0x1e)
6894 | ((insn >> 7) & 1);
6895
6896 switch (extn)
6897 {
6898 case 0: /* fcpy[sd]. */
6899 case 1: /* fabs[sd]. */
6900 case 2: /* fneg[sd]. */
6901 case 8: /* fcmp[sd]. */
6902 case 9: /* fcmpe[sd]. */
6903 case 10: /* fcmpz[sd]. */
6904 case 11: /* fcmpez[sd]. */
6905 case 16: /* fuito[sd]. */
6906 case 17: /* fsito[sd]. */
6907 case 24: /* ftoui[sd]. */
6908 case 25: /* ftouiz[sd]. */
6909 case 26: /* ftosi[sd]. */
6910 case 27: /* ftosiz[sd]. */
6911 /* These instructions will not bounce due to underflow. */
6912 *numregs = 0;
6913 vpipe = VFP11_FMAC;
6914 break;
6915
6916 case 3: /* fsqrt[sd]. */
6917 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6918 registers to cause the erratum in previous instructions. */
6919 bfd_arm_vfp11_write_mask (destmask, fd);
6920 vpipe = VFP11_DS;
6921 break;
6922
6923 case 15: /* fcvt{ds,sd}. */
6924 {
6925 int rnum = 0;
6926
6927 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 6928
6929 /* Only FCVTSD can underflow. */
99059e56
RM		 6930 if ((insn & 0x100) != 0)
6931 regs[rnum++] = fm;
c7b8f16e 6932
99059e56 6933 *numregs = rnum;
c7b8f16e 6934
99059e56
RM		 6935 vpipe = VFP11_FMAC;
6936 }
6937 break;
c7b8f16e 6938
99059e56
RM		 6939 default:
6940 return VFP11_BAD;
6941 }
6942 }
6943 break;
c7b8f16e 6944
99059e56
RM		 6945 default:
6946 return VFP11_BAD;
6947 }
c7b8f16e
JB		 6948 }
6949 /* Two-register transfer. */
6950 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
6951 {
6952 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 6953
c7b8f16e
JB		 6954 if ((insn & 0x100000) == 0)
6955 {
99059e56
RM		 6956 if (is_double)
6957 bfd_arm_vfp11_write_mask (destmask, fm);
6958 else
6959 {
6960 bfd_arm_vfp11_write_mask (destmask, fm);
6961 bfd_arm_vfp11_write_mask (destmask, fm + 1);
6962 }
c7b8f16e
JB		 6963 }
6964
91d6fa6a 6965 vpipe = VFP11_LS;
c7b8f16e
JB		 6966 }
6967 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
6968 {
6969 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6970 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 6971
c7b8f16e 6972 switch (puw)
99059e56
RM		 6973 {
6974 case 0: /* Two-reg transfer. We should catch these above. */
6975 abort ();
906e58ca 6976
99059e56
RM		 6977 case 2: /* fldm[sdx]. */
6978 case 3:
6979 case 5:
6980 {
6981 unsigned int i, offset = insn & 0xff;
c7b8f16e 6982
99059e56
RM		 6983 if (is_double)
6984 offset >>= 1;
c7b8f16e 6985
99059e56
RM		 6986 for (i = fd; i < fd + offset; i++)
6987 bfd_arm_vfp11_write_mask (destmask, i);
6988 }
6989 break;
906e58ca 6990
99059e56
RM		 6991 case 4: /* fld[sd]. */
6992 case 6:
6993 bfd_arm_vfp11_write_mask (destmask, fd);
6994 break;
906e58ca 6995
99059e56
RM		 6996 default:
6997 return VFP11_BAD;
6998 }
c7b8f16e 6999
91d6fa6a 7000 vpipe = VFP11_LS;
c7b8f16e
JB		 7001 }
7002 /* Single-register transfer. Note L==0. */
7003 else if ((insn & 0x0f100e10) == 0x0e000a10)
7004 {
7005 unsigned int opcode = (insn >> 21) & 7;
7006 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
7007
7008 switch (opcode)
99059e56
RM		 7009 {
7010 case 0: /* fmsr/fmdlr. */
7011 case 1: /* fmdhr. */
7012 /* Mark fmdhr and fmdlr as writing to the whole of the DP
7013 destination register. I don't know if this is exactly right,
7014 but it is the conservative choice. */
7015 bfd_arm_vfp11_write_mask (destmask, fn);
7016 break;
7017
7018 case 7: /* fmxr. */
7019 break;
7020 }
c7b8f16e 7021
91d6fa6a 7022 vpipe = VFP11_LS;
c7b8f16e
JB		 7023 }
7024
91d6fa6a 7025 return vpipe;
c7b8f16e
JB		 7026}
7027
7028
7029static int elf32_arm_compare_mapping (const void * a, const void * b);
7030
7031
7032/* Look for potentially-troublesome code sequences which might trigger the
7033 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
7034 (available from ARM) for details of the erratum. A short version is
7035 described in ld.texinfo. */
7036
7037bfd_boolean
7038bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
7039{
7040 asection *sec;
7041 bfd_byte *contents = NULL;
7042 int state = 0;
7043 int regs[3], numregs = 0;
7044 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7045 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 7046
4dfe6ac6
NC		 7047 if (globals == NULL)
7048 return FALSE;
7049
c7b8f16e
JB		 7050 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
7051 The states transition as follows:
906e58ca 7052
c7b8f16e 7053 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 7054 A VFP FMAC-pipeline instruction has been seen. Fill
7055 regs[0]..regs[numregs-1] with its input operands. Remember this
7056 instruction in 'first_fmac'.
c7b8f16e
JB		 7057
7058 1 -> 2
99059e56
RM		 7059 Any instruction, except for a VFP instruction which overwrites
7060 regs[*].
906e58ca 7061
c7b8f16e
JB		 7062 1 -> 3 [ -> 0 ] or
7063 2 -> 3 [ -> 0 ]
99059e56
RM		 7064 A VFP instruction has been seen which overwrites any of regs[*].
7065 We must make a veneer! Reset state to 0 before examining next
7066 instruction.
906e58ca 7067
c7b8f16e 7068 2 -> 0
99059e56
RM		 7069 If we fail to match anything in state 2, reset to state 0 and reset
7070 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 7071
7072 If the VFP11 vector mode is in use, there must be at least two unrelated
7073 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 7074 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 7075
7076 /* If we are only performing a partial link do not bother
7077 to construct any glue. */
0e1862bb 7078 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 7079 return TRUE;
7080
0ffa91dd
NC		 7081 /* Skip if this bfd does not correspond to an ELF image. */
7082 if (! is_arm_elf (abfd))
7083 return TRUE;
906e58ca 7084
c7b8f16e
JB		 7085 /* We should have chosen a fix type by the time we get here. */
7086 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
7087
7088 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
7089 return TRUE;
2e6030b9 7090
33a7ffc2
JM		 7091 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7092 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7093 return TRUE;
7094
c7b8f16e
JB		 7095 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7096 {
7097 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
7098 struct _arm_elf_section_data *sec_data;
7099
7100 /* If we don't have executable progbits, we're not interested in this
99059e56 7101 section. Also skip if section is to be excluded. */
c7b8f16e 7102 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 7103 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7104 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 7105 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 7106 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 7107 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
7108 continue;
c7b8f16e
JB		 7109
7110 sec_data = elf32_arm_section_data (sec);
906e58ca 7111
c7b8f16e 7112 if (sec_data->mapcount == 0)
99059e56 7113 continue;
906e58ca 7114
c7b8f16e
JB		 7115 if (elf_section_data (sec)->this_hdr.contents != NULL)
7116 contents = elf_section_data (sec)->this_hdr.contents;
7117 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7118 goto error_return;
7119
7120 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7121 elf32_arm_compare_mapping);
7122
7123 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 7124 {
7125 unsigned int span_start = sec_data->map[span].vma;
7126 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 7127 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 7128 char span_type = sec_data->map[span].type;
7129
7130 /* FIXME: Only ARM mode is supported at present. We may need to
7131 support Thumb-2 mode also at some point. */
7132 if (span_type != 'a')
7133 continue;
7134
7135 for (i = span_start; i < span_end;)
7136 {
7137 unsigned int next_i = i + 4;
7138 unsigned int insn = bfd_big_endian (abfd)
7139 ? (contents[i] << 24)
7140 | (contents[i + 1] << 16)
7141 | (contents[i + 2] << 8)
7142 | contents[i + 3]
7143 : (contents[i + 3] << 24)
7144 | (contents[i + 2] << 16)
7145 | (contents[i + 1] << 8)
7146 | contents[i];
7147 unsigned int writemask = 0;
7148 enum bfd_arm_vfp11_pipe vpipe;
7149
7150 switch (state)
7151 {
7152 case 0:
7153 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
7154 &numregs);
7155 /* I'm assuming the VFP11 erratum can trigger with denorm
7156 operands on either the FMAC or the DS pipeline. This might
7157 lead to slightly overenthusiastic veneer insertion. */
7158 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
7159 {
7160 state = use_vector ? 1 : 2;
7161 first_fmac = i;
7162 veneer_of_insn = insn;
7163 }
7164 break;
7165
7166 case 1:
7167 {
7168 int other_regs[3], other_numregs;
7169 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7170 other_regs,
99059e56
RM		 7171 &other_numregs);
7172 if (vpipe != VFP11_BAD
7173 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7174 numregs))
99059e56
RM		 7175 state = 3;
7176 else
7177 state = 2;
7178 }
7179 break;
7180
7181 case 2:
7182 {
7183 int other_regs[3], other_numregs;
7184 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7185 other_regs,
99059e56
RM		 7186 &other_numregs);
7187 if (vpipe != VFP11_BAD
7188 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7189 numregs))
99059e56
RM		 7190 state = 3;
7191 else
7192 {
7193 state = 0;
7194 next_i = first_fmac + 4;
7195 }
7196 }
7197 break;
7198
7199 case 3:
7200 abort (); /* Should be unreachable. */
7201 }
7202
7203 if (state == 3)
7204 {
7205 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
7206 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7207
7208 elf32_arm_section_data (sec)->erratumcount += 1;
7209
7210 newerr->u.b.vfp_insn = veneer_of_insn;
7211
7212 switch (span_type)
7213 {
7214 case 'a':
7215 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
7216 break;
7217
7218 default:
7219 abort ();
7220 }
7221
7222 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 7223 first_fmac);
7224
99059e56 7225 newerr->vma = -1;
c7b8f16e 7226
99059e56
RM		 7227 newerr->next = sec_data->erratumlist;
7228 sec_data->erratumlist = newerr;
c7b8f16e 7229
99059e56
RM		 7230 state = 0;
7231 }
c7b8f16e 7232
99059e56
RM		 7233 i = next_i;
7234 }
7235 }
906e58ca 7236
c7b8f16e 7237 if (contents != NULL
99059e56
RM		 7238 && elf_section_data (sec)->this_hdr.contents != contents)
7239 free (contents);
c7b8f16e
JB		 7240 contents = NULL;
7241 }
7242
7243 return TRUE;
7244
7245error_return:
7246 if (contents != NULL
7247 && elf_section_data (sec)->this_hdr.contents != contents)
7248 free (contents);
906e58ca 7249
c7b8f16e
JB		 7250 return FALSE;
7251}
7252
7253/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7254 after sections have been laid out, using specially-named symbols. */
7255
7256void
7257bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
7258 struct bfd_link_info *link_info)
7259{
7260 asection *sec;
7261 struct elf32_arm_link_hash_table *globals;
7262 char *tmp_name;
906e58ca 7263
0e1862bb 7264 if (bfd_link_relocatable (link_info))
c7b8f16e 7265 return;
2e6030b9
MS		 7266
7267 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 7268 if (! is_arm_elf (abfd))
2e6030b9
MS		 7269 return;
7270
c7b8f16e 7271 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7272 if (globals == NULL)
7273 return;
906e58ca 7274
21d799b5 7275 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7276 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 7277
7278 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7279 {
7280 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7281 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 7282
c7b8f16e 7283 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 7284 {
7285 struct elf_link_hash_entry *myh;
7286 bfd_vma vma;
7287
7288 switch (errnode->type)
7289 {
7290 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
7291 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
7292 /* Find veneer symbol. */
7293 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 7294 errnode->u.b.veneer->u.v.id);
7295
99059e56
RM		 7296 myh = elf_link_hash_lookup
7297 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 7298
a504d23a
LA		 7299 if (myh == NULL)
7300 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7301 "`%s'"), abfd, tmp_name);
7302
7303 vma = myh->root.u.def.section->output_section->vma
7304 + myh->root.u.def.section->output_offset
7305 + myh->root.u.def.value;
7306
7307 errnode->u.b.veneer->vma = vma;
7308 break;
7309
7310 case VFP11_ERRATUM_ARM_VENEER:
7311 case VFP11_ERRATUM_THUMB_VENEER:
7312 /* Find return location. */
7313 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7314 errnode->u.v.id);
7315
7316 myh = elf_link_hash_lookup
7317 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7318
7319 if (myh == NULL)
7320 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7321 "`%s'"), abfd, tmp_name);
7322
7323 vma = myh->root.u.def.section->output_section->vma
7324 + myh->root.u.def.section->output_offset
7325 + myh->root.u.def.value;
7326
7327 errnode->u.v.branch->vma = vma;
7328 break;
7329
7330 default:
7331 abort ();
7332 }
7333 }
7334 }
7335
7336 free (tmp_name);
7337}
7338
7339/* Find virtual-memory addresses for STM32L4XX erratum veneers and
7340 return locations after sections have been laid out, using
7341 specially-named symbols. */
7342
7343void
7344bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
7345 struct bfd_link_info *link_info)
7346{
7347 asection *sec;
7348 struct elf32_arm_link_hash_table *globals;
7349 char *tmp_name;
7350
7351 if (bfd_link_relocatable (link_info))
7352 return;
7353
7354 /* Skip if this bfd does not correspond to an ELF image. */
7355 if (! is_arm_elf (abfd))
7356 return;
7357
7358 globals = elf32_arm_hash_table (link_info);
7359 if (globals == NULL)
7360 return;
7361
7362 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7363 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7364
7365 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7366 {
7367 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7368 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
7369
7370 for (; errnode != NULL; errnode = errnode->next)
7371 {
7372 struct elf_link_hash_entry *myh;
7373 bfd_vma vma;
7374
7375 switch (errnode->type)
7376 {
7377 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
7378 /* Find veneer symbol. */
7379 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7380 errnode->u.b.veneer->u.v.id);
7381
7382 myh = elf_link_hash_lookup
7383 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7384
7385 if (myh == NULL)
7386 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7387 "`%s'"), abfd, tmp_name);
7388
7389 vma = myh->root.u.def.section->output_section->vma
7390 + myh->root.u.def.section->output_offset
7391 + myh->root.u.def.value;
7392
7393 errnode->u.b.veneer->vma = vma;
7394 break;
7395
7396 case STM32L4XX_ERRATUM_VENEER:
7397 /* Find return location. */
7398 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7399 errnode->u.v.id);
7400
7401 myh = elf_link_hash_lookup
7402 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7403
7404 if (myh == NULL)
7405 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7406 "`%s'"), abfd, tmp_name);
7407
7408 vma = myh->root.u.def.section->output_section->vma
7409 + myh->root.u.def.section->output_offset
7410 + myh->root.u.def.value;
7411
7412 errnode->u.v.branch->vma = vma;
7413 break;
7414
7415 default:
7416 abort ();
7417 }
7418 }
7419 }
7420
7421 free (tmp_name);
7422}
7423
7424static inline bfd_boolean
7425is_thumb2_ldmia (const insn32 insn)
7426{
7427 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
7428 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
7429 return (insn & 0xffd02000) == 0xe8900000;
7430}
7431
7432static inline bfd_boolean
7433is_thumb2_ldmdb (const insn32 insn)
7434{
7435 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
7436 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
7437 return (insn & 0xffd02000) == 0xe9100000;
7438}
7439
7440static inline bfd_boolean
7441is_thumb2_vldm (const insn32 insn)
7442{
7443 /* A6.5 Extension register load or store instruction
7444 A7.7.229
7445 We look only for the 32-bit registers case since the DP (64-bit
7446 registers) are not supported for STM32L4XX
7447 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
7448 <list> is consecutive 32-bit registers
7449 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
7450 if P==0 && U==1 && W==1 && Rn=1101 VPOP
7451 if PUW=010 || PUW=011 || PUW=101 VLDM. */
7452 return
7453 ((insn & 0xfe100f00) == 0xec100a00)
7454 && /* (IA without !). */
7455 (((((insn << 7) >> 28) & 0xd) == 0x4)
7456 /* (IA with !), includes VPOP (when reg number is SP). */
7457 || ((((insn << 7) >> 28) & 0xd) == 0x5)
7458 /* (DB with !). */
7459 || ((((insn << 7) >> 28) & 0xd) == 0x9));
7460}
7461
7462/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
7463 VLDM opcode and:
7464 - computes the number and the mode of memory accesses
7465 - decides if the replacement should be done:
7466 . replaces only if > 8-word accesses
7467 . or (testing purposes only) replaces all accesses. */
7468
7469static bfd_boolean
7470stm32l4xx_need_create_replacing_stub (const insn32 insn,
7471 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
7472{
7473 int nb_regs = 0;
7474
7475 /* The field encoding the register list is the same for both LDMIA
7476 and LDMDB encodings. */
7477 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
7478 nb_regs = popcount (insn & 0x0000ffff);
7479 else if (is_thumb2_vldm (insn))
7480 nb_regs = (insn & 0xff);
7481
7482 /* DEFAULT mode accounts for the real bug condition situation,
7483 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
7484 return
7485 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_regs > 8 :
7486 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
7487}
7488
7489/* Look for potentially-troublesome code sequences which might trigger
7490 the STM STM32L4XX erratum. */
7491
7492bfd_boolean
7493bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
7494 struct bfd_link_info *link_info)
7495{
7496 asection *sec;
7497 bfd_byte *contents = NULL;
7498 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7499
7500 if (globals == NULL)
7501 return FALSE;
7502
7503 /* If we are only performing a partial link do not bother
7504 to construct any glue. */
7505 if (bfd_link_relocatable (link_info))
7506 return TRUE;
7507
7508 /* Skip if this bfd does not correspond to an ELF image. */
7509 if (! is_arm_elf (abfd))
7510 return TRUE;
7511
7512 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
7513 return TRUE;
7514
7515 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7516 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7517 return TRUE;
7518
7519 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7520 {
7521 unsigned int i, span;
7522 struct _arm_elf_section_data *sec_data;
7523
7524 /* If we don't have executable progbits, we're not interested in this
7525 section. Also skip if section is to be excluded. */
7526 if (elf_section_type (sec) != SHT_PROGBITS
7527 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7528 || (sec->flags & SEC_EXCLUDE) != 0
7529 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
7530 || sec->output_section == bfd_abs_section_ptr
7531 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
7532 continue;
7533
7534 sec_data = elf32_arm_section_data (sec);
c7b8f16e 7535
a504d23a
LA		 7536 if (sec_data->mapcount == 0)
7537 continue;
c7b8f16e 7538
a504d23a
LA		 7539 if (elf_section_data (sec)->this_hdr.contents != NULL)
7540 contents = elf_section_data (sec)->this_hdr.contents;
7541 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7542 goto error_return;
c7b8f16e 7543
a504d23a
LA		 7544 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7545 elf32_arm_compare_mapping);
c7b8f16e 7546
a504d23a
LA		 7547 for (span = 0; span < sec_data->mapcount; span++)
7548 {
7549 unsigned int span_start = sec_data->map[span].vma;
7550 unsigned int span_end = (span == sec_data->mapcount - 1)
7551 ? sec->size : sec_data->map[span + 1].vma;
7552 char span_type = sec_data->map[span].type;
7553 int itblock_current_pos = 0;
c7b8f16e 7554
a504d23a
LA		 7555 /* Only Thumb2 mode need be supported with this CM4 specific
7556 code, we should not encounter any arm mode eg span_type
7557 != 'a'. */
7558 if (span_type != 't')
7559 continue;
c7b8f16e 7560
a504d23a
LA		 7561 for (i = span_start; i < span_end;)
7562 {
7563 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
7564 bfd_boolean insn_32bit = FALSE;
7565 bfd_boolean is_ldm = FALSE;
7566 bfd_boolean is_vldm = FALSE;
7567 bfd_boolean is_not_last_in_it_block = FALSE;
7568
7569 /* The first 16-bits of all 32-bit thumb2 instructions start
7570 with opcode[15..13]=0b111 and the encoded op1 can be anything
7571 except opcode[12..11]!=0b00.
7572 See 32-bit Thumb instruction encoding. */
7573 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
7574 insn_32bit = TRUE;
c7b8f16e 7575
a504d23a
LA		 7576 /* Compute the predicate that tells if the instruction
7577 is concerned by the IT block
7578 - Creates an error if there is a ldm that is not
7579 last in the IT block thus cannot be replaced
7580 - Otherwise we can create a branch at the end of the
7581 IT block, it will be controlled naturally by IT
7582 with the proper pseudo-predicate
7583 - So the only interesting predicate is the one that
7584 tells that we are not on the last item of an IT
7585 block. */
7586 if (itblock_current_pos != 0)
7587 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 7588
a504d23a
LA		 7589 if (insn_32bit)
7590 {
7591 /* Load the rest of the insn (in manual-friendly order). */
7592 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
7593 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
7594 is_vldm = is_thumb2_vldm (insn);
7595
7596 /* Veneers are created for (v)ldm depending on
7597 option flags and memory accesses conditions; but
7598 if the instruction is not the last instruction of
7599 an IT block, we cannot create a jump there, so we
7600 bail out. */
7601 if ((is_ldm || is_vldm) &&
7602 stm32l4xx_need_create_replacing_stub
7603 (insn, globals->stm32l4xx_fix))
7604 {
7605 if (is_not_last_in_it_block)
7606 {
7607 (*_bfd_error_handler)
7608 /* Note - overlong line used here to allow for translation. */
7609 (_("\
7610%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
7611 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
7612 abfd, sec, (long)i);
7613 }
7614 else
7615 {
7616 elf32_stm32l4xx_erratum_list *newerr =
7617 (elf32_stm32l4xx_erratum_list *)
7618 bfd_zmalloc
7619 (sizeof (elf32_stm32l4xx_erratum_list));
7620
7621 elf32_arm_section_data (sec)
7622 ->stm32l4xx_erratumcount += 1;
7623 newerr->u.b.insn = insn;
7624 /* We create only thumb branches. */
7625 newerr->type =
7626 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
7627 record_stm32l4xx_erratum_veneer
7628 (link_info, newerr, abfd, sec,
7629 i,
7630 is_ldm ?
7631 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
7632 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
7633 newerr->vma = -1;
7634 newerr->next = sec_data->stm32l4xx_erratumlist;
7635 sec_data->stm32l4xx_erratumlist = newerr;
7636 }
7637 }
7638 }
7639 else
7640 {
7641 /* A7.7.37 IT p208
7642 IT blocks are only encoded in T1
7643 Encoding T1: IT{x{y{z}}} <firstcond>
7644 1 0 1 1 - 1 1 1 1 - firstcond - mask
7645 if mask = '0000' then see 'related encodings'
7646 We don't deal with UNPREDICTABLE, just ignore these.
7647 There can be no nested IT blocks so an IT block
7648 is naturally a new one for which it is worth
7649 computing its size. */
7650 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
7651 ((insn & 0x000f) != 0x0000);
7652 /* If we have a new IT block we compute its size. */
7653 if (is_newitblock)
7654 {
7655 /* Compute the number of instructions controlled
7656 by the IT block, it will be used to decide
7657 whether we are inside an IT block or not. */
7658 unsigned int mask = insn & 0x000f;
7659 itblock_current_pos = 4 - ctz (mask);
7660 }
7661 }
7662
7663 i += insn_32bit ? 4 : 2;
99059e56
RM		 7664 }
7665 }
a504d23a
LA		 7666
7667 if (contents != NULL
7668 && elf_section_data (sec)->this_hdr.contents != contents)
7669 free (contents);
7670 contents = NULL;
c7b8f16e 7671 }
906e58ca 7672
a504d23a
LA		 7673 return TRUE;
7674
7675error_return:
7676 if (contents != NULL
7677 && elf_section_data (sec)->this_hdr.contents != contents)
7678 free (contents);
c7b8f16e 7679
a504d23a
LA		 7680 return FALSE;
7681}
c7b8f16e 7682
eb043451
PB		 7683/* Set target relocation values needed during linking. */
7684
7685void
bf21ed78
MS		 7686bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
7687 struct bfd_link_info *link_info,
eb043451 7688 int target1_is_rel,
319850b4 7689 char * target2_type,
99059e56 7690 int fix_v4bx,
c7b8f16e 7691 int use_blx,
99059e56 7692 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 7693 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 7694 int no_enum_warn, int no_wchar_warn,
2de70689
MGD		 7695 int pic_veneer, int fix_cortex_a8,
7696 int fix_arm1176)
eb043451
PB		 7697{
7698 struct elf32_arm_link_hash_table *globals;
7699
7700 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7701 if (globals == NULL)
7702 return;
eb043451
PB		 7703
7704 globals->target1_is_rel = target1_is_rel;
7705 if (strcmp (target2_type, "rel") == 0)
7706 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 7707 else if (strcmp (target2_type, "abs") == 0)
7708 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 7709 else if (strcmp (target2_type, "got-rel") == 0)
7710 globals->target2_reloc = R_ARM_GOT_PREL;
7711 else
7712 {
7713 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
7714 target2_type);
7715 }
319850b4 7716 globals->fix_v4bx = fix_v4bx;
33bfe774 7717 globals->use_blx |= use_blx;
c7b8f16e 7718 globals->vfp11_fix = vfp11_fix;
a504d23a 7719 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 7720 globals->pic_veneer = pic_veneer;
48229727 7721 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 7722 globals->fix_arm1176 = fix_arm1176;
bf21ed78 7723
0ffa91dd
NC		 7724 BFD_ASSERT (is_arm_elf (output_bfd));
7725 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 7726 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 7727}
eb043451 7728
12a0a0fd 7729/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 7730
12a0a0fd
PB		 7731static void
7732insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
7733{
7734 bfd_vma upper;
7735 bfd_vma lower;
7736 int reloc_sign;
7737
7738 BFD_ASSERT ((offset & 1) == 0);
7739
7740 upper = bfd_get_16 (abfd, insn);
7741 lower = bfd_get_16 (abfd, insn + 2);
7742 reloc_sign = (offset < 0) ? 1 : 0;
7743 upper = (upper & ~(bfd_vma) 0x7ff)
7744 | ((offset >> 12) & 0x3ff)
7745 | (reloc_sign << 10);
906e58ca 7746 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 7747 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
7748 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
7749 | ((offset >> 1) & 0x7ff);
7750 bfd_put_16 (abfd, upper, insn);
7751 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 7752}
7753
9b485d32
NC		 7754/* Thumb code calling an ARM function. */
7755
252b5132 7756static int
57e8b36a
NC		 7757elf32_thumb_to_arm_stub (struct bfd_link_info * info,
7758 const char * name,
7759 bfd * input_bfd,
7760 bfd * output_bfd,
7761 asection * input_section,
7762 bfd_byte * hit_data,
7763 asection * sym_sec,
7764 bfd_vma offset,
7765 bfd_signed_vma addend,
f2a9dd69
DJ		 7766 bfd_vma val,
7767 char **error_message)
252b5132 7768{
bcbdc74c 7769 asection * s = 0;
dc810e39 7770 bfd_vma my_offset;
252b5132 7771 long int ret_offset;
bcbdc74c
NC		 7772 struct elf_link_hash_entry * myh;
7773 struct elf32_arm_link_hash_table * globals;
252b5132 7774
f2a9dd69 7775 myh = find_thumb_glue (info, name, error_message);
252b5132 7776 if (myh == NULL)
b34976b6 7777 return FALSE;
252b5132
RH		 7778
7779 globals = elf32_arm_hash_table (info);
252b5132
RH		 7780 BFD_ASSERT (globals != NULL);
7781 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7782
7783 my_offset = myh->root.u.def.value;
7784
3d4d4302
AM		 7785 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7786 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 7787
7788 BFD_ASSERT (s != NULL);
7789 BFD_ASSERT (s->contents != NULL);
7790 BFD_ASSERT (s->output_section != NULL);
7791
7792 if ((my_offset & 0x01) == 0x01)
7793 {
7794 if (sym_sec != NULL
7795 && sym_sec->owner != NULL
7796 && !INTERWORK_FLAG (sym_sec->owner))
7797 {
8f615d07 7798 (*_bfd_error_handler)
d003868e 7799 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 7800 " first occurrence: %B: Thumb call to ARM"),
d003868e 7801 sym_sec->owner, input_bfd, name);
252b5132 7802
b34976b6 7803 return FALSE;
252b5132
RH		 7804 }
7805
7806 --my_offset;
7807 myh->root.u.def.value = my_offset;
7808
52ab56c2
PB		 7809 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
7810 s->contents + my_offset);
252b5132 7811
52ab56c2
PB		 7812 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
7813 s->contents + my_offset + 2);
252b5132
RH		 7814
7815 ret_offset =
9b485d32
NC		 7816 /* Address of destination of the stub. */
7817 ((bfd_signed_vma) val)
252b5132 7818 - ((bfd_signed_vma)
57e8b36a
NC		 7819 /* Offset from the start of the current section
7820 to the start of the stubs. */
9b485d32
NC		 7821 (s->output_offset
7822 /* Offset of the start of this stub from the start of the stubs. */
7823 + my_offset
7824 /* Address of the start of the current section. */
7825 + s->output_section->vma)
7826 /* The branch instruction is 4 bytes into the stub. */
7827 + 4
7828 /* ARM branches work from the pc of the instruction + 8. */
7829 + 8);
252b5132 7830
52ab56c2
PB		 7831 put_arm_insn (globals, output_bfd,
7832 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
7833 s->contents + my_offset + 4);
252b5132
RH		 7834 }
7835
7836 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
7837
427bfd90
NC		 7838 /* Now go back and fix up the original BL insn to point to here. */
7839 ret_offset =
7840 /* Address of where the stub is located. */
7841 (s->output_section->vma + s->output_offset + my_offset)
7842 /* Address of where the BL is located. */
57e8b36a
NC		 7843 - (input_section->output_section->vma + input_section->output_offset
7844 + offset)
427bfd90
NC		 7845 /* Addend in the relocation. */
7846 - addend
7847 /* Biassing for PC-relative addressing. */
7848 - 8;
252b5132 7849
12a0a0fd 7850 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 7851
b34976b6 7852 return TRUE;
252b5132
RH		 7853}
7854
a4fd1a8e 7855/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 7856
a4fd1a8e
PB		 7857static struct elf_link_hash_entry *
7858elf32_arm_create_thumb_stub (struct bfd_link_info * info,
7859 const char * name,
7860 bfd * input_bfd,
7861 bfd * output_bfd,
7862 asection * sym_sec,
7863 bfd_vma val,
8029a119
NC		 7864 asection * s,
7865 char ** error_message)
252b5132 7866{
dc810e39 7867 bfd_vma my_offset;
252b5132 7868 long int ret_offset;
bcbdc74c
NC		 7869 struct elf_link_hash_entry * myh;
7870 struct elf32_arm_link_hash_table * globals;
252b5132 7871
f2a9dd69 7872 myh = find_arm_glue (info, name, error_message);
252b5132 7873 if (myh == NULL)
a4fd1a8e 7874 return NULL;
252b5132
RH		 7875
7876 globals = elf32_arm_hash_table (info);
252b5132
RH		 7877 BFD_ASSERT (globals != NULL);
7878 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7879
7880 my_offset = myh->root.u.def.value;
252b5132
RH		 7881
7882 if ((my_offset & 0x01) == 0x01)
7883 {
7884 if (sym_sec != NULL
7885 && sym_sec->owner != NULL
7886 && !INTERWORK_FLAG (sym_sec->owner))
7887 {
8f615d07 7888 (*_bfd_error_handler)
d003868e
AM		 7889 (_("%B(%s): warning: interworking not enabled.\n"
7890 " first occurrence: %B: arm call to thumb"),
7891 sym_sec->owner, input_bfd, name);
252b5132 7892 }
9b485d32 7893
252b5132
RH		 7894 --my_offset;
7895 myh->root.u.def.value = my_offset;
7896
0e1862bb
L		 7897 if (bfd_link_pic (info)
7898 || globals->root.is_relocatable_executable
27e55c4d 7899 || globals->pic_veneer)
8f6277f5
PB		 7900 {
7901 /* For relocatable objects we can't use absolute addresses,
7902 so construct the address from a relative offset. */
7903 /* TODO: If the offset is small it's probably worth
7904 constructing the address with adds. */
52ab56c2
PB		 7905 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
7906 s->contents + my_offset);
7907 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
7908 s->contents + my_offset + 4);
7909 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
7910 s->contents + my_offset + 8);
8f6277f5
PB		 7911 /* Adjust the offset by 4 for the position of the add,
7912 and 8 for the pipeline offset. */
7913 ret_offset = (val - (s->output_offset
7914 + s->output_section->vma
7915 + my_offset + 12))
7916 | 1;
7917 bfd_put_32 (output_bfd, ret_offset,
7918 s->contents + my_offset + 12);
7919 }
26079076
PB		 7920 else if (globals->use_blx)
7921 {
7922 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
7923 s->contents + my_offset);
7924
7925 /* It's a thumb address. Add the low order bit. */
7926 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
7927 s->contents + my_offset + 4);
7928 }
8f6277f5
PB		 7929 else
7930 {
52ab56c2
PB		 7931 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
7932 s->contents + my_offset);
252b5132 7933
52ab56c2
PB		 7934 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
7935 s->contents + my_offset + 4);
252b5132 7936
8f6277f5
PB		 7937 /* It's a thumb address. Add the low order bit. */
7938 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
7939 s->contents + my_offset + 8);
8029a119
NC		 7940
7941 my_offset += 12;
8f6277f5 7942 }
252b5132
RH		 7943 }
7944
7945 BFD_ASSERT (my_offset <= globals->arm_glue_size);
7946
a4fd1a8e
PB		 7947 return myh;
7948}
7949
7950/* Arm code calling a Thumb function. */
7951
7952static int
7953elf32_arm_to_thumb_stub (struct bfd_link_info * info,
7954 const char * name,
7955 bfd * input_bfd,
7956 bfd * output_bfd,
7957 asection * input_section,
7958 bfd_byte * hit_data,
7959 asection * sym_sec,
7960 bfd_vma offset,
7961 bfd_signed_vma addend,
f2a9dd69
DJ		 7962 bfd_vma val,
7963 char **error_message)
a4fd1a8e
PB		 7964{
7965 unsigned long int tmp;
7966 bfd_vma my_offset;
7967 asection * s;
7968 long int ret_offset;
7969 struct elf_link_hash_entry * myh;
7970 struct elf32_arm_link_hash_table * globals;
7971
7972 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 7973 BFD_ASSERT (globals != NULL);
7974 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7975
3d4d4302
AM		 7976 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7977 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 7978 BFD_ASSERT (s != NULL);
7979 BFD_ASSERT (s->contents != NULL);
7980 BFD_ASSERT (s->output_section != NULL);
7981
7982 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 7983 sym_sec, val, s, error_message);
a4fd1a8e
PB		 7984 if (!myh)
7985 return FALSE;
7986
7987 my_offset = myh->root.u.def.value;
252b5132
RH		 7988 tmp = bfd_get_32 (input_bfd, hit_data);
7989 tmp = tmp & 0xFF000000;
7990
9b485d32 7991 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 7992 ret_offset = (s->output_offset
7993 + my_offset
7994 + s->output_section->vma
7995 - (input_section->output_offset
7996 + input_section->output_section->vma
7997 + offset + addend)
7998 - 8);
9a5aca8c 7999
252b5132
RH		 8000 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
8001
dc810e39 8002 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 8003
b34976b6 8004 return TRUE;
252b5132
RH		 8005}
8006
a4fd1a8e
PB		 8007/* Populate Arm stub for an exported Thumb function. */
8008
8009static bfd_boolean
8010elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
8011{
8012 struct bfd_link_info * info = (struct bfd_link_info *) inf;
8013 asection * s;
8014 struct elf_link_hash_entry * myh;
8015 struct elf32_arm_link_hash_entry *eh;
8016 struct elf32_arm_link_hash_table * globals;
8017 asection *sec;
8018 bfd_vma val;
f2a9dd69 8019 char *error_message;
a4fd1a8e 8020
906e58ca 8021 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 8022 /* Allocate stubs for exported Thumb functions on v4t. */
8023 if (eh->export_glue == NULL)
8024 return TRUE;
8025
8026 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8027 BFD_ASSERT (globals != NULL);
8028 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8029
3d4d4302
AM		 8030 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8031 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8032 BFD_ASSERT (s != NULL);
8033 BFD_ASSERT (s->contents != NULL);
8034 BFD_ASSERT (s->output_section != NULL);
8035
8036 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 8037
8038 BFD_ASSERT (sec->output_section != NULL);
8039
a4fd1a8e
PB		 8040 val = eh->export_glue->root.u.def.value + sec->output_offset
8041 + sec->output_section->vma;
8029a119 8042
a4fd1a8e
PB		 8043 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
8044 h->root.u.def.section->owner,
f2a9dd69
DJ		 8045 globals->obfd, sec, val, s,
8046 &error_message);
a4fd1a8e
PB		 8047 BFD_ASSERT (myh);
8048 return TRUE;
8049}
8050
845b51d6
PB		 8051/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
8052
8053static bfd_vma
8054elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
8055{
8056 bfd_byte *p;
8057 bfd_vma glue_addr;
8058 asection *s;
8059 struct elf32_arm_link_hash_table *globals;
8060
8061 globals = elf32_arm_hash_table (info);
845b51d6
PB		 8062 BFD_ASSERT (globals != NULL);
8063 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8064
3d4d4302
AM		 8065 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8066 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 8067 BFD_ASSERT (s != NULL);
8068 BFD_ASSERT (s->contents != NULL);
8069 BFD_ASSERT (s->output_section != NULL);
8070
8071 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
8072
8073 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
8074
8075 if ((globals->bx_glue_offset[reg] & 1) == 0)
8076 {
8077 p = s->contents + glue_addr;
8078 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
8079 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
8080 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
8081 globals->bx_glue_offset[reg] |= 1;
8082 }
8083
8084 return glue_addr + s->output_section->vma + s->output_offset;
8085}
8086
a4fd1a8e
PB		 8087/* Generate Arm stubs for exported Thumb symbols. */
8088static void
906e58ca 8089elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 8090 struct bfd_link_info *link_info)
8091{
8092 struct elf32_arm_link_hash_table * globals;
8093
8029a119
NC		 8094 if (link_info == NULL)
8095 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 8096 return;
8097
8098 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8099 if (globals == NULL)
8100 return;
8101
84c08195
PB		 8102 /* If blx is available then exported Thumb symbols are OK and there is
8103 nothing to do. */
a4fd1a8e
PB		 8104 if (globals->use_blx)
8105 return;
8106
8107 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
8108 link_info);
8109}
8110
47beaa6a
RS		 8111/* Reserve space for COUNT dynamic relocations in relocation selection
8112 SRELOC. */
8113
8114static void
8115elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
8116 bfd_size_type count)
8117{
8118 struct elf32_arm_link_hash_table *htab;
8119
8120 htab = elf32_arm_hash_table (info);
8121 BFD_ASSERT (htab->root.dynamic_sections_created);
8122 if (sreloc == NULL)
8123 abort ();
8124 sreloc->size += RELOC_SIZE (htab) * count;
8125}
8126
34e77a92
RS		 8127/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8128 dynamic, the relocations should go in SRELOC, otherwise they should
8129 go in the special .rel.iplt section. */
8130
8131static void
8132elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
8133 bfd_size_type count)
8134{
8135 struct elf32_arm_link_hash_table *htab;
8136
8137 htab = elf32_arm_hash_table (info);
8138 if (!htab->root.dynamic_sections_created)
8139 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
8140 else
8141 {
8142 BFD_ASSERT (sreloc != NULL);
8143 sreloc->size += RELOC_SIZE (htab) * count;
8144 }
8145}
8146
47beaa6a
RS		 8147/* Add relocation REL to the end of relocation section SRELOC. */
8148
8149static void
8150elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
8151 asection *sreloc, Elf_Internal_Rela *rel)
8152{
8153 bfd_byte *loc;
8154 struct elf32_arm_link_hash_table *htab;
8155
8156 htab = elf32_arm_hash_table (info);
34e77a92
RS		 8157 if (!htab->root.dynamic_sections_created
8158 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
8159 sreloc = htab->root.irelplt;
47beaa6a
RS		 8160 if (sreloc == NULL)
8161 abort ();
8162 loc = sreloc->contents;
8163 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
8164 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
8165 abort ();
8166 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
8167}
8168
34e77a92
RS		 8169/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8170 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8171 to .plt. */
8172
8173static void
8174elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
8175 bfd_boolean is_iplt_entry,
8176 union gotplt_union *root_plt,
8177 struct arm_plt_info *arm_plt)
8178{
8179 struct elf32_arm_link_hash_table *htab;
8180 asection *splt;
8181 asection *sgotplt;
8182
8183 htab = elf32_arm_hash_table (info);
8184
8185 if (is_iplt_entry)
8186 {
8187 splt = htab->root.iplt;
8188 sgotplt = htab->root.igotplt;
8189
99059e56
RM		 8190 /* NaCl uses a special first entry in .iplt too. */
8191 if (htab->nacl_p && splt->size == 0)
8192 splt->size += htab->plt_header_size;
8193
34e77a92
RS		 8194 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8195 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
8196 }
8197 else
8198 {
8199 splt = htab->root.splt;
8200 sgotplt = htab->root.sgotplt;
8201
8202 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8203 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
8204
8205 /* If this is the first .plt entry, make room for the special
8206 first entry. */
8207 if (splt->size == 0)
8208 splt->size += htab->plt_header_size;
9f19ab6d
WN		 8209
8210 htab->next_tls_desc_index++;
34e77a92
RS		 8211 }
8212
8213 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8214 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8215 splt->size += PLT_THUMB_STUB_SIZE;
8216 root_plt->offset = splt->size;
8217 splt->size += htab->plt_entry_size;
8218
8219 if (!htab->symbian_p)
8220 {
8221 /* We also need to make an entry in the .got.plt section, which
8222 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 8223 if (is_iplt_entry)
8224 arm_plt->got_offset = sgotplt->size;
8225 else
8226 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 8227 sgotplt->size += 4;
8228 }
8229}
8230
b38cadfb
NC		 8231static bfd_vma
8232arm_movw_immediate (bfd_vma value)
8233{
8234 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
8235}
8236
8237static bfd_vma
8238arm_movt_immediate (bfd_vma value)
8239{
8240 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
8241}
8242
34e77a92
RS		 8243/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8244 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8245 Otherwise, DYNINDX is the index of the symbol in the dynamic
8246 symbol table and SYM_VALUE is undefined.
8247
8248 ROOT_PLT points to the offset of the PLT entry from the start of its
8249 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 8250 bookkeeping information.
34e77a92 8251
57460bcf
NC		 8252 Returns FALSE if there was a problem. */
8253
8254static bfd_boolean
34e77a92
RS		 8255elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
8256 union gotplt_union *root_plt,
8257 struct arm_plt_info *arm_plt,
8258 int dynindx, bfd_vma sym_value)
8259{
8260 struct elf32_arm_link_hash_table *htab;
8261 asection *sgot;
8262 asection *splt;
8263 asection *srel;
8264 bfd_byte *loc;
8265 bfd_vma plt_index;
8266 Elf_Internal_Rela rel;
8267 bfd_vma plt_header_size;
8268 bfd_vma got_header_size;
8269
8270 htab = elf32_arm_hash_table (info);
8271
8272 /* Pick the appropriate sections and sizes. */
8273 if (dynindx == -1)
8274 {
8275 splt = htab->root.iplt;
8276 sgot = htab->root.igotplt;
8277 srel = htab->root.irelplt;
8278
8279 /* There are no reserved entries in .igot.plt, and no special
8280 first entry in .iplt. */
8281 got_header_size = 0;
8282 plt_header_size = 0;
8283 }
8284 else
8285 {
8286 splt = htab->root.splt;
8287 sgot = htab->root.sgotplt;
8288 srel = htab->root.srelplt;
8289
8290 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
8291 plt_header_size = htab->plt_header_size;
8292 }
8293 BFD_ASSERT (splt != NULL && srel != NULL);
8294
8295 /* Fill in the entry in the procedure linkage table. */
8296 if (htab->symbian_p)
8297 {
8298 BFD_ASSERT (dynindx >= 0);
8299 put_arm_insn (htab, output_bfd,
8300 elf32_arm_symbian_plt_entry[0],
8301 splt->contents + root_plt->offset);
8302 bfd_put_32 (output_bfd,
8303 elf32_arm_symbian_plt_entry[1],
8304 splt->contents + root_plt->offset + 4);
8305
8306 /* Fill in the entry in the .rel.plt section. */
8307 rel.r_offset = (splt->output_section->vma
8308 + splt->output_offset
8309 + root_plt->offset + 4);
8310 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
8311
8312 /* Get the index in the procedure linkage table which
8313 corresponds to this symbol. This is the index of this symbol
8314 in all the symbols for which we are making plt entries. The
8315 first entry in the procedure linkage table is reserved. */
8316 plt_index = ((root_plt->offset - plt_header_size)
8317 / htab->plt_entry_size);
8318 }
8319 else
8320 {
8321 bfd_vma got_offset, got_address, plt_address;
8322 bfd_vma got_displacement, initial_got_entry;
8323 bfd_byte * ptr;
8324
8325 BFD_ASSERT (sgot != NULL);
8326
8327 /* Get the offset into the .(i)got.plt table of the entry that
8328 corresponds to this function. */
8329 got_offset = (arm_plt->got_offset & -2);
8330
8331 /* Get the index in the procedure linkage table which
8332 corresponds to this symbol. This is the index of this symbol
8333 in all the symbols for which we are making plt entries.
8334 After the reserved .got.plt entries, all symbols appear in
8335 the same order as in .plt. */
8336 plt_index = (got_offset - got_header_size) / 4;
8337
8338 /* Calculate the address of the GOT entry. */
8339 got_address = (sgot->output_section->vma
8340 + sgot->output_offset
8341 + got_offset);
8342
8343 /* ...and the address of the PLT entry. */
8344 plt_address = (splt->output_section->vma
8345 + splt->output_offset
8346 + root_plt->offset);
8347
8348 ptr = splt->contents + root_plt->offset;
0e1862bb 8349 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 8350 {
8351 unsigned int i;
8352 bfd_vma val;
8353
8354 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8355 {
8356 val = elf32_arm_vxworks_shared_plt_entry[i];
8357 if (i == 2)
8358 val |= got_address - sgot->output_section->vma;
8359 if (i == 5)
8360 val |= plt_index * RELOC_SIZE (htab);
8361 if (i == 2 || i == 5)
8362 bfd_put_32 (output_bfd, val, ptr);
8363 else
8364 put_arm_insn (htab, output_bfd, val, ptr);
8365 }
8366 }
8367 else if (htab->vxworks_p)
8368 {
8369 unsigned int i;
8370 bfd_vma val;
8371
8372 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8373 {
8374 val = elf32_arm_vxworks_exec_plt_entry[i];
8375 if (i == 2)
8376 val |= got_address;
8377 if (i == 4)
8378 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
8379 if (i == 5)
8380 val |= plt_index * RELOC_SIZE (htab);
8381 if (i == 2 || i == 5)
8382 bfd_put_32 (output_bfd, val, ptr);
8383 else
8384 put_arm_insn (htab, output_bfd, val, ptr);
8385 }
8386
8387 loc = (htab->srelplt2->contents
8388 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
8389
8390 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
8391 referencing the GOT for this PLT entry. */
8392 rel.r_offset = plt_address + 8;
8393 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
8394 rel.r_addend = got_offset;
8395 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8396 loc += RELOC_SIZE (htab);
8397
8398 /* Create the R_ARM_ABS32 relocation referencing the
8399 beginning of the PLT for this GOT entry. */
8400 rel.r_offset = got_address;
8401 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
8402 rel.r_addend = 0;
8403 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8404 }
b38cadfb
NC		 8405 else if (htab->nacl_p)
8406 {
8407 /* Calculate the displacement between the PLT slot and the
8408 common tail that's part of the special initial PLT slot. */
6034aab8 8409 int32_t tail_displacement
b38cadfb
NC		 8410 = ((splt->output_section->vma + splt->output_offset
8411 + ARM_NACL_PLT_TAIL_OFFSET)
8412 - (plt_address + htab->plt_entry_size + 4));
8413 BFD_ASSERT ((tail_displacement & 3) == 0);
8414 tail_displacement >>= 2;
8415
8416 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
8417 || (-tail_displacement & 0xff000000) == 0);
8418
8419 /* Calculate the displacement between the PLT slot and the entry
8420 in the GOT. The offset accounts for the value produced by
8421 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 8422 got_displacement = (got_address
99059e56 8423 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 8424
8425 /* NaCl does not support interworking at all. */
8426 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
8427
8428 put_arm_insn (htab, output_bfd,
8429 elf32_arm_nacl_plt_entry[0]
8430 | arm_movw_immediate (got_displacement),
8431 ptr + 0);
8432 put_arm_insn (htab, output_bfd,
8433 elf32_arm_nacl_plt_entry[1]
8434 | arm_movt_immediate (got_displacement),
8435 ptr + 4);
8436 put_arm_insn (htab, output_bfd,
8437 elf32_arm_nacl_plt_entry[2],
8438 ptr + 8);
8439 put_arm_insn (htab, output_bfd,
8440 elf32_arm_nacl_plt_entry[3]
8441 | (tail_displacement & 0x00ffffff),
8442 ptr + 12);
8443 }
57460bcf
NC		 8444 else if (using_thumb_only (htab))
8445 {
eed94f8f 8446 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 8447 if (!using_thumb2 (htab))
eed94f8f
NC		 8448 {
8449 /* FIXME: We ought to be able to generate thumb-1 PLT
8450 instructions... */
8451 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
8452 output_bfd);
8453 return FALSE;
8454 }
57460bcf 8455
eed94f8f
NC		 8456 /* Calculate the displacement between the PLT slot and the entry in
8457 the GOT. The 12-byte offset accounts for the value produced by
8458 adding to pc in the 3rd instruction of the PLT stub. */
8459 got_displacement = got_address - (plt_address + 12);
8460
8461 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
8462 instead of 'put_thumb_insn'. */
8463 put_arm_insn (htab, output_bfd,
8464 elf32_thumb2_plt_entry[0]
8465 | ((got_displacement & 0x000000ff) << 16)
8466 | ((got_displacement & 0x00000700) << 20)
8467 | ((got_displacement & 0x00000800) >> 1)
8468 | ((got_displacement & 0x0000f000) >> 12),
8469 ptr + 0);
8470 put_arm_insn (htab, output_bfd,
8471 elf32_thumb2_plt_entry[1]
8472 | ((got_displacement & 0x00ff0000) )
8473 | ((got_displacement & 0x07000000) << 4)
8474 | ((got_displacement & 0x08000000) >> 17)
8475 | ((got_displacement & 0xf0000000) >> 28),
8476 ptr + 4);
8477 put_arm_insn (htab, output_bfd,
8478 elf32_thumb2_plt_entry[2],
8479 ptr + 8);
8480 put_arm_insn (htab, output_bfd,
8481 elf32_thumb2_plt_entry[3],
8482 ptr + 12);
57460bcf 8483 }
34e77a92
RS		 8484 else
8485 {
8486 /* Calculate the displacement between the PLT slot and the
8487 entry in the GOT. The eight-byte offset accounts for the
8488 value produced by adding to pc in the first instruction
8489 of the PLT stub. */
8490 got_displacement = got_address - (plt_address + 8);
8491
34e77a92
RS		 8492 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8493 {
8494 put_thumb_insn (htab, output_bfd,
8495 elf32_arm_plt_thumb_stub[0], ptr - 4);
8496 put_thumb_insn (htab, output_bfd,
8497 elf32_arm_plt_thumb_stub[1], ptr - 2);
8498 }
8499
1db37fe6
YG		 8500 if (!elf32_arm_use_long_plt_entry)
8501 {
8502 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
8503
8504 put_arm_insn (htab, output_bfd,
8505 elf32_arm_plt_entry_short[0]
8506 | ((got_displacement & 0x0ff00000) >> 20),
8507 ptr + 0);
8508 put_arm_insn (htab, output_bfd,
8509 elf32_arm_plt_entry_short[1]
8510 | ((got_displacement & 0x000ff000) >> 12),
8511 ptr+ 4);
8512 put_arm_insn (htab, output_bfd,
8513 elf32_arm_plt_entry_short[2]
8514 | (got_displacement & 0x00000fff),
8515 ptr + 8);
34e77a92 8516#ifdef FOUR_WORD_PLT
1db37fe6 8517 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 8518#endif
1db37fe6
YG		 8519 }
8520 else
8521 {
8522 put_arm_insn (htab, output_bfd,
8523 elf32_arm_plt_entry_long[0]
8524 | ((got_displacement & 0xf0000000) >> 28),
8525 ptr + 0);
8526 put_arm_insn (htab, output_bfd,
8527 elf32_arm_plt_entry_long[1]
8528 | ((got_displacement & 0x0ff00000) >> 20),
8529 ptr + 4);
8530 put_arm_insn (htab, output_bfd,
8531 elf32_arm_plt_entry_long[2]
8532 | ((got_displacement & 0x000ff000) >> 12),
8533 ptr+ 8);
8534 put_arm_insn (htab, output_bfd,
8535 elf32_arm_plt_entry_long[3]
8536 | (got_displacement & 0x00000fff),
8537 ptr + 12);
8538 }
34e77a92
RS		 8539 }
8540
8541 /* Fill in the entry in the .rel(a).(i)plt section. */
8542 rel.r_offset = got_address;
8543 rel.r_addend = 0;
8544 if (dynindx == -1)
8545 {
8546 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
8547 The dynamic linker or static executable then calls SYM_VALUE
8548 to determine the correct run-time value of the .igot.plt entry. */
8549 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
8550 initial_got_entry = sym_value;
8551 }
8552 else
8553 {
8554 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
8555 initial_got_entry = (splt->output_section->vma
8556 + splt->output_offset);
8557 }
8558
8559 /* Fill in the entry in the global offset table. */
8560 bfd_put_32 (output_bfd, initial_got_entry,
8561 sgot->contents + got_offset);
8562 }
8563
aba8c3de
WN		 8564 if (dynindx == -1)
8565 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
8566 else
8567 {
8568 loc = srel->contents + plt_index * RELOC_SIZE (htab);
8569 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8570 }
57460bcf
NC		 8571
8572 return TRUE;
34e77a92
RS		 8573}
8574
eb043451
PB		 8575/* Some relocations map to different relocations depending on the
8576 target. Return the real relocation. */
8029a119 8577
eb043451
PB		 8578static int
8579arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
8580 int r_type)
8581{
8582 switch (r_type)
8583 {
8584 case R_ARM_TARGET1:
8585 if (globals->target1_is_rel)
8586 return R_ARM_REL32;
8587 else
8588 return R_ARM_ABS32;
8589
8590 case R_ARM_TARGET2:
8591 return globals->target2_reloc;
8592
8593 default:
8594 return r_type;
8595 }
8596}
eb043451 8597
ba93b8ac
DJ		 8598/* Return the base VMA address which should be subtracted from real addresses
8599 when resolving @dtpoff relocation.
8600 This is PT_TLS segment p_vaddr. */
8601
8602static bfd_vma
8603dtpoff_base (struct bfd_link_info *info)
8604{
8605 /* If tls_sec is NULL, we should have signalled an error already. */
8606 if (elf_hash_table (info)->tls_sec == NULL)
8607 return 0;
8608 return elf_hash_table (info)->tls_sec->vma;
8609}
8610
8611/* Return the relocation value for @tpoff relocation
8612 if STT_TLS virtual address is ADDRESS. */
8613
8614static bfd_vma
8615tpoff (struct bfd_link_info *info, bfd_vma address)
8616{
8617 struct elf_link_hash_table *htab = elf_hash_table (info);
8618 bfd_vma base;
8619
8620 /* If tls_sec is NULL, we should have signalled an error already. */
8621 if (htab->tls_sec == NULL)
8622 return 0;
8623 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
8624 return address - htab->tls_sec->vma + base;
8625}
8626
00a97672
RS		 8627/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
8628 VALUE is the relocation value. */
8629
8630static bfd_reloc_status_type
8631elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
8632{
8633 if (value > 0xfff)
8634 return bfd_reloc_overflow;
8635
8636 value |= bfd_get_32 (abfd, data) & 0xfffff000;
8637 bfd_put_32 (abfd, value, data);
8638 return bfd_reloc_ok;
8639}
8640
0855e32b
NS		 8641/* Handle TLS relaxations. Relaxing is possible for symbols that use
8642 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
8643 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
8644
8645 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
8646 is to then call final_link_relocate. Return other values in the
62672b10
NS		 8647 case of error.
8648
8649 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
8650 the pre-relaxed code. It would be nice if the relocs were updated
8651 to match the optimization. */
0855e32b 8652
b38cadfb 8653static bfd_reloc_status_type
0855e32b 8654elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 8655 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 8656 Elf_Internal_Rela *rel, unsigned long is_local)
8657{
8658 unsigned long insn;
b38cadfb 8659
0855e32b
NS		 8660 switch (ELF32_R_TYPE (rel->r_info))
8661 {
8662 default:
8663 return bfd_reloc_notsupported;
b38cadfb 8664
0855e32b
NS		 8665 case R_ARM_TLS_GOTDESC:
8666 if (is_local)
8667 insn = 0;
8668 else
8669 {
8670 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8671 if (insn & 1)
8672 insn -= 5; /* THUMB */
8673 else
8674 insn -= 8; /* ARM */
8675 }
8676 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8677 return bfd_reloc_continue;
8678
8679 case R_ARM_THM_TLS_DESCSEQ:
8680 /* Thumb insn. */
8681 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
8682 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
8683 {
8684 if (is_local)
8685 /* nop */
8686 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8687 }
8688 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
8689 {
8690 if (is_local)
8691 /* nop */
8692 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8693 else
8694 /* ldr rx,[ry] */
8695 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
8696 }
8697 else if ((insn & 0xff87) == 0x4780) /* blx rx */
8698 {
8699 if (is_local)
8700 /* nop */
8701 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8702 else
8703 /* mov r0, rx */
8704 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
8705 contents + rel->r_offset);
8706 }
8707 else
8708 {
8709 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
8710 /* It's a 32 bit instruction, fetch the rest of it for
8711 error generation. */
8712 insn = (insn << 16)
8713 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
8714 (*_bfd_error_handler)
8715 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
8716 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8717 return bfd_reloc_notsupported;
8718 }
8719 break;
b38cadfb 8720
0855e32b
NS		 8721 case R_ARM_TLS_DESCSEQ:
8722 /* arm insn. */
8723 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8724 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
8725 {
8726 if (is_local)
8727 /* mov rx, ry */
8728 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
8729 contents + rel->r_offset);
8730 }
8731 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
8732 {
8733 if (is_local)
8734 /* nop */
8735 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8736 else
8737 /* ldr rx,[ry] */
8738 bfd_put_32 (input_bfd, insn & 0xfffff000,
8739 contents + rel->r_offset);
8740 }
8741 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
8742 {
8743 if (is_local)
8744 /* nop */
8745 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8746 else
8747 /* mov r0, rx */
8748 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
8749 contents + rel->r_offset);
8750 }
8751 else
8752 {
8753 (*_bfd_error_handler)
8754 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
8755 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8756 return bfd_reloc_notsupported;
8757 }
8758 break;
8759
8760 case R_ARM_TLS_CALL:
8761 /* GD->IE relaxation, turn the instruction into 'nop' or
8762 'ldr r0, [pc,r0]' */
8763 insn = is_local ? 0xe1a00000 : 0xe79f0000;
8764 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8765 break;
b38cadfb 8766
0855e32b 8767 case R_ARM_THM_TLS_CALL:
6a631e86 8768 /* GD->IE relaxation. */
0855e32b
NS		 8769 if (!is_local)
8770 /* add r0,pc; ldr r0, [r0] */
8771 insn = 0x44786800;
8772 else if (arch_has_thumb2_nop (globals))
8773 /* nop.w */
8774 insn = 0xf3af8000;
8775 else
8776 /* nop; nop */
8777 insn = 0xbf00bf00;
b38cadfb 8778
0855e32b
NS		 8779 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
8780 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
8781 break;
8782 }
8783 return bfd_reloc_ok;
8784}
8785
4962c51a
MS		 8786/* For a given value of n, calculate the value of G_n as required to
8787 deal with group relocations. We return it in the form of an
8788 encoded constant-and-rotation, together with the final residual. If n is
8789 specified as less than zero, then final_residual is filled with the
8790 input value and no further action is performed. */
8791
8792static bfd_vma
8793calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
8794{
8795 int current_n;
8796 bfd_vma g_n;
8797 bfd_vma encoded_g_n = 0;
8798 bfd_vma residual = value; /* Also known as Y_n. */
8799
8800 for (current_n = 0; current_n <= n; current_n++)
8801 {
8802 int shift;
8803
8804 /* Calculate which part of the value to mask. */
8805 if (residual == 0)
99059e56 8806 shift = 0;
4962c51a 8807 else
99059e56
RM		 8808 {
8809 int msb;
8810
8811 /* Determine the most significant bit in the residual and
8812 align the resulting value to a 2-bit boundary. */
8813 for (msb = 30; msb >= 0; msb -= 2)
8814 if (residual & (3 << msb))
8815 break;
8816
8817 /* The desired shift is now (msb - 6), or zero, whichever
8818 is the greater. */
8819 shift = msb - 6;
8820 if (shift < 0)
8821 shift = 0;
8822 }
4962c51a
MS		 8823
8824 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
8825 g_n = residual & (0xff << shift);
8826 encoded_g_n = (g_n >> shift)
99059e56 8827 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 8828
8829 /* Calculate the residual for the next time around. */
8830 residual &= ~g_n;
8831 }
8832
8833 *final_residual = residual;
8834
8835 return encoded_g_n;
8836}
8837
8838/* Given an ARM instruction, determine whether it is an ADD or a SUB.
8839 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 8840
4962c51a 8841static int
906e58ca 8842identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 8843{
8844 int opcode = insn & 0x1e00000;
8845
8846 if (opcode == 1 << 23) /* ADD */
8847 return 1;
8848
8849 if (opcode == 1 << 22) /* SUB */
8850 return -1;
8851
8852 return 0;
8853}
8854
252b5132 8855/* Perform a relocation as part of a final link. */
9b485d32 8856
252b5132 8857static bfd_reloc_status_type
57e8b36a
NC		 8858elf32_arm_final_link_relocate (reloc_howto_type * howto,
8859 bfd * input_bfd,
8860 bfd * output_bfd,
8861 asection * input_section,
8862 bfd_byte * contents,
8863 Elf_Internal_Rela * rel,
8864 bfd_vma value,
8865 struct bfd_link_info * info,
8866 asection * sym_sec,
8867 const char * sym_name,
34e77a92
RS		 8868 unsigned char st_type,
8869 enum arm_st_branch_type branch_type,
0945cdfd 8870 struct elf_link_hash_entry * h,
f2a9dd69 8871 bfd_boolean * unresolved_reloc_p,
8029a119 8872 char ** error_message)
252b5132
RH		 8873{
8874 unsigned long r_type = howto->type;
8875 unsigned long r_symndx;
8876 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 8877 bfd_vma * local_got_offsets;
0855e32b 8878 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 8879 asection * sgot;
8880 asection * splt;
252b5132 8881 asection * sreloc = NULL;
362d30a1 8882 asection * srelgot;
252b5132 8883 bfd_vma addend;
ba96a88f 8884 bfd_signed_vma signed_addend;
34e77a92
RS		 8885 unsigned char dynreloc_st_type;
8886 bfd_vma dynreloc_value;
ba96a88f 8887 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 8888 struct elf32_arm_link_hash_entry *eh;
8889 union gotplt_union *root_plt;
8890 struct arm_plt_info *arm_plt;
8891 bfd_vma plt_offset;
8892 bfd_vma gotplt_offset;
8893 bfd_boolean has_iplt_entry;
f21f3fe0 8894
9c504268 8895 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 8896 if (globals == NULL)
8897 return bfd_reloc_notsupported;
9c504268 8898
0ffa91dd
NC		 8899 BFD_ASSERT (is_arm_elf (input_bfd));
8900
8901 /* Some relocation types map to different relocations depending on the
9c504268 8902 target. We pick the right one here. */
eb043451 8903 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 8904
8905 /* It is possible to have linker relaxations on some TLS access
8906 models. Update our information here. */
8907 r_type = elf32_arm_tls_transition (info, r_type, h);
8908
eb043451
PB		 8909 if (r_type != howto->type)
8910 howto = elf32_arm_howto_from_type (r_type);
9c504268 8911
34e77a92 8912 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 8913 sgot = globals->root.sgot;
252b5132 8914 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 8915 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
8916
34e77a92
RS		 8917 if (globals->root.dynamic_sections_created)
8918 srelgot = globals->root.srelgot;
8919 else
8920 srelgot = NULL;
8921
252b5132
RH		 8922 r_symndx = ELF32_R_SYM (rel->r_info);
8923
4e7fd91e 8924 if (globals->use_rel)
ba96a88f 8925 {
4e7fd91e
PB		 8926 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
8927
8928 if (addend & ((howto->src_mask + 1) >> 1))
8929 {
8930 signed_addend = -1;
8931 signed_addend &= ~ howto->src_mask;
8932 signed_addend |= addend;
8933 }
8934 else
8935 signed_addend = addend;
ba96a88f
NC		 8936 }
8937 else
4e7fd91e 8938 addend = signed_addend = rel->r_addend;
f21f3fe0 8939
39f21624
NC		 8940 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
8941 are resolving a function call relocation. */
8942 if (using_thumb_only (globals)
8943 && (r_type == R_ARM_THM_CALL
8944 || r_type == R_ARM_THM_JUMP24)
8945 && branch_type == ST_BRANCH_TO_ARM)
8946 branch_type = ST_BRANCH_TO_THUMB;
8947
34e77a92
RS		 8948 /* Record the symbol information that should be used in dynamic
8949 relocations. */
8950 dynreloc_st_type = st_type;
8951 dynreloc_value = value;
8952 if (branch_type == ST_BRANCH_TO_THUMB)
8953 dynreloc_value |= 1;
8954
8955 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8956 VALUE appropriately for relocations that we resolve at link time. */
8957 has_iplt_entry = FALSE;
8958 if (elf32_arm_get_plt_info (input_bfd, eh, r_symndx, &root_plt, &arm_plt)
8959 && root_plt->offset != (bfd_vma) -1)
8960 {
8961 plt_offset = root_plt->offset;
8962 gotplt_offset = arm_plt->got_offset;
8963
8964 if (h == NULL || eh->is_iplt)
8965 {
8966 has_iplt_entry = TRUE;
8967 splt = globals->root.iplt;
8968
8969 /* Populate .iplt entries here, because not all of them will
8970 be seen by finish_dynamic_symbol. The lower bit is set if
8971 we have already populated the entry. */
8972 if (plt_offset & 1)
8973 plt_offset--;
8974 else
8975 {
57460bcf
NC		 8976 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
8977 -1, dynreloc_value))
8978 root_plt->offset |= 1;
8979 else
8980 return bfd_reloc_notsupported;
34e77a92
RS		 8981 }
8982
8983 /* Static relocations always resolve to the .iplt entry. */
8984 st_type = STT_FUNC;
8985 value = (splt->output_section->vma
8986 + splt->output_offset
8987 + plt_offset);
8988 branch_type = ST_BRANCH_TO_ARM;
8989
8990 /* If there are non-call relocations that resolve to the .iplt
8991 entry, then all dynamic ones must too. */
8992 if (arm_plt->noncall_refcount != 0)
8993 {
8994 dynreloc_st_type = st_type;
8995 dynreloc_value = value;
8996 }
8997 }
8998 else
8999 /* We populate the .plt entry in finish_dynamic_symbol. */
9000 splt = globals->root.splt;
9001 }
9002 else
9003 {
9004 splt = NULL;
9005 plt_offset = (bfd_vma) -1;
9006 gotplt_offset = (bfd_vma) -1;
9007 }
9008
252b5132
RH		 9009 switch (r_type)
9010 {
9011 case R_ARM_NONE:
28a094c2
DJ		 9012 /* We don't need to find a value for this symbol. It's just a
9013 marker. */
9014 *unresolved_reloc_p = FALSE;
252b5132
RH		 9015 return bfd_reloc_ok;
9016
00a97672
RS		 9017 case R_ARM_ABS12:
9018 if (!globals->vxworks_p)
9019 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9020
252b5132
RH		 9021 case R_ARM_PC24:
9022 case R_ARM_ABS32:
bb224fc3 9023 case R_ARM_ABS32_NOI:
252b5132 9024 case R_ARM_REL32:
bb224fc3 9025 case R_ARM_REL32_NOI:
5b5bb741
PB		 9026 case R_ARM_CALL:
9027 case R_ARM_JUMP24:
dfc5f959 9028 case R_ARM_XPC25:
eb043451 9029 case R_ARM_PREL31:
7359ea65 9030 case R_ARM_PLT32:
7359ea65
DJ		 9031 /* Handle relocations which should use the PLT entry. ABS32/REL32
9032 will use the symbol's value, which may point to a PLT entry, but we
9033 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 9034 branches in this object should go to it, except if the PLT is too
9035 far away, in which case a long branch stub should be inserted. */
bb224fc3 9036 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 9037 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 9038 && r_type != R_ARM_CALL
9039 && r_type != R_ARM_JUMP24
9040 && r_type != R_ARM_PLT32)
34e77a92 9041 && plt_offset != (bfd_vma) -1)
7359ea65 9042 {
34e77a92
RS		 9043 /* If we've created a .plt section, and assigned a PLT entry
9044 to this function, it must either be a STT_GNU_IFUNC reference
9045 or not be known to bind locally. In other cases, we should
9046 have cleared the PLT entry by now. */
9047 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 9048
9049 value = (splt->output_section->vma
9050 + splt->output_offset
34e77a92 9051 + plt_offset);
0945cdfd 9052 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 9053 return _bfd_final_link_relocate (howto, input_bfd, input_section,
9054 contents, rel->r_offset, value,
00a97672 9055 rel->r_addend);
7359ea65
DJ		 9056 }
9057
67687978
PB		 9058 /* When generating a shared object or relocatable executable, these
9059 relocations are copied into the output file to be resolved at
9060 run time. */
0e1862bb
L		 9061 if ((bfd_link_pic (info)
9062 || globals->root.is_relocatable_executable)
7359ea65 9063 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 9064 && !(globals->vxworks_p
3348747a
NS		 9065 && strcmp (input_section->output_section->name,
9066 ".tls_vars") == 0)
bb224fc3 9067 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 9068 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 9069 && !(input_bfd == globals->stub_bfd
9070 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 9071 && (h == NULL
9072 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
9073 || h->root.type != bfd_link_hash_undefweak)
9074 && r_type != R_ARM_PC24
5b5bb741
PB		 9075 && r_type != R_ARM_CALL
9076 && r_type != R_ARM_JUMP24
ee06dc07 9077 && r_type != R_ARM_PREL31
7359ea65 9078 && r_type != R_ARM_PLT32)
252b5132 9079 {
947216bf 9080 Elf_Internal_Rela outrel;
b34976b6 9081 bfd_boolean skip, relocate;
f21f3fe0 9082
52db4ec2
JW		 9083 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
9084 && !h->def_regular)
9085 {
9086 char *v = _("shared object");
9087
0e1862bb 9088 if (bfd_link_executable (info))
52db4ec2
JW		 9089 v = _("PIE executable");
9090
9091 (*_bfd_error_handler)
9092 (_("%B: relocation %s against external or undefined symbol `%s'"
9093 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
9094 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
9095 return bfd_reloc_notsupported;
9096 }
9097
0945cdfd
DJ		 9098 *unresolved_reloc_p = FALSE;
9099
34e77a92 9100 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 9101 {
83bac4b0
NC		 9102 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
9103 ! globals->use_rel);
f21f3fe0 9104
83bac4b0 9105 if (sreloc == NULL)
252b5132 9106 return bfd_reloc_notsupported;
252b5132 9107 }
f21f3fe0 9108
b34976b6
AM		 9109 skip = FALSE;
9110 relocate = FALSE;
f21f3fe0 9111
00a97672 9112 outrel.r_addend = addend;
c629eae0
JJ		 9113 outrel.r_offset =
9114 _bfd_elf_section_offset (output_bfd, info, input_section,
9115 rel->r_offset);
9116 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 9117 skip = TRUE;
0bb2d96a 9118 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 9119 skip = TRUE, relocate = TRUE;
252b5132
RH		 9120 outrel.r_offset += (input_section->output_section->vma
9121 + input_section->output_offset);
f21f3fe0 9122
252b5132 9123 if (skip)
0bb2d96a 9124 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 9125 else if (h != NULL
9126 && h->dynindx != -1
0e1862bb 9127 && (!bfd_link_pic (info)
a496fbc8 9128 || !SYMBOLIC_BIND (info, h)
f5385ebf 9129 || !h->def_regular))
5e681ec4 9130 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 9131 else
9132 {
a16385dc
MM		 9133 int symbol;
9134
5e681ec4 9135 /* This symbol is local, or marked to become local. */
34e77a92 9136 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 9137 if (globals->symbian_p)
6366ff1e 9138 {
74541ad4
AM		 9139 asection *osec;
9140
6366ff1e
MM		 9141 /* On Symbian OS, the data segment and text segement
9142 can be relocated independently. Therefore, we
9143 must indicate the segment to which this
9144 relocation is relative. The BPABI allows us to
9145 use any symbol in the right segment; we just use
9146 the section symbol as it is convenient. (We
9147 cannot use the symbol given by "h" directly as it
74541ad4
AM		 9148 will not appear in the dynamic symbol table.)
9149
9150 Note that the dynamic linker ignores the section
9151 symbol value, so we don't subtract osec->vma
9152 from the emitted reloc addend. */
10dbd1f3 9153 if (sym_sec)
74541ad4 9154 osec = sym_sec->output_section;
10dbd1f3 9155 else
74541ad4
AM		 9156 osec = input_section->output_section;
9157 symbol = elf_section_data (osec)->dynindx;
9158 if (symbol == 0)
9159 {
9160 struct elf_link_hash_table *htab = elf_hash_table (info);
9161
9162 if ((osec->flags & SEC_READONLY) == 0
9163 && htab->data_index_section != NULL)
9164 osec = htab->data_index_section;
9165 else
9166 osec = htab->text_index_section;
9167 symbol = elf_section_data (osec)->dynindx;
9168 }
6366ff1e
MM		 9169 BFD_ASSERT (symbol != 0);
9170 }
a16385dc
MM		 9171 else
9172 /* On SVR4-ish systems, the dynamic loader cannot
9173 relocate the text and data segments independently,
9174 so the symbol does not matter. */
9175 symbol = 0;
34e77a92
RS		 9176 if (dynreloc_st_type == STT_GNU_IFUNC)
9177 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9178 to the .iplt entry. Instead, every non-call reference
9179 must use an R_ARM_IRELATIVE relocation to obtain the
9180 correct run-time address. */
9181 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
9182 else
9183 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 9184 if (globals->use_rel)
9185 relocate = TRUE;
9186 else
34e77a92 9187 outrel.r_addend += dynreloc_value;
252b5132 9188 }
f21f3fe0 9189
47beaa6a 9190 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 9191
f21f3fe0 9192 /* If this reloc is against an external symbol, we do not want to
252b5132 9193 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 9194 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 9195 if (! relocate)
9196 return bfd_reloc_ok;
9a5aca8c 9197
f21f3fe0 9198 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 9199 contents, rel->r_offset,
9200 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 9201 }
9202 else switch (r_type)
9203 {
00a97672
RS		 9204 case R_ARM_ABS12:
9205 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9206
dfc5f959 9207 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 9208 case R_ARM_CALL:
9209 case R_ARM_JUMP24:
8029a119 9210 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 9211 case R_ARM_PLT32:
906e58ca 9212 {
906e58ca
NC		 9213 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
9214
dfc5f959 9215 if (r_type == R_ARM_XPC25)
252b5132 9216 {
dfc5f959
NC		 9217 /* Check for Arm calling Arm function. */
9218 /* FIXME: Should we translate the instruction into a BL
9219 instruction instead ? */
35fc36a8 9220 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 9221 (*_bfd_error_handler)
9222 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
9223 input_bfd,
9224 h ? h->root.root.string : "(local)");
dfc5f959 9225 }
155d87d7 9226 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 9227 {
9228 /* Check for Arm calling Thumb function. */
35fc36a8 9229 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 9230 {
f2a9dd69
DJ		 9231 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
9232 output_bfd, input_section,
9233 hit_data, sym_sec, rel->r_offset,
9234 signed_addend, value,
9235 error_message))
9236 return bfd_reloc_ok;
9237 else
9238 return bfd_reloc_dangerous;
dfc5f959 9239 }
252b5132 9240 }
ba96a88f 9241
906e58ca 9242 /* Check if a stub has to be inserted because the
8029a119 9243 destination is too far or we are changing mode. */
155d87d7
CL		 9244 if ( r_type == R_ARM_CALL
9245 || r_type == R_ARM_JUMP24
9246 || r_type == R_ARM_PLT32)
906e58ca 9247 {
fe33d2fa
CL		 9248 enum elf32_arm_stub_type stub_type = arm_stub_none;
9249 struct elf32_arm_link_hash_entry *hash;
9250
9251 hash = (struct elf32_arm_link_hash_entry *) h;
9252 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9253 st_type, &branch_type,
9254 hash, value, sym_sec,
fe33d2fa 9255 input_bfd, sym_name);
5fa9e92f 9256
fe33d2fa 9257 if (stub_type != arm_stub_none)
906e58ca
NC		 9258 {
9259 /* The target is out of reach, so redirect the
9260 branch to the local stub for this function. */
906e58ca
NC		 9261 stub_entry = elf32_arm_get_stub_entry (input_section,
9262 sym_sec, h,
fe33d2fa
CL		 9263 rel, globals,
9264 stub_type);
9cd3e4e5
NC		 9265 {
9266 if (stub_entry != NULL)
9267 value = (stub_entry->stub_offset
9268 + stub_entry->stub_sec->output_offset
9269 + stub_entry->stub_sec->output_section->vma);
9270
9271 if (plt_offset != (bfd_vma) -1)
9272 *unresolved_reloc_p = FALSE;
9273 }
906e58ca 9274 }
fe33d2fa
CL		 9275 else
9276 {
9277 /* If the call goes through a PLT entry, make sure to
9278 check distance to the right destination address. */
34e77a92 9279 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9280 {
9281 value = (splt->output_section->vma
9282 + splt->output_offset
34e77a92 9283 + plt_offset);
fe33d2fa
CL		 9284 *unresolved_reloc_p = FALSE;
9285 /* The PLT entry is in ARM mode, regardless of the
9286 target function. */
35fc36a8 9287 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9288 }
9289 }
906e58ca
NC		 9290 }
9291
dea514f5
PB		 9292 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9293 where:
9294 S is the address of the symbol in the relocation.
9295 P is address of the instruction being relocated.
9296 A is the addend (extracted from the instruction) in bytes.
9297
9298 S is held in 'value'.
9299 P is the base address of the section containing the
9300 instruction plus the offset of the reloc into that
9301 section, ie:
9302 (input_section->output_section->vma +
9303 input_section->output_offset +
9304 rel->r_offset).
9305 A is the addend, converted into bytes, ie:
9306 (signed_addend * 4)
9307
9308 Note: None of these operations have knowledge of the pipeline
9309 size of the processor, thus it is up to the assembler to
9310 encode this information into the addend. */
9311 value -= (input_section->output_section->vma
9312 + input_section->output_offset);
9313 value -= rel->r_offset;
4e7fd91e
PB		 9314 if (globals->use_rel)
9315 value += (signed_addend << howto->size);
9316 else
9317 /* RELA addends do not have to be adjusted by howto->size. */
9318 value += signed_addend;
23080146 9319
dcb5e6e6
NC		 9320 signed_addend = value;
9321 signed_addend >>= howto->rightshift;
9a5aca8c 9322
5ab79981 9323 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 9324 the next instruction unless a PLT entry will be created.
77b4f08f 9325 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 9326 The jump to the next instruction is optimized as a NOP depending
9327 on the architecture. */
ffcb4889 9328 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 9329 && plt_offset == (bfd_vma) -1)
77b4f08f 9330 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 9331 {
cd1dac3d
DG		 9332 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
9333
9334 if (arch_has_arm_nop (globals))
9335 value |= 0x0320f000;
9336 else
9337 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 9338 }
9339 else
59f2c4e7 9340 {
9b485d32 9341 /* Perform a signed range check. */
dcb5e6e6 9342 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 9343 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
9344 return bfd_reloc_overflow;
9a5aca8c 9345
5ab79981 9346 addend = (value & 2);
39b41c9c 9347
5ab79981
PB		 9348 value = (signed_addend & howto->dst_mask)
9349 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 9350
5ab79981
PB		 9351 if (r_type == R_ARM_CALL)
9352 {
155d87d7 9353 /* Set the H bit in the BLX instruction. */
35fc36a8 9354 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 9355 {
9356 if (addend)
9357 value |= (1 << 24);
9358 else
9359 value &= ~(bfd_vma)(1 << 24);
9360 }
9361
5ab79981 9362 /* Select the correct instruction (BL or BLX). */
906e58ca 9363 /* Only if we are not handling a BL to a stub. In this
8029a119 9364 case, mode switching is performed by the stub. */
35fc36a8 9365 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 9366 value |= (1 << 28);
63e1a0fc 9367 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 9368 {
9369 value &= ~(bfd_vma)(1 << 28);
9370 value |= (1 << 24);
9371 }
39b41c9c
PB		 9372 }
9373 }
906e58ca 9374 }
252b5132 9375 break;
f21f3fe0 9376
252b5132
RH		 9377 case R_ARM_ABS32:
9378 value += addend;
35fc36a8 9379 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 9380 value |= 1;
9381 break;
f21f3fe0 9382
bb224fc3
MS		 9383 case R_ARM_ABS32_NOI:
9384 value += addend;
9385 break;
9386
252b5132 9387 case R_ARM_REL32:
a8bc6c78 9388 value += addend;
35fc36a8 9389 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 9390 value |= 1;
252b5132 9391 value -= (input_section->output_section->vma
62efb346 9392 + input_section->output_offset + rel->r_offset);
252b5132 9393 break;
eb043451 9394
bb224fc3
MS		 9395 case R_ARM_REL32_NOI:
9396 value += addend;
9397 value -= (input_section->output_section->vma
9398 + input_section->output_offset + rel->r_offset);
9399 break;
9400
eb043451
PB		 9401 case R_ARM_PREL31:
9402 value -= (input_section->output_section->vma
9403 + input_section->output_offset + rel->r_offset);
9404 value += signed_addend;
9405 if (! h || h->root.type != bfd_link_hash_undefweak)
9406 {
8029a119 9407 /* Check for overflow. */
eb043451
PB		 9408 if ((value ^ (value >> 1)) & (1 << 30))
9409 return bfd_reloc_overflow;
9410 }
9411 value &= 0x7fffffff;
9412 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 9413 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 9414 value |= 1;
9415 break;
252b5132 9416 }
f21f3fe0 9417
252b5132
RH		 9418 bfd_put_32 (input_bfd, value, hit_data);
9419 return bfd_reloc_ok;
9420
9421 case R_ARM_ABS8:
fd0fd00c
MJ		 9422 /* PR 16202: Refectch the addend using the correct size. */
9423 if (globals->use_rel)
9424 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 9425 value += addend;
4e67d4ca
DG		 9426
9427 /* There is no way to tell whether the user intended to use a signed or
9428 unsigned addend. When checking for overflow we accept either,
9429 as specified by the AAELF. */
9430 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 9431 return bfd_reloc_overflow;
9432
9433 bfd_put_8 (input_bfd, value, hit_data);
9434 return bfd_reloc_ok;
9435
9436 case R_ARM_ABS16:
fd0fd00c
MJ		 9437 /* PR 16202: Refectch the addend using the correct size. */
9438 if (globals->use_rel)
9439 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 9440 value += addend;
9441
4e67d4ca
DG		 9442 /* See comment for R_ARM_ABS8. */
9443 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 9444 return bfd_reloc_overflow;
9445
9446 bfd_put_16 (input_bfd, value, hit_data);
9447 return bfd_reloc_ok;
9448
252b5132 9449 case R_ARM_THM_ABS5:
9b485d32 9450 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 9451 if (globals->use_rel)
9452 {
9453 /* Need to refetch addend. */
9454 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9455 /* ??? Need to determine shift amount from operand size. */
9456 addend >>= howto->rightshift;
9457 }
252b5132
RH		 9458 value += addend;
9459
9460 /* ??? Isn't value unsigned? */
9461 if ((long) value > 0x1f || (long) value < -0x10)
9462 return bfd_reloc_overflow;
9463
9464 /* ??? Value needs to be properly shifted into place first. */
9465 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
9466 bfd_put_16 (input_bfd, value, hit_data);
9467 return bfd_reloc_ok;
9468
2cab6cc3
MS		 9469 case R_ARM_THM_ALU_PREL_11_0:
9470 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
9471 {
9472 bfd_vma insn;
9473 bfd_signed_vma relocation;
9474
9475 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9476 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9477
99059e56
RM		 9478 if (globals->use_rel)
9479 {
9480 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
9481 | ((insn & (1 << 26)) >> 15);
9482 if (insn & 0xf00000)
9483 signed_addend = -signed_addend;
9484 }
2cab6cc3
MS		 9485
9486 relocation = value + signed_addend;
79f08007 9487 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9488 + input_section->output_offset
9489 + rel->r_offset);
2cab6cc3 9490
b6518b38 9491 value = relocation;
2cab6cc3 9492
99059e56
RM		 9493 if (value >= 0x1000)
9494 return bfd_reloc_overflow;
2cab6cc3
MS		 9495
9496 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 9497 | ((value & 0x700) << 4)
9498 | ((value & 0x800) << 15);
9499 if (relocation < 0)
9500 insn |= 0xa00000;
2cab6cc3
MS		 9501
9502 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9503 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9504
99059e56 9505 return bfd_reloc_ok;
2cab6cc3
MS		 9506 }
9507
e1ec24c6
NC		 9508 case R_ARM_THM_PC8:
9509 /* PR 10073: This reloc is not generated by the GNU toolchain,
9510 but it is supported for compatibility with third party libraries
9511 generated by other compilers, specifically the ARM/IAR. */
9512 {
9513 bfd_vma insn;
9514 bfd_signed_vma relocation;
9515
9516 insn = bfd_get_16 (input_bfd, hit_data);
9517
99059e56 9518 if (globals->use_rel)
79f08007 9519 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 9520
9521 relocation = value + addend;
79f08007 9522 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9523 + input_section->output_offset
9524 + rel->r_offset);
e1ec24c6 9525
b6518b38 9526 value = relocation;
e1ec24c6
NC		 9527
9528 /* We do not check for overflow of this reloc. Although strictly
9529 speaking this is incorrect, it appears to be necessary in order
9530 to work with IAR generated relocs. Since GCC and GAS do not
9531 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
9532 a problem for them. */
9533 value &= 0x3fc;
9534
9535 insn = (insn & 0xff00) | (value >> 2);
9536
9537 bfd_put_16 (input_bfd, insn, hit_data);
9538
99059e56 9539 return bfd_reloc_ok;
e1ec24c6
NC		 9540 }
9541
2cab6cc3
MS		 9542 case R_ARM_THM_PC12:
9543 /* Corresponds to: ldr.w reg, [pc, #offset]. */
9544 {
9545 bfd_vma insn;
9546 bfd_signed_vma relocation;
9547
9548 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9549 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9550
99059e56
RM		 9551 if (globals->use_rel)
9552 {
9553 signed_addend = insn & 0xfff;
9554 if (!(insn & (1 << 23)))
9555 signed_addend = -signed_addend;
9556 }
2cab6cc3
MS		 9557
9558 relocation = value + signed_addend;
79f08007 9559 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9560 + input_section->output_offset
9561 + rel->r_offset);
2cab6cc3 9562
b6518b38 9563 value = relocation;
2cab6cc3 9564
99059e56
RM		 9565 if (value >= 0x1000)
9566 return bfd_reloc_overflow;
2cab6cc3
MS		 9567
9568 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 9569 if (relocation >= 0)
9570 insn |= (1 << 23);
2cab6cc3
MS		 9571
9572 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9573 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9574
99059e56 9575 return bfd_reloc_ok;
2cab6cc3
MS		 9576 }
9577
dfc5f959 9578 case R_ARM_THM_XPC22:
c19d1205 9579 case R_ARM_THM_CALL:
bd97cb95 9580 case R_ARM_THM_JUMP24:
dfc5f959 9581 /* Thumb BL (branch long instruction). */
252b5132 9582 {
b34976b6 9583 bfd_vma relocation;
99059e56 9584 bfd_vma reloc_sign;
b34976b6
AM		 9585 bfd_boolean overflow = FALSE;
9586 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9587 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 9588 bfd_signed_vma reloc_signed_max;
9589 bfd_signed_vma reloc_signed_min;
b34976b6 9590 bfd_vma check;
252b5132 9591 bfd_signed_vma signed_check;
e95de063 9592 int bitsize;
cd1dac3d 9593 const int thumb2 = using_thumb2 (globals);
252b5132 9594
5ab79981 9595 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 9596 the next instruction unless a PLT entry will be created.
9597 The jump to the next instruction is optimized as a NOP.W for
9598 Thumb-2 enabled architectures. */
19540007 9599 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 9600 && plt_offset == (bfd_vma) -1)
5ab79981 9601 {
cd1dac3d
DG		 9602 if (arch_has_thumb2_nop (globals))
9603 {
9604 bfd_put_16 (input_bfd, 0xf3af, hit_data);
9605 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
9606 }
9607 else
9608 {
9609 bfd_put_16 (input_bfd, 0xe000, hit_data);
9610 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
9611 }
5ab79981
PB		 9612 return bfd_reloc_ok;
9613 }
9614
e95de063 9615 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 9616 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 9617 if (globals->use_rel)
9618 {
99059e56
RM		 9619 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
9620 bfd_vma upper = upper_insn & 0x3ff;
9621 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 9622 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
9623 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 9624 bfd_vma i1 = j1 ^ s ? 0 : 1;
9625 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 9626
99059e56
RM		 9627 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
9628 /* Sign extend. */
9629 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 9630
4e7fd91e
PB		 9631 signed_addend = addend;
9632 }
cb1afa5c 9633
dfc5f959
NC		 9634 if (r_type == R_ARM_THM_XPC22)
9635 {
9636 /* Check for Thumb to Thumb call. */
9637 /* FIXME: Should we translate the instruction into a BL
9638 instruction instead ? */
35fc36a8 9639 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 9640 (*_bfd_error_handler)
9641 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
9642 input_bfd,
9643 h ? h->root.root.string : "(local)");
dfc5f959
NC		 9644 }
9645 else
252b5132 9646 {
dfc5f959
NC		 9647 /* If it is not a call to Thumb, assume call to Arm.
9648 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 9649 function call at all, but rather a long jump. Calls through
9650 the PLT do not require stubs. */
34e77a92 9651 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 9652 {
bd97cb95 9653 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9654 {
9655 /* Convert BL to BLX. */
9656 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9657 }
155d87d7
CL		 9658 else if (( r_type != R_ARM_THM_CALL)
9659 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 9660 {
9661 if (elf32_thumb_to_arm_stub
9662 (info, sym_name, input_bfd, output_bfd, input_section,
9663 hit_data, sym_sec, rel->r_offset, signed_addend, value,
9664 error_message))
9665 return bfd_reloc_ok;
9666 else
9667 return bfd_reloc_dangerous;
9668 }
da5938a2 9669 }
35fc36a8
RS		 9670 else if (branch_type == ST_BRANCH_TO_THUMB
9671 && globals->use_blx
bd97cb95 9672 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9673 {
9674 /* Make sure this is a BL. */
9675 lower_insn |= 0x1800;
9676 }
252b5132 9677 }
f21f3fe0 9678
fe33d2fa 9679 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 9680 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 9681 {
9682 /* Check if a stub has to be inserted because the destination
8029a119 9683 is too far. */
fe33d2fa
CL		 9684 struct elf32_arm_stub_hash_entry *stub_entry;
9685 struct elf32_arm_link_hash_entry *hash;
9686
9687 hash = (struct elf32_arm_link_hash_entry *) h;
9688
9689 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9690 st_type, &branch_type,
9691 hash, value, sym_sec,
fe33d2fa
CL		 9692 input_bfd, sym_name);
9693
9694 if (stub_type != arm_stub_none)
906e58ca
NC		 9695 {
9696 /* The target is out of reach or we are changing modes, so
9697 redirect the branch to the local stub for this
9698 function. */
9699 stub_entry = elf32_arm_get_stub_entry (input_section,
9700 sym_sec, h,
fe33d2fa
CL		 9701 rel, globals,
9702 stub_type);
906e58ca 9703 if (stub_entry != NULL)
9cd3e4e5
NC		 9704 {
9705 value = (stub_entry->stub_offset
9706 + stub_entry->stub_sec->output_offset
9707 + stub_entry->stub_sec->output_section->vma);
9708
9709 if (plt_offset != (bfd_vma) -1)
9710 *unresolved_reloc_p = FALSE;
9711 }
906e58ca 9712
f4ac8484 9713 /* If this call becomes a call to Arm, force BLX. */
155d87d7 9714 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 9715 {
9716 if ((stub_entry
9717 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 9718 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 9719 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9720 }
906e58ca
NC		 9721 }
9722 }
9723
fe33d2fa 9724 /* Handle calls via the PLT. */
34e77a92 9725 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9726 {
9727 value = (splt->output_section->vma
9728 + splt->output_offset
34e77a92 9729 + plt_offset);
fe33d2fa 9730
eed94f8f
NC		 9731 if (globals->use_blx
9732 && r_type == R_ARM_THM_CALL
9733 && ! using_thumb_only (globals))
fe33d2fa
CL		 9734 {
9735 /* If the Thumb BLX instruction is available, convert
9736 the BL to a BLX instruction to call the ARM-mode
9737 PLT entry. */
9738 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 9739 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9740 }
9741 else
9742 {
eed94f8f
NC		 9743 if (! using_thumb_only (globals))
9744 /* Target the Thumb stub before the ARM PLT entry. */
9745 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 9746 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 9747 }
9748 *unresolved_reloc_p = FALSE;
9749 }
9750
ba96a88f 9751 relocation = value + signed_addend;
f21f3fe0 9752
252b5132 9753 relocation -= (input_section->output_section->vma
ba96a88f
NC		 9754 + input_section->output_offset
9755 + rel->r_offset);
9a5aca8c 9756
252b5132
RH		 9757 check = relocation >> howto->rightshift;
9758
9759 /* If this is a signed value, the rightshift just dropped
9760 leading 1 bits (assuming twos complement). */
9761 if ((bfd_signed_vma) relocation >= 0)
9762 signed_check = check;
9763 else
9764 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
9765
e95de063
MS		 9766 /* Calculate the permissable maximum and minimum values for
9767 this relocation according to whether we're relocating for
9768 Thumb-2 or not. */
9769 bitsize = howto->bitsize;
9770 if (!thumb2)
9771 bitsize -= 2;
f6ebfac0 9772 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 9773 reloc_signed_min = ~reloc_signed_max;
9774
252b5132 9775 /* Assumes two's complement. */
ba96a88f 9776 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 9777 overflow = TRUE;
252b5132 9778
bd97cb95 9779 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 9780 /* For a BLX instruction, make sure that the relocation is rounded up
9781 to a word boundary. This follows the semantics of the instruction
9782 which specifies that bit 1 of the target address will come from bit
9783 1 of the base address. */
9784 relocation = (relocation + 2) & ~ 3;
cb1afa5c 9785
e95de063
MS		 9786 /* Put RELOCATION back into the insn. Assumes two's complement.
9787 We use the Thumb-2 encoding, which is safe even if dealing with
9788 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 9789 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 9790 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 9791 | ((relocation >> 12) & 0x3ff)
9792 | (reloc_sign << 10);
906e58ca 9793 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 9794 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
9795 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
9796 | ((relocation >> 1) & 0x7ff);
c62e1cc3 9797
252b5132
RH		 9798 /* Put the relocated value back in the object file: */
9799 bfd_put_16 (input_bfd, upper_insn, hit_data);
9800 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9801
9802 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9803 }
9804 break;
9805
c19d1205
ZW		 9806 case R_ARM_THM_JUMP19:
9807 /* Thumb32 conditional branch instruction. */
9808 {
9809 bfd_vma relocation;
9810 bfd_boolean overflow = FALSE;
9811 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9812 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 9813 bfd_signed_vma reloc_signed_max = 0xffffe;
9814 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 9815 bfd_signed_vma signed_check;
c5423981
TG		 9816 enum elf32_arm_stub_type stub_type = arm_stub_none;
9817 struct elf32_arm_stub_hash_entry *stub_entry;
9818 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 9819
9820 /* Need to refetch the addend, reconstruct the top three bits,
9821 and squish the two 11 bit pieces together. */
9822 if (globals->use_rel)
9823 {
9824 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 9825 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 9826 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
9827 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
9828 bfd_vma lower = (lower_insn & 0x07ff);
9829
a00a1f35
MS		 9830 upper |= J1 << 6;
9831 upper |= J2 << 7;
9832 upper |= (!S) << 8;
c19d1205
ZW		 9833 upper -= 0x0100; /* Sign extend. */
9834
9835 addend = (upper << 12) | (lower << 1);
9836 signed_addend = addend;
9837 }
9838
bd97cb95 9839 /* Handle calls via the PLT. */
34e77a92 9840 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 9841 {
9842 value = (splt->output_section->vma
9843 + splt->output_offset
34e77a92 9844 + plt_offset);
bd97cb95
DJ		 9845 /* Target the Thumb stub before the ARM PLT entry. */
9846 value -= PLT_THUMB_STUB_SIZE;
9847 *unresolved_reloc_p = FALSE;
9848 }
9849
c5423981
TG		 9850 hash = (struct elf32_arm_link_hash_entry *)h;
9851
9852 stub_type = arm_type_of_stub (info, input_section, rel,
9853 st_type, &branch_type,
9854 hash, value, sym_sec,
9855 input_bfd, sym_name);
9856 if (stub_type != arm_stub_none)
9857 {
9858 stub_entry = elf32_arm_get_stub_entry (input_section,
9859 sym_sec, h,
9860 rel, globals,
9861 stub_type);
9862 if (stub_entry != NULL)
9863 {
9864 value = (stub_entry->stub_offset
9865 + stub_entry->stub_sec->output_offset
9866 + stub_entry->stub_sec->output_section->vma);
9867 }
9868 }
c19d1205 9869
99059e56 9870 relocation = value + signed_addend;
c19d1205
ZW		 9871 relocation -= (input_section->output_section->vma
9872 + input_section->output_offset
9873 + rel->r_offset);
a00a1f35 9874 signed_check = (bfd_signed_vma) relocation;
c19d1205 9875
c19d1205
ZW		 9876 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9877 overflow = TRUE;
9878
9879 /* Put RELOCATION back into the insn. */
9880 {
9881 bfd_vma S = (relocation & 0x00100000) >> 20;
9882 bfd_vma J2 = (relocation & 0x00080000) >> 19;
9883 bfd_vma J1 = (relocation & 0x00040000) >> 18;
9884 bfd_vma hi = (relocation & 0x0003f000) >> 12;
9885 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
9886
a00a1f35 9887 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 9888 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
9889 }
9890
9891 /* Put the relocated value back in the object file: */
9892 bfd_put_16 (input_bfd, upper_insn, hit_data);
9893 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9894
9895 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9896 }
9897
9898 case R_ARM_THM_JUMP11:
9899 case R_ARM_THM_JUMP8:
9900 case R_ARM_THM_JUMP6:
51c5503b
NC		 9901 /* Thumb B (branch) instruction). */
9902 {
6cf9e9fe 9903 bfd_signed_vma relocation;
51c5503b
NC		 9904 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
9905 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 9906 bfd_signed_vma signed_check;
9907
c19d1205
ZW		 9908 /* CZB cannot jump backward. */
9909 if (r_type == R_ARM_THM_JUMP6)
9910 reloc_signed_min = 0;
9911
4e7fd91e 9912 if (globals->use_rel)
6cf9e9fe 9913 {
4e7fd91e
PB		 9914 /* Need to refetch addend. */
9915 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9916 if (addend & ((howto->src_mask + 1) >> 1))
9917 {
9918 signed_addend = -1;
9919 signed_addend &= ~ howto->src_mask;
9920 signed_addend |= addend;
9921 }
9922 else
9923 signed_addend = addend;
9924 /* The value in the insn has been right shifted. We need to
9925 undo this, so that we can perform the address calculation
9926 in terms of bytes. */
9927 signed_addend <<= howto->rightshift;
6cf9e9fe 9928 }
6cf9e9fe 9929 relocation = value + signed_addend;
51c5503b
NC		 9930
9931 relocation -= (input_section->output_section->vma
9932 + input_section->output_offset
9933 + rel->r_offset);
9934
6cf9e9fe
NC		 9935 relocation >>= howto->rightshift;
9936 signed_check = relocation;
c19d1205
ZW		 9937
9938 if (r_type == R_ARM_THM_JUMP6)
9939 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
9940 else
9941 relocation &= howto->dst_mask;
51c5503b 9942 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 9943
51c5503b
NC		 9944 bfd_put_16 (input_bfd, relocation, hit_data);
9945
9946 /* Assumes two's complement. */
9947 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9948 return bfd_reloc_overflow;
9949
9950 return bfd_reloc_ok;
9951 }
cedb70c5 9952
8375c36b
PB		 9953 case R_ARM_ALU_PCREL7_0:
9954 case R_ARM_ALU_PCREL15_8:
9955 case R_ARM_ALU_PCREL23_15:
9956 {
9957 bfd_vma insn;
9958 bfd_vma relocation;
9959
9960 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 9961 if (globals->use_rel)
9962 {
9963 /* Extract the addend. */
9964 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
9965 signed_addend = addend;
9966 }
8375c36b
PB		 9967 relocation = value + signed_addend;
9968
9969 relocation -= (input_section->output_section->vma
9970 + input_section->output_offset
9971 + rel->r_offset);
9972 insn = (insn & ~0xfff)
9973 | ((howto->bitpos << 7) & 0xf00)
9974 | ((relocation >> howto->bitpos) & 0xff);
9975 bfd_put_32 (input_bfd, value, hit_data);
9976 }
9977 return bfd_reloc_ok;
9978
252b5132
RH		 9979 case R_ARM_GNU_VTINHERIT:
9980 case R_ARM_GNU_VTENTRY:
9981 return bfd_reloc_ok;
9982
c19d1205 9983 case R_ARM_GOTOFF32:
252b5132 9984 /* Relocation is relative to the start of the
99059e56 9985 global offset table. */
252b5132
RH		 9986
9987 BFD_ASSERT (sgot != NULL);
9988 if (sgot == NULL)
99059e56 9989 return bfd_reloc_notsupported;
9a5aca8c 9990
cedb70c5 9991 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 9992 address by one, so that attempts to call the function pointer will
9993 correctly interpret it as Thumb code. */
35fc36a8 9994 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 9995 value += 1;
9996
252b5132 9997 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 9998 calculation. We always want the start of .got. If we
9999 define _GLOBAL_OFFSET_TABLE in a different way, as is
10000 permitted by the ABI, we might have to change this
10001 calculation. */
252b5132 10002 value -= sgot->output_section->vma;
f21f3fe0 10003 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10004 contents, rel->r_offset, value,
00a97672 10005 rel->r_addend);
252b5132
RH		 10006
10007 case R_ARM_GOTPC:
a7c10850 10008 /* Use global offset table as symbol value. */
252b5132 10009 BFD_ASSERT (sgot != NULL);
f21f3fe0 10010
252b5132 10011 if (sgot == NULL)
99059e56 10012 return bfd_reloc_notsupported;
252b5132 10013
0945cdfd 10014 *unresolved_reloc_p = FALSE;
252b5132 10015 value = sgot->output_section->vma;
f21f3fe0 10016 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10017 contents, rel->r_offset, value,
00a97672 10018 rel->r_addend);
f21f3fe0 10019
252b5132 10020 case R_ARM_GOT32:
eb043451 10021 case R_ARM_GOT_PREL:
252b5132 10022 /* Relocation is to the entry for this symbol in the
99059e56 10023 global offset table. */
252b5132
RH		 10024 if (sgot == NULL)
10025 return bfd_reloc_notsupported;
f21f3fe0 10026
34e77a92
RS		 10027 if (dynreloc_st_type == STT_GNU_IFUNC
10028 && plt_offset != (bfd_vma) -1
10029 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
10030 {
10031 /* We have a relocation against a locally-binding STT_GNU_IFUNC
10032 symbol, and the relocation resolves directly to the runtime
10033 target rather than to the .iplt entry. This means that any
10034 .got entry would be the same value as the .igot.plt entry,
10035 so there's no point creating both. */
10036 sgot = globals->root.igotplt;
10037 value = sgot->output_offset + gotplt_offset;
10038 }
10039 else if (h != NULL)
252b5132
RH		 10040 {
10041 bfd_vma off;
f21f3fe0 10042
252b5132
RH		 10043 off = h->got.offset;
10044 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 10045 if ((off & 1) != 0)
252b5132 10046 {
b436d854
RS		 10047 /* We have already processsed one GOT relocation against
10048 this symbol. */
10049 off &= ~1;
10050 if (globals->root.dynamic_sections_created
10051 && !SYMBOL_REFERENCES_LOCAL (info, h))
10052 *unresolved_reloc_p = FALSE;
10053 }
10054 else
10055 {
10056 Elf_Internal_Rela outrel;
10057
6f820c85 10058 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 10059 {
10060 /* If the symbol doesn't resolve locally in a static
10061 object, we have an undefined reference. If the
10062 symbol doesn't resolve locally in a dynamic object,
10063 it should be resolved by the dynamic linker. */
10064 if (globals->root.dynamic_sections_created)
10065 {
10066 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
10067 *unresolved_reloc_p = FALSE;
10068 }
10069 else
10070 outrel.r_info = 0;
10071 outrel.r_addend = 0;
10072 }
252b5132
RH		 10073 else
10074 {
34e77a92 10075 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10076 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 10077 else if (bfd_link_pic (info) &&
31943882
WN		 10078 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10079 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 10080 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
10081 else
10082 outrel.r_info = 0;
34e77a92 10083 outrel.r_addend = dynreloc_value;
b436d854 10084 }
ee29b9fb 10085
b436d854
RS		 10086 /* The GOT entry is initialized to zero by default.
10087 See if we should install a different value. */
10088 if (outrel.r_addend != 0
10089 && (outrel.r_info == 0 || globals->use_rel))
10090 {
10091 bfd_put_32 (output_bfd, outrel.r_addend,
10092 sgot->contents + off);
10093 outrel.r_addend = 0;
252b5132 10094 }
f21f3fe0 10095
b436d854
RS		 10096 if (outrel.r_info != 0)
10097 {
10098 outrel.r_offset = (sgot->output_section->vma
10099 + sgot->output_offset
10100 + off);
10101 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
10102 }
10103 h->got.offset |= 1;
10104 }
252b5132
RH		 10105 value = sgot->output_offset + off;
10106 }
10107 else
10108 {
10109 bfd_vma off;
f21f3fe0 10110
252b5132
RH		 10111 BFD_ASSERT (local_got_offsets != NULL &&
10112 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 10113
252b5132 10114 off = local_got_offsets[r_symndx];
f21f3fe0 10115
252b5132
RH		 10116 /* The offset must always be a multiple of 4. We use the
10117 least significant bit to record whether we have already
9b485d32 10118 generated the necessary reloc. */
252b5132
RH		 10119 if ((off & 1) != 0)
10120 off &= ~1;
10121 else
10122 {
00a97672 10123 if (globals->use_rel)
34e77a92 10124 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 10125
0e1862bb 10126 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 10127 {
947216bf 10128 Elf_Internal_Rela outrel;
f21f3fe0 10129
34e77a92 10130 outrel.r_addend = addend + dynreloc_value;
252b5132 10131 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 10132 + sgot->output_offset
252b5132 10133 + off);
34e77a92 10134 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10135 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 10136 else
10137 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 10138 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 10139 }
f21f3fe0 10140
252b5132
RH		 10141 local_got_offsets[r_symndx] |= 1;
10142 }
f21f3fe0 10143
252b5132
RH		 10144 value = sgot->output_offset + off;
10145 }
eb043451
PB		 10146 if (r_type != R_ARM_GOT32)
10147 value += sgot->output_section->vma;
9a5aca8c 10148
f21f3fe0 10149 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10150 contents, rel->r_offset, value,
00a97672 10151 rel->r_addend);
f21f3fe0 10152
ba93b8ac
DJ		 10153 case R_ARM_TLS_LDO32:
10154 value = value - dtpoff_base (info);
10155
10156 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10157 contents, rel->r_offset, value,
10158 rel->r_addend);
ba93b8ac
DJ		 10159
10160 case R_ARM_TLS_LDM32:
10161 {
10162 bfd_vma off;
10163
362d30a1 10164 if (sgot == NULL)
ba93b8ac
DJ		 10165 abort ();
10166
10167 off = globals->tls_ldm_got.offset;
10168
10169 if ((off & 1) != 0)
10170 off &= ~1;
10171 else
10172 {
10173 /* If we don't know the module number, create a relocation
10174 for it. */
0e1862bb 10175 if (bfd_link_pic (info))
ba93b8ac
DJ		 10176 {
10177 Elf_Internal_Rela outrel;
ba93b8ac 10178
362d30a1 10179 if (srelgot == NULL)
ba93b8ac
DJ		 10180 abort ();
10181
00a97672 10182 outrel.r_addend = 0;
362d30a1
RS		 10183 outrel.r_offset = (sgot->output_section->vma
10184 + sgot->output_offset + off);
ba93b8ac
DJ		 10185 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
10186
00a97672
RS		 10187 if (globals->use_rel)
10188 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10189 sgot->contents + off);
ba93b8ac 10190
47beaa6a 10191 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10192 }
10193 else
362d30a1 10194 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 10195
10196 globals->tls_ldm_got.offset |= 1;
10197 }
10198
362d30a1 10199 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 10200 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
10201
10202 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10203 contents, rel->r_offset, value,
00a97672 10204 rel->r_addend);
ba93b8ac
DJ		 10205 }
10206
0855e32b
NS		 10207 case R_ARM_TLS_CALL:
10208 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 10209 case R_ARM_TLS_GD32:
10210 case R_ARM_TLS_IE32:
0855e32b
NS		 10211 case R_ARM_TLS_GOTDESC:
10212 case R_ARM_TLS_DESCSEQ:
10213 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 10214 {
0855e32b
NS		 10215 bfd_vma off, offplt;
10216 int indx = 0;
ba93b8ac
DJ		 10217 char tls_type;
10218
0855e32b 10219 BFD_ASSERT (sgot != NULL);
ba93b8ac 10220
ba93b8ac
DJ		 10221 if (h != NULL)
10222 {
10223 bfd_boolean dyn;
10224 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 10225 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
10226 bfd_link_pic (info),
10227 h)
10228 && (!bfd_link_pic (info)
ba93b8ac
DJ		 10229 || !SYMBOL_REFERENCES_LOCAL (info, h)))
10230 {
10231 *unresolved_reloc_p = FALSE;
10232 indx = h->dynindx;
10233 }
10234 off = h->got.offset;
0855e32b 10235 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 10236 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
10237 }
10238 else
10239 {
0855e32b 10240 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 10241 off = local_got_offsets[r_symndx];
0855e32b 10242 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 10243 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
10244 }
10245
0855e32b 10246 /* Linker relaxations happens from one of the
b38cadfb 10247 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 10248 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 10249 tls_type = GOT_TLS_IE;
0855e32b
NS		 10250
10251 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 10252
10253 if ((off & 1) != 0)
10254 off &= ~1;
10255 else
10256 {
10257 bfd_boolean need_relocs = FALSE;
10258 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 10259 int cur_off = off;
10260
10261 /* The GOT entries have not been initialized yet. Do it
10262 now, and emit any relocations. If both an IE GOT and a
10263 GD GOT are necessary, we emit the GD first. */
10264
0e1862bb 10265 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 10266 && (h == NULL
10267 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10268 || h->root.type != bfd_link_hash_undefweak))
10269 {
10270 need_relocs = TRUE;
0855e32b 10271 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 10272 }
10273
0855e32b
NS		 10274 if (tls_type & GOT_TLS_GDESC)
10275 {
47beaa6a
RS		 10276 bfd_byte *loc;
10277
0855e32b
NS		 10278 /* We should have relaxed, unless this is an undefined
10279 weak symbol. */
10280 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 10281 || bfd_link_pic (info));
0855e32b 10282 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 10283 <= globals->root.sgotplt->size);
0855e32b
NS		 10284
10285 outrel.r_addend = 0;
10286 outrel.r_offset = (globals->root.sgotplt->output_section->vma
10287 + globals->root.sgotplt->output_offset
10288 + offplt
10289 + globals->sgotplt_jump_table_size);
b38cadfb 10290
0855e32b
NS		 10291 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
10292 sreloc = globals->root.srelplt;
10293 loc = sreloc->contents;
10294 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
10295 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 10296 <= sreloc->contents + sreloc->size);
0855e32b
NS		 10297
10298 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
10299
10300 /* For globals, the first word in the relocation gets
10301 the relocation index and the top bit set, or zero,
10302 if we're binding now. For locals, it gets the
10303 symbol's offset in the tls section. */
99059e56 10304 bfd_put_32 (output_bfd,
0855e32b
NS		 10305 !h ? value - elf_hash_table (info)->tls_sec->vma
10306 : info->flags & DF_BIND_NOW ? 0
10307 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 10308 globals->root.sgotplt->contents + offplt
10309 + globals->sgotplt_jump_table_size);
10310
0855e32b 10311 /* Second word in the relocation is always zero. */
99059e56 10312 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 10313 globals->root.sgotplt->contents + offplt
10314 + globals->sgotplt_jump_table_size + 4);
0855e32b 10315 }
ba93b8ac
DJ		 10316 if (tls_type & GOT_TLS_GD)
10317 {
10318 if (need_relocs)
10319 {
00a97672 10320 outrel.r_addend = 0;
362d30a1
RS		 10321 outrel.r_offset = (sgot->output_section->vma
10322 + sgot->output_offset
00a97672 10323 + cur_off);
ba93b8ac 10324 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 10325
00a97672
RS		 10326 if (globals->use_rel)
10327 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10328 sgot->contents + cur_off);
00a97672 10329
47beaa6a 10330 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10331
10332 if (indx == 0)
10333 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10334 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10335 else
10336 {
00a97672 10337 outrel.r_addend = 0;
ba93b8ac
DJ		 10338 outrel.r_info = ELF32_R_INFO (indx,
10339 R_ARM_TLS_DTPOFF32);
10340 outrel.r_offset += 4;
00a97672
RS		 10341
10342 if (globals->use_rel)
10343 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10344 sgot->contents + cur_off + 4);
00a97672 10345
47beaa6a
RS		 10346 elf32_arm_add_dynreloc (output_bfd, info,
10347 srelgot, &outrel);
ba93b8ac
DJ		 10348 }
10349 }
10350 else
10351 {
10352 /* If we are not emitting relocations for a
10353 general dynamic reference, then we must be in a
10354 static link or an executable link with the
10355 symbol binding locally. Mark it as belonging
10356 to module 1, the executable. */
10357 bfd_put_32 (output_bfd, 1,
362d30a1 10358 sgot->contents + cur_off);
ba93b8ac 10359 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10360 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10361 }
10362
10363 cur_off += 8;
10364 }
10365
10366 if (tls_type & GOT_TLS_IE)
10367 {
10368 if (need_relocs)
10369 {
00a97672
RS		 10370 if (indx == 0)
10371 outrel.r_addend = value - dtpoff_base (info);
10372 else
10373 outrel.r_addend = 0;
362d30a1
RS		 10374 outrel.r_offset = (sgot->output_section->vma
10375 + sgot->output_offset
ba93b8ac
DJ		 10376 + cur_off);
10377 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
10378
00a97672
RS		 10379 if (globals->use_rel)
10380 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10381 sgot->contents + cur_off);
ba93b8ac 10382
47beaa6a 10383 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10384 }
10385 else
10386 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 10387 sgot->contents + cur_off);
ba93b8ac
DJ		 10388 cur_off += 4;
10389 }
10390
10391 if (h != NULL)
10392 h->got.offset |= 1;
10393 else
10394 local_got_offsets[r_symndx] |= 1;
10395 }
10396
10397 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
10398 off += 8;
0855e32b
NS		 10399 else if (tls_type & GOT_TLS_GDESC)
10400 off = offplt;
10401
10402 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
10403 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
10404 {
10405 bfd_signed_vma offset;
12352d3f
PB		 10406 /* TLS stubs are arm mode. The original symbol is a
10407 data object, so branch_type is bogus. */
10408 branch_type = ST_BRANCH_TO_ARM;
0855e32b 10409 enum elf32_arm_stub_type stub_type
34e77a92
RS		 10410 = arm_type_of_stub (info, input_section, rel,
10411 st_type, &branch_type,
0855e32b
NS		 10412 (struct elf32_arm_link_hash_entry *)h,
10413 globals->tls_trampoline, globals->root.splt,
10414 input_bfd, sym_name);
10415
10416 if (stub_type != arm_stub_none)
10417 {
10418 struct elf32_arm_stub_hash_entry *stub_entry
10419 = elf32_arm_get_stub_entry
10420 (input_section, globals->root.splt, 0, rel,
10421 globals, stub_type);
10422 offset = (stub_entry->stub_offset
10423 + stub_entry->stub_sec->output_offset
10424 + stub_entry->stub_sec->output_section->vma);
10425 }
10426 else
10427 offset = (globals->root.splt->output_section->vma
10428 + globals->root.splt->output_offset
10429 + globals->tls_trampoline);
10430
10431 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
10432 {
10433 unsigned long inst;
b38cadfb
NC		 10434
10435 offset -= (input_section->output_section->vma
10436 + input_section->output_offset
10437 + rel->r_offset + 8);
0855e32b
NS		 10438
10439 inst = offset >> 2;
10440 inst &= 0x00ffffff;
10441 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
10442 }
10443 else
10444 {
10445 /* Thumb blx encodes the offset in a complicated
10446 fashion. */
10447 unsigned upper_insn, lower_insn;
10448 unsigned neg;
10449
b38cadfb
NC		 10450 offset -= (input_section->output_section->vma
10451 + input_section->output_offset
0855e32b 10452 + rel->r_offset + 4);
b38cadfb 10453
12352d3f
PB		 10454 if (stub_type != arm_stub_none
10455 && arm_stub_is_thumb (stub_type))
10456 {
10457 lower_insn = 0xd000;
10458 }
10459 else
10460 {
10461 lower_insn = 0xc000;
6a631e86 10462 /* Round up the offset to a word boundary. */
12352d3f
PB		 10463 offset = (offset + 2) & ~2;
10464 }
10465
0855e32b
NS		 10466 neg = offset < 0;
10467 upper_insn = (0xf000
10468 | ((offset >> 12) & 0x3ff)
10469 | (neg << 10));
12352d3f 10470 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 10471 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 10472 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 10473 bfd_put_16 (input_bfd, upper_insn, hit_data);
10474 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10475 return bfd_reloc_ok;
10476 }
10477 }
10478 /* These relocations needs special care, as besides the fact
10479 they point somewhere in .gotplt, the addend must be
10480 adjusted accordingly depending on the type of instruction
6a631e86 10481 we refer to. */
0855e32b
NS		 10482 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
10483 {
10484 unsigned long data, insn;
10485 unsigned thumb;
b38cadfb 10486
0855e32b
NS		 10487 data = bfd_get_32 (input_bfd, hit_data);
10488 thumb = data & 1;
10489 data &= ~1u;
b38cadfb 10490
0855e32b
NS		 10491 if (thumb)
10492 {
10493 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
10494 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10495 insn = (insn << 16)
10496 | bfd_get_16 (input_bfd,
10497 contents + rel->r_offset - data + 2);
10498 if ((insn & 0xf800c000) == 0xf000c000)
10499 /* bl/blx */
10500 value = -6;
10501 else if ((insn & 0xffffff00) == 0x4400)
10502 /* add */
10503 value = -5;
10504 else
10505 {
10506 (*_bfd_error_handler)
10507 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
10508 input_bfd, input_section,
10509 (unsigned long)rel->r_offset, insn);
10510 return bfd_reloc_notsupported;
10511 }
10512 }
10513 else
10514 {
10515 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
10516
10517 switch (insn >> 24)
10518 {
10519 case 0xeb: /* bl */
10520 case 0xfa: /* blx */
10521 value = -4;
10522 break;
10523
10524 case 0xe0: /* add */
10525 value = -8;
10526 break;
b38cadfb 10527
0855e32b
NS		 10528 default:
10529 (*_bfd_error_handler)
10530 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
10531 input_bfd, input_section,
10532 (unsigned long)rel->r_offset, insn);
10533 return bfd_reloc_notsupported;
10534 }
10535 }
b38cadfb 10536
0855e32b
NS		 10537 value += ((globals->root.sgotplt->output_section->vma
10538 + globals->root.sgotplt->output_offset + off)
10539 - (input_section->output_section->vma
10540 + input_section->output_offset
10541 + rel->r_offset)
10542 + globals->sgotplt_jump_table_size);
10543 }
10544 else
10545 value = ((globals->root.sgot->output_section->vma
10546 + globals->root.sgot->output_offset + off)
10547 - (input_section->output_section->vma
10548 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 10549
10550 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10551 contents, rel->r_offset, value,
00a97672 10552 rel->r_addend);
ba93b8ac
DJ		 10553 }
10554
10555 case R_ARM_TLS_LE32:
3cbc1e5e 10556 if (bfd_link_dll (info))
ba93b8ac
DJ		 10557 {
10558 (*_bfd_error_handler)
10559 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
10560 input_bfd, input_section,
10561 (long) rel->r_offset, howto->name);
46691134 10562 return bfd_reloc_notsupported;
ba93b8ac
DJ		 10563 }
10564 else
10565 value = tpoff (info, value);
906e58ca 10566
ba93b8ac 10567 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10568 contents, rel->r_offset, value,
10569 rel->r_addend);
ba93b8ac 10570
319850b4
JB		 10571 case R_ARM_V4BX:
10572 if (globals->fix_v4bx)
845b51d6
PB		 10573 {
10574 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 10575
845b51d6
PB		 10576 /* Ensure that we have a BX instruction. */
10577 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 10578
845b51d6
PB		 10579 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
10580 {
10581 /* Branch to veneer. */
10582 bfd_vma glue_addr;
10583 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
10584 glue_addr -= input_section->output_section->vma
10585 + input_section->output_offset
10586 + rel->r_offset + 8;
10587 insn = (insn & 0xf0000000) | 0x0a000000
10588 | ((glue_addr >> 2) & 0x00ffffff);
10589 }
10590 else
10591 {
10592 /* Preserve Rm (lowest four bits) and the condition code
10593 (highest four bits). Other bits encode MOV PC,Rm. */
10594 insn = (insn & 0xf000000f) | 0x01a0f000;
10595 }
319850b4 10596
845b51d6
PB		 10597 bfd_put_32 (input_bfd, insn, hit_data);
10598 }
319850b4
JB		 10599 return bfd_reloc_ok;
10600
b6895b4f
PB		 10601 case R_ARM_MOVW_ABS_NC:
10602 case R_ARM_MOVT_ABS:
10603 case R_ARM_MOVW_PREL_NC:
10604 case R_ARM_MOVT_PREL:
92f5d02b
MS		 10605 /* Until we properly support segment-base-relative addressing then
10606 we assume the segment base to be zero, as for the group relocations.
10607 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
10608 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
10609 case R_ARM_MOVW_BREL_NC:
10610 case R_ARM_MOVW_BREL:
10611 case R_ARM_MOVT_BREL:
b6895b4f
PB		 10612 {
10613 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
10614
10615 if (globals->use_rel)
10616 {
10617 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 10618 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10619 }
92f5d02b 10620
b6895b4f 10621 value += signed_addend;
b6895b4f
PB		 10622
10623 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
10624 value -= (input_section->output_section->vma
10625 + input_section->output_offset + rel->r_offset);
10626
92f5d02b 10627 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 10628 return bfd_reloc_overflow;
92f5d02b 10629
35fc36a8 10630 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10631 value |= 1;
10632
10633 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 10634 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 10635 value >>= 16;
10636
10637 insn &= 0xfff0f000;
10638 insn |= value & 0xfff;
10639 insn |= (value & 0xf000) << 4;
10640 bfd_put_32 (input_bfd, insn, hit_data);
10641 }
10642 return bfd_reloc_ok;
10643
10644 case R_ARM_THM_MOVW_ABS_NC:
10645 case R_ARM_THM_MOVT_ABS:
10646 case R_ARM_THM_MOVW_PREL_NC:
10647 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 10648 /* Until we properly support segment-base-relative addressing then
10649 we assume the segment base to be zero, as for the above relocations.
10650 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
10651 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
10652 as R_ARM_THM_MOVT_ABS. */
10653 case R_ARM_THM_MOVW_BREL_NC:
10654 case R_ARM_THM_MOVW_BREL:
10655 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 10656 {
10657 bfd_vma insn;
906e58ca 10658
b6895b4f
PB		 10659 insn = bfd_get_16 (input_bfd, hit_data) << 16;
10660 insn |= bfd_get_16 (input_bfd, hit_data + 2);
10661
10662 if (globals->use_rel)
10663 {
10664 addend = ((insn >> 4) & 0xf000)
10665 | ((insn >> 15) & 0x0800)
10666 | ((insn >> 4) & 0x0700)
10667 | (insn & 0x00ff);
39623e12 10668 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10669 }
92f5d02b 10670
b6895b4f 10671 value += signed_addend;
b6895b4f
PB		 10672
10673 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
10674 value -= (input_section->output_section->vma
10675 + input_section->output_offset + rel->r_offset);
10676
92f5d02b 10677 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 10678 return bfd_reloc_overflow;
92f5d02b 10679
35fc36a8 10680 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10681 value |= 1;
10682
10683 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 10684 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 10685 value >>= 16;
10686
10687 insn &= 0xfbf08f00;
10688 insn |= (value & 0xf000) << 4;
10689 insn |= (value & 0x0800) << 15;
10690 insn |= (value & 0x0700) << 4;
10691 insn |= (value & 0x00ff);
10692
10693 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10694 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10695 }
10696 return bfd_reloc_ok;
10697
4962c51a
MS		 10698 case R_ARM_ALU_PC_G0_NC:
10699 case R_ARM_ALU_PC_G1_NC:
10700 case R_ARM_ALU_PC_G0:
10701 case R_ARM_ALU_PC_G1:
10702 case R_ARM_ALU_PC_G2:
10703 case R_ARM_ALU_SB_G0_NC:
10704 case R_ARM_ALU_SB_G1_NC:
10705 case R_ARM_ALU_SB_G0:
10706 case R_ARM_ALU_SB_G1:
10707 case R_ARM_ALU_SB_G2:
10708 {
10709 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10710 bfd_vma pc = input_section->output_section->vma
4962c51a 10711 + input_section->output_offset + rel->r_offset;
31a91d61 10712 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10713 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 10714 bfd_vma residual;
10715 bfd_vma g_n;
4962c51a 10716 bfd_signed_vma signed_value;
99059e56
RM		 10717 int group = 0;
10718
10719 /* Determine which group of bits to select. */
10720 switch (r_type)
10721 {
10722 case R_ARM_ALU_PC_G0_NC:
10723 case R_ARM_ALU_PC_G0:
10724 case R_ARM_ALU_SB_G0_NC:
10725 case R_ARM_ALU_SB_G0:
10726 group = 0;
10727 break;
10728
10729 case R_ARM_ALU_PC_G1_NC:
10730 case R_ARM_ALU_PC_G1:
10731 case R_ARM_ALU_SB_G1_NC:
10732 case R_ARM_ALU_SB_G1:
10733 group = 1;
10734 break;
10735
10736 case R_ARM_ALU_PC_G2:
10737 case R_ARM_ALU_SB_G2:
10738 group = 2;
10739 break;
10740
10741 default:
10742 abort ();
10743 }
10744
10745 /* If REL, extract the addend from the insn. If RELA, it will
10746 have already been fetched for us. */
4962c51a 10747 if (globals->use_rel)
99059e56
RM		 10748 {
10749 int negative;
10750 bfd_vma constant = insn & 0xff;
10751 bfd_vma rotation = (insn & 0xf00) >> 8;
10752
10753 if (rotation == 0)
10754 signed_addend = constant;
10755 else
10756 {
10757 /* Compensate for the fact that in the instruction, the
10758 rotation is stored in multiples of 2 bits. */
10759 rotation *= 2;
10760
10761 /* Rotate "constant" right by "rotation" bits. */
10762 signed_addend = (constant >> rotation) |
10763 (constant << (8 * sizeof (bfd_vma) - rotation));
10764 }
10765
10766 /* Determine if the instruction is an ADD or a SUB.
10767 (For REL, this determines the sign of the addend.) */
10768 negative = identify_add_or_sub (insn);
10769 if (negative == 0)
10770 {
10771 (*_bfd_error_handler)
10772 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
10773 input_bfd, input_section,
10774 (long) rel->r_offset, howto->name);
10775 return bfd_reloc_overflow;
10776 }
10777
10778 signed_addend *= negative;
10779 }
4962c51a
MS		 10780
10781 /* Compute the value (X) to go in the place. */
99059e56
RM		 10782 if (r_type == R_ARM_ALU_PC_G0_NC
10783 || r_type == R_ARM_ALU_PC_G1_NC
10784 || r_type == R_ARM_ALU_PC_G0
10785 || r_type == R_ARM_ALU_PC_G1
10786 || r_type == R_ARM_ALU_PC_G2)
10787 /* PC relative. */
10788 signed_value = value - pc + signed_addend;
10789 else
10790 /* Section base relative. */
10791 signed_value = value - sb + signed_addend;
10792
10793 /* If the target symbol is a Thumb function, then set the
10794 Thumb bit in the address. */
35fc36a8 10795 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 10796 signed_value |= 1;
10797
99059e56
RM		 10798 /* Calculate the value of the relevant G_n, in encoded
10799 constant-with-rotation format. */
b6518b38
NC		 10800 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10801 group, &residual);
99059e56
RM		 10802
10803 /* Check for overflow if required. */
10804 if ((r_type == R_ARM_ALU_PC_G0
10805 || r_type == R_ARM_ALU_PC_G1
10806 || r_type == R_ARM_ALU_PC_G2
10807 || r_type == R_ARM_ALU_SB_G0
10808 || r_type == R_ARM_ALU_SB_G1
10809 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
10810 {
10811 (*_bfd_error_handler)
10812 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
10813 input_bfd, input_section,
b6518b38
NC		 10814 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
10815 howto->name);
99059e56
RM		 10816 return bfd_reloc_overflow;
10817 }
10818
10819 /* Mask out the value and the ADD/SUB part of the opcode; take care
10820 not to destroy the S bit. */
10821 insn &= 0xff1ff000;
10822
10823 /* Set the opcode according to whether the value to go in the
10824 place is negative. */
10825 if (signed_value < 0)
10826 insn |= 1 << 22;
10827 else
10828 insn |= 1 << 23;
10829
10830 /* Encode the offset. */
10831 insn |= g_n;
4962c51a
MS		 10832
10833 bfd_put_32 (input_bfd, insn, hit_data);
10834 }
10835 return bfd_reloc_ok;
10836
10837 case R_ARM_LDR_PC_G0:
10838 case R_ARM_LDR_PC_G1:
10839 case R_ARM_LDR_PC_G2:
10840 case R_ARM_LDR_SB_G0:
10841 case R_ARM_LDR_SB_G1:
10842 case R_ARM_LDR_SB_G2:
10843 {
10844 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10845 bfd_vma pc = input_section->output_section->vma
4962c51a 10846 + input_section->output_offset + rel->r_offset;
31a91d61 10847 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10848 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10849 bfd_vma residual;
4962c51a 10850 bfd_signed_vma signed_value;
99059e56
RM		 10851 int group = 0;
10852
10853 /* Determine which groups of bits to calculate. */
10854 switch (r_type)
10855 {
10856 case R_ARM_LDR_PC_G0:
10857 case R_ARM_LDR_SB_G0:
10858 group = 0;
10859 break;
10860
10861 case R_ARM_LDR_PC_G1:
10862 case R_ARM_LDR_SB_G1:
10863 group = 1;
10864 break;
10865
10866 case R_ARM_LDR_PC_G2:
10867 case R_ARM_LDR_SB_G2:
10868 group = 2;
10869 break;
10870
10871 default:
10872 abort ();
10873 }
10874
10875 /* If REL, extract the addend from the insn. If RELA, it will
10876 have already been fetched for us. */
4962c51a 10877 if (globals->use_rel)
99059e56
RM		 10878 {
10879 int negative = (insn & (1 << 23)) ? 1 : -1;
10880 signed_addend = negative * (insn & 0xfff);
10881 }
4962c51a
MS		 10882
10883 /* Compute the value (X) to go in the place. */
99059e56
RM		 10884 if (r_type == R_ARM_LDR_PC_G0
10885 || r_type == R_ARM_LDR_PC_G1
10886 || r_type == R_ARM_LDR_PC_G2)
10887 /* PC relative. */
10888 signed_value = value - pc + signed_addend;
10889 else
10890 /* Section base relative. */
10891 signed_value = value - sb + signed_addend;
10892
10893 /* Calculate the value of the relevant G_{n-1} to obtain
10894 the residual at that stage. */
b6518b38
NC		 10895 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10896 group - 1, &residual);
99059e56
RM		 10897
10898 /* Check for overflow. */
10899 if (residual >= 0x1000)
10900 {
10901 (*_bfd_error_handler)
10902 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10903 input_bfd, input_section,
10904 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10905 return bfd_reloc_overflow;
10906 }
10907
10908 /* Mask out the value and U bit. */
10909 insn &= 0xff7ff000;
10910
10911 /* Set the U bit if the value to go in the place is non-negative. */
10912 if (signed_value >= 0)
10913 insn |= 1 << 23;
10914
10915 /* Encode the offset. */
10916 insn |= residual;
4962c51a
MS		 10917
10918 bfd_put_32 (input_bfd, insn, hit_data);
10919 }
10920 return bfd_reloc_ok;
10921
10922 case R_ARM_LDRS_PC_G0:
10923 case R_ARM_LDRS_PC_G1:
10924 case R_ARM_LDRS_PC_G2:
10925 case R_ARM_LDRS_SB_G0:
10926 case R_ARM_LDRS_SB_G1:
10927 case R_ARM_LDRS_SB_G2:
10928 {
10929 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10930 bfd_vma pc = input_section->output_section->vma
4962c51a 10931 + input_section->output_offset + rel->r_offset;
31a91d61 10932 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10933 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10934 bfd_vma residual;
4962c51a 10935 bfd_signed_vma signed_value;
99059e56
RM		 10936 int group = 0;
10937
10938 /* Determine which groups of bits to calculate. */
10939 switch (r_type)
10940 {
10941 case R_ARM_LDRS_PC_G0:
10942 case R_ARM_LDRS_SB_G0:
10943 group = 0;
10944 break;
10945
10946 case R_ARM_LDRS_PC_G1:
10947 case R_ARM_LDRS_SB_G1:
10948 group = 1;
10949 break;
10950
10951 case R_ARM_LDRS_PC_G2:
10952 case R_ARM_LDRS_SB_G2:
10953 group = 2;
10954 break;
10955
10956 default:
10957 abort ();
10958 }
10959
10960 /* If REL, extract the addend from the insn. If RELA, it will
10961 have already been fetched for us. */
4962c51a 10962 if (globals->use_rel)
99059e56
RM		 10963 {
10964 int negative = (insn & (1 << 23)) ? 1 : -1;
10965 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
10966 }
4962c51a
MS		 10967
10968 /* Compute the value (X) to go in the place. */
99059e56
RM		 10969 if (r_type == R_ARM_LDRS_PC_G0
10970 || r_type == R_ARM_LDRS_PC_G1
10971 || r_type == R_ARM_LDRS_PC_G2)
10972 /* PC relative. */
10973 signed_value = value - pc + signed_addend;
10974 else
10975 /* Section base relative. */
10976 signed_value = value - sb + signed_addend;
10977
10978 /* Calculate the value of the relevant G_{n-1} to obtain
10979 the residual at that stage. */
b6518b38
NC		 10980 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10981 group - 1, &residual);
99059e56
RM		 10982
10983 /* Check for overflow. */
10984 if (residual >= 0x100)
10985 {
10986 (*_bfd_error_handler)
10987 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10988 input_bfd, input_section,
10989 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10990 return bfd_reloc_overflow;
10991 }
10992
10993 /* Mask out the value and U bit. */
10994 insn &= 0xff7ff0f0;
10995
10996 /* Set the U bit if the value to go in the place is non-negative. */
10997 if (signed_value >= 0)
10998 insn |= 1 << 23;
10999
11000 /* Encode the offset. */
11001 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 11002
11003 bfd_put_32 (input_bfd, insn, hit_data);
11004 }
11005 return bfd_reloc_ok;
11006
11007 case R_ARM_LDC_PC_G0:
11008 case R_ARM_LDC_PC_G1:
11009 case R_ARM_LDC_PC_G2:
11010 case R_ARM_LDC_SB_G0:
11011 case R_ARM_LDC_SB_G1:
11012 case R_ARM_LDC_SB_G2:
11013 {
11014 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11015 bfd_vma pc = input_section->output_section->vma
4962c51a 11016 + input_section->output_offset + rel->r_offset;
31a91d61 11017 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11018 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11019 bfd_vma residual;
4962c51a 11020 bfd_signed_vma signed_value;
99059e56
RM		 11021 int group = 0;
11022
11023 /* Determine which groups of bits to calculate. */
11024 switch (r_type)
11025 {
11026 case R_ARM_LDC_PC_G0:
11027 case R_ARM_LDC_SB_G0:
11028 group = 0;
11029 break;
11030
11031 case R_ARM_LDC_PC_G1:
11032 case R_ARM_LDC_SB_G1:
11033 group = 1;
11034 break;
11035
11036 case R_ARM_LDC_PC_G2:
11037 case R_ARM_LDC_SB_G2:
11038 group = 2;
11039 break;
11040
11041 default:
11042 abort ();
11043 }
11044
11045 /* If REL, extract the addend from the insn. If RELA, it will
11046 have already been fetched for us. */
4962c51a 11047 if (globals->use_rel)
99059e56
RM		 11048 {
11049 int negative = (insn & (1 << 23)) ? 1 : -1;
11050 signed_addend = negative * ((insn & 0xff) << 2);
11051 }
4962c51a
MS		 11052
11053 /* Compute the value (X) to go in the place. */
99059e56
RM		 11054 if (r_type == R_ARM_LDC_PC_G0
11055 || r_type == R_ARM_LDC_PC_G1
11056 || r_type == R_ARM_LDC_PC_G2)
11057 /* PC relative. */
11058 signed_value = value - pc + signed_addend;
11059 else
11060 /* Section base relative. */
11061 signed_value = value - sb + signed_addend;
11062
11063 /* Calculate the value of the relevant G_{n-1} to obtain
11064 the residual at that stage. */
b6518b38
NC		 11065 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11066 group - 1, &residual);
99059e56
RM		 11067
11068 /* Check for overflow. (The absolute value to go in the place must be
11069 divisible by four and, after having been divided by four, must
11070 fit in eight bits.) */
11071 if ((residual & 0x3) != 0 || residual >= 0x400)
11072 {
11073 (*_bfd_error_handler)
11074 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11075 input_bfd, input_section,
b6518b38 11076 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11077 return bfd_reloc_overflow;
11078 }
11079
11080 /* Mask out the value and U bit. */
11081 insn &= 0xff7fff00;
11082
11083 /* Set the U bit if the value to go in the place is non-negative. */
11084 if (signed_value >= 0)
11085 insn |= 1 << 23;
11086
11087 /* Encode the offset. */
11088 insn |= residual >> 2;
4962c51a
MS		 11089
11090 bfd_put_32 (input_bfd, insn, hit_data);
11091 }
11092 return bfd_reloc_ok;
11093
72d98d16
MG		 11094 case R_ARM_THM_ALU_ABS_G0_NC:
11095 case R_ARM_THM_ALU_ABS_G1_NC:
11096 case R_ARM_THM_ALU_ABS_G2_NC:
11097 case R_ARM_THM_ALU_ABS_G3_NC:
11098 {
11099 const int shift_array[4] = {0, 8, 16, 24};
11100 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
11101 bfd_vma addr = value;
11102 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
11103
11104 /* Compute address. */
11105 if (globals->use_rel)
11106 signed_addend = insn & 0xff;
11107 addr += signed_addend;
11108 if (branch_type == ST_BRANCH_TO_THUMB)
11109 addr |= 1;
11110 /* Clean imm8 insn. */
11111 insn &= 0xff00;
11112 /* And update with correct part of address. */
11113 insn |= (addr >> shift) & 0xff;
11114 /* Update insn. */
11115 bfd_put_16 (input_bfd, insn, hit_data);
11116 }
11117
11118 *unresolved_reloc_p = FALSE;
11119 return bfd_reloc_ok;
11120
252b5132
RH		 11121 default:
11122 return bfd_reloc_notsupported;
11123 }
11124}
11125
98c1d4aa
NC		 11126/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11127static void
57e8b36a
NC		 11128arm_add_to_rel (bfd * abfd,
11129 bfd_byte * address,
11130 reloc_howto_type * howto,
11131 bfd_signed_vma increment)
98c1d4aa 11132{
98c1d4aa
NC		 11133 bfd_signed_vma addend;
11134
bd97cb95
DJ		 11135 if (howto->type == R_ARM_THM_CALL
11136 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 11137 {
9a5aca8c
AM		 11138 int upper_insn, lower_insn;
11139 int upper, lower;
98c1d4aa 11140
9a5aca8c
AM		 11141 upper_insn = bfd_get_16 (abfd, address);
11142 lower_insn = bfd_get_16 (abfd, address + 2);
11143 upper = upper_insn & 0x7ff;
11144 lower = lower_insn & 0x7ff;
11145
11146 addend = (upper << 12) | (lower << 1);
ddda4409 11147 addend += increment;
9a5aca8c 11148 addend >>= 1;
98c1d4aa 11149
9a5aca8c
AM		 11150 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
11151 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
11152
dc810e39
AM		 11153 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
11154 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 11155 }
11156 else
11157 {
11158 bfd_vma contents;
11159
11160 contents = bfd_get_32 (abfd, address);
11161
11162 /* Get the (signed) value from the instruction. */
11163 addend = contents & howto->src_mask;
11164 if (addend & ((howto->src_mask + 1) >> 1))
11165 {
11166 bfd_signed_vma mask;
11167
11168 mask = -1;
11169 mask &= ~ howto->src_mask;
11170 addend |= mask;
11171 }
11172
11173 /* Add in the increment, (which is a byte value). */
11174 switch (howto->type)
11175 {
11176 default:
11177 addend += increment;
11178 break;
11179
11180 case R_ARM_PC24:
c6596c5e 11181 case R_ARM_PLT32:
5b5bb741
PB		 11182 case R_ARM_CALL:
11183 case R_ARM_JUMP24:
9a5aca8c 11184 addend <<= howto->size;
dc810e39 11185 addend += increment;
9a5aca8c
AM		 11186
11187 /* Should we check for overflow here ? */
11188
11189 /* Drop any undesired bits. */
11190 addend >>= howto->rightshift;
11191 break;
11192 }
11193
11194 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
11195
11196 bfd_put_32 (abfd, contents, address);
ddda4409 11197 }
98c1d4aa 11198}
252b5132 11199
ba93b8ac
DJ		 11200#define IS_ARM_TLS_RELOC(R_TYPE) \
11201 ((R_TYPE) == R_ARM_TLS_GD32 \
11202 || (R_TYPE) == R_ARM_TLS_LDO32 \
11203 || (R_TYPE) == R_ARM_TLS_LDM32 \
11204 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11205 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11206 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11207 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 11208 || (R_TYPE) == R_ARM_TLS_IE32 \
11209 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11210
11211/* Specific set of relocations for the gnu tls dialect. */
11212#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11213 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11214 || (R_TYPE) == R_ARM_TLS_CALL \
11215 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11216 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11217 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 11218
252b5132 11219/* Relocate an ARM ELF section. */
906e58ca 11220
b34976b6 11221static bfd_boolean
57e8b36a
NC		 11222elf32_arm_relocate_section (bfd * output_bfd,
11223 struct bfd_link_info * info,
11224 bfd * input_bfd,
11225 asection * input_section,
11226 bfd_byte * contents,
11227 Elf_Internal_Rela * relocs,
11228 Elf_Internal_Sym * local_syms,
11229 asection ** local_sections)
252b5132 11230{
b34976b6
AM		 11231 Elf_Internal_Shdr *symtab_hdr;
11232 struct elf_link_hash_entry **sym_hashes;
11233 Elf_Internal_Rela *rel;
11234 Elf_Internal_Rela *relend;
11235 const char *name;
b32d3aa2 11236 struct elf32_arm_link_hash_table * globals;
252b5132 11237
4e7fd91e 11238 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 11239 if (globals == NULL)
11240 return FALSE;
b491616a 11241
0ffa91dd 11242 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 11243 sym_hashes = elf_sym_hashes (input_bfd);
11244
11245 rel = relocs;
11246 relend = relocs + input_section->reloc_count;
11247 for (; rel < relend; rel++)
11248 {
ba96a88f
NC		 11249 int r_type;
11250 reloc_howto_type * howto;
11251 unsigned long r_symndx;
11252 Elf_Internal_Sym * sym;
11253 asection * sec;
252b5132 11254 struct elf_link_hash_entry * h;
ba96a88f
NC		 11255 bfd_vma relocation;
11256 bfd_reloc_status_type r;
11257 arelent bfd_reloc;
ba93b8ac 11258 char sym_type;
0945cdfd 11259 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 11260 char *error_message = NULL;
f21f3fe0 11261
252b5132 11262 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 11263 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 11264 r_type = arm_real_reloc_type (globals, r_type);
252b5132 11265
ba96a88f 11266 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 11267 || r_type == R_ARM_GNU_VTINHERIT)
11268 continue;
252b5132 11269
b32d3aa2 11270 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 11271 howto = bfd_reloc.howto;
252b5132 11272
252b5132
RH		 11273 h = NULL;
11274 sym = NULL;
11275 sec = NULL;
9b485d32 11276
252b5132
RH		 11277 if (r_symndx < symtab_hdr->sh_info)
11278 {
11279 sym = local_syms + r_symndx;
ba93b8ac 11280 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 11281 sec = local_sections[r_symndx];
ffcb4889
NS		 11282
11283 /* An object file might have a reference to a local
11284 undefined symbol. This is a daft object file, but we
11285 should at least do something about it. V4BX & NONE
11286 relocations do not use the symbol and are explicitly
77b4f08f
TS		 11287 allowed to use the undefined symbol, so allow those.
11288 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 11289 if (r_type != R_ARM_V4BX
11290 && r_type != R_ARM_NONE
77b4f08f 11291 && r_symndx != STN_UNDEF
ffcb4889
NS		 11292 && bfd_is_und_section (sec)
11293 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
11294 {
11295 if (!info->callbacks->undefined_symbol
11296 (info, bfd_elf_string_from_elf_section
11297 (input_bfd, symtab_hdr->sh_link, sym->st_name),
11298 input_bfd, input_section,
11299 rel->r_offset, TRUE))
11300 return FALSE;
11301 }
b38cadfb 11302
4e7fd91e 11303 if (globals->use_rel)
f8df10f4 11304 {
4e7fd91e
PB		 11305 relocation = (sec->output_section->vma
11306 + sec->output_offset
11307 + sym->st_value);
0e1862bb 11308 if (!bfd_link_relocatable (info)
ab96bf03
AM		 11309 && (sec->flags & SEC_MERGE)
11310 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 11311 {
4e7fd91e
PB		 11312 asection *msec;
11313 bfd_vma addend, value;
11314
39623e12 11315 switch (r_type)
4e7fd91e 11316 {
39623e12
PB		 11317 case R_ARM_MOVW_ABS_NC:
11318 case R_ARM_MOVT_ABS:
11319 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11320 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
11321 addend = (addend ^ 0x8000) - 0x8000;
11322 break;
f8df10f4 11323
39623e12
PB		 11324 case R_ARM_THM_MOVW_ABS_NC:
11325 case R_ARM_THM_MOVT_ABS:
11326 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
11327 << 16;
11328 value |= bfd_get_16 (input_bfd,
11329 contents + rel->r_offset + 2);
11330 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
11331 | ((value & 0x04000000) >> 15);
11332 addend = (addend ^ 0x8000) - 0x8000;
11333 break;
f8df10f4 11334
39623e12
PB		 11335 default:
11336 if (howto->rightshift
11337 || (howto->src_mask & (howto->src_mask + 1)))
11338 {
11339 (*_bfd_error_handler)
11340 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
11341 input_bfd, input_section,
11342 (long) rel->r_offset, howto->name);
11343 return FALSE;
11344 }
11345
11346 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11347
11348 /* Get the (signed) value from the instruction. */
11349 addend = value & howto->src_mask;
11350 if (addend & ((howto->src_mask + 1) >> 1))
11351 {
11352 bfd_signed_vma mask;
11353
11354 mask = -1;
11355 mask &= ~ howto->src_mask;
11356 addend |= mask;
11357 }
11358 break;
4e7fd91e 11359 }
39623e12 11360
4e7fd91e
PB		 11361 msec = sec;
11362 addend =
11363 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
11364 - relocation;
11365 addend += msec->output_section->vma + msec->output_offset;
39623e12 11366
cc643b88 11367 /* Cases here must match those in the preceding
39623e12
PB		 11368 switch statement. */
11369 switch (r_type)
11370 {
11371 case R_ARM_MOVW_ABS_NC:
11372 case R_ARM_MOVT_ABS:
11373 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
11374 | (addend & 0xfff);
11375 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11376 break;
11377
11378 case R_ARM_THM_MOVW_ABS_NC:
11379 case R_ARM_THM_MOVT_ABS:
11380 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
11381 | (addend & 0xff) | ((addend & 0x0800) << 15);
11382 bfd_put_16 (input_bfd, value >> 16,
11383 contents + rel->r_offset);
11384 bfd_put_16 (input_bfd, value,
11385 contents + rel->r_offset + 2);
11386 break;
11387
11388 default:
11389 value = (value & ~ howto->dst_mask)
11390 | (addend & howto->dst_mask);
11391 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11392 break;
11393 }
f8df10f4 11394 }
f8df10f4 11395 }
4e7fd91e
PB		 11396 else
11397 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 11398 }
11399 else
11400 {
62d887d4 11401 bfd_boolean warned, ignored;
560e09e9 11402
b2a8e766
AM		 11403 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
11404 r_symndx, symtab_hdr, sym_hashes,
11405 h, sec, relocation,
62d887d4 11406 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 11407
11408 sym_type = h->type;
252b5132
RH		 11409 }
11410
dbaa2011 11411 if (sec != NULL && discarded_section (sec))
e4067dbb 11412 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 11413 rel, 1, relend, howto, 0, contents);
ab96bf03 11414
0e1862bb 11415 if (bfd_link_relocatable (info))
ab96bf03
AM		 11416 {
11417 /* This is a relocatable link. We don't have to change
11418 anything, unless the reloc is against a section symbol,
11419 in which case we have to adjust according to where the
11420 section symbol winds up in the output section. */
11421 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
11422 {
11423 if (globals->use_rel)
11424 arm_add_to_rel (input_bfd, contents + rel->r_offset,
11425 howto, (bfd_signed_vma) sec->output_offset);
11426 else
11427 rel->r_addend += sec->output_offset;
11428 }
11429 continue;
11430 }
11431
252b5132
RH		 11432 if (h != NULL)
11433 name = h->root.root.string;
11434 else
11435 {
11436 name = (bfd_elf_string_from_elf_section
11437 (input_bfd, symtab_hdr->sh_link, sym->st_name));
11438 if (name == NULL || *name == '\0')
11439 name = bfd_section_name (input_bfd, sec);
11440 }
f21f3fe0 11441
cf35638d 11442 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 11443 && r_type != R_ARM_NONE
11444 && (h == NULL
11445 || h->root.type == bfd_link_hash_defined
11446 || h->root.type == bfd_link_hash_defweak)
11447 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
11448 {
11449 (*_bfd_error_handler)
11450 ((sym_type == STT_TLS
11451 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
11452 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
11453 input_bfd,
11454 input_section,
11455 (long) rel->r_offset,
11456 howto->name,
11457 name);
11458 }
11459
0855e32b 11460 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 11461 done, i.e., the relaxation produced the final output we want,
11462 and we won't let anybody mess with it. Also, we have to do
11463 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 11464 both in relaxed and non-relaxed cases. */
0855e32b
NS		 11465 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
11466 || (IS_ARM_TLS_GNU_RELOC (r_type)
b38cadfb 11467 && !((h ? elf32_arm_hash_entry (h)->tls_type :
0855e32b
NS		 11468 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
11469 & GOT_TLS_GDESC)))
11470 {
11471 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
11472 contents, rel, h == NULL);
11473 /* This may have been marked unresolved because it came from
11474 a shared library. But we've just dealt with that. */
11475 unresolved_reloc = 0;
11476 }
11477 else
11478 r = bfd_reloc_continue;
b38cadfb 11479
0855e32b
NS		 11480 if (r == bfd_reloc_continue)
11481 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
11482 input_section, contents, rel,
34e77a92 11483 relocation, info, sec, name, sym_type,
35fc36a8
RS		 11484 (h ? h->target_internal
11485 : ARM_SYM_BRANCH_TYPE (sym)), h,
0855e32b 11486 &unresolved_reloc, &error_message);
0945cdfd
DJ		 11487
11488 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
11489 because such sections are not SEC_ALLOC and thus ld.so will
11490 not process them. */
11491 if (unresolved_reloc
99059e56
RM		 11492 && !((input_section->flags & SEC_DEBUGGING) != 0
11493 && h->def_dynamic)
1d5316ab
AM		 11494 && _bfd_elf_section_offset (output_bfd, info, input_section,
11495 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 11496 {
11497 (*_bfd_error_handler)
843fe662
L		 11498 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
11499 input_bfd,
11500 input_section,
11501 (long) rel->r_offset,
11502 howto->name,
11503 h->root.root.string);
0945cdfd
DJ		 11504 return FALSE;
11505 }
252b5132
RH		 11506
11507 if (r != bfd_reloc_ok)
11508 {
252b5132
RH		 11509 switch (r)
11510 {
11511 case bfd_reloc_overflow:
cf919dfd
PB		 11512 /* If the overflowing reloc was to an undefined symbol,
11513 we have already printed one error message and there
11514 is no point complaining again. */
11515 if ((! h ||
11516 h->root.type != bfd_link_hash_undefined)
11517 && (!((*info->callbacks->reloc_overflow)
dfeffb9f
L		 11518 (info, (h ? &h->root : NULL), name, howto->name,
11519 (bfd_vma) 0, input_bfd, input_section,
11520 rel->r_offset))))
b34976b6 11521 return FALSE;
252b5132
RH		 11522 break;
11523
11524 case bfd_reloc_undefined:
11525 if (!((*info->callbacks->undefined_symbol)
11526 (info, name, input_bfd, input_section,
b34976b6
AM		 11527 rel->r_offset, TRUE)))
11528 return FALSE;
252b5132
RH		 11529 break;
11530
11531 case bfd_reloc_outofrange:
f2a9dd69 11532 error_message = _("out of range");
252b5132
RH		 11533 goto common_error;
11534
11535 case bfd_reloc_notsupported:
f2a9dd69 11536 error_message = _("unsupported relocation");
252b5132
RH		 11537 goto common_error;
11538
11539 case bfd_reloc_dangerous:
f2a9dd69 11540 /* error_message should already be set. */
252b5132
RH		 11541 goto common_error;
11542
11543 default:
f2a9dd69 11544 error_message = _("unknown error");
8029a119 11545 /* Fall through. */
252b5132
RH		 11546
11547 common_error:
f2a9dd69
DJ		 11548 BFD_ASSERT (error_message != NULL);
11549 if (!((*info->callbacks->reloc_dangerous)
11550 (info, error_message, input_bfd, input_section,
252b5132 11551 rel->r_offset)))
b34976b6 11552 return FALSE;
252b5132
RH		 11553 break;
11554 }
11555 }
11556 }
11557
b34976b6 11558 return TRUE;
252b5132
RH		 11559}
11560
91d6fa6a 11561/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 11562 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 11563 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 11564 maintaining that condition). */
11565
11566static void
11567add_unwind_table_edit (arm_unwind_table_edit **head,
11568 arm_unwind_table_edit **tail,
11569 arm_unwind_edit_type type,
11570 asection *linked_section,
91d6fa6a 11571 unsigned int tindex)
2468f9c9 11572{
21d799b5
NC		 11573 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
11574 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 11575
2468f9c9
PB		 11576 new_edit->type = type;
11577 new_edit->linked_section = linked_section;
91d6fa6a 11578 new_edit->index = tindex;
b38cadfb 11579
91d6fa6a 11580 if (tindex > 0)
2468f9c9
PB		 11581 {
11582 new_edit->next = NULL;
11583
11584 if (*tail)
11585 (*tail)->next = new_edit;
11586
11587 (*tail) = new_edit;
11588
11589 if (!*head)
11590 (*head) = new_edit;
11591 }
11592 else
11593 {
11594 new_edit->next = *head;
11595
11596 if (!*tail)
11597 *tail = new_edit;
11598
11599 *head = new_edit;
11600 }
11601}
11602
11603static _arm_elf_section_data *get_arm_elf_section_data (asection *);
11604
11605/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
11606static void
11607adjust_exidx_size(asection *exidx_sec, int adjust)
11608{
11609 asection *out_sec;
11610
11611 if (!exidx_sec->rawsize)
11612 exidx_sec->rawsize = exidx_sec->size;
11613
11614 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
11615 out_sec = exidx_sec->output_section;
11616 /* Adjust size of output section. */
11617 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
11618}
11619
11620/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
11621static void
11622insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
11623{
11624 struct _arm_elf_section_data *exidx_arm_data;
11625
11626 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11627 add_unwind_table_edit (
11628 &exidx_arm_data->u.exidx.unwind_edit_list,
11629 &exidx_arm_data->u.exidx.unwind_edit_tail,
11630 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
11631
491d01d3
YU		 11632 exidx_arm_data->additional_reloc_count++;
11633
2468f9c9
PB		 11634 adjust_exidx_size(exidx_sec, 8);
11635}
11636
11637/* Scan .ARM.exidx tables, and create a list describing edits which should be
11638 made to those tables, such that:
b38cadfb 11639
2468f9c9
PB		 11640 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
11641 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 11642 codes which have been inlined into the index).
2468f9c9 11643
85fdf906
AH		 11644 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
11645
2468f9c9 11646 The edits are applied when the tables are written
b38cadfb 11647 (in elf32_arm_write_section). */
2468f9c9
PB		 11648
11649bfd_boolean
11650elf32_arm_fix_exidx_coverage (asection **text_section_order,
11651 unsigned int num_text_sections,
85fdf906
AH		 11652 struct bfd_link_info *info,
11653 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 11654{
11655 bfd *inp;
11656 unsigned int last_second_word = 0, i;
11657 asection *last_exidx_sec = NULL;
11658 asection *last_text_sec = NULL;
11659 int last_unwind_type = -1;
11660
11661 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
11662 text sections. */
c72f2fb2 11663 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 11664 {
11665 asection *sec;
b38cadfb 11666
2468f9c9 11667 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 11668 {
2468f9c9
PB		 11669 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
11670 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 11671
dec9d5df 11672 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 11673 continue;
b38cadfb 11674
2468f9c9
PB		 11675 if (elf_sec->linked_to)
11676 {
11677 Elf_Internal_Shdr *linked_hdr
99059e56 11678 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 11679 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 11680 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 11681
11682 if (linked_sec_arm_data == NULL)
99059e56 11683 continue;
2468f9c9
PB		 11684
11685 /* Link this .ARM.exidx section back from the text section it
99059e56 11686 describes. */
2468f9c9
PB		 11687 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
11688 }
11689 }
11690 }
11691
11692 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
11693 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 11694 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 11695
11696 for (i = 0; i < num_text_sections; i++)
11697 {
11698 asection *sec = text_section_order[i];
11699 asection *exidx_sec;
11700 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
11701 struct _arm_elf_section_data *exidx_arm_data;
11702 bfd_byte *contents = NULL;
11703 int deleted_exidx_bytes = 0;
11704 bfd_vma j;
11705 arm_unwind_table_edit *unwind_edit_head = NULL;
11706 arm_unwind_table_edit *unwind_edit_tail = NULL;
11707 Elf_Internal_Shdr *hdr;
11708 bfd *ibfd;
11709
11710 if (arm_data == NULL)
99059e56 11711 continue;
2468f9c9
PB		 11712
11713 exidx_sec = arm_data->u.text.arm_exidx_sec;
11714 if (exidx_sec == NULL)
11715 {
11716 /* Section has no unwind data. */
11717 if (last_unwind_type == 0 || !last_exidx_sec)
11718 continue;
11719
11720 /* Ignore zero sized sections. */
11721 if (sec->size == 0)
11722 continue;
11723
11724 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11725 last_unwind_type = 0;
11726 continue;
11727 }
11728
22a8f80e
PB		 11729 /* Skip /DISCARD/ sections. */
11730 if (bfd_is_abs_section (exidx_sec->output_section))
11731 continue;
11732
2468f9c9
PB		 11733 hdr = &elf_section_data (exidx_sec)->this_hdr;
11734 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 11735 continue;
b38cadfb 11736
2468f9c9
PB		 11737 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11738 if (exidx_arm_data == NULL)
99059e56 11739 continue;
b38cadfb 11740
2468f9c9 11741 ibfd = exidx_sec->owner;
b38cadfb 11742
2468f9c9
PB		 11743 if (hdr->contents != NULL)
11744 contents = hdr->contents;
11745 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
11746 /* An error? */
11747 continue;
11748
ac06903d
YU		 11749 if (last_unwind_type > 0)
11750 {
11751 unsigned int first_word = bfd_get_32 (ibfd, contents);
11752 /* Add cantunwind if first unwind item does not match section
11753 start. */
11754 if (first_word != sec->vma)
11755 {
11756 insert_cantunwind_after (last_text_sec, last_exidx_sec);
11757 last_unwind_type = 0;
11758 }
11759 }
11760
2468f9c9
PB		 11761 for (j = 0; j < hdr->sh_size; j += 8)
11762 {
11763 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
11764 int unwind_type;
11765 int elide = 0;
11766
11767 /* An EXIDX_CANTUNWIND entry. */
11768 if (second_word == 1)
11769 {
11770 if (last_unwind_type == 0)
11771 elide = 1;
11772 unwind_type = 0;
11773 }
11774 /* Inlined unwinding data. Merge if equal to previous. */
11775 else if ((second_word & 0x80000000) != 0)
11776 {
85fdf906
AH		 11777 if (merge_exidx_entries
11778 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 11779 elide = 1;
11780 unwind_type = 1;
11781 last_second_word = second_word;
11782 }
11783 /* Normal table entry. In theory we could merge these too,
11784 but duplicate entries are likely to be much less common. */
11785 else
11786 unwind_type = 2;
11787
491d01d3 11788 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 11789 {
11790 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
11791 DELETE_EXIDX_ENTRY, NULL, j / 8);
11792
11793 deleted_exidx_bytes += 8;
11794 }
11795
11796 last_unwind_type = unwind_type;
11797 }
11798
11799 /* Free contents if we allocated it ourselves. */
11800 if (contents != hdr->contents)
99059e56 11801 free (contents);
2468f9c9
PB		 11802
11803 /* Record edits to be applied later (in elf32_arm_write_section). */
11804 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
11805 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 11806
2468f9c9
PB		 11807 if (deleted_exidx_bytes > 0)
11808 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
11809
11810 last_exidx_sec = exidx_sec;
11811 last_text_sec = sec;
11812 }
11813
11814 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 11815 if (!bfd_link_relocatable (info) && last_exidx_sec
11816 && last_unwind_type != 0)
2468f9c9
PB		 11817 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11818
11819 return TRUE;
11820}
11821
3e6b1042
DJ		 11822static bfd_boolean
11823elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
11824 bfd *ibfd, const char *name)
11825{
11826 asection *sec, *osec;
11827
3d4d4302 11828 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 11829 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
11830 return TRUE;
11831
11832 osec = sec->output_section;
11833 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
11834 return TRUE;
11835
11836 if (! bfd_set_section_contents (obfd, osec, sec->contents,
11837 sec->output_offset, sec->size))
11838 return FALSE;
11839
11840 return TRUE;
11841}
11842
11843static bfd_boolean
11844elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
11845{
11846 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 11847 asection *sec, *osec;
3e6b1042 11848
4dfe6ac6
NC		 11849 if (globals == NULL)
11850 return FALSE;
11851
3e6b1042
DJ		 11852 /* Invoke the regular ELF backend linker to do all the work. */
11853 if (!bfd_elf_final_link (abfd, info))
11854 return FALSE;
11855
fe33d2fa
CL		 11856 /* Process stub sections (eg BE8 encoding, ...). */
11857 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 11858 unsigned int i;
cdb21a0a
NS		 11859 for (i=0; i<htab->top_id; i++)
11860 {
11861 sec = htab->stub_group[i].stub_sec;
11862 /* Only process it once, in its link_sec slot. */
11863 if (sec && i == htab->stub_group[i].link_sec->id)
11864 {
11865 osec = sec->output_section;
11866 elf32_arm_write_section (abfd, info, sec, sec->contents);
11867 if (! bfd_set_section_contents (abfd, osec, sec->contents,
11868 sec->output_offset, sec->size))
11869 return FALSE;
11870 }
fe33d2fa 11871 }
fe33d2fa 11872
3e6b1042
DJ		 11873 /* Write out any glue sections now that we have created all the
11874 stubs. */
11875 if (globals->bfd_of_glue_owner != NULL)
11876 {
11877 if (! elf32_arm_output_glue_section (info, abfd,
11878 globals->bfd_of_glue_owner,
11879 ARM2THUMB_GLUE_SECTION_NAME))
11880 return FALSE;
11881
11882 if (! elf32_arm_output_glue_section (info, abfd,
11883 globals->bfd_of_glue_owner,
11884 THUMB2ARM_GLUE_SECTION_NAME))
11885 return FALSE;
11886
11887 if (! elf32_arm_output_glue_section (info, abfd,
11888 globals->bfd_of_glue_owner,
11889 VFP11_ERRATUM_VENEER_SECTION_NAME))
11890 return FALSE;
11891
a504d23a
LA		 11892 if (! elf32_arm_output_glue_section (info, abfd,
11893 globals->bfd_of_glue_owner,
11894 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
11895 return FALSE;
11896
3e6b1042
DJ		 11897 if (! elf32_arm_output_glue_section (info, abfd,
11898 globals->bfd_of_glue_owner,
11899 ARM_BX_GLUE_SECTION_NAME))
11900 return FALSE;
11901 }
11902
11903 return TRUE;
11904}
11905
5968a7b8
NC		 11906/* Return a best guess for the machine number based on the attributes. */
11907
11908static unsigned int
11909bfd_arm_get_mach_from_attributes (bfd * abfd)
11910{
11911 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
11912
11913 switch (arch)
11914 {
11915 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
11916 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
11917 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
11918
11919 case TAG_CPU_ARCH_V5TE:
11920 {
11921 char * name;
11922
11923 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
11924 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
11925
11926 if (name)
11927 {
11928 if (strcmp (name, "IWMMXT2") == 0)
11929 return bfd_mach_arm_iWMMXt2;
11930
11931 if (strcmp (name, "IWMMXT") == 0)
6034aab8 11932 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 11933
11934 if (strcmp (name, "XSCALE") == 0)
11935 {
11936 int wmmx;
11937
11938 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
11939 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
11940 switch (wmmx)
11941 {
11942 case 1: return bfd_mach_arm_iWMMXt;
11943 case 2: return bfd_mach_arm_iWMMXt2;
11944 default: return bfd_mach_arm_XScale;
11945 }
11946 }
5968a7b8
NC		 11947 }
11948
11949 return bfd_mach_arm_5TE;
11950 }
11951
11952 default:
11953 return bfd_mach_arm_unknown;
11954 }
11955}
11956
c178919b
NC		 11957/* Set the right machine number. */
11958
11959static bfd_boolean
57e8b36a 11960elf32_arm_object_p (bfd *abfd)
c178919b 11961{
5a6c6817 11962 unsigned int mach;
57e8b36a 11963
5a6c6817 11964 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 11965
5968a7b8
NC		 11966 if (mach == bfd_mach_arm_unknown)
11967 {
11968 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
11969 mach = bfd_mach_arm_ep9312;
11970 else
11971 mach = bfd_arm_get_mach_from_attributes (abfd);
11972 }
c178919b 11973
5968a7b8 11974 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 11975 return TRUE;
11976}
11977
fc830a83 11978/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 11979
b34976b6 11980static bfd_boolean
57e8b36a 11981elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 11982{
11983 if (elf_flags_init (abfd)
11984 && elf_elfheader (abfd)->e_flags != flags)
11985 {
fc830a83
NC		 11986 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
11987 {
fd2ec330 11988 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 11989 (*_bfd_error_handler)
11990 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
11991 abfd);
fc830a83 11992 else
d003868e
AM		 11993 _bfd_error_handler
11994 (_("Warning: Clearing the interworking flag of %B due to outside request"),
11995 abfd);
fc830a83 11996 }
252b5132
RH		 11997 }
11998 else
11999 {
12000 elf_elfheader (abfd)->e_flags = flags;
b34976b6 12001 elf_flags_init (abfd) = TRUE;
252b5132
RH		 12002 }
12003
b34976b6 12004 return TRUE;
252b5132
RH		 12005}
12006
fc830a83 12007/* Copy backend specific data from one object module to another. */
9b485d32 12008
b34976b6 12009static bfd_boolean
57e8b36a 12010elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 12011{
12012 flagword in_flags;
12013 flagword out_flags;
12014
0ffa91dd 12015 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 12016 return TRUE;
252b5132 12017
fc830a83 12018 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 12019 out_flags = elf_elfheader (obfd)->e_flags;
12020
fc830a83
NC		 12021 if (elf_flags_init (obfd)
12022 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
12023 && in_flags != out_flags)
252b5132 12024 {
252b5132 12025 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 12026 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 12027 return FALSE;
252b5132
RH		 12028
12029 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 12030 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 12031 return FALSE;
252b5132
RH		 12032
12033 /* If the src and dest have different interworking flags
99059e56 12034 then turn off the interworking bit. */
fd2ec330 12035 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 12036 {
fd2ec330 12037 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 12038 _bfd_error_handler
12039 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
12040 obfd, ibfd);
252b5132 12041
fd2ec330 12042 in_flags &= ~EF_ARM_INTERWORK;
252b5132 12043 }
1006ba19
PB		 12044
12045 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 12046 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
12047 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 12048 }
12049
12050 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 12051 elf_flags_init (obfd) = TRUE;
252b5132 12052
e2349352 12053 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 12054}
12055
12056/* Values for Tag_ABI_PCS_R9_use. */
12057enum
12058{
12059 AEABI_R9_V6,
12060 AEABI_R9_SB,
12061 AEABI_R9_TLS,
12062 AEABI_R9_unused
12063};
12064
12065/* Values for Tag_ABI_PCS_RW_data. */
12066enum
12067{
12068 AEABI_PCS_RW_data_absolute,
12069 AEABI_PCS_RW_data_PCrel,
12070 AEABI_PCS_RW_data_SBrel,
12071 AEABI_PCS_RW_data_unused
12072};
12073
12074/* Values for Tag_ABI_enum_size. */
12075enum
12076{
12077 AEABI_enum_unused,
12078 AEABI_enum_short,
12079 AEABI_enum_wide,
12080 AEABI_enum_forced_wide
12081};
12082
104d59d1
JM		 12083/* Determine whether an object attribute tag takes an integer, a
12084 string or both. */
906e58ca 12085
104d59d1
JM		 12086static int
12087elf32_arm_obj_attrs_arg_type (int tag)
12088{
12089 if (tag == Tag_compatibility)
3483fe2e 12090 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 12091 else if (tag == Tag_nodefaults)
3483fe2e
AS		 12092 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
12093 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
12094 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 12095 else if (tag < 32)
3483fe2e 12096 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 12097 else
3483fe2e 12098 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 12099}
12100
5aa6ff7c
AS		 12101/* The ABI defines that Tag_conformance should be emitted first, and that
12102 Tag_nodefaults should be second (if either is defined). This sets those
12103 two positions, and bumps up the position of all the remaining tags to
12104 compensate. */
12105static int
12106elf32_arm_obj_attrs_order (int num)
12107{
3de4a297 12108 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 12109 return Tag_conformance;
3de4a297 12110 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 12111 return Tag_nodefaults;
12112 if ((num - 2) < Tag_nodefaults)
12113 return num - 2;
12114 if ((num - 1) < Tag_conformance)
12115 return num - 1;
12116 return num;
12117}
12118
e8b36cd1
JM		 12119/* Attribute numbers >=64 (mod 128) can be safely ignored. */
12120static bfd_boolean
12121elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
12122{
12123 if ((tag & 127) < 64)
12124 {
12125 _bfd_error_handler
12126 (_("%B: Unknown mandatory EABI object attribute %d"),
12127 abfd, tag);
12128 bfd_set_error (bfd_error_bad_value);
12129 return FALSE;
12130 }
12131 else
12132 {
12133 _bfd_error_handler
12134 (_("Warning: %B: Unknown EABI object attribute %d"),
12135 abfd, tag);
12136 return TRUE;
12137 }
12138}
12139
91e22acd
AS		 12140/* Read the architecture from the Tag_also_compatible_with attribute, if any.
12141 Returns -1 if no architecture could be read. */
12142
12143static int
12144get_secondary_compatible_arch (bfd *abfd)
12145{
12146 obj_attribute *attr =
12147 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
12148
12149 /* Note: the tag and its argument below are uleb128 values, though
12150 currently-defined values fit in one byte for each. */
12151 if (attr->s
12152 && attr->s[0] == Tag_CPU_arch
12153 && (attr->s[1] & 128) != 128
12154 && attr->s[2] == 0)
12155 return attr->s[1];
12156
12157 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12158 return -1;
12159}
12160
12161/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12162 The tag is removed if ARCH is -1. */
12163
8e79c3df 12164static void
91e22acd 12165set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 12166{
91e22acd
AS		 12167 obj_attribute *attr =
12168 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 12169
91e22acd
AS		 12170 if (arch == -1)
12171 {
12172 attr->s = NULL;
12173 return;
8e79c3df 12174 }
91e22acd
AS		 12175
12176 /* Note: the tag and its argument below are uleb128 values, though
12177 currently-defined values fit in one byte for each. */
12178 if (!attr->s)
21d799b5 12179 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 12180 attr->s[0] = Tag_CPU_arch;
12181 attr->s[1] = arch;
12182 attr->s[2] = '\0';
8e79c3df
CM		 12183}
12184
91e22acd
AS		 12185/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12186 into account. */
12187
12188static int
12189tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
12190 int newtag, int secondary_compat)
8e79c3df 12191{
91e22acd
AS		 12192#define T(X) TAG_CPU_ARCH_##X
12193 int tagl, tagh, result;
12194 const int v6t2[] =
12195 {
12196 T(V6T2), /* PRE_V4. */
12197 T(V6T2), /* V4. */
12198 T(V6T2), /* V4T. */
12199 T(V6T2), /* V5T. */
12200 T(V6T2), /* V5TE. */
12201 T(V6T2), /* V5TEJ. */
12202 T(V6T2), /* V6. */
12203 T(V7), /* V6KZ. */
12204 T(V6T2) /* V6T2. */
12205 };
12206 const int v6k[] =
12207 {
12208 T(V6K), /* PRE_V4. */
12209 T(V6K), /* V4. */
12210 T(V6K), /* V4T. */
12211 T(V6K), /* V5T. */
12212 T(V6K), /* V5TE. */
12213 T(V6K), /* V5TEJ. */
12214 T(V6K), /* V6. */
12215 T(V6KZ), /* V6KZ. */
12216 T(V7), /* V6T2. */
12217 T(V6K) /* V6K. */
12218 };
12219 const int v7[] =
12220 {
12221 T(V7), /* PRE_V4. */
12222 T(V7), /* V4. */
12223 T(V7), /* V4T. */
12224 T(V7), /* V5T. */
12225 T(V7), /* V5TE. */
12226 T(V7), /* V5TEJ. */
12227 T(V7), /* V6. */
12228 T(V7), /* V6KZ. */
12229 T(V7), /* V6T2. */
12230 T(V7), /* V6K. */
12231 T(V7) /* V7. */
12232 };
12233 const int v6_m[] =
12234 {
12235 -1, /* PRE_V4. */
12236 -1, /* V4. */
12237 T(V6K), /* V4T. */
12238 T(V6K), /* V5T. */
12239 T(V6K), /* V5TE. */
12240 T(V6K), /* V5TEJ. */
12241 T(V6K), /* V6. */
12242 T(V6KZ), /* V6KZ. */
12243 T(V7), /* V6T2. */
12244 T(V6K), /* V6K. */
12245 T(V7), /* V7. */
12246 T(V6_M) /* V6_M. */
12247 };
12248 const int v6s_m[] =
12249 {
12250 -1, /* PRE_V4. */
12251 -1, /* V4. */
12252 T(V6K), /* V4T. */
12253 T(V6K), /* V5T. */
12254 T(V6K), /* V5TE. */
12255 T(V6K), /* V5TEJ. */
12256 T(V6K), /* V6. */
12257 T(V6KZ), /* V6KZ. */
12258 T(V7), /* V6T2. */
12259 T(V6K), /* V6K. */
12260 T(V7), /* V7. */
12261 T(V6S_M), /* V6_M. */
12262 T(V6S_M) /* V6S_M. */
12263 };
9e3c6df6
PB		 12264 const int v7e_m[] =
12265 {
12266 -1, /* PRE_V4. */
12267 -1, /* V4. */
12268 T(V7E_M), /* V4T. */
12269 T(V7E_M), /* V5T. */
12270 T(V7E_M), /* V5TE. */
12271 T(V7E_M), /* V5TEJ. */
12272 T(V7E_M), /* V6. */
12273 T(V7E_M), /* V6KZ. */
12274 T(V7E_M), /* V6T2. */
12275 T(V7E_M), /* V6K. */
12276 T(V7E_M), /* V7. */
12277 T(V7E_M), /* V6_M. */
12278 T(V7E_M), /* V6S_M. */
12279 T(V7E_M) /* V7E_M. */
12280 };
bca38921
MGD		 12281 const int v8[] =
12282 {
12283 T(V8), /* PRE_V4. */
12284 T(V8), /* V4. */
12285 T(V8), /* V4T. */
12286 T(V8), /* V5T. */
12287 T(V8), /* V5TE. */
12288 T(V8), /* V5TEJ. */
12289 T(V8), /* V6. */
12290 T(V8), /* V6KZ. */
12291 T(V8), /* V6T2. */
12292 T(V8), /* V6K. */
12293 T(V8), /* V7. */
12294 T(V8), /* V6_M. */
12295 T(V8), /* V6S_M. */
12296 T(V8), /* V7E_M. */
12297 T(V8) /* V8. */
12298 };
2fd158eb
TP		 12299 const int v8m_baseline[] =
12300 {
12301 -1, /* PRE_V4. */
12302 -1, /* V4. */
12303 -1, /* V4T. */
12304 -1, /* V5T. */
12305 -1, /* V5TE. */
12306 -1, /* V5TEJ. */
12307 -1, /* V6. */
12308 -1, /* V6KZ. */
12309 -1, /* V6T2. */
12310 -1, /* V6K. */
12311 -1, /* V7. */
12312 T(V8M_BASE), /* V6_M. */
12313 T(V8M_BASE), /* V6S_M. */
12314 -1, /* V7E_M. */
12315 -1, /* V8. */
12316 -1,
12317 T(V8M_BASE) /* V8-M BASELINE. */
12318 };
12319 const int v8m_mainline[] =
12320 {
12321 -1, /* PRE_V4. */
12322 -1, /* V4. */
12323 -1, /* V4T. */
12324 -1, /* V5T. */
12325 -1, /* V5TE. */
12326 -1, /* V5TEJ. */
12327 -1, /* V6. */
12328 -1, /* V6KZ. */
12329 -1, /* V6T2. */
12330 -1, /* V6K. */
12331 T(V8M_MAIN), /* V7. */
12332 T(V8M_MAIN), /* V6_M. */
12333 T(V8M_MAIN), /* V6S_M. */
12334 T(V8M_MAIN), /* V7E_M. */
12335 -1, /* V8. */
12336 -1,
12337 T(V8M_MAIN), /* V8-M BASELINE. */
12338 T(V8M_MAIN) /* V8-M MAINLINE. */
12339 };
91e22acd
AS		 12340 const int v4t_plus_v6_m[] =
12341 {
12342 -1, /* PRE_V4. */
12343 -1, /* V4. */
12344 T(V4T), /* V4T. */
12345 T(V5T), /* V5T. */
12346 T(V5TE), /* V5TE. */
12347 T(V5TEJ), /* V5TEJ. */
12348 T(V6), /* V6. */
12349 T(V6KZ), /* V6KZ. */
12350 T(V6T2), /* V6T2. */
12351 T(V6K), /* V6K. */
12352 T(V7), /* V7. */
12353 T(V6_M), /* V6_M. */
12354 T(V6S_M), /* V6S_M. */
9e3c6df6 12355 T(V7E_M), /* V7E_M. */
bca38921 12356 T(V8), /* V8. */
4ed7ed8d 12357 -1, /* Unused. */
2fd158eb
TP		 12358 T(V8M_BASE), /* V8-M BASELINE. */
12359 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 12360 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
12361 };
12362 const int *comb[] =
12363 {
12364 v6t2,
12365 v6k,
12366 v7,
12367 v6_m,
12368 v6s_m,
9e3c6df6 12369 v7e_m,
bca38921 12370 v8,
4ed7ed8d 12371 NULL,
2fd158eb
TP		 12372 v8m_baseline,
12373 v8m_mainline,
91e22acd
AS		 12374 /* Pseudo-architecture. */
12375 v4t_plus_v6_m
12376 };
12377
12378 /* Check we've not got a higher architecture than we know about. */
12379
9e3c6df6 12380 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 12381 {
3895f852 12382 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 12383 return -1;
12384 }
12385
12386 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12387
12388 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
12389 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
12390 oldtag = T(V4T_PLUS_V6_M);
12391
12392 /* And override the new tag if we have a Tag_also_compatible_with on the
12393 input. */
12394
12395 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
12396 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
12397 newtag = T(V4T_PLUS_V6_M);
12398
12399 tagl = (oldtag < newtag) ? oldtag : newtag;
12400 result = tagh = (oldtag > newtag) ? oldtag : newtag;
12401
12402 /* Architectures before V6KZ add features monotonically. */
12403 if (tagh <= TAG_CPU_ARCH_V6KZ)
12404 return result;
12405
4ed7ed8d 12406 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 12407
12408 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
12409 as the canonical version. */
12410 if (result == T(V4T_PLUS_V6_M))
12411 {
12412 result = T(V4T);
12413 *secondary_compat_out = T(V6_M);
12414 }
12415 else
12416 *secondary_compat_out = -1;
12417
12418 if (result == -1)
12419 {
3895f852 12420 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 12421 ibfd, oldtag, newtag);
12422 return -1;
12423 }
12424
12425 return result;
12426#undef T
8e79c3df
CM		 12427}
12428
ac56ee8f
MGD		 12429/* Query attributes object to see if integer divide instructions may be
12430 present in an object. */
12431static bfd_boolean
12432elf32_arm_attributes_accept_div (const obj_attribute *attr)
12433{
12434 int arch = attr[Tag_CPU_arch].i;
12435 int profile = attr[Tag_CPU_arch_profile].i;
12436
12437 switch (attr[Tag_DIV_use].i)
12438 {
12439 case 0:
12440 /* Integer divide allowed if instruction contained in archetecture. */
12441 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
12442 return TRUE;
12443 else if (arch >= TAG_CPU_ARCH_V7E_M)
12444 return TRUE;
12445 else
12446 return FALSE;
12447
12448 case 1:
12449 /* Integer divide explicitly prohibited. */
12450 return FALSE;
12451
12452 default:
12453 /* Unrecognised case - treat as allowing divide everywhere. */
12454 case 2:
12455 /* Integer divide allowed in ARM state. */
12456 return TRUE;
12457 }
12458}
12459
12460/* Query attributes object to see if integer divide instructions are
12461 forbidden to be in the object. This is not the inverse of
12462 elf32_arm_attributes_accept_div. */
12463static bfd_boolean
12464elf32_arm_attributes_forbid_div (const obj_attribute *attr)
12465{
12466 return attr[Tag_DIV_use].i == 1;
12467}
12468
ee065d83
PB		 12469/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
12470 are conflicting attributes. */
906e58ca 12471
ee065d83
PB		 12472static bfd_boolean
12473elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
12474{
104d59d1
JM		 12475 obj_attribute *in_attr;
12476 obj_attribute *out_attr;
ee065d83
PB		 12477 /* Some tags have 0 = don't care, 1 = strong requirement,
12478 2 = weak requirement. */
91e22acd 12479 static const int order_021[3] = {0, 2, 1};
ee065d83 12480 int i;
91e22acd 12481 bfd_boolean result = TRUE;
9274e9de 12482 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 12483
3e6b1042
DJ		 12484 /* Skip the linker stubs file. This preserves previous behavior
12485 of accepting unknown attributes in the first input file - but
12486 is that a bug? */
12487 if (ibfd->flags & BFD_LINKER_CREATED)
12488 return TRUE;
12489
9274e9de
TG		 12490 /* Skip any input that hasn't attribute section.
12491 This enables to link object files without attribute section with
12492 any others. */
12493 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
12494 return TRUE;
12495
104d59d1 12496 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 12497 {
12498 /* This is the first object. Copy the attributes. */
104d59d1 12499 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 12500
cd21e546
MGD		 12501 out_attr = elf_known_obj_attributes_proc (obfd);
12502
004ae526
PB		 12503 /* Use the Tag_null value to indicate the attributes have been
12504 initialized. */
cd21e546 12505 out_attr[0].i = 1;
004ae526 12506
cd21e546
MGD		 12507 /* We do not output objects with Tag_MPextension_use_legacy - we move
12508 the attribute's value to Tag_MPextension_use. */
12509 if (out_attr[Tag_MPextension_use_legacy].i != 0)
12510 {
12511 if (out_attr[Tag_MPextension_use].i != 0
12512 && out_attr[Tag_MPextension_use_legacy].i
99059e56 12513 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 12514 {
12515 _bfd_error_handler
12516 (_("Error: %B has both the current and legacy "
12517 "Tag_MPextension_use attributes"), ibfd);
12518 result = FALSE;
12519 }
12520
12521 out_attr[Tag_MPextension_use] =
12522 out_attr[Tag_MPextension_use_legacy];
12523 out_attr[Tag_MPextension_use_legacy].type = 0;
12524 out_attr[Tag_MPextension_use_legacy].i = 0;
12525 }
12526
12527 return result;
ee065d83
PB		 12528 }
12529
104d59d1
JM		 12530 in_attr = elf_known_obj_attributes_proc (ibfd);
12531 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 12532 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
12533 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
12534 {
5c294fee
TG		 12535 /* Ignore mismatches if the object doesn't use floating point or is
12536 floating point ABI independent. */
12537 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
12538 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12539 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 12540 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 12541 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12542 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 12543 {
12544 _bfd_error_handler
3895f852 12545 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 12546 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
12547 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 12548 result = FALSE;
ee065d83
PB		 12549 }
12550 }
12551
3de4a297 12552 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 12553 {
12554 /* Merge this attribute with existing attributes. */
12555 switch (i)
12556 {
12557 case Tag_CPU_raw_name:
12558 case Tag_CPU_name:
6a631e86 12559 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 12560 break;
12561
12562 case Tag_ABI_optimization_goals:
12563 case Tag_ABI_FP_optimization_goals:
12564 /* Use the first value seen. */
12565 break;
12566
12567 case Tag_CPU_arch:
91e22acd
AS		 12568 {
12569 int secondary_compat = -1, secondary_compat_out = -1;
12570 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 12571 int arch_attr;
12572 static const char *name_table[] =
12573 {
91e22acd
AS		 12574 /* These aren't real CPU names, but we can't guess
12575 that from the architecture version alone. */
12576 "Pre v4",
12577 "ARM v4",
12578 "ARM v4T",
12579 "ARM v5T",
12580 "ARM v5TE",
12581 "ARM v5TEJ",
12582 "ARM v6",
12583 "ARM v6KZ",
12584 "ARM v6T2",
12585 "ARM v6K",
12586 "ARM v7",
12587 "ARM v6-M",
bca38921 12588 "ARM v6S-M",
2fd158eb
TP		 12589 "ARM v8",
12590 "",
12591 "ARM v8-M.baseline",
12592 "ARM v8-M.mainline",
91e22acd
AS		 12593 };
12594
12595 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
12596 secondary_compat = get_secondary_compatible_arch (ibfd);
12597 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 12598 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
12599 &secondary_compat_out,
12600 in_attr[i].i,
12601 secondary_compat);
12602
12603 /* Return with error if failed to merge. */
12604 if (arch_attr == -1)
12605 return FALSE;
12606
12607 out_attr[i].i = arch_attr;
12608
91e22acd
AS		 12609 set_secondary_compatible_arch (obfd, secondary_compat_out);
12610
12611 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
12612 if (out_attr[i].i == saved_out_attr)
12613 ; /* Leave the names alone. */
12614 else if (out_attr[i].i == in_attr[i].i)
12615 {
12616 /* The output architecture has been changed to match the
12617 input architecture. Use the input names. */
12618 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
12619 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
12620 : NULL;
12621 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
12622 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
12623 : NULL;
12624 }
12625 else
12626 {
12627 out_attr[Tag_CPU_name].s = NULL;
12628 out_attr[Tag_CPU_raw_name].s = NULL;
12629 }
12630
12631 /* If we still don't have a value for Tag_CPU_name,
12632 make one up now. Tag_CPU_raw_name remains blank. */
12633 if (out_attr[Tag_CPU_name].s == NULL
12634 && out_attr[i].i < ARRAY_SIZE (name_table))
12635 out_attr[Tag_CPU_name].s =
12636 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
12637 }
12638 break;
12639
ee065d83
PB		 12640 case Tag_ARM_ISA_use:
12641 case Tag_THUMB_ISA_use:
ee065d83 12642 case Tag_WMMX_arch:
91e22acd
AS		 12643 case Tag_Advanced_SIMD_arch:
12644 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 12645 case Tag_ABI_FP_rounding:
ee065d83
PB		 12646 case Tag_ABI_FP_exceptions:
12647 case Tag_ABI_FP_user_exceptions:
12648 case Tag_ABI_FP_number_model:
75375b3e 12649 case Tag_FP_HP_extension:
91e22acd
AS		 12650 case Tag_CPU_unaligned_access:
12651 case Tag_T2EE_use:
91e22acd 12652 case Tag_MPextension_use:
ee065d83
PB		 12653 /* Use the largest value specified. */
12654 if (in_attr[i].i > out_attr[i].i)
12655 out_attr[i].i = in_attr[i].i;
12656 break;
12657
75375b3e 12658 case Tag_ABI_align_preserved:
91e22acd
AS		 12659 case Tag_ABI_PCS_RO_data:
12660 /* Use the smallest value specified. */
12661 if (in_attr[i].i < out_attr[i].i)
12662 out_attr[i].i = in_attr[i].i;
12663 break;
12664
75375b3e 12665 case Tag_ABI_align_needed:
91e22acd 12666 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 12667 && (in_attr[Tag_ABI_align_preserved].i == 0
12668 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 12669 {
91e22acd
AS		 12670 /* This error message should be enabled once all non-conformant
12671 binaries in the toolchain have had the attributes set
12672 properly.
ee065d83 12673 _bfd_error_handler
3895f852 12674 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 12675 obfd, ibfd);
12676 result = FALSE; */
ee065d83 12677 }
91e22acd
AS		 12678 /* Fall through. */
12679 case Tag_ABI_FP_denormal:
12680 case Tag_ABI_PCS_GOT_use:
12681 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
12682 value if greater than 2 (for future-proofing). */
12683 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
12684 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
12685 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 12686 out_attr[i].i = in_attr[i].i;
12687 break;
91e22acd 12688
75375b3e
MGD		 12689 case Tag_Virtualization_use:
12690 /* The virtualization tag effectively stores two bits of
12691 information: the intended use of TrustZone (in bit 0), and the
12692 intended use of Virtualization (in bit 1). */
12693 if (out_attr[i].i == 0)
12694 out_attr[i].i = in_attr[i].i;
12695 else if (in_attr[i].i != 0
12696 && in_attr[i].i != out_attr[i].i)
12697 {
12698 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
12699 out_attr[i].i = 3;
12700 else
12701 {
12702 _bfd_error_handler
12703 (_("error: %B: unable to merge virtualization attributes "
12704 "with %B"),
12705 obfd, ibfd);
12706 result = FALSE;
12707 }
12708 }
12709 break;
91e22acd
AS		 12710
12711 case Tag_CPU_arch_profile:
12712 if (out_attr[i].i != in_attr[i].i)
12713 {
12714 /* 0 will merge with anything.
12715 'A' and 'S' merge to 'A'.
12716 'R' and 'S' merge to 'R'.
99059e56 12717 'M' and 'A|R|S' is an error. */
91e22acd
AS		 12718 if (out_attr[i].i == 0
12719 || (out_attr[i].i == 'S'
12720 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
12721 out_attr[i].i = in_attr[i].i;
12722 else if (in_attr[i].i == 0
12723 || (in_attr[i].i == 'S'
12724 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 12725 ; /* Do nothing. */
91e22acd
AS		 12726 else
12727 {
12728 _bfd_error_handler
3895f852 12729 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 12730 ibfd,
12731 in_attr[i].i ? in_attr[i].i : '0',
12732 out_attr[i].i ? out_attr[i].i : '0');
12733 result = FALSE;
12734 }
12735 }
12736 break;
75375b3e 12737 case Tag_FP_arch:
62f3b8c8 12738 {
4547cb56
NC		 12739 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
12740 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
12741 when it's 0. It might mean absence of FP hardware if
99654aaf 12742 Tag_FP_arch is zero. */
4547cb56 12743
a715796b 12744#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 12745 static const struct
12746 {
12747 int ver;
12748 int regs;
bca38921 12749 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 12750 {
12751 {0, 0},
12752 {1, 16},
12753 {2, 16},
12754 {3, 32},
12755 {3, 16},
12756 {4, 32},
bca38921 12757 {4, 16},
a715796b
TG		 12758 {8, 32},
12759 {8, 16}
62f3b8c8
PB		 12760 };
12761 int ver;
12762 int regs;
12763 int newval;
12764
4547cb56
NC		 12765 /* If the output has no requirement about FP hardware,
12766 follow the requirement of the input. */
12767 if (out_attr[i].i == 0)
12768 {
12769 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
12770 out_attr[i].i = in_attr[i].i;
12771 out_attr[Tag_ABI_HardFP_use].i
12772 = in_attr[Tag_ABI_HardFP_use].i;
12773 break;
12774 }
12775 /* If the input has no requirement about FP hardware, do
12776 nothing. */
12777 else if (in_attr[i].i == 0)
12778 {
12779 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
12780 break;
12781 }
12782
12783 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 12784 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 12785
12786 /* If both the input and the output have zero Tag_ABI_HardFP_use,
12787 do nothing. */
12788 if (in_attr[Tag_ABI_HardFP_use].i == 0
12789 && out_attr[Tag_ABI_HardFP_use].i == 0)
12790 ;
12791 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 12792 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 12793 else if (in_attr[Tag_ABI_HardFP_use].i
12794 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 12795 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 12796
12797 /* Now we can handle Tag_FP_arch. */
12798
bca38921
MGD		 12799 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
12800 pick the biggest. */
12801 if (in_attr[i].i >= VFP_VERSION_COUNT
12802 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 12803 {
12804 out_attr[i] = in_attr[i];
12805 break;
12806 }
12807 /* The output uses the superset of input features
12808 (ISA version) and registers. */
12809 ver = vfp_versions[in_attr[i].i].ver;
12810 if (ver < vfp_versions[out_attr[i].i].ver)
12811 ver = vfp_versions[out_attr[i].i].ver;
12812 regs = vfp_versions[in_attr[i].i].regs;
12813 if (regs < vfp_versions[out_attr[i].i].regs)
12814 regs = vfp_versions[out_attr[i].i].regs;
12815 /* This assumes all possible supersets are also a valid
99059e56 12816 options. */
bca38921 12817 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 12818 {
12819 if (regs == vfp_versions[newval].regs
12820 && ver == vfp_versions[newval].ver)
12821 break;
12822 }
12823 out_attr[i].i = newval;
12824 }
b1cc4aeb 12825 break;
ee065d83
PB		 12826 case Tag_PCS_config:
12827 if (out_attr[i].i == 0)
12828 out_attr[i].i = in_attr[i].i;
b6009aca 12829 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 12830 {
12831 /* It's sometimes ok to mix different configs, so this is only
99059e56 12832 a warning. */
ee065d83
PB		 12833 _bfd_error_handler
12834 (_("Warning: %B: Conflicting platform configuration"), ibfd);
12835 }
12836 break;
12837 case Tag_ABI_PCS_R9_use:
004ae526
PB		 12838 if (in_attr[i].i != out_attr[i].i
12839 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 12840 && in_attr[i].i != AEABI_R9_unused)
12841 {
12842 _bfd_error_handler
3895f852 12843 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 12844 result = FALSE;
ee065d83
PB		 12845 }
12846 if (out_attr[i].i == AEABI_R9_unused)
12847 out_attr[i].i = in_attr[i].i;
12848 break;
12849 case Tag_ABI_PCS_RW_data:
12850 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
12851 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
12852 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
12853 {
12854 _bfd_error_handler
3895f852 12855 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 12856 ibfd);
91e22acd 12857 result = FALSE;
ee065d83
PB		 12858 }
12859 /* Use the smallest value specified. */
12860 if (in_attr[i].i < out_attr[i].i)
12861 out_attr[i].i = in_attr[i].i;
12862 break;
ee065d83 12863 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 12864 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
12865 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 12866 {
12867 _bfd_error_handler
a9dc9481
JM		 12868 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
12869 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 12870 }
a9dc9481 12871 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 12872 out_attr[i].i = in_attr[i].i;
12873 break;
ee065d83
PB		 12874 case Tag_ABI_enum_size:
12875 if (in_attr[i].i != AEABI_enum_unused)
12876 {
12877 if (out_attr[i].i == AEABI_enum_unused
12878 || out_attr[i].i == AEABI_enum_forced_wide)
12879 {
12880 /* The existing object is compatible with anything.
12881 Use whatever requirements the new object has. */
12882 out_attr[i].i = in_attr[i].i;
12883 }
12884 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 12885 && out_attr[i].i != in_attr[i].i
0ffa91dd 12886 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 12887 {
91e22acd 12888 static const char *aeabi_enum_names[] =
bf21ed78 12889 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 12890 const char *in_name =
12891 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12892 ? aeabi_enum_names[in_attr[i].i]
12893 : "<unknown>";
12894 const char *out_name =
12895 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12896 ? aeabi_enum_names[out_attr[i].i]
12897 : "<unknown>";
ee065d83 12898 _bfd_error_handler
bf21ed78 12899 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 12900 ibfd, in_name, out_name);
ee065d83
PB		 12901 }
12902 }
12903 break;
12904 case Tag_ABI_VFP_args:
12905 /* Aready done. */
12906 break;
12907 case Tag_ABI_WMMX_args:
12908 if (in_attr[i].i != out_attr[i].i)
12909 {
12910 _bfd_error_handler
3895f852 12911 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 12912 ibfd, obfd);
91e22acd 12913 result = FALSE;
ee065d83
PB		 12914 }
12915 break;
7b86a9fa
AS		 12916 case Tag_compatibility:
12917 /* Merged in target-independent code. */
12918 break;
91e22acd 12919 case Tag_ABI_HardFP_use:
4547cb56 12920 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 12921 break;
12922 case Tag_ABI_FP_16bit_format:
12923 if (in_attr[i].i != 0 && out_attr[i].i != 0)
12924 {
12925 if (in_attr[i].i != out_attr[i].i)
12926 {
12927 _bfd_error_handler
3895f852 12928 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 12929 ibfd, obfd);
12930 result = FALSE;
12931 }
12932 }
12933 if (in_attr[i].i != 0)
12934 out_attr[i].i = in_attr[i].i;
12935 break;
7b86a9fa 12936
cd21e546 12937 case Tag_DIV_use:
ac56ee8f
MGD		 12938 /* A value of zero on input means that the divide instruction may
12939 be used if available in the base architecture as specified via
12940 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
12941 the user did not want divide instructions. A value of 2
12942 explicitly means that divide instructions were allowed in ARM
12943 and Thumb state. */
12944 if (in_attr[i].i == out_attr[i].i)
12945 /* Do nothing. */ ;
12946 else if (elf32_arm_attributes_forbid_div (in_attr)
12947 && !elf32_arm_attributes_accept_div (out_attr))
12948 out_attr[i].i = 1;
12949 else if (elf32_arm_attributes_forbid_div (out_attr)
12950 && elf32_arm_attributes_accept_div (in_attr))
12951 out_attr[i].i = in_attr[i].i;
12952 else if (in_attr[i].i == 2)
12953 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 12954 break;
12955
12956 case Tag_MPextension_use_legacy:
12957 /* We don't output objects with Tag_MPextension_use_legacy - we
12958 move the value to Tag_MPextension_use. */
12959 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
12960 {
12961 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
12962 {
12963 _bfd_error_handler
12964 (_("%B has has both the current and legacy "
b38cadfb 12965 "Tag_MPextension_use attributes"),
cd21e546
MGD		 12966 ibfd);
12967 result = FALSE;
12968 }
12969 }
12970
12971 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
12972 out_attr[Tag_MPextension_use] = in_attr[i];
12973
12974 break;
12975
91e22acd 12976 case Tag_nodefaults:
2d0bb761
AS		 12977 /* This tag is set if it exists, but the value is unused (and is
12978 typically zero). We don't actually need to do anything here -
12979 the merge happens automatically when the type flags are merged
12980 below. */
91e22acd
AS		 12981 break;
12982 case Tag_also_compatible_with:
12983 /* Already done in Tag_CPU_arch. */
12984 break;
12985 case Tag_conformance:
12986 /* Keep the attribute if it matches. Throw it away otherwise.
12987 No attribute means no claim to conform. */
12988 if (!in_attr[i].s || !out_attr[i].s
12989 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
12990 out_attr[i].s = NULL;
12991 break;
3cfad14c 12992
91e22acd 12993 default:
e8b36cd1
JM		 12994 result
12995 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 12996 }
12997
12998 /* If out_attr was copied from in_attr then it won't have a type yet. */
12999 if (in_attr[i].type && !out_attr[i].type)
13000 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 13001 }
13002
104d59d1 13003 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 13004 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
13005 return FALSE;
ee065d83 13006
104d59d1 13007 /* Check for any attributes not known on ARM. */
e8b36cd1 13008 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 13009
91e22acd 13010 return result;
252b5132
RH		 13011}
13012
3a4a14e9
PB		 13013
13014/* Return TRUE if the two EABI versions are incompatible. */
13015
13016static bfd_boolean
13017elf32_arm_versions_compatible (unsigned iver, unsigned over)
13018{
13019 /* v4 and v5 are the same spec before and after it was released,
13020 so allow mixing them. */
13021 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
13022 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
13023 return TRUE;
13024
13025 return (iver == over);
13026}
13027
252b5132
RH		 13028/* Merge backend specific data from an object file to the output
13029 object file when linking. */
9b485d32 13030
b34976b6 13031static bfd_boolean
21d799b5 13032elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 13033
9b485d32
NC		 13034/* Display the flags field. */
13035
b34976b6 13036static bfd_boolean
57e8b36a 13037elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 13038{
fc830a83
NC		 13039 FILE * file = (FILE *) ptr;
13040 unsigned long flags;
252b5132
RH		 13041
13042 BFD_ASSERT (abfd != NULL && ptr != NULL);
13043
13044 /* Print normal ELF private data. */
13045 _bfd_elf_print_private_bfd_data (abfd, ptr);
13046
fc830a83 13047 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 13048 /* Ignore init flag - it may not be set, despite the flags field
13049 containing valid data. */
252b5132
RH		 13050
13051 /* xgettext:c-format */
9b485d32 13052 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 13053
fc830a83
NC		 13054 switch (EF_ARM_EABI_VERSION (flags))
13055 {
13056 case EF_ARM_EABI_UNKNOWN:
4cc11e76 13057 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 13058 official ARM ELF extended ABI. Hence they are only decoded if
13059 the EABI version is not set. */
fd2ec330 13060 if (flags & EF_ARM_INTERWORK)
9b485d32 13061 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 13062
fd2ec330 13063 if (flags & EF_ARM_APCS_26)
6c571f00 13064 fprintf (file, " [APCS-26]");
fc830a83 13065 else
6c571f00 13066 fprintf (file, " [APCS-32]");
9a5aca8c 13067
96a846ea
RE		 13068 if (flags & EF_ARM_VFP_FLOAT)
13069 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 13070 else if (flags & EF_ARM_MAVERICK_FLOAT)
13071 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 13072 else
13073 fprintf (file, _(" [FPA float format]"));
13074
fd2ec330 13075 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 13076 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 13077
fd2ec330 13078 if (flags & EF_ARM_PIC)
9b485d32 13079 fprintf (file, _(" [position independent]"));
fc830a83 13080
fd2ec330 13081 if (flags & EF_ARM_NEW_ABI)
9b485d32 13082 fprintf (file, _(" [new ABI]"));
9a5aca8c 13083
fd2ec330 13084 if (flags & EF_ARM_OLD_ABI)
9b485d32 13085 fprintf (file, _(" [old ABI]"));
9a5aca8c 13086
fd2ec330 13087 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 13088 fprintf (file, _(" [software FP]"));
9a5aca8c 13089
96a846ea
RE		 13090 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
13091 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 13092 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
13093 | EF_ARM_MAVERICK_FLOAT);
fc830a83 13094 break;
9a5aca8c 13095
fc830a83 13096 case EF_ARM_EABI_VER1:
9b485d32 13097 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 13098
fc830a83 13099 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 13100 fprintf (file, _(" [sorted symbol table]"));
fc830a83 13101 else
9b485d32 13102 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 13103
fc830a83
NC		 13104 flags &= ~ EF_ARM_SYMSARESORTED;
13105 break;
9a5aca8c 13106
fd2ec330
PB		 13107 case EF_ARM_EABI_VER2:
13108 fprintf (file, _(" [Version2 EABI]"));
13109
13110 if (flags & EF_ARM_SYMSARESORTED)
13111 fprintf (file, _(" [sorted symbol table]"));
13112 else
13113 fprintf (file, _(" [unsorted symbol table]"));
13114
13115 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
13116 fprintf (file, _(" [dynamic symbols use segment index]"));
13117
13118 if (flags & EF_ARM_MAPSYMSFIRST)
13119 fprintf (file, _(" [mapping symbols precede others]"));
13120
99e4ae17 13121 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 13122 | EF_ARM_MAPSYMSFIRST);
13123 break;
13124
d507cf36
PB		 13125 case EF_ARM_EABI_VER3:
13126 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 13127 break;
13128
13129 case EF_ARM_EABI_VER4:
13130 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 13131 goto eabi;
d507cf36 13132
3a4a14e9
PB		 13133 case EF_ARM_EABI_VER5:
13134 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 13135
13136 if (flags & EF_ARM_ABI_FLOAT_SOFT)
13137 fprintf (file, _(" [soft-float ABI]"));
13138
13139 if (flags & EF_ARM_ABI_FLOAT_HARD)
13140 fprintf (file, _(" [hard-float ABI]"));
13141
13142 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
13143
3a4a14e9 13144 eabi:
d507cf36
PB		 13145 if (flags & EF_ARM_BE8)
13146 fprintf (file, _(" [BE8]"));
13147
13148 if (flags & EF_ARM_LE8)
13149 fprintf (file, _(" [LE8]"));
13150
13151 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
13152 break;
13153
fc830a83 13154 default:
9b485d32 13155 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 13156 break;
13157 }
252b5132 13158
fc830a83 13159 flags &= ~ EF_ARM_EABIMASK;
252b5132 13160
fc830a83 13161 if (flags & EF_ARM_RELEXEC)
9b485d32 13162 fprintf (file, _(" [relocatable executable]"));
252b5132 13163
a5721edd 13164 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 13165
13166 if (flags)
9b485d32 13167 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 13168
252b5132
RH		 13169 fputc ('\n', file);
13170
b34976b6 13171 return TRUE;
252b5132
RH		 13172}
13173
13174static int
57e8b36a 13175elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 13176{
2f0ca46a
NC		 13177 switch (ELF_ST_TYPE (elf_sym->st_info))
13178 {
13179 case STT_ARM_TFUNC:
13180 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 13181
2f0ca46a
NC		 13182 case STT_ARM_16BIT:
13183 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13184 This allows us to distinguish between data used by Thumb instructions
13185 and non-data (which is probably code) inside Thumb regions of an
13186 executable. */
1a0eb693 13187 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 13188 return ELF_ST_TYPE (elf_sym->st_info);
13189 break;
9a5aca8c 13190
ce855c42
NC		 13191 default:
13192 break;
2f0ca46a
NC		 13193 }
13194
13195 return type;
252b5132 13196}
f21f3fe0 13197
252b5132 13198static asection *
07adf181
AM		 13199elf32_arm_gc_mark_hook (asection *sec,
13200 struct bfd_link_info *info,
13201 Elf_Internal_Rela *rel,
13202 struct elf_link_hash_entry *h,
13203 Elf_Internal_Sym *sym)
252b5132
RH		 13204{
13205 if (h != NULL)
07adf181 13206 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 13207 {
13208 case R_ARM_GNU_VTINHERIT:
13209 case R_ARM_GNU_VTENTRY:
07adf181
AM		 13210 return NULL;
13211 }
9ad5cbcf 13212
07adf181 13213 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 13214}
13215
780a67af
NC		 13216/* Update the got entry reference counts for the section being removed. */
13217
b34976b6 13218static bfd_boolean
ba93b8ac
DJ		 13219elf32_arm_gc_sweep_hook (bfd * abfd,
13220 struct bfd_link_info * info,
13221 asection * sec,
13222 const Elf_Internal_Rela * relocs)
252b5132 13223{
5e681ec4
PB		 13224 Elf_Internal_Shdr *symtab_hdr;
13225 struct elf_link_hash_entry **sym_hashes;
13226 bfd_signed_vma *local_got_refcounts;
13227 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 13228 struct elf32_arm_link_hash_table * globals;
13229
0e1862bb 13230 if (bfd_link_relocatable (info))
7dda2462
TG		 13231 return TRUE;
13232
eb043451 13233 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13234 if (globals == NULL)
13235 return FALSE;
5e681ec4
PB		 13236
13237 elf_section_data (sec)->local_dynrel = NULL;
13238
0ffa91dd 13239 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 13240 sym_hashes = elf_sym_hashes (abfd);
13241 local_got_refcounts = elf_local_got_refcounts (abfd);
13242
906e58ca 13243 check_use_blx (globals);
bd97cb95 13244
5e681ec4
PB		 13245 relend = relocs + sec->reloc_count;
13246 for (rel = relocs; rel < relend; rel++)
eb043451 13247 {
3eb128b2
AM		 13248 unsigned long r_symndx;
13249 struct elf_link_hash_entry *h = NULL;
f6e32f6d 13250 struct elf32_arm_link_hash_entry *eh;
eb043451 13251 int r_type;
34e77a92 13252 bfd_boolean call_reloc_p;
f6e32f6d
RS		 13253 bfd_boolean may_become_dynamic_p;
13254 bfd_boolean may_need_local_target_p;
34e77a92
RS		 13255 union gotplt_union *root_plt;
13256 struct arm_plt_info *arm_plt;
5e681ec4 13257
3eb128b2
AM		 13258 r_symndx = ELF32_R_SYM (rel->r_info);
13259 if (r_symndx >= symtab_hdr->sh_info)
13260 {
13261 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13262 while (h->root.type == bfd_link_hash_indirect
13263 || h->root.type == bfd_link_hash_warning)
13264 h = (struct elf_link_hash_entry *) h->root.u.i.link;
13265 }
f6e32f6d
RS		 13266 eh = (struct elf32_arm_link_hash_entry *) h;
13267
34e77a92 13268 call_reloc_p = FALSE;
f6e32f6d
RS		 13269 may_become_dynamic_p = FALSE;
13270 may_need_local_target_p = FALSE;
3eb128b2 13271
eb043451 13272 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13273 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 13274 switch (r_type)
13275 {
13276 case R_ARM_GOT32:
eb043451 13277 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13278 case R_ARM_TLS_GD32:
13279 case R_ARM_TLS_IE32:
3eb128b2 13280 if (h != NULL)
eb043451 13281 {
eb043451
PB		 13282 if (h->got.refcount > 0)
13283 h->got.refcount -= 1;
13284 }
13285 else if (local_got_refcounts != NULL)
13286 {
13287 if (local_got_refcounts[r_symndx] > 0)
13288 local_got_refcounts[r_symndx] -= 1;
13289 }
13290 break;
13291
ba93b8ac 13292 case R_ARM_TLS_LDM32:
4dfe6ac6 13293 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 13294 break;
13295
eb043451
PB		 13296 case R_ARM_PC24:
13297 case R_ARM_PLT32:
5b5bb741
PB		 13298 case R_ARM_CALL:
13299 case R_ARM_JUMP24:
eb043451 13300 case R_ARM_PREL31:
c19d1205 13301 case R_ARM_THM_CALL:
bd97cb95
DJ		 13302 case R_ARM_THM_JUMP24:
13303 case R_ARM_THM_JUMP19:
34e77a92 13304 call_reloc_p = TRUE;
f6e32f6d
RS		 13305 may_need_local_target_p = TRUE;
13306 break;
13307
13308 case R_ARM_ABS12:
13309 if (!globals->vxworks_p)
13310 {
13311 may_need_local_target_p = TRUE;
13312 break;
13313 }
13314 /* Fall through. */
13315 case R_ARM_ABS32:
13316 case R_ARM_ABS32_NOI:
13317 case R_ARM_REL32:
13318 case R_ARM_REL32_NOI:
b6895b4f
PB		 13319 case R_ARM_MOVW_ABS_NC:
13320 case R_ARM_MOVT_ABS:
13321 case R_ARM_MOVW_PREL_NC:
13322 case R_ARM_MOVT_PREL:
13323 case R_ARM_THM_MOVW_ABS_NC:
13324 case R_ARM_THM_MOVT_ABS:
13325 case R_ARM_THM_MOVW_PREL_NC:
13326 case R_ARM_THM_MOVT_PREL:
b7693d02 13327 /* Should the interworking branches be here also? */
0e1862bb 13328 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 13329 && (sec->flags & SEC_ALLOC) != 0)
13330 {
13331 if (h == NULL
469a3493 13332 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13333 {
13334 call_reloc_p = TRUE;
13335 may_need_local_target_p = TRUE;
13336 }
13337 else
13338 may_become_dynamic_p = TRUE;
13339 }
f6e32f6d
RS		 13340 else
13341 may_need_local_target_p = TRUE;
13342 break;
b7693d02 13343
f6e32f6d
RS		 13344 default:
13345 break;
13346 }
5e681ec4 13347
34e77a92
RS		 13348 if (may_need_local_target_p
13349 && elf32_arm_get_plt_info (abfd, eh, r_symndx, &root_plt, &arm_plt))
f6e32f6d 13350 {
27586251
HPN		 13351 /* If PLT refcount book-keeping is wrong and too low, we'll
13352 see a zero value (going to -1) for the root PLT reference
13353 count. */
13354 if (root_plt->refcount >= 0)
13355 {
13356 BFD_ASSERT (root_plt->refcount != 0);
13357 root_plt->refcount -= 1;
13358 }
13359 else
13360 /* A value of -1 means the symbol has become local, forced
13361 or seeing a hidden definition. Any other negative value
13362 is an error. */
13363 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 13364
13365 if (!call_reloc_p)
13366 arm_plt->noncall_refcount--;
5e681ec4 13367
f6e32f6d 13368 if (r_type == R_ARM_THM_CALL)
34e77a92 13369 arm_plt->maybe_thumb_refcount--;
bd97cb95 13370
f6e32f6d
RS		 13371 if (r_type == R_ARM_THM_JUMP24
13372 || r_type == R_ARM_THM_JUMP19)
34e77a92 13373 arm_plt->thumb_refcount--;
f6e32f6d 13374 }
5e681ec4 13375
34e77a92 13376 if (may_become_dynamic_p)
f6e32f6d
RS		 13377 {
13378 struct elf_dyn_relocs **pp;
13379 struct elf_dyn_relocs *p;
5e681ec4 13380
34e77a92 13381 if (h != NULL)
9c489990 13382 pp = &(eh->dyn_relocs);
34e77a92
RS		 13383 else
13384 {
13385 Elf_Internal_Sym *isym;
13386
13387 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
13388 abfd, r_symndx);
13389 if (isym == NULL)
13390 return FALSE;
13391 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13392 if (pp == NULL)
13393 return FALSE;
13394 }
9c489990 13395 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 13396 if (p->sec == sec)
13397 {
13398 /* Everything must go for SEC. */
13399 *pp = p->next;
13400 break;
13401 }
eb043451
PB		 13402 }
13403 }
5e681ec4 13404
b34976b6 13405 return TRUE;
252b5132
RH		 13406}
13407
780a67af
NC		 13408/* Look through the relocs for a section during the first phase. */
13409
b34976b6 13410static bfd_boolean
57e8b36a
NC		 13411elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
13412 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 13413{
b34976b6
AM		 13414 Elf_Internal_Shdr *symtab_hdr;
13415 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 13416 const Elf_Internal_Rela *rel;
13417 const Elf_Internal_Rela *rel_end;
13418 bfd *dynobj;
5e681ec4 13419 asection *sreloc;
5e681ec4 13420 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 13421 bfd_boolean call_reloc_p;
13422 bfd_boolean may_become_dynamic_p;
13423 bfd_boolean may_need_local_target_p;
ce98a316 13424 unsigned long nsyms;
9a5aca8c 13425
0e1862bb 13426 if (bfd_link_relocatable (info))
b34976b6 13427 return TRUE;
9a5aca8c 13428
0ffa91dd
NC		 13429 BFD_ASSERT (is_arm_elf (abfd));
13430
5e681ec4 13431 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13432 if (htab == NULL)
13433 return FALSE;
13434
5e681ec4 13435 sreloc = NULL;
9a5aca8c 13436
67687978
PB		 13437 /* Create dynamic sections for relocatable executables so that we can
13438 copy relocations. */
13439 if (htab->root.is_relocatable_executable
13440 && ! htab->root.dynamic_sections_created)
13441 {
13442 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
13443 return FALSE;
13444 }
13445
cbc704f3
RS		 13446 if (htab->root.dynobj == NULL)
13447 htab->root.dynobj = abfd;
34e77a92
RS		 13448 if (!create_ifunc_sections (info))
13449 return FALSE;
cbc704f3
RS		 13450
13451 dynobj = htab->root.dynobj;
13452
0ffa91dd 13453 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 13454 sym_hashes = elf_sym_hashes (abfd);
ce98a316 13455 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 13456
252b5132
RH		 13457 rel_end = relocs + sec->reloc_count;
13458 for (rel = relocs; rel < rel_end; rel++)
13459 {
34e77a92 13460 Elf_Internal_Sym *isym;
252b5132 13461 struct elf_link_hash_entry *h;
b7693d02 13462 struct elf32_arm_link_hash_entry *eh;
252b5132 13463 unsigned long r_symndx;
eb043451 13464 int r_type;
9a5aca8c 13465
252b5132 13466 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 13467 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13468 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 13469
ce98a316
NC		 13470 if (r_symndx >= nsyms
13471 /* PR 9934: It is possible to have relocations that do not
13472 refer to symbols, thus it is also possible to have an
13473 object file containing relocations but no symbol table. */
cf35638d 13474 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 13475 {
13476 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 13477 r_symndx);
ba93b8ac
DJ		 13478 return FALSE;
13479 }
13480
34e77a92
RS		 13481 h = NULL;
13482 isym = NULL;
13483 if (nsyms > 0)
973a3492 13484 {
34e77a92
RS		 13485 if (r_symndx < symtab_hdr->sh_info)
13486 {
13487 /* A local symbol. */
13488 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
13489 abfd, r_symndx);
13490 if (isym == NULL)
13491 return FALSE;
13492 }
13493 else
13494 {
13495 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13496 while (h->root.type == bfd_link_hash_indirect
13497 || h->root.type == bfd_link_hash_warning)
13498 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 13499
13500 /* PR15323, ref flags aren't set for references in the
13501 same object. */
13502 h->root.non_ir_ref = 1;
34e77a92 13503 }
973a3492 13504 }
9a5aca8c 13505
b7693d02
DJ		 13506 eh = (struct elf32_arm_link_hash_entry *) h;
13507
f6e32f6d
RS		 13508 call_reloc_p = FALSE;
13509 may_become_dynamic_p = FALSE;
13510 may_need_local_target_p = FALSE;
13511
0855e32b
NS		 13512 /* Could be done earlier, if h were already available. */
13513 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 13514 switch (r_type)
99059e56 13515 {
5e681ec4 13516 case R_ARM_GOT32:
eb043451 13517 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13518 case R_ARM_TLS_GD32:
13519 case R_ARM_TLS_IE32:
0855e32b
NS		 13520 case R_ARM_TLS_GOTDESC:
13521 case R_ARM_TLS_DESCSEQ:
13522 case R_ARM_THM_TLS_DESCSEQ:
13523 case R_ARM_TLS_CALL:
13524 case R_ARM_THM_TLS_CALL:
5e681ec4 13525 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 13526 {
13527 int tls_type, old_tls_type;
5e681ec4 13528
ba93b8ac
DJ		 13529 switch (r_type)
13530 {
13531 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 13532
ba93b8ac 13533 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 13534
0855e32b
NS		 13535 case R_ARM_TLS_GOTDESC:
13536 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
13537 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
13538 tls_type = GOT_TLS_GDESC; break;
b38cadfb 13539
ba93b8ac
DJ		 13540 default: tls_type = GOT_NORMAL; break;
13541 }
252b5132 13542
0e1862bb 13543 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 13544 info->flags |= DF_STATIC_TLS;
13545
ba93b8ac
DJ		 13546 if (h != NULL)
13547 {
13548 h->got.refcount++;
13549 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
13550 }
13551 else
13552 {
ba93b8ac 13553 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 13554 if (!elf32_arm_allocate_local_sym_info (abfd))
13555 return FALSE;
13556 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 13557 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
13558 }
13559
0855e32b 13560 /* If a variable is accessed with both tls methods, two
99059e56 13561 slots may be created. */
0855e32b
NS		 13562 if (GOT_TLS_GD_ANY_P (old_tls_type)
13563 && GOT_TLS_GD_ANY_P (tls_type))
13564 tls_type |= old_tls_type;
13565
13566 /* We will already have issued an error message if there
13567 is a TLS/non-TLS mismatch, based on the symbol
13568 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 13569 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
13570 && tls_type != GOT_NORMAL)
13571 tls_type |= old_tls_type;
13572
0855e32b 13573 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 13574 method, we're able to relax. Turn off the GDESC flag,
13575 without messing up with any other kind of tls types
6a631e86 13576 that may be involved. */
0855e32b
NS		 13577 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
13578 tls_type &= ~GOT_TLS_GDESC;
13579
ba93b8ac
DJ		 13580 if (old_tls_type != tls_type)
13581 {
13582 if (h != NULL)
13583 elf32_arm_hash_entry (h)->tls_type = tls_type;
13584 else
13585 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
13586 }
13587 }
8029a119 13588 /* Fall through. */
ba93b8ac
DJ		 13589
13590 case R_ARM_TLS_LDM32:
13591 if (r_type == R_ARM_TLS_LDM32)
13592 htab->tls_ldm_got.refcount++;
8029a119 13593 /* Fall through. */
252b5132 13594
c19d1205 13595 case R_ARM_GOTOFF32:
5e681ec4 13596 case R_ARM_GOTPC:
cbc704f3
RS		 13597 if (htab->root.sgot == NULL
13598 && !create_got_section (htab->root.dynobj, info))
13599 return FALSE;
252b5132
RH		 13600 break;
13601
252b5132 13602 case R_ARM_PC24:
7359ea65 13603 case R_ARM_PLT32:
5b5bb741
PB		 13604 case R_ARM_CALL:
13605 case R_ARM_JUMP24:
eb043451 13606 case R_ARM_PREL31:
c19d1205 13607 case R_ARM_THM_CALL:
bd97cb95
DJ		 13608 case R_ARM_THM_JUMP24:
13609 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 13610 call_reloc_p = TRUE;
13611 may_need_local_target_p = TRUE;
13612 break;
13613
13614 case R_ARM_ABS12:
13615 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
13616 ldr __GOTT_INDEX__ offsets. */
13617 if (!htab->vxworks_p)
13618 {
13619 may_need_local_target_p = TRUE;
13620 break;
13621 }
aebf9be7
NC		 13622 else goto jump_over;
13623
f6e32f6d 13624 /* Fall through. */
39623e12 13625
96c23d59
JM		 13626 case R_ARM_MOVW_ABS_NC:
13627 case R_ARM_MOVT_ABS:
13628 case R_ARM_THM_MOVW_ABS_NC:
13629 case R_ARM_THM_MOVT_ABS:
0e1862bb 13630 if (bfd_link_pic (info))
96c23d59
JM		 13631 {
13632 (*_bfd_error_handler)
13633 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
13634 abfd, elf32_arm_howto_table_1[r_type].name,
13635 (h) ? h->root.root.string : "a local symbol");
13636 bfd_set_error (bfd_error_bad_value);
13637 return FALSE;
13638 }
13639
13640 /* Fall through. */
39623e12
PB		 13641 case R_ARM_ABS32:
13642 case R_ARM_ABS32_NOI:
aebf9be7 13643 jump_over:
0e1862bb 13644 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 13645 {
13646 h->pointer_equality_needed = 1;
13647 }
13648 /* Fall through. */
39623e12
PB		 13649 case R_ARM_REL32:
13650 case R_ARM_REL32_NOI:
b6895b4f
PB		 13651 case R_ARM_MOVW_PREL_NC:
13652 case R_ARM_MOVT_PREL:
b6895b4f
PB		 13653 case R_ARM_THM_MOVW_PREL_NC:
13654 case R_ARM_THM_MOVT_PREL:
39623e12 13655
b7693d02 13656 /* Should the interworking branches be listed here? */
0e1862bb 13657 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 13658 && (sec->flags & SEC_ALLOC) != 0)
13659 {
13660 if (h == NULL
469a3493 13661 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13662 {
13663 /* In shared libraries and relocatable executables,
13664 we treat local relative references as calls;
13665 see the related SYMBOL_CALLS_LOCAL code in
13666 allocate_dynrelocs. */
13667 call_reloc_p = TRUE;
13668 may_need_local_target_p = TRUE;
13669 }
13670 else
13671 /* We are creating a shared library or relocatable
13672 executable, and this is a reloc against a global symbol,
13673 or a non-PC-relative reloc against a local symbol.
13674 We may need to copy the reloc into the output. */
13675 may_become_dynamic_p = TRUE;
13676 }
f6e32f6d
RS		 13677 else
13678 may_need_local_target_p = TRUE;
252b5132
RH		 13679 break;
13680
99059e56
RM		 13681 /* This relocation describes the C++ object vtable hierarchy.
13682 Reconstruct it for later use during GC. */
13683 case R_ARM_GNU_VTINHERIT:
13684 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
13685 return FALSE;
13686 break;
13687
13688 /* This relocation describes which C++ vtable entries are actually
13689 used. Record for later use during GC. */
13690 case R_ARM_GNU_VTENTRY:
13691 BFD_ASSERT (h != NULL);
13692 if (h != NULL
13693 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
13694 return FALSE;
13695 break;
13696 }
f6e32f6d
RS		 13697
13698 if (h != NULL)
13699 {
13700 if (call_reloc_p)
13701 /* We may need a .plt entry if the function this reloc
13702 refers to is in a different object, regardless of the
13703 symbol's type. We can't tell for sure yet, because
13704 something later might force the symbol local. */
13705 h->needs_plt = 1;
13706 else if (may_need_local_target_p)
13707 /* If this reloc is in a read-only section, we might
13708 need a copy reloc. We can't check reliably at this
13709 stage whether the section is read-only, as input
13710 sections have not yet been mapped to output sections.
13711 Tentatively set the flag for now, and correct in
13712 adjust_dynamic_symbol. */
13713 h->non_got_ref = 1;
13714 }
13715
34e77a92
RS		 13716 if (may_need_local_target_p
13717 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 13718 {
34e77a92
RS		 13719 union gotplt_union *root_plt;
13720 struct arm_plt_info *arm_plt;
13721 struct arm_local_iplt_info *local_iplt;
13722
13723 if (h != NULL)
13724 {
13725 root_plt = &h->plt;
13726 arm_plt = &eh->plt;
13727 }
13728 else
13729 {
13730 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
13731 if (local_iplt == NULL)
13732 return FALSE;
13733 root_plt = &local_iplt->root;
13734 arm_plt = &local_iplt->arm;
13735 }
13736
f6e32f6d
RS		 13737 /* If the symbol is a function that doesn't bind locally,
13738 this relocation will need a PLT entry. */
a8c887dd
NC		 13739 if (root_plt->refcount != -1)
13740 root_plt->refcount += 1;
34e77a92
RS		 13741
13742 if (!call_reloc_p)
13743 arm_plt->noncall_refcount++;
f6e32f6d
RS		 13744
13745 /* It's too early to use htab->use_blx here, so we have to
13746 record possible blx references separately from
13747 relocs that definitely need a thumb stub. */
13748
13749 if (r_type == R_ARM_THM_CALL)
34e77a92 13750 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 13751
13752 if (r_type == R_ARM_THM_JUMP24
13753 || r_type == R_ARM_THM_JUMP19)
34e77a92 13754 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 13755 }
13756
13757 if (may_become_dynamic_p)
13758 {
13759 struct elf_dyn_relocs *p, **head;
13760
13761 /* Create a reloc section in dynobj. */
13762 if (sreloc == NULL)
13763 {
13764 sreloc = _bfd_elf_make_dynamic_reloc_section
13765 (sec, dynobj, 2, abfd, ! htab->use_rel);
13766
13767 if (sreloc == NULL)
13768 return FALSE;
13769
13770 /* BPABI objects never have dynamic relocations mapped. */
13771 if (htab->symbian_p)
13772 {
13773 flagword flags;
13774
13775 flags = bfd_get_section_flags (dynobj, sreloc);
13776 flags &= ~(SEC_LOAD | SEC_ALLOC);
13777 bfd_set_section_flags (dynobj, sreloc, flags);
13778 }
13779 }
13780
13781 /* If this is a global symbol, count the number of
13782 relocations we need for this symbol. */
13783 if (h != NULL)
13784 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
13785 else
13786 {
34e77a92
RS		 13787 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13788 if (head == NULL)
f6e32f6d 13789 return FALSE;
f6e32f6d
RS		 13790 }
13791
13792 p = *head;
13793 if (p == NULL || p->sec != sec)
13794 {
13795 bfd_size_type amt = sizeof *p;
13796
13797 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
13798 if (p == NULL)
13799 return FALSE;
13800 p->next = *head;
13801 *head = p;
13802 p->sec = sec;
13803 p->count = 0;
13804 p->pc_count = 0;
13805 }
13806
469a3493 13807 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 13808 p->pc_count += 1;
13809 p->count += 1;
13810 }
252b5132 13811 }
f21f3fe0 13812
b34976b6 13813 return TRUE;
252b5132
RH		 13814}
13815
6a5bb875
PB		 13816/* Unwinding tables are not referenced directly. This pass marks them as
13817 required if the corresponding code section is marked. */
13818
13819static bfd_boolean
906e58ca
NC		 13820elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
13821 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 13822{
13823 bfd *sub;
13824 Elf_Internal_Shdr **elf_shdrp;
13825 bfd_boolean again;
13826
7f6ab9f8
AM		 13827 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
13828
6a5bb875
PB		 13829 /* Marking EH data may cause additional code sections to be marked,
13830 requiring multiple passes. */
13831 again = TRUE;
13832 while (again)
13833 {
13834 again = FALSE;
c72f2fb2 13835 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 13836 {
13837 asection *o;
13838
0ffa91dd 13839 if (! is_arm_elf (sub))
6a5bb875
PB		 13840 continue;
13841
13842 elf_shdrp = elf_elfsections (sub);
13843 for (o = sub->sections; o != NULL; o = o->next)
13844 {
13845 Elf_Internal_Shdr *hdr;
0ffa91dd 13846
6a5bb875 13847 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 13848 if (hdr->sh_type == SHT_ARM_EXIDX
13849 && hdr->sh_link
13850 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 13851 && !o->gc_mark
13852 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
13853 {
13854 again = TRUE;
13855 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
13856 return FALSE;
13857 }
13858 }
13859 }
13860 }
13861
13862 return TRUE;
13863}
13864
3c9458e9
NC		 13865/* Treat mapping symbols as special target symbols. */
13866
13867static bfd_boolean
13868elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
13869{
b0796911
PB		 13870 return bfd_is_arm_special_symbol_name (sym->name,
13871 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 13872}
13873
0367ecfb
NC		 13874/* This is a copy of elf_find_function() from elf.c except that
13875 ARM mapping symbols are ignored when looking for function names
13876 and STT_ARM_TFUNC is considered to a function type. */
252b5132 13877
0367ecfb
NC		 13878static bfd_boolean
13879arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 13880 asymbol ** symbols,
fb167eb2 13881 asection * section,
0367ecfb
NC		 13882 bfd_vma offset,
13883 const char ** filename_ptr,
13884 const char ** functionname_ptr)
13885{
13886 const char * filename = NULL;
13887 asymbol * func = NULL;
13888 bfd_vma low_func = 0;
13889 asymbol ** p;
252b5132
RH		 13890
13891 for (p = symbols; *p != NULL; p++)
13892 {
13893 elf_symbol_type *q;
13894
13895 q = (elf_symbol_type *) *p;
13896
252b5132
RH		 13897 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
13898 {
13899 default:
13900 break;
13901 case STT_FILE:
13902 filename = bfd_asymbol_name (&q->symbol);
13903 break;
252b5132
RH		 13904 case STT_FUNC:
13905 case STT_ARM_TFUNC:
9d2da7ca 13906 case STT_NOTYPE:
b0796911 13907 /* Skip mapping symbols. */
0367ecfb 13908 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 13909 && bfd_is_arm_special_symbol_name (q->symbol.name,
13910 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 13911 continue;
13912 /* Fall through. */
6b40fcba 13913 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 13914 && q->symbol.value >= low_func
13915 && q->symbol.value <= offset)
13916 {
13917 func = (asymbol *) q;
13918 low_func = q->symbol.value;
13919 }
13920 break;
13921 }
13922 }
13923
13924 if (func == NULL)
b34976b6 13925 return FALSE;
252b5132 13926
0367ecfb
NC		 13927 if (filename_ptr)
13928 *filename_ptr = filename;
13929 if (functionname_ptr)
13930 *functionname_ptr = bfd_asymbol_name (func);
13931
13932 return TRUE;
906e58ca 13933}
0367ecfb
NC		 13934
13935
13936/* Find the nearest line to a particular section and offset, for error
13937 reporting. This code is a duplicate of the code in elf.c, except
13938 that it uses arm_elf_find_function. */
13939
13940static bfd_boolean
13941elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 13942 asymbol ** symbols,
fb167eb2 13943 asection * section,
0367ecfb
NC		 13944 bfd_vma offset,
13945 const char ** filename_ptr,
13946 const char ** functionname_ptr,
fb167eb2
AM		 13947 unsigned int * line_ptr,
13948 unsigned int * discriminator_ptr)
0367ecfb
NC		 13949{
13950 bfd_boolean found = FALSE;
13951
fb167eb2 13952 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 13953 filename_ptr, functionname_ptr,
fb167eb2
AM		 13954 line_ptr, discriminator_ptr,
13955 dwarf_debug_sections, 0,
0367ecfb
NC		 13956 & elf_tdata (abfd)->dwarf2_find_line_info))
13957 {
13958 if (!*functionname_ptr)
fb167eb2 13959 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 13960 *filename_ptr ? NULL : filename_ptr,
13961 functionname_ptr);
f21f3fe0 13962
0367ecfb
NC		 13963 return TRUE;
13964 }
13965
fb167eb2
AM		 13966 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
13967 uses DWARF1. */
13968
0367ecfb
NC		 13969 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
13970 & found, filename_ptr,
13971 functionname_ptr, line_ptr,
13972 & elf_tdata (abfd)->line_info))
13973 return FALSE;
13974
13975 if (found && (*functionname_ptr || *line_ptr))
13976 return TRUE;
13977
13978 if (symbols == NULL)
13979 return FALSE;
13980
fb167eb2 13981 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 13982 filename_ptr, functionname_ptr))
13983 return FALSE;
13984
13985 *line_ptr = 0;
b34976b6 13986 return TRUE;
252b5132
RH		 13987}
13988
4ab527b0
FF		 13989static bfd_boolean
13990elf32_arm_find_inliner_info (bfd * abfd,
13991 const char ** filename_ptr,
13992 const char ** functionname_ptr,
13993 unsigned int * line_ptr)
13994{
13995 bfd_boolean found;
13996 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
13997 functionname_ptr, line_ptr,
13998 & elf_tdata (abfd)->dwarf2_find_line_info);
13999 return found;
14000}
14001
252b5132
RH		 14002/* Adjust a symbol defined by a dynamic object and referenced by a
14003 regular object. The current definition is in some section of the
14004 dynamic object, but we're not including those sections. We have to
14005 change the definition to something the rest of the link can
14006 understand. */
14007
b34976b6 14008static bfd_boolean
57e8b36a
NC		 14009elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
14010 struct elf_link_hash_entry * h)
252b5132
RH		 14011{
14012 bfd * dynobj;
14013 asection * s;
b7693d02 14014 struct elf32_arm_link_hash_entry * eh;
67687978 14015 struct elf32_arm_link_hash_table *globals;
252b5132 14016
67687978 14017 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14018 if (globals == NULL)
14019 return FALSE;
14020
252b5132
RH		 14021 dynobj = elf_hash_table (info)->dynobj;
14022
14023 /* Make sure we know what is going on here. */
14024 BFD_ASSERT (dynobj != NULL
f5385ebf 14025 && (h->needs_plt
34e77a92 14026 || h->type == STT_GNU_IFUNC
f6e332e6 14027 || h->u.weakdef != NULL
f5385ebf
AM		 14028 || (h->def_dynamic
14029 && h->ref_regular
14030 && !h->def_regular)));
252b5132 14031
b7693d02
DJ		 14032 eh = (struct elf32_arm_link_hash_entry *) h;
14033
252b5132
RH		 14034 /* If this is a function, put it in the procedure linkage table. We
14035 will fill in the contents of the procedure linkage table later,
14036 when we know the address of the .got section. */
34e77a92 14037 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 14038 {
34e77a92
RS		 14039 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
14040 symbol binds locally. */
5e681ec4 14041 if (h->plt.refcount <= 0
34e77a92
RS		 14042 || (h->type != STT_GNU_IFUNC
14043 && (SYMBOL_CALLS_LOCAL (info, h)
14044 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
14045 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 14046 {
14047 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 14048 file, but the symbol was never referred to by a dynamic
14049 object, or if all references were garbage collected. In
14050 such a case, we don't actually need to build a procedure
14051 linkage table, and we can just do a PC24 reloc instead. */
14052 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14053 eh->plt.thumb_refcount = 0;
14054 eh->plt.maybe_thumb_refcount = 0;
14055 eh->plt.noncall_refcount = 0;
f5385ebf 14056 h->needs_plt = 0;
252b5132
RH		 14057 }
14058
b34976b6 14059 return TRUE;
252b5132 14060 }
5e681ec4 14061 else
b7693d02
DJ		 14062 {
14063 /* It's possible that we incorrectly decided a .plt reloc was
14064 needed for an R_ARM_PC24 or similar reloc to a non-function sym
14065 in check_relocs. We can't decide accurately between function
14066 and non-function syms in check-relocs; Objects loaded later in
14067 the link may change h->type. So fix it now. */
14068 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14069 eh->plt.thumb_refcount = 0;
14070 eh->plt.maybe_thumb_refcount = 0;
14071 eh->plt.noncall_refcount = 0;
b7693d02 14072 }
252b5132
RH		 14073
14074 /* If this is a weak symbol, and there is a real definition, the
14075 processor independent code will have arranged for us to see the
14076 real definition first, and we can just use the same value. */
f6e332e6 14077 if (h->u.weakdef != NULL)
252b5132 14078 {
f6e332e6
AM		 14079 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
14080 || h->u.weakdef->root.type == bfd_link_hash_defweak);
14081 h->root.u.def.section = h->u.weakdef->root.u.def.section;
14082 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 14083 return TRUE;
252b5132
RH		 14084 }
14085
ba93b8ac
DJ		 14086 /* If there are no non-GOT references, we do not need a copy
14087 relocation. */
14088 if (!h->non_got_ref)
14089 return TRUE;
14090
252b5132
RH		 14091 /* This is a reference to a symbol defined by a dynamic object which
14092 is not a function. */
14093
14094 /* If we are creating a shared library, we must presume that the
14095 only references to the symbol are via the global offset table.
14096 For such cases we need not do anything here; the relocations will
67687978
PB		 14097 be handled correctly by relocate_section. Relocatable executables
14098 can reference data in shared objects directly, so we don't need to
14099 do anything here. */
0e1862bb 14100 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 14101 return TRUE;
252b5132
RH		 14102
14103 /* We must allocate the symbol in our .dynbss section, which will
14104 become part of the .bss section of the executable. There will be
14105 an entry for this symbol in the .dynsym section. The dynamic
14106 object will contain position independent code, so all references
14107 from the dynamic object to this symbol will go through the global
14108 offset table. The dynamic linker will use the .dynsym entry to
14109 determine the address it must put in the global offset table, so
14110 both the dynamic object and the regular object will refer to the
14111 same memory location for the variable. */
3d4d4302 14112 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 14113 BFD_ASSERT (s != NULL);
14114
14115 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
14116 copy the initial value out of the dynamic object and into the
14117 runtime process image. We need to remember the offset into the
00a97672 14118 .rel(a).bss section we are going to use. */
1d7e9d18 14119 if ((h->root.u.def.section->flags & SEC_ALLOC) != 0 && h->size != 0)
252b5132
RH		 14120 {
14121 asection *srel;
14122
3d4d4302 14123 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 14124 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 14125 h->needs_copy = 1;
252b5132
RH		 14126 }
14127
6cabe1ea 14128 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 14129}
14130
5e681ec4
PB		 14131/* Allocate space in .plt, .got and associated reloc sections for
14132 dynamic relocs. */
14133
14134static bfd_boolean
47beaa6a 14135allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 14136{
14137 struct bfd_link_info *info;
14138 struct elf32_arm_link_hash_table *htab;
14139 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 14140 struct elf_dyn_relocs *p;
5e681ec4
PB		 14141
14142 if (h->root.type == bfd_link_hash_indirect)
14143 return TRUE;
14144
e6a6bb22
AM		 14145 eh = (struct elf32_arm_link_hash_entry *) h;
14146
5e681ec4
PB		 14147 info = (struct bfd_link_info *) inf;
14148 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14149 if (htab == NULL)
14150 return FALSE;
5e681ec4 14151
34e77a92 14152 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 14153 && h->plt.refcount > 0)
14154 {
14155 /* Make sure this symbol is output as a dynamic symbol.
14156 Undefined weak syms won't yet be marked as dynamic. */
14157 if (h->dynindx == -1
f5385ebf 14158 && !h->forced_local)
5e681ec4 14159 {
c152c796 14160 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14161 return FALSE;
14162 }
14163
34e77a92
RS		 14164 /* If the call in the PLT entry binds locally, the associated
14165 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14166 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14167 than the .plt section. */
14168 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
14169 {
14170 eh->is_iplt = 1;
14171 if (eh->plt.noncall_refcount == 0
14172 && SYMBOL_REFERENCES_LOCAL (info, h))
14173 /* All non-call references can be resolved directly.
14174 This means that they can (and in some cases, must)
14175 resolve directly to the run-time target, rather than
14176 to the PLT. That in turns means that any .got entry
14177 would be equal to the .igot.plt entry, so there's
14178 no point having both. */
14179 h->got.refcount = 0;
14180 }
14181
0e1862bb 14182 if (bfd_link_pic (info)
34e77a92 14183 || eh->is_iplt
7359ea65 14184 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 14185 {
34e77a92 14186 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 14187
5e681ec4
PB		 14188 /* If this symbol is not defined in a regular file, and we are
14189 not generating a shared library, then set the symbol to this
14190 location in the .plt. This is required to make function
14191 pointers compare as equal between the normal executable and
14192 the shared library. */
0e1862bb 14193 if (! bfd_link_pic (info)
f5385ebf 14194 && !h->def_regular)
5e681ec4 14195 {
34e77a92 14196 h->root.u.def.section = htab->root.splt;
5e681ec4 14197 h->root.u.def.value = h->plt.offset;
5e681ec4 14198
67d74e43
DJ		 14199 /* Make sure the function is not marked as Thumb, in case
14200 it is the target of an ABS32 relocation, which will
14201 point to the PLT entry. */
35fc36a8 14202 h->target_internal = ST_BRANCH_TO_ARM;
67d74e43 14203 }
022f8312 14204
00a97672
RS		 14205 /* VxWorks executables have a second set of relocations for
14206 each PLT entry. They go in a separate relocation section,
14207 which is processed by the kernel loader. */
0e1862bb 14208 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 14209 {
14210 /* There is a relocation for the initial PLT entry:
14211 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14212 if (h->plt.offset == htab->plt_header_size)
47beaa6a 14213 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 14214
14215 /* There are two extra relocations for each subsequent
14216 PLT entry: an R_ARM_32 relocation for the GOT entry,
14217 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 14218 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 14219 }
5e681ec4
PB		 14220 }
14221 else
14222 {
14223 h->plt.offset = (bfd_vma) -1;
f5385ebf 14224 h->needs_plt = 0;
5e681ec4
PB		 14225 }
14226 }
14227 else
14228 {
14229 h->plt.offset = (bfd_vma) -1;
f5385ebf 14230 h->needs_plt = 0;
5e681ec4
PB		 14231 }
14232
0855e32b
NS		 14233 eh = (struct elf32_arm_link_hash_entry *) h;
14234 eh->tlsdesc_got = (bfd_vma) -1;
14235
5e681ec4
PB		 14236 if (h->got.refcount > 0)
14237 {
14238 asection *s;
14239 bfd_boolean dyn;
ba93b8ac
DJ		 14240 int tls_type = elf32_arm_hash_entry (h)->tls_type;
14241 int indx;
5e681ec4
PB		 14242
14243 /* Make sure this symbol is output as a dynamic symbol.
14244 Undefined weak syms won't yet be marked as dynamic. */
14245 if (h->dynindx == -1
f5385ebf 14246 && !h->forced_local)
5e681ec4 14247 {
c152c796 14248 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14249 return FALSE;
14250 }
14251
e5a52504
MM		 14252 if (!htab->symbian_p)
14253 {
362d30a1 14254 s = htab->root.sgot;
e5a52504 14255 h->got.offset = s->size;
ba93b8ac
DJ		 14256
14257 if (tls_type == GOT_UNKNOWN)
14258 abort ();
14259
14260 if (tls_type == GOT_NORMAL)
14261 /* Non-TLS symbols need one GOT slot. */
14262 s->size += 4;
14263 else
14264 {
99059e56
RM		 14265 if (tls_type & GOT_TLS_GDESC)
14266 {
0855e32b 14267 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 14268 eh->tlsdesc_got
0855e32b
NS		 14269 = (htab->root.sgotplt->size
14270 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 14271 htab->root.sgotplt->size += 8;
14272 h->got.offset = (bfd_vma) -2;
34e77a92 14273 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14274 reloc in the middle of .got.plt. */
99059e56
RM		 14275 htab->num_tls_desc++;
14276 }
0855e32b 14277
ba93b8ac 14278 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 14279 {
14280 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14281 the symbol is both GD and GDESC, got.offset may
14282 have been overwritten. */
14283 h->got.offset = s->size;
14284 s->size += 8;
14285 }
14286
ba93b8ac
DJ		 14287 if (tls_type & GOT_TLS_IE)
14288 /* R_ARM_TLS_IE32 needs one GOT slot. */
14289 s->size += 4;
14290 }
14291
e5a52504 14292 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 14293
14294 indx = 0;
0e1862bb
L		 14295 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
14296 bfd_link_pic (info),
14297 h)
14298 && (!bfd_link_pic (info)
ba93b8ac
DJ		 14299 || !SYMBOL_REFERENCES_LOCAL (info, h)))
14300 indx = h->dynindx;
14301
14302 if (tls_type != GOT_NORMAL
0e1862bb 14303 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 14304 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14305 || h->root.type != bfd_link_hash_undefweak))
14306 {
14307 if (tls_type & GOT_TLS_IE)
47beaa6a 14308 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14309
14310 if (tls_type & GOT_TLS_GD)
47beaa6a 14311 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14312
b38cadfb 14313 if (tls_type & GOT_TLS_GDESC)
0855e32b 14314 {
47beaa6a 14315 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 14316 /* GDESC needs a trampoline to jump to. */
14317 htab->tls_trampoline = -1;
14318 }
14319
14320 /* Only GD needs it. GDESC just emits one relocation per
14321 2 entries. */
b38cadfb 14322 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 14323 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14324 }
6f820c85 14325 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 14326 {
14327 if (htab->root.dynamic_sections_created)
14328 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
14329 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
14330 }
34e77a92
RS		 14331 else if (h->type == STT_GNU_IFUNC
14332 && eh->plt.noncall_refcount == 0)
14333 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
14334 they all resolve dynamically instead. Reserve room for the
14335 GOT entry's R_ARM_IRELATIVE relocation. */
14336 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 14337 else if (bfd_link_pic (info)
14338 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14339 || h->root.type != bfd_link_hash_undefweak))
b436d854 14340 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 14341 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 14342 }
5e681ec4
PB		 14343 }
14344 else
14345 h->got.offset = (bfd_vma) -1;
14346
a4fd1a8e
PB		 14347 /* Allocate stubs for exported Thumb functions on v4t. */
14348 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 14349 && h->def_regular
35fc36a8 14350 && h->target_internal == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 14351 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
14352 {
14353 struct elf_link_hash_entry * th;
14354 struct bfd_link_hash_entry * bh;
14355 struct elf_link_hash_entry * myh;
14356 char name[1024];
14357 asection *s;
14358 bh = NULL;
14359 /* Create a new symbol to regist the real location of the function. */
14360 s = h->root.u.def.section;
906e58ca 14361 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 14362 _bfd_generic_link_add_one_symbol (info, s->owner,
14363 name, BSF_GLOBAL, s,
14364 h->root.u.def.value,
14365 NULL, TRUE, FALSE, &bh);
14366
14367 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 14368 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 14369 myh->forced_local = 1;
35fc36a8 14370 myh->target_internal = ST_BRANCH_TO_THUMB;
a4fd1a8e
PB		 14371 eh->export_glue = myh;
14372 th = record_arm_to_thumb_glue (info, h);
14373 /* Point the symbol at the stub. */
14374 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
35fc36a8 14375 h->target_internal = ST_BRANCH_TO_ARM;
a4fd1a8e
PB		 14376 h->root.u.def.section = th->root.u.def.section;
14377 h->root.u.def.value = th->root.u.def.value & ~1;
14378 }
14379
0bdcacaf 14380 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 14381 return TRUE;
14382
14383 /* In the shared -Bsymbolic case, discard space allocated for
14384 dynamic pc-relative relocs against symbols which turn out to be
14385 defined in regular objects. For the normal shared case, discard
14386 space for pc-relative relocs that have become local due to symbol
14387 visibility changes. */
14388
0e1862bb 14389 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 14390 {
469a3493
RM		 14391 /* Relocs that use pc_count are PC-relative forms, which will appear
14392 on something like ".long foo - ." or "movw REG, foo - .". We want
14393 calls to protected symbols to resolve directly to the function
14394 rather than going via the plt. If people want function pointer
14395 comparisons to work as expected then they should avoid writing
14396 assembly like ".long foo - .". */
ba93b8ac
DJ		 14397 if (SYMBOL_CALLS_LOCAL (info, h))
14398 {
0bdcacaf 14399 struct elf_dyn_relocs **pp;
ba93b8ac 14400
0bdcacaf 14401 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 14402 {
14403 p->count -= p->pc_count;
14404 p->pc_count = 0;
14405 if (p->count == 0)
14406 *pp = p->next;
14407 else
14408 pp = &p->next;
14409 }
14410 }
14411
4dfe6ac6 14412 if (htab->vxworks_p)
3348747a 14413 {
0bdcacaf 14414 struct elf_dyn_relocs **pp;
3348747a 14415
0bdcacaf 14416 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 14417 {
0bdcacaf 14418 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 14419 *pp = p->next;
14420 else
14421 pp = &p->next;
14422 }
14423 }
14424
ba93b8ac 14425 /* Also discard relocs on undefined weak syms with non-default
99059e56 14426 visibility. */
0bdcacaf 14427 if (eh->dyn_relocs != NULL
5e681ec4 14428 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 14429 {
14430 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 14431 eh->dyn_relocs = NULL;
22d606e9
AM		 14432
14433 /* Make sure undefined weak symbols are output as a dynamic
14434 symbol in PIEs. */
14435 else if (h->dynindx == -1
14436 && !h->forced_local)
14437 {
14438 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14439 return FALSE;
14440 }
14441 }
14442
67687978
PB		 14443 else if (htab->root.is_relocatable_executable && h->dynindx == -1
14444 && h->root.type == bfd_link_hash_new)
14445 {
14446 /* Output absolute symbols so that we can create relocations
14447 against them. For normal symbols we output a relocation
14448 against the section that contains them. */
14449 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14450 return FALSE;
14451 }
14452
5e681ec4
PB		 14453 }
14454 else
14455 {
14456 /* For the non-shared case, discard space for relocs against
14457 symbols which turn out to need copy relocs or are not
14458 dynamic. */
14459
f5385ebf
AM		 14460 if (!h->non_got_ref
14461 && ((h->def_dynamic
14462 && !h->def_regular)
5e681ec4
PB		 14463 || (htab->root.dynamic_sections_created
14464 && (h->root.type == bfd_link_hash_undefweak
14465 || h->root.type == bfd_link_hash_undefined))))
14466 {
14467 /* Make sure this symbol is output as a dynamic symbol.
14468 Undefined weak syms won't yet be marked as dynamic. */
14469 if (h->dynindx == -1
f5385ebf 14470 && !h->forced_local)
5e681ec4 14471 {
c152c796 14472 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14473 return FALSE;
14474 }
14475
14476 /* If that succeeded, we know we'll be keeping all the
14477 relocs. */
14478 if (h->dynindx != -1)
14479 goto keep;
14480 }
14481
0bdcacaf 14482 eh->dyn_relocs = NULL;
5e681ec4
PB		 14483
14484 keep: ;
14485 }
14486
14487 /* Finally, allocate space. */
0bdcacaf 14488 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 14489 {
0bdcacaf 14490 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 14491 if (h->type == STT_GNU_IFUNC
14492 && eh->plt.noncall_refcount == 0
14493 && SYMBOL_REFERENCES_LOCAL (info, h))
14494 elf32_arm_allocate_irelocs (info, sreloc, p->count);
14495 else
14496 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 14497 }
14498
14499 return TRUE;
14500}
14501
08d1f311
DJ		 14502/* Find any dynamic relocs that apply to read-only sections. */
14503
14504static bfd_boolean
8029a119 14505elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 14506{
8029a119 14507 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 14508 struct elf_dyn_relocs * p;
08d1f311 14509
08d1f311 14510 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 14511 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 14512 {
0bdcacaf 14513 asection *s = p->sec;
08d1f311
DJ		 14514
14515 if (s != NULL && (s->flags & SEC_READONLY) != 0)
14516 {
14517 struct bfd_link_info *info = (struct bfd_link_info *) inf;
14518
14519 info->flags |= DF_TEXTREL;
14520
14521 /* Not an error, just cut short the traversal. */
14522 return FALSE;
14523 }
14524 }
14525 return TRUE;
14526}
14527
d504ffc8
DJ		 14528void
14529bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
14530 int byteswap_code)
14531{
14532 struct elf32_arm_link_hash_table *globals;
14533
14534 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14535 if (globals == NULL)
14536 return;
14537
d504ffc8
DJ		 14538 globals->byteswap_code = byteswap_code;
14539}
14540
252b5132
RH		 14541/* Set the sizes of the dynamic sections. */
14542
b34976b6 14543static bfd_boolean
57e8b36a
NC		 14544elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
14545 struct bfd_link_info * info)
252b5132
RH		 14546{
14547 bfd * dynobj;
14548 asection * s;
b34976b6
AM		 14549 bfd_boolean plt;
14550 bfd_boolean relocs;
5e681ec4
PB		 14551 bfd *ibfd;
14552 struct elf32_arm_link_hash_table *htab;
252b5132 14553
5e681ec4 14554 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14555 if (htab == NULL)
14556 return FALSE;
14557
252b5132
RH		 14558 dynobj = elf_hash_table (info)->dynobj;
14559 BFD_ASSERT (dynobj != NULL);
39b41c9c 14560 check_use_blx (htab);
252b5132
RH		 14561
14562 if (elf_hash_table (info)->dynamic_sections_created)
14563 {
14564 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 14565 if (bfd_link_executable (info) && !info->nointerp)
252b5132 14566 {
3d4d4302 14567 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 14568 BFD_ASSERT (s != NULL);
eea6121a 14569 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 14570 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
14571 }
14572 }
5e681ec4
PB		 14573
14574 /* Set up .got offsets for local syms, and space for local dynamic
14575 relocs. */
c72f2fb2 14576 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 14577 {
5e681ec4
PB		 14578 bfd_signed_vma *local_got;
14579 bfd_signed_vma *end_local_got;
34e77a92 14580 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 14581 char *local_tls_type;
0855e32b 14582 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 14583 bfd_size_type locsymcount;
14584 Elf_Internal_Shdr *symtab_hdr;
14585 asection *srel;
4dfe6ac6 14586 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 14587 unsigned int symndx;
5e681ec4 14588
0ffa91dd 14589 if (! is_arm_elf (ibfd))
5e681ec4
PB		 14590 continue;
14591
14592 for (s = ibfd->sections; s != NULL; s = s->next)
14593 {
0bdcacaf 14594 struct elf_dyn_relocs *p;
5e681ec4 14595
0bdcacaf 14596 for (p = (struct elf_dyn_relocs *)
99059e56 14597 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 14598 {
0bdcacaf
RS		 14599 if (!bfd_is_abs_section (p->sec)
14600 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 14601 {
14602 /* Input section has been discarded, either because
14603 it is a copy of a linkonce section or due to
14604 linker script /DISCARD/, so we'll be discarding
14605 the relocs too. */
14606 }
3348747a 14607 else if (is_vxworks
0bdcacaf 14608 && strcmp (p->sec->output_section->name,
3348747a
NS		 14609 ".tls_vars") == 0)
14610 {
14611 /* Relocations in vxworks .tls_vars sections are
14612 handled specially by the loader. */
14613 }
5e681ec4
PB		 14614 else if (p->count != 0)
14615 {
0bdcacaf 14616 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 14617 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 14618 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 14619 info->flags |= DF_TEXTREL;
14620 }
14621 }
14622 }
14623
14624 local_got = elf_local_got_refcounts (ibfd);
14625 if (!local_got)
14626 continue;
14627
0ffa91dd 14628 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 14629 locsymcount = symtab_hdr->sh_info;
14630 end_local_got = local_got + locsymcount;
34e77a92 14631 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 14632 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 14633 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 14634 symndx = 0;
362d30a1
RS		 14635 s = htab->root.sgot;
14636 srel = htab->root.srelgot;
0855e32b 14637 for (; local_got < end_local_got;
34e77a92
RS		 14638 ++local_got, ++local_iplt_ptr, ++local_tls_type,
14639 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 14640 {
0855e32b 14641 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 14642 local_iplt = *local_iplt_ptr;
14643 if (local_iplt != NULL)
14644 {
14645 struct elf_dyn_relocs *p;
14646
14647 if (local_iplt->root.refcount > 0)
14648 {
14649 elf32_arm_allocate_plt_entry (info, TRUE,
14650 &local_iplt->root,
14651 &local_iplt->arm);
14652 if (local_iplt->arm.noncall_refcount == 0)
14653 /* All references to the PLT are calls, so all
14654 non-call references can resolve directly to the
14655 run-time target. This means that the .got entry
14656 would be the same as the .igot.plt entry, so there's
14657 no point creating both. */
14658 *local_got = 0;
14659 }
14660 else
14661 {
14662 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
14663 local_iplt->root.offset = (bfd_vma) -1;
14664 }
14665
14666 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
14667 {
14668 asection *psrel;
14669
14670 psrel = elf_section_data (p->sec)->sreloc;
14671 if (local_iplt->arm.noncall_refcount == 0)
14672 elf32_arm_allocate_irelocs (info, psrel, p->count);
14673 else
14674 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
14675 }
14676 }
5e681ec4
PB		 14677 if (*local_got > 0)
14678 {
34e77a92
RS		 14679 Elf_Internal_Sym *isym;
14680
eea6121a 14681 *local_got = s->size;
ba93b8ac
DJ		 14682 if (*local_tls_type & GOT_TLS_GD)
14683 /* TLS_GD relocs need an 8-byte structure in the GOT. */
14684 s->size += 8;
0855e32b
NS		 14685 if (*local_tls_type & GOT_TLS_GDESC)
14686 {
14687 *local_tlsdesc_gotent = htab->root.sgotplt->size
14688 - elf32_arm_compute_jump_table_size (htab);
14689 htab->root.sgotplt->size += 8;
14690 *local_got = (bfd_vma) -2;
34e77a92 14691 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14692 reloc in the middle of .got.plt. */
99059e56 14693 htab->num_tls_desc++;
0855e32b 14694 }
ba93b8ac
DJ		 14695 if (*local_tls_type & GOT_TLS_IE)
14696 s->size += 4;
ba93b8ac 14697
0855e32b
NS		 14698 if (*local_tls_type & GOT_NORMAL)
14699 {
14700 /* If the symbol is both GD and GDESC, *local_got
14701 may have been overwritten. */
14702 *local_got = s->size;
14703 s->size += 4;
14704 }
14705
34e77a92
RS		 14706 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
14707 if (isym == NULL)
14708 return FALSE;
14709
14710 /* If all references to an STT_GNU_IFUNC PLT are calls,
14711 then all non-call references, including this GOT entry,
14712 resolve directly to the run-time target. */
14713 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
14714 && (local_iplt == NULL
14715 || local_iplt->arm.noncall_refcount == 0))
14716 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 14717 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 14718 {
0e1862bb 14719 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 14720 || *local_tls_type & GOT_TLS_GD)
14721 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 14722
0e1862bb 14723 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 14724 {
14725 elf32_arm_allocate_dynrelocs (info,
14726 htab->root.srelplt, 1);
14727 htab->tls_trampoline = -1;
14728 }
0855e32b 14729 }
5e681ec4
PB		 14730 }
14731 else
14732 *local_got = (bfd_vma) -1;
14733 }
252b5132
RH		 14734 }
14735
ba93b8ac
DJ		 14736 if (htab->tls_ldm_got.refcount > 0)
14737 {
14738 /* Allocate two GOT entries and one dynamic relocation (if necessary)
14739 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 14740 htab->tls_ldm_got.offset = htab->root.sgot->size;
14741 htab->root.sgot->size += 8;
0e1862bb 14742 if (bfd_link_pic (info))
47beaa6a 14743 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14744 }
14745 else
14746 htab->tls_ldm_got.offset = -1;
14747
5e681ec4
PB		 14748 /* Allocate global sym .plt and .got entries, and space for global
14749 sym dynamic relocs. */
47beaa6a 14750 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 14751
d504ffc8 14752 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 14753 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 14754 {
0ffa91dd 14755 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 14756 continue;
14757
c7b8f16e
JB		 14758 /* Initialise mapping tables for code/data. */
14759 bfd_elf32_arm_init_maps (ibfd);
906e58ca 14760
c7b8f16e 14761 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 14762 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
14763 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 14764 /* xgettext:c-format */
14765 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 14766 ibfd->filename);
14767 }
d504ffc8 14768
3e6b1042
DJ		 14769 /* Allocate space for the glue sections now that we've sized them. */
14770 bfd_elf32_arm_allocate_interworking_sections (info);
14771
0855e32b
NS		 14772 /* For every jump slot reserved in the sgotplt, reloc_count is
14773 incremented. However, when we reserve space for TLS descriptors,
14774 it's not incremented, so in order to compute the space reserved
14775 for them, it suffices to multiply the reloc count by the jump
14776 slot size. */
14777 if (htab->root.srelplt)
14778 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
14779
14780 if (htab->tls_trampoline)
14781 {
14782 if (htab->root.splt->size == 0)
14783 htab->root.splt->size += htab->plt_header_size;
b38cadfb 14784
0855e32b
NS		 14785 htab->tls_trampoline = htab->root.splt->size;
14786 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 14787
0855e32b 14788 /* If we're not using lazy TLS relocations, don't generate the
99059e56 14789 PLT and GOT entries they require. */
0855e32b
NS		 14790 if (!(info->flags & DF_BIND_NOW))
14791 {
14792 htab->dt_tlsdesc_got = htab->root.sgot->size;
14793 htab->root.sgot->size += 4;
14794
14795 htab->dt_tlsdesc_plt = htab->root.splt->size;
14796 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
14797 }
14798 }
14799
252b5132
RH		 14800 /* The check_relocs and adjust_dynamic_symbol entry points have
14801 determined the sizes of the various dynamic sections. Allocate
14802 memory for them. */
b34976b6
AM		 14803 plt = FALSE;
14804 relocs = FALSE;
252b5132
RH		 14805 for (s = dynobj->sections; s != NULL; s = s->next)
14806 {
14807 const char * name;
252b5132
RH		 14808
14809 if ((s->flags & SEC_LINKER_CREATED) == 0)
14810 continue;
14811
14812 /* It's OK to base decisions on the section name, because none
14813 of the dynobj section names depend upon the input files. */
14814 name = bfd_get_section_name (dynobj, s);
14815
34e77a92 14816 if (s == htab->root.splt)
252b5132 14817 {
c456f082
AM		 14818 /* Remember whether there is a PLT. */
14819 plt = s->size != 0;
252b5132 14820 }
0112cd26 14821 else if (CONST_STRNEQ (name, ".rel"))
252b5132 14822 {
c456f082 14823 if (s->size != 0)
252b5132 14824 {
252b5132 14825 /* Remember whether there are any reloc sections other
00a97672 14826 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 14827 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 14828 relocs = TRUE;
252b5132
RH		 14829
14830 /* We use the reloc_count field as a counter if we need
14831 to copy relocs into the output file. */
14832 s->reloc_count = 0;
14833 }
14834 }
34e77a92
RS		 14835 else if (s != htab->root.sgot
14836 && s != htab->root.sgotplt
14837 && s != htab->root.iplt
14838 && s != htab->root.igotplt
14839 && s != htab->sdynbss)
252b5132
RH		 14840 {
14841 /* It's not one of our sections, so don't allocate space. */
14842 continue;
14843 }
14844
c456f082 14845 if (s->size == 0)
252b5132 14846 {
c456f082 14847 /* If we don't need this section, strip it from the
00a97672
RS		 14848 output file. This is mostly to handle .rel(a).bss and
14849 .rel(a).plt. We must create both sections in
c456f082
AM		 14850 create_dynamic_sections, because they must be created
14851 before the linker maps input sections to output
14852 sections. The linker does that before
14853 adjust_dynamic_symbol is called, and it is that
14854 function which decides whether anything needs to go
14855 into these sections. */
8423293d 14856 s->flags |= SEC_EXCLUDE;
252b5132
RH		 14857 continue;
14858 }
14859
c456f082
AM		 14860 if ((s->flags & SEC_HAS_CONTENTS) == 0)
14861 continue;
14862
252b5132 14863 /* Allocate memory for the section contents. */
21d799b5 14864 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 14865 if (s->contents == NULL)
b34976b6 14866 return FALSE;
252b5132
RH		 14867 }
14868
14869 if (elf_hash_table (info)->dynamic_sections_created)
14870 {
14871 /* Add some entries to the .dynamic section. We fill in the
14872 values later, in elf32_arm_finish_dynamic_sections, but we
14873 must add the entries now so that we get the correct size for
14874 the .dynamic section. The DT_DEBUG entry is filled in by the
14875 dynamic linker and used by the debugger. */
dc810e39 14876#define add_dynamic_entry(TAG, VAL) \
5a580b3a 14877 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 14878
0e1862bb 14879 if (bfd_link_executable (info))
252b5132 14880 {
dc810e39 14881 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 14882 return FALSE;
252b5132
RH		 14883 }
14884
14885 if (plt)
14886 {
dc810e39
AM		 14887 if ( !add_dynamic_entry (DT_PLTGOT, 0)
14888 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 14889 || !add_dynamic_entry (DT_PLTREL,
14890 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 14891 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 14892 return FALSE;
0855e32b
NS		 14893
14894 if (htab->dt_tlsdesc_plt &&
b38cadfb 14895 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 14896 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 14897 return FALSE;
252b5132
RH		 14898 }
14899
14900 if (relocs)
14901 {
00a97672
RS		 14902 if (htab->use_rel)
14903 {
14904 if (!add_dynamic_entry (DT_REL, 0)
14905 || !add_dynamic_entry (DT_RELSZ, 0)
14906 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
14907 return FALSE;
14908 }
14909 else
14910 {
14911 if (!add_dynamic_entry (DT_RELA, 0)
14912 || !add_dynamic_entry (DT_RELASZ, 0)
14913 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
14914 return FALSE;
14915 }
252b5132
RH		 14916 }
14917
08d1f311
DJ		 14918 /* If any dynamic relocs apply to a read-only section,
14919 then we need a DT_TEXTREL entry. */
14920 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 14921 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
14922 info);
08d1f311 14923
99e4ae17 14924 if ((info->flags & DF_TEXTREL) != 0)
252b5132 14925 {
dc810e39 14926 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 14927 return FALSE;
252b5132 14928 }
7a2b07ff
NS		 14929 if (htab->vxworks_p
14930 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
14931 return FALSE;
252b5132 14932 }
8532796c 14933#undef add_dynamic_entry
252b5132 14934
b34976b6 14935 return TRUE;
252b5132
RH		 14936}
14937
0855e32b
NS		 14938/* Size sections even though they're not dynamic. We use it to setup
14939 _TLS_MODULE_BASE_, if needed. */
14940
14941static bfd_boolean
14942elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 14943 struct bfd_link_info *info)
0855e32b
NS		 14944{
14945 asection *tls_sec;
14946
0e1862bb 14947 if (bfd_link_relocatable (info))
0855e32b
NS		 14948 return TRUE;
14949
14950 tls_sec = elf_hash_table (info)->tls_sec;
14951
14952 if (tls_sec)
14953 {
14954 struct elf_link_hash_entry *tlsbase;
14955
14956 tlsbase = elf_link_hash_lookup
14957 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
14958
14959 if (tlsbase)
99059e56
RM		 14960 {
14961 struct bfd_link_hash_entry *bh = NULL;
0855e32b 14962 const struct elf_backend_data *bed
99059e56 14963 = get_elf_backend_data (output_bfd);
0855e32b 14964
99059e56 14965 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 14966 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
14967 tls_sec, 0, NULL, FALSE,
14968 bed->collect, &bh)))
14969 return FALSE;
b38cadfb 14970
99059e56
RM		 14971 tlsbase->type = STT_TLS;
14972 tlsbase = (struct elf_link_hash_entry *)bh;
14973 tlsbase->def_regular = 1;
14974 tlsbase->other = STV_HIDDEN;
14975 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 14976 }
14977 }
14978 return TRUE;
14979}
14980
252b5132
RH		 14981/* Finish up dynamic symbol handling. We set the contents of various
14982 dynamic sections here. */
14983
b34976b6 14984static bfd_boolean
906e58ca
NC		 14985elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
14986 struct bfd_link_info * info,
14987 struct elf_link_hash_entry * h,
14988 Elf_Internal_Sym * sym)
252b5132 14989{
e5a52504 14990 struct elf32_arm_link_hash_table *htab;
b7693d02 14991 struct elf32_arm_link_hash_entry *eh;
252b5132 14992
e5a52504 14993 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14994 if (htab == NULL)
14995 return FALSE;
14996
b7693d02 14997 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 14998
14999 if (h->plt.offset != (bfd_vma) -1)
15000 {
34e77a92 15001 if (!eh->is_iplt)
e5a52504 15002 {
34e77a92 15003 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 15004 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
15005 h->dynindx, 0))
15006 return FALSE;
e5a52504 15007 }
57e8b36a 15008
f5385ebf 15009 if (!h->def_regular)
252b5132
RH		 15010 {
15011 /* Mark the symbol as undefined, rather than as defined in
3a635617 15012 the .plt section. */
252b5132 15013 sym->st_shndx = SHN_UNDEF;
3a635617 15014 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 15015 Otherwise, the PLT entry would provide a definition for
15016 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 15017 and so the symbol would never be NULL. Leave the value if
15018 there were any relocations where pointer equality matters
15019 (this is a clue for the dynamic linker, to make function
15020 pointer comparisons work between an application and shared
15021 library). */
97323ad1 15022 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 15023 sym->st_value = 0;
252b5132 15024 }
34e77a92
RS		 15025 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
15026 {
15027 /* At least one non-call relocation references this .iplt entry,
15028 so the .iplt entry is the function's canonical address. */
15029 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
15030 sym->st_target_internal = ST_BRANCH_TO_ARM;
15031 sym->st_shndx = (_bfd_elf_section_from_bfd_section
15032 (output_bfd, htab->root.iplt->output_section));
15033 sym->st_value = (h->plt.offset
15034 + htab->root.iplt->output_section->vma
15035 + htab->root.iplt->output_offset);
15036 }
252b5132
RH		 15037 }
15038
f5385ebf 15039 if (h->needs_copy)
252b5132
RH		 15040 {
15041 asection * s;
947216bf 15042 Elf_Internal_Rela rel;
252b5132
RH		 15043
15044 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 15045 BFD_ASSERT (h->dynindx != -1
15046 && (h->root.type == bfd_link_hash_defined
15047 || h->root.type == bfd_link_hash_defweak));
15048
362d30a1 15049 s = htab->srelbss;
252b5132
RH		 15050 BFD_ASSERT (s != NULL);
15051
00a97672 15052 rel.r_addend = 0;
252b5132
RH		 15053 rel.r_offset = (h->root.u.def.value
15054 + h->root.u.def.section->output_section->vma
15055 + h->root.u.def.section->output_offset);
15056 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 15057 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 15058 }
15059
00a97672
RS		 15060 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
15061 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
15062 to the ".got" section. */
9637f6ef 15063 if (h == htab->root.hdynamic
00a97672 15064 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 15065 sym->st_shndx = SHN_ABS;
15066
b34976b6 15067 return TRUE;
252b5132
RH		 15068}
15069
0855e32b
NS		 15070static void
15071arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15072 void *contents,
15073 const unsigned long *template, unsigned count)
15074{
15075 unsigned ix;
b38cadfb 15076
0855e32b
NS		 15077 for (ix = 0; ix != count; ix++)
15078 {
15079 unsigned long insn = template[ix];
15080
15081 /* Emit mov pc,rx if bx is not permitted. */
15082 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
15083 insn = (insn & 0xf000000f) | 0x01a0f000;
15084 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
15085 }
15086}
15087
99059e56
RM		 15088/* Install the special first PLT entry for elf32-arm-nacl. Unlike
15089 other variants, NaCl needs this entry in a static executable's
15090 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
15091 zero. For .iplt really only the last bundle is useful, and .iplt
15092 could have a shorter first entry, with each individual PLT entry's
15093 relative branch calculated differently so it targets the last
15094 bundle instead of the instruction before it (labelled .Lplt_tail
15095 above). But it's simpler to keep the size and layout of PLT0
15096 consistent with the dynamic case, at the cost of some dead code at
15097 the start of .iplt and the one dead store to the stack at the start
15098 of .Lplt_tail. */
15099static void
15100arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15101 asection *plt, bfd_vma got_displacement)
15102{
15103 unsigned int i;
15104
15105 put_arm_insn (htab, output_bfd,
15106 elf32_arm_nacl_plt0_entry[0]
15107 | arm_movw_immediate (got_displacement),
15108 plt->contents + 0);
15109 put_arm_insn (htab, output_bfd,
15110 elf32_arm_nacl_plt0_entry[1]
15111 | arm_movt_immediate (got_displacement),
15112 plt->contents + 4);
15113
15114 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
15115 put_arm_insn (htab, output_bfd,
15116 elf32_arm_nacl_plt0_entry[i],
15117 plt->contents + (i * 4));
15118}
15119
252b5132
RH		 15120/* Finish up the dynamic sections. */
15121
b34976b6 15122static bfd_boolean
57e8b36a 15123elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 15124{
15125 bfd * dynobj;
15126 asection * sgot;
15127 asection * sdyn;
4dfe6ac6
NC		 15128 struct elf32_arm_link_hash_table *htab;
15129
15130 htab = elf32_arm_hash_table (info);
15131 if (htab == NULL)
15132 return FALSE;
252b5132
RH		 15133
15134 dynobj = elf_hash_table (info)->dynobj;
15135
362d30a1 15136 sgot = htab->root.sgotplt;
894891db
NC		 15137 /* A broken linker script might have discarded the dynamic sections.
15138 Catch this here so that we do not seg-fault later on. */
15139 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
15140 return FALSE;
3d4d4302 15141 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 15142
15143 if (elf_hash_table (info)->dynamic_sections_created)
15144 {
15145 asection *splt;
15146 Elf32_External_Dyn *dyncon, *dynconend;
15147
362d30a1 15148 splt = htab->root.splt;
24a1ba0f 15149 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 15150 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 15151
15152 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 15153 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 15154
252b5132
RH		 15155 for (; dyncon < dynconend; dyncon++)
15156 {
15157 Elf_Internal_Dyn dyn;
15158 const char * name;
15159 asection * s;
15160
15161 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
15162
15163 switch (dyn.d_tag)
15164 {
229fcec5
MM		 15165 unsigned int type;
15166
252b5132 15167 default:
7a2b07ff
NS		 15168 if (htab->vxworks_p
15169 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
15170 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 15171 break;
15172
229fcec5
MM		 15173 case DT_HASH:
15174 name = ".hash";
15175 goto get_vma_if_bpabi;
15176 case DT_STRTAB:
15177 name = ".dynstr";
15178 goto get_vma_if_bpabi;
15179 case DT_SYMTAB:
15180 name = ".dynsym";
15181 goto get_vma_if_bpabi;
c0042f5d
MM		 15182 case DT_VERSYM:
15183 name = ".gnu.version";
15184 goto get_vma_if_bpabi;
15185 case DT_VERDEF:
15186 name = ".gnu.version_d";
15187 goto get_vma_if_bpabi;
15188 case DT_VERNEED:
15189 name = ".gnu.version_r";
15190 goto get_vma_if_bpabi;
15191
252b5132
RH		 15192 case DT_PLTGOT:
15193 name = ".got";
15194 goto get_vma;
15195 case DT_JMPREL:
00a97672 15196 name = RELOC_SECTION (htab, ".plt");
252b5132
RH		 15197 get_vma:
15198 s = bfd_get_section_by_name (output_bfd, name);
05456594
NC		 15199 if (s == NULL)
15200 {
15201 /* PR ld/14397: Issue an error message if a required section is missing. */
15202 (*_bfd_error_handler)
15203 (_("error: required section '%s' not found in the linker script"), name);
15204 bfd_set_error (bfd_error_invalid_operation);
15205 return FALSE;
15206 }
229fcec5
MM		 15207 if (!htab->symbian_p)
15208 dyn.d_un.d_ptr = s->vma;
15209 else
15210 /* In the BPABI, tags in the PT_DYNAMIC section point
15211 at the file offset, not the memory address, for the
15212 convenience of the post linker. */
15213 dyn.d_un.d_ptr = s->filepos;
252b5132
RH		 15214 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15215 break;
15216
229fcec5
MM		 15217 get_vma_if_bpabi:
15218 if (htab->symbian_p)
15219 goto get_vma;
15220 break;
15221
252b5132 15222 case DT_PLTRELSZ:
362d30a1 15223 s = htab->root.srelplt;
252b5132 15224 BFD_ASSERT (s != NULL);
eea6121a 15225 dyn.d_un.d_val = s->size;
252b5132
RH		 15226 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15227 break;
906e58ca 15228
252b5132 15229 case DT_RELSZ:
00a97672 15230 case DT_RELASZ:
229fcec5
MM		 15231 if (!htab->symbian_p)
15232 {
15233 /* My reading of the SVR4 ABI indicates that the
15234 procedure linkage table relocs (DT_JMPREL) should be
15235 included in the overall relocs (DT_REL). This is
15236 what Solaris does. However, UnixWare can not handle
15237 that case. Therefore, we override the DT_RELSZ entry
15238 here to make it not include the JMPREL relocs. Since
00a97672 15239 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 15240 other relocation sections, we don't have to worry
15241 about changing the DT_REL entry. */
362d30a1 15242 s = htab->root.srelplt;
229fcec5
MM		 15243 if (s != NULL)
15244 dyn.d_un.d_val -= s->size;
15245 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15246 break;
15247 }
8029a119 15248 /* Fall through. */
229fcec5
MM		 15249
15250 case DT_REL:
15251 case DT_RELA:
229fcec5
MM		 15252 /* In the BPABI, the DT_REL tag must point at the file
15253 offset, not the VMA, of the first relocation
15254 section. So, we use code similar to that in
15255 elflink.c, but do not check for SHF_ALLOC on the
15256 relcoation section, since relocations sections are
15257 never allocated under the BPABI. The comments above
15258 about Unixware notwithstanding, we include all of the
15259 relocations here. */
15260 if (htab->symbian_p)
15261 {
15262 unsigned int i;
15263 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
15264 ? SHT_REL : SHT_RELA);
15265 dyn.d_un.d_val = 0;
15266 for (i = 1; i < elf_numsections (output_bfd); i++)
15267 {
906e58ca 15268 Elf_Internal_Shdr *hdr
229fcec5
MM		 15269 = elf_elfsections (output_bfd)[i];
15270 if (hdr->sh_type == type)
15271 {
906e58ca 15272 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 15273 || dyn.d_tag == DT_RELASZ)
15274 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 15275 else if ((ufile_ptr) hdr->sh_offset
15276 <= dyn.d_un.d_val - 1)
229fcec5
MM		 15277 dyn.d_un.d_val = hdr->sh_offset;
15278 }
15279 }
15280 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15281 }
252b5132 15282 break;
88f7bcd5 15283
0855e32b 15284 case DT_TLSDESC_PLT:
99059e56 15285 s = htab->root.splt;
0855e32b
NS		 15286 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
15287 + htab->dt_tlsdesc_plt);
15288 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15289 break;
15290
15291 case DT_TLSDESC_GOT:
99059e56 15292 s = htab->root.sgot;
0855e32b 15293 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 15294 + htab->dt_tlsdesc_got);
0855e32b
NS		 15295 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15296 break;
15297
88f7bcd5
NC		 15298 /* Set the bottom bit of DT_INIT/FINI if the
15299 corresponding function is Thumb. */
15300 case DT_INIT:
15301 name = info->init_function;
15302 goto get_sym;
15303 case DT_FINI:
15304 name = info->fini_function;
15305 get_sym:
15306 /* If it wasn't set by elf_bfd_final_link
4cc11e76 15307 then there is nothing to adjust. */
88f7bcd5
NC		 15308 if (dyn.d_un.d_val != 0)
15309 {
15310 struct elf_link_hash_entry * eh;
15311
15312 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 15313 FALSE, FALSE, TRUE);
35fc36a8 15314 if (eh != NULL && eh->target_internal == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 15315 {
15316 dyn.d_un.d_val |= 1;
b34976b6 15317 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 15318 }
15319 }
15320 break;
252b5132
RH		 15321 }
15322 }
15323
24a1ba0f 15324 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 15325 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 15326 {
00a97672
RS		 15327 const bfd_vma *plt0_entry;
15328 bfd_vma got_address, plt_address, got_displacement;
15329
15330 /* Calculate the addresses of the GOT and PLT. */
15331 got_address = sgot->output_section->vma + sgot->output_offset;
15332 plt_address = splt->output_section->vma + splt->output_offset;
15333
15334 if (htab->vxworks_p)
15335 {
15336 /* The VxWorks GOT is relocated by the dynamic linker.
15337 Therefore, we must emit relocations rather than simply
15338 computing the values now. */
15339 Elf_Internal_Rela rel;
15340
15341 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 15342 put_arm_insn (htab, output_bfd, plt0_entry[0],
15343 splt->contents + 0);
15344 put_arm_insn (htab, output_bfd, plt0_entry[1],
15345 splt->contents + 4);
15346 put_arm_insn (htab, output_bfd, plt0_entry[2],
15347 splt->contents + 8);
00a97672
RS		 15348 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
15349
8029a119 15350 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 15351 rel.r_offset = plt_address + 12;
15352 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15353 rel.r_addend = 0;
15354 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
15355 htab->srelplt2->contents);
15356 }
b38cadfb 15357 else if (htab->nacl_p)
99059e56
RM		 15358 arm_nacl_put_plt0 (htab, output_bfd, splt,
15359 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 15360 else if (using_thumb_only (htab))
15361 {
15362 got_displacement = got_address - (plt_address + 12);
15363
15364 plt0_entry = elf32_thumb2_plt0_entry;
15365 put_arm_insn (htab, output_bfd, plt0_entry[0],
15366 splt->contents + 0);
15367 put_arm_insn (htab, output_bfd, plt0_entry[1],
15368 splt->contents + 4);
15369 put_arm_insn (htab, output_bfd, plt0_entry[2],
15370 splt->contents + 8);
15371
15372 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
15373 }
00a97672
RS		 15374 else
15375 {
15376 got_displacement = got_address - (plt_address + 16);
15377
15378 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 15379 put_arm_insn (htab, output_bfd, plt0_entry[0],
15380 splt->contents + 0);
15381 put_arm_insn (htab, output_bfd, plt0_entry[1],
15382 splt->contents + 4);
15383 put_arm_insn (htab, output_bfd, plt0_entry[2],
15384 splt->contents + 8);
15385 put_arm_insn (htab, output_bfd, plt0_entry[3],
15386 splt->contents + 12);
5e681ec4 15387
5e681ec4 15388#ifdef FOUR_WORD_PLT
00a97672
RS		 15389 /* The displacement value goes in the otherwise-unused
15390 last word of the second entry. */
15391 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 15392#else
00a97672 15393 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 15394#endif
00a97672 15395 }
f7a74f8c 15396 }
252b5132
RH		 15397
15398 /* UnixWare sets the entsize of .plt to 4, although that doesn't
15399 really seem like the right value. */
74541ad4
AM		 15400 if (splt->output_section->owner == output_bfd)
15401 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 15402
0855e32b
NS		 15403 if (htab->dt_tlsdesc_plt)
15404 {
15405 bfd_vma got_address
15406 = sgot->output_section->vma + sgot->output_offset;
15407 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
15408 + htab->root.sgot->output_offset);
15409 bfd_vma plt_address
15410 = splt->output_section->vma + splt->output_offset;
15411
b38cadfb 15412 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15413 splt->contents + htab->dt_tlsdesc_plt,
15414 dl_tlsdesc_lazy_trampoline, 6);
15415
15416 bfd_put_32 (output_bfd,
15417 gotplt_address + htab->dt_tlsdesc_got
15418 - (plt_address + htab->dt_tlsdesc_plt)
15419 - dl_tlsdesc_lazy_trampoline[6],
15420 splt->contents + htab->dt_tlsdesc_plt + 24);
15421 bfd_put_32 (output_bfd,
15422 got_address - (plt_address + htab->dt_tlsdesc_plt)
15423 - dl_tlsdesc_lazy_trampoline[7],
15424 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
15425 }
15426
15427 if (htab->tls_trampoline)
15428 {
b38cadfb 15429 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15430 splt->contents + htab->tls_trampoline,
15431 tls_trampoline, 3);
15432#ifdef FOUR_WORD_PLT
15433 bfd_put_32 (output_bfd, 0x00000000,
15434 splt->contents + htab->tls_trampoline + 12);
b38cadfb 15435#endif
0855e32b
NS		 15436 }
15437
0e1862bb
L		 15438 if (htab->vxworks_p
15439 && !bfd_link_pic (info)
15440 && htab->root.splt->size > 0)
00a97672
RS		 15441 {
15442 /* Correct the .rel(a).plt.unloaded relocations. They will have
15443 incorrect symbol indexes. */
15444 int num_plts;
eed62c48 15445 unsigned char *p;
00a97672 15446
362d30a1 15447 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 15448 / htab->plt_entry_size);
15449 p = htab->srelplt2->contents + RELOC_SIZE (htab);
15450
15451 for (; num_plts; num_plts--)
15452 {
15453 Elf_Internal_Rela rel;
15454
15455 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15456 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15457 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15458 p += RELOC_SIZE (htab);
15459
15460 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15461 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
15462 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15463 p += RELOC_SIZE (htab);
15464 }
15465 }
252b5132
RH		 15466 }
15467
99059e56
RM		 15468 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
15469 /* NaCl uses a special first entry in .iplt too. */
15470 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
15471
252b5132 15472 /* Fill in the first three entries in the global offset table. */
229fcec5 15473 if (sgot)
252b5132 15474 {
229fcec5
MM		 15475 if (sgot->size > 0)
15476 {
15477 if (sdyn == NULL)
15478 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
15479 else
15480 bfd_put_32 (output_bfd,
15481 sdyn->output_section->vma + sdyn->output_offset,
15482 sgot->contents);
15483 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
15484 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
15485 }
252b5132 15486
229fcec5
MM		 15487 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
15488 }
252b5132 15489
b34976b6 15490 return TRUE;
252b5132
RH		 15491}
15492
ba96a88f 15493static void
57e8b36a 15494elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 15495{
9b485d32 15496 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 15497 struct elf32_arm_link_hash_table *globals;
ac4c9b04 15498 struct elf_segment_map *m;
ba96a88f
NC		 15499
15500 i_ehdrp = elf_elfheader (abfd);
15501
94a3258f
PB		 15502 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
15503 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
15504 else
7394f108 15505 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 15506 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 15507
93204d3a
PB		 15508 if (link_info)
15509 {
15510 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 15511 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 15512 i_ehdrp->e_flags |= EF_ARM_BE8;
15513 }
3bfcb652
NC		 15514
15515 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
15516 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
15517 {
15518 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 15519 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 15520 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
15521 else
15522 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
15523 }
ac4c9b04
MG		 15524
15525 /* Scan segment to set p_flags attribute if it contains only sections with
15526 SHF_ARM_NOREAD flag. */
15527 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
15528 {
15529 unsigned int j;
15530
15531 if (m->count == 0)
15532 continue;
15533 for (j = 0; j < m->count; j++)
15534 {
15535 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_NOREAD))
15536 break;
15537 }
15538 if (j == m->count)
15539 {
15540 m->p_flags = PF_X;
15541 m->p_flags_valid = 1;
15542 }
15543 }
ba96a88f
NC		 15544}
15545
99e4ae17 15546static enum elf_reloc_type_class
7e612e98
AM		 15547elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
15548 const asection *rel_sec ATTRIBUTE_UNUSED,
15549 const Elf_Internal_Rela *rela)
99e4ae17 15550{
f51e552e 15551 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 15552 {
15553 case R_ARM_RELATIVE:
15554 return reloc_class_relative;
15555 case R_ARM_JUMP_SLOT:
15556 return reloc_class_plt;
15557 case R_ARM_COPY:
15558 return reloc_class_copy;
109575d7
JW		 15559 case R_ARM_IRELATIVE:
15560 return reloc_class_ifunc;
99e4ae17
AJ		 15561 default:
15562 return reloc_class_normal;
15563 }
15564}
15565
e489d0ae 15566static void
57e8b36a 15567elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 15568{
5a6c6817 15569 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 15570}
15571
40a18ebd
NC		 15572/* Return TRUE if this is an unwinding table entry. */
15573
15574static bfd_boolean
15575is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
15576{
0112cd26
NC		 15577 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
15578 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 15579}
15580
15581
15582/* Set the type and flags for an ARM section. We do this by
15583 the section name, which is a hack, but ought to work. */
15584
15585static bfd_boolean
15586elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
15587{
15588 const char * name;
15589
15590 name = bfd_get_section_name (abfd, sec);
15591
15592 if (is_arm_elf_unwind_section_name (abfd, name))
15593 {
15594 hdr->sh_type = SHT_ARM_EXIDX;
15595 hdr->sh_flags |= SHF_LINK_ORDER;
15596 }
ac4c9b04
MG		 15597
15598 if (sec->flags & SEC_ELF_NOREAD)
15599 hdr->sh_flags |= SHF_ARM_NOREAD;
15600
40a18ebd
NC		 15601 return TRUE;
15602}
15603
6dc132d9
L		 15604/* Handle an ARM specific section when reading an object file. This is
15605 called when bfd_section_from_shdr finds a section with an unknown
15606 type. */
40a18ebd
NC		 15607
15608static bfd_boolean
15609elf32_arm_section_from_shdr (bfd *abfd,
15610 Elf_Internal_Shdr * hdr,
6dc132d9
L		 15611 const char *name,
15612 int shindex)
40a18ebd
NC		 15613{
15614 /* There ought to be a place to keep ELF backend specific flags, but
15615 at the moment there isn't one. We just keep track of the
15616 sections by their name, instead. Fortunately, the ABI gives
15617 names for all the ARM specific sections, so we will probably get
15618 away with this. */
15619 switch (hdr->sh_type)
15620 {
15621 case SHT_ARM_EXIDX:
0951f019
RE		 15622 case SHT_ARM_PREEMPTMAP:
15623 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 15624 break;
15625
15626 default:
15627 return FALSE;
15628 }
15629
6dc132d9 15630 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 15631 return FALSE;
15632
15633 return TRUE;
15634}
e489d0ae 15635
44444f50
NC		 15636static _arm_elf_section_data *
15637get_arm_elf_section_data (asection * sec)
15638{
47b2e99c
JZ		 15639 if (sec && sec->owner && is_arm_elf (sec->owner))
15640 return elf32_arm_section_data (sec);
44444f50
NC		 15641 else
15642 return NULL;
8e3de13a
NC		 15643}
15644
4e617b1e
PB		 15645typedef struct
15646{
57402f1e 15647 void *flaginfo;
4e617b1e 15648 struct bfd_link_info *info;
91a5743d
PB		 15649 asection *sec;
15650 int sec_shndx;
6e0b88f1
AM		 15651 int (*func) (void *, const char *, Elf_Internal_Sym *,
15652 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 15653} output_arch_syminfo;
15654
15655enum map_symbol_type
15656{
15657 ARM_MAP_ARM,
15658 ARM_MAP_THUMB,
15659 ARM_MAP_DATA
15660};
15661
15662
7413f23f 15663/* Output a single mapping symbol. */
4e617b1e
PB		 15664
15665static bfd_boolean
7413f23f
DJ		 15666elf32_arm_output_map_sym (output_arch_syminfo *osi,
15667 enum map_symbol_type type,
15668 bfd_vma offset)
4e617b1e
PB		 15669{
15670 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 15671 Elf_Internal_Sym sym;
15672
91a5743d
PB		 15673 sym.st_value = osi->sec->output_section->vma
15674 + osi->sec->output_offset
15675 + offset;
4e617b1e
PB		 15676 sym.st_size = 0;
15677 sym.st_other = 0;
15678 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 15679 sym.st_shndx = osi->sec_shndx;
35fc36a8 15680 sym.st_target_internal = 0;
fe33d2fa 15681 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 15682 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 15683}
15684
34e77a92
RS		 15685/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
15686 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 15687
15688static bfd_boolean
34e77a92
RS		 15689elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
15690 bfd_boolean is_iplt_entry_p,
15691 union gotplt_union *root_plt,
15692 struct arm_plt_info *arm_plt)
4e617b1e 15693{
4e617b1e 15694 struct elf32_arm_link_hash_table *htab;
34e77a92 15695 bfd_vma addr, plt_header_size;
4e617b1e 15696
34e77a92 15697 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 15698 return TRUE;
15699
4dfe6ac6
NC		 15700 htab = elf32_arm_hash_table (osi->info);
15701 if (htab == NULL)
15702 return FALSE;
15703
34e77a92
RS		 15704 if (is_iplt_entry_p)
15705 {
15706 osi->sec = htab->root.iplt;
15707 plt_header_size = 0;
15708 }
15709 else
15710 {
15711 osi->sec = htab->root.splt;
15712 plt_header_size = htab->plt_header_size;
15713 }
15714 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
15715 (osi->info->output_bfd, osi->sec->output_section));
15716
15717 addr = root_plt->offset & -2;
4e617b1e
PB		 15718 if (htab->symbian_p)
15719 {
7413f23f 15720 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15721 return FALSE;
7413f23f 15722 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 15723 return FALSE;
15724 }
15725 else if (htab->vxworks_p)
15726 {
7413f23f 15727 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15728 return FALSE;
7413f23f 15729 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 15730 return FALSE;
7413f23f 15731 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 15732 return FALSE;
7413f23f 15733 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 15734 return FALSE;
15735 }
b38cadfb
NC		 15736 else if (htab->nacl_p)
15737 {
15738 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
15739 return FALSE;
15740 }
eed94f8f
NC		 15741 else if (using_thumb_only (htab))
15742 {
15743 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
15744 return FALSE;
6a631e86 15745 }
4e617b1e
PB		 15746 else
15747 {
34e77a92 15748 bfd_boolean thumb_stub_p;
bd97cb95 15749
34e77a92
RS		 15750 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
15751 if (thumb_stub_p)
4e617b1e 15752 {
7413f23f 15753 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 15754 return FALSE;
15755 }
15756#ifdef FOUR_WORD_PLT
7413f23f 15757 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15758 return FALSE;
7413f23f 15759 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 15760 return FALSE;
15761#else
906e58ca 15762 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 15763 so only need to output a mapping symbol for the first PLT entry and
15764 entries with thumb thunks. */
34e77a92 15765 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 15766 {
7413f23f 15767 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 15768 return FALSE;
15769 }
15770#endif
15771 }
15772
15773 return TRUE;
15774}
15775
34e77a92
RS		 15776/* Output mapping symbols for PLT entries associated with H. */
15777
15778static bfd_boolean
15779elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
15780{
15781 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
15782 struct elf32_arm_link_hash_entry *eh;
15783
15784 if (h->root.type == bfd_link_hash_indirect)
15785 return TRUE;
15786
15787 if (h->root.type == bfd_link_hash_warning)
15788 /* When warning symbols are created, they **replace** the "real"
15789 entry in the hash table, thus we never get to see the real
15790 symbol in a hash traversal. So look at it now. */
15791 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15792
15793 eh = (struct elf32_arm_link_hash_entry *) h;
15794 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
15795 &h->plt, &eh->plt);
15796}
15797
7413f23f
DJ		 15798/* Output a single local symbol for a generated stub. */
15799
15800static bfd_boolean
15801elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
15802 bfd_vma offset, bfd_vma size)
15803{
7413f23f
DJ		 15804 Elf_Internal_Sym sym;
15805
7413f23f
DJ		 15806 sym.st_value = osi->sec->output_section->vma
15807 + osi->sec->output_offset
15808 + offset;
15809 sym.st_size = size;
15810 sym.st_other = 0;
15811 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
15812 sym.st_shndx = osi->sec_shndx;
35fc36a8 15813 sym.st_target_internal = 0;
57402f1e 15814 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 15815}
4e617b1e 15816
da5938a2 15817static bfd_boolean
8029a119
NC		 15818arm_map_one_stub (struct bfd_hash_entry * gen_entry,
15819 void * in_arg)
da5938a2
NC		 15820{
15821 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 15822 asection *stub_sec;
15823 bfd_vma addr;
7413f23f 15824 char *stub_name;
9a008db3 15825 output_arch_syminfo *osi;
d3ce72d0 15826 const insn_sequence *template_sequence;
461a49ca
DJ		 15827 enum stub_insn_type prev_type;
15828 int size;
15829 int i;
15830 enum map_symbol_type sym_type;
da5938a2
NC		 15831
15832 /* Massage our args to the form they really have. */
15833 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 15834 osi = (output_arch_syminfo *) in_arg;
da5938a2 15835
da5938a2
NC		 15836 stub_sec = stub_entry->stub_sec;
15837
15838 /* Ensure this stub is attached to the current section being
7413f23f 15839 processed. */
da5938a2
NC		 15840 if (stub_sec != osi->sec)
15841 return TRUE;
15842
7413f23f
DJ		 15843 addr = (bfd_vma) stub_entry->stub_offset;
15844 stub_name = stub_entry->output_name;
da5938a2 15845
d3ce72d0
NC		 15846 template_sequence = stub_entry->stub_template;
15847 switch (template_sequence[0].type)
7413f23f 15848 {
461a49ca
DJ		 15849 case ARM_TYPE:
15850 if (!elf32_arm_output_stub_sym (osi, stub_name, addr, stub_entry->stub_size))
da5938a2
NC		 15851 return FALSE;
15852 break;
461a49ca 15853 case THUMB16_TYPE:
48229727 15854 case THUMB32_TYPE:
461a49ca
DJ		 15855 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
15856 stub_entry->stub_size))
da5938a2
NC		 15857 return FALSE;
15858 break;
15859 default:
15860 BFD_FAIL ();
48229727 15861 return 0;
7413f23f 15862 }
da5938a2 15863
461a49ca
DJ		 15864 prev_type = DATA_TYPE;
15865 size = 0;
15866 for (i = 0; i < stub_entry->stub_template_size; i++)
15867 {
d3ce72d0 15868 switch (template_sequence[i].type)
461a49ca
DJ		 15869 {
15870 case ARM_TYPE:
15871 sym_type = ARM_MAP_ARM;
15872 break;
15873
15874 case THUMB16_TYPE:
48229727 15875 case THUMB32_TYPE:
461a49ca
DJ		 15876 sym_type = ARM_MAP_THUMB;
15877 break;
15878
15879 case DATA_TYPE:
15880 sym_type = ARM_MAP_DATA;
15881 break;
15882
15883 default:
15884 BFD_FAIL ();
4e31c731 15885 return FALSE;
461a49ca
DJ		 15886 }
15887
d3ce72d0 15888 if (template_sequence[i].type != prev_type)
461a49ca 15889 {
d3ce72d0 15890 prev_type = template_sequence[i].type;
461a49ca
DJ		 15891 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
15892 return FALSE;
15893 }
15894
d3ce72d0 15895 switch (template_sequence[i].type)
461a49ca
DJ		 15896 {
15897 case ARM_TYPE:
48229727 15898 case THUMB32_TYPE:
461a49ca
DJ		 15899 size += 4;
15900 break;
15901
15902 case THUMB16_TYPE:
15903 size += 2;
15904 break;
15905
15906 case DATA_TYPE:
15907 size += 4;
15908 break;
15909
15910 default:
15911 BFD_FAIL ();
4e31c731 15912 return FALSE;
461a49ca
DJ		 15913 }
15914 }
15915
da5938a2
NC		 15916 return TRUE;
15917}
15918
33811162
DG		 15919/* Output mapping symbols for linker generated sections,
15920 and for those data-only sections that do not have a
15921 $d. */
4e617b1e
PB		 15922
15923static bfd_boolean
15924elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 15925 struct bfd_link_info *info,
57402f1e 15926 void *flaginfo,
6e0b88f1
AM		 15927 int (*func) (void *, const char *,
15928 Elf_Internal_Sym *,
15929 asection *,
15930 struct elf_link_hash_entry *))
4e617b1e
PB		 15931{
15932 output_arch_syminfo osi;
15933 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 15934 bfd_vma offset;
15935 bfd_size_type size;
33811162 15936 bfd *input_bfd;
4e617b1e
PB		 15937
15938 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15939 if (htab == NULL)
15940 return FALSE;
15941
906e58ca 15942 check_use_blx (htab);
91a5743d 15943
57402f1e 15944 osi.flaginfo = flaginfo;
4e617b1e
PB		 15945 osi.info = info;
15946 osi.func = func;
906e58ca 15947
33811162
DG		 15948 /* Add a $d mapping symbol to data-only sections that
15949 don't have any mapping symbol. This may result in (harmless) redundant
15950 mapping symbols. */
15951 for (input_bfd = info->input_bfds;
15952 input_bfd != NULL;
c72f2fb2 15953 input_bfd = input_bfd->link.next)
33811162
DG		 15954 {
15955 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
15956 for (osi.sec = input_bfd->sections;
15957 osi.sec != NULL;
15958 osi.sec = osi.sec->next)
15959 {
15960 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 15961 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
15962 != 0)
33811162
DG		 15963 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
15964 == SEC_HAS_CONTENTS
15965 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 15966 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 15967 && osi.sec->size > 0
15968 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 15969 {
15970 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15971 (output_bfd, osi.sec->output_section);
15972 if (osi.sec_shndx != (int)SHN_BAD)
15973 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
15974 }
15975 }
15976 }
15977
91a5743d
PB		 15978 /* ARM->Thumb glue. */
15979 if (htab->arm_glue_size > 0)
15980 {
3d4d4302
AM		 15981 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
15982 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 15983
15984 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15985 (output_bfd, osi.sec->output_section);
0e1862bb 15986 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 15987 || htab->pic_veneer)
15988 size = ARM2THUMB_PIC_GLUE_SIZE;
15989 else if (htab->use_blx)
15990 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
15991 else
15992 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 15993
91a5743d
PB		 15994 for (offset = 0; offset < htab->arm_glue_size; offset += size)
15995 {
7413f23f
DJ		 15996 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
15997 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 15998 }
15999 }
16000
16001 /* Thumb->ARM glue. */
16002 if (htab->thumb_glue_size > 0)
16003 {
3d4d4302
AM		 16004 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16005 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 16006
16007 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16008 (output_bfd, osi.sec->output_section);
16009 size = THUMB2ARM_GLUE_SIZE;
16010
16011 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
16012 {
7413f23f
DJ		 16013 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
16014 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 16015 }
16016 }
16017
845b51d6
PB		 16018 /* ARMv4 BX veneers. */
16019 if (htab->bx_glue_size > 0)
16020 {
3d4d4302
AM		 16021 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16022 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 16023
16024 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16025 (output_bfd, osi.sec->output_section);
16026
7413f23f 16027 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 16028 }
16029
8029a119
NC		 16030 /* Long calls stubs. */
16031 if (htab->stub_bfd && htab->stub_bfd->sections)
16032 {
da5938a2 16033 asection* stub_sec;
8029a119 16034
da5938a2
NC		 16035 for (stub_sec = htab->stub_bfd->sections;
16036 stub_sec != NULL;
8029a119
NC		 16037 stub_sec = stub_sec->next)
16038 {
16039 /* Ignore non-stub sections. */
16040 if (!strstr (stub_sec->name, STUB_SUFFIX))
16041 continue;
da5938a2 16042
8029a119 16043 osi.sec = stub_sec;
da5938a2 16044
8029a119
NC		 16045 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16046 (output_bfd, osi.sec->output_section);
da5938a2 16047
8029a119
NC		 16048 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
16049 }
16050 }
da5938a2 16051
91a5743d 16052 /* Finally, output mapping symbols for the PLT. */
34e77a92 16053 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 16054 {
34e77a92
RS		 16055 osi.sec = htab->root.splt;
16056 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16057 (output_bfd, osi.sec->output_section));
16058
16059 /* Output mapping symbols for the plt header. SymbianOS does not have a
16060 plt header. */
16061 if (htab->vxworks_p)
16062 {
16063 /* VxWorks shared libraries have no PLT header. */
0e1862bb 16064 if (!bfd_link_pic (info))
34e77a92
RS		 16065 {
16066 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16067 return FALSE;
16068 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16069 return FALSE;
16070 }
16071 }
b38cadfb
NC		 16072 else if (htab->nacl_p)
16073 {
16074 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16075 return FALSE;
16076 }
eed94f8f
NC		 16077 else if (using_thumb_only (htab))
16078 {
16079 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
16080 return FALSE;
16081 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16082 return FALSE;
16083 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
16084 return FALSE;
16085 }
34e77a92 16086 else if (!htab->symbian_p)
4e617b1e 16087 {
7413f23f 16088 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 16089 return FALSE;
34e77a92
RS		 16090#ifndef FOUR_WORD_PLT
16091 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 16092 return FALSE;
34e77a92 16093#endif
4e617b1e
PB		 16094 }
16095 }
99059e56
RM		 16096 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
16097 {
16098 /* NaCl uses a special first entry in .iplt too. */
16099 osi.sec = htab->root.iplt;
16100 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16101 (output_bfd, osi.sec->output_section));
16102 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16103 return FALSE;
16104 }
34e77a92
RS		 16105 if ((htab->root.splt && htab->root.splt->size > 0)
16106 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 16107 {
34e77a92
RS		 16108 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
16109 for (input_bfd = info->input_bfds;
16110 input_bfd != NULL;
c72f2fb2 16111 input_bfd = input_bfd->link.next)
34e77a92
RS		 16112 {
16113 struct arm_local_iplt_info **local_iplt;
16114 unsigned int i, num_syms;
4e617b1e 16115
34e77a92
RS		 16116 local_iplt = elf32_arm_local_iplt (input_bfd);
16117 if (local_iplt != NULL)
16118 {
16119 num_syms = elf_symtab_hdr (input_bfd).sh_info;
16120 for (i = 0; i < num_syms; i++)
16121 if (local_iplt[i] != NULL
16122 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
16123 &local_iplt[i]->root,
16124 &local_iplt[i]->arm))
16125 return FALSE;
16126 }
16127 }
16128 }
0855e32b
NS		 16129 if (htab->dt_tlsdesc_plt != 0)
16130 {
16131 /* Mapping symbols for the lazy tls trampoline. */
16132 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
16133 return FALSE;
b38cadfb 16134
0855e32b
NS		 16135 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16136 htab->dt_tlsdesc_plt + 24))
16137 return FALSE;
16138 }
16139 if (htab->tls_trampoline != 0)
16140 {
16141 /* Mapping symbols for the tls trampoline. */
16142 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
16143 return FALSE;
16144#ifdef FOUR_WORD_PLT
16145 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16146 htab->tls_trampoline + 12))
16147 return FALSE;
b38cadfb 16148#endif
0855e32b 16149 }
b38cadfb 16150
4e617b1e
PB		 16151 return TRUE;
16152}
16153
e489d0ae
PB		 16154/* Allocate target specific section data. */
16155
16156static bfd_boolean
16157elf32_arm_new_section_hook (bfd *abfd, asection *sec)
16158{
f592407e
AM		 16159 if (!sec->used_by_bfd)
16160 {
16161 _arm_elf_section_data *sdata;
16162 bfd_size_type amt = sizeof (*sdata);
e489d0ae 16163
21d799b5 16164 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 16165 if (sdata == NULL)
16166 return FALSE;
16167 sec->used_by_bfd = sdata;
16168 }
e489d0ae
PB		 16169
16170 return _bfd_elf_new_section_hook (abfd, sec);
16171}
16172
16173
16174/* Used to order a list of mapping symbols by address. */
16175
16176static int
16177elf32_arm_compare_mapping (const void * a, const void * b)
16178{
7f6a71ff
JM		 16179 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
16180 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
16181
16182 if (amap->vma > bmap->vma)
16183 return 1;
16184 else if (amap->vma < bmap->vma)
16185 return -1;
16186 else if (amap->type > bmap->type)
16187 /* Ensure results do not depend on the host qsort for objects with
16188 multiple mapping symbols at the same address by sorting on type
16189 after vma. */
16190 return 1;
16191 else if (amap->type < bmap->type)
16192 return -1;
16193 else
16194 return 0;
e489d0ae
PB		 16195}
16196
2468f9c9
PB		 16197/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16198
16199static unsigned long
16200offset_prel31 (unsigned long addr, bfd_vma offset)
16201{
16202 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
16203}
16204
16205/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16206 relocations. */
16207
16208static void
16209copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
16210{
16211 unsigned long first_word = bfd_get_32 (output_bfd, from);
16212 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 16213
2468f9c9
PB		 16214 /* High bit of first word is supposed to be zero. */
16215 if ((first_word & 0x80000000ul) == 0)
16216 first_word = offset_prel31 (first_word, offset);
b38cadfb 16217
2468f9c9
PB		 16218 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16219 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16220 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
16221 second_word = offset_prel31 (second_word, offset);
b38cadfb 16222
2468f9c9
PB		 16223 bfd_put_32 (output_bfd, first_word, to);
16224 bfd_put_32 (output_bfd, second_word, to + 4);
16225}
e489d0ae 16226
48229727
JB		 16227/* Data for make_branch_to_a8_stub(). */
16228
b38cadfb
NC		 16229struct a8_branch_to_stub_data
16230{
48229727
JB		 16231 asection *writing_section;
16232 bfd_byte *contents;
16233};
16234
16235
16236/* Helper to insert branches to Cortex-A8 erratum stubs in the right
16237 places for a particular section. */
16238
16239static bfd_boolean
16240make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 16241 void *in_arg)
48229727
JB		 16242{
16243 struct elf32_arm_stub_hash_entry *stub_entry;
16244 struct a8_branch_to_stub_data *data;
16245 bfd_byte *contents;
16246 unsigned long branch_insn;
16247 bfd_vma veneered_insn_loc, veneer_entry_loc;
16248 bfd_signed_vma branch_offset;
16249 bfd *abfd;
91d6fa6a 16250 unsigned int target;
48229727
JB		 16251
16252 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
16253 data = (struct a8_branch_to_stub_data *) in_arg;
16254
16255 if (stub_entry->target_section != data->writing_section
4563a860 16256 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 16257 return TRUE;
16258
16259 contents = data->contents;
16260
16261 veneered_insn_loc = stub_entry->target_section->output_section->vma
16262 + stub_entry->target_section->output_offset
16263 + stub_entry->target_value;
16264
16265 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
16266 + stub_entry->stub_sec->output_offset
16267 + stub_entry->stub_offset;
16268
16269 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
16270 veneered_insn_loc &= ~3u;
16271
16272 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
16273
16274 abfd = stub_entry->target_section->owner;
91d6fa6a 16275 target = stub_entry->target_value;
48229727
JB		 16276
16277 /* We attempt to avoid this condition by setting stubs_always_after_branch
16278 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16279 This check is just to be on the safe side... */
16280 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
16281 {
16282 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
16283 "allocated in unsafe location"), abfd);
16284 return FALSE;
16285 }
16286
16287 switch (stub_entry->stub_type)
16288 {
16289 case arm_stub_a8_veneer_b:
16290 case arm_stub_a8_veneer_b_cond:
16291 branch_insn = 0xf0009000;
16292 goto jump24;
16293
16294 case arm_stub_a8_veneer_blx:
16295 branch_insn = 0xf000e800;
16296 goto jump24;
16297
16298 case arm_stub_a8_veneer_bl:
16299 {
16300 unsigned int i1, j1, i2, j2, s;
16301
16302 branch_insn = 0xf000d000;
16303
16304 jump24:
16305 if (branch_offset < -16777216 || branch_offset > 16777214)
16306 {
16307 /* There's not much we can do apart from complain if this
16308 happens. */
16309 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
16310 "of range (input file too large)"), abfd);
16311 return FALSE;
16312 }
16313
16314 /* i1 = not(j1 eor s), so:
16315 not i1 = j1 eor s
16316 j1 = (not i1) eor s. */
16317
16318 branch_insn |= (branch_offset >> 1) & 0x7ff;
16319 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
16320 i2 = (branch_offset >> 22) & 1;
16321 i1 = (branch_offset >> 23) & 1;
16322 s = (branch_offset >> 24) & 1;
16323 j1 = (!i1) ^ s;
16324 j2 = (!i2) ^ s;
16325 branch_insn |= j2 << 11;
16326 branch_insn |= j1 << 13;
16327 branch_insn |= s << 26;
16328 }
16329 break;
16330
16331 default:
16332 BFD_FAIL ();
16333 return FALSE;
16334 }
16335
91d6fa6a
NC		 16336 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[target]);
16337 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[target + 2]);
48229727
JB		 16338
16339 return TRUE;
16340}
16341
a504d23a
LA		 16342/* Beginning of stm32l4xx work-around. */
16343
16344/* Functions encoding instructions necessary for the emission of the
16345 fix-stm32l4xx-629360.
16346 Encoding is extracted from the
16347 ARM (C) Architecture Reference Manual
16348 ARMv7-A and ARMv7-R edition
16349 ARM DDI 0406C.b (ID072512). */
16350
16351static inline bfd_vma
82188b29 16352create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 16353{
16354 /* A8.8.18 B (A8-334)
16355 B target_address (Encoding T4). */
16356 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
16357 /* jump offset is: S:I1:I2:imm10:imm11:0. */
16358 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
16359
a504d23a
LA		 16360 int s = ((branch_offset & 0x1000000) >> 24);
16361 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
16362 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
16363
16364 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
16365 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
16366
16367 bfd_vma patched_inst = 0xf0009000
16368 | s << 26 /* S. */
16369 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
16370 | j1 << 13 /* J1. */
16371 | j2 << 11 /* J2. */
16372 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
16373
16374 return patched_inst;
16375}
16376
16377static inline bfd_vma
16378create_instruction_ldmia (int base_reg, int wback, int reg_mask)
16379{
16380 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
16381 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
16382 bfd_vma patched_inst = 0xe8900000
16383 | (/*W=*/wback << 21)
16384 | (base_reg << 16)
16385 | (reg_mask & 0x0000ffff);
16386
16387 return patched_inst;
16388}
16389
16390static inline bfd_vma
16391create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
16392{
16393 /* A8.8.60 LDMDB/LDMEA (A8-402)
16394 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
16395 bfd_vma patched_inst = 0xe9100000
16396 | (/*W=*/wback << 21)
16397 | (base_reg << 16)
16398 | (reg_mask & 0x0000ffff);
16399
16400 return patched_inst;
16401}
16402
16403static inline bfd_vma
16404create_instruction_mov (int target_reg, int source_reg)
16405{
16406 /* A8.8.103 MOV (register) (A8-486)
16407 MOV Rd, Rm (Encoding T1). */
16408 bfd_vma patched_inst = 0x4600
16409 | (target_reg & 0x7)
16410 | ((target_reg & 0x8) >> 3) << 7
16411 | (source_reg << 3);
16412
16413 return patched_inst;
16414}
16415
16416static inline bfd_vma
16417create_instruction_sub (int target_reg, int source_reg, int value)
16418{
16419 /* A8.8.221 SUB (immediate) (A8-708)
16420 SUB Rd, Rn, #value (Encoding T3). */
16421 bfd_vma patched_inst = 0xf1a00000
16422 | (target_reg << 8)
16423 | (source_reg << 16)
16424 | (/*S=*/0 << 20)
16425 | ((value & 0x800) >> 11) << 26
16426 | ((value & 0x700) >> 8) << 12
16427 | (value & 0x0ff);
16428
16429 return patched_inst;
16430}
16431
16432static inline bfd_vma
16433create_instruction_vldmia (int base_reg, int wback, int num_regs,
16434 int first_reg)
16435{
16436 /* A8.8.332 VLDM (A8-922)
16437 VLMD{MODE} Rn{!}, {list} (Encoding T2). */
16438 bfd_vma patched_inst = 0xec900a00
16439 | (/*W=*/wback << 21)
16440 | (base_reg << 16)
16441 | (num_regs & 0x000000ff)
16442 | (((unsigned)first_reg>>1) & 0x0000000f) << 12
16443 | (first_reg & 0x00000001) << 22;
16444
16445 return patched_inst;
16446}
16447
16448static inline bfd_vma
16449create_instruction_vldmdb (int base_reg, int num_regs, int first_reg)
16450{
16451 /* A8.8.332 VLDM (A8-922)
16452 VLMD{MODE} Rn!, {} (Encoding T2). */
16453 bfd_vma patched_inst = 0xed300a00
16454 | (base_reg << 16)
16455 | (num_regs & 0x000000ff)
16456 | (((unsigned)first_reg>>1) & 0x0000000f) << 12
16457 | (first_reg & 0x00000001) << 22;
16458
16459 return patched_inst;
16460}
16461
16462static inline bfd_vma
16463create_instruction_udf_w (int value)
16464{
16465 /* A8.8.247 UDF (A8-758)
16466 Undefined (Encoding T2). */
16467 bfd_vma patched_inst = 0xf7f0a000
16468 | (value & 0x00000fff)
16469 | (value & 0x000f0000) << 16;
16470
16471 return patched_inst;
16472}
16473
16474static inline bfd_vma
16475create_instruction_udf (int value)
16476{
16477 /* A8.8.247 UDF (A8-758)
16478 Undefined (Encoding T1). */
16479 bfd_vma patched_inst = 0xde00
16480 | (value & 0xff);
16481
16482 return patched_inst;
16483}
16484
16485/* Functions writing an instruction in memory, returning the next
16486 memory position to write to. */
16487
16488static inline bfd_byte *
16489push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
16490 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16491{
16492 put_thumb2_insn (htab, output_bfd, insn, pt);
16493 return pt + 4;
16494}
16495
16496static inline bfd_byte *
16497push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
16498 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16499{
16500 put_thumb_insn (htab, output_bfd, insn, pt);
16501 return pt + 2;
16502}
16503
16504/* Function filling up a region in memory with T1 and T2 UDFs taking
16505 care of alignment. */
16506
16507static bfd_byte *
16508stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
16509 bfd * output_bfd,
16510 const bfd_byte * const base_stub_contents,
16511 bfd_byte * const from_stub_contents,
16512 const bfd_byte * const end_stub_contents)
16513{
16514 bfd_byte *current_stub_contents = from_stub_contents;
16515
16516 /* Fill the remaining of the stub with deterministic contents : UDF
16517 instructions.
16518 Check if realignment is needed on modulo 4 frontier using T1, to
16519 further use T2. */
16520 if ((current_stub_contents < end_stub_contents)
16521 && !((current_stub_contents - base_stub_contents) % 2)
16522 && ((current_stub_contents - base_stub_contents) % 4))
16523 current_stub_contents =
16524 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16525 create_instruction_udf (0));
16526
16527 for (; current_stub_contents < end_stub_contents;)
16528 current_stub_contents =
16529 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16530 create_instruction_udf_w (0));
16531
16532 return current_stub_contents;
16533}
16534
16535/* Functions writing the stream of instructions equivalent to the
16536 derived sequence for ldmia, ldmdb, vldm respectively. */
16537
16538static void
16539stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
16540 bfd * output_bfd,
16541 const insn32 initial_insn,
16542 const bfd_byte *const initial_insn_addr,
16543 bfd_byte *const base_stub_contents)
16544{
16545 int wback = (initial_insn & 0x00200000) >> 21;
16546 int ri, rn = (initial_insn & 0x000F0000) >> 16;
16547 int insn_all_registers = initial_insn & 0x0000ffff;
16548 int insn_low_registers, insn_high_registers;
16549 int usable_register_mask;
16550 int nb_registers = popcount (insn_all_registers);
16551 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16552 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16553 bfd_byte *current_stub_contents = base_stub_contents;
16554
16555 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
16556
16557 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16558 smaller than 8 registers load sequences that do not cause the
16559 hardware issue. */
16560 if (nb_registers <= 8)
16561 {
16562 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16563 current_stub_contents =
16564 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16565 initial_insn);
16566
16567 /* B initial_insn_addr+4. */
16568 if (!restore_pc)
16569 current_stub_contents =
16570 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16571 create_instruction_branch_absolute
82188b29
NC		 16572 (initial_insn_addr - current_stub_contents));
16573
a504d23a
LA		 16574
16575 /* Fill the remaining of the stub with deterministic contents. */
16576 current_stub_contents =
16577 stm32l4xx_fill_stub_udf (htab, output_bfd,
16578 base_stub_contents, current_stub_contents,
16579 base_stub_contents +
16580 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16581
16582 return;
16583 }
16584
16585 /* - reg_list[13] == 0. */
16586 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
16587
16588 /* - reg_list[14] & reg_list[15] != 1. */
16589 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16590
16591 /* - if (wback==1) reg_list[rn] == 0. */
16592 BFD_ASSERT (!wback || !restore_rn);
16593
16594 /* - nb_registers > 8. */
16595 BFD_ASSERT (popcount (insn_all_registers) > 8);
16596
16597 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16598
16599 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
16600 - One with the 7 lowest registers (register mask 0x007F)
16601 This LDM will finally contain between 2 and 7 registers
16602 - One with the 7 highest registers (register mask 0xDF80)
16603 This ldm will finally contain between 2 and 7 registers. */
16604 insn_low_registers = insn_all_registers & 0x007F;
16605 insn_high_registers = insn_all_registers & 0xDF80;
16606
16607 /* A spare register may be needed during this veneer to temporarily
16608 handle the base register. This register will be restored with the
16609 last LDM operation.
16610 The usable register may be any general purpose register (that
16611 excludes PC, SP, LR : register mask is 0x1FFF). */
16612 usable_register_mask = 0x1FFF;
16613
16614 /* Generate the stub function. */
16615 if (wback)
16616 {
16617 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
16618 current_stub_contents =
16619 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16620 create_instruction_ldmia
16621 (rn, /*wback=*/1, insn_low_registers));
16622
16623 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
16624 current_stub_contents =
16625 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16626 create_instruction_ldmia
16627 (rn, /*wback=*/1, insn_high_registers));
16628 if (!restore_pc)
16629 {
16630 /* B initial_insn_addr+4. */
16631 current_stub_contents =
16632 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16633 create_instruction_branch_absolute
82188b29 16634 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16635 }
16636 }
16637 else /* if (!wback). */
16638 {
16639 ri = rn;
16640
16641 /* If Rn is not part of the high-register-list, move it there. */
16642 if (!(insn_high_registers & (1 << rn)))
16643 {
16644 /* Choose a Ri in the high-register-list that will be restored. */
16645 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16646
16647 /* MOV Ri, Rn. */
16648 current_stub_contents =
16649 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16650 create_instruction_mov (ri, rn));
16651 }
16652
16653 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
16654 current_stub_contents =
16655 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16656 create_instruction_ldmia
16657 (ri, /*wback=*/1, insn_low_registers));
16658
16659 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
16660 current_stub_contents =
16661 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16662 create_instruction_ldmia
16663 (ri, /*wback=*/0, insn_high_registers));
16664
16665 if (!restore_pc)
16666 {
16667 /* B initial_insn_addr+4. */
16668 current_stub_contents =
16669 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16670 create_instruction_branch_absolute
82188b29 16671 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16672 }
16673 }
16674
16675 /* Fill the remaining of the stub with deterministic contents. */
16676 current_stub_contents =
16677 stm32l4xx_fill_stub_udf (htab, output_bfd,
16678 base_stub_contents, current_stub_contents,
16679 base_stub_contents +
16680 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16681}
16682
16683static void
16684stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
16685 bfd * output_bfd,
16686 const insn32 initial_insn,
16687 const bfd_byte *const initial_insn_addr,
16688 bfd_byte *const base_stub_contents)
16689{
16690 int wback = (initial_insn & 0x00200000) >> 21;
16691 int ri, rn = (initial_insn & 0x000f0000) >> 16;
16692 int insn_all_registers = initial_insn & 0x0000ffff;
16693 int insn_low_registers, insn_high_registers;
16694 int usable_register_mask;
16695 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16696 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16697 int nb_registers = popcount (insn_all_registers);
16698 bfd_byte *current_stub_contents = base_stub_contents;
16699
16700 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
16701
16702 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16703 smaller than 8 registers load sequences that do not cause the
16704 hardware issue. */
16705 if (nb_registers <= 8)
16706 {
16707 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16708 current_stub_contents =
16709 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16710 initial_insn);
16711
16712 /* B initial_insn_addr+4. */
16713 current_stub_contents =
16714 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16715 create_instruction_branch_absolute
82188b29 16716 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16717
16718 /* Fill the remaining of the stub with deterministic contents. */
16719 current_stub_contents =
16720 stm32l4xx_fill_stub_udf (htab, output_bfd,
16721 base_stub_contents, current_stub_contents,
16722 base_stub_contents +
16723 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16724
16725 return;
16726 }
16727
16728 /* - reg_list[13] == 0. */
16729 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
16730
16731 /* - reg_list[14] & reg_list[15] != 1. */
16732 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16733
16734 /* - if (wback==1) reg_list[rn] == 0. */
16735 BFD_ASSERT (!wback || !restore_rn);
16736
16737 /* - nb_registers > 8. */
16738 BFD_ASSERT (popcount (insn_all_registers) > 8);
16739
16740 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16741
16742 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
16743 - One with the 7 lowest registers (register mask 0x007F)
16744 This LDM will finally contain between 2 and 7 registers
16745 - One with the 7 highest registers (register mask 0xDF80)
16746 This ldm will finally contain between 2 and 7 registers. */
16747 insn_low_registers = insn_all_registers & 0x007F;
16748 insn_high_registers = insn_all_registers & 0xDF80;
16749
16750 /* A spare register may be needed during this veneer to temporarily
16751 handle the base register. This register will be restored with
16752 the last LDM operation.
16753 The usable register may be any general purpose register (that excludes
16754 PC, SP, LR : register mask is 0x1FFF). */
16755 usable_register_mask = 0x1FFF;
16756
16757 /* Generate the stub function. */
16758 if (!wback && !restore_pc && !restore_rn)
16759 {
16760 /* Choose a Ri in the low-register-list that will be restored. */
16761 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16762
16763 /* MOV Ri, Rn. */
16764 current_stub_contents =
16765 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16766 create_instruction_mov (ri, rn));
16767
16768 /* LDMDB Ri!, {R-high-register-list}. */
16769 current_stub_contents =
16770 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16771 create_instruction_ldmdb
16772 (ri, /*wback=*/1, insn_high_registers));
16773
16774 /* LDMDB Ri, {R-low-register-list}. */
16775 current_stub_contents =
16776 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16777 create_instruction_ldmdb
16778 (ri, /*wback=*/0, insn_low_registers));
16779
16780 /* B initial_insn_addr+4. */
16781 current_stub_contents =
16782 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16783 create_instruction_branch_absolute
82188b29 16784 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16785 }
16786 else if (wback && !restore_pc && !restore_rn)
16787 {
16788 /* LDMDB Rn!, {R-high-register-list}. */
16789 current_stub_contents =
16790 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16791 create_instruction_ldmdb
16792 (rn, /*wback=*/1, insn_high_registers));
16793
16794 /* LDMDB Rn!, {R-low-register-list}. */
16795 current_stub_contents =
16796 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16797 create_instruction_ldmdb
16798 (rn, /*wback=*/1, insn_low_registers));
16799
16800 /* B initial_insn_addr+4. */
16801 current_stub_contents =
16802 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16803 create_instruction_branch_absolute
82188b29 16804 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16805 }
16806 else if (!wback && restore_pc && !restore_rn)
16807 {
16808 /* Choose a Ri in the high-register-list that will be restored. */
16809 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16810
16811 /* SUB Ri, Rn, #(4*nb_registers). */
16812 current_stub_contents =
16813 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16814 create_instruction_sub (ri, rn, (4 * nb_registers)));
16815
16816 /* LDMIA Ri!, {R-low-register-list}. */
16817 current_stub_contents =
16818 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16819 create_instruction_ldmia
16820 (ri, /*wback=*/1, insn_low_registers));
16821
16822 /* LDMIA Ri, {R-high-register-list}. */
16823 current_stub_contents =
16824 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16825 create_instruction_ldmia
16826 (ri, /*wback=*/0, insn_high_registers));
16827 }
16828 else if (wback && restore_pc && !restore_rn)
16829 {
16830 /* Choose a Ri in the high-register-list that will be restored. */
16831 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16832
16833 /* SUB Rn, Rn, #(4*nb_registers) */
16834 current_stub_contents =
16835 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16836 create_instruction_sub (rn, rn, (4 * nb_registers)));
16837
16838 /* MOV Ri, Rn. */
16839 current_stub_contents =
16840 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16841 create_instruction_mov (ri, rn));
16842
16843 /* LDMIA Ri!, {R-low-register-list}. */
16844 current_stub_contents =
16845 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16846 create_instruction_ldmia
16847 (ri, /*wback=*/1, insn_low_registers));
16848
16849 /* LDMIA Ri, {R-high-register-list}. */
16850 current_stub_contents =
16851 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16852 create_instruction_ldmia
16853 (ri, /*wback=*/0, insn_high_registers));
16854 }
16855 else if (!wback && !restore_pc && restore_rn)
16856 {
16857 ri = rn;
16858 if (!(insn_low_registers & (1 << rn)))
16859 {
16860 /* Choose a Ri in the low-register-list that will be restored. */
16861 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16862
16863 /* MOV Ri, Rn. */
16864 current_stub_contents =
16865 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16866 create_instruction_mov (ri, rn));
16867 }
16868
16869 /* LDMDB Ri!, {R-high-register-list}. */
16870 current_stub_contents =
16871 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16872 create_instruction_ldmdb
16873 (ri, /*wback=*/1, insn_high_registers));
16874
16875 /* LDMDB Ri, {R-low-register-list}. */
16876 current_stub_contents =
16877 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16878 create_instruction_ldmdb
16879 (ri, /*wback=*/0, insn_low_registers));
16880
16881 /* B initial_insn_addr+4. */
16882 current_stub_contents =
16883 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16884 create_instruction_branch_absolute
82188b29 16885 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16886 }
16887 else if (!wback && restore_pc && restore_rn)
16888 {
16889 ri = rn;
16890 if (!(insn_high_registers & (1 << rn)))
16891 {
16892 /* Choose a Ri in the high-register-list that will be restored. */
16893 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16894 }
16895
16896 /* SUB Ri, Rn, #(4*nb_registers). */
16897 current_stub_contents =
16898 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16899 create_instruction_sub (ri, rn, (4 * nb_registers)));
16900
16901 /* LDMIA Ri!, {R-low-register-list}. */
16902 current_stub_contents =
16903 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16904 create_instruction_ldmia
16905 (ri, /*wback=*/1, insn_low_registers));
16906
16907 /* LDMIA Ri, {R-high-register-list}. */
16908 current_stub_contents =
16909 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16910 create_instruction_ldmia
16911 (ri, /*wback=*/0, insn_high_registers));
16912 }
16913 else if (wback && restore_rn)
16914 {
16915 /* The assembler should not have accepted to encode this. */
16916 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
16917 "undefined behavior.\n");
16918 }
16919
16920 /* Fill the remaining of the stub with deterministic contents. */
16921 current_stub_contents =
16922 stm32l4xx_fill_stub_udf (htab, output_bfd,
16923 base_stub_contents, current_stub_contents,
16924 base_stub_contents +
16925 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16926
16927}
16928
16929static void
16930stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
16931 bfd * output_bfd,
16932 const insn32 initial_insn,
16933 const bfd_byte *const initial_insn_addr,
16934 bfd_byte *const base_stub_contents)
16935{
16936 int num_regs = ((unsigned int)initial_insn << 24) >> 24;
16937 bfd_byte *current_stub_contents = base_stub_contents;
16938
16939 BFD_ASSERT (is_thumb2_vldm (initial_insn));
16940
16941 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16942 smaller than 8 registers load sequences that do not cause the
16943 hardware issue. */
16944 if (num_regs <= 8)
16945 {
16946 /* Untouched instruction. */
16947 current_stub_contents =
16948 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16949 initial_insn);
16950
16951 /* B initial_insn_addr+4. */
16952 current_stub_contents =
16953 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16954 create_instruction_branch_absolute
82188b29 16955 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16956 }
16957 else
16958 {
16959 bfd_boolean is_ia_nobang = /* (IA without !). */
16960 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
16961 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
16962 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
16963 bfd_boolean is_db_bang = /* (DB with !). */
16964 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
16965 int base_reg = ((unsigned int)initial_insn << 12) >> 28;
16966 /* d = UInt (Vd:D);. */
16967 int first_reg = ((((unsigned int)initial_insn << 16) >> 28) << 1)
16968 | (((unsigned int)initial_insn << 9) >> 31);
16969
16970 /* Compute the number of 8-register chunks needed to split. */
16971 int chunks = (num_regs%8) ? (num_regs/8 + 1) : (num_regs/8);
16972 int chunk;
16973
16974 /* The test coverage has been done assuming the following
16975 hypothesis that exactly one of the previous is_ predicates is
16976 true. */
16977 BFD_ASSERT ((is_ia_nobang ^ is_ia_bang ^ is_db_bang) &&
16978 !(is_ia_nobang & is_ia_bang & is_db_bang));
16979
16980 /* We treat the cutting of the register in one pass for all
16981 cases, then we emit the adjustments:
16982
16983 vldm rx, {...}
16984 -> vldm rx!, {8_words_or_less} for each needed 8_word
16985 -> sub rx, rx, #size (list)
16986
16987 vldm rx!, {...}
16988 -> vldm rx!, {8_words_or_less} for each needed 8_word
16989 This also handles vpop instruction (when rx is sp)
16990
16991 vldmd rx!, {...}
16992 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
16993 for (chunk = 0; chunk<chunks; ++chunk)
16994 {
16995 if (is_ia_nobang || is_ia_bang)
16996 {
16997 current_stub_contents =
16998 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16999 create_instruction_vldmia
17000 (base_reg,
17001 /*wback= . */1,
17002 chunks - (chunk + 1) ?
17003 8 : num_regs - chunk * 8,
17004 first_reg + chunk * 8));
17005 }
17006 else if (is_db_bang)
17007 {
17008 current_stub_contents =
17009 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17010 create_instruction_vldmdb
17011 (base_reg,
17012 chunks - (chunk + 1) ?
17013 8 : num_regs - chunk * 8,
17014 first_reg + chunk * 8));
17015 }
17016 }
17017
17018 /* Only this case requires the base register compensation
17019 subtract. */
17020 if (is_ia_nobang)
17021 {
17022 current_stub_contents =
17023 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17024 create_instruction_sub
17025 (base_reg, base_reg, 4*num_regs));
17026 }
17027
17028 /* B initial_insn_addr+4. */
17029 current_stub_contents =
17030 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17031 create_instruction_branch_absolute
82188b29 17032 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17033 }
17034
17035 /* Fill the remaining of the stub with deterministic contents. */
17036 current_stub_contents =
17037 stm32l4xx_fill_stub_udf (htab, output_bfd,
17038 base_stub_contents, current_stub_contents,
17039 base_stub_contents +
17040 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
17041}
17042
17043static void
17044stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
17045 bfd * output_bfd,
17046 const insn32 wrong_insn,
17047 const bfd_byte *const wrong_insn_addr,
17048 bfd_byte *const stub_contents)
17049{
17050 if (is_thumb2_ldmia (wrong_insn))
17051 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
17052 wrong_insn, wrong_insn_addr,
17053 stub_contents);
17054 else if (is_thumb2_ldmdb (wrong_insn))
17055 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
17056 wrong_insn, wrong_insn_addr,
17057 stub_contents);
17058 else if (is_thumb2_vldm (wrong_insn))
17059 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
17060 wrong_insn, wrong_insn_addr,
17061 stub_contents);
17062}
17063
17064/* End of stm32l4xx work-around. */
17065
17066
491d01d3
YU		 17067static void
17068elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
17069 asection *output_sec, Elf_Internal_Rela *rel)
17070{
17071 BFD_ASSERT (output_sec && rel);
17072 struct bfd_elf_section_reloc_data *output_reldata;
17073 struct elf32_arm_link_hash_table *htab;
17074 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
17075 Elf_Internal_Shdr *rel_hdr;
17076
17077
17078 if (oesd->rel.hdr)
17079 {
17080 rel_hdr = oesd->rel.hdr;
17081 output_reldata = &(oesd->rel);
17082 }
17083 else if (oesd->rela.hdr)
17084 {
17085 rel_hdr = oesd->rela.hdr;
17086 output_reldata = &(oesd->rela);
17087 }
17088 else
17089 {
17090 abort ();
17091 }
17092
17093 bfd_byte *erel = rel_hdr->contents;
17094 erel += output_reldata->count * rel_hdr->sh_entsize;
17095 htab = elf32_arm_hash_table (info);
17096 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
17097 output_reldata->count++;
17098}
17099
e489d0ae
PB		 17100/* Do code byteswapping. Return FALSE afterwards so that the section is
17101 written out as normal. */
17102
17103static bfd_boolean
c7b8f16e 17104elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 17105 struct bfd_link_info *link_info,
17106 asection *sec,
e489d0ae
PB		 17107 bfd_byte *contents)
17108{
48229727 17109 unsigned int mapcount, errcount;
8e3de13a 17110 _arm_elf_section_data *arm_data;
c7b8f16e 17111 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 17112 elf32_arm_section_map *map;
c7b8f16e 17113 elf32_vfp11_erratum_list *errnode;
a504d23a 17114 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 17115 bfd_vma ptr;
17116 bfd_vma end;
c7b8f16e 17117 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 17118 bfd_byte tmp;
48229727 17119 unsigned int i;
57e8b36a 17120
4dfe6ac6
NC		 17121 if (globals == NULL)
17122 return FALSE;
17123
8e3de13a
NC		 17124 /* If this section has not been allocated an _arm_elf_section_data
17125 structure then we cannot record anything. */
17126 arm_data = get_arm_elf_section_data (sec);
17127 if (arm_data == NULL)
17128 return FALSE;
17129
17130 mapcount = arm_data->mapcount;
17131 map = arm_data->map;
c7b8f16e
JB		 17132 errcount = arm_data->erratumcount;
17133
17134 if (errcount != 0)
17135 {
17136 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
17137
17138 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 17139 errnode = errnode->next)
17140 {
17141 bfd_vma target = errnode->vma - offset;
17142
17143 switch (errnode->type)
17144 {
17145 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
17146 {
17147 bfd_vma branch_to_veneer;
17148 /* Original condition code of instruction, plus bit mask for
17149 ARM B instruction. */
17150 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
17151 | 0x0a000000;
c7b8f16e
JB		 17152
17153 /* The instruction is before the label. */
91d6fa6a 17154 target -= 4;
c7b8f16e
JB		 17155
17156 /* Above offset included in -4 below. */
17157 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 17158 - errnode->vma - 4;
c7b8f16e
JB		 17159
17160 if ((signed) branch_to_veneer < -(1 << 25)
17161 || (signed) branch_to_veneer >= (1 << 25))
17162 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17163 "range"), output_bfd);
17164
99059e56
RM		 17165 insn |= (branch_to_veneer >> 2) & 0xffffff;
17166 contents[endianflip ^ target] = insn & 0xff;
17167 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17168 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17169 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17170 }
17171 break;
c7b8f16e
JB		 17172
17173 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 17174 {
17175 bfd_vma branch_from_veneer;
17176 unsigned int insn;
c7b8f16e 17177
99059e56
RM		 17178 /* Take size of veneer into account. */
17179 branch_from_veneer = errnode->u.v.branch->vma
17180 - errnode->vma - 12;
c7b8f16e
JB		 17181
17182 if ((signed) branch_from_veneer < -(1 << 25)
17183 || (signed) branch_from_veneer >= (1 << 25))
17184 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17185 "range"), output_bfd);
17186
99059e56
RM		 17187 /* Original instruction. */
17188 insn = errnode->u.v.branch->u.b.vfp_insn;
17189 contents[endianflip ^ target] = insn & 0xff;
17190 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17191 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17192 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17193
17194 /* Branch back to insn after original insn. */
17195 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
17196 contents[endianflip ^ (target + 4)] = insn & 0xff;
17197 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
17198 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
17199 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
17200 }
17201 break;
c7b8f16e 17202
99059e56
RM		 17203 default:
17204 abort ();
17205 }
17206 }
c7b8f16e 17207 }
e489d0ae 17208
a504d23a
LA		 17209 if (arm_data->stm32l4xx_erratumcount != 0)
17210 {
17211 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
17212 stm32l4xx_errnode != 0;
17213 stm32l4xx_errnode = stm32l4xx_errnode->next)
17214 {
17215 bfd_vma target = stm32l4xx_errnode->vma - offset;
17216
17217 switch (stm32l4xx_errnode->type)
17218 {
17219 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
17220 {
17221 unsigned int insn;
17222 bfd_vma branch_to_veneer =
17223 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
17224
17225 if ((signed) branch_to_veneer < -(1 << 24)
17226 || (signed) branch_to_veneer >= (1 << 24))
17227 {
17228 bfd_vma out_of_range =
17229 ((signed) branch_to_veneer < -(1 << 24)) ?
17230 - branch_to_veneer - (1 << 24) :
17231 ((signed) branch_to_veneer >= (1 << 24)) ?
17232 branch_to_veneer - (1 << 24) : 0;
17233
17234 (*_bfd_error_handler)
17235 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 17236 "Jump out of range by %ld bytes. "
a504d23a
LA		 17237 "Cannot encode branch instruction. "),
17238 output_bfd,
eee926f2 17239 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 17240 out_of_range);
17241 continue;
17242 }
17243
17244 insn = create_instruction_branch_absolute
82188b29 17245 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 17246
17247 /* The instruction is before the label. */
17248 target -= 4;
17249
17250 put_thumb2_insn (globals, output_bfd,
17251 (bfd_vma) insn, contents + target);
17252 }
17253 break;
17254
17255 case STM32L4XX_ERRATUM_VENEER:
17256 {
82188b29
NC		 17257 bfd_byte * veneer;
17258 bfd_byte * veneer_r;
a504d23a
LA		 17259 unsigned int insn;
17260
82188b29
NC		 17261 veneer = contents + target;
17262 veneer_r = veneer
17263 + stm32l4xx_errnode->u.b.veneer->vma
17264 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 17265
17266 if ((signed) (veneer_r - veneer -
17267 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17268 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17269 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17270 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
17271 || (signed) (veneer_r - veneer) >= (1 << 24))
17272 {
17273 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
17274 "veneer."), output_bfd);
17275 continue;
17276 }
17277
17278 /* Original instruction. */
17279 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
17280
17281 stm32l4xx_create_replacing_stub
17282 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
17283 }
17284 break;
17285
17286 default:
17287 abort ();
17288 }
17289 }
17290 }
17291
2468f9c9
PB		 17292 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
17293 {
17294 arm_unwind_table_edit *edit_node
99059e56 17295 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 17296 /* Now, sec->size is the size of the section we will write. The original
99059e56 17297 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 17298 markers) was sec->rawsize. (This isn't the case if we perform no
17299 edits, then rawsize will be zero and we should use size). */
21d799b5 17300 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 17301 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
17302 unsigned int in_index, out_index;
17303 bfd_vma add_to_offsets = 0;
17304
17305 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 17306 {
2468f9c9
PB		 17307 if (edit_node)
17308 {
17309 unsigned int edit_index = edit_node->index;
b38cadfb 17310
2468f9c9 17311 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 17312 {
2468f9c9
PB		 17313 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17314 contents + in_index * 8, add_to_offsets);
17315 out_index++;
17316 in_index++;
17317 }
17318 else if (in_index == edit_index
17319 || (in_index * 8 >= input_size
17320 && edit_index == UINT_MAX))
99059e56 17321 {
2468f9c9
PB		 17322 switch (edit_node->type)
17323 {
17324 case DELETE_EXIDX_ENTRY:
17325 in_index++;
17326 add_to_offsets += 8;
17327 break;
b38cadfb 17328
2468f9c9
PB		 17329 case INSERT_EXIDX_CANTUNWIND_AT_END:
17330 {
99059e56 17331 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 17332 bfd_vma text_offset = text_sec->output_section->vma
17333 + text_sec->output_offset
17334 + text_sec->size;
17335 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 17336 unsigned long prel31_offset;
2468f9c9
PB		 17337
17338 /* Note: this is meant to be equivalent to an
17339 R_ARM_PREL31 relocation. These synthetic
17340 EXIDX_CANTUNWIND markers are not relocated by the
17341 usual BFD method. */
17342 prel31_offset = (text_offset - exidx_offset)
17343 & 0x7ffffffful;
491d01d3
YU		 17344 if (bfd_link_relocatable (link_info))
17345 {
17346 /* Here relocation for new EXIDX_CANTUNWIND is
17347 created, so there is no need to
17348 adjust offset by hand. */
17349 prel31_offset = text_sec->output_offset
17350 + text_sec->size;
17351
17352 /* New relocation entity. */
17353 asection *text_out = text_sec->output_section;
17354 Elf_Internal_Rela rel;
17355 rel.r_addend = 0;
17356 rel.r_offset = exidx_offset;
17357 rel.r_info = ELF32_R_INFO (text_out->target_index,
17358 R_ARM_PREL31);
17359
17360 elf32_arm_add_relocation (output_bfd, link_info,
17361 sec->output_section,
17362 &rel);
17363 }
2468f9c9
PB		 17364
17365 /* First address we can't unwind. */
17366 bfd_put_32 (output_bfd, prel31_offset,
17367 &edited_contents[out_index * 8]);
17368
17369 /* Code for EXIDX_CANTUNWIND. */
17370 bfd_put_32 (output_bfd, 0x1,
17371 &edited_contents[out_index * 8 + 4]);
17372
17373 out_index++;
17374 add_to_offsets -= 8;
17375 }
17376 break;
17377 }
b38cadfb 17378
2468f9c9
PB		 17379 edit_node = edit_node->next;
17380 }
17381 }
17382 else
17383 {
17384 /* No more edits, copy remaining entries verbatim. */
17385 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17386 contents + in_index * 8, add_to_offsets);
17387 out_index++;
17388 in_index++;
17389 }
17390 }
17391
17392 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
17393 bfd_set_section_contents (output_bfd, sec->output_section,
17394 edited_contents,
17395 (file_ptr) sec->output_offset, sec->size);
17396
17397 return TRUE;
17398 }
17399
48229727
JB		 17400 /* Fix code to point to Cortex-A8 erratum stubs. */
17401 if (globals->fix_cortex_a8)
17402 {
17403 struct a8_branch_to_stub_data data;
17404
17405 data.writing_section = sec;
17406 data.contents = contents;
17407
a504d23a
LA		 17408 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
17409 & data);
48229727
JB		 17410 }
17411
e489d0ae
PB		 17412 if (mapcount == 0)
17413 return FALSE;
17414
c7b8f16e 17415 if (globals->byteswap_code)
e489d0ae 17416 {
c7b8f16e 17417 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 17418
c7b8f16e
JB		 17419 ptr = map[0].vma;
17420 for (i = 0; i < mapcount; i++)
99059e56
RM		 17421 {
17422 if (i == mapcount - 1)
c7b8f16e 17423 end = sec->size;
99059e56
RM		 17424 else
17425 end = map[i + 1].vma;
e489d0ae 17426
99059e56 17427 switch (map[i].type)
e489d0ae 17428 {
c7b8f16e
JB		 17429 case 'a':
17430 /* Byte swap code words. */
17431 while (ptr + 3 < end)
99059e56
RM		 17432 {
17433 tmp = contents[ptr];
17434 contents[ptr] = contents[ptr + 3];
17435 contents[ptr + 3] = tmp;
17436 tmp = contents[ptr + 1];
17437 contents[ptr + 1] = contents[ptr + 2];
17438 contents[ptr + 2] = tmp;
17439 ptr += 4;
17440 }
c7b8f16e 17441 break;
e489d0ae 17442
c7b8f16e
JB		 17443 case 't':
17444 /* Byte swap code halfwords. */
17445 while (ptr + 1 < end)
99059e56
RM		 17446 {
17447 tmp = contents[ptr];
17448 contents[ptr] = contents[ptr + 1];
17449 contents[ptr + 1] = tmp;
17450 ptr += 2;
17451 }
c7b8f16e
JB		 17452 break;
17453
17454 case 'd':
17455 /* Leave data alone. */
17456 break;
17457 }
99059e56
RM		 17458 ptr = end;
17459 }
e489d0ae 17460 }
8e3de13a 17461
93204d3a 17462 free (map);
47b2e99c 17463 arm_data->mapcount = -1;
c7b8f16e 17464 arm_data->mapsize = 0;
8e3de13a 17465 arm_data->map = NULL;
8e3de13a 17466
e489d0ae
PB		 17467 return FALSE;
17468}
17469
0beaef2b
PB		 17470/* Mangle thumb function symbols as we read them in. */
17471
8384fb8f 17472static bfd_boolean
0beaef2b
PB		 17473elf32_arm_swap_symbol_in (bfd * abfd,
17474 const void *psrc,
17475 const void *pshn,
17476 Elf_Internal_Sym *dst)
17477{
8384fb8f
AM		 17478 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
17479 return FALSE;
0beaef2b
PB		 17480
17481 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 17482 the address. */
63e1a0fc
PB		 17483 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
17484 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 17485 {
63e1a0fc
PB		 17486 if (dst->st_value & 1)
17487 {
17488 dst->st_value &= ~(bfd_vma) 1;
17489 dst->st_target_internal = ST_BRANCH_TO_THUMB;
17490 }
17491 else
17492 dst->st_target_internal = ST_BRANCH_TO_ARM;
35fc36a8
RS		 17493 }
17494 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
17495 {
17496 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
17497 dst->st_target_internal = ST_BRANCH_TO_THUMB;
0beaef2b 17498 }
35fc36a8
RS		 17499 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
17500 dst->st_target_internal = ST_BRANCH_LONG;
17501 else
63e1a0fc 17502 dst->st_target_internal = ST_BRANCH_UNKNOWN;
35fc36a8 17503
8384fb8f 17504 return TRUE;
0beaef2b
PB		 17505}
17506
17507
17508/* Mangle thumb function symbols as we write them out. */
17509
17510static void
17511elf32_arm_swap_symbol_out (bfd *abfd,
17512 const Elf_Internal_Sym *src,
17513 void *cdst,
17514 void *shndx)
17515{
17516 Elf_Internal_Sym newsym;
17517
17518 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
17519 of the address set, as per the new EABI. We do this unconditionally
17520 because objcopy does not set the elf header flags until after
17521 it writes out the symbol table. */
35fc36a8 17522 if (src->st_target_internal == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 17523 {
17524 newsym = *src;
34e77a92
RS		 17525 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
17526 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 17527 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 17528 {
17529 /* Do this only for defined symbols. At link type, the static
17530 linker will simulate the work of dynamic linker of resolving
17531 symbols and will carry over the thumbness of found symbols to
17532 the output symbol table. It's not clear how it happens, but
17533 the thumbness of undefined symbols can well be different at
17534 runtime, and writing '1' for them will be confusing for users
17535 and possibly for dynamic linker itself.
17536 */
17537 newsym.st_value |= 1;
17538 }
906e58ca 17539
0beaef2b
PB		 17540 src = &newsym;
17541 }
17542 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
17543}
17544
b294bdf8
MM		 17545/* Add the PT_ARM_EXIDX program header. */
17546
17547static bfd_boolean
906e58ca 17548elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 17549 struct bfd_link_info *info ATTRIBUTE_UNUSED)
17550{
17551 struct elf_segment_map *m;
17552 asection *sec;
17553
17554 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17555 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17556 {
17557 /* If there is already a PT_ARM_EXIDX header, then we do not
17558 want to add another one. This situation arises when running
17559 "strip"; the input binary already has the header. */
12bd6957 17560 m = elf_seg_map (abfd);
b294bdf8
MM		 17561 while (m && m->p_type != PT_ARM_EXIDX)
17562 m = m->next;
17563 if (!m)
17564 {
21d799b5 17565 m = (struct elf_segment_map *)
99059e56 17566 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 17567 if (m == NULL)
17568 return FALSE;
17569 m->p_type = PT_ARM_EXIDX;
17570 m->count = 1;
17571 m->sections[0] = sec;
17572
12bd6957
AM		 17573 m->next = elf_seg_map (abfd);
17574 elf_seg_map (abfd) = m;
b294bdf8
MM		 17575 }
17576 }
17577
17578 return TRUE;
17579}
17580
17581/* We may add a PT_ARM_EXIDX program header. */
17582
17583static int
a6b96beb
AM		 17584elf32_arm_additional_program_headers (bfd *abfd,
17585 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 17586{
17587 asection *sec;
17588
17589 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17590 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17591 return 1;
17592 else
17593 return 0;
17594}
17595
34e77a92
RS		 17596/* Hook called by the linker routine which adds symbols from an object
17597 file. */
17598
17599static bfd_boolean
17600elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
17601 Elf_Internal_Sym *sym, const char **namep,
17602 flagword *flagsp, asection **secp, bfd_vma *valp)
17603{
f1885d1e
AM		 17604 if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
17605 || ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE)
17606 && (abfd->flags & DYNAMIC) == 0
17607 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
13a2df29 17608 elf_tdata (info->output_bfd)->has_gnu_symbols = elf_gnu_symbol_any;
34e77a92 17609
c792917c
NC		 17610 if (elf32_arm_hash_table (info) == NULL)
17611 return FALSE;
17612
34e77a92
RS		 17613 if (elf32_arm_hash_table (info)->vxworks_p
17614 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
17615 flagsp, secp, valp))
17616 return FALSE;
17617
17618 return TRUE;
17619}
17620
0beaef2b 17621/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 17622const struct elf_size_info elf32_arm_size_info =
17623{
0beaef2b
PB		 17624 sizeof (Elf32_External_Ehdr),
17625 sizeof (Elf32_External_Phdr),
17626 sizeof (Elf32_External_Shdr),
17627 sizeof (Elf32_External_Rel),
17628 sizeof (Elf32_External_Rela),
17629 sizeof (Elf32_External_Sym),
17630 sizeof (Elf32_External_Dyn),
17631 sizeof (Elf_External_Note),
17632 4,
17633 1,
17634 32, 2,
17635 ELFCLASS32, EV_CURRENT,
17636 bfd_elf32_write_out_phdrs,
17637 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 17638 bfd_elf32_checksum_contents,
0beaef2b
PB		 17639 bfd_elf32_write_relocs,
17640 elf32_arm_swap_symbol_in,
17641 elf32_arm_swap_symbol_out,
17642 bfd_elf32_slurp_reloc_table,
17643 bfd_elf32_slurp_symbol_table,
17644 bfd_elf32_swap_dyn_in,
17645 bfd_elf32_swap_dyn_out,
17646 bfd_elf32_swap_reloc_in,
17647 bfd_elf32_swap_reloc_out,
17648 bfd_elf32_swap_reloca_in,
17649 bfd_elf32_swap_reloca_out
17650};
17651
685e70ae
VK		 17652static bfd_vma
17653read_code32 (const bfd *abfd, const bfd_byte *addr)
17654{
17655 /* V7 BE8 code is always little endian. */
17656 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17657 return bfd_getl32 (addr);
17658
17659 return bfd_get_32 (abfd, addr);
17660}
17661
17662static bfd_vma
17663read_code16 (const bfd *abfd, const bfd_byte *addr)
17664{
17665 /* V7 BE8 code is always little endian. */
17666 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17667 return bfd_getl16 (addr);
17668
17669 return bfd_get_16 (abfd, addr);
17670}
17671
6a631e86
YG		 17672/* Return size of plt0 entry starting at ADDR
17673 or (bfd_vma) -1 if size can not be determined. */
17674
17675static bfd_vma
17676elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
17677{
17678 bfd_vma first_word;
17679 bfd_vma plt0_size;
17680
685e70ae 17681 first_word = read_code32 (abfd, addr);
6a631e86
YG		 17682
17683 if (first_word == elf32_arm_plt0_entry[0])
17684 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
17685 else if (first_word == elf32_thumb2_plt0_entry[0])
17686 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
17687 else
17688 /* We don't yet handle this PLT format. */
17689 return (bfd_vma) -1;
17690
17691 return plt0_size;
17692}
17693
17694/* Return size of plt entry starting at offset OFFSET
17695 of plt section located at address START
17696 or (bfd_vma) -1 if size can not be determined. */
17697
17698static bfd_vma
17699elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
17700{
17701 bfd_vma first_insn;
17702 bfd_vma plt_size = 0;
17703 const bfd_byte *addr = start + offset;
17704
17705 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 17706 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 17707 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
17708
17709 /* Respect Thumb stub if necessary. */
685e70ae 17710 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 17711 {
17712 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
17713 }
17714
17715 /* Strip immediate from first add. */
685e70ae 17716 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 17717
17718#ifdef FOUR_WORD_PLT
17719 if (first_insn == elf32_arm_plt_entry[0])
17720 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
17721#else
17722 if (first_insn == elf32_arm_plt_entry_long[0])
17723 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
17724 else if (first_insn == elf32_arm_plt_entry_short[0])
17725 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
17726#endif
17727 else
17728 /* We don't yet handle this PLT format. */
17729 return (bfd_vma) -1;
17730
17731 return plt_size;
17732}
17733
17734/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
17735
17736static long
17737elf32_arm_get_synthetic_symtab (bfd *abfd,
17738 long symcount ATTRIBUTE_UNUSED,
17739 asymbol **syms ATTRIBUTE_UNUSED,
17740 long dynsymcount,
17741 asymbol **dynsyms,
17742 asymbol **ret)
17743{
17744 asection *relplt;
17745 asymbol *s;
17746 arelent *p;
17747 long count, i, n;
17748 size_t size;
17749 Elf_Internal_Shdr *hdr;
17750 char *names;
17751 asection *plt;
17752 bfd_vma offset;
17753 bfd_byte *data;
17754
17755 *ret = NULL;
17756
17757 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
17758 return 0;
17759
17760 if (dynsymcount <= 0)
17761 return 0;
17762
17763 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
17764 if (relplt == NULL)
17765 return 0;
17766
17767 hdr = &elf_section_data (relplt)->this_hdr;
17768 if (hdr->sh_link != elf_dynsymtab (abfd)
17769 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
17770 return 0;
17771
17772 plt = bfd_get_section_by_name (abfd, ".plt");
17773 if (plt == NULL)
17774 return 0;
17775
17776 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
17777 return -1;
17778
17779 data = plt->contents;
17780 if (data == NULL)
17781 {
17782 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
17783 return -1;
17784 bfd_cache_section_contents((asection *) plt, data);
17785 }
17786
17787 count = relplt->size / hdr->sh_entsize;
17788 size = count * sizeof (asymbol);
17789 p = relplt->relocation;
17790 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17791 {
17792 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
17793 if (p->addend != 0)
17794 size += sizeof ("+0x") - 1 + 8;
17795 }
17796
17797 s = *ret = (asymbol *) bfd_malloc (size);
17798 if (s == NULL)
17799 return -1;
17800
17801 offset = elf32_arm_plt0_size (abfd, data);
17802 if (offset == (bfd_vma) -1)
17803 return -1;
17804
17805 names = (char *) (s + count);
17806 p = relplt->relocation;
17807 n = 0;
17808 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17809 {
17810 size_t len;
17811
17812 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
17813 if (plt_size == (bfd_vma) -1)
17814 break;
17815
17816 *s = **p->sym_ptr_ptr;
17817 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
17818 we are defining a symbol, ensure one of them is set. */
17819 if ((s->flags & BSF_LOCAL) == 0)
17820 s->flags |= BSF_GLOBAL;
17821 s->flags |= BSF_SYNTHETIC;
17822 s->section = plt;
17823 s->value = offset;
17824 s->name = names;
17825 s->udata.p = NULL;
17826 len = strlen ((*p->sym_ptr_ptr)->name);
17827 memcpy (names, (*p->sym_ptr_ptr)->name, len);
17828 names += len;
17829 if (p->addend != 0)
17830 {
17831 char buf[30], *a;
17832
17833 memcpy (names, "+0x", sizeof ("+0x") - 1);
17834 names += sizeof ("+0x") - 1;
17835 bfd_sprintf_vma (abfd, buf, p->addend);
17836 for (a = buf; *a == '0'; ++a)
17837 ;
17838 len = strlen (a);
17839 memcpy (names, a, len);
17840 names += len;
17841 }
17842 memcpy (names, "@plt", sizeof ("@plt"));
17843 names += sizeof ("@plt");
17844 ++s, ++n;
17845 offset += plt_size;
17846 }
17847
17848 return n;
17849}
17850
ac4c9b04
MG		 17851static bfd_boolean
17852elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
17853{
17854 if (hdr->sh_flags & SHF_ARM_NOREAD)
17855 *flags |= SEC_ELF_NOREAD;
17856 return TRUE;
17857}
17858
17859static flagword
17860elf32_arm_lookup_section_flags (char *flag_name)
17861{
17862 if (!strcmp (flag_name, "SHF_ARM_NOREAD"))
17863 return SHF_ARM_NOREAD;
17864
17865 return SEC_NO_FLAGS;
17866}
17867
491d01d3
YU		 17868static unsigned int
17869elf32_arm_count_additional_relocs (asection *sec)
17870{
17871 struct _arm_elf_section_data *arm_data;
17872 arm_data = get_arm_elf_section_data (sec);
17873 return arm_data->additional_reloc_count;
17874}
17875
252b5132 17876#define ELF_ARCH bfd_arch_arm
ae95ffa6 17877#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 17878#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 17879#ifdef __QNXTARGET__
17880#define ELF_MAXPAGESIZE 0x1000
17881#else
7572ca89 17882#define ELF_MAXPAGESIZE 0x10000
d0facd1b 17883#endif
b1342370 17884#define ELF_MINPAGESIZE 0x1000
24718e3b 17885#define ELF_COMMONPAGESIZE 0x1000
252b5132 17886
ba93b8ac
DJ		 17887#define bfd_elf32_mkobject elf32_arm_mkobject
17888
99e4ae17
AJ		 17889#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
17890#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 17891#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
17892#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
17893#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 17894#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 17895#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 17896#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 17897#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 17898#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 17899#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 17900#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 17901#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 17902
17903#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
17904#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 17905#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 17906#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
17907#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 17908#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 17909#define elf_backend_write_section elf32_arm_write_section
252b5132 17910#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 17911#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 17912#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
17913#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
17914#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 17915#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 17916#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 17917#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 17918#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 17919#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 17920#define elf_backend_fake_sections elf32_arm_fake_sections
17921#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 17922#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 17923#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 17924#define elf_backend_size_info elf32_arm_size_info
b294bdf8 17925#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 17926#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
17927#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
17928#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 17929#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 17930#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
906e58ca
NC		 17931
17932#define elf_backend_can_refcount 1
17933#define elf_backend_can_gc_sections 1
17934#define elf_backend_plt_readonly 1
17935#define elf_backend_want_got_plt 1
17936#define elf_backend_want_plt_sym 0
17937#define elf_backend_may_use_rel_p 1
17938#define elf_backend_may_use_rela_p 0
4e7fd91e 17939#define elf_backend_default_use_rela_p 0
252b5132 17940
04f7c78d 17941#define elf_backend_got_header_size 12
b68a20d6 17942#define elf_backend_extern_protected_data 1
04f7c78d 17943
906e58ca
NC		 17944#undef elf_backend_obj_attrs_vendor
17945#define elf_backend_obj_attrs_vendor "aeabi"
17946#undef elf_backend_obj_attrs_section
17947#define elf_backend_obj_attrs_section ".ARM.attributes"
17948#undef elf_backend_obj_attrs_arg_type
17949#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
17950#undef elf_backend_obj_attrs_section_type
104d59d1 17951#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 17952#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
17953#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 17954
ac4c9b04
MG		 17955#undef elf_backend_section_flags
17956#define elf_backend_section_flags elf32_arm_section_flags
17957#undef elf_backend_lookup_section_flags_hook
17958#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
17959
252b5132 17960#include "elf32-target.h"
7f266840 17961
b38cadfb
NC		 17962/* Native Client targets. */
17963
17964#undef TARGET_LITTLE_SYM
6d00b590 17965#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 17966#undef TARGET_LITTLE_NAME
17967#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
17968#undef TARGET_BIG_SYM
6d00b590 17969#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 17970#undef TARGET_BIG_NAME
17971#define TARGET_BIG_NAME "elf32-bigarm-nacl"
17972
17973/* Like elf32_arm_link_hash_table_create -- but overrides
17974 appropriately for NaCl. */
17975
17976static struct bfd_link_hash_table *
17977elf32_arm_nacl_link_hash_table_create (bfd *abfd)
17978{
17979 struct bfd_link_hash_table *ret;
17980
17981 ret = elf32_arm_link_hash_table_create (abfd);
17982 if (ret)
17983 {
17984 struct elf32_arm_link_hash_table *htab
17985 = (struct elf32_arm_link_hash_table *) ret;
17986
17987 htab->nacl_p = 1;
17988
17989 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
17990 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
17991 }
17992 return ret;
17993}
17994
17995/* Since NaCl doesn't use the ARM-specific unwind format, we don't
17996 really need to use elf32_arm_modify_segment_map. But we do it
17997 anyway just to reduce gratuitous differences with the stock ARM backend. */
17998
17999static bfd_boolean
18000elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
18001{
18002 return (elf32_arm_modify_segment_map (abfd, info)
18003 && nacl_modify_segment_map (abfd, info));
18004}
18005
887badb3
RM		 18006static void
18007elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
18008{
18009 elf32_arm_final_write_processing (abfd, linker);
18010 nacl_final_write_processing (abfd, linker);
18011}
18012
6a631e86
YG		 18013static bfd_vma
18014elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
18015 const arelent *rel ATTRIBUTE_UNUSED)
18016{
18017 return plt->vma
18018 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
18019 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
18020}
887badb3 18021
b38cadfb 18022#undef elf32_bed
6a631e86 18023#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 18024#undef bfd_elf32_bfd_link_hash_table_create
18025#define bfd_elf32_bfd_link_hash_table_create \
18026 elf32_arm_nacl_link_hash_table_create
18027#undef elf_backend_plt_alignment
6a631e86 18028#define elf_backend_plt_alignment 4
b38cadfb
NC		 18029#undef elf_backend_modify_segment_map
18030#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
18031#undef elf_backend_modify_program_headers
18032#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 18033#undef elf_backend_final_write_processing
18034#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 18035#undef bfd_elf32_get_synthetic_symtab
18036#undef elf_backend_plt_sym_val
18037#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
b38cadfb 18038
887badb3
RM		 18039#undef ELF_MINPAGESIZE
18040#undef ELF_COMMONPAGESIZE
18041
b38cadfb
NC		 18042
18043#include "elf32-target.h"
18044
18045/* Reset to defaults. */
18046#undef elf_backend_plt_alignment
18047#undef elf_backend_modify_segment_map
18048#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
18049#undef elf_backend_modify_program_headers
887badb3
RM		 18050#undef elf_backend_final_write_processing
18051#define elf_backend_final_write_processing elf32_arm_final_write_processing
18052#undef ELF_MINPAGESIZE
18053#define ELF_MINPAGESIZE 0x1000
18054#undef ELF_COMMONPAGESIZE
18055#define ELF_COMMONPAGESIZE 0x1000
18056
b38cadfb 18057
906e58ca 18058/* VxWorks Targets. */
4e7fd91e 18059
906e58ca 18060#undef TARGET_LITTLE_SYM
6d00b590 18061#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 18062#undef TARGET_LITTLE_NAME
4e7fd91e 18063#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 18064#undef TARGET_BIG_SYM
6d00b590 18065#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 18066#undef TARGET_BIG_NAME
4e7fd91e
PB		 18067#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
18068
18069/* Like elf32_arm_link_hash_table_create -- but overrides
18070 appropriately for VxWorks. */
906e58ca 18071
4e7fd91e
PB		 18072static struct bfd_link_hash_table *
18073elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
18074{
18075 struct bfd_link_hash_table *ret;
18076
18077 ret = elf32_arm_link_hash_table_create (abfd);
18078 if (ret)
18079 {
18080 struct elf32_arm_link_hash_table *htab
00a97672 18081 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 18082 htab->use_rel = 0;
00a97672 18083 htab->vxworks_p = 1;
4e7fd91e
PB		 18084 }
18085 return ret;
906e58ca 18086}
4e7fd91e 18087
00a97672
RS		 18088static void
18089elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
18090{
18091 elf32_arm_final_write_processing (abfd, linker);
18092 elf_vxworks_final_write_processing (abfd, linker);
18093}
18094
906e58ca 18095#undef elf32_bed
4e7fd91e
PB		 18096#define elf32_bed elf32_arm_vxworks_bed
18097
906e58ca
NC		 18098#undef bfd_elf32_bfd_link_hash_table_create
18099#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 18100#undef elf_backend_final_write_processing
18101#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
18102#undef elf_backend_emit_relocs
18103#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 18104
906e58ca 18105#undef elf_backend_may_use_rel_p
00a97672 18106#define elf_backend_may_use_rel_p 0
906e58ca 18107#undef elf_backend_may_use_rela_p
00a97672 18108#define elf_backend_may_use_rela_p 1
906e58ca 18109#undef elf_backend_default_use_rela_p
00a97672 18110#define elf_backend_default_use_rela_p 1
906e58ca 18111#undef elf_backend_want_plt_sym
00a97672 18112#define elf_backend_want_plt_sym 1
906e58ca 18113#undef ELF_MAXPAGESIZE
00a97672 18114#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 18115
18116#include "elf32-target.h"
18117
18118
21d799b5
NC		 18119/* Merge backend specific data from an object file to the output
18120 object file when linking. */
18121
18122static bfd_boolean
18123elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
18124{
18125 flagword out_flags;
18126 flagword in_flags;
18127 bfd_boolean flags_compatible = TRUE;
18128 asection *sec;
18129
cc643b88 18130 /* Check if we have the same endianness. */
21d799b5
NC		 18131 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
18132 return FALSE;
18133
18134 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
18135 return TRUE;
18136
18137 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
18138 return FALSE;
18139
18140 /* The input BFD must have had its flags initialised. */
18141 /* The following seems bogus to me -- The flags are initialized in
18142 the assembler but I don't think an elf_flags_init field is
18143 written into the object. */
18144 /* BFD_ASSERT (elf_flags_init (ibfd)); */
18145
18146 in_flags = elf_elfheader (ibfd)->e_flags;
18147 out_flags = elf_elfheader (obfd)->e_flags;
18148
18149 /* In theory there is no reason why we couldn't handle this. However
18150 in practice it isn't even close to working and there is no real
18151 reason to want it. */
18152 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
18153 && !(ibfd->flags & DYNAMIC)
18154 && (in_flags & EF_ARM_BE8))
18155 {
18156 _bfd_error_handler (_("error: %B is already in final BE8 format"),
18157 ibfd);
18158 return FALSE;
18159 }
18160
18161 if (!elf_flags_init (obfd))
18162 {
18163 /* If the input is the default architecture and had the default
18164 flags then do not bother setting the flags for the output
18165 architecture, instead allow future merges to do this. If no
18166 future merges ever set these flags then they will retain their
99059e56
RM		 18167 uninitialised values, which surprise surprise, correspond
18168 to the default values. */
21d799b5
NC		 18169 if (bfd_get_arch_info (ibfd)->the_default
18170 && elf_elfheader (ibfd)->e_flags == 0)
18171 return TRUE;
18172
18173 elf_flags_init (obfd) = TRUE;
18174 elf_elfheader (obfd)->e_flags = in_flags;
18175
18176 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
18177 && bfd_get_arch_info (obfd)->the_default)
18178 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
18179
18180 return TRUE;
18181 }
18182
18183 /* Determine what should happen if the input ARM architecture
18184 does not match the output ARM architecture. */
18185 if (! bfd_arm_merge_machines (ibfd, obfd))
18186 return FALSE;
18187
18188 /* Identical flags must be compatible. */
18189 if (in_flags == out_flags)
18190 return TRUE;
18191
18192 /* Check to see if the input BFD actually contains any sections. If
18193 not, its flags may not have been initialised either, but it
18194 cannot actually cause any incompatiblity. Do not short-circuit
18195 dynamic objects; their section list may be emptied by
18196 elf_link_add_object_symbols.
18197
18198 Also check to see if there are no code sections in the input.
18199 In this case there is no need to check for code specific flags.
18200 XXX - do we need to worry about floating-point format compatability
18201 in data sections ? */
18202 if (!(ibfd->flags & DYNAMIC))
18203 {
18204 bfd_boolean null_input_bfd = TRUE;
18205 bfd_boolean only_data_sections = TRUE;
18206
18207 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
18208 {
18209 /* Ignore synthetic glue sections. */
18210 if (strcmp (sec->name, ".glue_7")
18211 && strcmp (sec->name, ".glue_7t"))
18212 {
18213 if ((bfd_get_section_flags (ibfd, sec)
18214 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
18215 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 18216 only_data_sections = FALSE;
21d799b5
NC		 18217
18218 null_input_bfd = FALSE;
18219 break;
18220 }
18221 }
18222
18223 if (null_input_bfd || only_data_sections)
18224 return TRUE;
18225 }
18226
18227 /* Complain about various flag mismatches. */
18228 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
18229 EF_ARM_EABI_VERSION (out_flags)))
18230 {
18231 _bfd_error_handler
18232 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
18233 ibfd, obfd,
18234 (in_flags & EF_ARM_EABIMASK) >> 24,
18235 (out_flags & EF_ARM_EABIMASK) >> 24);
18236 return FALSE;
18237 }
18238
18239 /* Not sure what needs to be checked for EABI versions >= 1. */
18240 /* VxWorks libraries do not use these flags. */
18241 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
18242 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
18243 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
18244 {
18245 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
18246 {
18247 _bfd_error_handler
18248 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
18249 ibfd, obfd,
18250 in_flags & EF_ARM_APCS_26 ? 26 : 32,
18251 out_flags & EF_ARM_APCS_26 ? 26 : 32);
18252 flags_compatible = FALSE;
18253 }
18254
18255 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
18256 {
18257 if (in_flags & EF_ARM_APCS_FLOAT)
18258 _bfd_error_handler
18259 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
18260 ibfd, obfd);
18261 else
18262 _bfd_error_handler
18263 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
18264 ibfd, obfd);
18265
18266 flags_compatible = FALSE;
18267 }
18268
18269 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
18270 {
18271 if (in_flags & EF_ARM_VFP_FLOAT)
18272 _bfd_error_handler
18273 (_("error: %B uses VFP instructions, whereas %B does not"),
18274 ibfd, obfd);
18275 else
18276 _bfd_error_handler
18277 (_("error: %B uses FPA instructions, whereas %B does not"),
18278 ibfd, obfd);
18279
18280 flags_compatible = FALSE;
18281 }
18282
18283 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
18284 {
18285 if (in_flags & EF_ARM_MAVERICK_FLOAT)
18286 _bfd_error_handler
18287 (_("error: %B uses Maverick instructions, whereas %B does not"),
18288 ibfd, obfd);
18289 else
18290 _bfd_error_handler
18291 (_("error: %B does not use Maverick instructions, whereas %B does"),
18292 ibfd, obfd);
18293
18294 flags_compatible = FALSE;
18295 }
18296
18297#ifdef EF_ARM_SOFT_FLOAT
18298 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
18299 {
18300 /* We can allow interworking between code that is VFP format
18301 layout, and uses either soft float or integer regs for
18302 passing floating point arguments and results. We already
18303 know that the APCS_FLOAT flags match; similarly for VFP
18304 flags. */
18305 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
18306 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
18307 {
18308 if (in_flags & EF_ARM_SOFT_FLOAT)
18309 _bfd_error_handler
18310 (_("error: %B uses software FP, whereas %B uses hardware FP"),
18311 ibfd, obfd);
18312 else
18313 _bfd_error_handler
18314 (_("error: %B uses hardware FP, whereas %B uses software FP"),
18315 ibfd, obfd);
18316
18317 flags_compatible = FALSE;
18318 }
18319 }
18320#endif
18321
18322 /* Interworking mismatch is only a warning. */
18323 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
18324 {
18325 if (in_flags & EF_ARM_INTERWORK)
18326 {
18327 _bfd_error_handler
18328 (_("Warning: %B supports interworking, whereas %B does not"),
18329 ibfd, obfd);
18330 }
18331 else
18332 {
18333 _bfd_error_handler
18334 (_("Warning: %B does not support interworking, whereas %B does"),
18335 ibfd, obfd);
18336 }
18337 }
18338 }
18339
18340 return flags_compatible;
18341}
18342
18343
906e58ca 18344/* Symbian OS Targets. */
7f266840 18345
906e58ca 18346#undef TARGET_LITTLE_SYM
6d00b590 18347#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 18348#undef TARGET_LITTLE_NAME
7f266840 18349#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 18350#undef TARGET_BIG_SYM
6d00b590 18351#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 18352#undef TARGET_BIG_NAME
7f266840
DJ		 18353#define TARGET_BIG_NAME "elf32-bigarm-symbian"
18354
18355/* Like elf32_arm_link_hash_table_create -- but overrides
18356 appropriately for Symbian OS. */
906e58ca 18357
7f266840
DJ		 18358static struct bfd_link_hash_table *
18359elf32_arm_symbian_link_hash_table_create (bfd *abfd)
18360{
18361 struct bfd_link_hash_table *ret;
18362
18363 ret = elf32_arm_link_hash_table_create (abfd);
18364 if (ret)
18365 {
18366 struct elf32_arm_link_hash_table *htab
18367 = (struct elf32_arm_link_hash_table *)ret;
18368 /* There is no PLT header for Symbian OS. */
18369 htab->plt_header_size = 0;
95720a86
DJ		 18370 /* The PLT entries are each one instruction and one word. */
18371 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 18372 htab->symbian_p = 1;
33bfe774
JB		 18373 /* Symbian uses armv5t or above, so use_blx is always true. */
18374 htab->use_blx = 1;
67687978 18375 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 18376 }
18377 return ret;
906e58ca 18378}
7f266840 18379
b35d266b 18380static const struct bfd_elf_special_section
551b43fd 18381elf32_arm_symbian_special_sections[] =
7f266840 18382{
5cd3778d
MM		 18383 /* In a BPABI executable, the dynamic linking sections do not go in
18384 the loadable read-only segment. The post-linker may wish to
18385 refer to these sections, but they are not part of the final
18386 program image. */
0112cd26
NC		 18387 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
18388 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
18389 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
18390 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
18391 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 18392 /* These sections do not need to be writable as the SymbianOS
18393 postlinker will arrange things so that no dynamic relocation is
18394 required. */
0112cd26
NC		 18395 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
18396 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
18397 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
18398 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 18399};
18400
c3c76620 18401static void
906e58ca 18402elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 18403 struct bfd_link_info *link_info)
c3c76620
MM		 18404{
18405 /* BPABI objects are never loaded directly by an OS kernel; they are
18406 processed by a postlinker first, into an OS-specific format. If
18407 the D_PAGED bit is set on the file, BFD will align segments on
18408 page boundaries, so that an OS can directly map the file. With
18409 BPABI objects, that just results in wasted space. In addition,
18410 because we clear the D_PAGED bit, map_sections_to_segments will
18411 recognize that the program headers should not be mapped into any
18412 loadable segment. */
18413 abfd->flags &= ~D_PAGED;
906e58ca 18414 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 18415}
7f266840
DJ		 18416
18417static bfd_boolean
906e58ca 18418elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 18419 struct bfd_link_info *info)
7f266840
DJ		 18420{
18421 struct elf_segment_map *m;
18422 asection *dynsec;
18423
7f266840
DJ		 18424 /* BPABI shared libraries and executables should have a PT_DYNAMIC
18425 segment. However, because the .dynamic section is not marked
18426 with SEC_LOAD, the generic ELF code will not create such a
18427 segment. */
18428 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
18429 if (dynsec)
18430 {
12bd6957 18431 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 18432 if (m->p_type == PT_DYNAMIC)
18433 break;
18434
18435 if (m == NULL)
18436 {
18437 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 18438 m->next = elf_seg_map (abfd);
18439 elf_seg_map (abfd) = m;
8ded5a0f 18440 }
7f266840
DJ		 18441 }
18442
b294bdf8
MM		 18443 /* Also call the generic arm routine. */
18444 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 18445}
18446
95720a86
DJ		 18447/* Return address for Ith PLT stub in section PLT, for relocation REL
18448 or (bfd_vma) -1 if it should not be included. */
18449
18450static bfd_vma
18451elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
18452 const arelent *rel ATTRIBUTE_UNUSED)
18453{
18454 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
18455}
18456
18457
8029a119 18458#undef elf32_bed
7f266840
DJ		 18459#define elf32_bed elf32_arm_symbian_bed
18460
18461/* The dynamic sections are not allocated on SymbianOS; the postlinker
18462 will process them and then discard them. */
906e58ca 18463#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 18464#define ELF_DYNAMIC_SEC_FLAGS \
18465 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
18466
00a97672 18467#undef elf_backend_emit_relocs
c3c76620 18468
906e58ca
NC		 18469#undef bfd_elf32_bfd_link_hash_table_create
18470#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
18471#undef elf_backend_special_sections
18472#define elf_backend_special_sections elf32_arm_symbian_special_sections
18473#undef elf_backend_begin_write_processing
18474#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
18475#undef elf_backend_final_write_processing
18476#define elf_backend_final_write_processing elf32_arm_final_write_processing
18477
18478#undef elf_backend_modify_segment_map
7f266840
DJ		 18479#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
18480
18481/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 18482#undef elf_backend_got_header_size
7f266840
DJ		 18483#define elf_backend_got_header_size 0
18484
18485/* Similarly, there is no .got.plt section. */
906e58ca 18486#undef elf_backend_want_got_plt
7f266840
DJ		 18487#define elf_backend_want_got_plt 0
18488
906e58ca 18489#undef elf_backend_plt_sym_val
95720a86
DJ		 18490#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
18491
906e58ca 18492#undef elf_backend_may_use_rel_p
00a97672 18493#define elf_backend_may_use_rel_p 1
906e58ca 18494#undef elf_backend_may_use_rela_p
00a97672 18495#define elf_backend_may_use_rela_p 0
906e58ca 18496#undef elf_backend_default_use_rela_p
00a97672 18497#define elf_backend_default_use_rela_p 0
906e58ca 18498#undef elf_backend_want_plt_sym
00a97672 18499#define elf_backend_want_plt_sym 0
906e58ca 18500#undef ELF_MAXPAGESIZE
00a97672 18501#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 18502
7f266840 18503#include "elf32-target.h"
GDB Binutils - Deliverables
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