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[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
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252b5132 1/* 32-bit ELF support for ARM
2571583a 2 Copyright (C) 1998-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca
NC		 3161 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3162 asection *srelplt2;
00a97672 3163
0855e32b
NS		 3164 /* The offset into splt of the PLT entry for the TLS descriptor
3165 resolver. Special values are 0, if not necessary (or not found
3166 to be necessary yet), and -1 if needed but not determined
3167 yet. */
3168 bfd_vma dt_tlsdesc_plt;
3169
3170 /* The offset into sgot of the GOT entry used by the PLT entry
3171 above. */
b38cadfb 3172 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3173
3174 /* Offset in .plt section of tls_arm_trampoline. */
3175 bfd_vma tls_trampoline;
3176
906e58ca
NC		 3177 /* Data for R_ARM_TLS_LDM32 relocations. */
3178 union
3179 {
3180 bfd_signed_vma refcount;
3181 bfd_vma offset;
3182 } tls_ldm_got;
b7693d02 3183
87d72d41
AM		 3184 /* Small local sym cache. */
3185 struct sym_cache sym_cache;
906e58ca
NC		 3186
3187 /* For convenience in allocate_dynrelocs. */
3188 bfd * obfd;
3189
0855e32b
NS		 3190 /* The amount of space used by the reserved portion of the sgotplt
3191 section, plus whatever space is used by the jump slots. */
3192 bfd_vma sgotplt_jump_table_size;
3193
906e58ca
NC		 3194 /* The stub hash table. */
3195 struct bfd_hash_table stub_hash_table;
3196
3197 /* Linker stub bfd. */
3198 bfd *stub_bfd;
3199
3200 /* Linker call-backs. */
6bde4c52
TP		 3201 asection * (*add_stub_section) (const char *, asection *, asection *,
3202 unsigned int);
906e58ca
NC		 3203 void (*layout_sections_again) (void);
3204
3205 /* Array to keep track of which stub sections have been created, and
3206 information on stub grouping. */
21d799b5 3207 struct map_stub *stub_group;
906e58ca 3208
4ba2ef8f
TP		 3209 /* Input stub section holding secure gateway veneers. */
3210 asection *cmse_stub_sec;
3211
0955507f
TP		 3212 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3213 start to be allocated. */
3214 bfd_vma new_cmse_stub_offset;
3215
fe33d2fa 3216 /* Number of elements in stub_group. */
7292b3ac 3217 unsigned int top_id;
fe33d2fa 3218
906e58ca
NC		 3219 /* Assorted information used by elf32_arm_size_stubs. */
3220 unsigned int bfd_count;
7292b3ac 3221 unsigned int top_index;
906e58ca
NC		 3222 asection **input_list;
3223};
252b5132 3224
a504d23a
LA		 3225static inline int
3226ctz (unsigned int mask)
3227{
3228#if GCC_VERSION >= 3004
3229 return __builtin_ctz (mask);
3230#else
3231 unsigned int i;
3232
3233 for (i = 0; i < 8 * sizeof (mask); i++)
3234 {
3235 if (mask & 0x1)
3236 break;
3237 mask = (mask >> 1);
3238 }
3239 return i;
3240#endif
3241}
3242
3243static inline int
b25e998d 3244elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3245{
3246#if GCC_VERSION >= 3004
3247 return __builtin_popcount (mask);
3248#else
b25e998d
CG		 3249 unsigned int i;
3250 int sum = 0;
a504d23a
LA		 3251
3252 for (i = 0; i < 8 * sizeof (mask); i++)
3253 {
3254 if (mask & 0x1)
3255 sum++;
3256 mask = (mask >> 1);
3257 }
3258 return sum;
3259#endif
3260}
3261
780a67af
NC		 3262/* Create an entry in an ARM ELF linker hash table. */
3263
3264static struct bfd_hash_entry *
57e8b36a 3265elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3266 struct bfd_hash_table * table,
3267 const char * string)
780a67af
NC		 3268{
3269 struct elf32_arm_link_hash_entry * ret =
3270 (struct elf32_arm_link_hash_entry *) entry;
3271
3272 /* Allocate the structure if it has not already been allocated by a
3273 subclass. */
906e58ca 3274 if (ret == NULL)
21d799b5 3275 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3276 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3277 if (ret == NULL)
780a67af
NC		 3278 return (struct bfd_hash_entry *) ret;
3279
3280 /* Call the allocation method of the superclass. */
3281 ret = ((struct elf32_arm_link_hash_entry *)
3282 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3283 table, string));
57e8b36a 3284 if (ret != NULL)
b7693d02 3285 {
0bdcacaf 3286 ret->dyn_relocs = NULL;
ba93b8ac 3287 ret->tls_type = GOT_UNKNOWN;
0855e32b 3288 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3289 ret->plt.thumb_refcount = 0;
3290 ret->plt.maybe_thumb_refcount = 0;
3291 ret->plt.noncall_refcount = 0;
3292 ret->plt.got_offset = -1;
3293 ret->is_iplt = FALSE;
a4fd1a8e 3294 ret->export_glue = NULL;
906e58ca
NC		 3295
3296 ret->stub_cache = NULL;
b7693d02 3297 }
780a67af
NC		 3298
3299 return (struct bfd_hash_entry *) ret;
3300}
3301
34e77a92
RS		 3302/* Ensure that we have allocated bookkeeping structures for ABFD's local
3303 symbols. */
3304
3305static bfd_boolean
3306elf32_arm_allocate_local_sym_info (bfd *abfd)
3307{
3308 if (elf_local_got_refcounts (abfd) == NULL)
3309 {
3310 bfd_size_type num_syms;
3311 bfd_size_type size;
3312 char *data;
3313
3314 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3315 size = num_syms * (sizeof (bfd_signed_vma)
3316 + sizeof (struct arm_local_iplt_info *)
3317 + sizeof (bfd_vma)
3318 + sizeof (char));
3319 data = bfd_zalloc (abfd, size);
3320 if (data == NULL)
3321 return FALSE;
3322
3323 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3324 data += num_syms * sizeof (bfd_signed_vma);
3325
3326 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3327 data += num_syms * sizeof (struct arm_local_iplt_info *);
3328
3329 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3330 data += num_syms * sizeof (bfd_vma);
3331
3332 elf32_arm_local_got_tls_type (abfd) = data;
3333 }
3334 return TRUE;
3335}
3336
3337/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3338 to input bfd ABFD. Create the information if it doesn't already exist.
3339 Return null if an allocation fails. */
3340
3341static struct arm_local_iplt_info *
3342elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3343{
3344 struct arm_local_iplt_info **ptr;
3345
3346 if (!elf32_arm_allocate_local_sym_info (abfd))
3347 return NULL;
3348
3349 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3350 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3351 if (*ptr == NULL)
3352 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3353 return *ptr;
3354}
3355
3356/* Try to obtain PLT information for the symbol with index R_SYMNDX
3357 in ABFD's symbol table. If the symbol is global, H points to its
3358 hash table entry, otherwise H is null.
3359
3360 Return true if the symbol does have PLT information. When returning
3361 true, point *ROOT_PLT at the target-independent reference count/offset
3362 union and *ARM_PLT at the ARM-specific information. */
3363
3364static bfd_boolean
4ba2ef8f
TP		 3365elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3366 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3367 unsigned long r_symndx, union gotplt_union **root_plt,
3368 struct arm_plt_info **arm_plt)
3369{
3370 struct arm_local_iplt_info *local_iplt;
3371
4ba2ef8f
TP		 3372 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3373 return FALSE;
3374
34e77a92
RS		 3375 if (h != NULL)
3376 {
3377 *root_plt = &h->root.plt;
3378 *arm_plt = &h->plt;
3379 return TRUE;
3380 }
3381
3382 if (elf32_arm_local_iplt (abfd) == NULL)
3383 return FALSE;
3384
3385 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3386 if (local_iplt == NULL)
3387 return FALSE;
3388
3389 *root_plt = &local_iplt->root;
3390 *arm_plt = &local_iplt->arm;
3391 return TRUE;
3392}
3393
3394/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3395 before it. */
3396
3397static bfd_boolean
3398elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3399 struct arm_plt_info *arm_plt)
3400{
3401 struct elf32_arm_link_hash_table *htab;
3402
3403 htab = elf32_arm_hash_table (info);
3404 return (arm_plt->thumb_refcount != 0
3405 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3406}
3407
3408/* Return a pointer to the head of the dynamic reloc list that should
3409 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3410 ABFD's symbol table. Return null if an error occurs. */
3411
3412static struct elf_dyn_relocs **
3413elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3414 Elf_Internal_Sym *isym)
3415{
3416 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3417 {
3418 struct arm_local_iplt_info *local_iplt;
3419
3420 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3421 if (local_iplt == NULL)
3422 return NULL;
3423 return &local_iplt->dyn_relocs;
3424 }
3425 else
3426 {
3427 /* Track dynamic relocs needed for local syms too.
3428 We really need local syms available to do this
3429 easily. Oh well. */
3430 asection *s;
3431 void *vpp;
3432
3433 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3434 if (s == NULL)
3435 abort ();
3436
3437 vpp = &elf_section_data (s)->local_dynrel;
3438 return (struct elf_dyn_relocs **) vpp;
3439 }
3440}
3441
906e58ca
NC		 3442/* Initialize an entry in the stub hash table. */
3443
3444static struct bfd_hash_entry *
3445stub_hash_newfunc (struct bfd_hash_entry *entry,
3446 struct bfd_hash_table *table,
3447 const char *string)
3448{
3449 /* Allocate the structure if it has not already been allocated by a
3450 subclass. */
3451 if (entry == NULL)
3452 {
21d799b5 3453 entry = (struct bfd_hash_entry *)
99059e56 3454 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3455 if (entry == NULL)
3456 return entry;
3457 }
3458
3459 /* Call the allocation method of the superclass. */
3460 entry = bfd_hash_newfunc (entry, table, string);
3461 if (entry != NULL)
3462 {
3463 struct elf32_arm_stub_hash_entry *eh;
3464
3465 /* Initialize the local fields. */
3466 eh = (struct elf32_arm_stub_hash_entry *) entry;
3467 eh->stub_sec = NULL;
0955507f 3468 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3469 eh->source_value = 0;
906e58ca
NC		 3470 eh->target_value = 0;
3471 eh->target_section = NULL;
cedfb179 3472 eh->orig_insn = 0;
906e58ca 3473 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3474 eh->stub_size = 0;
3475 eh->stub_template = NULL;
0955507f 3476 eh->stub_template_size = -1;
906e58ca
NC		 3477 eh->h = NULL;
3478 eh->id_sec = NULL;
d8d2f433 3479 eh->output_name = NULL;
906e58ca
NC		 3480 }
3481
3482 return entry;
3483}
3484
00a97672 3485/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3486 shortcuts to them in our hash table. */
3487
3488static bfd_boolean
57e8b36a 3489create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3490{
3491 struct elf32_arm_link_hash_table *htab;
3492
e5a52504 3493 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3494 if (htab == NULL)
3495 return FALSE;
3496
e5a52504
MM		 3497 /* BPABI objects never have a GOT, or associated sections. */
3498 if (htab->symbian_p)
3499 return TRUE;
3500
5e681ec4
PB		 3501 if (! _bfd_elf_create_got_section (dynobj, info))
3502 return FALSE;
3503
5e681ec4
PB		 3504 return TRUE;
3505}
3506
34e77a92
RS		 3507/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3508
3509static bfd_boolean
3510create_ifunc_sections (struct bfd_link_info *info)
3511{
3512 struct elf32_arm_link_hash_table *htab;
3513 const struct elf_backend_data *bed;
3514 bfd *dynobj;
3515 asection *s;
3516 flagword flags;
b38cadfb 3517
34e77a92
RS		 3518 htab = elf32_arm_hash_table (info);
3519 dynobj = htab->root.dynobj;
3520 bed = get_elf_backend_data (dynobj);
3521 flags = bed->dynamic_sec_flags;
3522
3523 if (htab->root.iplt == NULL)
3524 {
3d4d4302
AM		 3525 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3526 flags | SEC_READONLY | SEC_CODE);
34e77a92 3527 if (s == NULL
a0f49396 3528 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3529 return FALSE;
3530 htab->root.iplt = s;
3531 }
3532
3533 if (htab->root.irelplt == NULL)
3534 {
3d4d4302
AM		 3535 s = bfd_make_section_anyway_with_flags (dynobj,
3536 RELOC_SECTION (htab, ".iplt"),
3537 flags | SEC_READONLY);
34e77a92 3538 if (s == NULL
a0f49396 3539 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3540 return FALSE;
3541 htab->root.irelplt = s;
3542 }
3543
3544 if (htab->root.igotplt == NULL)
3545 {
3d4d4302 3546 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3547 if (s == NULL
3548 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3549 return FALSE;
3550 htab->root.igotplt = s;
3551 }
3552 return TRUE;
3553}
3554
eed94f8f
NC		 3555/* Determine if we're dealing with a Thumb only architecture. */
3556
3557static bfd_boolean
3558using_thumb_only (struct elf32_arm_link_hash_table *globals)
3559{
2fd158eb
TP		 3560 int arch;
3561 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3562 Tag_CPU_arch_profile);
eed94f8f 3563
2fd158eb
TP		 3564 if (profile)
3565 return profile == 'M';
eed94f8f 3566
2fd158eb 3567 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3568
60a019a0 3569 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3570 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0 3571
2fd158eb
TP		 3572 if (arch == TAG_CPU_ARCH_V6_M
3573 || arch == TAG_CPU_ARCH_V6S_M
3574 || arch == TAG_CPU_ARCH_V7E_M
3575 || arch == TAG_CPU_ARCH_V8M_BASE
3576 || arch == TAG_CPU_ARCH_V8M_MAIN)
3577 return TRUE;
eed94f8f 3578
2fd158eb 3579 return FALSE;
eed94f8f
NC		 3580}
3581
3582/* Determine if we're dealing with a Thumb-2 object. */
3583
3584static bfd_boolean
3585using_thumb2 (struct elf32_arm_link_hash_table *globals)
3586{
60a019a0
TP		 3587 int arch;
3588 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3589 Tag_THUMB_ISA_use);
3590
3591 if (thumb_isa)
3592 return thumb_isa == 2;
3593
3594 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3595
3596 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3597 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3598
3599 return (arch == TAG_CPU_ARCH_V6T2
3600 || arch == TAG_CPU_ARCH_V7
3601 || arch == TAG_CPU_ARCH_V7E_M
3602 || arch == TAG_CPU_ARCH_V8
bff0500d 3603 || arch == TAG_CPU_ARCH_V8R
60a019a0 3604 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3605}
3606
5e866f5a
TP		 3607/* Determine whether Thumb-2 BL instruction is available. */
3608
3609static bfd_boolean
3610using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3611{
3612 int arch =
3613 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3614
3615 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3616 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
5e866f5a
TP		 3617
3618 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3619 return (arch == TAG_CPU_ARCH_V6T2
3620 || arch >= TAG_CPU_ARCH_V7);
3621}
3622
00a97672
RS		 3623/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3624 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3625 hash table. */
3626
3627static bfd_boolean
57e8b36a 3628elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3629{
3630 struct elf32_arm_link_hash_table *htab;
3631
3632 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3633 if (htab == NULL)
3634 return FALSE;
3635
362d30a1 3636 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3637 return FALSE;
3638
3639 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3640 return FALSE;
3641
00a97672
RS		 3642 if (htab->vxworks_p)
3643 {
3644 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3645 return FALSE;
3646
0e1862bb 3647 if (bfd_link_pic (info))
00a97672
RS		 3648 {
3649 htab->plt_header_size = 0;
3650 htab->plt_entry_size
3651 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3652 }
3653 else
3654 {
3655 htab->plt_header_size
3656 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3657 htab->plt_entry_size
3658 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3659 }
aebf9be7
NC		 3660
3661 if (elf_elfheader (dynobj))
3662 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3663 }
eed94f8f
NC		 3664 else
3665 {
3666 /* PR ld/16017
3667 Test for thumb only architectures. Note - we cannot just call
3668 using_thumb_only() as the attributes in the output bfd have not been
3669 initialised at this point, so instead we use the input bfd. */
3670 bfd * saved_obfd = htab->obfd;
3671
3672 htab->obfd = dynobj;
3673 if (using_thumb_only (htab))
3674 {
3675 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3676 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3677 }
3678 htab->obfd = saved_obfd;
3679 }
5e681ec4 3680
362d30a1
RS		 3681 if (!htab->root.splt
3682 || !htab->root.srelplt
9d19e4fd
AM		 3683 || !htab->root.sdynbss
3684 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3685 abort ();
3686
3687 return TRUE;
3688}
3689
906e58ca
NC		 3690/* Copy the extra info we tack onto an elf_link_hash_entry. */
3691
3692static void
3693elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3694 struct elf_link_hash_entry *dir,
3695 struct elf_link_hash_entry *ind)
3696{
3697 struct elf32_arm_link_hash_entry *edir, *eind;
3698
3699 edir = (struct elf32_arm_link_hash_entry *) dir;
3700 eind = (struct elf32_arm_link_hash_entry *) ind;
3701
0bdcacaf 3702 if (eind->dyn_relocs != NULL)
906e58ca 3703 {
0bdcacaf 3704 if (edir->dyn_relocs != NULL)
906e58ca 3705 {
0bdcacaf
RS		 3706 struct elf_dyn_relocs **pp;
3707 struct elf_dyn_relocs *p;
906e58ca
NC		 3708
3709 /* Add reloc counts against the indirect sym to the direct sym
3710 list. Merge any entries against the same section. */
0bdcacaf 3711 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3712 {
0bdcacaf 3713 struct elf_dyn_relocs *q;
906e58ca 3714
0bdcacaf
RS		 3715 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3716 if (q->sec == p->sec)
906e58ca
NC		 3717 {
3718 q->pc_count += p->pc_count;
3719 q->count += p->count;
3720 *pp = p->next;
3721 break;
3722 }
3723 if (q == NULL)
3724 pp = &p->next;
3725 }
0bdcacaf 3726 *pp = edir->dyn_relocs;
906e58ca
NC		 3727 }
3728
0bdcacaf
RS		 3729 edir->dyn_relocs = eind->dyn_relocs;
3730 eind->dyn_relocs = NULL;
906e58ca
NC		 3731 }
3732
3733 if (ind->root.type == bfd_link_hash_indirect)
3734 {
3735 /* Copy over PLT info. */
34e77a92
RS		 3736 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3737 eind->plt.thumb_refcount = 0;
3738 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3739 eind->plt.maybe_thumb_refcount = 0;
3740 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3741 eind->plt.noncall_refcount = 0;
3742
3743 /* We should only allocate a function to .iplt once the final
3744 symbol information is known. */
3745 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3746
3747 if (dir->got.refcount <= 0)
3748 {
3749 edir->tls_type = eind->tls_type;
3750 eind->tls_type = GOT_UNKNOWN;
3751 }
3752 }
3753
3754 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3755}
3756
68faa637
AM		 3757/* Destroy an ARM elf linker hash table. */
3758
3759static void
d495ab0d 3760elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3761{
3762 struct elf32_arm_link_hash_table *ret
d495ab0d 3763 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3764
3765 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3766 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3767}
3768
906e58ca
NC		 3769/* Create an ARM elf linker hash table. */
3770
3771static struct bfd_link_hash_table *
3772elf32_arm_link_hash_table_create (bfd *abfd)
3773{
3774 struct elf32_arm_link_hash_table *ret;
3775 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3776
7bf52ea2 3777 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3778 if (ret == NULL)
3779 return NULL;
3780
3781 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3782 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3783 sizeof (struct elf32_arm_link_hash_entry),
3784 ARM_ELF_DATA))
906e58ca
NC		 3785 {
3786 free (ret);
3787 return NULL;
3788 }
3789
906e58ca 3790 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3791 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3792#ifdef FOUR_WORD_PLT
3793 ret->plt_header_size = 16;
3794 ret->plt_entry_size = 16;
3795#else
3796 ret->plt_header_size = 20;
1db37fe6 3797 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3798#endif
906e58ca 3799 ret->use_rel = 1;
906e58ca 3800 ret->obfd = abfd;
906e58ca
NC		 3801
3802 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3803 sizeof (struct elf32_arm_stub_hash_entry)))
3804 {
d495ab0d 3805 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3806 return NULL;
3807 }
d495ab0d 3808 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3809
3810 return &ret->root.root;
3811}
3812
cd1dac3d
DG		 3813/* Determine what kind of NOPs are available. */
3814
3815static bfd_boolean
3816arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3817{
3818 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3819 Tag_CPU_arch);
cd1dac3d 3820
60a019a0 3821 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3822 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3823
3824 return (arch == TAG_CPU_ARCH_V6T2
3825 || arch == TAG_CPU_ARCH_V6K
3826 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 3827 || arch == TAG_CPU_ARCH_V8
3828 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 3829}
3830
f4ac8484
DJ		 3831static bfd_boolean
3832arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3833{
3834 switch (stub_type)
3835 {
fea2b4d6 3836 case arm_stub_long_branch_thumb_only:
80c135e5 3837 case arm_stub_long_branch_thumb2_only:
d5a67c02 3838 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3839 case arm_stub_long_branch_v4t_thumb_arm:
3840 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3841 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3842 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3843 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3844 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3845 return TRUE;
3846 case arm_stub_none:
3847 BFD_FAIL ();
3848 return FALSE;
3849 break;
3850 default:
3851 return FALSE;
3852 }
3853}
3854
906e58ca
NC		 3855/* Determine the type of stub needed, if any, for a call. */
3856
3857static enum elf32_arm_stub_type
3858arm_type_of_stub (struct bfd_link_info *info,
3859 asection *input_sec,
3860 const Elf_Internal_Rela *rel,
34e77a92 3861 unsigned char st_type,
35fc36a8 3862 enum arm_st_branch_type *actual_branch_type,
906e58ca 3863 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3864 bfd_vma destination,
3865 asection *sym_sec,
3866 bfd *input_bfd,
3867 const char *name)
906e58ca
NC		 3868{
3869 bfd_vma location;
3870 bfd_signed_vma branch_offset;
3871 unsigned int r_type;
3872 struct elf32_arm_link_hash_table * globals;
5e866f5a 3873 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3874 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3875 int use_plt = 0;
35fc36a8 3876 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3877 union gotplt_union *root_plt;
3878 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3879 int arch;
3880 int thumb2_movw;
906e58ca 3881
35fc36a8 3882 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3883 return stub_type;
3884
906e58ca 3885 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3886 if (globals == NULL)
3887 return stub_type;
906e58ca
NC		 3888
3889 thumb_only = using_thumb_only (globals);
906e58ca 3890 thumb2 = using_thumb2 (globals);
5e866f5a 3891 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3892
d5a67c02
AV		 3893 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3894
3895 /* True for architectures that implement the thumb2 movw instruction. */
3896 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3897
906e58ca
NC		 3898 /* Determine where the call point is. */
3899 location = (input_sec->output_offset
3900 + input_sec->output_section->vma
3901 + rel->r_offset);
3902
906e58ca
NC		 3903 r_type = ELF32_R_TYPE (rel->r_info);
3904
39f21624
NC		 3905 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3906 are considering a function call relocation. */
c5423981
TG		 3907 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3908 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3909 && branch_type == ST_BRANCH_TO_ARM)
3910 branch_type = ST_BRANCH_TO_THUMB;
3911
34e77a92
RS		 3912 /* For TLS call relocs, it is the caller's responsibility to provide
3913 the address of the appropriate trampoline. */
3914 if (r_type != R_ARM_TLS_CALL
3915 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3916 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3917 ELF32_R_SYM (rel->r_info), &root_plt,
3918 &arm_plt)
34e77a92 3919 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3920 {
34e77a92 3921 asection *splt;
fe33d2fa 3922
34e77a92
RS		 3923 if (hash == NULL || hash->is_iplt)
3924 splt = globals->root.iplt;
3925 else
3926 splt = globals->root.splt;
3927 if (splt != NULL)
b38cadfb 3928 {
34e77a92
RS		 3929 use_plt = 1;
3930
3931 /* Note when dealing with PLT entries: the main PLT stub is in
3932 ARM mode, so if the branch is in Thumb mode, another
3933 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3934 PLT stub. If a long branch stub is needed, we'll add a
3935 Thumb->Arm one and branch directly to the ARM PLT entry.
3936 Here, we have to check if a pre-PLT Thumb->ARM stub
3937 is needed and if it will be close enough. */
34e77a92
RS		 3938
3939 destination = (splt->output_section->vma
3940 + splt->output_offset
3941 + root_plt->offset);
3942 st_type = STT_FUNC;
2df2751d
CL		 3943
3944 /* Thumb branch/call to PLT: it can become a branch to ARM
3945 or to Thumb. We must perform the same checks and
3946 corrections as in elf32_arm_final_link_relocate. */
3947 if ((r_type == R_ARM_THM_CALL)
3948 || (r_type == R_ARM_THM_JUMP24))
3949 {
3950 if (globals->use_blx
3951 && r_type == R_ARM_THM_CALL
3952 && !thumb_only)
3953 {
3954 /* If the Thumb BLX instruction is available, convert
3955 the BL to a BLX instruction to call the ARM-mode
3956 PLT entry. */
3957 branch_type = ST_BRANCH_TO_ARM;
3958 }
3959 else
3960 {
3961 if (!thumb_only)
3962 /* Target the Thumb stub before the ARM PLT entry. */
3963 destination -= PLT_THUMB_STUB_SIZE;
3964 branch_type = ST_BRANCH_TO_THUMB;
3965 }
3966 }
3967 else
3968 {
3969 branch_type = ST_BRANCH_TO_ARM;
3970 }
34e77a92 3971 }
5fa9e92f 3972 }
34e77a92
RS		 3973 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3974 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3975
fe33d2fa
CL		 3976 branch_offset = (bfd_signed_vma)(destination - location);
3977
0855e32b 3978 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3979 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3980 {
5fa9e92f
CL		 3981 /* Handle cases where:
3982 - this call goes too far (different Thumb/Thumb2 max
99059e56 3983 distance)
155d87d7 3984 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3985 Thumb->Arm branch (not bl). A stub is needed in this case,
3986 but only if this call is not through a PLT entry. Indeed,
695344c0 3987 PLT stubs handle mode switching already. */
5e866f5a 3988 if ((!thumb2_bl
906e58ca
NC		 3989 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3990 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 3991 || (thumb2_bl
906e58ca
NC		 3992 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3993 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3994 || (thumb2
3995 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3996 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3997 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3998 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3999 && (((r_type == R_ARM_THM_CALL
4000 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 4001 || (r_type == R_ARM_THM_JUMP24)
4002 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4003 && !use_plt))
906e58ca 4004 {
2df2751d
CL		 4005 /* If we need to insert a Thumb-Thumb long branch stub to a
4006 PLT, use one that branches directly to the ARM PLT
4007 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4008 stub, undo this now. */
695344c0
NC		 4009 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4010 {
4011 branch_type = ST_BRANCH_TO_ARM;
4012 branch_offset += PLT_THUMB_STUB_SIZE;
4013 }
2df2751d 4014
35fc36a8 4015 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4016 {
4017 /* Thumb to thumb. */
4018 if (!thumb_only)
4019 {
d5a67c02 4020 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4021 _bfd_error_handler
4022 (_("%B(%A): warning: long branch veneers used in"
4023 " section with SHF_ARM_PURECODE section"
4024 " attribute is only supported for M-profile"
4025 " targets that implement the movw instruction."),
4026 input_bfd, input_sec);
d5a67c02 4027
0e1862bb 4028 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4029 /* PIC stubs. */
155d87d7 4030 ? ((globals->use_blx
9553db3c 4031 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4032 /* V5T and above. Stub starts with ARM code, so
4033 we must be able to switch mode before
4034 reaching it, which is only possible for 'bl'
4035 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4036 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4037 /* On V4T, use Thumb code only. */
d3626fb0 4038 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4039
4040 /* non-PIC stubs. */
155d87d7 4041 : ((globals->use_blx
9553db3c 4042 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4043 /* V5T and above. */
4044 ? arm_stub_long_branch_any_any
4045 /* V4T. */
d3626fb0 4046 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4047 }
4048 else
4049 {
d5a67c02
AV		 4050 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4051 stub_type = arm_stub_long_branch_thumb2_only_pure;
4052 else
4053 {
4054 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4055 _bfd_error_handler
4056 (_("%B(%A): warning: long branch veneers used in"
4057 " section with SHF_ARM_PURECODE section"
4058 " attribute is only supported for M-profile"
4059 " targets that implement the movw instruction."),
4060 input_bfd, input_sec);
d5a67c02
AV		 4061
4062 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4063 /* PIC stub. */
4064 ? arm_stub_long_branch_thumb_only_pic
4065 /* non-PIC stub. */
4066 : (thumb2 ? arm_stub_long_branch_thumb2_only
4067 : arm_stub_long_branch_thumb_only);
4068 }
906e58ca
NC		 4069 }
4070 }
4071 else
4072 {
d5a67c02 4073 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4074 _bfd_error_handler
4075 (_("%B(%A): warning: long branch veneers used in"
4076 " section with SHF_ARM_PURECODE section"
4077 " attribute is only supported" " for M-profile"
4078 " targets that implement the movw instruction."),
4079 input_bfd, input_sec);
d5a67c02 4080
906e58ca 4081 /* Thumb to arm. */
c820be07
NC		 4082 if (sym_sec != NULL
4083 && sym_sec->owner != NULL
4084 && !INTERWORK_FLAG (sym_sec->owner))
4085 {
4eca0228 4086 _bfd_error_handler
c820be07
NC		 4087 (_("%B(%s): warning: interworking not enabled.\n"
4088 " first occurrence: %B: Thumb call to ARM"),
c08bb8dd 4089 sym_sec->owner, name, input_bfd);
c820be07
NC		 4090 }
4091
0855e32b 4092 stub_type =
0e1862bb 4093 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4094 /* PIC stubs. */
0855e32b 4095 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4096 /* TLS PIC stubs. */
0855e32b
NS		 4097 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4098 : arm_stub_long_branch_v4t_thumb_tls_pic)
4099 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4100 /* V5T PIC and above. */
4101 ? arm_stub_long_branch_any_arm_pic
4102 /* V4T PIC stub. */
4103 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4104
4105 /* non-PIC stubs. */
0855e32b 4106 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4107 /* V5T and above. */
4108 ? arm_stub_long_branch_any_any
4109 /* V4T. */
4110 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4111
4112 /* Handle v4t short branches. */
fea2b4d6 4113 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4114 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4115 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4116 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4117 }
4118 }
4119 }
fe33d2fa
CL		 4120 else if (r_type == R_ARM_CALL
4121 || r_type == R_ARM_JUMP24
0855e32b
NS		 4122 || r_type == R_ARM_PLT32
4123 || r_type == R_ARM_TLS_CALL)
906e58ca 4124 {
d5a67c02 4125 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4126 _bfd_error_handler
4127 (_("%B(%A): warning: long branch veneers used in"
4128 " section with SHF_ARM_PURECODE section"
4129 " attribute is only supported for M-profile"
4130 " targets that implement the movw instruction."),
4131 input_bfd, input_sec);
35fc36a8 4132 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4133 {
4134 /* Arm to thumb. */
c820be07
NC		 4135
4136 if (sym_sec != NULL
4137 && sym_sec->owner != NULL
4138 && !INTERWORK_FLAG (sym_sec->owner))
4139 {
4eca0228 4140 _bfd_error_handler
c820be07 4141 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4142 " first occurrence: %B: ARM call to Thumb"),
d42c267e 4143 sym_sec->owner, name, input_bfd);
c820be07
NC		 4144 }
4145
4146 /* We have an extra 2-bytes reach because of
4147 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4148 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4149 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4150 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4151 || (r_type == R_ARM_JUMP24)
4152 || (r_type == R_ARM_PLT32))
906e58ca 4153 {
0e1862bb 4154 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4155 /* PIC stubs. */
ebe24dd4
CL		 4156 ? ((globals->use_blx)
4157 /* V5T and above. */
4158 ? arm_stub_long_branch_any_thumb_pic
4159 /* V4T stub. */
4160 : arm_stub_long_branch_v4t_arm_thumb_pic)
4161
c2b4a39d
CL		 4162 /* non-PIC stubs. */
4163 : ((globals->use_blx)
4164 /* V5T and above. */
4165 ? arm_stub_long_branch_any_any
4166 /* V4T. */
4167 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4168 }
4169 }
4170 else
4171 {
4172 /* Arm to arm. */
4173 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4174 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4175 {
0855e32b 4176 stub_type =
0e1862bb 4177 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4178 /* PIC stubs. */
0855e32b 4179 ? (r_type == R_ARM_TLS_CALL
6a631e86 4180 /* TLS PIC Stub. */
0855e32b 4181 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4182 : (globals->nacl_p
4183 ? arm_stub_long_branch_arm_nacl_pic
4184 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4185 /* non-PIC stubs. */
7a89b94e
NC		 4186 : (globals->nacl_p
4187 ? arm_stub_long_branch_arm_nacl
4188 : arm_stub_long_branch_any_any);
906e58ca
NC		 4189 }
4190 }
4191 }
4192
fe33d2fa
CL		 4193 /* If a stub is needed, record the actual destination type. */
4194 if (stub_type != arm_stub_none)
35fc36a8 4195 *actual_branch_type = branch_type;
fe33d2fa 4196
906e58ca
NC		 4197 return stub_type;
4198}
4199
4200/* Build a name for an entry in the stub hash table. */
4201
4202static char *
4203elf32_arm_stub_name (const asection *input_section,
4204 const asection *sym_sec,
4205 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4206 const Elf_Internal_Rela *rel,
4207 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4208{
4209 char *stub_name;
4210 bfd_size_type len;
4211
4212 if (hash)
4213 {
fe33d2fa 4214 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4215 stub_name = (char *) bfd_malloc (len);
906e58ca 4216 if (stub_name != NULL)
fe33d2fa 4217 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4218 input_section->id & 0xffffffff,
4219 hash->root.root.root.string,
fe33d2fa
CL		 4220 (int) rel->r_addend & 0xffffffff,
4221 (int) stub_type);
906e58ca
NC		 4222 }
4223 else
4224 {
fe33d2fa 4225 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4226 stub_name = (char *) bfd_malloc (len);
906e58ca 4227 if (stub_name != NULL)
fe33d2fa 4228 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4229 input_section->id & 0xffffffff,
4230 sym_sec->id & 0xffffffff,
0855e32b
NS		 4231 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4232 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4233 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4234 (int) rel->r_addend & 0xffffffff,
4235 (int) stub_type);
906e58ca
NC		 4236 }
4237
4238 return stub_name;
4239}
4240
4241/* Look up an entry in the stub hash. Stub entries are cached because
4242 creating the stub name takes a bit of time. */
4243
4244static struct elf32_arm_stub_hash_entry *
4245elf32_arm_get_stub_entry (const asection *input_section,
4246 const asection *sym_sec,
4247 struct elf_link_hash_entry *hash,
4248 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4249 struct elf32_arm_link_hash_table *htab,
4250 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4251{
4252 struct elf32_arm_stub_hash_entry *stub_entry;
4253 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4254 const asection *id_sec;
4255
4256 if ((input_section->flags & SEC_CODE) == 0)
4257 return NULL;
4258
4259 /* If this input section is part of a group of sections sharing one
4260 stub section, then use the id of the first section in the group.
4261 Stub names need to include a section id, as there may well be
4262 more than one stub used to reach say, printf, and we need to
4263 distinguish between them. */
c2abbbeb 4264 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4265 id_sec = htab->stub_group[input_section->id].link_sec;
4266
4267 if (h != NULL && h->stub_cache != NULL
4268 && h->stub_cache->h == h
fe33d2fa
CL		 4269 && h->stub_cache->id_sec == id_sec
4270 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4271 {
4272 stub_entry = h->stub_cache;
4273 }
4274 else
4275 {
4276 char *stub_name;
4277
fe33d2fa 4278 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4279 if (stub_name == NULL)
4280 return NULL;
4281
4282 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4283 stub_name, FALSE, FALSE);
4284 if (h != NULL)
4285 h->stub_cache = stub_entry;
4286
4287 free (stub_name);
4288 }
4289
4290 return stub_entry;
4291}
4292
daa4adae
TP		 4293/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4294 section. */
4295
4296static bfd_boolean
4297arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4298{
4299 if (stub_type >= max_stub_type)
4300 abort (); /* Should be unreachable. */
4301
4ba2ef8f
TP		 4302 switch (stub_type)
4303 {
4304 case arm_stub_cmse_branch_thumb_only:
4305 return TRUE;
4306
4307 default:
4308 return FALSE;
4309 }
4310
4311 abort (); /* Should be unreachable. */
daa4adae
TP		 4312}
4313
4314/* Required alignment (as a power of 2) for the dedicated section holding
4315 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4316 with input sections. */
4317
4318static int
4319arm_dedicated_stub_output_section_required_alignment
4320 (enum elf32_arm_stub_type stub_type)
4321{
4322 if (stub_type >= max_stub_type)
4323 abort (); /* Should be unreachable. */
4324
4ba2ef8f
TP		 4325 switch (stub_type)
4326 {
4327 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4328 boundary. */
4329 case arm_stub_cmse_branch_thumb_only:
4330 return 5;
4331
4332 default:
4333 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4334 return 0;
4335 }
4336
4337 abort (); /* Should be unreachable. */
daa4adae
TP		 4338}
4339
4340/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4341 NULL if veneers of this type are interspersed with input sections. */
4342
4343static const char *
4344arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4345{
4346 if (stub_type >= max_stub_type)
4347 abort (); /* Should be unreachable. */
4348
4ba2ef8f
TP		 4349 switch (stub_type)
4350 {
4351 case arm_stub_cmse_branch_thumb_only:
4352 return ".gnu.sgstubs";
4353
4354 default:
4355 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4356 return NULL;
4357 }
4358
4359 abort (); /* Should be unreachable. */
daa4adae
TP		 4360}
4361
4362/* If veneers of type STUB_TYPE should go in a dedicated output section,
4363 returns the address of the hash table field in HTAB holding a pointer to the
4364 corresponding input section. Otherwise, returns NULL. */
4365
4366static asection **
4ba2ef8f
TP		 4367arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4368 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4369{
4370 if (stub_type >= max_stub_type)
4371 abort (); /* Should be unreachable. */
4372
4ba2ef8f
TP		 4373 switch (stub_type)
4374 {
4375 case arm_stub_cmse_branch_thumb_only:
4376 return &htab->cmse_stub_sec;
4377
4378 default:
4379 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4380 return NULL;
4381 }
4382
4383 abort (); /* Should be unreachable. */
daa4adae
TP		 4384}
4385
4386/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4387 is the section that branch into veneer and can be NULL if stub should go in
4388 a dedicated output section. Returns a pointer to the stub section, and the
4389 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4390 LINK_SEC_P may be NULL. */
906e58ca 4391
48229727
JB		 4392static asection *
4393elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4394 struct elf32_arm_link_hash_table *htab,
4395 enum elf32_arm_stub_type stub_type)
906e58ca 4396{
daa4adae
TP		 4397 asection *link_sec, *out_sec, **stub_sec_p;
4398 const char *stub_sec_prefix;
4399 bfd_boolean dedicated_output_section =
4400 arm_dedicated_stub_output_section_required (stub_type);
4401 int align;
906e58ca 4402
daa4adae 4403 if (dedicated_output_section)
906e58ca 4404 {
daa4adae
TP		 4405 bfd *output_bfd = htab->obfd;
4406 const char *out_sec_name =
4407 arm_dedicated_stub_output_section_name (stub_type);
4408 link_sec = NULL;
4409 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4410 stub_sec_prefix = out_sec_name;
4411 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4412 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4413 if (out_sec == NULL)
906e58ca 4414 {
4eca0228
AM		 4415 _bfd_error_handler (_("No address assigned to the veneers output "
4416 "section %s"), out_sec_name);
daa4adae 4417 return NULL;
906e58ca 4418 }
daa4adae
TP		 4419 }
4420 else
4421 {
c2abbbeb 4422 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4423 link_sec = htab->stub_group[section->id].link_sec;
4424 BFD_ASSERT (link_sec != NULL);
4425 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4426 if (*stub_sec_p == NULL)
4427 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4428 stub_sec_prefix = link_sec->name;
4429 out_sec = link_sec->output_section;
4430 align = htab->nacl_p ? 4 : 3;
906e58ca 4431 }
b38cadfb 4432
daa4adae
TP		 4433 if (*stub_sec_p == NULL)
4434 {
4435 size_t namelen;
4436 bfd_size_type len;
4437 char *s_name;
4438
4439 namelen = strlen (stub_sec_prefix);
4440 len = namelen + sizeof (STUB_SUFFIX);
4441 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4442 if (s_name == NULL)
4443 return NULL;
4444
4445 memcpy (s_name, stub_sec_prefix, namelen);
4446 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4447 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4448 align);
4449 if (*stub_sec_p == NULL)
4450 return NULL;
4451
4452 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4453 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4454 | SEC_KEEP;
4455 }
4456
4457 if (!dedicated_output_section)
4458 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4459
48229727
JB		 4460 if (link_sec_p)
4461 *link_sec_p = link_sec;
b38cadfb 4462
daa4adae 4463 return *stub_sec_p;
48229727
JB		 4464}
4465
4466/* Add a new stub entry to the stub hash. Not all fields of the new
4467 stub entry are initialised. */
4468
4469static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4470elf32_arm_add_stub (const char *stub_name, asection *section,
4471 struct elf32_arm_link_hash_table *htab,
4472 enum elf32_arm_stub_type stub_type)
48229727
JB		 4473{
4474 asection *link_sec;
4475 asection *stub_sec;
4476 struct elf32_arm_stub_hash_entry *stub_entry;
4477
daa4adae
TP		 4478 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4479 stub_type);
48229727
JB		 4480 if (stub_sec == NULL)
4481 return NULL;
906e58ca
NC		 4482
4483 /* Enter this entry into the linker stub hash table. */
4484 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4485 TRUE, FALSE);
4486 if (stub_entry == NULL)
4487 {
6bde4c52
TP		 4488 if (section == NULL)
4489 section = stub_sec;
dae82561 4490 _bfd_error_handler (_("%B: cannot create stub entry %s"),
4eca0228 4491 section->owner, stub_name);
906e58ca
NC		 4492 return NULL;
4493 }
4494
4495 stub_entry->stub_sec = stub_sec;
0955507f 4496 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4497 stub_entry->id_sec = link_sec;
4498
906e58ca
NC		 4499 return stub_entry;
4500}
4501
4502/* Store an Arm insn into an output section not processed by
4503 elf32_arm_write_section. */
4504
4505static void
8029a119
NC		 4506put_arm_insn (struct elf32_arm_link_hash_table * htab,
4507 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4508{
4509 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4510 bfd_putl32 (val, ptr);
4511 else
4512 bfd_putb32 (val, ptr);
4513}
4514
4515/* Store a 16-bit Thumb insn into an output section not processed by
4516 elf32_arm_write_section. */
4517
4518static void
8029a119
NC		 4519put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4520 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4521{
4522 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4523 bfd_putl16 (val, ptr);
4524 else
4525 bfd_putb16 (val, ptr);
4526}
4527
a504d23a
LA		 4528/* Store a Thumb2 insn into an output section not processed by
4529 elf32_arm_write_section. */
4530
4531static void
4532put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4533 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4534{
4535 /* T2 instructions are 16-bit streamed. */
4536 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4537 {
4538 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4539 bfd_putl16 ((val & 0xffff), ptr + 2);
4540 }
4541 else
4542 {
4543 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4544 bfd_putb16 ((val & 0xffff), ptr + 2);
4545 }
4546}
4547
0855e32b
NS		 4548/* If it's possible to change R_TYPE to a more efficient access
4549 model, return the new reloc type. */
4550
4551static unsigned
b38cadfb 4552elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4553 struct elf_link_hash_entry *h)
4554{
4555 int is_local = (h == NULL);
4556
0e1862bb
L		 4557 if (bfd_link_pic (info)
4558 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4559 return r_type;
4560
b38cadfb 4561 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4562 switch (r_type)
4563 {
4564 case R_ARM_TLS_GOTDESC:
4565 case R_ARM_TLS_CALL:
4566 case R_ARM_THM_TLS_CALL:
4567 case R_ARM_TLS_DESCSEQ:
4568 case R_ARM_THM_TLS_DESCSEQ:
4569 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4570 }
4571
4572 return r_type;
4573}
4574
48229727
JB		 4575static bfd_reloc_status_type elf32_arm_final_link_relocate
4576 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4577 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4578 const char *, unsigned char, enum arm_st_branch_type,
4579 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4580
4563a860
JB		 4581static unsigned int
4582arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4583{
4584 switch (stub_type)
4585 {
4586 case arm_stub_a8_veneer_b_cond:
4587 case arm_stub_a8_veneer_b:
4588 case arm_stub_a8_veneer_bl:
4589 return 2;
4590
4591 case arm_stub_long_branch_any_any:
4592 case arm_stub_long_branch_v4t_arm_thumb:
4593 case arm_stub_long_branch_thumb_only:
80c135e5 4594 case arm_stub_long_branch_thumb2_only:
d5a67c02 4595 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4596 case arm_stub_long_branch_v4t_thumb_thumb:
4597 case arm_stub_long_branch_v4t_thumb_arm:
4598 case arm_stub_short_branch_v4t_thumb_arm:
4599 case arm_stub_long_branch_any_arm_pic:
4600 case arm_stub_long_branch_any_thumb_pic:
4601 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4602 case arm_stub_long_branch_v4t_arm_thumb_pic:
4603 case arm_stub_long_branch_v4t_thumb_arm_pic:
4604 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4605 case arm_stub_long_branch_any_tls_pic:
4606 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4607 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4608 case arm_stub_a8_veneer_blx:
4609 return 4;
b38cadfb 4610
7a89b94e
NC		 4611 case arm_stub_long_branch_arm_nacl:
4612 case arm_stub_long_branch_arm_nacl_pic:
4613 return 16;
4614
4563a860
JB		 4615 default:
4616 abort (); /* Should be unreachable. */
4617 }
4618}
4619
4f4faa4d
TP		 4620/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4621 veneering (TRUE) or have their own symbol (FALSE). */
4622
4623static bfd_boolean
4624arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4625{
4626 if (stub_type >= max_stub_type)
4627 abort (); /* Should be unreachable. */
4628
4ba2ef8f
TP		 4629 switch (stub_type)
4630 {
4631 case arm_stub_cmse_branch_thumb_only:
4632 return TRUE;
4633
4634 default:
4635 return FALSE;
4636 }
4637
4638 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4639}
4640
d7c5bd02
TP		 4641/* Returns the padding needed for the dedicated section used stubs of type
4642 STUB_TYPE. */
4643
4644static int
4645arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4646{
4647 if (stub_type >= max_stub_type)
4648 abort (); /* Should be unreachable. */
4649
4ba2ef8f
TP		 4650 switch (stub_type)
4651 {
4652 case arm_stub_cmse_branch_thumb_only:
4653 return 32;
4654
4655 default:
4656 return 0;
4657 }
4658
4659 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4660}
4661
0955507f
TP		 4662/* If veneers of type STUB_TYPE should go in a dedicated output section,
4663 returns the address of the hash table field in HTAB holding the offset at
4664 which new veneers should be layed out in the stub section. */
4665
4666static bfd_vma*
4667arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4668 enum elf32_arm_stub_type stub_type)
4669{
4670 switch (stub_type)
4671 {
4672 case arm_stub_cmse_branch_thumb_only:
4673 return &htab->new_cmse_stub_offset;
4674
4675 default:
4676 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4677 return NULL;
4678 }
4679}
4680
906e58ca
NC		 4681static bfd_boolean
4682arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4683 void * in_arg)
4684{
7a89b94e 4685#define MAXRELOCS 3
0955507f 4686 bfd_boolean removed_sg_veneer;
906e58ca 4687 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4688 struct elf32_arm_link_hash_table *globals;
906e58ca 4689 struct bfd_link_info *info;
906e58ca
NC		 4690 asection *stub_sec;
4691 bfd *stub_bfd;
906e58ca
NC		 4692 bfd_byte *loc;
4693 bfd_vma sym_value;
4694 int template_size;
4695 int size;
d3ce72d0 4696 const insn_sequence *template_sequence;
906e58ca 4697 int i;
48229727
JB		 4698 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4699 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4700 int nrelocs = 0;
0955507f 4701 int just_allocated = 0;
906e58ca
NC		 4702
4703 /* Massage our args to the form they really have. */
4704 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4705 info = (struct bfd_link_info *) in_arg;
4706
4707 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4708 if (globals == NULL)
4709 return FALSE;
906e58ca 4710
906e58ca
NC		 4711 stub_sec = stub_entry->stub_sec;
4712
4dfe6ac6 4713 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4714 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4715 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4716 return TRUE;
fe33d2fa 4717
0955507f
TP		 4718 /* Assign a slot at the end of section if none assigned yet. */
4719 if (stub_entry->stub_offset == (bfd_vma) -1)
4720 {
4721 stub_entry->stub_offset = stub_sec->size;
4722 just_allocated = 1;
4723 }
906e58ca
NC		 4724 loc = stub_sec->contents + stub_entry->stub_offset;
4725
4726 stub_bfd = stub_sec->owner;
4727
906e58ca
NC		 4728 /* This is the address of the stub destination. */
4729 sym_value = (stub_entry->target_value
4730 + stub_entry->target_section->output_offset
4731 + stub_entry->target_section->output_section->vma);
4732
d3ce72d0 4733 template_sequence = stub_entry->stub_template;
461a49ca 4734 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4735
4736 size = 0;
461a49ca 4737 for (i = 0; i < template_size; i++)
906e58ca 4738 {
d3ce72d0 4739 switch (template_sequence[i].type)
461a49ca
DJ		 4740 {
4741 case THUMB16_TYPE:
48229727 4742 {
d3ce72d0
NC		 4743 bfd_vma data = (bfd_vma) template_sequence[i].data;
4744 if (template_sequence[i].reloc_addend != 0)
48229727 4745 {
99059e56
RM		 4746 /* We've borrowed the reloc_addend field to mean we should
4747 insert a condition code into this (Thumb-1 branch)
4748 instruction. See THUMB16_BCOND_INSN. */
4749 BFD_ASSERT ((data & 0xff00) == 0xd000);
4750 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4751 }
fe33d2fa 4752 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4753 size += 2;
4754 }
461a49ca 4755 break;
906e58ca 4756
48229727 4757 case THUMB32_TYPE:
fe33d2fa
CL		 4758 bfd_put_16 (stub_bfd,
4759 (template_sequence[i].data >> 16) & 0xffff,
4760 loc + size);
4761 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4762 loc + size + 2);
99059e56
RM		 4763 if (template_sequence[i].r_type != R_ARM_NONE)
4764 {
4765 stub_reloc_idx[nrelocs] = i;
4766 stub_reloc_offset[nrelocs++] = size;
4767 }
4768 size += 4;
4769 break;
48229727 4770
461a49ca 4771 case ARM_TYPE:
fe33d2fa
CL		 4772 bfd_put_32 (stub_bfd, template_sequence[i].data,
4773 loc + size);
461a49ca
DJ		 4774 /* Handle cases where the target is encoded within the
4775 instruction. */
d3ce72d0 4776 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4777 {
48229727
JB		 4778 stub_reloc_idx[nrelocs] = i;
4779 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4780 }
4781 size += 4;
4782 break;
4783
4784 case DATA_TYPE:
d3ce72d0 4785 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4786 stub_reloc_idx[nrelocs] = i;
4787 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4788 size += 4;
4789 break;
4790
4791 default:
4792 BFD_FAIL ();
4793 return FALSE;
4794 }
906e58ca 4795 }
461a49ca 4796
0955507f
TP		 4797 if (just_allocated)
4798 stub_sec->size += size;
906e58ca 4799
461a49ca
DJ		 4800 /* Stub size has already been computed in arm_size_one_stub. Check
4801 consistency. */
4802 BFD_ASSERT (size == stub_entry->stub_size);
4803
906e58ca 4804 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4805 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4806 sym_value |= 1;
4807
0955507f
TP		 4808 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4809 to relocate in each stub. */
4810 removed_sg_veneer =
4811 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4812 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4813
48229727 4814 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4815 {
4816 Elf_Internal_Rela rel;
4817 bfd_boolean unresolved_reloc;
4818 char *error_message;
4819 bfd_vma points_to =
4820 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4821
4822 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4823 rel.r_info = ELF32_R_INFO (0,
4824 template_sequence[stub_reloc_idx[i]].r_type);
4825 rel.r_addend = 0;
4826
4827 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4828 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4829 template should refer back to the instruction after the original
4830 branch. We use target_section as Cortex-A8 erratum workaround stubs
4831 are only generated when both source and target are in the same
4832 section. */
4833 points_to = stub_entry->target_section->output_section->vma
4834 + stub_entry->target_section->output_offset
4835 + stub_entry->source_value;
4836
4837 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4838 (template_sequence[stub_reloc_idx[i]].r_type),
4839 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4840 points_to, info, stub_entry->target_section, "", STT_FUNC,
4841 stub_entry->branch_type,
4842 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4843 &error_message);
4844 }
906e58ca
NC		 4845
4846 return TRUE;
48229727 4847#undef MAXRELOCS
906e58ca
NC		 4848}
4849
48229727
JB		 4850/* Calculate the template, template size and instruction size for a stub.
4851 Return value is the instruction size. */
906e58ca 4852
48229727
JB		 4853static unsigned int
4854find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4855 const insn_sequence **stub_template,
4856 int *stub_template_size)
906e58ca 4857{
d3ce72d0 4858 const insn_sequence *template_sequence = NULL;
48229727
JB		 4859 int template_size = 0, i;
4860 unsigned int size;
906e58ca 4861
d3ce72d0 4862 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4863 if (stub_template)
4864 *stub_template = template_sequence;
4865
48229727 4866 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4867 if (stub_template_size)
4868 *stub_template_size = template_size;
906e58ca
NC		 4869
4870 size = 0;
461a49ca
DJ		 4871 for (i = 0; i < template_size; i++)
4872 {
d3ce72d0 4873 switch (template_sequence[i].type)
461a49ca
DJ		 4874 {
4875 case THUMB16_TYPE:
4876 size += 2;
4877 break;
4878
4879 case ARM_TYPE:
48229727 4880 case THUMB32_TYPE:
461a49ca
DJ		 4881 case DATA_TYPE:
4882 size += 4;
4883 break;
4884
4885 default:
4886 BFD_FAIL ();
2a229407 4887 return 0;
461a49ca
DJ		 4888 }
4889 }
4890
48229727
JB		 4891 return size;
4892}
4893
4894/* As above, but don't actually build the stub. Just bump offset so
4895 we know stub section sizes. */
4896
4897static bfd_boolean
4898arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4899 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4900{
4901 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4902 const insn_sequence *template_sequence;
48229727
JB		 4903 int template_size, size;
4904
4905 /* Massage our args to the form they really have. */
4906 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4907
4908 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4909 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4910
d3ce72d0 4911 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4912 &template_size);
4913
0955507f
TP		 4914 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4915 if (stub_entry->stub_template_size)
4916 {
4917 stub_entry->stub_size = size;
4918 stub_entry->stub_template = template_sequence;
4919 stub_entry->stub_template_size = template_size;
4920 }
4921
4922 /* Already accounted for. */
4923 if (stub_entry->stub_offset != (bfd_vma) -1)
4924 return TRUE;
461a49ca 4925
906e58ca
NC		 4926 size = (size + 7) & ~7;
4927 stub_entry->stub_sec->size += size;
461a49ca 4928
906e58ca
NC		 4929 return TRUE;
4930}
4931
4932/* External entry points for sizing and building linker stubs. */
4933
4934/* Set up various things so that we can make a list of input sections
4935 for each output section included in the link. Returns -1 on error,
4936 0 when no stubs will be needed, and 1 on success. */
4937
4938int
4939elf32_arm_setup_section_lists (bfd *output_bfd,
4940 struct bfd_link_info *info)
4941{
4942 bfd *input_bfd;
4943 unsigned int bfd_count;
7292b3ac 4944 unsigned int top_id, top_index;
906e58ca
NC		 4945 asection *section;
4946 asection **input_list, **list;
4947 bfd_size_type amt;
4948 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4949
4dfe6ac6
NC		 4950 if (htab == NULL)
4951 return 0;
906e58ca
NC		 4952 if (! is_elf_hash_table (htab))
4953 return 0;
4954
4955 /* Count the number of input BFDs and find the top input section id. */
4956 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4957 input_bfd != NULL;
c72f2fb2 4958 input_bfd = input_bfd->link.next)
906e58ca
NC		 4959 {
4960 bfd_count += 1;
4961 for (section = input_bfd->sections;
4962 section != NULL;
4963 section = section->next)
4964 {
4965 if (top_id < section->id)
4966 top_id = section->id;
4967 }
4968 }
4969 htab->bfd_count = bfd_count;
4970
4971 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4972 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4973 if (htab->stub_group == NULL)
4974 return -1;
fe33d2fa 4975 htab->top_id = top_id;
906e58ca
NC		 4976
4977 /* We can't use output_bfd->section_count here to find the top output
4978 section index as some sections may have been removed, and
4979 _bfd_strip_section_from_output doesn't renumber the indices. */
4980 for (section = output_bfd->sections, top_index = 0;
4981 section != NULL;
4982 section = section->next)
4983 {
4984 if (top_index < section->index)
4985 top_index = section->index;
4986 }
4987
4988 htab->top_index = top_index;
4989 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4990 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4991 htab->input_list = input_list;
4992 if (input_list == NULL)
4993 return -1;
4994
4995 /* For sections we aren't interested in, mark their entries with a
4996 value we can check later. */
4997 list = input_list + top_index;
4998 do
4999 *list = bfd_abs_section_ptr;
5000 while (list-- != input_list);
5001
5002 for (section = output_bfd->sections;
5003 section != NULL;
5004 section = section->next)
5005 {
5006 if ((section->flags & SEC_CODE) != 0)
5007 input_list[section->index] = NULL;
5008 }
5009
5010 return 1;
5011}
5012
5013/* The linker repeatedly calls this function for each input section,
5014 in the order that input sections are linked into output sections.
5015 Build lists of input sections to determine groupings between which
5016 we may insert linker stubs. */
5017
5018void
5019elf32_arm_next_input_section (struct bfd_link_info *info,
5020 asection *isec)
5021{
5022 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5023
4dfe6ac6
NC		 5024 if (htab == NULL)
5025 return;
5026
906e58ca
NC		 5027 if (isec->output_section->index <= htab->top_index)
5028 {
5029 asection **list = htab->input_list + isec->output_section->index;
5030
a7470592 5031 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5032 {
5033 /* Steal the link_sec pointer for our list. */
5034#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5035 /* This happens to make the list in reverse order,
07d72278 5036 which we reverse later. */
906e58ca
NC		 5037 PREV_SEC (isec) = *list;
5038 *list = isec;
5039 }
5040 }
5041}
5042
5043/* See whether we can group stub sections together. Grouping stub
5044 sections may result in fewer stubs. More importantly, we need to
07d72278 5045 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5046 .fini output sections respectively, because glibc splits the
5047 _init and _fini functions into multiple parts. Putting a stub in
5048 the middle of a function is not a good idea. */
5049
5050static void
5051group_sections (struct elf32_arm_link_hash_table *htab,
5052 bfd_size_type stub_group_size,
07d72278 5053 bfd_boolean stubs_always_after_branch)
906e58ca 5054{
07d72278 5055 asection **list = htab->input_list;
906e58ca
NC		 5056
5057 do
5058 {
5059 asection *tail = *list;
07d72278 5060 asection *head;
906e58ca
NC		 5061
5062 if (tail == bfd_abs_section_ptr)
5063 continue;
5064
07d72278
DJ		 5065 /* Reverse the list: we must avoid placing stubs at the
5066 beginning of the section because the beginning of the text
5067 section may be required for an interrupt vector in bare metal
5068 code. */
5069#define NEXT_SEC PREV_SEC
e780aef2
CL		 5070 head = NULL;
5071 while (tail != NULL)
99059e56
RM		 5072 {
5073 /* Pop from tail. */
5074 asection *item = tail;
5075 tail = PREV_SEC (item);
e780aef2 5076
99059e56
RM		 5077 /* Push on head. */
5078 NEXT_SEC (item) = head;
5079 head = item;
5080 }
07d72278
DJ		 5081
5082 while (head != NULL)
906e58ca
NC		 5083 {
5084 asection *curr;
07d72278 5085 asection *next;
e780aef2
CL		 5086 bfd_vma stub_group_start = head->output_offset;
5087 bfd_vma end_of_next;
906e58ca 5088
07d72278 5089 curr = head;
e780aef2 5090 while (NEXT_SEC (curr) != NULL)
8cd931b7 5091 {
e780aef2
CL		 5092 next = NEXT_SEC (curr);
5093 end_of_next = next->output_offset + next->size;
5094 if (end_of_next - stub_group_start >= stub_group_size)
5095 /* End of NEXT is too far from start, so stop. */
8cd931b7 5096 break;
e780aef2
CL		 5097 /* Add NEXT to the group. */
5098 curr = next;
8cd931b7 5099 }
906e58ca 5100
07d72278 5101 /* OK, the size from the start to the start of CURR is less
906e58ca 5102 than stub_group_size and thus can be handled by one stub
07d72278 5103 section. (Or the head section is itself larger than
906e58ca
NC		 5104 stub_group_size, in which case we may be toast.)
5105 We should really be keeping track of the total size of
5106 stubs added here, as stubs contribute to the final output
7fb9f789 5107 section size. */
906e58ca
NC		 5108 do
5109 {
07d72278 5110 next = NEXT_SEC (head);
906e58ca 5111 /* Set up this stub group. */
07d72278 5112 htab->stub_group[head->id].link_sec = curr;
906e58ca 5113 }
07d72278 5114 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5115
5116 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5117 bytes after the stub section can be handled by it too. */
5118 if (!stubs_always_after_branch)
906e58ca 5119 {
e780aef2
CL		 5120 stub_group_start = curr->output_offset + curr->size;
5121
8cd931b7 5122 while (next != NULL)
906e58ca 5123 {
e780aef2
CL		 5124 end_of_next = next->output_offset + next->size;
5125 if (end_of_next - stub_group_start >= stub_group_size)
5126 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5127 break;
e780aef2 5128 /* Add NEXT to the stub group. */
07d72278
DJ		 5129 head = next;
5130 next = NEXT_SEC (head);
5131 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5132 }
5133 }
07d72278 5134 head = next;
906e58ca
NC		 5135 }
5136 }
07d72278 5137 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5138
5139 free (htab->input_list);
5140#undef PREV_SEC
07d72278 5141#undef NEXT_SEC
906e58ca
NC		 5142}
5143
48229727
JB		 5144/* Comparison function for sorting/searching relocations relating to Cortex-A8
5145 erratum fix. */
5146
5147static int
5148a8_reloc_compare (const void *a, const void *b)
5149{
21d799b5
NC		 5150 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5151 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5152
5153 if (ra->from < rb->from)
5154 return -1;
5155 else if (ra->from > rb->from)
5156 return 1;
5157 else
5158 return 0;
5159}
5160
5161static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5162 const char *, char **);
5163
5164/* Helper function to scan code for sequences which might trigger the Cortex-A8
5165 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5166 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5167 otherwise. */
5168
81694485
NC		 5169static bfd_boolean
5170cortex_a8_erratum_scan (bfd *input_bfd,
5171 struct bfd_link_info *info,
48229727
JB		 5172 struct a8_erratum_fix **a8_fixes_p,
5173 unsigned int *num_a8_fixes_p,
5174 unsigned int *a8_fix_table_size_p,
5175 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5176 unsigned int num_a8_relocs,
5177 unsigned prev_num_a8_fixes,
5178 bfd_boolean *stub_changed_p)
48229727
JB		 5179{
5180 asection *section;
5181 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5182 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5183 unsigned int num_a8_fixes = *num_a8_fixes_p;
5184 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5185
4dfe6ac6
NC		 5186 if (htab == NULL)
5187 return FALSE;
5188
48229727
JB		 5189 for (section = input_bfd->sections;
5190 section != NULL;
5191 section = section->next)
5192 {
5193 bfd_byte *contents = NULL;
5194 struct _arm_elf_section_data *sec_data;
5195 unsigned int span;
5196 bfd_vma base_vma;
5197
5198 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5199 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5200 || (section->flags & SEC_EXCLUDE) != 0
5201 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5202 || (section->output_section == bfd_abs_section_ptr))
5203 continue;
48229727
JB		 5204
5205 base_vma = section->output_section->vma + section->output_offset;
5206
5207 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5208 contents = elf_section_data (section)->this_hdr.contents;
48229727 5209 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5210 return TRUE;
48229727
JB		 5211
5212 sec_data = elf32_arm_section_data (section);
5213
5214 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5215 {
5216 unsigned int span_start = sec_data->map[span].vma;
5217 unsigned int span_end = (span == sec_data->mapcount - 1)
5218 ? section->size : sec_data->map[span + 1].vma;
5219 unsigned int i;
5220 char span_type = sec_data->map[span].type;
5221 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5222
5223 if (span_type != 't')
5224 continue;
5225
5226 /* Span is entirely within a single 4KB region: skip scanning. */
5227 if (((base_vma + span_start) & ~0xfff)
48229727 5228 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5229 continue;
5230
5231 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5232
5233 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5234 * The branch target is in the same 4KB region as the
5235 first half of the branch.
5236 * The instruction before the branch is a 32-bit
5237 length non-branch instruction. */
5238 for (i = span_start; i < span_end;)
5239 {
5240 unsigned int insn = bfd_getl16 (&contents[i]);
5241 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5242 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5243
99059e56
RM		 5244 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5245 insn_32bit = TRUE;
48229727
JB		 5246
5247 if (insn_32bit)
99059e56
RM		 5248 {
5249 /* Load the rest of the insn (in manual-friendly order). */
5250 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5251
5252 /* Encoding T4: B<c>.W. */
5253 is_b = (insn & 0xf800d000) == 0xf0009000;
5254 /* Encoding T1: BL<c>.W. */
5255 is_bl = (insn & 0xf800d000) == 0xf000d000;
5256 /* Encoding T2: BLX<c>.W. */
5257 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5258 /* Encoding T3: B<c>.W (not permitted in IT block). */
5259 is_bcc = (insn & 0xf800d000) == 0xf0008000
5260 && (insn & 0x07f00000) != 0x03800000;
5261 }
5262
5263 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5264
99059e56 5265 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5266 && insn_32bit
5267 && is_32bit_branch
5268 && last_was_32bit
5269 && ! last_was_branch)
99059e56
RM		 5270 {
5271 bfd_signed_vma offset = 0;
5272 bfd_boolean force_target_arm = FALSE;
48229727 5273 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5274 bfd_vma target;
5275 enum elf32_arm_stub_type stub_type = arm_stub_none;
5276 struct a8_erratum_reloc key, *found;
5277 bfd_boolean use_plt = FALSE;
48229727 5278
99059e56
RM		 5279 key.from = base_vma + i;
5280 found = (struct a8_erratum_reloc *)
5281 bsearch (&key, a8_relocs, num_a8_relocs,
5282 sizeof (struct a8_erratum_reloc),
5283 &a8_reloc_compare);
48229727
JB		 5284
5285 if (found)
5286 {
5287 char *error_message = NULL;
5288 struct elf_link_hash_entry *entry;
5289
5290 /* We don't care about the error returned from this
99059e56 5291 function, only if there is glue or not. */
48229727
JB		 5292 entry = find_thumb_glue (info, found->sym_name,
5293 &error_message);
5294
5295 if (entry)
5296 found->non_a8_stub = TRUE;
5297
92750f34 5298 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5299 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5300 && found->hash->root.plt.offset != (bfd_vma) -1)
5301 use_plt = TRUE;
5302
5303 if (found->r_type == R_ARM_THM_CALL)
5304 {
35fc36a8
RS		 5305 if (found->branch_type == ST_BRANCH_TO_ARM
5306 || use_plt)
92750f34
DJ		 5307 force_target_arm = TRUE;
5308 else
5309 force_target_thumb = TRUE;
5310 }
48229727
JB		 5311 }
5312
99059e56 5313 /* Check if we have an offending branch instruction. */
48229727
JB		 5314
5315 if (found && found->non_a8_stub)
5316 /* We've already made a stub for this instruction, e.g.
5317 it's a long branch or a Thumb->ARM stub. Assume that
5318 stub will suffice to work around the A8 erratum (see
5319 setting of always_after_branch above). */
5320 ;
99059e56
RM		 5321 else if (is_bcc)
5322 {
5323 offset = (insn & 0x7ff) << 1;
5324 offset |= (insn & 0x3f0000) >> 4;
5325 offset |= (insn & 0x2000) ? 0x40000 : 0;
5326 offset |= (insn & 0x800) ? 0x80000 : 0;
5327 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5328 if (offset & 0x100000)
5329 offset |= ~ ((bfd_signed_vma) 0xfffff);
5330 stub_type = arm_stub_a8_veneer_b_cond;
5331 }
5332 else if (is_b || is_bl || is_blx)
5333 {
5334 int s = (insn & 0x4000000) != 0;
5335 int j1 = (insn & 0x2000) != 0;
5336 int j2 = (insn & 0x800) != 0;
5337 int i1 = !(j1 ^ s);
5338 int i2 = !(j2 ^ s);
5339
5340 offset = (insn & 0x7ff) << 1;
5341 offset |= (insn & 0x3ff0000) >> 4;
5342 offset |= i2 << 22;
5343 offset |= i1 << 23;
5344 offset |= s << 24;
5345 if (offset & 0x1000000)
5346 offset |= ~ ((bfd_signed_vma) 0xffffff);
5347
5348 if (is_blx)
5349 offset &= ~ ((bfd_signed_vma) 3);
5350
5351 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5352 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5353 }
5354
5355 if (stub_type != arm_stub_none)
5356 {
5357 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5358
5359 /* The original instruction is a BL, but the target is
99059e56 5360 an ARM instruction. If we were not making a stub,
48229727
JB		 5361 the BL would have been converted to a BLX. Use the
5362 BLX stub instead in that case. */
5363 if (htab->use_blx && force_target_arm
5364 && stub_type == arm_stub_a8_veneer_bl)
5365 {
5366 stub_type = arm_stub_a8_veneer_blx;
5367 is_blx = TRUE;
5368 is_bl = FALSE;
5369 }
5370 /* Conversely, if the original instruction was
5371 BLX but the target is Thumb mode, use the BL
5372 stub. */
5373 else if (force_target_thumb
5374 && stub_type == arm_stub_a8_veneer_blx)
5375 {
5376 stub_type = arm_stub_a8_veneer_bl;
5377 is_blx = FALSE;
5378 is_bl = TRUE;
5379 }
5380
99059e56
RM		 5381 if (is_blx)
5382 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5383
99059e56
RM		 5384 /* If we found a relocation, use the proper destination,
5385 not the offset in the (unrelocated) instruction.
48229727
JB		 5386 Note this is always done if we switched the stub type
5387 above. */
99059e56
RM		 5388 if (found)
5389 offset =
81694485 5390 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5391
99059e56
RM		 5392 /* If the stub will use a Thumb-mode branch to a
5393 PLT target, redirect it to the preceding Thumb
5394 entry point. */
5395 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5396 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5397
99059e56 5398 target = pc_for_insn + offset;
48229727 5399
99059e56
RM		 5400 /* The BLX stub is ARM-mode code. Adjust the offset to
5401 take the different PC value (+8 instead of +4) into
48229727 5402 account. */
99059e56
RM		 5403 if (stub_type == arm_stub_a8_veneer_blx)
5404 offset += 4;
5405
5406 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5407 {
5408 char *stub_name = NULL;
5409
5410 if (num_a8_fixes == a8_fix_table_size)
5411 {
5412 a8_fix_table_size *= 2;
5413 a8_fixes = (struct a8_erratum_fix *)
5414 bfd_realloc (a8_fixes,
5415 sizeof (struct a8_erratum_fix)
5416 * a8_fix_table_size);
5417 }
48229727 5418
eb7c4339
NS		 5419 if (num_a8_fixes < prev_num_a8_fixes)
5420 {
5421 /* If we're doing a subsequent scan,
5422 check if we've found the same fix as
5423 before, and try and reuse the stub
5424 name. */
5425 stub_name = a8_fixes[num_a8_fixes].stub_name;
5426 if ((a8_fixes[num_a8_fixes].section != section)
5427 || (a8_fixes[num_a8_fixes].offset != i))
5428 {
5429 free (stub_name);
5430 stub_name = NULL;
5431 *stub_changed_p = TRUE;
5432 }
5433 }
5434
5435 if (!stub_name)
5436 {
21d799b5 5437 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5438 if (stub_name != NULL)
5439 sprintf (stub_name, "%x:%x", section->id, i);
5440 }
48229727 5441
99059e56
RM		 5442 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5443 a8_fixes[num_a8_fixes].section = section;
5444 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5445 a8_fixes[num_a8_fixes].target_offset =
5446 target - base_vma;
99059e56
RM		 5447 a8_fixes[num_a8_fixes].orig_insn = insn;
5448 a8_fixes[num_a8_fixes].stub_name = stub_name;
5449 a8_fixes[num_a8_fixes].stub_type = stub_type;
5450 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5451 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5452
99059e56
RM		 5453 num_a8_fixes++;
5454 }
5455 }
5456 }
48229727 5457
99059e56
RM		 5458 i += insn_32bit ? 4 : 2;
5459 last_was_32bit = insn_32bit;
48229727 5460 last_was_branch = is_32bit_branch;
99059e56
RM		 5461 }
5462 }
48229727
JB		 5463
5464 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5465 free (contents);
48229727 5466 }
fe33d2fa 5467
48229727
JB		 5468 *a8_fixes_p = a8_fixes;
5469 *num_a8_fixes_p = num_a8_fixes;
5470 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5471
81694485 5472 return FALSE;
48229727
JB		 5473}
5474
b715f643
TP		 5475/* Create or update a stub entry depending on whether the stub can already be
5476 found in HTAB. The stub is identified by:
5477 - its type STUB_TYPE
5478 - its source branch (note that several can share the same stub) whose
5479 section and relocation (if any) are given by SECTION and IRELA
5480 respectively
5481 - its target symbol whose input section, hash, name, value and branch type
5482 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5483 respectively
5484
5485 If found, the value of the stub's target symbol is updated from SYM_VALUE
5486 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5487 TRUE and the stub entry is initialized.
5488
0955507f
TP		 5489 Returns the stub that was created or updated, or NULL if an error
5490 occurred. */
b715f643 5491
0955507f 5492static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5493elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5494 enum elf32_arm_stub_type stub_type, asection *section,
5495 Elf_Internal_Rela *irela, asection *sym_sec,
5496 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5497 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5498 bfd_boolean *new_stub)
5499{
5500 const asection *id_sec;
5501 char *stub_name;
5502 struct elf32_arm_stub_hash_entry *stub_entry;
5503 unsigned int r_type;
4f4faa4d 5504 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5505
5506 BFD_ASSERT (stub_type != arm_stub_none);
5507 *new_stub = FALSE;
5508
4f4faa4d
TP		 5509 if (sym_claimed)
5510 stub_name = sym_name;
5511 else
5512 {
5513 BFD_ASSERT (irela);
5514 BFD_ASSERT (section);
c2abbbeb 5515 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5516
4f4faa4d
TP		 5517 /* Support for grouping stub sections. */
5518 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5519
4f4faa4d
TP		 5520 /* Get the name of this stub. */
5521 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5522 stub_type);
5523 if (!stub_name)
0955507f 5524 return NULL;
4f4faa4d 5525 }
b715f643
TP		 5526
5527 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5528 FALSE);
5529 /* The proper stub has already been created, just update its value. */
5530 if (stub_entry != NULL)
5531 {
4f4faa4d
TP		 5532 if (!sym_claimed)
5533 free (stub_name);
b715f643 5534 stub_entry->target_value = sym_value;
0955507f 5535 return stub_entry;
b715f643
TP		 5536 }
5537
daa4adae 5538 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5539 if (stub_entry == NULL)
5540 {
4f4faa4d
TP		 5541 if (!sym_claimed)
5542 free (stub_name);
0955507f 5543 return NULL;
b715f643
TP		 5544 }
5545
5546 stub_entry->target_value = sym_value;
5547 stub_entry->target_section = sym_sec;
5548 stub_entry->stub_type = stub_type;
5549 stub_entry->h = hash;
5550 stub_entry->branch_type = branch_type;
5551
4f4faa4d
TP		 5552 if (sym_claimed)
5553 stub_entry->output_name = sym_name;
5554 else
b715f643 5555 {
4f4faa4d
TP		 5556 if (sym_name == NULL)
5557 sym_name = "unnamed";
5558 stub_entry->output_name = (char *)
5559 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5560 + strlen (sym_name));
5561 if (stub_entry->output_name == NULL)
5562 {
5563 free (stub_name);
0955507f 5564 return NULL;
4f4faa4d 5565 }
b715f643 5566
4f4faa4d
TP		 5567 /* For historical reasons, use the existing names for ARM-to-Thumb and
5568 Thumb-to-ARM stubs. */
5569 r_type = ELF32_R_TYPE (irela->r_info);
5570 if ((r_type == (unsigned int) R_ARM_THM_CALL
5571 || r_type == (unsigned int) R_ARM_THM_JUMP24
5572 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5573 && branch_type == ST_BRANCH_TO_ARM)
5574 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5575 else if ((r_type == (unsigned int) R_ARM_CALL
5576 || r_type == (unsigned int) R_ARM_JUMP24)
5577 && branch_type == ST_BRANCH_TO_THUMB)
5578 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5579 else
5580 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5581 }
b715f643
TP		 5582
5583 *new_stub = TRUE;
0955507f 5584 return stub_entry;
b715f643
TP		 5585}
5586
4ba2ef8f
TP		 5587/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5588 gateway veneer to transition from non secure to secure state and create them
5589 accordingly.
5590
5591 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5592 defines the conditions that govern Secure Gateway veneer creation for a
5593 given symbol <SYM> as follows:
5594 - it has function type
5595 - it has non local binding
5596 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5597 same type, binding and value as <SYM> (called normal symbol).
5598 An entry function can handle secure state transition itself in which case
5599 its special symbol would have a different value from the normal symbol.
5600
5601 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5602 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5603 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5604 created.
4ba2ef8f 5605
0955507f 5606 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5607
5608static bfd_boolean
5609cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5610 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5611 int *cmse_stub_created)
4ba2ef8f
TP		 5612{
5613 const struct elf_backend_data *bed;
5614 Elf_Internal_Shdr *symtab_hdr;
5615 unsigned i, j, sym_count, ext_start;
5616 Elf_Internal_Sym *cmse_sym, *local_syms;
5617 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5618 enum arm_st_branch_type branch_type;
5619 char *sym_name, *lsym_name;
5620 bfd_vma sym_value;
5621 asection *section;
0955507f
TP		 5622 struct elf32_arm_stub_hash_entry *stub_entry;
5623 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5624
5625 bed = get_elf_backend_data (input_bfd);
5626 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5627 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5628 ext_start = symtab_hdr->sh_info;
5629 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5630 && out_attr[Tag_CPU_arch_profile].i == 'M');
5631
5632 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5633 if (local_syms == NULL)
5634 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5635 symtab_hdr->sh_info, 0, NULL, NULL,
5636 NULL);
5637 if (symtab_hdr->sh_info && local_syms == NULL)
5638 return FALSE;
5639
5640 /* Scan symbols. */
5641 for (i = 0; i < sym_count; i++)
5642 {
5643 cmse_invalid = FALSE;
5644
5645 if (i < ext_start)
5646 {
5647 cmse_sym = &local_syms[i];
5648 /* Not a special symbol. */
5649 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5650 continue;
5651 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5652 symtab_hdr->sh_link,
5653 cmse_sym->st_name);
5654 /* Special symbol with local binding. */
5655 cmse_invalid = TRUE;
5656 }
5657 else
5658 {
5659 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5660 sym_name = (char *) cmse_hash->root.root.root.string;
5661
5662 /* Not a special symbol. */
5663 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5664 continue;
5665
5666 /* Special symbol has incorrect binding or type. */
5667 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5668 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5669 || cmse_hash->root.type != STT_FUNC)
5670 cmse_invalid = TRUE;
5671 }
5672
5673 if (!is_v8m)
5674 {
4eca0228
AM		 5675 _bfd_error_handler (_("%B: Special symbol `%s' only allowed for "
5676 "ARMv8-M architecture or later."),
5677 input_bfd, sym_name);
4ba2ef8f
TP		 5678 is_v8m = TRUE; /* Avoid multiple warning. */
5679 ret = FALSE;
5680 }
5681
5682 if (cmse_invalid)
5683 {
4eca0228
AM		 5684 _bfd_error_handler (_("%B: invalid special symbol `%s'."),
5685 input_bfd, sym_name);
5686 _bfd_error_handler (_("It must be a global or weak function "
5687 "symbol."));
4ba2ef8f
TP		 5688 ret = FALSE;
5689 if (i < ext_start)
5690 continue;
5691 }
5692
5693 sym_name += strlen (CMSE_PREFIX);
5694 hash = (struct elf32_arm_link_hash_entry *)
5695 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5696
5697 /* No associated normal symbol or it is neither global nor weak. */
5698 if (!hash
5699 || (hash->root.root.type != bfd_link_hash_defined
5700 && hash->root.root.type != bfd_link_hash_defweak)
5701 || hash->root.type != STT_FUNC)
5702 {
5703 /* Initialize here to avoid warning about use of possibly
5704 uninitialized variable. */
5705 j = 0;
5706
5707 if (!hash)
5708 {
5709 /* Searching for a normal symbol with local binding. */
5710 for (; j < ext_start; j++)
5711 {
5712 lsym_name =
5713 bfd_elf_string_from_elf_section (input_bfd,
5714 symtab_hdr->sh_link,
5715 local_syms[j].st_name);
5716 if (!strcmp (sym_name, lsym_name))
5717 break;
5718 }
5719 }
5720
5721 if (hash || j < ext_start)
5722 {
4eca0228 5723 _bfd_error_handler
4ba2ef8f 5724 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
4eca0228 5725 _bfd_error_handler
4ba2ef8f
TP		 5726 (_("It must be a global or weak function symbol."));
5727 }
5728 else
4eca0228 5729 _bfd_error_handler
4ba2ef8f
TP		 5730 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5731 ret = FALSE;
5732 if (!hash)
5733 continue;
5734 }
5735
5736 sym_value = hash->root.root.u.def.value;
5737 section = hash->root.root.u.def.section;
5738
5739 if (cmse_hash->root.root.u.def.section != section)
5740 {
4eca0228 5741 _bfd_error_handler
4ba2ef8f
TP		 5742 (_("%B: `%s' and its special symbol are in different sections."),
5743 input_bfd, sym_name);
5744 ret = FALSE;
5745 }
5746 if (cmse_hash->root.root.u.def.value != sym_value)
5747 continue; /* Ignore: could be an entry function starting with SG. */
5748
5749 /* If this section is a link-once section that will be discarded, then
5750 don't create any stubs. */
5751 if (section->output_section == NULL)
5752 {
4eca0228 5753 _bfd_error_handler
4ba2ef8f
TP		 5754 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5755 continue;
5756 }
5757
5758 if (hash->root.size == 0)
5759 {
4eca0228 5760 _bfd_error_handler
4ba2ef8f
TP		 5761 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5762 ret = FALSE;
5763 }
5764
5765 if (!ret)
5766 continue;
5767 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5768 stub_entry
4ba2ef8f
TP		 5769 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5770 NULL, NULL, section, hash, sym_name,
5771 sym_value, branch_type, &new_stub);
5772
0955507f 5773 if (stub_entry == NULL)
4ba2ef8f
TP		 5774 ret = FALSE;
5775 else
5776 {
5777 BFD_ASSERT (new_stub);
0955507f 5778 (*cmse_stub_created)++;
4ba2ef8f
TP		 5779 }
5780 }
5781
5782 if (!symtab_hdr->contents)
5783 free (local_syms);
5784 return ret;
5785}
5786
0955507f
TP		 5787/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5788 code entry function, ie can be called from non secure code without using a
5789 veneer. */
5790
5791static bfd_boolean
5792cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5793{
42484486 5794 bfd_byte contents[4];
0955507f
TP		 5795 uint32_t first_insn;
5796 asection *section;
5797 file_ptr offset;
5798 bfd *abfd;
5799
5800 /* Defined symbol of function type. */
5801 if (hash->root.root.type != bfd_link_hash_defined
5802 && hash->root.root.type != bfd_link_hash_defweak)
5803 return FALSE;
5804 if (hash->root.type != STT_FUNC)
5805 return FALSE;
5806
5807 /* Read first instruction. */
5808 section = hash->root.root.u.def.section;
5809 abfd = section->owner;
5810 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5811 if (!bfd_get_section_contents (abfd, section, contents, offset,
5812 sizeof (contents)))
0955507f
TP		 5813 return FALSE;
5814
42484486
TP		 5815 first_insn = bfd_get_32 (abfd, contents);
5816
5817 /* Starts by SG instruction. */
0955507f
TP		 5818 return first_insn == 0xe97fe97f;
5819}
5820
5821/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5822 secure gateway veneers (ie. the veneers was not in the input import library)
5823 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5824
5825static bfd_boolean
5826arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5827{
5828 struct elf32_arm_stub_hash_entry *stub_entry;
5829 struct bfd_link_info *info;
5830
5831 /* Massage our args to the form they really have. */
5832 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5833 info = (struct bfd_link_info *) gen_info;
5834
5835 if (info->out_implib_bfd)
5836 return TRUE;
5837
5838 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5839 return TRUE;
5840
5841 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5842 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5843
5844 return TRUE;
5845}
5846
5847/* Set offset of each secure gateway veneers so that its address remain
5848 identical to the one in the input import library referred by
5849 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5850 (present in input import library but absent from the executable being
5851 linked) or if new veneers appeared and there is no output import library
5852 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5853 number of secure gateway veneers found in the input import library.
5854
5855 The function returns whether an error occurred. If no error occurred,
5856 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5857 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5858 veneer observed set for new veneers to be layed out after. */
5859
5860static bfd_boolean
5861set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5862 struct elf32_arm_link_hash_table *htab,
5863 int *cmse_stub_created)
5864{
5865 long symsize;
5866 char *sym_name;
5867 flagword flags;
5868 long i, symcount;
5869 bfd *in_implib_bfd;
5870 asection *stub_out_sec;
5871 bfd_boolean ret = TRUE;
5872 Elf_Internal_Sym *intsym;
5873 const char *out_sec_name;
5874 bfd_size_type cmse_stub_size;
5875 asymbol **sympp = NULL, *sym;
5876 struct elf32_arm_link_hash_entry *hash;
5877 const insn_sequence *cmse_stub_template;
5878 struct elf32_arm_stub_hash_entry *stub_entry;
5879 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5880 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5881 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5882
5883 /* No input secure gateway import library. */
5884 if (!htab->in_implib_bfd)
5885 return TRUE;
5886
5887 in_implib_bfd = htab->in_implib_bfd;
5888 if (!htab->cmse_implib)
5889 {
4eca0228
AM		 5890 _bfd_error_handler (_("%B: --in-implib only supported for Secure "
5891 "Gateway import libraries."), in_implib_bfd);
0955507f
TP		 5892 return FALSE;
5893 }
5894
5895 /* Get symbol table size. */
5896 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5897 if (symsize < 0)
5898 return FALSE;
5899
5900 /* Read in the input secure gateway import library's symbol table. */
5901 sympp = (asymbol **) xmalloc (symsize);
5902 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5903 if (symcount < 0)
5904 {
5905 ret = FALSE;
5906 goto free_sym_buf;
5907 }
5908
5909 htab->new_cmse_stub_offset = 0;
5910 cmse_stub_size =
5911 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5912 &cmse_stub_template,
5913 &cmse_stub_template_size);
5914 out_sec_name =
5915 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5916 stub_out_sec =
5917 bfd_get_section_by_name (htab->obfd, out_sec_name);
5918 if (stub_out_sec != NULL)
5919 cmse_stub_sec_vma = stub_out_sec->vma;
5920
5921 /* Set addresses of veneers mentionned in input secure gateway import
5922 library's symbol table. */
5923 for (i = 0; i < symcount; i++)
5924 {
5925 sym = sympp[i];
5926 flags = sym->flags;
5927 sym_name = (char *) bfd_asymbol_name (sym);
5928 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5929
5930 if (sym->section != bfd_abs_section_ptr
5931 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5932 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5933 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5934 != ST_BRANCH_TO_THUMB))
5935 {
4eca0228
AM		 5936 _bfd_error_handler (_("%B: invalid import library entry: `%s'."),
5937 in_implib_bfd, sym_name);
5938 _bfd_error_handler (_("Symbol should be absolute, global and "
5939 "refer to Thumb functions."));
0955507f
TP		 5940 ret = FALSE;
5941 continue;
5942 }
5943
5944 veneer_value = bfd_asymbol_value (sym);
5945 stub_offset = veneer_value - cmse_stub_sec_vma;
5946 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5947 FALSE, FALSE);
5948 hash = (struct elf32_arm_link_hash_entry *)
5949 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5950
5951 /* Stub entry should have been created by cmse_scan or the symbol be of
5952 a secure function callable from non secure code. */
5953 if (!stub_entry && !hash)
5954 {
5955 bfd_boolean new_stub;
5956
4eca0228 5957 _bfd_error_handler
0955507f
TP		 5958 (_("Entry function `%s' disappeared from secure code."), sym_name);
5959 hash = (struct elf32_arm_link_hash_entry *)
5960 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5961 stub_entry
5962 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5963 NULL, NULL, bfd_abs_section_ptr, hash,
5964 sym_name, veneer_value,
5965 ST_BRANCH_TO_THUMB, &new_stub);
5966 if (stub_entry == NULL)
5967 ret = FALSE;
5968 else
5969 {
5970 BFD_ASSERT (new_stub);
5971 new_cmse_stubs_created++;
5972 (*cmse_stub_created)++;
5973 }
5974 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5975 stub_entry->stub_offset = stub_offset;
5976 }
5977 /* Symbol found is not callable from non secure code. */
5978 else if (!stub_entry)
5979 {
5980 if (!cmse_entry_fct_p (hash))
5981 {
4eca0228
AM		 5982 _bfd_error_handler (_("`%s' refers to a non entry function."),
5983 sym_name);
0955507f
TP		 5984 ret = FALSE;
5985 }
5986 continue;
5987 }
5988 else
5989 {
5990 /* Only stubs for SG veneers should have been created. */
5991 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5992
5993 /* Check visibility hasn't changed. */
5994 if (!!(flags & BSF_GLOBAL)
5995 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 5996 _bfd_error_handler
0955507f
TP		 5997 (_("%B: visibility of symbol `%s' has changed."), in_implib_bfd,
5998 sym_name);
5999
6000 stub_entry->stub_offset = stub_offset;
6001 }
6002
6003 /* Size should match that of a SG veneer. */
6004 if (intsym->st_size != cmse_stub_size)
6005 {
4eca0228
AM		 6006 _bfd_error_handler (_("%B: incorrect size for symbol `%s'."),
6007 in_implib_bfd, sym_name);
0955507f
TP		 6008 ret = FALSE;
6009 }
6010
6011 /* Previous veneer address is before current SG veneer section. */
6012 if (veneer_value < cmse_stub_sec_vma)
6013 {
6014 /* Avoid offset underflow. */
6015 if (stub_entry)
6016 stub_entry->stub_offset = 0;
6017 stub_offset = 0;
6018 ret = FALSE;
6019 }
6020
6021 /* Complain if stub offset not a multiple of stub size. */
6022 if (stub_offset % cmse_stub_size)
6023 {
4eca0228 6024 _bfd_error_handler
0955507f
TP		 6025 (_("Offset of veneer for entry function `%s' not a multiple of "
6026 "its size."), sym_name);
6027 ret = FALSE;
6028 }
6029
6030 if (!ret)
6031 continue;
6032
6033 new_cmse_stubs_created--;
6034 if (veneer_value < cmse_stub_array_start)
6035 cmse_stub_array_start = veneer_value;
6036 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6037 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6038 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6039 }
6040
6041 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6042 {
6043 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6044 _bfd_error_handler
0955507f
TP		 6045 (_("new entry function(s) introduced but no output import library "
6046 "specified:"));
6047 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6048 }
6049
6050 if (cmse_stub_array_start != cmse_stub_sec_vma)
6051 {
4eca0228 6052 _bfd_error_handler
0955507f
TP		 6053 (_("Start address of `%s' is different from previous link."),
6054 out_sec_name);
6055 ret = FALSE;
6056 }
6057
6058free_sym_buf:
6059 free (sympp);
6060 return ret;
6061}
6062
906e58ca
NC		 6063/* Determine and set the size of the stub section for a final link.
6064
6065 The basic idea here is to examine all the relocations looking for
6066 PC-relative calls to a target that is unreachable with a "bl"
6067 instruction. */
6068
6069bfd_boolean
6070elf32_arm_size_stubs (bfd *output_bfd,
6071 bfd *stub_bfd,
6072 struct bfd_link_info *info,
6073 bfd_signed_vma group_size,
7a89b94e 6074 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6075 asection *,
7a89b94e 6076 unsigned int),
906e58ca
NC		 6077 void (*layout_sections_again) (void))
6078{
0955507f 6079 bfd_boolean ret = TRUE;
4ba2ef8f 6080 obj_attribute *out_attr;
0955507f 6081 int cmse_stub_created = 0;
906e58ca 6082 bfd_size_type stub_group_size;
4ba2ef8f 6083 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6084 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6085 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6086 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6087 struct a8_erratum_reloc *a8_relocs = NULL;
6088 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6089
4dfe6ac6
NC		 6090 if (htab == NULL)
6091 return FALSE;
6092
48229727
JB		 6093 if (htab->fix_cortex_a8)
6094 {
21d799b5 6095 a8_fixes = (struct a8_erratum_fix *)
99059e56 6096 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6097 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6098 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6099 }
906e58ca
NC		 6100
6101 /* Propagate mach to stub bfd, because it may not have been
6102 finalized when we created stub_bfd. */
6103 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6104 bfd_get_mach (output_bfd));
6105
6106 /* Stash our params away. */
6107 htab->stub_bfd = stub_bfd;
6108 htab->add_stub_section = add_stub_section;
6109 htab->layout_sections_again = layout_sections_again;
07d72278 6110 stubs_always_after_branch = group_size < 0;
48229727 6111
4ba2ef8f
TP		 6112 out_attr = elf_known_obj_attributes_proc (output_bfd);
6113 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6114
48229727
JB		 6115 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6116 as the first half of a 32-bit branch straddling two 4K pages. This is a
6117 crude way of enforcing that. */
6118 if (htab->fix_cortex_a8)
6119 stubs_always_after_branch = 1;
6120
906e58ca
NC		 6121 if (group_size < 0)
6122 stub_group_size = -group_size;
6123 else
6124 stub_group_size = group_size;
6125
6126 if (stub_group_size == 1)
6127 {
6128 /* Default values. */
6129 /* Thumb branch range is +-4MB has to be used as the default
6130 maximum size (a given section can contain both ARM and Thumb
6131 code, so the worst case has to be taken into account).
6132
6133 This value is 24K less than that, which allows for 2025
6134 12-byte stubs. If we exceed that, then we will fail to link.
6135 The user will have to relink with an explicit group size
6136 option. */
6137 stub_group_size = 4170000;
6138 }
6139
07d72278 6140 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6141
3ae046cc
NS		 6142 /* If we're applying the cortex A8 fix, we need to determine the
6143 program header size now, because we cannot change it later --
6144 that could alter section placements. Notice the A8 erratum fix
6145 ends up requiring the section addresses to remain unchanged
6146 modulo the page size. That's something we cannot represent
6147 inside BFD, and we don't want to force the section alignment to
6148 be the page size. */
6149 if (htab->fix_cortex_a8)
6150 (*htab->layout_sections_again) ();
6151
906e58ca
NC		 6152 while (1)
6153 {
6154 bfd *input_bfd;
6155 unsigned int bfd_indx;
6156 asection *stub_sec;
d7c5bd02 6157 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6158 bfd_boolean stub_changed = FALSE;
6159 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6160
48229727 6161 num_a8_fixes = 0;
906e58ca
NC		 6162 for (input_bfd = info->input_bfds, bfd_indx = 0;
6163 input_bfd != NULL;
c72f2fb2 6164 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6165 {
6166 Elf_Internal_Shdr *symtab_hdr;
6167 asection *section;
6168 Elf_Internal_Sym *local_syms = NULL;
6169
99059e56
RM		 6170 if (!is_arm_elf (input_bfd))
6171 continue;
adbcc655 6172
48229727
JB		 6173 num_a8_relocs = 0;
6174
906e58ca
NC		 6175 /* We'll need the symbol table in a second. */
6176 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6177 if (symtab_hdr->sh_info == 0)
6178 continue;
6179
4ba2ef8f
TP		 6180 /* Limit scan of symbols to object file whose profile is
6181 Microcontroller to not hinder performance in the general case. */
6182 if (m_profile && first_veneer_scan)
6183 {
6184 struct elf_link_hash_entry **sym_hashes;
6185
6186 sym_hashes = elf_sym_hashes (input_bfd);
6187 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6188 &cmse_stub_created))
4ba2ef8f 6189 goto error_ret_free_local;
0955507f
TP		 6190
6191 if (cmse_stub_created != 0)
6192 stub_changed = TRUE;
4ba2ef8f
TP		 6193 }
6194
906e58ca
NC		 6195 /* Walk over each section attached to the input bfd. */
6196 for (section = input_bfd->sections;
6197 section != NULL;
6198 section = section->next)
6199 {
6200 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6201
6202 /* If there aren't any relocs, then there's nothing more
6203 to do. */
6204 if ((section->flags & SEC_RELOC) == 0
6205 || section->reloc_count == 0
6206 || (section->flags & SEC_CODE) == 0)
6207 continue;
6208
6209 /* If this section is a link-once section that will be
6210 discarded, then don't create any stubs. */
6211 if (section->output_section == NULL
6212 || section->output_section->owner != output_bfd)
6213 continue;
6214
6215 /* Get the relocs. */
6216 internal_relocs
6217 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6218 NULL, info->keep_memory);
6219 if (internal_relocs == NULL)
6220 goto error_ret_free_local;
6221
6222 /* Now examine each relocation. */
6223 irela = internal_relocs;
6224 irelaend = irela + section->reloc_count;
6225 for (; irela < irelaend; irela++)
6226 {
6227 unsigned int r_type, r_indx;
906e58ca
NC		 6228 asection *sym_sec;
6229 bfd_vma sym_value;
6230 bfd_vma destination;
6231 struct elf32_arm_link_hash_entry *hash;
7413f23f 6232 const char *sym_name;
34e77a92 6233 unsigned char st_type;
35fc36a8 6234 enum arm_st_branch_type branch_type;
48229727 6235 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6236
6237 r_type = ELF32_R_TYPE (irela->r_info);
6238 r_indx = ELF32_R_SYM (irela->r_info);
6239
6240 if (r_type >= (unsigned int) R_ARM_max)
6241 {
6242 bfd_set_error (bfd_error_bad_value);
6243 error_ret_free_internal:
6244 if (elf_section_data (section)->relocs == NULL)
6245 free (internal_relocs);
15dd01b1
TP		 6246 /* Fall through. */
6247 error_ret_free_local:
6248 if (local_syms != NULL
6249 && (symtab_hdr->contents
6250 != (unsigned char *) local_syms))
6251 free (local_syms);
6252 return FALSE;
906e58ca 6253 }
b38cadfb 6254
0855e32b
NS		 6255 hash = NULL;
6256 if (r_indx >= symtab_hdr->sh_info)
6257 hash = elf32_arm_hash_entry
6258 (elf_sym_hashes (input_bfd)
6259 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6260
0855e32b
NS		 6261 /* Only look for stubs on branch instructions, or
6262 non-relaxed TLSCALL */
906e58ca 6263 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6264 && (r_type != (unsigned int) R_ARM_THM_CALL)
6265 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6266 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6267 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6268 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6269 && (r_type != (unsigned int) R_ARM_PLT32)
6270 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6271 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6272 && r_type == elf32_arm_tls_transition
6273 (info, r_type, &hash->root)
6274 && ((hash ? hash->tls_type
6275 : (elf32_arm_local_got_tls_type
6276 (input_bfd)[r_indx]))
6277 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6278 continue;
6279
6280 /* Now determine the call target, its name, value,
6281 section. */
6282 sym_sec = NULL;
6283 sym_value = 0;
6284 destination = 0;
7413f23f 6285 sym_name = NULL;
b38cadfb 6286
0855e32b
NS		 6287 if (r_type == (unsigned int) R_ARM_TLS_CALL
6288 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6289 {
6290 /* A non-relaxed TLS call. The target is the
6291 plt-resident trampoline and nothing to do
6292 with the symbol. */
6293 BFD_ASSERT (htab->tls_trampoline > 0);
6294 sym_sec = htab->root.splt;
6295 sym_value = htab->tls_trampoline;
6296 hash = 0;
34e77a92 6297 st_type = STT_FUNC;
35fc36a8 6298 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6299 }
6300 else if (!hash)
906e58ca
NC		 6301 {
6302 /* It's a local symbol. */
6303 Elf_Internal_Sym *sym;
906e58ca
NC		 6304
6305 if (local_syms == NULL)
6306 {
6307 local_syms
6308 = (Elf_Internal_Sym *) symtab_hdr->contents;
6309 if (local_syms == NULL)
6310 local_syms
6311 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6312 symtab_hdr->sh_info, 0,
6313 NULL, NULL, NULL);
6314 if (local_syms == NULL)
6315 goto error_ret_free_internal;
6316 }
6317
6318 sym = local_syms + r_indx;
f6d250ce
TS		 6319 if (sym->st_shndx == SHN_UNDEF)
6320 sym_sec = bfd_und_section_ptr;
6321 else if (sym->st_shndx == SHN_ABS)
6322 sym_sec = bfd_abs_section_ptr;
6323 else if (sym->st_shndx == SHN_COMMON)
6324 sym_sec = bfd_com_section_ptr;
6325 else
6326 sym_sec =
6327 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6328
ffcb4889
NS		 6329 if (!sym_sec)
6330 /* This is an undefined symbol. It can never
6a631e86 6331 be resolved. */
ffcb4889 6332 continue;
fe33d2fa 6333
906e58ca
NC		 6334 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6335 sym_value = sym->st_value;
6336 destination = (sym_value + irela->r_addend
6337 + sym_sec->output_offset
6338 + sym_sec->output_section->vma);
34e77a92 6339 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6340 branch_type =
6341 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6342 sym_name
6343 = bfd_elf_string_from_elf_section (input_bfd,
6344 symtab_hdr->sh_link,
6345 sym->st_name);
906e58ca
NC		 6346 }
6347 else
6348 {
6349 /* It's an external symbol. */
906e58ca
NC		 6350 while (hash->root.root.type == bfd_link_hash_indirect
6351 || hash->root.root.type == bfd_link_hash_warning)
6352 hash = ((struct elf32_arm_link_hash_entry *)
6353 hash->root.root.u.i.link);
6354
6355 if (hash->root.root.type == bfd_link_hash_defined
6356 || hash->root.root.type == bfd_link_hash_defweak)
6357 {
6358 sym_sec = hash->root.root.u.def.section;
6359 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6360
6361 struct elf32_arm_link_hash_table *globals =
6362 elf32_arm_hash_table (info);
6363
6364 /* For a destination in a shared library,
6365 use the PLT stub as target address to
6366 decide whether a branch stub is
6367 needed. */
4dfe6ac6 6368 if (globals != NULL
362d30a1 6369 && globals->root.splt != NULL
4dfe6ac6 6370 && hash != NULL
022f8312
CL		 6371 && hash->root.plt.offset != (bfd_vma) -1)
6372 {
362d30a1 6373 sym_sec = globals->root.splt;
022f8312
CL		 6374 sym_value = hash->root.plt.offset;
6375 if (sym_sec->output_section != NULL)
6376 destination = (sym_value
6377 + sym_sec->output_offset
6378 + sym_sec->output_section->vma);
6379 }
6380 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6381 destination = (sym_value + irela->r_addend
6382 + sym_sec->output_offset
6383 + sym_sec->output_section->vma);
6384 }
69c5861e
CL		 6385 else if ((hash->root.root.type == bfd_link_hash_undefined)
6386 || (hash->root.root.type == bfd_link_hash_undefweak))
6387 {
6388 /* For a shared library, use the PLT stub as
6389 target address to decide whether a long
6390 branch stub is needed.
6391 For absolute code, they cannot be handled. */
6392 struct elf32_arm_link_hash_table *globals =
6393 elf32_arm_hash_table (info);
6394
4dfe6ac6 6395 if (globals != NULL
362d30a1 6396 && globals->root.splt != NULL
4dfe6ac6 6397 && hash != NULL
69c5861e
CL		 6398 && hash->root.plt.offset != (bfd_vma) -1)
6399 {
362d30a1 6400 sym_sec = globals->root.splt;
69c5861e
CL		 6401 sym_value = hash->root.plt.offset;
6402 if (sym_sec->output_section != NULL)
6403 destination = (sym_value
6404 + sym_sec->output_offset
6405 + sym_sec->output_section->vma);
6406 }
6407 else
6408 continue;
6409 }
906e58ca
NC		 6410 else
6411 {
6412 bfd_set_error (bfd_error_bad_value);
6413 goto error_ret_free_internal;
6414 }
34e77a92 6415 st_type = hash->root.type;
39d911fc
TP		 6416 branch_type =
6417 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6418 sym_name = hash->root.root.root.string;
906e58ca
NC		 6419 }
6420
48229727 6421 do
7413f23f 6422 {
b715f643 6423 bfd_boolean new_stub;
0955507f 6424 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6425
48229727
JB		 6426 /* Determine what (if any) linker stub is needed. */
6427 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6428 st_type, &branch_type,
6429 hash, destination, sym_sec,
48229727
JB		 6430 input_bfd, sym_name);
6431 if (stub_type == arm_stub_none)
6432 break;
6433
48229727
JB		 6434 /* We've either created a stub for this reloc already,
6435 or we are about to. */
0955507f 6436 stub_entry =
b715f643
TP		 6437 elf32_arm_create_stub (htab, stub_type, section, irela,
6438 sym_sec, hash,
6439 (char *) sym_name, sym_value,
6440 branch_type, &new_stub);
7413f23f 6441
0955507f 6442 created_stub = stub_entry != NULL;
b715f643
TP		 6443 if (!created_stub)
6444 goto error_ret_free_internal;
6445 else if (!new_stub)
6446 break;
99059e56 6447 else
b715f643 6448 stub_changed = TRUE;
99059e56
RM		 6449 }
6450 while (0);
6451
6452 /* Look for relocations which might trigger Cortex-A8
6453 erratum. */
6454 if (htab->fix_cortex_a8
6455 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6456 || r_type == (unsigned int) R_ARM_THM_JUMP19
6457 || r_type == (unsigned int) R_ARM_THM_CALL
6458 || r_type == (unsigned int) R_ARM_THM_XPC22))
6459 {
6460 bfd_vma from = section->output_section->vma
6461 + section->output_offset
6462 + irela->r_offset;
6463
6464 if ((from & 0xfff) == 0xffe)
6465 {
6466 /* Found a candidate. Note we haven't checked the
6467 destination is within 4K here: if we do so (and
6468 don't create an entry in a8_relocs) we can't tell
6469 that a branch should have been relocated when
6470 scanning later. */
6471 if (num_a8_relocs == a8_reloc_table_size)
6472 {
6473 a8_reloc_table_size *= 2;
6474 a8_relocs = (struct a8_erratum_reloc *)
6475 bfd_realloc (a8_relocs,
6476 sizeof (struct a8_erratum_reloc)
6477 * a8_reloc_table_size);
6478 }
6479
6480 a8_relocs[num_a8_relocs].from = from;
6481 a8_relocs[num_a8_relocs].destination = destination;
6482 a8_relocs[num_a8_relocs].r_type = r_type;
6483 a8_relocs[num_a8_relocs].branch_type = branch_type;
6484 a8_relocs[num_a8_relocs].sym_name = sym_name;
6485 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6486 a8_relocs[num_a8_relocs].hash = hash;
6487
6488 num_a8_relocs++;
6489 }
6490 }
906e58ca
NC		 6491 }
6492
99059e56
RM		 6493 /* We're done with the internal relocs, free them. */
6494 if (elf_section_data (section)->relocs == NULL)
6495 free (internal_relocs);
6496 }
48229727 6497
99059e56 6498 if (htab->fix_cortex_a8)
48229727 6499 {
99059e56
RM		 6500 /* Sort relocs which might apply to Cortex-A8 erratum. */
6501 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6502 sizeof (struct a8_erratum_reloc),
99059e56 6503 &a8_reloc_compare);
48229727 6504
99059e56
RM		 6505 /* Scan for branches which might trigger Cortex-A8 erratum. */
6506 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6507 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6508 a8_relocs, num_a8_relocs,
6509 prev_num_a8_fixes, &stub_changed)
6510 != 0)
48229727 6511 goto error_ret_free_local;
5e681ec4 6512 }
7f991970
AM		 6513
6514 if (local_syms != NULL
6515 && symtab_hdr->contents != (unsigned char *) local_syms)
6516 {
6517 if (!info->keep_memory)
6518 free (local_syms);
6519 else
6520 symtab_hdr->contents = (unsigned char *) local_syms;
6521 }
5e681ec4
PB		 6522 }
6523
0955507f
TP		 6524 if (first_veneer_scan
6525 && !set_cmse_veneer_addr_from_implib (info, htab,
6526 &cmse_stub_created))
6527 ret = FALSE;
6528
eb7c4339 6529 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6530 stub_changed = TRUE;
48229727 6531
906e58ca
NC		 6532 if (!stub_changed)
6533 break;
5e681ec4 6534
906e58ca
NC		 6535 /* OK, we've added some stubs. Find out the new size of the
6536 stub sections. */
6537 for (stub_sec = htab->stub_bfd->sections;
6538 stub_sec != NULL;
6539 stub_sec = stub_sec->next)
3e6b1042
DJ		 6540 {
6541 /* Ignore non-stub sections. */
6542 if (!strstr (stub_sec->name, STUB_SUFFIX))
6543 continue;
6544
6545 stub_sec->size = 0;
6546 }
b34b2d70 6547
0955507f
TP		 6548 /* Add new SG veneers after those already in the input import
6549 library. */
6550 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6551 stub_type++)
6552 {
6553 bfd_vma *start_offset_p;
6554 asection **stub_sec_p;
6555
6556 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6557 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6558 if (start_offset_p == NULL)
6559 continue;
6560
6561 BFD_ASSERT (stub_sec_p != NULL);
6562 if (*stub_sec_p != NULL)
6563 (*stub_sec_p)->size = *start_offset_p;
6564 }
6565
d7c5bd02 6566 /* Compute stub section size, considering padding. */
906e58ca 6567 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6568 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6569 stub_type++)
6570 {
6571 int size, padding;
6572 asection **stub_sec_p;
6573
6574 padding = arm_dedicated_stub_section_padding (stub_type);
6575 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6576 /* Skip if no stub input section or no stub section padding
6577 required. */
6578 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6579 continue;
6580 /* Stub section padding required but no dedicated section. */
6581 BFD_ASSERT (stub_sec_p);
6582
6583 size = (*stub_sec_p)->size;
6584 size = (size + padding - 1) & ~(padding - 1);
6585 (*stub_sec_p)->size = size;
6586 }
906e58ca 6587
48229727
JB		 6588 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6589 if (htab->fix_cortex_a8)
99059e56
RM		 6590 for (i = 0; i < num_a8_fixes; i++)
6591 {
48229727 6592 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6593 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6594
6595 if (stub_sec == NULL)
7f991970 6596 return FALSE;
48229727 6597
99059e56
RM		 6598 stub_sec->size
6599 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6600 NULL);
6601 }
48229727
JB		 6602
6603
906e58ca
NC		 6604 /* Ask the linker to do its stuff. */
6605 (*htab->layout_sections_again) ();
4ba2ef8f 6606 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6607 }
6608
48229727
JB		 6609 /* Add stubs for Cortex-A8 erratum fixes now. */
6610 if (htab->fix_cortex_a8)
6611 {
6612 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6613 {
6614 struct elf32_arm_stub_hash_entry *stub_entry;
6615 char *stub_name = a8_fixes[i].stub_name;
6616 asection *section = a8_fixes[i].section;
6617 unsigned int section_id = a8_fixes[i].section->id;
6618 asection *link_sec = htab->stub_group[section_id].link_sec;
6619 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6620 const insn_sequence *template_sequence;
6621 int template_size, size = 0;
6622
6623 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6624 TRUE, FALSE);
6625 if (stub_entry == NULL)
6626 {
dae82561 6627 _bfd_error_handler (_("%B: cannot create stub entry %s"),
4eca0228 6628 section->owner, stub_name);
99059e56
RM		 6629 return FALSE;
6630 }
6631
6632 stub_entry->stub_sec = stub_sec;
0955507f 6633 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6634 stub_entry->id_sec = link_sec;
6635 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6636 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6637 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6638 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6639 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6640 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6641
99059e56
RM		 6642 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6643 &template_sequence,
6644 &template_size);
48229727 6645
99059e56
RM		 6646 stub_entry->stub_size = size;
6647 stub_entry->stub_template = template_sequence;
6648 stub_entry->stub_template_size = template_size;
6649 }
48229727
JB		 6650
6651 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6652 elf32_arm_write_section(). */
48229727
JB		 6653 htab->a8_erratum_fixes = a8_fixes;
6654 htab->num_a8_erratum_fixes = num_a8_fixes;
6655 }
6656 else
6657 {
6658 htab->a8_erratum_fixes = NULL;
6659 htab->num_a8_erratum_fixes = 0;
6660 }
0955507f 6661 return ret;
5e681ec4
PB		 6662}
6663
906e58ca
NC		 6664/* Build all the stubs associated with the current output file. The
6665 stubs are kept in a hash table attached to the main linker hash
6666 table. We also set up the .plt entries for statically linked PIC
6667 functions here. This function is called via arm_elf_finish in the
6668 linker. */
252b5132 6669
906e58ca
NC		 6670bfd_boolean
6671elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6672{
906e58ca
NC		 6673 asection *stub_sec;
6674 struct bfd_hash_table *table;
0955507f 6675 enum elf32_arm_stub_type stub_type;
906e58ca 6676 struct elf32_arm_link_hash_table *htab;
252b5132 6677
906e58ca 6678 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6679 if (htab == NULL)
6680 return FALSE;
252b5132 6681
906e58ca
NC		 6682 for (stub_sec = htab->stub_bfd->sections;
6683 stub_sec != NULL;
6684 stub_sec = stub_sec->next)
252b5132 6685 {
906e58ca
NC		 6686 bfd_size_type size;
6687
8029a119 6688 /* Ignore non-stub sections. */
906e58ca
NC		 6689 if (!strstr (stub_sec->name, STUB_SUFFIX))
6690 continue;
6691
d7c5bd02 6692 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6693 must at least be done for stub section requiring padding and for SG
6694 veneers to ensure that a non secure code branching to a removed SG
6695 veneer causes an error. */
906e58ca 6696 size = stub_sec->size;
21d799b5 6697 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6698 if (stub_sec->contents == NULL && size != 0)
6699 return FALSE;
0955507f 6700
906e58ca 6701 stub_sec->size = 0;
252b5132
RH		 6702 }
6703
0955507f
TP		 6704 /* Add new SG veneers after those already in the input import library. */
6705 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6706 {
6707 bfd_vma *start_offset_p;
6708 asection **stub_sec_p;
6709
6710 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6711 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6712 if (start_offset_p == NULL)
6713 continue;
6714
6715 BFD_ASSERT (stub_sec_p != NULL);
6716 if (*stub_sec_p != NULL)
6717 (*stub_sec_p)->size = *start_offset_p;
6718 }
6719
906e58ca
NC		 6720 /* Build the stubs as directed by the stub hash table. */
6721 table = &htab->stub_hash_table;
6722 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6723 if (htab->fix_cortex_a8)
6724 {
6725 /* Place the cortex a8 stubs last. */
6726 htab->fix_cortex_a8 = -1;
6727 bfd_hash_traverse (table, arm_build_one_stub, info);
6728 }
252b5132 6729
906e58ca 6730 return TRUE;
252b5132
RH		 6731}
6732
9b485d32
NC		 6733/* Locate the Thumb encoded calling stub for NAME. */
6734
252b5132 6735static struct elf_link_hash_entry *
57e8b36a
NC		 6736find_thumb_glue (struct bfd_link_info *link_info,
6737 const char *name,
f2a9dd69 6738 char **error_message)
252b5132
RH		 6739{
6740 char *tmp_name;
6741 struct elf_link_hash_entry *hash;
6742 struct elf32_arm_link_hash_table *hash_table;
6743
6744 /* We need a pointer to the armelf specific hash table. */
6745 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6746 if (hash_table == NULL)
6747 return NULL;
252b5132 6748
21d799b5 6749 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6750 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6751
6752 BFD_ASSERT (tmp_name);
6753
6754 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6755
6756 hash = elf_link_hash_lookup
b34976b6 6757 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6758
b1657152
AM		 6759 if (hash == NULL
6760 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6761 tmp_name, name) == -1)
6762 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6763
6764 free (tmp_name);
6765
6766 return hash;
6767}
6768
9b485d32
NC		 6769/* Locate the ARM encoded calling stub for NAME. */
6770
252b5132 6771static struct elf_link_hash_entry *
57e8b36a
NC		 6772find_arm_glue (struct bfd_link_info *link_info,
6773 const char *name,
f2a9dd69 6774 char **error_message)
252b5132
RH		 6775{
6776 char *tmp_name;
6777 struct elf_link_hash_entry *myh;
6778 struct elf32_arm_link_hash_table *hash_table;
6779
6780 /* We need a pointer to the elfarm specific hash table. */
6781 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6782 if (hash_table == NULL)
6783 return NULL;
252b5132 6784
21d799b5 6785 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6786 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6787
6788 BFD_ASSERT (tmp_name);
6789
6790 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6791
6792 myh = elf_link_hash_lookup
b34976b6 6793 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6794
b1657152
AM		 6795 if (myh == NULL
6796 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6797 tmp_name, name) == -1)
6798 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6799
6800 free (tmp_name);
6801
6802 return myh;
6803}
6804
8f6277f5 6805/* ARM->Thumb glue (static images):
252b5132
RH		 6806
6807 .arm
6808 __func_from_arm:
6809 ldr r12, __func_addr
6810 bx r12
6811 __func_addr:
906e58ca 6812 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6813
26079076
PB		 6814 (v5t static images)
6815 .arm
6816 __func_from_arm:
6817 ldr pc, __func_addr
6818 __func_addr:
906e58ca 6819 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6820
8f6277f5
PB		 6821 (relocatable images)
6822 .arm
6823 __func_from_arm:
6824 ldr r12, __func_offset
6825 add r12, r12, pc
6826 bx r12
6827 __func_offset:
8029a119 6828 .word func - . */
8f6277f5
PB		 6829
6830#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6831static const insn32 a2t1_ldr_insn = 0xe59fc000;
6832static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6833static const insn32 a2t3_func_addr_insn = 0x00000001;
6834
26079076
PB		 6835#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6836static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6837static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6838
8f6277f5
PB		 6839#define ARM2THUMB_PIC_GLUE_SIZE 16
6840static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6841static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6842static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6843
9b485d32 6844/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6845
8029a119
NC		 6846 .thumb .thumb
6847 .align 2 .align 2
6848 __func_from_thumb: __func_from_thumb:
6849 bx pc push {r6, lr}
6850 nop ldr r6, __func_addr
6851 .arm mov lr, pc
6852 b func bx r6
99059e56
RM		 6853 .arm
6854 ;; back_to_thumb
6855 ldmia r13! {r6, lr}
6856 bx lr
6857 __func_addr:
6858 .word func */
252b5132
RH		 6859
6860#define THUMB2ARM_GLUE_SIZE 8
6861static const insn16 t2a1_bx_pc_insn = 0x4778;
6862static const insn16 t2a2_noop_insn = 0x46c0;
6863static const insn32 t2a3_b_insn = 0xea000000;
6864
c7b8f16e 6865#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6866#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6867#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6868
845b51d6
PB		 6869#define ARM_BX_VENEER_SIZE 12
6870static const insn32 armbx1_tst_insn = 0xe3100001;
6871static const insn32 armbx2_moveq_insn = 0x01a0f000;
6872static const insn32 armbx3_bx_insn = 0xe12fff10;
6873
7e392df6 6874#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6875static void
6876arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6877{
6878 asection * s;
8029a119 6879 bfd_byte * contents;
252b5132 6880
8029a119 6881 if (size == 0)
3e6b1042
DJ		 6882 {
6883 /* Do not include empty glue sections in the output. */
6884 if (abfd != NULL)
6885 {
3d4d4302 6886 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6887 if (s != NULL)
6888 s->flags |= SEC_EXCLUDE;
6889 }
6890 return;
6891 }
252b5132 6892
8029a119 6893 BFD_ASSERT (abfd != NULL);
252b5132 6894
3d4d4302 6895 s = bfd_get_linker_section (abfd, name);
8029a119 6896 BFD_ASSERT (s != NULL);
252b5132 6897
21d799b5 6898 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6899
8029a119
NC		 6900 BFD_ASSERT (s->size == size);
6901 s->contents = contents;
6902}
906e58ca 6903
8029a119
NC		 6904bfd_boolean
6905bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6906{
6907 struct elf32_arm_link_hash_table * globals;
906e58ca 6908
8029a119
NC		 6909 globals = elf32_arm_hash_table (info);
6910 BFD_ASSERT (globals != NULL);
906e58ca 6911
8029a119
NC		 6912 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6913 globals->arm_glue_size,
6914 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6915
8029a119
NC		 6916 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6917 globals->thumb_glue_size,
6918 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6919
8029a119
NC		 6920 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6921 globals->vfp11_erratum_glue_size,
6922 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6923
a504d23a
LA		 6924 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6925 globals->stm32l4xx_erratum_glue_size,
6926 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6927
8029a119
NC		 6928 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6929 globals->bx_glue_size,
845b51d6
PB		 6930 ARM_BX_GLUE_SECTION_NAME);
6931
b34976b6 6932 return TRUE;
252b5132
RH		 6933}
6934
a4fd1a8e 6935/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6936 returns the symbol identifying the stub. */
6937
a4fd1a8e 6938static struct elf_link_hash_entry *
57e8b36a
NC		 6939record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6940 struct elf_link_hash_entry * h)
252b5132
RH		 6941{
6942 const char * name = h->root.root.string;
63b0f745 6943 asection * s;
252b5132
RH		 6944 char * tmp_name;
6945 struct elf_link_hash_entry * myh;
14a793b2 6946 struct bfd_link_hash_entry * bh;
252b5132 6947 struct elf32_arm_link_hash_table * globals;
dc810e39 6948 bfd_vma val;
2f475487 6949 bfd_size_type size;
252b5132
RH		 6950
6951 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6952 BFD_ASSERT (globals != NULL);
6953 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6954
3d4d4302 6955 s = bfd_get_linker_section
252b5132
RH		 6956 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6957
252b5132
RH		 6958 BFD_ASSERT (s != NULL);
6959
21d799b5 6960 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6961 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6962
6963 BFD_ASSERT (tmp_name);
6964
6965 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6966
6967 myh = elf_link_hash_lookup
b34976b6 6968 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6969
6970 if (myh != NULL)
6971 {
9b485d32 6972 /* We've already seen this guy. */
252b5132 6973 free (tmp_name);
a4fd1a8e 6974 return myh;
252b5132
RH		 6975 }
6976
57e8b36a
NC		 6977 /* The only trick here is using hash_table->arm_glue_size as the value.
6978 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6979 putting it. The +1 on the value marks that the stub has not been
6980 output yet - not that it is a Thumb function. */
14a793b2 6981 bh = NULL;
dc810e39
AM		 6982 val = globals->arm_glue_size + 1;
6983 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6984 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6985 NULL, TRUE, FALSE, &bh);
252b5132 6986
b7693d02
DJ		 6987 myh = (struct elf_link_hash_entry *) bh;
6988 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6989 myh->forced_local = 1;
6990
252b5132
RH		 6991 free (tmp_name);
6992
0e1862bb
L		 6993 if (bfd_link_pic (link_info)
6994 || globals->root.is_relocatable_executable
27e55c4d 6995 || globals->pic_veneer)
2f475487 6996 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6997 else if (globals->use_blx)
6998 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6999 else
2f475487
AM		 7000 size = ARM2THUMB_STATIC_GLUE_SIZE;
7001
7002 s->size += size;
7003 globals->arm_glue_size += size;
252b5132 7004
a4fd1a8e 7005 return myh;
252b5132
RH		 7006}
7007
845b51d6
PB		 7008/* Allocate space for ARMv4 BX veneers. */
7009
7010static void
7011record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7012{
7013 asection * s;
7014 struct elf32_arm_link_hash_table *globals;
7015 char *tmp_name;
7016 struct elf_link_hash_entry *myh;
7017 struct bfd_link_hash_entry *bh;
7018 bfd_vma val;
7019
7020 /* BX PC does not need a veneer. */
7021 if (reg == 15)
7022 return;
7023
7024 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7025 BFD_ASSERT (globals != NULL);
7026 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7027
7028 /* Check if this veneer has already been allocated. */
7029 if (globals->bx_glue_offset[reg])
7030 return;
7031
3d4d4302 7032 s = bfd_get_linker_section
845b51d6
PB		 7033 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7034
7035 BFD_ASSERT (s != NULL);
7036
7037 /* Add symbol for veneer. */
21d799b5
NC		 7038 tmp_name = (char *)
7039 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7040
845b51d6 7041 BFD_ASSERT (tmp_name);
906e58ca 7042
845b51d6 7043 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7044
845b51d6
PB		 7045 myh = elf_link_hash_lookup
7046 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7047
845b51d6 7048 BFD_ASSERT (myh == NULL);
906e58ca 7049
845b51d6
PB		 7050 bh = NULL;
7051 val = globals->bx_glue_size;
7052 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7053 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7054 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7055
7056 myh = (struct elf_link_hash_entry *) bh;
7057 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7058 myh->forced_local = 1;
7059
7060 s->size += ARM_BX_VENEER_SIZE;
7061 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7062 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7063}
7064
7065
c7b8f16e
JB		 7066/* Add an entry to the code/data map for section SEC. */
7067
7068static void
7069elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7070{
7071 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7072 unsigned int newidx;
906e58ca 7073
c7b8f16e
JB		 7074 if (sec_data->map == NULL)
7075 {
21d799b5 7076 sec_data->map = (elf32_arm_section_map *)
99059e56 7077 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7078 sec_data->mapcount = 0;
7079 sec_data->mapsize = 1;
7080 }
906e58ca 7081
c7b8f16e 7082 newidx = sec_data->mapcount++;
906e58ca 7083
c7b8f16e
JB		 7084 if (sec_data->mapcount > sec_data->mapsize)
7085 {
7086 sec_data->mapsize *= 2;
21d799b5 7087 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7088 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7089 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7090 }
7091
7092 if (sec_data->map)
7093 {
7094 sec_data->map[newidx].vma = vma;
7095 sec_data->map[newidx].type = type;
c7b8f16e 7096 }
c7b8f16e
JB		 7097}
7098
7099
7100/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7101 veneers are handled for now. */
7102
7103static bfd_vma
7104record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7105 elf32_vfp11_erratum_list *branch,
7106 bfd *branch_bfd,
7107 asection *branch_sec,
7108 unsigned int offset)
c7b8f16e
JB		 7109{
7110 asection *s;
7111 struct elf32_arm_link_hash_table *hash_table;
7112 char *tmp_name;
7113 struct elf_link_hash_entry *myh;
7114 struct bfd_link_hash_entry *bh;
7115 bfd_vma val;
7116 struct _arm_elf_section_data *sec_data;
c7b8f16e 7117 elf32_vfp11_erratum_list *newerr;
906e58ca 7118
c7b8f16e 7119 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7120 BFD_ASSERT (hash_table != NULL);
7121 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7122
3d4d4302 7123 s = bfd_get_linker_section
c7b8f16e 7124 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7125
c7b8f16e 7126 sec_data = elf32_arm_section_data (s);
906e58ca 7127
c7b8f16e 7128 BFD_ASSERT (s != NULL);
906e58ca 7129
21d799b5 7130 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7131 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7132
c7b8f16e 7133 BFD_ASSERT (tmp_name);
906e58ca 7134
c7b8f16e
JB		 7135 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7136 hash_table->num_vfp11_fixes);
906e58ca 7137
c7b8f16e
JB		 7138 myh = elf_link_hash_lookup
7139 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7140
c7b8f16e 7141 BFD_ASSERT (myh == NULL);
906e58ca 7142
c7b8f16e
JB		 7143 bh = NULL;
7144 val = hash_table->vfp11_erratum_glue_size;
7145 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7146 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7147 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7148
7149 myh = (struct elf_link_hash_entry *) bh;
7150 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7151 myh->forced_local = 1;
7152
7153 /* Link veneer back to calling location. */
c7e2358a 7154 sec_data->erratumcount += 1;
21d799b5
NC		 7155 newerr = (elf32_vfp11_erratum_list *)
7156 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7157
c7b8f16e
JB		 7158 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7159 newerr->vma = -1;
7160 newerr->u.v.branch = branch;
7161 newerr->u.v.id = hash_table->num_vfp11_fixes;
7162 branch->u.b.veneer = newerr;
7163
7164 newerr->next = sec_data->erratumlist;
7165 sec_data->erratumlist = newerr;
7166
7167 /* A symbol for the return from the veneer. */
7168 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7169 hash_table->num_vfp11_fixes);
7170
7171 myh = elf_link_hash_lookup
7172 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7173
c7b8f16e
JB		 7174 if (myh != NULL)
7175 abort ();
7176
7177 bh = NULL;
7178 val = offset + 4;
7179 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7180 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7181
c7b8f16e
JB		 7182 myh = (struct elf_link_hash_entry *) bh;
7183 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7184 myh->forced_local = 1;
7185
7186 free (tmp_name);
906e58ca 7187
c7b8f16e
JB		 7188 /* Generate a mapping symbol for the veneer section, and explicitly add an
7189 entry for that symbol to the code/data map for the section. */
7190 if (hash_table->vfp11_erratum_glue_size == 0)
7191 {
7192 bh = NULL;
7193 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7194 ever requires this erratum fix. */
c7b8f16e
JB		 7195 _bfd_generic_link_add_one_symbol (link_info,
7196 hash_table->bfd_of_glue_owner, "$a",
7197 BSF_LOCAL, s, 0, NULL,
99059e56 7198 TRUE, FALSE, &bh);
c7b8f16e
JB		 7199
7200 myh = (struct elf_link_hash_entry *) bh;
7201 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7202 myh->forced_local = 1;
906e58ca 7203
c7b8f16e 7204 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7205 BFDs. We must make a note of this generated mapping symbol
7206 ourselves so that code byteswapping works properly in
7207 elf32_arm_write_section. */
c7b8f16e
JB		 7208 elf32_arm_section_map_add (s, 'a', 0);
7209 }
906e58ca 7210
c7b8f16e
JB		 7211 s->size += VFP11_ERRATUM_VENEER_SIZE;
7212 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7213 hash_table->num_vfp11_fixes++;
906e58ca 7214
c7b8f16e
JB		 7215 /* The offset of the veneer. */
7216 return val;
7217}
7218
a504d23a
LA		 7219/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7220 veneers need to be handled because used only in Cortex-M. */
7221
7222static bfd_vma
7223record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7224 elf32_stm32l4xx_erratum_list *branch,
7225 bfd *branch_bfd,
7226 asection *branch_sec,
7227 unsigned int offset,
7228 bfd_size_type veneer_size)
7229{
7230 asection *s;
7231 struct elf32_arm_link_hash_table *hash_table;
7232 char *tmp_name;
7233 struct elf_link_hash_entry *myh;
7234 struct bfd_link_hash_entry *bh;
7235 bfd_vma val;
7236 struct _arm_elf_section_data *sec_data;
7237 elf32_stm32l4xx_erratum_list *newerr;
7238
7239 hash_table = elf32_arm_hash_table (link_info);
7240 BFD_ASSERT (hash_table != NULL);
7241 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7242
7243 s = bfd_get_linker_section
7244 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7245
7246 BFD_ASSERT (s != NULL);
7247
7248 sec_data = elf32_arm_section_data (s);
7249
7250 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7251 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7252
7253 BFD_ASSERT (tmp_name);
7254
7255 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7256 hash_table->num_stm32l4xx_fixes);
7257
7258 myh = elf_link_hash_lookup
7259 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7260
7261 BFD_ASSERT (myh == NULL);
7262
7263 bh = NULL;
7264 val = hash_table->stm32l4xx_erratum_glue_size;
7265 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7266 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7267 NULL, TRUE, FALSE, &bh);
7268
7269 myh = (struct elf_link_hash_entry *) bh;
7270 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7271 myh->forced_local = 1;
7272
7273 /* Link veneer back to calling location. */
7274 sec_data->stm32l4xx_erratumcount += 1;
7275 newerr = (elf32_stm32l4xx_erratum_list *)
7276 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7277
7278 newerr->type = STM32L4XX_ERRATUM_VENEER;
7279 newerr->vma = -1;
7280 newerr->u.v.branch = branch;
7281 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7282 branch->u.b.veneer = newerr;
7283
7284 newerr->next = sec_data->stm32l4xx_erratumlist;
7285 sec_data->stm32l4xx_erratumlist = newerr;
7286
7287 /* A symbol for the return from the veneer. */
7288 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7289 hash_table->num_stm32l4xx_fixes);
7290
7291 myh = elf_link_hash_lookup
7292 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7293
7294 if (myh != NULL)
7295 abort ();
7296
7297 bh = NULL;
7298 val = offset + 4;
7299 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7300 branch_sec, val, NULL, TRUE, FALSE, &bh);
7301
7302 myh = (struct elf_link_hash_entry *) bh;
7303 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7304 myh->forced_local = 1;
7305
7306 free (tmp_name);
7307
7308 /* Generate a mapping symbol for the veneer section, and explicitly add an
7309 entry for that symbol to the code/data map for the section. */
7310 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7311 {
7312 bh = NULL;
7313 /* Creates a THUMB symbol since there is no other choice. */
7314 _bfd_generic_link_add_one_symbol (link_info,
7315 hash_table->bfd_of_glue_owner, "$t",
7316 BSF_LOCAL, s, 0, NULL,
7317 TRUE, FALSE, &bh);
7318
7319 myh = (struct elf_link_hash_entry *) bh;
7320 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7321 myh->forced_local = 1;
7322
7323 /* The elf32_arm_init_maps function only cares about symbols from input
7324 BFDs. We must make a note of this generated mapping symbol
7325 ourselves so that code byteswapping works properly in
7326 elf32_arm_write_section. */
7327 elf32_arm_section_map_add (s, 't', 0);
7328 }
7329
7330 s->size += veneer_size;
7331 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7332 hash_table->num_stm32l4xx_fixes++;
7333
7334 /* The offset of the veneer. */
7335 return val;
7336}
7337
8029a119 7338#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7339 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7340 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7341
7342/* Create a fake section for use by the ARM backend of the linker. */
7343
7344static bfd_boolean
7345arm_make_glue_section (bfd * abfd, const char * name)
7346{
7347 asection * sec;
7348
3d4d4302 7349 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7350 if (sec != NULL)
7351 /* Already made. */
7352 return TRUE;
7353
3d4d4302 7354 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7355
7356 if (sec == NULL
7357 || !bfd_set_section_alignment (abfd, sec, 2))
7358 return FALSE;
7359
7360 /* Set the gc mark to prevent the section from being removed by garbage
7361 collection, despite the fact that no relocs refer to this section. */
7362 sec->gc_mark = 1;
7363
7364 return TRUE;
7365}
7366
1db37fe6
YG		 7367/* Set size of .plt entries. This function is called from the
7368 linker scripts in ld/emultempl/{armelf}.em. */
7369
7370void
7371bfd_elf32_arm_use_long_plt (void)
7372{
7373 elf32_arm_use_long_plt_entry = TRUE;
7374}
7375
8afb0e02
NC		 7376/* Add the glue sections to ABFD. This function is called from the
7377 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7378
b34976b6 7379bfd_boolean
57e8b36a
NC		 7380bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7381 struct bfd_link_info *info)
252b5132 7382{
a504d23a
LA		 7383 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7384 bfd_boolean dostm32l4xx = globals
7385 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7386 bfd_boolean addglue;
7387
8afb0e02
NC		 7388 /* If we are only performing a partial
7389 link do not bother adding the glue. */
0e1862bb 7390 if (bfd_link_relocatable (info))
b34976b6 7391 return TRUE;
252b5132 7392
a504d23a 7393 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7394 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7395 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7396 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7397
7398 if (!dostm32l4xx)
7399 return addglue;
7400
7401 return addglue
7402 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7403}
7404
daa4adae
TP		 7405/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7406 ensures they are not marked for deletion by
7407 strip_excluded_output_sections () when veneers are going to be created
7408 later. Not doing so would trigger assert on empty section size in
7409 lang_size_sections_1 (). */
7410
7411void
7412bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7413{
7414 enum elf32_arm_stub_type stub_type;
7415
7416 /* If we are only performing a partial
7417 link do not bother adding the glue. */
7418 if (bfd_link_relocatable (info))
7419 return;
7420
7421 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7422 {
7423 asection *out_sec;
7424 const char *out_sec_name;
7425
7426 if (!arm_dedicated_stub_output_section_required (stub_type))
7427 continue;
7428
7429 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7430 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7431 if (out_sec != NULL)
7432 out_sec->flags |= SEC_KEEP;
7433 }
7434}
7435
8afb0e02
NC		 7436/* Select a BFD to be used to hold the sections used by the glue code.
7437 This function is called from the linker scripts in ld/emultempl/
8029a119 7438 {armelf/pe}.em. */
8afb0e02 7439
b34976b6 7440bfd_boolean
57e8b36a 7441bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7442{
7443 struct elf32_arm_link_hash_table *globals;
7444
7445 /* If we are only performing a partial link
7446 do not bother getting a bfd to hold the glue. */
0e1862bb 7447 if (bfd_link_relocatable (info))
b34976b6 7448 return TRUE;
8afb0e02 7449
b7693d02
DJ		 7450 /* Make sure we don't attach the glue sections to a dynamic object. */
7451 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7452
8afb0e02 7453 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7454 BFD_ASSERT (globals != NULL);
7455
7456 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7457 return TRUE;
8afb0e02 7458
252b5132
RH		 7459 /* Save the bfd for later use. */
7460 globals->bfd_of_glue_owner = abfd;
cedb70c5 7461
b34976b6 7462 return TRUE;
252b5132
RH		 7463}
7464
906e58ca
NC		 7465static void
7466check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7467{
2de70689
MGD		 7468 int cpu_arch;
7469
b38cadfb 7470 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7471 Tag_CPU_arch);
7472
7473 if (globals->fix_arm1176)
7474 {
7475 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7476 globals->use_blx = 1;
7477 }
7478 else
7479 {
7480 if (cpu_arch > TAG_CPU_ARCH_V4T)
7481 globals->use_blx = 1;
7482 }
39b41c9c
PB		 7483}
7484
b34976b6 7485bfd_boolean
57e8b36a 7486bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7487 struct bfd_link_info *link_info)
252b5132
RH		 7488{
7489 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7490 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7491 Elf_Internal_Rela *irel, *irelend;
7492 bfd_byte *contents = NULL;
252b5132
RH		 7493
7494 asection *sec;
7495 struct elf32_arm_link_hash_table *globals;
7496
7497 /* If we are only performing a partial link do not bother
7498 to construct any glue. */
0e1862bb 7499 if (bfd_link_relocatable (link_info))
b34976b6 7500 return TRUE;
252b5132 7501
39ce1a6a
NC		 7502 /* Here we have a bfd that is to be included on the link. We have a
7503 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7504 globals = elf32_arm_hash_table (link_info);
252b5132 7505 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7506
7507 check_use_blx (globals);
252b5132 7508
d504ffc8 7509 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7510 {
d003868e
AM		 7511 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7512 abfd);
e489d0ae
PB		 7513 return FALSE;
7514 }
f21f3fe0 7515
39ce1a6a
NC		 7516 /* PR 5398: If we have not decided to include any loadable sections in
7517 the output then we will not have a glue owner bfd. This is OK, it
7518 just means that there is nothing else for us to do here. */
7519 if (globals->bfd_of_glue_owner == NULL)
7520 return TRUE;
7521
252b5132
RH		 7522 /* Rummage around all the relocs and map the glue vectors. */
7523 sec = abfd->sections;
7524
7525 if (sec == NULL)
b34976b6 7526 return TRUE;
252b5132
RH		 7527
7528 for (; sec != NULL; sec = sec->next)
7529 {
7530 if (sec->reloc_count == 0)
7531 continue;
7532
2f475487
AM		 7533 if ((sec->flags & SEC_EXCLUDE) != 0)
7534 continue;
7535
0ffa91dd 7536 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7537
9b485d32 7538 /* Load the relocs. */
6cdc0ccc 7539 internal_relocs
906e58ca 7540 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7541
6cdc0ccc
AM		 7542 if (internal_relocs == NULL)
7543 goto error_return;
252b5132 7544
6cdc0ccc
AM		 7545 irelend = internal_relocs + sec->reloc_count;
7546 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7547 {
7548 long r_type;
7549 unsigned long r_index;
252b5132
RH		 7550
7551 struct elf_link_hash_entry *h;
7552
7553 r_type = ELF32_R_TYPE (irel->r_info);
7554 r_index = ELF32_R_SYM (irel->r_info);
7555
9b485d32 7556 /* These are the only relocation types we care about. */
ba96a88f 7557 if ( r_type != R_ARM_PC24
845b51d6 7558 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7559 continue;
7560
7561 /* Get the section contents if we haven't done so already. */
7562 if (contents == NULL)
7563 {
7564 /* Get cached copy if it exists. */
7565 if (elf_section_data (sec)->this_hdr.contents != NULL)
7566 contents = elf_section_data (sec)->this_hdr.contents;
7567 else
7568 {
7569 /* Go get them off disk. */
57e8b36a 7570 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7571 goto error_return;
7572 }
7573 }
7574
845b51d6
PB		 7575 if (r_type == R_ARM_V4BX)
7576 {
7577 int reg;
7578
7579 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7580 record_arm_bx_glue (link_info, reg);
7581 continue;
7582 }
7583
a7c10850 7584 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7585 h = NULL;
7586
9b485d32 7587 /* We don't care about local symbols. */
252b5132
RH		 7588 if (r_index < symtab_hdr->sh_info)
7589 continue;
7590
9b485d32 7591 /* This is an external symbol. */
252b5132
RH		 7592 r_index -= symtab_hdr->sh_info;
7593 h = (struct elf_link_hash_entry *)
7594 elf_sym_hashes (abfd)[r_index];
7595
7596 /* If the relocation is against a static symbol it must be within
7597 the current section and so cannot be a cross ARM/Thumb relocation. */
7598 if (h == NULL)
7599 continue;
7600
d504ffc8
DJ		 7601 /* If the call will go through a PLT entry then we do not need
7602 glue. */
362d30a1 7603 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7604 continue;
7605
252b5132
RH		 7606 switch (r_type)
7607 {
7608 case R_ARM_PC24:
7609 /* This one is a call from arm code. We need to look up
99059e56
RM		 7610 the target of the call. If it is a thumb target, we
7611 insert glue. */
39d911fc
TP		 7612 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7613 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7614 record_arm_to_thumb_glue (link_info, h);
7615 break;
7616
252b5132 7617 default:
c6596c5e 7618 abort ();
252b5132
RH		 7619 }
7620 }
6cdc0ccc
AM		 7621
7622 if (contents != NULL
7623 && elf_section_data (sec)->this_hdr.contents != contents)
7624 free (contents);
7625 contents = NULL;
7626
7627 if (internal_relocs != NULL
7628 && elf_section_data (sec)->relocs != internal_relocs)
7629 free (internal_relocs);
7630 internal_relocs = NULL;
252b5132
RH		 7631 }
7632
b34976b6 7633 return TRUE;
9a5aca8c 7634
252b5132 7635error_return:
6cdc0ccc
AM		 7636 if (contents != NULL
7637 && elf_section_data (sec)->this_hdr.contents != contents)
7638 free (contents);
7639 if (internal_relocs != NULL
7640 && elf_section_data (sec)->relocs != internal_relocs)
7641 free (internal_relocs);
9a5aca8c 7642
b34976b6 7643 return FALSE;
252b5132 7644}
7e392df6 7645#endif
252b5132 7646
eb043451 7647
c7b8f16e
JB		 7648/* Initialise maps of ARM/Thumb/data for input BFDs. */
7649
7650void
7651bfd_elf32_arm_init_maps (bfd *abfd)
7652{
7653 Elf_Internal_Sym *isymbuf;
7654 Elf_Internal_Shdr *hdr;
7655 unsigned int i, localsyms;
7656
af1f4419
NC		 7657 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7658 if (! is_arm_elf (abfd))
7659 return;
7660
c7b8f16e
JB		 7661 if ((abfd->flags & DYNAMIC) != 0)
7662 return;
7663
0ffa91dd 7664 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7665 localsyms = hdr->sh_info;
7666
7667 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7668 should contain the number of local symbols, which should come before any
7669 global symbols. Mapping symbols are always local. */
7670 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7671 NULL);
7672
7673 /* No internal symbols read? Skip this BFD. */
7674 if (isymbuf == NULL)
7675 return;
7676
7677 for (i = 0; i < localsyms; i++)
7678 {
7679 Elf_Internal_Sym *isym = &isymbuf[i];
7680 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7681 const char *name;
906e58ca 7682
c7b8f16e 7683 if (sec != NULL
99059e56
RM		 7684 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7685 {
7686 name = bfd_elf_string_from_elf_section (abfd,
7687 hdr->sh_link, isym->st_name);
906e58ca 7688
99059e56 7689 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7690 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7691 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7692 }
c7b8f16e
JB		 7693 }
7694}
7695
7696
48229727
JB		 7697/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7698 say what they wanted. */
7699
7700void
7701bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7702{
7703 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7704 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7705
4dfe6ac6
NC		 7706 if (globals == NULL)
7707 return;
7708
48229727
JB		 7709 if (globals->fix_cortex_a8 == -1)
7710 {
7711 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7712 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7713 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7714 || out_attr[Tag_CPU_arch_profile].i == 0))
7715 globals->fix_cortex_a8 = 1;
7716 else
7717 globals->fix_cortex_a8 = 0;
7718 }
7719}
7720
7721
c7b8f16e
JB		 7722void
7723bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7724{
7725 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7726 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7727
4dfe6ac6
NC		 7728 if (globals == NULL)
7729 return;
c7b8f16e
JB		 7730 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7731 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7732 {
7733 switch (globals->vfp11_fix)
99059e56
RM		 7734 {
7735 case BFD_ARM_VFP11_FIX_DEFAULT:
7736 case BFD_ARM_VFP11_FIX_NONE:
7737 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7738 break;
7739
7740 default:
7741 /* Give a warning, but do as the user requests anyway. */
4eca0228 7742 _bfd_error_handler (_("%B: warning: selected VFP11 erratum "
99059e56
RM		 7743 "workaround is not necessary for target architecture"), obfd);
7744 }
c7b8f16e
JB		 7745 }
7746 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7747 /* For earlier architectures, we might need the workaround, but do not
7748 enable it by default. If users is running with broken hardware, they
7749 must enable the erratum fix explicitly. */
7750 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7751}
7752
a504d23a
LA		 7753void
7754bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7755{
7756 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7757 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7758
7759 if (globals == NULL)
7760 return;
7761
7762 /* We assume only Cortex-M4 may require the fix. */
7763 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7764 || out_attr[Tag_CPU_arch_profile].i != 'M')
7765 {
7766 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7767 /* Give a warning, but do as the user requests anyway. */
4eca0228 7768 _bfd_error_handler
a504d23a
LA		 7769 (_("%B: warning: selected STM32L4XX erratum "
7770 "workaround is not necessary for target architecture"), obfd);
7771 }
7772}
c7b8f16e 7773
906e58ca
NC		 7774enum bfd_arm_vfp11_pipe
7775{
c7b8f16e
JB		 7776 VFP11_FMAC,
7777 VFP11_LS,
7778 VFP11_DS,
7779 VFP11_BAD
7780};
7781
7782/* Return a VFP register number. This is encoded as RX:X for single-precision
7783 registers, or X:RX for double-precision registers, where RX is the group of
7784 four bits in the instruction encoding and X is the single extension bit.
7785 RX and X fields are specified using their lowest (starting) bit. The return
7786 value is:
7787
7788 0...31: single-precision registers s0...s31
7789 32...63: double-precision registers d0...d31.
906e58ca 7790
c7b8f16e
JB		 7791 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7792 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7793
c7b8f16e
JB		 7794static unsigned int
7795bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7796 unsigned int x)
c7b8f16e
JB		 7797{
7798 if (is_double)
7799 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7800 else
7801 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7802}
7803
7804/* Set bits in *WMASK according to a register number REG as encoded by
7805 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7806
7807static void
7808bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7809{
7810 if (reg < 32)
7811 *wmask |= 1 << reg;
7812 else if (reg < 48)
7813 *wmask |= 3 << ((reg - 32) * 2);
7814}
7815
7816/* Return TRUE if WMASK overwrites anything in REGS. */
7817
7818static bfd_boolean
7819bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7820{
7821 int i;
906e58ca 7822
c7b8f16e
JB		 7823 for (i = 0; i < numregs; i++)
7824 {
7825 unsigned int reg = regs[i];
7826
7827 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7828 return TRUE;
906e58ca 7829
c7b8f16e
JB		 7830 reg -= 32;
7831
7832 if (reg >= 16)
99059e56 7833 continue;
906e58ca 7834
c7b8f16e 7835 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7836 return TRUE;
c7b8f16e 7837 }
906e58ca 7838
c7b8f16e
JB		 7839 return FALSE;
7840}
7841
7842/* In this function, we're interested in two things: finding input registers
7843 for VFP data-processing instructions, and finding the set of registers which
7844 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7845 hold the written set, so FLDM etc. are easy to deal with (we're only
7846 interested in 32 SP registers or 16 dp registers, due to the VFP version
7847 implemented by the chip in question). DP registers are marked by setting
7848 both SP registers in the write mask). */
7849
7850static enum bfd_arm_vfp11_pipe
7851bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7852 int *numregs)
c7b8f16e 7853{
91d6fa6a 7854 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7855 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7856
7857 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7858 {
7859 unsigned int pqrs;
7860 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7861 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7862
7863 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7864 | ((insn & 0x00300000) >> 19)
7865 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7866
7867 switch (pqrs)
99059e56
RM		 7868 {
7869 case 0: /* fmac[sd]. */
7870 case 1: /* fnmac[sd]. */
7871 case 2: /* fmsc[sd]. */
7872 case 3: /* fnmsc[sd]. */
7873 vpipe = VFP11_FMAC;
7874 bfd_arm_vfp11_write_mask (destmask, fd);
7875 regs[0] = fd;
7876 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7877 regs[2] = fm;
7878 *numregs = 3;
7879 break;
7880
7881 case 4: /* fmul[sd]. */
7882 case 5: /* fnmul[sd]. */
7883 case 6: /* fadd[sd]. */
7884 case 7: /* fsub[sd]. */
7885 vpipe = VFP11_FMAC;
7886 goto vfp_binop;
7887
7888 case 8: /* fdiv[sd]. */
7889 vpipe = VFP11_DS;
7890 vfp_binop:
7891 bfd_arm_vfp11_write_mask (destmask, fd);
7892 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7893 regs[1] = fm;
7894 *numregs = 2;
7895 break;
7896
7897 case 15: /* extended opcode. */
7898 {
7899 unsigned int extn = ((insn >> 15) & 0x1e)
7900 | ((insn >> 7) & 1);
7901
7902 switch (extn)
7903 {
7904 case 0: /* fcpy[sd]. */
7905 case 1: /* fabs[sd]. */
7906 case 2: /* fneg[sd]. */
7907 case 8: /* fcmp[sd]. */
7908 case 9: /* fcmpe[sd]. */
7909 case 10: /* fcmpz[sd]. */
7910 case 11: /* fcmpez[sd]. */
7911 case 16: /* fuito[sd]. */
7912 case 17: /* fsito[sd]. */
7913 case 24: /* ftoui[sd]. */
7914 case 25: /* ftouiz[sd]. */
7915 case 26: /* ftosi[sd]. */
7916 case 27: /* ftosiz[sd]. */
7917 /* These instructions will not bounce due to underflow. */
7918 *numregs = 0;
7919 vpipe = VFP11_FMAC;
7920 break;
7921
7922 case 3: /* fsqrt[sd]. */
7923 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7924 registers to cause the erratum in previous instructions. */
7925 bfd_arm_vfp11_write_mask (destmask, fd);
7926 vpipe = VFP11_DS;
7927 break;
7928
7929 case 15: /* fcvt{ds,sd}. */
7930 {
7931 int rnum = 0;
7932
7933 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7934
7935 /* Only FCVTSD can underflow. */
99059e56
RM		 7936 if ((insn & 0x100) != 0)
7937 regs[rnum++] = fm;
c7b8f16e 7938
99059e56 7939 *numregs = rnum;
c7b8f16e 7940
99059e56
RM		 7941 vpipe = VFP11_FMAC;
7942 }
7943 break;
c7b8f16e 7944
99059e56
RM		 7945 default:
7946 return VFP11_BAD;
7947 }
7948 }
7949 break;
c7b8f16e 7950
99059e56
RM		 7951 default:
7952 return VFP11_BAD;
7953 }
c7b8f16e
JB		 7954 }
7955 /* Two-register transfer. */
7956 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7957 {
7958 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7959
c7b8f16e
JB		 7960 if ((insn & 0x100000) == 0)
7961 {
99059e56
RM		 7962 if (is_double)
7963 bfd_arm_vfp11_write_mask (destmask, fm);
7964 else
7965 {
7966 bfd_arm_vfp11_write_mask (destmask, fm);
7967 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7968 }
c7b8f16e
JB		 7969 }
7970
91d6fa6a 7971 vpipe = VFP11_LS;
c7b8f16e
JB		 7972 }
7973 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7974 {
7975 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7976 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7977
c7b8f16e 7978 switch (puw)
99059e56
RM		 7979 {
7980 case 0: /* Two-reg transfer. We should catch these above. */
7981 abort ();
906e58ca 7982
99059e56
RM		 7983 case 2: /* fldm[sdx]. */
7984 case 3:
7985 case 5:
7986 {
7987 unsigned int i, offset = insn & 0xff;
c7b8f16e 7988
99059e56
RM		 7989 if (is_double)
7990 offset >>= 1;
c7b8f16e 7991
99059e56
RM		 7992 for (i = fd; i < fd + offset; i++)
7993 bfd_arm_vfp11_write_mask (destmask, i);
7994 }
7995 break;
906e58ca 7996
99059e56
RM		 7997 case 4: /* fld[sd]. */
7998 case 6:
7999 bfd_arm_vfp11_write_mask (destmask, fd);
8000 break;
906e58ca 8001
99059e56
RM		 8002 default:
8003 return VFP11_BAD;
8004 }
c7b8f16e 8005
91d6fa6a 8006 vpipe = VFP11_LS;
c7b8f16e
JB		 8007 }
8008 /* Single-register transfer. Note L==0. */
8009 else if ((insn & 0x0f100e10) == 0x0e000a10)
8010 {
8011 unsigned int opcode = (insn >> 21) & 7;
8012 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8013
8014 switch (opcode)
99059e56
RM		 8015 {
8016 case 0: /* fmsr/fmdlr. */
8017 case 1: /* fmdhr. */
8018 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8019 destination register. I don't know if this is exactly right,
8020 but it is the conservative choice. */
8021 bfd_arm_vfp11_write_mask (destmask, fn);
8022 break;
8023
8024 case 7: /* fmxr. */
8025 break;
8026 }
c7b8f16e 8027
91d6fa6a 8028 vpipe = VFP11_LS;
c7b8f16e
JB		 8029 }
8030
91d6fa6a 8031 return vpipe;
c7b8f16e
JB		 8032}
8033
8034
8035static int elf32_arm_compare_mapping (const void * a, const void * b);
8036
8037
8038/* Look for potentially-troublesome code sequences which might trigger the
8039 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8040 (available from ARM) for details of the erratum. A short version is
8041 described in ld.texinfo. */
8042
8043bfd_boolean
8044bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8045{
8046 asection *sec;
8047 bfd_byte *contents = NULL;
8048 int state = 0;
8049 int regs[3], numregs = 0;
8050 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8051 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8052
4dfe6ac6
NC		 8053 if (globals == NULL)
8054 return FALSE;
8055
c7b8f16e
JB		 8056 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8057 The states transition as follows:
906e58ca 8058
c7b8f16e 8059 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8060 A VFP FMAC-pipeline instruction has been seen. Fill
8061 regs[0]..regs[numregs-1] with its input operands. Remember this
8062 instruction in 'first_fmac'.
c7b8f16e
JB		 8063
8064 1 -> 2
99059e56
RM		 8065 Any instruction, except for a VFP instruction which overwrites
8066 regs[*].
906e58ca 8067
c7b8f16e
JB		 8068 1 -> 3 [ -> 0 ] or
8069 2 -> 3 [ -> 0 ]
99059e56
RM		 8070 A VFP instruction has been seen which overwrites any of regs[*].
8071 We must make a veneer! Reset state to 0 before examining next
8072 instruction.
906e58ca 8073
c7b8f16e 8074 2 -> 0
99059e56
RM		 8075 If we fail to match anything in state 2, reset to state 0 and reset
8076 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8077
8078 If the VFP11 vector mode is in use, there must be at least two unrelated
8079 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8080 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8081
8082 /* If we are only performing a partial link do not bother
8083 to construct any glue. */
0e1862bb 8084 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8085 return TRUE;
8086
0ffa91dd
NC		 8087 /* Skip if this bfd does not correspond to an ELF image. */
8088 if (! is_arm_elf (abfd))
8089 return TRUE;
906e58ca 8090
c7b8f16e
JB		 8091 /* We should have chosen a fix type by the time we get here. */
8092 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8093
8094 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8095 return TRUE;
2e6030b9 8096
33a7ffc2
JM		 8097 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8098 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8099 return TRUE;
8100
c7b8f16e
JB		 8101 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8102 {
8103 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8104 struct _arm_elf_section_data *sec_data;
8105
8106 /* If we don't have executable progbits, we're not interested in this
99059e56 8107 section. Also skip if section is to be excluded. */
c7b8f16e 8108 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8109 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8110 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8111 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8112 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8113 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8114 continue;
c7b8f16e
JB		 8115
8116 sec_data = elf32_arm_section_data (sec);
906e58ca 8117
c7b8f16e 8118 if (sec_data->mapcount == 0)
99059e56 8119 continue;
906e58ca 8120
c7b8f16e
JB		 8121 if (elf_section_data (sec)->this_hdr.contents != NULL)
8122 contents = elf_section_data (sec)->this_hdr.contents;
8123 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8124 goto error_return;
8125
8126 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8127 elf32_arm_compare_mapping);
8128
8129 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8130 {
8131 unsigned int span_start = sec_data->map[span].vma;
8132 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8133 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8134 char span_type = sec_data->map[span].type;
8135
8136 /* FIXME: Only ARM mode is supported at present. We may need to
8137 support Thumb-2 mode also at some point. */
8138 if (span_type != 'a')
8139 continue;
8140
8141 for (i = span_start; i < span_end;)
8142 {
8143 unsigned int next_i = i + 4;
8144 unsigned int insn = bfd_big_endian (abfd)
8145 ? (contents[i] << 24)
8146 | (contents[i + 1] << 16)
8147 | (contents[i + 2] << 8)
8148 | contents[i + 3]
8149 : (contents[i + 3] << 24)
8150 | (contents[i + 2] << 16)
8151 | (contents[i + 1] << 8)
8152 | contents[i];
8153 unsigned int writemask = 0;
8154 enum bfd_arm_vfp11_pipe vpipe;
8155
8156 switch (state)
8157 {
8158 case 0:
8159 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8160 &numregs);
8161 /* I'm assuming the VFP11 erratum can trigger with denorm
8162 operands on either the FMAC or the DS pipeline. This might
8163 lead to slightly overenthusiastic veneer insertion. */
8164 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8165 {
8166 state = use_vector ? 1 : 2;
8167 first_fmac = i;
8168 veneer_of_insn = insn;
8169 }
8170 break;
8171
8172 case 1:
8173 {
8174 int other_regs[3], other_numregs;
8175 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8176 other_regs,
99059e56
RM		 8177 &other_numregs);
8178 if (vpipe != VFP11_BAD
8179 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8180 numregs))
99059e56
RM		 8181 state = 3;
8182 else
8183 state = 2;
8184 }
8185 break;
8186
8187 case 2:
8188 {
8189 int other_regs[3], other_numregs;
8190 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8191 other_regs,
99059e56
RM		 8192 &other_numregs);
8193 if (vpipe != VFP11_BAD
8194 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8195 numregs))
99059e56
RM		 8196 state = 3;
8197 else
8198 {
8199 state = 0;
8200 next_i = first_fmac + 4;
8201 }
8202 }
8203 break;
8204
8205 case 3:
8206 abort (); /* Should be unreachable. */
8207 }
8208
8209 if (state == 3)
8210 {
8211 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8212 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8213
8214 elf32_arm_section_data (sec)->erratumcount += 1;
8215
8216 newerr->u.b.vfp_insn = veneer_of_insn;
8217
8218 switch (span_type)
8219 {
8220 case 'a':
8221 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8222 break;
8223
8224 default:
8225 abort ();
8226 }
8227
8228 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8229 first_fmac);
8230
99059e56 8231 newerr->vma = -1;
c7b8f16e 8232
99059e56
RM		 8233 newerr->next = sec_data->erratumlist;
8234 sec_data->erratumlist = newerr;
c7b8f16e 8235
99059e56
RM		 8236 state = 0;
8237 }
c7b8f16e 8238
99059e56
RM		 8239 i = next_i;
8240 }
8241 }
906e58ca 8242
c7b8f16e 8243 if (contents != NULL
99059e56
RM		 8244 && elf_section_data (sec)->this_hdr.contents != contents)
8245 free (contents);
c7b8f16e
JB		 8246 contents = NULL;
8247 }
8248
8249 return TRUE;
8250
8251error_return:
8252 if (contents != NULL
8253 && elf_section_data (sec)->this_hdr.contents != contents)
8254 free (contents);
906e58ca 8255
c7b8f16e
JB		 8256 return FALSE;
8257}
8258
8259/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8260 after sections have been laid out, using specially-named symbols. */
8261
8262void
8263bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8264 struct bfd_link_info *link_info)
8265{
8266 asection *sec;
8267 struct elf32_arm_link_hash_table *globals;
8268 char *tmp_name;
906e58ca 8269
0e1862bb 8270 if (bfd_link_relocatable (link_info))
c7b8f16e 8271 return;
2e6030b9
MS		 8272
8273 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8274 if (! is_arm_elf (abfd))
2e6030b9
MS		 8275 return;
8276
c7b8f16e 8277 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8278 if (globals == NULL)
8279 return;
906e58ca 8280
21d799b5 8281 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8282 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8283
8284 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8285 {
8286 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8287 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8288
c7b8f16e 8289 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8290 {
8291 struct elf_link_hash_entry *myh;
8292 bfd_vma vma;
8293
8294 switch (errnode->type)
8295 {
8296 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8297 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8298 /* Find veneer symbol. */
8299 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8300 errnode->u.b.veneer->u.v.id);
8301
99059e56
RM		 8302 myh = elf_link_hash_lookup
8303 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8304
a504d23a 8305 if (myh == NULL)
4eca0228
AM		 8306 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8307 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8308
8309 vma = myh->root.u.def.section->output_section->vma
8310 + myh->root.u.def.section->output_offset
8311 + myh->root.u.def.value;
8312
8313 errnode->u.b.veneer->vma = vma;
8314 break;
8315
8316 case VFP11_ERRATUM_ARM_VENEER:
8317 case VFP11_ERRATUM_THUMB_VENEER:
8318 /* Find return location. */
8319 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8320 errnode->u.v.id);
8321
8322 myh = elf_link_hash_lookup
8323 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8324
8325 if (myh == NULL)
4eca0228
AM		 8326 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8327 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8328
8329 vma = myh->root.u.def.section->output_section->vma
8330 + myh->root.u.def.section->output_offset
8331 + myh->root.u.def.value;
8332
8333 errnode->u.v.branch->vma = vma;
8334 break;
8335
8336 default:
8337 abort ();
8338 }
8339 }
8340 }
8341
8342 free (tmp_name);
8343}
8344
8345/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8346 return locations after sections have been laid out, using
8347 specially-named symbols. */
8348
8349void
8350bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8351 struct bfd_link_info *link_info)
8352{
8353 asection *sec;
8354 struct elf32_arm_link_hash_table *globals;
8355 char *tmp_name;
8356
8357 if (bfd_link_relocatable (link_info))
8358 return;
8359
8360 /* Skip if this bfd does not correspond to an ELF image. */
8361 if (! is_arm_elf (abfd))
8362 return;
8363
8364 globals = elf32_arm_hash_table (link_info);
8365 if (globals == NULL)
8366 return;
8367
8368 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8369 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8370
8371 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8372 {
8373 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8374 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8375
8376 for (; errnode != NULL; errnode = errnode->next)
8377 {
8378 struct elf_link_hash_entry *myh;
8379 bfd_vma vma;
8380
8381 switch (errnode->type)
8382 {
8383 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8384 /* Find veneer symbol. */
8385 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8386 errnode->u.b.veneer->u.v.id);
8387
8388 myh = elf_link_hash_lookup
8389 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8390
8391 if (myh == NULL)
4eca0228
AM		 8392 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8393 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8394
8395 vma = myh->root.u.def.section->output_section->vma
8396 + myh->root.u.def.section->output_offset
8397 + myh->root.u.def.value;
8398
8399 errnode->u.b.veneer->vma = vma;
8400 break;
8401
8402 case STM32L4XX_ERRATUM_VENEER:
8403 /* Find return location. */
8404 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8405 errnode->u.v.id);
8406
8407 myh = elf_link_hash_lookup
8408 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8409
8410 if (myh == NULL)
4eca0228
AM		 8411 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8412 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8413
8414 vma = myh->root.u.def.section->output_section->vma
8415 + myh->root.u.def.section->output_offset
8416 + myh->root.u.def.value;
8417
8418 errnode->u.v.branch->vma = vma;
8419 break;
8420
8421 default:
8422 abort ();
8423 }
8424 }
8425 }
8426
8427 free (tmp_name);
8428}
8429
8430static inline bfd_boolean
8431is_thumb2_ldmia (const insn32 insn)
8432{
8433 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8434 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8435 return (insn & 0xffd02000) == 0xe8900000;
8436}
8437
8438static inline bfd_boolean
8439is_thumb2_ldmdb (const insn32 insn)
8440{
8441 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8442 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8443 return (insn & 0xffd02000) == 0xe9100000;
8444}
8445
8446static inline bfd_boolean
8447is_thumb2_vldm (const insn32 insn)
8448{
8449 /* A6.5 Extension register load or store instruction
8450 A7.7.229
9239bbd3
CM		 8451 We look for SP 32-bit and DP 64-bit registers.
8452 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8453 <list> is consecutive 64-bit registers
8454 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8455 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8456 <list> is consecutive 32-bit registers
8457 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8458 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8459 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8460 return
9239bbd3
CM		 8461 (((insn & 0xfe100f00) == 0xec100b00) ||
8462 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8463 && /* (IA without !). */
8464 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8465 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8466 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8467 /* (DB with !). */
8468 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8469}
8470
8471/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8472 VLDM opcode and:
8473 - computes the number and the mode of memory accesses
8474 - decides if the replacement should be done:
8475 . replaces only if > 8-word accesses
8476 . or (testing purposes only) replaces all accesses. */
8477
8478static bfd_boolean
8479stm32l4xx_need_create_replacing_stub (const insn32 insn,
8480 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8481{
9239bbd3 8482 int nb_words = 0;
a504d23a
LA		 8483
8484 /* The field encoding the register list is the same for both LDMIA
8485 and LDMDB encodings. */
8486 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8487 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8488 else if (is_thumb2_vldm (insn))
9239bbd3 8489 nb_words = (insn & 0xff);
a504d23a
LA		 8490
8491 /* DEFAULT mode accounts for the real bug condition situation,
8492 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8493 return
9239bbd3 8494 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8495 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8496}
8497
8498/* Look for potentially-troublesome code sequences which might trigger
8499 the STM STM32L4XX erratum. */
8500
8501bfd_boolean
8502bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8503 struct bfd_link_info *link_info)
8504{
8505 asection *sec;
8506 bfd_byte *contents = NULL;
8507 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8508
8509 if (globals == NULL)
8510 return FALSE;
8511
8512 /* If we are only performing a partial link do not bother
8513 to construct any glue. */
8514 if (bfd_link_relocatable (link_info))
8515 return TRUE;
8516
8517 /* Skip if this bfd does not correspond to an ELF image. */
8518 if (! is_arm_elf (abfd))
8519 return TRUE;
8520
8521 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8522 return TRUE;
8523
8524 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8525 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8526 return TRUE;
8527
8528 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8529 {
8530 unsigned int i, span;
8531 struct _arm_elf_section_data *sec_data;
8532
8533 /* If we don't have executable progbits, we're not interested in this
8534 section. Also skip if section is to be excluded. */
8535 if (elf_section_type (sec) != SHT_PROGBITS
8536 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8537 || (sec->flags & SEC_EXCLUDE) != 0
8538 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8539 || sec->output_section == bfd_abs_section_ptr
8540 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8541 continue;
8542
8543 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8544
a504d23a
LA		 8545 if (sec_data->mapcount == 0)
8546 continue;
c7b8f16e 8547
a504d23a
LA		 8548 if (elf_section_data (sec)->this_hdr.contents != NULL)
8549 contents = elf_section_data (sec)->this_hdr.contents;
8550 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8551 goto error_return;
c7b8f16e 8552
a504d23a
LA		 8553 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8554 elf32_arm_compare_mapping);
c7b8f16e 8555
a504d23a
LA		 8556 for (span = 0; span < sec_data->mapcount; span++)
8557 {
8558 unsigned int span_start = sec_data->map[span].vma;
8559 unsigned int span_end = (span == sec_data->mapcount - 1)
8560 ? sec->size : sec_data->map[span + 1].vma;
8561 char span_type = sec_data->map[span].type;
8562 int itblock_current_pos = 0;
c7b8f16e 8563
a504d23a
LA		 8564 /* Only Thumb2 mode need be supported with this CM4 specific
8565 code, we should not encounter any arm mode eg span_type
8566 != 'a'. */
8567 if (span_type != 't')
8568 continue;
c7b8f16e 8569
a504d23a
LA		 8570 for (i = span_start; i < span_end;)
8571 {
8572 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8573 bfd_boolean insn_32bit = FALSE;
8574 bfd_boolean is_ldm = FALSE;
8575 bfd_boolean is_vldm = FALSE;
8576 bfd_boolean is_not_last_in_it_block = FALSE;
8577
8578 /* The first 16-bits of all 32-bit thumb2 instructions start
8579 with opcode[15..13]=0b111 and the encoded op1 can be anything
8580 except opcode[12..11]!=0b00.
8581 See 32-bit Thumb instruction encoding. */
8582 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8583 insn_32bit = TRUE;
c7b8f16e 8584
a504d23a
LA		 8585 /* Compute the predicate that tells if the instruction
8586 is concerned by the IT block
8587 - Creates an error if there is a ldm that is not
8588 last in the IT block thus cannot be replaced
8589 - Otherwise we can create a branch at the end of the
8590 IT block, it will be controlled naturally by IT
8591 with the proper pseudo-predicate
8592 - So the only interesting predicate is the one that
8593 tells that we are not on the last item of an IT
8594 block. */
8595 if (itblock_current_pos != 0)
8596 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8597
a504d23a
LA		 8598 if (insn_32bit)
8599 {
8600 /* Load the rest of the insn (in manual-friendly order). */
8601 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8602 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8603 is_vldm = is_thumb2_vldm (insn);
8604
8605 /* Veneers are created for (v)ldm depending on
8606 option flags and memory accesses conditions; but
8607 if the instruction is not the last instruction of
8608 an IT block, we cannot create a jump there, so we
8609 bail out. */
5025eb7c
AO		 8610 if ((is_ldm || is_vldm)
8611 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8612 (insn, globals->stm32l4xx_fix))
8613 {
8614 if (is_not_last_in_it_block)
8615 {
4eca0228 8616 _bfd_error_handler
695344c0 8617 /* xgettext:c-format */
d42c267e 8618 (_("%B(%A+%#x): error: multiple load detected"
63a5468a
AM		 8619 " in non-last IT block instruction :"
8620 " STM32L4XX veneer cannot be generated.\n"
8621 "Use gcc option -mrestrict-it to generate"
8622 " only one instruction per IT block.\n"),
d42c267e 8623 abfd, sec, i);
a504d23a
LA		 8624 }
8625 else
8626 {
8627 elf32_stm32l4xx_erratum_list *newerr =
8628 (elf32_stm32l4xx_erratum_list *)
8629 bfd_zmalloc
8630 (sizeof (elf32_stm32l4xx_erratum_list));
8631
8632 elf32_arm_section_data (sec)
8633 ->stm32l4xx_erratumcount += 1;
8634 newerr->u.b.insn = insn;
8635 /* We create only thumb branches. */
8636 newerr->type =
8637 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8638 record_stm32l4xx_erratum_veneer
8639 (link_info, newerr, abfd, sec,
8640 i,
8641 is_ldm ?
8642 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8643 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8644 newerr->vma = -1;
8645 newerr->next = sec_data->stm32l4xx_erratumlist;
8646 sec_data->stm32l4xx_erratumlist = newerr;
8647 }
8648 }
8649 }
8650 else
8651 {
8652 /* A7.7.37 IT p208
8653 IT blocks are only encoded in T1
8654 Encoding T1: IT{x{y{z}}} <firstcond>
8655 1 0 1 1 - 1 1 1 1 - firstcond - mask
8656 if mask = '0000' then see 'related encodings'
8657 We don't deal with UNPREDICTABLE, just ignore these.
8658 There can be no nested IT blocks so an IT block
8659 is naturally a new one for which it is worth
8660 computing its size. */
5025eb7c
AO		 8661 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8662 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8663 /* If we have a new IT block we compute its size. */
8664 if (is_newitblock)
8665 {
8666 /* Compute the number of instructions controlled
8667 by the IT block, it will be used to decide
8668 whether we are inside an IT block or not. */
8669 unsigned int mask = insn & 0x000f;
8670 itblock_current_pos = 4 - ctz (mask);
8671 }
8672 }
8673
8674 i += insn_32bit ? 4 : 2;
99059e56
RM		 8675 }
8676 }
a504d23a
LA		 8677
8678 if (contents != NULL
8679 && elf_section_data (sec)->this_hdr.contents != contents)
8680 free (contents);
8681 contents = NULL;
c7b8f16e 8682 }
906e58ca 8683
a504d23a
LA		 8684 return TRUE;
8685
8686error_return:
8687 if (contents != NULL
8688 && elf_section_data (sec)->this_hdr.contents != contents)
8689 free (contents);
c7b8f16e 8690
a504d23a
LA		 8691 return FALSE;
8692}
c7b8f16e 8693
eb043451
PB		 8694/* Set target relocation values needed during linking. */
8695
8696void
68c39892 8697bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8698 struct bfd_link_info *link_info,
68c39892 8699 struct elf32_arm_params *params)
eb043451
PB		 8700{
8701 struct elf32_arm_link_hash_table *globals;
8702
8703 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8704 if (globals == NULL)
8705 return;
eb043451 8706
68c39892
TP		 8707 globals->target1_is_rel = params->target1_is_rel;
8708 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8709 globals->target2_reloc = R_ARM_REL32;
68c39892 8710 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8711 globals->target2_reloc = R_ARM_ABS32;
68c39892 8712 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8713 globals->target2_reloc = R_ARM_GOT_PREL;
8714 else
8715 {
8716 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
68c39892 8717 params->target2_type);
eb043451 8718 }
68c39892
TP		 8719 globals->fix_v4bx = params->fix_v4bx;
8720 globals->use_blx |= params->use_blx;
8721 globals->vfp11_fix = params->vfp11_denorm_fix;
8722 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8723 globals->pic_veneer = params->pic_veneer;
8724 globals->fix_cortex_a8 = params->fix_cortex_a8;
8725 globals->fix_arm1176 = params->fix_arm1176;
8726 globals->cmse_implib = params->cmse_implib;
8727 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8728
0ffa91dd 8729 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8730 elf_arm_tdata (output_bfd)->no_enum_size_warning
8731 = params->no_enum_size_warning;
8732 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8733 = params->no_wchar_size_warning;
eb043451 8734}
eb043451 8735
12a0a0fd 8736/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8737
12a0a0fd
PB		 8738static void
8739insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8740{
8741 bfd_vma upper;
8742 bfd_vma lower;
8743 int reloc_sign;
8744
8745 BFD_ASSERT ((offset & 1) == 0);
8746
8747 upper = bfd_get_16 (abfd, insn);
8748 lower = bfd_get_16 (abfd, insn + 2);
8749 reloc_sign = (offset < 0) ? 1 : 0;
8750 upper = (upper & ~(bfd_vma) 0x7ff)
8751 | ((offset >> 12) & 0x3ff)
8752 | (reloc_sign << 10);
906e58ca 8753 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8754 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8755 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8756 | ((offset >> 1) & 0x7ff);
8757 bfd_put_16 (abfd, upper, insn);
8758 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8759}
8760
9b485d32
NC		 8761/* Thumb code calling an ARM function. */
8762
252b5132 8763static int
57e8b36a
NC		 8764elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8765 const char * name,
8766 bfd * input_bfd,
8767 bfd * output_bfd,
8768 asection * input_section,
8769 bfd_byte * hit_data,
8770 asection * sym_sec,
8771 bfd_vma offset,
8772 bfd_signed_vma addend,
f2a9dd69
DJ		 8773 bfd_vma val,
8774 char **error_message)
252b5132 8775{
bcbdc74c 8776 asection * s = 0;
dc810e39 8777 bfd_vma my_offset;
252b5132 8778 long int ret_offset;
bcbdc74c
NC		 8779 struct elf_link_hash_entry * myh;
8780 struct elf32_arm_link_hash_table * globals;
252b5132 8781
f2a9dd69 8782 myh = find_thumb_glue (info, name, error_message);
252b5132 8783 if (myh == NULL)
b34976b6 8784 return FALSE;
252b5132
RH		 8785
8786 globals = elf32_arm_hash_table (info);
252b5132
RH		 8787 BFD_ASSERT (globals != NULL);
8788 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8789
8790 my_offset = myh->root.u.def.value;
8791
3d4d4302
AM		 8792 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8793 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8794
8795 BFD_ASSERT (s != NULL);
8796 BFD_ASSERT (s->contents != NULL);
8797 BFD_ASSERT (s->output_section != NULL);
8798
8799 if ((my_offset & 0x01) == 0x01)
8800 {
8801 if (sym_sec != NULL
8802 && sym_sec->owner != NULL
8803 && !INTERWORK_FLAG (sym_sec->owner))
8804 {
4eca0228 8805 _bfd_error_handler
d003868e 8806 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8807 " first occurrence: %B: Thumb call to ARM"),
c08bb8dd 8808 sym_sec->owner, name, input_bfd);
252b5132 8809
b34976b6 8810 return FALSE;
252b5132
RH		 8811 }
8812
8813 --my_offset;
8814 myh->root.u.def.value = my_offset;
8815
52ab56c2
PB		 8816 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8817 s->contents + my_offset);
252b5132 8818
52ab56c2
PB		 8819 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8820 s->contents + my_offset + 2);
252b5132
RH		 8821
8822 ret_offset =
9b485d32
NC		 8823 /* Address of destination of the stub. */
8824 ((bfd_signed_vma) val)
252b5132 8825 - ((bfd_signed_vma)
57e8b36a
NC		 8826 /* Offset from the start of the current section
8827 to the start of the stubs. */
9b485d32
NC		 8828 (s->output_offset
8829 /* Offset of the start of this stub from the start of the stubs. */
8830 + my_offset
8831 /* Address of the start of the current section. */
8832 + s->output_section->vma)
8833 /* The branch instruction is 4 bytes into the stub. */
8834 + 4
8835 /* ARM branches work from the pc of the instruction + 8. */
8836 + 8);
252b5132 8837
52ab56c2
PB		 8838 put_arm_insn (globals, output_bfd,
8839 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8840 s->contents + my_offset + 4);
252b5132
RH		 8841 }
8842
8843 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8844
427bfd90
NC		 8845 /* Now go back and fix up the original BL insn to point to here. */
8846 ret_offset =
8847 /* Address of where the stub is located. */
8848 (s->output_section->vma + s->output_offset + my_offset)
8849 /* Address of where the BL is located. */
57e8b36a
NC		 8850 - (input_section->output_section->vma + input_section->output_offset
8851 + offset)
427bfd90
NC		 8852 /* Addend in the relocation. */
8853 - addend
8854 /* Biassing for PC-relative addressing. */
8855 - 8;
252b5132 8856
12a0a0fd 8857 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8858
b34976b6 8859 return TRUE;
252b5132
RH		 8860}
8861
a4fd1a8e 8862/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8863
a4fd1a8e
PB		 8864static struct elf_link_hash_entry *
8865elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8866 const char * name,
8867 bfd * input_bfd,
8868 bfd * output_bfd,
8869 asection * sym_sec,
8870 bfd_vma val,
8029a119
NC		 8871 asection * s,
8872 char ** error_message)
252b5132 8873{
dc810e39 8874 bfd_vma my_offset;
252b5132 8875 long int ret_offset;
bcbdc74c
NC		 8876 struct elf_link_hash_entry * myh;
8877 struct elf32_arm_link_hash_table * globals;
252b5132 8878
f2a9dd69 8879 myh = find_arm_glue (info, name, error_message);
252b5132 8880 if (myh == NULL)
a4fd1a8e 8881 return NULL;
252b5132
RH		 8882
8883 globals = elf32_arm_hash_table (info);
252b5132
RH		 8884 BFD_ASSERT (globals != NULL);
8885 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8886
8887 my_offset = myh->root.u.def.value;
252b5132
RH		 8888
8889 if ((my_offset & 0x01) == 0x01)
8890 {
8891 if (sym_sec != NULL
8892 && sym_sec->owner != NULL
8893 && !INTERWORK_FLAG (sym_sec->owner))
8894 {
4eca0228 8895 _bfd_error_handler
d003868e
AM		 8896 (_("%B(%s): warning: interworking not enabled.\n"
8897 " first occurrence: %B: arm call to thumb"),
c08bb8dd 8898 sym_sec->owner, name, input_bfd);
252b5132 8899 }
9b485d32 8900
252b5132
RH		 8901 --my_offset;
8902 myh->root.u.def.value = my_offset;
8903
0e1862bb
L		 8904 if (bfd_link_pic (info)
8905 || globals->root.is_relocatable_executable
27e55c4d 8906 || globals->pic_veneer)
8f6277f5
PB		 8907 {
8908 /* For relocatable objects we can't use absolute addresses,
8909 so construct the address from a relative offset. */
8910 /* TODO: If the offset is small it's probably worth
8911 constructing the address with adds. */
52ab56c2
PB		 8912 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8913 s->contents + my_offset);
8914 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8915 s->contents + my_offset + 4);
8916 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8917 s->contents + my_offset + 8);
8f6277f5
PB		 8918 /* Adjust the offset by 4 for the position of the add,
8919 and 8 for the pipeline offset. */
8920 ret_offset = (val - (s->output_offset
8921 + s->output_section->vma
8922 + my_offset + 12))
8923 | 1;
8924 bfd_put_32 (output_bfd, ret_offset,
8925 s->contents + my_offset + 12);
8926 }
26079076
PB		 8927 else if (globals->use_blx)
8928 {
8929 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8930 s->contents + my_offset);
8931
8932 /* It's a thumb address. Add the low order bit. */
8933 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8934 s->contents + my_offset + 4);
8935 }
8f6277f5
PB		 8936 else
8937 {
52ab56c2
PB		 8938 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8939 s->contents + my_offset);
252b5132 8940
52ab56c2
PB		 8941 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8942 s->contents + my_offset + 4);
252b5132 8943
8f6277f5
PB		 8944 /* It's a thumb address. Add the low order bit. */
8945 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8946 s->contents + my_offset + 8);
8029a119
NC		 8947
8948 my_offset += 12;
8f6277f5 8949 }
252b5132
RH		 8950 }
8951
8952 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8953
a4fd1a8e
PB		 8954 return myh;
8955}
8956
8957/* Arm code calling a Thumb function. */
8958
8959static int
8960elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8961 const char * name,
8962 bfd * input_bfd,
8963 bfd * output_bfd,
8964 asection * input_section,
8965 bfd_byte * hit_data,
8966 asection * sym_sec,
8967 bfd_vma offset,
8968 bfd_signed_vma addend,
f2a9dd69
DJ		 8969 bfd_vma val,
8970 char **error_message)
a4fd1a8e
PB		 8971{
8972 unsigned long int tmp;
8973 bfd_vma my_offset;
8974 asection * s;
8975 long int ret_offset;
8976 struct elf_link_hash_entry * myh;
8977 struct elf32_arm_link_hash_table * globals;
8978
8979 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8980 BFD_ASSERT (globals != NULL);
8981 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8982
3d4d4302
AM		 8983 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8984 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8985 BFD_ASSERT (s != NULL);
8986 BFD_ASSERT (s->contents != NULL);
8987 BFD_ASSERT (s->output_section != NULL);
8988
8989 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8990 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8991 if (!myh)
8992 return FALSE;
8993
8994 my_offset = myh->root.u.def.value;
252b5132
RH		 8995 tmp = bfd_get_32 (input_bfd, hit_data);
8996 tmp = tmp & 0xFF000000;
8997
9b485d32 8998 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 8999 ret_offset = (s->output_offset
9000 + my_offset
9001 + s->output_section->vma
9002 - (input_section->output_offset
9003 + input_section->output_section->vma
9004 + offset + addend)
9005 - 8);
9a5aca8c 9006
252b5132
RH		 9007 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9008
dc810e39 9009 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9010
b34976b6 9011 return TRUE;
252b5132
RH		 9012}
9013
a4fd1a8e
PB		 9014/* Populate Arm stub for an exported Thumb function. */
9015
9016static bfd_boolean
9017elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9018{
9019 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9020 asection * s;
9021 struct elf_link_hash_entry * myh;
9022 struct elf32_arm_link_hash_entry *eh;
9023 struct elf32_arm_link_hash_table * globals;
9024 asection *sec;
9025 bfd_vma val;
f2a9dd69 9026 char *error_message;
a4fd1a8e 9027
906e58ca 9028 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9029 /* Allocate stubs for exported Thumb functions on v4t. */
9030 if (eh->export_glue == NULL)
9031 return TRUE;
9032
9033 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9034 BFD_ASSERT (globals != NULL);
9035 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9036
3d4d4302
AM		 9037 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9038 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9039 BFD_ASSERT (s != NULL);
9040 BFD_ASSERT (s->contents != NULL);
9041 BFD_ASSERT (s->output_section != NULL);
9042
9043 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9044
9045 BFD_ASSERT (sec->output_section != NULL);
9046
a4fd1a8e
PB		 9047 val = eh->export_glue->root.u.def.value + sec->output_offset
9048 + sec->output_section->vma;
8029a119 9049
a4fd1a8e
PB		 9050 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9051 h->root.u.def.section->owner,
f2a9dd69
DJ		 9052 globals->obfd, sec, val, s,
9053 &error_message);
a4fd1a8e
PB		 9054 BFD_ASSERT (myh);
9055 return TRUE;
9056}
9057
845b51d6
PB		 9058/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9059
9060static bfd_vma
9061elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9062{
9063 bfd_byte *p;
9064 bfd_vma glue_addr;
9065 asection *s;
9066 struct elf32_arm_link_hash_table *globals;
9067
9068 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9069 BFD_ASSERT (globals != NULL);
9070 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9071
3d4d4302
AM		 9072 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9073 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9074 BFD_ASSERT (s != NULL);
9075 BFD_ASSERT (s->contents != NULL);
9076 BFD_ASSERT (s->output_section != NULL);
9077
9078 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9079
9080 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9081
9082 if ((globals->bx_glue_offset[reg] & 1) == 0)
9083 {
9084 p = s->contents + glue_addr;
9085 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9086 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9087 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9088 globals->bx_glue_offset[reg] |= 1;
9089 }
9090
9091 return glue_addr + s->output_section->vma + s->output_offset;
9092}
9093
a4fd1a8e
PB		 9094/* Generate Arm stubs for exported Thumb symbols. */
9095static void
906e58ca 9096elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9097 struct bfd_link_info *link_info)
9098{
9099 struct elf32_arm_link_hash_table * globals;
9100
8029a119
NC		 9101 if (link_info == NULL)
9102 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9103 return;
9104
9105 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9106 if (globals == NULL)
9107 return;
9108
84c08195
PB		 9109 /* If blx is available then exported Thumb symbols are OK and there is
9110 nothing to do. */
a4fd1a8e
PB		 9111 if (globals->use_blx)
9112 return;
9113
9114 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9115 link_info);
9116}
9117
47beaa6a
RS		 9118/* Reserve space for COUNT dynamic relocations in relocation selection
9119 SRELOC. */
9120
9121static void
9122elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9123 bfd_size_type count)
9124{
9125 struct elf32_arm_link_hash_table *htab;
9126
9127 htab = elf32_arm_hash_table (info);
9128 BFD_ASSERT (htab->root.dynamic_sections_created);
9129 if (sreloc == NULL)
9130 abort ();
9131 sreloc->size += RELOC_SIZE (htab) * count;
9132}
9133
34e77a92
RS		 9134/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9135 dynamic, the relocations should go in SRELOC, otherwise they should
9136 go in the special .rel.iplt section. */
9137
9138static void
9139elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9140 bfd_size_type count)
9141{
9142 struct elf32_arm_link_hash_table *htab;
9143
9144 htab = elf32_arm_hash_table (info);
9145 if (!htab->root.dynamic_sections_created)
9146 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9147 else
9148 {
9149 BFD_ASSERT (sreloc != NULL);
9150 sreloc->size += RELOC_SIZE (htab) * count;
9151 }
9152}
9153
47beaa6a
RS		 9154/* Add relocation REL to the end of relocation section SRELOC. */
9155
9156static void
9157elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9158 asection *sreloc, Elf_Internal_Rela *rel)
9159{
9160 bfd_byte *loc;
9161 struct elf32_arm_link_hash_table *htab;
9162
9163 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9164 if (!htab->root.dynamic_sections_created
9165 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9166 sreloc = htab->root.irelplt;
47beaa6a
RS		 9167 if (sreloc == NULL)
9168 abort ();
9169 loc = sreloc->contents;
9170 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9171 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9172 abort ();
9173 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9174}
9175
34e77a92
RS		 9176/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9177 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9178 to .plt. */
9179
9180static void
9181elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9182 bfd_boolean is_iplt_entry,
9183 union gotplt_union *root_plt,
9184 struct arm_plt_info *arm_plt)
9185{
9186 struct elf32_arm_link_hash_table *htab;
9187 asection *splt;
9188 asection *sgotplt;
9189
9190 htab = elf32_arm_hash_table (info);
9191
9192 if (is_iplt_entry)
9193 {
9194 splt = htab->root.iplt;
9195 sgotplt = htab->root.igotplt;
9196
99059e56
RM		 9197 /* NaCl uses a special first entry in .iplt too. */
9198 if (htab->nacl_p && splt->size == 0)
9199 splt->size += htab->plt_header_size;
9200
34e77a92
RS		 9201 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9202 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9203 }
9204 else
9205 {
9206 splt = htab->root.splt;
9207 sgotplt = htab->root.sgotplt;
9208
9209 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9210 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9211
9212 /* If this is the first .plt entry, make room for the special
9213 first entry. */
9214 if (splt->size == 0)
9215 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9216
9217 htab->next_tls_desc_index++;
34e77a92
RS		 9218 }
9219
9220 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9221 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9222 splt->size += PLT_THUMB_STUB_SIZE;
9223 root_plt->offset = splt->size;
9224 splt->size += htab->plt_entry_size;
9225
9226 if (!htab->symbian_p)
9227 {
9228 /* We also need to make an entry in the .got.plt section, which
9229 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9230 if (is_iplt_entry)
9231 arm_plt->got_offset = sgotplt->size;
9232 else
9233 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9234 sgotplt->size += 4;
9235 }
9236}
9237
b38cadfb
NC		 9238static bfd_vma
9239arm_movw_immediate (bfd_vma value)
9240{
9241 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9242}
9243
9244static bfd_vma
9245arm_movt_immediate (bfd_vma value)
9246{
9247 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9248}
9249
34e77a92
RS		 9250/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9251 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9252 Otherwise, DYNINDX is the index of the symbol in the dynamic
9253 symbol table and SYM_VALUE is undefined.
9254
9255 ROOT_PLT points to the offset of the PLT entry from the start of its
9256 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9257 bookkeeping information.
34e77a92 9258
57460bcf
NC		 9259 Returns FALSE if there was a problem. */
9260
9261static bfd_boolean
34e77a92
RS		 9262elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9263 union gotplt_union *root_plt,
9264 struct arm_plt_info *arm_plt,
9265 int dynindx, bfd_vma sym_value)
9266{
9267 struct elf32_arm_link_hash_table *htab;
9268 asection *sgot;
9269 asection *splt;
9270 asection *srel;
9271 bfd_byte *loc;
9272 bfd_vma plt_index;
9273 Elf_Internal_Rela rel;
9274 bfd_vma plt_header_size;
9275 bfd_vma got_header_size;
9276
9277 htab = elf32_arm_hash_table (info);
9278
9279 /* Pick the appropriate sections and sizes. */
9280 if (dynindx == -1)
9281 {
9282 splt = htab->root.iplt;
9283 sgot = htab->root.igotplt;
9284 srel = htab->root.irelplt;
9285
9286 /* There are no reserved entries in .igot.plt, and no special
9287 first entry in .iplt. */
9288 got_header_size = 0;
9289 plt_header_size = 0;
9290 }
9291 else
9292 {
9293 splt = htab->root.splt;
9294 sgot = htab->root.sgotplt;
9295 srel = htab->root.srelplt;
9296
9297 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9298 plt_header_size = htab->plt_header_size;
9299 }
9300 BFD_ASSERT (splt != NULL && srel != NULL);
9301
9302 /* Fill in the entry in the procedure linkage table. */
9303 if (htab->symbian_p)
9304 {
9305 BFD_ASSERT (dynindx >= 0);
9306 put_arm_insn (htab, output_bfd,
9307 elf32_arm_symbian_plt_entry[0],
9308 splt->contents + root_plt->offset);
9309 bfd_put_32 (output_bfd,
9310 elf32_arm_symbian_plt_entry[1],
9311 splt->contents + root_plt->offset + 4);
9312
9313 /* Fill in the entry in the .rel.plt section. */
9314 rel.r_offset = (splt->output_section->vma
9315 + splt->output_offset
9316 + root_plt->offset + 4);
9317 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9318
9319 /* Get the index in the procedure linkage table which
9320 corresponds to this symbol. This is the index of this symbol
9321 in all the symbols for which we are making plt entries. The
9322 first entry in the procedure linkage table is reserved. */
9323 plt_index = ((root_plt->offset - plt_header_size)
9324 / htab->plt_entry_size);
9325 }
9326 else
9327 {
9328 bfd_vma got_offset, got_address, plt_address;
9329 bfd_vma got_displacement, initial_got_entry;
9330 bfd_byte * ptr;
9331
9332 BFD_ASSERT (sgot != NULL);
9333
9334 /* Get the offset into the .(i)got.plt table of the entry that
9335 corresponds to this function. */
9336 got_offset = (arm_plt->got_offset & -2);
9337
9338 /* Get the index in the procedure linkage table which
9339 corresponds to this symbol. This is the index of this symbol
9340 in all the symbols for which we are making plt entries.
9341 After the reserved .got.plt entries, all symbols appear in
9342 the same order as in .plt. */
9343 plt_index = (got_offset - got_header_size) / 4;
9344
9345 /* Calculate the address of the GOT entry. */
9346 got_address = (sgot->output_section->vma
9347 + sgot->output_offset
9348 + got_offset);
9349
9350 /* ...and the address of the PLT entry. */
9351 plt_address = (splt->output_section->vma
9352 + splt->output_offset
9353 + root_plt->offset);
9354
9355 ptr = splt->contents + root_plt->offset;
0e1862bb 9356 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9357 {
9358 unsigned int i;
9359 bfd_vma val;
9360
9361 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9362 {
9363 val = elf32_arm_vxworks_shared_plt_entry[i];
9364 if (i == 2)
9365 val |= got_address - sgot->output_section->vma;
9366 if (i == 5)
9367 val |= plt_index * RELOC_SIZE (htab);
9368 if (i == 2 || i == 5)
9369 bfd_put_32 (output_bfd, val, ptr);
9370 else
9371 put_arm_insn (htab, output_bfd, val, ptr);
9372 }
9373 }
9374 else if (htab->vxworks_p)
9375 {
9376 unsigned int i;
9377 bfd_vma val;
9378
9379 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9380 {
9381 val = elf32_arm_vxworks_exec_plt_entry[i];
9382 if (i == 2)
9383 val |= got_address;
9384 if (i == 4)
9385 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9386 if (i == 5)
9387 val |= plt_index * RELOC_SIZE (htab);
9388 if (i == 2 || i == 5)
9389 bfd_put_32 (output_bfd, val, ptr);
9390 else
9391 put_arm_insn (htab, output_bfd, val, ptr);
9392 }
9393
9394 loc = (htab->srelplt2->contents
9395 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9396
9397 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9398 referencing the GOT for this PLT entry. */
9399 rel.r_offset = plt_address + 8;
9400 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9401 rel.r_addend = got_offset;
9402 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9403 loc += RELOC_SIZE (htab);
9404
9405 /* Create the R_ARM_ABS32 relocation referencing the
9406 beginning of the PLT for this GOT entry. */
9407 rel.r_offset = got_address;
9408 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9409 rel.r_addend = 0;
9410 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9411 }
b38cadfb
NC		 9412 else if (htab->nacl_p)
9413 {
9414 /* Calculate the displacement between the PLT slot and the
9415 common tail that's part of the special initial PLT slot. */
6034aab8 9416 int32_t tail_displacement
b38cadfb
NC		 9417 = ((splt->output_section->vma + splt->output_offset
9418 + ARM_NACL_PLT_TAIL_OFFSET)
9419 - (plt_address + htab->plt_entry_size + 4));
9420 BFD_ASSERT ((tail_displacement & 3) == 0);
9421 tail_displacement >>= 2;
9422
9423 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9424 || (-tail_displacement & 0xff000000) == 0);
9425
9426 /* Calculate the displacement between the PLT slot and the entry
9427 in the GOT. The offset accounts for the value produced by
9428 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9429 got_displacement = (got_address
99059e56 9430 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9431
9432 /* NaCl does not support interworking at all. */
9433 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9434
9435 put_arm_insn (htab, output_bfd,
9436 elf32_arm_nacl_plt_entry[0]
9437 | arm_movw_immediate (got_displacement),
9438 ptr + 0);
9439 put_arm_insn (htab, output_bfd,
9440 elf32_arm_nacl_plt_entry[1]
9441 | arm_movt_immediate (got_displacement),
9442 ptr + 4);
9443 put_arm_insn (htab, output_bfd,
9444 elf32_arm_nacl_plt_entry[2],
9445 ptr + 8);
9446 put_arm_insn (htab, output_bfd,
9447 elf32_arm_nacl_plt_entry[3]
9448 | (tail_displacement & 0x00ffffff),
9449 ptr + 12);
9450 }
57460bcf
NC		 9451 else if (using_thumb_only (htab))
9452 {
eed94f8f 9453 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9454 if (!using_thumb2 (htab))
eed94f8f
NC		 9455 {
9456 /* FIXME: We ought to be able to generate thumb-1 PLT
9457 instructions... */
9458 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9459 output_bfd);
9460 return FALSE;
9461 }
57460bcf 9462
eed94f8f
NC		 9463 /* Calculate the displacement between the PLT slot and the entry in
9464 the GOT. The 12-byte offset accounts for the value produced by
9465 adding to pc in the 3rd instruction of the PLT stub. */
9466 got_displacement = got_address - (plt_address + 12);
9467
9468 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9469 instead of 'put_thumb_insn'. */
9470 put_arm_insn (htab, output_bfd,
9471 elf32_thumb2_plt_entry[0]
9472 | ((got_displacement & 0x000000ff) << 16)
9473 | ((got_displacement & 0x00000700) << 20)
9474 | ((got_displacement & 0x00000800) >> 1)
9475 | ((got_displacement & 0x0000f000) >> 12),
9476 ptr + 0);
9477 put_arm_insn (htab, output_bfd,
9478 elf32_thumb2_plt_entry[1]
9479 | ((got_displacement & 0x00ff0000) )
9480 | ((got_displacement & 0x07000000) << 4)
9481 | ((got_displacement & 0x08000000) >> 17)
9482 | ((got_displacement & 0xf0000000) >> 28),
9483 ptr + 4);
9484 put_arm_insn (htab, output_bfd,
9485 elf32_thumb2_plt_entry[2],
9486 ptr + 8);
9487 put_arm_insn (htab, output_bfd,
9488 elf32_thumb2_plt_entry[3],
9489 ptr + 12);
57460bcf 9490 }
34e77a92
RS		 9491 else
9492 {
9493 /* Calculate the displacement between the PLT slot and the
9494 entry in the GOT. The eight-byte offset accounts for the
9495 value produced by adding to pc in the first instruction
9496 of the PLT stub. */
9497 got_displacement = got_address - (plt_address + 8);
9498
34e77a92
RS		 9499 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9500 {
9501 put_thumb_insn (htab, output_bfd,
9502 elf32_arm_plt_thumb_stub[0], ptr - 4);
9503 put_thumb_insn (htab, output_bfd,
9504 elf32_arm_plt_thumb_stub[1], ptr - 2);
9505 }
9506
1db37fe6
YG		 9507 if (!elf32_arm_use_long_plt_entry)
9508 {
9509 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9510
9511 put_arm_insn (htab, output_bfd,
9512 elf32_arm_plt_entry_short[0]
9513 | ((got_displacement & 0x0ff00000) >> 20),
9514 ptr + 0);
9515 put_arm_insn (htab, output_bfd,
9516 elf32_arm_plt_entry_short[1]
9517 | ((got_displacement & 0x000ff000) >> 12),
9518 ptr+ 4);
9519 put_arm_insn (htab, output_bfd,
9520 elf32_arm_plt_entry_short[2]
9521 | (got_displacement & 0x00000fff),
9522 ptr + 8);
34e77a92 9523#ifdef FOUR_WORD_PLT
1db37fe6 9524 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9525#endif
1db37fe6
YG		 9526 }
9527 else
9528 {
9529 put_arm_insn (htab, output_bfd,
9530 elf32_arm_plt_entry_long[0]
9531 | ((got_displacement & 0xf0000000) >> 28),
9532 ptr + 0);
9533 put_arm_insn (htab, output_bfd,
9534 elf32_arm_plt_entry_long[1]
9535 | ((got_displacement & 0x0ff00000) >> 20),
9536 ptr + 4);
9537 put_arm_insn (htab, output_bfd,
9538 elf32_arm_plt_entry_long[2]
9539 | ((got_displacement & 0x000ff000) >> 12),
9540 ptr+ 8);
9541 put_arm_insn (htab, output_bfd,
9542 elf32_arm_plt_entry_long[3]
9543 | (got_displacement & 0x00000fff),
9544 ptr + 12);
9545 }
34e77a92
RS		 9546 }
9547
9548 /* Fill in the entry in the .rel(a).(i)plt section. */
9549 rel.r_offset = got_address;
9550 rel.r_addend = 0;
9551 if (dynindx == -1)
9552 {
9553 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9554 The dynamic linker or static executable then calls SYM_VALUE
9555 to determine the correct run-time value of the .igot.plt entry. */
9556 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9557 initial_got_entry = sym_value;
9558 }
9559 else
9560 {
9561 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9562 initial_got_entry = (splt->output_section->vma
9563 + splt->output_offset);
9564 }
9565
9566 /* Fill in the entry in the global offset table. */
9567 bfd_put_32 (output_bfd, initial_got_entry,
9568 sgot->contents + got_offset);
9569 }
9570
aba8c3de
WN		 9571 if (dynindx == -1)
9572 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9573 else
9574 {
9575 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9576 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9577 }
57460bcf
NC		 9578
9579 return TRUE;
34e77a92
RS		 9580}
9581
eb043451
PB		 9582/* Some relocations map to different relocations depending on the
9583 target. Return the real relocation. */
8029a119 9584
eb043451
PB		 9585static int
9586arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9587 int r_type)
9588{
9589 switch (r_type)
9590 {
9591 case R_ARM_TARGET1:
9592 if (globals->target1_is_rel)
9593 return R_ARM_REL32;
9594 else
9595 return R_ARM_ABS32;
9596
9597 case R_ARM_TARGET2:
9598 return globals->target2_reloc;
9599
9600 default:
9601 return r_type;
9602 }
9603}
eb043451 9604
ba93b8ac
DJ		 9605/* Return the base VMA address which should be subtracted from real addresses
9606 when resolving @dtpoff relocation.
9607 This is PT_TLS segment p_vaddr. */
9608
9609static bfd_vma
9610dtpoff_base (struct bfd_link_info *info)
9611{
9612 /* If tls_sec is NULL, we should have signalled an error already. */
9613 if (elf_hash_table (info)->tls_sec == NULL)
9614 return 0;
9615 return elf_hash_table (info)->tls_sec->vma;
9616}
9617
9618/* Return the relocation value for @tpoff relocation
9619 if STT_TLS virtual address is ADDRESS. */
9620
9621static bfd_vma
9622tpoff (struct bfd_link_info *info, bfd_vma address)
9623{
9624 struct elf_link_hash_table *htab = elf_hash_table (info);
9625 bfd_vma base;
9626
9627 /* If tls_sec is NULL, we should have signalled an error already. */
9628 if (htab->tls_sec == NULL)
9629 return 0;
9630 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9631 return address - htab->tls_sec->vma + base;
9632}
9633
00a97672
RS		 9634/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9635 VALUE is the relocation value. */
9636
9637static bfd_reloc_status_type
9638elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9639{
9640 if (value > 0xfff)
9641 return bfd_reloc_overflow;
9642
9643 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9644 bfd_put_32 (abfd, value, data);
9645 return bfd_reloc_ok;
9646}
9647
0855e32b
NS		 9648/* Handle TLS relaxations. Relaxing is possible for symbols that use
9649 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9650 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9651
9652 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9653 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9654 case of error.
9655
9656 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9657 the pre-relaxed code. It would be nice if the relocs were updated
9658 to match the optimization. */
0855e32b 9659
b38cadfb 9660static bfd_reloc_status_type
0855e32b 9661elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9662 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9663 Elf_Internal_Rela *rel, unsigned long is_local)
9664{
9665 unsigned long insn;
b38cadfb 9666
0855e32b
NS		 9667 switch (ELF32_R_TYPE (rel->r_info))
9668 {
9669 default:
9670 return bfd_reloc_notsupported;
b38cadfb 9671
0855e32b
NS		 9672 case R_ARM_TLS_GOTDESC:
9673 if (is_local)
9674 insn = 0;
9675 else
9676 {
9677 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9678 if (insn & 1)
9679 insn -= 5; /* THUMB */
9680 else
9681 insn -= 8; /* ARM */
9682 }
9683 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9684 return bfd_reloc_continue;
9685
9686 case R_ARM_THM_TLS_DESCSEQ:
9687 /* Thumb insn. */
9688 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9689 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9690 {
9691 if (is_local)
9692 /* nop */
9693 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9694 }
9695 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9696 {
9697 if (is_local)
9698 /* nop */
9699 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9700 else
9701 /* ldr rx,[ry] */
9702 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9703 }
9704 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9705 {
9706 if (is_local)
9707 /* nop */
9708 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9709 else
9710 /* mov r0, rx */
9711 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9712 contents + rel->r_offset);
9713 }
9714 else
9715 {
9716 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9717 /* It's a 32 bit instruction, fetch the rest of it for
9718 error generation. */
9719 insn = (insn << 16)
9720 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9721 _bfd_error_handler
695344c0 9722 /* xgettext:c-format */
d42c267e
AM		 9723 (_("%B(%A+%#Lx): unexpected Thumb instruction '%#lx' in TLS trampoline"),
9724 input_bfd, input_sec, rel->r_offset, insn);
0855e32b
NS		 9725 return bfd_reloc_notsupported;
9726 }
9727 break;
b38cadfb 9728
0855e32b
NS		 9729 case R_ARM_TLS_DESCSEQ:
9730 /* arm insn. */
9731 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9732 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9733 {
9734 if (is_local)
9735 /* mov rx, ry */
9736 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9737 contents + rel->r_offset);
9738 }
9739 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9740 {
9741 if (is_local)
9742 /* nop */
9743 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9744 else
9745 /* ldr rx,[ry] */
9746 bfd_put_32 (input_bfd, insn & 0xfffff000,
9747 contents + rel->r_offset);
9748 }
9749 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9750 {
9751 if (is_local)
9752 /* nop */
9753 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9754 else
9755 /* mov r0, rx */
9756 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9757 contents + rel->r_offset);
9758 }
9759 else
9760 {
4eca0228 9761 _bfd_error_handler
695344c0 9762 /* xgettext:c-format */
d42c267e
AM		 9763 (_("%B(%A+%#Lx): unexpected ARM instruction '%#lx' in TLS trampoline"),
9764 input_bfd, input_sec, rel->r_offset, insn);
0855e32b
NS		 9765 return bfd_reloc_notsupported;
9766 }
9767 break;
9768
9769 case R_ARM_TLS_CALL:
9770 /* GD->IE relaxation, turn the instruction into 'nop' or
9771 'ldr r0, [pc,r0]' */
9772 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9773 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9774 break;
b38cadfb 9775
0855e32b 9776 case R_ARM_THM_TLS_CALL:
6a631e86 9777 /* GD->IE relaxation. */
0855e32b
NS		 9778 if (!is_local)
9779 /* add r0,pc; ldr r0, [r0] */
9780 insn = 0x44786800;
60a019a0 9781 else if (using_thumb2 (globals))
0855e32b
NS		 9782 /* nop.w */
9783 insn = 0xf3af8000;
9784 else
9785 /* nop; nop */
9786 insn = 0xbf00bf00;
b38cadfb 9787
0855e32b
NS		 9788 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9789 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9790 break;
9791 }
9792 return bfd_reloc_ok;
9793}
9794
4962c51a
MS		 9795/* For a given value of n, calculate the value of G_n as required to
9796 deal with group relocations. We return it in the form of an
9797 encoded constant-and-rotation, together with the final residual. If n is
9798 specified as less than zero, then final_residual is filled with the
9799 input value and no further action is performed. */
9800
9801static bfd_vma
9802calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9803{
9804 int current_n;
9805 bfd_vma g_n;
9806 bfd_vma encoded_g_n = 0;
9807 bfd_vma residual = value; /* Also known as Y_n. */
9808
9809 for (current_n = 0; current_n <= n; current_n++)
9810 {
9811 int shift;
9812
9813 /* Calculate which part of the value to mask. */
9814 if (residual == 0)
99059e56 9815 shift = 0;
4962c51a 9816 else
99059e56
RM		 9817 {
9818 int msb;
9819
9820 /* Determine the most significant bit in the residual and
9821 align the resulting value to a 2-bit boundary. */
9822 for (msb = 30; msb >= 0; msb -= 2)
9823 if (residual & (3 << msb))
9824 break;
9825
9826 /* The desired shift is now (msb - 6), or zero, whichever
9827 is the greater. */
9828 shift = msb - 6;
9829 if (shift < 0)
9830 shift = 0;
9831 }
4962c51a
MS		 9832
9833 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9834 g_n = residual & (0xff << shift);
9835 encoded_g_n = (g_n >> shift)
99059e56 9836 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9837
9838 /* Calculate the residual for the next time around. */
9839 residual &= ~g_n;
9840 }
9841
9842 *final_residual = residual;
9843
9844 return encoded_g_n;
9845}
9846
9847/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9848 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9849
4962c51a 9850static int
906e58ca 9851identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9852{
9853 int opcode = insn & 0x1e00000;
9854
9855 if (opcode == 1 << 23) /* ADD */
9856 return 1;
9857
9858 if (opcode == 1 << 22) /* SUB */
9859 return -1;
9860
9861 return 0;
9862}
9863
252b5132 9864/* Perform a relocation as part of a final link. */
9b485d32 9865
252b5132 9866static bfd_reloc_status_type
57e8b36a
NC		 9867elf32_arm_final_link_relocate (reloc_howto_type * howto,
9868 bfd * input_bfd,
9869 bfd * output_bfd,
9870 asection * input_section,
9871 bfd_byte * contents,
9872 Elf_Internal_Rela * rel,
9873 bfd_vma value,
9874 struct bfd_link_info * info,
9875 asection * sym_sec,
9876 const char * sym_name,
34e77a92
RS		 9877 unsigned char st_type,
9878 enum arm_st_branch_type branch_type,
0945cdfd 9879 struct elf_link_hash_entry * h,
f2a9dd69 9880 bfd_boolean * unresolved_reloc_p,
8029a119 9881 char ** error_message)
252b5132
RH		 9882{
9883 unsigned long r_type = howto->type;
9884 unsigned long r_symndx;
9885 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9886 bfd_vma * local_got_offsets;
0855e32b 9887 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9888 asection * sgot;
9889 asection * splt;
252b5132 9890 asection * sreloc = NULL;
362d30a1 9891 asection * srelgot;
252b5132 9892 bfd_vma addend;
ba96a88f 9893 bfd_signed_vma signed_addend;
34e77a92
RS		 9894 unsigned char dynreloc_st_type;
9895 bfd_vma dynreloc_value;
ba96a88f 9896 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9897 struct elf32_arm_link_hash_entry *eh;
9898 union gotplt_union *root_plt;
9899 struct arm_plt_info *arm_plt;
9900 bfd_vma plt_offset;
9901 bfd_vma gotplt_offset;
9902 bfd_boolean has_iplt_entry;
95b03e4a 9903 bfd_boolean resolved_to_zero;
f21f3fe0 9904
9c504268 9905 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9906 if (globals == NULL)
9907 return bfd_reloc_notsupported;
9c504268 9908
0ffa91dd 9909 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 9910 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 9911
9912 /* Some relocation types map to different relocations depending on the
9c504268 9913 target. We pick the right one here. */
eb043451 9914 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9915
9916 /* It is possible to have linker relaxations on some TLS access
9917 models. Update our information here. */
9918 r_type = elf32_arm_tls_transition (info, r_type, h);
9919
eb043451
PB		 9920 if (r_type != howto->type)
9921 howto = elf32_arm_howto_from_type (r_type);
9c504268 9922
34e77a92 9923 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9924 sgot = globals->root.sgot;
252b5132 9925 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9926 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9927
34e77a92
RS		 9928 if (globals->root.dynamic_sections_created)
9929 srelgot = globals->root.srelgot;
9930 else
9931 srelgot = NULL;
9932
252b5132
RH		 9933 r_symndx = ELF32_R_SYM (rel->r_info);
9934
4e7fd91e 9935 if (globals->use_rel)
ba96a88f 9936 {
4e7fd91e
PB		 9937 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9938
9939 if (addend & ((howto->src_mask + 1) >> 1))
9940 {
9941 signed_addend = -1;
9942 signed_addend &= ~ howto->src_mask;
9943 signed_addend |= addend;
9944 }
9945 else
9946 signed_addend = addend;
ba96a88f
NC		 9947 }
9948 else
4e7fd91e 9949 addend = signed_addend = rel->r_addend;
f21f3fe0 9950
39f21624
NC		 9951 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9952 are resolving a function call relocation. */
9953 if (using_thumb_only (globals)
9954 && (r_type == R_ARM_THM_CALL
9955 || r_type == R_ARM_THM_JUMP24)
9956 && branch_type == ST_BRANCH_TO_ARM)
9957 branch_type = ST_BRANCH_TO_THUMB;
9958
34e77a92
RS		 9959 /* Record the symbol information that should be used in dynamic
9960 relocations. */
9961 dynreloc_st_type = st_type;
9962 dynreloc_value = value;
9963 if (branch_type == ST_BRANCH_TO_THUMB)
9964 dynreloc_value |= 1;
9965
9966 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9967 VALUE appropriately for relocations that we resolve at link time. */
9968 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9969 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9970 &arm_plt)
34e77a92
RS		 9971 && root_plt->offset != (bfd_vma) -1)
9972 {
9973 plt_offset = root_plt->offset;
9974 gotplt_offset = arm_plt->got_offset;
9975
9976 if (h == NULL || eh->is_iplt)
9977 {
9978 has_iplt_entry = TRUE;
9979 splt = globals->root.iplt;
9980
9981 /* Populate .iplt entries here, because not all of them will
9982 be seen by finish_dynamic_symbol. The lower bit is set if
9983 we have already populated the entry. */
9984 if (plt_offset & 1)
9985 plt_offset--;
9986 else
9987 {
57460bcf
NC		 9988 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9989 -1, dynreloc_value))
9990 root_plt->offset |= 1;
9991 else
9992 return bfd_reloc_notsupported;
34e77a92
RS		 9993 }
9994
9995 /* Static relocations always resolve to the .iplt entry. */
9996 st_type = STT_FUNC;
9997 value = (splt->output_section->vma
9998 + splt->output_offset
9999 + plt_offset);
10000 branch_type = ST_BRANCH_TO_ARM;
10001
10002 /* If there are non-call relocations that resolve to the .iplt
10003 entry, then all dynamic ones must too. */
10004 if (arm_plt->noncall_refcount != 0)
10005 {
10006 dynreloc_st_type = st_type;
10007 dynreloc_value = value;
10008 }
10009 }
10010 else
10011 /* We populate the .plt entry in finish_dynamic_symbol. */
10012 splt = globals->root.splt;
10013 }
10014 else
10015 {
10016 splt = NULL;
10017 plt_offset = (bfd_vma) -1;
10018 gotplt_offset = (bfd_vma) -1;
10019 }
10020
95b03e4a
L		 10021 resolved_to_zero = (h != NULL
10022 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10023
252b5132
RH		 10024 switch (r_type)
10025 {
10026 case R_ARM_NONE:
28a094c2
DJ		 10027 /* We don't need to find a value for this symbol. It's just a
10028 marker. */
10029 *unresolved_reloc_p = FALSE;
252b5132
RH		 10030 return bfd_reloc_ok;
10031
00a97672
RS		 10032 case R_ARM_ABS12:
10033 if (!globals->vxworks_p)
10034 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10035 /* Fall through. */
00a97672 10036
252b5132
RH		 10037 case R_ARM_PC24:
10038 case R_ARM_ABS32:
bb224fc3 10039 case R_ARM_ABS32_NOI:
252b5132 10040 case R_ARM_REL32:
bb224fc3 10041 case R_ARM_REL32_NOI:
5b5bb741
PB		 10042 case R_ARM_CALL:
10043 case R_ARM_JUMP24:
dfc5f959 10044 case R_ARM_XPC25:
eb043451 10045 case R_ARM_PREL31:
7359ea65 10046 case R_ARM_PLT32:
7359ea65
DJ		 10047 /* Handle relocations which should use the PLT entry. ABS32/REL32
10048 will use the symbol's value, which may point to a PLT entry, but we
10049 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10050 branches in this object should go to it, except if the PLT is too
10051 far away, in which case a long branch stub should be inserted. */
bb224fc3 10052 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10053 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10054 && r_type != R_ARM_CALL
10055 && r_type != R_ARM_JUMP24
10056 && r_type != R_ARM_PLT32)
34e77a92 10057 && plt_offset != (bfd_vma) -1)
7359ea65 10058 {
34e77a92
RS		 10059 /* If we've created a .plt section, and assigned a PLT entry
10060 to this function, it must either be a STT_GNU_IFUNC reference
10061 or not be known to bind locally. In other cases, we should
10062 have cleared the PLT entry by now. */
10063 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10064
10065 value = (splt->output_section->vma
10066 + splt->output_offset
34e77a92 10067 + plt_offset);
0945cdfd 10068 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10069 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10070 contents, rel->r_offset, value,
00a97672 10071 rel->r_addend);
7359ea65
DJ		 10072 }
10073
67687978
PB		 10074 /* When generating a shared object or relocatable executable, these
10075 relocations are copied into the output file to be resolved at
10076 run time. */
0e1862bb
L		 10077 if ((bfd_link_pic (info)
10078 || globals->root.is_relocatable_executable)
7359ea65 10079 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10080 && !(globals->vxworks_p
3348747a
NS		 10081 && strcmp (input_section->output_section->name,
10082 ".tls_vars") == 0)
bb224fc3 10083 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10084 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10085 && !(input_bfd == globals->stub_bfd
10086 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10087 && (h == NULL
95b03e4a
L		 10088 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10089 && !resolved_to_zero)
7359ea65
DJ		 10090 || h->root.type != bfd_link_hash_undefweak)
10091 && r_type != R_ARM_PC24
5b5bb741
PB		 10092 && r_type != R_ARM_CALL
10093 && r_type != R_ARM_JUMP24
ee06dc07 10094 && r_type != R_ARM_PREL31
7359ea65 10095 && r_type != R_ARM_PLT32)
252b5132 10096 {
947216bf 10097 Elf_Internal_Rela outrel;
b34976b6 10098 bfd_boolean skip, relocate;
f21f3fe0 10099
52db4ec2
JW		 10100 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10101 && !h->def_regular)
10102 {
10103 char *v = _("shared object");
10104
0e1862bb 10105 if (bfd_link_executable (info))
52db4ec2
JW		 10106 v = _("PIE executable");
10107
4eca0228 10108 _bfd_error_handler
52db4ec2
JW		 10109 (_("%B: relocation %s against external or undefined symbol `%s'"
10110 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10111 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10112 return bfd_reloc_notsupported;
10113 }
10114
0945cdfd
DJ		 10115 *unresolved_reloc_p = FALSE;
10116
34e77a92 10117 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10118 {
83bac4b0
NC		 10119 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10120 ! globals->use_rel);
f21f3fe0 10121
83bac4b0 10122 if (sreloc == NULL)
252b5132 10123 return bfd_reloc_notsupported;
252b5132 10124 }
f21f3fe0 10125
b34976b6
AM		 10126 skip = FALSE;
10127 relocate = FALSE;
f21f3fe0 10128
00a97672 10129 outrel.r_addend = addend;
c629eae0
JJ		 10130 outrel.r_offset =
10131 _bfd_elf_section_offset (output_bfd, info, input_section,
10132 rel->r_offset);
10133 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10134 skip = TRUE;
0bb2d96a 10135 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10136 skip = TRUE, relocate = TRUE;
252b5132
RH		 10137 outrel.r_offset += (input_section->output_section->vma
10138 + input_section->output_offset);
f21f3fe0 10139
252b5132 10140 if (skip)
0bb2d96a 10141 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10142 else if (h != NULL
10143 && h->dynindx != -1
0e1862bb 10144 && (!bfd_link_pic (info)
1dcb9720
JW		 10145 || !(bfd_link_pie (info)
10146 || SYMBOLIC_BIND (info, h))
f5385ebf 10147 || !h->def_regular))
5e681ec4 10148 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10149 else
10150 {
a16385dc
MM		 10151 int symbol;
10152
5e681ec4 10153 /* This symbol is local, or marked to become local. */
34e77a92 10154 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10155 if (globals->symbian_p)
6366ff1e 10156 {
74541ad4
AM		 10157 asection *osec;
10158
6366ff1e
MM		 10159 /* On Symbian OS, the data segment and text segement
10160 can be relocated independently. Therefore, we
10161 must indicate the segment to which this
10162 relocation is relative. The BPABI allows us to
10163 use any symbol in the right segment; we just use
10164 the section symbol as it is convenient. (We
10165 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10166 will not appear in the dynamic symbol table.)
10167
10168 Note that the dynamic linker ignores the section
10169 symbol value, so we don't subtract osec->vma
10170 from the emitted reloc addend. */
10dbd1f3 10171 if (sym_sec)
74541ad4 10172 osec = sym_sec->output_section;
10dbd1f3 10173 else
74541ad4
AM		 10174 osec = input_section->output_section;
10175 symbol = elf_section_data (osec)->dynindx;
10176 if (symbol == 0)
10177 {
10178 struct elf_link_hash_table *htab = elf_hash_table (info);
10179
10180 if ((osec->flags & SEC_READONLY) == 0
10181 && htab->data_index_section != NULL)
10182 osec = htab->data_index_section;
10183 else
10184 osec = htab->text_index_section;
10185 symbol = elf_section_data (osec)->dynindx;
10186 }
6366ff1e
MM		 10187 BFD_ASSERT (symbol != 0);
10188 }
a16385dc
MM		 10189 else
10190 /* On SVR4-ish systems, the dynamic loader cannot
10191 relocate the text and data segments independently,
10192 so the symbol does not matter. */
10193 symbol = 0;
34e77a92
RS		 10194 if (dynreloc_st_type == STT_GNU_IFUNC)
10195 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10196 to the .iplt entry. Instead, every non-call reference
10197 must use an R_ARM_IRELATIVE relocation to obtain the
10198 correct run-time address. */
10199 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10200 else
10201 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10202 if (globals->use_rel)
10203 relocate = TRUE;
10204 else
34e77a92 10205 outrel.r_addend += dynreloc_value;
252b5132 10206 }
f21f3fe0 10207
47beaa6a 10208 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10209
f21f3fe0 10210 /* If this reloc is against an external symbol, we do not want to
252b5132 10211 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10212 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10213 if (! relocate)
10214 return bfd_reloc_ok;
9a5aca8c 10215
f21f3fe0 10216 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10217 contents, rel->r_offset,
10218 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10219 }
10220 else switch (r_type)
10221 {
00a97672
RS		 10222 case R_ARM_ABS12:
10223 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10224
dfc5f959 10225 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10226 case R_ARM_CALL:
10227 case R_ARM_JUMP24:
8029a119 10228 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10229 case R_ARM_PLT32:
906e58ca 10230 {
906e58ca
NC		 10231 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10232
dfc5f959 10233 if (r_type == R_ARM_XPC25)
252b5132 10234 {
dfc5f959
NC		 10235 /* Check for Arm calling Arm function. */
10236 /* FIXME: Should we translate the instruction into a BL
10237 instruction instead ? */
35fc36a8 10238 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10239 _bfd_error_handler
d003868e
AM		 10240 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
10241 input_bfd,
10242 h ? h->root.root.string : "(local)");
dfc5f959 10243 }
155d87d7 10244 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10245 {
10246 /* Check for Arm calling Thumb function. */
35fc36a8 10247 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10248 {
f2a9dd69
DJ		 10249 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10250 output_bfd, input_section,
10251 hit_data, sym_sec, rel->r_offset,
10252 signed_addend, value,
10253 error_message))
10254 return bfd_reloc_ok;
10255 else
10256 return bfd_reloc_dangerous;
dfc5f959 10257 }
252b5132 10258 }
ba96a88f 10259
906e58ca 10260 /* Check if a stub has to be inserted because the
8029a119 10261 destination is too far or we are changing mode. */
155d87d7
CL		 10262 if ( r_type == R_ARM_CALL
10263 || r_type == R_ARM_JUMP24
10264 || r_type == R_ARM_PLT32)
906e58ca 10265 {
fe33d2fa
CL		 10266 enum elf32_arm_stub_type stub_type = arm_stub_none;
10267 struct elf32_arm_link_hash_entry *hash;
10268
10269 hash = (struct elf32_arm_link_hash_entry *) h;
10270 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10271 st_type, &branch_type,
10272 hash, value, sym_sec,
fe33d2fa 10273 input_bfd, sym_name);
5fa9e92f 10274
fe33d2fa 10275 if (stub_type != arm_stub_none)
906e58ca
NC		 10276 {
10277 /* The target is out of reach, so redirect the
10278 branch to the local stub for this function. */
906e58ca
NC		 10279 stub_entry = elf32_arm_get_stub_entry (input_section,
10280 sym_sec, h,
fe33d2fa
CL		 10281 rel, globals,
10282 stub_type);
9cd3e4e5
NC		 10283 {
10284 if (stub_entry != NULL)
10285 value = (stub_entry->stub_offset
10286 + stub_entry->stub_sec->output_offset
10287 + stub_entry->stub_sec->output_section->vma);
10288
10289 if (plt_offset != (bfd_vma) -1)
10290 *unresolved_reloc_p = FALSE;
10291 }
906e58ca 10292 }
fe33d2fa
CL		 10293 else
10294 {
10295 /* If the call goes through a PLT entry, make sure to
10296 check distance to the right destination address. */
34e77a92 10297 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10298 {
10299 value = (splt->output_section->vma
10300 + splt->output_offset
34e77a92 10301 + plt_offset);
fe33d2fa
CL		 10302 *unresolved_reloc_p = FALSE;
10303 /* The PLT entry is in ARM mode, regardless of the
10304 target function. */
35fc36a8 10305 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10306 }
10307 }
906e58ca
NC		 10308 }
10309
dea514f5
PB		 10310 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10311 where:
10312 S is the address of the symbol in the relocation.
10313 P is address of the instruction being relocated.
10314 A is the addend (extracted from the instruction) in bytes.
10315
10316 S is held in 'value'.
10317 P is the base address of the section containing the
10318 instruction plus the offset of the reloc into that
10319 section, ie:
10320 (input_section->output_section->vma +
10321 input_section->output_offset +
10322 rel->r_offset).
10323 A is the addend, converted into bytes, ie:
10324 (signed_addend * 4)
10325
10326 Note: None of these operations have knowledge of the pipeline
10327 size of the processor, thus it is up to the assembler to
10328 encode this information into the addend. */
10329 value -= (input_section->output_section->vma
10330 + input_section->output_offset);
10331 value -= rel->r_offset;
4e7fd91e
PB		 10332 if (globals->use_rel)
10333 value += (signed_addend << howto->size);
10334 else
10335 /* RELA addends do not have to be adjusted by howto->size. */
10336 value += signed_addend;
23080146 10337
dcb5e6e6
NC		 10338 signed_addend = value;
10339 signed_addend >>= howto->rightshift;
9a5aca8c 10340
5ab79981 10341 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10342 the next instruction unless a PLT entry will be created.
77b4f08f 10343 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10344 The jump to the next instruction is optimized as a NOP depending
10345 on the architecture. */
ffcb4889 10346 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10347 && plt_offset == (bfd_vma) -1)
77b4f08f 10348 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10349 {
cd1dac3d
DG		 10350 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10351
10352 if (arch_has_arm_nop (globals))
10353 value |= 0x0320f000;
10354 else
10355 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10356 }
10357 else
59f2c4e7 10358 {
9b485d32 10359 /* Perform a signed range check. */
dcb5e6e6 10360 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10361 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10362 return bfd_reloc_overflow;
9a5aca8c 10363
5ab79981 10364 addend = (value & 2);
39b41c9c 10365
5ab79981
PB		 10366 value = (signed_addend & howto->dst_mask)
10367 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10368
5ab79981
PB		 10369 if (r_type == R_ARM_CALL)
10370 {
155d87d7 10371 /* Set the H bit in the BLX instruction. */
35fc36a8 10372 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10373 {
10374 if (addend)
10375 value |= (1 << 24);
10376 else
10377 value &= ~(bfd_vma)(1 << 24);
10378 }
10379
5ab79981 10380 /* Select the correct instruction (BL or BLX). */
906e58ca 10381 /* Only if we are not handling a BL to a stub. In this
8029a119 10382 case, mode switching is performed by the stub. */
35fc36a8 10383 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10384 value |= (1 << 28);
63e1a0fc 10385 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10386 {
10387 value &= ~(bfd_vma)(1 << 28);
10388 value |= (1 << 24);
10389 }
39b41c9c
PB		 10390 }
10391 }
906e58ca 10392 }
252b5132 10393 break;
f21f3fe0 10394
252b5132
RH		 10395 case R_ARM_ABS32:
10396 value += addend;
35fc36a8 10397 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10398 value |= 1;
10399 break;
f21f3fe0 10400
bb224fc3
MS		 10401 case R_ARM_ABS32_NOI:
10402 value += addend;
10403 break;
10404
252b5132 10405 case R_ARM_REL32:
a8bc6c78 10406 value += addend;
35fc36a8 10407 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10408 value |= 1;
252b5132 10409 value -= (input_section->output_section->vma
62efb346 10410 + input_section->output_offset + rel->r_offset);
252b5132 10411 break;
eb043451 10412
bb224fc3
MS		 10413 case R_ARM_REL32_NOI:
10414 value += addend;
10415 value -= (input_section->output_section->vma
10416 + input_section->output_offset + rel->r_offset);
10417 break;
10418
eb043451
PB		 10419 case R_ARM_PREL31:
10420 value -= (input_section->output_section->vma
10421 + input_section->output_offset + rel->r_offset);
10422 value += signed_addend;
10423 if (! h || h->root.type != bfd_link_hash_undefweak)
10424 {
8029a119 10425 /* Check for overflow. */
eb043451
PB		 10426 if ((value ^ (value >> 1)) & (1 << 30))
10427 return bfd_reloc_overflow;
10428 }
10429 value &= 0x7fffffff;
10430 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10431 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10432 value |= 1;
10433 break;
252b5132 10434 }
f21f3fe0 10435
252b5132
RH		 10436 bfd_put_32 (input_bfd, value, hit_data);
10437 return bfd_reloc_ok;
10438
10439 case R_ARM_ABS8:
fd0fd00c
MJ		 10440 /* PR 16202: Refectch the addend using the correct size. */
10441 if (globals->use_rel)
10442 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10443 value += addend;
4e67d4ca
DG		 10444
10445 /* There is no way to tell whether the user intended to use a signed or
10446 unsigned addend. When checking for overflow we accept either,
10447 as specified by the AAELF. */
10448 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10449 return bfd_reloc_overflow;
10450
10451 bfd_put_8 (input_bfd, value, hit_data);
10452 return bfd_reloc_ok;
10453
10454 case R_ARM_ABS16:
fd0fd00c
MJ		 10455 /* PR 16202: Refectch the addend using the correct size. */
10456 if (globals->use_rel)
10457 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10458 value += addend;
10459
4e67d4ca
DG		 10460 /* See comment for R_ARM_ABS8. */
10461 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10462 return bfd_reloc_overflow;
10463
10464 bfd_put_16 (input_bfd, value, hit_data);
10465 return bfd_reloc_ok;
10466
252b5132 10467 case R_ARM_THM_ABS5:
9b485d32 10468 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10469 if (globals->use_rel)
10470 {
10471 /* Need to refetch addend. */
10472 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10473 /* ??? Need to determine shift amount from operand size. */
10474 addend >>= howto->rightshift;
10475 }
252b5132
RH		 10476 value += addend;
10477
10478 /* ??? Isn't value unsigned? */
10479 if ((long) value > 0x1f || (long) value < -0x10)
10480 return bfd_reloc_overflow;
10481
10482 /* ??? Value needs to be properly shifted into place first. */
10483 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10484 bfd_put_16 (input_bfd, value, hit_data);
10485 return bfd_reloc_ok;
10486
2cab6cc3
MS		 10487 case R_ARM_THM_ALU_PREL_11_0:
10488 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10489 {
10490 bfd_vma insn;
10491 bfd_signed_vma relocation;
10492
10493 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10494 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10495
99059e56
RM		 10496 if (globals->use_rel)
10497 {
10498 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10499 | ((insn & (1 << 26)) >> 15);
10500 if (insn & 0xf00000)
10501 signed_addend = -signed_addend;
10502 }
2cab6cc3
MS		 10503
10504 relocation = value + signed_addend;
79f08007 10505 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10506 + input_section->output_offset
10507 + rel->r_offset);
2cab6cc3 10508
8c65b54f
CS		 10509 /* PR 21523: Use an absolute value. The user of this reloc will
10510 have already selected an ADD or SUB insn appropriately. */
e652757b 10511 value = labs (relocation);
2cab6cc3 10512
99059e56
RM		 10513 if (value >= 0x1000)
10514 return bfd_reloc_overflow;
2cab6cc3 10515
e645cf40
AG		 10516 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10517 if (branch_type == ST_BRANCH_TO_THUMB)
10518 value |= 1;
10519
2cab6cc3 10520 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10521 | ((value & 0x700) << 4)
10522 | ((value & 0x800) << 15);
10523 if (relocation < 0)
10524 insn |= 0xa00000;
2cab6cc3
MS		 10525
10526 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10527 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10528
99059e56 10529 return bfd_reloc_ok;
2cab6cc3
MS		 10530 }
10531
e1ec24c6
NC		 10532 case R_ARM_THM_PC8:
10533 /* PR 10073: This reloc is not generated by the GNU toolchain,
10534 but it is supported for compatibility with third party libraries
10535 generated by other compilers, specifically the ARM/IAR. */
10536 {
10537 bfd_vma insn;
10538 bfd_signed_vma relocation;
10539
10540 insn = bfd_get_16 (input_bfd, hit_data);
10541
99059e56 10542 if (globals->use_rel)
79f08007 10543 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10544
10545 relocation = value + addend;
79f08007 10546 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10547 + input_section->output_offset
10548 + rel->r_offset);
e1ec24c6 10549
b6518b38 10550 value = relocation;
e1ec24c6
NC		 10551
10552 /* We do not check for overflow of this reloc. Although strictly
10553 speaking this is incorrect, it appears to be necessary in order
10554 to work with IAR generated relocs. Since GCC and GAS do not
10555 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10556 a problem for them. */
10557 value &= 0x3fc;
10558
10559 insn = (insn & 0xff00) | (value >> 2);
10560
10561 bfd_put_16 (input_bfd, insn, hit_data);
10562
99059e56 10563 return bfd_reloc_ok;
e1ec24c6
NC		 10564 }
10565
2cab6cc3
MS		 10566 case R_ARM_THM_PC12:
10567 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10568 {
10569 bfd_vma insn;
10570 bfd_signed_vma relocation;
10571
10572 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10573 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10574
99059e56
RM		 10575 if (globals->use_rel)
10576 {
10577 signed_addend = insn & 0xfff;
10578 if (!(insn & (1 << 23)))
10579 signed_addend = -signed_addend;
10580 }
2cab6cc3
MS		 10581
10582 relocation = value + signed_addend;
79f08007 10583 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10584 + input_section->output_offset
10585 + rel->r_offset);
2cab6cc3 10586
b6518b38 10587 value = relocation;
2cab6cc3 10588
99059e56
RM		 10589 if (value >= 0x1000)
10590 return bfd_reloc_overflow;
2cab6cc3
MS		 10591
10592 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10593 if (relocation >= 0)
10594 insn |= (1 << 23);
2cab6cc3
MS		 10595
10596 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10597 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10598
99059e56 10599 return bfd_reloc_ok;
2cab6cc3
MS		 10600 }
10601
dfc5f959 10602 case R_ARM_THM_XPC22:
c19d1205 10603 case R_ARM_THM_CALL:
bd97cb95 10604 case R_ARM_THM_JUMP24:
dfc5f959 10605 /* Thumb BL (branch long instruction). */
252b5132 10606 {
b34976b6 10607 bfd_vma relocation;
99059e56 10608 bfd_vma reloc_sign;
b34976b6
AM		 10609 bfd_boolean overflow = FALSE;
10610 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10611 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10612 bfd_signed_vma reloc_signed_max;
10613 bfd_signed_vma reloc_signed_min;
b34976b6 10614 bfd_vma check;
252b5132 10615 bfd_signed_vma signed_check;
e95de063 10616 int bitsize;
cd1dac3d 10617 const int thumb2 = using_thumb2 (globals);
5e866f5a 10618 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10619
5ab79981 10620 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10621 the next instruction unless a PLT entry will be created.
10622 The jump to the next instruction is optimized as a NOP.W for
10623 Thumb-2 enabled architectures. */
19540007 10624 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10625 && plt_offset == (bfd_vma) -1)
5ab79981 10626 {
60a019a0 10627 if (thumb2)
cd1dac3d
DG		 10628 {
10629 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10630 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10631 }
10632 else
10633 {
10634 bfd_put_16 (input_bfd, 0xe000, hit_data);
10635 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10636 }
5ab79981
PB		 10637 return bfd_reloc_ok;
10638 }
10639
e95de063 10640 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10641 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10642 if (globals->use_rel)
10643 {
99059e56
RM		 10644 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10645 bfd_vma upper = upper_insn & 0x3ff;
10646 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10647 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10648 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10649 bfd_vma i1 = j1 ^ s ? 0 : 1;
10650 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10651
99059e56
RM		 10652 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10653 /* Sign extend. */
10654 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10655
4e7fd91e
PB		 10656 signed_addend = addend;
10657 }
cb1afa5c 10658
dfc5f959
NC		 10659 if (r_type == R_ARM_THM_XPC22)
10660 {
10661 /* Check for Thumb to Thumb call. */
10662 /* FIXME: Should we translate the instruction into a BL
10663 instruction instead ? */
35fc36a8 10664 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10665 _bfd_error_handler
d003868e
AM		 10666 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10667 input_bfd,
10668 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10669 }
10670 else
252b5132 10671 {
dfc5f959
NC		 10672 /* If it is not a call to Thumb, assume call to Arm.
10673 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10674 function call at all, but rather a long jump. Calls through
10675 the PLT do not require stubs. */
34e77a92 10676 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10677 {
bd97cb95 10678 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10679 {
10680 /* Convert BL to BLX. */
10681 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10682 }
155d87d7
CL		 10683 else if (( r_type != R_ARM_THM_CALL)
10684 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10685 {
10686 if (elf32_thumb_to_arm_stub
10687 (info, sym_name, input_bfd, output_bfd, input_section,
10688 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10689 error_message))
10690 return bfd_reloc_ok;
10691 else
10692 return bfd_reloc_dangerous;
10693 }
da5938a2 10694 }
35fc36a8
RS		 10695 else if (branch_type == ST_BRANCH_TO_THUMB
10696 && globals->use_blx
bd97cb95 10697 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10698 {
10699 /* Make sure this is a BL. */
10700 lower_insn |= 0x1800;
10701 }
252b5132 10702 }
f21f3fe0 10703
fe33d2fa 10704 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10705 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10706 {
10707 /* Check if a stub has to be inserted because the destination
8029a119 10708 is too far. */
fe33d2fa
CL		 10709 struct elf32_arm_stub_hash_entry *stub_entry;
10710 struct elf32_arm_link_hash_entry *hash;
10711
10712 hash = (struct elf32_arm_link_hash_entry *) h;
10713
10714 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10715 st_type, &branch_type,
10716 hash, value, sym_sec,
fe33d2fa
CL		 10717 input_bfd, sym_name);
10718
10719 if (stub_type != arm_stub_none)
906e58ca
NC		 10720 {
10721 /* The target is out of reach or we are changing modes, so
10722 redirect the branch to the local stub for this
10723 function. */
10724 stub_entry = elf32_arm_get_stub_entry (input_section,
10725 sym_sec, h,
fe33d2fa
CL		 10726 rel, globals,
10727 stub_type);
906e58ca 10728 if (stub_entry != NULL)
9cd3e4e5
NC		 10729 {
10730 value = (stub_entry->stub_offset
10731 + stub_entry->stub_sec->output_offset
10732 + stub_entry->stub_sec->output_section->vma);
10733
10734 if (plt_offset != (bfd_vma) -1)
10735 *unresolved_reloc_p = FALSE;
10736 }
906e58ca 10737
f4ac8484 10738 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10739 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10740 {
10741 if ((stub_entry
10742 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10743 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10744 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10745 }
906e58ca
NC		 10746 }
10747 }
10748
fe33d2fa 10749 /* Handle calls via the PLT. */
34e77a92 10750 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10751 {
10752 value = (splt->output_section->vma
10753 + splt->output_offset
34e77a92 10754 + plt_offset);
fe33d2fa 10755
eed94f8f
NC		 10756 if (globals->use_blx
10757 && r_type == R_ARM_THM_CALL
10758 && ! using_thumb_only (globals))
fe33d2fa
CL		 10759 {
10760 /* If the Thumb BLX instruction is available, convert
10761 the BL to a BLX instruction to call the ARM-mode
10762 PLT entry. */
10763 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10764 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10765 }
10766 else
10767 {
eed94f8f
NC		 10768 if (! using_thumb_only (globals))
10769 /* Target the Thumb stub before the ARM PLT entry. */
10770 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10771 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10772 }
10773 *unresolved_reloc_p = FALSE;
10774 }
10775
ba96a88f 10776 relocation = value + signed_addend;
f21f3fe0 10777
252b5132 10778 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10779 + input_section->output_offset
10780 + rel->r_offset);
9a5aca8c 10781
252b5132
RH		 10782 check = relocation >> howto->rightshift;
10783
10784 /* If this is a signed value, the rightshift just dropped
10785 leading 1 bits (assuming twos complement). */
10786 if ((bfd_signed_vma) relocation >= 0)
10787 signed_check = check;
10788 else
10789 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10790
e95de063
MS		 10791 /* Calculate the permissable maximum and minimum values for
10792 this relocation according to whether we're relocating for
10793 Thumb-2 or not. */
10794 bitsize = howto->bitsize;
5e866f5a 10795 if (!thumb2_bl)
e95de063 10796 bitsize -= 2;
f6ebfac0 10797 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10798 reloc_signed_min = ~reloc_signed_max;
10799
252b5132 10800 /* Assumes two's complement. */
ba96a88f 10801 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10802 overflow = TRUE;
252b5132 10803
bd97cb95 10804 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10805 /* For a BLX instruction, make sure that the relocation is rounded up
10806 to a word boundary. This follows the semantics of the instruction
10807 which specifies that bit 1 of the target address will come from bit
10808 1 of the base address. */
10809 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10810
e95de063
MS		 10811 /* Put RELOCATION back into the insn. Assumes two's complement.
10812 We use the Thumb-2 encoding, which is safe even if dealing with
10813 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10814 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10815 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10816 | ((relocation >> 12) & 0x3ff)
10817 | (reloc_sign << 10);
906e58ca 10818 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10819 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10820 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10821 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10822
252b5132
RH		 10823 /* Put the relocated value back in the object file: */
10824 bfd_put_16 (input_bfd, upper_insn, hit_data);
10825 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10826
10827 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10828 }
10829 break;
10830
c19d1205
ZW		 10831 case R_ARM_THM_JUMP19:
10832 /* Thumb32 conditional branch instruction. */
10833 {
10834 bfd_vma relocation;
10835 bfd_boolean overflow = FALSE;
10836 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10837 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10838 bfd_signed_vma reloc_signed_max = 0xffffe;
10839 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10840 bfd_signed_vma signed_check;
c5423981
TG		 10841 enum elf32_arm_stub_type stub_type = arm_stub_none;
10842 struct elf32_arm_stub_hash_entry *stub_entry;
10843 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10844
10845 /* Need to refetch the addend, reconstruct the top three bits,
10846 and squish the two 11 bit pieces together. */
10847 if (globals->use_rel)
10848 {
10849 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10850 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10851 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10852 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10853 bfd_vma lower = (lower_insn & 0x07ff);
10854
a00a1f35
MS		 10855 upper |= J1 << 6;
10856 upper |= J2 << 7;
10857 upper |= (!S) << 8;
c19d1205
ZW		 10858 upper -= 0x0100; /* Sign extend. */
10859
10860 addend = (upper << 12) | (lower << 1);
10861 signed_addend = addend;
10862 }
10863
bd97cb95 10864 /* Handle calls via the PLT. */
34e77a92 10865 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10866 {
10867 value = (splt->output_section->vma
10868 + splt->output_offset
34e77a92 10869 + plt_offset);
bd97cb95
DJ		 10870 /* Target the Thumb stub before the ARM PLT entry. */
10871 value -= PLT_THUMB_STUB_SIZE;
10872 *unresolved_reloc_p = FALSE;
10873 }
10874
c5423981
TG		 10875 hash = (struct elf32_arm_link_hash_entry *)h;
10876
10877 stub_type = arm_type_of_stub (info, input_section, rel,
10878 st_type, &branch_type,
10879 hash, value, sym_sec,
10880 input_bfd, sym_name);
10881 if (stub_type != arm_stub_none)
10882 {
10883 stub_entry = elf32_arm_get_stub_entry (input_section,
10884 sym_sec, h,
10885 rel, globals,
10886 stub_type);
10887 if (stub_entry != NULL)
10888 {
10889 value = (stub_entry->stub_offset
10890 + stub_entry->stub_sec->output_offset
10891 + stub_entry->stub_sec->output_section->vma);
10892 }
10893 }
c19d1205 10894
99059e56 10895 relocation = value + signed_addend;
c19d1205
ZW		 10896 relocation -= (input_section->output_section->vma
10897 + input_section->output_offset
10898 + rel->r_offset);
a00a1f35 10899 signed_check = (bfd_signed_vma) relocation;
c19d1205 10900
c19d1205
ZW		 10901 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10902 overflow = TRUE;
10903
10904 /* Put RELOCATION back into the insn. */
10905 {
10906 bfd_vma S = (relocation & 0x00100000) >> 20;
10907 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10908 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10909 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10910 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10911
a00a1f35 10912 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10913 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10914 }
10915
10916 /* Put the relocated value back in the object file: */
10917 bfd_put_16 (input_bfd, upper_insn, hit_data);
10918 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10919
10920 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10921 }
10922
10923 case R_ARM_THM_JUMP11:
10924 case R_ARM_THM_JUMP8:
10925 case R_ARM_THM_JUMP6:
51c5503b
NC		 10926 /* Thumb B (branch) instruction). */
10927 {
6cf9e9fe 10928 bfd_signed_vma relocation;
51c5503b
NC		 10929 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10930 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10931 bfd_signed_vma signed_check;
10932
c19d1205
ZW		 10933 /* CZB cannot jump backward. */
10934 if (r_type == R_ARM_THM_JUMP6)
10935 reloc_signed_min = 0;
10936
4e7fd91e 10937 if (globals->use_rel)
6cf9e9fe 10938 {
4e7fd91e
PB		 10939 /* Need to refetch addend. */
10940 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10941 if (addend & ((howto->src_mask + 1) >> 1))
10942 {
10943 signed_addend = -1;
10944 signed_addend &= ~ howto->src_mask;
10945 signed_addend |= addend;
10946 }
10947 else
10948 signed_addend = addend;
10949 /* The value in the insn has been right shifted. We need to
10950 undo this, so that we can perform the address calculation
10951 in terms of bytes. */
10952 signed_addend <<= howto->rightshift;
6cf9e9fe 10953 }
6cf9e9fe 10954 relocation = value + signed_addend;
51c5503b
NC		 10955
10956 relocation -= (input_section->output_section->vma
10957 + input_section->output_offset
10958 + rel->r_offset);
10959
6cf9e9fe
NC		 10960 relocation >>= howto->rightshift;
10961 signed_check = relocation;
c19d1205
ZW		 10962
10963 if (r_type == R_ARM_THM_JUMP6)
10964 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10965 else
10966 relocation &= howto->dst_mask;
51c5503b 10967 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10968
51c5503b
NC		 10969 bfd_put_16 (input_bfd, relocation, hit_data);
10970
10971 /* Assumes two's complement. */
10972 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10973 return bfd_reloc_overflow;
10974
10975 return bfd_reloc_ok;
10976 }
cedb70c5 10977
8375c36b
PB		 10978 case R_ARM_ALU_PCREL7_0:
10979 case R_ARM_ALU_PCREL15_8:
10980 case R_ARM_ALU_PCREL23_15:
10981 {
10982 bfd_vma insn;
10983 bfd_vma relocation;
10984
10985 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10986 if (globals->use_rel)
10987 {
10988 /* Extract the addend. */
10989 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10990 signed_addend = addend;
10991 }
8375c36b
PB		 10992 relocation = value + signed_addend;
10993
10994 relocation -= (input_section->output_section->vma
10995 + input_section->output_offset
10996 + rel->r_offset);
10997 insn = (insn & ~0xfff)
10998 | ((howto->bitpos << 7) & 0xf00)
10999 | ((relocation >> howto->bitpos) & 0xff);
11000 bfd_put_32 (input_bfd, value, hit_data);
11001 }
11002 return bfd_reloc_ok;
11003
252b5132
RH		 11004 case R_ARM_GNU_VTINHERIT:
11005 case R_ARM_GNU_VTENTRY:
11006 return bfd_reloc_ok;
11007
c19d1205 11008 case R_ARM_GOTOFF32:
252b5132 11009 /* Relocation is relative to the start of the
99059e56 11010 global offset table. */
252b5132
RH		 11011
11012 BFD_ASSERT (sgot != NULL);
11013 if (sgot == NULL)
99059e56 11014 return bfd_reloc_notsupported;
9a5aca8c 11015
cedb70c5 11016 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11017 address by one, so that attempts to call the function pointer will
11018 correctly interpret it as Thumb code. */
35fc36a8 11019 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11020 value += 1;
11021
252b5132 11022 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11023 calculation. We always want the start of .got. If we
11024 define _GLOBAL_OFFSET_TABLE in a different way, as is
11025 permitted by the ABI, we might have to change this
11026 calculation. */
252b5132 11027 value -= sgot->output_section->vma;
f21f3fe0 11028 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11029 contents, rel->r_offset, value,
00a97672 11030 rel->r_addend);
252b5132
RH		 11031
11032 case R_ARM_GOTPC:
a7c10850 11033 /* Use global offset table as symbol value. */
252b5132 11034 BFD_ASSERT (sgot != NULL);
f21f3fe0 11035
252b5132 11036 if (sgot == NULL)
99059e56 11037 return bfd_reloc_notsupported;
252b5132 11038
0945cdfd 11039 *unresolved_reloc_p = FALSE;
252b5132 11040 value = sgot->output_section->vma;
f21f3fe0 11041 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11042 contents, rel->r_offset, value,
00a97672 11043 rel->r_addend);
f21f3fe0 11044
252b5132 11045 case R_ARM_GOT32:
eb043451 11046 case R_ARM_GOT_PREL:
252b5132 11047 /* Relocation is to the entry for this symbol in the
99059e56 11048 global offset table. */
252b5132
RH		 11049 if (sgot == NULL)
11050 return bfd_reloc_notsupported;
f21f3fe0 11051
34e77a92
RS		 11052 if (dynreloc_st_type == STT_GNU_IFUNC
11053 && plt_offset != (bfd_vma) -1
11054 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11055 {
11056 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11057 symbol, and the relocation resolves directly to the runtime
11058 target rather than to the .iplt entry. This means that any
11059 .got entry would be the same value as the .igot.plt entry,
11060 so there's no point creating both. */
11061 sgot = globals->root.igotplt;
11062 value = sgot->output_offset + gotplt_offset;
11063 }
11064 else if (h != NULL)
252b5132
RH		 11065 {
11066 bfd_vma off;
f21f3fe0 11067
252b5132
RH		 11068 off = h->got.offset;
11069 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11070 if ((off & 1) != 0)
252b5132 11071 {
b436d854
RS		 11072 /* We have already processsed one GOT relocation against
11073 this symbol. */
11074 off &= ~1;
11075 if (globals->root.dynamic_sections_created
11076 && !SYMBOL_REFERENCES_LOCAL (info, h))
11077 *unresolved_reloc_p = FALSE;
11078 }
11079 else
11080 {
11081 Elf_Internal_Rela outrel;
11082
6f820c85 11083 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11084 {
11085 /* If the symbol doesn't resolve locally in a static
11086 object, we have an undefined reference. If the
11087 symbol doesn't resolve locally in a dynamic object,
11088 it should be resolved by the dynamic linker. */
11089 if (globals->root.dynamic_sections_created)
11090 {
11091 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11092 *unresolved_reloc_p = FALSE;
11093 }
11094 else
11095 outrel.r_info = 0;
11096 outrel.r_addend = 0;
11097 }
252b5132
RH		 11098 else
11099 {
34e77a92 11100 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11101 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11102 else if (bfd_link_pic (info)
11103 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11104 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11105 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11106 else
11107 outrel.r_info = 0;
34e77a92 11108 outrel.r_addend = dynreloc_value;
b436d854 11109 }
ee29b9fb 11110
b436d854
RS		 11111 /* The GOT entry is initialized to zero by default.
11112 See if we should install a different value. */
11113 if (outrel.r_addend != 0
11114 && (outrel.r_info == 0 || globals->use_rel))
11115 {
11116 bfd_put_32 (output_bfd, outrel.r_addend,
11117 sgot->contents + off);
11118 outrel.r_addend = 0;
252b5132 11119 }
f21f3fe0 11120
b436d854
RS		 11121 if (outrel.r_info != 0)
11122 {
11123 outrel.r_offset = (sgot->output_section->vma
11124 + sgot->output_offset
11125 + off);
11126 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11127 }
11128 h->got.offset |= 1;
11129 }
252b5132
RH		 11130 value = sgot->output_offset + off;
11131 }
11132 else
11133 {
11134 bfd_vma off;
f21f3fe0 11135
5025eb7c
AO		 11136 BFD_ASSERT (local_got_offsets != NULL
11137 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11138
252b5132 11139 off = local_got_offsets[r_symndx];
f21f3fe0 11140
252b5132
RH		 11141 /* The offset must always be a multiple of 4. We use the
11142 least significant bit to record whether we have already
9b485d32 11143 generated the necessary reloc. */
252b5132
RH		 11144 if ((off & 1) != 0)
11145 off &= ~1;
11146 else
11147 {
00a97672 11148 if (globals->use_rel)
34e77a92 11149 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11150
0e1862bb 11151 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11152 {
947216bf 11153 Elf_Internal_Rela outrel;
f21f3fe0 11154
34e77a92 11155 outrel.r_addend = addend + dynreloc_value;
252b5132 11156 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11157 + sgot->output_offset
252b5132 11158 + off);
34e77a92 11159 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11160 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11161 else
11162 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11163 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11164 }
f21f3fe0 11165
252b5132
RH		 11166 local_got_offsets[r_symndx] |= 1;
11167 }
f21f3fe0 11168
252b5132
RH		 11169 value = sgot->output_offset + off;
11170 }
eb043451
PB		 11171 if (r_type != R_ARM_GOT32)
11172 value += sgot->output_section->vma;
9a5aca8c 11173
f21f3fe0 11174 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11175 contents, rel->r_offset, value,
00a97672 11176 rel->r_addend);
f21f3fe0 11177
ba93b8ac
DJ		 11178 case R_ARM_TLS_LDO32:
11179 value = value - dtpoff_base (info);
11180
11181 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11182 contents, rel->r_offset, value,
11183 rel->r_addend);
ba93b8ac
DJ		 11184
11185 case R_ARM_TLS_LDM32:
11186 {
11187 bfd_vma off;
11188
362d30a1 11189 if (sgot == NULL)
ba93b8ac
DJ		 11190 abort ();
11191
11192 off = globals->tls_ldm_got.offset;
11193
11194 if ((off & 1) != 0)
11195 off &= ~1;
11196 else
11197 {
11198 /* If we don't know the module number, create a relocation
11199 for it. */
0e1862bb 11200 if (bfd_link_pic (info))
ba93b8ac
DJ		 11201 {
11202 Elf_Internal_Rela outrel;
ba93b8ac 11203
362d30a1 11204 if (srelgot == NULL)
ba93b8ac
DJ		 11205 abort ();
11206
00a97672 11207 outrel.r_addend = 0;
362d30a1
RS		 11208 outrel.r_offset = (sgot->output_section->vma
11209 + sgot->output_offset + off);
ba93b8ac
DJ		 11210 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11211
00a97672
RS		 11212 if (globals->use_rel)
11213 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11214 sgot->contents + off);
ba93b8ac 11215
47beaa6a 11216 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11217 }
11218 else
362d30a1 11219 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11220
11221 globals->tls_ldm_got.offset |= 1;
11222 }
11223
362d30a1 11224 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11225 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11226
11227 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11228 contents, rel->r_offset, value,
00a97672 11229 rel->r_addend);
ba93b8ac
DJ		 11230 }
11231
0855e32b
NS		 11232 case R_ARM_TLS_CALL:
11233 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11234 case R_ARM_TLS_GD32:
11235 case R_ARM_TLS_IE32:
0855e32b
NS		 11236 case R_ARM_TLS_GOTDESC:
11237 case R_ARM_TLS_DESCSEQ:
11238 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11239 {
0855e32b
NS		 11240 bfd_vma off, offplt;
11241 int indx = 0;
ba93b8ac
DJ		 11242 char tls_type;
11243
0855e32b 11244 BFD_ASSERT (sgot != NULL);
ba93b8ac 11245
ba93b8ac
DJ		 11246 if (h != NULL)
11247 {
11248 bfd_boolean dyn;
11249 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11250 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11251 bfd_link_pic (info),
11252 h)
11253 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11254 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11255 {
11256 *unresolved_reloc_p = FALSE;
11257 indx = h->dynindx;
11258 }
11259 off = h->got.offset;
0855e32b 11260 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11261 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11262 }
11263 else
11264 {
0855e32b 11265 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11266 off = local_got_offsets[r_symndx];
0855e32b 11267 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11268 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11269 }
11270
0855e32b 11271 /* Linker relaxations happens from one of the
b38cadfb 11272 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11273 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11274 tls_type = GOT_TLS_IE;
0855e32b
NS		 11275
11276 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11277
11278 if ((off & 1) != 0)
11279 off &= ~1;
11280 else
11281 {
11282 bfd_boolean need_relocs = FALSE;
11283 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11284 int cur_off = off;
11285
11286 /* The GOT entries have not been initialized yet. Do it
11287 now, and emit any relocations. If both an IE GOT and a
11288 GD GOT are necessary, we emit the GD first. */
11289
0e1862bb 11290 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11291 && (h == NULL
95b03e4a
L		 11292 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11293 && !resolved_to_zero)
ba93b8ac
DJ		 11294 || h->root.type != bfd_link_hash_undefweak))
11295 {
11296 need_relocs = TRUE;
0855e32b 11297 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11298 }
11299
0855e32b
NS		 11300 if (tls_type & GOT_TLS_GDESC)
11301 {
47beaa6a
RS		 11302 bfd_byte *loc;
11303
0855e32b
NS		 11304 /* We should have relaxed, unless this is an undefined
11305 weak symbol. */
11306 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11307 || bfd_link_pic (info));
0855e32b 11308 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11309 <= globals->root.sgotplt->size);
0855e32b
NS		 11310
11311 outrel.r_addend = 0;
11312 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11313 + globals->root.sgotplt->output_offset
11314 + offplt
11315 + globals->sgotplt_jump_table_size);
b38cadfb 11316
0855e32b
NS		 11317 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11318 sreloc = globals->root.srelplt;
11319 loc = sreloc->contents;
11320 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11321 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11322 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11323
11324 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11325
11326 /* For globals, the first word in the relocation gets
11327 the relocation index and the top bit set, or zero,
11328 if we're binding now. For locals, it gets the
11329 symbol's offset in the tls section. */
99059e56 11330 bfd_put_32 (output_bfd,
0855e32b
NS		 11331 !h ? value - elf_hash_table (info)->tls_sec->vma
11332 : info->flags & DF_BIND_NOW ? 0
11333 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11334 globals->root.sgotplt->contents + offplt
11335 + globals->sgotplt_jump_table_size);
11336
0855e32b 11337 /* Second word in the relocation is always zero. */
99059e56 11338 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11339 globals->root.sgotplt->contents + offplt
11340 + globals->sgotplt_jump_table_size + 4);
0855e32b 11341 }
ba93b8ac
DJ		 11342 if (tls_type & GOT_TLS_GD)
11343 {
11344 if (need_relocs)
11345 {
00a97672 11346 outrel.r_addend = 0;
362d30a1
RS		 11347 outrel.r_offset = (sgot->output_section->vma
11348 + sgot->output_offset
00a97672 11349 + cur_off);
ba93b8ac 11350 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11351
00a97672
RS		 11352 if (globals->use_rel)
11353 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11354 sgot->contents + cur_off);
00a97672 11355
47beaa6a 11356 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11357
11358 if (indx == 0)
11359 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11360 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11361 else
11362 {
00a97672 11363 outrel.r_addend = 0;
ba93b8ac
DJ		 11364 outrel.r_info = ELF32_R_INFO (indx,
11365 R_ARM_TLS_DTPOFF32);
11366 outrel.r_offset += 4;
00a97672
RS		 11367
11368 if (globals->use_rel)
11369 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11370 sgot->contents + cur_off + 4);
00a97672 11371
47beaa6a
RS		 11372 elf32_arm_add_dynreloc (output_bfd, info,
11373 srelgot, &outrel);
ba93b8ac
DJ		 11374 }
11375 }
11376 else
11377 {
11378 /* If we are not emitting relocations for a
11379 general dynamic reference, then we must be in a
11380 static link or an executable link with the
11381 symbol binding locally. Mark it as belonging
11382 to module 1, the executable. */
11383 bfd_put_32 (output_bfd, 1,
362d30a1 11384 sgot->contents + cur_off);
ba93b8ac 11385 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11386 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11387 }
11388
11389 cur_off += 8;
11390 }
11391
11392 if (tls_type & GOT_TLS_IE)
11393 {
11394 if (need_relocs)
11395 {
00a97672
RS		 11396 if (indx == 0)
11397 outrel.r_addend = value - dtpoff_base (info);
11398 else
11399 outrel.r_addend = 0;
362d30a1
RS		 11400 outrel.r_offset = (sgot->output_section->vma
11401 + sgot->output_offset
ba93b8ac
DJ		 11402 + cur_off);
11403 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11404
00a97672
RS		 11405 if (globals->use_rel)
11406 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11407 sgot->contents + cur_off);
ba93b8ac 11408
47beaa6a 11409 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11410 }
11411 else
11412 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11413 sgot->contents + cur_off);
ba93b8ac
DJ		 11414 cur_off += 4;
11415 }
11416
11417 if (h != NULL)
11418 h->got.offset |= 1;
11419 else
11420 local_got_offsets[r_symndx] |= 1;
11421 }
11422
11423 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11424 off += 8;
0855e32b
NS		 11425 else if (tls_type & GOT_TLS_GDESC)
11426 off = offplt;
11427
11428 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11429 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11430 {
11431 bfd_signed_vma offset;
12352d3f
PB		 11432 /* TLS stubs are arm mode. The original symbol is a
11433 data object, so branch_type is bogus. */
11434 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11435 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11436 = arm_type_of_stub (info, input_section, rel,
11437 st_type, &branch_type,
0855e32b
NS		 11438 (struct elf32_arm_link_hash_entry *)h,
11439 globals->tls_trampoline, globals->root.splt,
11440 input_bfd, sym_name);
11441
11442 if (stub_type != arm_stub_none)
11443 {
11444 struct elf32_arm_stub_hash_entry *stub_entry
11445 = elf32_arm_get_stub_entry
11446 (input_section, globals->root.splt, 0, rel,
11447 globals, stub_type);
11448 offset = (stub_entry->stub_offset
11449 + stub_entry->stub_sec->output_offset
11450 + stub_entry->stub_sec->output_section->vma);
11451 }
11452 else
11453 offset = (globals->root.splt->output_section->vma
11454 + globals->root.splt->output_offset
11455 + globals->tls_trampoline);
11456
11457 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11458 {
11459 unsigned long inst;
b38cadfb
NC		 11460
11461 offset -= (input_section->output_section->vma
11462 + input_section->output_offset
11463 + rel->r_offset + 8);
0855e32b
NS		 11464
11465 inst = offset >> 2;
11466 inst &= 0x00ffffff;
11467 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11468 }
11469 else
11470 {
11471 /* Thumb blx encodes the offset in a complicated
11472 fashion. */
11473 unsigned upper_insn, lower_insn;
11474 unsigned neg;
11475
b38cadfb
NC		 11476 offset -= (input_section->output_section->vma
11477 + input_section->output_offset
0855e32b 11478 + rel->r_offset + 4);
b38cadfb 11479
12352d3f
PB		 11480 if (stub_type != arm_stub_none
11481 && arm_stub_is_thumb (stub_type))
11482 {
11483 lower_insn = 0xd000;
11484 }
11485 else
11486 {
11487 lower_insn = 0xc000;
6a631e86 11488 /* Round up the offset to a word boundary. */
12352d3f
PB		 11489 offset = (offset + 2) & ~2;
11490 }
11491
0855e32b
NS		 11492 neg = offset < 0;
11493 upper_insn = (0xf000
11494 | ((offset >> 12) & 0x3ff)
11495 | (neg << 10));
12352d3f 11496 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11497 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11498 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11499 bfd_put_16 (input_bfd, upper_insn, hit_data);
11500 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11501 return bfd_reloc_ok;
11502 }
11503 }
11504 /* These relocations needs special care, as besides the fact
11505 they point somewhere in .gotplt, the addend must be
11506 adjusted accordingly depending on the type of instruction
6a631e86 11507 we refer to. */
0855e32b
NS		 11508 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11509 {
11510 unsigned long data, insn;
11511 unsigned thumb;
b38cadfb 11512
0855e32b
NS		 11513 data = bfd_get_32 (input_bfd, hit_data);
11514 thumb = data & 1;
11515 data &= ~1u;
b38cadfb 11516
0855e32b
NS		 11517 if (thumb)
11518 {
11519 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11520 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11521 insn = (insn << 16)
11522 | bfd_get_16 (input_bfd,
11523 contents + rel->r_offset - data + 2);
11524 if ((insn & 0xf800c000) == 0xf000c000)
11525 /* bl/blx */
11526 value = -6;
11527 else if ((insn & 0xffffff00) == 0x4400)
11528 /* add */
11529 value = -5;
11530 else
11531 {
4eca0228 11532 _bfd_error_handler
695344c0 11533 /* xgettext:c-format */
d42c267e
AM		 11534 (_("%B(%A+%#Lx): unexpected Thumb instruction '%#lx' referenced by TLS_GOTDESC"),
11535 input_bfd, input_section, rel->r_offset, insn);
0855e32b
NS		 11536 return bfd_reloc_notsupported;
11537 }
11538 }
11539 else
11540 {
11541 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11542
11543 switch (insn >> 24)
11544 {
11545 case 0xeb: /* bl */
11546 case 0xfa: /* blx */
11547 value = -4;
11548 break;
11549
11550 case 0xe0: /* add */
11551 value = -8;
11552 break;
b38cadfb 11553
0855e32b 11554 default:
4eca0228 11555 _bfd_error_handler
695344c0 11556 /* xgettext:c-format */
d42c267e
AM		 11557 (_("%B(%A+%#Lx): unexpected ARM instruction '%#lx' referenced by TLS_GOTDESC"),
11558 input_bfd, input_section, rel->r_offset, insn);
0855e32b
NS		 11559 return bfd_reloc_notsupported;
11560 }
11561 }
b38cadfb 11562
0855e32b
NS		 11563 value += ((globals->root.sgotplt->output_section->vma
11564 + globals->root.sgotplt->output_offset + off)
11565 - (input_section->output_section->vma
11566 + input_section->output_offset
11567 + rel->r_offset)
11568 + globals->sgotplt_jump_table_size);
11569 }
11570 else
11571 value = ((globals->root.sgot->output_section->vma
11572 + globals->root.sgot->output_offset + off)
11573 - (input_section->output_section->vma
11574 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11575
11576 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11577 contents, rel->r_offset, value,
00a97672 11578 rel->r_addend);
ba93b8ac
DJ		 11579 }
11580
11581 case R_ARM_TLS_LE32:
3cbc1e5e 11582 if (bfd_link_dll (info))
ba93b8ac 11583 {
4eca0228 11584 _bfd_error_handler
695344c0 11585 /* xgettext:c-format */
d42c267e
AM		 11586 (_("%B(%A+%#Lx): %s relocation not permitted in shared object"),
11587 input_bfd, input_section, rel->r_offset, howto->name);
46691134 11588 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11589 }
11590 else
11591 value = tpoff (info, value);
906e58ca 11592
ba93b8ac 11593 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11594 contents, rel->r_offset, value,
11595 rel->r_addend);
ba93b8ac 11596
319850b4
JB		 11597 case R_ARM_V4BX:
11598 if (globals->fix_v4bx)
845b51d6
PB		 11599 {
11600 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11601
845b51d6
PB		 11602 /* Ensure that we have a BX instruction. */
11603 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11604
845b51d6
PB		 11605 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11606 {
11607 /* Branch to veneer. */
11608 bfd_vma glue_addr;
11609 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11610 glue_addr -= input_section->output_section->vma
11611 + input_section->output_offset
11612 + rel->r_offset + 8;
11613 insn = (insn & 0xf0000000) | 0x0a000000
11614 | ((glue_addr >> 2) & 0x00ffffff);
11615 }
11616 else
11617 {
11618 /* Preserve Rm (lowest four bits) and the condition code
11619 (highest four bits). Other bits encode MOV PC,Rm. */
11620 insn = (insn & 0xf000000f) | 0x01a0f000;
11621 }
319850b4 11622
845b51d6
PB		 11623 bfd_put_32 (input_bfd, insn, hit_data);
11624 }
319850b4
JB		 11625 return bfd_reloc_ok;
11626
b6895b4f
PB		 11627 case R_ARM_MOVW_ABS_NC:
11628 case R_ARM_MOVT_ABS:
11629 case R_ARM_MOVW_PREL_NC:
11630 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11631 /* Until we properly support segment-base-relative addressing then
11632 we assume the segment base to be zero, as for the group relocations.
11633 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11634 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11635 case R_ARM_MOVW_BREL_NC:
11636 case R_ARM_MOVW_BREL:
11637 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11638 {
11639 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11640
11641 if (globals->use_rel)
11642 {
11643 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11644 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11645 }
92f5d02b 11646
b6895b4f 11647 value += signed_addend;
b6895b4f
PB		 11648
11649 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11650 value -= (input_section->output_section->vma
11651 + input_section->output_offset + rel->r_offset);
11652
92f5d02b 11653 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11654 return bfd_reloc_overflow;
92f5d02b 11655
35fc36a8 11656 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11657 value |= 1;
11658
11659 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11660 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11661 value >>= 16;
11662
11663 insn &= 0xfff0f000;
11664 insn |= value & 0xfff;
11665 insn |= (value & 0xf000) << 4;
11666 bfd_put_32 (input_bfd, insn, hit_data);
11667 }
11668 return bfd_reloc_ok;
11669
11670 case R_ARM_THM_MOVW_ABS_NC:
11671 case R_ARM_THM_MOVT_ABS:
11672 case R_ARM_THM_MOVW_PREL_NC:
11673 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11674 /* Until we properly support segment-base-relative addressing then
11675 we assume the segment base to be zero, as for the above relocations.
11676 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11677 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11678 as R_ARM_THM_MOVT_ABS. */
11679 case R_ARM_THM_MOVW_BREL_NC:
11680 case R_ARM_THM_MOVW_BREL:
11681 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11682 {
11683 bfd_vma insn;
906e58ca 11684
b6895b4f
PB		 11685 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11686 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11687
11688 if (globals->use_rel)
11689 {
11690 addend = ((insn >> 4) & 0xf000)
11691 | ((insn >> 15) & 0x0800)
11692 | ((insn >> 4) & 0x0700)
11693 | (insn & 0x00ff);
39623e12 11694 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11695 }
92f5d02b 11696
b6895b4f 11697 value += signed_addend;
b6895b4f
PB		 11698
11699 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11700 value -= (input_section->output_section->vma
11701 + input_section->output_offset + rel->r_offset);
11702
92f5d02b 11703 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11704 return bfd_reloc_overflow;
92f5d02b 11705
35fc36a8 11706 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11707 value |= 1;
11708
11709 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11710 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11711 value >>= 16;
11712
11713 insn &= 0xfbf08f00;
11714 insn |= (value & 0xf000) << 4;
11715 insn |= (value & 0x0800) << 15;
11716 insn |= (value & 0x0700) << 4;
11717 insn |= (value & 0x00ff);
11718
11719 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11720 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11721 }
11722 return bfd_reloc_ok;
11723
4962c51a
MS		 11724 case R_ARM_ALU_PC_G0_NC:
11725 case R_ARM_ALU_PC_G1_NC:
11726 case R_ARM_ALU_PC_G0:
11727 case R_ARM_ALU_PC_G1:
11728 case R_ARM_ALU_PC_G2:
11729 case R_ARM_ALU_SB_G0_NC:
11730 case R_ARM_ALU_SB_G1_NC:
11731 case R_ARM_ALU_SB_G0:
11732 case R_ARM_ALU_SB_G1:
11733 case R_ARM_ALU_SB_G2:
11734 {
11735 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11736 bfd_vma pc = input_section->output_section->vma
4962c51a 11737 + input_section->output_offset + rel->r_offset;
31a91d61 11738 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11739 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11740 bfd_vma residual;
11741 bfd_vma g_n;
4962c51a 11742 bfd_signed_vma signed_value;
99059e56
RM		 11743 int group = 0;
11744
11745 /* Determine which group of bits to select. */
11746 switch (r_type)
11747 {
11748 case R_ARM_ALU_PC_G0_NC:
11749 case R_ARM_ALU_PC_G0:
11750 case R_ARM_ALU_SB_G0_NC:
11751 case R_ARM_ALU_SB_G0:
11752 group = 0;
11753 break;
11754
11755 case R_ARM_ALU_PC_G1_NC:
11756 case R_ARM_ALU_PC_G1:
11757 case R_ARM_ALU_SB_G1_NC:
11758 case R_ARM_ALU_SB_G1:
11759 group = 1;
11760 break;
11761
11762 case R_ARM_ALU_PC_G2:
11763 case R_ARM_ALU_SB_G2:
11764 group = 2;
11765 break;
11766
11767 default:
11768 abort ();
11769 }
11770
11771 /* If REL, extract the addend from the insn. If RELA, it will
11772 have already been fetched for us. */
4962c51a 11773 if (globals->use_rel)
99059e56
RM		 11774 {
11775 int negative;
11776 bfd_vma constant = insn & 0xff;
11777 bfd_vma rotation = (insn & 0xf00) >> 8;
11778
11779 if (rotation == 0)
11780 signed_addend = constant;
11781 else
11782 {
11783 /* Compensate for the fact that in the instruction, the
11784 rotation is stored in multiples of 2 bits. */
11785 rotation *= 2;
11786
11787 /* Rotate "constant" right by "rotation" bits. */
11788 signed_addend = (constant >> rotation) |
11789 (constant << (8 * sizeof (bfd_vma) - rotation));
11790 }
11791
11792 /* Determine if the instruction is an ADD or a SUB.
11793 (For REL, this determines the sign of the addend.) */
11794 negative = identify_add_or_sub (insn);
11795 if (negative == 0)
11796 {
4eca0228 11797 _bfd_error_handler
695344c0 11798 /* xgettext:c-format */
d42c267e
AM		 11799 (_("%B(%A+%#Lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11800 input_bfd, input_section, rel->r_offset);
99059e56
RM		 11801 return bfd_reloc_overflow;
11802 }
11803
11804 signed_addend *= negative;
11805 }
4962c51a
MS		 11806
11807 /* Compute the value (X) to go in the place. */
99059e56
RM		 11808 if (r_type == R_ARM_ALU_PC_G0_NC
11809 || r_type == R_ARM_ALU_PC_G1_NC
11810 || r_type == R_ARM_ALU_PC_G0
11811 || r_type == R_ARM_ALU_PC_G1
11812 || r_type == R_ARM_ALU_PC_G2)
11813 /* PC relative. */
11814 signed_value = value - pc + signed_addend;
11815 else
11816 /* Section base relative. */
11817 signed_value = value - sb + signed_addend;
11818
11819 /* If the target symbol is a Thumb function, then set the
11820 Thumb bit in the address. */
35fc36a8 11821 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11822 signed_value |= 1;
11823
99059e56
RM		 11824 /* Calculate the value of the relevant G_n, in encoded
11825 constant-with-rotation format. */
b6518b38
NC		 11826 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11827 group, &residual);
99059e56
RM		 11828
11829 /* Check for overflow if required. */
11830 if ((r_type == R_ARM_ALU_PC_G0
11831 || r_type == R_ARM_ALU_PC_G1
11832 || r_type == R_ARM_ALU_PC_G2
11833 || r_type == R_ARM_ALU_SB_G0
11834 || r_type == R_ARM_ALU_SB_G1
11835 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11836 {
4eca0228 11837 _bfd_error_handler
695344c0 11838 /* xgettext:c-format */
d42c267e
AM		 11839 (_("%B(%A+%#Lx): Overflow whilst splitting %#Lx for group relocation %s"),
11840 input_bfd, input_section, rel->r_offset,
11841 signed_value < 0 ? -signed_value : signed_value, howto->name);
99059e56
RM		 11842 return bfd_reloc_overflow;
11843 }
11844
11845 /* Mask out the value and the ADD/SUB part of the opcode; take care
11846 not to destroy the S bit. */
11847 insn &= 0xff1ff000;
11848
11849 /* Set the opcode according to whether the value to go in the
11850 place is negative. */
11851 if (signed_value < 0)
11852 insn |= 1 << 22;
11853 else
11854 insn |= 1 << 23;
11855
11856 /* Encode the offset. */
11857 insn |= g_n;
4962c51a
MS		 11858
11859 bfd_put_32 (input_bfd, insn, hit_data);
11860 }
11861 return bfd_reloc_ok;
11862
11863 case R_ARM_LDR_PC_G0:
11864 case R_ARM_LDR_PC_G1:
11865 case R_ARM_LDR_PC_G2:
11866 case R_ARM_LDR_SB_G0:
11867 case R_ARM_LDR_SB_G1:
11868 case R_ARM_LDR_SB_G2:
11869 {
11870 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11871 bfd_vma pc = input_section->output_section->vma
4962c51a 11872 + input_section->output_offset + rel->r_offset;
31a91d61 11873 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11874 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11875 bfd_vma residual;
4962c51a 11876 bfd_signed_vma signed_value;
99059e56
RM		 11877 int group = 0;
11878
11879 /* Determine which groups of bits to calculate. */
11880 switch (r_type)
11881 {
11882 case R_ARM_LDR_PC_G0:
11883 case R_ARM_LDR_SB_G0:
11884 group = 0;
11885 break;
11886
11887 case R_ARM_LDR_PC_G1:
11888 case R_ARM_LDR_SB_G1:
11889 group = 1;
11890 break;
11891
11892 case R_ARM_LDR_PC_G2:
11893 case R_ARM_LDR_SB_G2:
11894 group = 2;
11895 break;
11896
11897 default:
11898 abort ();
11899 }
11900
11901 /* If REL, extract the addend from the insn. If RELA, it will
11902 have already been fetched for us. */
4962c51a 11903 if (globals->use_rel)
99059e56
RM		 11904 {
11905 int negative = (insn & (1 << 23)) ? 1 : -1;
11906 signed_addend = negative * (insn & 0xfff);
11907 }
4962c51a
MS		 11908
11909 /* Compute the value (X) to go in the place. */
99059e56
RM		 11910 if (r_type == R_ARM_LDR_PC_G0
11911 || r_type == R_ARM_LDR_PC_G1
11912 || r_type == R_ARM_LDR_PC_G2)
11913 /* PC relative. */
11914 signed_value = value - pc + signed_addend;
11915 else
11916 /* Section base relative. */
11917 signed_value = value - sb + signed_addend;
11918
11919 /* Calculate the value of the relevant G_{n-1} to obtain
11920 the residual at that stage. */
b6518b38
NC		 11921 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11922 group - 1, &residual);
99059e56
RM		 11923
11924 /* Check for overflow. */
11925 if (residual >= 0x1000)
11926 {
4eca0228 11927 _bfd_error_handler
695344c0 11928 /* xgettext:c-format */
d42c267e
AM		 11929 (_("%B(%A+%#Lx): Overflow whilst splitting %#Lx for group relocation %s"),
11930 input_bfd, input_section, rel->r_offset,
11931 signed_value < 0 ? -signed_value : signed_value, howto->name);
99059e56
RM		 11932 return bfd_reloc_overflow;
11933 }
11934
11935 /* Mask out the value and U bit. */
11936 insn &= 0xff7ff000;
11937
11938 /* Set the U bit if the value to go in the place is non-negative. */
11939 if (signed_value >= 0)
11940 insn |= 1 << 23;
11941
11942 /* Encode the offset. */
11943 insn |= residual;
4962c51a
MS		 11944
11945 bfd_put_32 (input_bfd, insn, hit_data);
11946 }
11947 return bfd_reloc_ok;
11948
11949 case R_ARM_LDRS_PC_G0:
11950 case R_ARM_LDRS_PC_G1:
11951 case R_ARM_LDRS_PC_G2:
11952 case R_ARM_LDRS_SB_G0:
11953 case R_ARM_LDRS_SB_G1:
11954 case R_ARM_LDRS_SB_G2:
11955 {
11956 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11957 bfd_vma pc = input_section->output_section->vma
4962c51a 11958 + input_section->output_offset + rel->r_offset;
31a91d61 11959 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11960 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11961 bfd_vma residual;
4962c51a 11962 bfd_signed_vma signed_value;
99059e56
RM		 11963 int group = 0;
11964
11965 /* Determine which groups of bits to calculate. */
11966 switch (r_type)
11967 {
11968 case R_ARM_LDRS_PC_G0:
11969 case R_ARM_LDRS_SB_G0:
11970 group = 0;
11971 break;
11972
11973 case R_ARM_LDRS_PC_G1:
11974 case R_ARM_LDRS_SB_G1:
11975 group = 1;
11976 break;
11977
11978 case R_ARM_LDRS_PC_G2:
11979 case R_ARM_LDRS_SB_G2:
11980 group = 2;
11981 break;
11982
11983 default:
11984 abort ();
11985 }
11986
11987 /* If REL, extract the addend from the insn. If RELA, it will
11988 have already been fetched for us. */
4962c51a 11989 if (globals->use_rel)
99059e56
RM		 11990 {
11991 int negative = (insn & (1 << 23)) ? 1 : -1;
11992 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11993 }
4962c51a
MS		 11994
11995 /* Compute the value (X) to go in the place. */
99059e56
RM		 11996 if (r_type == R_ARM_LDRS_PC_G0
11997 || r_type == R_ARM_LDRS_PC_G1
11998 || r_type == R_ARM_LDRS_PC_G2)
11999 /* PC relative. */
12000 signed_value = value - pc + signed_addend;
12001 else
12002 /* Section base relative. */
12003 signed_value = value - sb + signed_addend;
12004
12005 /* Calculate the value of the relevant G_{n-1} to obtain
12006 the residual at that stage. */
b6518b38
NC		 12007 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12008 group - 1, &residual);
99059e56
RM		 12009
12010 /* Check for overflow. */
12011 if (residual >= 0x100)
12012 {
4eca0228 12013 _bfd_error_handler
695344c0 12014 /* xgettext:c-format */
d42c267e
AM		 12015 (_("%B(%A+%#Lx): Overflow whilst splitting %#Lx for group relocation %s"),
12016 input_bfd, input_section, rel->r_offset,
12017 signed_value < 0 ? -signed_value : signed_value, howto->name);
99059e56
RM		 12018 return bfd_reloc_overflow;
12019 }
12020
12021 /* Mask out the value and U bit. */
12022 insn &= 0xff7ff0f0;
12023
12024 /* Set the U bit if the value to go in the place is non-negative. */
12025 if (signed_value >= 0)
12026 insn |= 1 << 23;
12027
12028 /* Encode the offset. */
12029 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12030
12031 bfd_put_32 (input_bfd, insn, hit_data);
12032 }
12033 return bfd_reloc_ok;
12034
12035 case R_ARM_LDC_PC_G0:
12036 case R_ARM_LDC_PC_G1:
12037 case R_ARM_LDC_PC_G2:
12038 case R_ARM_LDC_SB_G0:
12039 case R_ARM_LDC_SB_G1:
12040 case R_ARM_LDC_SB_G2:
12041 {
12042 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12043 bfd_vma pc = input_section->output_section->vma
4962c51a 12044 + input_section->output_offset + rel->r_offset;
31a91d61 12045 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12046 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12047 bfd_vma residual;
4962c51a 12048 bfd_signed_vma signed_value;
99059e56
RM		 12049 int group = 0;
12050
12051 /* Determine which groups of bits to calculate. */
12052 switch (r_type)
12053 {
12054 case R_ARM_LDC_PC_G0:
12055 case R_ARM_LDC_SB_G0:
12056 group = 0;
12057 break;
12058
12059 case R_ARM_LDC_PC_G1:
12060 case R_ARM_LDC_SB_G1:
12061 group = 1;
12062 break;
12063
12064 case R_ARM_LDC_PC_G2:
12065 case R_ARM_LDC_SB_G2:
12066 group = 2;
12067 break;
12068
12069 default:
12070 abort ();
12071 }
12072
12073 /* If REL, extract the addend from the insn. If RELA, it will
12074 have already been fetched for us. */
4962c51a 12075 if (globals->use_rel)
99059e56
RM		 12076 {
12077 int negative = (insn & (1 << 23)) ? 1 : -1;
12078 signed_addend = negative * ((insn & 0xff) << 2);
12079 }
4962c51a
MS		 12080
12081 /* Compute the value (X) to go in the place. */
99059e56
RM		 12082 if (r_type == R_ARM_LDC_PC_G0
12083 || r_type == R_ARM_LDC_PC_G1
12084 || r_type == R_ARM_LDC_PC_G2)
12085 /* PC relative. */
12086 signed_value = value - pc + signed_addend;
12087 else
12088 /* Section base relative. */
12089 signed_value = value - sb + signed_addend;
12090
12091 /* Calculate the value of the relevant G_{n-1} to obtain
12092 the residual at that stage. */
b6518b38
NC		 12093 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12094 group - 1, &residual);
99059e56
RM		 12095
12096 /* Check for overflow. (The absolute value to go in the place must be
12097 divisible by four and, after having been divided by four, must
12098 fit in eight bits.) */
12099 if ((residual & 0x3) != 0 || residual >= 0x400)
12100 {
4eca0228 12101 _bfd_error_handler
695344c0 12102 /* xgettext:c-format */
d42c267e
AM		 12103 (_("%B(%A+%#Lx): Overflow whilst splitting %#Lx for group relocation %s"),
12104 input_bfd, input_section, rel->r_offset,
12105 signed_value < 0 ? -signed_value : signed_value, howto->name);
99059e56
RM		 12106 return bfd_reloc_overflow;
12107 }
12108
12109 /* Mask out the value and U bit. */
12110 insn &= 0xff7fff00;
12111
12112 /* Set the U bit if the value to go in the place is non-negative. */
12113 if (signed_value >= 0)
12114 insn |= 1 << 23;
12115
12116 /* Encode the offset. */
12117 insn |= residual >> 2;
4962c51a
MS		 12118
12119 bfd_put_32 (input_bfd, insn, hit_data);
12120 }
12121 return bfd_reloc_ok;
12122
72d98d16
MG		 12123 case R_ARM_THM_ALU_ABS_G0_NC:
12124 case R_ARM_THM_ALU_ABS_G1_NC:
12125 case R_ARM_THM_ALU_ABS_G2_NC:
12126 case R_ARM_THM_ALU_ABS_G3_NC:
12127 {
12128 const int shift_array[4] = {0, 8, 16, 24};
12129 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12130 bfd_vma addr = value;
12131 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12132
12133 /* Compute address. */
12134 if (globals->use_rel)
12135 signed_addend = insn & 0xff;
12136 addr += signed_addend;
12137 if (branch_type == ST_BRANCH_TO_THUMB)
12138 addr |= 1;
12139 /* Clean imm8 insn. */
12140 insn &= 0xff00;
12141 /* And update with correct part of address. */
12142 insn |= (addr >> shift) & 0xff;
12143 /* Update insn. */
12144 bfd_put_16 (input_bfd, insn, hit_data);
12145 }
12146
12147 *unresolved_reloc_p = FALSE;
12148 return bfd_reloc_ok;
12149
252b5132
RH		 12150 default:
12151 return bfd_reloc_notsupported;
12152 }
12153}
12154
98c1d4aa
NC		 12155/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12156static void
57e8b36a
NC		 12157arm_add_to_rel (bfd * abfd,
12158 bfd_byte * address,
12159 reloc_howto_type * howto,
12160 bfd_signed_vma increment)
98c1d4aa 12161{
98c1d4aa
NC		 12162 bfd_signed_vma addend;
12163
bd97cb95
DJ		 12164 if (howto->type == R_ARM_THM_CALL
12165 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12166 {
9a5aca8c
AM		 12167 int upper_insn, lower_insn;
12168 int upper, lower;
98c1d4aa 12169
9a5aca8c
AM		 12170 upper_insn = bfd_get_16 (abfd, address);
12171 lower_insn = bfd_get_16 (abfd, address + 2);
12172 upper = upper_insn & 0x7ff;
12173 lower = lower_insn & 0x7ff;
12174
12175 addend = (upper << 12) | (lower << 1);
ddda4409 12176 addend += increment;
9a5aca8c 12177 addend >>= 1;
98c1d4aa 12178
9a5aca8c
AM		 12179 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12180 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12181
dc810e39
AM		 12182 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12183 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12184 }
12185 else
12186 {
12187 bfd_vma contents;
12188
12189 contents = bfd_get_32 (abfd, address);
12190
12191 /* Get the (signed) value from the instruction. */
12192 addend = contents & howto->src_mask;
12193 if (addend & ((howto->src_mask + 1) >> 1))
12194 {
12195 bfd_signed_vma mask;
12196
12197 mask = -1;
12198 mask &= ~ howto->src_mask;
12199 addend |= mask;
12200 }
12201
12202 /* Add in the increment, (which is a byte value). */
12203 switch (howto->type)
12204 {
12205 default:
12206 addend += increment;
12207 break;
12208
12209 case R_ARM_PC24:
c6596c5e 12210 case R_ARM_PLT32:
5b5bb741
PB		 12211 case R_ARM_CALL:
12212 case R_ARM_JUMP24:
9a5aca8c 12213 addend <<= howto->size;
dc810e39 12214 addend += increment;
9a5aca8c
AM		 12215
12216 /* Should we check for overflow here ? */
12217
12218 /* Drop any undesired bits. */
12219 addend >>= howto->rightshift;
12220 break;
12221 }
12222
12223 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12224
12225 bfd_put_32 (abfd, contents, address);
ddda4409 12226 }
98c1d4aa 12227}
252b5132 12228
ba93b8ac
DJ		 12229#define IS_ARM_TLS_RELOC(R_TYPE) \
12230 ((R_TYPE) == R_ARM_TLS_GD32 \
12231 || (R_TYPE) == R_ARM_TLS_LDO32 \
12232 || (R_TYPE) == R_ARM_TLS_LDM32 \
12233 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12234 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12235 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12236 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12237 || (R_TYPE) == R_ARM_TLS_IE32 \
12238 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12239
12240/* Specific set of relocations for the gnu tls dialect. */
12241#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12242 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12243 || (R_TYPE) == R_ARM_TLS_CALL \
12244 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12245 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12246 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12247
252b5132 12248/* Relocate an ARM ELF section. */
906e58ca 12249
b34976b6 12250static bfd_boolean
57e8b36a
NC		 12251elf32_arm_relocate_section (bfd * output_bfd,
12252 struct bfd_link_info * info,
12253 bfd * input_bfd,
12254 asection * input_section,
12255 bfd_byte * contents,
12256 Elf_Internal_Rela * relocs,
12257 Elf_Internal_Sym * local_syms,
12258 asection ** local_sections)
252b5132 12259{
b34976b6
AM		 12260 Elf_Internal_Shdr *symtab_hdr;
12261 struct elf_link_hash_entry **sym_hashes;
12262 Elf_Internal_Rela *rel;
12263 Elf_Internal_Rela *relend;
12264 const char *name;
b32d3aa2 12265 struct elf32_arm_link_hash_table * globals;
252b5132 12266
4e7fd91e 12267 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12268 if (globals == NULL)
12269 return FALSE;
b491616a 12270
0ffa91dd 12271 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12272 sym_hashes = elf_sym_hashes (input_bfd);
12273
12274 rel = relocs;
12275 relend = relocs + input_section->reloc_count;
12276 for (; rel < relend; rel++)
12277 {
ba96a88f
NC		 12278 int r_type;
12279 reloc_howto_type * howto;
12280 unsigned long r_symndx;
12281 Elf_Internal_Sym * sym;
12282 asection * sec;
252b5132 12283 struct elf_link_hash_entry * h;
ba96a88f
NC		 12284 bfd_vma relocation;
12285 bfd_reloc_status_type r;
12286 arelent bfd_reloc;
ba93b8ac 12287 char sym_type;
0945cdfd 12288 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12289 char *error_message = NULL;
f21f3fe0 12290
252b5132 12291 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12292 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12293 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12294
ba96a88f 12295 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12296 || r_type == R_ARM_GNU_VTINHERIT)
12297 continue;
252b5132 12298
47aeb64c
NC		 12299 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
12300
12301 if (howto == NULL)
12302 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 12303
252b5132
RH		 12304 h = NULL;
12305 sym = NULL;
12306 sec = NULL;
9b485d32 12307
252b5132
RH		 12308 if (r_symndx < symtab_hdr->sh_info)
12309 {
12310 sym = local_syms + r_symndx;
ba93b8ac 12311 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12312 sec = local_sections[r_symndx];
ffcb4889
NS		 12313
12314 /* An object file might have a reference to a local
12315 undefined symbol. This is a daft object file, but we
12316 should at least do something about it. V4BX & NONE
12317 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12318 allowed to use the undefined symbol, so allow those.
12319 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12320 if (r_type != R_ARM_V4BX
12321 && r_type != R_ARM_NONE
77b4f08f 12322 && r_symndx != STN_UNDEF
ffcb4889
NS		 12323 && bfd_is_und_section (sec)
12324 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12325 (*info->callbacks->undefined_symbol)
12326 (info, bfd_elf_string_from_elf_section
12327 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12328 input_bfd, input_section,
12329 rel->r_offset, TRUE);
b38cadfb 12330
4e7fd91e 12331 if (globals->use_rel)
f8df10f4 12332 {
4e7fd91e
PB		 12333 relocation = (sec->output_section->vma
12334 + sec->output_offset
12335 + sym->st_value);
0e1862bb 12336 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12337 && (sec->flags & SEC_MERGE)
12338 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12339 {
4e7fd91e
PB		 12340 asection *msec;
12341 bfd_vma addend, value;
12342
39623e12 12343 switch (r_type)
4e7fd91e 12344 {
39623e12
PB		 12345 case R_ARM_MOVW_ABS_NC:
12346 case R_ARM_MOVT_ABS:
12347 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12348 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12349 addend = (addend ^ 0x8000) - 0x8000;
12350 break;
f8df10f4 12351
39623e12
PB		 12352 case R_ARM_THM_MOVW_ABS_NC:
12353 case R_ARM_THM_MOVT_ABS:
12354 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12355 << 16;
12356 value |= bfd_get_16 (input_bfd,
12357 contents + rel->r_offset + 2);
12358 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12359 | ((value & 0x04000000) >> 15);
12360 addend = (addend ^ 0x8000) - 0x8000;
12361 break;
f8df10f4 12362
39623e12
PB		 12363 default:
12364 if (howto->rightshift
12365 || (howto->src_mask & (howto->src_mask + 1)))
12366 {
4eca0228 12367 _bfd_error_handler
695344c0 12368 /* xgettext:c-format */
d42c267e 12369 (_("%B(%A+%#Lx): %s relocation against SEC_MERGE section"),
39623e12 12370 input_bfd, input_section,
d42c267e 12371 rel->r_offset, howto->name);
39623e12
PB		 12372 return FALSE;
12373 }
12374
12375 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12376
12377 /* Get the (signed) value from the instruction. */
12378 addend = value & howto->src_mask;
12379 if (addend & ((howto->src_mask + 1) >> 1))
12380 {
12381 bfd_signed_vma mask;
12382
12383 mask = -1;
12384 mask &= ~ howto->src_mask;
12385 addend |= mask;
12386 }
12387 break;
4e7fd91e 12388 }
39623e12 12389
4e7fd91e
PB		 12390 msec = sec;
12391 addend =
12392 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12393 - relocation;
12394 addend += msec->output_section->vma + msec->output_offset;
39623e12 12395
cc643b88 12396 /* Cases here must match those in the preceding
39623e12
PB		 12397 switch statement. */
12398 switch (r_type)
12399 {
12400 case R_ARM_MOVW_ABS_NC:
12401 case R_ARM_MOVT_ABS:
12402 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12403 | (addend & 0xfff);
12404 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12405 break;
12406
12407 case R_ARM_THM_MOVW_ABS_NC:
12408 case R_ARM_THM_MOVT_ABS:
12409 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12410 | (addend & 0xff) | ((addend & 0x0800) << 15);
12411 bfd_put_16 (input_bfd, value >> 16,
12412 contents + rel->r_offset);
12413 bfd_put_16 (input_bfd, value,
12414 contents + rel->r_offset + 2);
12415 break;
12416
12417 default:
12418 value = (value & ~ howto->dst_mask)
12419 | (addend & howto->dst_mask);
12420 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12421 break;
12422 }
f8df10f4 12423 }
f8df10f4 12424 }
4e7fd91e
PB		 12425 else
12426 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12427 }
12428 else
12429 {
62d887d4 12430 bfd_boolean warned, ignored;
560e09e9 12431
b2a8e766
AM		 12432 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12433 r_symndx, symtab_hdr, sym_hashes,
12434 h, sec, relocation,
62d887d4 12435 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12436
12437 sym_type = h->type;
252b5132
RH		 12438 }
12439
dbaa2011 12440 if (sec != NULL && discarded_section (sec))
e4067dbb 12441 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12442 rel, 1, relend, howto, 0, contents);
ab96bf03 12443
0e1862bb 12444 if (bfd_link_relocatable (info))
ab96bf03
AM		 12445 {
12446 /* This is a relocatable link. We don't have to change
12447 anything, unless the reloc is against a section symbol,
12448 in which case we have to adjust according to where the
12449 section symbol winds up in the output section. */
12450 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12451 {
12452 if (globals->use_rel)
12453 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12454 howto, (bfd_signed_vma) sec->output_offset);
12455 else
12456 rel->r_addend += sec->output_offset;
12457 }
12458 continue;
12459 }
12460
252b5132
RH		 12461 if (h != NULL)
12462 name = h->root.root.string;
12463 else
12464 {
12465 name = (bfd_elf_string_from_elf_section
12466 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12467 if (name == NULL || *name == '\0')
12468 name = bfd_section_name (input_bfd, sec);
12469 }
f21f3fe0 12470
cf35638d 12471 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12472 && r_type != R_ARM_NONE
12473 && (h == NULL
12474 || h->root.type == bfd_link_hash_defined
12475 || h->root.type == bfd_link_hash_defweak)
12476 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12477 {
4eca0228 12478 _bfd_error_handler
ba93b8ac 12479 ((sym_type == STT_TLS
695344c0 12480 /* xgettext:c-format */
d42c267e 12481 ? _("%B(%A+%#Lx): %s used with TLS symbol %s")
695344c0 12482 /* xgettext:c-format */
d42c267e 12483 : _("%B(%A+%#Lx): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 12484 input_bfd,
12485 input_section,
d42c267e 12486 rel->r_offset,
ba93b8ac
DJ		 12487 howto->name,
12488 name);
12489 }
12490
0855e32b 12491 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12492 done, i.e., the relaxation produced the final output we want,
12493 and we won't let anybody mess with it. Also, we have to do
12494 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12495 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12496 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12497 || (IS_ARM_TLS_GNU_RELOC (r_type)
12498 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12499 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12500 & GOT_TLS_GDESC)))
12501 {
12502 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12503 contents, rel, h == NULL);
12504 /* This may have been marked unresolved because it came from
12505 a shared library. But we've just dealt with that. */
12506 unresolved_reloc = 0;
12507 }
12508 else
12509 r = bfd_reloc_continue;
b38cadfb 12510
39d911fc
TP		 12511 if (r == bfd_reloc_continue)
12512 {
12513 unsigned char branch_type =
12514 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12515 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12516
12517 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12518 input_section, contents, rel,
12519 relocation, info, sec, name,
12520 sym_type, branch_type, h,
12521 &unresolved_reloc,
12522 &error_message);
12523 }
0945cdfd
DJ		 12524
12525 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12526 because such sections are not SEC_ALLOC and thus ld.so will
12527 not process them. */
12528 if (unresolved_reloc
99059e56
RM		 12529 && !((input_section->flags & SEC_DEBUGGING) != 0
12530 && h->def_dynamic)
1d5316ab
AM		 12531 && _bfd_elf_section_offset (output_bfd, info, input_section,
12532 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12533 {
4eca0228 12534 _bfd_error_handler
695344c0 12535 /* xgettext:c-format */
d42c267e 12536 (_("%B(%A+%#Lx): unresolvable %s relocation against symbol `%s'"),
843fe662
L		 12537 input_bfd,
12538 input_section,
d42c267e 12539 rel->r_offset,
843fe662
L		 12540 howto->name,
12541 h->root.root.string);
0945cdfd
DJ		 12542 return FALSE;
12543 }
252b5132
RH		 12544
12545 if (r != bfd_reloc_ok)
12546 {
252b5132
RH		 12547 switch (r)
12548 {
12549 case bfd_reloc_overflow:
cf919dfd
PB		 12550 /* If the overflowing reloc was to an undefined symbol,
12551 we have already printed one error message and there
12552 is no point complaining again. */
1a72702b
AM		 12553 if (!h || h->root.type != bfd_link_hash_undefined)
12554 (*info->callbacks->reloc_overflow)
12555 (info, (h ? &h->root : NULL), name, howto->name,
12556 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12557 break;
12558
12559 case bfd_reloc_undefined:
1a72702b
AM		 12560 (*info->callbacks->undefined_symbol)
12561 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12562 break;
12563
12564 case bfd_reloc_outofrange:
f2a9dd69 12565 error_message = _("out of range");
252b5132
RH		 12566 goto common_error;
12567
12568 case bfd_reloc_notsupported:
f2a9dd69 12569 error_message = _("unsupported relocation");
252b5132
RH		 12570 goto common_error;
12571
12572 case bfd_reloc_dangerous:
f2a9dd69 12573 /* error_message should already be set. */
252b5132
RH		 12574 goto common_error;
12575
12576 default:
f2a9dd69 12577 error_message = _("unknown error");
8029a119 12578 /* Fall through. */
252b5132
RH		 12579
12580 common_error:
f2a9dd69 12581 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12582 (*info->callbacks->reloc_dangerous)
12583 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12584 break;
12585 }
12586 }
12587 }
12588
b34976b6 12589 return TRUE;
252b5132
RH		 12590}
12591
91d6fa6a 12592/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12593 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12594 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12595 maintaining that condition). */
12596
12597static void
12598add_unwind_table_edit (arm_unwind_table_edit **head,
12599 arm_unwind_table_edit **tail,
12600 arm_unwind_edit_type type,
12601 asection *linked_section,
91d6fa6a 12602 unsigned int tindex)
2468f9c9 12603{
21d799b5
NC		 12604 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12605 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12606
2468f9c9
PB		 12607 new_edit->type = type;
12608 new_edit->linked_section = linked_section;
91d6fa6a 12609 new_edit->index = tindex;
b38cadfb 12610
91d6fa6a 12611 if (tindex > 0)
2468f9c9
PB		 12612 {
12613 new_edit->next = NULL;
12614
12615 if (*tail)
12616 (*tail)->next = new_edit;
12617
12618 (*tail) = new_edit;
12619
12620 if (!*head)
12621 (*head) = new_edit;
12622 }
12623 else
12624 {
12625 new_edit->next = *head;
12626
12627 if (!*tail)
12628 *tail = new_edit;
12629
12630 *head = new_edit;
12631 }
12632}
12633
12634static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12635
12636/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12637static void
12638adjust_exidx_size(asection *exidx_sec, int adjust)
12639{
12640 asection *out_sec;
12641
12642 if (!exidx_sec->rawsize)
12643 exidx_sec->rawsize = exidx_sec->size;
12644
12645 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12646 out_sec = exidx_sec->output_section;
12647 /* Adjust size of output section. */
12648 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12649}
12650
12651/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12652static void
12653insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12654{
12655 struct _arm_elf_section_data *exidx_arm_data;
12656
12657 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12658 add_unwind_table_edit (
12659 &exidx_arm_data->u.exidx.unwind_edit_list,
12660 &exidx_arm_data->u.exidx.unwind_edit_tail,
12661 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12662
491d01d3
YU		 12663 exidx_arm_data->additional_reloc_count++;
12664
2468f9c9
PB		 12665 adjust_exidx_size(exidx_sec, 8);
12666}
12667
12668/* Scan .ARM.exidx tables, and create a list describing edits which should be
12669 made to those tables, such that:
b38cadfb 12670
2468f9c9
PB		 12671 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12672 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12673 codes which have been inlined into the index).
2468f9c9 12674
85fdf906
AH		 12675 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12676
2468f9c9 12677 The edits are applied when the tables are written
b38cadfb 12678 (in elf32_arm_write_section). */
2468f9c9
PB		 12679
12680bfd_boolean
12681elf32_arm_fix_exidx_coverage (asection **text_section_order,
12682 unsigned int num_text_sections,
85fdf906
AH		 12683 struct bfd_link_info *info,
12684 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12685{
12686 bfd *inp;
12687 unsigned int last_second_word = 0, i;
12688 asection *last_exidx_sec = NULL;
12689 asection *last_text_sec = NULL;
12690 int last_unwind_type = -1;
12691
12692 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12693 text sections. */
c72f2fb2 12694 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12695 {
12696 asection *sec;
b38cadfb 12697
2468f9c9 12698 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12699 {
2468f9c9
PB		 12700 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12701 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12702
dec9d5df 12703 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12704 continue;
b38cadfb 12705
2468f9c9
PB		 12706 if (elf_sec->linked_to)
12707 {
12708 Elf_Internal_Shdr *linked_hdr
99059e56 12709 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12710 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12711 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12712
12713 if (linked_sec_arm_data == NULL)
99059e56 12714 continue;
2468f9c9
PB		 12715
12716 /* Link this .ARM.exidx section back from the text section it
99059e56 12717 describes. */
2468f9c9
PB		 12718 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12719 }
12720 }
12721 }
12722
12723 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12724 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12725 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12726
12727 for (i = 0; i < num_text_sections; i++)
12728 {
12729 asection *sec = text_section_order[i];
12730 asection *exidx_sec;
12731 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12732 struct _arm_elf_section_data *exidx_arm_data;
12733 bfd_byte *contents = NULL;
12734 int deleted_exidx_bytes = 0;
12735 bfd_vma j;
12736 arm_unwind_table_edit *unwind_edit_head = NULL;
12737 arm_unwind_table_edit *unwind_edit_tail = NULL;
12738 Elf_Internal_Shdr *hdr;
12739 bfd *ibfd;
12740
12741 if (arm_data == NULL)
99059e56 12742 continue;
2468f9c9
PB		 12743
12744 exidx_sec = arm_data->u.text.arm_exidx_sec;
12745 if (exidx_sec == NULL)
12746 {
12747 /* Section has no unwind data. */
12748 if (last_unwind_type == 0 || !last_exidx_sec)
12749 continue;
12750
12751 /* Ignore zero sized sections. */
12752 if (sec->size == 0)
12753 continue;
12754
12755 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12756 last_unwind_type = 0;
12757 continue;
12758 }
12759
22a8f80e
PB		 12760 /* Skip /DISCARD/ sections. */
12761 if (bfd_is_abs_section (exidx_sec->output_section))
12762 continue;
12763
2468f9c9
PB		 12764 hdr = &elf_section_data (exidx_sec)->this_hdr;
12765 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12766 continue;
b38cadfb 12767
2468f9c9
PB		 12768 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12769 if (exidx_arm_data == NULL)
99059e56 12770 continue;
b38cadfb 12771
2468f9c9 12772 ibfd = exidx_sec->owner;
b38cadfb 12773
2468f9c9
PB		 12774 if (hdr->contents != NULL)
12775 contents = hdr->contents;
12776 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12777 /* An error? */
12778 continue;
12779
ac06903d
YU		 12780 if (last_unwind_type > 0)
12781 {
12782 unsigned int first_word = bfd_get_32 (ibfd, contents);
12783 /* Add cantunwind if first unwind item does not match section
12784 start. */
12785 if (first_word != sec->vma)
12786 {
12787 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12788 last_unwind_type = 0;
12789 }
12790 }
12791
2468f9c9
PB		 12792 for (j = 0; j < hdr->sh_size; j += 8)
12793 {
12794 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12795 int unwind_type;
12796 int elide = 0;
12797
12798 /* An EXIDX_CANTUNWIND entry. */
12799 if (second_word == 1)
12800 {
12801 if (last_unwind_type == 0)
12802 elide = 1;
12803 unwind_type = 0;
12804 }
12805 /* Inlined unwinding data. Merge if equal to previous. */
12806 else if ((second_word & 0x80000000) != 0)
12807 {
85fdf906
AH		 12808 if (merge_exidx_entries
12809 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12810 elide = 1;
12811 unwind_type = 1;
12812 last_second_word = second_word;
12813 }
12814 /* Normal table entry. In theory we could merge these too,
12815 but duplicate entries are likely to be much less common. */
12816 else
12817 unwind_type = 2;
12818
491d01d3 12819 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12820 {
12821 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12822 DELETE_EXIDX_ENTRY, NULL, j / 8);
12823
12824 deleted_exidx_bytes += 8;
12825 }
12826
12827 last_unwind_type = unwind_type;
12828 }
12829
12830 /* Free contents if we allocated it ourselves. */
12831 if (contents != hdr->contents)
99059e56 12832 free (contents);
2468f9c9
PB		 12833
12834 /* Record edits to be applied later (in elf32_arm_write_section). */
12835 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12836 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12837
2468f9c9
PB		 12838 if (deleted_exidx_bytes > 0)
12839 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12840
12841 last_exidx_sec = exidx_sec;
12842 last_text_sec = sec;
12843 }
12844
12845 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12846 if (!bfd_link_relocatable (info) && last_exidx_sec
12847 && last_unwind_type != 0)
2468f9c9
PB		 12848 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12849
12850 return TRUE;
12851}
12852
3e6b1042
DJ		 12853static bfd_boolean
12854elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12855 bfd *ibfd, const char *name)
12856{
12857 asection *sec, *osec;
12858
3d4d4302 12859 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12860 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12861 return TRUE;
12862
12863 osec = sec->output_section;
12864 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12865 return TRUE;
12866
12867 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12868 sec->output_offset, sec->size))
12869 return FALSE;
12870
12871 return TRUE;
12872}
12873
12874static bfd_boolean
12875elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12876{
12877 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12878 asection *sec, *osec;
3e6b1042 12879
4dfe6ac6
NC		 12880 if (globals == NULL)
12881 return FALSE;
12882
3e6b1042
DJ		 12883 /* Invoke the regular ELF backend linker to do all the work. */
12884 if (!bfd_elf_final_link (abfd, info))
12885 return FALSE;
12886
fe33d2fa
CL		 12887 /* Process stub sections (eg BE8 encoding, ...). */
12888 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12889 unsigned int i;
cdb21a0a
NS		 12890 for (i=0; i<htab->top_id; i++)
12891 {
12892 sec = htab->stub_group[i].stub_sec;
12893 /* Only process it once, in its link_sec slot. */
12894 if (sec && i == htab->stub_group[i].link_sec->id)
12895 {
12896 osec = sec->output_section;
12897 elf32_arm_write_section (abfd, info, sec, sec->contents);
12898 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12899 sec->output_offset, sec->size))
12900 return FALSE;
12901 }
fe33d2fa 12902 }
fe33d2fa 12903
3e6b1042
DJ		 12904 /* Write out any glue sections now that we have created all the
12905 stubs. */
12906 if (globals->bfd_of_glue_owner != NULL)
12907 {
12908 if (! elf32_arm_output_glue_section (info, abfd,
12909 globals->bfd_of_glue_owner,
12910 ARM2THUMB_GLUE_SECTION_NAME))
12911 return FALSE;
12912
12913 if (! elf32_arm_output_glue_section (info, abfd,
12914 globals->bfd_of_glue_owner,
12915 THUMB2ARM_GLUE_SECTION_NAME))
12916 return FALSE;
12917
12918 if (! elf32_arm_output_glue_section (info, abfd,
12919 globals->bfd_of_glue_owner,
12920 VFP11_ERRATUM_VENEER_SECTION_NAME))
12921 return FALSE;
12922
a504d23a
LA		 12923 if (! elf32_arm_output_glue_section (info, abfd,
12924 globals->bfd_of_glue_owner,
12925 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12926 return FALSE;
12927
3e6b1042
DJ		 12928 if (! elf32_arm_output_glue_section (info, abfd,
12929 globals->bfd_of_glue_owner,
12930 ARM_BX_GLUE_SECTION_NAME))
12931 return FALSE;
12932 }
12933
12934 return TRUE;
12935}
12936
5968a7b8
NC		 12937/* Return a best guess for the machine number based on the attributes. */
12938
12939static unsigned int
12940bfd_arm_get_mach_from_attributes (bfd * abfd)
12941{
12942 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12943
12944 switch (arch)
12945 {
12946 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12947 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12948 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12949
12950 case TAG_CPU_ARCH_V5TE:
12951 {
12952 char * name;
12953
12954 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12955 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12956
12957 if (name)
12958 {
12959 if (strcmp (name, "IWMMXT2") == 0)
12960 return bfd_mach_arm_iWMMXt2;
12961
12962 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12963 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12964
12965 if (strcmp (name, "XSCALE") == 0)
12966 {
12967 int wmmx;
12968
12969 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12970 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12971 switch (wmmx)
12972 {
12973 case 1: return bfd_mach_arm_iWMMXt;
12974 case 2: return bfd_mach_arm_iWMMXt2;
12975 default: return bfd_mach_arm_XScale;
12976 }
12977 }
5968a7b8
NC		 12978 }
12979
12980 return bfd_mach_arm_5TE;
12981 }
12982
12983 default:
12984 return bfd_mach_arm_unknown;
12985 }
12986}
12987
c178919b
NC		 12988/* Set the right machine number. */
12989
12990static bfd_boolean
57e8b36a 12991elf32_arm_object_p (bfd *abfd)
c178919b 12992{
5a6c6817 12993 unsigned int mach;
57e8b36a 12994
5a6c6817 12995 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12996
5968a7b8
NC		 12997 if (mach == bfd_mach_arm_unknown)
12998 {
12999 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13000 mach = bfd_mach_arm_ep9312;
13001 else
13002 mach = bfd_arm_get_mach_from_attributes (abfd);
13003 }
c178919b 13004
5968a7b8 13005 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13006 return TRUE;
13007}
13008
fc830a83 13009/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13010
b34976b6 13011static bfd_boolean
57e8b36a 13012elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13013{
13014 if (elf_flags_init (abfd)
13015 && elf_elfheader (abfd)->e_flags != flags)
13016 {
fc830a83
NC		 13017 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13018 {
fd2ec330 13019 if (flags & EF_ARM_INTERWORK)
4eca0228 13020 _bfd_error_handler
d003868e
AM		 13021 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
13022 abfd);
fc830a83 13023 else
d003868e
AM		 13024 _bfd_error_handler
13025 (_("Warning: Clearing the interworking flag of %B due to outside request"),
13026 abfd);
fc830a83 13027 }
252b5132
RH		 13028 }
13029 else
13030 {
13031 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13032 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13033 }
13034
b34976b6 13035 return TRUE;
252b5132
RH		 13036}
13037
fc830a83 13038/* Copy backend specific data from one object module to another. */
9b485d32 13039
b34976b6 13040static bfd_boolean
57e8b36a 13041elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13042{
13043 flagword in_flags;
13044 flagword out_flags;
13045
0ffa91dd 13046 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13047 return TRUE;
252b5132 13048
fc830a83 13049 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13050 out_flags = elf_elfheader (obfd)->e_flags;
13051
fc830a83
NC		 13052 if (elf_flags_init (obfd)
13053 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13054 && in_flags != out_flags)
252b5132 13055 {
252b5132 13056 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13057 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13058 return FALSE;
252b5132
RH		 13059
13060 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13061 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13062 return FALSE;
252b5132
RH		 13063
13064 /* If the src and dest have different interworking flags
99059e56 13065 then turn off the interworking bit. */
fd2ec330 13066 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13067 {
fd2ec330 13068 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 13069 _bfd_error_handler
13070 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
13071 obfd, ibfd);
252b5132 13072
fd2ec330 13073 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13074 }
1006ba19
PB		 13075
13076 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13077 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13078 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13079 }
13080
13081 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13082 elf_flags_init (obfd) = TRUE;
252b5132 13083
e2349352 13084 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13085}
13086
13087/* Values for Tag_ABI_PCS_R9_use. */
13088enum
13089{
13090 AEABI_R9_V6,
13091 AEABI_R9_SB,
13092 AEABI_R9_TLS,
13093 AEABI_R9_unused
13094};
13095
13096/* Values for Tag_ABI_PCS_RW_data. */
13097enum
13098{
13099 AEABI_PCS_RW_data_absolute,
13100 AEABI_PCS_RW_data_PCrel,
13101 AEABI_PCS_RW_data_SBrel,
13102 AEABI_PCS_RW_data_unused
13103};
13104
13105/* Values for Tag_ABI_enum_size. */
13106enum
13107{
13108 AEABI_enum_unused,
13109 AEABI_enum_short,
13110 AEABI_enum_wide,
13111 AEABI_enum_forced_wide
13112};
13113
104d59d1
JM		 13114/* Determine whether an object attribute tag takes an integer, a
13115 string or both. */
906e58ca 13116
104d59d1
JM		 13117static int
13118elf32_arm_obj_attrs_arg_type (int tag)
13119{
13120 if (tag == Tag_compatibility)
3483fe2e 13121 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13122 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13123 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13124 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13125 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13126 else if (tag < 32)
3483fe2e 13127 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13128 else
3483fe2e 13129 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13130}
13131
5aa6ff7c
AS		 13132/* The ABI defines that Tag_conformance should be emitted first, and that
13133 Tag_nodefaults should be second (if either is defined). This sets those
13134 two positions, and bumps up the position of all the remaining tags to
13135 compensate. */
13136static int
13137elf32_arm_obj_attrs_order (int num)
13138{
3de4a297 13139 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13140 return Tag_conformance;
3de4a297 13141 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13142 return Tag_nodefaults;
13143 if ((num - 2) < Tag_nodefaults)
13144 return num - 2;
13145 if ((num - 1) < Tag_conformance)
13146 return num - 1;
13147 return num;
13148}
13149
e8b36cd1
JM		 13150/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13151static bfd_boolean
13152elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13153{
13154 if ((tag & 127) < 64)
13155 {
13156 _bfd_error_handler
13157 (_("%B: Unknown mandatory EABI object attribute %d"),
13158 abfd, tag);
13159 bfd_set_error (bfd_error_bad_value);
13160 return FALSE;
13161 }
13162 else
13163 {
13164 _bfd_error_handler
13165 (_("Warning: %B: Unknown EABI object attribute %d"),
13166 abfd, tag);
13167 return TRUE;
13168 }
13169}
13170
91e22acd
AS		 13171/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13172 Returns -1 if no architecture could be read. */
13173
13174static int
13175get_secondary_compatible_arch (bfd *abfd)
13176{
13177 obj_attribute *attr =
13178 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13179
13180 /* Note: the tag and its argument below are uleb128 values, though
13181 currently-defined values fit in one byte for each. */
13182 if (attr->s
13183 && attr->s[0] == Tag_CPU_arch
13184 && (attr->s[1] & 128) != 128
13185 && attr->s[2] == 0)
13186 return attr->s[1];
13187
13188 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13189 return -1;
13190}
13191
13192/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13193 The tag is removed if ARCH is -1. */
13194
8e79c3df 13195static void
91e22acd 13196set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13197{
91e22acd
AS		 13198 obj_attribute *attr =
13199 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13200
91e22acd
AS		 13201 if (arch == -1)
13202 {
13203 attr->s = NULL;
13204 return;
8e79c3df 13205 }
91e22acd
AS		 13206
13207 /* Note: the tag and its argument below are uleb128 values, though
13208 currently-defined values fit in one byte for each. */
13209 if (!attr->s)
21d799b5 13210 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13211 attr->s[0] = Tag_CPU_arch;
13212 attr->s[1] = arch;
13213 attr->s[2] = '\0';
8e79c3df
CM		 13214}
13215
91e22acd
AS		 13216/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13217 into account. */
13218
13219static int
13220tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13221 int newtag, int secondary_compat)
8e79c3df 13222{
91e22acd
AS		 13223#define T(X) TAG_CPU_ARCH_##X
13224 int tagl, tagh, result;
13225 const int v6t2[] =
13226 {
13227 T(V6T2), /* PRE_V4. */
13228 T(V6T2), /* V4. */
13229 T(V6T2), /* V4T. */
13230 T(V6T2), /* V5T. */
13231 T(V6T2), /* V5TE. */
13232 T(V6T2), /* V5TEJ. */
13233 T(V6T2), /* V6. */
13234 T(V7), /* V6KZ. */
13235 T(V6T2) /* V6T2. */
13236 };
13237 const int v6k[] =
13238 {
13239 T(V6K), /* PRE_V4. */
13240 T(V6K), /* V4. */
13241 T(V6K), /* V4T. */
13242 T(V6K), /* V5T. */
13243 T(V6K), /* V5TE. */
13244 T(V6K), /* V5TEJ. */
13245 T(V6K), /* V6. */
13246 T(V6KZ), /* V6KZ. */
13247 T(V7), /* V6T2. */
13248 T(V6K) /* V6K. */
13249 };
13250 const int v7[] =
13251 {
13252 T(V7), /* PRE_V4. */
13253 T(V7), /* V4. */
13254 T(V7), /* V4T. */
13255 T(V7), /* V5T. */
13256 T(V7), /* V5TE. */
13257 T(V7), /* V5TEJ. */
13258 T(V7), /* V6. */
13259 T(V7), /* V6KZ. */
13260 T(V7), /* V6T2. */
13261 T(V7), /* V6K. */
13262 T(V7) /* V7. */
13263 };
13264 const int v6_m[] =
13265 {
13266 -1, /* PRE_V4. */
13267 -1, /* V4. */
13268 T(V6K), /* V4T. */
13269 T(V6K), /* V5T. */
13270 T(V6K), /* V5TE. */
13271 T(V6K), /* V5TEJ. */
13272 T(V6K), /* V6. */
13273 T(V6KZ), /* V6KZ. */
13274 T(V7), /* V6T2. */
13275 T(V6K), /* V6K. */
13276 T(V7), /* V7. */
13277 T(V6_M) /* V6_M. */
13278 };
13279 const int v6s_m[] =
13280 {
13281 -1, /* PRE_V4. */
13282 -1, /* V4. */
13283 T(V6K), /* V4T. */
13284 T(V6K), /* V5T. */
13285 T(V6K), /* V5TE. */
13286 T(V6K), /* V5TEJ. */
13287 T(V6K), /* V6. */
13288 T(V6KZ), /* V6KZ. */
13289 T(V7), /* V6T2. */
13290 T(V6K), /* V6K. */
13291 T(V7), /* V7. */
13292 T(V6S_M), /* V6_M. */
13293 T(V6S_M) /* V6S_M. */
13294 };
9e3c6df6
PB		 13295 const int v7e_m[] =
13296 {
13297 -1, /* PRE_V4. */
13298 -1, /* V4. */
13299 T(V7E_M), /* V4T. */
13300 T(V7E_M), /* V5T. */
13301 T(V7E_M), /* V5TE. */
13302 T(V7E_M), /* V5TEJ. */
13303 T(V7E_M), /* V6. */
13304 T(V7E_M), /* V6KZ. */
13305 T(V7E_M), /* V6T2. */
13306 T(V7E_M), /* V6K. */
13307 T(V7E_M), /* V7. */
13308 T(V7E_M), /* V6_M. */
13309 T(V7E_M), /* V6S_M. */
13310 T(V7E_M) /* V7E_M. */
13311 };
bca38921
MGD		 13312 const int v8[] =
13313 {
13314 T(V8), /* PRE_V4. */
13315 T(V8), /* V4. */
13316 T(V8), /* V4T. */
13317 T(V8), /* V5T. */
13318 T(V8), /* V5TE. */
13319 T(V8), /* V5TEJ. */
13320 T(V8), /* V6. */
13321 T(V8), /* V6KZ. */
13322 T(V8), /* V6T2. */
13323 T(V8), /* V6K. */
13324 T(V8), /* V7. */
13325 T(V8), /* V6_M. */
13326 T(V8), /* V6S_M. */
13327 T(V8), /* V7E_M. */
13328 T(V8) /* V8. */
13329 };
bff0500d
TP		 13330 const int v8r[] =
13331 {
13332 T(V8R), /* PRE_V4. */
13333 T(V8R), /* V4. */
13334 T(V8R), /* V4T. */
13335 T(V8R), /* V5T. */
13336 T(V8R), /* V5TE. */
13337 T(V8R), /* V5TEJ. */
13338 T(V8R), /* V6. */
13339 T(V8R), /* V6KZ. */
13340 T(V8R), /* V6T2. */
13341 T(V8R), /* V6K. */
13342 T(V8R), /* V7. */
13343 T(V8R), /* V6_M. */
13344 T(V8R), /* V6S_M. */
13345 T(V8R), /* V7E_M. */
13346 T(V8), /* V8. */
13347 T(V8R), /* V8R. */
13348 };
2fd158eb
TP		 13349 const int v8m_baseline[] =
13350 {
13351 -1, /* PRE_V4. */
13352 -1, /* V4. */
13353 -1, /* V4T. */
13354 -1, /* V5T. */
13355 -1, /* V5TE. */
13356 -1, /* V5TEJ. */
13357 -1, /* V6. */
13358 -1, /* V6KZ. */
13359 -1, /* V6T2. */
13360 -1, /* V6K. */
13361 -1, /* V7. */
13362 T(V8M_BASE), /* V6_M. */
13363 T(V8M_BASE), /* V6S_M. */
13364 -1, /* V7E_M. */
13365 -1, /* V8. */
bff0500d 13366 -1, /* V8R. */
2fd158eb
TP		 13367 T(V8M_BASE) /* V8-M BASELINE. */
13368 };
13369 const int v8m_mainline[] =
13370 {
13371 -1, /* PRE_V4. */
13372 -1, /* V4. */
13373 -1, /* V4T. */
13374 -1, /* V5T. */
13375 -1, /* V5TE. */
13376 -1, /* V5TEJ. */
13377 -1, /* V6. */
13378 -1, /* V6KZ. */
13379 -1, /* V6T2. */
13380 -1, /* V6K. */
13381 T(V8M_MAIN), /* V7. */
13382 T(V8M_MAIN), /* V6_M. */
13383 T(V8M_MAIN), /* V6S_M. */
13384 T(V8M_MAIN), /* V7E_M. */
13385 -1, /* V8. */
bff0500d 13386 -1, /* V8R. */
2fd158eb
TP		 13387 T(V8M_MAIN), /* V8-M BASELINE. */
13388 T(V8M_MAIN) /* V8-M MAINLINE. */
13389 };
91e22acd
AS		 13390 const int v4t_plus_v6_m[] =
13391 {
13392 -1, /* PRE_V4. */
13393 -1, /* V4. */
13394 T(V4T), /* V4T. */
13395 T(V5T), /* V5T. */
13396 T(V5TE), /* V5TE. */
13397 T(V5TEJ), /* V5TEJ. */
13398 T(V6), /* V6. */
13399 T(V6KZ), /* V6KZ. */
13400 T(V6T2), /* V6T2. */
13401 T(V6K), /* V6K. */
13402 T(V7), /* V7. */
13403 T(V6_M), /* V6_M. */
13404 T(V6S_M), /* V6S_M. */
9e3c6df6 13405 T(V7E_M), /* V7E_M. */
bca38921 13406 T(V8), /* V8. */
bff0500d 13407 -1, /* V8R. */
2fd158eb
TP		 13408 T(V8M_BASE), /* V8-M BASELINE. */
13409 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13410 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13411 };
13412 const int *comb[] =
13413 {
13414 v6t2,
13415 v6k,
13416 v7,
13417 v6_m,
13418 v6s_m,
9e3c6df6 13419 v7e_m,
bca38921 13420 v8,
bff0500d 13421 v8r,
2fd158eb
TP		 13422 v8m_baseline,
13423 v8m_mainline,
91e22acd
AS		 13424 /* Pseudo-architecture. */
13425 v4t_plus_v6_m
13426 };
13427
13428 /* Check we've not got a higher architecture than we know about. */
13429
9e3c6df6 13430 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13431 {
3895f852 13432 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 13433 return -1;
13434 }
13435
13436 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13437
13438 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13439 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13440 oldtag = T(V4T_PLUS_V6_M);
13441
13442 /* And override the new tag if we have a Tag_also_compatible_with on the
13443 input. */
13444
13445 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13446 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13447 newtag = T(V4T_PLUS_V6_M);
13448
13449 tagl = (oldtag < newtag) ? oldtag : newtag;
13450 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13451
13452 /* Architectures before V6KZ add features monotonically. */
13453 if (tagh <= TAG_CPU_ARCH_V6KZ)
13454 return result;
13455
4ed7ed8d 13456 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13457
13458 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13459 as the canonical version. */
13460 if (result == T(V4T_PLUS_V6_M))
13461 {
13462 result = T(V4T);
13463 *secondary_compat_out = T(V6_M);
13464 }
13465 else
13466 *secondary_compat_out = -1;
13467
13468 if (result == -1)
13469 {
3895f852 13470 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13471 ibfd, oldtag, newtag);
13472 return -1;
13473 }
13474
13475 return result;
13476#undef T
8e79c3df
CM		 13477}
13478
ac56ee8f
MGD		 13479/* Query attributes object to see if integer divide instructions may be
13480 present in an object. */
13481static bfd_boolean
13482elf32_arm_attributes_accept_div (const obj_attribute *attr)
13483{
13484 int arch = attr[Tag_CPU_arch].i;
13485 int profile = attr[Tag_CPU_arch_profile].i;
13486
13487 switch (attr[Tag_DIV_use].i)
13488 {
13489 case 0:
13490 /* Integer divide allowed if instruction contained in archetecture. */
13491 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13492 return TRUE;
13493 else if (arch >= TAG_CPU_ARCH_V7E_M)
13494 return TRUE;
13495 else
13496 return FALSE;
13497
13498 case 1:
13499 /* Integer divide explicitly prohibited. */
13500 return FALSE;
13501
13502 default:
13503 /* Unrecognised case - treat as allowing divide everywhere. */
13504 case 2:
13505 /* Integer divide allowed in ARM state. */
13506 return TRUE;
13507 }
13508}
13509
13510/* Query attributes object to see if integer divide instructions are
13511 forbidden to be in the object. This is not the inverse of
13512 elf32_arm_attributes_accept_div. */
13513static bfd_boolean
13514elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13515{
13516 return attr[Tag_DIV_use].i == 1;
13517}
13518
ee065d83
PB		 13519/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13520 are conflicting attributes. */
906e58ca 13521
ee065d83 13522static bfd_boolean
50e03d47 13523elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 13524{
50e03d47 13525 bfd *obfd = info->output_bfd;
104d59d1
JM		 13526 obj_attribute *in_attr;
13527 obj_attribute *out_attr;
ee065d83
PB		 13528 /* Some tags have 0 = don't care, 1 = strong requirement,
13529 2 = weak requirement. */
91e22acd 13530 static const int order_021[3] = {0, 2, 1};
ee065d83 13531 int i;
91e22acd 13532 bfd_boolean result = TRUE;
9274e9de 13533 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13534
3e6b1042
DJ		 13535 /* Skip the linker stubs file. This preserves previous behavior
13536 of accepting unknown attributes in the first input file - but
13537 is that a bug? */
13538 if (ibfd->flags & BFD_LINKER_CREATED)
13539 return TRUE;
13540
9274e9de
TG		 13541 /* Skip any input that hasn't attribute section.
13542 This enables to link object files without attribute section with
13543 any others. */
13544 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13545 return TRUE;
13546
104d59d1 13547 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13548 {
13549 /* This is the first object. Copy the attributes. */
104d59d1 13550 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13551
cd21e546
MGD		 13552 out_attr = elf_known_obj_attributes_proc (obfd);
13553
004ae526
PB		 13554 /* Use the Tag_null value to indicate the attributes have been
13555 initialized. */
cd21e546 13556 out_attr[0].i = 1;
004ae526 13557
cd21e546
MGD		 13558 /* We do not output objects with Tag_MPextension_use_legacy - we move
13559 the attribute's value to Tag_MPextension_use. */
13560 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13561 {
13562 if (out_attr[Tag_MPextension_use].i != 0
13563 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13564 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13565 {
13566 _bfd_error_handler
13567 (_("Error: %B has both the current and legacy "
13568 "Tag_MPextension_use attributes"), ibfd);
13569 result = FALSE;
13570 }
13571
13572 out_attr[Tag_MPextension_use] =
13573 out_attr[Tag_MPextension_use_legacy];
13574 out_attr[Tag_MPextension_use_legacy].type = 0;
13575 out_attr[Tag_MPextension_use_legacy].i = 0;
13576 }
13577
13578 return result;
ee065d83
PB		 13579 }
13580
104d59d1
JM		 13581 in_attr = elf_known_obj_attributes_proc (ibfd);
13582 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13583 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13584 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13585 {
5c294fee
TG		 13586 /* Ignore mismatches if the object doesn't use floating point or is
13587 floating point ABI independent. */
13588 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13589 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13590 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13591 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13592 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13593 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13594 {
13595 _bfd_error_handler
3895f852 13596 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13597 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13598 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13599 result = FALSE;
ee065d83
PB		 13600 }
13601 }
13602
3de4a297 13603 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13604 {
13605 /* Merge this attribute with existing attributes. */
13606 switch (i)
13607 {
13608 case Tag_CPU_raw_name:
13609 case Tag_CPU_name:
6a631e86 13610 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13611 break;
13612
13613 case Tag_ABI_optimization_goals:
13614 case Tag_ABI_FP_optimization_goals:
13615 /* Use the first value seen. */
13616 break;
13617
13618 case Tag_CPU_arch:
91e22acd
AS		 13619 {
13620 int secondary_compat = -1, secondary_compat_out = -1;
13621 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13622 int arch_attr;
13623 static const char *name_table[] =
13624 {
91e22acd
AS		 13625 /* These aren't real CPU names, but we can't guess
13626 that from the architecture version alone. */
13627 "Pre v4",
13628 "ARM v4",
13629 "ARM v4T",
13630 "ARM v5T",
13631 "ARM v5TE",
13632 "ARM v5TEJ",
13633 "ARM v6",
13634 "ARM v6KZ",
13635 "ARM v6T2",
13636 "ARM v6K",
13637 "ARM v7",
13638 "ARM v6-M",
bca38921 13639 "ARM v6S-M",
2fd158eb
TP		 13640 "ARM v8",
13641 "",
13642 "ARM v8-M.baseline",
13643 "ARM v8-M.mainline",
91e22acd
AS		 13644 };
13645
13646 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13647 secondary_compat = get_secondary_compatible_arch (ibfd);
13648 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13649 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13650 &secondary_compat_out,
13651 in_attr[i].i,
13652 secondary_compat);
13653
13654 /* Return with error if failed to merge. */
13655 if (arch_attr == -1)
13656 return FALSE;
13657
13658 out_attr[i].i = arch_attr;
13659
91e22acd
AS		 13660 set_secondary_compatible_arch (obfd, secondary_compat_out);
13661
13662 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13663 if (out_attr[i].i == saved_out_attr)
13664 ; /* Leave the names alone. */
13665 else if (out_attr[i].i == in_attr[i].i)
13666 {
13667 /* The output architecture has been changed to match the
13668 input architecture. Use the input names. */
13669 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13670 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13671 : NULL;
13672 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13673 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13674 : NULL;
13675 }
13676 else
13677 {
13678 out_attr[Tag_CPU_name].s = NULL;
13679 out_attr[Tag_CPU_raw_name].s = NULL;
13680 }
13681
13682 /* If we still don't have a value for Tag_CPU_name,
13683 make one up now. Tag_CPU_raw_name remains blank. */
13684 if (out_attr[Tag_CPU_name].s == NULL
13685 && out_attr[i].i < ARRAY_SIZE (name_table))
13686 out_attr[Tag_CPU_name].s =
13687 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13688 }
13689 break;
13690
ee065d83
PB		 13691 case Tag_ARM_ISA_use:
13692 case Tag_THUMB_ISA_use:
ee065d83 13693 case Tag_WMMX_arch:
91e22acd
AS		 13694 case Tag_Advanced_SIMD_arch:
13695 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13696 case Tag_ABI_FP_rounding:
ee065d83
PB		 13697 case Tag_ABI_FP_exceptions:
13698 case Tag_ABI_FP_user_exceptions:
13699 case Tag_ABI_FP_number_model:
75375b3e 13700 case Tag_FP_HP_extension:
91e22acd
AS		 13701 case Tag_CPU_unaligned_access:
13702 case Tag_T2EE_use:
91e22acd 13703 case Tag_MPextension_use:
ee065d83
PB		 13704 /* Use the largest value specified. */
13705 if (in_attr[i].i > out_attr[i].i)
13706 out_attr[i].i = in_attr[i].i;
13707 break;
13708
75375b3e 13709 case Tag_ABI_align_preserved:
91e22acd
AS		 13710 case Tag_ABI_PCS_RO_data:
13711 /* Use the smallest value specified. */
13712 if (in_attr[i].i < out_attr[i].i)
13713 out_attr[i].i = in_attr[i].i;
13714 break;
13715
75375b3e 13716 case Tag_ABI_align_needed:
91e22acd 13717 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13718 && (in_attr[Tag_ABI_align_preserved].i == 0
13719 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13720 {
91e22acd
AS		 13721 /* This error message should be enabled once all non-conformant
13722 binaries in the toolchain have had the attributes set
13723 properly.
ee065d83 13724 _bfd_error_handler
3895f852 13725 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13726 obfd, ibfd);
13727 result = FALSE; */
ee065d83 13728 }
91e22acd
AS		 13729 /* Fall through. */
13730 case Tag_ABI_FP_denormal:
13731 case Tag_ABI_PCS_GOT_use:
13732 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13733 value if greater than 2 (for future-proofing). */
13734 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13735 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13736 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13737 out_attr[i].i = in_attr[i].i;
13738 break;
91e22acd 13739
75375b3e
MGD		 13740 case Tag_Virtualization_use:
13741 /* The virtualization tag effectively stores two bits of
13742 information: the intended use of TrustZone (in bit 0), and the
13743 intended use of Virtualization (in bit 1). */
13744 if (out_attr[i].i == 0)
13745 out_attr[i].i = in_attr[i].i;
13746 else if (in_attr[i].i != 0
13747 && in_attr[i].i != out_attr[i].i)
13748 {
13749 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13750 out_attr[i].i = 3;
13751 else
13752 {
13753 _bfd_error_handler
13754 (_("error: %B: unable to merge virtualization attributes "
13755 "with %B"),
13756 obfd, ibfd);
13757 result = FALSE;
13758 }
13759 }
13760 break;
91e22acd
AS		 13761
13762 case Tag_CPU_arch_profile:
13763 if (out_attr[i].i != in_attr[i].i)
13764 {
13765 /* 0 will merge with anything.
13766 'A' and 'S' merge to 'A'.
13767 'R' and 'S' merge to 'R'.
99059e56 13768 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13769 if (out_attr[i].i == 0
13770 || (out_attr[i].i == 'S'
13771 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13772 out_attr[i].i = in_attr[i].i;
13773 else if (in_attr[i].i == 0
13774 || (in_attr[i].i == 'S'
13775 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13776 ; /* Do nothing. */
91e22acd
AS		 13777 else
13778 {
13779 _bfd_error_handler
3895f852 13780 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13781 ibfd,
13782 in_attr[i].i ? in_attr[i].i : '0',
13783 out_attr[i].i ? out_attr[i].i : '0');
13784 result = FALSE;
13785 }
13786 }
13787 break;
15afaa63
TP		 13788
13789 case Tag_DSP_extension:
13790 /* No need to change output value if any of:
13791 - pre (<=) ARMv5T input architecture (do not have DSP)
13792 - M input profile not ARMv7E-M and do not have DSP. */
13793 if (in_attr[Tag_CPU_arch].i <= 3
13794 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13795 && in_attr[Tag_CPU_arch].i != 13
13796 && in_attr[i].i == 0))
13797 ; /* Do nothing. */
13798 /* Output value should be 0 if DSP part of architecture, ie.
13799 - post (>=) ARMv5te architecture output
13800 - A, R or S profile output or ARMv7E-M output architecture. */
13801 else if (out_attr[Tag_CPU_arch].i >= 4
13802 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13803 || out_attr[Tag_CPU_arch_profile].i == 'R'
13804 || out_attr[Tag_CPU_arch_profile].i == 'S'
13805 || out_attr[Tag_CPU_arch].i == 13))
13806 out_attr[i].i = 0;
13807 /* Otherwise, DSP instructions are added and not part of output
13808 architecture. */
13809 else
13810 out_attr[i].i = 1;
13811 break;
13812
75375b3e 13813 case Tag_FP_arch:
62f3b8c8 13814 {
4547cb56
NC		 13815 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13816 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13817 when it's 0. It might mean absence of FP hardware if
99654aaf 13818 Tag_FP_arch is zero. */
4547cb56 13819
a715796b 13820#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13821 static const struct
13822 {
13823 int ver;
13824 int regs;
bca38921 13825 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13826 {
13827 {0, 0},
13828 {1, 16},
13829 {2, 16},
13830 {3, 32},
13831 {3, 16},
13832 {4, 32},
bca38921 13833 {4, 16},
a715796b
TG		 13834 {8, 32},
13835 {8, 16}
62f3b8c8
PB		 13836 };
13837 int ver;
13838 int regs;
13839 int newval;
13840
4547cb56
NC		 13841 /* If the output has no requirement about FP hardware,
13842 follow the requirement of the input. */
13843 if (out_attr[i].i == 0)
13844 {
4ec192e6
RE		 13845 /* This assert is still reasonable, we shouldn't
13846 produce the suspicious build attribute
13847 combination (See below for in_attr). */
4547cb56
NC		 13848 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13849 out_attr[i].i = in_attr[i].i;
13850 out_attr[Tag_ABI_HardFP_use].i
13851 = in_attr[Tag_ABI_HardFP_use].i;
13852 break;
13853 }
13854 /* If the input has no requirement about FP hardware, do
13855 nothing. */
13856 else if (in_attr[i].i == 0)
13857 {
4ec192e6
RE		 13858 /* We used to assert that Tag_ABI_HardFP_use was
13859 zero here, but we should never assert when
13860 consuming an object file that has suspicious
13861 build attributes. The single precision variant
13862 of 'no FP architecture' is still 'no FP
13863 architecture', so we just ignore the tag in this
13864 case. */
4547cb56
NC		 13865 break;
13866 }
13867
13868 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13869 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13870
13871 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13872 do nothing. */
13873 if (in_attr[Tag_ABI_HardFP_use].i == 0
13874 && out_attr[Tag_ABI_HardFP_use].i == 0)
13875 ;
13876 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13877 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13878 else if (in_attr[Tag_ABI_HardFP_use].i
13879 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13880 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13881
13882 /* Now we can handle Tag_FP_arch. */
13883
bca38921
MGD		 13884 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13885 pick the biggest. */
13886 if (in_attr[i].i >= VFP_VERSION_COUNT
13887 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13888 {
13889 out_attr[i] = in_attr[i];
13890 break;
13891 }
13892 /* The output uses the superset of input features
13893 (ISA version) and registers. */
13894 ver = vfp_versions[in_attr[i].i].ver;
13895 if (ver < vfp_versions[out_attr[i].i].ver)
13896 ver = vfp_versions[out_attr[i].i].ver;
13897 regs = vfp_versions[in_attr[i].i].regs;
13898 if (regs < vfp_versions[out_attr[i].i].regs)
13899 regs = vfp_versions[out_attr[i].i].regs;
13900 /* This assumes all possible supersets are also a valid
99059e56 13901 options. */
bca38921 13902 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13903 {
13904 if (regs == vfp_versions[newval].regs
13905 && ver == vfp_versions[newval].ver)
13906 break;
13907 }
13908 out_attr[i].i = newval;
13909 }
b1cc4aeb 13910 break;
ee065d83
PB		 13911 case Tag_PCS_config:
13912 if (out_attr[i].i == 0)
13913 out_attr[i].i = in_attr[i].i;
b6009aca 13914 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13915 {
13916 /* It's sometimes ok to mix different configs, so this is only
99059e56 13917 a warning. */
ee065d83
PB		 13918 _bfd_error_handler
13919 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13920 }
13921 break;
13922 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13923 if (in_attr[i].i != out_attr[i].i
13924 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13925 && in_attr[i].i != AEABI_R9_unused)
13926 {
13927 _bfd_error_handler
3895f852 13928 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13929 result = FALSE;
ee065d83
PB		 13930 }
13931 if (out_attr[i].i == AEABI_R9_unused)
13932 out_attr[i].i = in_attr[i].i;
13933 break;
13934 case Tag_ABI_PCS_RW_data:
13935 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13936 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13937 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13938 {
13939 _bfd_error_handler
3895f852 13940 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13941 ibfd);
91e22acd 13942 result = FALSE;
ee065d83
PB		 13943 }
13944 /* Use the smallest value specified. */
13945 if (in_attr[i].i < out_attr[i].i)
13946 out_attr[i].i = in_attr[i].i;
13947 break;
ee065d83 13948 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13949 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13950 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13951 {
13952 _bfd_error_handler
a9dc9481
JM		 13953 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13954 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13955 }
a9dc9481 13956 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13957 out_attr[i].i = in_attr[i].i;
13958 break;
ee065d83
PB		 13959 case Tag_ABI_enum_size:
13960 if (in_attr[i].i != AEABI_enum_unused)
13961 {
13962 if (out_attr[i].i == AEABI_enum_unused
13963 || out_attr[i].i == AEABI_enum_forced_wide)
13964 {
13965 /* The existing object is compatible with anything.
13966 Use whatever requirements the new object has. */
13967 out_attr[i].i = in_attr[i].i;
13968 }
13969 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13970 && out_attr[i].i != in_attr[i].i
0ffa91dd 13971 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13972 {
91e22acd 13973 static const char *aeabi_enum_names[] =
bf21ed78 13974 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13975 const char *in_name =
13976 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13977 ? aeabi_enum_names[in_attr[i].i]
13978 : "<unknown>";
13979 const char *out_name =
13980 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13981 ? aeabi_enum_names[out_attr[i].i]
13982 : "<unknown>";
ee065d83 13983 _bfd_error_handler
bf21ed78 13984 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13985 ibfd, in_name, out_name);
ee065d83
PB		 13986 }
13987 }
13988 break;
13989 case Tag_ABI_VFP_args:
13990 /* Aready done. */
13991 break;
13992 case Tag_ABI_WMMX_args:
13993 if (in_attr[i].i != out_attr[i].i)
13994 {
13995 _bfd_error_handler
3895f852 13996 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13997 ibfd, obfd);
91e22acd 13998 result = FALSE;
ee065d83
PB		 13999 }
14000 break;
7b86a9fa
AS		 14001 case Tag_compatibility:
14002 /* Merged in target-independent code. */
14003 break;
91e22acd 14004 case Tag_ABI_HardFP_use:
4547cb56 14005 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14006 break;
14007 case Tag_ABI_FP_16bit_format:
14008 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14009 {
14010 if (in_attr[i].i != out_attr[i].i)
14011 {
14012 _bfd_error_handler
3895f852 14013 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 14014 ibfd, obfd);
14015 result = FALSE;
14016 }
14017 }
14018 if (in_attr[i].i != 0)
14019 out_attr[i].i = in_attr[i].i;
14020 break;
7b86a9fa 14021
cd21e546 14022 case Tag_DIV_use:
ac56ee8f
MGD		 14023 /* A value of zero on input means that the divide instruction may
14024 be used if available in the base architecture as specified via
14025 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14026 the user did not want divide instructions. A value of 2
14027 explicitly means that divide instructions were allowed in ARM
14028 and Thumb state. */
14029 if (in_attr[i].i == out_attr[i].i)
14030 /* Do nothing. */ ;
14031 else if (elf32_arm_attributes_forbid_div (in_attr)
14032 && !elf32_arm_attributes_accept_div (out_attr))
14033 out_attr[i].i = 1;
14034 else if (elf32_arm_attributes_forbid_div (out_attr)
14035 && elf32_arm_attributes_accept_div (in_attr))
14036 out_attr[i].i = in_attr[i].i;
14037 else if (in_attr[i].i == 2)
14038 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14039 break;
14040
14041 case Tag_MPextension_use_legacy:
14042 /* We don't output objects with Tag_MPextension_use_legacy - we
14043 move the value to Tag_MPextension_use. */
14044 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14045 {
14046 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14047 {
14048 _bfd_error_handler
de194d85 14049 (_("%B has both the current and legacy "
b38cadfb 14050 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14051 ibfd);
14052 result = FALSE;
14053 }
14054 }
14055
14056 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14057 out_attr[Tag_MPextension_use] = in_attr[i];
14058
14059 break;
14060
91e22acd 14061 case Tag_nodefaults:
2d0bb761
AS		 14062 /* This tag is set if it exists, but the value is unused (and is
14063 typically zero). We don't actually need to do anything here -
14064 the merge happens automatically when the type flags are merged
14065 below. */
91e22acd
AS		 14066 break;
14067 case Tag_also_compatible_with:
14068 /* Already done in Tag_CPU_arch. */
14069 break;
14070 case Tag_conformance:
14071 /* Keep the attribute if it matches. Throw it away otherwise.
14072 No attribute means no claim to conform. */
14073 if (!in_attr[i].s || !out_attr[i].s
14074 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14075 out_attr[i].s = NULL;
14076 break;
3cfad14c 14077
91e22acd 14078 default:
e8b36cd1
JM		 14079 result
14080 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14081 }
14082
14083 /* If out_attr was copied from in_attr then it won't have a type yet. */
14084 if (in_attr[i].type && !out_attr[i].type)
14085 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14086 }
14087
104d59d1 14088 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14089 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14090 return FALSE;
ee065d83 14091
104d59d1 14092 /* Check for any attributes not known on ARM. */
e8b36cd1 14093 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14094
91e22acd 14095 return result;
252b5132
RH		 14096}
14097
3a4a14e9
PB		 14098
14099/* Return TRUE if the two EABI versions are incompatible. */
14100
14101static bfd_boolean
14102elf32_arm_versions_compatible (unsigned iver, unsigned over)
14103{
14104 /* v4 and v5 are the same spec before and after it was released,
14105 so allow mixing them. */
14106 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14107 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14108 return TRUE;
14109
14110 return (iver == over);
14111}
14112
252b5132
RH		 14113/* Merge backend specific data from an object file to the output
14114 object file when linking. */
9b485d32 14115
b34976b6 14116static bfd_boolean
50e03d47 14117elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14118
9b485d32
NC		 14119/* Display the flags field. */
14120
b34976b6 14121static bfd_boolean
57e8b36a 14122elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14123{
fc830a83
NC		 14124 FILE * file = (FILE *) ptr;
14125 unsigned long flags;
252b5132
RH		 14126
14127 BFD_ASSERT (abfd != NULL && ptr != NULL);
14128
14129 /* Print normal ELF private data. */
14130 _bfd_elf_print_private_bfd_data (abfd, ptr);
14131
fc830a83 14132 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14133 /* Ignore init flag - it may not be set, despite the flags field
14134 containing valid data. */
252b5132 14135
9b485d32 14136 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14137
fc830a83
NC		 14138 switch (EF_ARM_EABI_VERSION (flags))
14139 {
14140 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14141 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14142 official ARM ELF extended ABI. Hence they are only decoded if
14143 the EABI version is not set. */
fd2ec330 14144 if (flags & EF_ARM_INTERWORK)
9b485d32 14145 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14146
fd2ec330 14147 if (flags & EF_ARM_APCS_26)
6c571f00 14148 fprintf (file, " [APCS-26]");
fc830a83 14149 else
6c571f00 14150 fprintf (file, " [APCS-32]");
9a5aca8c 14151
96a846ea
RE		 14152 if (flags & EF_ARM_VFP_FLOAT)
14153 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14154 else if (flags & EF_ARM_MAVERICK_FLOAT)
14155 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14156 else
14157 fprintf (file, _(" [FPA float format]"));
14158
fd2ec330 14159 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14160 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14161
fd2ec330 14162 if (flags & EF_ARM_PIC)
9b485d32 14163 fprintf (file, _(" [position independent]"));
fc830a83 14164
fd2ec330 14165 if (flags & EF_ARM_NEW_ABI)
9b485d32 14166 fprintf (file, _(" [new ABI]"));
9a5aca8c 14167
fd2ec330 14168 if (flags & EF_ARM_OLD_ABI)
9b485d32 14169 fprintf (file, _(" [old ABI]"));
9a5aca8c 14170
fd2ec330 14171 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14172 fprintf (file, _(" [software FP]"));
9a5aca8c 14173
96a846ea
RE		 14174 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14175 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14176 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14177 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14178 break;
9a5aca8c 14179
fc830a83 14180 case EF_ARM_EABI_VER1:
9b485d32 14181 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14182
fc830a83 14183 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14184 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14185 else
9b485d32 14186 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14187
fc830a83
NC		 14188 flags &= ~ EF_ARM_SYMSARESORTED;
14189 break;
9a5aca8c 14190
fd2ec330
PB		 14191 case EF_ARM_EABI_VER2:
14192 fprintf (file, _(" [Version2 EABI]"));
14193
14194 if (flags & EF_ARM_SYMSARESORTED)
14195 fprintf (file, _(" [sorted symbol table]"));
14196 else
14197 fprintf (file, _(" [unsorted symbol table]"));
14198
14199 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14200 fprintf (file, _(" [dynamic symbols use segment index]"));
14201
14202 if (flags & EF_ARM_MAPSYMSFIRST)
14203 fprintf (file, _(" [mapping symbols precede others]"));
14204
99e4ae17 14205 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14206 | EF_ARM_MAPSYMSFIRST);
14207 break;
14208
d507cf36
PB		 14209 case EF_ARM_EABI_VER3:
14210 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14211 break;
14212
14213 case EF_ARM_EABI_VER4:
14214 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14215 goto eabi;
d507cf36 14216
3a4a14e9
PB		 14217 case EF_ARM_EABI_VER5:
14218 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14219
14220 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14221 fprintf (file, _(" [soft-float ABI]"));
14222
14223 if (flags & EF_ARM_ABI_FLOAT_HARD)
14224 fprintf (file, _(" [hard-float ABI]"));
14225
14226 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14227
3a4a14e9 14228 eabi:
d507cf36
PB		 14229 if (flags & EF_ARM_BE8)
14230 fprintf (file, _(" [BE8]"));
14231
14232 if (flags & EF_ARM_LE8)
14233 fprintf (file, _(" [LE8]"));
14234
14235 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14236 break;
14237
fc830a83 14238 default:
9b485d32 14239 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14240 break;
14241 }
252b5132 14242
fc830a83 14243 flags &= ~ EF_ARM_EABIMASK;
252b5132 14244
fc830a83 14245 if (flags & EF_ARM_RELEXEC)
9b485d32 14246 fprintf (file, _(" [relocatable executable]"));
252b5132 14247
a5721edd 14248 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14249
14250 if (flags)
9b485d32 14251 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14252
252b5132
RH		 14253 fputc ('\n', file);
14254
b34976b6 14255 return TRUE;
252b5132
RH		 14256}
14257
14258static int
57e8b36a 14259elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14260{
2f0ca46a
NC		 14261 switch (ELF_ST_TYPE (elf_sym->st_info))
14262 {
14263 case STT_ARM_TFUNC:
14264 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14265
2f0ca46a
NC		 14266 case STT_ARM_16BIT:
14267 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14268 This allows us to distinguish between data used by Thumb instructions
14269 and non-data (which is probably code) inside Thumb regions of an
14270 executable. */
1a0eb693 14271 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14272 return ELF_ST_TYPE (elf_sym->st_info);
14273 break;
9a5aca8c 14274
ce855c42
NC		 14275 default:
14276 break;
2f0ca46a
NC		 14277 }
14278
14279 return type;
252b5132 14280}
f21f3fe0 14281
252b5132 14282static asection *
07adf181
AM		 14283elf32_arm_gc_mark_hook (asection *sec,
14284 struct bfd_link_info *info,
14285 Elf_Internal_Rela *rel,
14286 struct elf_link_hash_entry *h,
14287 Elf_Internal_Sym *sym)
252b5132
RH		 14288{
14289 if (h != NULL)
07adf181 14290 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14291 {
14292 case R_ARM_GNU_VTINHERIT:
14293 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14294 return NULL;
14295 }
9ad5cbcf 14296
07adf181 14297 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14298}
14299
780a67af
NC		 14300/* Look through the relocs for a section during the first phase. */
14301
b34976b6 14302static bfd_boolean
57e8b36a
NC		 14303elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14304 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14305{
b34976b6
AM		 14306 Elf_Internal_Shdr *symtab_hdr;
14307 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14308 const Elf_Internal_Rela *rel;
14309 const Elf_Internal_Rela *rel_end;
14310 bfd *dynobj;
5e681ec4 14311 asection *sreloc;
5e681ec4 14312 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14313 bfd_boolean call_reloc_p;
14314 bfd_boolean may_become_dynamic_p;
14315 bfd_boolean may_need_local_target_p;
ce98a316 14316 unsigned long nsyms;
9a5aca8c 14317
0e1862bb 14318 if (bfd_link_relocatable (info))
b34976b6 14319 return TRUE;
9a5aca8c 14320
0ffa91dd
NC		 14321 BFD_ASSERT (is_arm_elf (abfd));
14322
5e681ec4 14323 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14324 if (htab == NULL)
14325 return FALSE;
14326
5e681ec4 14327 sreloc = NULL;
9a5aca8c 14328
67687978
PB		 14329 /* Create dynamic sections for relocatable executables so that we can
14330 copy relocations. */
14331 if (htab->root.is_relocatable_executable
14332 && ! htab->root.dynamic_sections_created)
14333 {
14334 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14335 return FALSE;
14336 }
14337
cbc704f3
RS		 14338 if (htab->root.dynobj == NULL)
14339 htab->root.dynobj = abfd;
34e77a92
RS		 14340 if (!create_ifunc_sections (info))
14341 return FALSE;
cbc704f3
RS		 14342
14343 dynobj = htab->root.dynobj;
14344
0ffa91dd 14345 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14346 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14347 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14348
252b5132
RH		 14349 rel_end = relocs + sec->reloc_count;
14350 for (rel = relocs; rel < rel_end; rel++)
14351 {
34e77a92 14352 Elf_Internal_Sym *isym;
252b5132 14353 struct elf_link_hash_entry *h;
b7693d02 14354 struct elf32_arm_link_hash_entry *eh;
d42c267e 14355 unsigned int r_symndx;
eb043451 14356 int r_type;
9a5aca8c 14357
252b5132 14358 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14359 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14360 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14361
ce98a316
NC		 14362 if (r_symndx >= nsyms
14363 /* PR 9934: It is possible to have relocations that do not
14364 refer to symbols, thus it is also possible to have an
14365 object file containing relocations but no symbol table. */
cf35638d 14366 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14367 {
4eca0228
AM		 14368 _bfd_error_handler (_("%B: bad symbol index: %d"), abfd,
14369 r_symndx);
ba93b8ac
DJ		 14370 return FALSE;
14371 }
14372
34e77a92
RS		 14373 h = NULL;
14374 isym = NULL;
14375 if (nsyms > 0)
973a3492 14376 {
34e77a92
RS		 14377 if (r_symndx < symtab_hdr->sh_info)
14378 {
14379 /* A local symbol. */
14380 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14381 abfd, r_symndx);
14382 if (isym == NULL)
14383 return FALSE;
14384 }
14385 else
14386 {
14387 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14388 while (h->root.type == bfd_link_hash_indirect
14389 || h->root.type == bfd_link_hash_warning)
14390 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14391 }
973a3492 14392 }
9a5aca8c 14393
b7693d02
DJ		 14394 eh = (struct elf32_arm_link_hash_entry *) h;
14395
f6e32f6d
RS		 14396 call_reloc_p = FALSE;
14397 may_become_dynamic_p = FALSE;
14398 may_need_local_target_p = FALSE;
14399
0855e32b
NS		 14400 /* Could be done earlier, if h were already available. */
14401 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14402 switch (r_type)
99059e56 14403 {
5e681ec4 14404 case R_ARM_GOT32:
eb043451 14405 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14406 case R_ARM_TLS_GD32:
14407 case R_ARM_TLS_IE32:
0855e32b
NS		 14408 case R_ARM_TLS_GOTDESC:
14409 case R_ARM_TLS_DESCSEQ:
14410 case R_ARM_THM_TLS_DESCSEQ:
14411 case R_ARM_TLS_CALL:
14412 case R_ARM_THM_TLS_CALL:
5e681ec4 14413 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14414 {
14415 int tls_type, old_tls_type;
5e681ec4 14416
ba93b8ac
DJ		 14417 switch (r_type)
14418 {
14419 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14420
ba93b8ac 14421 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14422
0855e32b
NS		 14423 case R_ARM_TLS_GOTDESC:
14424 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14425 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14426 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14427
ba93b8ac
DJ		 14428 default: tls_type = GOT_NORMAL; break;
14429 }
252b5132 14430
0e1862bb 14431 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14432 info->flags |= DF_STATIC_TLS;
14433
ba93b8ac
DJ		 14434 if (h != NULL)
14435 {
14436 h->got.refcount++;
14437 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14438 }
14439 else
14440 {
ba93b8ac 14441 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14442 if (!elf32_arm_allocate_local_sym_info (abfd))
14443 return FALSE;
14444 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14445 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14446 }
14447
0855e32b 14448 /* If a variable is accessed with both tls methods, two
99059e56 14449 slots may be created. */
0855e32b
NS		 14450 if (GOT_TLS_GD_ANY_P (old_tls_type)
14451 && GOT_TLS_GD_ANY_P (tls_type))
14452 tls_type |= old_tls_type;
14453
14454 /* We will already have issued an error message if there
14455 is a TLS/non-TLS mismatch, based on the symbol
14456 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14457 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14458 && tls_type != GOT_NORMAL)
14459 tls_type |= old_tls_type;
14460
0855e32b 14461 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14462 method, we're able to relax. Turn off the GDESC flag,
14463 without messing up with any other kind of tls types
6a631e86 14464 that may be involved. */
0855e32b
NS		 14465 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14466 tls_type &= ~GOT_TLS_GDESC;
14467
ba93b8ac
DJ		 14468 if (old_tls_type != tls_type)
14469 {
14470 if (h != NULL)
14471 elf32_arm_hash_entry (h)->tls_type = tls_type;
14472 else
14473 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14474 }
14475 }
8029a119 14476 /* Fall through. */
ba93b8ac
DJ		 14477
14478 case R_ARM_TLS_LDM32:
14479 if (r_type == R_ARM_TLS_LDM32)
14480 htab->tls_ldm_got.refcount++;
8029a119 14481 /* Fall through. */
252b5132 14482
c19d1205 14483 case R_ARM_GOTOFF32:
5e681ec4 14484 case R_ARM_GOTPC:
cbc704f3
RS		 14485 if (htab->root.sgot == NULL
14486 && !create_got_section (htab->root.dynobj, info))
14487 return FALSE;
252b5132
RH		 14488 break;
14489
252b5132 14490 case R_ARM_PC24:
7359ea65 14491 case R_ARM_PLT32:
5b5bb741
PB		 14492 case R_ARM_CALL:
14493 case R_ARM_JUMP24:
eb043451 14494 case R_ARM_PREL31:
c19d1205 14495 case R_ARM_THM_CALL:
bd97cb95
DJ		 14496 case R_ARM_THM_JUMP24:
14497 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14498 call_reloc_p = TRUE;
14499 may_need_local_target_p = TRUE;
14500 break;
14501
14502 case R_ARM_ABS12:
14503 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14504 ldr __GOTT_INDEX__ offsets. */
14505 if (!htab->vxworks_p)
14506 {
14507 may_need_local_target_p = TRUE;
14508 break;
14509 }
aebf9be7 14510 else goto jump_over;
9eaff861 14511
f6e32f6d 14512 /* Fall through. */
39623e12 14513
96c23d59
JM		 14514 case R_ARM_MOVW_ABS_NC:
14515 case R_ARM_MOVT_ABS:
14516 case R_ARM_THM_MOVW_ABS_NC:
14517 case R_ARM_THM_MOVT_ABS:
0e1862bb 14518 if (bfd_link_pic (info))
96c23d59 14519 {
4eca0228 14520 _bfd_error_handler
96c23d59
JM		 14521 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14522 abfd, elf32_arm_howto_table_1[r_type].name,
14523 (h) ? h->root.root.string : "a local symbol");
14524 bfd_set_error (bfd_error_bad_value);
14525 return FALSE;
14526 }
14527
14528 /* Fall through. */
39623e12
PB		 14529 case R_ARM_ABS32:
14530 case R_ARM_ABS32_NOI:
aebf9be7 14531 jump_over:
0e1862bb 14532 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14533 {
14534 h->pointer_equality_needed = 1;
14535 }
14536 /* Fall through. */
39623e12
PB		 14537 case R_ARM_REL32:
14538 case R_ARM_REL32_NOI:
b6895b4f
PB		 14539 case R_ARM_MOVW_PREL_NC:
14540 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14541 case R_ARM_THM_MOVW_PREL_NC:
14542 case R_ARM_THM_MOVT_PREL:
39623e12 14543
b7693d02 14544 /* Should the interworking branches be listed here? */
0e1862bb 14545 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14546 && (sec->flags & SEC_ALLOC) != 0)
14547 {
14548 if (h == NULL
469a3493 14549 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14550 {
14551 /* In shared libraries and relocatable executables,
14552 we treat local relative references as calls;
14553 see the related SYMBOL_CALLS_LOCAL code in
14554 allocate_dynrelocs. */
14555 call_reloc_p = TRUE;
14556 may_need_local_target_p = TRUE;
14557 }
14558 else
14559 /* We are creating a shared library or relocatable
14560 executable, and this is a reloc against a global symbol,
14561 or a non-PC-relative reloc against a local symbol.
14562 We may need to copy the reloc into the output. */
14563 may_become_dynamic_p = TRUE;
14564 }
f6e32f6d
RS		 14565 else
14566 may_need_local_target_p = TRUE;
252b5132
RH		 14567 break;
14568
99059e56
RM		 14569 /* This relocation describes the C++ object vtable hierarchy.
14570 Reconstruct it for later use during GC. */
14571 case R_ARM_GNU_VTINHERIT:
14572 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14573 return FALSE;
14574 break;
14575
14576 /* This relocation describes which C++ vtable entries are actually
14577 used. Record for later use during GC. */
14578 case R_ARM_GNU_VTENTRY:
14579 BFD_ASSERT (h != NULL);
14580 if (h != NULL
14581 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14582 return FALSE;
14583 break;
14584 }
f6e32f6d
RS		 14585
14586 if (h != NULL)
14587 {
14588 if (call_reloc_p)
14589 /* We may need a .plt entry if the function this reloc
14590 refers to is in a different object, regardless of the
14591 symbol's type. We can't tell for sure yet, because
14592 something later might force the symbol local. */
14593 h->needs_plt = 1;
14594 else if (may_need_local_target_p)
14595 /* If this reloc is in a read-only section, we might
14596 need a copy reloc. We can't check reliably at this
14597 stage whether the section is read-only, as input
14598 sections have not yet been mapped to output sections.
14599 Tentatively set the flag for now, and correct in
14600 adjust_dynamic_symbol. */
14601 h->non_got_ref = 1;
14602 }
14603
34e77a92
RS		 14604 if (may_need_local_target_p
14605 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14606 {
34e77a92
RS		 14607 union gotplt_union *root_plt;
14608 struct arm_plt_info *arm_plt;
14609 struct arm_local_iplt_info *local_iplt;
14610
14611 if (h != NULL)
14612 {
14613 root_plt = &h->plt;
14614 arm_plt = &eh->plt;
14615 }
14616 else
14617 {
14618 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14619 if (local_iplt == NULL)
14620 return FALSE;
14621 root_plt = &local_iplt->root;
14622 arm_plt = &local_iplt->arm;
14623 }
14624
f6e32f6d
RS		 14625 /* If the symbol is a function that doesn't bind locally,
14626 this relocation will need a PLT entry. */
a8c887dd
NC		 14627 if (root_plt->refcount != -1)
14628 root_plt->refcount += 1;
34e77a92
RS		 14629
14630 if (!call_reloc_p)
14631 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14632
14633 /* It's too early to use htab->use_blx here, so we have to
14634 record possible blx references separately from
14635 relocs that definitely need a thumb stub. */
14636
14637 if (r_type == R_ARM_THM_CALL)
34e77a92 14638 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14639
14640 if (r_type == R_ARM_THM_JUMP24
14641 || r_type == R_ARM_THM_JUMP19)
34e77a92 14642 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14643 }
14644
14645 if (may_become_dynamic_p)
14646 {
14647 struct elf_dyn_relocs *p, **head;
14648
14649 /* Create a reloc section in dynobj. */
14650 if (sreloc == NULL)
14651 {
14652 sreloc = _bfd_elf_make_dynamic_reloc_section
14653 (sec, dynobj, 2, abfd, ! htab->use_rel);
14654
14655 if (sreloc == NULL)
14656 return FALSE;
14657
14658 /* BPABI objects never have dynamic relocations mapped. */
14659 if (htab->symbian_p)
14660 {
14661 flagword flags;
14662
14663 flags = bfd_get_section_flags (dynobj, sreloc);
14664 flags &= ~(SEC_LOAD | SEC_ALLOC);
14665 bfd_set_section_flags (dynobj, sreloc, flags);
14666 }
14667 }
14668
14669 /* If this is a global symbol, count the number of
14670 relocations we need for this symbol. */
14671 if (h != NULL)
14672 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14673 else
14674 {
34e77a92
RS		 14675 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14676 if (head == NULL)
f6e32f6d 14677 return FALSE;
f6e32f6d
RS		 14678 }
14679
14680 p = *head;
14681 if (p == NULL || p->sec != sec)
14682 {
14683 bfd_size_type amt = sizeof *p;
14684
14685 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14686 if (p == NULL)
14687 return FALSE;
14688 p->next = *head;
14689 *head = p;
14690 p->sec = sec;
14691 p->count = 0;
14692 p->pc_count = 0;
14693 }
14694
469a3493 14695 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14696 p->pc_count += 1;
14697 p->count += 1;
14698 }
252b5132 14699 }
f21f3fe0 14700
b34976b6 14701 return TRUE;
252b5132
RH		 14702}
14703
9eaff861
AO		 14704static void
14705elf32_arm_update_relocs (asection *o,
14706 struct bfd_elf_section_reloc_data *reldata)
14707{
14708 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14709 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14710 const struct elf_backend_data *bed;
14711 _arm_elf_section_data *eado;
14712 struct bfd_link_order *p;
14713 bfd_byte *erela_head, *erela;
14714 Elf_Internal_Rela *irela_head, *irela;
14715 Elf_Internal_Shdr *rel_hdr;
14716 bfd *abfd;
14717 unsigned int count;
14718
14719 eado = get_arm_elf_section_data (o);
14720
14721 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14722 return;
14723
14724 abfd = o->owner;
14725 bed = get_elf_backend_data (abfd);
14726 rel_hdr = reldata->hdr;
14727
14728 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14729 {
14730 swap_in = bed->s->swap_reloc_in;
14731 swap_out = bed->s->swap_reloc_out;
14732 }
14733 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14734 {
14735 swap_in = bed->s->swap_reloca_in;
14736 swap_out = bed->s->swap_reloca_out;
14737 }
14738 else
14739 abort ();
14740
14741 erela_head = rel_hdr->contents;
14742 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14743 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14744
14745 erela = erela_head;
14746 irela = irela_head;
14747 count = 0;
14748
14749 for (p = o->map_head.link_order; p; p = p->next)
14750 {
14751 if (p->type == bfd_section_reloc_link_order
14752 || p->type == bfd_symbol_reloc_link_order)
14753 {
14754 (*swap_in) (abfd, erela, irela);
14755 erela += rel_hdr->sh_entsize;
14756 irela++;
14757 count++;
14758 }
14759 else if (p->type == bfd_indirect_link_order)
14760 {
14761 struct bfd_elf_section_reloc_data *input_reldata;
14762 arm_unwind_table_edit *edit_list, *edit_tail;
14763 _arm_elf_section_data *eadi;
14764 bfd_size_type j;
14765 bfd_vma offset;
14766 asection *i;
14767
14768 i = p->u.indirect.section;
14769
14770 eadi = get_arm_elf_section_data (i);
14771 edit_list = eadi->u.exidx.unwind_edit_list;
14772 edit_tail = eadi->u.exidx.unwind_edit_tail;
14773 offset = o->vma + i->output_offset;
14774
14775 if (eadi->elf.rel.hdr &&
14776 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14777 input_reldata = &eadi->elf.rel;
14778 else if (eadi->elf.rela.hdr &&
14779 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14780 input_reldata = &eadi->elf.rela;
14781 else
14782 abort ();
14783
14784 if (edit_list)
14785 {
14786 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14787 {
14788 arm_unwind_table_edit *edit_node, *edit_next;
14789 bfd_vma bias;
c48182bf 14790 bfd_vma reloc_index;
9eaff861
AO		 14791
14792 (*swap_in) (abfd, erela, irela);
c48182bf 14793 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 14794
14795 bias = 0;
14796 edit_node = edit_list;
14797 for (edit_next = edit_list;
c48182bf 14798 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 14799 edit_next = edit_node->next)
14800 {
14801 bias++;
14802 edit_node = edit_next;
14803 }
14804
14805 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 14806 || edit_node->index != reloc_index)
9eaff861
AO		 14807 {
14808 irela->r_offset -= bias * 8;
14809 irela++;
14810 count++;
14811 }
14812
14813 erela += rel_hdr->sh_entsize;
14814 }
14815
14816 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
14817 {
14818 /* New relocation entity. */
14819 asection *text_sec = edit_tail->linked_section;
14820 asection *text_out = text_sec->output_section;
14821 bfd_vma exidx_offset = offset + i->size - 8;
14822
14823 irela->r_addend = 0;
14824 irela->r_offset = exidx_offset;
14825 irela->r_info = ELF32_R_INFO
14826 (text_out->target_index, R_ARM_PREL31);
14827 irela++;
14828 count++;
14829 }
14830 }
14831 else
14832 {
14833 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14834 {
14835 (*swap_in) (abfd, erela, irela);
14836 erela += rel_hdr->sh_entsize;
14837 irela++;
14838 }
14839
14840 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
14841 }
14842 }
14843 }
14844
14845 reldata->count = count;
14846 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
14847
14848 erela = erela_head;
14849 irela = irela_head;
14850 while (count > 0)
14851 {
14852 (*swap_out) (abfd, irela, erela);
14853 erela += rel_hdr->sh_entsize;
14854 irela++;
14855 count--;
14856 }
14857
14858 free (irela_head);
14859
14860 /* Hashes are no longer valid. */
14861 free (reldata->hashes);
14862 reldata->hashes = NULL;
14863}
14864
6a5bb875 14865/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 14866 required if the corresponding code section is marked. Similarly, ARMv8-M
14867 secure entry functions can only be referenced by SG veneers which are
14868 created after the GC process. They need to be marked in case they reside in
14869 their own section (as would be the case if code was compiled with
14870 -ffunction-sections). */
6a5bb875
PB		 14871
14872static bfd_boolean
906e58ca
NC		 14873elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
14874 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 14875{
14876 bfd *sub;
14877 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 14878 asection *cmse_sec;
14879 obj_attribute *out_attr;
14880 Elf_Internal_Shdr *symtab_hdr;
14881 unsigned i, sym_count, ext_start;
14882 const struct elf_backend_data *bed;
14883 struct elf_link_hash_entry **sym_hashes;
14884 struct elf32_arm_link_hash_entry *cmse_hash;
14885 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 14886
7f6ab9f8
AM		 14887 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
14888
4ba2ef8f
TP		 14889 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
14890 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
14891 && out_attr[Tag_CPU_arch_profile].i == 'M';
14892
6a5bb875
PB		 14893 /* Marking EH data may cause additional code sections to be marked,
14894 requiring multiple passes. */
14895 again = TRUE;
14896 while (again)
14897 {
14898 again = FALSE;
c72f2fb2 14899 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 14900 {
14901 asection *o;
14902
0ffa91dd 14903 if (! is_arm_elf (sub))
6a5bb875
PB		 14904 continue;
14905
14906 elf_shdrp = elf_elfsections (sub);
14907 for (o = sub->sections; o != NULL; o = o->next)
14908 {
14909 Elf_Internal_Shdr *hdr;
0ffa91dd 14910
6a5bb875 14911 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 14912 if (hdr->sh_type == SHT_ARM_EXIDX
14913 && hdr->sh_link
14914 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 14915 && !o->gc_mark
14916 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
14917 {
14918 again = TRUE;
14919 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
14920 return FALSE;
14921 }
14922 }
4ba2ef8f
TP		 14923
14924 /* Mark section holding ARMv8-M secure entry functions. We mark all
14925 of them so no need for a second browsing. */
14926 if (is_v8m && first_bfd_browse)
14927 {
14928 sym_hashes = elf_sym_hashes (sub);
14929 bed = get_elf_backend_data (sub);
14930 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
14931 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
14932 ext_start = symtab_hdr->sh_info;
14933
14934 /* Scan symbols. */
14935 for (i = ext_start; i < sym_count; i++)
14936 {
14937 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
14938
14939 /* Assume it is a special symbol. If not, cmse_scan will
14940 warn about it and user can do something about it. */
14941 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
14942 {
14943 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 14944 if (!cmse_sec->gc_mark
14945 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 14946 return FALSE;
14947 }
14948 }
14949 }
6a5bb875 14950 }
4ba2ef8f 14951 first_bfd_browse = FALSE;
6a5bb875
PB		 14952 }
14953
14954 return TRUE;
14955}
14956
3c9458e9
NC		 14957/* Treat mapping symbols as special target symbols. */
14958
14959static bfd_boolean
14960elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
14961{
b0796911
PB		 14962 return bfd_is_arm_special_symbol_name (sym->name,
14963 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 14964}
14965
0367ecfb
NC		 14966/* This is a copy of elf_find_function() from elf.c except that
14967 ARM mapping symbols are ignored when looking for function names
14968 and STT_ARM_TFUNC is considered to a function type. */
252b5132 14969
0367ecfb
NC		 14970static bfd_boolean
14971arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 14972 asymbol ** symbols,
fb167eb2 14973 asection * section,
0367ecfb
NC		 14974 bfd_vma offset,
14975 const char ** filename_ptr,
14976 const char ** functionname_ptr)
14977{
14978 const char * filename = NULL;
14979 asymbol * func = NULL;
14980 bfd_vma low_func = 0;
14981 asymbol ** p;
252b5132
RH		 14982
14983 for (p = symbols; *p != NULL; p++)
14984 {
14985 elf_symbol_type *q;
14986
14987 q = (elf_symbol_type *) *p;
14988
252b5132
RH		 14989 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
14990 {
14991 default:
14992 break;
14993 case STT_FILE:
14994 filename = bfd_asymbol_name (&q->symbol);
14995 break;
252b5132
RH		 14996 case STT_FUNC:
14997 case STT_ARM_TFUNC:
9d2da7ca 14998 case STT_NOTYPE:
b0796911 14999 /* Skip mapping symbols. */
0367ecfb 15000 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15001 && bfd_is_arm_special_symbol_name (q->symbol.name,
15002 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15003 continue;
15004 /* Fall through. */
6b40fcba 15005 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15006 && q->symbol.value >= low_func
15007 && q->symbol.value <= offset)
15008 {
15009 func = (asymbol *) q;
15010 low_func = q->symbol.value;
15011 }
15012 break;
15013 }
15014 }
15015
15016 if (func == NULL)
b34976b6 15017 return FALSE;
252b5132 15018
0367ecfb
NC		 15019 if (filename_ptr)
15020 *filename_ptr = filename;
15021 if (functionname_ptr)
15022 *functionname_ptr = bfd_asymbol_name (func);
15023
15024 return TRUE;
906e58ca 15025}
0367ecfb
NC		 15026
15027
15028/* Find the nearest line to a particular section and offset, for error
15029 reporting. This code is a duplicate of the code in elf.c, except
15030 that it uses arm_elf_find_function. */
15031
15032static bfd_boolean
15033elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 15034 asymbol ** symbols,
fb167eb2 15035 asection * section,
0367ecfb
NC		 15036 bfd_vma offset,
15037 const char ** filename_ptr,
15038 const char ** functionname_ptr,
fb167eb2
AM		 15039 unsigned int * line_ptr,
15040 unsigned int * discriminator_ptr)
0367ecfb
NC		 15041{
15042 bfd_boolean found = FALSE;
15043
fb167eb2 15044 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15045 filename_ptr, functionname_ptr,
fb167eb2
AM		 15046 line_ptr, discriminator_ptr,
15047 dwarf_debug_sections, 0,
0367ecfb
NC		 15048 & elf_tdata (abfd)->dwarf2_find_line_info))
15049 {
15050 if (!*functionname_ptr)
fb167eb2 15051 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15052 *filename_ptr ? NULL : filename_ptr,
15053 functionname_ptr);
f21f3fe0 15054
0367ecfb
NC		 15055 return TRUE;
15056 }
15057
fb167eb2
AM		 15058 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15059 uses DWARF1. */
15060
0367ecfb
NC		 15061 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15062 & found, filename_ptr,
15063 functionname_ptr, line_ptr,
15064 & elf_tdata (abfd)->line_info))
15065 return FALSE;
15066
15067 if (found && (*functionname_ptr || *line_ptr))
15068 return TRUE;
15069
15070 if (symbols == NULL)
15071 return FALSE;
15072
fb167eb2 15073 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15074 filename_ptr, functionname_ptr))
15075 return FALSE;
15076
15077 *line_ptr = 0;
b34976b6 15078 return TRUE;
252b5132
RH		 15079}
15080
4ab527b0
FF		 15081static bfd_boolean
15082elf32_arm_find_inliner_info (bfd * abfd,
15083 const char ** filename_ptr,
15084 const char ** functionname_ptr,
15085 unsigned int * line_ptr)
15086{
15087 bfd_boolean found;
15088 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15089 functionname_ptr, line_ptr,
15090 & elf_tdata (abfd)->dwarf2_find_line_info);
15091 return found;
15092}
15093
252b5132
RH		 15094/* Adjust a symbol defined by a dynamic object and referenced by a
15095 regular object. The current definition is in some section of the
15096 dynamic object, but we're not including those sections. We have to
15097 change the definition to something the rest of the link can
15098 understand. */
15099
b34976b6 15100static bfd_boolean
57e8b36a
NC		 15101elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15102 struct elf_link_hash_entry * h)
252b5132
RH		 15103{
15104 bfd * dynobj;
5474d94f 15105 asection *s, *srel;
b7693d02 15106 struct elf32_arm_link_hash_entry * eh;
67687978 15107 struct elf32_arm_link_hash_table *globals;
252b5132 15108
67687978 15109 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15110 if (globals == NULL)
15111 return FALSE;
15112
252b5132
RH		 15113 dynobj = elf_hash_table (info)->dynobj;
15114
15115 /* Make sure we know what is going on here. */
15116 BFD_ASSERT (dynobj != NULL
f5385ebf 15117 && (h->needs_plt
34e77a92 15118 || h->type == STT_GNU_IFUNC
60d67dc8 15119 || h->is_weakalias
f5385ebf
AM		 15120 || (h->def_dynamic
15121 && h->ref_regular
15122 && !h->def_regular)));
252b5132 15123
b7693d02
DJ		 15124 eh = (struct elf32_arm_link_hash_entry *) h;
15125
252b5132
RH		 15126 /* If this is a function, put it in the procedure linkage table. We
15127 will fill in the contents of the procedure linkage table later,
15128 when we know the address of the .got section. */
34e77a92 15129 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15130 {
34e77a92
RS		 15131 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15132 symbol binds locally. */
5e681ec4 15133 if (h->plt.refcount <= 0
34e77a92
RS		 15134 || (h->type != STT_GNU_IFUNC
15135 && (SYMBOL_CALLS_LOCAL (info, h)
15136 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15137 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15138 {
15139 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15140 file, but the symbol was never referred to by a dynamic
15141 object, or if all references were garbage collected. In
15142 such a case, we don't actually need to build a procedure
15143 linkage table, and we can just do a PC24 reloc instead. */
15144 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15145 eh->plt.thumb_refcount = 0;
15146 eh->plt.maybe_thumb_refcount = 0;
15147 eh->plt.noncall_refcount = 0;
f5385ebf 15148 h->needs_plt = 0;
252b5132
RH		 15149 }
15150
b34976b6 15151 return TRUE;
252b5132 15152 }
5e681ec4 15153 else
b7693d02
DJ		 15154 {
15155 /* It's possible that we incorrectly decided a .plt reloc was
15156 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15157 in check_relocs. We can't decide accurately between function
15158 and non-function syms in check-relocs; Objects loaded later in
15159 the link may change h->type. So fix it now. */
15160 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15161 eh->plt.thumb_refcount = 0;
15162 eh->plt.maybe_thumb_refcount = 0;
15163 eh->plt.noncall_refcount = 0;
b7693d02 15164 }
252b5132
RH		 15165
15166 /* If this is a weak symbol, and there is a real definition, the
15167 processor independent code will have arranged for us to see the
15168 real definition first, and we can just use the same value. */
60d67dc8 15169 if (h->is_weakalias)
252b5132 15170 {
60d67dc8
AM		 15171 struct elf_link_hash_entry *def = weakdef (h);
15172 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
15173 h->root.u.def.section = def->root.u.def.section;
15174 h->root.u.def.value = def->root.u.def.value;
b34976b6 15175 return TRUE;
252b5132
RH		 15176 }
15177
ba93b8ac
DJ		 15178 /* If there are no non-GOT references, we do not need a copy
15179 relocation. */
15180 if (!h->non_got_ref)
15181 return TRUE;
15182
252b5132
RH		 15183 /* This is a reference to a symbol defined by a dynamic object which
15184 is not a function. */
15185
15186 /* If we are creating a shared library, we must presume that the
15187 only references to the symbol are via the global offset table.
15188 For such cases we need not do anything here; the relocations will
67687978
PB		 15189 be handled correctly by relocate_section. Relocatable executables
15190 can reference data in shared objects directly, so we don't need to
15191 do anything here. */
0e1862bb 15192 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15193 return TRUE;
252b5132
RH		 15194
15195 /* We must allocate the symbol in our .dynbss section, which will
15196 become part of the .bss section of the executable. There will be
15197 an entry for this symbol in the .dynsym section. The dynamic
15198 object will contain position independent code, so all references
15199 from the dynamic object to this symbol will go through the global
15200 offset table. The dynamic linker will use the .dynsym entry to
15201 determine the address it must put in the global offset table, so
15202 both the dynamic object and the regular object will refer to the
15203 same memory location for the variable. */
5522f910
NC		 15204 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15205 linker to copy the initial value out of the dynamic object and into
15206 the runtime process image. We need to remember the offset into the
00a97672 15207 .rel(a).bss section we are going to use. */
5474d94f
AM		 15208 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
15209 {
15210 s = globals->root.sdynrelro;
15211 srel = globals->root.sreldynrelro;
15212 }
15213 else
15214 {
15215 s = globals->root.sdynbss;
15216 srel = globals->root.srelbss;
15217 }
5522f910
NC		 15218 if (info->nocopyreloc == 0
15219 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15220 && h->size != 0)
252b5132 15221 {
47beaa6a 15222 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15223 h->needs_copy = 1;
252b5132
RH		 15224 }
15225
6cabe1ea 15226 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15227}
15228
5e681ec4
PB		 15229/* Allocate space in .plt, .got and associated reloc sections for
15230 dynamic relocs. */
15231
15232static bfd_boolean
47beaa6a 15233allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15234{
15235 struct bfd_link_info *info;
15236 struct elf32_arm_link_hash_table *htab;
15237 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15238 struct elf_dyn_relocs *p;
5e681ec4
PB		 15239
15240 if (h->root.type == bfd_link_hash_indirect)
15241 return TRUE;
15242
e6a6bb22
AM		 15243 eh = (struct elf32_arm_link_hash_entry *) h;
15244
5e681ec4
PB		 15245 info = (struct bfd_link_info *) inf;
15246 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15247 if (htab == NULL)
15248 return FALSE;
5e681ec4 15249
34e77a92 15250 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15251 && h->plt.refcount > 0)
15252 {
15253 /* Make sure this symbol is output as a dynamic symbol.
15254 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15255 if (h->dynindx == -1 && !h->forced_local
15256 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15257 {
c152c796 15258 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15259 return FALSE;
15260 }
15261
34e77a92
RS		 15262 /* If the call in the PLT entry binds locally, the associated
15263 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15264 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15265 than the .plt section. */
15266 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15267 {
15268 eh->is_iplt = 1;
15269 if (eh->plt.noncall_refcount == 0
15270 && SYMBOL_REFERENCES_LOCAL (info, h))
15271 /* All non-call references can be resolved directly.
15272 This means that they can (and in some cases, must)
15273 resolve directly to the run-time target, rather than
15274 to the PLT. That in turns means that any .got entry
15275 would be equal to the .igot.plt entry, so there's
15276 no point having both. */
15277 h->got.refcount = 0;
15278 }
15279
0e1862bb 15280 if (bfd_link_pic (info)
34e77a92 15281 || eh->is_iplt
7359ea65 15282 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15283 {
34e77a92 15284 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15285
5e681ec4
PB		 15286 /* If this symbol is not defined in a regular file, and we are
15287 not generating a shared library, then set the symbol to this
15288 location in the .plt. This is required to make function
15289 pointers compare as equal between the normal executable and
15290 the shared library. */
0e1862bb 15291 if (! bfd_link_pic (info)
f5385ebf 15292 && !h->def_regular)
5e681ec4 15293 {
34e77a92 15294 h->root.u.def.section = htab->root.splt;
5e681ec4 15295 h->root.u.def.value = h->plt.offset;
5e681ec4 15296
67d74e43
DJ		 15297 /* Make sure the function is not marked as Thumb, in case
15298 it is the target of an ABS32 relocation, which will
15299 point to the PLT entry. */
39d911fc 15300 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15301 }
022f8312 15302
00a97672
RS		 15303 /* VxWorks executables have a second set of relocations for
15304 each PLT entry. They go in a separate relocation section,
15305 which is processed by the kernel loader. */
0e1862bb 15306 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15307 {
15308 /* There is a relocation for the initial PLT entry:
15309 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15310 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15311 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15312
15313 /* There are two extra relocations for each subsequent
15314 PLT entry: an R_ARM_32 relocation for the GOT entry,
15315 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15316 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15317 }
5e681ec4
PB		 15318 }
15319 else
15320 {
15321 h->plt.offset = (bfd_vma) -1;
f5385ebf 15322 h->needs_plt = 0;
5e681ec4
PB		 15323 }
15324 }
15325 else
15326 {
15327 h->plt.offset = (bfd_vma) -1;
f5385ebf 15328 h->needs_plt = 0;
5e681ec4
PB		 15329 }
15330
0855e32b
NS		 15331 eh = (struct elf32_arm_link_hash_entry *) h;
15332 eh->tlsdesc_got = (bfd_vma) -1;
15333
5e681ec4
PB		 15334 if (h->got.refcount > 0)
15335 {
15336 asection *s;
15337 bfd_boolean dyn;
ba93b8ac
DJ		 15338 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15339 int indx;
5e681ec4
PB		 15340
15341 /* Make sure this symbol is output as a dynamic symbol.
15342 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15343 if (h->dynindx == -1 && !h->forced_local
15344 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15345 {
c152c796 15346 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15347 return FALSE;
15348 }
15349
e5a52504
MM		 15350 if (!htab->symbian_p)
15351 {
362d30a1 15352 s = htab->root.sgot;
e5a52504 15353 h->got.offset = s->size;
ba93b8ac
DJ		 15354
15355 if (tls_type == GOT_UNKNOWN)
15356 abort ();
15357
15358 if (tls_type == GOT_NORMAL)
15359 /* Non-TLS symbols need one GOT slot. */
15360 s->size += 4;
15361 else
15362 {
99059e56
RM		 15363 if (tls_type & GOT_TLS_GDESC)
15364 {
0855e32b 15365 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15366 eh->tlsdesc_got
0855e32b
NS		 15367 = (htab->root.sgotplt->size
15368 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15369 htab->root.sgotplt->size += 8;
15370 h->got.offset = (bfd_vma) -2;
34e77a92 15371 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15372 reloc in the middle of .got.plt. */
99059e56
RM		 15373 htab->num_tls_desc++;
15374 }
0855e32b 15375
ba93b8ac 15376 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15377 {
15378 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15379 the symbol is both GD and GDESC, got.offset may
15380 have been overwritten. */
15381 h->got.offset = s->size;
15382 s->size += 8;
15383 }
15384
ba93b8ac
DJ		 15385 if (tls_type & GOT_TLS_IE)
15386 /* R_ARM_TLS_IE32 needs one GOT slot. */
15387 s->size += 4;
15388 }
15389
e5a52504 15390 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15391
15392 indx = 0;
0e1862bb
L		 15393 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15394 bfd_link_pic (info),
15395 h)
15396 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15397 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15398 indx = h->dynindx;
15399
15400 if (tls_type != GOT_NORMAL
0e1862bb 15401 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15402 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15403 || h->root.type != bfd_link_hash_undefweak))
15404 {
15405 if (tls_type & GOT_TLS_IE)
47beaa6a 15406 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15407
15408 if (tls_type & GOT_TLS_GD)
47beaa6a 15409 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15410
b38cadfb 15411 if (tls_type & GOT_TLS_GDESC)
0855e32b 15412 {
47beaa6a 15413 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15414 /* GDESC needs a trampoline to jump to. */
15415 htab->tls_trampoline = -1;
15416 }
15417
15418 /* Only GD needs it. GDESC just emits one relocation per
15419 2 entries. */
b38cadfb 15420 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15421 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15422 }
6f820c85 15423 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15424 {
15425 if (htab->root.dynamic_sections_created)
15426 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15427 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15428 }
34e77a92
RS		 15429 else if (h->type == STT_GNU_IFUNC
15430 && eh->plt.noncall_refcount == 0)
15431 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15432 they all resolve dynamically instead. Reserve room for the
15433 GOT entry's R_ARM_IRELATIVE relocation. */
15434 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15435 else if (bfd_link_pic (info)
15436 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15437 || h->root.type != bfd_link_hash_undefweak))
b436d854 15438 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15439 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15440 }
5e681ec4
PB		 15441 }
15442 else
15443 h->got.offset = (bfd_vma) -1;
15444
a4fd1a8e
PB		 15445 /* Allocate stubs for exported Thumb functions on v4t. */
15446 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15447 && h->def_regular
39d911fc 15448 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15449 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15450 {
15451 struct elf_link_hash_entry * th;
15452 struct bfd_link_hash_entry * bh;
15453 struct elf_link_hash_entry * myh;
15454 char name[1024];
15455 asection *s;
15456 bh = NULL;
15457 /* Create a new symbol to regist the real location of the function. */
15458 s = h->root.u.def.section;
906e58ca 15459 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15460 _bfd_generic_link_add_one_symbol (info, s->owner,
15461 name, BSF_GLOBAL, s,
15462 h->root.u.def.value,
15463 NULL, TRUE, FALSE, &bh);
15464
15465 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15466 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15467 myh->forced_local = 1;
39d911fc 15468 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15469 eh->export_glue = myh;
15470 th = record_arm_to_thumb_glue (info, h);
15471 /* Point the symbol at the stub. */
15472 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15473 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15474 h->root.u.def.section = th->root.u.def.section;
15475 h->root.u.def.value = th->root.u.def.value & ~1;
15476 }
15477
0bdcacaf 15478 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15479 return TRUE;
15480
15481 /* In the shared -Bsymbolic case, discard space allocated for
15482 dynamic pc-relative relocs against symbols which turn out to be
15483 defined in regular objects. For the normal shared case, discard
15484 space for pc-relative relocs that have become local due to symbol
15485 visibility changes. */
15486
0e1862bb 15487 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15488 {
469a3493
RM		 15489 /* Relocs that use pc_count are PC-relative forms, which will appear
15490 on something like ".long foo - ." or "movw REG, foo - .". We want
15491 calls to protected symbols to resolve directly to the function
15492 rather than going via the plt. If people want function pointer
15493 comparisons to work as expected then they should avoid writing
15494 assembly like ".long foo - .". */
ba93b8ac
DJ		 15495 if (SYMBOL_CALLS_LOCAL (info, h))
15496 {
0bdcacaf 15497 struct elf_dyn_relocs **pp;
ba93b8ac 15498
0bdcacaf 15499 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15500 {
15501 p->count -= p->pc_count;
15502 p->pc_count = 0;
15503 if (p->count == 0)
15504 *pp = p->next;
15505 else
15506 pp = &p->next;
15507 }
15508 }
15509
4dfe6ac6 15510 if (htab->vxworks_p)
3348747a 15511 {
0bdcacaf 15512 struct elf_dyn_relocs **pp;
3348747a 15513
0bdcacaf 15514 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15515 {
0bdcacaf 15516 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15517 *pp = p->next;
15518 else
15519 pp = &p->next;
15520 }
15521 }
15522
ba93b8ac 15523 /* Also discard relocs on undefined weak syms with non-default
99059e56 15524 visibility. */
0bdcacaf 15525 if (eh->dyn_relocs != NULL
5e681ec4 15526 && h->root.type == bfd_link_hash_undefweak)
22d606e9 15527 {
95b03e4a
L		 15528 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15529 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 15530 eh->dyn_relocs = NULL;
22d606e9
AM		 15531
15532 /* Make sure undefined weak symbols are output as a dynamic
15533 symbol in PIEs. */
15534 else if (h->dynindx == -1
15535 && !h->forced_local)
15536 {
15537 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15538 return FALSE;
15539 }
15540 }
15541
67687978
PB		 15542 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15543 && h->root.type == bfd_link_hash_new)
15544 {
15545 /* Output absolute symbols so that we can create relocations
15546 against them. For normal symbols we output a relocation
15547 against the section that contains them. */
15548 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15549 return FALSE;
15550 }
15551
5e681ec4
PB		 15552 }
15553 else
15554 {
15555 /* For the non-shared case, discard space for relocs against
15556 symbols which turn out to need copy relocs or are not
15557 dynamic. */
15558
f5385ebf
AM		 15559 if (!h->non_got_ref
15560 && ((h->def_dynamic
15561 && !h->def_regular)
5e681ec4
PB		 15562 || (htab->root.dynamic_sections_created
15563 && (h->root.type == bfd_link_hash_undefweak
15564 || h->root.type == bfd_link_hash_undefined))))
15565 {
15566 /* Make sure this symbol is output as a dynamic symbol.
15567 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15568 if (h->dynindx == -1 && !h->forced_local
15569 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15570 {
c152c796 15571 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15572 return FALSE;
15573 }
15574
15575 /* If that succeeded, we know we'll be keeping all the
15576 relocs. */
15577 if (h->dynindx != -1)
15578 goto keep;
15579 }
15580
0bdcacaf 15581 eh->dyn_relocs = NULL;
5e681ec4
PB		 15582
15583 keep: ;
15584 }
15585
15586 /* Finally, allocate space. */
0bdcacaf 15587 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15588 {
0bdcacaf 15589 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15590 if (h->type == STT_GNU_IFUNC
15591 && eh->plt.noncall_refcount == 0
15592 && SYMBOL_REFERENCES_LOCAL (info, h))
15593 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15594 else
15595 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15596 }
15597
15598 return TRUE;
15599}
15600
08d1f311
DJ		 15601/* Find any dynamic relocs that apply to read-only sections. */
15602
15603static bfd_boolean
8029a119 15604elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15605{
8029a119 15606 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15607 struct elf_dyn_relocs * p;
08d1f311 15608
08d1f311 15609 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15610 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15611 {
0bdcacaf 15612 asection *s = p->sec;
08d1f311
DJ		 15613
15614 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15615 {
15616 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15617
15618 info->flags |= DF_TEXTREL;
15619
15620 /* Not an error, just cut short the traversal. */
15621 return FALSE;
15622 }
15623 }
15624 return TRUE;
15625}
15626
d504ffc8
DJ		 15627void
15628bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15629 int byteswap_code)
15630{
15631 struct elf32_arm_link_hash_table *globals;
15632
15633 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15634 if (globals == NULL)
15635 return;
15636
d504ffc8
DJ		 15637 globals->byteswap_code = byteswap_code;
15638}
15639
252b5132
RH		 15640/* Set the sizes of the dynamic sections. */
15641
b34976b6 15642static bfd_boolean
57e8b36a
NC		 15643elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15644 struct bfd_link_info * info)
252b5132
RH		 15645{
15646 bfd * dynobj;
15647 asection * s;
b34976b6
AM		 15648 bfd_boolean plt;
15649 bfd_boolean relocs;
5e681ec4
PB		 15650 bfd *ibfd;
15651 struct elf32_arm_link_hash_table *htab;
252b5132 15652
5e681ec4 15653 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15654 if (htab == NULL)
15655 return FALSE;
15656
252b5132
RH		 15657 dynobj = elf_hash_table (info)->dynobj;
15658 BFD_ASSERT (dynobj != NULL);
39b41c9c 15659 check_use_blx (htab);
252b5132
RH		 15660
15661 if (elf_hash_table (info)->dynamic_sections_created)
15662 {
15663 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15664 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15665 {
3d4d4302 15666 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15667 BFD_ASSERT (s != NULL);
eea6121a 15668 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15669 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15670 }
15671 }
5e681ec4
PB		 15672
15673 /* Set up .got offsets for local syms, and space for local dynamic
15674 relocs. */
c72f2fb2 15675 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15676 {
5e681ec4
PB		 15677 bfd_signed_vma *local_got;
15678 bfd_signed_vma *end_local_got;
34e77a92 15679 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15680 char *local_tls_type;
0855e32b 15681 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15682 bfd_size_type locsymcount;
15683 Elf_Internal_Shdr *symtab_hdr;
15684 asection *srel;
4dfe6ac6 15685 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15686 unsigned int symndx;
5e681ec4 15687
0ffa91dd 15688 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15689 continue;
15690
15691 for (s = ibfd->sections; s != NULL; s = s->next)
15692 {
0bdcacaf 15693 struct elf_dyn_relocs *p;
5e681ec4 15694
0bdcacaf 15695 for (p = (struct elf_dyn_relocs *)
99059e56 15696 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15697 {
0bdcacaf
RS		 15698 if (!bfd_is_abs_section (p->sec)
15699 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15700 {
15701 /* Input section has been discarded, either because
15702 it is a copy of a linkonce section or due to
15703 linker script /DISCARD/, so we'll be discarding
15704 the relocs too. */
15705 }
3348747a 15706 else if (is_vxworks
0bdcacaf 15707 && strcmp (p->sec->output_section->name,
3348747a
NS		 15708 ".tls_vars") == 0)
15709 {
15710 /* Relocations in vxworks .tls_vars sections are
15711 handled specially by the loader. */
15712 }
5e681ec4
PB		 15713 else if (p->count != 0)
15714 {
0bdcacaf 15715 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15716 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15717 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15718 info->flags |= DF_TEXTREL;
15719 }
15720 }
15721 }
15722
15723 local_got = elf_local_got_refcounts (ibfd);
15724 if (!local_got)
15725 continue;
15726
0ffa91dd 15727 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15728 locsymcount = symtab_hdr->sh_info;
15729 end_local_got = local_got + locsymcount;
34e77a92 15730 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15731 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15732 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15733 symndx = 0;
362d30a1
RS		 15734 s = htab->root.sgot;
15735 srel = htab->root.srelgot;
0855e32b 15736 for (; local_got < end_local_got;
34e77a92
RS		 15737 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15738 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15739 {
0855e32b 15740 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15741 local_iplt = *local_iplt_ptr;
15742 if (local_iplt != NULL)
15743 {
15744 struct elf_dyn_relocs *p;
15745
15746 if (local_iplt->root.refcount > 0)
15747 {
15748 elf32_arm_allocate_plt_entry (info, TRUE,
15749 &local_iplt->root,
15750 &local_iplt->arm);
15751 if (local_iplt->arm.noncall_refcount == 0)
15752 /* All references to the PLT are calls, so all
15753 non-call references can resolve directly to the
15754 run-time target. This means that the .got entry
15755 would be the same as the .igot.plt entry, so there's
15756 no point creating both. */
15757 *local_got = 0;
15758 }
15759 else
15760 {
15761 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15762 local_iplt->root.offset = (bfd_vma) -1;
15763 }
15764
15765 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15766 {
15767 asection *psrel;
15768
15769 psrel = elf_section_data (p->sec)->sreloc;
15770 if (local_iplt->arm.noncall_refcount == 0)
15771 elf32_arm_allocate_irelocs (info, psrel, p->count);
15772 else
15773 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15774 }
15775 }
5e681ec4
PB		 15776 if (*local_got > 0)
15777 {
34e77a92
RS		 15778 Elf_Internal_Sym *isym;
15779
eea6121a 15780 *local_got = s->size;
ba93b8ac
DJ		 15781 if (*local_tls_type & GOT_TLS_GD)
15782 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15783 s->size += 8;
0855e32b
NS		 15784 if (*local_tls_type & GOT_TLS_GDESC)
15785 {
15786 *local_tlsdesc_gotent = htab->root.sgotplt->size
15787 - elf32_arm_compute_jump_table_size (htab);
15788 htab->root.sgotplt->size += 8;
15789 *local_got = (bfd_vma) -2;
34e77a92 15790 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15791 reloc in the middle of .got.plt. */
99059e56 15792 htab->num_tls_desc++;
0855e32b 15793 }
ba93b8ac
DJ		 15794 if (*local_tls_type & GOT_TLS_IE)
15795 s->size += 4;
ba93b8ac 15796
0855e32b
NS		 15797 if (*local_tls_type & GOT_NORMAL)
15798 {
15799 /* If the symbol is both GD and GDESC, *local_got
15800 may have been overwritten. */
15801 *local_got = s->size;
15802 s->size += 4;
15803 }
15804
34e77a92
RS		 15805 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15806 if (isym == NULL)
15807 return FALSE;
15808
15809 /* If all references to an STT_GNU_IFUNC PLT are calls,
15810 then all non-call references, including this GOT entry,
15811 resolve directly to the run-time target. */
15812 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15813 && (local_iplt == NULL
15814 || local_iplt->arm.noncall_refcount == 0))
15815 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15816 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15817 {
0e1862bb 15818 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15819 || *local_tls_type & GOT_TLS_GD)
15820 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15821
0e1862bb 15822 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15823 {
15824 elf32_arm_allocate_dynrelocs (info,
15825 htab->root.srelplt, 1);
15826 htab->tls_trampoline = -1;
15827 }
0855e32b 15828 }
5e681ec4
PB		 15829 }
15830 else
15831 *local_got = (bfd_vma) -1;
15832 }
252b5132
RH		 15833 }
15834
ba93b8ac
DJ		 15835 if (htab->tls_ldm_got.refcount > 0)
15836 {
15837 /* Allocate two GOT entries and one dynamic relocation (if necessary)
15838 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 15839 htab->tls_ldm_got.offset = htab->root.sgot->size;
15840 htab->root.sgot->size += 8;
0e1862bb 15841 if (bfd_link_pic (info))
47beaa6a 15842 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15843 }
15844 else
15845 htab->tls_ldm_got.offset = -1;
15846
5e681ec4
PB		 15847 /* Allocate global sym .plt and .got entries, and space for global
15848 sym dynamic relocs. */
47beaa6a 15849 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 15850
d504ffc8 15851 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 15852 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 15853 {
0ffa91dd 15854 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 15855 continue;
15856
c7b8f16e
JB		 15857 /* Initialise mapping tables for code/data. */
15858 bfd_elf32_arm_init_maps (ibfd);
906e58ca 15859
c7b8f16e 15860 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 15861 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
15862 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
dae82561 15863 _bfd_error_handler (_("Errors encountered processing file %B"), ibfd);
c7b8f16e 15864 }
d504ffc8 15865
3e6b1042
DJ		 15866 /* Allocate space for the glue sections now that we've sized them. */
15867 bfd_elf32_arm_allocate_interworking_sections (info);
15868
0855e32b
NS		 15869 /* For every jump slot reserved in the sgotplt, reloc_count is
15870 incremented. However, when we reserve space for TLS descriptors,
15871 it's not incremented, so in order to compute the space reserved
15872 for them, it suffices to multiply the reloc count by the jump
15873 slot size. */
15874 if (htab->root.srelplt)
15875 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
15876
15877 if (htab->tls_trampoline)
15878 {
15879 if (htab->root.splt->size == 0)
15880 htab->root.splt->size += htab->plt_header_size;
b38cadfb 15881
0855e32b
NS		 15882 htab->tls_trampoline = htab->root.splt->size;
15883 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 15884
0855e32b 15885 /* If we're not using lazy TLS relocations, don't generate the
99059e56 15886 PLT and GOT entries they require. */
0855e32b
NS		 15887 if (!(info->flags & DF_BIND_NOW))
15888 {
15889 htab->dt_tlsdesc_got = htab->root.sgot->size;
15890 htab->root.sgot->size += 4;
15891
15892 htab->dt_tlsdesc_plt = htab->root.splt->size;
15893 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
15894 }
15895 }
15896
252b5132
RH		 15897 /* The check_relocs and adjust_dynamic_symbol entry points have
15898 determined the sizes of the various dynamic sections. Allocate
15899 memory for them. */
b34976b6
AM		 15900 plt = FALSE;
15901 relocs = FALSE;
252b5132
RH		 15902 for (s = dynobj->sections; s != NULL; s = s->next)
15903 {
15904 const char * name;
252b5132
RH		 15905
15906 if ((s->flags & SEC_LINKER_CREATED) == 0)
15907 continue;
15908
15909 /* It's OK to base decisions on the section name, because none
15910 of the dynobj section names depend upon the input files. */
15911 name = bfd_get_section_name (dynobj, s);
15912
34e77a92 15913 if (s == htab->root.splt)
252b5132 15914 {
c456f082
AM		 15915 /* Remember whether there is a PLT. */
15916 plt = s->size != 0;
252b5132 15917 }
0112cd26 15918 else if (CONST_STRNEQ (name, ".rel"))
252b5132 15919 {
c456f082 15920 if (s->size != 0)
252b5132 15921 {
252b5132 15922 /* Remember whether there are any reloc sections other
00a97672 15923 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 15924 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 15925 relocs = TRUE;
252b5132
RH		 15926
15927 /* We use the reloc_count field as a counter if we need
15928 to copy relocs into the output file. */
15929 s->reloc_count = 0;
15930 }
15931 }
34e77a92
RS		 15932 else if (s != htab->root.sgot
15933 && s != htab->root.sgotplt
15934 && s != htab->root.iplt
15935 && s != htab->root.igotplt
5474d94f
AM		 15936 && s != htab->root.sdynbss
15937 && s != htab->root.sdynrelro)
252b5132
RH		 15938 {
15939 /* It's not one of our sections, so don't allocate space. */
15940 continue;
15941 }
15942
c456f082 15943 if (s->size == 0)
252b5132 15944 {
c456f082 15945 /* If we don't need this section, strip it from the
00a97672
RS		 15946 output file. This is mostly to handle .rel(a).bss and
15947 .rel(a).plt. We must create both sections in
c456f082
AM		 15948 create_dynamic_sections, because they must be created
15949 before the linker maps input sections to output
15950 sections. The linker does that before
15951 adjust_dynamic_symbol is called, and it is that
15952 function which decides whether anything needs to go
15953 into these sections. */
8423293d 15954 s->flags |= SEC_EXCLUDE;
252b5132
RH		 15955 continue;
15956 }
15957
c456f082
AM		 15958 if ((s->flags & SEC_HAS_CONTENTS) == 0)
15959 continue;
15960
252b5132 15961 /* Allocate memory for the section contents. */
21d799b5 15962 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 15963 if (s->contents == NULL)
b34976b6 15964 return FALSE;
252b5132
RH		 15965 }
15966
15967 if (elf_hash_table (info)->dynamic_sections_created)
15968 {
15969 /* Add some entries to the .dynamic section. We fill in the
15970 values later, in elf32_arm_finish_dynamic_sections, but we
15971 must add the entries now so that we get the correct size for
15972 the .dynamic section. The DT_DEBUG entry is filled in by the
15973 dynamic linker and used by the debugger. */
dc810e39 15974#define add_dynamic_entry(TAG, VAL) \
5a580b3a 15975 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 15976
0e1862bb 15977 if (bfd_link_executable (info))
252b5132 15978 {
dc810e39 15979 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 15980 return FALSE;
252b5132
RH		 15981 }
15982
15983 if (plt)
15984 {
dc810e39
AM		 15985 if ( !add_dynamic_entry (DT_PLTGOT, 0)
15986 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 15987 || !add_dynamic_entry (DT_PLTREL,
15988 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 15989 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 15990 return FALSE;
0855e32b 15991
5025eb7c
AO		 15992 if (htab->dt_tlsdesc_plt
15993 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
15994 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 15995 return FALSE;
252b5132
RH		 15996 }
15997
15998 if (relocs)
15999 {
00a97672
RS		 16000 if (htab->use_rel)
16001 {
16002 if (!add_dynamic_entry (DT_REL, 0)
16003 || !add_dynamic_entry (DT_RELSZ, 0)
16004 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16005 return FALSE;
16006 }
16007 else
16008 {
16009 if (!add_dynamic_entry (DT_RELA, 0)
16010 || !add_dynamic_entry (DT_RELASZ, 0)
16011 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16012 return FALSE;
16013 }
252b5132
RH		 16014 }
16015
08d1f311
DJ		 16016 /* If any dynamic relocs apply to a read-only section,
16017 then we need a DT_TEXTREL entry. */
16018 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 16019 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
16020 info);
08d1f311 16021
99e4ae17 16022 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16023 {
dc810e39 16024 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16025 return FALSE;
252b5132 16026 }
7a2b07ff
NS		 16027 if (htab->vxworks_p
16028 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16029 return FALSE;
252b5132 16030 }
8532796c 16031#undef add_dynamic_entry
252b5132 16032
b34976b6 16033 return TRUE;
252b5132
RH		 16034}
16035
0855e32b
NS		 16036/* Size sections even though they're not dynamic. We use it to setup
16037 _TLS_MODULE_BASE_, if needed. */
16038
16039static bfd_boolean
16040elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16041 struct bfd_link_info *info)
0855e32b
NS		 16042{
16043 asection *tls_sec;
16044
0e1862bb 16045 if (bfd_link_relocatable (info))
0855e32b
NS		 16046 return TRUE;
16047
16048 tls_sec = elf_hash_table (info)->tls_sec;
16049
16050 if (tls_sec)
16051 {
16052 struct elf_link_hash_entry *tlsbase;
16053
16054 tlsbase = elf_link_hash_lookup
16055 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16056
16057 if (tlsbase)
99059e56
RM		 16058 {
16059 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16060 const struct elf_backend_data *bed
99059e56 16061 = get_elf_backend_data (output_bfd);
0855e32b 16062
99059e56 16063 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16064 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16065 tls_sec, 0, NULL, FALSE,
16066 bed->collect, &bh)))
16067 return FALSE;
b38cadfb 16068
99059e56
RM		 16069 tlsbase->type = STT_TLS;
16070 tlsbase = (struct elf_link_hash_entry *)bh;
16071 tlsbase->def_regular = 1;
16072 tlsbase->other = STV_HIDDEN;
16073 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16074 }
16075 }
16076 return TRUE;
16077}
16078
252b5132
RH		 16079/* Finish up dynamic symbol handling. We set the contents of various
16080 dynamic sections here. */
16081
b34976b6 16082static bfd_boolean
906e58ca
NC		 16083elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16084 struct bfd_link_info * info,
16085 struct elf_link_hash_entry * h,
16086 Elf_Internal_Sym * sym)
252b5132 16087{
e5a52504 16088 struct elf32_arm_link_hash_table *htab;
b7693d02 16089 struct elf32_arm_link_hash_entry *eh;
252b5132 16090
e5a52504 16091 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16092 if (htab == NULL)
16093 return FALSE;
16094
b7693d02 16095 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16096
16097 if (h->plt.offset != (bfd_vma) -1)
16098 {
34e77a92 16099 if (!eh->is_iplt)
e5a52504 16100 {
34e77a92 16101 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16102 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16103 h->dynindx, 0))
16104 return FALSE;
e5a52504 16105 }
57e8b36a 16106
f5385ebf 16107 if (!h->def_regular)
252b5132
RH		 16108 {
16109 /* Mark the symbol as undefined, rather than as defined in
3a635617 16110 the .plt section. */
252b5132 16111 sym->st_shndx = SHN_UNDEF;
3a635617 16112 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16113 Otherwise, the PLT entry would provide a definition for
16114 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16115 and so the symbol would never be NULL. Leave the value if
16116 there were any relocations where pointer equality matters
16117 (this is a clue for the dynamic linker, to make function
16118 pointer comparisons work between an application and shared
16119 library). */
97323ad1 16120 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16121 sym->st_value = 0;
252b5132 16122 }
34e77a92
RS		 16123 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16124 {
16125 /* At least one non-call relocation references this .iplt entry,
16126 so the .iplt entry is the function's canonical address. */
16127 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16128 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16129 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16130 (output_bfd, htab->root.iplt->output_section));
16131 sym->st_value = (h->plt.offset
16132 + htab->root.iplt->output_section->vma
16133 + htab->root.iplt->output_offset);
16134 }
252b5132
RH		 16135 }
16136
f5385ebf 16137 if (h->needs_copy)
252b5132
RH		 16138 {
16139 asection * s;
947216bf 16140 Elf_Internal_Rela rel;
252b5132
RH		 16141
16142 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16143 BFD_ASSERT (h->dynindx != -1
16144 && (h->root.type == bfd_link_hash_defined
16145 || h->root.type == bfd_link_hash_defweak));
16146
00a97672 16147 rel.r_addend = 0;
252b5132
RH		 16148 rel.r_offset = (h->root.u.def.value
16149 + h->root.u.def.section->output_section->vma
16150 + h->root.u.def.section->output_offset);
16151 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 16152 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 16153 s = htab->root.sreldynrelro;
16154 else
16155 s = htab->root.srelbss;
47beaa6a 16156 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16157 }
16158
00a97672
RS		 16159 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16160 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16161 to the ".got" section. */
9637f6ef 16162 if (h == htab->root.hdynamic
00a97672 16163 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16164 sym->st_shndx = SHN_ABS;
16165
b34976b6 16166 return TRUE;
252b5132
RH		 16167}
16168
0855e32b
NS		 16169static void
16170arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16171 void *contents,
16172 const unsigned long *template, unsigned count)
16173{
16174 unsigned ix;
b38cadfb 16175
0855e32b
NS		 16176 for (ix = 0; ix != count; ix++)
16177 {
16178 unsigned long insn = template[ix];
16179
16180 /* Emit mov pc,rx if bx is not permitted. */
16181 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16182 insn = (insn & 0xf000000f) | 0x01a0f000;
16183 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16184 }
16185}
16186
99059e56
RM		 16187/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16188 other variants, NaCl needs this entry in a static executable's
16189 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16190 zero. For .iplt really only the last bundle is useful, and .iplt
16191 could have a shorter first entry, with each individual PLT entry's
16192 relative branch calculated differently so it targets the last
16193 bundle instead of the instruction before it (labelled .Lplt_tail
16194 above). But it's simpler to keep the size and layout of PLT0
16195 consistent with the dynamic case, at the cost of some dead code at
16196 the start of .iplt and the one dead store to the stack at the start
16197 of .Lplt_tail. */
16198static void
16199arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16200 asection *plt, bfd_vma got_displacement)
16201{
16202 unsigned int i;
16203
16204 put_arm_insn (htab, output_bfd,
16205 elf32_arm_nacl_plt0_entry[0]
16206 | arm_movw_immediate (got_displacement),
16207 plt->contents + 0);
16208 put_arm_insn (htab, output_bfd,
16209 elf32_arm_nacl_plt0_entry[1]
16210 | arm_movt_immediate (got_displacement),
16211 plt->contents + 4);
16212
16213 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16214 put_arm_insn (htab, output_bfd,
16215 elf32_arm_nacl_plt0_entry[i],
16216 plt->contents + (i * 4));
16217}
16218
252b5132
RH		 16219/* Finish up the dynamic sections. */
16220
b34976b6 16221static bfd_boolean
57e8b36a 16222elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16223{
16224 bfd * dynobj;
16225 asection * sgot;
16226 asection * sdyn;
4dfe6ac6
NC		 16227 struct elf32_arm_link_hash_table *htab;
16228
16229 htab = elf32_arm_hash_table (info);
16230 if (htab == NULL)
16231 return FALSE;
252b5132
RH		 16232
16233 dynobj = elf_hash_table (info)->dynobj;
16234
362d30a1 16235 sgot = htab->root.sgotplt;
894891db
NC		 16236 /* A broken linker script might have discarded the dynamic sections.
16237 Catch this here so that we do not seg-fault later on. */
16238 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16239 return FALSE;
3d4d4302 16240 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16241
16242 if (elf_hash_table (info)->dynamic_sections_created)
16243 {
16244 asection *splt;
16245 Elf32_External_Dyn *dyncon, *dynconend;
16246
362d30a1 16247 splt = htab->root.splt;
24a1ba0f 16248 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16249 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16250
16251 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16252 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16253
252b5132
RH		 16254 for (; dyncon < dynconend; dyncon++)
16255 {
16256 Elf_Internal_Dyn dyn;
16257 const char * name;
16258 asection * s;
16259
16260 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16261
16262 switch (dyn.d_tag)
16263 {
229fcec5
MM		 16264 unsigned int type;
16265
252b5132 16266 default:
7a2b07ff
NS		 16267 if (htab->vxworks_p
16268 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16269 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16270 break;
16271
229fcec5
MM		 16272 case DT_HASH:
16273 name = ".hash";
16274 goto get_vma_if_bpabi;
16275 case DT_STRTAB:
16276 name = ".dynstr";
16277 goto get_vma_if_bpabi;
16278 case DT_SYMTAB:
16279 name = ".dynsym";
16280 goto get_vma_if_bpabi;
c0042f5d
MM		 16281 case DT_VERSYM:
16282 name = ".gnu.version";
16283 goto get_vma_if_bpabi;
16284 case DT_VERDEF:
16285 name = ".gnu.version_d";
16286 goto get_vma_if_bpabi;
16287 case DT_VERNEED:
16288 name = ".gnu.version_r";
16289 goto get_vma_if_bpabi;
16290
252b5132 16291 case DT_PLTGOT:
4ade44b7 16292 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16293 goto get_vma;
16294 case DT_JMPREL:
00a97672 16295 name = RELOC_SECTION (htab, ".plt");
252b5132 16296 get_vma:
4ade44b7 16297 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16298 if (s == NULL)
16299 {
4eca0228 16300 _bfd_error_handler
4ade44b7 16301 (_("could not find section %s"), name);
05456594
NC		 16302 bfd_set_error (bfd_error_invalid_operation);
16303 return FALSE;
16304 }
229fcec5 16305 if (!htab->symbian_p)
4ade44b7 16306 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16307 else
16308 /* In the BPABI, tags in the PT_DYNAMIC section point
16309 at the file offset, not the memory address, for the
16310 convenience of the post linker. */
4ade44b7 16311 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16312 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16313 break;
16314
229fcec5
MM		 16315 get_vma_if_bpabi:
16316 if (htab->symbian_p)
16317 goto get_vma;
16318 break;
16319
252b5132 16320 case DT_PLTRELSZ:
362d30a1 16321 s = htab->root.srelplt;
252b5132 16322 BFD_ASSERT (s != NULL);
eea6121a 16323 dyn.d_un.d_val = s->size;
252b5132
RH		 16324 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16325 break;
906e58ca 16326
252b5132 16327 case DT_RELSZ:
00a97672 16328 case DT_RELASZ:
229fcec5
MM		 16329 case DT_REL:
16330 case DT_RELA:
229fcec5
MM		 16331 /* In the BPABI, the DT_REL tag must point at the file
16332 offset, not the VMA, of the first relocation
16333 section. So, we use code similar to that in
16334 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 16335 relocation section, since relocation sections are
16336 never allocated under the BPABI. PLT relocs are also
16337 included. */
229fcec5
MM		 16338 if (htab->symbian_p)
16339 {
16340 unsigned int i;
16341 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16342 ? SHT_REL : SHT_RELA);
16343 dyn.d_un.d_val = 0;
16344 for (i = 1; i < elf_numsections (output_bfd); i++)
16345 {
906e58ca 16346 Elf_Internal_Shdr *hdr
229fcec5
MM		 16347 = elf_elfsections (output_bfd)[i];
16348 if (hdr->sh_type == type)
16349 {
906e58ca 16350 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16351 || dyn.d_tag == DT_RELASZ)
16352 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16353 else if ((ufile_ptr) hdr->sh_offset
16354 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16355 dyn.d_un.d_val = hdr->sh_offset;
16356 }
16357 }
16358 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16359 }
252b5132 16360 break;
88f7bcd5 16361
0855e32b 16362 case DT_TLSDESC_PLT:
99059e56 16363 s = htab->root.splt;
0855e32b
NS		 16364 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16365 + htab->dt_tlsdesc_plt);
16366 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16367 break;
16368
16369 case DT_TLSDESC_GOT:
99059e56 16370 s = htab->root.sgot;
0855e32b 16371 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16372 + htab->dt_tlsdesc_got);
0855e32b
NS		 16373 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16374 break;
16375
88f7bcd5
NC		 16376 /* Set the bottom bit of DT_INIT/FINI if the
16377 corresponding function is Thumb. */
16378 case DT_INIT:
16379 name = info->init_function;
16380 goto get_sym;
16381 case DT_FINI:
16382 name = info->fini_function;
16383 get_sym:
16384 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16385 then there is nothing to adjust. */
88f7bcd5
NC		 16386 if (dyn.d_un.d_val != 0)
16387 {
16388 struct elf_link_hash_entry * eh;
16389
16390 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16391 FALSE, FALSE, TRUE);
39d911fc
TP		 16392 if (eh != NULL
16393 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16394 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16395 {
16396 dyn.d_un.d_val |= 1;
b34976b6 16397 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16398 }
16399 }
16400 break;
252b5132
RH		 16401 }
16402 }
16403
24a1ba0f 16404 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16405 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16406 {
00a97672
RS		 16407 const bfd_vma *plt0_entry;
16408 bfd_vma got_address, plt_address, got_displacement;
16409
16410 /* Calculate the addresses of the GOT and PLT. */
16411 got_address = sgot->output_section->vma + sgot->output_offset;
16412 plt_address = splt->output_section->vma + splt->output_offset;
16413
16414 if (htab->vxworks_p)
16415 {
16416 /* The VxWorks GOT is relocated by the dynamic linker.
16417 Therefore, we must emit relocations rather than simply
16418 computing the values now. */
16419 Elf_Internal_Rela rel;
16420
16421 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16422 put_arm_insn (htab, output_bfd, plt0_entry[0],
16423 splt->contents + 0);
16424 put_arm_insn (htab, output_bfd, plt0_entry[1],
16425 splt->contents + 4);
16426 put_arm_insn (htab, output_bfd, plt0_entry[2],
16427 splt->contents + 8);
00a97672
RS		 16428 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16429
8029a119 16430 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16431 rel.r_offset = plt_address + 12;
16432 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16433 rel.r_addend = 0;
16434 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16435 htab->srelplt2->contents);
16436 }
b38cadfb 16437 else if (htab->nacl_p)
99059e56
RM		 16438 arm_nacl_put_plt0 (htab, output_bfd, splt,
16439 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16440 else if (using_thumb_only (htab))
16441 {
16442 got_displacement = got_address - (plt_address + 12);
16443
16444 plt0_entry = elf32_thumb2_plt0_entry;
16445 put_arm_insn (htab, output_bfd, plt0_entry[0],
16446 splt->contents + 0);
16447 put_arm_insn (htab, output_bfd, plt0_entry[1],
16448 splt->contents + 4);
16449 put_arm_insn (htab, output_bfd, plt0_entry[2],
16450 splt->contents + 8);
16451
16452 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16453 }
00a97672
RS		 16454 else
16455 {
16456 got_displacement = got_address - (plt_address + 16);
16457
16458 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16459 put_arm_insn (htab, output_bfd, plt0_entry[0],
16460 splt->contents + 0);
16461 put_arm_insn (htab, output_bfd, plt0_entry[1],
16462 splt->contents + 4);
16463 put_arm_insn (htab, output_bfd, plt0_entry[2],
16464 splt->contents + 8);
16465 put_arm_insn (htab, output_bfd, plt0_entry[3],
16466 splt->contents + 12);
5e681ec4 16467
5e681ec4 16468#ifdef FOUR_WORD_PLT
00a97672
RS		 16469 /* The displacement value goes in the otherwise-unused
16470 last word of the second entry. */
16471 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16472#else
00a97672 16473 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16474#endif
00a97672 16475 }
f7a74f8c 16476 }
252b5132
RH		 16477
16478 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16479 really seem like the right value. */
74541ad4
AM		 16480 if (splt->output_section->owner == output_bfd)
16481 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16482
0855e32b
NS		 16483 if (htab->dt_tlsdesc_plt)
16484 {
16485 bfd_vma got_address
16486 = sgot->output_section->vma + sgot->output_offset;
16487 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16488 + htab->root.sgot->output_offset);
16489 bfd_vma plt_address
16490 = splt->output_section->vma + splt->output_offset;
16491
b38cadfb 16492 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16493 splt->contents + htab->dt_tlsdesc_plt,
16494 dl_tlsdesc_lazy_trampoline, 6);
16495
16496 bfd_put_32 (output_bfd,
16497 gotplt_address + htab->dt_tlsdesc_got
16498 - (plt_address + htab->dt_tlsdesc_plt)
16499 - dl_tlsdesc_lazy_trampoline[6],
16500 splt->contents + htab->dt_tlsdesc_plt + 24);
16501 bfd_put_32 (output_bfd,
16502 got_address - (plt_address + htab->dt_tlsdesc_plt)
16503 - dl_tlsdesc_lazy_trampoline[7],
16504 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16505 }
16506
16507 if (htab->tls_trampoline)
16508 {
b38cadfb 16509 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16510 splt->contents + htab->tls_trampoline,
16511 tls_trampoline, 3);
16512#ifdef FOUR_WORD_PLT
16513 bfd_put_32 (output_bfd, 0x00000000,
16514 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16515#endif
0855e32b
NS		 16516 }
16517
0e1862bb
L		 16518 if (htab->vxworks_p
16519 && !bfd_link_pic (info)
16520 && htab->root.splt->size > 0)
00a97672
RS		 16521 {
16522 /* Correct the .rel(a).plt.unloaded relocations. They will have
16523 incorrect symbol indexes. */
16524 int num_plts;
eed62c48 16525 unsigned char *p;
00a97672 16526
362d30a1 16527 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16528 / htab->plt_entry_size);
16529 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16530
16531 for (; num_plts; num_plts--)
16532 {
16533 Elf_Internal_Rela rel;
16534
16535 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16536 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16537 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16538 p += RELOC_SIZE (htab);
16539
16540 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16541 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16542 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16543 p += RELOC_SIZE (htab);
16544 }
16545 }
252b5132
RH		 16546 }
16547
99059e56
RM		 16548 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16549 /* NaCl uses a special first entry in .iplt too. */
16550 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16551
252b5132 16552 /* Fill in the first three entries in the global offset table. */
229fcec5 16553 if (sgot)
252b5132 16554 {
229fcec5
MM		 16555 if (sgot->size > 0)
16556 {
16557 if (sdyn == NULL)
16558 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16559 else
16560 bfd_put_32 (output_bfd,
16561 sdyn->output_section->vma + sdyn->output_offset,
16562 sgot->contents);
16563 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16564 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16565 }
252b5132 16566
229fcec5
MM		 16567 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16568 }
252b5132 16569
b34976b6 16570 return TRUE;
252b5132
RH		 16571}
16572
ba96a88f 16573static void
57e8b36a 16574elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16575{
9b485d32 16576 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16577 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16578 struct elf_segment_map *m;
ba96a88f
NC		 16579
16580 i_ehdrp = elf_elfheader (abfd);
16581
94a3258f
PB		 16582 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16583 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16584 else
7394f108 16585 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16586 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16587
93204d3a
PB		 16588 if (link_info)
16589 {
16590 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16591 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16592 i_ehdrp->e_flags |= EF_ARM_BE8;
16593 }
3bfcb652
NC		 16594
16595 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16596 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16597 {
16598 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16599 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16600 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16601 else
16602 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16603 }
ac4c9b04
MG		 16604
16605 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16606 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16607 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16608 {
16609 unsigned int j;
16610
16611 if (m->count == 0)
16612 continue;
16613 for (j = 0; j < m->count; j++)
16614 {
f0728ee3 16615 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16616 break;
16617 }
16618 if (j == m->count)
16619 {
16620 m->p_flags = PF_X;
16621 m->p_flags_valid = 1;
16622 }
16623 }
ba96a88f
NC		 16624}
16625
99e4ae17 16626static enum elf_reloc_type_class
7e612e98
AM		 16627elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16628 const asection *rel_sec ATTRIBUTE_UNUSED,
16629 const Elf_Internal_Rela *rela)
99e4ae17 16630{
f51e552e 16631 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16632 {
16633 case R_ARM_RELATIVE:
16634 return reloc_class_relative;
16635 case R_ARM_JUMP_SLOT:
16636 return reloc_class_plt;
16637 case R_ARM_COPY:
16638 return reloc_class_copy;
109575d7
JW		 16639 case R_ARM_IRELATIVE:
16640 return reloc_class_ifunc;
99e4ae17
AJ		 16641 default:
16642 return reloc_class_normal;
16643 }
16644}
16645
e489d0ae 16646static void
57e8b36a 16647elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16648{
5a6c6817 16649 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16650}
16651
40a18ebd
NC		 16652/* Return TRUE if this is an unwinding table entry. */
16653
16654static bfd_boolean
16655is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16656{
0112cd26
NC		 16657 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16658 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16659}
16660
16661
16662/* Set the type and flags for an ARM section. We do this by
16663 the section name, which is a hack, but ought to work. */
16664
16665static bfd_boolean
16666elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16667{
16668 const char * name;
16669
16670 name = bfd_get_section_name (abfd, sec);
16671
16672 if (is_arm_elf_unwind_section_name (abfd, name))
16673 {
16674 hdr->sh_type = SHT_ARM_EXIDX;
16675 hdr->sh_flags |= SHF_LINK_ORDER;
16676 }
ac4c9b04 16677
f0728ee3
AV		 16678 if (sec->flags & SEC_ELF_PURECODE)
16679 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16680
40a18ebd
NC		 16681 return TRUE;
16682}
16683
6dc132d9
L		 16684/* Handle an ARM specific section when reading an object file. This is
16685 called when bfd_section_from_shdr finds a section with an unknown
16686 type. */
40a18ebd
NC		 16687
16688static bfd_boolean
16689elf32_arm_section_from_shdr (bfd *abfd,
16690 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16691 const char *name,
16692 int shindex)
40a18ebd
NC		 16693{
16694 /* There ought to be a place to keep ELF backend specific flags, but
16695 at the moment there isn't one. We just keep track of the
16696 sections by their name, instead. Fortunately, the ABI gives
16697 names for all the ARM specific sections, so we will probably get
16698 away with this. */
16699 switch (hdr->sh_type)
16700 {
16701 case SHT_ARM_EXIDX:
0951f019
RE		 16702 case SHT_ARM_PREEMPTMAP:
16703 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16704 break;
16705
16706 default:
16707 return FALSE;
16708 }
16709
6dc132d9 16710 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16711 return FALSE;
16712
16713 return TRUE;
16714}
e489d0ae 16715
44444f50
NC		 16716static _arm_elf_section_data *
16717get_arm_elf_section_data (asection * sec)
16718{
47b2e99c
JZ		 16719 if (sec && sec->owner && is_arm_elf (sec->owner))
16720 return elf32_arm_section_data (sec);
44444f50
NC		 16721 else
16722 return NULL;
8e3de13a
NC		 16723}
16724
4e617b1e
PB		 16725typedef struct
16726{
57402f1e 16727 void *flaginfo;
4e617b1e 16728 struct bfd_link_info *info;
91a5743d
PB		 16729 asection *sec;
16730 int sec_shndx;
6e0b88f1
AM		 16731 int (*func) (void *, const char *, Elf_Internal_Sym *,
16732 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16733} output_arch_syminfo;
16734
16735enum map_symbol_type
16736{
16737 ARM_MAP_ARM,
16738 ARM_MAP_THUMB,
16739 ARM_MAP_DATA
16740};
16741
16742
7413f23f 16743/* Output a single mapping symbol. */
4e617b1e
PB		 16744
16745static bfd_boolean
7413f23f
DJ		 16746elf32_arm_output_map_sym (output_arch_syminfo *osi,
16747 enum map_symbol_type type,
16748 bfd_vma offset)
4e617b1e
PB		 16749{
16750 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16751 Elf_Internal_Sym sym;
16752
91a5743d
PB		 16753 sym.st_value = osi->sec->output_section->vma
16754 + osi->sec->output_offset
16755 + offset;
4e617b1e
PB		 16756 sym.st_size = 0;
16757 sym.st_other = 0;
16758 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16759 sym.st_shndx = osi->sec_shndx;
35fc36a8 16760 sym.st_target_internal = 0;
fe33d2fa 16761 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16762 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16763}
16764
34e77a92
RS		 16765/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16766 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16767
16768static bfd_boolean
34e77a92
RS		 16769elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16770 bfd_boolean is_iplt_entry_p,
16771 union gotplt_union *root_plt,
16772 struct arm_plt_info *arm_plt)
4e617b1e 16773{
4e617b1e 16774 struct elf32_arm_link_hash_table *htab;
34e77a92 16775 bfd_vma addr, plt_header_size;
4e617b1e 16776
34e77a92 16777 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16778 return TRUE;
16779
4dfe6ac6
NC		 16780 htab = elf32_arm_hash_table (osi->info);
16781 if (htab == NULL)
16782 return FALSE;
16783
34e77a92
RS		 16784 if (is_iplt_entry_p)
16785 {
16786 osi->sec = htab->root.iplt;
16787 plt_header_size = 0;
16788 }
16789 else
16790 {
16791 osi->sec = htab->root.splt;
16792 plt_header_size = htab->plt_header_size;
16793 }
16794 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16795 (osi->info->output_bfd, osi->sec->output_section));
16796
16797 addr = root_plt->offset & -2;
4e617b1e
PB		 16798 if (htab->symbian_p)
16799 {
7413f23f 16800 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16801 return FALSE;
7413f23f 16802 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16803 return FALSE;
16804 }
16805 else if (htab->vxworks_p)
16806 {
7413f23f 16807 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16808 return FALSE;
7413f23f 16809 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16810 return FALSE;
7413f23f 16811 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16812 return FALSE;
7413f23f 16813 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16814 return FALSE;
16815 }
b38cadfb
NC		 16816 else if (htab->nacl_p)
16817 {
16818 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16819 return FALSE;
16820 }
eed94f8f
NC		 16821 else if (using_thumb_only (htab))
16822 {
16823 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16824 return FALSE;
6a631e86 16825 }
4e617b1e
PB		 16826 else
16827 {
34e77a92 16828 bfd_boolean thumb_stub_p;
bd97cb95 16829
34e77a92
RS		 16830 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16831 if (thumb_stub_p)
4e617b1e 16832 {
7413f23f 16833 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16834 return FALSE;
16835 }
16836#ifdef FOUR_WORD_PLT
7413f23f 16837 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16838 return FALSE;
7413f23f 16839 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 16840 return FALSE;
16841#else
906e58ca 16842 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 16843 so only need to output a mapping symbol for the first PLT entry and
16844 entries with thumb thunks. */
34e77a92 16845 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 16846 {
7413f23f 16847 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 16848 return FALSE;
16849 }
16850#endif
16851 }
16852
16853 return TRUE;
16854}
16855
34e77a92
RS		 16856/* Output mapping symbols for PLT entries associated with H. */
16857
16858static bfd_boolean
16859elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
16860{
16861 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
16862 struct elf32_arm_link_hash_entry *eh;
16863
16864 if (h->root.type == bfd_link_hash_indirect)
16865 return TRUE;
16866
16867 if (h->root.type == bfd_link_hash_warning)
16868 /* When warning symbols are created, they **replace** the "real"
16869 entry in the hash table, thus we never get to see the real
16870 symbol in a hash traversal. So look at it now. */
16871 h = (struct elf_link_hash_entry *) h->root.u.i.link;
16872
16873 eh = (struct elf32_arm_link_hash_entry *) h;
16874 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
16875 &h->plt, &eh->plt);
16876}
16877
4f4faa4d
TP		 16878/* Bind a veneered symbol to its veneer identified by its hash entry
16879 STUB_ENTRY. The veneered location thus loose its symbol. */
16880
16881static void
16882arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
16883{
16884 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
16885
16886 BFD_ASSERT (hash);
16887 hash->root.root.u.def.section = stub_entry->stub_sec;
16888 hash->root.root.u.def.value = stub_entry->stub_offset;
16889 hash->root.size = stub_entry->stub_size;
16890}
16891
7413f23f
DJ		 16892/* Output a single local symbol for a generated stub. */
16893
16894static bfd_boolean
16895elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
16896 bfd_vma offset, bfd_vma size)
16897{
7413f23f
DJ		 16898 Elf_Internal_Sym sym;
16899
7413f23f
DJ		 16900 sym.st_value = osi->sec->output_section->vma
16901 + osi->sec->output_offset
16902 + offset;
16903 sym.st_size = size;
16904 sym.st_other = 0;
16905 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
16906 sym.st_shndx = osi->sec_shndx;
35fc36a8 16907 sym.st_target_internal = 0;
57402f1e 16908 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 16909}
4e617b1e 16910
da5938a2 16911static bfd_boolean
8029a119
NC		 16912arm_map_one_stub (struct bfd_hash_entry * gen_entry,
16913 void * in_arg)
da5938a2
NC		 16914{
16915 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 16916 asection *stub_sec;
16917 bfd_vma addr;
7413f23f 16918 char *stub_name;
9a008db3 16919 output_arch_syminfo *osi;
d3ce72d0 16920 const insn_sequence *template_sequence;
461a49ca
DJ		 16921 enum stub_insn_type prev_type;
16922 int size;
16923 int i;
16924 enum map_symbol_type sym_type;
da5938a2
NC		 16925
16926 /* Massage our args to the form they really have. */
16927 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 16928 osi = (output_arch_syminfo *) in_arg;
da5938a2 16929
da5938a2
NC		 16930 stub_sec = stub_entry->stub_sec;
16931
16932 /* Ensure this stub is attached to the current section being
7413f23f 16933 processed. */
da5938a2
NC		 16934 if (stub_sec != osi->sec)
16935 return TRUE;
16936
7413f23f 16937 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 16938 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 16939
16940 if (arm_stub_sym_claimed (stub_entry->stub_type))
16941 arm_stub_claim_sym (stub_entry);
16942 else
7413f23f 16943 {
4f4faa4d
TP		 16944 stub_name = stub_entry->output_name;
16945 switch (template_sequence[0].type)
16946 {
16947 case ARM_TYPE:
16948 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
16949 stub_entry->stub_size))
16950 return FALSE;
16951 break;
16952 case THUMB16_TYPE:
16953 case THUMB32_TYPE:
16954 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
16955 stub_entry->stub_size))
16956 return FALSE;
16957 break;
16958 default:
16959 BFD_FAIL ();
16960 return 0;
16961 }
7413f23f 16962 }
da5938a2 16963
461a49ca
DJ		 16964 prev_type = DATA_TYPE;
16965 size = 0;
16966 for (i = 0; i < stub_entry->stub_template_size; i++)
16967 {
d3ce72d0 16968 switch (template_sequence[i].type)
461a49ca
DJ		 16969 {
16970 case ARM_TYPE:
16971 sym_type = ARM_MAP_ARM;
16972 break;
16973
16974 case THUMB16_TYPE:
48229727 16975 case THUMB32_TYPE:
461a49ca
DJ		 16976 sym_type = ARM_MAP_THUMB;
16977 break;
16978
16979 case DATA_TYPE:
16980 sym_type = ARM_MAP_DATA;
16981 break;
16982
16983 default:
16984 BFD_FAIL ();
4e31c731 16985 return FALSE;
461a49ca
DJ		 16986 }
16987
d3ce72d0 16988 if (template_sequence[i].type != prev_type)
461a49ca 16989 {
d3ce72d0 16990 prev_type = template_sequence[i].type;
461a49ca
DJ		 16991 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
16992 return FALSE;
16993 }
16994
d3ce72d0 16995 switch (template_sequence[i].type)
461a49ca
DJ		 16996 {
16997 case ARM_TYPE:
48229727 16998 case THUMB32_TYPE:
461a49ca
DJ		 16999 size += 4;
17000 break;
17001
17002 case THUMB16_TYPE:
17003 size += 2;
17004 break;
17005
17006 case DATA_TYPE:
17007 size += 4;
17008 break;
17009
17010 default:
17011 BFD_FAIL ();
4e31c731 17012 return FALSE;
461a49ca
DJ		 17013 }
17014 }
17015
da5938a2
NC		 17016 return TRUE;
17017}
17018
33811162
DG		 17019/* Output mapping symbols for linker generated sections,
17020 and for those data-only sections that do not have a
17021 $d. */
4e617b1e
PB		 17022
17023static bfd_boolean
17024elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17025 struct bfd_link_info *info,
57402f1e 17026 void *flaginfo,
6e0b88f1
AM		 17027 int (*func) (void *, const char *,
17028 Elf_Internal_Sym *,
17029 asection *,
17030 struct elf_link_hash_entry *))
4e617b1e
PB		 17031{
17032 output_arch_syminfo osi;
17033 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17034 bfd_vma offset;
17035 bfd_size_type size;
33811162 17036 bfd *input_bfd;
4e617b1e
PB		 17037
17038 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17039 if (htab == NULL)
17040 return FALSE;
17041
906e58ca 17042 check_use_blx (htab);
91a5743d 17043
57402f1e 17044 osi.flaginfo = flaginfo;
4e617b1e
PB		 17045 osi.info = info;
17046 osi.func = func;
906e58ca 17047
33811162
DG		 17048 /* Add a $d mapping symbol to data-only sections that
17049 don't have any mapping symbol. This may result in (harmless) redundant
17050 mapping symbols. */
17051 for (input_bfd = info->input_bfds;
17052 input_bfd != NULL;
c72f2fb2 17053 input_bfd = input_bfd->link.next)
33811162
DG		 17054 {
17055 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17056 for (osi.sec = input_bfd->sections;
17057 osi.sec != NULL;
17058 osi.sec = osi.sec->next)
17059 {
17060 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17061 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17062 != 0)
33811162
DG		 17063 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17064 == SEC_HAS_CONTENTS
17065 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17066 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17067 && osi.sec->size > 0
17068 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17069 {
17070 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17071 (output_bfd, osi.sec->output_section);
17072 if (osi.sec_shndx != (int)SHN_BAD)
17073 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17074 }
17075 }
17076 }
17077
91a5743d
PB		 17078 /* ARM->Thumb glue. */
17079 if (htab->arm_glue_size > 0)
17080 {
3d4d4302
AM		 17081 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17082 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17083
17084 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17085 (output_bfd, osi.sec->output_section);
0e1862bb 17086 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17087 || htab->pic_veneer)
17088 size = ARM2THUMB_PIC_GLUE_SIZE;
17089 else if (htab->use_blx)
17090 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17091 else
17092 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17093
91a5743d
PB		 17094 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17095 {
7413f23f
DJ		 17096 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17097 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17098 }
17099 }
17100
17101 /* Thumb->ARM glue. */
17102 if (htab->thumb_glue_size > 0)
17103 {
3d4d4302
AM		 17104 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17105 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17106
17107 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17108 (output_bfd, osi.sec->output_section);
17109 size = THUMB2ARM_GLUE_SIZE;
17110
17111 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17112 {
7413f23f
DJ		 17113 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17114 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17115 }
17116 }
17117
845b51d6
PB		 17118 /* ARMv4 BX veneers. */
17119 if (htab->bx_glue_size > 0)
17120 {
3d4d4302
AM		 17121 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17122 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17123
17124 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17125 (output_bfd, osi.sec->output_section);
17126
7413f23f 17127 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17128 }
17129
8029a119
NC		 17130 /* Long calls stubs. */
17131 if (htab->stub_bfd && htab->stub_bfd->sections)
17132 {
da5938a2 17133 asection* stub_sec;
8029a119 17134
da5938a2
NC		 17135 for (stub_sec = htab->stub_bfd->sections;
17136 stub_sec != NULL;
8029a119
NC		 17137 stub_sec = stub_sec->next)
17138 {
17139 /* Ignore non-stub sections. */
17140 if (!strstr (stub_sec->name, STUB_SUFFIX))
17141 continue;
da5938a2 17142
8029a119 17143 osi.sec = stub_sec;
da5938a2 17144
8029a119
NC		 17145 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17146 (output_bfd, osi.sec->output_section);
da5938a2 17147
8029a119
NC		 17148 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17149 }
17150 }
da5938a2 17151
91a5743d 17152 /* Finally, output mapping symbols for the PLT. */
34e77a92 17153 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17154 {
34e77a92
RS		 17155 osi.sec = htab->root.splt;
17156 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17157 (output_bfd, osi.sec->output_section));
17158
17159 /* Output mapping symbols for the plt header. SymbianOS does not have a
17160 plt header. */
17161 if (htab->vxworks_p)
17162 {
17163 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17164 if (!bfd_link_pic (info))
34e77a92
RS		 17165 {
17166 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17167 return FALSE;
17168 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17169 return FALSE;
17170 }
17171 }
b38cadfb
NC		 17172 else if (htab->nacl_p)
17173 {
17174 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17175 return FALSE;
17176 }
eed94f8f
NC		 17177 else if (using_thumb_only (htab))
17178 {
17179 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17180 return FALSE;
17181 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17182 return FALSE;
17183 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17184 return FALSE;
17185 }
34e77a92 17186 else if (!htab->symbian_p)
4e617b1e 17187 {
7413f23f 17188 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17189 return FALSE;
34e77a92
RS		 17190#ifndef FOUR_WORD_PLT
17191 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17192 return FALSE;
34e77a92 17193#endif
4e617b1e
PB		 17194 }
17195 }
99059e56
RM		 17196 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17197 {
17198 /* NaCl uses a special first entry in .iplt too. */
17199 osi.sec = htab->root.iplt;
17200 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17201 (output_bfd, osi.sec->output_section));
17202 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17203 return FALSE;
17204 }
34e77a92
RS		 17205 if ((htab->root.splt && htab->root.splt->size > 0)
17206 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17207 {
34e77a92
RS		 17208 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17209 for (input_bfd = info->input_bfds;
17210 input_bfd != NULL;
c72f2fb2 17211 input_bfd = input_bfd->link.next)
34e77a92
RS		 17212 {
17213 struct arm_local_iplt_info **local_iplt;
17214 unsigned int i, num_syms;
4e617b1e 17215
34e77a92
RS		 17216 local_iplt = elf32_arm_local_iplt (input_bfd);
17217 if (local_iplt != NULL)
17218 {
17219 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17220 for (i = 0; i < num_syms; i++)
17221 if (local_iplt[i] != NULL
17222 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17223 &local_iplt[i]->root,
17224 &local_iplt[i]->arm))
17225 return FALSE;
17226 }
17227 }
17228 }
0855e32b
NS		 17229 if (htab->dt_tlsdesc_plt != 0)
17230 {
17231 /* Mapping symbols for the lazy tls trampoline. */
17232 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17233 return FALSE;
b38cadfb 17234
0855e32b
NS		 17235 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17236 htab->dt_tlsdesc_plt + 24))
17237 return FALSE;
17238 }
17239 if (htab->tls_trampoline != 0)
17240 {
17241 /* Mapping symbols for the tls trampoline. */
17242 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17243 return FALSE;
17244#ifdef FOUR_WORD_PLT
17245 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17246 htab->tls_trampoline + 12))
17247 return FALSE;
b38cadfb 17248#endif
0855e32b 17249 }
b38cadfb 17250
4e617b1e
PB		 17251 return TRUE;
17252}
17253
54ddd295
TP		 17254/* Filter normal symbols of CMSE entry functions of ABFD to include in
17255 the import library. All SYMCOUNT symbols of ABFD can be examined
17256 from their pointers in SYMS. Pointers of symbols to keep should be
17257 stored continuously at the beginning of that array.
17258
17259 Returns the number of symbols to keep. */
17260
17261static unsigned int
17262elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17263 struct bfd_link_info *info,
17264 asymbol **syms, long symcount)
17265{
17266 size_t maxnamelen;
17267 char *cmse_name;
17268 long src_count, dst_count = 0;
17269 struct elf32_arm_link_hash_table *htab;
17270
17271 htab = elf32_arm_hash_table (info);
17272 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17273 symcount = 0;
17274
17275 maxnamelen = 128;
17276 cmse_name = (char *) bfd_malloc (maxnamelen);
17277 for (src_count = 0; src_count < symcount; src_count++)
17278 {
17279 struct elf32_arm_link_hash_entry *cmse_hash;
17280 asymbol *sym;
17281 flagword flags;
17282 char *name;
17283 size_t namelen;
17284
17285 sym = syms[src_count];
17286 flags = sym->flags;
17287 name = (char *) bfd_asymbol_name (sym);
17288
17289 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17290 continue;
17291 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17292 continue;
17293
17294 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17295 if (namelen > maxnamelen)
17296 {
17297 cmse_name = (char *)
17298 bfd_realloc (cmse_name, namelen);
17299 maxnamelen = namelen;
17300 }
17301 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17302 cmse_hash = (struct elf32_arm_link_hash_entry *)
17303 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17304
17305 if (!cmse_hash
17306 || (cmse_hash->root.root.type != bfd_link_hash_defined
17307 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17308 || cmse_hash->root.type != STT_FUNC)
17309 continue;
17310
17311 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17312 continue;
17313
17314 syms[dst_count++] = sym;
17315 }
17316 free (cmse_name);
17317
17318 syms[dst_count] = NULL;
17319
17320 return dst_count;
17321}
17322
17323/* Filter symbols of ABFD to include in the import library. All
17324 SYMCOUNT symbols of ABFD can be examined from their pointers in
17325 SYMS. Pointers of symbols to keep should be stored continuously at
17326 the beginning of that array.
17327
17328 Returns the number of symbols to keep. */
17329
17330static unsigned int
17331elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17332 struct bfd_link_info *info,
17333 asymbol **syms, long symcount)
17334{
17335 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17336
046734ff
TP		 17337 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
17338 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
17339 library to be a relocatable object file. */
17340 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 17341 if (globals->cmse_implib)
17342 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17343 else
17344 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17345}
17346
e489d0ae
PB		 17347/* Allocate target specific section data. */
17348
17349static bfd_boolean
17350elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17351{
f592407e
AM		 17352 if (!sec->used_by_bfd)
17353 {
17354 _arm_elf_section_data *sdata;
17355 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17356
21d799b5 17357 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17358 if (sdata == NULL)
17359 return FALSE;
17360 sec->used_by_bfd = sdata;
17361 }
e489d0ae
PB		 17362
17363 return _bfd_elf_new_section_hook (abfd, sec);
17364}
17365
17366
17367/* Used to order a list of mapping symbols by address. */
17368
17369static int
17370elf32_arm_compare_mapping (const void * a, const void * b)
17371{
7f6a71ff
JM		 17372 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17373 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17374
17375 if (amap->vma > bmap->vma)
17376 return 1;
17377 else if (amap->vma < bmap->vma)
17378 return -1;
17379 else if (amap->type > bmap->type)
17380 /* Ensure results do not depend on the host qsort for objects with
17381 multiple mapping symbols at the same address by sorting on type
17382 after vma. */
17383 return 1;
17384 else if (amap->type < bmap->type)
17385 return -1;
17386 else
17387 return 0;
e489d0ae
PB		 17388}
17389
2468f9c9
PB		 17390/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17391
17392static unsigned long
17393offset_prel31 (unsigned long addr, bfd_vma offset)
17394{
17395 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17396}
17397
17398/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17399 relocations. */
17400
17401static void
17402copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17403{
17404 unsigned long first_word = bfd_get_32 (output_bfd, from);
17405 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17406
2468f9c9
PB		 17407 /* High bit of first word is supposed to be zero. */
17408 if ((first_word & 0x80000000ul) == 0)
17409 first_word = offset_prel31 (first_word, offset);
b38cadfb 17410
2468f9c9
PB		 17411 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17412 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17413 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17414 second_word = offset_prel31 (second_word, offset);
b38cadfb 17415
2468f9c9
PB		 17416 bfd_put_32 (output_bfd, first_word, to);
17417 bfd_put_32 (output_bfd, second_word, to + 4);
17418}
e489d0ae 17419
48229727
JB		 17420/* Data for make_branch_to_a8_stub(). */
17421
b38cadfb
NC		 17422struct a8_branch_to_stub_data
17423{
48229727
JB		 17424 asection *writing_section;
17425 bfd_byte *contents;
17426};
17427
17428
17429/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17430 places for a particular section. */
17431
17432static bfd_boolean
17433make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17434 void *in_arg)
48229727
JB		 17435{
17436 struct elf32_arm_stub_hash_entry *stub_entry;
17437 struct a8_branch_to_stub_data *data;
17438 bfd_byte *contents;
17439 unsigned long branch_insn;
17440 bfd_vma veneered_insn_loc, veneer_entry_loc;
17441 bfd_signed_vma branch_offset;
17442 bfd *abfd;
8d9d9490 17443 unsigned int loc;
48229727
JB		 17444
17445 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17446 data = (struct a8_branch_to_stub_data *) in_arg;
17447
17448 if (stub_entry->target_section != data->writing_section
4563a860 17449 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17450 return TRUE;
17451
17452 contents = data->contents;
17453
8d9d9490
TP		 17454 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17455 generated when both source and target are in the same section. */
48229727
JB		 17456 veneered_insn_loc = stub_entry->target_section->output_section->vma
17457 + stub_entry->target_section->output_offset
8d9d9490 17458 + stub_entry->source_value;
48229727
JB		 17459
17460 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17461 + stub_entry->stub_sec->output_offset
17462 + stub_entry->stub_offset;
17463
17464 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17465 veneered_insn_loc &= ~3u;
17466
17467 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17468
17469 abfd = stub_entry->target_section->owner;
8d9d9490 17470 loc = stub_entry->source_value;
48229727
JB		 17471
17472 /* We attempt to avoid this condition by setting stubs_always_after_branch
17473 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17474 This check is just to be on the safe side... */
17475 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17476 {
4eca0228
AM		 17477 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub is "
17478 "allocated in unsafe location"), abfd);
48229727
JB		 17479 return FALSE;
17480 }
17481
17482 switch (stub_entry->stub_type)
17483 {
17484 case arm_stub_a8_veneer_b:
17485 case arm_stub_a8_veneer_b_cond:
17486 branch_insn = 0xf0009000;
17487 goto jump24;
17488
17489 case arm_stub_a8_veneer_blx:
17490 branch_insn = 0xf000e800;
17491 goto jump24;
17492
17493 case arm_stub_a8_veneer_bl:
17494 {
17495 unsigned int i1, j1, i2, j2, s;
17496
17497 branch_insn = 0xf000d000;
17498
17499 jump24:
17500 if (branch_offset < -16777216 || branch_offset > 16777214)
17501 {
17502 /* There's not much we can do apart from complain if this
17503 happens. */
4eca0228
AM		 17504 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub out "
17505 "of range (input file too large)"), abfd);
48229727
JB		 17506 return FALSE;
17507 }
17508
17509 /* i1 = not(j1 eor s), so:
17510 not i1 = j1 eor s
17511 j1 = (not i1) eor s. */
17512
17513 branch_insn |= (branch_offset >> 1) & 0x7ff;
17514 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17515 i2 = (branch_offset >> 22) & 1;
17516 i1 = (branch_offset >> 23) & 1;
17517 s = (branch_offset >> 24) & 1;
17518 j1 = (!i1) ^ s;
17519 j2 = (!i2) ^ s;
17520 branch_insn |= j2 << 11;
17521 branch_insn |= j1 << 13;
17522 branch_insn |= s << 26;
17523 }
17524 break;
17525
17526 default:
17527 BFD_FAIL ();
17528 return FALSE;
17529 }
17530
8d9d9490
TP		 17531 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17532 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17533
17534 return TRUE;
17535}
17536
a504d23a
LA		 17537/* Beginning of stm32l4xx work-around. */
17538
17539/* Functions encoding instructions necessary for the emission of the
17540 fix-stm32l4xx-629360.
17541 Encoding is extracted from the
17542 ARM (C) Architecture Reference Manual
17543 ARMv7-A and ARMv7-R edition
17544 ARM DDI 0406C.b (ID072512). */
17545
17546static inline bfd_vma
82188b29 17547create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17548{
17549 /* A8.8.18 B (A8-334)
17550 B target_address (Encoding T4). */
17551 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17552 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17553 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17554
a504d23a
LA		 17555 int s = ((branch_offset & 0x1000000) >> 24);
17556 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17557 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17558
17559 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17560 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17561
17562 bfd_vma patched_inst = 0xf0009000
17563 | s << 26 /* S. */
17564 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17565 | j1 << 13 /* J1. */
17566 | j2 << 11 /* J2. */
17567 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17568
17569 return patched_inst;
17570}
17571
17572static inline bfd_vma
17573create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17574{
17575 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17576 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17577 bfd_vma patched_inst = 0xe8900000
17578 | (/*W=*/wback << 21)
17579 | (base_reg << 16)
17580 | (reg_mask & 0x0000ffff);
17581
17582 return patched_inst;
17583}
17584
17585static inline bfd_vma
17586create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17587{
17588 /* A8.8.60 LDMDB/LDMEA (A8-402)
17589 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17590 bfd_vma patched_inst = 0xe9100000
17591 | (/*W=*/wback << 21)
17592 | (base_reg << 16)
17593 | (reg_mask & 0x0000ffff);
17594
17595 return patched_inst;
17596}
17597
17598static inline bfd_vma
17599create_instruction_mov (int target_reg, int source_reg)
17600{
17601 /* A8.8.103 MOV (register) (A8-486)
17602 MOV Rd, Rm (Encoding T1). */
17603 bfd_vma patched_inst = 0x4600
17604 | (target_reg & 0x7)
17605 | ((target_reg & 0x8) >> 3) << 7
17606 | (source_reg << 3);
17607
17608 return patched_inst;
17609}
17610
17611static inline bfd_vma
17612create_instruction_sub (int target_reg, int source_reg, int value)
17613{
17614 /* A8.8.221 SUB (immediate) (A8-708)
17615 SUB Rd, Rn, #value (Encoding T3). */
17616 bfd_vma patched_inst = 0xf1a00000
17617 | (target_reg << 8)
17618 | (source_reg << 16)
17619 | (/*S=*/0 << 20)
17620 | ((value & 0x800) >> 11) << 26
17621 | ((value & 0x700) >> 8) << 12
17622 | (value & 0x0ff);
17623
17624 return patched_inst;
17625}
17626
17627static inline bfd_vma
9239bbd3 17628create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17629 int first_reg)
17630{
17631 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17632 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17633 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17634 | (/*W=*/wback << 21)
17635 | (base_reg << 16)
9239bbd3
CM		 17636 | (num_words & 0x000000ff)
17637 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17638 | (first_reg & 0x00000001) << 22;
17639
17640 return patched_inst;
17641}
17642
17643static inline bfd_vma
9239bbd3
CM		 17644create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17645 int first_reg)
a504d23a
LA		 17646{
17647 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17648 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17649 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17650 | (base_reg << 16)
9239bbd3
CM		 17651 | (num_words & 0x000000ff)
17652 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17653 | (first_reg & 0x00000001) << 22;
17654
17655 return patched_inst;
17656}
17657
17658static inline bfd_vma
17659create_instruction_udf_w (int value)
17660{
17661 /* A8.8.247 UDF (A8-758)
17662 Undefined (Encoding T2). */
17663 bfd_vma patched_inst = 0xf7f0a000
17664 | (value & 0x00000fff)
17665 | (value & 0x000f0000) << 16;
17666
17667 return patched_inst;
17668}
17669
17670static inline bfd_vma
17671create_instruction_udf (int value)
17672{
17673 /* A8.8.247 UDF (A8-758)
17674 Undefined (Encoding T1). */
17675 bfd_vma patched_inst = 0xde00
17676 | (value & 0xff);
17677
17678 return patched_inst;
17679}
17680
17681/* Functions writing an instruction in memory, returning the next
17682 memory position to write to. */
17683
17684static inline bfd_byte *
17685push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17686 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17687{
17688 put_thumb2_insn (htab, output_bfd, insn, pt);
17689 return pt + 4;
17690}
17691
17692static inline bfd_byte *
17693push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17694 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17695{
17696 put_thumb_insn (htab, output_bfd, insn, pt);
17697 return pt + 2;
17698}
17699
17700/* Function filling up a region in memory with T1 and T2 UDFs taking
17701 care of alignment. */
17702
17703static bfd_byte *
17704stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17705 bfd * output_bfd,
17706 const bfd_byte * const base_stub_contents,
17707 bfd_byte * const from_stub_contents,
17708 const bfd_byte * const end_stub_contents)
17709{
17710 bfd_byte *current_stub_contents = from_stub_contents;
17711
17712 /* Fill the remaining of the stub with deterministic contents : UDF
17713 instructions.
17714 Check if realignment is needed on modulo 4 frontier using T1, to
17715 further use T2. */
17716 if ((current_stub_contents < end_stub_contents)
17717 && !((current_stub_contents - base_stub_contents) % 2)
17718 && ((current_stub_contents - base_stub_contents) % 4))
17719 current_stub_contents =
17720 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17721 create_instruction_udf (0));
17722
17723 for (; current_stub_contents < end_stub_contents;)
17724 current_stub_contents =
17725 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17726 create_instruction_udf_w (0));
17727
17728 return current_stub_contents;
17729}
17730
17731/* Functions writing the stream of instructions equivalent to the
17732 derived sequence for ldmia, ldmdb, vldm respectively. */
17733
17734static void
17735stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17736 bfd * output_bfd,
17737 const insn32 initial_insn,
17738 const bfd_byte *const initial_insn_addr,
17739 bfd_byte *const base_stub_contents)
17740{
17741 int wback = (initial_insn & 0x00200000) >> 21;
17742 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17743 int insn_all_registers = initial_insn & 0x0000ffff;
17744 int insn_low_registers, insn_high_registers;
17745 int usable_register_mask;
b25e998d 17746 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17747 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17748 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17749 bfd_byte *current_stub_contents = base_stub_contents;
17750
17751 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17752
17753 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17754 smaller than 8 registers load sequences that do not cause the
17755 hardware issue. */
17756 if (nb_registers <= 8)
17757 {
17758 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17759 current_stub_contents =
17760 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17761 initial_insn);
17762
17763 /* B initial_insn_addr+4. */
17764 if (!restore_pc)
17765 current_stub_contents =
17766 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17767 create_instruction_branch_absolute
82188b29 17768 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17769
17770 /* Fill the remaining of the stub with deterministic contents. */
17771 current_stub_contents =
17772 stm32l4xx_fill_stub_udf (htab, output_bfd,
17773 base_stub_contents, current_stub_contents,
17774 base_stub_contents +
17775 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17776
17777 return;
17778 }
17779
17780 /* - reg_list[13] == 0. */
17781 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17782
17783 /* - reg_list[14] & reg_list[15] != 1. */
17784 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17785
17786 /* - if (wback==1) reg_list[rn] == 0. */
17787 BFD_ASSERT (!wback || !restore_rn);
17788
17789 /* - nb_registers > 8. */
b25e998d 17790 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17791
17792 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17793
17794 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17795 - One with the 7 lowest registers (register mask 0x007F)
17796 This LDM will finally contain between 2 and 7 registers
17797 - One with the 7 highest registers (register mask 0xDF80)
17798 This ldm will finally contain between 2 and 7 registers. */
17799 insn_low_registers = insn_all_registers & 0x007F;
17800 insn_high_registers = insn_all_registers & 0xDF80;
17801
17802 /* A spare register may be needed during this veneer to temporarily
17803 handle the base register. This register will be restored with the
17804 last LDM operation.
17805 The usable register may be any general purpose register (that
17806 excludes PC, SP, LR : register mask is 0x1FFF). */
17807 usable_register_mask = 0x1FFF;
17808
17809 /* Generate the stub function. */
17810 if (wback)
17811 {
17812 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17813 current_stub_contents =
17814 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17815 create_instruction_ldmia
17816 (rn, /*wback=*/1, insn_low_registers));
17817
17818 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17819 current_stub_contents =
17820 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17821 create_instruction_ldmia
17822 (rn, /*wback=*/1, insn_high_registers));
17823 if (!restore_pc)
17824 {
17825 /* B initial_insn_addr+4. */
17826 current_stub_contents =
17827 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17828 create_instruction_branch_absolute
82188b29 17829 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17830 }
17831 }
17832 else /* if (!wback). */
17833 {
17834 ri = rn;
17835
17836 /* If Rn is not part of the high-register-list, move it there. */
17837 if (!(insn_high_registers & (1 << rn)))
17838 {
17839 /* Choose a Ri in the high-register-list that will be restored. */
17840 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17841
17842 /* MOV Ri, Rn. */
17843 current_stub_contents =
17844 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17845 create_instruction_mov (ri, rn));
17846 }
17847
17848 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
17849 current_stub_contents =
17850 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17851 create_instruction_ldmia
17852 (ri, /*wback=*/1, insn_low_registers));
17853
17854 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
17855 current_stub_contents =
17856 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17857 create_instruction_ldmia
17858 (ri, /*wback=*/0, insn_high_registers));
17859
17860 if (!restore_pc)
17861 {
17862 /* B initial_insn_addr+4. */
17863 current_stub_contents =
17864 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17865 create_instruction_branch_absolute
82188b29 17866 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17867 }
17868 }
17869
17870 /* Fill the remaining of the stub with deterministic contents. */
17871 current_stub_contents =
17872 stm32l4xx_fill_stub_udf (htab, output_bfd,
17873 base_stub_contents, current_stub_contents,
17874 base_stub_contents +
17875 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17876}
17877
17878static void
17879stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
17880 bfd * output_bfd,
17881 const insn32 initial_insn,
17882 const bfd_byte *const initial_insn_addr,
17883 bfd_byte *const base_stub_contents)
17884{
17885 int wback = (initial_insn & 0x00200000) >> 21;
17886 int ri, rn = (initial_insn & 0x000f0000) >> 16;
17887 int insn_all_registers = initial_insn & 0x0000ffff;
17888 int insn_low_registers, insn_high_registers;
17889 int usable_register_mask;
17890 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17891 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 17892 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17893 bfd_byte *current_stub_contents = base_stub_contents;
17894
17895 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
17896
17897 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17898 smaller than 8 registers load sequences that do not cause the
17899 hardware issue. */
17900 if (nb_registers <= 8)
17901 {
17902 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17903 current_stub_contents =
17904 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17905 initial_insn);
17906
17907 /* B initial_insn_addr+4. */
17908 current_stub_contents =
17909 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17910 create_instruction_branch_absolute
82188b29 17911 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17912
17913 /* Fill the remaining of the stub with deterministic contents. */
17914 current_stub_contents =
17915 stm32l4xx_fill_stub_udf (htab, output_bfd,
17916 base_stub_contents, current_stub_contents,
17917 base_stub_contents +
17918 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17919
17920 return;
17921 }
17922
17923 /* - reg_list[13] == 0. */
17924 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
17925
17926 /* - reg_list[14] & reg_list[15] != 1. */
17927 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17928
17929 /* - if (wback==1) reg_list[rn] == 0. */
17930 BFD_ASSERT (!wback || !restore_rn);
17931
17932 /* - nb_registers > 8. */
b25e998d 17933 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17934
17935 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17936
17937 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
17938 - One with the 7 lowest registers (register mask 0x007F)
17939 This LDM will finally contain between 2 and 7 registers
17940 - One with the 7 highest registers (register mask 0xDF80)
17941 This ldm will finally contain between 2 and 7 registers. */
17942 insn_low_registers = insn_all_registers & 0x007F;
17943 insn_high_registers = insn_all_registers & 0xDF80;
17944
17945 /* A spare register may be needed during this veneer to temporarily
17946 handle the base register. This register will be restored with
17947 the last LDM operation.
17948 The usable register may be any general purpose register (that excludes
17949 PC, SP, LR : register mask is 0x1FFF). */
17950 usable_register_mask = 0x1FFF;
17951
17952 /* Generate the stub function. */
17953 if (!wback && !restore_pc && !restore_rn)
17954 {
17955 /* Choose a Ri in the low-register-list that will be restored. */
17956 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
17957
17958 /* MOV Ri, Rn. */
17959 current_stub_contents =
17960 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17961 create_instruction_mov (ri, rn));
17962
17963 /* LDMDB Ri!, {R-high-register-list}. */
17964 current_stub_contents =
17965 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17966 create_instruction_ldmdb
17967 (ri, /*wback=*/1, insn_high_registers));
17968
17969 /* LDMDB Ri, {R-low-register-list}. */
17970 current_stub_contents =
17971 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17972 create_instruction_ldmdb
17973 (ri, /*wback=*/0, insn_low_registers));
17974
17975 /* B initial_insn_addr+4. */
17976 current_stub_contents =
17977 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17978 create_instruction_branch_absolute
82188b29 17979 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17980 }
17981 else if (wback && !restore_pc && !restore_rn)
17982 {
17983 /* LDMDB Rn!, {R-high-register-list}. */
17984 current_stub_contents =
17985 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17986 create_instruction_ldmdb
17987 (rn, /*wback=*/1, insn_high_registers));
17988
17989 /* LDMDB Rn!, {R-low-register-list}. */
17990 current_stub_contents =
17991 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17992 create_instruction_ldmdb
17993 (rn, /*wback=*/1, insn_low_registers));
17994
17995 /* B initial_insn_addr+4. */
17996 current_stub_contents =
17997 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17998 create_instruction_branch_absolute
82188b29 17999 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18000 }
18001 else if (!wback && restore_pc && !restore_rn)
18002 {
18003 /* Choose a Ri in the high-register-list that will be restored. */
18004 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18005
18006 /* SUB Ri, Rn, #(4*nb_registers). */
18007 current_stub_contents =
18008 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18009 create_instruction_sub (ri, rn, (4 * nb_registers)));
18010
18011 /* LDMIA Ri!, {R-low-register-list}. */
18012 current_stub_contents =
18013 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18014 create_instruction_ldmia
18015 (ri, /*wback=*/1, insn_low_registers));
18016
18017 /* LDMIA Ri, {R-high-register-list}. */
18018 current_stub_contents =
18019 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18020 create_instruction_ldmia
18021 (ri, /*wback=*/0, insn_high_registers));
18022 }
18023 else if (wback && restore_pc && !restore_rn)
18024 {
18025 /* Choose a Ri in the high-register-list that will be restored. */
18026 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18027
18028 /* SUB Rn, Rn, #(4*nb_registers) */
18029 current_stub_contents =
18030 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18031 create_instruction_sub (rn, rn, (4 * nb_registers)));
18032
18033 /* MOV Ri, Rn. */
18034 current_stub_contents =
18035 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18036 create_instruction_mov (ri, rn));
18037
18038 /* LDMIA Ri!, {R-low-register-list}. */
18039 current_stub_contents =
18040 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18041 create_instruction_ldmia
18042 (ri, /*wback=*/1, insn_low_registers));
18043
18044 /* LDMIA Ri, {R-high-register-list}. */
18045 current_stub_contents =
18046 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18047 create_instruction_ldmia
18048 (ri, /*wback=*/0, insn_high_registers));
18049 }
18050 else if (!wback && !restore_pc && restore_rn)
18051 {
18052 ri = rn;
18053 if (!(insn_low_registers & (1 << rn)))
18054 {
18055 /* Choose a Ri in the low-register-list that will be restored. */
18056 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18057
18058 /* MOV Ri, Rn. */
18059 current_stub_contents =
18060 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18061 create_instruction_mov (ri, rn));
18062 }
18063
18064 /* LDMDB Ri!, {R-high-register-list}. */
18065 current_stub_contents =
18066 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18067 create_instruction_ldmdb
18068 (ri, /*wback=*/1, insn_high_registers));
18069
18070 /* LDMDB Ri, {R-low-register-list}. */
18071 current_stub_contents =
18072 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18073 create_instruction_ldmdb
18074 (ri, /*wback=*/0, insn_low_registers));
18075
18076 /* B initial_insn_addr+4. */
18077 current_stub_contents =
18078 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18079 create_instruction_branch_absolute
82188b29 18080 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18081 }
18082 else if (!wback && restore_pc && restore_rn)
18083 {
18084 ri = rn;
18085 if (!(insn_high_registers & (1 << rn)))
18086 {
18087 /* Choose a Ri in the high-register-list that will be restored. */
18088 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18089 }
18090
18091 /* SUB Ri, Rn, #(4*nb_registers). */
18092 current_stub_contents =
18093 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18094 create_instruction_sub (ri, rn, (4 * nb_registers)));
18095
18096 /* LDMIA Ri!, {R-low-register-list}. */
18097 current_stub_contents =
18098 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18099 create_instruction_ldmia
18100 (ri, /*wback=*/1, insn_low_registers));
18101
18102 /* LDMIA Ri, {R-high-register-list}. */
18103 current_stub_contents =
18104 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18105 create_instruction_ldmia
18106 (ri, /*wback=*/0, insn_high_registers));
18107 }
18108 else if (wback && restore_rn)
18109 {
18110 /* The assembler should not have accepted to encode this. */
18111 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18112 "undefined behavior.\n");
18113 }
18114
18115 /* Fill the remaining of the stub with deterministic contents. */
18116 current_stub_contents =
18117 stm32l4xx_fill_stub_udf (htab, output_bfd,
18118 base_stub_contents, current_stub_contents,
18119 base_stub_contents +
18120 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18121
18122}
18123
18124static void
18125stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18126 bfd * output_bfd,
18127 const insn32 initial_insn,
18128 const bfd_byte *const initial_insn_addr,
18129 bfd_byte *const base_stub_contents)
18130{
9239bbd3 18131 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18132 bfd_byte *current_stub_contents = base_stub_contents;
18133
18134 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18135
18136 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18137 smaller than 8 words load sequences that do not cause the
a504d23a 18138 hardware issue. */
9239bbd3 18139 if (num_words <= 8)
a504d23a
LA		 18140 {
18141 /* Untouched instruction. */
18142 current_stub_contents =
18143 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18144 initial_insn);
18145
18146 /* B initial_insn_addr+4. */
18147 current_stub_contents =
18148 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18149 create_instruction_branch_absolute
82188b29 18150 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18151 }
18152 else
18153 {
9eaff861 18154 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18155 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18156 bfd_boolean is_ia_nobang = /* (IA without !). */
18157 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18158 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18159 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18160 bfd_boolean is_db_bang = /* (DB with !). */
18161 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18162 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18163 /* d = UInt (Vd:D);. */
9239bbd3 18164 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18165 | (((unsigned int)initial_insn << 9) >> 31);
18166
9239bbd3
CM		 18167 /* Compute the number of 8-words chunks needed to split. */
18168 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18169 int chunk;
18170
18171 /* The test coverage has been done assuming the following
18172 hypothesis that exactly one of the previous is_ predicates is
18173 true. */
9239bbd3
CM		 18174 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18175 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18176
9239bbd3 18177 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18178 cases, then we emit the adjustments:
18179
18180 vldm rx, {...}
18181 -> vldm rx!, {8_words_or_less} for each needed 8_word
18182 -> sub rx, rx, #size (list)
18183
18184 vldm rx!, {...}
18185 -> vldm rx!, {8_words_or_less} for each needed 8_word
18186 This also handles vpop instruction (when rx is sp)
18187
18188 vldmd rx!, {...}
18189 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18190 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18191 {
9239bbd3
CM		 18192 bfd_vma new_insn = 0;
18193
a504d23a
LA		 18194 if (is_ia_nobang || is_ia_bang)
18195 {
9239bbd3
CM		 18196 new_insn = create_instruction_vldmia
18197 (base_reg,
18198 is_dp,
18199 /*wback= . */1,
18200 chunks - (chunk + 1) ?
18201 8 : num_words - chunk * 8,
18202 first_reg + chunk * 8);
a504d23a
LA		 18203 }
18204 else if (is_db_bang)
18205 {
9239bbd3
CM		 18206 new_insn = create_instruction_vldmdb
18207 (base_reg,
18208 is_dp,
18209 chunks - (chunk + 1) ?
18210 8 : num_words - chunk * 8,
18211 first_reg + chunk * 8);
a504d23a 18212 }
9239bbd3
CM		 18213
18214 if (new_insn)
18215 current_stub_contents =
18216 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18217 new_insn);
a504d23a
LA		 18218 }
18219
18220 /* Only this case requires the base register compensation
18221 subtract. */
18222 if (is_ia_nobang)
18223 {
18224 current_stub_contents =
18225 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18226 create_instruction_sub
9239bbd3 18227 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18228 }
18229
18230 /* B initial_insn_addr+4. */
18231 current_stub_contents =
18232 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18233 create_instruction_branch_absolute
82188b29 18234 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18235 }
18236
18237 /* Fill the remaining of the stub with deterministic contents. */
18238 current_stub_contents =
18239 stm32l4xx_fill_stub_udf (htab, output_bfd,
18240 base_stub_contents, current_stub_contents,
18241 base_stub_contents +
18242 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18243}
18244
18245static void
18246stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18247 bfd * output_bfd,
18248 const insn32 wrong_insn,
18249 const bfd_byte *const wrong_insn_addr,
18250 bfd_byte *const stub_contents)
18251{
18252 if (is_thumb2_ldmia (wrong_insn))
18253 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18254 wrong_insn, wrong_insn_addr,
18255 stub_contents);
18256 else if (is_thumb2_ldmdb (wrong_insn))
18257 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18258 wrong_insn, wrong_insn_addr,
18259 stub_contents);
18260 else if (is_thumb2_vldm (wrong_insn))
18261 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18262 wrong_insn, wrong_insn_addr,
18263 stub_contents);
18264}
18265
18266/* End of stm32l4xx work-around. */
18267
18268
e489d0ae
PB		 18269/* Do code byteswapping. Return FALSE afterwards so that the section is
18270 written out as normal. */
18271
18272static bfd_boolean
c7b8f16e 18273elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18274 struct bfd_link_info *link_info,
18275 asection *sec,
e489d0ae
PB		 18276 bfd_byte *contents)
18277{
48229727 18278 unsigned int mapcount, errcount;
8e3de13a 18279 _arm_elf_section_data *arm_data;
c7b8f16e 18280 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18281 elf32_arm_section_map *map;
c7b8f16e 18282 elf32_vfp11_erratum_list *errnode;
a504d23a 18283 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18284 bfd_vma ptr;
18285 bfd_vma end;
c7b8f16e 18286 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18287 bfd_byte tmp;
48229727 18288 unsigned int i;
57e8b36a 18289
4dfe6ac6
NC		 18290 if (globals == NULL)
18291 return FALSE;
18292
8e3de13a
NC		 18293 /* If this section has not been allocated an _arm_elf_section_data
18294 structure then we cannot record anything. */
18295 arm_data = get_arm_elf_section_data (sec);
18296 if (arm_data == NULL)
18297 return FALSE;
18298
18299 mapcount = arm_data->mapcount;
18300 map = arm_data->map;
c7b8f16e
JB		 18301 errcount = arm_data->erratumcount;
18302
18303 if (errcount != 0)
18304 {
18305 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18306
18307 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18308 errnode = errnode->next)
18309 {
18310 bfd_vma target = errnode->vma - offset;
18311
18312 switch (errnode->type)
18313 {
18314 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18315 {
18316 bfd_vma branch_to_veneer;
18317 /* Original condition code of instruction, plus bit mask for
18318 ARM B instruction. */
18319 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18320 | 0x0a000000;
c7b8f16e
JB		 18321
18322 /* The instruction is before the label. */
91d6fa6a 18323 target -= 4;
c7b8f16e
JB		 18324
18325 /* Above offset included in -4 below. */
18326 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18327 - errnode->vma - 4;
c7b8f16e
JB		 18328
18329 if ((signed) branch_to_veneer < -(1 << 25)
18330 || (signed) branch_to_veneer >= (1 << 25))
4eca0228
AM		 18331 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18332 "range"), output_bfd);
c7b8f16e 18333
99059e56
RM		 18334 insn |= (branch_to_veneer >> 2) & 0xffffff;
18335 contents[endianflip ^ target] = insn & 0xff;
18336 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18337 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18338 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18339 }
18340 break;
c7b8f16e
JB		 18341
18342 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18343 {
18344 bfd_vma branch_from_veneer;
18345 unsigned int insn;
c7b8f16e 18346
99059e56
RM		 18347 /* Take size of veneer into account. */
18348 branch_from_veneer = errnode->u.v.branch->vma
18349 - errnode->vma - 12;
c7b8f16e
JB		 18350
18351 if ((signed) branch_from_veneer < -(1 << 25)
18352 || (signed) branch_from_veneer >= (1 << 25))
4eca0228
AM		 18353 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18354 "range"), output_bfd);
c7b8f16e 18355
99059e56
RM		 18356 /* Original instruction. */
18357 insn = errnode->u.v.branch->u.b.vfp_insn;
18358 contents[endianflip ^ target] = insn & 0xff;
18359 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18360 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18361 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18362
18363 /* Branch back to insn after original insn. */
18364 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18365 contents[endianflip ^ (target + 4)] = insn & 0xff;
18366 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18367 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18368 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18369 }
18370 break;
c7b8f16e 18371
99059e56
RM		 18372 default:
18373 abort ();
18374 }
18375 }
c7b8f16e 18376 }
e489d0ae 18377
a504d23a
LA		 18378 if (arm_data->stm32l4xx_erratumcount != 0)
18379 {
18380 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18381 stm32l4xx_errnode != 0;
18382 stm32l4xx_errnode = stm32l4xx_errnode->next)
18383 {
18384 bfd_vma target = stm32l4xx_errnode->vma - offset;
18385
18386 switch (stm32l4xx_errnode->type)
18387 {
18388 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18389 {
18390 unsigned int insn;
18391 bfd_vma branch_to_veneer =
18392 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18393
18394 if ((signed) branch_to_veneer < -(1 << 24)
18395 || (signed) branch_to_veneer >= (1 << 24))
18396 {
18397 bfd_vma out_of_range =
18398 ((signed) branch_to_veneer < -(1 << 24)) ?
18399 - branch_to_veneer - (1 << 24) :
18400 ((signed) branch_to_veneer >= (1 << 24)) ?
18401 branch_to_veneer - (1 << 24) : 0;
18402
4eca0228 18403 _bfd_error_handler
d42c267e
AM		 18404 (_("%B(%#Lx): error: Cannot create STM32L4XX veneer. "
18405 "Jump out of range by %Ld bytes. "
a504d23a
LA		 18406 "Cannot encode branch instruction. "),
18407 output_bfd,
d42c267e 18408 stm32l4xx_errnode->vma - 4,
a504d23a
LA		 18409 out_of_range);
18410 continue;
18411 }
18412
18413 insn = create_instruction_branch_absolute
82188b29 18414 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18415
18416 /* The instruction is before the label. */
18417 target -= 4;
18418
18419 put_thumb2_insn (globals, output_bfd,
18420 (bfd_vma) insn, contents + target);
18421 }
18422 break;
18423
18424 case STM32L4XX_ERRATUM_VENEER:
18425 {
82188b29
NC		 18426 bfd_byte * veneer;
18427 bfd_byte * veneer_r;
a504d23a
LA		 18428 unsigned int insn;
18429
82188b29
NC		 18430 veneer = contents + target;
18431 veneer_r = veneer
18432 + stm32l4xx_errnode->u.b.veneer->vma
18433 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18434
18435 if ((signed) (veneer_r - veneer -
18436 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18437 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18438 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18439 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18440 || (signed) (veneer_r - veneer) >= (1 << 24))
18441 {
4eca0228
AM		 18442 _bfd_error_handler (_("%B: error: Cannot create STM32L4XX "
18443 "veneer."), output_bfd);
a504d23a
LA		 18444 continue;
18445 }
18446
18447 /* Original instruction. */
18448 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18449
18450 stm32l4xx_create_replacing_stub
18451 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18452 }
18453 break;
18454
18455 default:
18456 abort ();
18457 }
18458 }
18459 }
18460
2468f9c9
PB		 18461 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18462 {
18463 arm_unwind_table_edit *edit_node
99059e56 18464 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18465 /* Now, sec->size is the size of the section we will write. The original
99059e56 18466 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18467 markers) was sec->rawsize. (This isn't the case if we perform no
18468 edits, then rawsize will be zero and we should use size). */
21d799b5 18469 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18470 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18471 unsigned int in_index, out_index;
18472 bfd_vma add_to_offsets = 0;
18473
18474 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18475 {
2468f9c9
PB		 18476 if (edit_node)
18477 {
18478 unsigned int edit_index = edit_node->index;
b38cadfb 18479
2468f9c9 18480 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18481 {
2468f9c9
PB		 18482 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18483 contents + in_index * 8, add_to_offsets);
18484 out_index++;
18485 in_index++;
18486 }
18487 else if (in_index == edit_index
18488 || (in_index * 8 >= input_size
18489 && edit_index == UINT_MAX))
99059e56 18490 {
2468f9c9
PB		 18491 switch (edit_node->type)
18492 {
18493 case DELETE_EXIDX_ENTRY:
18494 in_index++;
18495 add_to_offsets += 8;
18496 break;
b38cadfb 18497
2468f9c9
PB		 18498 case INSERT_EXIDX_CANTUNWIND_AT_END:
18499 {
99059e56 18500 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18501 bfd_vma text_offset = text_sec->output_section->vma
18502 + text_sec->output_offset
18503 + text_sec->size;
18504 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18505 unsigned long prel31_offset;
2468f9c9
PB		 18506
18507 /* Note: this is meant to be equivalent to an
18508 R_ARM_PREL31 relocation. These synthetic
18509 EXIDX_CANTUNWIND markers are not relocated by the
18510 usual BFD method. */
18511 prel31_offset = (text_offset - exidx_offset)
18512 & 0x7ffffffful;
491d01d3
YU		 18513 if (bfd_link_relocatable (link_info))
18514 {
18515 /* Here relocation for new EXIDX_CANTUNWIND is
18516 created, so there is no need to
18517 adjust offset by hand. */
18518 prel31_offset = text_sec->output_offset
18519 + text_sec->size;
491d01d3 18520 }
2468f9c9
PB		 18521
18522 /* First address we can't unwind. */
18523 bfd_put_32 (output_bfd, prel31_offset,
18524 &edited_contents[out_index * 8]);
18525
18526 /* Code for EXIDX_CANTUNWIND. */
18527 bfd_put_32 (output_bfd, 0x1,
18528 &edited_contents[out_index * 8 + 4]);
18529
18530 out_index++;
18531 add_to_offsets -= 8;
18532 }
18533 break;
18534 }
b38cadfb 18535
2468f9c9
PB		 18536 edit_node = edit_node->next;
18537 }
18538 }
18539 else
18540 {
18541 /* No more edits, copy remaining entries verbatim. */
18542 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18543 contents + in_index * 8, add_to_offsets);
18544 out_index++;
18545 in_index++;
18546 }
18547 }
18548
18549 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18550 bfd_set_section_contents (output_bfd, sec->output_section,
18551 edited_contents,
18552 (file_ptr) sec->output_offset, sec->size);
18553
18554 return TRUE;
18555 }
18556
48229727
JB		 18557 /* Fix code to point to Cortex-A8 erratum stubs. */
18558 if (globals->fix_cortex_a8)
18559 {
18560 struct a8_branch_to_stub_data data;
18561
18562 data.writing_section = sec;
18563 data.contents = contents;
18564
a504d23a
LA		 18565 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18566 & data);
48229727
JB		 18567 }
18568
e489d0ae
PB		 18569 if (mapcount == 0)
18570 return FALSE;
18571
c7b8f16e 18572 if (globals->byteswap_code)
e489d0ae 18573 {
c7b8f16e 18574 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18575
c7b8f16e
JB		 18576 ptr = map[0].vma;
18577 for (i = 0; i < mapcount; i++)
99059e56
RM		 18578 {
18579 if (i == mapcount - 1)
c7b8f16e 18580 end = sec->size;
99059e56
RM		 18581 else
18582 end = map[i + 1].vma;
e489d0ae 18583
99059e56 18584 switch (map[i].type)
e489d0ae 18585 {
c7b8f16e
JB		 18586 case 'a':
18587 /* Byte swap code words. */
18588 while (ptr + 3 < end)
99059e56
RM		 18589 {
18590 tmp = contents[ptr];
18591 contents[ptr] = contents[ptr + 3];
18592 contents[ptr + 3] = tmp;
18593 tmp = contents[ptr + 1];
18594 contents[ptr + 1] = contents[ptr + 2];
18595 contents[ptr + 2] = tmp;
18596 ptr += 4;
18597 }
c7b8f16e 18598 break;
e489d0ae 18599
c7b8f16e
JB		 18600 case 't':
18601 /* Byte swap code halfwords. */
18602 while (ptr + 1 < end)
99059e56
RM		 18603 {
18604 tmp = contents[ptr];
18605 contents[ptr] = contents[ptr + 1];
18606 contents[ptr + 1] = tmp;
18607 ptr += 2;
18608 }
c7b8f16e
JB		 18609 break;
18610
18611 case 'd':
18612 /* Leave data alone. */
18613 break;
18614 }
99059e56
RM		 18615 ptr = end;
18616 }
e489d0ae 18617 }
8e3de13a 18618
93204d3a 18619 free (map);
47b2e99c 18620 arm_data->mapcount = -1;
c7b8f16e 18621 arm_data->mapsize = 0;
8e3de13a 18622 arm_data->map = NULL;
8e3de13a 18623
e489d0ae
PB		 18624 return FALSE;
18625}
18626
0beaef2b
PB		 18627/* Mangle thumb function symbols as we read them in. */
18628
8384fb8f 18629static bfd_boolean
0beaef2b
PB		 18630elf32_arm_swap_symbol_in (bfd * abfd,
18631 const void *psrc,
18632 const void *pshn,
18633 Elf_Internal_Sym *dst)
18634{
4ba2ef8f
TP		 18635 Elf_Internal_Shdr *symtab_hdr;
18636 const char *name = NULL;
18637
8384fb8f
AM		 18638 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18639 return FALSE;
39d911fc 18640 dst->st_target_internal = 0;
0beaef2b
PB		 18641
18642 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18643 the address. */
63e1a0fc
PB		 18644 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18645 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18646 {
63e1a0fc
PB		 18647 if (dst->st_value & 1)
18648 {
18649 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18650 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18651 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18652 }
18653 else
39d911fc 18654 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18655 }
18656 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18657 {
18658 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18659 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18660 }
35fc36a8 18661 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18662 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18663 else
39d911fc 18664 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18665
4ba2ef8f
TP		 18666 /* Mark CMSE special symbols. */
18667 symtab_hdr = & elf_symtab_hdr (abfd);
18668 if (symtab_hdr->sh_size)
18669 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18670 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18671 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18672
8384fb8f 18673 return TRUE;
0beaef2b
PB		 18674}
18675
18676
18677/* Mangle thumb function symbols as we write them out. */
18678
18679static void
18680elf32_arm_swap_symbol_out (bfd *abfd,
18681 const Elf_Internal_Sym *src,
18682 void *cdst,
18683 void *shndx)
18684{
18685 Elf_Internal_Sym newsym;
18686
18687 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18688 of the address set, as per the new EABI. We do this unconditionally
18689 because objcopy does not set the elf header flags until after
18690 it writes out the symbol table. */
39d911fc 18691 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18692 {
18693 newsym = *src;
34e77a92
RS		 18694 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18695 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18696 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18697 {
18698 /* Do this only for defined symbols. At link type, the static
18699 linker will simulate the work of dynamic linker of resolving
18700 symbols and will carry over the thumbness of found symbols to
18701 the output symbol table. It's not clear how it happens, but
18702 the thumbness of undefined symbols can well be different at
18703 runtime, and writing '1' for them will be confusing for users
18704 and possibly for dynamic linker itself.
18705 */
18706 newsym.st_value |= 1;
18707 }
906e58ca 18708
0beaef2b
PB		 18709 src = &newsym;
18710 }
18711 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18712}
18713
b294bdf8
MM		 18714/* Add the PT_ARM_EXIDX program header. */
18715
18716static bfd_boolean
906e58ca 18717elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18718 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18719{
18720 struct elf_segment_map *m;
18721 asection *sec;
18722
18723 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18724 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18725 {
18726 /* If there is already a PT_ARM_EXIDX header, then we do not
18727 want to add another one. This situation arises when running
18728 "strip"; the input binary already has the header. */
12bd6957 18729 m = elf_seg_map (abfd);
b294bdf8
MM		 18730 while (m && m->p_type != PT_ARM_EXIDX)
18731 m = m->next;
18732 if (!m)
18733 {
21d799b5 18734 m = (struct elf_segment_map *)
99059e56 18735 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18736 if (m == NULL)
18737 return FALSE;
18738 m->p_type = PT_ARM_EXIDX;
18739 m->count = 1;
18740 m->sections[0] = sec;
18741
12bd6957
AM		 18742 m->next = elf_seg_map (abfd);
18743 elf_seg_map (abfd) = m;
b294bdf8
MM		 18744 }
18745 }
18746
18747 return TRUE;
18748}
18749
18750/* We may add a PT_ARM_EXIDX program header. */
18751
18752static int
a6b96beb
AM		 18753elf32_arm_additional_program_headers (bfd *abfd,
18754 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18755{
18756 asection *sec;
18757
18758 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18759 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18760 return 1;
18761 else
18762 return 0;
18763}
18764
34e77a92
RS		 18765/* Hook called by the linker routine which adds symbols from an object
18766 file. */
18767
18768static bfd_boolean
18769elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18770 Elf_Internal_Sym *sym, const char **namep,
18771 flagword *flagsp, asection **secp, bfd_vma *valp)
18772{
a43942db 18773 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18774 && (abfd->flags & DYNAMIC) == 0
18775 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18776 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18777
c792917c
NC		 18778 if (elf32_arm_hash_table (info) == NULL)
18779 return FALSE;
18780
34e77a92
RS		 18781 if (elf32_arm_hash_table (info)->vxworks_p
18782 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18783 flagsp, secp, valp))
18784 return FALSE;
18785
18786 return TRUE;
18787}
18788
0beaef2b 18789/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18790const struct elf_size_info elf32_arm_size_info =
18791{
0beaef2b
PB		 18792 sizeof (Elf32_External_Ehdr),
18793 sizeof (Elf32_External_Phdr),
18794 sizeof (Elf32_External_Shdr),
18795 sizeof (Elf32_External_Rel),
18796 sizeof (Elf32_External_Rela),
18797 sizeof (Elf32_External_Sym),
18798 sizeof (Elf32_External_Dyn),
18799 sizeof (Elf_External_Note),
18800 4,
18801 1,
18802 32, 2,
18803 ELFCLASS32, EV_CURRENT,
18804 bfd_elf32_write_out_phdrs,
18805 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18806 bfd_elf32_checksum_contents,
0beaef2b
PB		 18807 bfd_elf32_write_relocs,
18808 elf32_arm_swap_symbol_in,
18809 elf32_arm_swap_symbol_out,
18810 bfd_elf32_slurp_reloc_table,
18811 bfd_elf32_slurp_symbol_table,
18812 bfd_elf32_swap_dyn_in,
18813 bfd_elf32_swap_dyn_out,
18814 bfd_elf32_swap_reloc_in,
18815 bfd_elf32_swap_reloc_out,
18816 bfd_elf32_swap_reloca_in,
18817 bfd_elf32_swap_reloca_out
18818};
18819
685e70ae
VK		 18820static bfd_vma
18821read_code32 (const bfd *abfd, const bfd_byte *addr)
18822{
18823 /* V7 BE8 code is always little endian. */
18824 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18825 return bfd_getl32 (addr);
18826
18827 return bfd_get_32 (abfd, addr);
18828}
18829
18830static bfd_vma
18831read_code16 (const bfd *abfd, const bfd_byte *addr)
18832{
18833 /* V7 BE8 code is always little endian. */
18834 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18835 return bfd_getl16 (addr);
18836
18837 return bfd_get_16 (abfd, addr);
18838}
18839
6a631e86
YG		 18840/* Return size of plt0 entry starting at ADDR
18841 or (bfd_vma) -1 if size can not be determined. */
18842
18843static bfd_vma
18844elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
18845{
18846 bfd_vma first_word;
18847 bfd_vma plt0_size;
18848
685e70ae 18849 first_word = read_code32 (abfd, addr);
6a631e86
YG		 18850
18851 if (first_word == elf32_arm_plt0_entry[0])
18852 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
18853 else if (first_word == elf32_thumb2_plt0_entry[0])
18854 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
18855 else
18856 /* We don't yet handle this PLT format. */
18857 return (bfd_vma) -1;
18858
18859 return plt0_size;
18860}
18861
18862/* Return size of plt entry starting at offset OFFSET
18863 of plt section located at address START
18864 or (bfd_vma) -1 if size can not be determined. */
18865
18866static bfd_vma
18867elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
18868{
18869 bfd_vma first_insn;
18870 bfd_vma plt_size = 0;
18871 const bfd_byte *addr = start + offset;
18872
18873 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 18874 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 18875 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
18876
18877 /* Respect Thumb stub if necessary. */
685e70ae 18878 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 18879 {
18880 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
18881 }
18882
18883 /* Strip immediate from first add. */
685e70ae 18884 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 18885
18886#ifdef FOUR_WORD_PLT
18887 if (first_insn == elf32_arm_plt_entry[0])
18888 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
18889#else
18890 if (first_insn == elf32_arm_plt_entry_long[0])
18891 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
18892 else if (first_insn == elf32_arm_plt_entry_short[0])
18893 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
18894#endif
18895 else
18896 /* We don't yet handle this PLT format. */
18897 return (bfd_vma) -1;
18898
18899 return plt_size;
18900}
18901
18902/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
18903
18904static long
18905elf32_arm_get_synthetic_symtab (bfd *abfd,
18906 long symcount ATTRIBUTE_UNUSED,
18907 asymbol **syms ATTRIBUTE_UNUSED,
18908 long dynsymcount,
18909 asymbol **dynsyms,
18910 asymbol **ret)
18911{
18912 asection *relplt;
18913 asymbol *s;
18914 arelent *p;
18915 long count, i, n;
18916 size_t size;
18917 Elf_Internal_Shdr *hdr;
18918 char *names;
18919 asection *plt;
18920 bfd_vma offset;
18921 bfd_byte *data;
18922
18923 *ret = NULL;
18924
18925 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
18926 return 0;
18927
18928 if (dynsymcount <= 0)
18929 return 0;
18930
18931 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
18932 if (relplt == NULL)
18933 return 0;
18934
18935 hdr = &elf_section_data (relplt)->this_hdr;
18936 if (hdr->sh_link != elf_dynsymtab (abfd)
18937 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
18938 return 0;
18939
18940 plt = bfd_get_section_by_name (abfd, ".plt");
18941 if (plt == NULL)
18942 return 0;
18943
18944 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
18945 return -1;
18946
18947 data = plt->contents;
18948 if (data == NULL)
18949 {
18950 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
18951 return -1;
18952 bfd_cache_section_contents((asection *) plt, data);
18953 }
18954
18955 count = relplt->size / hdr->sh_entsize;
18956 size = count * sizeof (asymbol);
18957 p = relplt->relocation;
18958 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
18959 {
18960 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
18961 if (p->addend != 0)
18962 size += sizeof ("+0x") - 1 + 8;
18963 }
18964
18965 s = *ret = (asymbol *) bfd_malloc (size);
18966 if (s == NULL)
18967 return -1;
18968
18969 offset = elf32_arm_plt0_size (abfd, data);
18970 if (offset == (bfd_vma) -1)
18971 return -1;
18972
18973 names = (char *) (s + count);
18974 p = relplt->relocation;
18975 n = 0;
18976 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
18977 {
18978 size_t len;
18979
18980 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
18981 if (plt_size == (bfd_vma) -1)
18982 break;
18983
18984 *s = **p->sym_ptr_ptr;
18985 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
18986 we are defining a symbol, ensure one of them is set. */
18987 if ((s->flags & BSF_LOCAL) == 0)
18988 s->flags |= BSF_GLOBAL;
18989 s->flags |= BSF_SYNTHETIC;
18990 s->section = plt;
18991 s->value = offset;
18992 s->name = names;
18993 s->udata.p = NULL;
18994 len = strlen ((*p->sym_ptr_ptr)->name);
18995 memcpy (names, (*p->sym_ptr_ptr)->name, len);
18996 names += len;
18997 if (p->addend != 0)
18998 {
18999 char buf[30], *a;
19000
19001 memcpy (names, "+0x", sizeof ("+0x") - 1);
19002 names += sizeof ("+0x") - 1;
19003 bfd_sprintf_vma (abfd, buf, p->addend);
19004 for (a = buf; *a == '0'; ++a)
19005 ;
19006 len = strlen (a);
19007 memcpy (names, a, len);
19008 names += len;
19009 }
19010 memcpy (names, "@plt", sizeof ("@plt"));
19011 names += sizeof ("@plt");
19012 ++s, ++n;
19013 offset += plt_size;
19014 }
19015
19016 return n;
19017}
19018
ac4c9b04
MG		 19019static bfd_boolean
19020elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19021{
f0728ee3
AV		 19022 if (hdr->sh_flags & SHF_ARM_PURECODE)
19023 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19024 return TRUE;
19025}
19026
19027static flagword
19028elf32_arm_lookup_section_flags (char *flag_name)
19029{
f0728ee3
AV		 19030 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19031 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19032
19033 return SEC_NO_FLAGS;
19034}
19035
491d01d3
YU		 19036static unsigned int
19037elf32_arm_count_additional_relocs (asection *sec)
19038{
19039 struct _arm_elf_section_data *arm_data;
19040 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19041
6342be70 19042 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19043}
19044
5522f910 19045/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19046 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19047 FALSE otherwise. ISECTION is the best guess matching section from the
19048 input bfd IBFD, but it might be NULL. */
19049
19050static bfd_boolean
19051elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19052 bfd *obfd ATTRIBUTE_UNUSED,
19053 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19054 Elf_Internal_Shdr *osection)
19055{
19056 switch (osection->sh_type)
19057 {
19058 case SHT_ARM_EXIDX:
19059 {
19060 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19061 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19062 unsigned i = 0;
19063
19064 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19065 osection->sh_info = 0;
19066
19067 /* The sh_link field must be set to the text section associated with
19068 this index section. Unfortunately the ARM EHABI does not specify
19069 exactly how to determine this association. Our caller does try
19070 to match up OSECTION with its corresponding input section however
19071 so that is a good first guess. */
19072 if (isection != NULL
19073 && osection->bfd_section != NULL
19074 && isection->bfd_section != NULL
19075 && isection->bfd_section->output_section != NULL
19076 && isection->bfd_section->output_section == osection->bfd_section
19077 && iheaders != NULL
19078 && isection->sh_link > 0
19079 && isection->sh_link < elf_numsections (ibfd)
19080 && iheaders[isection->sh_link]->bfd_section != NULL
19081 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19082 )
19083 {
19084 for (i = elf_numsections (obfd); i-- > 0;)
19085 if (oheaders[i]->bfd_section
19086 == iheaders[isection->sh_link]->bfd_section->output_section)
19087 break;
19088 }
9eaff861 19089
5522f910
NC		 19090 if (i == 0)
19091 {
19092 /* Failing that we have to find a matching section ourselves. If
19093 we had the output section name available we could compare that
19094 with input section names. Unfortunately we don't. So instead
19095 we use a simple heuristic and look for the nearest executable
19096 section before this one. */
19097 for (i = elf_numsections (obfd); i-- > 0;)
19098 if (oheaders[i] == osection)
19099 break;
19100 if (i == 0)
19101 break;
19102
19103 while (i-- > 0)
19104 if (oheaders[i]->sh_type == SHT_PROGBITS
19105 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19106 == (SHF_ALLOC | SHF_EXECINSTR))
19107 break;
19108 }
19109
19110 if (i)
19111 {
19112 osection->sh_link = i;
19113 /* If the text section was part of a group
19114 then the index section should be too. */
19115 if (oheaders[i]->sh_flags & SHF_GROUP)
19116 osection->sh_flags |= SHF_GROUP;
19117 return TRUE;
19118 }
19119 }
19120 break;
19121
19122 case SHT_ARM_PREEMPTMAP:
19123 osection->sh_flags = SHF_ALLOC;
19124 break;
19125
19126 case SHT_ARM_ATTRIBUTES:
19127 case SHT_ARM_DEBUGOVERLAY:
19128 case SHT_ARM_OVERLAYSECTION:
19129 default:
19130 break;
19131 }
19132
19133 return FALSE;
19134}
19135
d691934d
NC		 19136/* Returns TRUE if NAME is an ARM mapping symbol.
19137 Traditionally the symbols $a, $d and $t have been used.
19138 The ARM ELF standard also defines $x (for A64 code). It also allows a
19139 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19140 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19141 not support them here. $t.x indicates the start of ThumbEE instructions. */
19142
19143static bfd_boolean
19144is_arm_mapping_symbol (const char * name)
19145{
19146 return name != NULL /* Paranoia. */
19147 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19148 the mapping symbols could have acquired a prefix.
19149 We do not support this here, since such symbols no
19150 longer conform to the ARM ELF ABI. */
19151 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19152 && (name[2] == 0 || name[2] == '.');
19153 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19154 any characters that follow the period are legal characters for the body
19155 of a symbol's name. For now we just assume that this is the case. */
19156}
19157
fca2a38f
NC		 19158/* Make sure that mapping symbols in object files are not removed via the
19159 "strip --strip-unneeded" tool. These symbols are needed in order to
19160 correctly generate interworking veneers, and for byte swapping code
19161 regions. Once an object file has been linked, it is safe to remove the
19162 symbols as they will no longer be needed. */
19163
19164static void
19165elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19166{
19167 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19168 && sym->section != bfd_abs_section_ptr
d691934d 19169 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19170 sym->flags |= BSF_KEEP;
19171}
19172
5522f910
NC		 19173#undef elf_backend_copy_special_section_fields
19174#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19175
252b5132 19176#define ELF_ARCH bfd_arch_arm
ae95ffa6 19177#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19178#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19179#ifdef __QNXTARGET__
19180#define ELF_MAXPAGESIZE 0x1000
19181#else
7572ca89 19182#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19183#endif
b1342370 19184#define ELF_MINPAGESIZE 0x1000
24718e3b 19185#define ELF_COMMONPAGESIZE 0x1000
252b5132 19186
ba93b8ac
DJ		 19187#define bfd_elf32_mkobject elf32_arm_mkobject
19188
99e4ae17
AJ		 19189#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19190#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19191#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19192#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
19193#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19194#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19195#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 19196#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 19197#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19198#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19199#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19200#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 19201#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 19202
19203#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19204#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19205#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132 19206#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19207#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19208#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19209#define elf_backend_write_section elf32_arm_write_section
252b5132 19210#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 19211#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19212#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19213#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19214#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19215#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19216#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19217#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19218#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19219#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 19220#define elf_backend_fake_sections elf32_arm_fake_sections
19221#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 19222#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 19223#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19224#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19225#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 19226#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19227#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19228#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
906e58ca 19229#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19230#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19231#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19232#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19233
19234#define elf_backend_can_refcount 1
19235#define elf_backend_can_gc_sections 1
19236#define elf_backend_plt_readonly 1
19237#define elf_backend_want_got_plt 1
19238#define elf_backend_want_plt_sym 0
5474d94f 19239#define elf_backend_want_dynrelro 1
906e58ca
NC		 19240#define elf_backend_may_use_rel_p 1
19241#define elf_backend_may_use_rela_p 0
4e7fd91e 19242#define elf_backend_default_use_rela_p 0
64f52338 19243#define elf_backend_dtrel_excludes_plt 1
252b5132 19244
04f7c78d 19245#define elf_backend_got_header_size 12
b68a20d6 19246#define elf_backend_extern_protected_data 1
04f7c78d 19247
906e58ca
NC		 19248#undef elf_backend_obj_attrs_vendor
19249#define elf_backend_obj_attrs_vendor "aeabi"
19250#undef elf_backend_obj_attrs_section
19251#define elf_backend_obj_attrs_section ".ARM.attributes"
19252#undef elf_backend_obj_attrs_arg_type
19253#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
19254#undef elf_backend_obj_attrs_section_type
104d59d1 19255#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 19256#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
19257#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19258
5025eb7c 19259#undef elf_backend_section_flags
ac4c9b04 19260#define elf_backend_section_flags elf32_arm_section_flags
5025eb7c 19261#undef elf_backend_lookup_section_flags_hook
ac4c9b04
MG		 19262#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
19263
a2f63b2e
MR		 19264#define elf_backend_linux_prpsinfo32_ugid16 TRUE
19265
252b5132 19266#include "elf32-target.h"
7f266840 19267
b38cadfb
NC		 19268/* Native Client targets. */
19269
19270#undef TARGET_LITTLE_SYM
6d00b590 19271#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19272#undef TARGET_LITTLE_NAME
19273#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19274#undef TARGET_BIG_SYM
6d00b590 19275#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19276#undef TARGET_BIG_NAME
19277#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19278
19279/* Like elf32_arm_link_hash_table_create -- but overrides
19280 appropriately for NaCl. */
19281
19282static struct bfd_link_hash_table *
19283elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19284{
19285 struct bfd_link_hash_table *ret;
19286
19287 ret = elf32_arm_link_hash_table_create (abfd);
19288 if (ret)
19289 {
19290 struct elf32_arm_link_hash_table *htab
19291 = (struct elf32_arm_link_hash_table *) ret;
19292
19293 htab->nacl_p = 1;
19294
19295 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19296 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19297 }
19298 return ret;
19299}
19300
19301/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19302 really need to use elf32_arm_modify_segment_map. But we do it
19303 anyway just to reduce gratuitous differences with the stock ARM backend. */
19304
19305static bfd_boolean
19306elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19307{
19308 return (elf32_arm_modify_segment_map (abfd, info)
19309 && nacl_modify_segment_map (abfd, info));
19310}
19311
887badb3
RM		 19312static void
19313elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19314{
19315 elf32_arm_final_write_processing (abfd, linker);
19316 nacl_final_write_processing (abfd, linker);
19317}
19318
6a631e86
YG		 19319static bfd_vma
19320elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19321 const arelent *rel ATTRIBUTE_UNUSED)
19322{
19323 return plt->vma
19324 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19325 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19326}
887badb3 19327
b38cadfb 19328#undef elf32_bed
6a631e86 19329#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19330#undef bfd_elf32_bfd_link_hash_table_create
19331#define bfd_elf32_bfd_link_hash_table_create \
19332 elf32_arm_nacl_link_hash_table_create
19333#undef elf_backend_plt_alignment
6a631e86 19334#define elf_backend_plt_alignment 4
b38cadfb
NC		 19335#undef elf_backend_modify_segment_map
19336#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19337#undef elf_backend_modify_program_headers
19338#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19339#undef elf_backend_final_write_processing
19340#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19341#undef bfd_elf32_get_synthetic_symtab
19342#undef elf_backend_plt_sym_val
19343#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19344#undef elf_backend_copy_special_section_fields
b38cadfb 19345
887badb3
RM		 19346#undef ELF_MINPAGESIZE
19347#undef ELF_COMMONPAGESIZE
19348
b38cadfb
NC		 19349
19350#include "elf32-target.h"
19351
19352/* Reset to defaults. */
19353#undef elf_backend_plt_alignment
19354#undef elf_backend_modify_segment_map
19355#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19356#undef elf_backend_modify_program_headers
887badb3
RM		 19357#undef elf_backend_final_write_processing
19358#define elf_backend_final_write_processing elf32_arm_final_write_processing
19359#undef ELF_MINPAGESIZE
19360#define ELF_MINPAGESIZE 0x1000
19361#undef ELF_COMMONPAGESIZE
19362#define ELF_COMMONPAGESIZE 0x1000
19363
b38cadfb 19364
906e58ca 19365/* VxWorks Targets. */
4e7fd91e 19366
906e58ca 19367#undef TARGET_LITTLE_SYM
6d00b590 19368#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 19369#undef TARGET_LITTLE_NAME
4e7fd91e 19370#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 19371#undef TARGET_BIG_SYM
6d00b590 19372#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 19373#undef TARGET_BIG_NAME
4e7fd91e
PB		 19374#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
19375
19376/* Like elf32_arm_link_hash_table_create -- but overrides
19377 appropriately for VxWorks. */
906e58ca 19378
4e7fd91e
PB		 19379static struct bfd_link_hash_table *
19380elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19381{
19382 struct bfd_link_hash_table *ret;
19383
19384 ret = elf32_arm_link_hash_table_create (abfd);
19385 if (ret)
19386 {
19387 struct elf32_arm_link_hash_table *htab
00a97672 19388 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19389 htab->use_rel = 0;
00a97672 19390 htab->vxworks_p = 1;
4e7fd91e
PB		 19391 }
19392 return ret;
906e58ca 19393}
4e7fd91e 19394
00a97672
RS		 19395static void
19396elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19397{
19398 elf32_arm_final_write_processing (abfd, linker);
19399 elf_vxworks_final_write_processing (abfd, linker);
19400}
19401
906e58ca 19402#undef elf32_bed
4e7fd91e
PB		 19403#define elf32_bed elf32_arm_vxworks_bed
19404
906e58ca
NC		 19405#undef bfd_elf32_bfd_link_hash_table_create
19406#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19407#undef elf_backend_final_write_processing
19408#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19409#undef elf_backend_emit_relocs
9eaff861 19410#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19411
906e58ca 19412#undef elf_backend_may_use_rel_p
00a97672 19413#define elf_backend_may_use_rel_p 0
906e58ca 19414#undef elf_backend_may_use_rela_p
00a97672 19415#define elf_backend_may_use_rela_p 1
906e58ca 19416#undef elf_backend_default_use_rela_p
00a97672 19417#define elf_backend_default_use_rela_p 1
906e58ca 19418#undef elf_backend_want_plt_sym
00a97672 19419#define elf_backend_want_plt_sym 1
906e58ca 19420#undef ELF_MAXPAGESIZE
00a97672 19421#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19422
19423#include "elf32-target.h"
19424
19425
21d799b5
NC		 19426/* Merge backend specific data from an object file to the output
19427 object file when linking. */
19428
19429static bfd_boolean
50e03d47 19430elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 19431{
50e03d47 19432 bfd *obfd = info->output_bfd;
21d799b5
NC		 19433 flagword out_flags;
19434 flagword in_flags;
19435 bfd_boolean flags_compatible = TRUE;
19436 asection *sec;
19437
cc643b88 19438 /* Check if we have the same endianness. */
50e03d47 19439 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 19440 return FALSE;
19441
19442 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19443 return TRUE;
19444
50e03d47 19445 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 19446 return FALSE;
19447
19448 /* The input BFD must have had its flags initialised. */
19449 /* The following seems bogus to me -- The flags are initialized in
19450 the assembler but I don't think an elf_flags_init field is
19451 written into the object. */
19452 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19453
19454 in_flags = elf_elfheader (ibfd)->e_flags;
19455 out_flags = elf_elfheader (obfd)->e_flags;
19456
19457 /* In theory there is no reason why we couldn't handle this. However
19458 in practice it isn't even close to working and there is no real
19459 reason to want it. */
19460 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19461 && !(ibfd->flags & DYNAMIC)
19462 && (in_flags & EF_ARM_BE8))
19463 {
19464 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19465 ibfd);
19466 return FALSE;
19467 }
19468
19469 if (!elf_flags_init (obfd))
19470 {
19471 /* If the input is the default architecture and had the default
19472 flags then do not bother setting the flags for the output
19473 architecture, instead allow future merges to do this. If no
19474 future merges ever set these flags then they will retain their
99059e56
RM		 19475 uninitialised values, which surprise surprise, correspond
19476 to the default values. */
21d799b5
NC		 19477 if (bfd_get_arch_info (ibfd)->the_default
19478 && elf_elfheader (ibfd)->e_flags == 0)
19479 return TRUE;
19480
19481 elf_flags_init (obfd) = TRUE;
19482 elf_elfheader (obfd)->e_flags = in_flags;
19483
19484 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19485 && bfd_get_arch_info (obfd)->the_default)
19486 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19487
19488 return TRUE;
19489 }
19490
19491 /* Determine what should happen if the input ARM architecture
19492 does not match the output ARM architecture. */
19493 if (! bfd_arm_merge_machines (ibfd, obfd))
19494 return FALSE;
19495
19496 /* Identical flags must be compatible. */
19497 if (in_flags == out_flags)
19498 return TRUE;
19499
19500 /* Check to see if the input BFD actually contains any sections. If
19501 not, its flags may not have been initialised either, but it
19502 cannot actually cause any incompatiblity. Do not short-circuit
19503 dynamic objects; their section list may be emptied by
19504 elf_link_add_object_symbols.
19505
19506 Also check to see if there are no code sections in the input.
19507 In this case there is no need to check for code specific flags.
19508 XXX - do we need to worry about floating-point format compatability
19509 in data sections ? */
19510 if (!(ibfd->flags & DYNAMIC))
19511 {
19512 bfd_boolean null_input_bfd = TRUE;
19513 bfd_boolean only_data_sections = TRUE;
19514
19515 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19516 {
19517 /* Ignore synthetic glue sections. */
19518 if (strcmp (sec->name, ".glue_7")
19519 && strcmp (sec->name, ".glue_7t"))
19520 {
19521 if ((bfd_get_section_flags (ibfd, sec)
19522 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19523 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19524 only_data_sections = FALSE;
21d799b5
NC		 19525
19526 null_input_bfd = FALSE;
19527 break;
19528 }
19529 }
19530
19531 if (null_input_bfd || only_data_sections)
19532 return TRUE;
19533 }
19534
19535 /* Complain about various flag mismatches. */
19536 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19537 EF_ARM_EABI_VERSION (out_flags)))
19538 {
19539 _bfd_error_handler
19540 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
c08bb8dd
AM		 19541 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
19542 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 19543 return FALSE;
19544 }
19545
19546 /* Not sure what needs to be checked for EABI versions >= 1. */
19547 /* VxWorks libraries do not use these flags. */
19548 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19549 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19550 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19551 {
19552 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19553 {
19554 _bfd_error_handler
19555 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
c08bb8dd
AM		 19556 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
19557 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 19558 flags_compatible = FALSE;
19559 }
19560
19561 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19562 {
19563 if (in_flags & EF_ARM_APCS_FLOAT)
19564 _bfd_error_handler
19565 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19566 ibfd, obfd);
19567 else
19568 _bfd_error_handler
19569 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19570 ibfd, obfd);
19571
19572 flags_compatible = FALSE;
19573 }
19574
19575 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19576 {
19577 if (in_flags & EF_ARM_VFP_FLOAT)
19578 _bfd_error_handler
19579 (_("error: %B uses VFP instructions, whereas %B does not"),
19580 ibfd, obfd);
19581 else
19582 _bfd_error_handler
19583 (_("error: %B uses FPA instructions, whereas %B does not"),
19584 ibfd, obfd);
19585
19586 flags_compatible = FALSE;
19587 }
19588
19589 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19590 {
19591 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19592 _bfd_error_handler
19593 (_("error: %B uses Maverick instructions, whereas %B does not"),
19594 ibfd, obfd);
19595 else
19596 _bfd_error_handler
19597 (_("error: %B does not use Maverick instructions, whereas %B does"),
19598 ibfd, obfd);
19599
19600 flags_compatible = FALSE;
19601 }
19602
19603#ifdef EF_ARM_SOFT_FLOAT
19604 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19605 {
19606 /* We can allow interworking between code that is VFP format
19607 layout, and uses either soft float or integer regs for
19608 passing floating point arguments and results. We already
19609 know that the APCS_FLOAT flags match; similarly for VFP
19610 flags. */
19611 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19612 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19613 {
19614 if (in_flags & EF_ARM_SOFT_FLOAT)
19615 _bfd_error_handler
19616 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19617 ibfd, obfd);
19618 else
19619 _bfd_error_handler
19620 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19621 ibfd, obfd);
19622
19623 flags_compatible = FALSE;
19624 }
19625 }
19626#endif
19627
19628 /* Interworking mismatch is only a warning. */
19629 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19630 {
19631 if (in_flags & EF_ARM_INTERWORK)
19632 {
19633 _bfd_error_handler
19634 (_("Warning: %B supports interworking, whereas %B does not"),
19635 ibfd, obfd);
19636 }
19637 else
19638 {
19639 _bfd_error_handler
19640 (_("Warning: %B does not support interworking, whereas %B does"),
19641 ibfd, obfd);
19642 }
19643 }
19644 }
19645
19646 return flags_compatible;
19647}
19648
19649
906e58ca 19650/* Symbian OS Targets. */
7f266840 19651
906e58ca 19652#undef TARGET_LITTLE_SYM
6d00b590 19653#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19654#undef TARGET_LITTLE_NAME
7f266840 19655#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19656#undef TARGET_BIG_SYM
6d00b590 19657#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19658#undef TARGET_BIG_NAME
7f266840
DJ		 19659#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19660
19661/* Like elf32_arm_link_hash_table_create -- but overrides
19662 appropriately for Symbian OS. */
906e58ca 19663
7f266840
DJ		 19664static struct bfd_link_hash_table *
19665elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19666{
19667 struct bfd_link_hash_table *ret;
19668
19669 ret = elf32_arm_link_hash_table_create (abfd);
19670 if (ret)
19671 {
19672 struct elf32_arm_link_hash_table *htab
19673 = (struct elf32_arm_link_hash_table *)ret;
19674 /* There is no PLT header for Symbian OS. */
19675 htab->plt_header_size = 0;
95720a86
DJ		 19676 /* The PLT entries are each one instruction and one word. */
19677 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19678 htab->symbian_p = 1;
33bfe774
JB		 19679 /* Symbian uses armv5t or above, so use_blx is always true. */
19680 htab->use_blx = 1;
67687978 19681 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19682 }
19683 return ret;
906e58ca 19684}
7f266840 19685
b35d266b 19686static const struct bfd_elf_special_section
551b43fd 19687elf32_arm_symbian_special_sections[] =
7f266840 19688{
5cd3778d
MM		 19689 /* In a BPABI executable, the dynamic linking sections do not go in
19690 the loadable read-only segment. The post-linker may wish to
19691 refer to these sections, but they are not part of the final
19692 program image. */
0112cd26
NC		 19693 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19694 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19695 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19696 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19697 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19698 /* These sections do not need to be writable as the SymbianOS
19699 postlinker will arrange things so that no dynamic relocation is
19700 required. */
0112cd26
NC		 19701 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19702 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19703 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19704 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19705};
19706
c3c76620 19707static void
906e58ca 19708elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19709 struct bfd_link_info *link_info)
c3c76620
MM		 19710{
19711 /* BPABI objects are never loaded directly by an OS kernel; they are
19712 processed by a postlinker first, into an OS-specific format. If
19713 the D_PAGED bit is set on the file, BFD will align segments on
19714 page boundaries, so that an OS can directly map the file. With
19715 BPABI objects, that just results in wasted space. In addition,
19716 because we clear the D_PAGED bit, map_sections_to_segments will
19717 recognize that the program headers should not be mapped into any
19718 loadable segment. */
19719 abfd->flags &= ~D_PAGED;
906e58ca 19720 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19721}
7f266840
DJ		 19722
19723static bfd_boolean
906e58ca 19724elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19725 struct bfd_link_info *info)
7f266840
DJ		 19726{
19727 struct elf_segment_map *m;
19728 asection *dynsec;
19729
7f266840
DJ		 19730 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19731 segment. However, because the .dynamic section is not marked
19732 with SEC_LOAD, the generic ELF code will not create such a
19733 segment. */
19734 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19735 if (dynsec)
19736 {
12bd6957 19737 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19738 if (m->p_type == PT_DYNAMIC)
19739 break;
19740
19741 if (m == NULL)
19742 {
19743 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19744 m->next = elf_seg_map (abfd);
19745 elf_seg_map (abfd) = m;
8ded5a0f 19746 }
7f266840
DJ		 19747 }
19748
b294bdf8
MM		 19749 /* Also call the generic arm routine. */
19750 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19751}
19752
95720a86
DJ		 19753/* Return address for Ith PLT stub in section PLT, for relocation REL
19754 or (bfd_vma) -1 if it should not be included. */
19755
19756static bfd_vma
19757elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19758 const arelent *rel ATTRIBUTE_UNUSED)
19759{
19760 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19761}
19762
8029a119 19763#undef elf32_bed
7f266840
DJ		 19764#define elf32_bed elf32_arm_symbian_bed
19765
19766/* The dynamic sections are not allocated on SymbianOS; the postlinker
19767 will process them and then discard them. */
906e58ca 19768#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19769#define ELF_DYNAMIC_SEC_FLAGS \
19770 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19771
9eaff861 19772#undef elf_backend_emit_relocs
c3c76620 19773
906e58ca
NC		 19774#undef bfd_elf32_bfd_link_hash_table_create
19775#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19776#undef elf_backend_special_sections
19777#define elf_backend_special_sections elf32_arm_symbian_special_sections
19778#undef elf_backend_begin_write_processing
19779#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19780#undef elf_backend_final_write_processing
19781#define elf_backend_final_write_processing elf32_arm_final_write_processing
19782
19783#undef elf_backend_modify_segment_map
7f266840
DJ		 19784#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19785
19786/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19787#undef elf_backend_got_header_size
7f266840
DJ		 19788#define elf_backend_got_header_size 0
19789
19790/* Similarly, there is no .got.plt section. */
906e58ca 19791#undef elf_backend_want_got_plt
7f266840
DJ		 19792#define elf_backend_want_got_plt 0
19793
906e58ca 19794#undef elf_backend_plt_sym_val
95720a86
DJ		 19795#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19796
906e58ca 19797#undef elf_backend_may_use_rel_p
00a97672 19798#define elf_backend_may_use_rel_p 1
906e58ca 19799#undef elf_backend_may_use_rela_p
00a97672 19800#define elf_backend_may_use_rela_p 0
906e58ca 19801#undef elf_backend_default_use_rela_p
00a97672 19802#define elf_backend_default_use_rela_p 0
906e58ca 19803#undef elf_backend_want_plt_sym
00a97672 19804#define elf_backend_want_plt_sym 0
64f52338
AM		 19805#undef elf_backend_dtrel_excludes_plt
19806#define elf_backend_dtrel_excludes_plt 0
906e58ca 19807#undef ELF_MAXPAGESIZE
00a97672 19808#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19809
7f266840 19810#include "elf32-target.h"
GDB Binutils - Deliverables
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