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2016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
0855e32b
NS		 3147 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3148 bfd_vma next_tls_desc_index;
3149
3150 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3151 bfd_vma num_tls_desc;
3152
906e58ca 3153 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3154 asection *sdynbss;
3155 asection *srelbss;
5e681ec4 3156
906e58ca
NC		 3157 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3158 asection *srelplt2;
00a97672 3159
0855e32b
NS		 3160 /* The offset into splt of the PLT entry for the TLS descriptor
3161 resolver. Special values are 0, if not necessary (or not found
3162 to be necessary yet), and -1 if needed but not determined
3163 yet. */
3164 bfd_vma dt_tlsdesc_plt;
3165
3166 /* The offset into sgot of the GOT entry used by the PLT entry
3167 above. */
b38cadfb 3168 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3169
3170 /* Offset in .plt section of tls_arm_trampoline. */
3171 bfd_vma tls_trampoline;
3172
906e58ca
NC		 3173 /* Data for R_ARM_TLS_LDM32 relocations. */
3174 union
3175 {
3176 bfd_signed_vma refcount;
3177 bfd_vma offset;
3178 } tls_ldm_got;
b7693d02 3179
87d72d41
AM		 3180 /* Small local sym cache. */
3181 struct sym_cache sym_cache;
906e58ca
NC		 3182
3183 /* For convenience in allocate_dynrelocs. */
3184 bfd * obfd;
3185
0855e32b
NS		 3186 /* The amount of space used by the reserved portion of the sgotplt
3187 section, plus whatever space is used by the jump slots. */
3188 bfd_vma sgotplt_jump_table_size;
3189
906e58ca
NC		 3190 /* The stub hash table. */
3191 struct bfd_hash_table stub_hash_table;
3192
3193 /* Linker stub bfd. */
3194 bfd *stub_bfd;
3195
3196 /* Linker call-backs. */
6bde4c52
TP		 3197 asection * (*add_stub_section) (const char *, asection *, asection *,
3198 unsigned int);
906e58ca
NC		 3199 void (*layout_sections_again) (void);
3200
3201 /* Array to keep track of which stub sections have been created, and
3202 information on stub grouping. */
21d799b5 3203 struct map_stub *stub_group;
906e58ca 3204
4ba2ef8f
TP		 3205 /* Input stub section holding secure gateway veneers. */
3206 asection *cmse_stub_sec;
3207
fe33d2fa 3208 /* Number of elements in stub_group. */
7292b3ac 3209 unsigned int top_id;
fe33d2fa 3210
906e58ca
NC		 3211 /* Assorted information used by elf32_arm_size_stubs. */
3212 unsigned int bfd_count;
7292b3ac 3213 unsigned int top_index;
906e58ca
NC		 3214 asection **input_list;
3215};
252b5132 3216
a504d23a
LA		 3217static inline int
3218ctz (unsigned int mask)
3219{
3220#if GCC_VERSION >= 3004
3221 return __builtin_ctz (mask);
3222#else
3223 unsigned int i;
3224
3225 for (i = 0; i < 8 * sizeof (mask); i++)
3226 {
3227 if (mask & 0x1)
3228 break;
3229 mask = (mask >> 1);
3230 }
3231 return i;
3232#endif
3233}
3234
3235static inline int
3236popcount (unsigned int mask)
3237{
3238#if GCC_VERSION >= 3004
3239 return __builtin_popcount (mask);
3240#else
3241 unsigned int i, sum = 0;
3242
3243 for (i = 0; i < 8 * sizeof (mask); i++)
3244 {
3245 if (mask & 0x1)
3246 sum++;
3247 mask = (mask >> 1);
3248 }
3249 return sum;
3250#endif
3251}
3252
780a67af
NC		 3253/* Create an entry in an ARM ELF linker hash table. */
3254
3255static struct bfd_hash_entry *
57e8b36a 3256elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3257 struct bfd_hash_table * table,
3258 const char * string)
780a67af
NC		 3259{
3260 struct elf32_arm_link_hash_entry * ret =
3261 (struct elf32_arm_link_hash_entry *) entry;
3262
3263 /* Allocate the structure if it has not already been allocated by a
3264 subclass. */
906e58ca 3265 if (ret == NULL)
21d799b5 3266 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3267 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3268 if (ret == NULL)
780a67af
NC		 3269 return (struct bfd_hash_entry *) ret;
3270
3271 /* Call the allocation method of the superclass. */
3272 ret = ((struct elf32_arm_link_hash_entry *)
3273 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3274 table, string));
57e8b36a 3275 if (ret != NULL)
b7693d02 3276 {
0bdcacaf 3277 ret->dyn_relocs = NULL;
ba93b8ac 3278 ret->tls_type = GOT_UNKNOWN;
0855e32b 3279 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3280 ret->plt.thumb_refcount = 0;
3281 ret->plt.maybe_thumb_refcount = 0;
3282 ret->plt.noncall_refcount = 0;
3283 ret->plt.got_offset = -1;
3284 ret->is_iplt = FALSE;
a4fd1a8e 3285 ret->export_glue = NULL;
906e58ca
NC		 3286
3287 ret->stub_cache = NULL;
b7693d02 3288 }
780a67af
NC		 3289
3290 return (struct bfd_hash_entry *) ret;
3291}
3292
34e77a92
RS		 3293/* Ensure that we have allocated bookkeeping structures for ABFD's local
3294 symbols. */
3295
3296static bfd_boolean
3297elf32_arm_allocate_local_sym_info (bfd *abfd)
3298{
3299 if (elf_local_got_refcounts (abfd) == NULL)
3300 {
3301 bfd_size_type num_syms;
3302 bfd_size_type size;
3303 char *data;
3304
3305 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3306 size = num_syms * (sizeof (bfd_signed_vma)
3307 + sizeof (struct arm_local_iplt_info *)
3308 + sizeof (bfd_vma)
3309 + sizeof (char));
3310 data = bfd_zalloc (abfd, size);
3311 if (data == NULL)
3312 return FALSE;
3313
3314 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3315 data += num_syms * sizeof (bfd_signed_vma);
3316
3317 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3318 data += num_syms * sizeof (struct arm_local_iplt_info *);
3319
3320 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3321 data += num_syms * sizeof (bfd_vma);
3322
3323 elf32_arm_local_got_tls_type (abfd) = data;
3324 }
3325 return TRUE;
3326}
3327
3328/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3329 to input bfd ABFD. Create the information if it doesn't already exist.
3330 Return null if an allocation fails. */
3331
3332static struct arm_local_iplt_info *
3333elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3334{
3335 struct arm_local_iplt_info **ptr;
3336
3337 if (!elf32_arm_allocate_local_sym_info (abfd))
3338 return NULL;
3339
3340 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3341 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3342 if (*ptr == NULL)
3343 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3344 return *ptr;
3345}
3346
3347/* Try to obtain PLT information for the symbol with index R_SYMNDX
3348 in ABFD's symbol table. If the symbol is global, H points to its
3349 hash table entry, otherwise H is null.
3350
3351 Return true if the symbol does have PLT information. When returning
3352 true, point *ROOT_PLT at the target-independent reference count/offset
3353 union and *ARM_PLT at the ARM-specific information. */
3354
3355static bfd_boolean
4ba2ef8f
TP		 3356elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3357 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3358 unsigned long r_symndx, union gotplt_union **root_plt,
3359 struct arm_plt_info **arm_plt)
3360{
3361 struct arm_local_iplt_info *local_iplt;
3362
4ba2ef8f
TP		 3363 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3364 return FALSE;
3365
34e77a92
RS		 3366 if (h != NULL)
3367 {
3368 *root_plt = &h->root.plt;
3369 *arm_plt = &h->plt;
3370 return TRUE;
3371 }
3372
3373 if (elf32_arm_local_iplt (abfd) == NULL)
3374 return FALSE;
3375
3376 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3377 if (local_iplt == NULL)
3378 return FALSE;
3379
3380 *root_plt = &local_iplt->root;
3381 *arm_plt = &local_iplt->arm;
3382 return TRUE;
3383}
3384
3385/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3386 before it. */
3387
3388static bfd_boolean
3389elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3390 struct arm_plt_info *arm_plt)
3391{
3392 struct elf32_arm_link_hash_table *htab;
3393
3394 htab = elf32_arm_hash_table (info);
3395 return (arm_plt->thumb_refcount != 0
3396 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3397}
3398
3399/* Return a pointer to the head of the dynamic reloc list that should
3400 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3401 ABFD's symbol table. Return null if an error occurs. */
3402
3403static struct elf_dyn_relocs **
3404elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3405 Elf_Internal_Sym *isym)
3406{
3407 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3408 {
3409 struct arm_local_iplt_info *local_iplt;
3410
3411 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3412 if (local_iplt == NULL)
3413 return NULL;
3414 return &local_iplt->dyn_relocs;
3415 }
3416 else
3417 {
3418 /* Track dynamic relocs needed for local syms too.
3419 We really need local syms available to do this
3420 easily. Oh well. */
3421 asection *s;
3422 void *vpp;
3423
3424 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3425 if (s == NULL)
3426 abort ();
3427
3428 vpp = &elf_section_data (s)->local_dynrel;
3429 return (struct elf_dyn_relocs **) vpp;
3430 }
3431}
3432
906e58ca
NC		 3433/* Initialize an entry in the stub hash table. */
3434
3435static struct bfd_hash_entry *
3436stub_hash_newfunc (struct bfd_hash_entry *entry,
3437 struct bfd_hash_table *table,
3438 const char *string)
3439{
3440 /* Allocate the structure if it has not already been allocated by a
3441 subclass. */
3442 if (entry == NULL)
3443 {
21d799b5 3444 entry = (struct bfd_hash_entry *)
99059e56 3445 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3446 if (entry == NULL)
3447 return entry;
3448 }
3449
3450 /* Call the allocation method of the superclass. */
3451 entry = bfd_hash_newfunc (entry, table, string);
3452 if (entry != NULL)
3453 {
3454 struct elf32_arm_stub_hash_entry *eh;
3455
3456 /* Initialize the local fields. */
3457 eh = (struct elf32_arm_stub_hash_entry *) entry;
3458 eh->stub_sec = NULL;
3459 eh->stub_offset = 0;
8d9d9490 3460 eh->source_value = 0;
906e58ca
NC		 3461 eh->target_value = 0;
3462 eh->target_section = NULL;
cedfb179 3463 eh->orig_insn = 0;
906e58ca 3464 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3465 eh->stub_size = 0;
3466 eh->stub_template = NULL;
3467 eh->stub_template_size = 0;
906e58ca
NC		 3468 eh->h = NULL;
3469 eh->id_sec = NULL;
d8d2f433 3470 eh->output_name = NULL;
906e58ca
NC		 3471 }
3472
3473 return entry;
3474}
3475
00a97672 3476/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3477 shortcuts to them in our hash table. */
3478
3479static bfd_boolean
57e8b36a 3480create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3481{
3482 struct elf32_arm_link_hash_table *htab;
3483
e5a52504 3484 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3485 if (htab == NULL)
3486 return FALSE;
3487
e5a52504
MM		 3488 /* BPABI objects never have a GOT, or associated sections. */
3489 if (htab->symbian_p)
3490 return TRUE;
3491
5e681ec4
PB		 3492 if (! _bfd_elf_create_got_section (dynobj, info))
3493 return FALSE;
3494
5e681ec4
PB		 3495 return TRUE;
3496}
3497
34e77a92
RS		 3498/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3499
3500static bfd_boolean
3501create_ifunc_sections (struct bfd_link_info *info)
3502{
3503 struct elf32_arm_link_hash_table *htab;
3504 const struct elf_backend_data *bed;
3505 bfd *dynobj;
3506 asection *s;
3507 flagword flags;
b38cadfb 3508
34e77a92
RS		 3509 htab = elf32_arm_hash_table (info);
3510 dynobj = htab->root.dynobj;
3511 bed = get_elf_backend_data (dynobj);
3512 flags = bed->dynamic_sec_flags;
3513
3514 if (htab->root.iplt == NULL)
3515 {
3d4d4302
AM		 3516 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3517 flags | SEC_READONLY | SEC_CODE);
34e77a92 3518 if (s == NULL
a0f49396 3519 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3520 return FALSE;
3521 htab->root.iplt = s;
3522 }
3523
3524 if (htab->root.irelplt == NULL)
3525 {
3d4d4302
AM		 3526 s = bfd_make_section_anyway_with_flags (dynobj,
3527 RELOC_SECTION (htab, ".iplt"),
3528 flags | SEC_READONLY);
34e77a92 3529 if (s == NULL
a0f49396 3530 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3531 return FALSE;
3532 htab->root.irelplt = s;
3533 }
3534
3535 if (htab->root.igotplt == NULL)
3536 {
3d4d4302 3537 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3538 if (s == NULL
3539 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3540 return FALSE;
3541 htab->root.igotplt = s;
3542 }
3543 return TRUE;
3544}
3545
eed94f8f
NC		 3546/* Determine if we're dealing with a Thumb only architecture. */
3547
3548static bfd_boolean
3549using_thumb_only (struct elf32_arm_link_hash_table *globals)
3550{
2fd158eb
TP		 3551 int arch;
3552 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3553 Tag_CPU_arch_profile);
eed94f8f 3554
2fd158eb
TP		 3555 if (profile)
3556 return profile == 'M';
eed94f8f 3557
2fd158eb 3558 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3559
60a019a0
TP		 3560 /* Force return logic to be reviewed for each new architecture. */
3561 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3562 || arch == TAG_CPU_ARCH_V8M_BASE
3563 || arch == TAG_CPU_ARCH_V8M_MAIN);
3564
2fd158eb
TP		 3565 if (arch == TAG_CPU_ARCH_V6_M
3566 || arch == TAG_CPU_ARCH_V6S_M
3567 || arch == TAG_CPU_ARCH_V7E_M
3568 || arch == TAG_CPU_ARCH_V8M_BASE
3569 || arch == TAG_CPU_ARCH_V8M_MAIN)
3570 return TRUE;
eed94f8f 3571
2fd158eb 3572 return FALSE;
eed94f8f
NC		 3573}
3574
3575/* Determine if we're dealing with a Thumb-2 object. */
3576
3577static bfd_boolean
3578using_thumb2 (struct elf32_arm_link_hash_table *globals)
3579{
60a019a0
TP		 3580 int arch;
3581 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3582 Tag_THUMB_ISA_use);
3583
3584 if (thumb_isa)
3585 return thumb_isa == 2;
3586
3587 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3588
3589 /* Force return logic to be reviewed for each new architecture. */
3590 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3591 || arch == TAG_CPU_ARCH_V8M_BASE
3592 || arch == TAG_CPU_ARCH_V8M_MAIN);
3593
3594 return (arch == TAG_CPU_ARCH_V6T2
3595 || arch == TAG_CPU_ARCH_V7
3596 || arch == TAG_CPU_ARCH_V7E_M
3597 || arch == TAG_CPU_ARCH_V8
3598 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3599}
3600
5e866f5a
TP		 3601/* Determine whether Thumb-2 BL instruction is available. */
3602
3603static bfd_boolean
3604using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3605{
3606 int arch =
3607 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3608
3609 /* Force return logic to be reviewed for each new architecture. */
3610 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3611 || arch == TAG_CPU_ARCH_V8M_BASE
3612 || arch == TAG_CPU_ARCH_V8M_MAIN);
3613
3614 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3615 return (arch == TAG_CPU_ARCH_V6T2
3616 || arch >= TAG_CPU_ARCH_V7);
3617}
3618
00a97672
RS		 3619/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3620 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3621 hash table. */
3622
3623static bfd_boolean
57e8b36a 3624elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3625{
3626 struct elf32_arm_link_hash_table *htab;
3627
3628 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3629 if (htab == NULL)
3630 return FALSE;
3631
362d30a1 3632 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3633 return FALSE;
3634
3635 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3636 return FALSE;
3637
3d4d4302 3638 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3639 if (!bfd_link_pic (info))
3d4d4302
AM		 3640 htab->srelbss = bfd_get_linker_section (dynobj,
3641 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3642
3643 if (htab->vxworks_p)
3644 {
3645 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3646 return FALSE;
3647
0e1862bb 3648 if (bfd_link_pic (info))
00a97672
RS		 3649 {
3650 htab->plt_header_size = 0;
3651 htab->plt_entry_size
3652 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3653 }
3654 else
3655 {
3656 htab->plt_header_size
3657 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3658 htab->plt_entry_size
3659 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3660 }
aebf9be7
NC		 3661
3662 if (elf_elfheader (dynobj))
3663 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3664 }
eed94f8f
NC		 3665 else
3666 {
3667 /* PR ld/16017
3668 Test for thumb only architectures. Note - we cannot just call
3669 using_thumb_only() as the attributes in the output bfd have not been
3670 initialised at this point, so instead we use the input bfd. */
3671 bfd * saved_obfd = htab->obfd;
3672
3673 htab->obfd = dynobj;
3674 if (using_thumb_only (htab))
3675 {
3676 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3677 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3678 }
3679 htab->obfd = saved_obfd;
3680 }
5e681ec4 3681
362d30a1
RS		 3682 if (!htab->root.splt
3683 || !htab->root.srelplt
e5a52504 3684 || !htab->sdynbss
0e1862bb 3685 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3686 abort ();
3687
3688 return TRUE;
3689}
3690
906e58ca
NC		 3691/* Copy the extra info we tack onto an elf_link_hash_entry. */
3692
3693static void
3694elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3695 struct elf_link_hash_entry *dir,
3696 struct elf_link_hash_entry *ind)
3697{
3698 struct elf32_arm_link_hash_entry *edir, *eind;
3699
3700 edir = (struct elf32_arm_link_hash_entry *) dir;
3701 eind = (struct elf32_arm_link_hash_entry *) ind;
3702
0bdcacaf 3703 if (eind->dyn_relocs != NULL)
906e58ca 3704 {
0bdcacaf 3705 if (edir->dyn_relocs != NULL)
906e58ca 3706 {
0bdcacaf
RS		 3707 struct elf_dyn_relocs **pp;
3708 struct elf_dyn_relocs *p;
906e58ca
NC		 3709
3710 /* Add reloc counts against the indirect sym to the direct sym
3711 list. Merge any entries against the same section. */
0bdcacaf 3712 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3713 {
0bdcacaf 3714 struct elf_dyn_relocs *q;
906e58ca 3715
0bdcacaf
RS		 3716 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3717 if (q->sec == p->sec)
906e58ca
NC		 3718 {
3719 q->pc_count += p->pc_count;
3720 q->count += p->count;
3721 *pp = p->next;
3722 break;
3723 }
3724 if (q == NULL)
3725 pp = &p->next;
3726 }
0bdcacaf 3727 *pp = edir->dyn_relocs;
906e58ca
NC		 3728 }
3729
0bdcacaf
RS		 3730 edir->dyn_relocs = eind->dyn_relocs;
3731 eind->dyn_relocs = NULL;
906e58ca
NC		 3732 }
3733
3734 if (ind->root.type == bfd_link_hash_indirect)
3735 {
3736 /* Copy over PLT info. */
34e77a92
RS		 3737 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3738 eind->plt.thumb_refcount = 0;
3739 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3740 eind->plt.maybe_thumb_refcount = 0;
3741 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3742 eind->plt.noncall_refcount = 0;
3743
3744 /* We should only allocate a function to .iplt once the final
3745 symbol information is known. */
3746 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3747
3748 if (dir->got.refcount <= 0)
3749 {
3750 edir->tls_type = eind->tls_type;
3751 eind->tls_type = GOT_UNKNOWN;
3752 }
3753 }
3754
3755 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3756}
3757
68faa637
AM		 3758/* Destroy an ARM elf linker hash table. */
3759
3760static void
d495ab0d 3761elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3762{
3763 struct elf32_arm_link_hash_table *ret
d495ab0d 3764 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3765
3766 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3767 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3768}
3769
906e58ca
NC		 3770/* Create an ARM elf linker hash table. */
3771
3772static struct bfd_link_hash_table *
3773elf32_arm_link_hash_table_create (bfd *abfd)
3774{
3775 struct elf32_arm_link_hash_table *ret;
3776 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3777
7bf52ea2 3778 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3779 if (ret == NULL)
3780 return NULL;
3781
3782 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3783 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3784 sizeof (struct elf32_arm_link_hash_entry),
3785 ARM_ELF_DATA))
906e58ca
NC		 3786 {
3787 free (ret);
3788 return NULL;
3789 }
3790
906e58ca 3791 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3792 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3793#ifdef FOUR_WORD_PLT
3794 ret->plt_header_size = 16;
3795 ret->plt_entry_size = 16;
3796#else
3797 ret->plt_header_size = 20;
1db37fe6 3798 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3799#endif
906e58ca 3800 ret->use_rel = 1;
906e58ca 3801 ret->obfd = abfd;
906e58ca
NC		 3802
3803 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3804 sizeof (struct elf32_arm_stub_hash_entry)))
3805 {
d495ab0d 3806 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3807 return NULL;
3808 }
d495ab0d 3809 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3810
3811 return &ret->root.root;
3812}
3813
cd1dac3d
DG		 3814/* Determine what kind of NOPs are available. */
3815
3816static bfd_boolean
3817arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3818{
3819 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3820 Tag_CPU_arch);
cd1dac3d 3821
60a019a0
TP		 3822 /* Force return logic to be reviewed for each new architecture. */
3823 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3824 || arch == TAG_CPU_ARCH_V8M_BASE
3825 || arch == TAG_CPU_ARCH_V8M_MAIN);
3826
3827 return (arch == TAG_CPU_ARCH_V6T2
3828 || arch == TAG_CPU_ARCH_V6K
3829 || arch == TAG_CPU_ARCH_V7
3830 || arch == TAG_CPU_ARCH_V8);
cd1dac3d
DG		 3831}
3832
f4ac8484
DJ		 3833static bfd_boolean
3834arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3835{
3836 switch (stub_type)
3837 {
fea2b4d6 3838 case arm_stub_long_branch_thumb_only:
80c135e5 3839 case arm_stub_long_branch_thumb2_only:
d5a67c02 3840 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3841 case arm_stub_long_branch_v4t_thumb_arm:
3842 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3843 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3844 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3845 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3846 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3847 return TRUE;
3848 case arm_stub_none:
3849 BFD_FAIL ();
3850 return FALSE;
3851 break;
3852 default:
3853 return FALSE;
3854 }
3855}
3856
906e58ca
NC		 3857/* Determine the type of stub needed, if any, for a call. */
3858
3859static enum elf32_arm_stub_type
3860arm_type_of_stub (struct bfd_link_info *info,
3861 asection *input_sec,
3862 const Elf_Internal_Rela *rel,
34e77a92 3863 unsigned char st_type,
35fc36a8 3864 enum arm_st_branch_type *actual_branch_type,
906e58ca 3865 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3866 bfd_vma destination,
3867 asection *sym_sec,
3868 bfd *input_bfd,
3869 const char *name)
906e58ca
NC		 3870{
3871 bfd_vma location;
3872 bfd_signed_vma branch_offset;
3873 unsigned int r_type;
3874 struct elf32_arm_link_hash_table * globals;
5e866f5a 3875 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3876 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3877 int use_plt = 0;
35fc36a8 3878 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3879 union gotplt_union *root_plt;
3880 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3881 int arch;
3882 int thumb2_movw;
906e58ca 3883
35fc36a8 3884 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3885 return stub_type;
3886
906e58ca 3887 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3888 if (globals == NULL)
3889 return stub_type;
906e58ca
NC		 3890
3891 thumb_only = using_thumb_only (globals);
906e58ca 3892 thumb2 = using_thumb2 (globals);
5e866f5a 3893 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3894
d5a67c02
AV		 3895 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3896
3897 /* True for architectures that implement the thumb2 movw instruction. */
3898 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3899
906e58ca
NC		 3900 /* Determine where the call point is. */
3901 location = (input_sec->output_offset
3902 + input_sec->output_section->vma
3903 + rel->r_offset);
3904
906e58ca
NC		 3905 r_type = ELF32_R_TYPE (rel->r_info);
3906
39f21624
NC		 3907 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3908 are considering a function call relocation. */
c5423981
TG		 3909 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3910 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3911 && branch_type == ST_BRANCH_TO_ARM)
3912 branch_type = ST_BRANCH_TO_THUMB;
3913
34e77a92
RS		 3914 /* For TLS call relocs, it is the caller's responsibility to provide
3915 the address of the appropriate trampoline. */
3916 if (r_type != R_ARM_TLS_CALL
3917 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3918 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3919 ELF32_R_SYM (rel->r_info), &root_plt,
3920 &arm_plt)
34e77a92 3921 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3922 {
34e77a92 3923 asection *splt;
fe33d2fa 3924
34e77a92
RS		 3925 if (hash == NULL || hash->is_iplt)
3926 splt = globals->root.iplt;
3927 else
3928 splt = globals->root.splt;
3929 if (splt != NULL)
b38cadfb 3930 {
34e77a92
RS		 3931 use_plt = 1;
3932
3933 /* Note when dealing with PLT entries: the main PLT stub is in
3934 ARM mode, so if the branch is in Thumb mode, another
3935 Thumb->ARM stub will be inserted later just before the ARM
3936 PLT stub. We don't take this extra distance into account
3937 here, because if a long branch stub is needed, we'll add a
3938 Thumb->Arm one and branch directly to the ARM PLT entry
3939 because it avoids spreading offset corrections in several
3940 places. */
3941
3942 destination = (splt->output_section->vma
3943 + splt->output_offset
3944 + root_plt->offset);
3945 st_type = STT_FUNC;
3946 branch_type = ST_BRANCH_TO_ARM;
3947 }
5fa9e92f 3948 }
34e77a92
RS		 3949 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3950 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3951
fe33d2fa
CL		 3952 branch_offset = (bfd_signed_vma)(destination - location);
3953
0855e32b 3954 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3955 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3956 {
5fa9e92f
CL		 3957 /* Handle cases where:
3958 - this call goes too far (different Thumb/Thumb2 max
99059e56 3959 distance)
155d87d7 3960 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3961 Thumb->Arm branch (not bl). A stub is needed in this case,
3962 but only if this call is not through a PLT entry. Indeed,
3963 PLT stubs handle mode switching already.
5fa9e92f 3964 */
5e866f5a 3965 if ((!thumb2_bl
906e58ca
NC		 3966 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3967 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 3968 || (thumb2_bl
906e58ca
NC		 3969 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3970 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3971 || (thumb2
3972 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3973 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3974 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3975 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3976 && (((r_type == R_ARM_THM_CALL
3977 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3978 || (r_type == R_ARM_THM_JUMP24)
3979 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3980 && !use_plt))
906e58ca 3981 {
35fc36a8 3982 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3983 {
3984 /* Thumb to thumb. */
3985 if (!thumb_only)
3986 {
d5a67c02
AV		 3987 if (input_sec->flags & SEC_ELF_PURECODE)
3988 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
3989 " veneers used in section with "
3990 "SHF_ARM_PURECODE section "
3991 "attribute is only supported"
3992 " for M-profile targets that "
3993 "implement the movw "
3994 "instruction."));
3995
0e1862bb 3996 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3997 /* PIC stubs. */
155d87d7 3998 ? ((globals->use_blx
9553db3c 3999 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4000 /* V5T and above. Stub starts with ARM code, so
4001 we must be able to switch mode before
4002 reaching it, which is only possible for 'bl'
4003 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4004 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4005 /* On V4T, use Thumb code only. */
d3626fb0 4006 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4007
4008 /* non-PIC stubs. */
155d87d7 4009 : ((globals->use_blx
9553db3c 4010 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4011 /* V5T and above. */
4012 ? arm_stub_long_branch_any_any
4013 /* V4T. */
d3626fb0 4014 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4015 }
4016 else
4017 {
d5a67c02
AV		 4018 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4019 stub_type = arm_stub_long_branch_thumb2_only_pure;
4020 else
4021 {
4022 if (input_sec->flags & SEC_ELF_PURECODE)
4023 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4024 " veneers used in section with "
4025 "SHF_ARM_PURECODE section "
4026 "attribute is only supported"
4027 " for M-profile targets that "
4028 "implement the movw "
4029 "instruction."));
4030
4031 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4032 /* PIC stub. */
4033 ? arm_stub_long_branch_thumb_only_pic
4034 /* non-PIC stub. */
4035 : (thumb2 ? arm_stub_long_branch_thumb2_only
4036 : arm_stub_long_branch_thumb_only);
4037 }
906e58ca
NC		 4038 }
4039 }
4040 else
4041 {
d5a67c02
AV		 4042 if (input_sec->flags & SEC_ELF_PURECODE)
4043 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4044 " veneers used in section with "
4045 "SHF_ARM_PURECODE section "
4046 "attribute is only supported"
4047 " for M-profile targets that "
4048 "implement the movw "
4049 "instruction."));
4050
906e58ca 4051 /* Thumb to arm. */
c820be07
NC		 4052 if (sym_sec != NULL
4053 && sym_sec->owner != NULL
4054 && !INTERWORK_FLAG (sym_sec->owner))
4055 {
4056 (*_bfd_error_handler)
4057 (_("%B(%s): warning: interworking not enabled.\n"
4058 " first occurrence: %B: Thumb call to ARM"),
4059 sym_sec->owner, input_bfd, name);
4060 }
4061
0855e32b 4062 stub_type =
0e1862bb 4063 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4064 /* PIC stubs. */
0855e32b 4065 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4066 /* TLS PIC stubs. */
0855e32b
NS		 4067 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4068 : arm_stub_long_branch_v4t_thumb_tls_pic)
4069 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4070 /* V5T PIC and above. */
4071 ? arm_stub_long_branch_any_arm_pic
4072 /* V4T PIC stub. */
4073 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4074
4075 /* non-PIC stubs. */
0855e32b 4076 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4077 /* V5T and above. */
4078 ? arm_stub_long_branch_any_any
4079 /* V4T. */
4080 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4081
4082 /* Handle v4t short branches. */
fea2b4d6 4083 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4084 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4085 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4086 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4087 }
4088 }
4089 }
fe33d2fa
CL		 4090 else if (r_type == R_ARM_CALL
4091 || r_type == R_ARM_JUMP24
0855e32b
NS		 4092 || r_type == R_ARM_PLT32
4093 || r_type == R_ARM_TLS_CALL)
906e58ca 4094 {
d5a67c02
AV		 4095 if (input_sec->flags & SEC_ELF_PURECODE)
4096 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4097 " veneers used in section with "
4098 "SHF_ARM_PURECODE section "
4099 "attribute is only supported"
4100 " for M-profile targets that "
4101 "implement the movw "
4102 "instruction."));
35fc36a8 4103 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4104 {
4105 /* Arm to thumb. */
c820be07
NC		 4106
4107 if (sym_sec != NULL
4108 && sym_sec->owner != NULL
4109 && !INTERWORK_FLAG (sym_sec->owner))
4110 {
4111 (*_bfd_error_handler)
4112 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4113 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 4114 sym_sec->owner, input_bfd, name);
4115 }
4116
4117 /* We have an extra 2-bytes reach because of
4118 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4119 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4120 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4121 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4122 || (r_type == R_ARM_JUMP24)
4123 || (r_type == R_ARM_PLT32))
906e58ca 4124 {
0e1862bb 4125 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4126 /* PIC stubs. */
ebe24dd4
CL		 4127 ? ((globals->use_blx)
4128 /* V5T and above. */
4129 ? arm_stub_long_branch_any_thumb_pic
4130 /* V4T stub. */
4131 : arm_stub_long_branch_v4t_arm_thumb_pic)
4132
c2b4a39d
CL		 4133 /* non-PIC stubs. */
4134 : ((globals->use_blx)
4135 /* V5T and above. */
4136 ? arm_stub_long_branch_any_any
4137 /* V4T. */
4138 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4139 }
4140 }
4141 else
4142 {
4143 /* Arm to arm. */
4144 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4145 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4146 {
0855e32b 4147 stub_type =
0e1862bb 4148 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4149 /* PIC stubs. */
0855e32b 4150 ? (r_type == R_ARM_TLS_CALL
6a631e86 4151 /* TLS PIC Stub. */
0855e32b 4152 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4153 : (globals->nacl_p
4154 ? arm_stub_long_branch_arm_nacl_pic
4155 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4156 /* non-PIC stubs. */
7a89b94e
NC		 4157 : (globals->nacl_p
4158 ? arm_stub_long_branch_arm_nacl
4159 : arm_stub_long_branch_any_any);
906e58ca
NC		 4160 }
4161 }
4162 }
4163
fe33d2fa
CL		 4164 /* If a stub is needed, record the actual destination type. */
4165 if (stub_type != arm_stub_none)
35fc36a8 4166 *actual_branch_type = branch_type;
fe33d2fa 4167
906e58ca
NC		 4168 return stub_type;
4169}
4170
4171/* Build a name for an entry in the stub hash table. */
4172
4173static char *
4174elf32_arm_stub_name (const asection *input_section,
4175 const asection *sym_sec,
4176 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4177 const Elf_Internal_Rela *rel,
4178 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4179{
4180 char *stub_name;
4181 bfd_size_type len;
4182
4183 if (hash)
4184 {
fe33d2fa 4185 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4186 stub_name = (char *) bfd_malloc (len);
906e58ca 4187 if (stub_name != NULL)
fe33d2fa 4188 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4189 input_section->id & 0xffffffff,
4190 hash->root.root.root.string,
fe33d2fa
CL		 4191 (int) rel->r_addend & 0xffffffff,
4192 (int) stub_type);
906e58ca
NC		 4193 }
4194 else
4195 {
fe33d2fa 4196 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4197 stub_name = (char *) bfd_malloc (len);
906e58ca 4198 if (stub_name != NULL)
fe33d2fa 4199 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4200 input_section->id & 0xffffffff,
4201 sym_sec->id & 0xffffffff,
0855e32b
NS		 4202 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4203 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4204 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4205 (int) rel->r_addend & 0xffffffff,
4206 (int) stub_type);
906e58ca
NC		 4207 }
4208
4209 return stub_name;
4210}
4211
4212/* Look up an entry in the stub hash. Stub entries are cached because
4213 creating the stub name takes a bit of time. */
4214
4215static struct elf32_arm_stub_hash_entry *
4216elf32_arm_get_stub_entry (const asection *input_section,
4217 const asection *sym_sec,
4218 struct elf_link_hash_entry *hash,
4219 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4220 struct elf32_arm_link_hash_table *htab,
4221 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4222{
4223 struct elf32_arm_stub_hash_entry *stub_entry;
4224 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4225 const asection *id_sec;
4226
4227 if ((input_section->flags & SEC_CODE) == 0)
4228 return NULL;
4229
4230 /* If this input section is part of a group of sections sharing one
4231 stub section, then use the id of the first section in the group.
4232 Stub names need to include a section id, as there may well be
4233 more than one stub used to reach say, printf, and we need to
4234 distinguish between them. */
4235 id_sec = htab->stub_group[input_section->id].link_sec;
4236
4237 if (h != NULL && h->stub_cache != NULL
4238 && h->stub_cache->h == h
fe33d2fa
CL		 4239 && h->stub_cache->id_sec == id_sec
4240 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4241 {
4242 stub_entry = h->stub_cache;
4243 }
4244 else
4245 {
4246 char *stub_name;
4247
fe33d2fa 4248 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4249 if (stub_name == NULL)
4250 return NULL;
4251
4252 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4253 stub_name, FALSE, FALSE);
4254 if (h != NULL)
4255 h->stub_cache = stub_entry;
4256
4257 free (stub_name);
4258 }
4259
4260 return stub_entry;
4261}
4262
daa4adae
TP		 4263/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4264 section. */
4265
4266static bfd_boolean
4267arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4268{
4269 if (stub_type >= max_stub_type)
4270 abort (); /* Should be unreachable. */
4271
4ba2ef8f
TP		 4272 switch (stub_type)
4273 {
4274 case arm_stub_cmse_branch_thumb_only:
4275 return TRUE;
4276
4277 default:
4278 return FALSE;
4279 }
4280
4281 abort (); /* Should be unreachable. */
daa4adae
TP		 4282}
4283
4284/* Required alignment (as a power of 2) for the dedicated section holding
4285 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4286 with input sections. */
4287
4288static int
4289arm_dedicated_stub_output_section_required_alignment
4290 (enum elf32_arm_stub_type stub_type)
4291{
4292 if (stub_type >= max_stub_type)
4293 abort (); /* Should be unreachable. */
4294
4ba2ef8f
TP		 4295 switch (stub_type)
4296 {
4297 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4298 boundary. */
4299 case arm_stub_cmse_branch_thumb_only:
4300 return 5;
4301
4302 default:
4303 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4304 return 0;
4305 }
4306
4307 abort (); /* Should be unreachable. */
daa4adae
TP		 4308}
4309
4310/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4311 NULL if veneers of this type are interspersed with input sections. */
4312
4313static const char *
4314arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4315{
4316 if (stub_type >= max_stub_type)
4317 abort (); /* Should be unreachable. */
4318
4ba2ef8f
TP		 4319 switch (stub_type)
4320 {
4321 case arm_stub_cmse_branch_thumb_only:
4322 return ".gnu.sgstubs";
4323
4324 default:
4325 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4326 return NULL;
4327 }
4328
4329 abort (); /* Should be unreachable. */
daa4adae
TP		 4330}
4331
4332/* If veneers of type STUB_TYPE should go in a dedicated output section,
4333 returns the address of the hash table field in HTAB holding a pointer to the
4334 corresponding input section. Otherwise, returns NULL. */
4335
4336static asection **
4ba2ef8f
TP		 4337arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4338 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4339{
4340 if (stub_type >= max_stub_type)
4341 abort (); /* Should be unreachable. */
4342
4ba2ef8f
TP		 4343 switch (stub_type)
4344 {
4345 case arm_stub_cmse_branch_thumb_only:
4346 return &htab->cmse_stub_sec;
4347
4348 default:
4349 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4350 return NULL;
4351 }
4352
4353 abort (); /* Should be unreachable. */
daa4adae
TP		 4354}
4355
4356/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4357 is the section that branch into veneer and can be NULL if stub should go in
4358 a dedicated output section. Returns a pointer to the stub section, and the
4359 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4360 LINK_SEC_P may be NULL. */
906e58ca 4361
48229727
JB		 4362static asection *
4363elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4364 struct elf32_arm_link_hash_table *htab,
4365 enum elf32_arm_stub_type stub_type)
906e58ca 4366{
daa4adae
TP		 4367 asection *link_sec, *out_sec, **stub_sec_p;
4368 const char *stub_sec_prefix;
4369 bfd_boolean dedicated_output_section =
4370 arm_dedicated_stub_output_section_required (stub_type);
4371 int align;
906e58ca 4372
daa4adae 4373 if (dedicated_output_section)
906e58ca 4374 {
daa4adae
TP		 4375 bfd *output_bfd = htab->obfd;
4376 const char *out_sec_name =
4377 arm_dedicated_stub_output_section_name (stub_type);
4378 link_sec = NULL;
4379 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4380 stub_sec_prefix = out_sec_name;
4381 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4382 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4383 if (out_sec == NULL)
906e58ca 4384 {
daa4adae
TP		 4385 (*_bfd_error_handler) (_("No address assigned to the veneers output "
4386 "section %s"), out_sec_name);
4387 return NULL;
906e58ca 4388 }
daa4adae
TP		 4389 }
4390 else
4391 {
4392 link_sec = htab->stub_group[section->id].link_sec;
4393 BFD_ASSERT (link_sec != NULL);
4394 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4395 if (*stub_sec_p == NULL)
4396 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4397 stub_sec_prefix = link_sec->name;
4398 out_sec = link_sec->output_section;
4399 align = htab->nacl_p ? 4 : 3;
906e58ca 4400 }
b38cadfb 4401
daa4adae
TP		 4402 if (*stub_sec_p == NULL)
4403 {
4404 size_t namelen;
4405 bfd_size_type len;
4406 char *s_name;
4407
4408 namelen = strlen (stub_sec_prefix);
4409 len = namelen + sizeof (STUB_SUFFIX);
4410 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4411 if (s_name == NULL)
4412 return NULL;
4413
4414 memcpy (s_name, stub_sec_prefix, namelen);
4415 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4416 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4417 align);
4418 if (*stub_sec_p == NULL)
4419 return NULL;
4420
4421 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4422 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4423 | SEC_KEEP;
4424 }
4425
4426 if (!dedicated_output_section)
4427 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4428
48229727
JB		 4429 if (link_sec_p)
4430 *link_sec_p = link_sec;
b38cadfb 4431
daa4adae 4432 return *stub_sec_p;
48229727
JB		 4433}
4434
4435/* Add a new stub entry to the stub hash. Not all fields of the new
4436 stub entry are initialised. */
4437
4438static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4439elf32_arm_add_stub (const char *stub_name, asection *section,
4440 struct elf32_arm_link_hash_table *htab,
4441 enum elf32_arm_stub_type stub_type)
48229727
JB		 4442{
4443 asection *link_sec;
4444 asection *stub_sec;
4445 struct elf32_arm_stub_hash_entry *stub_entry;
4446
daa4adae
TP		 4447 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4448 stub_type);
48229727
JB		 4449 if (stub_sec == NULL)
4450 return NULL;
906e58ca
NC		 4451
4452 /* Enter this entry into the linker stub hash table. */
4453 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4454 TRUE, FALSE);
4455 if (stub_entry == NULL)
4456 {
6bde4c52
TP		 4457 if (section == NULL)
4458 section = stub_sec;
906e58ca
NC		 4459 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4460 section->owner,
4461 stub_name);
4462 return NULL;
4463 }
4464
4465 stub_entry->stub_sec = stub_sec;
4466 stub_entry->stub_offset = 0;
4467 stub_entry->id_sec = link_sec;
4468
906e58ca
NC		 4469 return stub_entry;
4470}
4471
4472/* Store an Arm insn into an output section not processed by
4473 elf32_arm_write_section. */
4474
4475static void
8029a119
NC		 4476put_arm_insn (struct elf32_arm_link_hash_table * htab,
4477 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4478{
4479 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4480 bfd_putl32 (val, ptr);
4481 else
4482 bfd_putb32 (val, ptr);
4483}
4484
4485/* Store a 16-bit Thumb insn into an output section not processed by
4486 elf32_arm_write_section. */
4487
4488static void
8029a119
NC		 4489put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4490 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4491{
4492 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4493 bfd_putl16 (val, ptr);
4494 else
4495 bfd_putb16 (val, ptr);
4496}
4497
a504d23a
LA		 4498/* Store a Thumb2 insn into an output section not processed by
4499 elf32_arm_write_section. */
4500
4501static void
4502put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4503 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4504{
4505 /* T2 instructions are 16-bit streamed. */
4506 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4507 {
4508 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4509 bfd_putl16 ((val & 0xffff), ptr + 2);
4510 }
4511 else
4512 {
4513 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4514 bfd_putb16 ((val & 0xffff), ptr + 2);
4515 }
4516}
4517
0855e32b
NS		 4518/* If it's possible to change R_TYPE to a more efficient access
4519 model, return the new reloc type. */
4520
4521static unsigned
b38cadfb 4522elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4523 struct elf_link_hash_entry *h)
4524{
4525 int is_local = (h == NULL);
4526
0e1862bb
L		 4527 if (bfd_link_pic (info)
4528 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4529 return r_type;
4530
b38cadfb 4531 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4532 switch (r_type)
4533 {
4534 case R_ARM_TLS_GOTDESC:
4535 case R_ARM_TLS_CALL:
4536 case R_ARM_THM_TLS_CALL:
4537 case R_ARM_TLS_DESCSEQ:
4538 case R_ARM_THM_TLS_DESCSEQ:
4539 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4540 }
4541
4542 return r_type;
4543}
4544
48229727
JB		 4545static bfd_reloc_status_type elf32_arm_final_link_relocate
4546 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4547 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4548 const char *, unsigned char, enum arm_st_branch_type,
4549 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4550
4563a860
JB		 4551static unsigned int
4552arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4553{
4554 switch (stub_type)
4555 {
4556 case arm_stub_a8_veneer_b_cond:
4557 case arm_stub_a8_veneer_b:
4558 case arm_stub_a8_veneer_bl:
4559 return 2;
4560
4561 case arm_stub_long_branch_any_any:
4562 case arm_stub_long_branch_v4t_arm_thumb:
4563 case arm_stub_long_branch_thumb_only:
80c135e5 4564 case arm_stub_long_branch_thumb2_only:
d5a67c02 4565 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4566 case arm_stub_long_branch_v4t_thumb_thumb:
4567 case arm_stub_long_branch_v4t_thumb_arm:
4568 case arm_stub_short_branch_v4t_thumb_arm:
4569 case arm_stub_long_branch_any_arm_pic:
4570 case arm_stub_long_branch_any_thumb_pic:
4571 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4572 case arm_stub_long_branch_v4t_arm_thumb_pic:
4573 case arm_stub_long_branch_v4t_thumb_arm_pic:
4574 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4575 case arm_stub_long_branch_any_tls_pic:
4576 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4577 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4578 case arm_stub_a8_veneer_blx:
4579 return 4;
b38cadfb 4580
7a89b94e
NC		 4581 case arm_stub_long_branch_arm_nacl:
4582 case arm_stub_long_branch_arm_nacl_pic:
4583 return 16;
4584
4563a860
JB		 4585 default:
4586 abort (); /* Should be unreachable. */
4587 }
4588}
4589
4f4faa4d
TP		 4590/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4591 veneering (TRUE) or have their own symbol (FALSE). */
4592
4593static bfd_boolean
4594arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4595{
4596 if (stub_type >= max_stub_type)
4597 abort (); /* Should be unreachable. */
4598
4ba2ef8f
TP		 4599 switch (stub_type)
4600 {
4601 case arm_stub_cmse_branch_thumb_only:
4602 return TRUE;
4603
4604 default:
4605 return FALSE;
4606 }
4607
4608 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4609}
4610
d7c5bd02
TP		 4611/* Returns the padding needed for the dedicated section used stubs of type
4612 STUB_TYPE. */
4613
4614static int
4615arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4616{
4617 if (stub_type >= max_stub_type)
4618 abort (); /* Should be unreachable. */
4619
4ba2ef8f
TP		 4620 switch (stub_type)
4621 {
4622 case arm_stub_cmse_branch_thumb_only:
4623 return 32;
4624
4625 default:
4626 return 0;
4627 }
4628
4629 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4630}
4631
906e58ca
NC		 4632static bfd_boolean
4633arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4634 void * in_arg)
4635{
7a89b94e 4636#define MAXRELOCS 3
906e58ca 4637 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4638 struct elf32_arm_link_hash_table *globals;
906e58ca 4639 struct bfd_link_info *info;
906e58ca
NC		 4640 asection *stub_sec;
4641 bfd *stub_bfd;
906e58ca
NC		 4642 bfd_byte *loc;
4643 bfd_vma sym_value;
4644 int template_size;
4645 int size;
d3ce72d0 4646 const insn_sequence *template_sequence;
906e58ca 4647 int i;
48229727
JB		 4648 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4649 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4650 int nrelocs = 0;
906e58ca
NC		 4651
4652 /* Massage our args to the form they really have. */
4653 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4654 info = (struct bfd_link_info *) in_arg;
4655
4656 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4657 if (globals == NULL)
4658 return FALSE;
906e58ca 4659
906e58ca
NC		 4660 stub_sec = stub_entry->stub_sec;
4661
4dfe6ac6 4662 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4663 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4664 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4665 return TRUE;
fe33d2fa 4666
906e58ca
NC		 4667 /* Make a note of the offset within the stubs for this entry. */
4668 stub_entry->stub_offset = stub_sec->size;
4669 loc = stub_sec->contents + stub_entry->stub_offset;
4670
4671 stub_bfd = stub_sec->owner;
4672
906e58ca
NC		 4673 /* This is the address of the stub destination. */
4674 sym_value = (stub_entry->target_value
4675 + stub_entry->target_section->output_offset
4676 + stub_entry->target_section->output_section->vma);
4677
d3ce72d0 4678 template_sequence = stub_entry->stub_template;
461a49ca 4679 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4680
4681 size = 0;
461a49ca 4682 for (i = 0; i < template_size; i++)
906e58ca 4683 {
d3ce72d0 4684 switch (template_sequence[i].type)
461a49ca
DJ		 4685 {
4686 case THUMB16_TYPE:
48229727 4687 {
d3ce72d0
NC		 4688 bfd_vma data = (bfd_vma) template_sequence[i].data;
4689 if (template_sequence[i].reloc_addend != 0)
48229727 4690 {
99059e56
RM		 4691 /* We've borrowed the reloc_addend field to mean we should
4692 insert a condition code into this (Thumb-1 branch)
4693 instruction. See THUMB16_BCOND_INSN. */
4694 BFD_ASSERT ((data & 0xff00) == 0xd000);
4695 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4696 }
fe33d2fa 4697 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4698 size += 2;
4699 }
461a49ca 4700 break;
906e58ca 4701
48229727 4702 case THUMB32_TYPE:
fe33d2fa
CL		 4703 bfd_put_16 (stub_bfd,
4704 (template_sequence[i].data >> 16) & 0xffff,
4705 loc + size);
4706 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4707 loc + size + 2);
99059e56
RM		 4708 if (template_sequence[i].r_type != R_ARM_NONE)
4709 {
4710 stub_reloc_idx[nrelocs] = i;
4711 stub_reloc_offset[nrelocs++] = size;
4712 }
4713 size += 4;
4714 break;
48229727 4715
461a49ca 4716 case ARM_TYPE:
fe33d2fa
CL		 4717 bfd_put_32 (stub_bfd, template_sequence[i].data,
4718 loc + size);
461a49ca
DJ		 4719 /* Handle cases where the target is encoded within the
4720 instruction. */
d3ce72d0 4721 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4722 {
48229727
JB		 4723 stub_reloc_idx[nrelocs] = i;
4724 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4725 }
4726 size += 4;
4727 break;
4728
4729 case DATA_TYPE:
d3ce72d0 4730 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4731 stub_reloc_idx[nrelocs] = i;
4732 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4733 size += 4;
4734 break;
4735
4736 default:
4737 BFD_FAIL ();
4738 return FALSE;
4739 }
906e58ca 4740 }
461a49ca 4741
906e58ca
NC		 4742 stub_sec->size += size;
4743
461a49ca
DJ		 4744 /* Stub size has already been computed in arm_size_one_stub. Check
4745 consistency. */
4746 BFD_ASSERT (size == stub_entry->stub_size);
4747
906e58ca 4748 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4749 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4750 sym_value |= 1;
4751
48229727
JB		 4752 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4753 in each stub. */
4754 BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS);
c820be07 4755
48229727 4756 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4757 {
4758 Elf_Internal_Rela rel;
4759 bfd_boolean unresolved_reloc;
4760 char *error_message;
4761 bfd_vma points_to =
4762 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4763
4764 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4765 rel.r_info = ELF32_R_INFO (0,
4766 template_sequence[stub_reloc_idx[i]].r_type);
4767 rel.r_addend = 0;
4768
4769 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4770 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4771 template should refer back to the instruction after the original
4772 branch. We use target_section as Cortex-A8 erratum workaround stubs
4773 are only generated when both source and target are in the same
4774 section. */
4775 points_to = stub_entry->target_section->output_section->vma
4776 + stub_entry->target_section->output_offset
4777 + stub_entry->source_value;
4778
4779 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4780 (template_sequence[stub_reloc_idx[i]].r_type),
4781 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4782 points_to, info, stub_entry->target_section, "", STT_FUNC,
4783 stub_entry->branch_type,
4784 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4785 &error_message);
4786 }
906e58ca
NC		 4787
4788 return TRUE;
48229727 4789#undef MAXRELOCS
906e58ca
NC		 4790}
4791
48229727
JB		 4792/* Calculate the template, template size and instruction size for a stub.
4793 Return value is the instruction size. */
906e58ca 4794
48229727
JB		 4795static unsigned int
4796find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4797 const insn_sequence **stub_template,
4798 int *stub_template_size)
906e58ca 4799{
d3ce72d0 4800 const insn_sequence *template_sequence = NULL;
48229727
JB		 4801 int template_size = 0, i;
4802 unsigned int size;
906e58ca 4803
d3ce72d0 4804 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4805 if (stub_template)
4806 *stub_template = template_sequence;
4807
48229727 4808 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4809 if (stub_template_size)
4810 *stub_template_size = template_size;
906e58ca
NC		 4811
4812 size = 0;
461a49ca
DJ		 4813 for (i = 0; i < template_size; i++)
4814 {
d3ce72d0 4815 switch (template_sequence[i].type)
461a49ca
DJ		 4816 {
4817 case THUMB16_TYPE:
4818 size += 2;
4819 break;
4820
4821 case ARM_TYPE:
48229727 4822 case THUMB32_TYPE:
461a49ca
DJ		 4823 case DATA_TYPE:
4824 size += 4;
4825 break;
4826
4827 default:
4828 BFD_FAIL ();
2a229407 4829 return 0;
461a49ca
DJ		 4830 }
4831 }
4832
48229727
JB		 4833 return size;
4834}
4835
4836/* As above, but don't actually build the stub. Just bump offset so
4837 we know stub section sizes. */
4838
4839static bfd_boolean
4840arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4841 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4842{
4843 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4844 const insn_sequence *template_sequence;
48229727
JB		 4845 int template_size, size;
4846
4847 /* Massage our args to the form they really have. */
4848 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4849
4850 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4851 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4852
d3ce72d0 4853 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4854 &template_size);
4855
461a49ca 4856 stub_entry->stub_size = size;
d3ce72d0 4857 stub_entry->stub_template = template_sequence;
461a49ca
DJ		 4858 stub_entry->stub_template_size = template_size;
4859
906e58ca
NC		 4860 size = (size + 7) & ~7;
4861 stub_entry->stub_sec->size += size;
461a49ca 4862
906e58ca
NC		 4863 return TRUE;
4864}
4865
4866/* External entry points for sizing and building linker stubs. */
4867
4868/* Set up various things so that we can make a list of input sections
4869 for each output section included in the link. Returns -1 on error,
4870 0 when no stubs will be needed, and 1 on success. */
4871
4872int
4873elf32_arm_setup_section_lists (bfd *output_bfd,
4874 struct bfd_link_info *info)
4875{
4876 bfd *input_bfd;
4877 unsigned int bfd_count;
7292b3ac 4878 unsigned int top_id, top_index;
906e58ca
NC		 4879 asection *section;
4880 asection **input_list, **list;
4881 bfd_size_type amt;
4882 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4883
4dfe6ac6
NC		 4884 if (htab == NULL)
4885 return 0;
906e58ca
NC		 4886 if (! is_elf_hash_table (htab))
4887 return 0;
4888
4889 /* Count the number of input BFDs and find the top input section id. */
4890 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4891 input_bfd != NULL;
c72f2fb2 4892 input_bfd = input_bfd->link.next)
906e58ca
NC		 4893 {
4894 bfd_count += 1;
4895 for (section = input_bfd->sections;
4896 section != NULL;
4897 section = section->next)
4898 {
4899 if (top_id < section->id)
4900 top_id = section->id;
4901 }
4902 }
4903 htab->bfd_count = bfd_count;
4904
4905 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4906 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4907 if (htab->stub_group == NULL)
4908 return -1;
fe33d2fa 4909 htab->top_id = top_id;
906e58ca
NC		 4910
4911 /* We can't use output_bfd->section_count here to find the top output
4912 section index as some sections may have been removed, and
4913 _bfd_strip_section_from_output doesn't renumber the indices. */
4914 for (section = output_bfd->sections, top_index = 0;
4915 section != NULL;
4916 section = section->next)
4917 {
4918 if (top_index < section->index)
4919 top_index = section->index;
4920 }
4921
4922 htab->top_index = top_index;
4923 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4924 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4925 htab->input_list = input_list;
4926 if (input_list == NULL)
4927 return -1;
4928
4929 /* For sections we aren't interested in, mark their entries with a
4930 value we can check later. */
4931 list = input_list + top_index;
4932 do
4933 *list = bfd_abs_section_ptr;
4934 while (list-- != input_list);
4935
4936 for (section = output_bfd->sections;
4937 section != NULL;
4938 section = section->next)
4939 {
4940 if ((section->flags & SEC_CODE) != 0)
4941 input_list[section->index] = NULL;
4942 }
4943
4944 return 1;
4945}
4946
4947/* The linker repeatedly calls this function for each input section,
4948 in the order that input sections are linked into output sections.
4949 Build lists of input sections to determine groupings between which
4950 we may insert linker stubs. */
4951
4952void
4953elf32_arm_next_input_section (struct bfd_link_info *info,
4954 asection *isec)
4955{
4956 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4957
4dfe6ac6
NC		 4958 if (htab == NULL)
4959 return;
4960
906e58ca
NC		 4961 if (isec->output_section->index <= htab->top_index)
4962 {
4963 asection **list = htab->input_list + isec->output_section->index;
4964
a7470592 4965 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 4966 {
4967 /* Steal the link_sec pointer for our list. */
4968#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4969 /* This happens to make the list in reverse order,
07d72278 4970 which we reverse later. */
906e58ca
NC		 4971 PREV_SEC (isec) = *list;
4972 *list = isec;
4973 }
4974 }
4975}
4976
4977/* See whether we can group stub sections together. Grouping stub
4978 sections may result in fewer stubs. More importantly, we need to
07d72278 4979 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 4980 .fini output sections respectively, because glibc splits the
4981 _init and _fini functions into multiple parts. Putting a stub in
4982 the middle of a function is not a good idea. */
4983
4984static void
4985group_sections (struct elf32_arm_link_hash_table *htab,
4986 bfd_size_type stub_group_size,
07d72278 4987 bfd_boolean stubs_always_after_branch)
906e58ca 4988{
07d72278 4989 asection **list = htab->input_list;
906e58ca
NC		 4990
4991 do
4992 {
4993 asection *tail = *list;
07d72278 4994 asection *head;
906e58ca
NC		 4995
4996 if (tail == bfd_abs_section_ptr)
4997 continue;
4998
07d72278
DJ		 4999 /* Reverse the list: we must avoid placing stubs at the
5000 beginning of the section because the beginning of the text
5001 section may be required for an interrupt vector in bare metal
5002 code. */
5003#define NEXT_SEC PREV_SEC
e780aef2
CL		 5004 head = NULL;
5005 while (tail != NULL)
99059e56
RM		 5006 {
5007 /* Pop from tail. */
5008 asection *item = tail;
5009 tail = PREV_SEC (item);
e780aef2 5010
99059e56
RM		 5011 /* Push on head. */
5012 NEXT_SEC (item) = head;
5013 head = item;
5014 }
07d72278
DJ		 5015
5016 while (head != NULL)
906e58ca
NC		 5017 {
5018 asection *curr;
07d72278 5019 asection *next;
e780aef2
CL		 5020 bfd_vma stub_group_start = head->output_offset;
5021 bfd_vma end_of_next;
906e58ca 5022
07d72278 5023 curr = head;
e780aef2 5024 while (NEXT_SEC (curr) != NULL)
8cd931b7 5025 {
e780aef2
CL		 5026 next = NEXT_SEC (curr);
5027 end_of_next = next->output_offset + next->size;
5028 if (end_of_next - stub_group_start >= stub_group_size)
5029 /* End of NEXT is too far from start, so stop. */
8cd931b7 5030 break;
e780aef2
CL		 5031 /* Add NEXT to the group. */
5032 curr = next;
8cd931b7 5033 }
906e58ca 5034
07d72278 5035 /* OK, the size from the start to the start of CURR is less
906e58ca 5036 than stub_group_size and thus can be handled by one stub
07d72278 5037 section. (Or the head section is itself larger than
906e58ca
NC		 5038 stub_group_size, in which case we may be toast.)
5039 We should really be keeping track of the total size of
5040 stubs added here, as stubs contribute to the final output
7fb9f789 5041 section size. */
906e58ca
NC		 5042 do
5043 {
07d72278 5044 next = NEXT_SEC (head);
906e58ca 5045 /* Set up this stub group. */
07d72278 5046 htab->stub_group[head->id].link_sec = curr;
906e58ca 5047 }
07d72278 5048 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5049
5050 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5051 bytes after the stub section can be handled by it too. */
5052 if (!stubs_always_after_branch)
906e58ca 5053 {
e780aef2
CL		 5054 stub_group_start = curr->output_offset + curr->size;
5055
8cd931b7 5056 while (next != NULL)
906e58ca 5057 {
e780aef2
CL		 5058 end_of_next = next->output_offset + next->size;
5059 if (end_of_next - stub_group_start >= stub_group_size)
5060 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5061 break;
e780aef2 5062 /* Add NEXT to the stub group. */
07d72278
DJ		 5063 head = next;
5064 next = NEXT_SEC (head);
5065 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5066 }
5067 }
07d72278 5068 head = next;
906e58ca
NC		 5069 }
5070 }
07d72278 5071 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5072
5073 free (htab->input_list);
5074#undef PREV_SEC
07d72278 5075#undef NEXT_SEC
906e58ca
NC		 5076}
5077
48229727
JB		 5078/* Comparison function for sorting/searching relocations relating to Cortex-A8
5079 erratum fix. */
5080
5081static int
5082a8_reloc_compare (const void *a, const void *b)
5083{
21d799b5
NC		 5084 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5085 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5086
5087 if (ra->from < rb->from)
5088 return -1;
5089 else if (ra->from > rb->from)
5090 return 1;
5091 else
5092 return 0;
5093}
5094
5095static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5096 const char *, char **);
5097
5098/* Helper function to scan code for sequences which might trigger the Cortex-A8
5099 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5100 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5101 otherwise. */
5102
81694485
NC		 5103static bfd_boolean
5104cortex_a8_erratum_scan (bfd *input_bfd,
5105 struct bfd_link_info *info,
48229727
JB		 5106 struct a8_erratum_fix **a8_fixes_p,
5107 unsigned int *num_a8_fixes_p,
5108 unsigned int *a8_fix_table_size_p,
5109 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5110 unsigned int num_a8_relocs,
5111 unsigned prev_num_a8_fixes,
5112 bfd_boolean *stub_changed_p)
48229727
JB		 5113{
5114 asection *section;
5115 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5116 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5117 unsigned int num_a8_fixes = *num_a8_fixes_p;
5118 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5119
4dfe6ac6
NC		 5120 if (htab == NULL)
5121 return FALSE;
5122
48229727
JB		 5123 for (section = input_bfd->sections;
5124 section != NULL;
5125 section = section->next)
5126 {
5127 bfd_byte *contents = NULL;
5128 struct _arm_elf_section_data *sec_data;
5129 unsigned int span;
5130 bfd_vma base_vma;
5131
5132 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5133 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5134 || (section->flags & SEC_EXCLUDE) != 0
5135 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5136 || (section->output_section == bfd_abs_section_ptr))
5137 continue;
48229727
JB		 5138
5139 base_vma = section->output_section->vma + section->output_offset;
5140
5141 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5142 contents = elf_section_data (section)->this_hdr.contents;
48229727 5143 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5144 return TRUE;
48229727
JB		 5145
5146 sec_data = elf32_arm_section_data (section);
5147
5148 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5149 {
5150 unsigned int span_start = sec_data->map[span].vma;
5151 unsigned int span_end = (span == sec_data->mapcount - 1)
5152 ? section->size : sec_data->map[span + 1].vma;
5153 unsigned int i;
5154 char span_type = sec_data->map[span].type;
5155 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5156
5157 if (span_type != 't')
5158 continue;
5159
5160 /* Span is entirely within a single 4KB region: skip scanning. */
5161 if (((base_vma + span_start) & ~0xfff)
48229727 5162 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5163 continue;
5164
5165 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5166
5167 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5168 * The branch target is in the same 4KB region as the
5169 first half of the branch.
5170 * The instruction before the branch is a 32-bit
5171 length non-branch instruction. */
5172 for (i = span_start; i < span_end;)
5173 {
5174 unsigned int insn = bfd_getl16 (&contents[i]);
5175 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5176 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5177
99059e56
RM		 5178 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5179 insn_32bit = TRUE;
48229727
JB		 5180
5181 if (insn_32bit)
99059e56
RM		 5182 {
5183 /* Load the rest of the insn (in manual-friendly order). */
5184 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5185
5186 /* Encoding T4: B<c>.W. */
5187 is_b = (insn & 0xf800d000) == 0xf0009000;
5188 /* Encoding T1: BL<c>.W. */
5189 is_bl = (insn & 0xf800d000) == 0xf000d000;
5190 /* Encoding T2: BLX<c>.W. */
5191 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5192 /* Encoding T3: B<c>.W (not permitted in IT block). */
5193 is_bcc = (insn & 0xf800d000) == 0xf0008000
5194 && (insn & 0x07f00000) != 0x03800000;
5195 }
5196
5197 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5198
99059e56 5199 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5200 && insn_32bit
5201 && is_32bit_branch
5202 && last_was_32bit
5203 && ! last_was_branch)
99059e56
RM		 5204 {
5205 bfd_signed_vma offset = 0;
5206 bfd_boolean force_target_arm = FALSE;
48229727 5207 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5208 bfd_vma target;
5209 enum elf32_arm_stub_type stub_type = arm_stub_none;
5210 struct a8_erratum_reloc key, *found;
5211 bfd_boolean use_plt = FALSE;
48229727 5212
99059e56
RM		 5213 key.from = base_vma + i;
5214 found = (struct a8_erratum_reloc *)
5215 bsearch (&key, a8_relocs, num_a8_relocs,
5216 sizeof (struct a8_erratum_reloc),
5217 &a8_reloc_compare);
48229727
JB		 5218
5219 if (found)
5220 {
5221 char *error_message = NULL;
5222 struct elf_link_hash_entry *entry;
5223
5224 /* We don't care about the error returned from this
99059e56 5225 function, only if there is glue or not. */
48229727
JB		 5226 entry = find_thumb_glue (info, found->sym_name,
5227 &error_message);
5228
5229 if (entry)
5230 found->non_a8_stub = TRUE;
5231
92750f34 5232 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5233 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5234 && found->hash->root.plt.offset != (bfd_vma) -1)
5235 use_plt = TRUE;
5236
5237 if (found->r_type == R_ARM_THM_CALL)
5238 {
35fc36a8
RS		 5239 if (found->branch_type == ST_BRANCH_TO_ARM
5240 || use_plt)
92750f34
DJ		 5241 force_target_arm = TRUE;
5242 else
5243 force_target_thumb = TRUE;
5244 }
48229727
JB		 5245 }
5246
99059e56 5247 /* Check if we have an offending branch instruction. */
48229727
JB		 5248
5249 if (found && found->non_a8_stub)
5250 /* We've already made a stub for this instruction, e.g.
5251 it's a long branch or a Thumb->ARM stub. Assume that
5252 stub will suffice to work around the A8 erratum (see
5253 setting of always_after_branch above). */
5254 ;
99059e56
RM		 5255 else if (is_bcc)
5256 {
5257 offset = (insn & 0x7ff) << 1;
5258 offset |= (insn & 0x3f0000) >> 4;
5259 offset |= (insn & 0x2000) ? 0x40000 : 0;
5260 offset |= (insn & 0x800) ? 0x80000 : 0;
5261 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5262 if (offset & 0x100000)
5263 offset |= ~ ((bfd_signed_vma) 0xfffff);
5264 stub_type = arm_stub_a8_veneer_b_cond;
5265 }
5266 else if (is_b || is_bl || is_blx)
5267 {
5268 int s = (insn & 0x4000000) != 0;
5269 int j1 = (insn & 0x2000) != 0;
5270 int j2 = (insn & 0x800) != 0;
5271 int i1 = !(j1 ^ s);
5272 int i2 = !(j2 ^ s);
5273
5274 offset = (insn & 0x7ff) << 1;
5275 offset |= (insn & 0x3ff0000) >> 4;
5276 offset |= i2 << 22;
5277 offset |= i1 << 23;
5278 offset |= s << 24;
5279 if (offset & 0x1000000)
5280 offset |= ~ ((bfd_signed_vma) 0xffffff);
5281
5282 if (is_blx)
5283 offset &= ~ ((bfd_signed_vma) 3);
5284
5285 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5286 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5287 }
5288
5289 if (stub_type != arm_stub_none)
5290 {
5291 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5292
5293 /* The original instruction is a BL, but the target is
99059e56 5294 an ARM instruction. If we were not making a stub,
48229727
JB		 5295 the BL would have been converted to a BLX. Use the
5296 BLX stub instead in that case. */
5297 if (htab->use_blx && force_target_arm
5298 && stub_type == arm_stub_a8_veneer_bl)
5299 {
5300 stub_type = arm_stub_a8_veneer_blx;
5301 is_blx = TRUE;
5302 is_bl = FALSE;
5303 }
5304 /* Conversely, if the original instruction was
5305 BLX but the target is Thumb mode, use the BL
5306 stub. */
5307 else if (force_target_thumb
5308 && stub_type == arm_stub_a8_veneer_blx)
5309 {
5310 stub_type = arm_stub_a8_veneer_bl;
5311 is_blx = FALSE;
5312 is_bl = TRUE;
5313 }
5314
99059e56
RM		 5315 if (is_blx)
5316 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5317
99059e56
RM		 5318 /* If we found a relocation, use the proper destination,
5319 not the offset in the (unrelocated) instruction.
48229727
JB		 5320 Note this is always done if we switched the stub type
5321 above. */
99059e56
RM		 5322 if (found)
5323 offset =
81694485 5324 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5325
99059e56
RM		 5326 /* If the stub will use a Thumb-mode branch to a
5327 PLT target, redirect it to the preceding Thumb
5328 entry point. */
5329 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5330 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5331
99059e56 5332 target = pc_for_insn + offset;
48229727 5333
99059e56
RM		 5334 /* The BLX stub is ARM-mode code. Adjust the offset to
5335 take the different PC value (+8 instead of +4) into
48229727 5336 account. */
99059e56
RM		 5337 if (stub_type == arm_stub_a8_veneer_blx)
5338 offset += 4;
5339
5340 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5341 {
5342 char *stub_name = NULL;
5343
5344 if (num_a8_fixes == a8_fix_table_size)
5345 {
5346 a8_fix_table_size *= 2;
5347 a8_fixes = (struct a8_erratum_fix *)
5348 bfd_realloc (a8_fixes,
5349 sizeof (struct a8_erratum_fix)
5350 * a8_fix_table_size);
5351 }
48229727 5352
eb7c4339
NS		 5353 if (num_a8_fixes < prev_num_a8_fixes)
5354 {
5355 /* If we're doing a subsequent scan,
5356 check if we've found the same fix as
5357 before, and try and reuse the stub
5358 name. */
5359 stub_name = a8_fixes[num_a8_fixes].stub_name;
5360 if ((a8_fixes[num_a8_fixes].section != section)
5361 || (a8_fixes[num_a8_fixes].offset != i))
5362 {
5363 free (stub_name);
5364 stub_name = NULL;
5365 *stub_changed_p = TRUE;
5366 }
5367 }
5368
5369 if (!stub_name)
5370 {
21d799b5 5371 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5372 if (stub_name != NULL)
5373 sprintf (stub_name, "%x:%x", section->id, i);
5374 }
48229727 5375
99059e56
RM		 5376 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5377 a8_fixes[num_a8_fixes].section = section;
5378 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5379 a8_fixes[num_a8_fixes].target_offset =
5380 target - base_vma;
99059e56
RM		 5381 a8_fixes[num_a8_fixes].orig_insn = insn;
5382 a8_fixes[num_a8_fixes].stub_name = stub_name;
5383 a8_fixes[num_a8_fixes].stub_type = stub_type;
5384 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5385 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5386
99059e56
RM		 5387 num_a8_fixes++;
5388 }
5389 }
5390 }
48229727 5391
99059e56
RM		 5392 i += insn_32bit ? 4 : 2;
5393 last_was_32bit = insn_32bit;
48229727 5394 last_was_branch = is_32bit_branch;
99059e56
RM		 5395 }
5396 }
48229727
JB		 5397
5398 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5399 free (contents);
48229727 5400 }
fe33d2fa 5401
48229727
JB		 5402 *a8_fixes_p = a8_fixes;
5403 *num_a8_fixes_p = num_a8_fixes;
5404 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5405
81694485 5406 return FALSE;
48229727
JB		 5407}
5408
b715f643
TP		 5409/* Create or update a stub entry depending on whether the stub can already be
5410 found in HTAB. The stub is identified by:
5411 - its type STUB_TYPE
5412 - its source branch (note that several can share the same stub) whose
5413 section and relocation (if any) are given by SECTION and IRELA
5414 respectively
5415 - its target symbol whose input section, hash, name, value and branch type
5416 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5417 respectively
5418
5419 If found, the value of the stub's target symbol is updated from SYM_VALUE
5420 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5421 TRUE and the stub entry is initialized.
5422
5423 Returns whether the stub could be successfully created or updated, or FALSE
5424 if an error occured. */
5425
5426static bfd_boolean
5427elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5428 enum elf32_arm_stub_type stub_type, asection *section,
5429 Elf_Internal_Rela *irela, asection *sym_sec,
5430 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5431 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5432 bfd_boolean *new_stub)
5433{
5434 const asection *id_sec;
5435 char *stub_name;
5436 struct elf32_arm_stub_hash_entry *stub_entry;
5437 unsigned int r_type;
4f4faa4d 5438 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5439
5440 BFD_ASSERT (stub_type != arm_stub_none);
5441 *new_stub = FALSE;
5442
4f4faa4d
TP		 5443 if (sym_claimed)
5444 stub_name = sym_name;
5445 else
5446 {
5447 BFD_ASSERT (irela);
5448 BFD_ASSERT (section);
b715f643 5449
4f4faa4d
TP		 5450 /* Support for grouping stub sections. */
5451 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5452
4f4faa4d
TP		 5453 /* Get the name of this stub. */
5454 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5455 stub_type);
5456 if (!stub_name)
5457 return FALSE;
5458 }
b715f643
TP		 5459
5460 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5461 FALSE);
5462 /* The proper stub has already been created, just update its value. */
5463 if (stub_entry != NULL)
5464 {
4f4faa4d
TP		 5465 if (!sym_claimed)
5466 free (stub_name);
b715f643
TP		 5467 stub_entry->target_value = sym_value;
5468 return TRUE;
5469 }
5470
daa4adae 5471 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5472 if (stub_entry == NULL)
5473 {
4f4faa4d
TP		 5474 if (!sym_claimed)
5475 free (stub_name);
b715f643
TP		 5476 return FALSE;
5477 }
5478
5479 stub_entry->target_value = sym_value;
5480 stub_entry->target_section = sym_sec;
5481 stub_entry->stub_type = stub_type;
5482 stub_entry->h = hash;
5483 stub_entry->branch_type = branch_type;
5484
4f4faa4d
TP		 5485 if (sym_claimed)
5486 stub_entry->output_name = sym_name;
5487 else
b715f643 5488 {
4f4faa4d
TP		 5489 if (sym_name == NULL)
5490 sym_name = "unnamed";
5491 stub_entry->output_name = (char *)
5492 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5493 + strlen (sym_name));
5494 if (stub_entry->output_name == NULL)
5495 {
5496 free (stub_name);
5497 return FALSE;
5498 }
b715f643 5499
4f4faa4d
TP		 5500 /* For historical reasons, use the existing names for ARM-to-Thumb and
5501 Thumb-to-ARM stubs. */
5502 r_type = ELF32_R_TYPE (irela->r_info);
5503 if ((r_type == (unsigned int) R_ARM_THM_CALL
5504 || r_type == (unsigned int) R_ARM_THM_JUMP24
5505 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5506 && branch_type == ST_BRANCH_TO_ARM)
5507 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5508 else if ((r_type == (unsigned int) R_ARM_CALL
5509 || r_type == (unsigned int) R_ARM_JUMP24)
5510 && branch_type == ST_BRANCH_TO_THUMB)
5511 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5512 else
5513 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5514 }
b715f643
TP		 5515
5516 *new_stub = TRUE;
5517 return TRUE;
5518}
5519
4ba2ef8f
TP		 5520/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5521 gateway veneer to transition from non secure to secure state and create them
5522 accordingly.
5523
5524 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5525 defines the conditions that govern Secure Gateway veneer creation for a
5526 given symbol <SYM> as follows:
5527 - it has function type
5528 - it has non local binding
5529 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5530 same type, binding and value as <SYM> (called normal symbol).
5531 An entry function can handle secure state transition itself in which case
5532 its special symbol would have a different value from the normal symbol.
5533
5534 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5535 entry mapping while HTAB gives the name to hash entry mapping.
5536
5537 If any secure gateway veneer is created, *STUB_CHANGED is set to TRUE. The
5538 return value gives whether a stub failed to be allocated. */
5539
5540static bfd_boolean
5541cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5542 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
5543 bfd_boolean *stub_changed)
5544{
5545 const struct elf_backend_data *bed;
5546 Elf_Internal_Shdr *symtab_hdr;
5547 unsigned i, j, sym_count, ext_start;
5548 Elf_Internal_Sym *cmse_sym, *local_syms;
5549 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5550 enum arm_st_branch_type branch_type;
5551 char *sym_name, *lsym_name;
5552 bfd_vma sym_value;
5553 asection *section;
5554 bfd_boolean is_v8m, new_stub, created_stub, cmse_invalid, ret = TRUE;
5555
5556 bed = get_elf_backend_data (input_bfd);
5557 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5558 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5559 ext_start = symtab_hdr->sh_info;
5560 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5561 && out_attr[Tag_CPU_arch_profile].i == 'M');
5562
5563 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5564 if (local_syms == NULL)
5565 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5566 symtab_hdr->sh_info, 0, NULL, NULL,
5567 NULL);
5568 if (symtab_hdr->sh_info && local_syms == NULL)
5569 return FALSE;
5570
5571 /* Scan symbols. */
5572 for (i = 0; i < sym_count; i++)
5573 {
5574 cmse_invalid = FALSE;
5575
5576 if (i < ext_start)
5577 {
5578 cmse_sym = &local_syms[i];
5579 /* Not a special symbol. */
5580 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5581 continue;
5582 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5583 symtab_hdr->sh_link,
5584 cmse_sym->st_name);
5585 /* Special symbol with local binding. */
5586 cmse_invalid = TRUE;
5587 }
5588 else
5589 {
5590 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5591 sym_name = (char *) cmse_hash->root.root.root.string;
5592
5593 /* Not a special symbol. */
5594 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5595 continue;
5596
5597 /* Special symbol has incorrect binding or type. */
5598 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5599 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5600 || cmse_hash->root.type != STT_FUNC)
5601 cmse_invalid = TRUE;
5602 }
5603
5604 if (!is_v8m)
5605 {
5606 (*_bfd_error_handler) (_("%B: Special symbol `%s' only allowed for "
5607 "ARMv8-M architecture or later."),
5608 input_bfd, sym_name);
5609 is_v8m = TRUE; /* Avoid multiple warning. */
5610 ret = FALSE;
5611 }
5612
5613 if (cmse_invalid)
5614 {
5615 (*_bfd_error_handler) (_("%B: invalid special symbol `%s'."),
5616 input_bfd, sym_name);
5617 (*_bfd_error_handler) (_("It must be a global or weak function "
5618 "symbol."));
5619 ret = FALSE;
5620 if (i < ext_start)
5621 continue;
5622 }
5623
5624 sym_name += strlen (CMSE_PREFIX);
5625 hash = (struct elf32_arm_link_hash_entry *)
5626 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5627
5628 /* No associated normal symbol or it is neither global nor weak. */
5629 if (!hash
5630 || (hash->root.root.type != bfd_link_hash_defined
5631 && hash->root.root.type != bfd_link_hash_defweak)
5632 || hash->root.type != STT_FUNC)
5633 {
5634 /* Initialize here to avoid warning about use of possibly
5635 uninitialized variable. */
5636 j = 0;
5637
5638 if (!hash)
5639 {
5640 /* Searching for a normal symbol with local binding. */
5641 for (; j < ext_start; j++)
5642 {
5643 lsym_name =
5644 bfd_elf_string_from_elf_section (input_bfd,
5645 symtab_hdr->sh_link,
5646 local_syms[j].st_name);
5647 if (!strcmp (sym_name, lsym_name))
5648 break;
5649 }
5650 }
5651
5652 if (hash || j < ext_start)
5653 {
5654 (*_bfd_error_handler)
5655 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
5656 (*_bfd_error_handler)
5657 (_("It must be a global or weak function symbol."));
5658 }
5659 else
5660 (*_bfd_error_handler)
5661 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5662 ret = FALSE;
5663 if (!hash)
5664 continue;
5665 }
5666
5667 sym_value = hash->root.root.u.def.value;
5668 section = hash->root.root.u.def.section;
5669
5670 if (cmse_hash->root.root.u.def.section != section)
5671 {
5672 (*_bfd_error_handler)
5673 (_("%B: `%s' and its special symbol are in different sections."),
5674 input_bfd, sym_name);
5675 ret = FALSE;
5676 }
5677 if (cmse_hash->root.root.u.def.value != sym_value)
5678 continue; /* Ignore: could be an entry function starting with SG. */
5679
5680 /* If this section is a link-once section that will be discarded, then
5681 don't create any stubs. */
5682 if (section->output_section == NULL)
5683 {
5684 (*_bfd_error_handler)
5685 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5686 continue;
5687 }
5688
5689 if (hash->root.size == 0)
5690 {
5691 (*_bfd_error_handler)
5692 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5693 ret = FALSE;
5694 }
5695
5696 if (!ret)
5697 continue;
5698 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
5699 created_stub
5700 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5701 NULL, NULL, section, hash, sym_name,
5702 sym_value, branch_type, &new_stub);
5703
5704 if (!created_stub)
5705 ret = FALSE;
5706 else
5707 {
5708 BFD_ASSERT (new_stub);
5709 *stub_changed = TRUE;
5710 }
5711 }
5712
5713 if (!symtab_hdr->contents)
5714 free (local_syms);
5715 return ret;
5716}
5717
906e58ca
NC		 5718/* Determine and set the size of the stub section for a final link.
5719
5720 The basic idea here is to examine all the relocations looking for
5721 PC-relative calls to a target that is unreachable with a "bl"
5722 instruction. */
5723
5724bfd_boolean
5725elf32_arm_size_stubs (bfd *output_bfd,
5726 bfd *stub_bfd,
5727 struct bfd_link_info *info,
5728 bfd_signed_vma group_size,
7a89b94e 5729 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 5730 asection *,
7a89b94e 5731 unsigned int),
906e58ca
NC		 5732 void (*layout_sections_again) (void))
5733{
4ba2ef8f 5734 obj_attribute *out_attr;
906e58ca 5735 bfd_size_type stub_group_size;
4ba2ef8f 5736 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 5737 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 5738 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 5739 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 5740 struct a8_erratum_reloc *a8_relocs = NULL;
5741 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
5742
4dfe6ac6
NC		 5743 if (htab == NULL)
5744 return FALSE;
5745
48229727
JB		 5746 if (htab->fix_cortex_a8)
5747 {
21d799b5 5748 a8_fixes = (struct a8_erratum_fix *)
99059e56 5749 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 5750 a8_relocs = (struct a8_erratum_reloc *)
99059e56 5751 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 5752 }
906e58ca
NC		 5753
5754 /* Propagate mach to stub bfd, because it may not have been
5755 finalized when we created stub_bfd. */
5756 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
5757 bfd_get_mach (output_bfd));
5758
5759 /* Stash our params away. */
5760 htab->stub_bfd = stub_bfd;
5761 htab->add_stub_section = add_stub_section;
5762 htab->layout_sections_again = layout_sections_again;
07d72278 5763 stubs_always_after_branch = group_size < 0;
48229727 5764
4ba2ef8f
TP		 5765 out_attr = elf_known_obj_attributes_proc (output_bfd);
5766 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
48229727
JB		 5767 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5768 as the first half of a 32-bit branch straddling two 4K pages. This is a
5769 crude way of enforcing that. */
5770 if (htab->fix_cortex_a8)
5771 stubs_always_after_branch = 1;
5772
906e58ca
NC		 5773 if (group_size < 0)
5774 stub_group_size = -group_size;
5775 else
5776 stub_group_size = group_size;
5777
5778 if (stub_group_size == 1)
5779 {
5780 /* Default values. */
5781 /* Thumb branch range is +-4MB has to be used as the default
5782 maximum size (a given section can contain both ARM and Thumb
5783 code, so the worst case has to be taken into account).
5784
5785 This value is 24K less than that, which allows for 2025
5786 12-byte stubs. If we exceed that, then we will fail to link.
5787 The user will have to relink with an explicit group size
5788 option. */
5789 stub_group_size = 4170000;
5790 }
5791
07d72278 5792 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 5793
3ae046cc
NS		 5794 /* If we're applying the cortex A8 fix, we need to determine the
5795 program header size now, because we cannot change it later --
5796 that could alter section placements. Notice the A8 erratum fix
5797 ends up requiring the section addresses to remain unchanged
5798 modulo the page size. That's something we cannot represent
5799 inside BFD, and we don't want to force the section alignment to
5800 be the page size. */
5801 if (htab->fix_cortex_a8)
5802 (*htab->layout_sections_again) ();
5803
906e58ca
NC		 5804 while (1)
5805 {
5806 bfd *input_bfd;
5807 unsigned int bfd_indx;
5808 asection *stub_sec;
d7c5bd02 5809 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 5810 bfd_boolean stub_changed = FALSE;
5811 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 5812
48229727 5813 num_a8_fixes = 0;
906e58ca
NC		 5814 for (input_bfd = info->input_bfds, bfd_indx = 0;
5815 input_bfd != NULL;
c72f2fb2 5816 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 5817 {
5818 Elf_Internal_Shdr *symtab_hdr;
5819 asection *section;
5820 Elf_Internal_Sym *local_syms = NULL;
5821
99059e56
RM		 5822 if (!is_arm_elf (input_bfd))
5823 continue;
adbcc655 5824
48229727
JB		 5825 num_a8_relocs = 0;
5826
906e58ca
NC		 5827 /* We'll need the symbol table in a second. */
5828 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5829 if (symtab_hdr->sh_info == 0)
5830 continue;
5831
4ba2ef8f
TP		 5832 /* Limit scan of symbols to object file whose profile is
5833 Microcontroller to not hinder performance in the general case. */
5834 if (m_profile && first_veneer_scan)
5835 {
5836 struct elf_link_hash_entry **sym_hashes;
5837
5838 sym_hashes = elf_sym_hashes (input_bfd);
5839 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
5840 &stub_changed))
5841 goto error_ret_free_local;
5842 }
5843
906e58ca
NC		 5844 /* Walk over each section attached to the input bfd. */
5845 for (section = input_bfd->sections;
5846 section != NULL;
5847 section = section->next)
5848 {
5849 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
5850
5851 /* If there aren't any relocs, then there's nothing more
5852 to do. */
5853 if ((section->flags & SEC_RELOC) == 0
5854 || section->reloc_count == 0
5855 || (section->flags & SEC_CODE) == 0)
5856 continue;
5857
5858 /* If this section is a link-once section that will be
5859 discarded, then don't create any stubs. */
5860 if (section->output_section == NULL
5861 || section->output_section->owner != output_bfd)
5862 continue;
5863
5864 /* Get the relocs. */
5865 internal_relocs
5866 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
5867 NULL, info->keep_memory);
5868 if (internal_relocs == NULL)
5869 goto error_ret_free_local;
5870
5871 /* Now examine each relocation. */
5872 irela = internal_relocs;
5873 irelaend = irela + section->reloc_count;
5874 for (; irela < irelaend; irela++)
5875 {
5876 unsigned int r_type, r_indx;
906e58ca
NC		 5877 asection *sym_sec;
5878 bfd_vma sym_value;
5879 bfd_vma destination;
5880 struct elf32_arm_link_hash_entry *hash;
7413f23f 5881 const char *sym_name;
34e77a92 5882 unsigned char st_type;
35fc36a8 5883 enum arm_st_branch_type branch_type;
48229727 5884 bfd_boolean created_stub = FALSE;
906e58ca
NC		 5885
5886 r_type = ELF32_R_TYPE (irela->r_info);
5887 r_indx = ELF32_R_SYM (irela->r_info);
5888
5889 if (r_type >= (unsigned int) R_ARM_max)
5890 {
5891 bfd_set_error (bfd_error_bad_value);
5892 error_ret_free_internal:
5893 if (elf_section_data (section)->relocs == NULL)
5894 free (internal_relocs);
15dd01b1
TP		 5895 /* Fall through. */
5896 error_ret_free_local:
5897 if (local_syms != NULL
5898 && (symtab_hdr->contents
5899 != (unsigned char *) local_syms))
5900 free (local_syms);
5901 return FALSE;
906e58ca 5902 }
b38cadfb 5903
0855e32b
NS		 5904 hash = NULL;
5905 if (r_indx >= symtab_hdr->sh_info)
5906 hash = elf32_arm_hash_entry
5907 (elf_sym_hashes (input_bfd)
5908 [r_indx - symtab_hdr->sh_info]);
b38cadfb 5909
0855e32b
NS		 5910 /* Only look for stubs on branch instructions, or
5911 non-relaxed TLSCALL */
906e58ca 5912 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 5913 && (r_type != (unsigned int) R_ARM_THM_CALL)
5914 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 5915 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
5916 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 5917 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 5918 && (r_type != (unsigned int) R_ARM_PLT32)
5919 && !((r_type == (unsigned int) R_ARM_TLS_CALL
5920 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5921 && r_type == elf32_arm_tls_transition
5922 (info, r_type, &hash->root)
5923 && ((hash ? hash->tls_type
5924 : (elf32_arm_local_got_tls_type
5925 (input_bfd)[r_indx]))
5926 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 5927 continue;
5928
5929 /* Now determine the call target, its name, value,
5930 section. */
5931 sym_sec = NULL;
5932 sym_value = 0;
5933 destination = 0;
7413f23f 5934 sym_name = NULL;
b38cadfb 5935
0855e32b
NS		 5936 if (r_type == (unsigned int) R_ARM_TLS_CALL
5937 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5938 {
5939 /* A non-relaxed TLS call. The target is the
5940 plt-resident trampoline and nothing to do
5941 with the symbol. */
5942 BFD_ASSERT (htab->tls_trampoline > 0);
5943 sym_sec = htab->root.splt;
5944 sym_value = htab->tls_trampoline;
5945 hash = 0;
34e77a92 5946 st_type = STT_FUNC;
35fc36a8 5947 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 5948 }
5949 else if (!hash)
906e58ca
NC		 5950 {
5951 /* It's a local symbol. */
5952 Elf_Internal_Sym *sym;
906e58ca
NC		 5953
5954 if (local_syms == NULL)
5955 {
5956 local_syms
5957 = (Elf_Internal_Sym *) symtab_hdr->contents;
5958 if (local_syms == NULL)
5959 local_syms
5960 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5961 symtab_hdr->sh_info, 0,
5962 NULL, NULL, NULL);
5963 if (local_syms == NULL)
5964 goto error_ret_free_internal;
5965 }
5966
5967 sym = local_syms + r_indx;
f6d250ce
TS		 5968 if (sym->st_shndx == SHN_UNDEF)
5969 sym_sec = bfd_und_section_ptr;
5970 else if (sym->st_shndx == SHN_ABS)
5971 sym_sec = bfd_abs_section_ptr;
5972 else if (sym->st_shndx == SHN_COMMON)
5973 sym_sec = bfd_com_section_ptr;
5974 else
5975 sym_sec =
5976 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
5977
ffcb4889
NS		 5978 if (!sym_sec)
5979 /* This is an undefined symbol. It can never
6a631e86 5980 be resolved. */
ffcb4889 5981 continue;
fe33d2fa 5982
906e58ca
NC		 5983 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
5984 sym_value = sym->st_value;
5985 destination = (sym_value + irela->r_addend
5986 + sym_sec->output_offset
5987 + sym_sec->output_section->vma);
34e77a92 5988 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 5989 branch_type =
5990 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 5991 sym_name
5992 = bfd_elf_string_from_elf_section (input_bfd,
5993 symtab_hdr->sh_link,
5994 sym->st_name);
906e58ca
NC		 5995 }
5996 else
5997 {
5998 /* It's an external symbol. */
906e58ca
NC		 5999 while (hash->root.root.type == bfd_link_hash_indirect
6000 || hash->root.root.type == bfd_link_hash_warning)
6001 hash = ((struct elf32_arm_link_hash_entry *)
6002 hash->root.root.u.i.link);
6003
6004 if (hash->root.root.type == bfd_link_hash_defined
6005 || hash->root.root.type == bfd_link_hash_defweak)
6006 {
6007 sym_sec = hash->root.root.u.def.section;
6008 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6009
6010 struct elf32_arm_link_hash_table *globals =
6011 elf32_arm_hash_table (info);
6012
6013 /* For a destination in a shared library,
6014 use the PLT stub as target address to
6015 decide whether a branch stub is
6016 needed. */
4dfe6ac6 6017 if (globals != NULL
362d30a1 6018 && globals->root.splt != NULL
4dfe6ac6 6019 && hash != NULL
022f8312
CL		 6020 && hash->root.plt.offset != (bfd_vma) -1)
6021 {
362d30a1 6022 sym_sec = globals->root.splt;
022f8312
CL		 6023 sym_value = hash->root.plt.offset;
6024 if (sym_sec->output_section != NULL)
6025 destination = (sym_value
6026 + sym_sec->output_offset
6027 + sym_sec->output_section->vma);
6028 }
6029 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6030 destination = (sym_value + irela->r_addend
6031 + sym_sec->output_offset
6032 + sym_sec->output_section->vma);
6033 }
69c5861e
CL		 6034 else if ((hash->root.root.type == bfd_link_hash_undefined)
6035 || (hash->root.root.type == bfd_link_hash_undefweak))
6036 {
6037 /* For a shared library, use the PLT stub as
6038 target address to decide whether a long
6039 branch stub is needed.
6040 For absolute code, they cannot be handled. */
6041 struct elf32_arm_link_hash_table *globals =
6042 elf32_arm_hash_table (info);
6043
4dfe6ac6 6044 if (globals != NULL
362d30a1 6045 && globals->root.splt != NULL
4dfe6ac6 6046 && hash != NULL
69c5861e
CL		 6047 && hash->root.plt.offset != (bfd_vma) -1)
6048 {
362d30a1 6049 sym_sec = globals->root.splt;
69c5861e
CL		 6050 sym_value = hash->root.plt.offset;
6051 if (sym_sec->output_section != NULL)
6052 destination = (sym_value
6053 + sym_sec->output_offset
6054 + sym_sec->output_section->vma);
6055 }
6056 else
6057 continue;
6058 }
906e58ca
NC		 6059 else
6060 {
6061 bfd_set_error (bfd_error_bad_value);
6062 goto error_ret_free_internal;
6063 }
34e77a92 6064 st_type = hash->root.type;
39d911fc
TP		 6065 branch_type =
6066 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6067 sym_name = hash->root.root.root.string;
906e58ca
NC		 6068 }
6069
48229727 6070 do
7413f23f 6071 {
b715f643
TP		 6072 bfd_boolean new_stub;
6073
48229727
JB		 6074 /* Determine what (if any) linker stub is needed. */
6075 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6076 st_type, &branch_type,
6077 hash, destination, sym_sec,
48229727
JB		 6078 input_bfd, sym_name);
6079 if (stub_type == arm_stub_none)
6080 break;
6081
48229727
JB		 6082 /* We've either created a stub for this reloc already,
6083 or we are about to. */
b715f643
TP		 6084 created_stub =
6085 elf32_arm_create_stub (htab, stub_type, section, irela,
6086 sym_sec, hash,
6087 (char *) sym_name, sym_value,
6088 branch_type, &new_stub);
7413f23f 6089
b715f643
TP		 6090 if (!created_stub)
6091 goto error_ret_free_internal;
6092 else if (!new_stub)
6093 break;
99059e56 6094 else
b715f643 6095 stub_changed = TRUE;
99059e56
RM		 6096 }
6097 while (0);
6098
6099 /* Look for relocations which might trigger Cortex-A8
6100 erratum. */
6101 if (htab->fix_cortex_a8
6102 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6103 || r_type == (unsigned int) R_ARM_THM_JUMP19
6104 || r_type == (unsigned int) R_ARM_THM_CALL
6105 || r_type == (unsigned int) R_ARM_THM_XPC22))
6106 {
6107 bfd_vma from = section->output_section->vma
6108 + section->output_offset
6109 + irela->r_offset;
6110
6111 if ((from & 0xfff) == 0xffe)
6112 {
6113 /* Found a candidate. Note we haven't checked the
6114 destination is within 4K here: if we do so (and
6115 don't create an entry in a8_relocs) we can't tell
6116 that a branch should have been relocated when
6117 scanning later. */
6118 if (num_a8_relocs == a8_reloc_table_size)
6119 {
6120 a8_reloc_table_size *= 2;
6121 a8_relocs = (struct a8_erratum_reloc *)
6122 bfd_realloc (a8_relocs,
6123 sizeof (struct a8_erratum_reloc)
6124 * a8_reloc_table_size);
6125 }
6126
6127 a8_relocs[num_a8_relocs].from = from;
6128 a8_relocs[num_a8_relocs].destination = destination;
6129 a8_relocs[num_a8_relocs].r_type = r_type;
6130 a8_relocs[num_a8_relocs].branch_type = branch_type;
6131 a8_relocs[num_a8_relocs].sym_name = sym_name;
6132 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6133 a8_relocs[num_a8_relocs].hash = hash;
6134
6135 num_a8_relocs++;
6136 }
6137 }
906e58ca
NC		 6138 }
6139
99059e56
RM		 6140 /* We're done with the internal relocs, free them. */
6141 if (elf_section_data (section)->relocs == NULL)
6142 free (internal_relocs);
6143 }
48229727 6144
99059e56 6145 if (htab->fix_cortex_a8)
48229727 6146 {
99059e56
RM		 6147 /* Sort relocs which might apply to Cortex-A8 erratum. */
6148 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6149 sizeof (struct a8_erratum_reloc),
99059e56 6150 &a8_reloc_compare);
48229727 6151
99059e56
RM		 6152 /* Scan for branches which might trigger Cortex-A8 erratum. */
6153 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6154 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6155 a8_relocs, num_a8_relocs,
6156 prev_num_a8_fixes, &stub_changed)
6157 != 0)
48229727 6158 goto error_ret_free_local;
5e681ec4 6159 }
7f991970
AM		 6160
6161 if (local_syms != NULL
6162 && symtab_hdr->contents != (unsigned char *) local_syms)
6163 {
6164 if (!info->keep_memory)
6165 free (local_syms);
6166 else
6167 symtab_hdr->contents = (unsigned char *) local_syms;
6168 }
5e681ec4
PB		 6169 }
6170
eb7c4339 6171 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6172 stub_changed = TRUE;
48229727 6173
906e58ca
NC		 6174 if (!stub_changed)
6175 break;
5e681ec4 6176
906e58ca
NC		 6177 /* OK, we've added some stubs. Find out the new size of the
6178 stub sections. */
6179 for (stub_sec = htab->stub_bfd->sections;
6180 stub_sec != NULL;
6181 stub_sec = stub_sec->next)
3e6b1042
DJ		 6182 {
6183 /* Ignore non-stub sections. */
6184 if (!strstr (stub_sec->name, STUB_SUFFIX))
6185 continue;
6186
6187 stub_sec->size = 0;
6188 }
b34b2d70 6189
d7c5bd02 6190 /* Compute stub section size, considering padding. */
906e58ca 6191 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6192 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6193 stub_type++)
6194 {
6195 int size, padding;
6196 asection **stub_sec_p;
6197
6198 padding = arm_dedicated_stub_section_padding (stub_type);
6199 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6200 /* Skip if no stub input section or no stub section padding
6201 required. */
6202 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6203 continue;
6204 /* Stub section padding required but no dedicated section. */
6205 BFD_ASSERT (stub_sec_p);
6206
6207 size = (*stub_sec_p)->size;
6208 size = (size + padding - 1) & ~(padding - 1);
6209 (*stub_sec_p)->size = size;
6210 }
906e58ca 6211
48229727
JB		 6212 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6213 if (htab->fix_cortex_a8)
99059e56
RM		 6214 for (i = 0; i < num_a8_fixes; i++)
6215 {
48229727 6216 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6217 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6218
6219 if (stub_sec == NULL)
7f991970 6220 return FALSE;
48229727 6221
99059e56
RM		 6222 stub_sec->size
6223 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6224 NULL);
6225 }
48229727
JB		 6226
6227
906e58ca
NC		 6228 /* Ask the linker to do its stuff. */
6229 (*htab->layout_sections_again) ();
4ba2ef8f 6230 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6231 }
6232
48229727
JB		 6233 /* Add stubs for Cortex-A8 erratum fixes now. */
6234 if (htab->fix_cortex_a8)
6235 {
6236 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6237 {
6238 struct elf32_arm_stub_hash_entry *stub_entry;
6239 char *stub_name = a8_fixes[i].stub_name;
6240 asection *section = a8_fixes[i].section;
6241 unsigned int section_id = a8_fixes[i].section->id;
6242 asection *link_sec = htab->stub_group[section_id].link_sec;
6243 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6244 const insn_sequence *template_sequence;
6245 int template_size, size = 0;
6246
6247 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6248 TRUE, FALSE);
6249 if (stub_entry == NULL)
6250 {
6251 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
6252 section->owner,
6253 stub_name);
6254 return FALSE;
6255 }
6256
6257 stub_entry->stub_sec = stub_sec;
6258 stub_entry->stub_offset = 0;
6259 stub_entry->id_sec = link_sec;
6260 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6261 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6262 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6263 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6264 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6265 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6266
99059e56
RM		 6267 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6268 &template_sequence,
6269 &template_size);
48229727 6270
99059e56
RM		 6271 stub_entry->stub_size = size;
6272 stub_entry->stub_template = template_sequence;
6273 stub_entry->stub_template_size = template_size;
6274 }
48229727
JB		 6275
6276 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6277 elf32_arm_write_section(). */
48229727
JB		 6278 htab->a8_erratum_fixes = a8_fixes;
6279 htab->num_a8_erratum_fixes = num_a8_fixes;
6280 }
6281 else
6282 {
6283 htab->a8_erratum_fixes = NULL;
6284 htab->num_a8_erratum_fixes = 0;
6285 }
906e58ca 6286 return TRUE;
5e681ec4
PB		 6287}
6288
906e58ca
NC		 6289/* Build all the stubs associated with the current output file. The
6290 stubs are kept in a hash table attached to the main linker hash
6291 table. We also set up the .plt entries for statically linked PIC
6292 functions here. This function is called via arm_elf_finish in the
6293 linker. */
252b5132 6294
906e58ca
NC		 6295bfd_boolean
6296elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6297{
906e58ca
NC		 6298 asection *stub_sec;
6299 struct bfd_hash_table *table;
6300 struct elf32_arm_link_hash_table *htab;
252b5132 6301
906e58ca 6302 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6303 if (htab == NULL)
6304 return FALSE;
252b5132 6305
906e58ca
NC		 6306 for (stub_sec = htab->stub_bfd->sections;
6307 stub_sec != NULL;
6308 stub_sec = stub_sec->next)
252b5132 6309 {
906e58ca
NC		 6310 bfd_size_type size;
6311
8029a119 6312 /* Ignore non-stub sections. */
906e58ca
NC		 6313 if (!strstr (stub_sec->name, STUB_SUFFIX))
6314 continue;
6315
d7c5bd02
TP		 6316 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
6317 must at least be done for stub section requiring padding. */
906e58ca 6318 size = stub_sec->size;
21d799b5 6319 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6320 if (stub_sec->contents == NULL && size != 0)
6321 return FALSE;
6322 stub_sec->size = 0;
252b5132
RH		 6323 }
6324
906e58ca
NC		 6325 /* Build the stubs as directed by the stub hash table. */
6326 table = &htab->stub_hash_table;
6327 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6328 if (htab->fix_cortex_a8)
6329 {
6330 /* Place the cortex a8 stubs last. */
6331 htab->fix_cortex_a8 = -1;
6332 bfd_hash_traverse (table, arm_build_one_stub, info);
6333 }
252b5132 6334
906e58ca 6335 return TRUE;
252b5132
RH		 6336}
6337
9b485d32
NC		 6338/* Locate the Thumb encoded calling stub for NAME. */
6339
252b5132 6340static struct elf_link_hash_entry *
57e8b36a
NC		 6341find_thumb_glue (struct bfd_link_info *link_info,
6342 const char *name,
f2a9dd69 6343 char **error_message)
252b5132
RH		 6344{
6345 char *tmp_name;
6346 struct elf_link_hash_entry *hash;
6347 struct elf32_arm_link_hash_table *hash_table;
6348
6349 /* We need a pointer to the armelf specific hash table. */
6350 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6351 if (hash_table == NULL)
6352 return NULL;
252b5132 6353
21d799b5 6354 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6355 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6356
6357 BFD_ASSERT (tmp_name);
6358
6359 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6360
6361 hash = elf_link_hash_lookup
b34976b6 6362 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6363
b1657152
AM		 6364 if (hash == NULL
6365 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6366 tmp_name, name) == -1)
6367 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6368
6369 free (tmp_name);
6370
6371 return hash;
6372}
6373
9b485d32
NC		 6374/* Locate the ARM encoded calling stub for NAME. */
6375
252b5132 6376static struct elf_link_hash_entry *
57e8b36a
NC		 6377find_arm_glue (struct bfd_link_info *link_info,
6378 const char *name,
f2a9dd69 6379 char **error_message)
252b5132
RH		 6380{
6381 char *tmp_name;
6382 struct elf_link_hash_entry *myh;
6383 struct elf32_arm_link_hash_table *hash_table;
6384
6385 /* We need a pointer to the elfarm specific hash table. */
6386 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6387 if (hash_table == NULL)
6388 return NULL;
252b5132 6389
21d799b5 6390 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6391 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6392
6393 BFD_ASSERT (tmp_name);
6394
6395 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6396
6397 myh = elf_link_hash_lookup
b34976b6 6398 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6399
b1657152
AM		 6400 if (myh == NULL
6401 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6402 tmp_name, name) == -1)
6403 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6404
6405 free (tmp_name);
6406
6407 return myh;
6408}
6409
8f6277f5 6410/* ARM->Thumb glue (static images):
252b5132
RH		 6411
6412 .arm
6413 __func_from_arm:
6414 ldr r12, __func_addr
6415 bx r12
6416 __func_addr:
906e58ca 6417 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6418
26079076
PB		 6419 (v5t static images)
6420 .arm
6421 __func_from_arm:
6422 ldr pc, __func_addr
6423 __func_addr:
906e58ca 6424 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6425
8f6277f5
PB		 6426 (relocatable images)
6427 .arm
6428 __func_from_arm:
6429 ldr r12, __func_offset
6430 add r12, r12, pc
6431 bx r12
6432 __func_offset:
8029a119 6433 .word func - . */
8f6277f5
PB		 6434
6435#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6436static const insn32 a2t1_ldr_insn = 0xe59fc000;
6437static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6438static const insn32 a2t3_func_addr_insn = 0x00000001;
6439
26079076
PB		 6440#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6441static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6442static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6443
8f6277f5
PB		 6444#define ARM2THUMB_PIC_GLUE_SIZE 16
6445static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6446static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6447static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6448
9b485d32 6449/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6450
8029a119
NC		 6451 .thumb .thumb
6452 .align 2 .align 2
6453 __func_from_thumb: __func_from_thumb:
6454 bx pc push {r6, lr}
6455 nop ldr r6, __func_addr
6456 .arm mov lr, pc
6457 b func bx r6
99059e56
RM		 6458 .arm
6459 ;; back_to_thumb
6460 ldmia r13! {r6, lr}
6461 bx lr
6462 __func_addr:
6463 .word func */
252b5132
RH		 6464
6465#define THUMB2ARM_GLUE_SIZE 8
6466static const insn16 t2a1_bx_pc_insn = 0x4778;
6467static const insn16 t2a2_noop_insn = 0x46c0;
6468static const insn32 t2a3_b_insn = 0xea000000;
6469
c7b8f16e 6470#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6471#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6472#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6473
845b51d6
PB		 6474#define ARM_BX_VENEER_SIZE 12
6475static const insn32 armbx1_tst_insn = 0xe3100001;
6476static const insn32 armbx2_moveq_insn = 0x01a0f000;
6477static const insn32 armbx3_bx_insn = 0xe12fff10;
6478
7e392df6 6479#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6480static void
6481arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6482{
6483 asection * s;
8029a119 6484 bfd_byte * contents;
252b5132 6485
8029a119 6486 if (size == 0)
3e6b1042
DJ		 6487 {
6488 /* Do not include empty glue sections in the output. */
6489 if (abfd != NULL)
6490 {
3d4d4302 6491 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6492 if (s != NULL)
6493 s->flags |= SEC_EXCLUDE;
6494 }
6495 return;
6496 }
252b5132 6497
8029a119 6498 BFD_ASSERT (abfd != NULL);
252b5132 6499
3d4d4302 6500 s = bfd_get_linker_section (abfd, name);
8029a119 6501 BFD_ASSERT (s != NULL);
252b5132 6502
21d799b5 6503 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6504
8029a119
NC		 6505 BFD_ASSERT (s->size == size);
6506 s->contents = contents;
6507}
906e58ca 6508
8029a119
NC		 6509bfd_boolean
6510bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6511{
6512 struct elf32_arm_link_hash_table * globals;
906e58ca 6513
8029a119
NC		 6514 globals = elf32_arm_hash_table (info);
6515 BFD_ASSERT (globals != NULL);
906e58ca 6516
8029a119
NC		 6517 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6518 globals->arm_glue_size,
6519 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6520
8029a119
NC		 6521 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6522 globals->thumb_glue_size,
6523 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6524
8029a119
NC		 6525 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6526 globals->vfp11_erratum_glue_size,
6527 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6528
a504d23a
LA		 6529 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6530 globals->stm32l4xx_erratum_glue_size,
6531 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6532
8029a119
NC		 6533 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6534 globals->bx_glue_size,
845b51d6
PB		 6535 ARM_BX_GLUE_SECTION_NAME);
6536
b34976b6 6537 return TRUE;
252b5132
RH		 6538}
6539
a4fd1a8e 6540/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6541 returns the symbol identifying the stub. */
6542
a4fd1a8e 6543static struct elf_link_hash_entry *
57e8b36a
NC		 6544record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6545 struct elf_link_hash_entry * h)
252b5132
RH		 6546{
6547 const char * name = h->root.root.string;
63b0f745 6548 asection * s;
252b5132
RH		 6549 char * tmp_name;
6550 struct elf_link_hash_entry * myh;
14a793b2 6551 struct bfd_link_hash_entry * bh;
252b5132 6552 struct elf32_arm_link_hash_table * globals;
dc810e39 6553 bfd_vma val;
2f475487 6554 bfd_size_type size;
252b5132
RH		 6555
6556 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6557 BFD_ASSERT (globals != NULL);
6558 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6559
3d4d4302 6560 s = bfd_get_linker_section
252b5132
RH		 6561 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6562
252b5132
RH		 6563 BFD_ASSERT (s != NULL);
6564
21d799b5 6565 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6566 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6567
6568 BFD_ASSERT (tmp_name);
6569
6570 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6571
6572 myh = elf_link_hash_lookup
b34976b6 6573 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6574
6575 if (myh != NULL)
6576 {
9b485d32 6577 /* We've already seen this guy. */
252b5132 6578 free (tmp_name);
a4fd1a8e 6579 return myh;
252b5132
RH		 6580 }
6581
57e8b36a
NC		 6582 /* The only trick here is using hash_table->arm_glue_size as the value.
6583 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6584 putting it. The +1 on the value marks that the stub has not been
6585 output yet - not that it is a Thumb function. */
14a793b2 6586 bh = NULL;
dc810e39
AM		 6587 val = globals->arm_glue_size + 1;
6588 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6589 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6590 NULL, TRUE, FALSE, &bh);
252b5132 6591
b7693d02
DJ		 6592 myh = (struct elf_link_hash_entry *) bh;
6593 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6594 myh->forced_local = 1;
6595
252b5132
RH		 6596 free (tmp_name);
6597
0e1862bb
L		 6598 if (bfd_link_pic (link_info)
6599 || globals->root.is_relocatable_executable
27e55c4d 6600 || globals->pic_veneer)
2f475487 6601 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6602 else if (globals->use_blx)
6603 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6604 else
2f475487
AM		 6605 size = ARM2THUMB_STATIC_GLUE_SIZE;
6606
6607 s->size += size;
6608 globals->arm_glue_size += size;
252b5132 6609
a4fd1a8e 6610 return myh;
252b5132
RH		 6611}
6612
845b51d6
PB		 6613/* Allocate space for ARMv4 BX veneers. */
6614
6615static void
6616record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6617{
6618 asection * s;
6619 struct elf32_arm_link_hash_table *globals;
6620 char *tmp_name;
6621 struct elf_link_hash_entry *myh;
6622 struct bfd_link_hash_entry *bh;
6623 bfd_vma val;
6624
6625 /* BX PC does not need a veneer. */
6626 if (reg == 15)
6627 return;
6628
6629 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 6630 BFD_ASSERT (globals != NULL);
6631 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6632
6633 /* Check if this veneer has already been allocated. */
6634 if (globals->bx_glue_offset[reg])
6635 return;
6636
3d4d4302 6637 s = bfd_get_linker_section
845b51d6
PB		 6638 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
6639
6640 BFD_ASSERT (s != NULL);
6641
6642 /* Add symbol for veneer. */
21d799b5
NC		 6643 tmp_name = (char *)
6644 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 6645
845b51d6 6646 BFD_ASSERT (tmp_name);
906e58ca 6647
845b51d6 6648 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 6649
845b51d6
PB		 6650 myh = elf_link_hash_lookup
6651 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6652
845b51d6 6653 BFD_ASSERT (myh == NULL);
906e58ca 6654
845b51d6
PB		 6655 bh = NULL;
6656 val = globals->bx_glue_size;
6657 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 6658 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6659 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 6660
6661 myh = (struct elf_link_hash_entry *) bh;
6662 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6663 myh->forced_local = 1;
6664
6665 s->size += ARM_BX_VENEER_SIZE;
6666 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
6667 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
6668}
6669
6670
c7b8f16e
JB		 6671/* Add an entry to the code/data map for section SEC. */
6672
6673static void
6674elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
6675{
6676 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
6677 unsigned int newidx;
906e58ca 6678
c7b8f16e
JB		 6679 if (sec_data->map == NULL)
6680 {
21d799b5 6681 sec_data->map = (elf32_arm_section_map *)
99059e56 6682 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 6683 sec_data->mapcount = 0;
6684 sec_data->mapsize = 1;
6685 }
906e58ca 6686
c7b8f16e 6687 newidx = sec_data->mapcount++;
906e58ca 6688
c7b8f16e
JB		 6689 if (sec_data->mapcount > sec_data->mapsize)
6690 {
6691 sec_data->mapsize *= 2;
21d799b5 6692 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 6693 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
6694 * sizeof (elf32_arm_section_map));
515ef31d
NC		 6695 }
6696
6697 if (sec_data->map)
6698 {
6699 sec_data->map[newidx].vma = vma;
6700 sec_data->map[newidx].type = type;
c7b8f16e 6701 }
c7b8f16e
JB		 6702}
6703
6704
6705/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6706 veneers are handled for now. */
6707
6708static bfd_vma
6709record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 6710 elf32_vfp11_erratum_list *branch,
6711 bfd *branch_bfd,
6712 asection *branch_sec,
6713 unsigned int offset)
c7b8f16e
JB		 6714{
6715 asection *s;
6716 struct elf32_arm_link_hash_table *hash_table;
6717 char *tmp_name;
6718 struct elf_link_hash_entry *myh;
6719 struct bfd_link_hash_entry *bh;
6720 bfd_vma val;
6721 struct _arm_elf_section_data *sec_data;
c7b8f16e 6722 elf32_vfp11_erratum_list *newerr;
906e58ca 6723
c7b8f16e 6724 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 6725 BFD_ASSERT (hash_table != NULL);
6726 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 6727
3d4d4302 6728 s = bfd_get_linker_section
c7b8f16e 6729 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 6730
c7b8f16e 6731 sec_data = elf32_arm_section_data (s);
906e58ca 6732
c7b8f16e 6733 BFD_ASSERT (s != NULL);
906e58ca 6734
21d799b5 6735 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 6736 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 6737
c7b8f16e 6738 BFD_ASSERT (tmp_name);
906e58ca 6739
c7b8f16e
JB		 6740 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
6741 hash_table->num_vfp11_fixes);
906e58ca 6742
c7b8f16e
JB		 6743 myh = elf_link_hash_lookup
6744 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6745
c7b8f16e 6746 BFD_ASSERT (myh == NULL);
906e58ca 6747
c7b8f16e
JB		 6748 bh = NULL;
6749 val = hash_table->vfp11_erratum_glue_size;
6750 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 6751 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6752 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 6753
6754 myh = (struct elf_link_hash_entry *) bh;
6755 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6756 myh->forced_local = 1;
6757
6758 /* Link veneer back to calling location. */
c7e2358a 6759 sec_data->erratumcount += 1;
21d799b5
NC		 6760 newerr = (elf32_vfp11_erratum_list *)
6761 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 6762
c7b8f16e
JB		 6763 newerr->type = VFP11_ERRATUM_ARM_VENEER;
6764 newerr->vma = -1;
6765 newerr->u.v.branch = branch;
6766 newerr->u.v.id = hash_table->num_vfp11_fixes;
6767 branch->u.b.veneer = newerr;
6768
6769 newerr->next = sec_data->erratumlist;
6770 sec_data->erratumlist = newerr;
6771
6772 /* A symbol for the return from the veneer. */
6773 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
6774 hash_table->num_vfp11_fixes);
6775
6776 myh = elf_link_hash_lookup
6777 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6778
c7b8f16e
JB		 6779 if (myh != NULL)
6780 abort ();
6781
6782 bh = NULL;
6783 val = offset + 4;
6784 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6785 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 6786
c7b8f16e
JB		 6787 myh = (struct elf_link_hash_entry *) bh;
6788 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6789 myh->forced_local = 1;
6790
6791 free (tmp_name);
906e58ca 6792
c7b8f16e
JB		 6793 /* Generate a mapping symbol for the veneer section, and explicitly add an
6794 entry for that symbol to the code/data map for the section. */
6795 if (hash_table->vfp11_erratum_glue_size == 0)
6796 {
6797 bh = NULL;
6798 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 6799 ever requires this erratum fix. */
c7b8f16e
JB		 6800 _bfd_generic_link_add_one_symbol (link_info,
6801 hash_table->bfd_of_glue_owner, "$a",
6802 BSF_LOCAL, s, 0, NULL,
99059e56 6803 TRUE, FALSE, &bh);
c7b8f16e
JB		 6804
6805 myh = (struct elf_link_hash_entry *) bh;
6806 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6807 myh->forced_local = 1;
906e58ca 6808
c7b8f16e 6809 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 6810 BFDs. We must make a note of this generated mapping symbol
6811 ourselves so that code byteswapping works properly in
6812 elf32_arm_write_section. */
c7b8f16e
JB		 6813 elf32_arm_section_map_add (s, 'a', 0);
6814 }
906e58ca 6815
c7b8f16e
JB		 6816 s->size += VFP11_ERRATUM_VENEER_SIZE;
6817 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
6818 hash_table->num_vfp11_fixes++;
906e58ca 6819
c7b8f16e
JB		 6820 /* The offset of the veneer. */
6821 return val;
6822}
6823
a504d23a
LA		 6824/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6825 veneers need to be handled because used only in Cortex-M. */
6826
6827static bfd_vma
6828record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
6829 elf32_stm32l4xx_erratum_list *branch,
6830 bfd *branch_bfd,
6831 asection *branch_sec,
6832 unsigned int offset,
6833 bfd_size_type veneer_size)
6834{
6835 asection *s;
6836 struct elf32_arm_link_hash_table *hash_table;
6837 char *tmp_name;
6838 struct elf_link_hash_entry *myh;
6839 struct bfd_link_hash_entry *bh;
6840 bfd_vma val;
6841 struct _arm_elf_section_data *sec_data;
6842 elf32_stm32l4xx_erratum_list *newerr;
6843
6844 hash_table = elf32_arm_hash_table (link_info);
6845 BFD_ASSERT (hash_table != NULL);
6846 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
6847
6848 s = bfd_get_linker_section
6849 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6850
6851 BFD_ASSERT (s != NULL);
6852
6853 sec_data = elf32_arm_section_data (s);
6854
6855 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
6856 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
6857
6858 BFD_ASSERT (tmp_name);
6859
6860 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
6861 hash_table->num_stm32l4xx_fixes);
6862
6863 myh = elf_link_hash_lookup
6864 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6865
6866 BFD_ASSERT (myh == NULL);
6867
6868 bh = NULL;
6869 val = hash_table->stm32l4xx_erratum_glue_size;
6870 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
6871 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6872 NULL, TRUE, FALSE, &bh);
6873
6874 myh = (struct elf_link_hash_entry *) bh;
6875 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6876 myh->forced_local = 1;
6877
6878 /* Link veneer back to calling location. */
6879 sec_data->stm32l4xx_erratumcount += 1;
6880 newerr = (elf32_stm32l4xx_erratum_list *)
6881 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
6882
6883 newerr->type = STM32L4XX_ERRATUM_VENEER;
6884 newerr->vma = -1;
6885 newerr->u.v.branch = branch;
6886 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
6887 branch->u.b.veneer = newerr;
6888
6889 newerr->next = sec_data->stm32l4xx_erratumlist;
6890 sec_data->stm32l4xx_erratumlist = newerr;
6891
6892 /* A symbol for the return from the veneer. */
6893 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
6894 hash_table->num_stm32l4xx_fixes);
6895
6896 myh = elf_link_hash_lookup
6897 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6898
6899 if (myh != NULL)
6900 abort ();
6901
6902 bh = NULL;
6903 val = offset + 4;
6904 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6905 branch_sec, val, NULL, TRUE, FALSE, &bh);
6906
6907 myh = (struct elf_link_hash_entry *) bh;
6908 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6909 myh->forced_local = 1;
6910
6911 free (tmp_name);
6912
6913 /* Generate a mapping symbol for the veneer section, and explicitly add an
6914 entry for that symbol to the code/data map for the section. */
6915 if (hash_table->stm32l4xx_erratum_glue_size == 0)
6916 {
6917 bh = NULL;
6918 /* Creates a THUMB symbol since there is no other choice. */
6919 _bfd_generic_link_add_one_symbol (link_info,
6920 hash_table->bfd_of_glue_owner, "$t",
6921 BSF_LOCAL, s, 0, NULL,
6922 TRUE, FALSE, &bh);
6923
6924 myh = (struct elf_link_hash_entry *) bh;
6925 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6926 myh->forced_local = 1;
6927
6928 /* The elf32_arm_init_maps function only cares about symbols from input
6929 BFDs. We must make a note of this generated mapping symbol
6930 ourselves so that code byteswapping works properly in
6931 elf32_arm_write_section. */
6932 elf32_arm_section_map_add (s, 't', 0);
6933 }
6934
6935 s->size += veneer_size;
6936 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
6937 hash_table->num_stm32l4xx_fixes++;
6938
6939 /* The offset of the veneer. */
6940 return val;
6941}
6942
8029a119 6943#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 6944 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6945 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 6946
6947/* Create a fake section for use by the ARM backend of the linker. */
6948
6949static bfd_boolean
6950arm_make_glue_section (bfd * abfd, const char * name)
6951{
6952 asection * sec;
6953
3d4d4302 6954 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 6955 if (sec != NULL)
6956 /* Already made. */
6957 return TRUE;
6958
3d4d4302 6959 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 6960
6961 if (sec == NULL
6962 || !bfd_set_section_alignment (abfd, sec, 2))
6963 return FALSE;
6964
6965 /* Set the gc mark to prevent the section from being removed by garbage
6966 collection, despite the fact that no relocs refer to this section. */
6967 sec->gc_mark = 1;
6968
6969 return TRUE;
6970}
6971
1db37fe6
YG		 6972/* Set size of .plt entries. This function is called from the
6973 linker scripts in ld/emultempl/{armelf}.em. */
6974
6975void
6976bfd_elf32_arm_use_long_plt (void)
6977{
6978 elf32_arm_use_long_plt_entry = TRUE;
6979}
6980
8afb0e02
NC		 6981/* Add the glue sections to ABFD. This function is called from the
6982 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 6983
b34976b6 6984bfd_boolean
57e8b36a
NC		 6985bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
6986 struct bfd_link_info *info)
252b5132 6987{
a504d23a
LA		 6988 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
6989 bfd_boolean dostm32l4xx = globals
6990 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
6991 bfd_boolean addglue;
6992
8afb0e02
NC		 6993 /* If we are only performing a partial
6994 link do not bother adding the glue. */
0e1862bb 6995 if (bfd_link_relocatable (info))
b34976b6 6996 return TRUE;
252b5132 6997
a504d23a 6998 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 6999 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7000 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7001 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7002
7003 if (!dostm32l4xx)
7004 return addglue;
7005
7006 return addglue
7007 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7008}
7009
daa4adae
TP		 7010/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7011 ensures they are not marked for deletion by
7012 strip_excluded_output_sections () when veneers are going to be created
7013 later. Not doing so would trigger assert on empty section size in
7014 lang_size_sections_1 (). */
7015
7016void
7017bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7018{
7019 enum elf32_arm_stub_type stub_type;
7020
7021 /* If we are only performing a partial
7022 link do not bother adding the glue. */
7023 if (bfd_link_relocatable (info))
7024 return;
7025
7026 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7027 {
7028 asection *out_sec;
7029 const char *out_sec_name;
7030
7031 if (!arm_dedicated_stub_output_section_required (stub_type))
7032 continue;
7033
7034 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7035 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7036 if (out_sec != NULL)
7037 out_sec->flags |= SEC_KEEP;
7038 }
7039}
7040
8afb0e02
NC		 7041/* Select a BFD to be used to hold the sections used by the glue code.
7042 This function is called from the linker scripts in ld/emultempl/
8029a119 7043 {armelf/pe}.em. */
8afb0e02 7044
b34976b6 7045bfd_boolean
57e8b36a 7046bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7047{
7048 struct elf32_arm_link_hash_table *globals;
7049
7050 /* If we are only performing a partial link
7051 do not bother getting a bfd to hold the glue. */
0e1862bb 7052 if (bfd_link_relocatable (info))
b34976b6 7053 return TRUE;
8afb0e02 7054
b7693d02
DJ		 7055 /* Make sure we don't attach the glue sections to a dynamic object. */
7056 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7057
8afb0e02 7058 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7059 BFD_ASSERT (globals != NULL);
7060
7061 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7062 return TRUE;
8afb0e02 7063
252b5132
RH		 7064 /* Save the bfd for later use. */
7065 globals->bfd_of_glue_owner = abfd;
cedb70c5 7066
b34976b6 7067 return TRUE;
252b5132
RH		 7068}
7069
906e58ca
NC		 7070static void
7071check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7072{
2de70689
MGD		 7073 int cpu_arch;
7074
b38cadfb 7075 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7076 Tag_CPU_arch);
7077
7078 if (globals->fix_arm1176)
7079 {
7080 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7081 globals->use_blx = 1;
7082 }
7083 else
7084 {
7085 if (cpu_arch > TAG_CPU_ARCH_V4T)
7086 globals->use_blx = 1;
7087 }
39b41c9c
PB		 7088}
7089
b34976b6 7090bfd_boolean
57e8b36a 7091bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7092 struct bfd_link_info *link_info)
252b5132
RH		 7093{
7094 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7095 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7096 Elf_Internal_Rela *irel, *irelend;
7097 bfd_byte *contents = NULL;
252b5132
RH		 7098
7099 asection *sec;
7100 struct elf32_arm_link_hash_table *globals;
7101
7102 /* If we are only performing a partial link do not bother
7103 to construct any glue. */
0e1862bb 7104 if (bfd_link_relocatable (link_info))
b34976b6 7105 return TRUE;
252b5132 7106
39ce1a6a
NC		 7107 /* Here we have a bfd that is to be included on the link. We have a
7108 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7109 globals = elf32_arm_hash_table (link_info);
252b5132 7110 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7111
7112 check_use_blx (globals);
252b5132 7113
d504ffc8 7114 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7115 {
d003868e
AM		 7116 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7117 abfd);
e489d0ae
PB		 7118 return FALSE;
7119 }
f21f3fe0 7120
39ce1a6a
NC		 7121 /* PR 5398: If we have not decided to include any loadable sections in
7122 the output then we will not have a glue owner bfd. This is OK, it
7123 just means that there is nothing else for us to do here. */
7124 if (globals->bfd_of_glue_owner == NULL)
7125 return TRUE;
7126
252b5132
RH		 7127 /* Rummage around all the relocs and map the glue vectors. */
7128 sec = abfd->sections;
7129
7130 if (sec == NULL)
b34976b6 7131 return TRUE;
252b5132
RH		 7132
7133 for (; sec != NULL; sec = sec->next)
7134 {
7135 if (sec->reloc_count == 0)
7136 continue;
7137
2f475487
AM		 7138 if ((sec->flags & SEC_EXCLUDE) != 0)
7139 continue;
7140
0ffa91dd 7141 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7142
9b485d32 7143 /* Load the relocs. */
6cdc0ccc 7144 internal_relocs
906e58ca 7145 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7146
6cdc0ccc
AM		 7147 if (internal_relocs == NULL)
7148 goto error_return;
252b5132 7149
6cdc0ccc
AM		 7150 irelend = internal_relocs + sec->reloc_count;
7151 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7152 {
7153 long r_type;
7154 unsigned long r_index;
252b5132
RH		 7155
7156 struct elf_link_hash_entry *h;
7157
7158 r_type = ELF32_R_TYPE (irel->r_info);
7159 r_index = ELF32_R_SYM (irel->r_info);
7160
9b485d32 7161 /* These are the only relocation types we care about. */
ba96a88f 7162 if ( r_type != R_ARM_PC24
845b51d6 7163 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7164 continue;
7165
7166 /* Get the section contents if we haven't done so already. */
7167 if (contents == NULL)
7168 {
7169 /* Get cached copy if it exists. */
7170 if (elf_section_data (sec)->this_hdr.contents != NULL)
7171 contents = elf_section_data (sec)->this_hdr.contents;
7172 else
7173 {
7174 /* Go get them off disk. */
57e8b36a 7175 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7176 goto error_return;
7177 }
7178 }
7179
845b51d6
PB		 7180 if (r_type == R_ARM_V4BX)
7181 {
7182 int reg;
7183
7184 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7185 record_arm_bx_glue (link_info, reg);
7186 continue;
7187 }
7188
a7c10850 7189 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7190 h = NULL;
7191
9b485d32 7192 /* We don't care about local symbols. */
252b5132
RH		 7193 if (r_index < symtab_hdr->sh_info)
7194 continue;
7195
9b485d32 7196 /* This is an external symbol. */
252b5132
RH		 7197 r_index -= symtab_hdr->sh_info;
7198 h = (struct elf_link_hash_entry *)
7199 elf_sym_hashes (abfd)[r_index];
7200
7201 /* If the relocation is against a static symbol it must be within
7202 the current section and so cannot be a cross ARM/Thumb relocation. */
7203 if (h == NULL)
7204 continue;
7205
d504ffc8
DJ		 7206 /* If the call will go through a PLT entry then we do not need
7207 glue. */
362d30a1 7208 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7209 continue;
7210
252b5132
RH		 7211 switch (r_type)
7212 {
7213 case R_ARM_PC24:
7214 /* This one is a call from arm code. We need to look up
99059e56
RM		 7215 the target of the call. If it is a thumb target, we
7216 insert glue. */
39d911fc
TP		 7217 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7218 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7219 record_arm_to_thumb_glue (link_info, h);
7220 break;
7221
252b5132 7222 default:
c6596c5e 7223 abort ();
252b5132
RH		 7224 }
7225 }
6cdc0ccc
AM		 7226
7227 if (contents != NULL
7228 && elf_section_data (sec)->this_hdr.contents != contents)
7229 free (contents);
7230 contents = NULL;
7231
7232 if (internal_relocs != NULL
7233 && elf_section_data (sec)->relocs != internal_relocs)
7234 free (internal_relocs);
7235 internal_relocs = NULL;
252b5132
RH		 7236 }
7237
b34976b6 7238 return TRUE;
9a5aca8c 7239
252b5132 7240error_return:
6cdc0ccc
AM		 7241 if (contents != NULL
7242 && elf_section_data (sec)->this_hdr.contents != contents)
7243 free (contents);
7244 if (internal_relocs != NULL
7245 && elf_section_data (sec)->relocs != internal_relocs)
7246 free (internal_relocs);
9a5aca8c 7247
b34976b6 7248 return FALSE;
252b5132 7249}
7e392df6 7250#endif
252b5132 7251
eb043451 7252
c7b8f16e
JB		 7253/* Initialise maps of ARM/Thumb/data for input BFDs. */
7254
7255void
7256bfd_elf32_arm_init_maps (bfd *abfd)
7257{
7258 Elf_Internal_Sym *isymbuf;
7259 Elf_Internal_Shdr *hdr;
7260 unsigned int i, localsyms;
7261
af1f4419
NC		 7262 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7263 if (! is_arm_elf (abfd))
7264 return;
7265
c7b8f16e
JB		 7266 if ((abfd->flags & DYNAMIC) != 0)
7267 return;
7268
0ffa91dd 7269 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7270 localsyms = hdr->sh_info;
7271
7272 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7273 should contain the number of local symbols, which should come before any
7274 global symbols. Mapping symbols are always local. */
7275 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7276 NULL);
7277
7278 /* No internal symbols read? Skip this BFD. */
7279 if (isymbuf == NULL)
7280 return;
7281
7282 for (i = 0; i < localsyms; i++)
7283 {
7284 Elf_Internal_Sym *isym = &isymbuf[i];
7285 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7286 const char *name;
906e58ca 7287
c7b8f16e 7288 if (sec != NULL
99059e56
RM		 7289 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7290 {
7291 name = bfd_elf_string_from_elf_section (abfd,
7292 hdr->sh_link, isym->st_name);
906e58ca 7293
99059e56 7294 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7295 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7296 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7297 }
c7b8f16e
JB		 7298 }
7299}
7300
7301
48229727
JB		 7302/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7303 say what they wanted. */
7304
7305void
7306bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7307{
7308 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7309 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7310
4dfe6ac6
NC		 7311 if (globals == NULL)
7312 return;
7313
48229727
JB		 7314 if (globals->fix_cortex_a8 == -1)
7315 {
7316 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7317 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7318 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7319 || out_attr[Tag_CPU_arch_profile].i == 0))
7320 globals->fix_cortex_a8 = 1;
7321 else
7322 globals->fix_cortex_a8 = 0;
7323 }
7324}
7325
7326
c7b8f16e
JB		 7327void
7328bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7329{
7330 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7331 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7332
4dfe6ac6
NC		 7333 if (globals == NULL)
7334 return;
c7b8f16e
JB		 7335 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7336 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7337 {
7338 switch (globals->vfp11_fix)
99059e56
RM		 7339 {
7340 case BFD_ARM_VFP11_FIX_DEFAULT:
7341 case BFD_ARM_VFP11_FIX_NONE:
7342 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7343 break;
7344
7345 default:
7346 /* Give a warning, but do as the user requests anyway. */
7347 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
7348 "workaround is not necessary for target architecture"), obfd);
7349 }
c7b8f16e
JB		 7350 }
7351 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7352 /* For earlier architectures, we might need the workaround, but do not
7353 enable it by default. If users is running with broken hardware, they
7354 must enable the erratum fix explicitly. */
7355 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7356}
7357
a504d23a
LA		 7358void
7359bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7360{
7361 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7362 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7363
7364 if (globals == NULL)
7365 return;
7366
7367 /* We assume only Cortex-M4 may require the fix. */
7368 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7369 || out_attr[Tag_CPU_arch_profile].i != 'M')
7370 {
7371 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7372 /* Give a warning, but do as the user requests anyway. */
7373 (*_bfd_error_handler)
7374 (_("%B: warning: selected STM32L4XX erratum "
7375 "workaround is not necessary for target architecture"), obfd);
7376 }
7377}
c7b8f16e 7378
906e58ca
NC		 7379enum bfd_arm_vfp11_pipe
7380{
c7b8f16e
JB		 7381 VFP11_FMAC,
7382 VFP11_LS,
7383 VFP11_DS,
7384 VFP11_BAD
7385};
7386
7387/* Return a VFP register number. This is encoded as RX:X for single-precision
7388 registers, or X:RX for double-precision registers, where RX is the group of
7389 four bits in the instruction encoding and X is the single extension bit.
7390 RX and X fields are specified using their lowest (starting) bit. The return
7391 value is:
7392
7393 0...31: single-precision registers s0...s31
7394 32...63: double-precision registers d0...d31.
906e58ca 7395
c7b8f16e
JB		 7396 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7397 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7398
c7b8f16e
JB		 7399static unsigned int
7400bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7401 unsigned int x)
c7b8f16e
JB		 7402{
7403 if (is_double)
7404 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7405 else
7406 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7407}
7408
7409/* Set bits in *WMASK according to a register number REG as encoded by
7410 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7411
7412static void
7413bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7414{
7415 if (reg < 32)
7416 *wmask |= 1 << reg;
7417 else if (reg < 48)
7418 *wmask |= 3 << ((reg - 32) * 2);
7419}
7420
7421/* Return TRUE if WMASK overwrites anything in REGS. */
7422
7423static bfd_boolean
7424bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7425{
7426 int i;
906e58ca 7427
c7b8f16e
JB		 7428 for (i = 0; i < numregs; i++)
7429 {
7430 unsigned int reg = regs[i];
7431
7432 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7433 return TRUE;
906e58ca 7434
c7b8f16e
JB		 7435 reg -= 32;
7436
7437 if (reg >= 16)
99059e56 7438 continue;
906e58ca 7439
c7b8f16e 7440 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7441 return TRUE;
c7b8f16e 7442 }
906e58ca 7443
c7b8f16e
JB		 7444 return FALSE;
7445}
7446
7447/* In this function, we're interested in two things: finding input registers
7448 for VFP data-processing instructions, and finding the set of registers which
7449 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7450 hold the written set, so FLDM etc. are easy to deal with (we're only
7451 interested in 32 SP registers or 16 dp registers, due to the VFP version
7452 implemented by the chip in question). DP registers are marked by setting
7453 both SP registers in the write mask). */
7454
7455static enum bfd_arm_vfp11_pipe
7456bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7457 int *numregs)
c7b8f16e 7458{
91d6fa6a 7459 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7460 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7461
7462 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7463 {
7464 unsigned int pqrs;
7465 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7466 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7467
7468 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7469 | ((insn & 0x00300000) >> 19)
7470 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7471
7472 switch (pqrs)
99059e56
RM		 7473 {
7474 case 0: /* fmac[sd]. */
7475 case 1: /* fnmac[sd]. */
7476 case 2: /* fmsc[sd]. */
7477 case 3: /* fnmsc[sd]. */
7478 vpipe = VFP11_FMAC;
7479 bfd_arm_vfp11_write_mask (destmask, fd);
7480 regs[0] = fd;
7481 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7482 regs[2] = fm;
7483 *numregs = 3;
7484 break;
7485
7486 case 4: /* fmul[sd]. */
7487 case 5: /* fnmul[sd]. */
7488 case 6: /* fadd[sd]. */
7489 case 7: /* fsub[sd]. */
7490 vpipe = VFP11_FMAC;
7491 goto vfp_binop;
7492
7493 case 8: /* fdiv[sd]. */
7494 vpipe = VFP11_DS;
7495 vfp_binop:
7496 bfd_arm_vfp11_write_mask (destmask, fd);
7497 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7498 regs[1] = fm;
7499 *numregs = 2;
7500 break;
7501
7502 case 15: /* extended opcode. */
7503 {
7504 unsigned int extn = ((insn >> 15) & 0x1e)
7505 | ((insn >> 7) & 1);
7506
7507 switch (extn)
7508 {
7509 case 0: /* fcpy[sd]. */
7510 case 1: /* fabs[sd]. */
7511 case 2: /* fneg[sd]. */
7512 case 8: /* fcmp[sd]. */
7513 case 9: /* fcmpe[sd]. */
7514 case 10: /* fcmpz[sd]. */
7515 case 11: /* fcmpez[sd]. */
7516 case 16: /* fuito[sd]. */
7517 case 17: /* fsito[sd]. */
7518 case 24: /* ftoui[sd]. */
7519 case 25: /* ftouiz[sd]. */
7520 case 26: /* ftosi[sd]. */
7521 case 27: /* ftosiz[sd]. */
7522 /* These instructions will not bounce due to underflow. */
7523 *numregs = 0;
7524 vpipe = VFP11_FMAC;
7525 break;
7526
7527 case 3: /* fsqrt[sd]. */
7528 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7529 registers to cause the erratum in previous instructions. */
7530 bfd_arm_vfp11_write_mask (destmask, fd);
7531 vpipe = VFP11_DS;
7532 break;
7533
7534 case 15: /* fcvt{ds,sd}. */
7535 {
7536 int rnum = 0;
7537
7538 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7539
7540 /* Only FCVTSD can underflow. */
99059e56
RM		 7541 if ((insn & 0x100) != 0)
7542 regs[rnum++] = fm;
c7b8f16e 7543
99059e56 7544 *numregs = rnum;
c7b8f16e 7545
99059e56
RM		 7546 vpipe = VFP11_FMAC;
7547 }
7548 break;
c7b8f16e 7549
99059e56
RM		 7550 default:
7551 return VFP11_BAD;
7552 }
7553 }
7554 break;
c7b8f16e 7555
99059e56
RM		 7556 default:
7557 return VFP11_BAD;
7558 }
c7b8f16e
JB		 7559 }
7560 /* Two-register transfer. */
7561 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7562 {
7563 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7564
c7b8f16e
JB		 7565 if ((insn & 0x100000) == 0)
7566 {
99059e56
RM		 7567 if (is_double)
7568 bfd_arm_vfp11_write_mask (destmask, fm);
7569 else
7570 {
7571 bfd_arm_vfp11_write_mask (destmask, fm);
7572 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7573 }
c7b8f16e
JB		 7574 }
7575
91d6fa6a 7576 vpipe = VFP11_LS;
c7b8f16e
JB		 7577 }
7578 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7579 {
7580 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7581 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7582
c7b8f16e 7583 switch (puw)
99059e56
RM		 7584 {
7585 case 0: /* Two-reg transfer. We should catch these above. */
7586 abort ();
906e58ca 7587
99059e56
RM		 7588 case 2: /* fldm[sdx]. */
7589 case 3:
7590 case 5:
7591 {
7592 unsigned int i, offset = insn & 0xff;
c7b8f16e 7593
99059e56
RM		 7594 if (is_double)
7595 offset >>= 1;
c7b8f16e 7596
99059e56
RM		 7597 for (i = fd; i < fd + offset; i++)
7598 bfd_arm_vfp11_write_mask (destmask, i);
7599 }
7600 break;
906e58ca 7601
99059e56
RM		 7602 case 4: /* fld[sd]. */
7603 case 6:
7604 bfd_arm_vfp11_write_mask (destmask, fd);
7605 break;
906e58ca 7606
99059e56
RM		 7607 default:
7608 return VFP11_BAD;
7609 }
c7b8f16e 7610
91d6fa6a 7611 vpipe = VFP11_LS;
c7b8f16e
JB		 7612 }
7613 /* Single-register transfer. Note L==0. */
7614 else if ((insn & 0x0f100e10) == 0x0e000a10)
7615 {
7616 unsigned int opcode = (insn >> 21) & 7;
7617 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
7618
7619 switch (opcode)
99059e56
RM		 7620 {
7621 case 0: /* fmsr/fmdlr. */
7622 case 1: /* fmdhr. */
7623 /* Mark fmdhr and fmdlr as writing to the whole of the DP
7624 destination register. I don't know if this is exactly right,
7625 but it is the conservative choice. */
7626 bfd_arm_vfp11_write_mask (destmask, fn);
7627 break;
7628
7629 case 7: /* fmxr. */
7630 break;
7631 }
c7b8f16e 7632
91d6fa6a 7633 vpipe = VFP11_LS;
c7b8f16e
JB		 7634 }
7635
91d6fa6a 7636 return vpipe;
c7b8f16e
JB		 7637}
7638
7639
7640static int elf32_arm_compare_mapping (const void * a, const void * b);
7641
7642
7643/* Look for potentially-troublesome code sequences which might trigger the
7644 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
7645 (available from ARM) for details of the erratum. A short version is
7646 described in ld.texinfo. */
7647
7648bfd_boolean
7649bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
7650{
7651 asection *sec;
7652 bfd_byte *contents = NULL;
7653 int state = 0;
7654 int regs[3], numregs = 0;
7655 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7656 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 7657
4dfe6ac6
NC		 7658 if (globals == NULL)
7659 return FALSE;
7660
c7b8f16e
JB		 7661 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
7662 The states transition as follows:
906e58ca 7663
c7b8f16e 7664 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 7665 A VFP FMAC-pipeline instruction has been seen. Fill
7666 regs[0]..regs[numregs-1] with its input operands. Remember this
7667 instruction in 'first_fmac'.
c7b8f16e
JB		 7668
7669 1 -> 2
99059e56
RM		 7670 Any instruction, except for a VFP instruction which overwrites
7671 regs[*].
906e58ca 7672
c7b8f16e
JB		 7673 1 -> 3 [ -> 0 ] or
7674 2 -> 3 [ -> 0 ]
99059e56
RM		 7675 A VFP instruction has been seen which overwrites any of regs[*].
7676 We must make a veneer! Reset state to 0 before examining next
7677 instruction.
906e58ca 7678
c7b8f16e 7679 2 -> 0
99059e56
RM		 7680 If we fail to match anything in state 2, reset to state 0 and reset
7681 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 7682
7683 If the VFP11 vector mode is in use, there must be at least two unrelated
7684 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 7685 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 7686
7687 /* If we are only performing a partial link do not bother
7688 to construct any glue. */
0e1862bb 7689 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 7690 return TRUE;
7691
0ffa91dd
NC		 7692 /* Skip if this bfd does not correspond to an ELF image. */
7693 if (! is_arm_elf (abfd))
7694 return TRUE;
906e58ca 7695
c7b8f16e
JB		 7696 /* We should have chosen a fix type by the time we get here. */
7697 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
7698
7699 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
7700 return TRUE;
2e6030b9 7701
33a7ffc2
JM		 7702 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7703 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7704 return TRUE;
7705
c7b8f16e
JB		 7706 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7707 {
7708 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
7709 struct _arm_elf_section_data *sec_data;
7710
7711 /* If we don't have executable progbits, we're not interested in this
99059e56 7712 section. Also skip if section is to be excluded. */
c7b8f16e 7713 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 7714 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7715 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 7716 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 7717 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 7718 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
7719 continue;
c7b8f16e
JB		 7720
7721 sec_data = elf32_arm_section_data (sec);
906e58ca 7722
c7b8f16e 7723 if (sec_data->mapcount == 0)
99059e56 7724 continue;
906e58ca 7725
c7b8f16e
JB		 7726 if (elf_section_data (sec)->this_hdr.contents != NULL)
7727 contents = elf_section_data (sec)->this_hdr.contents;
7728 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7729 goto error_return;
7730
7731 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7732 elf32_arm_compare_mapping);
7733
7734 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 7735 {
7736 unsigned int span_start = sec_data->map[span].vma;
7737 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 7738 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 7739 char span_type = sec_data->map[span].type;
7740
7741 /* FIXME: Only ARM mode is supported at present. We may need to
7742 support Thumb-2 mode also at some point. */
7743 if (span_type != 'a')
7744 continue;
7745
7746 for (i = span_start; i < span_end;)
7747 {
7748 unsigned int next_i = i + 4;
7749 unsigned int insn = bfd_big_endian (abfd)
7750 ? (contents[i] << 24)
7751 | (contents[i + 1] << 16)
7752 | (contents[i + 2] << 8)
7753 | contents[i + 3]
7754 : (contents[i + 3] << 24)
7755 | (contents[i + 2] << 16)
7756 | (contents[i + 1] << 8)
7757 | contents[i];
7758 unsigned int writemask = 0;
7759 enum bfd_arm_vfp11_pipe vpipe;
7760
7761 switch (state)
7762 {
7763 case 0:
7764 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
7765 &numregs);
7766 /* I'm assuming the VFP11 erratum can trigger with denorm
7767 operands on either the FMAC or the DS pipeline. This might
7768 lead to slightly overenthusiastic veneer insertion. */
7769 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
7770 {
7771 state = use_vector ? 1 : 2;
7772 first_fmac = i;
7773 veneer_of_insn = insn;
7774 }
7775 break;
7776
7777 case 1:
7778 {
7779 int other_regs[3], other_numregs;
7780 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7781 other_regs,
99059e56
RM		 7782 &other_numregs);
7783 if (vpipe != VFP11_BAD
7784 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7785 numregs))
99059e56
RM		 7786 state = 3;
7787 else
7788 state = 2;
7789 }
7790 break;
7791
7792 case 2:
7793 {
7794 int other_regs[3], other_numregs;
7795 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7796 other_regs,
99059e56
RM		 7797 &other_numregs);
7798 if (vpipe != VFP11_BAD
7799 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7800 numregs))
99059e56
RM		 7801 state = 3;
7802 else
7803 {
7804 state = 0;
7805 next_i = first_fmac + 4;
7806 }
7807 }
7808 break;
7809
7810 case 3:
7811 abort (); /* Should be unreachable. */
7812 }
7813
7814 if (state == 3)
7815 {
7816 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
7817 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7818
7819 elf32_arm_section_data (sec)->erratumcount += 1;
7820
7821 newerr->u.b.vfp_insn = veneer_of_insn;
7822
7823 switch (span_type)
7824 {
7825 case 'a':
7826 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
7827 break;
7828
7829 default:
7830 abort ();
7831 }
7832
7833 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 7834 first_fmac);
7835
99059e56 7836 newerr->vma = -1;
c7b8f16e 7837
99059e56
RM		 7838 newerr->next = sec_data->erratumlist;
7839 sec_data->erratumlist = newerr;
c7b8f16e 7840
99059e56
RM		 7841 state = 0;
7842 }
c7b8f16e 7843
99059e56
RM		 7844 i = next_i;
7845 }
7846 }
906e58ca 7847
c7b8f16e 7848 if (contents != NULL
99059e56
RM		 7849 && elf_section_data (sec)->this_hdr.contents != contents)
7850 free (contents);
c7b8f16e
JB		 7851 contents = NULL;
7852 }
7853
7854 return TRUE;
7855
7856error_return:
7857 if (contents != NULL
7858 && elf_section_data (sec)->this_hdr.contents != contents)
7859 free (contents);
906e58ca 7860
c7b8f16e
JB		 7861 return FALSE;
7862}
7863
7864/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7865 after sections have been laid out, using specially-named symbols. */
7866
7867void
7868bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
7869 struct bfd_link_info *link_info)
7870{
7871 asection *sec;
7872 struct elf32_arm_link_hash_table *globals;
7873 char *tmp_name;
906e58ca 7874
0e1862bb 7875 if (bfd_link_relocatable (link_info))
c7b8f16e 7876 return;
2e6030b9
MS		 7877
7878 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 7879 if (! is_arm_elf (abfd))
2e6030b9
MS		 7880 return;
7881
c7b8f16e 7882 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7883 if (globals == NULL)
7884 return;
906e58ca 7885
21d799b5 7886 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7887 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 7888
7889 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7890 {
7891 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7892 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 7893
c7b8f16e 7894 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 7895 {
7896 struct elf_link_hash_entry *myh;
7897 bfd_vma vma;
7898
7899 switch (errnode->type)
7900 {
7901 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
7902 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
7903 /* Find veneer symbol. */
7904 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 7905 errnode->u.b.veneer->u.v.id);
7906
99059e56
RM		 7907 myh = elf_link_hash_lookup
7908 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 7909
a504d23a
LA		 7910 if (myh == NULL)
7911 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7912 "`%s'"), abfd, tmp_name);
7913
7914 vma = myh->root.u.def.section->output_section->vma
7915 + myh->root.u.def.section->output_offset
7916 + myh->root.u.def.value;
7917
7918 errnode->u.b.veneer->vma = vma;
7919 break;
7920
7921 case VFP11_ERRATUM_ARM_VENEER:
7922 case VFP11_ERRATUM_THUMB_VENEER:
7923 /* Find return location. */
7924 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7925 errnode->u.v.id);
7926
7927 myh = elf_link_hash_lookup
7928 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7929
7930 if (myh == NULL)
7931 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7932 "`%s'"), abfd, tmp_name);
7933
7934 vma = myh->root.u.def.section->output_section->vma
7935 + myh->root.u.def.section->output_offset
7936 + myh->root.u.def.value;
7937
7938 errnode->u.v.branch->vma = vma;
7939 break;
7940
7941 default:
7942 abort ();
7943 }
7944 }
7945 }
7946
7947 free (tmp_name);
7948}
7949
7950/* Find virtual-memory addresses for STM32L4XX erratum veneers and
7951 return locations after sections have been laid out, using
7952 specially-named symbols. */
7953
7954void
7955bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
7956 struct bfd_link_info *link_info)
7957{
7958 asection *sec;
7959 struct elf32_arm_link_hash_table *globals;
7960 char *tmp_name;
7961
7962 if (bfd_link_relocatable (link_info))
7963 return;
7964
7965 /* Skip if this bfd does not correspond to an ELF image. */
7966 if (! is_arm_elf (abfd))
7967 return;
7968
7969 globals = elf32_arm_hash_table (link_info);
7970 if (globals == NULL)
7971 return;
7972
7973 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7974 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7975
7976 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7977 {
7978 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7979 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
7980
7981 for (; errnode != NULL; errnode = errnode->next)
7982 {
7983 struct elf_link_hash_entry *myh;
7984 bfd_vma vma;
7985
7986 switch (errnode->type)
7987 {
7988 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
7989 /* Find veneer symbol. */
7990 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7991 errnode->u.b.veneer->u.v.id);
7992
7993 myh = elf_link_hash_lookup
7994 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7995
7996 if (myh == NULL)
7997 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7998 "`%s'"), abfd, tmp_name);
7999
8000 vma = myh->root.u.def.section->output_section->vma
8001 + myh->root.u.def.section->output_offset
8002 + myh->root.u.def.value;
8003
8004 errnode->u.b.veneer->vma = vma;
8005 break;
8006
8007 case STM32L4XX_ERRATUM_VENEER:
8008 /* Find return location. */
8009 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8010 errnode->u.v.id);
8011
8012 myh = elf_link_hash_lookup
8013 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8014
8015 if (myh == NULL)
8016 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
8017 "`%s'"), abfd, tmp_name);
8018
8019 vma = myh->root.u.def.section->output_section->vma
8020 + myh->root.u.def.section->output_offset
8021 + myh->root.u.def.value;
8022
8023 errnode->u.v.branch->vma = vma;
8024 break;
8025
8026 default:
8027 abort ();
8028 }
8029 }
8030 }
8031
8032 free (tmp_name);
8033}
8034
8035static inline bfd_boolean
8036is_thumb2_ldmia (const insn32 insn)
8037{
8038 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8039 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8040 return (insn & 0xffd02000) == 0xe8900000;
8041}
8042
8043static inline bfd_boolean
8044is_thumb2_ldmdb (const insn32 insn)
8045{
8046 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8047 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8048 return (insn & 0xffd02000) == 0xe9100000;
8049}
8050
8051static inline bfd_boolean
8052is_thumb2_vldm (const insn32 insn)
8053{
8054 /* A6.5 Extension register load or store instruction
8055 A7.7.229
9239bbd3
CM		 8056 We look for SP 32-bit and DP 64-bit registers.
8057 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8058 <list> is consecutive 64-bit registers
8059 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8060 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8061 <list> is consecutive 32-bit registers
8062 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8063 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8064 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8065 return
9239bbd3
CM		 8066 (((insn & 0xfe100f00) == 0xec100b00) ||
8067 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8068 && /* (IA without !). */
8069 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8070 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8071 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8072 /* (DB with !). */
8073 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8074}
8075
8076/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8077 VLDM opcode and:
8078 - computes the number and the mode of memory accesses
8079 - decides if the replacement should be done:
8080 . replaces only if > 8-word accesses
8081 . or (testing purposes only) replaces all accesses. */
8082
8083static bfd_boolean
8084stm32l4xx_need_create_replacing_stub (const insn32 insn,
8085 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8086{
9239bbd3 8087 int nb_words = 0;
a504d23a
LA		 8088
8089 /* The field encoding the register list is the same for both LDMIA
8090 and LDMDB encodings. */
8091 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 8092 nb_words = popcount (insn & 0x0000ffff);
a504d23a 8093 else if (is_thumb2_vldm (insn))
9239bbd3 8094 nb_words = (insn & 0xff);
a504d23a
LA		 8095
8096 /* DEFAULT mode accounts for the real bug condition situation,
8097 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8098 return
9239bbd3 8099 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8100 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8101}
8102
8103/* Look for potentially-troublesome code sequences which might trigger
8104 the STM STM32L4XX erratum. */
8105
8106bfd_boolean
8107bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8108 struct bfd_link_info *link_info)
8109{
8110 asection *sec;
8111 bfd_byte *contents = NULL;
8112 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8113
8114 if (globals == NULL)
8115 return FALSE;
8116
8117 /* If we are only performing a partial link do not bother
8118 to construct any glue. */
8119 if (bfd_link_relocatable (link_info))
8120 return TRUE;
8121
8122 /* Skip if this bfd does not correspond to an ELF image. */
8123 if (! is_arm_elf (abfd))
8124 return TRUE;
8125
8126 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8127 return TRUE;
8128
8129 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8130 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8131 return TRUE;
8132
8133 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8134 {
8135 unsigned int i, span;
8136 struct _arm_elf_section_data *sec_data;
8137
8138 /* If we don't have executable progbits, we're not interested in this
8139 section. Also skip if section is to be excluded. */
8140 if (elf_section_type (sec) != SHT_PROGBITS
8141 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8142 || (sec->flags & SEC_EXCLUDE) != 0
8143 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8144 || sec->output_section == bfd_abs_section_ptr
8145 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8146 continue;
8147
8148 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8149
a504d23a
LA		 8150 if (sec_data->mapcount == 0)
8151 continue;
c7b8f16e 8152
a504d23a
LA		 8153 if (elf_section_data (sec)->this_hdr.contents != NULL)
8154 contents = elf_section_data (sec)->this_hdr.contents;
8155 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8156 goto error_return;
c7b8f16e 8157
a504d23a
LA		 8158 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8159 elf32_arm_compare_mapping);
c7b8f16e 8160
a504d23a
LA		 8161 for (span = 0; span < sec_data->mapcount; span++)
8162 {
8163 unsigned int span_start = sec_data->map[span].vma;
8164 unsigned int span_end = (span == sec_data->mapcount - 1)
8165 ? sec->size : sec_data->map[span + 1].vma;
8166 char span_type = sec_data->map[span].type;
8167 int itblock_current_pos = 0;
c7b8f16e 8168
a504d23a
LA		 8169 /* Only Thumb2 mode need be supported with this CM4 specific
8170 code, we should not encounter any arm mode eg span_type
8171 != 'a'. */
8172 if (span_type != 't')
8173 continue;
c7b8f16e 8174
a504d23a
LA		 8175 for (i = span_start; i < span_end;)
8176 {
8177 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8178 bfd_boolean insn_32bit = FALSE;
8179 bfd_boolean is_ldm = FALSE;
8180 bfd_boolean is_vldm = FALSE;
8181 bfd_boolean is_not_last_in_it_block = FALSE;
8182
8183 /* The first 16-bits of all 32-bit thumb2 instructions start
8184 with opcode[15..13]=0b111 and the encoded op1 can be anything
8185 except opcode[12..11]!=0b00.
8186 See 32-bit Thumb instruction encoding. */
8187 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8188 insn_32bit = TRUE;
c7b8f16e 8189
a504d23a
LA		 8190 /* Compute the predicate that tells if the instruction
8191 is concerned by the IT block
8192 - Creates an error if there is a ldm that is not
8193 last in the IT block thus cannot be replaced
8194 - Otherwise we can create a branch at the end of the
8195 IT block, it will be controlled naturally by IT
8196 with the proper pseudo-predicate
8197 - So the only interesting predicate is the one that
8198 tells that we are not on the last item of an IT
8199 block. */
8200 if (itblock_current_pos != 0)
8201 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8202
a504d23a
LA		 8203 if (insn_32bit)
8204 {
8205 /* Load the rest of the insn (in manual-friendly order). */
8206 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8207 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8208 is_vldm = is_thumb2_vldm (insn);
8209
8210 /* Veneers are created for (v)ldm depending on
8211 option flags and memory accesses conditions; but
8212 if the instruction is not the last instruction of
8213 an IT block, we cannot create a jump there, so we
8214 bail out. */
8215 if ((is_ldm || is_vldm) &&
8216 stm32l4xx_need_create_replacing_stub
8217 (insn, globals->stm32l4xx_fix))
8218 {
8219 if (is_not_last_in_it_block)
8220 {
8221 (*_bfd_error_handler)
8222 /* Note - overlong line used here to allow for translation. */
8223 (_("\
8224%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
8225 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
8226 abfd, sec, (long)i);
8227 }
8228 else
8229 {
8230 elf32_stm32l4xx_erratum_list *newerr =
8231 (elf32_stm32l4xx_erratum_list *)
8232 bfd_zmalloc
8233 (sizeof (elf32_stm32l4xx_erratum_list));
8234
8235 elf32_arm_section_data (sec)
8236 ->stm32l4xx_erratumcount += 1;
8237 newerr->u.b.insn = insn;
8238 /* We create only thumb branches. */
8239 newerr->type =
8240 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8241 record_stm32l4xx_erratum_veneer
8242 (link_info, newerr, abfd, sec,
8243 i,
8244 is_ldm ?
8245 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8246 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8247 newerr->vma = -1;
8248 newerr->next = sec_data->stm32l4xx_erratumlist;
8249 sec_data->stm32l4xx_erratumlist = newerr;
8250 }
8251 }
8252 }
8253 else
8254 {
8255 /* A7.7.37 IT p208
8256 IT blocks are only encoded in T1
8257 Encoding T1: IT{x{y{z}}} <firstcond>
8258 1 0 1 1 - 1 1 1 1 - firstcond - mask
8259 if mask = '0000' then see 'related encodings'
8260 We don't deal with UNPREDICTABLE, just ignore these.
8261 There can be no nested IT blocks so an IT block
8262 is naturally a new one for which it is worth
8263 computing its size. */
8264 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
8265 ((insn & 0x000f) != 0x0000);
8266 /* If we have a new IT block we compute its size. */
8267 if (is_newitblock)
8268 {
8269 /* Compute the number of instructions controlled
8270 by the IT block, it will be used to decide
8271 whether we are inside an IT block or not. */
8272 unsigned int mask = insn & 0x000f;
8273 itblock_current_pos = 4 - ctz (mask);
8274 }
8275 }
8276
8277 i += insn_32bit ? 4 : 2;
99059e56
RM		 8278 }
8279 }
a504d23a
LA		 8280
8281 if (contents != NULL
8282 && elf_section_data (sec)->this_hdr.contents != contents)
8283 free (contents);
8284 contents = NULL;
c7b8f16e 8285 }
906e58ca 8286
a504d23a
LA		 8287 return TRUE;
8288
8289error_return:
8290 if (contents != NULL
8291 && elf_section_data (sec)->this_hdr.contents != contents)
8292 free (contents);
c7b8f16e 8293
a504d23a
LA		 8294 return FALSE;
8295}
c7b8f16e 8296
eb043451
PB		 8297/* Set target relocation values needed during linking. */
8298
8299void
bf21ed78
MS		 8300bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
8301 struct bfd_link_info *link_info,
eb043451 8302 int target1_is_rel,
319850b4 8303 char * target2_type,
99059e56 8304 int fix_v4bx,
c7b8f16e 8305 int use_blx,
99059e56 8306 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 8307 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 8308 int no_enum_warn, int no_wchar_warn,
2de70689
MGD		 8309 int pic_veneer, int fix_cortex_a8,
8310 int fix_arm1176)
eb043451
PB		 8311{
8312 struct elf32_arm_link_hash_table *globals;
8313
8314 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8315 if (globals == NULL)
8316 return;
eb043451
PB		 8317
8318 globals->target1_is_rel = target1_is_rel;
8319 if (strcmp (target2_type, "rel") == 0)
8320 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 8321 else if (strcmp (target2_type, "abs") == 0)
8322 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 8323 else if (strcmp (target2_type, "got-rel") == 0)
8324 globals->target2_reloc = R_ARM_GOT_PREL;
8325 else
8326 {
8327 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
8328 target2_type);
8329 }
319850b4 8330 globals->fix_v4bx = fix_v4bx;
33bfe774 8331 globals->use_blx |= use_blx;
c7b8f16e 8332 globals->vfp11_fix = vfp11_fix;
a504d23a 8333 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 8334 globals->pic_veneer = pic_veneer;
48229727 8335 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 8336 globals->fix_arm1176 = fix_arm1176;
bf21ed78 8337
0ffa91dd
NC		 8338 BFD_ASSERT (is_arm_elf (output_bfd));
8339 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 8340 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 8341}
eb043451 8342
12a0a0fd 8343/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8344
12a0a0fd
PB		 8345static void
8346insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8347{
8348 bfd_vma upper;
8349 bfd_vma lower;
8350 int reloc_sign;
8351
8352 BFD_ASSERT ((offset & 1) == 0);
8353
8354 upper = bfd_get_16 (abfd, insn);
8355 lower = bfd_get_16 (abfd, insn + 2);
8356 reloc_sign = (offset < 0) ? 1 : 0;
8357 upper = (upper & ~(bfd_vma) 0x7ff)
8358 | ((offset >> 12) & 0x3ff)
8359 | (reloc_sign << 10);
906e58ca 8360 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8361 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8362 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8363 | ((offset >> 1) & 0x7ff);
8364 bfd_put_16 (abfd, upper, insn);
8365 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8366}
8367
9b485d32
NC		 8368/* Thumb code calling an ARM function. */
8369
252b5132 8370static int
57e8b36a
NC		 8371elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8372 const char * name,
8373 bfd * input_bfd,
8374 bfd * output_bfd,
8375 asection * input_section,
8376 bfd_byte * hit_data,
8377 asection * sym_sec,
8378 bfd_vma offset,
8379 bfd_signed_vma addend,
f2a9dd69
DJ		 8380 bfd_vma val,
8381 char **error_message)
252b5132 8382{
bcbdc74c 8383 asection * s = 0;
dc810e39 8384 bfd_vma my_offset;
252b5132 8385 long int ret_offset;
bcbdc74c
NC		 8386 struct elf_link_hash_entry * myh;
8387 struct elf32_arm_link_hash_table * globals;
252b5132 8388
f2a9dd69 8389 myh = find_thumb_glue (info, name, error_message);
252b5132 8390 if (myh == NULL)
b34976b6 8391 return FALSE;
252b5132
RH		 8392
8393 globals = elf32_arm_hash_table (info);
252b5132
RH		 8394 BFD_ASSERT (globals != NULL);
8395 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8396
8397 my_offset = myh->root.u.def.value;
8398
3d4d4302
AM		 8399 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8400 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8401
8402 BFD_ASSERT (s != NULL);
8403 BFD_ASSERT (s->contents != NULL);
8404 BFD_ASSERT (s->output_section != NULL);
8405
8406 if ((my_offset & 0x01) == 0x01)
8407 {
8408 if (sym_sec != NULL
8409 && sym_sec->owner != NULL
8410 && !INTERWORK_FLAG (sym_sec->owner))
8411 {
8f615d07 8412 (*_bfd_error_handler)
d003868e 8413 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8414 " first occurrence: %B: Thumb call to ARM"),
d003868e 8415 sym_sec->owner, input_bfd, name);
252b5132 8416
b34976b6 8417 return FALSE;
252b5132
RH		 8418 }
8419
8420 --my_offset;
8421 myh->root.u.def.value = my_offset;
8422
52ab56c2
PB		 8423 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8424 s->contents + my_offset);
252b5132 8425
52ab56c2
PB		 8426 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8427 s->contents + my_offset + 2);
252b5132
RH		 8428
8429 ret_offset =
9b485d32
NC		 8430 /* Address of destination of the stub. */
8431 ((bfd_signed_vma) val)
252b5132 8432 - ((bfd_signed_vma)
57e8b36a
NC		 8433 /* Offset from the start of the current section
8434 to the start of the stubs. */
9b485d32
NC		 8435 (s->output_offset
8436 /* Offset of the start of this stub from the start of the stubs. */
8437 + my_offset
8438 /* Address of the start of the current section. */
8439 + s->output_section->vma)
8440 /* The branch instruction is 4 bytes into the stub. */
8441 + 4
8442 /* ARM branches work from the pc of the instruction + 8. */
8443 + 8);
252b5132 8444
52ab56c2
PB		 8445 put_arm_insn (globals, output_bfd,
8446 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8447 s->contents + my_offset + 4);
252b5132
RH		 8448 }
8449
8450 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8451
427bfd90
NC		 8452 /* Now go back and fix up the original BL insn to point to here. */
8453 ret_offset =
8454 /* Address of where the stub is located. */
8455 (s->output_section->vma + s->output_offset + my_offset)
8456 /* Address of where the BL is located. */
57e8b36a
NC		 8457 - (input_section->output_section->vma + input_section->output_offset
8458 + offset)
427bfd90
NC		 8459 /* Addend in the relocation. */
8460 - addend
8461 /* Biassing for PC-relative addressing. */
8462 - 8;
252b5132 8463
12a0a0fd 8464 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8465
b34976b6 8466 return TRUE;
252b5132
RH		 8467}
8468
a4fd1a8e 8469/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8470
a4fd1a8e
PB		 8471static struct elf_link_hash_entry *
8472elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8473 const char * name,
8474 bfd * input_bfd,
8475 bfd * output_bfd,
8476 asection * sym_sec,
8477 bfd_vma val,
8029a119
NC		 8478 asection * s,
8479 char ** error_message)
252b5132 8480{
dc810e39 8481 bfd_vma my_offset;
252b5132 8482 long int ret_offset;
bcbdc74c
NC		 8483 struct elf_link_hash_entry * myh;
8484 struct elf32_arm_link_hash_table * globals;
252b5132 8485
f2a9dd69 8486 myh = find_arm_glue (info, name, error_message);
252b5132 8487 if (myh == NULL)
a4fd1a8e 8488 return NULL;
252b5132
RH		 8489
8490 globals = elf32_arm_hash_table (info);
252b5132
RH		 8491 BFD_ASSERT (globals != NULL);
8492 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8493
8494 my_offset = myh->root.u.def.value;
252b5132
RH		 8495
8496 if ((my_offset & 0x01) == 0x01)
8497 {
8498 if (sym_sec != NULL
8499 && sym_sec->owner != NULL
8500 && !INTERWORK_FLAG (sym_sec->owner))
8501 {
8f615d07 8502 (*_bfd_error_handler)
d003868e
AM		 8503 (_("%B(%s): warning: interworking not enabled.\n"
8504 " first occurrence: %B: arm call to thumb"),
8505 sym_sec->owner, input_bfd, name);
252b5132 8506 }
9b485d32 8507
252b5132
RH		 8508 --my_offset;
8509 myh->root.u.def.value = my_offset;
8510
0e1862bb
L		 8511 if (bfd_link_pic (info)
8512 || globals->root.is_relocatable_executable
27e55c4d 8513 || globals->pic_veneer)
8f6277f5
PB		 8514 {
8515 /* For relocatable objects we can't use absolute addresses,
8516 so construct the address from a relative offset. */
8517 /* TODO: If the offset is small it's probably worth
8518 constructing the address with adds. */
52ab56c2
PB		 8519 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8520 s->contents + my_offset);
8521 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8522 s->contents + my_offset + 4);
8523 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8524 s->contents + my_offset + 8);
8f6277f5
PB		 8525 /* Adjust the offset by 4 for the position of the add,
8526 and 8 for the pipeline offset. */
8527 ret_offset = (val - (s->output_offset
8528 + s->output_section->vma
8529 + my_offset + 12))
8530 | 1;
8531 bfd_put_32 (output_bfd, ret_offset,
8532 s->contents + my_offset + 12);
8533 }
26079076
PB		 8534 else if (globals->use_blx)
8535 {
8536 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8537 s->contents + my_offset);
8538
8539 /* It's a thumb address. Add the low order bit. */
8540 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8541 s->contents + my_offset + 4);
8542 }
8f6277f5
PB		 8543 else
8544 {
52ab56c2
PB		 8545 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8546 s->contents + my_offset);
252b5132 8547
52ab56c2
PB		 8548 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8549 s->contents + my_offset + 4);
252b5132 8550
8f6277f5
PB		 8551 /* It's a thumb address. Add the low order bit. */
8552 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8553 s->contents + my_offset + 8);
8029a119
NC		 8554
8555 my_offset += 12;
8f6277f5 8556 }
252b5132
RH		 8557 }
8558
8559 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8560
a4fd1a8e
PB		 8561 return myh;
8562}
8563
8564/* Arm code calling a Thumb function. */
8565
8566static int
8567elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8568 const char * name,
8569 bfd * input_bfd,
8570 bfd * output_bfd,
8571 asection * input_section,
8572 bfd_byte * hit_data,
8573 asection * sym_sec,
8574 bfd_vma offset,
8575 bfd_signed_vma addend,
f2a9dd69
DJ		 8576 bfd_vma val,
8577 char **error_message)
a4fd1a8e
PB		 8578{
8579 unsigned long int tmp;
8580 bfd_vma my_offset;
8581 asection * s;
8582 long int ret_offset;
8583 struct elf_link_hash_entry * myh;
8584 struct elf32_arm_link_hash_table * globals;
8585
8586 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8587 BFD_ASSERT (globals != NULL);
8588 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8589
3d4d4302
AM		 8590 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8591 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8592 BFD_ASSERT (s != NULL);
8593 BFD_ASSERT (s->contents != NULL);
8594 BFD_ASSERT (s->output_section != NULL);
8595
8596 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8597 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8598 if (!myh)
8599 return FALSE;
8600
8601 my_offset = myh->root.u.def.value;
252b5132
RH		 8602 tmp = bfd_get_32 (input_bfd, hit_data);
8603 tmp = tmp & 0xFF000000;
8604
9b485d32 8605 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 8606 ret_offset = (s->output_offset
8607 + my_offset
8608 + s->output_section->vma
8609 - (input_section->output_offset
8610 + input_section->output_section->vma
8611 + offset + addend)
8612 - 8);
9a5aca8c 8613
252b5132
RH		 8614 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
8615
dc810e39 8616 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 8617
b34976b6 8618 return TRUE;
252b5132
RH		 8619}
8620
a4fd1a8e
PB		 8621/* Populate Arm stub for an exported Thumb function. */
8622
8623static bfd_boolean
8624elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
8625{
8626 struct bfd_link_info * info = (struct bfd_link_info *) inf;
8627 asection * s;
8628 struct elf_link_hash_entry * myh;
8629 struct elf32_arm_link_hash_entry *eh;
8630 struct elf32_arm_link_hash_table * globals;
8631 asection *sec;
8632 bfd_vma val;
f2a9dd69 8633 char *error_message;
a4fd1a8e 8634
906e58ca 8635 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 8636 /* Allocate stubs for exported Thumb functions on v4t. */
8637 if (eh->export_glue == NULL)
8638 return TRUE;
8639
8640 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8641 BFD_ASSERT (globals != NULL);
8642 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8643
3d4d4302
AM		 8644 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8645 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8646 BFD_ASSERT (s != NULL);
8647 BFD_ASSERT (s->contents != NULL);
8648 BFD_ASSERT (s->output_section != NULL);
8649
8650 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 8651
8652 BFD_ASSERT (sec->output_section != NULL);
8653
a4fd1a8e
PB		 8654 val = eh->export_glue->root.u.def.value + sec->output_offset
8655 + sec->output_section->vma;
8029a119 8656
a4fd1a8e
PB		 8657 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
8658 h->root.u.def.section->owner,
f2a9dd69
DJ		 8659 globals->obfd, sec, val, s,
8660 &error_message);
a4fd1a8e
PB		 8661 BFD_ASSERT (myh);
8662 return TRUE;
8663}
8664
845b51d6
PB		 8665/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
8666
8667static bfd_vma
8668elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
8669{
8670 bfd_byte *p;
8671 bfd_vma glue_addr;
8672 asection *s;
8673 struct elf32_arm_link_hash_table *globals;
8674
8675 globals = elf32_arm_hash_table (info);
845b51d6
PB		 8676 BFD_ASSERT (globals != NULL);
8677 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8678
3d4d4302
AM		 8679 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8680 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 8681 BFD_ASSERT (s != NULL);
8682 BFD_ASSERT (s->contents != NULL);
8683 BFD_ASSERT (s->output_section != NULL);
8684
8685 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
8686
8687 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
8688
8689 if ((globals->bx_glue_offset[reg] & 1) == 0)
8690 {
8691 p = s->contents + glue_addr;
8692 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
8693 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
8694 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
8695 globals->bx_glue_offset[reg] |= 1;
8696 }
8697
8698 return glue_addr + s->output_section->vma + s->output_offset;
8699}
8700
a4fd1a8e
PB		 8701/* Generate Arm stubs for exported Thumb symbols. */
8702static void
906e58ca 8703elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 8704 struct bfd_link_info *link_info)
8705{
8706 struct elf32_arm_link_hash_table * globals;
8707
8029a119
NC		 8708 if (link_info == NULL)
8709 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 8710 return;
8711
8712 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8713 if (globals == NULL)
8714 return;
8715
84c08195
PB		 8716 /* If blx is available then exported Thumb symbols are OK and there is
8717 nothing to do. */
a4fd1a8e
PB		 8718 if (globals->use_blx)
8719 return;
8720
8721 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
8722 link_info);
8723}
8724
47beaa6a
RS		 8725/* Reserve space for COUNT dynamic relocations in relocation selection
8726 SRELOC. */
8727
8728static void
8729elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
8730 bfd_size_type count)
8731{
8732 struct elf32_arm_link_hash_table *htab;
8733
8734 htab = elf32_arm_hash_table (info);
8735 BFD_ASSERT (htab->root.dynamic_sections_created);
8736 if (sreloc == NULL)
8737 abort ();
8738 sreloc->size += RELOC_SIZE (htab) * count;
8739}
8740
34e77a92
RS		 8741/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8742 dynamic, the relocations should go in SRELOC, otherwise they should
8743 go in the special .rel.iplt section. */
8744
8745static void
8746elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
8747 bfd_size_type count)
8748{
8749 struct elf32_arm_link_hash_table *htab;
8750
8751 htab = elf32_arm_hash_table (info);
8752 if (!htab->root.dynamic_sections_created)
8753 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
8754 else
8755 {
8756 BFD_ASSERT (sreloc != NULL);
8757 sreloc->size += RELOC_SIZE (htab) * count;
8758 }
8759}
8760
47beaa6a
RS		 8761/* Add relocation REL to the end of relocation section SRELOC. */
8762
8763static void
8764elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
8765 asection *sreloc, Elf_Internal_Rela *rel)
8766{
8767 bfd_byte *loc;
8768 struct elf32_arm_link_hash_table *htab;
8769
8770 htab = elf32_arm_hash_table (info);
34e77a92
RS		 8771 if (!htab->root.dynamic_sections_created
8772 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
8773 sreloc = htab->root.irelplt;
47beaa6a
RS		 8774 if (sreloc == NULL)
8775 abort ();
8776 loc = sreloc->contents;
8777 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
8778 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
8779 abort ();
8780 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
8781}
8782
34e77a92
RS		 8783/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8784 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8785 to .plt. */
8786
8787static void
8788elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
8789 bfd_boolean is_iplt_entry,
8790 union gotplt_union *root_plt,
8791 struct arm_plt_info *arm_plt)
8792{
8793 struct elf32_arm_link_hash_table *htab;
8794 asection *splt;
8795 asection *sgotplt;
8796
8797 htab = elf32_arm_hash_table (info);
8798
8799 if (is_iplt_entry)
8800 {
8801 splt = htab->root.iplt;
8802 sgotplt = htab->root.igotplt;
8803
99059e56
RM		 8804 /* NaCl uses a special first entry in .iplt too. */
8805 if (htab->nacl_p && splt->size == 0)
8806 splt->size += htab->plt_header_size;
8807
34e77a92
RS		 8808 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8809 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
8810 }
8811 else
8812 {
8813 splt = htab->root.splt;
8814 sgotplt = htab->root.sgotplt;
8815
8816 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8817 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
8818
8819 /* If this is the first .plt entry, make room for the special
8820 first entry. */
8821 if (splt->size == 0)
8822 splt->size += htab->plt_header_size;
9f19ab6d
WN		 8823
8824 htab->next_tls_desc_index++;
34e77a92
RS		 8825 }
8826
8827 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8828 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8829 splt->size += PLT_THUMB_STUB_SIZE;
8830 root_plt->offset = splt->size;
8831 splt->size += htab->plt_entry_size;
8832
8833 if (!htab->symbian_p)
8834 {
8835 /* We also need to make an entry in the .got.plt section, which
8836 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 8837 if (is_iplt_entry)
8838 arm_plt->got_offset = sgotplt->size;
8839 else
8840 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 8841 sgotplt->size += 4;
8842 }
8843}
8844
b38cadfb
NC		 8845static bfd_vma
8846arm_movw_immediate (bfd_vma value)
8847{
8848 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
8849}
8850
8851static bfd_vma
8852arm_movt_immediate (bfd_vma value)
8853{
8854 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
8855}
8856
34e77a92
RS		 8857/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8858 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8859 Otherwise, DYNINDX is the index of the symbol in the dynamic
8860 symbol table and SYM_VALUE is undefined.
8861
8862 ROOT_PLT points to the offset of the PLT entry from the start of its
8863 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 8864 bookkeeping information.
34e77a92 8865
57460bcf
NC		 8866 Returns FALSE if there was a problem. */
8867
8868static bfd_boolean
34e77a92
RS		 8869elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
8870 union gotplt_union *root_plt,
8871 struct arm_plt_info *arm_plt,
8872 int dynindx, bfd_vma sym_value)
8873{
8874 struct elf32_arm_link_hash_table *htab;
8875 asection *sgot;
8876 asection *splt;
8877 asection *srel;
8878 bfd_byte *loc;
8879 bfd_vma plt_index;
8880 Elf_Internal_Rela rel;
8881 bfd_vma plt_header_size;
8882 bfd_vma got_header_size;
8883
8884 htab = elf32_arm_hash_table (info);
8885
8886 /* Pick the appropriate sections and sizes. */
8887 if (dynindx == -1)
8888 {
8889 splt = htab->root.iplt;
8890 sgot = htab->root.igotplt;
8891 srel = htab->root.irelplt;
8892
8893 /* There are no reserved entries in .igot.plt, and no special
8894 first entry in .iplt. */
8895 got_header_size = 0;
8896 plt_header_size = 0;
8897 }
8898 else
8899 {
8900 splt = htab->root.splt;
8901 sgot = htab->root.sgotplt;
8902 srel = htab->root.srelplt;
8903
8904 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
8905 plt_header_size = htab->plt_header_size;
8906 }
8907 BFD_ASSERT (splt != NULL && srel != NULL);
8908
8909 /* Fill in the entry in the procedure linkage table. */
8910 if (htab->symbian_p)
8911 {
8912 BFD_ASSERT (dynindx >= 0);
8913 put_arm_insn (htab, output_bfd,
8914 elf32_arm_symbian_plt_entry[0],
8915 splt->contents + root_plt->offset);
8916 bfd_put_32 (output_bfd,
8917 elf32_arm_symbian_plt_entry[1],
8918 splt->contents + root_plt->offset + 4);
8919
8920 /* Fill in the entry in the .rel.plt section. */
8921 rel.r_offset = (splt->output_section->vma
8922 + splt->output_offset
8923 + root_plt->offset + 4);
8924 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
8925
8926 /* Get the index in the procedure linkage table which
8927 corresponds to this symbol. This is the index of this symbol
8928 in all the symbols for which we are making plt entries. The
8929 first entry in the procedure linkage table is reserved. */
8930 plt_index = ((root_plt->offset - plt_header_size)
8931 / htab->plt_entry_size);
8932 }
8933 else
8934 {
8935 bfd_vma got_offset, got_address, plt_address;
8936 bfd_vma got_displacement, initial_got_entry;
8937 bfd_byte * ptr;
8938
8939 BFD_ASSERT (sgot != NULL);
8940
8941 /* Get the offset into the .(i)got.plt table of the entry that
8942 corresponds to this function. */
8943 got_offset = (arm_plt->got_offset & -2);
8944
8945 /* Get the index in the procedure linkage table which
8946 corresponds to this symbol. This is the index of this symbol
8947 in all the symbols for which we are making plt entries.
8948 After the reserved .got.plt entries, all symbols appear in
8949 the same order as in .plt. */
8950 plt_index = (got_offset - got_header_size) / 4;
8951
8952 /* Calculate the address of the GOT entry. */
8953 got_address = (sgot->output_section->vma
8954 + sgot->output_offset
8955 + got_offset);
8956
8957 /* ...and the address of the PLT entry. */
8958 plt_address = (splt->output_section->vma
8959 + splt->output_offset
8960 + root_plt->offset);
8961
8962 ptr = splt->contents + root_plt->offset;
0e1862bb 8963 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 8964 {
8965 unsigned int i;
8966 bfd_vma val;
8967
8968 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8969 {
8970 val = elf32_arm_vxworks_shared_plt_entry[i];
8971 if (i == 2)
8972 val |= got_address - sgot->output_section->vma;
8973 if (i == 5)
8974 val |= plt_index * RELOC_SIZE (htab);
8975 if (i == 2 || i == 5)
8976 bfd_put_32 (output_bfd, val, ptr);
8977 else
8978 put_arm_insn (htab, output_bfd, val, ptr);
8979 }
8980 }
8981 else if (htab->vxworks_p)
8982 {
8983 unsigned int i;
8984 bfd_vma val;
8985
8986 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8987 {
8988 val = elf32_arm_vxworks_exec_plt_entry[i];
8989 if (i == 2)
8990 val |= got_address;
8991 if (i == 4)
8992 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
8993 if (i == 5)
8994 val |= plt_index * RELOC_SIZE (htab);
8995 if (i == 2 || i == 5)
8996 bfd_put_32 (output_bfd, val, ptr);
8997 else
8998 put_arm_insn (htab, output_bfd, val, ptr);
8999 }
9000
9001 loc = (htab->srelplt2->contents
9002 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9003
9004 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9005 referencing the GOT for this PLT entry. */
9006 rel.r_offset = plt_address + 8;
9007 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9008 rel.r_addend = got_offset;
9009 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9010 loc += RELOC_SIZE (htab);
9011
9012 /* Create the R_ARM_ABS32 relocation referencing the
9013 beginning of the PLT for this GOT entry. */
9014 rel.r_offset = got_address;
9015 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9016 rel.r_addend = 0;
9017 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9018 }
b38cadfb
NC		 9019 else if (htab->nacl_p)
9020 {
9021 /* Calculate the displacement between the PLT slot and the
9022 common tail that's part of the special initial PLT slot. */
6034aab8 9023 int32_t tail_displacement
b38cadfb
NC		 9024 = ((splt->output_section->vma + splt->output_offset
9025 + ARM_NACL_PLT_TAIL_OFFSET)
9026 - (plt_address + htab->plt_entry_size + 4));
9027 BFD_ASSERT ((tail_displacement & 3) == 0);
9028 tail_displacement >>= 2;
9029
9030 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9031 || (-tail_displacement & 0xff000000) == 0);
9032
9033 /* Calculate the displacement between the PLT slot and the entry
9034 in the GOT. The offset accounts for the value produced by
9035 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9036 got_displacement = (got_address
99059e56 9037 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9038
9039 /* NaCl does not support interworking at all. */
9040 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9041
9042 put_arm_insn (htab, output_bfd,
9043 elf32_arm_nacl_plt_entry[0]
9044 | arm_movw_immediate (got_displacement),
9045 ptr + 0);
9046 put_arm_insn (htab, output_bfd,
9047 elf32_arm_nacl_plt_entry[1]
9048 | arm_movt_immediate (got_displacement),
9049 ptr + 4);
9050 put_arm_insn (htab, output_bfd,
9051 elf32_arm_nacl_plt_entry[2],
9052 ptr + 8);
9053 put_arm_insn (htab, output_bfd,
9054 elf32_arm_nacl_plt_entry[3]
9055 | (tail_displacement & 0x00ffffff),
9056 ptr + 12);
9057 }
57460bcf
NC		 9058 else if (using_thumb_only (htab))
9059 {
eed94f8f 9060 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9061 if (!using_thumb2 (htab))
eed94f8f
NC		 9062 {
9063 /* FIXME: We ought to be able to generate thumb-1 PLT
9064 instructions... */
9065 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9066 output_bfd);
9067 return FALSE;
9068 }
57460bcf 9069
eed94f8f
NC		 9070 /* Calculate the displacement between the PLT slot and the entry in
9071 the GOT. The 12-byte offset accounts for the value produced by
9072 adding to pc in the 3rd instruction of the PLT stub. */
9073 got_displacement = got_address - (plt_address + 12);
9074
9075 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9076 instead of 'put_thumb_insn'. */
9077 put_arm_insn (htab, output_bfd,
9078 elf32_thumb2_plt_entry[0]
9079 | ((got_displacement & 0x000000ff) << 16)
9080 | ((got_displacement & 0x00000700) << 20)
9081 | ((got_displacement & 0x00000800) >> 1)
9082 | ((got_displacement & 0x0000f000) >> 12),
9083 ptr + 0);
9084 put_arm_insn (htab, output_bfd,
9085 elf32_thumb2_plt_entry[1]
9086 | ((got_displacement & 0x00ff0000) )
9087 | ((got_displacement & 0x07000000) << 4)
9088 | ((got_displacement & 0x08000000) >> 17)
9089 | ((got_displacement & 0xf0000000) >> 28),
9090 ptr + 4);
9091 put_arm_insn (htab, output_bfd,
9092 elf32_thumb2_plt_entry[2],
9093 ptr + 8);
9094 put_arm_insn (htab, output_bfd,
9095 elf32_thumb2_plt_entry[3],
9096 ptr + 12);
57460bcf 9097 }
34e77a92
RS		 9098 else
9099 {
9100 /* Calculate the displacement between the PLT slot and the
9101 entry in the GOT. The eight-byte offset accounts for the
9102 value produced by adding to pc in the first instruction
9103 of the PLT stub. */
9104 got_displacement = got_address - (plt_address + 8);
9105
34e77a92
RS		 9106 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9107 {
9108 put_thumb_insn (htab, output_bfd,
9109 elf32_arm_plt_thumb_stub[0], ptr - 4);
9110 put_thumb_insn (htab, output_bfd,
9111 elf32_arm_plt_thumb_stub[1], ptr - 2);
9112 }
9113
1db37fe6
YG		 9114 if (!elf32_arm_use_long_plt_entry)
9115 {
9116 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9117
9118 put_arm_insn (htab, output_bfd,
9119 elf32_arm_plt_entry_short[0]
9120 | ((got_displacement & 0x0ff00000) >> 20),
9121 ptr + 0);
9122 put_arm_insn (htab, output_bfd,
9123 elf32_arm_plt_entry_short[1]
9124 | ((got_displacement & 0x000ff000) >> 12),
9125 ptr+ 4);
9126 put_arm_insn (htab, output_bfd,
9127 elf32_arm_plt_entry_short[2]
9128 | (got_displacement & 0x00000fff),
9129 ptr + 8);
34e77a92 9130#ifdef FOUR_WORD_PLT
1db37fe6 9131 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9132#endif
1db37fe6
YG		 9133 }
9134 else
9135 {
9136 put_arm_insn (htab, output_bfd,
9137 elf32_arm_plt_entry_long[0]
9138 | ((got_displacement & 0xf0000000) >> 28),
9139 ptr + 0);
9140 put_arm_insn (htab, output_bfd,
9141 elf32_arm_plt_entry_long[1]
9142 | ((got_displacement & 0x0ff00000) >> 20),
9143 ptr + 4);
9144 put_arm_insn (htab, output_bfd,
9145 elf32_arm_plt_entry_long[2]
9146 | ((got_displacement & 0x000ff000) >> 12),
9147 ptr+ 8);
9148 put_arm_insn (htab, output_bfd,
9149 elf32_arm_plt_entry_long[3]
9150 | (got_displacement & 0x00000fff),
9151 ptr + 12);
9152 }
34e77a92
RS		 9153 }
9154
9155 /* Fill in the entry in the .rel(a).(i)plt section. */
9156 rel.r_offset = got_address;
9157 rel.r_addend = 0;
9158 if (dynindx == -1)
9159 {
9160 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9161 The dynamic linker or static executable then calls SYM_VALUE
9162 to determine the correct run-time value of the .igot.plt entry. */
9163 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9164 initial_got_entry = sym_value;
9165 }
9166 else
9167 {
9168 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9169 initial_got_entry = (splt->output_section->vma
9170 + splt->output_offset);
9171 }
9172
9173 /* Fill in the entry in the global offset table. */
9174 bfd_put_32 (output_bfd, initial_got_entry,
9175 sgot->contents + got_offset);
9176 }
9177
aba8c3de
WN		 9178 if (dynindx == -1)
9179 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9180 else
9181 {
9182 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9183 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9184 }
57460bcf
NC		 9185
9186 return TRUE;
34e77a92
RS		 9187}
9188
eb043451
PB		 9189/* Some relocations map to different relocations depending on the
9190 target. Return the real relocation. */
8029a119 9191
eb043451
PB		 9192static int
9193arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9194 int r_type)
9195{
9196 switch (r_type)
9197 {
9198 case R_ARM_TARGET1:
9199 if (globals->target1_is_rel)
9200 return R_ARM_REL32;
9201 else
9202 return R_ARM_ABS32;
9203
9204 case R_ARM_TARGET2:
9205 return globals->target2_reloc;
9206
9207 default:
9208 return r_type;
9209 }
9210}
eb043451 9211
ba93b8ac
DJ		 9212/* Return the base VMA address which should be subtracted from real addresses
9213 when resolving @dtpoff relocation.
9214 This is PT_TLS segment p_vaddr. */
9215
9216static bfd_vma
9217dtpoff_base (struct bfd_link_info *info)
9218{
9219 /* If tls_sec is NULL, we should have signalled an error already. */
9220 if (elf_hash_table (info)->tls_sec == NULL)
9221 return 0;
9222 return elf_hash_table (info)->tls_sec->vma;
9223}
9224
9225/* Return the relocation value for @tpoff relocation
9226 if STT_TLS virtual address is ADDRESS. */
9227
9228static bfd_vma
9229tpoff (struct bfd_link_info *info, bfd_vma address)
9230{
9231 struct elf_link_hash_table *htab = elf_hash_table (info);
9232 bfd_vma base;
9233
9234 /* If tls_sec is NULL, we should have signalled an error already. */
9235 if (htab->tls_sec == NULL)
9236 return 0;
9237 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9238 return address - htab->tls_sec->vma + base;
9239}
9240
00a97672
RS		 9241/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9242 VALUE is the relocation value. */
9243
9244static bfd_reloc_status_type
9245elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9246{
9247 if (value > 0xfff)
9248 return bfd_reloc_overflow;
9249
9250 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9251 bfd_put_32 (abfd, value, data);
9252 return bfd_reloc_ok;
9253}
9254
0855e32b
NS		 9255/* Handle TLS relaxations. Relaxing is possible for symbols that use
9256 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9257 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9258
9259 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9260 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9261 case of error.
9262
9263 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9264 the pre-relaxed code. It would be nice if the relocs were updated
9265 to match the optimization. */
0855e32b 9266
b38cadfb 9267static bfd_reloc_status_type
0855e32b 9268elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9269 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9270 Elf_Internal_Rela *rel, unsigned long is_local)
9271{
9272 unsigned long insn;
b38cadfb 9273
0855e32b
NS		 9274 switch (ELF32_R_TYPE (rel->r_info))
9275 {
9276 default:
9277 return bfd_reloc_notsupported;
b38cadfb 9278
0855e32b
NS		 9279 case R_ARM_TLS_GOTDESC:
9280 if (is_local)
9281 insn = 0;
9282 else
9283 {
9284 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9285 if (insn & 1)
9286 insn -= 5; /* THUMB */
9287 else
9288 insn -= 8; /* ARM */
9289 }
9290 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9291 return bfd_reloc_continue;
9292
9293 case R_ARM_THM_TLS_DESCSEQ:
9294 /* Thumb insn. */
9295 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9296 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9297 {
9298 if (is_local)
9299 /* nop */
9300 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9301 }
9302 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9303 {
9304 if (is_local)
9305 /* nop */
9306 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9307 else
9308 /* ldr rx,[ry] */
9309 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9310 }
9311 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9312 {
9313 if (is_local)
9314 /* nop */
9315 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9316 else
9317 /* mov r0, rx */
9318 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9319 contents + rel->r_offset);
9320 }
9321 else
9322 {
9323 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9324 /* It's a 32 bit instruction, fetch the rest of it for
9325 error generation. */
9326 insn = (insn << 16)
9327 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
9328 (*_bfd_error_handler)
9329 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
9330 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9331 return bfd_reloc_notsupported;
9332 }
9333 break;
b38cadfb 9334
0855e32b
NS		 9335 case R_ARM_TLS_DESCSEQ:
9336 /* arm insn. */
9337 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9338 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9339 {
9340 if (is_local)
9341 /* mov rx, ry */
9342 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9343 contents + rel->r_offset);
9344 }
9345 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9346 {
9347 if (is_local)
9348 /* nop */
9349 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9350 else
9351 /* ldr rx,[ry] */
9352 bfd_put_32 (input_bfd, insn & 0xfffff000,
9353 contents + rel->r_offset);
9354 }
9355 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9356 {
9357 if (is_local)
9358 /* nop */
9359 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9360 else
9361 /* mov r0, rx */
9362 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9363 contents + rel->r_offset);
9364 }
9365 else
9366 {
9367 (*_bfd_error_handler)
9368 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
9369 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9370 return bfd_reloc_notsupported;
9371 }
9372 break;
9373
9374 case R_ARM_TLS_CALL:
9375 /* GD->IE relaxation, turn the instruction into 'nop' or
9376 'ldr r0, [pc,r0]' */
9377 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9378 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9379 break;
b38cadfb 9380
0855e32b 9381 case R_ARM_THM_TLS_CALL:
6a631e86 9382 /* GD->IE relaxation. */
0855e32b
NS		 9383 if (!is_local)
9384 /* add r0,pc; ldr r0, [r0] */
9385 insn = 0x44786800;
60a019a0 9386 else if (using_thumb2 (globals))
0855e32b
NS		 9387 /* nop.w */
9388 insn = 0xf3af8000;
9389 else
9390 /* nop; nop */
9391 insn = 0xbf00bf00;
b38cadfb 9392
0855e32b
NS		 9393 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9394 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9395 break;
9396 }
9397 return bfd_reloc_ok;
9398}
9399
4962c51a
MS		 9400/* For a given value of n, calculate the value of G_n as required to
9401 deal with group relocations. We return it in the form of an
9402 encoded constant-and-rotation, together with the final residual. If n is
9403 specified as less than zero, then final_residual is filled with the
9404 input value and no further action is performed. */
9405
9406static bfd_vma
9407calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9408{
9409 int current_n;
9410 bfd_vma g_n;
9411 bfd_vma encoded_g_n = 0;
9412 bfd_vma residual = value; /* Also known as Y_n. */
9413
9414 for (current_n = 0; current_n <= n; current_n++)
9415 {
9416 int shift;
9417
9418 /* Calculate which part of the value to mask. */
9419 if (residual == 0)
99059e56 9420 shift = 0;
4962c51a 9421 else
99059e56
RM		 9422 {
9423 int msb;
9424
9425 /* Determine the most significant bit in the residual and
9426 align the resulting value to a 2-bit boundary. */
9427 for (msb = 30; msb >= 0; msb -= 2)
9428 if (residual & (3 << msb))
9429 break;
9430
9431 /* The desired shift is now (msb - 6), or zero, whichever
9432 is the greater. */
9433 shift = msb - 6;
9434 if (shift < 0)
9435 shift = 0;
9436 }
4962c51a
MS		 9437
9438 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9439 g_n = residual & (0xff << shift);
9440 encoded_g_n = (g_n >> shift)
99059e56 9441 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9442
9443 /* Calculate the residual for the next time around. */
9444 residual &= ~g_n;
9445 }
9446
9447 *final_residual = residual;
9448
9449 return encoded_g_n;
9450}
9451
9452/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9453 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9454
4962c51a 9455static int
906e58ca 9456identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9457{
9458 int opcode = insn & 0x1e00000;
9459
9460 if (opcode == 1 << 23) /* ADD */
9461 return 1;
9462
9463 if (opcode == 1 << 22) /* SUB */
9464 return -1;
9465
9466 return 0;
9467}
9468
252b5132 9469/* Perform a relocation as part of a final link. */
9b485d32 9470
252b5132 9471static bfd_reloc_status_type
57e8b36a
NC		 9472elf32_arm_final_link_relocate (reloc_howto_type * howto,
9473 bfd * input_bfd,
9474 bfd * output_bfd,
9475 asection * input_section,
9476 bfd_byte * contents,
9477 Elf_Internal_Rela * rel,
9478 bfd_vma value,
9479 struct bfd_link_info * info,
9480 asection * sym_sec,
9481 const char * sym_name,
34e77a92
RS		 9482 unsigned char st_type,
9483 enum arm_st_branch_type branch_type,
0945cdfd 9484 struct elf_link_hash_entry * h,
f2a9dd69 9485 bfd_boolean * unresolved_reloc_p,
8029a119 9486 char ** error_message)
252b5132
RH		 9487{
9488 unsigned long r_type = howto->type;
9489 unsigned long r_symndx;
9490 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9491 bfd_vma * local_got_offsets;
0855e32b 9492 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9493 asection * sgot;
9494 asection * splt;
252b5132 9495 asection * sreloc = NULL;
362d30a1 9496 asection * srelgot;
252b5132 9497 bfd_vma addend;
ba96a88f 9498 bfd_signed_vma signed_addend;
34e77a92
RS		 9499 unsigned char dynreloc_st_type;
9500 bfd_vma dynreloc_value;
ba96a88f 9501 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9502 struct elf32_arm_link_hash_entry *eh;
9503 union gotplt_union *root_plt;
9504 struct arm_plt_info *arm_plt;
9505 bfd_vma plt_offset;
9506 bfd_vma gotplt_offset;
9507 bfd_boolean has_iplt_entry;
f21f3fe0 9508
9c504268 9509 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9510 if (globals == NULL)
9511 return bfd_reloc_notsupported;
9c504268 9512
0ffa91dd
NC		 9513 BFD_ASSERT (is_arm_elf (input_bfd));
9514
9515 /* Some relocation types map to different relocations depending on the
9c504268 9516 target. We pick the right one here. */
eb043451 9517 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9518
9519 /* It is possible to have linker relaxations on some TLS access
9520 models. Update our information here. */
9521 r_type = elf32_arm_tls_transition (info, r_type, h);
9522
eb043451
PB		 9523 if (r_type != howto->type)
9524 howto = elf32_arm_howto_from_type (r_type);
9c504268 9525
34e77a92 9526 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9527 sgot = globals->root.sgot;
252b5132 9528 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9529 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9530
34e77a92
RS		 9531 if (globals->root.dynamic_sections_created)
9532 srelgot = globals->root.srelgot;
9533 else
9534 srelgot = NULL;
9535
252b5132
RH		 9536 r_symndx = ELF32_R_SYM (rel->r_info);
9537
4e7fd91e 9538 if (globals->use_rel)
ba96a88f 9539 {
4e7fd91e
PB		 9540 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9541
9542 if (addend & ((howto->src_mask + 1) >> 1))
9543 {
9544 signed_addend = -1;
9545 signed_addend &= ~ howto->src_mask;
9546 signed_addend |= addend;
9547 }
9548 else
9549 signed_addend = addend;
ba96a88f
NC		 9550 }
9551 else
4e7fd91e 9552 addend = signed_addend = rel->r_addend;
f21f3fe0 9553
39f21624
NC		 9554 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9555 are resolving a function call relocation. */
9556 if (using_thumb_only (globals)
9557 && (r_type == R_ARM_THM_CALL
9558 || r_type == R_ARM_THM_JUMP24)
9559 && branch_type == ST_BRANCH_TO_ARM)
9560 branch_type = ST_BRANCH_TO_THUMB;
9561
34e77a92
RS		 9562 /* Record the symbol information that should be used in dynamic
9563 relocations. */
9564 dynreloc_st_type = st_type;
9565 dynreloc_value = value;
9566 if (branch_type == ST_BRANCH_TO_THUMB)
9567 dynreloc_value |= 1;
9568
9569 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9570 VALUE appropriately for relocations that we resolve at link time. */
9571 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9572 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9573 &arm_plt)
34e77a92
RS		 9574 && root_plt->offset != (bfd_vma) -1)
9575 {
9576 plt_offset = root_plt->offset;
9577 gotplt_offset = arm_plt->got_offset;
9578
9579 if (h == NULL || eh->is_iplt)
9580 {
9581 has_iplt_entry = TRUE;
9582 splt = globals->root.iplt;
9583
9584 /* Populate .iplt entries here, because not all of them will
9585 be seen by finish_dynamic_symbol. The lower bit is set if
9586 we have already populated the entry. */
9587 if (plt_offset & 1)
9588 plt_offset--;
9589 else
9590 {
57460bcf
NC		 9591 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9592 -1, dynreloc_value))
9593 root_plt->offset |= 1;
9594 else
9595 return bfd_reloc_notsupported;
34e77a92
RS		 9596 }
9597
9598 /* Static relocations always resolve to the .iplt entry. */
9599 st_type = STT_FUNC;
9600 value = (splt->output_section->vma
9601 + splt->output_offset
9602 + plt_offset);
9603 branch_type = ST_BRANCH_TO_ARM;
9604
9605 /* If there are non-call relocations that resolve to the .iplt
9606 entry, then all dynamic ones must too. */
9607 if (arm_plt->noncall_refcount != 0)
9608 {
9609 dynreloc_st_type = st_type;
9610 dynreloc_value = value;
9611 }
9612 }
9613 else
9614 /* We populate the .plt entry in finish_dynamic_symbol. */
9615 splt = globals->root.splt;
9616 }
9617 else
9618 {
9619 splt = NULL;
9620 plt_offset = (bfd_vma) -1;
9621 gotplt_offset = (bfd_vma) -1;
9622 }
9623
252b5132
RH		 9624 switch (r_type)
9625 {
9626 case R_ARM_NONE:
28a094c2
DJ		 9627 /* We don't need to find a value for this symbol. It's just a
9628 marker. */
9629 *unresolved_reloc_p = FALSE;
252b5132
RH		 9630 return bfd_reloc_ok;
9631
00a97672
RS		 9632 case R_ARM_ABS12:
9633 if (!globals->vxworks_p)
9634 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9635
252b5132
RH		 9636 case R_ARM_PC24:
9637 case R_ARM_ABS32:
bb224fc3 9638 case R_ARM_ABS32_NOI:
252b5132 9639 case R_ARM_REL32:
bb224fc3 9640 case R_ARM_REL32_NOI:
5b5bb741
PB		 9641 case R_ARM_CALL:
9642 case R_ARM_JUMP24:
dfc5f959 9643 case R_ARM_XPC25:
eb043451 9644 case R_ARM_PREL31:
7359ea65 9645 case R_ARM_PLT32:
7359ea65
DJ		 9646 /* Handle relocations which should use the PLT entry. ABS32/REL32
9647 will use the symbol's value, which may point to a PLT entry, but we
9648 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 9649 branches in this object should go to it, except if the PLT is too
9650 far away, in which case a long branch stub should be inserted. */
bb224fc3 9651 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 9652 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 9653 && r_type != R_ARM_CALL
9654 && r_type != R_ARM_JUMP24
9655 && r_type != R_ARM_PLT32)
34e77a92 9656 && plt_offset != (bfd_vma) -1)
7359ea65 9657 {
34e77a92
RS		 9658 /* If we've created a .plt section, and assigned a PLT entry
9659 to this function, it must either be a STT_GNU_IFUNC reference
9660 or not be known to bind locally. In other cases, we should
9661 have cleared the PLT entry by now. */
9662 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 9663
9664 value = (splt->output_section->vma
9665 + splt->output_offset
34e77a92 9666 + plt_offset);
0945cdfd 9667 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 9668 return _bfd_final_link_relocate (howto, input_bfd, input_section,
9669 contents, rel->r_offset, value,
00a97672 9670 rel->r_addend);
7359ea65
DJ		 9671 }
9672
67687978
PB		 9673 /* When generating a shared object or relocatable executable, these
9674 relocations are copied into the output file to be resolved at
9675 run time. */
0e1862bb
L		 9676 if ((bfd_link_pic (info)
9677 || globals->root.is_relocatable_executable)
7359ea65 9678 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 9679 && !(globals->vxworks_p
3348747a
NS		 9680 && strcmp (input_section->output_section->name,
9681 ".tls_vars") == 0)
bb224fc3 9682 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 9683 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 9684 && !(input_bfd == globals->stub_bfd
9685 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 9686 && (h == NULL
9687 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
9688 || h->root.type != bfd_link_hash_undefweak)
9689 && r_type != R_ARM_PC24
5b5bb741
PB		 9690 && r_type != R_ARM_CALL
9691 && r_type != R_ARM_JUMP24
ee06dc07 9692 && r_type != R_ARM_PREL31
7359ea65 9693 && r_type != R_ARM_PLT32)
252b5132 9694 {
947216bf 9695 Elf_Internal_Rela outrel;
b34976b6 9696 bfd_boolean skip, relocate;
f21f3fe0 9697
52db4ec2
JW		 9698 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
9699 && !h->def_regular)
9700 {
9701 char *v = _("shared object");
9702
0e1862bb 9703 if (bfd_link_executable (info))
52db4ec2
JW		 9704 v = _("PIE executable");
9705
9706 (*_bfd_error_handler)
9707 (_("%B: relocation %s against external or undefined symbol `%s'"
9708 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
9709 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
9710 return bfd_reloc_notsupported;
9711 }
9712
0945cdfd
DJ		 9713 *unresolved_reloc_p = FALSE;
9714
34e77a92 9715 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 9716 {
83bac4b0
NC		 9717 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
9718 ! globals->use_rel);
f21f3fe0 9719
83bac4b0 9720 if (sreloc == NULL)
252b5132 9721 return bfd_reloc_notsupported;
252b5132 9722 }
f21f3fe0 9723
b34976b6
AM		 9724 skip = FALSE;
9725 relocate = FALSE;
f21f3fe0 9726
00a97672 9727 outrel.r_addend = addend;
c629eae0
JJ		 9728 outrel.r_offset =
9729 _bfd_elf_section_offset (output_bfd, info, input_section,
9730 rel->r_offset);
9731 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 9732 skip = TRUE;
0bb2d96a 9733 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 9734 skip = TRUE, relocate = TRUE;
252b5132
RH		 9735 outrel.r_offset += (input_section->output_section->vma
9736 + input_section->output_offset);
f21f3fe0 9737
252b5132 9738 if (skip)
0bb2d96a 9739 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 9740 else if (h != NULL
9741 && h->dynindx != -1
0e1862bb 9742 && (!bfd_link_pic (info)
a496fbc8 9743 || !SYMBOLIC_BIND (info, h)
f5385ebf 9744 || !h->def_regular))
5e681ec4 9745 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 9746 else
9747 {
a16385dc
MM		 9748 int symbol;
9749
5e681ec4 9750 /* This symbol is local, or marked to become local. */
34e77a92 9751 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 9752 if (globals->symbian_p)
6366ff1e 9753 {
74541ad4
AM		 9754 asection *osec;
9755
6366ff1e
MM		 9756 /* On Symbian OS, the data segment and text segement
9757 can be relocated independently. Therefore, we
9758 must indicate the segment to which this
9759 relocation is relative. The BPABI allows us to
9760 use any symbol in the right segment; we just use
9761 the section symbol as it is convenient. (We
9762 cannot use the symbol given by "h" directly as it
74541ad4
AM		 9763 will not appear in the dynamic symbol table.)
9764
9765 Note that the dynamic linker ignores the section
9766 symbol value, so we don't subtract osec->vma
9767 from the emitted reloc addend. */
10dbd1f3 9768 if (sym_sec)
74541ad4 9769 osec = sym_sec->output_section;
10dbd1f3 9770 else
74541ad4
AM		 9771 osec = input_section->output_section;
9772 symbol = elf_section_data (osec)->dynindx;
9773 if (symbol == 0)
9774 {
9775 struct elf_link_hash_table *htab = elf_hash_table (info);
9776
9777 if ((osec->flags & SEC_READONLY) == 0
9778 && htab->data_index_section != NULL)
9779 osec = htab->data_index_section;
9780 else
9781 osec = htab->text_index_section;
9782 symbol = elf_section_data (osec)->dynindx;
9783 }
6366ff1e
MM		 9784 BFD_ASSERT (symbol != 0);
9785 }
a16385dc
MM		 9786 else
9787 /* On SVR4-ish systems, the dynamic loader cannot
9788 relocate the text and data segments independently,
9789 so the symbol does not matter. */
9790 symbol = 0;
34e77a92
RS		 9791 if (dynreloc_st_type == STT_GNU_IFUNC)
9792 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9793 to the .iplt entry. Instead, every non-call reference
9794 must use an R_ARM_IRELATIVE relocation to obtain the
9795 correct run-time address. */
9796 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
9797 else
9798 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 9799 if (globals->use_rel)
9800 relocate = TRUE;
9801 else
34e77a92 9802 outrel.r_addend += dynreloc_value;
252b5132 9803 }
f21f3fe0 9804
47beaa6a 9805 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 9806
f21f3fe0 9807 /* If this reloc is against an external symbol, we do not want to
252b5132 9808 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 9809 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 9810 if (! relocate)
9811 return bfd_reloc_ok;
9a5aca8c 9812
f21f3fe0 9813 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 9814 contents, rel->r_offset,
9815 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 9816 }
9817 else switch (r_type)
9818 {
00a97672
RS		 9819 case R_ARM_ABS12:
9820 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9821
dfc5f959 9822 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 9823 case R_ARM_CALL:
9824 case R_ARM_JUMP24:
8029a119 9825 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 9826 case R_ARM_PLT32:
906e58ca 9827 {
906e58ca
NC		 9828 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
9829
dfc5f959 9830 if (r_type == R_ARM_XPC25)
252b5132 9831 {
dfc5f959
NC		 9832 /* Check for Arm calling Arm function. */
9833 /* FIXME: Should we translate the instruction into a BL
9834 instruction instead ? */
35fc36a8 9835 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 9836 (*_bfd_error_handler)
9837 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
9838 input_bfd,
9839 h ? h->root.root.string : "(local)");
dfc5f959 9840 }
155d87d7 9841 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 9842 {
9843 /* Check for Arm calling Thumb function. */
35fc36a8 9844 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 9845 {
f2a9dd69
DJ		 9846 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
9847 output_bfd, input_section,
9848 hit_data, sym_sec, rel->r_offset,
9849 signed_addend, value,
9850 error_message))
9851 return bfd_reloc_ok;
9852 else
9853 return bfd_reloc_dangerous;
dfc5f959 9854 }
252b5132 9855 }
ba96a88f 9856
906e58ca 9857 /* Check if a stub has to be inserted because the
8029a119 9858 destination is too far or we are changing mode. */
155d87d7
CL		 9859 if ( r_type == R_ARM_CALL
9860 || r_type == R_ARM_JUMP24
9861 || r_type == R_ARM_PLT32)
906e58ca 9862 {
fe33d2fa
CL		 9863 enum elf32_arm_stub_type stub_type = arm_stub_none;
9864 struct elf32_arm_link_hash_entry *hash;
9865
9866 hash = (struct elf32_arm_link_hash_entry *) h;
9867 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9868 st_type, &branch_type,
9869 hash, value, sym_sec,
fe33d2fa 9870 input_bfd, sym_name);
5fa9e92f 9871
fe33d2fa 9872 if (stub_type != arm_stub_none)
906e58ca
NC		 9873 {
9874 /* The target is out of reach, so redirect the
9875 branch to the local stub for this function. */
906e58ca
NC		 9876 stub_entry = elf32_arm_get_stub_entry (input_section,
9877 sym_sec, h,
fe33d2fa
CL		 9878 rel, globals,
9879 stub_type);
9cd3e4e5
NC		 9880 {
9881 if (stub_entry != NULL)
9882 value = (stub_entry->stub_offset
9883 + stub_entry->stub_sec->output_offset
9884 + stub_entry->stub_sec->output_section->vma);
9885
9886 if (plt_offset != (bfd_vma) -1)
9887 *unresolved_reloc_p = FALSE;
9888 }
906e58ca 9889 }
fe33d2fa
CL		 9890 else
9891 {
9892 /* If the call goes through a PLT entry, make sure to
9893 check distance to the right destination address. */
34e77a92 9894 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9895 {
9896 value = (splt->output_section->vma
9897 + splt->output_offset
34e77a92 9898 + plt_offset);
fe33d2fa
CL		 9899 *unresolved_reloc_p = FALSE;
9900 /* The PLT entry is in ARM mode, regardless of the
9901 target function. */
35fc36a8 9902 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9903 }
9904 }
906e58ca
NC		 9905 }
9906
dea514f5
PB		 9907 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9908 where:
9909 S is the address of the symbol in the relocation.
9910 P is address of the instruction being relocated.
9911 A is the addend (extracted from the instruction) in bytes.
9912
9913 S is held in 'value'.
9914 P is the base address of the section containing the
9915 instruction plus the offset of the reloc into that
9916 section, ie:
9917 (input_section->output_section->vma +
9918 input_section->output_offset +
9919 rel->r_offset).
9920 A is the addend, converted into bytes, ie:
9921 (signed_addend * 4)
9922
9923 Note: None of these operations have knowledge of the pipeline
9924 size of the processor, thus it is up to the assembler to
9925 encode this information into the addend. */
9926 value -= (input_section->output_section->vma
9927 + input_section->output_offset);
9928 value -= rel->r_offset;
4e7fd91e
PB		 9929 if (globals->use_rel)
9930 value += (signed_addend << howto->size);
9931 else
9932 /* RELA addends do not have to be adjusted by howto->size. */
9933 value += signed_addend;
23080146 9934
dcb5e6e6
NC		 9935 signed_addend = value;
9936 signed_addend >>= howto->rightshift;
9a5aca8c 9937
5ab79981 9938 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 9939 the next instruction unless a PLT entry will be created.
77b4f08f 9940 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 9941 The jump to the next instruction is optimized as a NOP depending
9942 on the architecture. */
ffcb4889 9943 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 9944 && plt_offset == (bfd_vma) -1)
77b4f08f 9945 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 9946 {
cd1dac3d
DG		 9947 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
9948
9949 if (arch_has_arm_nop (globals))
9950 value |= 0x0320f000;
9951 else
9952 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 9953 }
9954 else
59f2c4e7 9955 {
9b485d32 9956 /* Perform a signed range check. */
dcb5e6e6 9957 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 9958 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
9959 return bfd_reloc_overflow;
9a5aca8c 9960
5ab79981 9961 addend = (value & 2);
39b41c9c 9962
5ab79981
PB		 9963 value = (signed_addend & howto->dst_mask)
9964 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 9965
5ab79981
PB		 9966 if (r_type == R_ARM_CALL)
9967 {
155d87d7 9968 /* Set the H bit in the BLX instruction. */
35fc36a8 9969 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 9970 {
9971 if (addend)
9972 value |= (1 << 24);
9973 else
9974 value &= ~(bfd_vma)(1 << 24);
9975 }
9976
5ab79981 9977 /* Select the correct instruction (BL or BLX). */
906e58ca 9978 /* Only if we are not handling a BL to a stub. In this
8029a119 9979 case, mode switching is performed by the stub. */
35fc36a8 9980 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 9981 value |= (1 << 28);
63e1a0fc 9982 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 9983 {
9984 value &= ~(bfd_vma)(1 << 28);
9985 value |= (1 << 24);
9986 }
39b41c9c
PB		 9987 }
9988 }
906e58ca 9989 }
252b5132 9990 break;
f21f3fe0 9991
252b5132
RH		 9992 case R_ARM_ABS32:
9993 value += addend;
35fc36a8 9994 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 9995 value |= 1;
9996 break;
f21f3fe0 9997
bb224fc3
MS		 9998 case R_ARM_ABS32_NOI:
9999 value += addend;
10000 break;
10001
252b5132 10002 case R_ARM_REL32:
a8bc6c78 10003 value += addend;
35fc36a8 10004 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10005 value |= 1;
252b5132 10006 value -= (input_section->output_section->vma
62efb346 10007 + input_section->output_offset + rel->r_offset);
252b5132 10008 break;
eb043451 10009
bb224fc3
MS		 10010 case R_ARM_REL32_NOI:
10011 value += addend;
10012 value -= (input_section->output_section->vma
10013 + input_section->output_offset + rel->r_offset);
10014 break;
10015
eb043451
PB		 10016 case R_ARM_PREL31:
10017 value -= (input_section->output_section->vma
10018 + input_section->output_offset + rel->r_offset);
10019 value += signed_addend;
10020 if (! h || h->root.type != bfd_link_hash_undefweak)
10021 {
8029a119 10022 /* Check for overflow. */
eb043451
PB		 10023 if ((value ^ (value >> 1)) & (1 << 30))
10024 return bfd_reloc_overflow;
10025 }
10026 value &= 0x7fffffff;
10027 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10028 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10029 value |= 1;
10030 break;
252b5132 10031 }
f21f3fe0 10032
252b5132
RH		 10033 bfd_put_32 (input_bfd, value, hit_data);
10034 return bfd_reloc_ok;
10035
10036 case R_ARM_ABS8:
fd0fd00c
MJ		 10037 /* PR 16202: Refectch the addend using the correct size. */
10038 if (globals->use_rel)
10039 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10040 value += addend;
4e67d4ca
DG		 10041
10042 /* There is no way to tell whether the user intended to use a signed or
10043 unsigned addend. When checking for overflow we accept either,
10044 as specified by the AAELF. */
10045 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10046 return bfd_reloc_overflow;
10047
10048 bfd_put_8 (input_bfd, value, hit_data);
10049 return bfd_reloc_ok;
10050
10051 case R_ARM_ABS16:
fd0fd00c
MJ		 10052 /* PR 16202: Refectch the addend using the correct size. */
10053 if (globals->use_rel)
10054 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10055 value += addend;
10056
4e67d4ca
DG		 10057 /* See comment for R_ARM_ABS8. */
10058 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10059 return bfd_reloc_overflow;
10060
10061 bfd_put_16 (input_bfd, value, hit_data);
10062 return bfd_reloc_ok;
10063
252b5132 10064 case R_ARM_THM_ABS5:
9b485d32 10065 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10066 if (globals->use_rel)
10067 {
10068 /* Need to refetch addend. */
10069 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10070 /* ??? Need to determine shift amount from operand size. */
10071 addend >>= howto->rightshift;
10072 }
252b5132
RH		 10073 value += addend;
10074
10075 /* ??? Isn't value unsigned? */
10076 if ((long) value > 0x1f || (long) value < -0x10)
10077 return bfd_reloc_overflow;
10078
10079 /* ??? Value needs to be properly shifted into place first. */
10080 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10081 bfd_put_16 (input_bfd, value, hit_data);
10082 return bfd_reloc_ok;
10083
2cab6cc3
MS		 10084 case R_ARM_THM_ALU_PREL_11_0:
10085 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10086 {
10087 bfd_vma insn;
10088 bfd_signed_vma relocation;
10089
10090 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10091 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10092
99059e56
RM		 10093 if (globals->use_rel)
10094 {
10095 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10096 | ((insn & (1 << 26)) >> 15);
10097 if (insn & 0xf00000)
10098 signed_addend = -signed_addend;
10099 }
2cab6cc3
MS		 10100
10101 relocation = value + signed_addend;
79f08007 10102 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10103 + input_section->output_offset
10104 + rel->r_offset);
2cab6cc3 10105
b6518b38 10106 value = relocation;
2cab6cc3 10107
99059e56
RM		 10108 if (value >= 0x1000)
10109 return bfd_reloc_overflow;
2cab6cc3
MS		 10110
10111 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10112 | ((value & 0x700) << 4)
10113 | ((value & 0x800) << 15);
10114 if (relocation < 0)
10115 insn |= 0xa00000;
2cab6cc3
MS		 10116
10117 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10118 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10119
99059e56 10120 return bfd_reloc_ok;
2cab6cc3
MS		 10121 }
10122
e1ec24c6
NC		 10123 case R_ARM_THM_PC8:
10124 /* PR 10073: This reloc is not generated by the GNU toolchain,
10125 but it is supported for compatibility with third party libraries
10126 generated by other compilers, specifically the ARM/IAR. */
10127 {
10128 bfd_vma insn;
10129 bfd_signed_vma relocation;
10130
10131 insn = bfd_get_16 (input_bfd, hit_data);
10132
99059e56 10133 if (globals->use_rel)
79f08007 10134 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10135
10136 relocation = value + addend;
79f08007 10137 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10138 + input_section->output_offset
10139 + rel->r_offset);
e1ec24c6 10140
b6518b38 10141 value = relocation;
e1ec24c6
NC		 10142
10143 /* We do not check for overflow of this reloc. Although strictly
10144 speaking this is incorrect, it appears to be necessary in order
10145 to work with IAR generated relocs. Since GCC and GAS do not
10146 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10147 a problem for them. */
10148 value &= 0x3fc;
10149
10150 insn = (insn & 0xff00) | (value >> 2);
10151
10152 bfd_put_16 (input_bfd, insn, hit_data);
10153
99059e56 10154 return bfd_reloc_ok;
e1ec24c6
NC		 10155 }
10156
2cab6cc3
MS		 10157 case R_ARM_THM_PC12:
10158 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10159 {
10160 bfd_vma insn;
10161 bfd_signed_vma relocation;
10162
10163 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10164 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10165
99059e56
RM		 10166 if (globals->use_rel)
10167 {
10168 signed_addend = insn & 0xfff;
10169 if (!(insn & (1 << 23)))
10170 signed_addend = -signed_addend;
10171 }
2cab6cc3
MS		 10172
10173 relocation = value + signed_addend;
79f08007 10174 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10175 + input_section->output_offset
10176 + rel->r_offset);
2cab6cc3 10177
b6518b38 10178 value = relocation;
2cab6cc3 10179
99059e56
RM		 10180 if (value >= 0x1000)
10181 return bfd_reloc_overflow;
2cab6cc3
MS		 10182
10183 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10184 if (relocation >= 0)
10185 insn |= (1 << 23);
2cab6cc3
MS		 10186
10187 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10188 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10189
99059e56 10190 return bfd_reloc_ok;
2cab6cc3
MS		 10191 }
10192
dfc5f959 10193 case R_ARM_THM_XPC22:
c19d1205 10194 case R_ARM_THM_CALL:
bd97cb95 10195 case R_ARM_THM_JUMP24:
dfc5f959 10196 /* Thumb BL (branch long instruction). */
252b5132 10197 {
b34976b6 10198 bfd_vma relocation;
99059e56 10199 bfd_vma reloc_sign;
b34976b6
AM		 10200 bfd_boolean overflow = FALSE;
10201 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10202 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10203 bfd_signed_vma reloc_signed_max;
10204 bfd_signed_vma reloc_signed_min;
b34976b6 10205 bfd_vma check;
252b5132 10206 bfd_signed_vma signed_check;
e95de063 10207 int bitsize;
cd1dac3d 10208 const int thumb2 = using_thumb2 (globals);
5e866f5a 10209 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10210
5ab79981 10211 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10212 the next instruction unless a PLT entry will be created.
10213 The jump to the next instruction is optimized as a NOP.W for
10214 Thumb-2 enabled architectures. */
19540007 10215 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10216 && plt_offset == (bfd_vma) -1)
5ab79981 10217 {
60a019a0 10218 if (thumb2)
cd1dac3d
DG		 10219 {
10220 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10221 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10222 }
10223 else
10224 {
10225 bfd_put_16 (input_bfd, 0xe000, hit_data);
10226 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10227 }
5ab79981
PB		 10228 return bfd_reloc_ok;
10229 }
10230
e95de063 10231 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10232 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10233 if (globals->use_rel)
10234 {
99059e56
RM		 10235 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10236 bfd_vma upper = upper_insn & 0x3ff;
10237 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10238 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10239 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10240 bfd_vma i1 = j1 ^ s ? 0 : 1;
10241 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10242
99059e56
RM		 10243 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10244 /* Sign extend. */
10245 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10246
4e7fd91e
PB		 10247 signed_addend = addend;
10248 }
cb1afa5c 10249
dfc5f959
NC		 10250 if (r_type == R_ARM_THM_XPC22)
10251 {
10252 /* Check for Thumb to Thumb call. */
10253 /* FIXME: Should we translate the instruction into a BL
10254 instruction instead ? */
35fc36a8 10255 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 10256 (*_bfd_error_handler)
10257 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10258 input_bfd,
10259 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10260 }
10261 else
252b5132 10262 {
dfc5f959
NC		 10263 /* If it is not a call to Thumb, assume call to Arm.
10264 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10265 function call at all, but rather a long jump. Calls through
10266 the PLT do not require stubs. */
34e77a92 10267 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10268 {
bd97cb95 10269 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10270 {
10271 /* Convert BL to BLX. */
10272 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10273 }
155d87d7
CL		 10274 else if (( r_type != R_ARM_THM_CALL)
10275 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10276 {
10277 if (elf32_thumb_to_arm_stub
10278 (info, sym_name, input_bfd, output_bfd, input_section,
10279 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10280 error_message))
10281 return bfd_reloc_ok;
10282 else
10283 return bfd_reloc_dangerous;
10284 }
da5938a2 10285 }
35fc36a8
RS		 10286 else if (branch_type == ST_BRANCH_TO_THUMB
10287 && globals->use_blx
bd97cb95 10288 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10289 {
10290 /* Make sure this is a BL. */
10291 lower_insn |= 0x1800;
10292 }
252b5132 10293 }
f21f3fe0 10294
fe33d2fa 10295 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10296 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10297 {
10298 /* Check if a stub has to be inserted because the destination
8029a119 10299 is too far. */
fe33d2fa
CL		 10300 struct elf32_arm_stub_hash_entry *stub_entry;
10301 struct elf32_arm_link_hash_entry *hash;
10302
10303 hash = (struct elf32_arm_link_hash_entry *) h;
10304
10305 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10306 st_type, &branch_type,
10307 hash, value, sym_sec,
fe33d2fa
CL		 10308 input_bfd, sym_name);
10309
10310 if (stub_type != arm_stub_none)
906e58ca
NC		 10311 {
10312 /* The target is out of reach or we are changing modes, so
10313 redirect the branch to the local stub for this
10314 function. */
10315 stub_entry = elf32_arm_get_stub_entry (input_section,
10316 sym_sec, h,
fe33d2fa
CL		 10317 rel, globals,
10318 stub_type);
906e58ca 10319 if (stub_entry != NULL)
9cd3e4e5
NC		 10320 {
10321 value = (stub_entry->stub_offset
10322 + stub_entry->stub_sec->output_offset
10323 + stub_entry->stub_sec->output_section->vma);
10324
10325 if (plt_offset != (bfd_vma) -1)
10326 *unresolved_reloc_p = FALSE;
10327 }
906e58ca 10328
f4ac8484 10329 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10330 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10331 {
10332 if ((stub_entry
10333 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10334 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10335 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10336 }
906e58ca
NC		 10337 }
10338 }
10339
fe33d2fa 10340 /* Handle calls via the PLT. */
34e77a92 10341 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10342 {
10343 value = (splt->output_section->vma
10344 + splt->output_offset
34e77a92 10345 + plt_offset);
fe33d2fa 10346
eed94f8f
NC		 10347 if (globals->use_blx
10348 && r_type == R_ARM_THM_CALL
10349 && ! using_thumb_only (globals))
fe33d2fa
CL		 10350 {
10351 /* If the Thumb BLX instruction is available, convert
10352 the BL to a BLX instruction to call the ARM-mode
10353 PLT entry. */
10354 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10355 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10356 }
10357 else
10358 {
eed94f8f
NC		 10359 if (! using_thumb_only (globals))
10360 /* Target the Thumb stub before the ARM PLT entry. */
10361 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10362 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10363 }
10364 *unresolved_reloc_p = FALSE;
10365 }
10366
ba96a88f 10367 relocation = value + signed_addend;
f21f3fe0 10368
252b5132 10369 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10370 + input_section->output_offset
10371 + rel->r_offset);
9a5aca8c 10372
252b5132
RH		 10373 check = relocation >> howto->rightshift;
10374
10375 /* If this is a signed value, the rightshift just dropped
10376 leading 1 bits (assuming twos complement). */
10377 if ((bfd_signed_vma) relocation >= 0)
10378 signed_check = check;
10379 else
10380 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10381
e95de063
MS		 10382 /* Calculate the permissable maximum and minimum values for
10383 this relocation according to whether we're relocating for
10384 Thumb-2 or not. */
10385 bitsize = howto->bitsize;
5e866f5a 10386 if (!thumb2_bl)
e95de063 10387 bitsize -= 2;
f6ebfac0 10388 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10389 reloc_signed_min = ~reloc_signed_max;
10390
252b5132 10391 /* Assumes two's complement. */
ba96a88f 10392 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10393 overflow = TRUE;
252b5132 10394
bd97cb95 10395 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10396 /* For a BLX instruction, make sure that the relocation is rounded up
10397 to a word boundary. This follows the semantics of the instruction
10398 which specifies that bit 1 of the target address will come from bit
10399 1 of the base address. */
10400 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10401
e95de063
MS		 10402 /* Put RELOCATION back into the insn. Assumes two's complement.
10403 We use the Thumb-2 encoding, which is safe even if dealing with
10404 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10405 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10406 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10407 | ((relocation >> 12) & 0x3ff)
10408 | (reloc_sign << 10);
906e58ca 10409 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10410 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10411 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10412 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10413
252b5132
RH		 10414 /* Put the relocated value back in the object file: */
10415 bfd_put_16 (input_bfd, upper_insn, hit_data);
10416 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10417
10418 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10419 }
10420 break;
10421
c19d1205
ZW		 10422 case R_ARM_THM_JUMP19:
10423 /* Thumb32 conditional branch instruction. */
10424 {
10425 bfd_vma relocation;
10426 bfd_boolean overflow = FALSE;
10427 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10428 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10429 bfd_signed_vma reloc_signed_max = 0xffffe;
10430 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10431 bfd_signed_vma signed_check;
c5423981
TG		 10432 enum elf32_arm_stub_type stub_type = arm_stub_none;
10433 struct elf32_arm_stub_hash_entry *stub_entry;
10434 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10435
10436 /* Need to refetch the addend, reconstruct the top three bits,
10437 and squish the two 11 bit pieces together. */
10438 if (globals->use_rel)
10439 {
10440 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10441 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10442 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10443 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10444 bfd_vma lower = (lower_insn & 0x07ff);
10445
a00a1f35
MS		 10446 upper |= J1 << 6;
10447 upper |= J2 << 7;
10448 upper |= (!S) << 8;
c19d1205
ZW		 10449 upper -= 0x0100; /* Sign extend. */
10450
10451 addend = (upper << 12) | (lower << 1);
10452 signed_addend = addend;
10453 }
10454
bd97cb95 10455 /* Handle calls via the PLT. */
34e77a92 10456 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10457 {
10458 value = (splt->output_section->vma
10459 + splt->output_offset
34e77a92 10460 + plt_offset);
bd97cb95
DJ		 10461 /* Target the Thumb stub before the ARM PLT entry. */
10462 value -= PLT_THUMB_STUB_SIZE;
10463 *unresolved_reloc_p = FALSE;
10464 }
10465
c5423981
TG		 10466 hash = (struct elf32_arm_link_hash_entry *)h;
10467
10468 stub_type = arm_type_of_stub (info, input_section, rel,
10469 st_type, &branch_type,
10470 hash, value, sym_sec,
10471 input_bfd, sym_name);
10472 if (stub_type != arm_stub_none)
10473 {
10474 stub_entry = elf32_arm_get_stub_entry (input_section,
10475 sym_sec, h,
10476 rel, globals,
10477 stub_type);
10478 if (stub_entry != NULL)
10479 {
10480 value = (stub_entry->stub_offset
10481 + stub_entry->stub_sec->output_offset
10482 + stub_entry->stub_sec->output_section->vma);
10483 }
10484 }
c19d1205 10485
99059e56 10486 relocation = value + signed_addend;
c19d1205
ZW		 10487 relocation -= (input_section->output_section->vma
10488 + input_section->output_offset
10489 + rel->r_offset);
a00a1f35 10490 signed_check = (bfd_signed_vma) relocation;
c19d1205 10491
c19d1205
ZW		 10492 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10493 overflow = TRUE;
10494
10495 /* Put RELOCATION back into the insn. */
10496 {
10497 bfd_vma S = (relocation & 0x00100000) >> 20;
10498 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10499 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10500 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10501 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10502
a00a1f35 10503 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10504 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10505 }
10506
10507 /* Put the relocated value back in the object file: */
10508 bfd_put_16 (input_bfd, upper_insn, hit_data);
10509 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10510
10511 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10512 }
10513
10514 case R_ARM_THM_JUMP11:
10515 case R_ARM_THM_JUMP8:
10516 case R_ARM_THM_JUMP6:
51c5503b
NC		 10517 /* Thumb B (branch) instruction). */
10518 {
6cf9e9fe 10519 bfd_signed_vma relocation;
51c5503b
NC		 10520 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10521 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10522 bfd_signed_vma signed_check;
10523
c19d1205
ZW		 10524 /* CZB cannot jump backward. */
10525 if (r_type == R_ARM_THM_JUMP6)
10526 reloc_signed_min = 0;
10527
4e7fd91e 10528 if (globals->use_rel)
6cf9e9fe 10529 {
4e7fd91e
PB		 10530 /* Need to refetch addend. */
10531 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10532 if (addend & ((howto->src_mask + 1) >> 1))
10533 {
10534 signed_addend = -1;
10535 signed_addend &= ~ howto->src_mask;
10536 signed_addend |= addend;
10537 }
10538 else
10539 signed_addend = addend;
10540 /* The value in the insn has been right shifted. We need to
10541 undo this, so that we can perform the address calculation
10542 in terms of bytes. */
10543 signed_addend <<= howto->rightshift;
6cf9e9fe 10544 }
6cf9e9fe 10545 relocation = value + signed_addend;
51c5503b
NC		 10546
10547 relocation -= (input_section->output_section->vma
10548 + input_section->output_offset
10549 + rel->r_offset);
10550
6cf9e9fe
NC		 10551 relocation >>= howto->rightshift;
10552 signed_check = relocation;
c19d1205
ZW		 10553
10554 if (r_type == R_ARM_THM_JUMP6)
10555 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10556 else
10557 relocation &= howto->dst_mask;
51c5503b 10558 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10559
51c5503b
NC		 10560 bfd_put_16 (input_bfd, relocation, hit_data);
10561
10562 /* Assumes two's complement. */
10563 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10564 return bfd_reloc_overflow;
10565
10566 return bfd_reloc_ok;
10567 }
cedb70c5 10568
8375c36b
PB		 10569 case R_ARM_ALU_PCREL7_0:
10570 case R_ARM_ALU_PCREL15_8:
10571 case R_ARM_ALU_PCREL23_15:
10572 {
10573 bfd_vma insn;
10574 bfd_vma relocation;
10575
10576 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10577 if (globals->use_rel)
10578 {
10579 /* Extract the addend. */
10580 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10581 signed_addend = addend;
10582 }
8375c36b
PB		 10583 relocation = value + signed_addend;
10584
10585 relocation -= (input_section->output_section->vma
10586 + input_section->output_offset
10587 + rel->r_offset);
10588 insn = (insn & ~0xfff)
10589 | ((howto->bitpos << 7) & 0xf00)
10590 | ((relocation >> howto->bitpos) & 0xff);
10591 bfd_put_32 (input_bfd, value, hit_data);
10592 }
10593 return bfd_reloc_ok;
10594
252b5132
RH		 10595 case R_ARM_GNU_VTINHERIT:
10596 case R_ARM_GNU_VTENTRY:
10597 return bfd_reloc_ok;
10598
c19d1205 10599 case R_ARM_GOTOFF32:
252b5132 10600 /* Relocation is relative to the start of the
99059e56 10601 global offset table. */
252b5132
RH		 10602
10603 BFD_ASSERT (sgot != NULL);
10604 if (sgot == NULL)
99059e56 10605 return bfd_reloc_notsupported;
9a5aca8c 10606
cedb70c5 10607 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 10608 address by one, so that attempts to call the function pointer will
10609 correctly interpret it as Thumb code. */
35fc36a8 10610 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 10611 value += 1;
10612
252b5132 10613 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 10614 calculation. We always want the start of .got. If we
10615 define _GLOBAL_OFFSET_TABLE in a different way, as is
10616 permitted by the ABI, we might have to change this
10617 calculation. */
252b5132 10618 value -= sgot->output_section->vma;
f21f3fe0 10619 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10620 contents, rel->r_offset, value,
00a97672 10621 rel->r_addend);
252b5132
RH		 10622
10623 case R_ARM_GOTPC:
a7c10850 10624 /* Use global offset table as symbol value. */
252b5132 10625 BFD_ASSERT (sgot != NULL);
f21f3fe0 10626
252b5132 10627 if (sgot == NULL)
99059e56 10628 return bfd_reloc_notsupported;
252b5132 10629
0945cdfd 10630 *unresolved_reloc_p = FALSE;
252b5132 10631 value = sgot->output_section->vma;
f21f3fe0 10632 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10633 contents, rel->r_offset, value,
00a97672 10634 rel->r_addend);
f21f3fe0 10635
252b5132 10636 case R_ARM_GOT32:
eb043451 10637 case R_ARM_GOT_PREL:
252b5132 10638 /* Relocation is to the entry for this symbol in the
99059e56 10639 global offset table. */
252b5132
RH		 10640 if (sgot == NULL)
10641 return bfd_reloc_notsupported;
f21f3fe0 10642
34e77a92
RS		 10643 if (dynreloc_st_type == STT_GNU_IFUNC
10644 && plt_offset != (bfd_vma) -1
10645 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
10646 {
10647 /* We have a relocation against a locally-binding STT_GNU_IFUNC
10648 symbol, and the relocation resolves directly to the runtime
10649 target rather than to the .iplt entry. This means that any
10650 .got entry would be the same value as the .igot.plt entry,
10651 so there's no point creating both. */
10652 sgot = globals->root.igotplt;
10653 value = sgot->output_offset + gotplt_offset;
10654 }
10655 else if (h != NULL)
252b5132
RH		 10656 {
10657 bfd_vma off;
f21f3fe0 10658
252b5132
RH		 10659 off = h->got.offset;
10660 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 10661 if ((off & 1) != 0)
252b5132 10662 {
b436d854
RS		 10663 /* We have already processsed one GOT relocation against
10664 this symbol. */
10665 off &= ~1;
10666 if (globals->root.dynamic_sections_created
10667 && !SYMBOL_REFERENCES_LOCAL (info, h))
10668 *unresolved_reloc_p = FALSE;
10669 }
10670 else
10671 {
10672 Elf_Internal_Rela outrel;
10673
6f820c85 10674 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 10675 {
10676 /* If the symbol doesn't resolve locally in a static
10677 object, we have an undefined reference. If the
10678 symbol doesn't resolve locally in a dynamic object,
10679 it should be resolved by the dynamic linker. */
10680 if (globals->root.dynamic_sections_created)
10681 {
10682 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
10683 *unresolved_reloc_p = FALSE;
10684 }
10685 else
10686 outrel.r_info = 0;
10687 outrel.r_addend = 0;
10688 }
252b5132
RH		 10689 else
10690 {
34e77a92 10691 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10692 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 10693 else if (bfd_link_pic (info) &&
31943882
WN		 10694 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10695 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 10696 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
10697 else
10698 outrel.r_info = 0;
34e77a92 10699 outrel.r_addend = dynreloc_value;
b436d854 10700 }
ee29b9fb 10701
b436d854
RS		 10702 /* The GOT entry is initialized to zero by default.
10703 See if we should install a different value. */
10704 if (outrel.r_addend != 0
10705 && (outrel.r_info == 0 || globals->use_rel))
10706 {
10707 bfd_put_32 (output_bfd, outrel.r_addend,
10708 sgot->contents + off);
10709 outrel.r_addend = 0;
252b5132 10710 }
f21f3fe0 10711
b436d854
RS		 10712 if (outrel.r_info != 0)
10713 {
10714 outrel.r_offset = (sgot->output_section->vma
10715 + sgot->output_offset
10716 + off);
10717 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
10718 }
10719 h->got.offset |= 1;
10720 }
252b5132
RH		 10721 value = sgot->output_offset + off;
10722 }
10723 else
10724 {
10725 bfd_vma off;
f21f3fe0 10726
252b5132
RH		 10727 BFD_ASSERT (local_got_offsets != NULL &&
10728 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 10729
252b5132 10730 off = local_got_offsets[r_symndx];
f21f3fe0 10731
252b5132
RH		 10732 /* The offset must always be a multiple of 4. We use the
10733 least significant bit to record whether we have already
9b485d32 10734 generated the necessary reloc. */
252b5132
RH		 10735 if ((off & 1) != 0)
10736 off &= ~1;
10737 else
10738 {
00a97672 10739 if (globals->use_rel)
34e77a92 10740 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 10741
0e1862bb 10742 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 10743 {
947216bf 10744 Elf_Internal_Rela outrel;
f21f3fe0 10745
34e77a92 10746 outrel.r_addend = addend + dynreloc_value;
252b5132 10747 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 10748 + sgot->output_offset
252b5132 10749 + off);
34e77a92 10750 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10751 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 10752 else
10753 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 10754 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 10755 }
f21f3fe0 10756
252b5132
RH		 10757 local_got_offsets[r_symndx] |= 1;
10758 }
f21f3fe0 10759
252b5132
RH		 10760 value = sgot->output_offset + off;
10761 }
eb043451
PB		 10762 if (r_type != R_ARM_GOT32)
10763 value += sgot->output_section->vma;
9a5aca8c 10764
f21f3fe0 10765 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10766 contents, rel->r_offset, value,
00a97672 10767 rel->r_addend);
f21f3fe0 10768
ba93b8ac
DJ		 10769 case R_ARM_TLS_LDO32:
10770 value = value - dtpoff_base (info);
10771
10772 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10773 contents, rel->r_offset, value,
10774 rel->r_addend);
ba93b8ac
DJ		 10775
10776 case R_ARM_TLS_LDM32:
10777 {
10778 bfd_vma off;
10779
362d30a1 10780 if (sgot == NULL)
ba93b8ac
DJ		 10781 abort ();
10782
10783 off = globals->tls_ldm_got.offset;
10784
10785 if ((off & 1) != 0)
10786 off &= ~1;
10787 else
10788 {
10789 /* If we don't know the module number, create a relocation
10790 for it. */
0e1862bb 10791 if (bfd_link_pic (info))
ba93b8ac
DJ		 10792 {
10793 Elf_Internal_Rela outrel;
ba93b8ac 10794
362d30a1 10795 if (srelgot == NULL)
ba93b8ac
DJ		 10796 abort ();
10797
00a97672 10798 outrel.r_addend = 0;
362d30a1
RS		 10799 outrel.r_offset = (sgot->output_section->vma
10800 + sgot->output_offset + off);
ba93b8ac
DJ		 10801 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
10802
00a97672
RS		 10803 if (globals->use_rel)
10804 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10805 sgot->contents + off);
ba93b8ac 10806
47beaa6a 10807 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10808 }
10809 else
362d30a1 10810 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 10811
10812 globals->tls_ldm_got.offset |= 1;
10813 }
10814
362d30a1 10815 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 10816 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
10817
10818 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10819 contents, rel->r_offset, value,
00a97672 10820 rel->r_addend);
ba93b8ac
DJ		 10821 }
10822
0855e32b
NS		 10823 case R_ARM_TLS_CALL:
10824 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 10825 case R_ARM_TLS_GD32:
10826 case R_ARM_TLS_IE32:
0855e32b
NS		 10827 case R_ARM_TLS_GOTDESC:
10828 case R_ARM_TLS_DESCSEQ:
10829 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 10830 {
0855e32b
NS		 10831 bfd_vma off, offplt;
10832 int indx = 0;
ba93b8ac
DJ		 10833 char tls_type;
10834
0855e32b 10835 BFD_ASSERT (sgot != NULL);
ba93b8ac 10836
ba93b8ac
DJ		 10837 if (h != NULL)
10838 {
10839 bfd_boolean dyn;
10840 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 10841 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
10842 bfd_link_pic (info),
10843 h)
10844 && (!bfd_link_pic (info)
ba93b8ac
DJ		 10845 || !SYMBOL_REFERENCES_LOCAL (info, h)))
10846 {
10847 *unresolved_reloc_p = FALSE;
10848 indx = h->dynindx;
10849 }
10850 off = h->got.offset;
0855e32b 10851 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 10852 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
10853 }
10854 else
10855 {
0855e32b 10856 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 10857 off = local_got_offsets[r_symndx];
0855e32b 10858 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 10859 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
10860 }
10861
0855e32b 10862 /* Linker relaxations happens from one of the
b38cadfb 10863 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 10864 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 10865 tls_type = GOT_TLS_IE;
0855e32b
NS		 10866
10867 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 10868
10869 if ((off & 1) != 0)
10870 off &= ~1;
10871 else
10872 {
10873 bfd_boolean need_relocs = FALSE;
10874 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 10875 int cur_off = off;
10876
10877 /* The GOT entries have not been initialized yet. Do it
10878 now, and emit any relocations. If both an IE GOT and a
10879 GD GOT are necessary, we emit the GD first. */
10880
0e1862bb 10881 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 10882 && (h == NULL
10883 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10884 || h->root.type != bfd_link_hash_undefweak))
10885 {
10886 need_relocs = TRUE;
0855e32b 10887 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 10888 }
10889
0855e32b
NS		 10890 if (tls_type & GOT_TLS_GDESC)
10891 {
47beaa6a
RS		 10892 bfd_byte *loc;
10893
0855e32b
NS		 10894 /* We should have relaxed, unless this is an undefined
10895 weak symbol. */
10896 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 10897 || bfd_link_pic (info));
0855e32b 10898 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 10899 <= globals->root.sgotplt->size);
0855e32b
NS		 10900
10901 outrel.r_addend = 0;
10902 outrel.r_offset = (globals->root.sgotplt->output_section->vma
10903 + globals->root.sgotplt->output_offset
10904 + offplt
10905 + globals->sgotplt_jump_table_size);
b38cadfb 10906
0855e32b
NS		 10907 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
10908 sreloc = globals->root.srelplt;
10909 loc = sreloc->contents;
10910 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
10911 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 10912 <= sreloc->contents + sreloc->size);
0855e32b
NS		 10913
10914 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
10915
10916 /* For globals, the first word in the relocation gets
10917 the relocation index and the top bit set, or zero,
10918 if we're binding now. For locals, it gets the
10919 symbol's offset in the tls section. */
99059e56 10920 bfd_put_32 (output_bfd,
0855e32b
NS		 10921 !h ? value - elf_hash_table (info)->tls_sec->vma
10922 : info->flags & DF_BIND_NOW ? 0
10923 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 10924 globals->root.sgotplt->contents + offplt
10925 + globals->sgotplt_jump_table_size);
10926
0855e32b 10927 /* Second word in the relocation is always zero. */
99059e56 10928 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 10929 globals->root.sgotplt->contents + offplt
10930 + globals->sgotplt_jump_table_size + 4);
0855e32b 10931 }
ba93b8ac
DJ		 10932 if (tls_type & GOT_TLS_GD)
10933 {
10934 if (need_relocs)
10935 {
00a97672 10936 outrel.r_addend = 0;
362d30a1
RS		 10937 outrel.r_offset = (sgot->output_section->vma
10938 + sgot->output_offset
00a97672 10939 + cur_off);
ba93b8ac 10940 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 10941
00a97672
RS		 10942 if (globals->use_rel)
10943 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10944 sgot->contents + cur_off);
00a97672 10945
47beaa6a 10946 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10947
10948 if (indx == 0)
10949 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10950 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10951 else
10952 {
00a97672 10953 outrel.r_addend = 0;
ba93b8ac
DJ		 10954 outrel.r_info = ELF32_R_INFO (indx,
10955 R_ARM_TLS_DTPOFF32);
10956 outrel.r_offset += 4;
00a97672
RS		 10957
10958 if (globals->use_rel)
10959 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10960 sgot->contents + cur_off + 4);
00a97672 10961
47beaa6a
RS		 10962 elf32_arm_add_dynreloc (output_bfd, info,
10963 srelgot, &outrel);
ba93b8ac
DJ		 10964 }
10965 }
10966 else
10967 {
10968 /* If we are not emitting relocations for a
10969 general dynamic reference, then we must be in a
10970 static link or an executable link with the
10971 symbol binding locally. Mark it as belonging
10972 to module 1, the executable. */
10973 bfd_put_32 (output_bfd, 1,
362d30a1 10974 sgot->contents + cur_off);
ba93b8ac 10975 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10976 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10977 }
10978
10979 cur_off += 8;
10980 }
10981
10982 if (tls_type & GOT_TLS_IE)
10983 {
10984 if (need_relocs)
10985 {
00a97672
RS		 10986 if (indx == 0)
10987 outrel.r_addend = value - dtpoff_base (info);
10988 else
10989 outrel.r_addend = 0;
362d30a1
RS		 10990 outrel.r_offset = (sgot->output_section->vma
10991 + sgot->output_offset
ba93b8ac
DJ		 10992 + cur_off);
10993 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
10994
00a97672
RS		 10995 if (globals->use_rel)
10996 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10997 sgot->contents + cur_off);
ba93b8ac 10998
47beaa6a 10999 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11000 }
11001 else
11002 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11003 sgot->contents + cur_off);
ba93b8ac
DJ		 11004 cur_off += 4;
11005 }
11006
11007 if (h != NULL)
11008 h->got.offset |= 1;
11009 else
11010 local_got_offsets[r_symndx] |= 1;
11011 }
11012
11013 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11014 off += 8;
0855e32b
NS		 11015 else if (tls_type & GOT_TLS_GDESC)
11016 off = offplt;
11017
11018 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11019 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11020 {
11021 bfd_signed_vma offset;
12352d3f
PB		 11022 /* TLS stubs are arm mode. The original symbol is a
11023 data object, so branch_type is bogus. */
11024 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11025 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11026 = arm_type_of_stub (info, input_section, rel,
11027 st_type, &branch_type,
0855e32b
NS		 11028 (struct elf32_arm_link_hash_entry *)h,
11029 globals->tls_trampoline, globals->root.splt,
11030 input_bfd, sym_name);
11031
11032 if (stub_type != arm_stub_none)
11033 {
11034 struct elf32_arm_stub_hash_entry *stub_entry
11035 = elf32_arm_get_stub_entry
11036 (input_section, globals->root.splt, 0, rel,
11037 globals, stub_type);
11038 offset = (stub_entry->stub_offset
11039 + stub_entry->stub_sec->output_offset
11040 + stub_entry->stub_sec->output_section->vma);
11041 }
11042 else
11043 offset = (globals->root.splt->output_section->vma
11044 + globals->root.splt->output_offset
11045 + globals->tls_trampoline);
11046
11047 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11048 {
11049 unsigned long inst;
b38cadfb
NC		 11050
11051 offset -= (input_section->output_section->vma
11052 + input_section->output_offset
11053 + rel->r_offset + 8);
0855e32b
NS		 11054
11055 inst = offset >> 2;
11056 inst &= 0x00ffffff;
11057 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11058 }
11059 else
11060 {
11061 /* Thumb blx encodes the offset in a complicated
11062 fashion. */
11063 unsigned upper_insn, lower_insn;
11064 unsigned neg;
11065
b38cadfb
NC		 11066 offset -= (input_section->output_section->vma
11067 + input_section->output_offset
0855e32b 11068 + rel->r_offset + 4);
b38cadfb 11069
12352d3f
PB		 11070 if (stub_type != arm_stub_none
11071 && arm_stub_is_thumb (stub_type))
11072 {
11073 lower_insn = 0xd000;
11074 }
11075 else
11076 {
11077 lower_insn = 0xc000;
6a631e86 11078 /* Round up the offset to a word boundary. */
12352d3f
PB		 11079 offset = (offset + 2) & ~2;
11080 }
11081
0855e32b
NS		 11082 neg = offset < 0;
11083 upper_insn = (0xf000
11084 | ((offset >> 12) & 0x3ff)
11085 | (neg << 10));
12352d3f 11086 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11087 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11088 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11089 bfd_put_16 (input_bfd, upper_insn, hit_data);
11090 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11091 return bfd_reloc_ok;
11092 }
11093 }
11094 /* These relocations needs special care, as besides the fact
11095 they point somewhere in .gotplt, the addend must be
11096 adjusted accordingly depending on the type of instruction
6a631e86 11097 we refer to. */
0855e32b
NS		 11098 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11099 {
11100 unsigned long data, insn;
11101 unsigned thumb;
b38cadfb 11102
0855e32b
NS		 11103 data = bfd_get_32 (input_bfd, hit_data);
11104 thumb = data & 1;
11105 data &= ~1u;
b38cadfb 11106
0855e32b
NS		 11107 if (thumb)
11108 {
11109 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11110 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11111 insn = (insn << 16)
11112 | bfd_get_16 (input_bfd,
11113 contents + rel->r_offset - data + 2);
11114 if ((insn & 0xf800c000) == 0xf000c000)
11115 /* bl/blx */
11116 value = -6;
11117 else if ((insn & 0xffffff00) == 0x4400)
11118 /* add */
11119 value = -5;
11120 else
11121 {
11122 (*_bfd_error_handler)
11123 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
11124 input_bfd, input_section,
11125 (unsigned long)rel->r_offset, insn);
11126 return bfd_reloc_notsupported;
11127 }
11128 }
11129 else
11130 {
11131 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11132
11133 switch (insn >> 24)
11134 {
11135 case 0xeb: /* bl */
11136 case 0xfa: /* blx */
11137 value = -4;
11138 break;
11139
11140 case 0xe0: /* add */
11141 value = -8;
11142 break;
b38cadfb 11143
0855e32b
NS		 11144 default:
11145 (*_bfd_error_handler)
11146 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
11147 input_bfd, input_section,
11148 (unsigned long)rel->r_offset, insn);
11149 return bfd_reloc_notsupported;
11150 }
11151 }
b38cadfb 11152
0855e32b
NS		 11153 value += ((globals->root.sgotplt->output_section->vma
11154 + globals->root.sgotplt->output_offset + off)
11155 - (input_section->output_section->vma
11156 + input_section->output_offset
11157 + rel->r_offset)
11158 + globals->sgotplt_jump_table_size);
11159 }
11160 else
11161 value = ((globals->root.sgot->output_section->vma
11162 + globals->root.sgot->output_offset + off)
11163 - (input_section->output_section->vma
11164 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11165
11166 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11167 contents, rel->r_offset, value,
00a97672 11168 rel->r_addend);
ba93b8ac
DJ		 11169 }
11170
11171 case R_ARM_TLS_LE32:
3cbc1e5e 11172 if (bfd_link_dll (info))
ba93b8ac
DJ		 11173 {
11174 (*_bfd_error_handler)
11175 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
11176 input_bfd, input_section,
11177 (long) rel->r_offset, howto->name);
46691134 11178 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11179 }
11180 else
11181 value = tpoff (info, value);
906e58ca 11182
ba93b8ac 11183 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11184 contents, rel->r_offset, value,
11185 rel->r_addend);
ba93b8ac 11186
319850b4
JB		 11187 case R_ARM_V4BX:
11188 if (globals->fix_v4bx)
845b51d6
PB		 11189 {
11190 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11191
845b51d6
PB		 11192 /* Ensure that we have a BX instruction. */
11193 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11194
845b51d6
PB		 11195 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11196 {
11197 /* Branch to veneer. */
11198 bfd_vma glue_addr;
11199 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11200 glue_addr -= input_section->output_section->vma
11201 + input_section->output_offset
11202 + rel->r_offset + 8;
11203 insn = (insn & 0xf0000000) | 0x0a000000
11204 | ((glue_addr >> 2) & 0x00ffffff);
11205 }
11206 else
11207 {
11208 /* Preserve Rm (lowest four bits) and the condition code
11209 (highest four bits). Other bits encode MOV PC,Rm. */
11210 insn = (insn & 0xf000000f) | 0x01a0f000;
11211 }
319850b4 11212
845b51d6
PB		 11213 bfd_put_32 (input_bfd, insn, hit_data);
11214 }
319850b4
JB		 11215 return bfd_reloc_ok;
11216
b6895b4f
PB		 11217 case R_ARM_MOVW_ABS_NC:
11218 case R_ARM_MOVT_ABS:
11219 case R_ARM_MOVW_PREL_NC:
11220 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11221 /* Until we properly support segment-base-relative addressing then
11222 we assume the segment base to be zero, as for the group relocations.
11223 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11224 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11225 case R_ARM_MOVW_BREL_NC:
11226 case R_ARM_MOVW_BREL:
11227 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11228 {
11229 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11230
11231 if (globals->use_rel)
11232 {
11233 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11234 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11235 }
92f5d02b 11236
b6895b4f 11237 value += signed_addend;
b6895b4f
PB		 11238
11239 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11240 value -= (input_section->output_section->vma
11241 + input_section->output_offset + rel->r_offset);
11242
92f5d02b 11243 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11244 return bfd_reloc_overflow;
92f5d02b 11245
35fc36a8 11246 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11247 value |= 1;
11248
11249 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11250 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11251 value >>= 16;
11252
11253 insn &= 0xfff0f000;
11254 insn |= value & 0xfff;
11255 insn |= (value & 0xf000) << 4;
11256 bfd_put_32 (input_bfd, insn, hit_data);
11257 }
11258 return bfd_reloc_ok;
11259
11260 case R_ARM_THM_MOVW_ABS_NC:
11261 case R_ARM_THM_MOVT_ABS:
11262 case R_ARM_THM_MOVW_PREL_NC:
11263 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11264 /* Until we properly support segment-base-relative addressing then
11265 we assume the segment base to be zero, as for the above relocations.
11266 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11267 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11268 as R_ARM_THM_MOVT_ABS. */
11269 case R_ARM_THM_MOVW_BREL_NC:
11270 case R_ARM_THM_MOVW_BREL:
11271 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11272 {
11273 bfd_vma insn;
906e58ca 11274
b6895b4f
PB		 11275 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11276 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11277
11278 if (globals->use_rel)
11279 {
11280 addend = ((insn >> 4) & 0xf000)
11281 | ((insn >> 15) & 0x0800)
11282 | ((insn >> 4) & 0x0700)
11283 | (insn & 0x00ff);
39623e12 11284 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11285 }
92f5d02b 11286
b6895b4f 11287 value += signed_addend;
b6895b4f
PB		 11288
11289 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11290 value -= (input_section->output_section->vma
11291 + input_section->output_offset + rel->r_offset);
11292
92f5d02b 11293 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11294 return bfd_reloc_overflow;
92f5d02b 11295
35fc36a8 11296 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11297 value |= 1;
11298
11299 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11300 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11301 value >>= 16;
11302
11303 insn &= 0xfbf08f00;
11304 insn |= (value & 0xf000) << 4;
11305 insn |= (value & 0x0800) << 15;
11306 insn |= (value & 0x0700) << 4;
11307 insn |= (value & 0x00ff);
11308
11309 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11310 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11311 }
11312 return bfd_reloc_ok;
11313
4962c51a
MS		 11314 case R_ARM_ALU_PC_G0_NC:
11315 case R_ARM_ALU_PC_G1_NC:
11316 case R_ARM_ALU_PC_G0:
11317 case R_ARM_ALU_PC_G1:
11318 case R_ARM_ALU_PC_G2:
11319 case R_ARM_ALU_SB_G0_NC:
11320 case R_ARM_ALU_SB_G1_NC:
11321 case R_ARM_ALU_SB_G0:
11322 case R_ARM_ALU_SB_G1:
11323 case R_ARM_ALU_SB_G2:
11324 {
11325 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11326 bfd_vma pc = input_section->output_section->vma
4962c51a 11327 + input_section->output_offset + rel->r_offset;
31a91d61 11328 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11329 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11330 bfd_vma residual;
11331 bfd_vma g_n;
4962c51a 11332 bfd_signed_vma signed_value;
99059e56
RM		 11333 int group = 0;
11334
11335 /* Determine which group of bits to select. */
11336 switch (r_type)
11337 {
11338 case R_ARM_ALU_PC_G0_NC:
11339 case R_ARM_ALU_PC_G0:
11340 case R_ARM_ALU_SB_G0_NC:
11341 case R_ARM_ALU_SB_G0:
11342 group = 0;
11343 break;
11344
11345 case R_ARM_ALU_PC_G1_NC:
11346 case R_ARM_ALU_PC_G1:
11347 case R_ARM_ALU_SB_G1_NC:
11348 case R_ARM_ALU_SB_G1:
11349 group = 1;
11350 break;
11351
11352 case R_ARM_ALU_PC_G2:
11353 case R_ARM_ALU_SB_G2:
11354 group = 2;
11355 break;
11356
11357 default:
11358 abort ();
11359 }
11360
11361 /* If REL, extract the addend from the insn. If RELA, it will
11362 have already been fetched for us. */
4962c51a 11363 if (globals->use_rel)
99059e56
RM		 11364 {
11365 int negative;
11366 bfd_vma constant = insn & 0xff;
11367 bfd_vma rotation = (insn & 0xf00) >> 8;
11368
11369 if (rotation == 0)
11370 signed_addend = constant;
11371 else
11372 {
11373 /* Compensate for the fact that in the instruction, the
11374 rotation is stored in multiples of 2 bits. */
11375 rotation *= 2;
11376
11377 /* Rotate "constant" right by "rotation" bits. */
11378 signed_addend = (constant >> rotation) |
11379 (constant << (8 * sizeof (bfd_vma) - rotation));
11380 }
11381
11382 /* Determine if the instruction is an ADD or a SUB.
11383 (For REL, this determines the sign of the addend.) */
11384 negative = identify_add_or_sub (insn);
11385 if (negative == 0)
11386 {
11387 (*_bfd_error_handler)
11388 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11389 input_bfd, input_section,
11390 (long) rel->r_offset, howto->name);
11391 return bfd_reloc_overflow;
11392 }
11393
11394 signed_addend *= negative;
11395 }
4962c51a
MS		 11396
11397 /* Compute the value (X) to go in the place. */
99059e56
RM		 11398 if (r_type == R_ARM_ALU_PC_G0_NC
11399 || r_type == R_ARM_ALU_PC_G1_NC
11400 || r_type == R_ARM_ALU_PC_G0
11401 || r_type == R_ARM_ALU_PC_G1
11402 || r_type == R_ARM_ALU_PC_G2)
11403 /* PC relative. */
11404 signed_value = value - pc + signed_addend;
11405 else
11406 /* Section base relative. */
11407 signed_value = value - sb + signed_addend;
11408
11409 /* If the target symbol is a Thumb function, then set the
11410 Thumb bit in the address. */
35fc36a8 11411 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11412 signed_value |= 1;
11413
99059e56
RM		 11414 /* Calculate the value of the relevant G_n, in encoded
11415 constant-with-rotation format. */
b6518b38
NC		 11416 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11417 group, &residual);
99059e56
RM		 11418
11419 /* Check for overflow if required. */
11420 if ((r_type == R_ARM_ALU_PC_G0
11421 || r_type == R_ARM_ALU_PC_G1
11422 || r_type == R_ARM_ALU_PC_G2
11423 || r_type == R_ARM_ALU_SB_G0
11424 || r_type == R_ARM_ALU_SB_G1
11425 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11426 {
11427 (*_bfd_error_handler)
11428 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11429 input_bfd, input_section,
b6518b38
NC		 11430 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11431 howto->name);
99059e56
RM		 11432 return bfd_reloc_overflow;
11433 }
11434
11435 /* Mask out the value and the ADD/SUB part of the opcode; take care
11436 not to destroy the S bit. */
11437 insn &= 0xff1ff000;
11438
11439 /* Set the opcode according to whether the value to go in the
11440 place is negative. */
11441 if (signed_value < 0)
11442 insn |= 1 << 22;
11443 else
11444 insn |= 1 << 23;
11445
11446 /* Encode the offset. */
11447 insn |= g_n;
4962c51a
MS		 11448
11449 bfd_put_32 (input_bfd, insn, hit_data);
11450 }
11451 return bfd_reloc_ok;
11452
11453 case R_ARM_LDR_PC_G0:
11454 case R_ARM_LDR_PC_G1:
11455 case R_ARM_LDR_PC_G2:
11456 case R_ARM_LDR_SB_G0:
11457 case R_ARM_LDR_SB_G1:
11458 case R_ARM_LDR_SB_G2:
11459 {
11460 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11461 bfd_vma pc = input_section->output_section->vma
4962c51a 11462 + input_section->output_offset + rel->r_offset;
31a91d61 11463 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11464 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11465 bfd_vma residual;
4962c51a 11466 bfd_signed_vma signed_value;
99059e56
RM		 11467 int group = 0;
11468
11469 /* Determine which groups of bits to calculate. */
11470 switch (r_type)
11471 {
11472 case R_ARM_LDR_PC_G0:
11473 case R_ARM_LDR_SB_G0:
11474 group = 0;
11475 break;
11476
11477 case R_ARM_LDR_PC_G1:
11478 case R_ARM_LDR_SB_G1:
11479 group = 1;
11480 break;
11481
11482 case R_ARM_LDR_PC_G2:
11483 case R_ARM_LDR_SB_G2:
11484 group = 2;
11485 break;
11486
11487 default:
11488 abort ();
11489 }
11490
11491 /* If REL, extract the addend from the insn. If RELA, it will
11492 have already been fetched for us. */
4962c51a 11493 if (globals->use_rel)
99059e56
RM		 11494 {
11495 int negative = (insn & (1 << 23)) ? 1 : -1;
11496 signed_addend = negative * (insn & 0xfff);
11497 }
4962c51a
MS		 11498
11499 /* Compute the value (X) to go in the place. */
99059e56
RM		 11500 if (r_type == R_ARM_LDR_PC_G0
11501 || r_type == R_ARM_LDR_PC_G1
11502 || r_type == R_ARM_LDR_PC_G2)
11503 /* PC relative. */
11504 signed_value = value - pc + signed_addend;
11505 else
11506 /* Section base relative. */
11507 signed_value = value - sb + signed_addend;
11508
11509 /* Calculate the value of the relevant G_{n-1} to obtain
11510 the residual at that stage. */
b6518b38
NC		 11511 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11512 group - 1, &residual);
99059e56
RM		 11513
11514 /* Check for overflow. */
11515 if (residual >= 0x1000)
11516 {
11517 (*_bfd_error_handler)
11518 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11519 input_bfd, input_section,
11520 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11521 return bfd_reloc_overflow;
11522 }
11523
11524 /* Mask out the value and U bit. */
11525 insn &= 0xff7ff000;
11526
11527 /* Set the U bit if the value to go in the place is non-negative. */
11528 if (signed_value >= 0)
11529 insn |= 1 << 23;
11530
11531 /* Encode the offset. */
11532 insn |= residual;
4962c51a
MS		 11533
11534 bfd_put_32 (input_bfd, insn, hit_data);
11535 }
11536 return bfd_reloc_ok;
11537
11538 case R_ARM_LDRS_PC_G0:
11539 case R_ARM_LDRS_PC_G1:
11540 case R_ARM_LDRS_PC_G2:
11541 case R_ARM_LDRS_SB_G0:
11542 case R_ARM_LDRS_SB_G1:
11543 case R_ARM_LDRS_SB_G2:
11544 {
11545 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11546 bfd_vma pc = input_section->output_section->vma
4962c51a 11547 + input_section->output_offset + rel->r_offset;
31a91d61 11548 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11549 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11550 bfd_vma residual;
4962c51a 11551 bfd_signed_vma signed_value;
99059e56
RM		 11552 int group = 0;
11553
11554 /* Determine which groups of bits to calculate. */
11555 switch (r_type)
11556 {
11557 case R_ARM_LDRS_PC_G0:
11558 case R_ARM_LDRS_SB_G0:
11559 group = 0;
11560 break;
11561
11562 case R_ARM_LDRS_PC_G1:
11563 case R_ARM_LDRS_SB_G1:
11564 group = 1;
11565 break;
11566
11567 case R_ARM_LDRS_PC_G2:
11568 case R_ARM_LDRS_SB_G2:
11569 group = 2;
11570 break;
11571
11572 default:
11573 abort ();
11574 }
11575
11576 /* If REL, extract the addend from the insn. If RELA, it will
11577 have already been fetched for us. */
4962c51a 11578 if (globals->use_rel)
99059e56
RM		 11579 {
11580 int negative = (insn & (1 << 23)) ? 1 : -1;
11581 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11582 }
4962c51a
MS		 11583
11584 /* Compute the value (X) to go in the place. */
99059e56
RM		 11585 if (r_type == R_ARM_LDRS_PC_G0
11586 || r_type == R_ARM_LDRS_PC_G1
11587 || r_type == R_ARM_LDRS_PC_G2)
11588 /* PC relative. */
11589 signed_value = value - pc + signed_addend;
11590 else
11591 /* Section base relative. */
11592 signed_value = value - sb + signed_addend;
11593
11594 /* Calculate the value of the relevant G_{n-1} to obtain
11595 the residual at that stage. */
b6518b38
NC		 11596 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11597 group - 1, &residual);
99059e56
RM		 11598
11599 /* Check for overflow. */
11600 if (residual >= 0x100)
11601 {
11602 (*_bfd_error_handler)
11603 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11604 input_bfd, input_section,
11605 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11606 return bfd_reloc_overflow;
11607 }
11608
11609 /* Mask out the value and U bit. */
11610 insn &= 0xff7ff0f0;
11611
11612 /* Set the U bit if the value to go in the place is non-negative. */
11613 if (signed_value >= 0)
11614 insn |= 1 << 23;
11615
11616 /* Encode the offset. */
11617 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 11618
11619 bfd_put_32 (input_bfd, insn, hit_data);
11620 }
11621 return bfd_reloc_ok;
11622
11623 case R_ARM_LDC_PC_G0:
11624 case R_ARM_LDC_PC_G1:
11625 case R_ARM_LDC_PC_G2:
11626 case R_ARM_LDC_SB_G0:
11627 case R_ARM_LDC_SB_G1:
11628 case R_ARM_LDC_SB_G2:
11629 {
11630 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11631 bfd_vma pc = input_section->output_section->vma
4962c51a 11632 + input_section->output_offset + rel->r_offset;
31a91d61 11633 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11634 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11635 bfd_vma residual;
4962c51a 11636 bfd_signed_vma signed_value;
99059e56
RM		 11637 int group = 0;
11638
11639 /* Determine which groups of bits to calculate. */
11640 switch (r_type)
11641 {
11642 case R_ARM_LDC_PC_G0:
11643 case R_ARM_LDC_SB_G0:
11644 group = 0;
11645 break;
11646
11647 case R_ARM_LDC_PC_G1:
11648 case R_ARM_LDC_SB_G1:
11649 group = 1;
11650 break;
11651
11652 case R_ARM_LDC_PC_G2:
11653 case R_ARM_LDC_SB_G2:
11654 group = 2;
11655 break;
11656
11657 default:
11658 abort ();
11659 }
11660
11661 /* If REL, extract the addend from the insn. If RELA, it will
11662 have already been fetched for us. */
4962c51a 11663 if (globals->use_rel)
99059e56
RM		 11664 {
11665 int negative = (insn & (1 << 23)) ? 1 : -1;
11666 signed_addend = negative * ((insn & 0xff) << 2);
11667 }
4962c51a
MS		 11668
11669 /* Compute the value (X) to go in the place. */
99059e56
RM		 11670 if (r_type == R_ARM_LDC_PC_G0
11671 || r_type == R_ARM_LDC_PC_G1
11672 || r_type == R_ARM_LDC_PC_G2)
11673 /* PC relative. */
11674 signed_value = value - pc + signed_addend;
11675 else
11676 /* Section base relative. */
11677 signed_value = value - sb + signed_addend;
11678
11679 /* Calculate the value of the relevant G_{n-1} to obtain
11680 the residual at that stage. */
b6518b38
NC		 11681 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11682 group - 1, &residual);
99059e56
RM		 11683
11684 /* Check for overflow. (The absolute value to go in the place must be
11685 divisible by four and, after having been divided by four, must
11686 fit in eight bits.) */
11687 if ((residual & 0x3) != 0 || residual >= 0x400)
11688 {
11689 (*_bfd_error_handler)
11690 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11691 input_bfd, input_section,
b6518b38 11692 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11693 return bfd_reloc_overflow;
11694 }
11695
11696 /* Mask out the value and U bit. */
11697 insn &= 0xff7fff00;
11698
11699 /* Set the U bit if the value to go in the place is non-negative. */
11700 if (signed_value >= 0)
11701 insn |= 1 << 23;
11702
11703 /* Encode the offset. */
11704 insn |= residual >> 2;
4962c51a
MS		 11705
11706 bfd_put_32 (input_bfd, insn, hit_data);
11707 }
11708 return bfd_reloc_ok;
11709
72d98d16
MG		 11710 case R_ARM_THM_ALU_ABS_G0_NC:
11711 case R_ARM_THM_ALU_ABS_G1_NC:
11712 case R_ARM_THM_ALU_ABS_G2_NC:
11713 case R_ARM_THM_ALU_ABS_G3_NC:
11714 {
11715 const int shift_array[4] = {0, 8, 16, 24};
11716 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
11717 bfd_vma addr = value;
11718 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
11719
11720 /* Compute address. */
11721 if (globals->use_rel)
11722 signed_addend = insn & 0xff;
11723 addr += signed_addend;
11724 if (branch_type == ST_BRANCH_TO_THUMB)
11725 addr |= 1;
11726 /* Clean imm8 insn. */
11727 insn &= 0xff00;
11728 /* And update with correct part of address. */
11729 insn |= (addr >> shift) & 0xff;
11730 /* Update insn. */
11731 bfd_put_16 (input_bfd, insn, hit_data);
11732 }
11733
11734 *unresolved_reloc_p = FALSE;
11735 return bfd_reloc_ok;
11736
252b5132
RH		 11737 default:
11738 return bfd_reloc_notsupported;
11739 }
11740}
11741
98c1d4aa
NC		 11742/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11743static void
57e8b36a
NC		 11744arm_add_to_rel (bfd * abfd,
11745 bfd_byte * address,
11746 reloc_howto_type * howto,
11747 bfd_signed_vma increment)
98c1d4aa 11748{
98c1d4aa
NC		 11749 bfd_signed_vma addend;
11750
bd97cb95
DJ		 11751 if (howto->type == R_ARM_THM_CALL
11752 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 11753 {
9a5aca8c
AM		 11754 int upper_insn, lower_insn;
11755 int upper, lower;
98c1d4aa 11756
9a5aca8c
AM		 11757 upper_insn = bfd_get_16 (abfd, address);
11758 lower_insn = bfd_get_16 (abfd, address + 2);
11759 upper = upper_insn & 0x7ff;
11760 lower = lower_insn & 0x7ff;
11761
11762 addend = (upper << 12) | (lower << 1);
ddda4409 11763 addend += increment;
9a5aca8c 11764 addend >>= 1;
98c1d4aa 11765
9a5aca8c
AM		 11766 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
11767 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
11768
dc810e39
AM		 11769 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
11770 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 11771 }
11772 else
11773 {
11774 bfd_vma contents;
11775
11776 contents = bfd_get_32 (abfd, address);
11777
11778 /* Get the (signed) value from the instruction. */
11779 addend = contents & howto->src_mask;
11780 if (addend & ((howto->src_mask + 1) >> 1))
11781 {
11782 bfd_signed_vma mask;
11783
11784 mask = -1;
11785 mask &= ~ howto->src_mask;
11786 addend |= mask;
11787 }
11788
11789 /* Add in the increment, (which is a byte value). */
11790 switch (howto->type)
11791 {
11792 default:
11793 addend += increment;
11794 break;
11795
11796 case R_ARM_PC24:
c6596c5e 11797 case R_ARM_PLT32:
5b5bb741
PB		 11798 case R_ARM_CALL:
11799 case R_ARM_JUMP24:
9a5aca8c 11800 addend <<= howto->size;
dc810e39 11801 addend += increment;
9a5aca8c
AM		 11802
11803 /* Should we check for overflow here ? */
11804
11805 /* Drop any undesired bits. */
11806 addend >>= howto->rightshift;
11807 break;
11808 }
11809
11810 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
11811
11812 bfd_put_32 (abfd, contents, address);
ddda4409 11813 }
98c1d4aa 11814}
252b5132 11815
ba93b8ac
DJ		 11816#define IS_ARM_TLS_RELOC(R_TYPE) \
11817 ((R_TYPE) == R_ARM_TLS_GD32 \
11818 || (R_TYPE) == R_ARM_TLS_LDO32 \
11819 || (R_TYPE) == R_ARM_TLS_LDM32 \
11820 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11821 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11822 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11823 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 11824 || (R_TYPE) == R_ARM_TLS_IE32 \
11825 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11826
11827/* Specific set of relocations for the gnu tls dialect. */
11828#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11829 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11830 || (R_TYPE) == R_ARM_TLS_CALL \
11831 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11832 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11833 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 11834
252b5132 11835/* Relocate an ARM ELF section. */
906e58ca 11836
b34976b6 11837static bfd_boolean
57e8b36a
NC		 11838elf32_arm_relocate_section (bfd * output_bfd,
11839 struct bfd_link_info * info,
11840 bfd * input_bfd,
11841 asection * input_section,
11842 bfd_byte * contents,
11843 Elf_Internal_Rela * relocs,
11844 Elf_Internal_Sym * local_syms,
11845 asection ** local_sections)
252b5132 11846{
b34976b6
AM		 11847 Elf_Internal_Shdr *symtab_hdr;
11848 struct elf_link_hash_entry **sym_hashes;
11849 Elf_Internal_Rela *rel;
11850 Elf_Internal_Rela *relend;
11851 const char *name;
b32d3aa2 11852 struct elf32_arm_link_hash_table * globals;
252b5132 11853
4e7fd91e 11854 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 11855 if (globals == NULL)
11856 return FALSE;
b491616a 11857
0ffa91dd 11858 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 11859 sym_hashes = elf_sym_hashes (input_bfd);
11860
11861 rel = relocs;
11862 relend = relocs + input_section->reloc_count;
11863 for (; rel < relend; rel++)
11864 {
ba96a88f
NC		 11865 int r_type;
11866 reloc_howto_type * howto;
11867 unsigned long r_symndx;
11868 Elf_Internal_Sym * sym;
11869 asection * sec;
252b5132 11870 struct elf_link_hash_entry * h;
ba96a88f
NC		 11871 bfd_vma relocation;
11872 bfd_reloc_status_type r;
11873 arelent bfd_reloc;
ba93b8ac 11874 char sym_type;
0945cdfd 11875 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 11876 char *error_message = NULL;
f21f3fe0 11877
252b5132 11878 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 11879 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 11880 r_type = arm_real_reloc_type (globals, r_type);
252b5132 11881
ba96a88f 11882 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 11883 || r_type == R_ARM_GNU_VTINHERIT)
11884 continue;
252b5132 11885
b32d3aa2 11886 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 11887 howto = bfd_reloc.howto;
252b5132 11888
252b5132
RH		 11889 h = NULL;
11890 sym = NULL;
11891 sec = NULL;
9b485d32 11892
252b5132
RH		 11893 if (r_symndx < symtab_hdr->sh_info)
11894 {
11895 sym = local_syms + r_symndx;
ba93b8ac 11896 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 11897 sec = local_sections[r_symndx];
ffcb4889
NS		 11898
11899 /* An object file might have a reference to a local
11900 undefined symbol. This is a daft object file, but we
11901 should at least do something about it. V4BX & NONE
11902 relocations do not use the symbol and are explicitly
77b4f08f
TS		 11903 allowed to use the undefined symbol, so allow those.
11904 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 11905 if (r_type != R_ARM_V4BX
11906 && r_type != R_ARM_NONE
77b4f08f 11907 && r_symndx != STN_UNDEF
ffcb4889
NS		 11908 && bfd_is_und_section (sec)
11909 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 11910 (*info->callbacks->undefined_symbol)
11911 (info, bfd_elf_string_from_elf_section
11912 (input_bfd, symtab_hdr->sh_link, sym->st_name),
11913 input_bfd, input_section,
11914 rel->r_offset, TRUE);
b38cadfb 11915
4e7fd91e 11916 if (globals->use_rel)
f8df10f4 11917 {
4e7fd91e
PB		 11918 relocation = (sec->output_section->vma
11919 + sec->output_offset
11920 + sym->st_value);
0e1862bb 11921 if (!bfd_link_relocatable (info)
ab96bf03
AM		 11922 && (sec->flags & SEC_MERGE)
11923 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 11924 {
4e7fd91e
PB		 11925 asection *msec;
11926 bfd_vma addend, value;
11927
39623e12 11928 switch (r_type)
4e7fd91e 11929 {
39623e12
PB		 11930 case R_ARM_MOVW_ABS_NC:
11931 case R_ARM_MOVT_ABS:
11932 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11933 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
11934 addend = (addend ^ 0x8000) - 0x8000;
11935 break;
f8df10f4 11936
39623e12
PB		 11937 case R_ARM_THM_MOVW_ABS_NC:
11938 case R_ARM_THM_MOVT_ABS:
11939 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
11940 << 16;
11941 value |= bfd_get_16 (input_bfd,
11942 contents + rel->r_offset + 2);
11943 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
11944 | ((value & 0x04000000) >> 15);
11945 addend = (addend ^ 0x8000) - 0x8000;
11946 break;
f8df10f4 11947
39623e12
PB		 11948 default:
11949 if (howto->rightshift
11950 || (howto->src_mask & (howto->src_mask + 1)))
11951 {
11952 (*_bfd_error_handler)
11953 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
11954 input_bfd, input_section,
11955 (long) rel->r_offset, howto->name);
11956 return FALSE;
11957 }
11958
11959 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11960
11961 /* Get the (signed) value from the instruction. */
11962 addend = value & howto->src_mask;
11963 if (addend & ((howto->src_mask + 1) >> 1))
11964 {
11965 bfd_signed_vma mask;
11966
11967 mask = -1;
11968 mask &= ~ howto->src_mask;
11969 addend |= mask;
11970 }
11971 break;
4e7fd91e 11972 }
39623e12 11973
4e7fd91e
PB		 11974 msec = sec;
11975 addend =
11976 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
11977 - relocation;
11978 addend += msec->output_section->vma + msec->output_offset;
39623e12 11979
cc643b88 11980 /* Cases here must match those in the preceding
39623e12
PB		 11981 switch statement. */
11982 switch (r_type)
11983 {
11984 case R_ARM_MOVW_ABS_NC:
11985 case R_ARM_MOVT_ABS:
11986 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
11987 | (addend & 0xfff);
11988 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11989 break;
11990
11991 case R_ARM_THM_MOVW_ABS_NC:
11992 case R_ARM_THM_MOVT_ABS:
11993 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
11994 | (addend & 0xff) | ((addend & 0x0800) << 15);
11995 bfd_put_16 (input_bfd, value >> 16,
11996 contents + rel->r_offset);
11997 bfd_put_16 (input_bfd, value,
11998 contents + rel->r_offset + 2);
11999 break;
12000
12001 default:
12002 value = (value & ~ howto->dst_mask)
12003 | (addend & howto->dst_mask);
12004 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12005 break;
12006 }
f8df10f4 12007 }
f8df10f4 12008 }
4e7fd91e
PB		 12009 else
12010 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12011 }
12012 else
12013 {
62d887d4 12014 bfd_boolean warned, ignored;
560e09e9 12015
b2a8e766
AM		 12016 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12017 r_symndx, symtab_hdr, sym_hashes,
12018 h, sec, relocation,
62d887d4 12019 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12020
12021 sym_type = h->type;
252b5132
RH		 12022 }
12023
dbaa2011 12024 if (sec != NULL && discarded_section (sec))
e4067dbb 12025 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12026 rel, 1, relend, howto, 0, contents);
ab96bf03 12027
0e1862bb 12028 if (bfd_link_relocatable (info))
ab96bf03
AM		 12029 {
12030 /* This is a relocatable link. We don't have to change
12031 anything, unless the reloc is against a section symbol,
12032 in which case we have to adjust according to where the
12033 section symbol winds up in the output section. */
12034 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12035 {
12036 if (globals->use_rel)
12037 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12038 howto, (bfd_signed_vma) sec->output_offset);
12039 else
12040 rel->r_addend += sec->output_offset;
12041 }
12042 continue;
12043 }
12044
252b5132
RH		 12045 if (h != NULL)
12046 name = h->root.root.string;
12047 else
12048 {
12049 name = (bfd_elf_string_from_elf_section
12050 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12051 if (name == NULL || *name == '\0')
12052 name = bfd_section_name (input_bfd, sec);
12053 }
f21f3fe0 12054
cf35638d 12055 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12056 && r_type != R_ARM_NONE
12057 && (h == NULL
12058 || h->root.type == bfd_link_hash_defined
12059 || h->root.type == bfd_link_hash_defweak)
12060 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12061 {
12062 (*_bfd_error_handler)
12063 ((sym_type == STT_TLS
12064 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
12065 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
12066 input_bfd,
12067 input_section,
12068 (long) rel->r_offset,
12069 howto->name,
12070 name);
12071 }
12072
0855e32b 12073 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12074 done, i.e., the relaxation produced the final output we want,
12075 and we won't let anybody mess with it. Also, we have to do
12076 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12077 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12078 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12079 || (IS_ARM_TLS_GNU_RELOC (r_type)
12080 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12081 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12082 & GOT_TLS_GDESC)))
12083 {
12084 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12085 contents, rel, h == NULL);
12086 /* This may have been marked unresolved because it came from
12087 a shared library. But we've just dealt with that. */
12088 unresolved_reloc = 0;
12089 }
12090 else
12091 r = bfd_reloc_continue;
b38cadfb 12092
39d911fc
TP		 12093 if (r == bfd_reloc_continue)
12094 {
12095 unsigned char branch_type =
12096 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12097 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12098
12099 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12100 input_section, contents, rel,
12101 relocation, info, sec, name,
12102 sym_type, branch_type, h,
12103 &unresolved_reloc,
12104 &error_message);
12105 }
0945cdfd
DJ		 12106
12107 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12108 because such sections are not SEC_ALLOC and thus ld.so will
12109 not process them. */
12110 if (unresolved_reloc
99059e56
RM		 12111 && !((input_section->flags & SEC_DEBUGGING) != 0
12112 && h->def_dynamic)
1d5316ab
AM		 12113 && _bfd_elf_section_offset (output_bfd, info, input_section,
12114 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 12115 {
12116 (*_bfd_error_handler)
843fe662
L		 12117 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
12118 input_bfd,
12119 input_section,
12120 (long) rel->r_offset,
12121 howto->name,
12122 h->root.root.string);
0945cdfd
DJ		 12123 return FALSE;
12124 }
252b5132
RH		 12125
12126 if (r != bfd_reloc_ok)
12127 {
252b5132
RH		 12128 switch (r)
12129 {
12130 case bfd_reloc_overflow:
cf919dfd
PB		 12131 /* If the overflowing reloc was to an undefined symbol,
12132 we have already printed one error message and there
12133 is no point complaining again. */
1a72702b
AM		 12134 if (!h || h->root.type != bfd_link_hash_undefined)
12135 (*info->callbacks->reloc_overflow)
12136 (info, (h ? &h->root : NULL), name, howto->name,
12137 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12138 break;
12139
12140 case bfd_reloc_undefined:
1a72702b
AM		 12141 (*info->callbacks->undefined_symbol)
12142 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12143 break;
12144
12145 case bfd_reloc_outofrange:
f2a9dd69 12146 error_message = _("out of range");
252b5132
RH		 12147 goto common_error;
12148
12149 case bfd_reloc_notsupported:
f2a9dd69 12150 error_message = _("unsupported relocation");
252b5132
RH		 12151 goto common_error;
12152
12153 case bfd_reloc_dangerous:
f2a9dd69 12154 /* error_message should already be set. */
252b5132
RH		 12155 goto common_error;
12156
12157 default:
f2a9dd69 12158 error_message = _("unknown error");
8029a119 12159 /* Fall through. */
252b5132
RH		 12160
12161 common_error:
f2a9dd69 12162 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12163 (*info->callbacks->reloc_dangerous)
12164 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12165 break;
12166 }
12167 }
12168 }
12169
b34976b6 12170 return TRUE;
252b5132
RH		 12171}
12172
91d6fa6a 12173/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12174 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12175 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12176 maintaining that condition). */
12177
12178static void
12179add_unwind_table_edit (arm_unwind_table_edit **head,
12180 arm_unwind_table_edit **tail,
12181 arm_unwind_edit_type type,
12182 asection *linked_section,
91d6fa6a 12183 unsigned int tindex)
2468f9c9 12184{
21d799b5
NC		 12185 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12186 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12187
2468f9c9
PB		 12188 new_edit->type = type;
12189 new_edit->linked_section = linked_section;
91d6fa6a 12190 new_edit->index = tindex;
b38cadfb 12191
91d6fa6a 12192 if (tindex > 0)
2468f9c9
PB		 12193 {
12194 new_edit->next = NULL;
12195
12196 if (*tail)
12197 (*tail)->next = new_edit;
12198
12199 (*tail) = new_edit;
12200
12201 if (!*head)
12202 (*head) = new_edit;
12203 }
12204 else
12205 {
12206 new_edit->next = *head;
12207
12208 if (!*tail)
12209 *tail = new_edit;
12210
12211 *head = new_edit;
12212 }
12213}
12214
12215static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12216
12217/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12218static void
12219adjust_exidx_size(asection *exidx_sec, int adjust)
12220{
12221 asection *out_sec;
12222
12223 if (!exidx_sec->rawsize)
12224 exidx_sec->rawsize = exidx_sec->size;
12225
12226 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12227 out_sec = exidx_sec->output_section;
12228 /* Adjust size of output section. */
12229 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12230}
12231
12232/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12233static void
12234insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12235{
12236 struct _arm_elf_section_data *exidx_arm_data;
12237
12238 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12239 add_unwind_table_edit (
12240 &exidx_arm_data->u.exidx.unwind_edit_list,
12241 &exidx_arm_data->u.exidx.unwind_edit_tail,
12242 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12243
491d01d3
YU		 12244 exidx_arm_data->additional_reloc_count++;
12245
2468f9c9
PB		 12246 adjust_exidx_size(exidx_sec, 8);
12247}
12248
12249/* Scan .ARM.exidx tables, and create a list describing edits which should be
12250 made to those tables, such that:
b38cadfb 12251
2468f9c9
PB		 12252 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12253 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12254 codes which have been inlined into the index).
2468f9c9 12255
85fdf906
AH		 12256 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12257
2468f9c9 12258 The edits are applied when the tables are written
b38cadfb 12259 (in elf32_arm_write_section). */
2468f9c9
PB		 12260
12261bfd_boolean
12262elf32_arm_fix_exidx_coverage (asection **text_section_order,
12263 unsigned int num_text_sections,
85fdf906
AH		 12264 struct bfd_link_info *info,
12265 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12266{
12267 bfd *inp;
12268 unsigned int last_second_word = 0, i;
12269 asection *last_exidx_sec = NULL;
12270 asection *last_text_sec = NULL;
12271 int last_unwind_type = -1;
12272
12273 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12274 text sections. */
c72f2fb2 12275 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12276 {
12277 asection *sec;
b38cadfb 12278
2468f9c9 12279 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12280 {
2468f9c9
PB		 12281 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12282 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12283
dec9d5df 12284 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12285 continue;
b38cadfb 12286
2468f9c9
PB		 12287 if (elf_sec->linked_to)
12288 {
12289 Elf_Internal_Shdr *linked_hdr
99059e56 12290 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12291 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12292 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12293
12294 if (linked_sec_arm_data == NULL)
99059e56 12295 continue;
2468f9c9
PB		 12296
12297 /* Link this .ARM.exidx section back from the text section it
99059e56 12298 describes. */
2468f9c9
PB		 12299 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12300 }
12301 }
12302 }
12303
12304 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12305 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12306 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12307
12308 for (i = 0; i < num_text_sections; i++)
12309 {
12310 asection *sec = text_section_order[i];
12311 asection *exidx_sec;
12312 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12313 struct _arm_elf_section_data *exidx_arm_data;
12314 bfd_byte *contents = NULL;
12315 int deleted_exidx_bytes = 0;
12316 bfd_vma j;
12317 arm_unwind_table_edit *unwind_edit_head = NULL;
12318 arm_unwind_table_edit *unwind_edit_tail = NULL;
12319 Elf_Internal_Shdr *hdr;
12320 bfd *ibfd;
12321
12322 if (arm_data == NULL)
99059e56 12323 continue;
2468f9c9
PB		 12324
12325 exidx_sec = arm_data->u.text.arm_exidx_sec;
12326 if (exidx_sec == NULL)
12327 {
12328 /* Section has no unwind data. */
12329 if (last_unwind_type == 0 || !last_exidx_sec)
12330 continue;
12331
12332 /* Ignore zero sized sections. */
12333 if (sec->size == 0)
12334 continue;
12335
12336 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12337 last_unwind_type = 0;
12338 continue;
12339 }
12340
22a8f80e
PB		 12341 /* Skip /DISCARD/ sections. */
12342 if (bfd_is_abs_section (exidx_sec->output_section))
12343 continue;
12344
2468f9c9
PB		 12345 hdr = &elf_section_data (exidx_sec)->this_hdr;
12346 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12347 continue;
b38cadfb 12348
2468f9c9
PB		 12349 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12350 if (exidx_arm_data == NULL)
99059e56 12351 continue;
b38cadfb 12352
2468f9c9 12353 ibfd = exidx_sec->owner;
b38cadfb 12354
2468f9c9
PB		 12355 if (hdr->contents != NULL)
12356 contents = hdr->contents;
12357 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12358 /* An error? */
12359 continue;
12360
ac06903d
YU		 12361 if (last_unwind_type > 0)
12362 {
12363 unsigned int first_word = bfd_get_32 (ibfd, contents);
12364 /* Add cantunwind if first unwind item does not match section
12365 start. */
12366 if (first_word != sec->vma)
12367 {
12368 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12369 last_unwind_type = 0;
12370 }
12371 }
12372
2468f9c9
PB		 12373 for (j = 0; j < hdr->sh_size; j += 8)
12374 {
12375 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12376 int unwind_type;
12377 int elide = 0;
12378
12379 /* An EXIDX_CANTUNWIND entry. */
12380 if (second_word == 1)
12381 {
12382 if (last_unwind_type == 0)
12383 elide = 1;
12384 unwind_type = 0;
12385 }
12386 /* Inlined unwinding data. Merge if equal to previous. */
12387 else if ((second_word & 0x80000000) != 0)
12388 {
85fdf906
AH		 12389 if (merge_exidx_entries
12390 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12391 elide = 1;
12392 unwind_type = 1;
12393 last_second_word = second_word;
12394 }
12395 /* Normal table entry. In theory we could merge these too,
12396 but duplicate entries are likely to be much less common. */
12397 else
12398 unwind_type = 2;
12399
491d01d3 12400 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12401 {
12402 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12403 DELETE_EXIDX_ENTRY, NULL, j / 8);
12404
12405 deleted_exidx_bytes += 8;
12406 }
12407
12408 last_unwind_type = unwind_type;
12409 }
12410
12411 /* Free contents if we allocated it ourselves. */
12412 if (contents != hdr->contents)
99059e56 12413 free (contents);
2468f9c9
PB		 12414
12415 /* Record edits to be applied later (in elf32_arm_write_section). */
12416 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12417 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12418
2468f9c9
PB		 12419 if (deleted_exidx_bytes > 0)
12420 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12421
12422 last_exidx_sec = exidx_sec;
12423 last_text_sec = sec;
12424 }
12425
12426 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12427 if (!bfd_link_relocatable (info) && last_exidx_sec
12428 && last_unwind_type != 0)
2468f9c9
PB		 12429 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12430
12431 return TRUE;
12432}
12433
3e6b1042
DJ		 12434static bfd_boolean
12435elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12436 bfd *ibfd, const char *name)
12437{
12438 asection *sec, *osec;
12439
3d4d4302 12440 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12441 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12442 return TRUE;
12443
12444 osec = sec->output_section;
12445 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12446 return TRUE;
12447
12448 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12449 sec->output_offset, sec->size))
12450 return FALSE;
12451
12452 return TRUE;
12453}
12454
12455static bfd_boolean
12456elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12457{
12458 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12459 asection *sec, *osec;
3e6b1042 12460
4dfe6ac6
NC		 12461 if (globals == NULL)
12462 return FALSE;
12463
3e6b1042
DJ		 12464 /* Invoke the regular ELF backend linker to do all the work. */
12465 if (!bfd_elf_final_link (abfd, info))
12466 return FALSE;
12467
fe33d2fa
CL		 12468 /* Process stub sections (eg BE8 encoding, ...). */
12469 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12470 unsigned int i;
cdb21a0a
NS		 12471 for (i=0; i<htab->top_id; i++)
12472 {
12473 sec = htab->stub_group[i].stub_sec;
12474 /* Only process it once, in its link_sec slot. */
12475 if (sec && i == htab->stub_group[i].link_sec->id)
12476 {
12477 osec = sec->output_section;
12478 elf32_arm_write_section (abfd, info, sec, sec->contents);
12479 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12480 sec->output_offset, sec->size))
12481 return FALSE;
12482 }
fe33d2fa 12483 }
fe33d2fa 12484
3e6b1042
DJ		 12485 /* Write out any glue sections now that we have created all the
12486 stubs. */
12487 if (globals->bfd_of_glue_owner != NULL)
12488 {
12489 if (! elf32_arm_output_glue_section (info, abfd,
12490 globals->bfd_of_glue_owner,
12491 ARM2THUMB_GLUE_SECTION_NAME))
12492 return FALSE;
12493
12494 if (! elf32_arm_output_glue_section (info, abfd,
12495 globals->bfd_of_glue_owner,
12496 THUMB2ARM_GLUE_SECTION_NAME))
12497 return FALSE;
12498
12499 if (! elf32_arm_output_glue_section (info, abfd,
12500 globals->bfd_of_glue_owner,
12501 VFP11_ERRATUM_VENEER_SECTION_NAME))
12502 return FALSE;
12503
a504d23a
LA		 12504 if (! elf32_arm_output_glue_section (info, abfd,
12505 globals->bfd_of_glue_owner,
12506 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12507 return FALSE;
12508
3e6b1042
DJ		 12509 if (! elf32_arm_output_glue_section (info, abfd,
12510 globals->bfd_of_glue_owner,
12511 ARM_BX_GLUE_SECTION_NAME))
12512 return FALSE;
12513 }
12514
12515 return TRUE;
12516}
12517
5968a7b8
NC		 12518/* Return a best guess for the machine number based on the attributes. */
12519
12520static unsigned int
12521bfd_arm_get_mach_from_attributes (bfd * abfd)
12522{
12523 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12524
12525 switch (arch)
12526 {
12527 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12528 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12529 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12530
12531 case TAG_CPU_ARCH_V5TE:
12532 {
12533 char * name;
12534
12535 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12536 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12537
12538 if (name)
12539 {
12540 if (strcmp (name, "IWMMXT2") == 0)
12541 return bfd_mach_arm_iWMMXt2;
12542
12543 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12544 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12545
12546 if (strcmp (name, "XSCALE") == 0)
12547 {
12548 int wmmx;
12549
12550 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12551 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12552 switch (wmmx)
12553 {
12554 case 1: return bfd_mach_arm_iWMMXt;
12555 case 2: return bfd_mach_arm_iWMMXt2;
12556 default: return bfd_mach_arm_XScale;
12557 }
12558 }
5968a7b8
NC		 12559 }
12560
12561 return bfd_mach_arm_5TE;
12562 }
12563
12564 default:
12565 return bfd_mach_arm_unknown;
12566 }
12567}
12568
c178919b
NC		 12569/* Set the right machine number. */
12570
12571static bfd_boolean
57e8b36a 12572elf32_arm_object_p (bfd *abfd)
c178919b 12573{
5a6c6817 12574 unsigned int mach;
57e8b36a 12575
5a6c6817 12576 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12577
5968a7b8
NC		 12578 if (mach == bfd_mach_arm_unknown)
12579 {
12580 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12581 mach = bfd_mach_arm_ep9312;
12582 else
12583 mach = bfd_arm_get_mach_from_attributes (abfd);
12584 }
c178919b 12585
5968a7b8 12586 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 12587 return TRUE;
12588}
12589
fc830a83 12590/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 12591
b34976b6 12592static bfd_boolean
57e8b36a 12593elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 12594{
12595 if (elf_flags_init (abfd)
12596 && elf_elfheader (abfd)->e_flags != flags)
12597 {
fc830a83
NC		 12598 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
12599 {
fd2ec330 12600 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 12601 (*_bfd_error_handler)
12602 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
12603 abfd);
fc830a83 12604 else
d003868e
AM		 12605 _bfd_error_handler
12606 (_("Warning: Clearing the interworking flag of %B due to outside request"),
12607 abfd);
fc830a83 12608 }
252b5132
RH		 12609 }
12610 else
12611 {
12612 elf_elfheader (abfd)->e_flags = flags;
b34976b6 12613 elf_flags_init (abfd) = TRUE;
252b5132
RH		 12614 }
12615
b34976b6 12616 return TRUE;
252b5132
RH		 12617}
12618
fc830a83 12619/* Copy backend specific data from one object module to another. */
9b485d32 12620
b34976b6 12621static bfd_boolean
57e8b36a 12622elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 12623{
12624 flagword in_flags;
12625 flagword out_flags;
12626
0ffa91dd 12627 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 12628 return TRUE;
252b5132 12629
fc830a83 12630 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 12631 out_flags = elf_elfheader (obfd)->e_flags;
12632
fc830a83
NC		 12633 if (elf_flags_init (obfd)
12634 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
12635 && in_flags != out_flags)
252b5132 12636 {
252b5132 12637 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 12638 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 12639 return FALSE;
252b5132
RH		 12640
12641 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 12642 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 12643 return FALSE;
252b5132
RH		 12644
12645 /* If the src and dest have different interworking flags
99059e56 12646 then turn off the interworking bit. */
fd2ec330 12647 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 12648 {
fd2ec330 12649 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 12650 _bfd_error_handler
12651 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
12652 obfd, ibfd);
252b5132 12653
fd2ec330 12654 in_flags &= ~EF_ARM_INTERWORK;
252b5132 12655 }
1006ba19
PB		 12656
12657 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 12658 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
12659 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 12660 }
12661
12662 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 12663 elf_flags_init (obfd) = TRUE;
252b5132 12664
e2349352 12665 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 12666}
12667
12668/* Values for Tag_ABI_PCS_R9_use. */
12669enum
12670{
12671 AEABI_R9_V6,
12672 AEABI_R9_SB,
12673 AEABI_R9_TLS,
12674 AEABI_R9_unused
12675};
12676
12677/* Values for Tag_ABI_PCS_RW_data. */
12678enum
12679{
12680 AEABI_PCS_RW_data_absolute,
12681 AEABI_PCS_RW_data_PCrel,
12682 AEABI_PCS_RW_data_SBrel,
12683 AEABI_PCS_RW_data_unused
12684};
12685
12686/* Values for Tag_ABI_enum_size. */
12687enum
12688{
12689 AEABI_enum_unused,
12690 AEABI_enum_short,
12691 AEABI_enum_wide,
12692 AEABI_enum_forced_wide
12693};
12694
104d59d1
JM		 12695/* Determine whether an object attribute tag takes an integer, a
12696 string or both. */
906e58ca 12697
104d59d1
JM		 12698static int
12699elf32_arm_obj_attrs_arg_type (int tag)
12700{
12701 if (tag == Tag_compatibility)
3483fe2e 12702 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 12703 else if (tag == Tag_nodefaults)
3483fe2e
AS		 12704 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
12705 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
12706 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 12707 else if (tag < 32)
3483fe2e 12708 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 12709 else
3483fe2e 12710 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 12711}
12712
5aa6ff7c
AS		 12713/* The ABI defines that Tag_conformance should be emitted first, and that
12714 Tag_nodefaults should be second (if either is defined). This sets those
12715 two positions, and bumps up the position of all the remaining tags to
12716 compensate. */
12717static int
12718elf32_arm_obj_attrs_order (int num)
12719{
3de4a297 12720 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 12721 return Tag_conformance;
3de4a297 12722 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 12723 return Tag_nodefaults;
12724 if ((num - 2) < Tag_nodefaults)
12725 return num - 2;
12726 if ((num - 1) < Tag_conformance)
12727 return num - 1;
12728 return num;
12729}
12730
e8b36cd1
JM		 12731/* Attribute numbers >=64 (mod 128) can be safely ignored. */
12732static bfd_boolean
12733elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
12734{
12735 if ((tag & 127) < 64)
12736 {
12737 _bfd_error_handler
12738 (_("%B: Unknown mandatory EABI object attribute %d"),
12739 abfd, tag);
12740 bfd_set_error (bfd_error_bad_value);
12741 return FALSE;
12742 }
12743 else
12744 {
12745 _bfd_error_handler
12746 (_("Warning: %B: Unknown EABI object attribute %d"),
12747 abfd, tag);
12748 return TRUE;
12749 }
12750}
12751
91e22acd
AS		 12752/* Read the architecture from the Tag_also_compatible_with attribute, if any.
12753 Returns -1 if no architecture could be read. */
12754
12755static int
12756get_secondary_compatible_arch (bfd *abfd)
12757{
12758 obj_attribute *attr =
12759 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
12760
12761 /* Note: the tag and its argument below are uleb128 values, though
12762 currently-defined values fit in one byte for each. */
12763 if (attr->s
12764 && attr->s[0] == Tag_CPU_arch
12765 && (attr->s[1] & 128) != 128
12766 && attr->s[2] == 0)
12767 return attr->s[1];
12768
12769 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12770 return -1;
12771}
12772
12773/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12774 The tag is removed if ARCH is -1. */
12775
8e79c3df 12776static void
91e22acd 12777set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 12778{
91e22acd
AS		 12779 obj_attribute *attr =
12780 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 12781
91e22acd
AS		 12782 if (arch == -1)
12783 {
12784 attr->s = NULL;
12785 return;
8e79c3df 12786 }
91e22acd
AS		 12787
12788 /* Note: the tag and its argument below are uleb128 values, though
12789 currently-defined values fit in one byte for each. */
12790 if (!attr->s)
21d799b5 12791 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 12792 attr->s[0] = Tag_CPU_arch;
12793 attr->s[1] = arch;
12794 attr->s[2] = '\0';
8e79c3df
CM		 12795}
12796
91e22acd
AS		 12797/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12798 into account. */
12799
12800static int
12801tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
12802 int newtag, int secondary_compat)
8e79c3df 12803{
91e22acd
AS		 12804#define T(X) TAG_CPU_ARCH_##X
12805 int tagl, tagh, result;
12806 const int v6t2[] =
12807 {
12808 T(V6T2), /* PRE_V4. */
12809 T(V6T2), /* V4. */
12810 T(V6T2), /* V4T. */
12811 T(V6T2), /* V5T. */
12812 T(V6T2), /* V5TE. */
12813 T(V6T2), /* V5TEJ. */
12814 T(V6T2), /* V6. */
12815 T(V7), /* V6KZ. */
12816 T(V6T2) /* V6T2. */
12817 };
12818 const int v6k[] =
12819 {
12820 T(V6K), /* PRE_V4. */
12821 T(V6K), /* V4. */
12822 T(V6K), /* V4T. */
12823 T(V6K), /* V5T. */
12824 T(V6K), /* V5TE. */
12825 T(V6K), /* V5TEJ. */
12826 T(V6K), /* V6. */
12827 T(V6KZ), /* V6KZ. */
12828 T(V7), /* V6T2. */
12829 T(V6K) /* V6K. */
12830 };
12831 const int v7[] =
12832 {
12833 T(V7), /* PRE_V4. */
12834 T(V7), /* V4. */
12835 T(V7), /* V4T. */
12836 T(V7), /* V5T. */
12837 T(V7), /* V5TE. */
12838 T(V7), /* V5TEJ. */
12839 T(V7), /* V6. */
12840 T(V7), /* V6KZ. */
12841 T(V7), /* V6T2. */
12842 T(V7), /* V6K. */
12843 T(V7) /* V7. */
12844 };
12845 const int v6_m[] =
12846 {
12847 -1, /* PRE_V4. */
12848 -1, /* V4. */
12849 T(V6K), /* V4T. */
12850 T(V6K), /* V5T. */
12851 T(V6K), /* V5TE. */
12852 T(V6K), /* V5TEJ. */
12853 T(V6K), /* V6. */
12854 T(V6KZ), /* V6KZ. */
12855 T(V7), /* V6T2. */
12856 T(V6K), /* V6K. */
12857 T(V7), /* V7. */
12858 T(V6_M) /* V6_M. */
12859 };
12860 const int v6s_m[] =
12861 {
12862 -1, /* PRE_V4. */
12863 -1, /* V4. */
12864 T(V6K), /* V4T. */
12865 T(V6K), /* V5T. */
12866 T(V6K), /* V5TE. */
12867 T(V6K), /* V5TEJ. */
12868 T(V6K), /* V6. */
12869 T(V6KZ), /* V6KZ. */
12870 T(V7), /* V6T2. */
12871 T(V6K), /* V6K. */
12872 T(V7), /* V7. */
12873 T(V6S_M), /* V6_M. */
12874 T(V6S_M) /* V6S_M. */
12875 };
9e3c6df6
PB		 12876 const int v7e_m[] =
12877 {
12878 -1, /* PRE_V4. */
12879 -1, /* V4. */
12880 T(V7E_M), /* V4T. */
12881 T(V7E_M), /* V5T. */
12882 T(V7E_M), /* V5TE. */
12883 T(V7E_M), /* V5TEJ. */
12884 T(V7E_M), /* V6. */
12885 T(V7E_M), /* V6KZ. */
12886 T(V7E_M), /* V6T2. */
12887 T(V7E_M), /* V6K. */
12888 T(V7E_M), /* V7. */
12889 T(V7E_M), /* V6_M. */
12890 T(V7E_M), /* V6S_M. */
12891 T(V7E_M) /* V7E_M. */
12892 };
bca38921
MGD		 12893 const int v8[] =
12894 {
12895 T(V8), /* PRE_V4. */
12896 T(V8), /* V4. */
12897 T(V8), /* V4T. */
12898 T(V8), /* V5T. */
12899 T(V8), /* V5TE. */
12900 T(V8), /* V5TEJ. */
12901 T(V8), /* V6. */
12902 T(V8), /* V6KZ. */
12903 T(V8), /* V6T2. */
12904 T(V8), /* V6K. */
12905 T(V8), /* V7. */
12906 T(V8), /* V6_M. */
12907 T(V8), /* V6S_M. */
12908 T(V8), /* V7E_M. */
12909 T(V8) /* V8. */
12910 };
2fd158eb
TP		 12911 const int v8m_baseline[] =
12912 {
12913 -1, /* PRE_V4. */
12914 -1, /* V4. */
12915 -1, /* V4T. */
12916 -1, /* V5T. */
12917 -1, /* V5TE. */
12918 -1, /* V5TEJ. */
12919 -1, /* V6. */
12920 -1, /* V6KZ. */
12921 -1, /* V6T2. */
12922 -1, /* V6K. */
12923 -1, /* V7. */
12924 T(V8M_BASE), /* V6_M. */
12925 T(V8M_BASE), /* V6S_M. */
12926 -1, /* V7E_M. */
12927 -1, /* V8. */
12928 -1,
12929 T(V8M_BASE) /* V8-M BASELINE. */
12930 };
12931 const int v8m_mainline[] =
12932 {
12933 -1, /* PRE_V4. */
12934 -1, /* V4. */
12935 -1, /* V4T. */
12936 -1, /* V5T. */
12937 -1, /* V5TE. */
12938 -1, /* V5TEJ. */
12939 -1, /* V6. */
12940 -1, /* V6KZ. */
12941 -1, /* V6T2. */
12942 -1, /* V6K. */
12943 T(V8M_MAIN), /* V7. */
12944 T(V8M_MAIN), /* V6_M. */
12945 T(V8M_MAIN), /* V6S_M. */
12946 T(V8M_MAIN), /* V7E_M. */
12947 -1, /* V8. */
12948 -1,
12949 T(V8M_MAIN), /* V8-M BASELINE. */
12950 T(V8M_MAIN) /* V8-M MAINLINE. */
12951 };
91e22acd
AS		 12952 const int v4t_plus_v6_m[] =
12953 {
12954 -1, /* PRE_V4. */
12955 -1, /* V4. */
12956 T(V4T), /* V4T. */
12957 T(V5T), /* V5T. */
12958 T(V5TE), /* V5TE. */
12959 T(V5TEJ), /* V5TEJ. */
12960 T(V6), /* V6. */
12961 T(V6KZ), /* V6KZ. */
12962 T(V6T2), /* V6T2. */
12963 T(V6K), /* V6K. */
12964 T(V7), /* V7. */
12965 T(V6_M), /* V6_M. */
12966 T(V6S_M), /* V6S_M. */
9e3c6df6 12967 T(V7E_M), /* V7E_M. */
bca38921 12968 T(V8), /* V8. */
4ed7ed8d 12969 -1, /* Unused. */
2fd158eb
TP		 12970 T(V8M_BASE), /* V8-M BASELINE. */
12971 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 12972 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
12973 };
12974 const int *comb[] =
12975 {
12976 v6t2,
12977 v6k,
12978 v7,
12979 v6_m,
12980 v6s_m,
9e3c6df6 12981 v7e_m,
bca38921 12982 v8,
4ed7ed8d 12983 NULL,
2fd158eb
TP		 12984 v8m_baseline,
12985 v8m_mainline,
91e22acd
AS		 12986 /* Pseudo-architecture. */
12987 v4t_plus_v6_m
12988 };
12989
12990 /* Check we've not got a higher architecture than we know about. */
12991
9e3c6df6 12992 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 12993 {
3895f852 12994 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 12995 return -1;
12996 }
12997
12998 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12999
13000 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13001 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13002 oldtag = T(V4T_PLUS_V6_M);
13003
13004 /* And override the new tag if we have a Tag_also_compatible_with on the
13005 input. */
13006
13007 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13008 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13009 newtag = T(V4T_PLUS_V6_M);
13010
13011 tagl = (oldtag < newtag) ? oldtag : newtag;
13012 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13013
13014 /* Architectures before V6KZ add features monotonically. */
13015 if (tagh <= TAG_CPU_ARCH_V6KZ)
13016 return result;
13017
4ed7ed8d 13018 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13019
13020 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13021 as the canonical version. */
13022 if (result == T(V4T_PLUS_V6_M))
13023 {
13024 result = T(V4T);
13025 *secondary_compat_out = T(V6_M);
13026 }
13027 else
13028 *secondary_compat_out = -1;
13029
13030 if (result == -1)
13031 {
3895f852 13032 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13033 ibfd, oldtag, newtag);
13034 return -1;
13035 }
13036
13037 return result;
13038#undef T
8e79c3df
CM		 13039}
13040
ac56ee8f
MGD		 13041/* Query attributes object to see if integer divide instructions may be
13042 present in an object. */
13043static bfd_boolean
13044elf32_arm_attributes_accept_div (const obj_attribute *attr)
13045{
13046 int arch = attr[Tag_CPU_arch].i;
13047 int profile = attr[Tag_CPU_arch_profile].i;
13048
13049 switch (attr[Tag_DIV_use].i)
13050 {
13051 case 0:
13052 /* Integer divide allowed if instruction contained in archetecture. */
13053 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13054 return TRUE;
13055 else if (arch >= TAG_CPU_ARCH_V7E_M)
13056 return TRUE;
13057 else
13058 return FALSE;
13059
13060 case 1:
13061 /* Integer divide explicitly prohibited. */
13062 return FALSE;
13063
13064 default:
13065 /* Unrecognised case - treat as allowing divide everywhere. */
13066 case 2:
13067 /* Integer divide allowed in ARM state. */
13068 return TRUE;
13069 }
13070}
13071
13072/* Query attributes object to see if integer divide instructions are
13073 forbidden to be in the object. This is not the inverse of
13074 elf32_arm_attributes_accept_div. */
13075static bfd_boolean
13076elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13077{
13078 return attr[Tag_DIV_use].i == 1;
13079}
13080
ee065d83
PB		 13081/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13082 are conflicting attributes. */
906e58ca 13083
ee065d83
PB		 13084static bfd_boolean
13085elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
13086{
104d59d1
JM		 13087 obj_attribute *in_attr;
13088 obj_attribute *out_attr;
ee065d83
PB		 13089 /* Some tags have 0 = don't care, 1 = strong requirement,
13090 2 = weak requirement. */
91e22acd 13091 static const int order_021[3] = {0, 2, 1};
ee065d83 13092 int i;
91e22acd 13093 bfd_boolean result = TRUE;
9274e9de 13094 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13095
3e6b1042
DJ		 13096 /* Skip the linker stubs file. This preserves previous behavior
13097 of accepting unknown attributes in the first input file - but
13098 is that a bug? */
13099 if (ibfd->flags & BFD_LINKER_CREATED)
13100 return TRUE;
13101
9274e9de
TG		 13102 /* Skip any input that hasn't attribute section.
13103 This enables to link object files without attribute section with
13104 any others. */
13105 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13106 return TRUE;
13107
104d59d1 13108 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13109 {
13110 /* This is the first object. Copy the attributes. */
104d59d1 13111 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13112
cd21e546
MGD		 13113 out_attr = elf_known_obj_attributes_proc (obfd);
13114
004ae526
PB		 13115 /* Use the Tag_null value to indicate the attributes have been
13116 initialized. */
cd21e546 13117 out_attr[0].i = 1;
004ae526 13118
cd21e546
MGD		 13119 /* We do not output objects with Tag_MPextension_use_legacy - we move
13120 the attribute's value to Tag_MPextension_use. */
13121 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13122 {
13123 if (out_attr[Tag_MPextension_use].i != 0
13124 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13125 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13126 {
13127 _bfd_error_handler
13128 (_("Error: %B has both the current and legacy "
13129 "Tag_MPextension_use attributes"), ibfd);
13130 result = FALSE;
13131 }
13132
13133 out_attr[Tag_MPextension_use] =
13134 out_attr[Tag_MPextension_use_legacy];
13135 out_attr[Tag_MPextension_use_legacy].type = 0;
13136 out_attr[Tag_MPextension_use_legacy].i = 0;
13137 }
13138
13139 return result;
ee065d83
PB		 13140 }
13141
104d59d1
JM		 13142 in_attr = elf_known_obj_attributes_proc (ibfd);
13143 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13144 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13145 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13146 {
5c294fee
TG		 13147 /* Ignore mismatches if the object doesn't use floating point or is
13148 floating point ABI independent. */
13149 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13150 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13151 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13152 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13153 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13154 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13155 {
13156 _bfd_error_handler
3895f852 13157 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13158 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13159 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13160 result = FALSE;
ee065d83
PB		 13161 }
13162 }
13163
3de4a297 13164 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13165 {
13166 /* Merge this attribute with existing attributes. */
13167 switch (i)
13168 {
13169 case Tag_CPU_raw_name:
13170 case Tag_CPU_name:
6a631e86 13171 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13172 break;
13173
13174 case Tag_ABI_optimization_goals:
13175 case Tag_ABI_FP_optimization_goals:
13176 /* Use the first value seen. */
13177 break;
13178
13179 case Tag_CPU_arch:
91e22acd
AS		 13180 {
13181 int secondary_compat = -1, secondary_compat_out = -1;
13182 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13183 int arch_attr;
13184 static const char *name_table[] =
13185 {
91e22acd
AS		 13186 /* These aren't real CPU names, but we can't guess
13187 that from the architecture version alone. */
13188 "Pre v4",
13189 "ARM v4",
13190 "ARM v4T",
13191 "ARM v5T",
13192 "ARM v5TE",
13193 "ARM v5TEJ",
13194 "ARM v6",
13195 "ARM v6KZ",
13196 "ARM v6T2",
13197 "ARM v6K",
13198 "ARM v7",
13199 "ARM v6-M",
bca38921 13200 "ARM v6S-M",
2fd158eb
TP		 13201 "ARM v8",
13202 "",
13203 "ARM v8-M.baseline",
13204 "ARM v8-M.mainline",
91e22acd
AS		 13205 };
13206
13207 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13208 secondary_compat = get_secondary_compatible_arch (ibfd);
13209 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13210 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13211 &secondary_compat_out,
13212 in_attr[i].i,
13213 secondary_compat);
13214
13215 /* Return with error if failed to merge. */
13216 if (arch_attr == -1)
13217 return FALSE;
13218
13219 out_attr[i].i = arch_attr;
13220
91e22acd
AS		 13221 set_secondary_compatible_arch (obfd, secondary_compat_out);
13222
13223 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13224 if (out_attr[i].i == saved_out_attr)
13225 ; /* Leave the names alone. */
13226 else if (out_attr[i].i == in_attr[i].i)
13227 {
13228 /* The output architecture has been changed to match the
13229 input architecture. Use the input names. */
13230 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13231 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13232 : NULL;
13233 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13234 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13235 : NULL;
13236 }
13237 else
13238 {
13239 out_attr[Tag_CPU_name].s = NULL;
13240 out_attr[Tag_CPU_raw_name].s = NULL;
13241 }
13242
13243 /* If we still don't have a value for Tag_CPU_name,
13244 make one up now. Tag_CPU_raw_name remains blank. */
13245 if (out_attr[Tag_CPU_name].s == NULL
13246 && out_attr[i].i < ARRAY_SIZE (name_table))
13247 out_attr[Tag_CPU_name].s =
13248 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13249 }
13250 break;
13251
ee065d83
PB		 13252 case Tag_ARM_ISA_use:
13253 case Tag_THUMB_ISA_use:
ee065d83 13254 case Tag_WMMX_arch:
91e22acd
AS		 13255 case Tag_Advanced_SIMD_arch:
13256 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13257 case Tag_ABI_FP_rounding:
ee065d83
PB		 13258 case Tag_ABI_FP_exceptions:
13259 case Tag_ABI_FP_user_exceptions:
13260 case Tag_ABI_FP_number_model:
75375b3e 13261 case Tag_FP_HP_extension:
91e22acd
AS		 13262 case Tag_CPU_unaligned_access:
13263 case Tag_T2EE_use:
91e22acd 13264 case Tag_MPextension_use:
ee065d83
PB		 13265 /* Use the largest value specified. */
13266 if (in_attr[i].i > out_attr[i].i)
13267 out_attr[i].i = in_attr[i].i;
13268 break;
13269
75375b3e 13270 case Tag_ABI_align_preserved:
91e22acd
AS		 13271 case Tag_ABI_PCS_RO_data:
13272 /* Use the smallest value specified. */
13273 if (in_attr[i].i < out_attr[i].i)
13274 out_attr[i].i = in_attr[i].i;
13275 break;
13276
75375b3e 13277 case Tag_ABI_align_needed:
91e22acd 13278 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13279 && (in_attr[Tag_ABI_align_preserved].i == 0
13280 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13281 {
91e22acd
AS		 13282 /* This error message should be enabled once all non-conformant
13283 binaries in the toolchain have had the attributes set
13284 properly.
ee065d83 13285 _bfd_error_handler
3895f852 13286 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13287 obfd, ibfd);
13288 result = FALSE; */
ee065d83 13289 }
91e22acd
AS		 13290 /* Fall through. */
13291 case Tag_ABI_FP_denormal:
13292 case Tag_ABI_PCS_GOT_use:
13293 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13294 value if greater than 2 (for future-proofing). */
13295 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13296 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13297 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13298 out_attr[i].i = in_attr[i].i;
13299 break;
91e22acd 13300
75375b3e
MGD		 13301 case Tag_Virtualization_use:
13302 /* The virtualization tag effectively stores two bits of
13303 information: the intended use of TrustZone (in bit 0), and the
13304 intended use of Virtualization (in bit 1). */
13305 if (out_attr[i].i == 0)
13306 out_attr[i].i = in_attr[i].i;
13307 else if (in_attr[i].i != 0
13308 && in_attr[i].i != out_attr[i].i)
13309 {
13310 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13311 out_attr[i].i = 3;
13312 else
13313 {
13314 _bfd_error_handler
13315 (_("error: %B: unable to merge virtualization attributes "
13316 "with %B"),
13317 obfd, ibfd);
13318 result = FALSE;
13319 }
13320 }
13321 break;
91e22acd
AS		 13322
13323 case Tag_CPU_arch_profile:
13324 if (out_attr[i].i != in_attr[i].i)
13325 {
13326 /* 0 will merge with anything.
13327 'A' and 'S' merge to 'A'.
13328 'R' and 'S' merge to 'R'.
99059e56 13329 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13330 if (out_attr[i].i == 0
13331 || (out_attr[i].i == 'S'
13332 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13333 out_attr[i].i = in_attr[i].i;
13334 else if (in_attr[i].i == 0
13335 || (in_attr[i].i == 'S'
13336 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13337 ; /* Do nothing. */
91e22acd
AS		 13338 else
13339 {
13340 _bfd_error_handler
3895f852 13341 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13342 ibfd,
13343 in_attr[i].i ? in_attr[i].i : '0',
13344 out_attr[i].i ? out_attr[i].i : '0');
13345 result = FALSE;
13346 }
13347 }
13348 break;
15afaa63
TP		 13349
13350 case Tag_DSP_extension:
13351 /* No need to change output value if any of:
13352 - pre (<=) ARMv5T input architecture (do not have DSP)
13353 - M input profile not ARMv7E-M and do not have DSP. */
13354 if (in_attr[Tag_CPU_arch].i <= 3
13355 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13356 && in_attr[Tag_CPU_arch].i != 13
13357 && in_attr[i].i == 0))
13358 ; /* Do nothing. */
13359 /* Output value should be 0 if DSP part of architecture, ie.
13360 - post (>=) ARMv5te architecture output
13361 - A, R or S profile output or ARMv7E-M output architecture. */
13362 else if (out_attr[Tag_CPU_arch].i >= 4
13363 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13364 || out_attr[Tag_CPU_arch_profile].i == 'R'
13365 || out_attr[Tag_CPU_arch_profile].i == 'S'
13366 || out_attr[Tag_CPU_arch].i == 13))
13367 out_attr[i].i = 0;
13368 /* Otherwise, DSP instructions are added and not part of output
13369 architecture. */
13370 else
13371 out_attr[i].i = 1;
13372 break;
13373
75375b3e 13374 case Tag_FP_arch:
62f3b8c8 13375 {
4547cb56
NC		 13376 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13377 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13378 when it's 0. It might mean absence of FP hardware if
99654aaf 13379 Tag_FP_arch is zero. */
4547cb56 13380
a715796b 13381#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13382 static const struct
13383 {
13384 int ver;
13385 int regs;
bca38921 13386 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13387 {
13388 {0, 0},
13389 {1, 16},
13390 {2, 16},
13391 {3, 32},
13392 {3, 16},
13393 {4, 32},
bca38921 13394 {4, 16},
a715796b
TG		 13395 {8, 32},
13396 {8, 16}
62f3b8c8
PB		 13397 };
13398 int ver;
13399 int regs;
13400 int newval;
13401
4547cb56
NC		 13402 /* If the output has no requirement about FP hardware,
13403 follow the requirement of the input. */
13404 if (out_attr[i].i == 0)
13405 {
13406 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13407 out_attr[i].i = in_attr[i].i;
13408 out_attr[Tag_ABI_HardFP_use].i
13409 = in_attr[Tag_ABI_HardFP_use].i;
13410 break;
13411 }
13412 /* If the input has no requirement about FP hardware, do
13413 nothing. */
13414 else if (in_attr[i].i == 0)
13415 {
13416 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
13417 break;
13418 }
13419
13420 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13421 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13422
13423 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13424 do nothing. */
13425 if (in_attr[Tag_ABI_HardFP_use].i == 0
13426 && out_attr[Tag_ABI_HardFP_use].i == 0)
13427 ;
13428 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13429 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13430 else if (in_attr[Tag_ABI_HardFP_use].i
13431 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13432 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13433
13434 /* Now we can handle Tag_FP_arch. */
13435
bca38921
MGD		 13436 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13437 pick the biggest. */
13438 if (in_attr[i].i >= VFP_VERSION_COUNT
13439 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13440 {
13441 out_attr[i] = in_attr[i];
13442 break;
13443 }
13444 /* The output uses the superset of input features
13445 (ISA version) and registers. */
13446 ver = vfp_versions[in_attr[i].i].ver;
13447 if (ver < vfp_versions[out_attr[i].i].ver)
13448 ver = vfp_versions[out_attr[i].i].ver;
13449 regs = vfp_versions[in_attr[i].i].regs;
13450 if (regs < vfp_versions[out_attr[i].i].regs)
13451 regs = vfp_versions[out_attr[i].i].regs;
13452 /* This assumes all possible supersets are also a valid
99059e56 13453 options. */
bca38921 13454 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13455 {
13456 if (regs == vfp_versions[newval].regs
13457 && ver == vfp_versions[newval].ver)
13458 break;
13459 }
13460 out_attr[i].i = newval;
13461 }
b1cc4aeb 13462 break;
ee065d83
PB		 13463 case Tag_PCS_config:
13464 if (out_attr[i].i == 0)
13465 out_attr[i].i = in_attr[i].i;
b6009aca 13466 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13467 {
13468 /* It's sometimes ok to mix different configs, so this is only
99059e56 13469 a warning. */
ee065d83
PB		 13470 _bfd_error_handler
13471 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13472 }
13473 break;
13474 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13475 if (in_attr[i].i != out_attr[i].i
13476 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13477 && in_attr[i].i != AEABI_R9_unused)
13478 {
13479 _bfd_error_handler
3895f852 13480 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13481 result = FALSE;
ee065d83
PB		 13482 }
13483 if (out_attr[i].i == AEABI_R9_unused)
13484 out_attr[i].i = in_attr[i].i;
13485 break;
13486 case Tag_ABI_PCS_RW_data:
13487 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13488 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13489 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13490 {
13491 _bfd_error_handler
3895f852 13492 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13493 ibfd);
91e22acd 13494 result = FALSE;
ee065d83
PB		 13495 }
13496 /* Use the smallest value specified. */
13497 if (in_attr[i].i < out_attr[i].i)
13498 out_attr[i].i = in_attr[i].i;
13499 break;
ee065d83 13500 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13501 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13502 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13503 {
13504 _bfd_error_handler
a9dc9481
JM		 13505 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13506 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13507 }
a9dc9481 13508 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13509 out_attr[i].i = in_attr[i].i;
13510 break;
ee065d83
PB		 13511 case Tag_ABI_enum_size:
13512 if (in_attr[i].i != AEABI_enum_unused)
13513 {
13514 if (out_attr[i].i == AEABI_enum_unused
13515 || out_attr[i].i == AEABI_enum_forced_wide)
13516 {
13517 /* The existing object is compatible with anything.
13518 Use whatever requirements the new object has. */
13519 out_attr[i].i = in_attr[i].i;
13520 }
13521 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13522 && out_attr[i].i != in_attr[i].i
0ffa91dd 13523 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13524 {
91e22acd 13525 static const char *aeabi_enum_names[] =
bf21ed78 13526 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13527 const char *in_name =
13528 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13529 ? aeabi_enum_names[in_attr[i].i]
13530 : "<unknown>";
13531 const char *out_name =
13532 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13533 ? aeabi_enum_names[out_attr[i].i]
13534 : "<unknown>";
ee065d83 13535 _bfd_error_handler
bf21ed78 13536 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13537 ibfd, in_name, out_name);
ee065d83
PB		 13538 }
13539 }
13540 break;
13541 case Tag_ABI_VFP_args:
13542 /* Aready done. */
13543 break;
13544 case Tag_ABI_WMMX_args:
13545 if (in_attr[i].i != out_attr[i].i)
13546 {
13547 _bfd_error_handler
3895f852 13548 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13549 ibfd, obfd);
91e22acd 13550 result = FALSE;
ee065d83
PB		 13551 }
13552 break;
7b86a9fa
AS		 13553 case Tag_compatibility:
13554 /* Merged in target-independent code. */
13555 break;
91e22acd 13556 case Tag_ABI_HardFP_use:
4547cb56 13557 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13558 break;
13559 case Tag_ABI_FP_16bit_format:
13560 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13561 {
13562 if (in_attr[i].i != out_attr[i].i)
13563 {
13564 _bfd_error_handler
3895f852 13565 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13566 ibfd, obfd);
13567 result = FALSE;
13568 }
13569 }
13570 if (in_attr[i].i != 0)
13571 out_attr[i].i = in_attr[i].i;
13572 break;
7b86a9fa 13573
cd21e546 13574 case Tag_DIV_use:
ac56ee8f
MGD		 13575 /* A value of zero on input means that the divide instruction may
13576 be used if available in the base architecture as specified via
13577 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
13578 the user did not want divide instructions. A value of 2
13579 explicitly means that divide instructions were allowed in ARM
13580 and Thumb state. */
13581 if (in_attr[i].i == out_attr[i].i)
13582 /* Do nothing. */ ;
13583 else if (elf32_arm_attributes_forbid_div (in_attr)
13584 && !elf32_arm_attributes_accept_div (out_attr))
13585 out_attr[i].i = 1;
13586 else if (elf32_arm_attributes_forbid_div (out_attr)
13587 && elf32_arm_attributes_accept_div (in_attr))
13588 out_attr[i].i = in_attr[i].i;
13589 else if (in_attr[i].i == 2)
13590 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 13591 break;
13592
13593 case Tag_MPextension_use_legacy:
13594 /* We don't output objects with Tag_MPextension_use_legacy - we
13595 move the value to Tag_MPextension_use. */
13596 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
13597 {
13598 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
13599 {
13600 _bfd_error_handler
13601 (_("%B has has both the current and legacy "
b38cadfb 13602 "Tag_MPextension_use attributes"),
cd21e546
MGD		 13603 ibfd);
13604 result = FALSE;
13605 }
13606 }
13607
13608 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
13609 out_attr[Tag_MPextension_use] = in_attr[i];
13610
13611 break;
13612
91e22acd 13613 case Tag_nodefaults:
2d0bb761
AS		 13614 /* This tag is set if it exists, but the value is unused (and is
13615 typically zero). We don't actually need to do anything here -
13616 the merge happens automatically when the type flags are merged
13617 below. */
91e22acd
AS		 13618 break;
13619 case Tag_also_compatible_with:
13620 /* Already done in Tag_CPU_arch. */
13621 break;
13622 case Tag_conformance:
13623 /* Keep the attribute if it matches. Throw it away otherwise.
13624 No attribute means no claim to conform. */
13625 if (!in_attr[i].s || !out_attr[i].s
13626 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
13627 out_attr[i].s = NULL;
13628 break;
3cfad14c 13629
91e22acd 13630 default:
e8b36cd1
JM		 13631 result
13632 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 13633 }
13634
13635 /* If out_attr was copied from in_attr then it won't have a type yet. */
13636 if (in_attr[i].type && !out_attr[i].type)
13637 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 13638 }
13639
104d59d1 13640 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 13641 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
13642 return FALSE;
ee065d83 13643
104d59d1 13644 /* Check for any attributes not known on ARM. */
e8b36cd1 13645 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 13646
91e22acd 13647 return result;
252b5132
RH		 13648}
13649
3a4a14e9
PB		 13650
13651/* Return TRUE if the two EABI versions are incompatible. */
13652
13653static bfd_boolean
13654elf32_arm_versions_compatible (unsigned iver, unsigned over)
13655{
13656 /* v4 and v5 are the same spec before and after it was released,
13657 so allow mixing them. */
13658 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
13659 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
13660 return TRUE;
13661
13662 return (iver == over);
13663}
13664
252b5132
RH		 13665/* Merge backend specific data from an object file to the output
13666 object file when linking. */
9b485d32 13667
b34976b6 13668static bfd_boolean
21d799b5 13669elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 13670
9b485d32
NC		 13671/* Display the flags field. */
13672
b34976b6 13673static bfd_boolean
57e8b36a 13674elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 13675{
fc830a83
NC		 13676 FILE * file = (FILE *) ptr;
13677 unsigned long flags;
252b5132
RH		 13678
13679 BFD_ASSERT (abfd != NULL && ptr != NULL);
13680
13681 /* Print normal ELF private data. */
13682 _bfd_elf_print_private_bfd_data (abfd, ptr);
13683
fc830a83 13684 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 13685 /* Ignore init flag - it may not be set, despite the flags field
13686 containing valid data. */
252b5132
RH		 13687
13688 /* xgettext:c-format */
9b485d32 13689 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 13690
fc830a83
NC		 13691 switch (EF_ARM_EABI_VERSION (flags))
13692 {
13693 case EF_ARM_EABI_UNKNOWN:
4cc11e76 13694 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 13695 official ARM ELF extended ABI. Hence they are only decoded if
13696 the EABI version is not set. */
fd2ec330 13697 if (flags & EF_ARM_INTERWORK)
9b485d32 13698 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 13699
fd2ec330 13700 if (flags & EF_ARM_APCS_26)
6c571f00 13701 fprintf (file, " [APCS-26]");
fc830a83 13702 else
6c571f00 13703 fprintf (file, " [APCS-32]");
9a5aca8c 13704
96a846ea
RE		 13705 if (flags & EF_ARM_VFP_FLOAT)
13706 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 13707 else if (flags & EF_ARM_MAVERICK_FLOAT)
13708 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 13709 else
13710 fprintf (file, _(" [FPA float format]"));
13711
fd2ec330 13712 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 13713 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 13714
fd2ec330 13715 if (flags & EF_ARM_PIC)
9b485d32 13716 fprintf (file, _(" [position independent]"));
fc830a83 13717
fd2ec330 13718 if (flags & EF_ARM_NEW_ABI)
9b485d32 13719 fprintf (file, _(" [new ABI]"));
9a5aca8c 13720
fd2ec330 13721 if (flags & EF_ARM_OLD_ABI)
9b485d32 13722 fprintf (file, _(" [old ABI]"));
9a5aca8c 13723
fd2ec330 13724 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 13725 fprintf (file, _(" [software FP]"));
9a5aca8c 13726
96a846ea
RE		 13727 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
13728 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 13729 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
13730 | EF_ARM_MAVERICK_FLOAT);
fc830a83 13731 break;
9a5aca8c 13732
fc830a83 13733 case EF_ARM_EABI_VER1:
9b485d32 13734 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 13735
fc830a83 13736 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 13737 fprintf (file, _(" [sorted symbol table]"));
fc830a83 13738 else
9b485d32 13739 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 13740
fc830a83
NC		 13741 flags &= ~ EF_ARM_SYMSARESORTED;
13742 break;
9a5aca8c 13743
fd2ec330
PB		 13744 case EF_ARM_EABI_VER2:
13745 fprintf (file, _(" [Version2 EABI]"));
13746
13747 if (flags & EF_ARM_SYMSARESORTED)
13748 fprintf (file, _(" [sorted symbol table]"));
13749 else
13750 fprintf (file, _(" [unsorted symbol table]"));
13751
13752 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
13753 fprintf (file, _(" [dynamic symbols use segment index]"));
13754
13755 if (flags & EF_ARM_MAPSYMSFIRST)
13756 fprintf (file, _(" [mapping symbols precede others]"));
13757
99e4ae17 13758 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 13759 | EF_ARM_MAPSYMSFIRST);
13760 break;
13761
d507cf36
PB		 13762 case EF_ARM_EABI_VER3:
13763 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 13764 break;
13765
13766 case EF_ARM_EABI_VER4:
13767 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 13768 goto eabi;
d507cf36 13769
3a4a14e9
PB		 13770 case EF_ARM_EABI_VER5:
13771 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 13772
13773 if (flags & EF_ARM_ABI_FLOAT_SOFT)
13774 fprintf (file, _(" [soft-float ABI]"));
13775
13776 if (flags & EF_ARM_ABI_FLOAT_HARD)
13777 fprintf (file, _(" [hard-float ABI]"));
13778
13779 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
13780
3a4a14e9 13781 eabi:
d507cf36
PB		 13782 if (flags & EF_ARM_BE8)
13783 fprintf (file, _(" [BE8]"));
13784
13785 if (flags & EF_ARM_LE8)
13786 fprintf (file, _(" [LE8]"));
13787
13788 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
13789 break;
13790
fc830a83 13791 default:
9b485d32 13792 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 13793 break;
13794 }
252b5132 13795
fc830a83 13796 flags &= ~ EF_ARM_EABIMASK;
252b5132 13797
fc830a83 13798 if (flags & EF_ARM_RELEXEC)
9b485d32 13799 fprintf (file, _(" [relocatable executable]"));
252b5132 13800
a5721edd 13801 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 13802
13803 if (flags)
9b485d32 13804 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 13805
252b5132
RH		 13806 fputc ('\n', file);
13807
b34976b6 13808 return TRUE;
252b5132
RH		 13809}
13810
13811static int
57e8b36a 13812elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 13813{
2f0ca46a
NC		 13814 switch (ELF_ST_TYPE (elf_sym->st_info))
13815 {
13816 case STT_ARM_TFUNC:
13817 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 13818
2f0ca46a
NC		 13819 case STT_ARM_16BIT:
13820 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13821 This allows us to distinguish between data used by Thumb instructions
13822 and non-data (which is probably code) inside Thumb regions of an
13823 executable. */
1a0eb693 13824 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 13825 return ELF_ST_TYPE (elf_sym->st_info);
13826 break;
9a5aca8c 13827
ce855c42
NC		 13828 default:
13829 break;
2f0ca46a
NC		 13830 }
13831
13832 return type;
252b5132 13833}
f21f3fe0 13834
252b5132 13835static asection *
07adf181
AM		 13836elf32_arm_gc_mark_hook (asection *sec,
13837 struct bfd_link_info *info,
13838 Elf_Internal_Rela *rel,
13839 struct elf_link_hash_entry *h,
13840 Elf_Internal_Sym *sym)
252b5132
RH		 13841{
13842 if (h != NULL)
07adf181 13843 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 13844 {
13845 case R_ARM_GNU_VTINHERIT:
13846 case R_ARM_GNU_VTENTRY:
07adf181
AM		 13847 return NULL;
13848 }
9ad5cbcf 13849
07adf181 13850 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 13851}
13852
780a67af
NC		 13853/* Update the got entry reference counts for the section being removed. */
13854
b34976b6 13855static bfd_boolean
ba93b8ac
DJ		 13856elf32_arm_gc_sweep_hook (bfd * abfd,
13857 struct bfd_link_info * info,
13858 asection * sec,
13859 const Elf_Internal_Rela * relocs)
252b5132 13860{
5e681ec4
PB		 13861 Elf_Internal_Shdr *symtab_hdr;
13862 struct elf_link_hash_entry **sym_hashes;
13863 bfd_signed_vma *local_got_refcounts;
13864 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 13865 struct elf32_arm_link_hash_table * globals;
13866
0e1862bb 13867 if (bfd_link_relocatable (info))
7dda2462
TG		 13868 return TRUE;
13869
eb043451 13870 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13871 if (globals == NULL)
13872 return FALSE;
5e681ec4
PB		 13873
13874 elf_section_data (sec)->local_dynrel = NULL;
13875
0ffa91dd 13876 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 13877 sym_hashes = elf_sym_hashes (abfd);
13878 local_got_refcounts = elf_local_got_refcounts (abfd);
13879
906e58ca 13880 check_use_blx (globals);
bd97cb95 13881
5e681ec4
PB		 13882 relend = relocs + sec->reloc_count;
13883 for (rel = relocs; rel < relend; rel++)
eb043451 13884 {
3eb128b2
AM		 13885 unsigned long r_symndx;
13886 struct elf_link_hash_entry *h = NULL;
f6e32f6d 13887 struct elf32_arm_link_hash_entry *eh;
eb043451 13888 int r_type;
34e77a92 13889 bfd_boolean call_reloc_p;
f6e32f6d
RS		 13890 bfd_boolean may_become_dynamic_p;
13891 bfd_boolean may_need_local_target_p;
34e77a92
RS		 13892 union gotplt_union *root_plt;
13893 struct arm_plt_info *arm_plt;
5e681ec4 13894
3eb128b2
AM		 13895 r_symndx = ELF32_R_SYM (rel->r_info);
13896 if (r_symndx >= symtab_hdr->sh_info)
13897 {
13898 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13899 while (h->root.type == bfd_link_hash_indirect
13900 || h->root.type == bfd_link_hash_warning)
13901 h = (struct elf_link_hash_entry *) h->root.u.i.link;
13902 }
f6e32f6d
RS		 13903 eh = (struct elf32_arm_link_hash_entry *) h;
13904
34e77a92 13905 call_reloc_p = FALSE;
f6e32f6d
RS		 13906 may_become_dynamic_p = FALSE;
13907 may_need_local_target_p = FALSE;
3eb128b2 13908
eb043451 13909 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13910 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 13911 switch (r_type)
13912 {
13913 case R_ARM_GOT32:
eb043451 13914 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13915 case R_ARM_TLS_GD32:
13916 case R_ARM_TLS_IE32:
3eb128b2 13917 if (h != NULL)
eb043451 13918 {
eb043451
PB		 13919 if (h->got.refcount > 0)
13920 h->got.refcount -= 1;
13921 }
13922 else if (local_got_refcounts != NULL)
13923 {
13924 if (local_got_refcounts[r_symndx] > 0)
13925 local_got_refcounts[r_symndx] -= 1;
13926 }
13927 break;
13928
ba93b8ac 13929 case R_ARM_TLS_LDM32:
4dfe6ac6 13930 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 13931 break;
13932
eb043451
PB		 13933 case R_ARM_PC24:
13934 case R_ARM_PLT32:
5b5bb741
PB		 13935 case R_ARM_CALL:
13936 case R_ARM_JUMP24:
eb043451 13937 case R_ARM_PREL31:
c19d1205 13938 case R_ARM_THM_CALL:
bd97cb95
DJ		 13939 case R_ARM_THM_JUMP24:
13940 case R_ARM_THM_JUMP19:
34e77a92 13941 call_reloc_p = TRUE;
f6e32f6d
RS		 13942 may_need_local_target_p = TRUE;
13943 break;
13944
13945 case R_ARM_ABS12:
13946 if (!globals->vxworks_p)
13947 {
13948 may_need_local_target_p = TRUE;
13949 break;
13950 }
13951 /* Fall through. */
13952 case R_ARM_ABS32:
13953 case R_ARM_ABS32_NOI:
13954 case R_ARM_REL32:
13955 case R_ARM_REL32_NOI:
b6895b4f
PB		 13956 case R_ARM_MOVW_ABS_NC:
13957 case R_ARM_MOVT_ABS:
13958 case R_ARM_MOVW_PREL_NC:
13959 case R_ARM_MOVT_PREL:
13960 case R_ARM_THM_MOVW_ABS_NC:
13961 case R_ARM_THM_MOVT_ABS:
13962 case R_ARM_THM_MOVW_PREL_NC:
13963 case R_ARM_THM_MOVT_PREL:
b7693d02 13964 /* Should the interworking branches be here also? */
0e1862bb 13965 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 13966 && (sec->flags & SEC_ALLOC) != 0)
13967 {
13968 if (h == NULL
469a3493 13969 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13970 {
13971 call_reloc_p = TRUE;
13972 may_need_local_target_p = TRUE;
13973 }
13974 else
13975 may_become_dynamic_p = TRUE;
13976 }
f6e32f6d
RS		 13977 else
13978 may_need_local_target_p = TRUE;
13979 break;
b7693d02 13980
f6e32f6d
RS		 13981 default:
13982 break;
13983 }
5e681ec4 13984
34e77a92 13985 if (may_need_local_target_p
4ba2ef8f
TP		 13986 && elf32_arm_get_plt_info (abfd, globals, eh, r_symndx, &root_plt,
13987 &arm_plt))
f6e32f6d 13988 {
27586251
HPN		 13989 /* If PLT refcount book-keeping is wrong and too low, we'll
13990 see a zero value (going to -1) for the root PLT reference
13991 count. */
13992 if (root_plt->refcount >= 0)
13993 {
13994 BFD_ASSERT (root_plt->refcount != 0);
13995 root_plt->refcount -= 1;
13996 }
13997 else
13998 /* A value of -1 means the symbol has become local, forced
13999 or seeing a hidden definition. Any other negative value
14000 is an error. */
14001 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 14002
14003 if (!call_reloc_p)
14004 arm_plt->noncall_refcount--;
5e681ec4 14005
f6e32f6d 14006 if (r_type == R_ARM_THM_CALL)
34e77a92 14007 arm_plt->maybe_thumb_refcount--;
bd97cb95 14008
f6e32f6d
RS		 14009 if (r_type == R_ARM_THM_JUMP24
14010 || r_type == R_ARM_THM_JUMP19)
34e77a92 14011 arm_plt->thumb_refcount--;
f6e32f6d 14012 }
5e681ec4 14013
34e77a92 14014 if (may_become_dynamic_p)
f6e32f6d
RS		 14015 {
14016 struct elf_dyn_relocs **pp;
14017 struct elf_dyn_relocs *p;
5e681ec4 14018
34e77a92 14019 if (h != NULL)
9c489990 14020 pp = &(eh->dyn_relocs);
34e77a92
RS		 14021 else
14022 {
14023 Elf_Internal_Sym *isym;
14024
14025 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
14026 abfd, r_symndx);
14027 if (isym == NULL)
14028 return FALSE;
14029 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14030 if (pp == NULL)
14031 return FALSE;
14032 }
9c489990 14033 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 14034 if (p->sec == sec)
14035 {
14036 /* Everything must go for SEC. */
14037 *pp = p->next;
14038 break;
14039 }
eb043451
PB		 14040 }
14041 }
5e681ec4 14042
b34976b6 14043 return TRUE;
252b5132
RH		 14044}
14045
780a67af
NC		 14046/* Look through the relocs for a section during the first phase. */
14047
b34976b6 14048static bfd_boolean
57e8b36a
NC		 14049elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14050 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14051{
b34976b6
AM		 14052 Elf_Internal_Shdr *symtab_hdr;
14053 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14054 const Elf_Internal_Rela *rel;
14055 const Elf_Internal_Rela *rel_end;
14056 bfd *dynobj;
5e681ec4 14057 asection *sreloc;
5e681ec4 14058 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14059 bfd_boolean call_reloc_p;
14060 bfd_boolean may_become_dynamic_p;
14061 bfd_boolean may_need_local_target_p;
ce98a316 14062 unsigned long nsyms;
9a5aca8c 14063
0e1862bb 14064 if (bfd_link_relocatable (info))
b34976b6 14065 return TRUE;
9a5aca8c 14066
0ffa91dd
NC		 14067 BFD_ASSERT (is_arm_elf (abfd));
14068
5e681ec4 14069 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14070 if (htab == NULL)
14071 return FALSE;
14072
5e681ec4 14073 sreloc = NULL;
9a5aca8c 14074
67687978
PB		 14075 /* Create dynamic sections for relocatable executables so that we can
14076 copy relocations. */
14077 if (htab->root.is_relocatable_executable
14078 && ! htab->root.dynamic_sections_created)
14079 {
14080 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14081 return FALSE;
14082 }
14083
cbc704f3
RS		 14084 if (htab->root.dynobj == NULL)
14085 htab->root.dynobj = abfd;
34e77a92
RS		 14086 if (!create_ifunc_sections (info))
14087 return FALSE;
cbc704f3
RS		 14088
14089 dynobj = htab->root.dynobj;
14090
0ffa91dd 14091 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14092 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14093 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14094
252b5132
RH		 14095 rel_end = relocs + sec->reloc_count;
14096 for (rel = relocs; rel < rel_end; rel++)
14097 {
34e77a92 14098 Elf_Internal_Sym *isym;
252b5132 14099 struct elf_link_hash_entry *h;
b7693d02 14100 struct elf32_arm_link_hash_entry *eh;
252b5132 14101 unsigned long r_symndx;
eb043451 14102 int r_type;
9a5aca8c 14103
252b5132 14104 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14105 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14106 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14107
ce98a316
NC		 14108 if (r_symndx >= nsyms
14109 /* PR 9934: It is possible to have relocations that do not
14110 refer to symbols, thus it is also possible to have an
14111 object file containing relocations but no symbol table. */
cf35638d 14112 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 14113 {
14114 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 14115 r_symndx);
ba93b8ac
DJ		 14116 return FALSE;
14117 }
14118
34e77a92
RS		 14119 h = NULL;
14120 isym = NULL;
14121 if (nsyms > 0)
973a3492 14122 {
34e77a92
RS		 14123 if (r_symndx < symtab_hdr->sh_info)
14124 {
14125 /* A local symbol. */
14126 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14127 abfd, r_symndx);
14128 if (isym == NULL)
14129 return FALSE;
14130 }
14131 else
14132 {
14133 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14134 while (h->root.type == bfd_link_hash_indirect
14135 || h->root.type == bfd_link_hash_warning)
14136 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 14137
14138 /* PR15323, ref flags aren't set for references in the
14139 same object. */
14140 h->root.non_ir_ref = 1;
34e77a92 14141 }
973a3492 14142 }
9a5aca8c 14143
b7693d02
DJ		 14144 eh = (struct elf32_arm_link_hash_entry *) h;
14145
f6e32f6d
RS		 14146 call_reloc_p = FALSE;
14147 may_become_dynamic_p = FALSE;
14148 may_need_local_target_p = FALSE;
14149
0855e32b
NS		 14150 /* Could be done earlier, if h were already available. */
14151 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14152 switch (r_type)
99059e56 14153 {
5e681ec4 14154 case R_ARM_GOT32:
eb043451 14155 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14156 case R_ARM_TLS_GD32:
14157 case R_ARM_TLS_IE32:
0855e32b
NS		 14158 case R_ARM_TLS_GOTDESC:
14159 case R_ARM_TLS_DESCSEQ:
14160 case R_ARM_THM_TLS_DESCSEQ:
14161 case R_ARM_TLS_CALL:
14162 case R_ARM_THM_TLS_CALL:
5e681ec4 14163 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14164 {
14165 int tls_type, old_tls_type;
5e681ec4 14166
ba93b8ac
DJ		 14167 switch (r_type)
14168 {
14169 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14170
ba93b8ac 14171 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14172
0855e32b
NS		 14173 case R_ARM_TLS_GOTDESC:
14174 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14175 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14176 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14177
ba93b8ac
DJ		 14178 default: tls_type = GOT_NORMAL; break;
14179 }
252b5132 14180
0e1862bb 14181 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14182 info->flags |= DF_STATIC_TLS;
14183
ba93b8ac
DJ		 14184 if (h != NULL)
14185 {
14186 h->got.refcount++;
14187 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14188 }
14189 else
14190 {
ba93b8ac 14191 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14192 if (!elf32_arm_allocate_local_sym_info (abfd))
14193 return FALSE;
14194 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14195 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14196 }
14197
0855e32b 14198 /* If a variable is accessed with both tls methods, two
99059e56 14199 slots may be created. */
0855e32b
NS		 14200 if (GOT_TLS_GD_ANY_P (old_tls_type)
14201 && GOT_TLS_GD_ANY_P (tls_type))
14202 tls_type |= old_tls_type;
14203
14204 /* We will already have issued an error message if there
14205 is a TLS/non-TLS mismatch, based on the symbol
14206 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14207 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14208 && tls_type != GOT_NORMAL)
14209 tls_type |= old_tls_type;
14210
0855e32b 14211 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14212 method, we're able to relax. Turn off the GDESC flag,
14213 without messing up with any other kind of tls types
6a631e86 14214 that may be involved. */
0855e32b
NS		 14215 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14216 tls_type &= ~GOT_TLS_GDESC;
14217
ba93b8ac
DJ		 14218 if (old_tls_type != tls_type)
14219 {
14220 if (h != NULL)
14221 elf32_arm_hash_entry (h)->tls_type = tls_type;
14222 else
14223 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14224 }
14225 }
8029a119 14226 /* Fall through. */
ba93b8ac
DJ		 14227
14228 case R_ARM_TLS_LDM32:
14229 if (r_type == R_ARM_TLS_LDM32)
14230 htab->tls_ldm_got.refcount++;
8029a119 14231 /* Fall through. */
252b5132 14232
c19d1205 14233 case R_ARM_GOTOFF32:
5e681ec4 14234 case R_ARM_GOTPC:
cbc704f3
RS		 14235 if (htab->root.sgot == NULL
14236 && !create_got_section (htab->root.dynobj, info))
14237 return FALSE;
252b5132
RH		 14238 break;
14239
252b5132 14240 case R_ARM_PC24:
7359ea65 14241 case R_ARM_PLT32:
5b5bb741
PB		 14242 case R_ARM_CALL:
14243 case R_ARM_JUMP24:
eb043451 14244 case R_ARM_PREL31:
c19d1205 14245 case R_ARM_THM_CALL:
bd97cb95
DJ		 14246 case R_ARM_THM_JUMP24:
14247 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14248 call_reloc_p = TRUE;
14249 may_need_local_target_p = TRUE;
14250 break;
14251
14252 case R_ARM_ABS12:
14253 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14254 ldr __GOTT_INDEX__ offsets. */
14255 if (!htab->vxworks_p)
14256 {
14257 may_need_local_target_p = TRUE;
14258 break;
14259 }
aebf9be7
NC		 14260 else goto jump_over;
14261
f6e32f6d 14262 /* Fall through. */
39623e12 14263
96c23d59
JM		 14264 case R_ARM_MOVW_ABS_NC:
14265 case R_ARM_MOVT_ABS:
14266 case R_ARM_THM_MOVW_ABS_NC:
14267 case R_ARM_THM_MOVT_ABS:
0e1862bb 14268 if (bfd_link_pic (info))
96c23d59
JM		 14269 {
14270 (*_bfd_error_handler)
14271 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14272 abfd, elf32_arm_howto_table_1[r_type].name,
14273 (h) ? h->root.root.string : "a local symbol");
14274 bfd_set_error (bfd_error_bad_value);
14275 return FALSE;
14276 }
14277
14278 /* Fall through. */
39623e12
PB		 14279 case R_ARM_ABS32:
14280 case R_ARM_ABS32_NOI:
aebf9be7 14281 jump_over:
0e1862bb 14282 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14283 {
14284 h->pointer_equality_needed = 1;
14285 }
14286 /* Fall through. */
39623e12
PB		 14287 case R_ARM_REL32:
14288 case R_ARM_REL32_NOI:
b6895b4f
PB		 14289 case R_ARM_MOVW_PREL_NC:
14290 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14291 case R_ARM_THM_MOVW_PREL_NC:
14292 case R_ARM_THM_MOVT_PREL:
39623e12 14293
b7693d02 14294 /* Should the interworking branches be listed here? */
0e1862bb 14295 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14296 && (sec->flags & SEC_ALLOC) != 0)
14297 {
14298 if (h == NULL
469a3493 14299 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14300 {
14301 /* In shared libraries and relocatable executables,
14302 we treat local relative references as calls;
14303 see the related SYMBOL_CALLS_LOCAL code in
14304 allocate_dynrelocs. */
14305 call_reloc_p = TRUE;
14306 may_need_local_target_p = TRUE;
14307 }
14308 else
14309 /* We are creating a shared library or relocatable
14310 executable, and this is a reloc against a global symbol,
14311 or a non-PC-relative reloc against a local symbol.
14312 We may need to copy the reloc into the output. */
14313 may_become_dynamic_p = TRUE;
14314 }
f6e32f6d
RS		 14315 else
14316 may_need_local_target_p = TRUE;
252b5132
RH		 14317 break;
14318
99059e56
RM		 14319 /* This relocation describes the C++ object vtable hierarchy.
14320 Reconstruct it for later use during GC. */
14321 case R_ARM_GNU_VTINHERIT:
14322 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14323 return FALSE;
14324 break;
14325
14326 /* This relocation describes which C++ vtable entries are actually
14327 used. Record for later use during GC. */
14328 case R_ARM_GNU_VTENTRY:
14329 BFD_ASSERT (h != NULL);
14330 if (h != NULL
14331 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14332 return FALSE;
14333 break;
14334 }
f6e32f6d
RS		 14335
14336 if (h != NULL)
14337 {
14338 if (call_reloc_p)
14339 /* We may need a .plt entry if the function this reloc
14340 refers to is in a different object, regardless of the
14341 symbol's type. We can't tell for sure yet, because
14342 something later might force the symbol local. */
14343 h->needs_plt = 1;
14344 else if (may_need_local_target_p)
14345 /* If this reloc is in a read-only section, we might
14346 need a copy reloc. We can't check reliably at this
14347 stage whether the section is read-only, as input
14348 sections have not yet been mapped to output sections.
14349 Tentatively set the flag for now, and correct in
14350 adjust_dynamic_symbol. */
14351 h->non_got_ref = 1;
14352 }
14353
34e77a92
RS		 14354 if (may_need_local_target_p
14355 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14356 {
34e77a92
RS		 14357 union gotplt_union *root_plt;
14358 struct arm_plt_info *arm_plt;
14359 struct arm_local_iplt_info *local_iplt;
14360
14361 if (h != NULL)
14362 {
14363 root_plt = &h->plt;
14364 arm_plt = &eh->plt;
14365 }
14366 else
14367 {
14368 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14369 if (local_iplt == NULL)
14370 return FALSE;
14371 root_plt = &local_iplt->root;
14372 arm_plt = &local_iplt->arm;
14373 }
14374
f6e32f6d
RS		 14375 /* If the symbol is a function that doesn't bind locally,
14376 this relocation will need a PLT entry. */
a8c887dd
NC		 14377 if (root_plt->refcount != -1)
14378 root_plt->refcount += 1;
34e77a92
RS		 14379
14380 if (!call_reloc_p)
14381 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14382
14383 /* It's too early to use htab->use_blx here, so we have to
14384 record possible blx references separately from
14385 relocs that definitely need a thumb stub. */
14386
14387 if (r_type == R_ARM_THM_CALL)
34e77a92 14388 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14389
14390 if (r_type == R_ARM_THM_JUMP24
14391 || r_type == R_ARM_THM_JUMP19)
34e77a92 14392 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14393 }
14394
14395 if (may_become_dynamic_p)
14396 {
14397 struct elf_dyn_relocs *p, **head;
14398
14399 /* Create a reloc section in dynobj. */
14400 if (sreloc == NULL)
14401 {
14402 sreloc = _bfd_elf_make_dynamic_reloc_section
14403 (sec, dynobj, 2, abfd, ! htab->use_rel);
14404
14405 if (sreloc == NULL)
14406 return FALSE;
14407
14408 /* BPABI objects never have dynamic relocations mapped. */
14409 if (htab->symbian_p)
14410 {
14411 flagword flags;
14412
14413 flags = bfd_get_section_flags (dynobj, sreloc);
14414 flags &= ~(SEC_LOAD | SEC_ALLOC);
14415 bfd_set_section_flags (dynobj, sreloc, flags);
14416 }
14417 }
14418
14419 /* If this is a global symbol, count the number of
14420 relocations we need for this symbol. */
14421 if (h != NULL)
14422 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14423 else
14424 {
34e77a92
RS		 14425 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14426 if (head == NULL)
f6e32f6d 14427 return FALSE;
f6e32f6d
RS		 14428 }
14429
14430 p = *head;
14431 if (p == NULL || p->sec != sec)
14432 {
14433 bfd_size_type amt = sizeof *p;
14434
14435 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14436 if (p == NULL)
14437 return FALSE;
14438 p->next = *head;
14439 *head = p;
14440 p->sec = sec;
14441 p->count = 0;
14442 p->pc_count = 0;
14443 }
14444
469a3493 14445 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14446 p->pc_count += 1;
14447 p->count += 1;
14448 }
252b5132 14449 }
f21f3fe0 14450
b34976b6 14451 return TRUE;
252b5132
RH		 14452}
14453
6a5bb875 14454/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 14455 required if the corresponding code section is marked. Similarly, ARMv8-M
14456 secure entry functions can only be referenced by SG veneers which are
14457 created after the GC process. They need to be marked in case they reside in
14458 their own section (as would be the case if code was compiled with
14459 -ffunction-sections). */
6a5bb875
PB		 14460
14461static bfd_boolean
906e58ca
NC		 14462elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
14463 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 14464{
14465 bfd *sub;
14466 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 14467 asection *cmse_sec;
14468 obj_attribute *out_attr;
14469 Elf_Internal_Shdr *symtab_hdr;
14470 unsigned i, sym_count, ext_start;
14471 const struct elf_backend_data *bed;
14472 struct elf_link_hash_entry **sym_hashes;
14473 struct elf32_arm_link_hash_entry *cmse_hash;
14474 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 14475
7f6ab9f8
AM		 14476 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
14477
4ba2ef8f
TP		 14478 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
14479 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
14480 && out_attr[Tag_CPU_arch_profile].i == 'M';
14481
6a5bb875
PB		 14482 /* Marking EH data may cause additional code sections to be marked,
14483 requiring multiple passes. */
14484 again = TRUE;
14485 while (again)
14486 {
14487 again = FALSE;
c72f2fb2 14488 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 14489 {
14490 asection *o;
14491
0ffa91dd 14492 if (! is_arm_elf (sub))
6a5bb875
PB		 14493 continue;
14494
14495 elf_shdrp = elf_elfsections (sub);
14496 for (o = sub->sections; o != NULL; o = o->next)
14497 {
14498 Elf_Internal_Shdr *hdr;
0ffa91dd 14499
6a5bb875 14500 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 14501 if (hdr->sh_type == SHT_ARM_EXIDX
14502 && hdr->sh_link
14503 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 14504 && !o->gc_mark
14505 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
14506 {
14507 again = TRUE;
14508 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
14509 return FALSE;
14510 }
14511 }
4ba2ef8f
TP		 14512
14513 /* Mark section holding ARMv8-M secure entry functions. We mark all
14514 of them so no need for a second browsing. */
14515 if (is_v8m && first_bfd_browse)
14516 {
14517 sym_hashes = elf_sym_hashes (sub);
14518 bed = get_elf_backend_data (sub);
14519 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
14520 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
14521 ext_start = symtab_hdr->sh_info;
14522
14523 /* Scan symbols. */
14524 for (i = ext_start; i < sym_count; i++)
14525 {
14526 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
14527
14528 /* Assume it is a special symbol. If not, cmse_scan will
14529 warn about it and user can do something about it. */
14530 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
14531 {
14532 cmse_sec = cmse_hash->root.root.u.def.section;
14533 if (!_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
14534 return FALSE;
14535 }
14536 }
14537 }
6a5bb875 14538 }
4ba2ef8f 14539 first_bfd_browse = FALSE;
6a5bb875
PB		 14540 }
14541
14542 return TRUE;
14543}
14544
3c9458e9
NC		 14545/* Treat mapping symbols as special target symbols. */
14546
14547static bfd_boolean
14548elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
14549{
b0796911
PB		 14550 return bfd_is_arm_special_symbol_name (sym->name,
14551 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 14552}
14553
0367ecfb
NC		 14554/* This is a copy of elf_find_function() from elf.c except that
14555 ARM mapping symbols are ignored when looking for function names
14556 and STT_ARM_TFUNC is considered to a function type. */
252b5132 14557
0367ecfb
NC		 14558static bfd_boolean
14559arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 14560 asymbol ** symbols,
fb167eb2 14561 asection * section,
0367ecfb
NC		 14562 bfd_vma offset,
14563 const char ** filename_ptr,
14564 const char ** functionname_ptr)
14565{
14566 const char * filename = NULL;
14567 asymbol * func = NULL;
14568 bfd_vma low_func = 0;
14569 asymbol ** p;
252b5132
RH		 14570
14571 for (p = symbols; *p != NULL; p++)
14572 {
14573 elf_symbol_type *q;
14574
14575 q = (elf_symbol_type *) *p;
14576
252b5132
RH		 14577 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
14578 {
14579 default:
14580 break;
14581 case STT_FILE:
14582 filename = bfd_asymbol_name (&q->symbol);
14583 break;
252b5132
RH		 14584 case STT_FUNC:
14585 case STT_ARM_TFUNC:
9d2da7ca 14586 case STT_NOTYPE:
b0796911 14587 /* Skip mapping symbols. */
0367ecfb 14588 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 14589 && bfd_is_arm_special_symbol_name (q->symbol.name,
14590 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 14591 continue;
14592 /* Fall through. */
6b40fcba 14593 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 14594 && q->symbol.value >= low_func
14595 && q->symbol.value <= offset)
14596 {
14597 func = (asymbol *) q;
14598 low_func = q->symbol.value;
14599 }
14600 break;
14601 }
14602 }
14603
14604 if (func == NULL)
b34976b6 14605 return FALSE;
252b5132 14606
0367ecfb
NC		 14607 if (filename_ptr)
14608 *filename_ptr = filename;
14609 if (functionname_ptr)
14610 *functionname_ptr = bfd_asymbol_name (func);
14611
14612 return TRUE;
906e58ca 14613}
0367ecfb
NC		 14614
14615
14616/* Find the nearest line to a particular section and offset, for error
14617 reporting. This code is a duplicate of the code in elf.c, except
14618 that it uses arm_elf_find_function. */
14619
14620static bfd_boolean
14621elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 14622 asymbol ** symbols,
fb167eb2 14623 asection * section,
0367ecfb
NC		 14624 bfd_vma offset,
14625 const char ** filename_ptr,
14626 const char ** functionname_ptr,
fb167eb2
AM		 14627 unsigned int * line_ptr,
14628 unsigned int * discriminator_ptr)
0367ecfb
NC		 14629{
14630 bfd_boolean found = FALSE;
14631
fb167eb2 14632 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 14633 filename_ptr, functionname_ptr,
fb167eb2
AM		 14634 line_ptr, discriminator_ptr,
14635 dwarf_debug_sections, 0,
0367ecfb
NC		 14636 & elf_tdata (abfd)->dwarf2_find_line_info))
14637 {
14638 if (!*functionname_ptr)
fb167eb2 14639 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14640 *filename_ptr ? NULL : filename_ptr,
14641 functionname_ptr);
f21f3fe0 14642
0367ecfb
NC		 14643 return TRUE;
14644 }
14645
fb167eb2
AM		 14646 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
14647 uses DWARF1. */
14648
0367ecfb
NC		 14649 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
14650 & found, filename_ptr,
14651 functionname_ptr, line_ptr,
14652 & elf_tdata (abfd)->line_info))
14653 return FALSE;
14654
14655 if (found && (*functionname_ptr || *line_ptr))
14656 return TRUE;
14657
14658 if (symbols == NULL)
14659 return FALSE;
14660
fb167eb2 14661 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14662 filename_ptr, functionname_ptr))
14663 return FALSE;
14664
14665 *line_ptr = 0;
b34976b6 14666 return TRUE;
252b5132
RH		 14667}
14668
4ab527b0
FF		 14669static bfd_boolean
14670elf32_arm_find_inliner_info (bfd * abfd,
14671 const char ** filename_ptr,
14672 const char ** functionname_ptr,
14673 unsigned int * line_ptr)
14674{
14675 bfd_boolean found;
14676 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
14677 functionname_ptr, line_ptr,
14678 & elf_tdata (abfd)->dwarf2_find_line_info);
14679 return found;
14680}
14681
252b5132
RH		 14682/* Adjust a symbol defined by a dynamic object and referenced by a
14683 regular object. The current definition is in some section of the
14684 dynamic object, but we're not including those sections. We have to
14685 change the definition to something the rest of the link can
14686 understand. */
14687
b34976b6 14688static bfd_boolean
57e8b36a
NC		 14689elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
14690 struct elf_link_hash_entry * h)
252b5132
RH		 14691{
14692 bfd * dynobj;
14693 asection * s;
b7693d02 14694 struct elf32_arm_link_hash_entry * eh;
67687978 14695 struct elf32_arm_link_hash_table *globals;
252b5132 14696
67687978 14697 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14698 if (globals == NULL)
14699 return FALSE;
14700
252b5132
RH		 14701 dynobj = elf_hash_table (info)->dynobj;
14702
14703 /* Make sure we know what is going on here. */
14704 BFD_ASSERT (dynobj != NULL
f5385ebf 14705 && (h->needs_plt
34e77a92 14706 || h->type == STT_GNU_IFUNC
f6e332e6 14707 || h->u.weakdef != NULL
f5385ebf
AM		 14708 || (h->def_dynamic
14709 && h->ref_regular
14710 && !h->def_regular)));
252b5132 14711
b7693d02
DJ		 14712 eh = (struct elf32_arm_link_hash_entry *) h;
14713
252b5132
RH		 14714 /* If this is a function, put it in the procedure linkage table. We
14715 will fill in the contents of the procedure linkage table later,
14716 when we know the address of the .got section. */
34e77a92 14717 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 14718 {
34e77a92
RS		 14719 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
14720 symbol binds locally. */
5e681ec4 14721 if (h->plt.refcount <= 0
34e77a92
RS		 14722 || (h->type != STT_GNU_IFUNC
14723 && (SYMBOL_CALLS_LOCAL (info, h)
14724 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
14725 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 14726 {
14727 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 14728 file, but the symbol was never referred to by a dynamic
14729 object, or if all references were garbage collected. In
14730 such a case, we don't actually need to build a procedure
14731 linkage table, and we can just do a PC24 reloc instead. */
14732 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14733 eh->plt.thumb_refcount = 0;
14734 eh->plt.maybe_thumb_refcount = 0;
14735 eh->plt.noncall_refcount = 0;
f5385ebf 14736 h->needs_plt = 0;
252b5132
RH		 14737 }
14738
b34976b6 14739 return TRUE;
252b5132 14740 }
5e681ec4 14741 else
b7693d02
DJ		 14742 {
14743 /* It's possible that we incorrectly decided a .plt reloc was
14744 needed for an R_ARM_PC24 or similar reloc to a non-function sym
14745 in check_relocs. We can't decide accurately between function
14746 and non-function syms in check-relocs; Objects loaded later in
14747 the link may change h->type. So fix it now. */
14748 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14749 eh->plt.thumb_refcount = 0;
14750 eh->plt.maybe_thumb_refcount = 0;
14751 eh->plt.noncall_refcount = 0;
b7693d02 14752 }
252b5132
RH		 14753
14754 /* If this is a weak symbol, and there is a real definition, the
14755 processor independent code will have arranged for us to see the
14756 real definition first, and we can just use the same value. */
f6e332e6 14757 if (h->u.weakdef != NULL)
252b5132 14758 {
f6e332e6
AM		 14759 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
14760 || h->u.weakdef->root.type == bfd_link_hash_defweak);
14761 h->root.u.def.section = h->u.weakdef->root.u.def.section;
14762 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 14763 return TRUE;
252b5132
RH		 14764 }
14765
ba93b8ac
DJ		 14766 /* If there are no non-GOT references, we do not need a copy
14767 relocation. */
14768 if (!h->non_got_ref)
14769 return TRUE;
14770
252b5132
RH		 14771 /* This is a reference to a symbol defined by a dynamic object which
14772 is not a function. */
14773
14774 /* If we are creating a shared library, we must presume that the
14775 only references to the symbol are via the global offset table.
14776 For such cases we need not do anything here; the relocations will
67687978
PB		 14777 be handled correctly by relocate_section. Relocatable executables
14778 can reference data in shared objects directly, so we don't need to
14779 do anything here. */
0e1862bb 14780 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 14781 return TRUE;
252b5132
RH		 14782
14783 /* We must allocate the symbol in our .dynbss section, which will
14784 become part of the .bss section of the executable. There will be
14785 an entry for this symbol in the .dynsym section. The dynamic
14786 object will contain position independent code, so all references
14787 from the dynamic object to this symbol will go through the global
14788 offset table. The dynamic linker will use the .dynsym entry to
14789 determine the address it must put in the global offset table, so
14790 both the dynamic object and the regular object will refer to the
14791 same memory location for the variable. */
3d4d4302 14792 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 14793 BFD_ASSERT (s != NULL);
14794
5522f910
NC		 14795 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
14796 linker to copy the initial value out of the dynamic object and into
14797 the runtime process image. We need to remember the offset into the
00a97672 14798 .rel(a).bss section we are going to use. */
5522f910
NC		 14799 if (info->nocopyreloc == 0
14800 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 14801 && h->size != 0)
252b5132
RH		 14802 {
14803 asection *srel;
14804
3d4d4302 14805 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 14806 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 14807 h->needs_copy = 1;
252b5132
RH		 14808 }
14809
6cabe1ea 14810 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 14811}
14812
5e681ec4
PB		 14813/* Allocate space in .plt, .got and associated reloc sections for
14814 dynamic relocs. */
14815
14816static bfd_boolean
47beaa6a 14817allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 14818{
14819 struct bfd_link_info *info;
14820 struct elf32_arm_link_hash_table *htab;
14821 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 14822 struct elf_dyn_relocs *p;
5e681ec4
PB		 14823
14824 if (h->root.type == bfd_link_hash_indirect)
14825 return TRUE;
14826
e6a6bb22
AM		 14827 eh = (struct elf32_arm_link_hash_entry *) h;
14828
5e681ec4
PB		 14829 info = (struct bfd_link_info *) inf;
14830 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14831 if (htab == NULL)
14832 return FALSE;
5e681ec4 14833
34e77a92 14834 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 14835 && h->plt.refcount > 0)
14836 {
14837 /* Make sure this symbol is output as a dynamic symbol.
14838 Undefined weak syms won't yet be marked as dynamic. */
14839 if (h->dynindx == -1
f5385ebf 14840 && !h->forced_local)
5e681ec4 14841 {
c152c796 14842 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14843 return FALSE;
14844 }
14845
34e77a92
RS		 14846 /* If the call in the PLT entry binds locally, the associated
14847 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14848 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14849 than the .plt section. */
14850 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
14851 {
14852 eh->is_iplt = 1;
14853 if (eh->plt.noncall_refcount == 0
14854 && SYMBOL_REFERENCES_LOCAL (info, h))
14855 /* All non-call references can be resolved directly.
14856 This means that they can (and in some cases, must)
14857 resolve directly to the run-time target, rather than
14858 to the PLT. That in turns means that any .got entry
14859 would be equal to the .igot.plt entry, so there's
14860 no point having both. */
14861 h->got.refcount = 0;
14862 }
14863
0e1862bb 14864 if (bfd_link_pic (info)
34e77a92 14865 || eh->is_iplt
7359ea65 14866 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 14867 {
34e77a92 14868 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 14869
5e681ec4
PB		 14870 /* If this symbol is not defined in a regular file, and we are
14871 not generating a shared library, then set the symbol to this
14872 location in the .plt. This is required to make function
14873 pointers compare as equal between the normal executable and
14874 the shared library. */
0e1862bb 14875 if (! bfd_link_pic (info)
f5385ebf 14876 && !h->def_regular)
5e681ec4 14877 {
34e77a92 14878 h->root.u.def.section = htab->root.splt;
5e681ec4 14879 h->root.u.def.value = h->plt.offset;
5e681ec4 14880
67d74e43
DJ		 14881 /* Make sure the function is not marked as Thumb, in case
14882 it is the target of an ABS32 relocation, which will
14883 point to the PLT entry. */
39d911fc 14884 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 14885 }
022f8312 14886
00a97672
RS		 14887 /* VxWorks executables have a second set of relocations for
14888 each PLT entry. They go in a separate relocation section,
14889 which is processed by the kernel loader. */
0e1862bb 14890 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 14891 {
14892 /* There is a relocation for the initial PLT entry:
14893 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14894 if (h->plt.offset == htab->plt_header_size)
47beaa6a 14895 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 14896
14897 /* There are two extra relocations for each subsequent
14898 PLT entry: an R_ARM_32 relocation for the GOT entry,
14899 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 14900 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 14901 }
5e681ec4
PB		 14902 }
14903 else
14904 {
14905 h->plt.offset = (bfd_vma) -1;
f5385ebf 14906 h->needs_plt = 0;
5e681ec4
PB		 14907 }
14908 }
14909 else
14910 {
14911 h->plt.offset = (bfd_vma) -1;
f5385ebf 14912 h->needs_plt = 0;
5e681ec4
PB		 14913 }
14914
0855e32b
NS		 14915 eh = (struct elf32_arm_link_hash_entry *) h;
14916 eh->tlsdesc_got = (bfd_vma) -1;
14917
5e681ec4
PB		 14918 if (h->got.refcount > 0)
14919 {
14920 asection *s;
14921 bfd_boolean dyn;
ba93b8ac
DJ		 14922 int tls_type = elf32_arm_hash_entry (h)->tls_type;
14923 int indx;
5e681ec4
PB		 14924
14925 /* Make sure this symbol is output as a dynamic symbol.
14926 Undefined weak syms won't yet be marked as dynamic. */
14927 if (h->dynindx == -1
f5385ebf 14928 && !h->forced_local)
5e681ec4 14929 {
c152c796 14930 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14931 return FALSE;
14932 }
14933
e5a52504
MM		 14934 if (!htab->symbian_p)
14935 {
362d30a1 14936 s = htab->root.sgot;
e5a52504 14937 h->got.offset = s->size;
ba93b8ac
DJ		 14938
14939 if (tls_type == GOT_UNKNOWN)
14940 abort ();
14941
14942 if (tls_type == GOT_NORMAL)
14943 /* Non-TLS symbols need one GOT slot. */
14944 s->size += 4;
14945 else
14946 {
99059e56
RM		 14947 if (tls_type & GOT_TLS_GDESC)
14948 {
0855e32b 14949 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 14950 eh->tlsdesc_got
0855e32b
NS		 14951 = (htab->root.sgotplt->size
14952 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 14953 htab->root.sgotplt->size += 8;
14954 h->got.offset = (bfd_vma) -2;
34e77a92 14955 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14956 reloc in the middle of .got.plt. */
99059e56
RM		 14957 htab->num_tls_desc++;
14958 }
0855e32b 14959
ba93b8ac 14960 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 14961 {
14962 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14963 the symbol is both GD and GDESC, got.offset may
14964 have been overwritten. */
14965 h->got.offset = s->size;
14966 s->size += 8;
14967 }
14968
ba93b8ac
DJ		 14969 if (tls_type & GOT_TLS_IE)
14970 /* R_ARM_TLS_IE32 needs one GOT slot. */
14971 s->size += 4;
14972 }
14973
e5a52504 14974 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 14975
14976 indx = 0;
0e1862bb
L		 14977 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
14978 bfd_link_pic (info),
14979 h)
14980 && (!bfd_link_pic (info)
ba93b8ac
DJ		 14981 || !SYMBOL_REFERENCES_LOCAL (info, h)))
14982 indx = h->dynindx;
14983
14984 if (tls_type != GOT_NORMAL
0e1862bb 14985 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 14986 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14987 || h->root.type != bfd_link_hash_undefweak))
14988 {
14989 if (tls_type & GOT_TLS_IE)
47beaa6a 14990 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14991
14992 if (tls_type & GOT_TLS_GD)
47beaa6a 14993 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14994
b38cadfb 14995 if (tls_type & GOT_TLS_GDESC)
0855e32b 14996 {
47beaa6a 14997 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 14998 /* GDESC needs a trampoline to jump to. */
14999 htab->tls_trampoline = -1;
15000 }
15001
15002 /* Only GD needs it. GDESC just emits one relocation per
15003 2 entries. */
b38cadfb 15004 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15005 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15006 }
6f820c85 15007 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15008 {
15009 if (htab->root.dynamic_sections_created)
15010 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15011 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15012 }
34e77a92
RS		 15013 else if (h->type == STT_GNU_IFUNC
15014 && eh->plt.noncall_refcount == 0)
15015 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15016 they all resolve dynamically instead. Reserve room for the
15017 GOT entry's R_ARM_IRELATIVE relocation. */
15018 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15019 else if (bfd_link_pic (info)
15020 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15021 || h->root.type != bfd_link_hash_undefweak))
b436d854 15022 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15023 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15024 }
5e681ec4
PB		 15025 }
15026 else
15027 h->got.offset = (bfd_vma) -1;
15028
a4fd1a8e
PB		 15029 /* Allocate stubs for exported Thumb functions on v4t. */
15030 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15031 && h->def_regular
39d911fc 15032 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15033 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15034 {
15035 struct elf_link_hash_entry * th;
15036 struct bfd_link_hash_entry * bh;
15037 struct elf_link_hash_entry * myh;
15038 char name[1024];
15039 asection *s;
15040 bh = NULL;
15041 /* Create a new symbol to regist the real location of the function. */
15042 s = h->root.u.def.section;
906e58ca 15043 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15044 _bfd_generic_link_add_one_symbol (info, s->owner,
15045 name, BSF_GLOBAL, s,
15046 h->root.u.def.value,
15047 NULL, TRUE, FALSE, &bh);
15048
15049 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15050 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15051 myh->forced_local = 1;
39d911fc 15052 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15053 eh->export_glue = myh;
15054 th = record_arm_to_thumb_glue (info, h);
15055 /* Point the symbol at the stub. */
15056 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15057 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15058 h->root.u.def.section = th->root.u.def.section;
15059 h->root.u.def.value = th->root.u.def.value & ~1;
15060 }
15061
0bdcacaf 15062 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15063 return TRUE;
15064
15065 /* In the shared -Bsymbolic case, discard space allocated for
15066 dynamic pc-relative relocs against symbols which turn out to be
15067 defined in regular objects. For the normal shared case, discard
15068 space for pc-relative relocs that have become local due to symbol
15069 visibility changes. */
15070
0e1862bb 15071 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15072 {
469a3493
RM		 15073 /* Relocs that use pc_count are PC-relative forms, which will appear
15074 on something like ".long foo - ." or "movw REG, foo - .". We want
15075 calls to protected symbols to resolve directly to the function
15076 rather than going via the plt. If people want function pointer
15077 comparisons to work as expected then they should avoid writing
15078 assembly like ".long foo - .". */
ba93b8ac
DJ		 15079 if (SYMBOL_CALLS_LOCAL (info, h))
15080 {
0bdcacaf 15081 struct elf_dyn_relocs **pp;
ba93b8ac 15082
0bdcacaf 15083 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15084 {
15085 p->count -= p->pc_count;
15086 p->pc_count = 0;
15087 if (p->count == 0)
15088 *pp = p->next;
15089 else
15090 pp = &p->next;
15091 }
15092 }
15093
4dfe6ac6 15094 if (htab->vxworks_p)
3348747a 15095 {
0bdcacaf 15096 struct elf_dyn_relocs **pp;
3348747a 15097
0bdcacaf 15098 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15099 {
0bdcacaf 15100 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15101 *pp = p->next;
15102 else
15103 pp = &p->next;
15104 }
15105 }
15106
ba93b8ac 15107 /* Also discard relocs on undefined weak syms with non-default
99059e56 15108 visibility. */
0bdcacaf 15109 if (eh->dyn_relocs != NULL
5e681ec4 15110 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 15111 {
15112 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 15113 eh->dyn_relocs = NULL;
22d606e9
AM		 15114
15115 /* Make sure undefined weak symbols are output as a dynamic
15116 symbol in PIEs. */
15117 else if (h->dynindx == -1
15118 && !h->forced_local)
15119 {
15120 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15121 return FALSE;
15122 }
15123 }
15124
67687978
PB		 15125 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15126 && h->root.type == bfd_link_hash_new)
15127 {
15128 /* Output absolute symbols so that we can create relocations
15129 against them. For normal symbols we output a relocation
15130 against the section that contains them. */
15131 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15132 return FALSE;
15133 }
15134
5e681ec4
PB		 15135 }
15136 else
15137 {
15138 /* For the non-shared case, discard space for relocs against
15139 symbols which turn out to need copy relocs or are not
15140 dynamic. */
15141
f5385ebf
AM		 15142 if (!h->non_got_ref
15143 && ((h->def_dynamic
15144 && !h->def_regular)
5e681ec4
PB		 15145 || (htab->root.dynamic_sections_created
15146 && (h->root.type == bfd_link_hash_undefweak
15147 || h->root.type == bfd_link_hash_undefined))))
15148 {
15149 /* Make sure this symbol is output as a dynamic symbol.
15150 Undefined weak syms won't yet be marked as dynamic. */
15151 if (h->dynindx == -1
f5385ebf 15152 && !h->forced_local)
5e681ec4 15153 {
c152c796 15154 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15155 return FALSE;
15156 }
15157
15158 /* If that succeeded, we know we'll be keeping all the
15159 relocs. */
15160 if (h->dynindx != -1)
15161 goto keep;
15162 }
15163
0bdcacaf 15164 eh->dyn_relocs = NULL;
5e681ec4
PB		 15165
15166 keep: ;
15167 }
15168
15169 /* Finally, allocate space. */
0bdcacaf 15170 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15171 {
0bdcacaf 15172 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15173 if (h->type == STT_GNU_IFUNC
15174 && eh->plt.noncall_refcount == 0
15175 && SYMBOL_REFERENCES_LOCAL (info, h))
15176 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15177 else
15178 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15179 }
15180
15181 return TRUE;
15182}
15183
08d1f311
DJ		 15184/* Find any dynamic relocs that apply to read-only sections. */
15185
15186static bfd_boolean
8029a119 15187elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15188{
8029a119 15189 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15190 struct elf_dyn_relocs * p;
08d1f311 15191
08d1f311 15192 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15193 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15194 {
0bdcacaf 15195 asection *s = p->sec;
08d1f311
DJ		 15196
15197 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15198 {
15199 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15200
15201 info->flags |= DF_TEXTREL;
15202
15203 /* Not an error, just cut short the traversal. */
15204 return FALSE;
15205 }
15206 }
15207 return TRUE;
15208}
15209
d504ffc8
DJ		 15210void
15211bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15212 int byteswap_code)
15213{
15214 struct elf32_arm_link_hash_table *globals;
15215
15216 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15217 if (globals == NULL)
15218 return;
15219
d504ffc8
DJ		 15220 globals->byteswap_code = byteswap_code;
15221}
15222
252b5132
RH		 15223/* Set the sizes of the dynamic sections. */
15224
b34976b6 15225static bfd_boolean
57e8b36a
NC		 15226elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15227 struct bfd_link_info * info)
252b5132
RH		 15228{
15229 bfd * dynobj;
15230 asection * s;
b34976b6
AM		 15231 bfd_boolean plt;
15232 bfd_boolean relocs;
5e681ec4
PB		 15233 bfd *ibfd;
15234 struct elf32_arm_link_hash_table *htab;
252b5132 15235
5e681ec4 15236 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15237 if (htab == NULL)
15238 return FALSE;
15239
252b5132
RH		 15240 dynobj = elf_hash_table (info)->dynobj;
15241 BFD_ASSERT (dynobj != NULL);
39b41c9c 15242 check_use_blx (htab);
252b5132
RH		 15243
15244 if (elf_hash_table (info)->dynamic_sections_created)
15245 {
15246 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15247 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15248 {
3d4d4302 15249 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15250 BFD_ASSERT (s != NULL);
eea6121a 15251 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15252 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15253 }
15254 }
5e681ec4
PB		 15255
15256 /* Set up .got offsets for local syms, and space for local dynamic
15257 relocs. */
c72f2fb2 15258 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15259 {
5e681ec4
PB		 15260 bfd_signed_vma *local_got;
15261 bfd_signed_vma *end_local_got;
34e77a92 15262 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15263 char *local_tls_type;
0855e32b 15264 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15265 bfd_size_type locsymcount;
15266 Elf_Internal_Shdr *symtab_hdr;
15267 asection *srel;
4dfe6ac6 15268 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15269 unsigned int symndx;
5e681ec4 15270
0ffa91dd 15271 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15272 continue;
15273
15274 for (s = ibfd->sections; s != NULL; s = s->next)
15275 {
0bdcacaf 15276 struct elf_dyn_relocs *p;
5e681ec4 15277
0bdcacaf 15278 for (p = (struct elf_dyn_relocs *)
99059e56 15279 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15280 {
0bdcacaf
RS		 15281 if (!bfd_is_abs_section (p->sec)
15282 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15283 {
15284 /* Input section has been discarded, either because
15285 it is a copy of a linkonce section or due to
15286 linker script /DISCARD/, so we'll be discarding
15287 the relocs too. */
15288 }
3348747a 15289 else if (is_vxworks
0bdcacaf 15290 && strcmp (p->sec->output_section->name,
3348747a
NS		 15291 ".tls_vars") == 0)
15292 {
15293 /* Relocations in vxworks .tls_vars sections are
15294 handled specially by the loader. */
15295 }
5e681ec4
PB		 15296 else if (p->count != 0)
15297 {
0bdcacaf 15298 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15299 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15300 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15301 info->flags |= DF_TEXTREL;
15302 }
15303 }
15304 }
15305
15306 local_got = elf_local_got_refcounts (ibfd);
15307 if (!local_got)
15308 continue;
15309
0ffa91dd 15310 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15311 locsymcount = symtab_hdr->sh_info;
15312 end_local_got = local_got + locsymcount;
34e77a92 15313 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15314 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15315 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15316 symndx = 0;
362d30a1
RS		 15317 s = htab->root.sgot;
15318 srel = htab->root.srelgot;
0855e32b 15319 for (; local_got < end_local_got;
34e77a92
RS		 15320 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15321 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15322 {
0855e32b 15323 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15324 local_iplt = *local_iplt_ptr;
15325 if (local_iplt != NULL)
15326 {
15327 struct elf_dyn_relocs *p;
15328
15329 if (local_iplt->root.refcount > 0)
15330 {
15331 elf32_arm_allocate_plt_entry (info, TRUE,
15332 &local_iplt->root,
15333 &local_iplt->arm);
15334 if (local_iplt->arm.noncall_refcount == 0)
15335 /* All references to the PLT are calls, so all
15336 non-call references can resolve directly to the
15337 run-time target. This means that the .got entry
15338 would be the same as the .igot.plt entry, so there's
15339 no point creating both. */
15340 *local_got = 0;
15341 }
15342 else
15343 {
15344 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15345 local_iplt->root.offset = (bfd_vma) -1;
15346 }
15347
15348 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15349 {
15350 asection *psrel;
15351
15352 psrel = elf_section_data (p->sec)->sreloc;
15353 if (local_iplt->arm.noncall_refcount == 0)
15354 elf32_arm_allocate_irelocs (info, psrel, p->count);
15355 else
15356 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15357 }
15358 }
5e681ec4
PB		 15359 if (*local_got > 0)
15360 {
34e77a92
RS		 15361 Elf_Internal_Sym *isym;
15362
eea6121a 15363 *local_got = s->size;
ba93b8ac
DJ		 15364 if (*local_tls_type & GOT_TLS_GD)
15365 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15366 s->size += 8;
0855e32b
NS		 15367 if (*local_tls_type & GOT_TLS_GDESC)
15368 {
15369 *local_tlsdesc_gotent = htab->root.sgotplt->size
15370 - elf32_arm_compute_jump_table_size (htab);
15371 htab->root.sgotplt->size += 8;
15372 *local_got = (bfd_vma) -2;
34e77a92 15373 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15374 reloc in the middle of .got.plt. */
99059e56 15375 htab->num_tls_desc++;
0855e32b 15376 }
ba93b8ac
DJ		 15377 if (*local_tls_type & GOT_TLS_IE)
15378 s->size += 4;
ba93b8ac 15379
0855e32b
NS		 15380 if (*local_tls_type & GOT_NORMAL)
15381 {
15382 /* If the symbol is both GD and GDESC, *local_got
15383 may have been overwritten. */
15384 *local_got = s->size;
15385 s->size += 4;
15386 }
15387
34e77a92
RS		 15388 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15389 if (isym == NULL)
15390 return FALSE;
15391
15392 /* If all references to an STT_GNU_IFUNC PLT are calls,
15393 then all non-call references, including this GOT entry,
15394 resolve directly to the run-time target. */
15395 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15396 && (local_iplt == NULL
15397 || local_iplt->arm.noncall_refcount == 0))
15398 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15399 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15400 {
0e1862bb 15401 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15402 || *local_tls_type & GOT_TLS_GD)
15403 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15404
0e1862bb 15405 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15406 {
15407 elf32_arm_allocate_dynrelocs (info,
15408 htab->root.srelplt, 1);
15409 htab->tls_trampoline = -1;
15410 }
0855e32b 15411 }
5e681ec4
PB		 15412 }
15413 else
15414 *local_got = (bfd_vma) -1;
15415 }
252b5132
RH		 15416 }
15417
ba93b8ac
DJ		 15418 if (htab->tls_ldm_got.refcount > 0)
15419 {
15420 /* Allocate two GOT entries and one dynamic relocation (if necessary)
15421 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 15422 htab->tls_ldm_got.offset = htab->root.sgot->size;
15423 htab->root.sgot->size += 8;
0e1862bb 15424 if (bfd_link_pic (info))
47beaa6a 15425 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15426 }
15427 else
15428 htab->tls_ldm_got.offset = -1;
15429
5e681ec4
PB		 15430 /* Allocate global sym .plt and .got entries, and space for global
15431 sym dynamic relocs. */
47beaa6a 15432 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 15433
d504ffc8 15434 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 15435 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 15436 {
0ffa91dd 15437 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 15438 continue;
15439
c7b8f16e
JB		 15440 /* Initialise mapping tables for code/data. */
15441 bfd_elf32_arm_init_maps (ibfd);
906e58ca 15442
c7b8f16e 15443 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 15444 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
15445 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 15446 /* xgettext:c-format */
15447 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 15448 ibfd->filename);
15449 }
d504ffc8 15450
3e6b1042
DJ		 15451 /* Allocate space for the glue sections now that we've sized them. */
15452 bfd_elf32_arm_allocate_interworking_sections (info);
15453
0855e32b
NS		 15454 /* For every jump slot reserved in the sgotplt, reloc_count is
15455 incremented. However, when we reserve space for TLS descriptors,
15456 it's not incremented, so in order to compute the space reserved
15457 for them, it suffices to multiply the reloc count by the jump
15458 slot size. */
15459 if (htab->root.srelplt)
15460 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
15461
15462 if (htab->tls_trampoline)
15463 {
15464 if (htab->root.splt->size == 0)
15465 htab->root.splt->size += htab->plt_header_size;
b38cadfb 15466
0855e32b
NS		 15467 htab->tls_trampoline = htab->root.splt->size;
15468 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 15469
0855e32b 15470 /* If we're not using lazy TLS relocations, don't generate the
99059e56 15471 PLT and GOT entries they require. */
0855e32b
NS		 15472 if (!(info->flags & DF_BIND_NOW))
15473 {
15474 htab->dt_tlsdesc_got = htab->root.sgot->size;
15475 htab->root.sgot->size += 4;
15476
15477 htab->dt_tlsdesc_plt = htab->root.splt->size;
15478 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
15479 }
15480 }
15481
252b5132
RH		 15482 /* The check_relocs and adjust_dynamic_symbol entry points have
15483 determined the sizes of the various dynamic sections. Allocate
15484 memory for them. */
b34976b6
AM		 15485 plt = FALSE;
15486 relocs = FALSE;
252b5132
RH		 15487 for (s = dynobj->sections; s != NULL; s = s->next)
15488 {
15489 const char * name;
252b5132
RH		 15490
15491 if ((s->flags & SEC_LINKER_CREATED) == 0)
15492 continue;
15493
15494 /* It's OK to base decisions on the section name, because none
15495 of the dynobj section names depend upon the input files. */
15496 name = bfd_get_section_name (dynobj, s);
15497
34e77a92 15498 if (s == htab->root.splt)
252b5132 15499 {
c456f082
AM		 15500 /* Remember whether there is a PLT. */
15501 plt = s->size != 0;
252b5132 15502 }
0112cd26 15503 else if (CONST_STRNEQ (name, ".rel"))
252b5132 15504 {
c456f082 15505 if (s->size != 0)
252b5132 15506 {
252b5132 15507 /* Remember whether there are any reloc sections other
00a97672 15508 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 15509 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 15510 relocs = TRUE;
252b5132
RH		 15511
15512 /* We use the reloc_count field as a counter if we need
15513 to copy relocs into the output file. */
15514 s->reloc_count = 0;
15515 }
15516 }
34e77a92
RS		 15517 else if (s != htab->root.sgot
15518 && s != htab->root.sgotplt
15519 && s != htab->root.iplt
15520 && s != htab->root.igotplt
15521 && s != htab->sdynbss)
252b5132
RH		 15522 {
15523 /* It's not one of our sections, so don't allocate space. */
15524 continue;
15525 }
15526
c456f082 15527 if (s->size == 0)
252b5132 15528 {
c456f082 15529 /* If we don't need this section, strip it from the
00a97672
RS		 15530 output file. This is mostly to handle .rel(a).bss and
15531 .rel(a).plt. We must create both sections in
c456f082
AM		 15532 create_dynamic_sections, because they must be created
15533 before the linker maps input sections to output
15534 sections. The linker does that before
15535 adjust_dynamic_symbol is called, and it is that
15536 function which decides whether anything needs to go
15537 into these sections. */
8423293d 15538 s->flags |= SEC_EXCLUDE;
252b5132
RH		 15539 continue;
15540 }
15541
c456f082
AM		 15542 if ((s->flags & SEC_HAS_CONTENTS) == 0)
15543 continue;
15544
252b5132 15545 /* Allocate memory for the section contents. */
21d799b5 15546 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 15547 if (s->contents == NULL)
b34976b6 15548 return FALSE;
252b5132
RH		 15549 }
15550
15551 if (elf_hash_table (info)->dynamic_sections_created)
15552 {
15553 /* Add some entries to the .dynamic section. We fill in the
15554 values later, in elf32_arm_finish_dynamic_sections, but we
15555 must add the entries now so that we get the correct size for
15556 the .dynamic section. The DT_DEBUG entry is filled in by the
15557 dynamic linker and used by the debugger. */
dc810e39 15558#define add_dynamic_entry(TAG, VAL) \
5a580b3a 15559 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 15560
0e1862bb 15561 if (bfd_link_executable (info))
252b5132 15562 {
dc810e39 15563 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 15564 return FALSE;
252b5132
RH		 15565 }
15566
15567 if (plt)
15568 {
dc810e39
AM		 15569 if ( !add_dynamic_entry (DT_PLTGOT, 0)
15570 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 15571 || !add_dynamic_entry (DT_PLTREL,
15572 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 15573 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 15574 return FALSE;
0855e32b
NS		 15575
15576 if (htab->dt_tlsdesc_plt &&
b38cadfb 15577 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 15578 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 15579 return FALSE;
252b5132
RH		 15580 }
15581
15582 if (relocs)
15583 {
00a97672
RS		 15584 if (htab->use_rel)
15585 {
15586 if (!add_dynamic_entry (DT_REL, 0)
15587 || !add_dynamic_entry (DT_RELSZ, 0)
15588 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
15589 return FALSE;
15590 }
15591 else
15592 {
15593 if (!add_dynamic_entry (DT_RELA, 0)
15594 || !add_dynamic_entry (DT_RELASZ, 0)
15595 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
15596 return FALSE;
15597 }
252b5132
RH		 15598 }
15599
08d1f311
DJ		 15600 /* If any dynamic relocs apply to a read-only section,
15601 then we need a DT_TEXTREL entry. */
15602 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 15603 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
15604 info);
08d1f311 15605
99e4ae17 15606 if ((info->flags & DF_TEXTREL) != 0)
252b5132 15607 {
dc810e39 15608 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 15609 return FALSE;
252b5132 15610 }
7a2b07ff
NS		 15611 if (htab->vxworks_p
15612 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
15613 return FALSE;
252b5132 15614 }
8532796c 15615#undef add_dynamic_entry
252b5132 15616
b34976b6 15617 return TRUE;
252b5132
RH		 15618}
15619
0855e32b
NS		 15620/* Size sections even though they're not dynamic. We use it to setup
15621 _TLS_MODULE_BASE_, if needed. */
15622
15623static bfd_boolean
15624elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 15625 struct bfd_link_info *info)
0855e32b
NS		 15626{
15627 asection *tls_sec;
15628
0e1862bb 15629 if (bfd_link_relocatable (info))
0855e32b
NS		 15630 return TRUE;
15631
15632 tls_sec = elf_hash_table (info)->tls_sec;
15633
15634 if (tls_sec)
15635 {
15636 struct elf_link_hash_entry *tlsbase;
15637
15638 tlsbase = elf_link_hash_lookup
15639 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
15640
15641 if (tlsbase)
99059e56
RM		 15642 {
15643 struct bfd_link_hash_entry *bh = NULL;
0855e32b 15644 const struct elf_backend_data *bed
99059e56 15645 = get_elf_backend_data (output_bfd);
0855e32b 15646
99059e56 15647 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 15648 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
15649 tls_sec, 0, NULL, FALSE,
15650 bed->collect, &bh)))
15651 return FALSE;
b38cadfb 15652
99059e56
RM		 15653 tlsbase->type = STT_TLS;
15654 tlsbase = (struct elf_link_hash_entry *)bh;
15655 tlsbase->def_regular = 1;
15656 tlsbase->other = STV_HIDDEN;
15657 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 15658 }
15659 }
15660 return TRUE;
15661}
15662
252b5132
RH		 15663/* Finish up dynamic symbol handling. We set the contents of various
15664 dynamic sections here. */
15665
b34976b6 15666static bfd_boolean
906e58ca
NC		 15667elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
15668 struct bfd_link_info * info,
15669 struct elf_link_hash_entry * h,
15670 Elf_Internal_Sym * sym)
252b5132 15671{
e5a52504 15672 struct elf32_arm_link_hash_table *htab;
b7693d02 15673 struct elf32_arm_link_hash_entry *eh;
252b5132 15674
e5a52504 15675 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15676 if (htab == NULL)
15677 return FALSE;
15678
b7693d02 15679 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 15680
15681 if (h->plt.offset != (bfd_vma) -1)
15682 {
34e77a92 15683 if (!eh->is_iplt)
e5a52504 15684 {
34e77a92 15685 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 15686 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
15687 h->dynindx, 0))
15688 return FALSE;
e5a52504 15689 }
57e8b36a 15690
f5385ebf 15691 if (!h->def_regular)
252b5132
RH		 15692 {
15693 /* Mark the symbol as undefined, rather than as defined in
3a635617 15694 the .plt section. */
252b5132 15695 sym->st_shndx = SHN_UNDEF;
3a635617 15696 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 15697 Otherwise, the PLT entry would provide a definition for
15698 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 15699 and so the symbol would never be NULL. Leave the value if
15700 there were any relocations where pointer equality matters
15701 (this is a clue for the dynamic linker, to make function
15702 pointer comparisons work between an application and shared
15703 library). */
97323ad1 15704 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 15705 sym->st_value = 0;
252b5132 15706 }
34e77a92
RS		 15707 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
15708 {
15709 /* At least one non-call relocation references this .iplt entry,
15710 so the .iplt entry is the function's canonical address. */
15711 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 15712 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 15713 sym->st_shndx = (_bfd_elf_section_from_bfd_section
15714 (output_bfd, htab->root.iplt->output_section));
15715 sym->st_value = (h->plt.offset
15716 + htab->root.iplt->output_section->vma
15717 + htab->root.iplt->output_offset);
15718 }
252b5132
RH		 15719 }
15720
f5385ebf 15721 if (h->needs_copy)
252b5132
RH		 15722 {
15723 asection * s;
947216bf 15724 Elf_Internal_Rela rel;
252b5132
RH		 15725
15726 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 15727 BFD_ASSERT (h->dynindx != -1
15728 && (h->root.type == bfd_link_hash_defined
15729 || h->root.type == bfd_link_hash_defweak));
15730
362d30a1 15731 s = htab->srelbss;
252b5132
RH		 15732 BFD_ASSERT (s != NULL);
15733
00a97672 15734 rel.r_addend = 0;
252b5132
RH		 15735 rel.r_offset = (h->root.u.def.value
15736 + h->root.u.def.section->output_section->vma
15737 + h->root.u.def.section->output_offset);
15738 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 15739 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 15740 }
15741
00a97672
RS		 15742 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
15743 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
15744 to the ".got" section. */
9637f6ef 15745 if (h == htab->root.hdynamic
00a97672 15746 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 15747 sym->st_shndx = SHN_ABS;
15748
b34976b6 15749 return TRUE;
252b5132
RH		 15750}
15751
0855e32b
NS		 15752static void
15753arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15754 void *contents,
15755 const unsigned long *template, unsigned count)
15756{
15757 unsigned ix;
b38cadfb 15758
0855e32b
NS		 15759 for (ix = 0; ix != count; ix++)
15760 {
15761 unsigned long insn = template[ix];
15762
15763 /* Emit mov pc,rx if bx is not permitted. */
15764 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
15765 insn = (insn & 0xf000000f) | 0x01a0f000;
15766 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
15767 }
15768}
15769
99059e56
RM		 15770/* Install the special first PLT entry for elf32-arm-nacl. Unlike
15771 other variants, NaCl needs this entry in a static executable's
15772 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
15773 zero. For .iplt really only the last bundle is useful, and .iplt
15774 could have a shorter first entry, with each individual PLT entry's
15775 relative branch calculated differently so it targets the last
15776 bundle instead of the instruction before it (labelled .Lplt_tail
15777 above). But it's simpler to keep the size and layout of PLT0
15778 consistent with the dynamic case, at the cost of some dead code at
15779 the start of .iplt and the one dead store to the stack at the start
15780 of .Lplt_tail. */
15781static void
15782arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15783 asection *plt, bfd_vma got_displacement)
15784{
15785 unsigned int i;
15786
15787 put_arm_insn (htab, output_bfd,
15788 elf32_arm_nacl_plt0_entry[0]
15789 | arm_movw_immediate (got_displacement),
15790 plt->contents + 0);
15791 put_arm_insn (htab, output_bfd,
15792 elf32_arm_nacl_plt0_entry[1]
15793 | arm_movt_immediate (got_displacement),
15794 plt->contents + 4);
15795
15796 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
15797 put_arm_insn (htab, output_bfd,
15798 elf32_arm_nacl_plt0_entry[i],
15799 plt->contents + (i * 4));
15800}
15801
252b5132
RH		 15802/* Finish up the dynamic sections. */
15803
b34976b6 15804static bfd_boolean
57e8b36a 15805elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 15806{
15807 bfd * dynobj;
15808 asection * sgot;
15809 asection * sdyn;
4dfe6ac6
NC		 15810 struct elf32_arm_link_hash_table *htab;
15811
15812 htab = elf32_arm_hash_table (info);
15813 if (htab == NULL)
15814 return FALSE;
252b5132
RH		 15815
15816 dynobj = elf_hash_table (info)->dynobj;
15817
362d30a1 15818 sgot = htab->root.sgotplt;
894891db
NC		 15819 /* A broken linker script might have discarded the dynamic sections.
15820 Catch this here so that we do not seg-fault later on. */
15821 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
15822 return FALSE;
3d4d4302 15823 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 15824
15825 if (elf_hash_table (info)->dynamic_sections_created)
15826 {
15827 asection *splt;
15828 Elf32_External_Dyn *dyncon, *dynconend;
15829
362d30a1 15830 splt = htab->root.splt;
24a1ba0f 15831 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 15832 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 15833
15834 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 15835 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 15836
252b5132
RH		 15837 for (; dyncon < dynconend; dyncon++)
15838 {
15839 Elf_Internal_Dyn dyn;
15840 const char * name;
15841 asection * s;
15842
15843 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
15844
15845 switch (dyn.d_tag)
15846 {
229fcec5
MM		 15847 unsigned int type;
15848
252b5132 15849 default:
7a2b07ff
NS		 15850 if (htab->vxworks_p
15851 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
15852 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 15853 break;
15854
229fcec5
MM		 15855 case DT_HASH:
15856 name = ".hash";
15857 goto get_vma_if_bpabi;
15858 case DT_STRTAB:
15859 name = ".dynstr";
15860 goto get_vma_if_bpabi;
15861 case DT_SYMTAB:
15862 name = ".dynsym";
15863 goto get_vma_if_bpabi;
c0042f5d
MM		 15864 case DT_VERSYM:
15865 name = ".gnu.version";
15866 goto get_vma_if_bpabi;
15867 case DT_VERDEF:
15868 name = ".gnu.version_d";
15869 goto get_vma_if_bpabi;
15870 case DT_VERNEED:
15871 name = ".gnu.version_r";
15872 goto get_vma_if_bpabi;
15873
252b5132 15874 case DT_PLTGOT:
4ade44b7 15875 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 15876 goto get_vma;
15877 case DT_JMPREL:
00a97672 15878 name = RELOC_SECTION (htab, ".plt");
252b5132 15879 get_vma:
4ade44b7 15880 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 15881 if (s == NULL)
15882 {
05456594 15883 (*_bfd_error_handler)
4ade44b7 15884 (_("could not find section %s"), name);
05456594
NC		 15885 bfd_set_error (bfd_error_invalid_operation);
15886 return FALSE;
15887 }
229fcec5 15888 if (!htab->symbian_p)
4ade44b7 15889 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 15890 else
15891 /* In the BPABI, tags in the PT_DYNAMIC section point
15892 at the file offset, not the memory address, for the
15893 convenience of the post linker. */
4ade44b7 15894 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 15895 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15896 break;
15897
229fcec5
MM		 15898 get_vma_if_bpabi:
15899 if (htab->symbian_p)
15900 goto get_vma;
15901 break;
15902
252b5132 15903 case DT_PLTRELSZ:
362d30a1 15904 s = htab->root.srelplt;
252b5132 15905 BFD_ASSERT (s != NULL);
eea6121a 15906 dyn.d_un.d_val = s->size;
252b5132
RH		 15907 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15908 break;
906e58ca 15909
252b5132 15910 case DT_RELSZ:
00a97672 15911 case DT_RELASZ:
229fcec5
MM		 15912 if (!htab->symbian_p)
15913 {
15914 /* My reading of the SVR4 ABI indicates that the
15915 procedure linkage table relocs (DT_JMPREL) should be
15916 included in the overall relocs (DT_REL). This is
15917 what Solaris does. However, UnixWare can not handle
15918 that case. Therefore, we override the DT_RELSZ entry
15919 here to make it not include the JMPREL relocs. Since
00a97672 15920 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 15921 other relocation sections, we don't have to worry
15922 about changing the DT_REL entry. */
362d30a1 15923 s = htab->root.srelplt;
229fcec5
MM		 15924 if (s != NULL)
15925 dyn.d_un.d_val -= s->size;
15926 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15927 break;
15928 }
8029a119 15929 /* Fall through. */
229fcec5
MM		 15930
15931 case DT_REL:
15932 case DT_RELA:
229fcec5
MM		 15933 /* In the BPABI, the DT_REL tag must point at the file
15934 offset, not the VMA, of the first relocation
15935 section. So, we use code similar to that in
15936 elflink.c, but do not check for SHF_ALLOC on the
15937 relcoation section, since relocations sections are
15938 never allocated under the BPABI. The comments above
15939 about Unixware notwithstanding, we include all of the
15940 relocations here. */
15941 if (htab->symbian_p)
15942 {
15943 unsigned int i;
15944 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
15945 ? SHT_REL : SHT_RELA);
15946 dyn.d_un.d_val = 0;
15947 for (i = 1; i < elf_numsections (output_bfd); i++)
15948 {
906e58ca 15949 Elf_Internal_Shdr *hdr
229fcec5
MM		 15950 = elf_elfsections (output_bfd)[i];
15951 if (hdr->sh_type == type)
15952 {
906e58ca 15953 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 15954 || dyn.d_tag == DT_RELASZ)
15955 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 15956 else if ((ufile_ptr) hdr->sh_offset
15957 <= dyn.d_un.d_val - 1)
229fcec5
MM		 15958 dyn.d_un.d_val = hdr->sh_offset;
15959 }
15960 }
15961 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15962 }
252b5132 15963 break;
88f7bcd5 15964
0855e32b 15965 case DT_TLSDESC_PLT:
99059e56 15966 s = htab->root.splt;
0855e32b
NS		 15967 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
15968 + htab->dt_tlsdesc_plt);
15969 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15970 break;
15971
15972 case DT_TLSDESC_GOT:
99059e56 15973 s = htab->root.sgot;
0855e32b 15974 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 15975 + htab->dt_tlsdesc_got);
0855e32b
NS		 15976 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15977 break;
15978
88f7bcd5
NC		 15979 /* Set the bottom bit of DT_INIT/FINI if the
15980 corresponding function is Thumb. */
15981 case DT_INIT:
15982 name = info->init_function;
15983 goto get_sym;
15984 case DT_FINI:
15985 name = info->fini_function;
15986 get_sym:
15987 /* If it wasn't set by elf_bfd_final_link
4cc11e76 15988 then there is nothing to adjust. */
88f7bcd5
NC		 15989 if (dyn.d_un.d_val != 0)
15990 {
15991 struct elf_link_hash_entry * eh;
15992
15993 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 15994 FALSE, FALSE, TRUE);
39d911fc
TP		 15995 if (eh != NULL
15996 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
15997 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 15998 {
15999 dyn.d_un.d_val |= 1;
b34976b6 16000 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16001 }
16002 }
16003 break;
252b5132
RH		 16004 }
16005 }
16006
24a1ba0f 16007 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16008 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16009 {
00a97672
RS		 16010 const bfd_vma *plt0_entry;
16011 bfd_vma got_address, plt_address, got_displacement;
16012
16013 /* Calculate the addresses of the GOT and PLT. */
16014 got_address = sgot->output_section->vma + sgot->output_offset;
16015 plt_address = splt->output_section->vma + splt->output_offset;
16016
16017 if (htab->vxworks_p)
16018 {
16019 /* The VxWorks GOT is relocated by the dynamic linker.
16020 Therefore, we must emit relocations rather than simply
16021 computing the values now. */
16022 Elf_Internal_Rela rel;
16023
16024 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16025 put_arm_insn (htab, output_bfd, plt0_entry[0],
16026 splt->contents + 0);
16027 put_arm_insn (htab, output_bfd, plt0_entry[1],
16028 splt->contents + 4);
16029 put_arm_insn (htab, output_bfd, plt0_entry[2],
16030 splt->contents + 8);
00a97672
RS		 16031 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16032
8029a119 16033 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16034 rel.r_offset = plt_address + 12;
16035 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16036 rel.r_addend = 0;
16037 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16038 htab->srelplt2->contents);
16039 }
b38cadfb 16040 else if (htab->nacl_p)
99059e56
RM		 16041 arm_nacl_put_plt0 (htab, output_bfd, splt,
16042 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16043 else if (using_thumb_only (htab))
16044 {
16045 got_displacement = got_address - (plt_address + 12);
16046
16047 plt0_entry = elf32_thumb2_plt0_entry;
16048 put_arm_insn (htab, output_bfd, plt0_entry[0],
16049 splt->contents + 0);
16050 put_arm_insn (htab, output_bfd, plt0_entry[1],
16051 splt->contents + 4);
16052 put_arm_insn (htab, output_bfd, plt0_entry[2],
16053 splt->contents + 8);
16054
16055 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16056 }
00a97672
RS		 16057 else
16058 {
16059 got_displacement = got_address - (plt_address + 16);
16060
16061 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16062 put_arm_insn (htab, output_bfd, plt0_entry[0],
16063 splt->contents + 0);
16064 put_arm_insn (htab, output_bfd, plt0_entry[1],
16065 splt->contents + 4);
16066 put_arm_insn (htab, output_bfd, plt0_entry[2],
16067 splt->contents + 8);
16068 put_arm_insn (htab, output_bfd, plt0_entry[3],
16069 splt->contents + 12);
5e681ec4 16070
5e681ec4 16071#ifdef FOUR_WORD_PLT
00a97672
RS		 16072 /* The displacement value goes in the otherwise-unused
16073 last word of the second entry. */
16074 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16075#else
00a97672 16076 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16077#endif
00a97672 16078 }
f7a74f8c 16079 }
252b5132
RH		 16080
16081 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16082 really seem like the right value. */
74541ad4
AM		 16083 if (splt->output_section->owner == output_bfd)
16084 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16085
0855e32b
NS		 16086 if (htab->dt_tlsdesc_plt)
16087 {
16088 bfd_vma got_address
16089 = sgot->output_section->vma + sgot->output_offset;
16090 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16091 + htab->root.sgot->output_offset);
16092 bfd_vma plt_address
16093 = splt->output_section->vma + splt->output_offset;
16094
b38cadfb 16095 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16096 splt->contents + htab->dt_tlsdesc_plt,
16097 dl_tlsdesc_lazy_trampoline, 6);
16098
16099 bfd_put_32 (output_bfd,
16100 gotplt_address + htab->dt_tlsdesc_got
16101 - (plt_address + htab->dt_tlsdesc_plt)
16102 - dl_tlsdesc_lazy_trampoline[6],
16103 splt->contents + htab->dt_tlsdesc_plt + 24);
16104 bfd_put_32 (output_bfd,
16105 got_address - (plt_address + htab->dt_tlsdesc_plt)
16106 - dl_tlsdesc_lazy_trampoline[7],
16107 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16108 }
16109
16110 if (htab->tls_trampoline)
16111 {
b38cadfb 16112 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16113 splt->contents + htab->tls_trampoline,
16114 tls_trampoline, 3);
16115#ifdef FOUR_WORD_PLT
16116 bfd_put_32 (output_bfd, 0x00000000,
16117 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16118#endif
0855e32b
NS		 16119 }
16120
0e1862bb
L		 16121 if (htab->vxworks_p
16122 && !bfd_link_pic (info)
16123 && htab->root.splt->size > 0)
00a97672
RS		 16124 {
16125 /* Correct the .rel(a).plt.unloaded relocations. They will have
16126 incorrect symbol indexes. */
16127 int num_plts;
eed62c48 16128 unsigned char *p;
00a97672 16129
362d30a1 16130 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16131 / htab->plt_entry_size);
16132 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16133
16134 for (; num_plts; num_plts--)
16135 {
16136 Elf_Internal_Rela rel;
16137
16138 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16139 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16140 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16141 p += RELOC_SIZE (htab);
16142
16143 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16144 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16145 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16146 p += RELOC_SIZE (htab);
16147 }
16148 }
252b5132
RH		 16149 }
16150
99059e56
RM		 16151 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16152 /* NaCl uses a special first entry in .iplt too. */
16153 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16154
252b5132 16155 /* Fill in the first three entries in the global offset table. */
229fcec5 16156 if (sgot)
252b5132 16157 {
229fcec5
MM		 16158 if (sgot->size > 0)
16159 {
16160 if (sdyn == NULL)
16161 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16162 else
16163 bfd_put_32 (output_bfd,
16164 sdyn->output_section->vma + sdyn->output_offset,
16165 sgot->contents);
16166 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16167 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16168 }
252b5132 16169
229fcec5
MM		 16170 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16171 }
252b5132 16172
b34976b6 16173 return TRUE;
252b5132
RH		 16174}
16175
ba96a88f 16176static void
57e8b36a 16177elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16178{
9b485d32 16179 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16180 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16181 struct elf_segment_map *m;
ba96a88f
NC		 16182
16183 i_ehdrp = elf_elfheader (abfd);
16184
94a3258f
PB		 16185 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16186 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16187 else
7394f108 16188 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16189 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16190
93204d3a
PB		 16191 if (link_info)
16192 {
16193 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16194 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16195 i_ehdrp->e_flags |= EF_ARM_BE8;
16196 }
3bfcb652
NC		 16197
16198 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16199 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16200 {
16201 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16202 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16203 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16204 else
16205 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16206 }
ac4c9b04
MG		 16207
16208 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16209 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16210 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16211 {
16212 unsigned int j;
16213
16214 if (m->count == 0)
16215 continue;
16216 for (j = 0; j < m->count; j++)
16217 {
f0728ee3 16218 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16219 break;
16220 }
16221 if (j == m->count)
16222 {
16223 m->p_flags = PF_X;
16224 m->p_flags_valid = 1;
16225 }
16226 }
ba96a88f
NC		 16227}
16228
99e4ae17 16229static enum elf_reloc_type_class
7e612e98
AM		 16230elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16231 const asection *rel_sec ATTRIBUTE_UNUSED,
16232 const Elf_Internal_Rela *rela)
99e4ae17 16233{
f51e552e 16234 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16235 {
16236 case R_ARM_RELATIVE:
16237 return reloc_class_relative;
16238 case R_ARM_JUMP_SLOT:
16239 return reloc_class_plt;
16240 case R_ARM_COPY:
16241 return reloc_class_copy;
109575d7
JW		 16242 case R_ARM_IRELATIVE:
16243 return reloc_class_ifunc;
99e4ae17
AJ		 16244 default:
16245 return reloc_class_normal;
16246 }
16247}
16248
e489d0ae 16249static void
57e8b36a 16250elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16251{
5a6c6817 16252 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16253}
16254
40a18ebd
NC		 16255/* Return TRUE if this is an unwinding table entry. */
16256
16257static bfd_boolean
16258is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16259{
0112cd26
NC		 16260 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16261 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16262}
16263
16264
16265/* Set the type and flags for an ARM section. We do this by
16266 the section name, which is a hack, but ought to work. */
16267
16268static bfd_boolean
16269elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16270{
16271 const char * name;
16272
16273 name = bfd_get_section_name (abfd, sec);
16274
16275 if (is_arm_elf_unwind_section_name (abfd, name))
16276 {
16277 hdr->sh_type = SHT_ARM_EXIDX;
16278 hdr->sh_flags |= SHF_LINK_ORDER;
16279 }
ac4c9b04 16280
f0728ee3
AV		 16281 if (sec->flags & SEC_ELF_PURECODE)
16282 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16283
40a18ebd
NC		 16284 return TRUE;
16285}
16286
6dc132d9
L		 16287/* Handle an ARM specific section when reading an object file. This is
16288 called when bfd_section_from_shdr finds a section with an unknown
16289 type. */
40a18ebd
NC		 16290
16291static bfd_boolean
16292elf32_arm_section_from_shdr (bfd *abfd,
16293 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16294 const char *name,
16295 int shindex)
40a18ebd
NC		 16296{
16297 /* There ought to be a place to keep ELF backend specific flags, but
16298 at the moment there isn't one. We just keep track of the
16299 sections by their name, instead. Fortunately, the ABI gives
16300 names for all the ARM specific sections, so we will probably get
16301 away with this. */
16302 switch (hdr->sh_type)
16303 {
16304 case SHT_ARM_EXIDX:
0951f019
RE		 16305 case SHT_ARM_PREEMPTMAP:
16306 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16307 break;
16308
16309 default:
16310 return FALSE;
16311 }
16312
6dc132d9 16313 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16314 return FALSE;
16315
16316 return TRUE;
16317}
e489d0ae 16318
44444f50
NC		 16319static _arm_elf_section_data *
16320get_arm_elf_section_data (asection * sec)
16321{
47b2e99c
JZ		 16322 if (sec && sec->owner && is_arm_elf (sec->owner))
16323 return elf32_arm_section_data (sec);
44444f50
NC		 16324 else
16325 return NULL;
8e3de13a
NC		 16326}
16327
4e617b1e
PB		 16328typedef struct
16329{
57402f1e 16330 void *flaginfo;
4e617b1e 16331 struct bfd_link_info *info;
91a5743d
PB		 16332 asection *sec;
16333 int sec_shndx;
6e0b88f1
AM		 16334 int (*func) (void *, const char *, Elf_Internal_Sym *,
16335 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16336} output_arch_syminfo;
16337
16338enum map_symbol_type
16339{
16340 ARM_MAP_ARM,
16341 ARM_MAP_THUMB,
16342 ARM_MAP_DATA
16343};
16344
16345
7413f23f 16346/* Output a single mapping symbol. */
4e617b1e
PB		 16347
16348static bfd_boolean
7413f23f
DJ		 16349elf32_arm_output_map_sym (output_arch_syminfo *osi,
16350 enum map_symbol_type type,
16351 bfd_vma offset)
4e617b1e
PB		 16352{
16353 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16354 Elf_Internal_Sym sym;
16355
91a5743d
PB		 16356 sym.st_value = osi->sec->output_section->vma
16357 + osi->sec->output_offset
16358 + offset;
4e617b1e
PB		 16359 sym.st_size = 0;
16360 sym.st_other = 0;
16361 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16362 sym.st_shndx = osi->sec_shndx;
35fc36a8 16363 sym.st_target_internal = 0;
fe33d2fa 16364 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16365 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16366}
16367
34e77a92
RS		 16368/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16369 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16370
16371static bfd_boolean
34e77a92
RS		 16372elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16373 bfd_boolean is_iplt_entry_p,
16374 union gotplt_union *root_plt,
16375 struct arm_plt_info *arm_plt)
4e617b1e 16376{
4e617b1e 16377 struct elf32_arm_link_hash_table *htab;
34e77a92 16378 bfd_vma addr, plt_header_size;
4e617b1e 16379
34e77a92 16380 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16381 return TRUE;
16382
4dfe6ac6
NC		 16383 htab = elf32_arm_hash_table (osi->info);
16384 if (htab == NULL)
16385 return FALSE;
16386
34e77a92
RS		 16387 if (is_iplt_entry_p)
16388 {
16389 osi->sec = htab->root.iplt;
16390 plt_header_size = 0;
16391 }
16392 else
16393 {
16394 osi->sec = htab->root.splt;
16395 plt_header_size = htab->plt_header_size;
16396 }
16397 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16398 (osi->info->output_bfd, osi->sec->output_section));
16399
16400 addr = root_plt->offset & -2;
4e617b1e
PB		 16401 if (htab->symbian_p)
16402 {
7413f23f 16403 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16404 return FALSE;
7413f23f 16405 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16406 return FALSE;
16407 }
16408 else if (htab->vxworks_p)
16409 {
7413f23f 16410 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16411 return FALSE;
7413f23f 16412 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16413 return FALSE;
7413f23f 16414 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16415 return FALSE;
7413f23f 16416 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16417 return FALSE;
16418 }
b38cadfb
NC		 16419 else if (htab->nacl_p)
16420 {
16421 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16422 return FALSE;
16423 }
eed94f8f
NC		 16424 else if (using_thumb_only (htab))
16425 {
16426 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16427 return FALSE;
6a631e86 16428 }
4e617b1e
PB		 16429 else
16430 {
34e77a92 16431 bfd_boolean thumb_stub_p;
bd97cb95 16432
34e77a92
RS		 16433 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16434 if (thumb_stub_p)
4e617b1e 16435 {
7413f23f 16436 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16437 return FALSE;
16438 }
16439#ifdef FOUR_WORD_PLT
7413f23f 16440 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16441 return FALSE;
7413f23f 16442 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 16443 return FALSE;
16444#else
906e58ca 16445 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 16446 so only need to output a mapping symbol for the first PLT entry and
16447 entries with thumb thunks. */
34e77a92 16448 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 16449 {
7413f23f 16450 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 16451 return FALSE;
16452 }
16453#endif
16454 }
16455
16456 return TRUE;
16457}
16458
34e77a92
RS		 16459/* Output mapping symbols for PLT entries associated with H. */
16460
16461static bfd_boolean
16462elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
16463{
16464 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
16465 struct elf32_arm_link_hash_entry *eh;
16466
16467 if (h->root.type == bfd_link_hash_indirect)
16468 return TRUE;
16469
16470 if (h->root.type == bfd_link_hash_warning)
16471 /* When warning symbols are created, they **replace** the "real"
16472 entry in the hash table, thus we never get to see the real
16473 symbol in a hash traversal. So look at it now. */
16474 h = (struct elf_link_hash_entry *) h->root.u.i.link;
16475
16476 eh = (struct elf32_arm_link_hash_entry *) h;
16477 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
16478 &h->plt, &eh->plt);
16479}
16480
4f4faa4d
TP		 16481/* Bind a veneered symbol to its veneer identified by its hash entry
16482 STUB_ENTRY. The veneered location thus loose its symbol. */
16483
16484static void
16485arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
16486{
16487 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
16488
16489 BFD_ASSERT (hash);
16490 hash->root.root.u.def.section = stub_entry->stub_sec;
16491 hash->root.root.u.def.value = stub_entry->stub_offset;
16492 hash->root.size = stub_entry->stub_size;
16493}
16494
7413f23f
DJ		 16495/* Output a single local symbol for a generated stub. */
16496
16497static bfd_boolean
16498elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
16499 bfd_vma offset, bfd_vma size)
16500{
7413f23f
DJ		 16501 Elf_Internal_Sym sym;
16502
7413f23f
DJ		 16503 sym.st_value = osi->sec->output_section->vma
16504 + osi->sec->output_offset
16505 + offset;
16506 sym.st_size = size;
16507 sym.st_other = 0;
16508 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
16509 sym.st_shndx = osi->sec_shndx;
35fc36a8 16510 sym.st_target_internal = 0;
57402f1e 16511 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 16512}
4e617b1e 16513
da5938a2 16514static bfd_boolean
8029a119
NC		 16515arm_map_one_stub (struct bfd_hash_entry * gen_entry,
16516 void * in_arg)
da5938a2
NC		 16517{
16518 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 16519 asection *stub_sec;
16520 bfd_vma addr;
7413f23f 16521 char *stub_name;
9a008db3 16522 output_arch_syminfo *osi;
d3ce72d0 16523 const insn_sequence *template_sequence;
461a49ca
DJ		 16524 enum stub_insn_type prev_type;
16525 int size;
16526 int i;
16527 enum map_symbol_type sym_type;
da5938a2
NC		 16528
16529 /* Massage our args to the form they really have. */
16530 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 16531 osi = (output_arch_syminfo *) in_arg;
da5938a2 16532
da5938a2
NC		 16533 stub_sec = stub_entry->stub_sec;
16534
16535 /* Ensure this stub is attached to the current section being
7413f23f 16536 processed. */
da5938a2
NC		 16537 if (stub_sec != osi->sec)
16538 return TRUE;
16539
7413f23f 16540 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 16541 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 16542
16543 if (arm_stub_sym_claimed (stub_entry->stub_type))
16544 arm_stub_claim_sym (stub_entry);
16545 else
7413f23f 16546 {
4f4faa4d
TP		 16547 stub_name = stub_entry->output_name;
16548 switch (template_sequence[0].type)
16549 {
16550 case ARM_TYPE:
16551 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
16552 stub_entry->stub_size))
16553 return FALSE;
16554 break;
16555 case THUMB16_TYPE:
16556 case THUMB32_TYPE:
16557 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
16558 stub_entry->stub_size))
16559 return FALSE;
16560 break;
16561 default:
16562 BFD_FAIL ();
16563 return 0;
16564 }
7413f23f 16565 }
da5938a2 16566
461a49ca
DJ		 16567 prev_type = DATA_TYPE;
16568 size = 0;
16569 for (i = 0; i < stub_entry->stub_template_size; i++)
16570 {
d3ce72d0 16571 switch (template_sequence[i].type)
461a49ca
DJ		 16572 {
16573 case ARM_TYPE:
16574 sym_type = ARM_MAP_ARM;
16575 break;
16576
16577 case THUMB16_TYPE:
48229727 16578 case THUMB32_TYPE:
461a49ca
DJ		 16579 sym_type = ARM_MAP_THUMB;
16580 break;
16581
16582 case DATA_TYPE:
16583 sym_type = ARM_MAP_DATA;
16584 break;
16585
16586 default:
16587 BFD_FAIL ();
4e31c731 16588 return FALSE;
461a49ca
DJ		 16589 }
16590
d3ce72d0 16591 if (template_sequence[i].type != prev_type)
461a49ca 16592 {
d3ce72d0 16593 prev_type = template_sequence[i].type;
461a49ca
DJ		 16594 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
16595 return FALSE;
16596 }
16597
d3ce72d0 16598 switch (template_sequence[i].type)
461a49ca
DJ		 16599 {
16600 case ARM_TYPE:
48229727 16601 case THUMB32_TYPE:
461a49ca
DJ		 16602 size += 4;
16603 break;
16604
16605 case THUMB16_TYPE:
16606 size += 2;
16607 break;
16608
16609 case DATA_TYPE:
16610 size += 4;
16611 break;
16612
16613 default:
16614 BFD_FAIL ();
4e31c731 16615 return FALSE;
461a49ca
DJ		 16616 }
16617 }
16618
da5938a2
NC		 16619 return TRUE;
16620}
16621
33811162
DG		 16622/* Output mapping symbols for linker generated sections,
16623 and for those data-only sections that do not have a
16624 $d. */
4e617b1e
PB		 16625
16626static bfd_boolean
16627elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 16628 struct bfd_link_info *info,
57402f1e 16629 void *flaginfo,
6e0b88f1
AM		 16630 int (*func) (void *, const char *,
16631 Elf_Internal_Sym *,
16632 asection *,
16633 struct elf_link_hash_entry *))
4e617b1e
PB		 16634{
16635 output_arch_syminfo osi;
16636 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 16637 bfd_vma offset;
16638 bfd_size_type size;
33811162 16639 bfd *input_bfd;
4e617b1e
PB		 16640
16641 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16642 if (htab == NULL)
16643 return FALSE;
16644
906e58ca 16645 check_use_blx (htab);
91a5743d 16646
57402f1e 16647 osi.flaginfo = flaginfo;
4e617b1e
PB		 16648 osi.info = info;
16649 osi.func = func;
906e58ca 16650
33811162
DG		 16651 /* Add a $d mapping symbol to data-only sections that
16652 don't have any mapping symbol. This may result in (harmless) redundant
16653 mapping symbols. */
16654 for (input_bfd = info->input_bfds;
16655 input_bfd != NULL;
c72f2fb2 16656 input_bfd = input_bfd->link.next)
33811162
DG		 16657 {
16658 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
16659 for (osi.sec = input_bfd->sections;
16660 osi.sec != NULL;
16661 osi.sec = osi.sec->next)
16662 {
16663 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 16664 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
16665 != 0)
33811162
DG		 16666 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
16667 == SEC_HAS_CONTENTS
16668 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 16669 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 16670 && osi.sec->size > 0
16671 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 16672 {
16673 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16674 (output_bfd, osi.sec->output_section);
16675 if (osi.sec_shndx != (int)SHN_BAD)
16676 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
16677 }
16678 }
16679 }
16680
91a5743d
PB		 16681 /* ARM->Thumb glue. */
16682 if (htab->arm_glue_size > 0)
16683 {
3d4d4302
AM		 16684 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16685 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 16686
16687 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16688 (output_bfd, osi.sec->output_section);
0e1862bb 16689 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 16690 || htab->pic_veneer)
16691 size = ARM2THUMB_PIC_GLUE_SIZE;
16692 else if (htab->use_blx)
16693 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
16694 else
16695 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 16696
91a5743d
PB		 16697 for (offset = 0; offset < htab->arm_glue_size; offset += size)
16698 {
7413f23f
DJ		 16699 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
16700 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 16701 }
16702 }
16703
16704 /* Thumb->ARM glue. */
16705 if (htab->thumb_glue_size > 0)
16706 {
3d4d4302
AM		 16707 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16708 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 16709
16710 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16711 (output_bfd, osi.sec->output_section);
16712 size = THUMB2ARM_GLUE_SIZE;
16713
16714 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
16715 {
7413f23f
DJ		 16716 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
16717 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 16718 }
16719 }
16720
845b51d6
PB		 16721 /* ARMv4 BX veneers. */
16722 if (htab->bx_glue_size > 0)
16723 {
3d4d4302
AM		 16724 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16725 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 16726
16727 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16728 (output_bfd, osi.sec->output_section);
16729
7413f23f 16730 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 16731 }
16732
8029a119
NC		 16733 /* Long calls stubs. */
16734 if (htab->stub_bfd && htab->stub_bfd->sections)
16735 {
da5938a2 16736 asection* stub_sec;
8029a119 16737
da5938a2
NC		 16738 for (stub_sec = htab->stub_bfd->sections;
16739 stub_sec != NULL;
8029a119
NC		 16740 stub_sec = stub_sec->next)
16741 {
16742 /* Ignore non-stub sections. */
16743 if (!strstr (stub_sec->name, STUB_SUFFIX))
16744 continue;
da5938a2 16745
8029a119 16746 osi.sec = stub_sec;
da5938a2 16747
8029a119
NC		 16748 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16749 (output_bfd, osi.sec->output_section);
da5938a2 16750
8029a119
NC		 16751 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
16752 }
16753 }
da5938a2 16754
91a5743d 16755 /* Finally, output mapping symbols for the PLT. */
34e77a92 16756 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 16757 {
34e77a92
RS		 16758 osi.sec = htab->root.splt;
16759 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16760 (output_bfd, osi.sec->output_section));
16761
16762 /* Output mapping symbols for the plt header. SymbianOS does not have a
16763 plt header. */
16764 if (htab->vxworks_p)
16765 {
16766 /* VxWorks shared libraries have no PLT header. */
0e1862bb 16767 if (!bfd_link_pic (info))
34e77a92
RS		 16768 {
16769 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16770 return FALSE;
16771 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16772 return FALSE;
16773 }
16774 }
b38cadfb
NC		 16775 else if (htab->nacl_p)
16776 {
16777 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16778 return FALSE;
16779 }
eed94f8f
NC		 16780 else if (using_thumb_only (htab))
16781 {
16782 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
16783 return FALSE;
16784 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16785 return FALSE;
16786 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
16787 return FALSE;
16788 }
34e77a92 16789 else if (!htab->symbian_p)
4e617b1e 16790 {
7413f23f 16791 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 16792 return FALSE;
34e77a92
RS		 16793#ifndef FOUR_WORD_PLT
16794 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 16795 return FALSE;
34e77a92 16796#endif
4e617b1e
PB		 16797 }
16798 }
99059e56
RM		 16799 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
16800 {
16801 /* NaCl uses a special first entry in .iplt too. */
16802 osi.sec = htab->root.iplt;
16803 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16804 (output_bfd, osi.sec->output_section));
16805 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16806 return FALSE;
16807 }
34e77a92
RS		 16808 if ((htab->root.splt && htab->root.splt->size > 0)
16809 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 16810 {
34e77a92
RS		 16811 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
16812 for (input_bfd = info->input_bfds;
16813 input_bfd != NULL;
c72f2fb2 16814 input_bfd = input_bfd->link.next)
34e77a92
RS		 16815 {
16816 struct arm_local_iplt_info **local_iplt;
16817 unsigned int i, num_syms;
4e617b1e 16818
34e77a92
RS		 16819 local_iplt = elf32_arm_local_iplt (input_bfd);
16820 if (local_iplt != NULL)
16821 {
16822 num_syms = elf_symtab_hdr (input_bfd).sh_info;
16823 for (i = 0; i < num_syms; i++)
16824 if (local_iplt[i] != NULL
16825 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
16826 &local_iplt[i]->root,
16827 &local_iplt[i]->arm))
16828 return FALSE;
16829 }
16830 }
16831 }
0855e32b
NS		 16832 if (htab->dt_tlsdesc_plt != 0)
16833 {
16834 /* Mapping symbols for the lazy tls trampoline. */
16835 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
16836 return FALSE;
b38cadfb 16837
0855e32b
NS		 16838 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16839 htab->dt_tlsdesc_plt + 24))
16840 return FALSE;
16841 }
16842 if (htab->tls_trampoline != 0)
16843 {
16844 /* Mapping symbols for the tls trampoline. */
16845 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
16846 return FALSE;
16847#ifdef FOUR_WORD_PLT
16848 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16849 htab->tls_trampoline + 12))
16850 return FALSE;
b38cadfb 16851#endif
0855e32b 16852 }
b38cadfb 16853
4e617b1e
PB		 16854 return TRUE;
16855}
16856
e489d0ae
PB		 16857/* Allocate target specific section data. */
16858
16859static bfd_boolean
16860elf32_arm_new_section_hook (bfd *abfd, asection *sec)
16861{
f592407e
AM		 16862 if (!sec->used_by_bfd)
16863 {
16864 _arm_elf_section_data *sdata;
16865 bfd_size_type amt = sizeof (*sdata);
e489d0ae 16866
21d799b5 16867 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 16868 if (sdata == NULL)
16869 return FALSE;
16870 sec->used_by_bfd = sdata;
16871 }
e489d0ae
PB		 16872
16873 return _bfd_elf_new_section_hook (abfd, sec);
16874}
16875
16876
16877/* Used to order a list of mapping symbols by address. */
16878
16879static int
16880elf32_arm_compare_mapping (const void * a, const void * b)
16881{
7f6a71ff
JM		 16882 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
16883 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
16884
16885 if (amap->vma > bmap->vma)
16886 return 1;
16887 else if (amap->vma < bmap->vma)
16888 return -1;
16889 else if (amap->type > bmap->type)
16890 /* Ensure results do not depend on the host qsort for objects with
16891 multiple mapping symbols at the same address by sorting on type
16892 after vma. */
16893 return 1;
16894 else if (amap->type < bmap->type)
16895 return -1;
16896 else
16897 return 0;
e489d0ae
PB		 16898}
16899
2468f9c9
PB		 16900/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16901
16902static unsigned long
16903offset_prel31 (unsigned long addr, bfd_vma offset)
16904{
16905 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
16906}
16907
16908/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16909 relocations. */
16910
16911static void
16912copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
16913{
16914 unsigned long first_word = bfd_get_32 (output_bfd, from);
16915 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 16916
2468f9c9
PB		 16917 /* High bit of first word is supposed to be zero. */
16918 if ((first_word & 0x80000000ul) == 0)
16919 first_word = offset_prel31 (first_word, offset);
b38cadfb 16920
2468f9c9
PB		 16921 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16922 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16923 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
16924 second_word = offset_prel31 (second_word, offset);
b38cadfb 16925
2468f9c9
PB		 16926 bfd_put_32 (output_bfd, first_word, to);
16927 bfd_put_32 (output_bfd, second_word, to + 4);
16928}
e489d0ae 16929
48229727
JB		 16930/* Data for make_branch_to_a8_stub(). */
16931
b38cadfb
NC		 16932struct a8_branch_to_stub_data
16933{
48229727
JB		 16934 asection *writing_section;
16935 bfd_byte *contents;
16936};
16937
16938
16939/* Helper to insert branches to Cortex-A8 erratum stubs in the right
16940 places for a particular section. */
16941
16942static bfd_boolean
16943make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 16944 void *in_arg)
48229727
JB		 16945{
16946 struct elf32_arm_stub_hash_entry *stub_entry;
16947 struct a8_branch_to_stub_data *data;
16948 bfd_byte *contents;
16949 unsigned long branch_insn;
16950 bfd_vma veneered_insn_loc, veneer_entry_loc;
16951 bfd_signed_vma branch_offset;
16952 bfd *abfd;
8d9d9490 16953 unsigned int loc;
48229727
JB		 16954
16955 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
16956 data = (struct a8_branch_to_stub_data *) in_arg;
16957
16958 if (stub_entry->target_section != data->writing_section
4563a860 16959 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 16960 return TRUE;
16961
16962 contents = data->contents;
16963
8d9d9490
TP		 16964 /* We use target_section as Cortex-A8 erratum workaround stubs are only
16965 generated when both source and target are in the same section. */
48229727
JB		 16966 veneered_insn_loc = stub_entry->target_section->output_section->vma
16967 + stub_entry->target_section->output_offset
8d9d9490 16968 + stub_entry->source_value;
48229727
JB		 16969
16970 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
16971 + stub_entry->stub_sec->output_offset
16972 + stub_entry->stub_offset;
16973
16974 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
16975 veneered_insn_loc &= ~3u;
16976
16977 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
16978
16979 abfd = stub_entry->target_section->owner;
8d9d9490 16980 loc = stub_entry->source_value;
48229727
JB		 16981
16982 /* We attempt to avoid this condition by setting stubs_always_after_branch
16983 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16984 This check is just to be on the safe side... */
16985 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
16986 {
16987 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
16988 "allocated in unsafe location"), abfd);
16989 return FALSE;
16990 }
16991
16992 switch (stub_entry->stub_type)
16993 {
16994 case arm_stub_a8_veneer_b:
16995 case arm_stub_a8_veneer_b_cond:
16996 branch_insn = 0xf0009000;
16997 goto jump24;
16998
16999 case arm_stub_a8_veneer_blx:
17000 branch_insn = 0xf000e800;
17001 goto jump24;
17002
17003 case arm_stub_a8_veneer_bl:
17004 {
17005 unsigned int i1, j1, i2, j2, s;
17006
17007 branch_insn = 0xf000d000;
17008
17009 jump24:
17010 if (branch_offset < -16777216 || branch_offset > 16777214)
17011 {
17012 /* There's not much we can do apart from complain if this
17013 happens. */
17014 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
17015 "of range (input file too large)"), abfd);
17016 return FALSE;
17017 }
17018
17019 /* i1 = not(j1 eor s), so:
17020 not i1 = j1 eor s
17021 j1 = (not i1) eor s. */
17022
17023 branch_insn |= (branch_offset >> 1) & 0x7ff;
17024 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17025 i2 = (branch_offset >> 22) & 1;
17026 i1 = (branch_offset >> 23) & 1;
17027 s = (branch_offset >> 24) & 1;
17028 j1 = (!i1) ^ s;
17029 j2 = (!i2) ^ s;
17030 branch_insn |= j2 << 11;
17031 branch_insn |= j1 << 13;
17032 branch_insn |= s << 26;
17033 }
17034 break;
17035
17036 default:
17037 BFD_FAIL ();
17038 return FALSE;
17039 }
17040
8d9d9490
TP		 17041 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17042 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17043
17044 return TRUE;
17045}
17046
a504d23a
LA		 17047/* Beginning of stm32l4xx work-around. */
17048
17049/* Functions encoding instructions necessary for the emission of the
17050 fix-stm32l4xx-629360.
17051 Encoding is extracted from the
17052 ARM (C) Architecture Reference Manual
17053 ARMv7-A and ARMv7-R edition
17054 ARM DDI 0406C.b (ID072512). */
17055
17056static inline bfd_vma
82188b29 17057create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17058{
17059 /* A8.8.18 B (A8-334)
17060 B target_address (Encoding T4). */
17061 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17062 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17063 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17064
a504d23a
LA		 17065 int s = ((branch_offset & 0x1000000) >> 24);
17066 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17067 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17068
17069 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17070 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17071
17072 bfd_vma patched_inst = 0xf0009000
17073 | s << 26 /* S. */
17074 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17075 | j1 << 13 /* J1. */
17076 | j2 << 11 /* J2. */
17077 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17078
17079 return patched_inst;
17080}
17081
17082static inline bfd_vma
17083create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17084{
17085 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17086 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17087 bfd_vma patched_inst = 0xe8900000
17088 | (/*W=*/wback << 21)
17089 | (base_reg << 16)
17090 | (reg_mask & 0x0000ffff);
17091
17092 return patched_inst;
17093}
17094
17095static inline bfd_vma
17096create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17097{
17098 /* A8.8.60 LDMDB/LDMEA (A8-402)
17099 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17100 bfd_vma patched_inst = 0xe9100000
17101 | (/*W=*/wback << 21)
17102 | (base_reg << 16)
17103 | (reg_mask & 0x0000ffff);
17104
17105 return patched_inst;
17106}
17107
17108static inline bfd_vma
17109create_instruction_mov (int target_reg, int source_reg)
17110{
17111 /* A8.8.103 MOV (register) (A8-486)
17112 MOV Rd, Rm (Encoding T1). */
17113 bfd_vma patched_inst = 0x4600
17114 | (target_reg & 0x7)
17115 | ((target_reg & 0x8) >> 3) << 7
17116 | (source_reg << 3);
17117
17118 return patched_inst;
17119}
17120
17121static inline bfd_vma
17122create_instruction_sub (int target_reg, int source_reg, int value)
17123{
17124 /* A8.8.221 SUB (immediate) (A8-708)
17125 SUB Rd, Rn, #value (Encoding T3). */
17126 bfd_vma patched_inst = 0xf1a00000
17127 | (target_reg << 8)
17128 | (source_reg << 16)
17129 | (/*S=*/0 << 20)
17130 | ((value & 0x800) >> 11) << 26
17131 | ((value & 0x700) >> 8) << 12
17132 | (value & 0x0ff);
17133
17134 return patched_inst;
17135}
17136
17137static inline bfd_vma
9239bbd3 17138create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17139 int first_reg)
17140{
17141 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17142 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17143 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17144 | (/*W=*/wback << 21)
17145 | (base_reg << 16)
9239bbd3
CM		 17146 | (num_words & 0x000000ff)
17147 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17148 | (first_reg & 0x00000001) << 22;
17149
17150 return patched_inst;
17151}
17152
17153static inline bfd_vma
9239bbd3
CM		 17154create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17155 int first_reg)
a504d23a
LA		 17156{
17157 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17158 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17159 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17160 | (base_reg << 16)
9239bbd3
CM		 17161 | (num_words & 0x000000ff)
17162 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17163 | (first_reg & 0x00000001) << 22;
17164
17165 return patched_inst;
17166}
17167
17168static inline bfd_vma
17169create_instruction_udf_w (int value)
17170{
17171 /* A8.8.247 UDF (A8-758)
17172 Undefined (Encoding T2). */
17173 bfd_vma patched_inst = 0xf7f0a000
17174 | (value & 0x00000fff)
17175 | (value & 0x000f0000) << 16;
17176
17177 return patched_inst;
17178}
17179
17180static inline bfd_vma
17181create_instruction_udf (int value)
17182{
17183 /* A8.8.247 UDF (A8-758)
17184 Undefined (Encoding T1). */
17185 bfd_vma patched_inst = 0xde00
17186 | (value & 0xff);
17187
17188 return patched_inst;
17189}
17190
17191/* Functions writing an instruction in memory, returning the next
17192 memory position to write to. */
17193
17194static inline bfd_byte *
17195push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17196 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17197{
17198 put_thumb2_insn (htab, output_bfd, insn, pt);
17199 return pt + 4;
17200}
17201
17202static inline bfd_byte *
17203push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17204 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17205{
17206 put_thumb_insn (htab, output_bfd, insn, pt);
17207 return pt + 2;
17208}
17209
17210/* Function filling up a region in memory with T1 and T2 UDFs taking
17211 care of alignment. */
17212
17213static bfd_byte *
17214stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17215 bfd * output_bfd,
17216 const bfd_byte * const base_stub_contents,
17217 bfd_byte * const from_stub_contents,
17218 const bfd_byte * const end_stub_contents)
17219{
17220 bfd_byte *current_stub_contents = from_stub_contents;
17221
17222 /* Fill the remaining of the stub with deterministic contents : UDF
17223 instructions.
17224 Check if realignment is needed on modulo 4 frontier using T1, to
17225 further use T2. */
17226 if ((current_stub_contents < end_stub_contents)
17227 && !((current_stub_contents - base_stub_contents) % 2)
17228 && ((current_stub_contents - base_stub_contents) % 4))
17229 current_stub_contents =
17230 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17231 create_instruction_udf (0));
17232
17233 for (; current_stub_contents < end_stub_contents;)
17234 current_stub_contents =
17235 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17236 create_instruction_udf_w (0));
17237
17238 return current_stub_contents;
17239}
17240
17241/* Functions writing the stream of instructions equivalent to the
17242 derived sequence for ldmia, ldmdb, vldm respectively. */
17243
17244static void
17245stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17246 bfd * output_bfd,
17247 const insn32 initial_insn,
17248 const bfd_byte *const initial_insn_addr,
17249 bfd_byte *const base_stub_contents)
17250{
17251 int wback = (initial_insn & 0x00200000) >> 21;
17252 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17253 int insn_all_registers = initial_insn & 0x0000ffff;
17254 int insn_low_registers, insn_high_registers;
17255 int usable_register_mask;
17256 int nb_registers = popcount (insn_all_registers);
17257 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17258 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17259 bfd_byte *current_stub_contents = base_stub_contents;
17260
17261 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17262
17263 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17264 smaller than 8 registers load sequences that do not cause the
17265 hardware issue. */
17266 if (nb_registers <= 8)
17267 {
17268 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17269 current_stub_contents =
17270 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17271 initial_insn);
17272
17273 /* B initial_insn_addr+4. */
17274 if (!restore_pc)
17275 current_stub_contents =
17276 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17277 create_instruction_branch_absolute
82188b29
NC		 17278 (initial_insn_addr - current_stub_contents));
17279
a504d23a
LA		 17280
17281 /* Fill the remaining of the stub with deterministic contents. */
17282 current_stub_contents =
17283 stm32l4xx_fill_stub_udf (htab, output_bfd,
17284 base_stub_contents, current_stub_contents,
17285 base_stub_contents +
17286 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17287
17288 return;
17289 }
17290
17291 /* - reg_list[13] == 0. */
17292 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17293
17294 /* - reg_list[14] & reg_list[15] != 1. */
17295 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17296
17297 /* - if (wback==1) reg_list[rn] == 0. */
17298 BFD_ASSERT (!wback || !restore_rn);
17299
17300 /* - nb_registers > 8. */
17301 BFD_ASSERT (popcount (insn_all_registers) > 8);
17302
17303 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17304
17305 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17306 - One with the 7 lowest registers (register mask 0x007F)
17307 This LDM will finally contain between 2 and 7 registers
17308 - One with the 7 highest registers (register mask 0xDF80)
17309 This ldm will finally contain between 2 and 7 registers. */
17310 insn_low_registers = insn_all_registers & 0x007F;
17311 insn_high_registers = insn_all_registers & 0xDF80;
17312
17313 /* A spare register may be needed during this veneer to temporarily
17314 handle the base register. This register will be restored with the
17315 last LDM operation.
17316 The usable register may be any general purpose register (that
17317 excludes PC, SP, LR : register mask is 0x1FFF). */
17318 usable_register_mask = 0x1FFF;
17319
17320 /* Generate the stub function. */
17321 if (wback)
17322 {
17323 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17324 current_stub_contents =
17325 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17326 create_instruction_ldmia
17327 (rn, /*wback=*/1, insn_low_registers));
17328
17329 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17330 current_stub_contents =
17331 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17332 create_instruction_ldmia
17333 (rn, /*wback=*/1, insn_high_registers));
17334 if (!restore_pc)
17335 {
17336 /* B initial_insn_addr+4. */
17337 current_stub_contents =
17338 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17339 create_instruction_branch_absolute
82188b29 17340 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17341 }
17342 }
17343 else /* if (!wback). */
17344 {
17345 ri = rn;
17346
17347 /* If Rn is not part of the high-register-list, move it there. */
17348 if (!(insn_high_registers & (1 << rn)))
17349 {
17350 /* Choose a Ri in the high-register-list that will be restored. */
17351 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17352
17353 /* MOV Ri, Rn. */
17354 current_stub_contents =
17355 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17356 create_instruction_mov (ri, rn));
17357 }
17358
17359 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
17360 current_stub_contents =
17361 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17362 create_instruction_ldmia
17363 (ri, /*wback=*/1, insn_low_registers));
17364
17365 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
17366 current_stub_contents =
17367 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17368 create_instruction_ldmia
17369 (ri, /*wback=*/0, insn_high_registers));
17370
17371 if (!restore_pc)
17372 {
17373 /* B initial_insn_addr+4. */
17374 current_stub_contents =
17375 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17376 create_instruction_branch_absolute
82188b29 17377 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17378 }
17379 }
17380
17381 /* Fill the remaining of the stub with deterministic contents. */
17382 current_stub_contents =
17383 stm32l4xx_fill_stub_udf (htab, output_bfd,
17384 base_stub_contents, current_stub_contents,
17385 base_stub_contents +
17386 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17387}
17388
17389static void
17390stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
17391 bfd * output_bfd,
17392 const insn32 initial_insn,
17393 const bfd_byte *const initial_insn_addr,
17394 bfd_byte *const base_stub_contents)
17395{
17396 int wback = (initial_insn & 0x00200000) >> 21;
17397 int ri, rn = (initial_insn & 0x000f0000) >> 16;
17398 int insn_all_registers = initial_insn & 0x0000ffff;
17399 int insn_low_registers, insn_high_registers;
17400 int usable_register_mask;
17401 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17402 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17403 int nb_registers = popcount (insn_all_registers);
17404 bfd_byte *current_stub_contents = base_stub_contents;
17405
17406 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
17407
17408 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17409 smaller than 8 registers load sequences that do not cause the
17410 hardware issue. */
17411 if (nb_registers <= 8)
17412 {
17413 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17414 current_stub_contents =
17415 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17416 initial_insn);
17417
17418 /* B initial_insn_addr+4. */
17419 current_stub_contents =
17420 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17421 create_instruction_branch_absolute
82188b29 17422 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17423
17424 /* Fill the remaining of the stub with deterministic contents. */
17425 current_stub_contents =
17426 stm32l4xx_fill_stub_udf (htab, output_bfd,
17427 base_stub_contents, current_stub_contents,
17428 base_stub_contents +
17429 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17430
17431 return;
17432 }
17433
17434 /* - reg_list[13] == 0. */
17435 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
17436
17437 /* - reg_list[14] & reg_list[15] != 1. */
17438 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17439
17440 /* - if (wback==1) reg_list[rn] == 0. */
17441 BFD_ASSERT (!wback || !restore_rn);
17442
17443 /* - nb_registers > 8. */
17444 BFD_ASSERT (popcount (insn_all_registers) > 8);
17445
17446 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17447
17448 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
17449 - One with the 7 lowest registers (register mask 0x007F)
17450 This LDM will finally contain between 2 and 7 registers
17451 - One with the 7 highest registers (register mask 0xDF80)
17452 This ldm will finally contain between 2 and 7 registers. */
17453 insn_low_registers = insn_all_registers & 0x007F;
17454 insn_high_registers = insn_all_registers & 0xDF80;
17455
17456 /* A spare register may be needed during this veneer to temporarily
17457 handle the base register. This register will be restored with
17458 the last LDM operation.
17459 The usable register may be any general purpose register (that excludes
17460 PC, SP, LR : register mask is 0x1FFF). */
17461 usable_register_mask = 0x1FFF;
17462
17463 /* Generate the stub function. */
17464 if (!wback && !restore_pc && !restore_rn)
17465 {
17466 /* Choose a Ri in the low-register-list that will be restored. */
17467 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
17468
17469 /* MOV Ri, Rn. */
17470 current_stub_contents =
17471 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17472 create_instruction_mov (ri, rn));
17473
17474 /* LDMDB Ri!, {R-high-register-list}. */
17475 current_stub_contents =
17476 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17477 create_instruction_ldmdb
17478 (ri, /*wback=*/1, insn_high_registers));
17479
17480 /* LDMDB Ri, {R-low-register-list}. */
17481 current_stub_contents =
17482 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17483 create_instruction_ldmdb
17484 (ri, /*wback=*/0, insn_low_registers));
17485
17486 /* B initial_insn_addr+4. */
17487 current_stub_contents =
17488 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17489 create_instruction_branch_absolute
82188b29 17490 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17491 }
17492 else if (wback && !restore_pc && !restore_rn)
17493 {
17494 /* LDMDB Rn!, {R-high-register-list}. */
17495 current_stub_contents =
17496 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17497 create_instruction_ldmdb
17498 (rn, /*wback=*/1, insn_high_registers));
17499
17500 /* LDMDB Rn!, {R-low-register-list}. */
17501 current_stub_contents =
17502 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17503 create_instruction_ldmdb
17504 (rn, /*wback=*/1, insn_low_registers));
17505
17506 /* B initial_insn_addr+4. */
17507 current_stub_contents =
17508 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17509 create_instruction_branch_absolute
82188b29 17510 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17511 }
17512 else if (!wback && restore_pc && !restore_rn)
17513 {
17514 /* Choose a Ri in the high-register-list that will be restored. */
17515 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17516
17517 /* SUB Ri, Rn, #(4*nb_registers). */
17518 current_stub_contents =
17519 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17520 create_instruction_sub (ri, rn, (4 * nb_registers)));
17521
17522 /* LDMIA Ri!, {R-low-register-list}. */
17523 current_stub_contents =
17524 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17525 create_instruction_ldmia
17526 (ri, /*wback=*/1, insn_low_registers));
17527
17528 /* LDMIA Ri, {R-high-register-list}. */
17529 current_stub_contents =
17530 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17531 create_instruction_ldmia
17532 (ri, /*wback=*/0, insn_high_registers));
17533 }
17534 else if (wback && restore_pc && !restore_rn)
17535 {
17536 /* Choose a Ri in the high-register-list that will be restored. */
17537 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17538
17539 /* SUB Rn, Rn, #(4*nb_registers) */
17540 current_stub_contents =
17541 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17542 create_instruction_sub (rn, rn, (4 * nb_registers)));
17543
17544 /* MOV Ri, Rn. */
17545 current_stub_contents =
17546 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17547 create_instruction_mov (ri, rn));
17548
17549 /* LDMIA Ri!, {R-low-register-list}. */
17550 current_stub_contents =
17551 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17552 create_instruction_ldmia
17553 (ri, /*wback=*/1, insn_low_registers));
17554
17555 /* LDMIA Ri, {R-high-register-list}. */
17556 current_stub_contents =
17557 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17558 create_instruction_ldmia
17559 (ri, /*wback=*/0, insn_high_registers));
17560 }
17561 else if (!wback && !restore_pc && restore_rn)
17562 {
17563 ri = rn;
17564 if (!(insn_low_registers & (1 << rn)))
17565 {
17566 /* Choose a Ri in the low-register-list that will be restored. */
17567 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
17568
17569 /* MOV Ri, Rn. */
17570 current_stub_contents =
17571 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17572 create_instruction_mov (ri, rn));
17573 }
17574
17575 /* LDMDB Ri!, {R-high-register-list}. */
17576 current_stub_contents =
17577 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17578 create_instruction_ldmdb
17579 (ri, /*wback=*/1, insn_high_registers));
17580
17581 /* LDMDB Ri, {R-low-register-list}. */
17582 current_stub_contents =
17583 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17584 create_instruction_ldmdb
17585 (ri, /*wback=*/0, insn_low_registers));
17586
17587 /* B initial_insn_addr+4. */
17588 current_stub_contents =
17589 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17590 create_instruction_branch_absolute
82188b29 17591 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17592 }
17593 else if (!wback && restore_pc && restore_rn)
17594 {
17595 ri = rn;
17596 if (!(insn_high_registers & (1 << rn)))
17597 {
17598 /* Choose a Ri in the high-register-list that will be restored. */
17599 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17600 }
17601
17602 /* SUB Ri, Rn, #(4*nb_registers). */
17603 current_stub_contents =
17604 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17605 create_instruction_sub (ri, rn, (4 * nb_registers)));
17606
17607 /* LDMIA Ri!, {R-low-register-list}. */
17608 current_stub_contents =
17609 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17610 create_instruction_ldmia
17611 (ri, /*wback=*/1, insn_low_registers));
17612
17613 /* LDMIA Ri, {R-high-register-list}. */
17614 current_stub_contents =
17615 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17616 create_instruction_ldmia
17617 (ri, /*wback=*/0, insn_high_registers));
17618 }
17619 else if (wback && restore_rn)
17620 {
17621 /* The assembler should not have accepted to encode this. */
17622 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
17623 "undefined behavior.\n");
17624 }
17625
17626 /* Fill the remaining of the stub with deterministic contents. */
17627 current_stub_contents =
17628 stm32l4xx_fill_stub_udf (htab, output_bfd,
17629 base_stub_contents, current_stub_contents,
17630 base_stub_contents +
17631 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17632
17633}
17634
17635static void
17636stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
17637 bfd * output_bfd,
17638 const insn32 initial_insn,
17639 const bfd_byte *const initial_insn_addr,
17640 bfd_byte *const base_stub_contents)
17641{
9239bbd3 17642 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 17643 bfd_byte *current_stub_contents = base_stub_contents;
17644
17645 BFD_ASSERT (is_thumb2_vldm (initial_insn));
17646
17647 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 17648 smaller than 8 words load sequences that do not cause the
a504d23a 17649 hardware issue. */
9239bbd3 17650 if (num_words <= 8)
a504d23a
LA		 17651 {
17652 /* Untouched instruction. */
17653 current_stub_contents =
17654 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17655 initial_insn);
17656
17657 /* B initial_insn_addr+4. */
17658 current_stub_contents =
17659 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17660 create_instruction_branch_absolute
82188b29 17661 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17662 }
17663 else
17664 {
9239bbd3
CM		 17665 bfd_boolean is_dp = /* DP encoding. */
17666 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 17667 bfd_boolean is_ia_nobang = /* (IA without !). */
17668 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
17669 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
17670 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
17671 bfd_boolean is_db_bang = /* (DB with !). */
17672 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 17673 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 17674 /* d = UInt (Vd:D);. */
9239bbd3 17675 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 17676 | (((unsigned int)initial_insn << 9) >> 31);
17677
9239bbd3
CM		 17678 /* Compute the number of 8-words chunks needed to split. */
17679 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 17680 int chunk;
17681
17682 /* The test coverage has been done assuming the following
17683 hypothesis that exactly one of the previous is_ predicates is
17684 true. */
9239bbd3
CM		 17685 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
17686 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 17687
9239bbd3 17688 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 17689 cases, then we emit the adjustments:
17690
17691 vldm rx, {...}
17692 -> vldm rx!, {8_words_or_less} for each needed 8_word
17693 -> sub rx, rx, #size (list)
17694
17695 vldm rx!, {...}
17696 -> vldm rx!, {8_words_or_less} for each needed 8_word
17697 This also handles vpop instruction (when rx is sp)
17698
17699 vldmd rx!, {...}
17700 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 17701 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 17702 {
9239bbd3
CM		 17703 bfd_vma new_insn = 0;
17704
a504d23a
LA		 17705 if (is_ia_nobang || is_ia_bang)
17706 {
9239bbd3
CM		 17707 new_insn = create_instruction_vldmia
17708 (base_reg,
17709 is_dp,
17710 /*wback= . */1,
17711 chunks - (chunk + 1) ?
17712 8 : num_words - chunk * 8,
17713 first_reg + chunk * 8);
a504d23a
LA		 17714 }
17715 else if (is_db_bang)
17716 {
9239bbd3
CM		 17717 new_insn = create_instruction_vldmdb
17718 (base_reg,
17719 is_dp,
17720 chunks - (chunk + 1) ?
17721 8 : num_words - chunk * 8,
17722 first_reg + chunk * 8);
a504d23a 17723 }
9239bbd3
CM		 17724
17725 if (new_insn)
17726 current_stub_contents =
17727 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17728 new_insn);
a504d23a
LA		 17729 }
17730
17731 /* Only this case requires the base register compensation
17732 subtract. */
17733 if (is_ia_nobang)
17734 {
17735 current_stub_contents =
17736 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17737 create_instruction_sub
9239bbd3 17738 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 17739 }
17740
17741 /* B initial_insn_addr+4. */
17742 current_stub_contents =
17743 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17744 create_instruction_branch_absolute
82188b29 17745 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17746 }
17747
17748 /* Fill the remaining of the stub with deterministic contents. */
17749 current_stub_contents =
17750 stm32l4xx_fill_stub_udf (htab, output_bfd,
17751 base_stub_contents, current_stub_contents,
17752 base_stub_contents +
17753 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
17754}
17755
17756static void
17757stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
17758 bfd * output_bfd,
17759 const insn32 wrong_insn,
17760 const bfd_byte *const wrong_insn_addr,
17761 bfd_byte *const stub_contents)
17762{
17763 if (is_thumb2_ldmia (wrong_insn))
17764 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
17765 wrong_insn, wrong_insn_addr,
17766 stub_contents);
17767 else if (is_thumb2_ldmdb (wrong_insn))
17768 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
17769 wrong_insn, wrong_insn_addr,
17770 stub_contents);
17771 else if (is_thumb2_vldm (wrong_insn))
17772 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
17773 wrong_insn, wrong_insn_addr,
17774 stub_contents);
17775}
17776
17777/* End of stm32l4xx work-around. */
17778
17779
491d01d3
YU		 17780static void
17781elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
17782 asection *output_sec, Elf_Internal_Rela *rel)
17783{
17784 BFD_ASSERT (output_sec && rel);
17785 struct bfd_elf_section_reloc_data *output_reldata;
17786 struct elf32_arm_link_hash_table *htab;
17787 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
17788 Elf_Internal_Shdr *rel_hdr;
17789
17790
17791 if (oesd->rel.hdr)
17792 {
17793 rel_hdr = oesd->rel.hdr;
17794 output_reldata = &(oesd->rel);
17795 }
17796 else if (oesd->rela.hdr)
17797 {
17798 rel_hdr = oesd->rela.hdr;
17799 output_reldata = &(oesd->rela);
17800 }
17801 else
17802 {
17803 abort ();
17804 }
17805
17806 bfd_byte *erel = rel_hdr->contents;
17807 erel += output_reldata->count * rel_hdr->sh_entsize;
17808 htab = elf32_arm_hash_table (info);
17809 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
17810 output_reldata->count++;
17811}
17812
e489d0ae
PB		 17813/* Do code byteswapping. Return FALSE afterwards so that the section is
17814 written out as normal. */
17815
17816static bfd_boolean
c7b8f16e 17817elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 17818 struct bfd_link_info *link_info,
17819 asection *sec,
e489d0ae
PB		 17820 bfd_byte *contents)
17821{
48229727 17822 unsigned int mapcount, errcount;
8e3de13a 17823 _arm_elf_section_data *arm_data;
c7b8f16e 17824 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 17825 elf32_arm_section_map *map;
c7b8f16e 17826 elf32_vfp11_erratum_list *errnode;
a504d23a 17827 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 17828 bfd_vma ptr;
17829 bfd_vma end;
c7b8f16e 17830 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 17831 bfd_byte tmp;
48229727 17832 unsigned int i;
57e8b36a 17833
4dfe6ac6
NC		 17834 if (globals == NULL)
17835 return FALSE;
17836
8e3de13a
NC		 17837 /* If this section has not been allocated an _arm_elf_section_data
17838 structure then we cannot record anything. */
17839 arm_data = get_arm_elf_section_data (sec);
17840 if (arm_data == NULL)
17841 return FALSE;
17842
17843 mapcount = arm_data->mapcount;
17844 map = arm_data->map;
c7b8f16e
JB		 17845 errcount = arm_data->erratumcount;
17846
17847 if (errcount != 0)
17848 {
17849 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
17850
17851 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 17852 errnode = errnode->next)
17853 {
17854 bfd_vma target = errnode->vma - offset;
17855
17856 switch (errnode->type)
17857 {
17858 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
17859 {
17860 bfd_vma branch_to_veneer;
17861 /* Original condition code of instruction, plus bit mask for
17862 ARM B instruction. */
17863 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
17864 | 0x0a000000;
c7b8f16e
JB		 17865
17866 /* The instruction is before the label. */
91d6fa6a 17867 target -= 4;
c7b8f16e
JB		 17868
17869 /* Above offset included in -4 below. */
17870 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 17871 - errnode->vma - 4;
c7b8f16e
JB		 17872
17873 if ((signed) branch_to_veneer < -(1 << 25)
17874 || (signed) branch_to_veneer >= (1 << 25))
17875 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17876 "range"), output_bfd);
17877
99059e56
RM		 17878 insn |= (branch_to_veneer >> 2) & 0xffffff;
17879 contents[endianflip ^ target] = insn & 0xff;
17880 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17881 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17882 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17883 }
17884 break;
c7b8f16e
JB		 17885
17886 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 17887 {
17888 bfd_vma branch_from_veneer;
17889 unsigned int insn;
c7b8f16e 17890
99059e56
RM		 17891 /* Take size of veneer into account. */
17892 branch_from_veneer = errnode->u.v.branch->vma
17893 - errnode->vma - 12;
c7b8f16e
JB		 17894
17895 if ((signed) branch_from_veneer < -(1 << 25)
17896 || (signed) branch_from_veneer >= (1 << 25))
17897 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17898 "range"), output_bfd);
17899
99059e56
RM		 17900 /* Original instruction. */
17901 insn = errnode->u.v.branch->u.b.vfp_insn;
17902 contents[endianflip ^ target] = insn & 0xff;
17903 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17904 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17905 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17906
17907 /* Branch back to insn after original insn. */
17908 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
17909 contents[endianflip ^ (target + 4)] = insn & 0xff;
17910 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
17911 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
17912 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
17913 }
17914 break;
c7b8f16e 17915
99059e56
RM		 17916 default:
17917 abort ();
17918 }
17919 }
c7b8f16e 17920 }
e489d0ae 17921
a504d23a
LA		 17922 if (arm_data->stm32l4xx_erratumcount != 0)
17923 {
17924 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
17925 stm32l4xx_errnode != 0;
17926 stm32l4xx_errnode = stm32l4xx_errnode->next)
17927 {
17928 bfd_vma target = stm32l4xx_errnode->vma - offset;
17929
17930 switch (stm32l4xx_errnode->type)
17931 {
17932 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
17933 {
17934 unsigned int insn;
17935 bfd_vma branch_to_veneer =
17936 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
17937
17938 if ((signed) branch_to_veneer < -(1 << 24)
17939 || (signed) branch_to_veneer >= (1 << 24))
17940 {
17941 bfd_vma out_of_range =
17942 ((signed) branch_to_veneer < -(1 << 24)) ?
17943 - branch_to_veneer - (1 << 24) :
17944 ((signed) branch_to_veneer >= (1 << 24)) ?
17945 branch_to_veneer - (1 << 24) : 0;
17946
17947 (*_bfd_error_handler)
17948 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 17949 "Jump out of range by %ld bytes. "
a504d23a
LA		 17950 "Cannot encode branch instruction. "),
17951 output_bfd,
eee926f2 17952 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 17953 out_of_range);
17954 continue;
17955 }
17956
17957 insn = create_instruction_branch_absolute
82188b29 17958 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 17959
17960 /* The instruction is before the label. */
17961 target -= 4;
17962
17963 put_thumb2_insn (globals, output_bfd,
17964 (bfd_vma) insn, contents + target);
17965 }
17966 break;
17967
17968 case STM32L4XX_ERRATUM_VENEER:
17969 {
82188b29
NC		 17970 bfd_byte * veneer;
17971 bfd_byte * veneer_r;
a504d23a
LA		 17972 unsigned int insn;
17973
82188b29
NC		 17974 veneer = contents + target;
17975 veneer_r = veneer
17976 + stm32l4xx_errnode->u.b.veneer->vma
17977 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 17978
17979 if ((signed) (veneer_r - veneer -
17980 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17981 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17982 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17983 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
17984 || (signed) (veneer_r - veneer) >= (1 << 24))
17985 {
17986 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
17987 "veneer."), output_bfd);
17988 continue;
17989 }
17990
17991 /* Original instruction. */
17992 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
17993
17994 stm32l4xx_create_replacing_stub
17995 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
17996 }
17997 break;
17998
17999 default:
18000 abort ();
18001 }
18002 }
18003 }
18004
2468f9c9
PB		 18005 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18006 {
18007 arm_unwind_table_edit *edit_node
99059e56 18008 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18009 /* Now, sec->size is the size of the section we will write. The original
99059e56 18010 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18011 markers) was sec->rawsize. (This isn't the case if we perform no
18012 edits, then rawsize will be zero and we should use size). */
21d799b5 18013 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18014 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18015 unsigned int in_index, out_index;
18016 bfd_vma add_to_offsets = 0;
18017
18018 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18019 {
2468f9c9
PB		 18020 if (edit_node)
18021 {
18022 unsigned int edit_index = edit_node->index;
b38cadfb 18023
2468f9c9 18024 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18025 {
2468f9c9
PB		 18026 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18027 contents + in_index * 8, add_to_offsets);
18028 out_index++;
18029 in_index++;
18030 }
18031 else if (in_index == edit_index
18032 || (in_index * 8 >= input_size
18033 && edit_index == UINT_MAX))
99059e56 18034 {
2468f9c9
PB		 18035 switch (edit_node->type)
18036 {
18037 case DELETE_EXIDX_ENTRY:
18038 in_index++;
18039 add_to_offsets += 8;
18040 break;
b38cadfb 18041
2468f9c9
PB		 18042 case INSERT_EXIDX_CANTUNWIND_AT_END:
18043 {
99059e56 18044 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18045 bfd_vma text_offset = text_sec->output_section->vma
18046 + text_sec->output_offset
18047 + text_sec->size;
18048 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18049 unsigned long prel31_offset;
2468f9c9
PB		 18050
18051 /* Note: this is meant to be equivalent to an
18052 R_ARM_PREL31 relocation. These synthetic
18053 EXIDX_CANTUNWIND markers are not relocated by the
18054 usual BFD method. */
18055 prel31_offset = (text_offset - exidx_offset)
18056 & 0x7ffffffful;
491d01d3
YU		 18057 if (bfd_link_relocatable (link_info))
18058 {
18059 /* Here relocation for new EXIDX_CANTUNWIND is
18060 created, so there is no need to
18061 adjust offset by hand. */
18062 prel31_offset = text_sec->output_offset
18063 + text_sec->size;
18064
18065 /* New relocation entity. */
18066 asection *text_out = text_sec->output_section;
18067 Elf_Internal_Rela rel;
18068 rel.r_addend = 0;
18069 rel.r_offset = exidx_offset;
18070 rel.r_info = ELF32_R_INFO (text_out->target_index,
18071 R_ARM_PREL31);
18072
18073 elf32_arm_add_relocation (output_bfd, link_info,
18074 sec->output_section,
18075 &rel);
18076 }
2468f9c9
PB		 18077
18078 /* First address we can't unwind. */
18079 bfd_put_32 (output_bfd, prel31_offset,
18080 &edited_contents[out_index * 8]);
18081
18082 /* Code for EXIDX_CANTUNWIND. */
18083 bfd_put_32 (output_bfd, 0x1,
18084 &edited_contents[out_index * 8 + 4]);
18085
18086 out_index++;
18087 add_to_offsets -= 8;
18088 }
18089 break;
18090 }
b38cadfb 18091
2468f9c9
PB		 18092 edit_node = edit_node->next;
18093 }
18094 }
18095 else
18096 {
18097 /* No more edits, copy remaining entries verbatim. */
18098 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18099 contents + in_index * 8, add_to_offsets);
18100 out_index++;
18101 in_index++;
18102 }
18103 }
18104
18105 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18106 bfd_set_section_contents (output_bfd, sec->output_section,
18107 edited_contents,
18108 (file_ptr) sec->output_offset, sec->size);
18109
18110 return TRUE;
18111 }
18112
48229727
JB		 18113 /* Fix code to point to Cortex-A8 erratum stubs. */
18114 if (globals->fix_cortex_a8)
18115 {
18116 struct a8_branch_to_stub_data data;
18117
18118 data.writing_section = sec;
18119 data.contents = contents;
18120
a504d23a
LA		 18121 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18122 & data);
48229727
JB		 18123 }
18124
e489d0ae
PB		 18125 if (mapcount == 0)
18126 return FALSE;
18127
c7b8f16e 18128 if (globals->byteswap_code)
e489d0ae 18129 {
c7b8f16e 18130 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18131
c7b8f16e
JB		 18132 ptr = map[0].vma;
18133 for (i = 0; i < mapcount; i++)
99059e56
RM		 18134 {
18135 if (i == mapcount - 1)
c7b8f16e 18136 end = sec->size;
99059e56
RM		 18137 else
18138 end = map[i + 1].vma;
e489d0ae 18139
99059e56 18140 switch (map[i].type)
e489d0ae 18141 {
c7b8f16e
JB		 18142 case 'a':
18143 /* Byte swap code words. */
18144 while (ptr + 3 < end)
99059e56
RM		 18145 {
18146 tmp = contents[ptr];
18147 contents[ptr] = contents[ptr + 3];
18148 contents[ptr + 3] = tmp;
18149 tmp = contents[ptr + 1];
18150 contents[ptr + 1] = contents[ptr + 2];
18151 contents[ptr + 2] = tmp;
18152 ptr += 4;
18153 }
c7b8f16e 18154 break;
e489d0ae 18155
c7b8f16e
JB		 18156 case 't':
18157 /* Byte swap code halfwords. */
18158 while (ptr + 1 < end)
99059e56
RM		 18159 {
18160 tmp = contents[ptr];
18161 contents[ptr] = contents[ptr + 1];
18162 contents[ptr + 1] = tmp;
18163 ptr += 2;
18164 }
c7b8f16e
JB		 18165 break;
18166
18167 case 'd':
18168 /* Leave data alone. */
18169 break;
18170 }
99059e56
RM		 18171 ptr = end;
18172 }
e489d0ae 18173 }
8e3de13a 18174
93204d3a 18175 free (map);
47b2e99c 18176 arm_data->mapcount = -1;
c7b8f16e 18177 arm_data->mapsize = 0;
8e3de13a 18178 arm_data->map = NULL;
8e3de13a 18179
e489d0ae
PB		 18180 return FALSE;
18181}
18182
0beaef2b
PB		 18183/* Mangle thumb function symbols as we read them in. */
18184
8384fb8f 18185static bfd_boolean
0beaef2b
PB		 18186elf32_arm_swap_symbol_in (bfd * abfd,
18187 const void *psrc,
18188 const void *pshn,
18189 Elf_Internal_Sym *dst)
18190{
4ba2ef8f
TP		 18191 Elf_Internal_Shdr *symtab_hdr;
18192 const char *name = NULL;
18193
8384fb8f
AM		 18194 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18195 return FALSE;
39d911fc 18196 dst->st_target_internal = 0;
0beaef2b
PB		 18197
18198 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18199 the address. */
63e1a0fc
PB		 18200 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18201 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18202 {
63e1a0fc
PB		 18203 if (dst->st_value & 1)
18204 {
18205 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18206 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18207 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18208 }
18209 else
39d911fc 18210 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18211 }
18212 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18213 {
18214 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18215 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18216 }
35fc36a8 18217 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18218 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18219 else
39d911fc 18220 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18221
4ba2ef8f
TP		 18222 /* Mark CMSE special symbols. */
18223 symtab_hdr = & elf_symtab_hdr (abfd);
18224 if (symtab_hdr->sh_size)
18225 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18226 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18227 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18228
8384fb8f 18229 return TRUE;
0beaef2b
PB		 18230}
18231
18232
18233/* Mangle thumb function symbols as we write them out. */
18234
18235static void
18236elf32_arm_swap_symbol_out (bfd *abfd,
18237 const Elf_Internal_Sym *src,
18238 void *cdst,
18239 void *shndx)
18240{
18241 Elf_Internal_Sym newsym;
18242
18243 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18244 of the address set, as per the new EABI. We do this unconditionally
18245 because objcopy does not set the elf header flags until after
18246 it writes out the symbol table. */
39d911fc 18247 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18248 {
18249 newsym = *src;
34e77a92
RS		 18250 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18251 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18252 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18253 {
18254 /* Do this only for defined symbols. At link type, the static
18255 linker will simulate the work of dynamic linker of resolving
18256 symbols and will carry over the thumbness of found symbols to
18257 the output symbol table. It's not clear how it happens, but
18258 the thumbness of undefined symbols can well be different at
18259 runtime, and writing '1' for them will be confusing for users
18260 and possibly for dynamic linker itself.
18261 */
18262 newsym.st_value |= 1;
18263 }
906e58ca 18264
0beaef2b
PB		 18265 src = &newsym;
18266 }
18267 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18268}
18269
b294bdf8
MM		 18270/* Add the PT_ARM_EXIDX program header. */
18271
18272static bfd_boolean
906e58ca 18273elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18274 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18275{
18276 struct elf_segment_map *m;
18277 asection *sec;
18278
18279 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18280 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18281 {
18282 /* If there is already a PT_ARM_EXIDX header, then we do not
18283 want to add another one. This situation arises when running
18284 "strip"; the input binary already has the header. */
12bd6957 18285 m = elf_seg_map (abfd);
b294bdf8
MM		 18286 while (m && m->p_type != PT_ARM_EXIDX)
18287 m = m->next;
18288 if (!m)
18289 {
21d799b5 18290 m = (struct elf_segment_map *)
99059e56 18291 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18292 if (m == NULL)
18293 return FALSE;
18294 m->p_type = PT_ARM_EXIDX;
18295 m->count = 1;
18296 m->sections[0] = sec;
18297
12bd6957
AM		 18298 m->next = elf_seg_map (abfd);
18299 elf_seg_map (abfd) = m;
b294bdf8
MM		 18300 }
18301 }
18302
18303 return TRUE;
18304}
18305
18306/* We may add a PT_ARM_EXIDX program header. */
18307
18308static int
a6b96beb
AM		 18309elf32_arm_additional_program_headers (bfd *abfd,
18310 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18311{
18312 asection *sec;
18313
18314 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18315 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18316 return 1;
18317 else
18318 return 0;
18319}
18320
34e77a92
RS		 18321/* Hook called by the linker routine which adds symbols from an object
18322 file. */
18323
18324static bfd_boolean
18325elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18326 Elf_Internal_Sym *sym, const char **namep,
18327 flagword *flagsp, asection **secp, bfd_vma *valp)
18328{
a43942db 18329 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18330 && (abfd->flags & DYNAMIC) == 0
18331 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18332 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18333
c792917c
NC		 18334 if (elf32_arm_hash_table (info) == NULL)
18335 return FALSE;
18336
34e77a92
RS		 18337 if (elf32_arm_hash_table (info)->vxworks_p
18338 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18339 flagsp, secp, valp))
18340 return FALSE;
18341
18342 return TRUE;
18343}
18344
0beaef2b 18345/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18346const struct elf_size_info elf32_arm_size_info =
18347{
0beaef2b
PB		 18348 sizeof (Elf32_External_Ehdr),
18349 sizeof (Elf32_External_Phdr),
18350 sizeof (Elf32_External_Shdr),
18351 sizeof (Elf32_External_Rel),
18352 sizeof (Elf32_External_Rela),
18353 sizeof (Elf32_External_Sym),
18354 sizeof (Elf32_External_Dyn),
18355 sizeof (Elf_External_Note),
18356 4,
18357 1,
18358 32, 2,
18359 ELFCLASS32, EV_CURRENT,
18360 bfd_elf32_write_out_phdrs,
18361 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18362 bfd_elf32_checksum_contents,
0beaef2b
PB		 18363 bfd_elf32_write_relocs,
18364 elf32_arm_swap_symbol_in,
18365 elf32_arm_swap_symbol_out,
18366 bfd_elf32_slurp_reloc_table,
18367 bfd_elf32_slurp_symbol_table,
18368 bfd_elf32_swap_dyn_in,
18369 bfd_elf32_swap_dyn_out,
18370 bfd_elf32_swap_reloc_in,
18371 bfd_elf32_swap_reloc_out,
18372 bfd_elf32_swap_reloca_in,
18373 bfd_elf32_swap_reloca_out
18374};
18375
685e70ae
VK		 18376static bfd_vma
18377read_code32 (const bfd *abfd, const bfd_byte *addr)
18378{
18379 /* V7 BE8 code is always little endian. */
18380 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18381 return bfd_getl32 (addr);
18382
18383 return bfd_get_32 (abfd, addr);
18384}
18385
18386static bfd_vma
18387read_code16 (const bfd *abfd, const bfd_byte *addr)
18388{
18389 /* V7 BE8 code is always little endian. */
18390 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18391 return bfd_getl16 (addr);
18392
18393 return bfd_get_16 (abfd, addr);
18394}
18395
6a631e86
YG		 18396/* Return size of plt0 entry starting at ADDR
18397 or (bfd_vma) -1 if size can not be determined. */
18398
18399static bfd_vma
18400elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
18401{
18402 bfd_vma first_word;
18403 bfd_vma plt0_size;
18404
685e70ae 18405 first_word = read_code32 (abfd, addr);
6a631e86
YG		 18406
18407 if (first_word == elf32_arm_plt0_entry[0])
18408 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
18409 else if (first_word == elf32_thumb2_plt0_entry[0])
18410 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
18411 else
18412 /* We don't yet handle this PLT format. */
18413 return (bfd_vma) -1;
18414
18415 return plt0_size;
18416}
18417
18418/* Return size of plt entry starting at offset OFFSET
18419 of plt section located at address START
18420 or (bfd_vma) -1 if size can not be determined. */
18421
18422static bfd_vma
18423elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
18424{
18425 bfd_vma first_insn;
18426 bfd_vma plt_size = 0;
18427 const bfd_byte *addr = start + offset;
18428
18429 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 18430 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 18431 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
18432
18433 /* Respect Thumb stub if necessary. */
685e70ae 18434 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 18435 {
18436 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
18437 }
18438
18439 /* Strip immediate from first add. */
685e70ae 18440 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 18441
18442#ifdef FOUR_WORD_PLT
18443 if (first_insn == elf32_arm_plt_entry[0])
18444 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
18445#else
18446 if (first_insn == elf32_arm_plt_entry_long[0])
18447 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
18448 else if (first_insn == elf32_arm_plt_entry_short[0])
18449 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
18450#endif
18451 else
18452 /* We don't yet handle this PLT format. */
18453 return (bfd_vma) -1;
18454
18455 return plt_size;
18456}
18457
18458/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
18459
18460static long
18461elf32_arm_get_synthetic_symtab (bfd *abfd,
18462 long symcount ATTRIBUTE_UNUSED,
18463 asymbol **syms ATTRIBUTE_UNUSED,
18464 long dynsymcount,
18465 asymbol **dynsyms,
18466 asymbol **ret)
18467{
18468 asection *relplt;
18469 asymbol *s;
18470 arelent *p;
18471 long count, i, n;
18472 size_t size;
18473 Elf_Internal_Shdr *hdr;
18474 char *names;
18475 asection *plt;
18476 bfd_vma offset;
18477 bfd_byte *data;
18478
18479 *ret = NULL;
18480
18481 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
18482 return 0;
18483
18484 if (dynsymcount <= 0)
18485 return 0;
18486
18487 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
18488 if (relplt == NULL)
18489 return 0;
18490
18491 hdr = &elf_section_data (relplt)->this_hdr;
18492 if (hdr->sh_link != elf_dynsymtab (abfd)
18493 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
18494 return 0;
18495
18496 plt = bfd_get_section_by_name (abfd, ".plt");
18497 if (plt == NULL)
18498 return 0;
18499
18500 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
18501 return -1;
18502
18503 data = plt->contents;
18504 if (data == NULL)
18505 {
18506 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
18507 return -1;
18508 bfd_cache_section_contents((asection *) plt, data);
18509 }
18510
18511 count = relplt->size / hdr->sh_entsize;
18512 size = count * sizeof (asymbol);
18513 p = relplt->relocation;
18514 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
18515 {
18516 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
18517 if (p->addend != 0)
18518 size += sizeof ("+0x") - 1 + 8;
18519 }
18520
18521 s = *ret = (asymbol *) bfd_malloc (size);
18522 if (s == NULL)
18523 return -1;
18524
18525 offset = elf32_arm_plt0_size (abfd, data);
18526 if (offset == (bfd_vma) -1)
18527 return -1;
18528
18529 names = (char *) (s + count);
18530 p = relplt->relocation;
18531 n = 0;
18532 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
18533 {
18534 size_t len;
18535
18536 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
18537 if (plt_size == (bfd_vma) -1)
18538 break;
18539
18540 *s = **p->sym_ptr_ptr;
18541 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
18542 we are defining a symbol, ensure one of them is set. */
18543 if ((s->flags & BSF_LOCAL) == 0)
18544 s->flags |= BSF_GLOBAL;
18545 s->flags |= BSF_SYNTHETIC;
18546 s->section = plt;
18547 s->value = offset;
18548 s->name = names;
18549 s->udata.p = NULL;
18550 len = strlen ((*p->sym_ptr_ptr)->name);
18551 memcpy (names, (*p->sym_ptr_ptr)->name, len);
18552 names += len;
18553 if (p->addend != 0)
18554 {
18555 char buf[30], *a;
18556
18557 memcpy (names, "+0x", sizeof ("+0x") - 1);
18558 names += sizeof ("+0x") - 1;
18559 bfd_sprintf_vma (abfd, buf, p->addend);
18560 for (a = buf; *a == '0'; ++a)
18561 ;
18562 len = strlen (a);
18563 memcpy (names, a, len);
18564 names += len;
18565 }
18566 memcpy (names, "@plt", sizeof ("@plt"));
18567 names += sizeof ("@plt");
18568 ++s, ++n;
18569 offset += plt_size;
18570 }
18571
18572 return n;
18573}
18574
ac4c9b04
MG		 18575static bfd_boolean
18576elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
18577{
f0728ee3
AV		 18578 if (hdr->sh_flags & SHF_ARM_PURECODE)
18579 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 18580 return TRUE;
18581}
18582
18583static flagword
18584elf32_arm_lookup_section_flags (char *flag_name)
18585{
f0728ee3
AV		 18586 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
18587 return SHF_ARM_PURECODE;
ac4c9b04
MG		 18588
18589 return SEC_NO_FLAGS;
18590}
18591
491d01d3
YU		 18592static unsigned int
18593elf32_arm_count_additional_relocs (asection *sec)
18594{
18595 struct _arm_elf_section_data *arm_data;
18596 arm_data = get_arm_elf_section_data (sec);
18597 return arm_data->additional_reloc_count;
18598}
18599
5522f910
NC		 18600/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
18601 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
18602 FALSE otherwise. ISECTION is the best guess matching section from the
18603 input bfd IBFD, but it might be NULL. */
18604
18605static bfd_boolean
18606elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
18607 bfd *obfd ATTRIBUTE_UNUSED,
18608 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
18609 Elf_Internal_Shdr *osection)
18610{
18611 switch (osection->sh_type)
18612 {
18613 case SHT_ARM_EXIDX:
18614 {
18615 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
18616 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
18617 unsigned i = 0;
18618
18619 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
18620 osection->sh_info = 0;
18621
18622 /* The sh_link field must be set to the text section associated with
18623 this index section. Unfortunately the ARM EHABI does not specify
18624 exactly how to determine this association. Our caller does try
18625 to match up OSECTION with its corresponding input section however
18626 so that is a good first guess. */
18627 if (isection != NULL
18628 && osection->bfd_section != NULL
18629 && isection->bfd_section != NULL
18630 && isection->bfd_section->output_section != NULL
18631 && isection->bfd_section->output_section == osection->bfd_section
18632 && iheaders != NULL
18633 && isection->sh_link > 0
18634 && isection->sh_link < elf_numsections (ibfd)
18635 && iheaders[isection->sh_link]->bfd_section != NULL
18636 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
18637 )
18638 {
18639 for (i = elf_numsections (obfd); i-- > 0;)
18640 if (oheaders[i]->bfd_section
18641 == iheaders[isection->sh_link]->bfd_section->output_section)
18642 break;
18643 }
18644
18645 if (i == 0)
18646 {
18647 /* Failing that we have to find a matching section ourselves. If
18648 we had the output section name available we could compare that
18649 with input section names. Unfortunately we don't. So instead
18650 we use a simple heuristic and look for the nearest executable
18651 section before this one. */
18652 for (i = elf_numsections (obfd); i-- > 0;)
18653 if (oheaders[i] == osection)
18654 break;
18655 if (i == 0)
18656 break;
18657
18658 while (i-- > 0)
18659 if (oheaders[i]->sh_type == SHT_PROGBITS
18660 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
18661 == (SHF_ALLOC | SHF_EXECINSTR))
18662 break;
18663 }
18664
18665 if (i)
18666 {
18667 osection->sh_link = i;
18668 /* If the text section was part of a group
18669 then the index section should be too. */
18670 if (oheaders[i]->sh_flags & SHF_GROUP)
18671 osection->sh_flags |= SHF_GROUP;
18672 return TRUE;
18673 }
18674 }
18675 break;
18676
18677 case SHT_ARM_PREEMPTMAP:
18678 osection->sh_flags = SHF_ALLOC;
18679 break;
18680
18681 case SHT_ARM_ATTRIBUTES:
18682 case SHT_ARM_DEBUGOVERLAY:
18683 case SHT_ARM_OVERLAYSECTION:
18684 default:
18685 break;
18686 }
18687
18688 return FALSE;
18689}
18690
d691934d
NC		 18691/* Returns TRUE if NAME is an ARM mapping symbol.
18692 Traditionally the symbols $a, $d and $t have been used.
18693 The ARM ELF standard also defines $x (for A64 code). It also allows a
18694 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
18695 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
18696 not support them here. $t.x indicates the start of ThumbEE instructions. */
18697
18698static bfd_boolean
18699is_arm_mapping_symbol (const char * name)
18700{
18701 return name != NULL /* Paranoia. */
18702 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
18703 the mapping symbols could have acquired a prefix.
18704 We do not support this here, since such symbols no
18705 longer conform to the ARM ELF ABI. */
18706 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
18707 && (name[2] == 0 || name[2] == '.');
18708 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
18709 any characters that follow the period are legal characters for the body
18710 of a symbol's name. For now we just assume that this is the case. */
18711}
18712
fca2a38f
NC		 18713/* Make sure that mapping symbols in object files are not removed via the
18714 "strip --strip-unneeded" tool. These symbols are needed in order to
18715 correctly generate interworking veneers, and for byte swapping code
18716 regions. Once an object file has been linked, it is safe to remove the
18717 symbols as they will no longer be needed. */
18718
18719static void
18720elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
18721{
18722 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 18723 && sym->section != bfd_abs_section_ptr
d691934d 18724 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 18725 sym->flags |= BSF_KEEP;
18726}
18727
5522f910
NC		 18728#undef elf_backend_copy_special_section_fields
18729#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
18730
252b5132 18731#define ELF_ARCH bfd_arch_arm
ae95ffa6 18732#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 18733#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 18734#ifdef __QNXTARGET__
18735#define ELF_MAXPAGESIZE 0x1000
18736#else
7572ca89 18737#define ELF_MAXPAGESIZE 0x10000
d0facd1b 18738#endif
b1342370 18739#define ELF_MINPAGESIZE 0x1000
24718e3b 18740#define ELF_COMMONPAGESIZE 0x1000
252b5132 18741
ba93b8ac
DJ		 18742#define bfd_elf32_mkobject elf32_arm_mkobject
18743
99e4ae17
AJ		 18744#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
18745#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 18746#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
18747#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
18748#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 18749#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 18750#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 18751#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 18752#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 18753#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 18754#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 18755#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 18756#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 18757
18758#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
18759#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 18760#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 18761#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
18762#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 18763#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 18764#define elf_backend_write_section elf32_arm_write_section
252b5132 18765#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 18766#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 18767#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
18768#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
18769#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 18770#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 18771#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 18772#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 18773#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 18774#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 18775#define elf_backend_fake_sections elf32_arm_fake_sections
18776#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 18777#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 18778#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 18779#define elf_backend_size_info elf32_arm_size_info
b294bdf8 18780#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 18781#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
18782#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
18783#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 18784#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 18785#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 18786#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 18787
18788#define elf_backend_can_refcount 1
18789#define elf_backend_can_gc_sections 1
18790#define elf_backend_plt_readonly 1
18791#define elf_backend_want_got_plt 1
18792#define elf_backend_want_plt_sym 0
18793#define elf_backend_may_use_rel_p 1
18794#define elf_backend_may_use_rela_p 0
4e7fd91e 18795#define elf_backend_default_use_rela_p 0
252b5132 18796
04f7c78d 18797#define elf_backend_got_header_size 12
b68a20d6 18798#define elf_backend_extern_protected_data 1
04f7c78d 18799
906e58ca
NC		 18800#undef elf_backend_obj_attrs_vendor
18801#define elf_backend_obj_attrs_vendor "aeabi"
18802#undef elf_backend_obj_attrs_section
18803#define elf_backend_obj_attrs_section ".ARM.attributes"
18804#undef elf_backend_obj_attrs_arg_type
18805#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
18806#undef elf_backend_obj_attrs_section_type
104d59d1 18807#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 18808#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
18809#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 18810
ac4c9b04
MG		 18811#undef elf_backend_section_flags
18812#define elf_backend_section_flags elf32_arm_section_flags
18813#undef elf_backend_lookup_section_flags_hook
18814#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
18815
252b5132 18816#include "elf32-target.h"
7f266840 18817
b38cadfb
NC		 18818/* Native Client targets. */
18819
18820#undef TARGET_LITTLE_SYM
6d00b590 18821#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 18822#undef TARGET_LITTLE_NAME
18823#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
18824#undef TARGET_BIG_SYM
6d00b590 18825#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 18826#undef TARGET_BIG_NAME
18827#define TARGET_BIG_NAME "elf32-bigarm-nacl"
18828
18829/* Like elf32_arm_link_hash_table_create -- but overrides
18830 appropriately for NaCl. */
18831
18832static struct bfd_link_hash_table *
18833elf32_arm_nacl_link_hash_table_create (bfd *abfd)
18834{
18835 struct bfd_link_hash_table *ret;
18836
18837 ret = elf32_arm_link_hash_table_create (abfd);
18838 if (ret)
18839 {
18840 struct elf32_arm_link_hash_table *htab
18841 = (struct elf32_arm_link_hash_table *) ret;
18842
18843 htab->nacl_p = 1;
18844
18845 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
18846 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
18847 }
18848 return ret;
18849}
18850
18851/* Since NaCl doesn't use the ARM-specific unwind format, we don't
18852 really need to use elf32_arm_modify_segment_map. But we do it
18853 anyway just to reduce gratuitous differences with the stock ARM backend. */
18854
18855static bfd_boolean
18856elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
18857{
18858 return (elf32_arm_modify_segment_map (abfd, info)
18859 && nacl_modify_segment_map (abfd, info));
18860}
18861
887badb3
RM		 18862static void
18863elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
18864{
18865 elf32_arm_final_write_processing (abfd, linker);
18866 nacl_final_write_processing (abfd, linker);
18867}
18868
6a631e86
YG		 18869static bfd_vma
18870elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
18871 const arelent *rel ATTRIBUTE_UNUSED)
18872{
18873 return plt->vma
18874 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
18875 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
18876}
887badb3 18877
b38cadfb 18878#undef elf32_bed
6a631e86 18879#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 18880#undef bfd_elf32_bfd_link_hash_table_create
18881#define bfd_elf32_bfd_link_hash_table_create \
18882 elf32_arm_nacl_link_hash_table_create
18883#undef elf_backend_plt_alignment
6a631e86 18884#define elf_backend_plt_alignment 4
b38cadfb
NC		 18885#undef elf_backend_modify_segment_map
18886#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
18887#undef elf_backend_modify_program_headers
18888#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 18889#undef elf_backend_final_write_processing
18890#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 18891#undef bfd_elf32_get_synthetic_symtab
18892#undef elf_backend_plt_sym_val
18893#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 18894#undef elf_backend_copy_special_section_fields
b38cadfb 18895
887badb3
RM		 18896#undef ELF_MINPAGESIZE
18897#undef ELF_COMMONPAGESIZE
18898
b38cadfb
NC		 18899
18900#include "elf32-target.h"
18901
18902/* Reset to defaults. */
18903#undef elf_backend_plt_alignment
18904#undef elf_backend_modify_segment_map
18905#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
18906#undef elf_backend_modify_program_headers
887badb3
RM		 18907#undef elf_backend_final_write_processing
18908#define elf_backend_final_write_processing elf32_arm_final_write_processing
18909#undef ELF_MINPAGESIZE
18910#define ELF_MINPAGESIZE 0x1000
18911#undef ELF_COMMONPAGESIZE
18912#define ELF_COMMONPAGESIZE 0x1000
18913
b38cadfb 18914
906e58ca 18915/* VxWorks Targets. */
4e7fd91e 18916
906e58ca 18917#undef TARGET_LITTLE_SYM
6d00b590 18918#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 18919#undef TARGET_LITTLE_NAME
4e7fd91e 18920#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 18921#undef TARGET_BIG_SYM
6d00b590 18922#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 18923#undef TARGET_BIG_NAME
4e7fd91e
PB		 18924#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
18925
18926/* Like elf32_arm_link_hash_table_create -- but overrides
18927 appropriately for VxWorks. */
906e58ca 18928
4e7fd91e
PB		 18929static struct bfd_link_hash_table *
18930elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
18931{
18932 struct bfd_link_hash_table *ret;
18933
18934 ret = elf32_arm_link_hash_table_create (abfd);
18935 if (ret)
18936 {
18937 struct elf32_arm_link_hash_table *htab
00a97672 18938 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 18939 htab->use_rel = 0;
00a97672 18940 htab->vxworks_p = 1;
4e7fd91e
PB		 18941 }
18942 return ret;
906e58ca 18943}
4e7fd91e 18944
00a97672
RS		 18945static void
18946elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
18947{
18948 elf32_arm_final_write_processing (abfd, linker);
18949 elf_vxworks_final_write_processing (abfd, linker);
18950}
18951
906e58ca 18952#undef elf32_bed
4e7fd91e
PB		 18953#define elf32_bed elf32_arm_vxworks_bed
18954
906e58ca
NC		 18955#undef bfd_elf32_bfd_link_hash_table_create
18956#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 18957#undef elf_backend_final_write_processing
18958#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
18959#undef elf_backend_emit_relocs
18960#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 18961
906e58ca 18962#undef elf_backend_may_use_rel_p
00a97672 18963#define elf_backend_may_use_rel_p 0
906e58ca 18964#undef elf_backend_may_use_rela_p
00a97672 18965#define elf_backend_may_use_rela_p 1
906e58ca 18966#undef elf_backend_default_use_rela_p
00a97672 18967#define elf_backend_default_use_rela_p 1
906e58ca 18968#undef elf_backend_want_plt_sym
00a97672 18969#define elf_backend_want_plt_sym 1
906e58ca 18970#undef ELF_MAXPAGESIZE
00a97672 18971#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 18972
18973#include "elf32-target.h"
18974
18975
21d799b5
NC		 18976/* Merge backend specific data from an object file to the output
18977 object file when linking. */
18978
18979static bfd_boolean
18980elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
18981{
18982 flagword out_flags;
18983 flagword in_flags;
18984 bfd_boolean flags_compatible = TRUE;
18985 asection *sec;
18986
cc643b88 18987 /* Check if we have the same endianness. */
21d799b5
NC		 18988 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
18989 return FALSE;
18990
18991 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
18992 return TRUE;
18993
18994 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
18995 return FALSE;
18996
18997 /* The input BFD must have had its flags initialised. */
18998 /* The following seems bogus to me -- The flags are initialized in
18999 the assembler but I don't think an elf_flags_init field is
19000 written into the object. */
19001 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19002
19003 in_flags = elf_elfheader (ibfd)->e_flags;
19004 out_flags = elf_elfheader (obfd)->e_flags;
19005
19006 /* In theory there is no reason why we couldn't handle this. However
19007 in practice it isn't even close to working and there is no real
19008 reason to want it. */
19009 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19010 && !(ibfd->flags & DYNAMIC)
19011 && (in_flags & EF_ARM_BE8))
19012 {
19013 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19014 ibfd);
19015 return FALSE;
19016 }
19017
19018 if (!elf_flags_init (obfd))
19019 {
19020 /* If the input is the default architecture and had the default
19021 flags then do not bother setting the flags for the output
19022 architecture, instead allow future merges to do this. If no
19023 future merges ever set these flags then they will retain their
99059e56
RM		 19024 uninitialised values, which surprise surprise, correspond
19025 to the default values. */
21d799b5
NC		 19026 if (bfd_get_arch_info (ibfd)->the_default
19027 && elf_elfheader (ibfd)->e_flags == 0)
19028 return TRUE;
19029
19030 elf_flags_init (obfd) = TRUE;
19031 elf_elfheader (obfd)->e_flags = in_flags;
19032
19033 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19034 && bfd_get_arch_info (obfd)->the_default)
19035 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19036
19037 return TRUE;
19038 }
19039
19040 /* Determine what should happen if the input ARM architecture
19041 does not match the output ARM architecture. */
19042 if (! bfd_arm_merge_machines (ibfd, obfd))
19043 return FALSE;
19044
19045 /* Identical flags must be compatible. */
19046 if (in_flags == out_flags)
19047 return TRUE;
19048
19049 /* Check to see if the input BFD actually contains any sections. If
19050 not, its flags may not have been initialised either, but it
19051 cannot actually cause any incompatiblity. Do not short-circuit
19052 dynamic objects; their section list may be emptied by
19053 elf_link_add_object_symbols.
19054
19055 Also check to see if there are no code sections in the input.
19056 In this case there is no need to check for code specific flags.
19057 XXX - do we need to worry about floating-point format compatability
19058 in data sections ? */
19059 if (!(ibfd->flags & DYNAMIC))
19060 {
19061 bfd_boolean null_input_bfd = TRUE;
19062 bfd_boolean only_data_sections = TRUE;
19063
19064 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19065 {
19066 /* Ignore synthetic glue sections. */
19067 if (strcmp (sec->name, ".glue_7")
19068 && strcmp (sec->name, ".glue_7t"))
19069 {
19070 if ((bfd_get_section_flags (ibfd, sec)
19071 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19072 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19073 only_data_sections = FALSE;
21d799b5
NC		 19074
19075 null_input_bfd = FALSE;
19076 break;
19077 }
19078 }
19079
19080 if (null_input_bfd || only_data_sections)
19081 return TRUE;
19082 }
19083
19084 /* Complain about various flag mismatches. */
19085 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19086 EF_ARM_EABI_VERSION (out_flags)))
19087 {
19088 _bfd_error_handler
19089 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
19090 ibfd, obfd,
19091 (in_flags & EF_ARM_EABIMASK) >> 24,
19092 (out_flags & EF_ARM_EABIMASK) >> 24);
19093 return FALSE;
19094 }
19095
19096 /* Not sure what needs to be checked for EABI versions >= 1. */
19097 /* VxWorks libraries do not use these flags. */
19098 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19099 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19100 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19101 {
19102 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19103 {
19104 _bfd_error_handler
19105 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
19106 ibfd, obfd,
19107 in_flags & EF_ARM_APCS_26 ? 26 : 32,
19108 out_flags & EF_ARM_APCS_26 ? 26 : 32);
19109 flags_compatible = FALSE;
19110 }
19111
19112 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19113 {
19114 if (in_flags & EF_ARM_APCS_FLOAT)
19115 _bfd_error_handler
19116 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19117 ibfd, obfd);
19118 else
19119 _bfd_error_handler
19120 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19121 ibfd, obfd);
19122
19123 flags_compatible = FALSE;
19124 }
19125
19126 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19127 {
19128 if (in_flags & EF_ARM_VFP_FLOAT)
19129 _bfd_error_handler
19130 (_("error: %B uses VFP instructions, whereas %B does not"),
19131 ibfd, obfd);
19132 else
19133 _bfd_error_handler
19134 (_("error: %B uses FPA instructions, whereas %B does not"),
19135 ibfd, obfd);
19136
19137 flags_compatible = FALSE;
19138 }
19139
19140 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19141 {
19142 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19143 _bfd_error_handler
19144 (_("error: %B uses Maverick instructions, whereas %B does not"),
19145 ibfd, obfd);
19146 else
19147 _bfd_error_handler
19148 (_("error: %B does not use Maverick instructions, whereas %B does"),
19149 ibfd, obfd);
19150
19151 flags_compatible = FALSE;
19152 }
19153
19154#ifdef EF_ARM_SOFT_FLOAT
19155 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19156 {
19157 /* We can allow interworking between code that is VFP format
19158 layout, and uses either soft float or integer regs for
19159 passing floating point arguments and results. We already
19160 know that the APCS_FLOAT flags match; similarly for VFP
19161 flags. */
19162 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19163 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19164 {
19165 if (in_flags & EF_ARM_SOFT_FLOAT)
19166 _bfd_error_handler
19167 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19168 ibfd, obfd);
19169 else
19170 _bfd_error_handler
19171 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19172 ibfd, obfd);
19173
19174 flags_compatible = FALSE;
19175 }
19176 }
19177#endif
19178
19179 /* Interworking mismatch is only a warning. */
19180 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19181 {
19182 if (in_flags & EF_ARM_INTERWORK)
19183 {
19184 _bfd_error_handler
19185 (_("Warning: %B supports interworking, whereas %B does not"),
19186 ibfd, obfd);
19187 }
19188 else
19189 {
19190 _bfd_error_handler
19191 (_("Warning: %B does not support interworking, whereas %B does"),
19192 ibfd, obfd);
19193 }
19194 }
19195 }
19196
19197 return flags_compatible;
19198}
19199
19200
906e58ca 19201/* Symbian OS Targets. */
7f266840 19202
906e58ca 19203#undef TARGET_LITTLE_SYM
6d00b590 19204#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19205#undef TARGET_LITTLE_NAME
7f266840 19206#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19207#undef TARGET_BIG_SYM
6d00b590 19208#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19209#undef TARGET_BIG_NAME
7f266840
DJ		 19210#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19211
19212/* Like elf32_arm_link_hash_table_create -- but overrides
19213 appropriately for Symbian OS. */
906e58ca 19214
7f266840
DJ		 19215static struct bfd_link_hash_table *
19216elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19217{
19218 struct bfd_link_hash_table *ret;
19219
19220 ret = elf32_arm_link_hash_table_create (abfd);
19221 if (ret)
19222 {
19223 struct elf32_arm_link_hash_table *htab
19224 = (struct elf32_arm_link_hash_table *)ret;
19225 /* There is no PLT header for Symbian OS. */
19226 htab->plt_header_size = 0;
95720a86
DJ		 19227 /* The PLT entries are each one instruction and one word. */
19228 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19229 htab->symbian_p = 1;
33bfe774
JB		 19230 /* Symbian uses armv5t or above, so use_blx is always true. */
19231 htab->use_blx = 1;
67687978 19232 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19233 }
19234 return ret;
906e58ca 19235}
7f266840 19236
b35d266b 19237static const struct bfd_elf_special_section
551b43fd 19238elf32_arm_symbian_special_sections[] =
7f266840 19239{
5cd3778d
MM		 19240 /* In a BPABI executable, the dynamic linking sections do not go in
19241 the loadable read-only segment. The post-linker may wish to
19242 refer to these sections, but they are not part of the final
19243 program image. */
0112cd26
NC		 19244 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19245 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19246 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19247 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19248 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19249 /* These sections do not need to be writable as the SymbianOS
19250 postlinker will arrange things so that no dynamic relocation is
19251 required. */
0112cd26
NC		 19252 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19253 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19254 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19255 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19256};
19257
c3c76620 19258static void
906e58ca 19259elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19260 struct bfd_link_info *link_info)
c3c76620
MM		 19261{
19262 /* BPABI objects are never loaded directly by an OS kernel; they are
19263 processed by a postlinker first, into an OS-specific format. If
19264 the D_PAGED bit is set on the file, BFD will align segments on
19265 page boundaries, so that an OS can directly map the file. With
19266 BPABI objects, that just results in wasted space. In addition,
19267 because we clear the D_PAGED bit, map_sections_to_segments will
19268 recognize that the program headers should not be mapped into any
19269 loadable segment. */
19270 abfd->flags &= ~D_PAGED;
906e58ca 19271 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19272}
7f266840
DJ		 19273
19274static bfd_boolean
906e58ca 19275elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19276 struct bfd_link_info *info)
7f266840
DJ		 19277{
19278 struct elf_segment_map *m;
19279 asection *dynsec;
19280
7f266840
DJ		 19281 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19282 segment. However, because the .dynamic section is not marked
19283 with SEC_LOAD, the generic ELF code will not create such a
19284 segment. */
19285 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19286 if (dynsec)
19287 {
12bd6957 19288 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19289 if (m->p_type == PT_DYNAMIC)
19290 break;
19291
19292 if (m == NULL)
19293 {
19294 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19295 m->next = elf_seg_map (abfd);
19296 elf_seg_map (abfd) = m;
8ded5a0f 19297 }
7f266840
DJ		 19298 }
19299
b294bdf8
MM		 19300 /* Also call the generic arm routine. */
19301 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19302}
19303
95720a86
DJ		 19304/* Return address for Ith PLT stub in section PLT, for relocation REL
19305 or (bfd_vma) -1 if it should not be included. */
19306
19307static bfd_vma
19308elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19309 const arelent *rel ATTRIBUTE_UNUSED)
19310{
19311 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19312}
19313
8029a119 19314#undef elf32_bed
7f266840
DJ		 19315#define elf32_bed elf32_arm_symbian_bed
19316
19317/* The dynamic sections are not allocated on SymbianOS; the postlinker
19318 will process them and then discard them. */
906e58ca 19319#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19320#define ELF_DYNAMIC_SEC_FLAGS \
19321 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19322
00a97672 19323#undef elf_backend_emit_relocs
c3c76620 19324
906e58ca
NC		 19325#undef bfd_elf32_bfd_link_hash_table_create
19326#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19327#undef elf_backend_special_sections
19328#define elf_backend_special_sections elf32_arm_symbian_special_sections
19329#undef elf_backend_begin_write_processing
19330#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19331#undef elf_backend_final_write_processing
19332#define elf_backend_final_write_processing elf32_arm_final_write_processing
19333
19334#undef elf_backend_modify_segment_map
7f266840
DJ		 19335#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19336
19337/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19338#undef elf_backend_got_header_size
7f266840
DJ		 19339#define elf_backend_got_header_size 0
19340
19341/* Similarly, there is no .got.plt section. */
906e58ca 19342#undef elf_backend_want_got_plt
7f266840
DJ		 19343#define elf_backend_want_got_plt 0
19344
906e58ca 19345#undef elf_backend_plt_sym_val
95720a86
DJ		 19346#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19347
906e58ca 19348#undef elf_backend_may_use_rel_p
00a97672 19349#define elf_backend_may_use_rel_p 1
906e58ca 19350#undef elf_backend_may_use_rela_p
00a97672 19351#define elf_backend_may_use_rela_p 0
906e58ca 19352#undef elf_backend_default_use_rela_p
00a97672 19353#define elf_backend_default_use_rela_p 0
906e58ca 19354#undef elf_backend_want_plt_sym
00a97672 19355#define elf_backend_want_plt_sym 0
906e58ca 19356#undef ELF_MAXPAGESIZE
00a97672 19357#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19358
7f266840 19359#include "elf32-target.h"
GDB Binutils - Deliverables
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