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Set debug registers on all threads belonging to the current inferior.
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
252b5132
RH		 2141/* The name of the dynamic interpreter. This is put in the .interp
2142 section. */
2143#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2144
0855e32b 2145static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2146{
2147 0xe08e0000, /* add r0, lr, r0 */
2148 0xe5901004, /* ldr r1, [r0,#4] */
2149 0xe12fff11, /* bx r1 */
2150};
0855e32b
NS		 2151
2152static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2153{
2154 0xe52d2004, /* push {r2} */
2155 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2156 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2157 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2158 0xe081100f, /* 2: add r1, pc */
2159 0xe12fff12, /* bx r2 */
2160 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2161 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2162 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2163};
0855e32b 2164
5e681ec4
PB		 2165#ifdef FOUR_WORD_PLT
2166
252b5132
RH		 2167/* The first entry in a procedure linkage table looks like
2168 this. It is set up so that any shared library function that is
59f2c4e7 2169 called before the relocation has been set up calls the dynamic
9b485d32 2170 linker first. */
e5a52504 2171static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2172{
2173 0xe52de004, /* str lr, [sp, #-4]! */
2174 0xe59fe010, /* ldr lr, [pc, #16] */
2175 0xe08fe00e, /* add lr, pc, lr */
2176 0xe5bef008, /* ldr pc, [lr, #8]! */
2177};
5e681ec4
PB		 2178
2179/* Subsequent entries in a procedure linkage table look like
2180 this. */
e5a52504 2181static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2182{
2183 0xe28fc600, /* add ip, pc, #NN */
2184 0xe28cca00, /* add ip, ip, #NN */
2185 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2186 0x00000000, /* unused */
2187};
5e681ec4 2188
eed94f8f 2189#else /* not FOUR_WORD_PLT */
5e681ec4 2190
5e681ec4
PB		 2191/* The first entry in a procedure linkage table looks like
2192 this. It is set up so that any shared library function that is
2193 called before the relocation has been set up calls the dynamic
2194 linker first. */
e5a52504 2195static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2196{
2197 0xe52de004, /* str lr, [sp, #-4]! */
2198 0xe59fe004, /* ldr lr, [pc, #4] */
2199 0xe08fe00e, /* add lr, pc, lr */
2200 0xe5bef008, /* ldr pc, [lr, #8]! */
2201 0x00000000, /* &GOT[0] - . */
2202};
252b5132 2203
1db37fe6
YG		 2204/* By default subsequent entries in a procedure linkage table look like
2205 this. Offsets that don't fit into 28 bits will cause link error. */
2206static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2207{
2208 0xe28fc600, /* add ip, pc, #0xNN00000 */
2209 0xe28cca00, /* add ip, ip, #0xNN000 */
2210 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2211};
5e681ec4 2212
1db37fe6
YG		 2213/* When explicitly asked, we'll use this "long" entry format
2214 which can cope with arbitrary displacements. */
2215static const bfd_vma elf32_arm_plt_entry_long [] =
2216{
2217 0xe28fc200, /* add ip, pc, #0xN0000000 */
2218 0xe28cc600, /* add ip, ip, #0xNN00000 */
2219 0xe28cca00, /* add ip, ip, #0xNN000 */
2220 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2221};
2222
2223static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2224
eed94f8f
NC		 2225#endif /* not FOUR_WORD_PLT */
2226
2227/* The first entry in a procedure linkage table looks like this.
2228 It is set up so that any shared library function that is called before the
2229 relocation has been set up calls the dynamic linker first. */
2230static const bfd_vma elf32_thumb2_plt0_entry [] =
2231{
2232 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2233 an instruction maybe encoded to one or two array elements. */
2234 0xf8dfb500, /* push {lr} */
2235 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2236 /* add lr, pc */
eed94f8f
NC		 2237 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2238 0x00000000, /* &GOT[0] - . */
2239};
2240
2241/* Subsequent entries in a procedure linkage table for thumb only target
2242 look like this. */
2243static const bfd_vma elf32_thumb2_plt_entry [] =
2244{
2245 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2246 an instruction maybe encoded to one or two array elements. */
2247 0x0c00f240, /* movw ip, #0xNNNN */
2248 0x0c00f2c0, /* movt ip, #0xNNNN */
2249 0xf8dc44fc, /* add ip, pc */
2250 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2251 /* nop */
eed94f8f 2252};
252b5132 2253
00a97672
RS		 2254/* The format of the first entry in the procedure linkage table
2255 for a VxWorks executable. */
2256static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2257{
2258 0xe52dc008, /* str ip,[sp,#-8]! */
2259 0xe59fc000, /* ldr ip,[pc] */
2260 0xe59cf008, /* ldr pc,[ip,#8] */
2261 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2262};
00a97672
RS		 2263
2264/* The format of subsequent entries in a VxWorks executable. */
2265static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2266{
2267 0xe59fc000, /* ldr ip,[pc] */
2268 0xe59cf000, /* ldr pc,[ip] */
2269 0x00000000, /* .long @got */
2270 0xe59fc000, /* ldr ip,[pc] */
2271 0xea000000, /* b _PLT */
2272 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2273};
00a97672
RS		 2274
2275/* The format of entries in a VxWorks shared library. */
2276static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2277{
2278 0xe59fc000, /* ldr ip,[pc] */
2279 0xe79cf009, /* ldr pc,[ip,r9] */
2280 0x00000000, /* .long @got */
2281 0xe59fc000, /* ldr ip,[pc] */
2282 0xe599f008, /* ldr pc,[r9,#8] */
2283 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2284};
00a97672 2285
b7693d02
DJ		 2286/* An initial stub used if the PLT entry is referenced from Thumb code. */
2287#define PLT_THUMB_STUB_SIZE 4
2288static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2289{
2290 0x4778, /* bx pc */
2291 0x46c0 /* nop */
2292};
b7693d02 2293
e5a52504
MM		 2294/* The entries in a PLT when using a DLL-based target with multiple
2295 address spaces. */
906e58ca 2296static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2297{
2298 0xe51ff004, /* ldr pc, [pc, #-4] */
2299 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2300};
2301
2302/* The first entry in a procedure linkage table looks like
2303 this. It is set up so that any shared library function that is
2304 called before the relocation has been set up calls the dynamic
2305 linker first. */
2306static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2307{
2308 /* First bundle: */
2309 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2310 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2311 0xe08cc00f, /* add ip, ip, pc */
2312 0xe52dc008, /* str ip, [sp, #-8]! */
2313 /* Second bundle: */
edccdf7c
RM		 2314 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2315 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2316 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2317 0xe12fff1c, /* bx ip */
b38cadfb 2318 /* Third bundle: */
edccdf7c
RM		 2319 0xe320f000, /* nop */
2320 0xe320f000, /* nop */
2321 0xe320f000, /* nop */
b38cadfb
NC		 2322 /* .Lplt_tail: */
2323 0xe50dc004, /* str ip, [sp, #-4] */
2324 /* Fourth bundle: */
edccdf7c
RM		 2325 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2326 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2327 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2328 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2329};
2330#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2331
2332/* Subsequent entries in a procedure linkage table look like this. */
2333static const bfd_vma elf32_arm_nacl_plt_entry [] =
2334{
2335 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2336 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2337 0xe08cc00f, /* add ip, ip, pc */
2338 0xea000000, /* b .Lplt_tail */
2339};
e5a52504 2340
906e58ca
NC		 2341#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2342#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2343#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2344#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2345#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2346#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2347#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2348#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2349
461a49ca 2350enum stub_insn_type
b38cadfb
NC		 2351{
2352 THUMB16_TYPE = 1,
2353 THUMB32_TYPE,
2354 ARM_TYPE,
2355 DATA_TYPE
2356};
461a49ca 2357
48229727
JB		 2358#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2359/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2360 is inserted in arm_build_one_stub(). */
2361#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2362#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2363#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2364#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2365#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2366#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2367
2368typedef struct
2369{
b38cadfb
NC		 2370 bfd_vma data;
2371 enum stub_insn_type type;
2372 unsigned int r_type;
2373 int reloc_addend;
461a49ca
DJ		 2374} insn_sequence;
2375
fea2b4d6
CL		 2376/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2377 to reach the stub if necessary. */
461a49ca 2378static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2379{
2380 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2381 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2382};
906e58ca 2383
fea2b4d6
CL		 2384/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2385 available. */
461a49ca 2386static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2387{
2388 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2389 ARM_INSN (0xe12fff1c), /* bx ip */
2390 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2391};
906e58ca 2392
d3626fb0 2393/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2394static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2395{
2396 THUMB16_INSN (0xb401), /* push {r0} */
2397 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2398 THUMB16_INSN (0x4684), /* mov ip, r0 */
2399 THUMB16_INSN (0xbc01), /* pop {r0} */
2400 THUMB16_INSN (0x4760), /* bx ip */
2401 THUMB16_INSN (0xbf00), /* nop */
2402 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2403};
906e58ca 2404
80c135e5
TP		 2405/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2406static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2407{
2408 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2409 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2410};
2411
d3626fb0
CL		 2412/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2413 allowed. */
2414static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2415{
2416 THUMB16_INSN (0x4778), /* bx pc */
2417 THUMB16_INSN (0x46c0), /* nop */
2418 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2419 ARM_INSN (0xe12fff1c), /* bx ip */
2420 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2421};
d3626fb0 2422
fea2b4d6
CL		 2423/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2424 available. */
461a49ca 2425static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2426{
2427 THUMB16_INSN (0x4778), /* bx pc */
2428 THUMB16_INSN (0x46c0), /* nop */
2429 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2430 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2431};
906e58ca 2432
fea2b4d6
CL		 2433/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2434 one, when the destination is close enough. */
461a49ca 2435static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2436{
2437 THUMB16_INSN (0x4778), /* bx pc */
2438 THUMB16_INSN (0x46c0), /* nop */
2439 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2440};
c820be07 2441
cf3eccff 2442/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2443 blx to reach the stub if necessary. */
cf3eccff 2444static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2445{
2446 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2447 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2448 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2449};
906e58ca 2450
cf3eccff
DJ		 2451/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2452 blx to reach the stub if necessary. We can not add into pc;
2453 it is not guaranteed to mode switch (different in ARMv6 and
2454 ARMv7). */
2455static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2456{
2457 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2458 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2459 ARM_INSN (0xe12fff1c), /* bx ip */
2460 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2461};
cf3eccff 2462
ebe24dd4
CL		 2463/* V4T ARM -> ARM long branch stub, PIC. */
2464static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2465{
2466 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2467 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2468 ARM_INSN (0xe12fff1c), /* bx ip */
2469 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2470};
ebe24dd4
CL		 2471
2472/* V4T Thumb -> ARM long branch stub, PIC. */
2473static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2474{
2475 THUMB16_INSN (0x4778), /* bx pc */
2476 THUMB16_INSN (0x46c0), /* nop */
2477 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2478 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2479 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2480};
ebe24dd4 2481
d3626fb0
CL		 2482/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2483 architectures. */
ebe24dd4 2484static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2485{
2486 THUMB16_INSN (0xb401), /* push {r0} */
2487 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2488 THUMB16_INSN (0x46fc), /* mov ip, pc */
2489 THUMB16_INSN (0x4484), /* add ip, r0 */
2490 THUMB16_INSN (0xbc01), /* pop {r0} */
2491 THUMB16_INSN (0x4760), /* bx ip */
2492 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2496 allowed. */
2497static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0x4778), /* bx pc */
2500 THUMB16_INSN (0x46c0), /* nop */
2501 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2502 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2503 ARM_INSN (0xe12fff1c), /* bx ip */
2504 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2505};
d3626fb0 2506
0855e32b
NS		 2507/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2508 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2509static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2510{
b38cadfb
NC		 2511 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2512 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2513 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2514};
2515
2516/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2517 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2518static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2519{
b38cadfb
NC		 2520 THUMB16_INSN (0x4778), /* bx pc */
2521 THUMB16_INSN (0x46c0), /* nop */
2522 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2523 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2524 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2525};
2526
7a89b94e
NC		 2527/* NaCl ARM -> ARM long branch stub. */
2528static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2529{
2530 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2531 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2532 ARM_INSN (0xe12fff1c), /* bx ip */
2533 ARM_INSN (0xe320f000), /* nop */
2534 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2535 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2536 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2537 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2538};
2539
2540/* NaCl ARM -> ARM long branch stub, PIC. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2545 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2546 ARM_INSN (0xe12fff1c), /* bx ip */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553
48229727
JB		 2554/* Cortex-A8 erratum-workaround stubs. */
2555
2556/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2557 can't use a conditional branch to reach this stub). */
2558
2559static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2560{
2561 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2562 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2563 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2564};
48229727
JB		 2565
2566/* Stub used for b.w and bl.w instructions. */
2567
2568static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2569{
2570 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2571};
48229727
JB		 2572
2573static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2574{
2575 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2576};
48229727
JB		 2577
2578/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2579 instruction (which switches to ARM mode) to point to this stub. Jump to the
2580 real destination using an ARM-mode branch. */
2581
2582static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2583{
2584 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2585};
48229727 2586
9553db3c
NC		 2587/* For each section group there can be a specially created linker section
2588 to hold the stubs for that group. The name of the stub section is based
2589 upon the name of another section within that group with the suffix below
2590 applied.
2591
2592 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2593 create what appeared to be a linker stub section when it actually
2594 contained user code/data. For example, consider this fragment:
b38cadfb 2595
9553db3c
NC		 2596 const char * stubborn_problems[] = { "np" };
2597
2598 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2599 section called:
2600
2601 .data.rel.local.stubborn_problems
2602
2603 This then causes problems in arm32_arm_build_stubs() as it triggers:
2604
2605 // Ignore non-stub sections.
2606 if (!strstr (stub_sec->name, STUB_SUFFIX))
2607 continue;
2608
2609 And so the section would be ignored instead of being processed. Hence
2610 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2611 C identifier. */
2612#define STUB_SUFFIX ".__stub"
906e58ca 2613
738a79f6
CL		 2614/* One entry per long/short branch stub defined above. */
2615#define DEF_STUBS \
2616 DEF_STUB(long_branch_any_any) \
2617 DEF_STUB(long_branch_v4t_arm_thumb) \
2618 DEF_STUB(long_branch_thumb_only) \
2619 DEF_STUB(long_branch_v4t_thumb_thumb) \
2620 DEF_STUB(long_branch_v4t_thumb_arm) \
2621 DEF_STUB(short_branch_v4t_thumb_arm) \
2622 DEF_STUB(long_branch_any_arm_pic) \
2623 DEF_STUB(long_branch_any_thumb_pic) \
2624 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2625 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2626 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2627 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2628 DEF_STUB(long_branch_any_tls_pic) \
2629 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2630 DEF_STUB(long_branch_arm_nacl) \
2631 DEF_STUB(long_branch_arm_nacl_pic) \
48229727
JB		 2632 DEF_STUB(a8_veneer_b_cond) \
2633 DEF_STUB(a8_veneer_b) \
2634 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2635 DEF_STUB(a8_veneer_blx) \
2636 DEF_STUB(long_branch_thumb2_only) \
738a79f6
CL		 2637
2638#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2639enum elf32_arm_stub_type
2640{
906e58ca 2641 arm_stub_none,
738a79f6 2642 DEF_STUBS
4f4faa4d 2643 max_stub_type
738a79f6
CL		 2644};
2645#undef DEF_STUB
2646
8d9d9490
TP		 2647/* Note the first a8_veneer type. */
2648const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2649
738a79f6
CL		 2650typedef struct
2651{
d3ce72d0 2652 const insn_sequence* template_sequence;
738a79f6
CL		 2653 int template_size;
2654} stub_def;
2655
2656#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2657static const stub_def stub_definitions[] =
2658{
738a79f6
CL		 2659 {NULL, 0},
2660 DEF_STUBS
906e58ca
NC		 2661};
2662
2663struct elf32_arm_stub_hash_entry
2664{
2665 /* Base hash table entry structure. */
2666 struct bfd_hash_entry root;
2667
2668 /* The stub section. */
2669 asection *stub_sec;
2670
2671 /* Offset within stub_sec of the beginning of this stub. */
2672 bfd_vma stub_offset;
2673
2674 /* Given the symbol's value and its section we can determine its final
2675 value when building the stubs (so the stub knows where to jump). */
2676 bfd_vma target_value;
2677 asection *target_section;
2678
8d9d9490
TP		 2679 /* Same as above but for the source of the branch to the stub. Used for
2680 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2681 such, source section does not need to be recorded since Cortex-A8 erratum
2682 workaround stubs are only generated when both source and target are in the
2683 same section. */
2684 bfd_vma source_value;
48229727
JB		 2685
2686 /* The instruction which caused this stub to be generated (only valid for
2687 Cortex-A8 erratum workaround stubs at present). */
2688 unsigned long orig_insn;
2689
461a49ca 2690 /* The stub type. */
906e58ca 2691 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2692 /* Its encoding size in bytes. */
2693 int stub_size;
2694 /* Its template. */
2695 const insn_sequence *stub_template;
2696 /* The size of the template (number of entries). */
2697 int stub_template_size;
906e58ca
NC		 2698
2699 /* The symbol table entry, if any, that this was derived from. */
2700 struct elf32_arm_link_hash_entry *h;
2701
35fc36a8
RS		 2702 /* Type of branch. */
2703 enum arm_st_branch_type branch_type;
906e58ca
NC		 2704
2705 /* Where this stub is being called from, or, in the case of combined
2706 stub sections, the first input section in the group. */
2707 asection *id_sec;
7413f23f
DJ		 2708
2709 /* The name for the local symbol at the start of this stub. The
2710 stub name in the hash table has to be unique; this does not, so
2711 it can be friendlier. */
2712 char *output_name;
906e58ca
NC		 2713};
2714
e489d0ae
PB		 2715/* Used to build a map of a section. This is required for mixed-endian
2716 code/data. */
2717
2718typedef struct elf32_elf_section_map
2719{
2720 bfd_vma vma;
2721 char type;
2722}
2723elf32_arm_section_map;
2724
c7b8f16e
JB		 2725/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2726
2727typedef enum
2728{
2729 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2730 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2731 VFP11_ERRATUM_ARM_VENEER,
2732 VFP11_ERRATUM_THUMB_VENEER
2733}
2734elf32_vfp11_erratum_type;
2735
2736typedef struct elf32_vfp11_erratum_list
2737{
2738 struct elf32_vfp11_erratum_list *next;
2739 bfd_vma vma;
2740 union
2741 {
2742 struct
2743 {
2744 struct elf32_vfp11_erratum_list *veneer;
2745 unsigned int vfp_insn;
2746 } b;
2747 struct
2748 {
2749 struct elf32_vfp11_erratum_list *branch;
2750 unsigned int id;
2751 } v;
2752 } u;
2753 elf32_vfp11_erratum_type type;
2754}
2755elf32_vfp11_erratum_list;
2756
a504d23a
LA		 2757/* Information about a STM32L4XX erratum veneer, or a branch to such a
2758 veneer. */
2759typedef enum
2760{
2761 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2762 STM32L4XX_ERRATUM_VENEER
2763}
2764elf32_stm32l4xx_erratum_type;
2765
2766typedef struct elf32_stm32l4xx_erratum_list
2767{
2768 struct elf32_stm32l4xx_erratum_list *next;
2769 bfd_vma vma;
2770 union
2771 {
2772 struct
2773 {
2774 struct elf32_stm32l4xx_erratum_list *veneer;
2775 unsigned int insn;
2776 } b;
2777 struct
2778 {
2779 struct elf32_stm32l4xx_erratum_list *branch;
2780 unsigned int id;
2781 } v;
2782 } u;
2783 elf32_stm32l4xx_erratum_type type;
2784}
2785elf32_stm32l4xx_erratum_list;
2786
2468f9c9
PB		 2787typedef enum
2788{
2789 DELETE_EXIDX_ENTRY,
2790 INSERT_EXIDX_CANTUNWIND_AT_END
2791}
2792arm_unwind_edit_type;
2793
2794/* A (sorted) list of edits to apply to an unwind table. */
2795typedef struct arm_unwind_table_edit
2796{
2797 arm_unwind_edit_type type;
2798 /* Note: we sometimes want to insert an unwind entry corresponding to a
2799 section different from the one we're currently writing out, so record the
2800 (text) section this edit relates to here. */
2801 asection *linked_section;
2802 unsigned int index;
2803 struct arm_unwind_table_edit *next;
2804}
2805arm_unwind_table_edit;
2806
8e3de13a 2807typedef struct _arm_elf_section_data
e489d0ae 2808{
2468f9c9 2809 /* Information about mapping symbols. */
e489d0ae 2810 struct bfd_elf_section_data elf;
8e3de13a 2811 unsigned int mapcount;
c7b8f16e 2812 unsigned int mapsize;
e489d0ae 2813 elf32_arm_section_map *map;
2468f9c9 2814 /* Information about CPU errata. */
c7b8f16e
JB		 2815 unsigned int erratumcount;
2816 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2817 unsigned int stm32l4xx_erratumcount;
2818 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2819 unsigned int additional_reloc_count;
2468f9c9
PB		 2820 /* Information about unwind tables. */
2821 union
2822 {
2823 /* Unwind info attached to a text section. */
2824 struct
2825 {
2826 asection *arm_exidx_sec;
2827 } text;
2828
2829 /* Unwind info attached to an .ARM.exidx section. */
2830 struct
2831 {
2832 arm_unwind_table_edit *unwind_edit_list;
2833 arm_unwind_table_edit *unwind_edit_tail;
2834 } exidx;
2835 } u;
8e3de13a
NC		 2836}
2837_arm_elf_section_data;
e489d0ae
PB		 2838
2839#define elf32_arm_section_data(sec) \
8e3de13a 2840 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2841
48229727
JB		 2842/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2843 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2844 so may be created multiple times: we use an array of these entries whilst
2845 relaxing which we can refresh easily, then create stubs for each potentially
2846 erratum-triggering instruction once we've settled on a solution. */
2847
b38cadfb
NC		 2848struct a8_erratum_fix
2849{
48229727
JB		 2850 bfd *input_bfd;
2851 asection *section;
2852 bfd_vma offset;
8d9d9490 2853 bfd_vma target_offset;
48229727
JB		 2854 unsigned long orig_insn;
2855 char *stub_name;
2856 enum elf32_arm_stub_type stub_type;
35fc36a8 2857 enum arm_st_branch_type branch_type;
48229727
JB		 2858};
2859
2860/* A table of relocs applied to branches which might trigger Cortex-A8
2861 erratum. */
2862
b38cadfb
NC		 2863struct a8_erratum_reloc
2864{
48229727
JB		 2865 bfd_vma from;
2866 bfd_vma destination;
92750f34
DJ		 2867 struct elf32_arm_link_hash_entry *hash;
2868 const char *sym_name;
48229727 2869 unsigned int r_type;
35fc36a8 2870 enum arm_st_branch_type branch_type;
48229727
JB		 2871 bfd_boolean non_a8_stub;
2872};
2873
ba93b8ac
DJ		 2874/* The size of the thread control block. */
2875#define TCB_SIZE 8
2876
34e77a92
RS		 2877/* ARM-specific information about a PLT entry, over and above the usual
2878 gotplt_union. */
b38cadfb
NC		 2879struct arm_plt_info
2880{
34e77a92
RS		 2881 /* We reference count Thumb references to a PLT entry separately,
2882 so that we can emit the Thumb trampoline only if needed. */
2883 bfd_signed_vma thumb_refcount;
2884
2885 /* Some references from Thumb code may be eliminated by BL->BLX
2886 conversion, so record them separately. */
2887 bfd_signed_vma maybe_thumb_refcount;
2888
2889 /* How many of the recorded PLT accesses were from non-call relocations.
2890 This information is useful when deciding whether anything takes the
2891 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2892 non-call references to the function should resolve directly to the
2893 real runtime target. */
2894 unsigned int noncall_refcount;
2895
2896 /* Since PLT entries have variable size if the Thumb prologue is
2897 used, we need to record the index into .got.plt instead of
2898 recomputing it from the PLT offset. */
2899 bfd_signed_vma got_offset;
2900};
2901
2902/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2903struct arm_local_iplt_info
2904{
34e77a92
RS		 2905 /* The information that is usually found in the generic ELF part of
2906 the hash table entry. */
2907 union gotplt_union root;
2908
2909 /* The information that is usually found in the ARM-specific part of
2910 the hash table entry. */
2911 struct arm_plt_info arm;
2912
2913 /* A list of all potential dynamic relocations against this symbol. */
2914 struct elf_dyn_relocs *dyn_relocs;
2915};
2916
0ffa91dd 2917struct elf_arm_obj_tdata
ba93b8ac
DJ		 2918{
2919 struct elf_obj_tdata root;
2920
2921 /* tls_type for each local got entry. */
2922 char *local_got_tls_type;
ee065d83 2923
0855e32b
NS		 2924 /* GOTPLT entries for TLS descriptors. */
2925 bfd_vma *local_tlsdesc_gotent;
2926
34e77a92
RS		 2927 /* Information for local symbols that need entries in .iplt. */
2928 struct arm_local_iplt_info **local_iplt;
2929
bf21ed78
MS		 2930 /* Zero to warn when linking objects with incompatible enum sizes. */
2931 int no_enum_size_warning;
a9dc9481
JM		 2932
2933 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2934 int no_wchar_size_warning;
ba93b8ac
DJ		 2935};
2936
0ffa91dd
NC		 2937#define elf_arm_tdata(bfd) \
2938 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2939
0ffa91dd
NC		 2940#define elf32_arm_local_got_tls_type(bfd) \
2941 (elf_arm_tdata (bfd)->local_got_tls_type)
2942
0855e32b
NS		 2943#define elf32_arm_local_tlsdesc_gotent(bfd) \
2944 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2945
34e77a92
RS		 2946#define elf32_arm_local_iplt(bfd) \
2947 (elf_arm_tdata (bfd)->local_iplt)
2948
0ffa91dd
NC		 2949#define is_arm_elf(bfd) \
2950 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2951 && elf_tdata (bfd) != NULL \
4dfe6ac6 2952 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2953
2954static bfd_boolean
2955elf32_arm_mkobject (bfd *abfd)
2956{
0ffa91dd 2957 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2958 ARM_ELF_DATA);
ba93b8ac
DJ		 2959}
2960
ba93b8ac
DJ		 2961#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2962
ba96a88f 2963/* Arm ELF linker hash entry. */
252b5132 2964struct elf32_arm_link_hash_entry
b38cadfb
NC		 2965{
2966 struct elf_link_hash_entry root;
252b5132 2967
b38cadfb
NC		 2968 /* Track dynamic relocs copied for this symbol. */
2969 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2970
b38cadfb
NC		 2971 /* ARM-specific PLT information. */
2972 struct arm_plt_info plt;
ba93b8ac
DJ		 2973
2974#define GOT_UNKNOWN 0
2975#define GOT_NORMAL 1
2976#define GOT_TLS_GD 2
2977#define GOT_TLS_IE 4
0855e32b
NS		 2978#define GOT_TLS_GDESC 8
2979#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 2980 unsigned int tls_type : 8;
34e77a92 2981
b38cadfb
NC		 2982 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2983 unsigned int is_iplt : 1;
34e77a92 2984
b38cadfb 2985 unsigned int unused : 23;
a4fd1a8e 2986
b38cadfb
NC		 2987 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2988 starting at the end of the jump table. */
2989 bfd_vma tlsdesc_got;
0855e32b 2990
b38cadfb
NC		 2991 /* The symbol marking the real symbol location for exported thumb
2992 symbols with Arm stubs. */
2993 struct elf_link_hash_entry *export_glue;
906e58ca 2994
b38cadfb 2995 /* A pointer to the most recently used stub hash entry against this
8029a119 2996 symbol. */
b38cadfb
NC		 2997 struct elf32_arm_stub_hash_entry *stub_cache;
2998};
252b5132 2999
252b5132 3000/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3001#define elf32_arm_link_hash_traverse(table, func, info) \
3002 (elf_link_hash_traverse \
3003 (&(table)->root, \
b7693d02 3004 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3005 (info)))
3006
3007/* Get the ARM elf linker hash table from a link_info structure. */
3008#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3009 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3010 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3011
906e58ca
NC		 3012#define arm_stub_hash_lookup(table, string, create, copy) \
3013 ((struct elf32_arm_stub_hash_entry *) \
3014 bfd_hash_lookup ((table), (string), (create), (copy)))
3015
21d799b5
NC		 3016/* Array to keep track of which stub sections have been created, and
3017 information on stub grouping. */
3018struct map_stub
3019{
3020 /* This is the section to which stubs in the group will be
3021 attached. */
3022 asection *link_sec;
3023 /* The stub section. */
3024 asection *stub_sec;
3025};
3026
0855e32b
NS		 3027#define elf32_arm_compute_jump_table_size(htab) \
3028 ((htab)->next_tls_desc_index * 4)
3029
9b485d32 3030/* ARM ELF linker hash table. */
252b5132 3031struct elf32_arm_link_hash_table
906e58ca
NC		 3032{
3033 /* The main hash table. */
3034 struct elf_link_hash_table root;
252b5132 3035
906e58ca
NC		 3036 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3037 bfd_size_type thumb_glue_size;
252b5132 3038
906e58ca
NC		 3039 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3040 bfd_size_type arm_glue_size;
252b5132 3041
906e58ca
NC		 3042 /* The size in bytes of section containing the ARMv4 BX veneers. */
3043 bfd_size_type bx_glue_size;
845b51d6 3044
906e58ca
NC		 3045 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3046 veneer has been populated. */
3047 bfd_vma bx_glue_offset[15];
845b51d6 3048
906e58ca
NC		 3049 /* The size in bytes of the section containing glue for VFP11 erratum
3050 veneers. */
3051 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3052
a504d23a
LA		 3053 /* The size in bytes of the section containing glue for STM32L4XX erratum
3054 veneers. */
3055 bfd_size_type stm32l4xx_erratum_glue_size;
3056
48229727
JB		 3057 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3058 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3059 elf32_arm_write_section(). */
3060 struct a8_erratum_fix *a8_erratum_fixes;
3061 unsigned int num_a8_erratum_fixes;
3062
906e58ca
NC		 3063 /* An arbitrary input BFD chosen to hold the glue sections. */
3064 bfd * bfd_of_glue_owner;
ba96a88f 3065
906e58ca
NC		 3066 /* Nonzero to output a BE8 image. */
3067 int byteswap_code;
e489d0ae 3068
906e58ca
NC		 3069 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3070 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3071 int target1_is_rel;
9c504268 3072
906e58ca
NC		 3073 /* The relocation to use for R_ARM_TARGET2 relocations. */
3074 int target2_reloc;
eb043451 3075
906e58ca
NC		 3076 /* 0 = Ignore R_ARM_V4BX.
3077 1 = Convert BX to MOV PC.
3078 2 = Generate v4 interworing stubs. */
3079 int fix_v4bx;
319850b4 3080
48229727
JB		 3081 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3082 int fix_cortex_a8;
3083
2de70689
MGD		 3084 /* Whether we should fix the ARM1176 BLX immediate issue. */
3085 int fix_arm1176;
3086
906e58ca
NC		 3087 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3088 int use_blx;
33bfe774 3089
906e58ca
NC		 3090 /* What sort of code sequences we should look for which may trigger the
3091 VFP11 denorm erratum. */
3092 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3093
906e58ca
NC		 3094 /* Global counter for the number of fixes we have emitted. */
3095 int num_vfp11_fixes;
c7b8f16e 3096
a504d23a
LA		 3097 /* What sort of code sequences we should look for which may trigger the
3098 STM32L4XX erratum. */
3099 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3100
3101 /* Global counter for the number of fixes we have emitted. */
3102 int num_stm32l4xx_fixes;
3103
906e58ca
NC		 3104 /* Nonzero to force PIC branch veneers. */
3105 int pic_veneer;
27e55c4d 3106
906e58ca
NC		 3107 /* The number of bytes in the initial entry in the PLT. */
3108 bfd_size_type plt_header_size;
e5a52504 3109
906e58ca
NC		 3110 /* The number of bytes in the subsequent PLT etries. */
3111 bfd_size_type plt_entry_size;
e5a52504 3112
906e58ca
NC		 3113 /* True if the target system is VxWorks. */
3114 int vxworks_p;
00a97672 3115
906e58ca
NC		 3116 /* True if the target system is Symbian OS. */
3117 int symbian_p;
e5a52504 3118
b38cadfb
NC		 3119 /* True if the target system is Native Client. */
3120 int nacl_p;
3121
906e58ca
NC		 3122 /* True if the target uses REL relocations. */
3123 int use_rel;
4e7fd91e 3124
0855e32b
NS		 3125 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3126 bfd_vma next_tls_desc_index;
3127
3128 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3129 bfd_vma num_tls_desc;
3130
906e58ca 3131 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3132 asection *sdynbss;
3133 asection *srelbss;
5e681ec4 3134
906e58ca
NC		 3135 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3136 asection *srelplt2;
00a97672 3137
0855e32b
NS		 3138 /* The offset into splt of the PLT entry for the TLS descriptor
3139 resolver. Special values are 0, if not necessary (or not found
3140 to be necessary yet), and -1 if needed but not determined
3141 yet. */
3142 bfd_vma dt_tlsdesc_plt;
3143
3144 /* The offset into sgot of the GOT entry used by the PLT entry
3145 above. */
b38cadfb 3146 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3147
3148 /* Offset in .plt section of tls_arm_trampoline. */
3149 bfd_vma tls_trampoline;
3150
906e58ca
NC		 3151 /* Data for R_ARM_TLS_LDM32 relocations. */
3152 union
3153 {
3154 bfd_signed_vma refcount;
3155 bfd_vma offset;
3156 } tls_ldm_got;
b7693d02 3157
87d72d41
AM		 3158 /* Small local sym cache. */
3159 struct sym_cache sym_cache;
906e58ca
NC		 3160
3161 /* For convenience in allocate_dynrelocs. */
3162 bfd * obfd;
3163
0855e32b
NS		 3164 /* The amount of space used by the reserved portion of the sgotplt
3165 section, plus whatever space is used by the jump slots. */
3166 bfd_vma sgotplt_jump_table_size;
3167
906e58ca
NC		 3168 /* The stub hash table. */
3169 struct bfd_hash_table stub_hash_table;
3170
3171 /* Linker stub bfd. */
3172 bfd *stub_bfd;
3173
3174 /* Linker call-backs. */
6bde4c52
TP		 3175 asection * (*add_stub_section) (const char *, asection *, asection *,
3176 unsigned int);
906e58ca
NC		 3177 void (*layout_sections_again) (void);
3178
3179 /* Array to keep track of which stub sections have been created, and
3180 information on stub grouping. */
21d799b5 3181 struct map_stub *stub_group;
906e58ca 3182
fe33d2fa 3183 /* Number of elements in stub_group. */
7292b3ac 3184 unsigned int top_id;
fe33d2fa 3185
906e58ca
NC		 3186 /* Assorted information used by elf32_arm_size_stubs. */
3187 unsigned int bfd_count;
7292b3ac 3188 unsigned int top_index;
906e58ca
NC		 3189 asection **input_list;
3190};
252b5132 3191
a504d23a
LA		 3192static inline int
3193ctz (unsigned int mask)
3194{
3195#if GCC_VERSION >= 3004
3196 return __builtin_ctz (mask);
3197#else
3198 unsigned int i;
3199
3200 for (i = 0; i < 8 * sizeof (mask); i++)
3201 {
3202 if (mask & 0x1)
3203 break;
3204 mask = (mask >> 1);
3205 }
3206 return i;
3207#endif
3208}
3209
3210static inline int
3211popcount (unsigned int mask)
3212{
3213#if GCC_VERSION >= 3004
3214 return __builtin_popcount (mask);
3215#else
3216 unsigned int i, sum = 0;
3217
3218 for (i = 0; i < 8 * sizeof (mask); i++)
3219 {
3220 if (mask & 0x1)
3221 sum++;
3222 mask = (mask >> 1);
3223 }
3224 return sum;
3225#endif
3226}
3227
780a67af
NC		 3228/* Create an entry in an ARM ELF linker hash table. */
3229
3230static struct bfd_hash_entry *
57e8b36a 3231elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3232 struct bfd_hash_table * table,
3233 const char * string)
780a67af
NC		 3234{
3235 struct elf32_arm_link_hash_entry * ret =
3236 (struct elf32_arm_link_hash_entry *) entry;
3237
3238 /* Allocate the structure if it has not already been allocated by a
3239 subclass. */
906e58ca 3240 if (ret == NULL)
21d799b5 3241 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3242 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3243 if (ret == NULL)
780a67af
NC		 3244 return (struct bfd_hash_entry *) ret;
3245
3246 /* Call the allocation method of the superclass. */
3247 ret = ((struct elf32_arm_link_hash_entry *)
3248 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3249 table, string));
57e8b36a 3250 if (ret != NULL)
b7693d02 3251 {
0bdcacaf 3252 ret->dyn_relocs = NULL;
ba93b8ac 3253 ret->tls_type = GOT_UNKNOWN;
0855e32b 3254 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3255 ret->plt.thumb_refcount = 0;
3256 ret->plt.maybe_thumb_refcount = 0;
3257 ret->plt.noncall_refcount = 0;
3258 ret->plt.got_offset = -1;
3259 ret->is_iplt = FALSE;
a4fd1a8e 3260 ret->export_glue = NULL;
906e58ca
NC		 3261
3262 ret->stub_cache = NULL;
b7693d02 3263 }
780a67af
NC		 3264
3265 return (struct bfd_hash_entry *) ret;
3266}
3267
34e77a92
RS		 3268/* Ensure that we have allocated bookkeeping structures for ABFD's local
3269 symbols. */
3270
3271static bfd_boolean
3272elf32_arm_allocate_local_sym_info (bfd *abfd)
3273{
3274 if (elf_local_got_refcounts (abfd) == NULL)
3275 {
3276 bfd_size_type num_syms;
3277 bfd_size_type size;
3278 char *data;
3279
3280 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3281 size = num_syms * (sizeof (bfd_signed_vma)
3282 + sizeof (struct arm_local_iplt_info *)
3283 + sizeof (bfd_vma)
3284 + sizeof (char));
3285 data = bfd_zalloc (abfd, size);
3286 if (data == NULL)
3287 return FALSE;
3288
3289 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3290 data += num_syms * sizeof (bfd_signed_vma);
3291
3292 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3293 data += num_syms * sizeof (struct arm_local_iplt_info *);
3294
3295 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3296 data += num_syms * sizeof (bfd_vma);
3297
3298 elf32_arm_local_got_tls_type (abfd) = data;
3299 }
3300 return TRUE;
3301}
3302
3303/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3304 to input bfd ABFD. Create the information if it doesn't already exist.
3305 Return null if an allocation fails. */
3306
3307static struct arm_local_iplt_info *
3308elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3309{
3310 struct arm_local_iplt_info **ptr;
3311
3312 if (!elf32_arm_allocate_local_sym_info (abfd))
3313 return NULL;
3314
3315 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3316 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3317 if (*ptr == NULL)
3318 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3319 return *ptr;
3320}
3321
3322/* Try to obtain PLT information for the symbol with index R_SYMNDX
3323 in ABFD's symbol table. If the symbol is global, H points to its
3324 hash table entry, otherwise H is null.
3325
3326 Return true if the symbol does have PLT information. When returning
3327 true, point *ROOT_PLT at the target-independent reference count/offset
3328 union and *ARM_PLT at the ARM-specific information. */
3329
3330static bfd_boolean
3331elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_entry *h,
3332 unsigned long r_symndx, union gotplt_union **root_plt,
3333 struct arm_plt_info **arm_plt)
3334{
3335 struct arm_local_iplt_info *local_iplt;
3336
3337 if (h != NULL)
3338 {
3339 *root_plt = &h->root.plt;
3340 *arm_plt = &h->plt;
3341 return TRUE;
3342 }
3343
3344 if (elf32_arm_local_iplt (abfd) == NULL)
3345 return FALSE;
3346
3347 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3348 if (local_iplt == NULL)
3349 return FALSE;
3350
3351 *root_plt = &local_iplt->root;
3352 *arm_plt = &local_iplt->arm;
3353 return TRUE;
3354}
3355
3356/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3357 before it. */
3358
3359static bfd_boolean
3360elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3361 struct arm_plt_info *arm_plt)
3362{
3363 struct elf32_arm_link_hash_table *htab;
3364
3365 htab = elf32_arm_hash_table (info);
3366 return (arm_plt->thumb_refcount != 0
3367 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3368}
3369
3370/* Return a pointer to the head of the dynamic reloc list that should
3371 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3372 ABFD's symbol table. Return null if an error occurs. */
3373
3374static struct elf_dyn_relocs **
3375elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3376 Elf_Internal_Sym *isym)
3377{
3378 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3379 {
3380 struct arm_local_iplt_info *local_iplt;
3381
3382 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3383 if (local_iplt == NULL)
3384 return NULL;
3385 return &local_iplt->dyn_relocs;
3386 }
3387 else
3388 {
3389 /* Track dynamic relocs needed for local syms too.
3390 We really need local syms available to do this
3391 easily. Oh well. */
3392 asection *s;
3393 void *vpp;
3394
3395 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3396 if (s == NULL)
3397 abort ();
3398
3399 vpp = &elf_section_data (s)->local_dynrel;
3400 return (struct elf_dyn_relocs **) vpp;
3401 }
3402}
3403
906e58ca
NC		 3404/* Initialize an entry in the stub hash table. */
3405
3406static struct bfd_hash_entry *
3407stub_hash_newfunc (struct bfd_hash_entry *entry,
3408 struct bfd_hash_table *table,
3409 const char *string)
3410{
3411 /* Allocate the structure if it has not already been allocated by a
3412 subclass. */
3413 if (entry == NULL)
3414 {
21d799b5 3415 entry = (struct bfd_hash_entry *)
99059e56 3416 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3417 if (entry == NULL)
3418 return entry;
3419 }
3420
3421 /* Call the allocation method of the superclass. */
3422 entry = bfd_hash_newfunc (entry, table, string);
3423 if (entry != NULL)
3424 {
3425 struct elf32_arm_stub_hash_entry *eh;
3426
3427 /* Initialize the local fields. */
3428 eh = (struct elf32_arm_stub_hash_entry *) entry;
3429 eh->stub_sec = NULL;
3430 eh->stub_offset = 0;
8d9d9490 3431 eh->source_value = 0;
906e58ca
NC		 3432 eh->target_value = 0;
3433 eh->target_section = NULL;
cedfb179 3434 eh->orig_insn = 0;
906e58ca 3435 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3436 eh->stub_size = 0;
3437 eh->stub_template = NULL;
3438 eh->stub_template_size = 0;
906e58ca
NC		 3439 eh->h = NULL;
3440 eh->id_sec = NULL;
d8d2f433 3441 eh->output_name = NULL;
906e58ca
NC		 3442 }
3443
3444 return entry;
3445}
3446
00a97672 3447/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3448 shortcuts to them in our hash table. */
3449
3450static bfd_boolean
57e8b36a 3451create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3452{
3453 struct elf32_arm_link_hash_table *htab;
3454
e5a52504 3455 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3456 if (htab == NULL)
3457 return FALSE;
3458
e5a52504
MM		 3459 /* BPABI objects never have a GOT, or associated sections. */
3460 if (htab->symbian_p)
3461 return TRUE;
3462
5e681ec4
PB		 3463 if (! _bfd_elf_create_got_section (dynobj, info))
3464 return FALSE;
3465
5e681ec4
PB		 3466 return TRUE;
3467}
3468
34e77a92
RS		 3469/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3470
3471static bfd_boolean
3472create_ifunc_sections (struct bfd_link_info *info)
3473{
3474 struct elf32_arm_link_hash_table *htab;
3475 const struct elf_backend_data *bed;
3476 bfd *dynobj;
3477 asection *s;
3478 flagword flags;
b38cadfb 3479
34e77a92
RS		 3480 htab = elf32_arm_hash_table (info);
3481 dynobj = htab->root.dynobj;
3482 bed = get_elf_backend_data (dynobj);
3483 flags = bed->dynamic_sec_flags;
3484
3485 if (htab->root.iplt == NULL)
3486 {
3d4d4302
AM		 3487 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3488 flags | SEC_READONLY | SEC_CODE);
34e77a92 3489 if (s == NULL
a0f49396 3490 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3491 return FALSE;
3492 htab->root.iplt = s;
3493 }
3494
3495 if (htab->root.irelplt == NULL)
3496 {
3d4d4302
AM		 3497 s = bfd_make_section_anyway_with_flags (dynobj,
3498 RELOC_SECTION (htab, ".iplt"),
3499 flags | SEC_READONLY);
34e77a92 3500 if (s == NULL
a0f49396 3501 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3502 return FALSE;
3503 htab->root.irelplt = s;
3504 }
3505
3506 if (htab->root.igotplt == NULL)
3507 {
3d4d4302 3508 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3509 if (s == NULL
3510 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3511 return FALSE;
3512 htab->root.igotplt = s;
3513 }
3514 return TRUE;
3515}
3516
eed94f8f
NC		 3517/* Determine if we're dealing with a Thumb only architecture. */
3518
3519static bfd_boolean
3520using_thumb_only (struct elf32_arm_link_hash_table *globals)
3521{
2fd158eb
TP		 3522 int arch;
3523 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3524 Tag_CPU_arch_profile);
eed94f8f 3525
2fd158eb
TP		 3526 if (profile)
3527 return profile == 'M';
eed94f8f 3528
2fd158eb 3529 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3530
60a019a0
TP		 3531 /* Force return logic to be reviewed for each new architecture. */
3532 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3533 || arch == TAG_CPU_ARCH_V8M_BASE
3534 || arch == TAG_CPU_ARCH_V8M_MAIN);
3535
2fd158eb
TP		 3536 if (arch == TAG_CPU_ARCH_V6_M
3537 || arch == TAG_CPU_ARCH_V6S_M
3538 || arch == TAG_CPU_ARCH_V7E_M
3539 || arch == TAG_CPU_ARCH_V8M_BASE
3540 || arch == TAG_CPU_ARCH_V8M_MAIN)
3541 return TRUE;
eed94f8f 3542
2fd158eb 3543 return FALSE;
eed94f8f
NC		 3544}
3545
3546/* Determine if we're dealing with a Thumb-2 object. */
3547
3548static bfd_boolean
3549using_thumb2 (struct elf32_arm_link_hash_table *globals)
3550{
60a019a0
TP		 3551 int arch;
3552 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3553 Tag_THUMB_ISA_use);
3554
3555 if (thumb_isa)
3556 return thumb_isa == 2;
3557
3558 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3559
3560 /* Force return logic to be reviewed for each new architecture. */
3561 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3562 || arch == TAG_CPU_ARCH_V8M_BASE
3563 || arch == TAG_CPU_ARCH_V8M_MAIN);
3564
3565 return (arch == TAG_CPU_ARCH_V6T2
3566 || arch == TAG_CPU_ARCH_V7
3567 || arch == TAG_CPU_ARCH_V7E_M
3568 || arch == TAG_CPU_ARCH_V8
3569 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3570}
3571
00a97672
RS		 3572/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3573 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3574 hash table. */
3575
3576static bfd_boolean
57e8b36a 3577elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3578{
3579 struct elf32_arm_link_hash_table *htab;
3580
3581 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3582 if (htab == NULL)
3583 return FALSE;
3584
362d30a1 3585 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3586 return FALSE;
3587
3588 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3589 return FALSE;
3590
3d4d4302 3591 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3592 if (!bfd_link_pic (info))
3d4d4302
AM		 3593 htab->srelbss = bfd_get_linker_section (dynobj,
3594 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3595
3596 if (htab->vxworks_p)
3597 {
3598 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3599 return FALSE;
3600
0e1862bb 3601 if (bfd_link_pic (info))
00a97672
RS		 3602 {
3603 htab->plt_header_size = 0;
3604 htab->plt_entry_size
3605 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3606 }
3607 else
3608 {
3609 htab->plt_header_size
3610 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3611 htab->plt_entry_size
3612 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3613 }
aebf9be7
NC		 3614
3615 if (elf_elfheader (dynobj))
3616 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3617 }
eed94f8f
NC		 3618 else
3619 {
3620 /* PR ld/16017
3621 Test for thumb only architectures. Note - we cannot just call
3622 using_thumb_only() as the attributes in the output bfd have not been
3623 initialised at this point, so instead we use the input bfd. */
3624 bfd * saved_obfd = htab->obfd;
3625
3626 htab->obfd = dynobj;
3627 if (using_thumb_only (htab))
3628 {
3629 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3630 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3631 }
3632 htab->obfd = saved_obfd;
3633 }
5e681ec4 3634
362d30a1
RS		 3635 if (!htab->root.splt
3636 || !htab->root.srelplt
e5a52504 3637 || !htab->sdynbss
0e1862bb 3638 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3639 abort ();
3640
3641 return TRUE;
3642}
3643
906e58ca
NC		 3644/* Copy the extra info we tack onto an elf_link_hash_entry. */
3645
3646static void
3647elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3648 struct elf_link_hash_entry *dir,
3649 struct elf_link_hash_entry *ind)
3650{
3651 struct elf32_arm_link_hash_entry *edir, *eind;
3652
3653 edir = (struct elf32_arm_link_hash_entry *) dir;
3654 eind = (struct elf32_arm_link_hash_entry *) ind;
3655
0bdcacaf 3656 if (eind->dyn_relocs != NULL)
906e58ca 3657 {
0bdcacaf 3658 if (edir->dyn_relocs != NULL)
906e58ca 3659 {
0bdcacaf
RS		 3660 struct elf_dyn_relocs **pp;
3661 struct elf_dyn_relocs *p;
906e58ca
NC		 3662
3663 /* Add reloc counts against the indirect sym to the direct sym
3664 list. Merge any entries against the same section. */
0bdcacaf 3665 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3666 {
0bdcacaf 3667 struct elf_dyn_relocs *q;
906e58ca 3668
0bdcacaf
RS		 3669 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3670 if (q->sec == p->sec)
906e58ca
NC		 3671 {
3672 q->pc_count += p->pc_count;
3673 q->count += p->count;
3674 *pp = p->next;
3675 break;
3676 }
3677 if (q == NULL)
3678 pp = &p->next;
3679 }
0bdcacaf 3680 *pp = edir->dyn_relocs;
906e58ca
NC		 3681 }
3682
0bdcacaf
RS		 3683 edir->dyn_relocs = eind->dyn_relocs;
3684 eind->dyn_relocs = NULL;
906e58ca
NC		 3685 }
3686
3687 if (ind->root.type == bfd_link_hash_indirect)
3688 {
3689 /* Copy over PLT info. */
34e77a92
RS		 3690 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3691 eind->plt.thumb_refcount = 0;
3692 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3693 eind->plt.maybe_thumb_refcount = 0;
3694 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3695 eind->plt.noncall_refcount = 0;
3696
3697 /* We should only allocate a function to .iplt once the final
3698 symbol information is known. */
3699 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3700
3701 if (dir->got.refcount <= 0)
3702 {
3703 edir->tls_type = eind->tls_type;
3704 eind->tls_type = GOT_UNKNOWN;
3705 }
3706 }
3707
3708 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3709}
3710
68faa637
AM		 3711/* Destroy an ARM elf linker hash table. */
3712
3713static void
d495ab0d 3714elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3715{
3716 struct elf32_arm_link_hash_table *ret
d495ab0d 3717 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3718
3719 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3720 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3721}
3722
906e58ca
NC		 3723/* Create an ARM elf linker hash table. */
3724
3725static struct bfd_link_hash_table *
3726elf32_arm_link_hash_table_create (bfd *abfd)
3727{
3728 struct elf32_arm_link_hash_table *ret;
3729 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3730
7bf52ea2 3731 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3732 if (ret == NULL)
3733 return NULL;
3734
3735 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3736 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3737 sizeof (struct elf32_arm_link_hash_entry),
3738 ARM_ELF_DATA))
906e58ca
NC		 3739 {
3740 free (ret);
3741 return NULL;
3742 }
3743
906e58ca 3744 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3745 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3746#ifdef FOUR_WORD_PLT
3747 ret->plt_header_size = 16;
3748 ret->plt_entry_size = 16;
3749#else
3750 ret->plt_header_size = 20;
1db37fe6 3751 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3752#endif
906e58ca 3753 ret->use_rel = 1;
906e58ca 3754 ret->obfd = abfd;
906e58ca
NC		 3755
3756 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3757 sizeof (struct elf32_arm_stub_hash_entry)))
3758 {
d495ab0d 3759 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3760 return NULL;
3761 }
d495ab0d 3762 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3763
3764 return &ret->root.root;
3765}
3766
cd1dac3d
DG		 3767/* Determine what kind of NOPs are available. */
3768
3769static bfd_boolean
3770arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3771{
3772 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3773 Tag_CPU_arch);
cd1dac3d 3774
60a019a0
TP		 3775 /* Force return logic to be reviewed for each new architecture. */
3776 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3777 || arch == TAG_CPU_ARCH_V8M_BASE
3778 || arch == TAG_CPU_ARCH_V8M_MAIN);
3779
3780 return (arch == TAG_CPU_ARCH_V6T2
3781 || arch == TAG_CPU_ARCH_V6K
3782 || arch == TAG_CPU_ARCH_V7
3783 || arch == TAG_CPU_ARCH_V8);
cd1dac3d
DG		 3784}
3785
f4ac8484
DJ		 3786static bfd_boolean
3787arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3788{
3789 switch (stub_type)
3790 {
fea2b4d6 3791 case arm_stub_long_branch_thumb_only:
80c135e5 3792 case arm_stub_long_branch_thumb2_only:
fea2b4d6
CL		 3793 case arm_stub_long_branch_v4t_thumb_arm:
3794 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3795 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3796 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3797 case arm_stub_long_branch_thumb_only_pic:
f4ac8484
DJ		 3798 return TRUE;
3799 case arm_stub_none:
3800 BFD_FAIL ();
3801 return FALSE;
3802 break;
3803 default:
3804 return FALSE;
3805 }
3806}
3807
906e58ca
NC		 3808/* Determine the type of stub needed, if any, for a call. */
3809
3810static enum elf32_arm_stub_type
3811arm_type_of_stub (struct bfd_link_info *info,
3812 asection *input_sec,
3813 const Elf_Internal_Rela *rel,
34e77a92 3814 unsigned char st_type,
35fc36a8 3815 enum arm_st_branch_type *actual_branch_type,
906e58ca 3816 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3817 bfd_vma destination,
3818 asection *sym_sec,
3819 bfd *input_bfd,
3820 const char *name)
906e58ca
NC		 3821{
3822 bfd_vma location;
3823 bfd_signed_vma branch_offset;
3824 unsigned int r_type;
3825 struct elf32_arm_link_hash_table * globals;
3826 int thumb2;
3827 int thumb_only;
3828 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3829 int use_plt = 0;
35fc36a8 3830 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3831 union gotplt_union *root_plt;
3832 struct arm_plt_info *arm_plt;
906e58ca 3833
35fc36a8 3834 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3835 return stub_type;
3836
906e58ca 3837 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3838 if (globals == NULL)
3839 return stub_type;
906e58ca
NC		 3840
3841 thumb_only = using_thumb_only (globals);
3842
3843 thumb2 = using_thumb2 (globals);
3844
3845 /* Determine where the call point is. */
3846 location = (input_sec->output_offset
3847 + input_sec->output_section->vma
3848 + rel->r_offset);
3849
906e58ca
NC		 3850 r_type = ELF32_R_TYPE (rel->r_info);
3851
39f21624
NC		 3852 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3853 are considering a function call relocation. */
c5423981
TG		 3854 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3855 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3856 && branch_type == ST_BRANCH_TO_ARM)
3857 branch_type = ST_BRANCH_TO_THUMB;
3858
34e77a92
RS		 3859 /* For TLS call relocs, it is the caller's responsibility to provide
3860 the address of the appropriate trampoline. */
3861 if (r_type != R_ARM_TLS_CALL
3862 && r_type != R_ARM_THM_TLS_CALL
3863 && elf32_arm_get_plt_info (input_bfd, hash, ELF32_R_SYM (rel->r_info),
3864 &root_plt, &arm_plt)
3865 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3866 {
34e77a92 3867 asection *splt;
fe33d2fa 3868
34e77a92
RS		 3869 if (hash == NULL || hash->is_iplt)
3870 splt = globals->root.iplt;
3871 else
3872 splt = globals->root.splt;
3873 if (splt != NULL)
b38cadfb 3874 {
34e77a92
RS		 3875 use_plt = 1;
3876
3877 /* Note when dealing with PLT entries: the main PLT stub is in
3878 ARM mode, so if the branch is in Thumb mode, another
3879 Thumb->ARM stub will be inserted later just before the ARM
3880 PLT stub. We don't take this extra distance into account
3881 here, because if a long branch stub is needed, we'll add a
3882 Thumb->Arm one and branch directly to the ARM PLT entry
3883 because it avoids spreading offset corrections in several
3884 places. */
3885
3886 destination = (splt->output_section->vma
3887 + splt->output_offset
3888 + root_plt->offset);
3889 st_type = STT_FUNC;
3890 branch_type = ST_BRANCH_TO_ARM;
3891 }
5fa9e92f 3892 }
34e77a92
RS		 3893 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3894 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3895
fe33d2fa
CL		 3896 branch_offset = (bfd_signed_vma)(destination - location);
3897
0855e32b 3898 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3899 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3900 {
5fa9e92f
CL		 3901 /* Handle cases where:
3902 - this call goes too far (different Thumb/Thumb2 max
99059e56 3903 distance)
155d87d7 3904 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3905 Thumb->Arm branch (not bl). A stub is needed in this case,
3906 but only if this call is not through a PLT entry. Indeed,
3907 PLT stubs handle mode switching already.
5fa9e92f 3908 */
906e58ca
NC		 3909 if ((!thumb2
3910 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3911 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
3912 || (thumb2
3913 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3914 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3915 || (thumb2
3916 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3917 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3918 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3919 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3920 && (((r_type == R_ARM_THM_CALL
3921 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3922 || (r_type == R_ARM_THM_JUMP24)
3923 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3924 && !use_plt))
906e58ca 3925 {
35fc36a8 3926 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3927 {
3928 /* Thumb to thumb. */
3929 if (!thumb_only)
3930 {
0e1862bb 3931 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3932 /* PIC stubs. */
155d87d7 3933 ? ((globals->use_blx
9553db3c 3934 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 3935 /* V5T and above. Stub starts with ARM code, so
3936 we must be able to switch mode before
3937 reaching it, which is only possible for 'bl'
3938 (ie R_ARM_THM_CALL relocation). */
cf3eccff 3939 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 3940 /* On V4T, use Thumb code only. */
d3626fb0 3941 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 3942
3943 /* non-PIC stubs. */
155d87d7 3944 : ((globals->use_blx
9553db3c 3945 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 3946 /* V5T and above. */
3947 ? arm_stub_long_branch_any_any
3948 /* V4T. */
d3626fb0 3949 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 3950 }
3951 else
3952 {
0e1862bb 3953 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
ebe24dd4
CL		 3954 /* PIC stub. */
3955 ? arm_stub_long_branch_thumb_only_pic
c2b4a39d 3956 /* non-PIC stub. */
80c135e5
TP		 3957 : (thumb2 ? arm_stub_long_branch_thumb2_only
3958 : arm_stub_long_branch_thumb_only);
906e58ca
NC		 3959 }
3960 }
3961 else
3962 {
3963 /* Thumb to arm. */
c820be07
NC		 3964 if (sym_sec != NULL
3965 && sym_sec->owner != NULL
3966 && !INTERWORK_FLAG (sym_sec->owner))
3967 {
3968 (*_bfd_error_handler)
3969 (_("%B(%s): warning: interworking not enabled.\n"
3970 " first occurrence: %B: Thumb call to ARM"),
3971 sym_sec->owner, input_bfd, name);
3972 }
3973
0855e32b 3974 stub_type =
0e1862bb 3975 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3976 /* PIC stubs. */
0855e32b 3977 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 3978 /* TLS PIC stubs. */
0855e32b
NS		 3979 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
3980 : arm_stub_long_branch_v4t_thumb_tls_pic)
3981 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
3982 /* V5T PIC and above. */
3983 ? arm_stub_long_branch_any_arm_pic
3984 /* V4T PIC stub. */
3985 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 3986
3987 /* non-PIC stubs. */
0855e32b 3988 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 3989 /* V5T and above. */
3990 ? arm_stub_long_branch_any_any
3991 /* V4T. */
3992 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 3993
3994 /* Handle v4t short branches. */
fea2b4d6 3995 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 3996 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
3997 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 3998 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 3999 }
4000 }
4001 }
fe33d2fa
CL		 4002 else if (r_type == R_ARM_CALL
4003 || r_type == R_ARM_JUMP24
0855e32b
NS		 4004 || r_type == R_ARM_PLT32
4005 || r_type == R_ARM_TLS_CALL)
906e58ca 4006 {
35fc36a8 4007 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4008 {
4009 /* Arm to thumb. */
c820be07
NC		 4010
4011 if (sym_sec != NULL
4012 && sym_sec->owner != NULL
4013 && !INTERWORK_FLAG (sym_sec->owner))
4014 {
4015 (*_bfd_error_handler)
4016 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4017 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 4018 sym_sec->owner, input_bfd, name);
4019 }
4020
4021 /* We have an extra 2-bytes reach because of
4022 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4023 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4024 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4025 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4026 || (r_type == R_ARM_JUMP24)
4027 || (r_type == R_ARM_PLT32))
906e58ca 4028 {
0e1862bb 4029 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4030 /* PIC stubs. */
ebe24dd4
CL		 4031 ? ((globals->use_blx)
4032 /* V5T and above. */
4033 ? arm_stub_long_branch_any_thumb_pic
4034 /* V4T stub. */
4035 : arm_stub_long_branch_v4t_arm_thumb_pic)
4036
c2b4a39d
CL		 4037 /* non-PIC stubs. */
4038 : ((globals->use_blx)
4039 /* V5T and above. */
4040 ? arm_stub_long_branch_any_any
4041 /* V4T. */
4042 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4043 }
4044 }
4045 else
4046 {
4047 /* Arm to arm. */
4048 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4049 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4050 {
0855e32b 4051 stub_type =
0e1862bb 4052 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4053 /* PIC stubs. */
0855e32b 4054 ? (r_type == R_ARM_TLS_CALL
6a631e86 4055 /* TLS PIC Stub. */
0855e32b 4056 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4057 : (globals->nacl_p
4058 ? arm_stub_long_branch_arm_nacl_pic
4059 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4060 /* non-PIC stubs. */
7a89b94e
NC		 4061 : (globals->nacl_p
4062 ? arm_stub_long_branch_arm_nacl
4063 : arm_stub_long_branch_any_any);
906e58ca
NC		 4064 }
4065 }
4066 }
4067
fe33d2fa
CL		 4068 /* If a stub is needed, record the actual destination type. */
4069 if (stub_type != arm_stub_none)
35fc36a8 4070 *actual_branch_type = branch_type;
fe33d2fa 4071
906e58ca
NC		 4072 return stub_type;
4073}
4074
4075/* Build a name for an entry in the stub hash table. */
4076
4077static char *
4078elf32_arm_stub_name (const asection *input_section,
4079 const asection *sym_sec,
4080 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4081 const Elf_Internal_Rela *rel,
4082 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4083{
4084 char *stub_name;
4085 bfd_size_type len;
4086
4087 if (hash)
4088 {
fe33d2fa 4089 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4090 stub_name = (char *) bfd_malloc (len);
906e58ca 4091 if (stub_name != NULL)
fe33d2fa 4092 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4093 input_section->id & 0xffffffff,
4094 hash->root.root.root.string,
fe33d2fa
CL		 4095 (int) rel->r_addend & 0xffffffff,
4096 (int) stub_type);
906e58ca
NC		 4097 }
4098 else
4099 {
fe33d2fa 4100 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4101 stub_name = (char *) bfd_malloc (len);
906e58ca 4102 if (stub_name != NULL)
fe33d2fa 4103 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4104 input_section->id & 0xffffffff,
4105 sym_sec->id & 0xffffffff,
0855e32b
NS		 4106 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4107 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4108 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4109 (int) rel->r_addend & 0xffffffff,
4110 (int) stub_type);
906e58ca
NC		 4111 }
4112
4113 return stub_name;
4114}
4115
4116/* Look up an entry in the stub hash. Stub entries are cached because
4117 creating the stub name takes a bit of time. */
4118
4119static struct elf32_arm_stub_hash_entry *
4120elf32_arm_get_stub_entry (const asection *input_section,
4121 const asection *sym_sec,
4122 struct elf_link_hash_entry *hash,
4123 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4124 struct elf32_arm_link_hash_table *htab,
4125 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4126{
4127 struct elf32_arm_stub_hash_entry *stub_entry;
4128 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4129 const asection *id_sec;
4130
4131 if ((input_section->flags & SEC_CODE) == 0)
4132 return NULL;
4133
4134 /* If this input section is part of a group of sections sharing one
4135 stub section, then use the id of the first section in the group.
4136 Stub names need to include a section id, as there may well be
4137 more than one stub used to reach say, printf, and we need to
4138 distinguish between them. */
4139 id_sec = htab->stub_group[input_section->id].link_sec;
4140
4141 if (h != NULL && h->stub_cache != NULL
4142 && h->stub_cache->h == h
fe33d2fa
CL		 4143 && h->stub_cache->id_sec == id_sec
4144 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4145 {
4146 stub_entry = h->stub_cache;
4147 }
4148 else
4149 {
4150 char *stub_name;
4151
fe33d2fa 4152 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4153 if (stub_name == NULL)
4154 return NULL;
4155
4156 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4157 stub_name, FALSE, FALSE);
4158 if (h != NULL)
4159 h->stub_cache = stub_entry;
4160
4161 free (stub_name);
4162 }
4163
4164 return stub_entry;
4165}
4166
daa4adae
TP		 4167/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4168 section. */
4169
4170static bfd_boolean
4171arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4172{
4173 if (stub_type >= max_stub_type)
4174 abort (); /* Should be unreachable. */
4175
4176 return FALSE;
4177}
4178
4179/* Required alignment (as a power of 2) for the dedicated section holding
4180 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4181 with input sections. */
4182
4183static int
4184arm_dedicated_stub_output_section_required_alignment
4185 (enum elf32_arm_stub_type stub_type)
4186{
4187 if (stub_type >= max_stub_type)
4188 abort (); /* Should be unreachable. */
4189
4190 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4191 return 0;
4192}
4193
4194/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4195 NULL if veneers of this type are interspersed with input sections. */
4196
4197static const char *
4198arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4199{
4200 if (stub_type >= max_stub_type)
4201 abort (); /* Should be unreachable. */
4202
4203 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4204 return NULL;
4205}
4206
4207/* If veneers of type STUB_TYPE should go in a dedicated output section,
4208 returns the address of the hash table field in HTAB holding a pointer to the
4209 corresponding input section. Otherwise, returns NULL. */
4210
4211static asection **
4212arm_dedicated_stub_input_section_ptr
4213 (struct elf32_arm_link_hash_table *htab ATTRIBUTE_UNUSED,
4214 enum elf32_arm_stub_type stub_type)
4215{
4216 if (stub_type >= max_stub_type)
4217 abort (); /* Should be unreachable. */
4218
4219 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4220 return NULL;
4221}
4222
4223/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4224 is the section that branch into veneer and can be NULL if stub should go in
4225 a dedicated output section. Returns a pointer to the stub section, and the
4226 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4227 LINK_SEC_P may be NULL. */
906e58ca 4228
48229727
JB		 4229static asection *
4230elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4231 struct elf32_arm_link_hash_table *htab,
4232 enum elf32_arm_stub_type stub_type)
906e58ca 4233{
daa4adae
TP		 4234 asection *link_sec, *out_sec, **stub_sec_p;
4235 const char *stub_sec_prefix;
4236 bfd_boolean dedicated_output_section =
4237 arm_dedicated_stub_output_section_required (stub_type);
4238 int align;
906e58ca 4239
daa4adae 4240 if (dedicated_output_section)
906e58ca 4241 {
daa4adae
TP		 4242 bfd *output_bfd = htab->obfd;
4243 const char *out_sec_name =
4244 arm_dedicated_stub_output_section_name (stub_type);
4245 link_sec = NULL;
4246 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4247 stub_sec_prefix = out_sec_name;
4248 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4249 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4250 if (out_sec == NULL)
906e58ca 4251 {
daa4adae
TP		 4252 (*_bfd_error_handler) (_("No address assigned to the veneers output "
4253 "section %s"), out_sec_name);
4254 return NULL;
906e58ca 4255 }
daa4adae
TP		 4256 }
4257 else
4258 {
4259 link_sec = htab->stub_group[section->id].link_sec;
4260 BFD_ASSERT (link_sec != NULL);
4261 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4262 if (*stub_sec_p == NULL)
4263 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4264 stub_sec_prefix = link_sec->name;
4265 out_sec = link_sec->output_section;
4266 align = htab->nacl_p ? 4 : 3;
906e58ca 4267 }
b38cadfb 4268
daa4adae
TP		 4269 if (*stub_sec_p == NULL)
4270 {
4271 size_t namelen;
4272 bfd_size_type len;
4273 char *s_name;
4274
4275 namelen = strlen (stub_sec_prefix);
4276 len = namelen + sizeof (STUB_SUFFIX);
4277 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4278 if (s_name == NULL)
4279 return NULL;
4280
4281 memcpy (s_name, stub_sec_prefix, namelen);
4282 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4283 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4284 align);
4285 if (*stub_sec_p == NULL)
4286 return NULL;
4287
4288 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4289 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4290 | SEC_KEEP;
4291 }
4292
4293 if (!dedicated_output_section)
4294 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4295
48229727
JB		 4296 if (link_sec_p)
4297 *link_sec_p = link_sec;
b38cadfb 4298
daa4adae 4299 return *stub_sec_p;
48229727
JB		 4300}
4301
4302/* Add a new stub entry to the stub hash. Not all fields of the new
4303 stub entry are initialised. */
4304
4305static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4306elf32_arm_add_stub (const char *stub_name, asection *section,
4307 struct elf32_arm_link_hash_table *htab,
4308 enum elf32_arm_stub_type stub_type)
48229727
JB		 4309{
4310 asection *link_sec;
4311 asection *stub_sec;
4312 struct elf32_arm_stub_hash_entry *stub_entry;
4313
daa4adae
TP		 4314 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4315 stub_type);
48229727
JB		 4316 if (stub_sec == NULL)
4317 return NULL;
906e58ca
NC		 4318
4319 /* Enter this entry into the linker stub hash table. */
4320 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4321 TRUE, FALSE);
4322 if (stub_entry == NULL)
4323 {
6bde4c52
TP		 4324 if (section == NULL)
4325 section = stub_sec;
906e58ca
NC		 4326 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4327 section->owner,
4328 stub_name);
4329 return NULL;
4330 }
4331
4332 stub_entry->stub_sec = stub_sec;
4333 stub_entry->stub_offset = 0;
4334 stub_entry->id_sec = link_sec;
4335
906e58ca
NC		 4336 return stub_entry;
4337}
4338
4339/* Store an Arm insn into an output section not processed by
4340 elf32_arm_write_section. */
4341
4342static void
8029a119
NC		 4343put_arm_insn (struct elf32_arm_link_hash_table * htab,
4344 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4345{
4346 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4347 bfd_putl32 (val, ptr);
4348 else
4349 bfd_putb32 (val, ptr);
4350}
4351
4352/* Store a 16-bit Thumb insn into an output section not processed by
4353 elf32_arm_write_section. */
4354
4355static void
8029a119
NC		 4356put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4357 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4358{
4359 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4360 bfd_putl16 (val, ptr);
4361 else
4362 bfd_putb16 (val, ptr);
4363}
4364
a504d23a
LA		 4365/* Store a Thumb2 insn into an output section not processed by
4366 elf32_arm_write_section. */
4367
4368static void
4369put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4370 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4371{
4372 /* T2 instructions are 16-bit streamed. */
4373 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4374 {
4375 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4376 bfd_putl16 ((val & 0xffff), ptr + 2);
4377 }
4378 else
4379 {
4380 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4381 bfd_putb16 ((val & 0xffff), ptr + 2);
4382 }
4383}
4384
0855e32b
NS		 4385/* If it's possible to change R_TYPE to a more efficient access
4386 model, return the new reloc type. */
4387
4388static unsigned
b38cadfb 4389elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4390 struct elf_link_hash_entry *h)
4391{
4392 int is_local = (h == NULL);
4393
0e1862bb
L		 4394 if (bfd_link_pic (info)
4395 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4396 return r_type;
4397
b38cadfb 4398 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4399 switch (r_type)
4400 {
4401 case R_ARM_TLS_GOTDESC:
4402 case R_ARM_TLS_CALL:
4403 case R_ARM_THM_TLS_CALL:
4404 case R_ARM_TLS_DESCSEQ:
4405 case R_ARM_THM_TLS_DESCSEQ:
4406 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4407 }
4408
4409 return r_type;
4410}
4411
48229727
JB		 4412static bfd_reloc_status_type elf32_arm_final_link_relocate
4413 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4414 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4415 const char *, unsigned char, enum arm_st_branch_type,
4416 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4417
4563a860
JB		 4418static unsigned int
4419arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4420{
4421 switch (stub_type)
4422 {
4423 case arm_stub_a8_veneer_b_cond:
4424 case arm_stub_a8_veneer_b:
4425 case arm_stub_a8_veneer_bl:
4426 return 2;
4427
4428 case arm_stub_long_branch_any_any:
4429 case arm_stub_long_branch_v4t_arm_thumb:
4430 case arm_stub_long_branch_thumb_only:
80c135e5 4431 case arm_stub_long_branch_thumb2_only:
4563a860
JB		 4432 case arm_stub_long_branch_v4t_thumb_thumb:
4433 case arm_stub_long_branch_v4t_thumb_arm:
4434 case arm_stub_short_branch_v4t_thumb_arm:
4435 case arm_stub_long_branch_any_arm_pic:
4436 case arm_stub_long_branch_any_thumb_pic:
4437 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4438 case arm_stub_long_branch_v4t_arm_thumb_pic:
4439 case arm_stub_long_branch_v4t_thumb_arm_pic:
4440 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4441 case arm_stub_long_branch_any_tls_pic:
4442 case arm_stub_long_branch_v4t_thumb_tls_pic:
4563a860
JB		 4443 case arm_stub_a8_veneer_blx:
4444 return 4;
b38cadfb 4445
7a89b94e
NC		 4446 case arm_stub_long_branch_arm_nacl:
4447 case arm_stub_long_branch_arm_nacl_pic:
4448 return 16;
4449
4563a860
JB		 4450 default:
4451 abort (); /* Should be unreachable. */
4452 }
4453}
4454
4f4faa4d
TP		 4455/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4456 veneering (TRUE) or have their own symbol (FALSE). */
4457
4458static bfd_boolean
4459arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4460{
4461 if (stub_type >= max_stub_type)
4462 abort (); /* Should be unreachable. */
4463
4464 return FALSE;
4465}
4466
d7c5bd02
TP		 4467/* Returns the padding needed for the dedicated section used stubs of type
4468 STUB_TYPE. */
4469
4470static int
4471arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4472{
4473 if (stub_type >= max_stub_type)
4474 abort (); /* Should be unreachable. */
4475
4476 return 0;
4477}
4478
906e58ca
NC		 4479static bfd_boolean
4480arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4481 void * in_arg)
4482{
7a89b94e 4483#define MAXRELOCS 3
906e58ca 4484 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4485 struct elf32_arm_link_hash_table *globals;
906e58ca 4486 struct bfd_link_info *info;
906e58ca
NC		 4487 asection *stub_sec;
4488 bfd *stub_bfd;
906e58ca
NC		 4489 bfd_byte *loc;
4490 bfd_vma sym_value;
4491 int template_size;
4492 int size;
d3ce72d0 4493 const insn_sequence *template_sequence;
906e58ca 4494 int i;
48229727
JB		 4495 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4496 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4497 int nrelocs = 0;
906e58ca
NC		 4498
4499 /* Massage our args to the form they really have. */
4500 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4501 info = (struct bfd_link_info *) in_arg;
4502
4503 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4504 if (globals == NULL)
4505 return FALSE;
906e58ca 4506
906e58ca
NC		 4507 stub_sec = stub_entry->stub_sec;
4508
4dfe6ac6 4509 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4510 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4511 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4512 return TRUE;
fe33d2fa 4513
906e58ca
NC		 4514 /* Make a note of the offset within the stubs for this entry. */
4515 stub_entry->stub_offset = stub_sec->size;
4516 loc = stub_sec->contents + stub_entry->stub_offset;
4517
4518 stub_bfd = stub_sec->owner;
4519
906e58ca
NC		 4520 /* This is the address of the stub destination. */
4521 sym_value = (stub_entry->target_value
4522 + stub_entry->target_section->output_offset
4523 + stub_entry->target_section->output_section->vma);
4524
d3ce72d0 4525 template_sequence = stub_entry->stub_template;
461a49ca 4526 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4527
4528 size = 0;
461a49ca 4529 for (i = 0; i < template_size; i++)
906e58ca 4530 {
d3ce72d0 4531 switch (template_sequence[i].type)
461a49ca
DJ		 4532 {
4533 case THUMB16_TYPE:
48229727 4534 {
d3ce72d0
NC		 4535 bfd_vma data = (bfd_vma) template_sequence[i].data;
4536 if (template_sequence[i].reloc_addend != 0)
48229727 4537 {
99059e56
RM		 4538 /* We've borrowed the reloc_addend field to mean we should
4539 insert a condition code into this (Thumb-1 branch)
4540 instruction. See THUMB16_BCOND_INSN. */
4541 BFD_ASSERT ((data & 0xff00) == 0xd000);
4542 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4543 }
fe33d2fa 4544 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4545 size += 2;
4546 }
461a49ca 4547 break;
906e58ca 4548
48229727 4549 case THUMB32_TYPE:
fe33d2fa
CL		 4550 bfd_put_16 (stub_bfd,
4551 (template_sequence[i].data >> 16) & 0xffff,
4552 loc + size);
4553 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4554 loc + size + 2);
99059e56
RM		 4555 if (template_sequence[i].r_type != R_ARM_NONE)
4556 {
4557 stub_reloc_idx[nrelocs] = i;
4558 stub_reloc_offset[nrelocs++] = size;
4559 }
4560 size += 4;
4561 break;
48229727 4562
461a49ca 4563 case ARM_TYPE:
fe33d2fa
CL		 4564 bfd_put_32 (stub_bfd, template_sequence[i].data,
4565 loc + size);
461a49ca
DJ		 4566 /* Handle cases where the target is encoded within the
4567 instruction. */
d3ce72d0 4568 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4569 {
48229727
JB		 4570 stub_reloc_idx[nrelocs] = i;
4571 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4572 }
4573 size += 4;
4574 break;
4575
4576 case DATA_TYPE:
d3ce72d0 4577 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4578 stub_reloc_idx[nrelocs] = i;
4579 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4580 size += 4;
4581 break;
4582
4583 default:
4584 BFD_FAIL ();
4585 return FALSE;
4586 }
906e58ca 4587 }
461a49ca 4588
906e58ca
NC		 4589 stub_sec->size += size;
4590
461a49ca
DJ		 4591 /* Stub size has already been computed in arm_size_one_stub. Check
4592 consistency. */
4593 BFD_ASSERT (size == stub_entry->stub_size);
4594
906e58ca 4595 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4596 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4597 sym_value |= 1;
4598
48229727
JB		 4599 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4600 in each stub. */
4601 BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS);
c820be07 4602
48229727 4603 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4604 {
4605 Elf_Internal_Rela rel;
4606 bfd_boolean unresolved_reloc;
4607 char *error_message;
4608 bfd_vma points_to =
4609 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4610
4611 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4612 rel.r_info = ELF32_R_INFO (0,
4613 template_sequence[stub_reloc_idx[i]].r_type);
4614 rel.r_addend = 0;
4615
4616 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4617 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4618 template should refer back to the instruction after the original
4619 branch. We use target_section as Cortex-A8 erratum workaround stubs
4620 are only generated when both source and target are in the same
4621 section. */
4622 points_to = stub_entry->target_section->output_section->vma
4623 + stub_entry->target_section->output_offset
4624 + stub_entry->source_value;
4625
4626 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4627 (template_sequence[stub_reloc_idx[i]].r_type),
4628 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4629 points_to, info, stub_entry->target_section, "", STT_FUNC,
4630 stub_entry->branch_type,
4631 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4632 &error_message);
4633 }
906e58ca
NC		 4634
4635 return TRUE;
48229727 4636#undef MAXRELOCS
906e58ca
NC		 4637}
4638
48229727
JB		 4639/* Calculate the template, template size and instruction size for a stub.
4640 Return value is the instruction size. */
906e58ca 4641
48229727
JB		 4642static unsigned int
4643find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4644 const insn_sequence **stub_template,
4645 int *stub_template_size)
906e58ca 4646{
d3ce72d0 4647 const insn_sequence *template_sequence = NULL;
48229727
JB		 4648 int template_size = 0, i;
4649 unsigned int size;
906e58ca 4650
d3ce72d0 4651 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4652 if (stub_template)
4653 *stub_template = template_sequence;
4654
48229727 4655 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4656 if (stub_template_size)
4657 *stub_template_size = template_size;
906e58ca
NC		 4658
4659 size = 0;
461a49ca
DJ		 4660 for (i = 0; i < template_size; i++)
4661 {
d3ce72d0 4662 switch (template_sequence[i].type)
461a49ca
DJ		 4663 {
4664 case THUMB16_TYPE:
4665 size += 2;
4666 break;
4667
4668 case ARM_TYPE:
48229727 4669 case THUMB32_TYPE:
461a49ca
DJ		 4670 case DATA_TYPE:
4671 size += 4;
4672 break;
4673
4674 default:
4675 BFD_FAIL ();
2a229407 4676 return 0;
461a49ca
DJ		 4677 }
4678 }
4679
48229727
JB		 4680 return size;
4681}
4682
4683/* As above, but don't actually build the stub. Just bump offset so
4684 we know stub section sizes. */
4685
4686static bfd_boolean
4687arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4688 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4689{
4690 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4691 const insn_sequence *template_sequence;
48229727
JB		 4692 int template_size, size;
4693
4694 /* Massage our args to the form they really have. */
4695 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4696
4697 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4698 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4699
d3ce72d0 4700 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4701 &template_size);
4702
461a49ca 4703 stub_entry->stub_size = size;
d3ce72d0 4704 stub_entry->stub_template = template_sequence;
461a49ca
DJ		 4705 stub_entry->stub_template_size = template_size;
4706
906e58ca
NC		 4707 size = (size + 7) & ~7;
4708 stub_entry->stub_sec->size += size;
461a49ca 4709
906e58ca
NC		 4710 return TRUE;
4711}
4712
4713/* External entry points for sizing and building linker stubs. */
4714
4715/* Set up various things so that we can make a list of input sections
4716 for each output section included in the link. Returns -1 on error,
4717 0 when no stubs will be needed, and 1 on success. */
4718
4719int
4720elf32_arm_setup_section_lists (bfd *output_bfd,
4721 struct bfd_link_info *info)
4722{
4723 bfd *input_bfd;
4724 unsigned int bfd_count;
7292b3ac 4725 unsigned int top_id, top_index;
906e58ca
NC		 4726 asection *section;
4727 asection **input_list, **list;
4728 bfd_size_type amt;
4729 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4730
4dfe6ac6
NC		 4731 if (htab == NULL)
4732 return 0;
906e58ca
NC		 4733 if (! is_elf_hash_table (htab))
4734 return 0;
4735
4736 /* Count the number of input BFDs and find the top input section id. */
4737 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4738 input_bfd != NULL;
c72f2fb2 4739 input_bfd = input_bfd->link.next)
906e58ca
NC		 4740 {
4741 bfd_count += 1;
4742 for (section = input_bfd->sections;
4743 section != NULL;
4744 section = section->next)
4745 {
4746 if (top_id < section->id)
4747 top_id = section->id;
4748 }
4749 }
4750 htab->bfd_count = bfd_count;
4751
4752 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4753 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4754 if (htab->stub_group == NULL)
4755 return -1;
fe33d2fa 4756 htab->top_id = top_id;
906e58ca
NC		 4757
4758 /* We can't use output_bfd->section_count here to find the top output
4759 section index as some sections may have been removed, and
4760 _bfd_strip_section_from_output doesn't renumber the indices. */
4761 for (section = output_bfd->sections, top_index = 0;
4762 section != NULL;
4763 section = section->next)
4764 {
4765 if (top_index < section->index)
4766 top_index = section->index;
4767 }
4768
4769 htab->top_index = top_index;
4770 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4771 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4772 htab->input_list = input_list;
4773 if (input_list == NULL)
4774 return -1;
4775
4776 /* For sections we aren't interested in, mark their entries with a
4777 value we can check later. */
4778 list = input_list + top_index;
4779 do
4780 *list = bfd_abs_section_ptr;
4781 while (list-- != input_list);
4782
4783 for (section = output_bfd->sections;
4784 section != NULL;
4785 section = section->next)
4786 {
4787 if ((section->flags & SEC_CODE) != 0)
4788 input_list[section->index] = NULL;
4789 }
4790
4791 return 1;
4792}
4793
4794/* The linker repeatedly calls this function for each input section,
4795 in the order that input sections are linked into output sections.
4796 Build lists of input sections to determine groupings between which
4797 we may insert linker stubs. */
4798
4799void
4800elf32_arm_next_input_section (struct bfd_link_info *info,
4801 asection *isec)
4802{
4803 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4804
4dfe6ac6
NC		 4805 if (htab == NULL)
4806 return;
4807
906e58ca
NC		 4808 if (isec->output_section->index <= htab->top_index)
4809 {
4810 asection **list = htab->input_list + isec->output_section->index;
4811
a7470592 4812 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 4813 {
4814 /* Steal the link_sec pointer for our list. */
4815#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4816 /* This happens to make the list in reverse order,
07d72278 4817 which we reverse later. */
906e58ca
NC		 4818 PREV_SEC (isec) = *list;
4819 *list = isec;
4820 }
4821 }
4822}
4823
4824/* See whether we can group stub sections together. Grouping stub
4825 sections may result in fewer stubs. More importantly, we need to
07d72278 4826 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 4827 .fini output sections respectively, because glibc splits the
4828 _init and _fini functions into multiple parts. Putting a stub in
4829 the middle of a function is not a good idea. */
4830
4831static void
4832group_sections (struct elf32_arm_link_hash_table *htab,
4833 bfd_size_type stub_group_size,
07d72278 4834 bfd_boolean stubs_always_after_branch)
906e58ca 4835{
07d72278 4836 asection **list = htab->input_list;
906e58ca
NC		 4837
4838 do
4839 {
4840 asection *tail = *list;
07d72278 4841 asection *head;
906e58ca
NC		 4842
4843 if (tail == bfd_abs_section_ptr)
4844 continue;
4845
07d72278
DJ		 4846 /* Reverse the list: we must avoid placing stubs at the
4847 beginning of the section because the beginning of the text
4848 section may be required for an interrupt vector in bare metal
4849 code. */
4850#define NEXT_SEC PREV_SEC
e780aef2
CL		 4851 head = NULL;
4852 while (tail != NULL)
99059e56
RM		 4853 {
4854 /* Pop from tail. */
4855 asection *item = tail;
4856 tail = PREV_SEC (item);
e780aef2 4857
99059e56
RM		 4858 /* Push on head. */
4859 NEXT_SEC (item) = head;
4860 head = item;
4861 }
07d72278
DJ		 4862
4863 while (head != NULL)
906e58ca
NC		 4864 {
4865 asection *curr;
07d72278 4866 asection *next;
e780aef2
CL		 4867 bfd_vma stub_group_start = head->output_offset;
4868 bfd_vma end_of_next;
906e58ca 4869
07d72278 4870 curr = head;
e780aef2 4871 while (NEXT_SEC (curr) != NULL)
8cd931b7 4872 {
e780aef2
CL		 4873 next = NEXT_SEC (curr);
4874 end_of_next = next->output_offset + next->size;
4875 if (end_of_next - stub_group_start >= stub_group_size)
4876 /* End of NEXT is too far from start, so stop. */
8cd931b7 4877 break;
e780aef2
CL		 4878 /* Add NEXT to the group. */
4879 curr = next;
8cd931b7 4880 }
906e58ca 4881
07d72278 4882 /* OK, the size from the start to the start of CURR is less
906e58ca 4883 than stub_group_size and thus can be handled by one stub
07d72278 4884 section. (Or the head section is itself larger than
906e58ca
NC		 4885 stub_group_size, in which case we may be toast.)
4886 We should really be keeping track of the total size of
4887 stubs added here, as stubs contribute to the final output
7fb9f789 4888 section size. */
906e58ca
NC		 4889 do
4890 {
07d72278 4891 next = NEXT_SEC (head);
906e58ca 4892 /* Set up this stub group. */
07d72278 4893 htab->stub_group[head->id].link_sec = curr;
906e58ca 4894 }
07d72278 4895 while (head != curr && (head = next) != NULL);
906e58ca
NC		 4896
4897 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 4898 bytes after the stub section can be handled by it too. */
4899 if (!stubs_always_after_branch)
906e58ca 4900 {
e780aef2
CL		 4901 stub_group_start = curr->output_offset + curr->size;
4902
8cd931b7 4903 while (next != NULL)
906e58ca 4904 {
e780aef2
CL		 4905 end_of_next = next->output_offset + next->size;
4906 if (end_of_next - stub_group_start >= stub_group_size)
4907 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 4908 break;
e780aef2 4909 /* Add NEXT to the stub group. */
07d72278
DJ		 4910 head = next;
4911 next = NEXT_SEC (head);
4912 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 4913 }
4914 }
07d72278 4915 head = next;
906e58ca
NC		 4916 }
4917 }
07d72278 4918 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 4919
4920 free (htab->input_list);
4921#undef PREV_SEC
07d72278 4922#undef NEXT_SEC
906e58ca
NC		 4923}
4924
48229727
JB		 4925/* Comparison function for sorting/searching relocations relating to Cortex-A8
4926 erratum fix. */
4927
4928static int
4929a8_reloc_compare (const void *a, const void *b)
4930{
21d799b5
NC		 4931 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
4932 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 4933
4934 if (ra->from < rb->from)
4935 return -1;
4936 else if (ra->from > rb->from)
4937 return 1;
4938 else
4939 return 0;
4940}
4941
4942static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
4943 const char *, char **);
4944
4945/* Helper function to scan code for sequences which might trigger the Cortex-A8
4946 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 4947 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 4948 otherwise. */
4949
81694485
NC		 4950static bfd_boolean
4951cortex_a8_erratum_scan (bfd *input_bfd,
4952 struct bfd_link_info *info,
48229727
JB		 4953 struct a8_erratum_fix **a8_fixes_p,
4954 unsigned int *num_a8_fixes_p,
4955 unsigned int *a8_fix_table_size_p,
4956 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 4957 unsigned int num_a8_relocs,
4958 unsigned prev_num_a8_fixes,
4959 bfd_boolean *stub_changed_p)
48229727
JB		 4960{
4961 asection *section;
4962 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4963 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
4964 unsigned int num_a8_fixes = *num_a8_fixes_p;
4965 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
4966
4dfe6ac6
NC		 4967 if (htab == NULL)
4968 return FALSE;
4969
48229727
JB		 4970 for (section = input_bfd->sections;
4971 section != NULL;
4972 section = section->next)
4973 {
4974 bfd_byte *contents = NULL;
4975 struct _arm_elf_section_data *sec_data;
4976 unsigned int span;
4977 bfd_vma base_vma;
4978
4979 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 4980 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
4981 || (section->flags & SEC_EXCLUDE) != 0
4982 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
4983 || (section->output_section == bfd_abs_section_ptr))
4984 continue;
48229727
JB		 4985
4986 base_vma = section->output_section->vma + section->output_offset;
4987
4988 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 4989 contents = elf_section_data (section)->this_hdr.contents;
48229727 4990 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 4991 return TRUE;
48229727
JB		 4992
4993 sec_data = elf32_arm_section_data (section);
4994
4995 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 4996 {
4997 unsigned int span_start = sec_data->map[span].vma;
4998 unsigned int span_end = (span == sec_data->mapcount - 1)
4999 ? section->size : sec_data->map[span + 1].vma;
5000 unsigned int i;
5001 char span_type = sec_data->map[span].type;
5002 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5003
5004 if (span_type != 't')
5005 continue;
5006
5007 /* Span is entirely within a single 4KB region: skip scanning. */
5008 if (((base_vma + span_start) & ~0xfff)
48229727 5009 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5010 continue;
5011
5012 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5013
5014 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5015 * The branch target is in the same 4KB region as the
5016 first half of the branch.
5017 * The instruction before the branch is a 32-bit
5018 length non-branch instruction. */
5019 for (i = span_start; i < span_end;)
5020 {
5021 unsigned int insn = bfd_getl16 (&contents[i]);
5022 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5023 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5024
99059e56
RM		 5025 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5026 insn_32bit = TRUE;
48229727
JB		 5027
5028 if (insn_32bit)
99059e56
RM		 5029 {
5030 /* Load the rest of the insn (in manual-friendly order). */
5031 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5032
5033 /* Encoding T4: B<c>.W. */
5034 is_b = (insn & 0xf800d000) == 0xf0009000;
5035 /* Encoding T1: BL<c>.W. */
5036 is_bl = (insn & 0xf800d000) == 0xf000d000;
5037 /* Encoding T2: BLX<c>.W. */
5038 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5039 /* Encoding T3: B<c>.W (not permitted in IT block). */
5040 is_bcc = (insn & 0xf800d000) == 0xf0008000
5041 && (insn & 0x07f00000) != 0x03800000;
5042 }
5043
5044 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5045
99059e56 5046 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5047 && insn_32bit
5048 && is_32bit_branch
5049 && last_was_32bit
5050 && ! last_was_branch)
99059e56
RM		 5051 {
5052 bfd_signed_vma offset = 0;
5053 bfd_boolean force_target_arm = FALSE;
48229727 5054 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5055 bfd_vma target;
5056 enum elf32_arm_stub_type stub_type = arm_stub_none;
5057 struct a8_erratum_reloc key, *found;
5058 bfd_boolean use_plt = FALSE;
48229727 5059
99059e56
RM		 5060 key.from = base_vma + i;
5061 found = (struct a8_erratum_reloc *)
5062 bsearch (&key, a8_relocs, num_a8_relocs,
5063 sizeof (struct a8_erratum_reloc),
5064 &a8_reloc_compare);
48229727
JB		 5065
5066 if (found)
5067 {
5068 char *error_message = NULL;
5069 struct elf_link_hash_entry *entry;
5070
5071 /* We don't care about the error returned from this
99059e56 5072 function, only if there is glue or not. */
48229727
JB		 5073 entry = find_thumb_glue (info, found->sym_name,
5074 &error_message);
5075
5076 if (entry)
5077 found->non_a8_stub = TRUE;
5078
92750f34 5079 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5080 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5081 && found->hash->root.plt.offset != (bfd_vma) -1)
5082 use_plt = TRUE;
5083
5084 if (found->r_type == R_ARM_THM_CALL)
5085 {
35fc36a8
RS		 5086 if (found->branch_type == ST_BRANCH_TO_ARM
5087 || use_plt)
92750f34
DJ		 5088 force_target_arm = TRUE;
5089 else
5090 force_target_thumb = TRUE;
5091 }
48229727
JB		 5092 }
5093
99059e56 5094 /* Check if we have an offending branch instruction. */
48229727
JB		 5095
5096 if (found && found->non_a8_stub)
5097 /* We've already made a stub for this instruction, e.g.
5098 it's a long branch or a Thumb->ARM stub. Assume that
5099 stub will suffice to work around the A8 erratum (see
5100 setting of always_after_branch above). */
5101 ;
99059e56
RM		 5102 else if (is_bcc)
5103 {
5104 offset = (insn & 0x7ff) << 1;
5105 offset |= (insn & 0x3f0000) >> 4;
5106 offset |= (insn & 0x2000) ? 0x40000 : 0;
5107 offset |= (insn & 0x800) ? 0x80000 : 0;
5108 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5109 if (offset & 0x100000)
5110 offset |= ~ ((bfd_signed_vma) 0xfffff);
5111 stub_type = arm_stub_a8_veneer_b_cond;
5112 }
5113 else if (is_b || is_bl || is_blx)
5114 {
5115 int s = (insn & 0x4000000) != 0;
5116 int j1 = (insn & 0x2000) != 0;
5117 int j2 = (insn & 0x800) != 0;
5118 int i1 = !(j1 ^ s);
5119 int i2 = !(j2 ^ s);
5120
5121 offset = (insn & 0x7ff) << 1;
5122 offset |= (insn & 0x3ff0000) >> 4;
5123 offset |= i2 << 22;
5124 offset |= i1 << 23;
5125 offset |= s << 24;
5126 if (offset & 0x1000000)
5127 offset |= ~ ((bfd_signed_vma) 0xffffff);
5128
5129 if (is_blx)
5130 offset &= ~ ((bfd_signed_vma) 3);
5131
5132 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5133 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5134 }
5135
5136 if (stub_type != arm_stub_none)
5137 {
5138 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5139
5140 /* The original instruction is a BL, but the target is
99059e56 5141 an ARM instruction. If we were not making a stub,
48229727
JB		 5142 the BL would have been converted to a BLX. Use the
5143 BLX stub instead in that case. */
5144 if (htab->use_blx && force_target_arm
5145 && stub_type == arm_stub_a8_veneer_bl)
5146 {
5147 stub_type = arm_stub_a8_veneer_blx;
5148 is_blx = TRUE;
5149 is_bl = FALSE;
5150 }
5151 /* Conversely, if the original instruction was
5152 BLX but the target is Thumb mode, use the BL
5153 stub. */
5154 else if (force_target_thumb
5155 && stub_type == arm_stub_a8_veneer_blx)
5156 {
5157 stub_type = arm_stub_a8_veneer_bl;
5158 is_blx = FALSE;
5159 is_bl = TRUE;
5160 }
5161
99059e56
RM		 5162 if (is_blx)
5163 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5164
99059e56
RM		 5165 /* If we found a relocation, use the proper destination,
5166 not the offset in the (unrelocated) instruction.
48229727
JB		 5167 Note this is always done if we switched the stub type
5168 above. */
99059e56
RM		 5169 if (found)
5170 offset =
81694485 5171 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5172
99059e56
RM		 5173 /* If the stub will use a Thumb-mode branch to a
5174 PLT target, redirect it to the preceding Thumb
5175 entry point. */
5176 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5177 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5178
99059e56 5179 target = pc_for_insn + offset;
48229727 5180
99059e56
RM		 5181 /* The BLX stub is ARM-mode code. Adjust the offset to
5182 take the different PC value (+8 instead of +4) into
48229727 5183 account. */
99059e56
RM		 5184 if (stub_type == arm_stub_a8_veneer_blx)
5185 offset += 4;
5186
5187 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5188 {
5189 char *stub_name = NULL;
5190
5191 if (num_a8_fixes == a8_fix_table_size)
5192 {
5193 a8_fix_table_size *= 2;
5194 a8_fixes = (struct a8_erratum_fix *)
5195 bfd_realloc (a8_fixes,
5196 sizeof (struct a8_erratum_fix)
5197 * a8_fix_table_size);
5198 }
48229727 5199
eb7c4339
NS		 5200 if (num_a8_fixes < prev_num_a8_fixes)
5201 {
5202 /* If we're doing a subsequent scan,
5203 check if we've found the same fix as
5204 before, and try and reuse the stub
5205 name. */
5206 stub_name = a8_fixes[num_a8_fixes].stub_name;
5207 if ((a8_fixes[num_a8_fixes].section != section)
5208 || (a8_fixes[num_a8_fixes].offset != i))
5209 {
5210 free (stub_name);
5211 stub_name = NULL;
5212 *stub_changed_p = TRUE;
5213 }
5214 }
5215
5216 if (!stub_name)
5217 {
21d799b5 5218 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5219 if (stub_name != NULL)
5220 sprintf (stub_name, "%x:%x", section->id, i);
5221 }
48229727 5222
99059e56
RM		 5223 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5224 a8_fixes[num_a8_fixes].section = section;
5225 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5226 a8_fixes[num_a8_fixes].target_offset =
5227 target - base_vma;
99059e56
RM		 5228 a8_fixes[num_a8_fixes].orig_insn = insn;
5229 a8_fixes[num_a8_fixes].stub_name = stub_name;
5230 a8_fixes[num_a8_fixes].stub_type = stub_type;
5231 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5232 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5233
99059e56
RM		 5234 num_a8_fixes++;
5235 }
5236 }
5237 }
48229727 5238
99059e56
RM		 5239 i += insn_32bit ? 4 : 2;
5240 last_was_32bit = insn_32bit;
48229727 5241 last_was_branch = is_32bit_branch;
99059e56
RM		 5242 }
5243 }
48229727
JB		 5244
5245 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5246 free (contents);
48229727 5247 }
fe33d2fa 5248
48229727
JB		 5249 *a8_fixes_p = a8_fixes;
5250 *num_a8_fixes_p = num_a8_fixes;
5251 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5252
81694485 5253 return FALSE;
48229727
JB		 5254}
5255
b715f643
TP		 5256/* Create or update a stub entry depending on whether the stub can already be
5257 found in HTAB. The stub is identified by:
5258 - its type STUB_TYPE
5259 - its source branch (note that several can share the same stub) whose
5260 section and relocation (if any) are given by SECTION and IRELA
5261 respectively
5262 - its target symbol whose input section, hash, name, value and branch type
5263 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5264 respectively
5265
5266 If found, the value of the stub's target symbol is updated from SYM_VALUE
5267 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5268 TRUE and the stub entry is initialized.
5269
5270 Returns whether the stub could be successfully created or updated, or FALSE
5271 if an error occured. */
5272
5273static bfd_boolean
5274elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5275 enum elf32_arm_stub_type stub_type, asection *section,
5276 Elf_Internal_Rela *irela, asection *sym_sec,
5277 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5278 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5279 bfd_boolean *new_stub)
5280{
5281 const asection *id_sec;
5282 char *stub_name;
5283 struct elf32_arm_stub_hash_entry *stub_entry;
5284 unsigned int r_type;
4f4faa4d 5285 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5286
5287 BFD_ASSERT (stub_type != arm_stub_none);
5288 *new_stub = FALSE;
5289
4f4faa4d
TP		 5290 if (sym_claimed)
5291 stub_name = sym_name;
5292 else
5293 {
5294 BFD_ASSERT (irela);
5295 BFD_ASSERT (section);
b715f643 5296
4f4faa4d
TP		 5297 /* Support for grouping stub sections. */
5298 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5299
4f4faa4d
TP		 5300 /* Get the name of this stub. */
5301 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5302 stub_type);
5303 if (!stub_name)
5304 return FALSE;
5305 }
b715f643
TP		 5306
5307 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5308 FALSE);
5309 /* The proper stub has already been created, just update its value. */
5310 if (stub_entry != NULL)
5311 {
4f4faa4d
TP		 5312 if (!sym_claimed)
5313 free (stub_name);
b715f643
TP		 5314 stub_entry->target_value = sym_value;
5315 return TRUE;
5316 }
5317
daa4adae 5318 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5319 if (stub_entry == NULL)
5320 {
4f4faa4d
TP		 5321 if (!sym_claimed)
5322 free (stub_name);
b715f643
TP		 5323 return FALSE;
5324 }
5325
5326 stub_entry->target_value = sym_value;
5327 stub_entry->target_section = sym_sec;
5328 stub_entry->stub_type = stub_type;
5329 stub_entry->h = hash;
5330 stub_entry->branch_type = branch_type;
5331
4f4faa4d
TP		 5332 if (sym_claimed)
5333 stub_entry->output_name = sym_name;
5334 else
b715f643 5335 {
4f4faa4d
TP		 5336 if (sym_name == NULL)
5337 sym_name = "unnamed";
5338 stub_entry->output_name = (char *)
5339 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5340 + strlen (sym_name));
5341 if (stub_entry->output_name == NULL)
5342 {
5343 free (stub_name);
5344 return FALSE;
5345 }
b715f643 5346
4f4faa4d
TP		 5347 /* For historical reasons, use the existing names for ARM-to-Thumb and
5348 Thumb-to-ARM stubs. */
5349 r_type = ELF32_R_TYPE (irela->r_info);
5350 if ((r_type == (unsigned int) R_ARM_THM_CALL
5351 || r_type == (unsigned int) R_ARM_THM_JUMP24
5352 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5353 && branch_type == ST_BRANCH_TO_ARM)
5354 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5355 else if ((r_type == (unsigned int) R_ARM_CALL
5356 || r_type == (unsigned int) R_ARM_JUMP24)
5357 && branch_type == ST_BRANCH_TO_THUMB)
5358 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5359 else
5360 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5361 }
b715f643
TP		 5362
5363 *new_stub = TRUE;
5364 return TRUE;
5365}
5366
906e58ca
NC		 5367/* Determine and set the size of the stub section for a final link.
5368
5369 The basic idea here is to examine all the relocations looking for
5370 PC-relative calls to a target that is unreachable with a "bl"
5371 instruction. */
5372
5373bfd_boolean
5374elf32_arm_size_stubs (bfd *output_bfd,
5375 bfd *stub_bfd,
5376 struct bfd_link_info *info,
5377 bfd_signed_vma group_size,
7a89b94e 5378 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 5379 asection *,
7a89b94e 5380 unsigned int),
906e58ca
NC		 5381 void (*layout_sections_again) (void))
5382{
5383 bfd_size_type stub_group_size;
07d72278 5384 bfd_boolean stubs_always_after_branch;
906e58ca 5385 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 5386 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 5387 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 5388 struct a8_erratum_reloc *a8_relocs = NULL;
5389 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
5390
4dfe6ac6
NC		 5391 if (htab == NULL)
5392 return FALSE;
5393
48229727
JB		 5394 if (htab->fix_cortex_a8)
5395 {
21d799b5 5396 a8_fixes = (struct a8_erratum_fix *)
99059e56 5397 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 5398 a8_relocs = (struct a8_erratum_reloc *)
99059e56 5399 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 5400 }
906e58ca
NC		 5401
5402 /* Propagate mach to stub bfd, because it may not have been
5403 finalized when we created stub_bfd. */
5404 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
5405 bfd_get_mach (output_bfd));
5406
5407 /* Stash our params away. */
5408 htab->stub_bfd = stub_bfd;
5409 htab->add_stub_section = add_stub_section;
5410 htab->layout_sections_again = layout_sections_again;
07d72278 5411 stubs_always_after_branch = group_size < 0;
48229727
JB		 5412
5413 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5414 as the first half of a 32-bit branch straddling two 4K pages. This is a
5415 crude way of enforcing that. */
5416 if (htab->fix_cortex_a8)
5417 stubs_always_after_branch = 1;
5418
906e58ca
NC		 5419 if (group_size < 0)
5420 stub_group_size = -group_size;
5421 else
5422 stub_group_size = group_size;
5423
5424 if (stub_group_size == 1)
5425 {
5426 /* Default values. */
5427 /* Thumb branch range is +-4MB has to be used as the default
5428 maximum size (a given section can contain both ARM and Thumb
5429 code, so the worst case has to be taken into account).
5430
5431 This value is 24K less than that, which allows for 2025
5432 12-byte stubs. If we exceed that, then we will fail to link.
5433 The user will have to relink with an explicit group size
5434 option. */
5435 stub_group_size = 4170000;
5436 }
5437
07d72278 5438 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 5439
3ae046cc
NS		 5440 /* If we're applying the cortex A8 fix, we need to determine the
5441 program header size now, because we cannot change it later --
5442 that could alter section placements. Notice the A8 erratum fix
5443 ends up requiring the section addresses to remain unchanged
5444 modulo the page size. That's something we cannot represent
5445 inside BFD, and we don't want to force the section alignment to
5446 be the page size. */
5447 if (htab->fix_cortex_a8)
5448 (*htab->layout_sections_again) ();
5449
906e58ca
NC		 5450 while (1)
5451 {
5452 bfd *input_bfd;
5453 unsigned int bfd_indx;
5454 asection *stub_sec;
d7c5bd02 5455 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 5456 bfd_boolean stub_changed = FALSE;
5457 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 5458
48229727 5459 num_a8_fixes = 0;
906e58ca
NC		 5460 for (input_bfd = info->input_bfds, bfd_indx = 0;
5461 input_bfd != NULL;
c72f2fb2 5462 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 5463 {
5464 Elf_Internal_Shdr *symtab_hdr;
5465 asection *section;
5466 Elf_Internal_Sym *local_syms = NULL;
5467
99059e56
RM		 5468 if (!is_arm_elf (input_bfd))
5469 continue;
adbcc655 5470
48229727
JB		 5471 num_a8_relocs = 0;
5472
906e58ca
NC		 5473 /* We'll need the symbol table in a second. */
5474 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5475 if (symtab_hdr->sh_info == 0)
5476 continue;
5477
5478 /* Walk over each section attached to the input bfd. */
5479 for (section = input_bfd->sections;
5480 section != NULL;
5481 section = section->next)
5482 {
5483 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
5484
5485 /* If there aren't any relocs, then there's nothing more
5486 to do. */
5487 if ((section->flags & SEC_RELOC) == 0
5488 || section->reloc_count == 0
5489 || (section->flags & SEC_CODE) == 0)
5490 continue;
5491
5492 /* If this section is a link-once section that will be
5493 discarded, then don't create any stubs. */
5494 if (section->output_section == NULL
5495 || section->output_section->owner != output_bfd)
5496 continue;
5497
5498 /* Get the relocs. */
5499 internal_relocs
5500 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
5501 NULL, info->keep_memory);
5502 if (internal_relocs == NULL)
5503 goto error_ret_free_local;
5504
5505 /* Now examine each relocation. */
5506 irela = internal_relocs;
5507 irelaend = irela + section->reloc_count;
5508 for (; irela < irelaend; irela++)
5509 {
5510 unsigned int r_type, r_indx;
906e58ca
NC		 5511 asection *sym_sec;
5512 bfd_vma sym_value;
5513 bfd_vma destination;
5514 struct elf32_arm_link_hash_entry *hash;
7413f23f 5515 const char *sym_name;
34e77a92 5516 unsigned char st_type;
35fc36a8 5517 enum arm_st_branch_type branch_type;
48229727 5518 bfd_boolean created_stub = FALSE;
906e58ca
NC		 5519
5520 r_type = ELF32_R_TYPE (irela->r_info);
5521 r_indx = ELF32_R_SYM (irela->r_info);
5522
5523 if (r_type >= (unsigned int) R_ARM_max)
5524 {
5525 bfd_set_error (bfd_error_bad_value);
5526 error_ret_free_internal:
5527 if (elf_section_data (section)->relocs == NULL)
5528 free (internal_relocs);
15dd01b1
TP		 5529 /* Fall through. */
5530 error_ret_free_local:
5531 if (local_syms != NULL
5532 && (symtab_hdr->contents
5533 != (unsigned char *) local_syms))
5534 free (local_syms);
5535 return FALSE;
906e58ca 5536 }
b38cadfb 5537
0855e32b
NS		 5538 hash = NULL;
5539 if (r_indx >= symtab_hdr->sh_info)
5540 hash = elf32_arm_hash_entry
5541 (elf_sym_hashes (input_bfd)
5542 [r_indx - symtab_hdr->sh_info]);
b38cadfb 5543
0855e32b
NS		 5544 /* Only look for stubs on branch instructions, or
5545 non-relaxed TLSCALL */
906e58ca 5546 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 5547 && (r_type != (unsigned int) R_ARM_THM_CALL)
5548 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 5549 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
5550 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 5551 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 5552 && (r_type != (unsigned int) R_ARM_PLT32)
5553 && !((r_type == (unsigned int) R_ARM_TLS_CALL
5554 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5555 && r_type == elf32_arm_tls_transition
5556 (info, r_type, &hash->root)
5557 && ((hash ? hash->tls_type
5558 : (elf32_arm_local_got_tls_type
5559 (input_bfd)[r_indx]))
5560 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 5561 continue;
5562
5563 /* Now determine the call target, its name, value,
5564 section. */
5565 sym_sec = NULL;
5566 sym_value = 0;
5567 destination = 0;
7413f23f 5568 sym_name = NULL;
b38cadfb 5569
0855e32b
NS		 5570 if (r_type == (unsigned int) R_ARM_TLS_CALL
5571 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5572 {
5573 /* A non-relaxed TLS call. The target is the
5574 plt-resident trampoline and nothing to do
5575 with the symbol. */
5576 BFD_ASSERT (htab->tls_trampoline > 0);
5577 sym_sec = htab->root.splt;
5578 sym_value = htab->tls_trampoline;
5579 hash = 0;
34e77a92 5580 st_type = STT_FUNC;
35fc36a8 5581 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 5582 }
5583 else if (!hash)
906e58ca
NC		 5584 {
5585 /* It's a local symbol. */
5586 Elf_Internal_Sym *sym;
906e58ca
NC		 5587
5588 if (local_syms == NULL)
5589 {
5590 local_syms
5591 = (Elf_Internal_Sym *) symtab_hdr->contents;
5592 if (local_syms == NULL)
5593 local_syms
5594 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5595 symtab_hdr->sh_info, 0,
5596 NULL, NULL, NULL);
5597 if (local_syms == NULL)
5598 goto error_ret_free_internal;
5599 }
5600
5601 sym = local_syms + r_indx;
f6d250ce
TS		 5602 if (sym->st_shndx == SHN_UNDEF)
5603 sym_sec = bfd_und_section_ptr;
5604 else if (sym->st_shndx == SHN_ABS)
5605 sym_sec = bfd_abs_section_ptr;
5606 else if (sym->st_shndx == SHN_COMMON)
5607 sym_sec = bfd_com_section_ptr;
5608 else
5609 sym_sec =
5610 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
5611
ffcb4889
NS		 5612 if (!sym_sec)
5613 /* This is an undefined symbol. It can never
6a631e86 5614 be resolved. */
ffcb4889 5615 continue;
fe33d2fa 5616
906e58ca
NC		 5617 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
5618 sym_value = sym->st_value;
5619 destination = (sym_value + irela->r_addend
5620 + sym_sec->output_offset
5621 + sym_sec->output_section->vma);
34e77a92 5622 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 5623 branch_type =
5624 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 5625 sym_name
5626 = bfd_elf_string_from_elf_section (input_bfd,
5627 symtab_hdr->sh_link,
5628 sym->st_name);
906e58ca
NC		 5629 }
5630 else
5631 {
5632 /* It's an external symbol. */
906e58ca
NC		 5633 while (hash->root.root.type == bfd_link_hash_indirect
5634 || hash->root.root.type == bfd_link_hash_warning)
5635 hash = ((struct elf32_arm_link_hash_entry *)
5636 hash->root.root.u.i.link);
5637
5638 if (hash->root.root.type == bfd_link_hash_defined
5639 || hash->root.root.type == bfd_link_hash_defweak)
5640 {
5641 sym_sec = hash->root.root.u.def.section;
5642 sym_value = hash->root.root.u.def.value;
022f8312
CL		 5643
5644 struct elf32_arm_link_hash_table *globals =
5645 elf32_arm_hash_table (info);
5646
5647 /* For a destination in a shared library,
5648 use the PLT stub as target address to
5649 decide whether a branch stub is
5650 needed. */
4dfe6ac6 5651 if (globals != NULL
362d30a1 5652 && globals->root.splt != NULL
4dfe6ac6 5653 && hash != NULL
022f8312
CL		 5654 && hash->root.plt.offset != (bfd_vma) -1)
5655 {
362d30a1 5656 sym_sec = globals->root.splt;
022f8312
CL		 5657 sym_value = hash->root.plt.offset;
5658 if (sym_sec->output_section != NULL)
5659 destination = (sym_value
5660 + sym_sec->output_offset
5661 + sym_sec->output_section->vma);
5662 }
5663 else if (sym_sec->output_section != NULL)
906e58ca
NC		 5664 destination = (sym_value + irela->r_addend
5665 + sym_sec->output_offset
5666 + sym_sec->output_section->vma);
5667 }
69c5861e
CL		 5668 else if ((hash->root.root.type == bfd_link_hash_undefined)
5669 || (hash->root.root.type == bfd_link_hash_undefweak))
5670 {
5671 /* For a shared library, use the PLT stub as
5672 target address to decide whether a long
5673 branch stub is needed.
5674 For absolute code, they cannot be handled. */
5675 struct elf32_arm_link_hash_table *globals =
5676 elf32_arm_hash_table (info);
5677
4dfe6ac6 5678 if (globals != NULL
362d30a1 5679 && globals->root.splt != NULL
4dfe6ac6 5680 && hash != NULL
69c5861e
CL		 5681 && hash->root.plt.offset != (bfd_vma) -1)
5682 {
362d30a1 5683 sym_sec = globals->root.splt;
69c5861e
CL		 5684 sym_value = hash->root.plt.offset;
5685 if (sym_sec->output_section != NULL)
5686 destination = (sym_value
5687 + sym_sec->output_offset
5688 + sym_sec->output_section->vma);
5689 }
5690 else
5691 continue;
5692 }
906e58ca
NC		 5693 else
5694 {
5695 bfd_set_error (bfd_error_bad_value);
5696 goto error_ret_free_internal;
5697 }
34e77a92 5698 st_type = hash->root.type;
39d911fc
TP		 5699 branch_type =
5700 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 5701 sym_name = hash->root.root.root.string;
906e58ca
NC		 5702 }
5703
48229727 5704 do
7413f23f 5705 {
b715f643
TP		 5706 bfd_boolean new_stub;
5707
48229727
JB		 5708 /* Determine what (if any) linker stub is needed. */
5709 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 5710 st_type, &branch_type,
5711 hash, destination, sym_sec,
48229727
JB		 5712 input_bfd, sym_name);
5713 if (stub_type == arm_stub_none)
5714 break;
5715
48229727
JB		 5716 /* We've either created a stub for this reloc already,
5717 or we are about to. */
b715f643
TP		 5718 created_stub =
5719 elf32_arm_create_stub (htab, stub_type, section, irela,
5720 sym_sec, hash,
5721 (char *) sym_name, sym_value,
5722 branch_type, &new_stub);
7413f23f 5723
b715f643
TP		 5724 if (!created_stub)
5725 goto error_ret_free_internal;
5726 else if (!new_stub)
5727 break;
99059e56 5728 else
b715f643 5729 stub_changed = TRUE;
99059e56
RM		 5730 }
5731 while (0);
5732
5733 /* Look for relocations which might trigger Cortex-A8
5734 erratum. */
5735 if (htab->fix_cortex_a8
5736 && (r_type == (unsigned int) R_ARM_THM_JUMP24
5737 || r_type == (unsigned int) R_ARM_THM_JUMP19
5738 || r_type == (unsigned int) R_ARM_THM_CALL
5739 || r_type == (unsigned int) R_ARM_THM_XPC22))
5740 {
5741 bfd_vma from = section->output_section->vma
5742 + section->output_offset
5743 + irela->r_offset;
5744
5745 if ((from & 0xfff) == 0xffe)
5746 {
5747 /* Found a candidate. Note we haven't checked the
5748 destination is within 4K here: if we do so (and
5749 don't create an entry in a8_relocs) we can't tell
5750 that a branch should have been relocated when
5751 scanning later. */
5752 if (num_a8_relocs == a8_reloc_table_size)
5753 {
5754 a8_reloc_table_size *= 2;
5755 a8_relocs = (struct a8_erratum_reloc *)
5756 bfd_realloc (a8_relocs,
5757 sizeof (struct a8_erratum_reloc)
5758 * a8_reloc_table_size);
5759 }
5760
5761 a8_relocs[num_a8_relocs].from = from;
5762 a8_relocs[num_a8_relocs].destination = destination;
5763 a8_relocs[num_a8_relocs].r_type = r_type;
5764 a8_relocs[num_a8_relocs].branch_type = branch_type;
5765 a8_relocs[num_a8_relocs].sym_name = sym_name;
5766 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
5767 a8_relocs[num_a8_relocs].hash = hash;
5768
5769 num_a8_relocs++;
5770 }
5771 }
906e58ca
NC		 5772 }
5773
99059e56
RM		 5774 /* We're done with the internal relocs, free them. */
5775 if (elf_section_data (section)->relocs == NULL)
5776 free (internal_relocs);
5777 }
48229727 5778
99059e56 5779 if (htab->fix_cortex_a8)
48229727 5780 {
99059e56
RM		 5781 /* Sort relocs which might apply to Cortex-A8 erratum. */
5782 qsort (a8_relocs, num_a8_relocs,
eb7c4339 5783 sizeof (struct a8_erratum_reloc),
99059e56 5784 &a8_reloc_compare);
48229727 5785
99059e56
RM		 5786 /* Scan for branches which might trigger Cortex-A8 erratum. */
5787 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 5788 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 5789 a8_relocs, num_a8_relocs,
5790 prev_num_a8_fixes, &stub_changed)
5791 != 0)
48229727 5792 goto error_ret_free_local;
5e681ec4 5793 }
7f991970
AM		 5794
5795 if (local_syms != NULL
5796 && symtab_hdr->contents != (unsigned char *) local_syms)
5797 {
5798 if (!info->keep_memory)
5799 free (local_syms);
5800 else
5801 symtab_hdr->contents = (unsigned char *) local_syms;
5802 }
5e681ec4
PB		 5803 }
5804
eb7c4339 5805 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 5806 stub_changed = TRUE;
48229727 5807
906e58ca
NC		 5808 if (!stub_changed)
5809 break;
5e681ec4 5810
906e58ca
NC		 5811 /* OK, we've added some stubs. Find out the new size of the
5812 stub sections. */
5813 for (stub_sec = htab->stub_bfd->sections;
5814 stub_sec != NULL;
5815 stub_sec = stub_sec->next)
3e6b1042
DJ		 5816 {
5817 /* Ignore non-stub sections. */
5818 if (!strstr (stub_sec->name, STUB_SUFFIX))
5819 continue;
5820
5821 stub_sec->size = 0;
5822 }
b34b2d70 5823
d7c5bd02 5824 /* Compute stub section size, considering padding. */
906e58ca 5825 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 5826 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
5827 stub_type++)
5828 {
5829 int size, padding;
5830 asection **stub_sec_p;
5831
5832 padding = arm_dedicated_stub_section_padding (stub_type);
5833 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
5834 /* Skip if no stub input section or no stub section padding
5835 required. */
5836 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
5837 continue;
5838 /* Stub section padding required but no dedicated section. */
5839 BFD_ASSERT (stub_sec_p);
5840
5841 size = (*stub_sec_p)->size;
5842 size = (size + padding - 1) & ~(padding - 1);
5843 (*stub_sec_p)->size = size;
5844 }
906e58ca 5845
48229727
JB		 5846 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5847 if (htab->fix_cortex_a8)
99059e56
RM		 5848 for (i = 0; i < num_a8_fixes; i++)
5849 {
48229727 5850 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 5851 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 5852
5853 if (stub_sec == NULL)
7f991970 5854 return FALSE;
48229727 5855
99059e56
RM		 5856 stub_sec->size
5857 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
5858 NULL);
5859 }
48229727
JB		 5860
5861
906e58ca
NC		 5862 /* Ask the linker to do its stuff. */
5863 (*htab->layout_sections_again) ();
ba93b8ac
DJ		 5864 }
5865
48229727
JB		 5866 /* Add stubs for Cortex-A8 erratum fixes now. */
5867 if (htab->fix_cortex_a8)
5868 {
5869 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 5870 {
5871 struct elf32_arm_stub_hash_entry *stub_entry;
5872 char *stub_name = a8_fixes[i].stub_name;
5873 asection *section = a8_fixes[i].section;
5874 unsigned int section_id = a8_fixes[i].section->id;
5875 asection *link_sec = htab->stub_group[section_id].link_sec;
5876 asection *stub_sec = htab->stub_group[section_id].stub_sec;
5877 const insn_sequence *template_sequence;
5878 int template_size, size = 0;
5879
5880 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
5881 TRUE, FALSE);
5882 if (stub_entry == NULL)
5883 {
5884 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
5885 section->owner,
5886 stub_name);
5887 return FALSE;
5888 }
5889
5890 stub_entry->stub_sec = stub_sec;
5891 stub_entry->stub_offset = 0;
5892 stub_entry->id_sec = link_sec;
5893 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 5894 stub_entry->source_value = a8_fixes[i].offset;
99059e56 5895 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 5896 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 5897 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 5898 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 5899
99059e56
RM		 5900 size = find_stub_size_and_template (a8_fixes[i].stub_type,
5901 &template_sequence,
5902 &template_size);
48229727 5903
99059e56
RM		 5904 stub_entry->stub_size = size;
5905 stub_entry->stub_template = template_sequence;
5906 stub_entry->stub_template_size = template_size;
5907 }
48229727
JB		 5908
5909 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 5910 elf32_arm_write_section(). */
48229727
JB		 5911 htab->a8_erratum_fixes = a8_fixes;
5912 htab->num_a8_erratum_fixes = num_a8_fixes;
5913 }
5914 else
5915 {
5916 htab->a8_erratum_fixes = NULL;
5917 htab->num_a8_erratum_fixes = 0;
5918 }
906e58ca 5919 return TRUE;
5e681ec4
PB		 5920}
5921
906e58ca
NC		 5922/* Build all the stubs associated with the current output file. The
5923 stubs are kept in a hash table attached to the main linker hash
5924 table. We also set up the .plt entries for statically linked PIC
5925 functions here. This function is called via arm_elf_finish in the
5926 linker. */
252b5132 5927
906e58ca
NC		 5928bfd_boolean
5929elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 5930{
906e58ca
NC		 5931 asection *stub_sec;
5932 struct bfd_hash_table *table;
5933 struct elf32_arm_link_hash_table *htab;
252b5132 5934
906e58ca 5935 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5936 if (htab == NULL)
5937 return FALSE;
252b5132 5938
906e58ca
NC		 5939 for (stub_sec = htab->stub_bfd->sections;
5940 stub_sec != NULL;
5941 stub_sec = stub_sec->next)
252b5132 5942 {
906e58ca
NC		 5943 bfd_size_type size;
5944
8029a119 5945 /* Ignore non-stub sections. */
906e58ca
NC		 5946 if (!strstr (stub_sec->name, STUB_SUFFIX))
5947 continue;
5948
d7c5bd02
TP		 5949 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
5950 must at least be done for stub section requiring padding. */
906e58ca 5951 size = stub_sec->size;
21d799b5 5952 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 5953 if (stub_sec->contents == NULL && size != 0)
5954 return FALSE;
5955 stub_sec->size = 0;
252b5132
RH		 5956 }
5957
906e58ca
NC		 5958 /* Build the stubs as directed by the stub hash table. */
5959 table = &htab->stub_hash_table;
5960 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 5961 if (htab->fix_cortex_a8)
5962 {
5963 /* Place the cortex a8 stubs last. */
5964 htab->fix_cortex_a8 = -1;
5965 bfd_hash_traverse (table, arm_build_one_stub, info);
5966 }
252b5132 5967
906e58ca 5968 return TRUE;
252b5132
RH		 5969}
5970
9b485d32
NC		 5971/* Locate the Thumb encoded calling stub for NAME. */
5972
252b5132 5973static struct elf_link_hash_entry *
57e8b36a
NC		 5974find_thumb_glue (struct bfd_link_info *link_info,
5975 const char *name,
f2a9dd69 5976 char **error_message)
252b5132
RH		 5977{
5978 char *tmp_name;
5979 struct elf_link_hash_entry *hash;
5980 struct elf32_arm_link_hash_table *hash_table;
5981
5982 /* We need a pointer to the armelf specific hash table. */
5983 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5984 if (hash_table == NULL)
5985 return NULL;
252b5132 5986
21d799b5 5987 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5988 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5989
5990 BFD_ASSERT (tmp_name);
5991
5992 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
5993
5994 hash = elf_link_hash_lookup
b34976b6 5995 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5996
b1657152
AM		 5997 if (hash == NULL
5998 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
5999 tmp_name, name) == -1)
6000 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6001
6002 free (tmp_name);
6003
6004 return hash;
6005}
6006
9b485d32
NC		 6007/* Locate the ARM encoded calling stub for NAME. */
6008
252b5132 6009static struct elf_link_hash_entry *
57e8b36a
NC		 6010find_arm_glue (struct bfd_link_info *link_info,
6011 const char *name,
f2a9dd69 6012 char **error_message)
252b5132
RH		 6013{
6014 char *tmp_name;
6015 struct elf_link_hash_entry *myh;
6016 struct elf32_arm_link_hash_table *hash_table;
6017
6018 /* We need a pointer to the elfarm specific hash table. */
6019 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6020 if (hash_table == NULL)
6021 return NULL;
252b5132 6022
21d799b5 6023 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6024 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6025
6026 BFD_ASSERT (tmp_name);
6027
6028 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6029
6030 myh = elf_link_hash_lookup
b34976b6 6031 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6032
b1657152
AM		 6033 if (myh == NULL
6034 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6035 tmp_name, name) == -1)
6036 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6037
6038 free (tmp_name);
6039
6040 return myh;
6041}
6042
8f6277f5 6043/* ARM->Thumb glue (static images):
252b5132
RH		 6044
6045 .arm
6046 __func_from_arm:
6047 ldr r12, __func_addr
6048 bx r12
6049 __func_addr:
906e58ca 6050 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6051
26079076
PB		 6052 (v5t static images)
6053 .arm
6054 __func_from_arm:
6055 ldr pc, __func_addr
6056 __func_addr:
906e58ca 6057 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6058
8f6277f5
PB		 6059 (relocatable images)
6060 .arm
6061 __func_from_arm:
6062 ldr r12, __func_offset
6063 add r12, r12, pc
6064 bx r12
6065 __func_offset:
8029a119 6066 .word func - . */
8f6277f5
PB		 6067
6068#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6069static const insn32 a2t1_ldr_insn = 0xe59fc000;
6070static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6071static const insn32 a2t3_func_addr_insn = 0x00000001;
6072
26079076
PB		 6073#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6074static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6075static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6076
8f6277f5
PB		 6077#define ARM2THUMB_PIC_GLUE_SIZE 16
6078static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6079static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6080static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6081
9b485d32 6082/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6083
8029a119
NC		 6084 .thumb .thumb
6085 .align 2 .align 2
6086 __func_from_thumb: __func_from_thumb:
6087 bx pc push {r6, lr}
6088 nop ldr r6, __func_addr
6089 .arm mov lr, pc
6090 b func bx r6
99059e56
RM		 6091 .arm
6092 ;; back_to_thumb
6093 ldmia r13! {r6, lr}
6094 bx lr
6095 __func_addr:
6096 .word func */
252b5132
RH		 6097
6098#define THUMB2ARM_GLUE_SIZE 8
6099static const insn16 t2a1_bx_pc_insn = 0x4778;
6100static const insn16 t2a2_noop_insn = 0x46c0;
6101static const insn32 t2a3_b_insn = 0xea000000;
6102
c7b8f16e 6103#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6104#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6105#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6106
845b51d6
PB		 6107#define ARM_BX_VENEER_SIZE 12
6108static const insn32 armbx1_tst_insn = 0xe3100001;
6109static const insn32 armbx2_moveq_insn = 0x01a0f000;
6110static const insn32 armbx3_bx_insn = 0xe12fff10;
6111
7e392df6 6112#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6113static void
6114arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6115{
6116 asection * s;
8029a119 6117 bfd_byte * contents;
252b5132 6118
8029a119 6119 if (size == 0)
3e6b1042
DJ		 6120 {
6121 /* Do not include empty glue sections in the output. */
6122 if (abfd != NULL)
6123 {
3d4d4302 6124 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6125 if (s != NULL)
6126 s->flags |= SEC_EXCLUDE;
6127 }
6128 return;
6129 }
252b5132 6130
8029a119 6131 BFD_ASSERT (abfd != NULL);
252b5132 6132
3d4d4302 6133 s = bfd_get_linker_section (abfd, name);
8029a119 6134 BFD_ASSERT (s != NULL);
252b5132 6135
21d799b5 6136 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6137
8029a119
NC		 6138 BFD_ASSERT (s->size == size);
6139 s->contents = contents;
6140}
906e58ca 6141
8029a119
NC		 6142bfd_boolean
6143bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6144{
6145 struct elf32_arm_link_hash_table * globals;
906e58ca 6146
8029a119
NC		 6147 globals = elf32_arm_hash_table (info);
6148 BFD_ASSERT (globals != NULL);
906e58ca 6149
8029a119
NC		 6150 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6151 globals->arm_glue_size,
6152 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6153
8029a119
NC		 6154 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6155 globals->thumb_glue_size,
6156 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6157
8029a119
NC		 6158 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6159 globals->vfp11_erratum_glue_size,
6160 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6161
a504d23a
LA		 6162 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6163 globals->stm32l4xx_erratum_glue_size,
6164 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6165
8029a119
NC		 6166 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6167 globals->bx_glue_size,
845b51d6
PB		 6168 ARM_BX_GLUE_SECTION_NAME);
6169
b34976b6 6170 return TRUE;
252b5132
RH		 6171}
6172
a4fd1a8e 6173/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6174 returns the symbol identifying the stub. */
6175
a4fd1a8e 6176static struct elf_link_hash_entry *
57e8b36a
NC		 6177record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6178 struct elf_link_hash_entry * h)
252b5132
RH		 6179{
6180 const char * name = h->root.root.string;
63b0f745 6181 asection * s;
252b5132
RH		 6182 char * tmp_name;
6183 struct elf_link_hash_entry * myh;
14a793b2 6184 struct bfd_link_hash_entry * bh;
252b5132 6185 struct elf32_arm_link_hash_table * globals;
dc810e39 6186 bfd_vma val;
2f475487 6187 bfd_size_type size;
252b5132
RH		 6188
6189 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6190 BFD_ASSERT (globals != NULL);
6191 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6192
3d4d4302 6193 s = bfd_get_linker_section
252b5132
RH		 6194 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6195
252b5132
RH		 6196 BFD_ASSERT (s != NULL);
6197
21d799b5 6198 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6199 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6200
6201 BFD_ASSERT (tmp_name);
6202
6203 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6204
6205 myh = elf_link_hash_lookup
b34976b6 6206 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6207
6208 if (myh != NULL)
6209 {
9b485d32 6210 /* We've already seen this guy. */
252b5132 6211 free (tmp_name);
a4fd1a8e 6212 return myh;
252b5132
RH		 6213 }
6214
57e8b36a
NC		 6215 /* The only trick here is using hash_table->arm_glue_size as the value.
6216 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6217 putting it. The +1 on the value marks that the stub has not been
6218 output yet - not that it is a Thumb function. */
14a793b2 6219 bh = NULL;
dc810e39
AM		 6220 val = globals->arm_glue_size + 1;
6221 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6222 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6223 NULL, TRUE, FALSE, &bh);
252b5132 6224
b7693d02
DJ		 6225 myh = (struct elf_link_hash_entry *) bh;
6226 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6227 myh->forced_local = 1;
6228
252b5132
RH		 6229 free (tmp_name);
6230
0e1862bb
L		 6231 if (bfd_link_pic (link_info)
6232 || globals->root.is_relocatable_executable
27e55c4d 6233 || globals->pic_veneer)
2f475487 6234 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6235 else if (globals->use_blx)
6236 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6237 else
2f475487
AM		 6238 size = ARM2THUMB_STATIC_GLUE_SIZE;
6239
6240 s->size += size;
6241 globals->arm_glue_size += size;
252b5132 6242
a4fd1a8e 6243 return myh;
252b5132
RH		 6244}
6245
845b51d6
PB		 6246/* Allocate space for ARMv4 BX veneers. */
6247
6248static void
6249record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6250{
6251 asection * s;
6252 struct elf32_arm_link_hash_table *globals;
6253 char *tmp_name;
6254 struct elf_link_hash_entry *myh;
6255 struct bfd_link_hash_entry *bh;
6256 bfd_vma val;
6257
6258 /* BX PC does not need a veneer. */
6259 if (reg == 15)
6260 return;
6261
6262 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 6263 BFD_ASSERT (globals != NULL);
6264 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6265
6266 /* Check if this veneer has already been allocated. */
6267 if (globals->bx_glue_offset[reg])
6268 return;
6269
3d4d4302 6270 s = bfd_get_linker_section
845b51d6
PB		 6271 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
6272
6273 BFD_ASSERT (s != NULL);
6274
6275 /* Add symbol for veneer. */
21d799b5
NC		 6276 tmp_name = (char *)
6277 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 6278
845b51d6 6279 BFD_ASSERT (tmp_name);
906e58ca 6280
845b51d6 6281 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 6282
845b51d6
PB		 6283 myh = elf_link_hash_lookup
6284 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6285
845b51d6 6286 BFD_ASSERT (myh == NULL);
906e58ca 6287
845b51d6
PB		 6288 bh = NULL;
6289 val = globals->bx_glue_size;
6290 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 6291 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6292 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 6293
6294 myh = (struct elf_link_hash_entry *) bh;
6295 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6296 myh->forced_local = 1;
6297
6298 s->size += ARM_BX_VENEER_SIZE;
6299 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
6300 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
6301}
6302
6303
c7b8f16e
JB		 6304/* Add an entry to the code/data map for section SEC. */
6305
6306static void
6307elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
6308{
6309 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
6310 unsigned int newidx;
906e58ca 6311
c7b8f16e
JB		 6312 if (sec_data->map == NULL)
6313 {
21d799b5 6314 sec_data->map = (elf32_arm_section_map *)
99059e56 6315 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 6316 sec_data->mapcount = 0;
6317 sec_data->mapsize = 1;
6318 }
906e58ca 6319
c7b8f16e 6320 newidx = sec_data->mapcount++;
906e58ca 6321
c7b8f16e
JB		 6322 if (sec_data->mapcount > sec_data->mapsize)
6323 {
6324 sec_data->mapsize *= 2;
21d799b5 6325 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 6326 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
6327 * sizeof (elf32_arm_section_map));
515ef31d
NC		 6328 }
6329
6330 if (sec_data->map)
6331 {
6332 sec_data->map[newidx].vma = vma;
6333 sec_data->map[newidx].type = type;
c7b8f16e 6334 }
c7b8f16e
JB		 6335}
6336
6337
6338/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6339 veneers are handled for now. */
6340
6341static bfd_vma
6342record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 6343 elf32_vfp11_erratum_list *branch,
6344 bfd *branch_bfd,
6345 asection *branch_sec,
6346 unsigned int offset)
c7b8f16e
JB		 6347{
6348 asection *s;
6349 struct elf32_arm_link_hash_table *hash_table;
6350 char *tmp_name;
6351 struct elf_link_hash_entry *myh;
6352 struct bfd_link_hash_entry *bh;
6353 bfd_vma val;
6354 struct _arm_elf_section_data *sec_data;
c7b8f16e 6355 elf32_vfp11_erratum_list *newerr;
906e58ca 6356
c7b8f16e 6357 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 6358 BFD_ASSERT (hash_table != NULL);
6359 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 6360
3d4d4302 6361 s = bfd_get_linker_section
c7b8f16e 6362 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 6363
c7b8f16e 6364 sec_data = elf32_arm_section_data (s);
906e58ca 6365
c7b8f16e 6366 BFD_ASSERT (s != NULL);
906e58ca 6367
21d799b5 6368 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 6369 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 6370
c7b8f16e 6371 BFD_ASSERT (tmp_name);
906e58ca 6372
c7b8f16e
JB		 6373 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
6374 hash_table->num_vfp11_fixes);
906e58ca 6375
c7b8f16e
JB		 6376 myh = elf_link_hash_lookup
6377 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6378
c7b8f16e 6379 BFD_ASSERT (myh == NULL);
906e58ca 6380
c7b8f16e
JB		 6381 bh = NULL;
6382 val = hash_table->vfp11_erratum_glue_size;
6383 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 6384 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6385 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 6386
6387 myh = (struct elf_link_hash_entry *) bh;
6388 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6389 myh->forced_local = 1;
6390
6391 /* Link veneer back to calling location. */
c7e2358a 6392 sec_data->erratumcount += 1;
21d799b5
NC		 6393 newerr = (elf32_vfp11_erratum_list *)
6394 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 6395
c7b8f16e
JB		 6396 newerr->type = VFP11_ERRATUM_ARM_VENEER;
6397 newerr->vma = -1;
6398 newerr->u.v.branch = branch;
6399 newerr->u.v.id = hash_table->num_vfp11_fixes;
6400 branch->u.b.veneer = newerr;
6401
6402 newerr->next = sec_data->erratumlist;
6403 sec_data->erratumlist = newerr;
6404
6405 /* A symbol for the return from the veneer. */
6406 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
6407 hash_table->num_vfp11_fixes);
6408
6409 myh = elf_link_hash_lookup
6410 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6411
c7b8f16e
JB		 6412 if (myh != NULL)
6413 abort ();
6414
6415 bh = NULL;
6416 val = offset + 4;
6417 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6418 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 6419
c7b8f16e
JB		 6420 myh = (struct elf_link_hash_entry *) bh;
6421 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6422 myh->forced_local = 1;
6423
6424 free (tmp_name);
906e58ca 6425
c7b8f16e
JB		 6426 /* Generate a mapping symbol for the veneer section, and explicitly add an
6427 entry for that symbol to the code/data map for the section. */
6428 if (hash_table->vfp11_erratum_glue_size == 0)
6429 {
6430 bh = NULL;
6431 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 6432 ever requires this erratum fix. */
c7b8f16e
JB		 6433 _bfd_generic_link_add_one_symbol (link_info,
6434 hash_table->bfd_of_glue_owner, "$a",
6435 BSF_LOCAL, s, 0, NULL,
99059e56 6436 TRUE, FALSE, &bh);
c7b8f16e
JB		 6437
6438 myh = (struct elf_link_hash_entry *) bh;
6439 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6440 myh->forced_local = 1;
906e58ca 6441
c7b8f16e 6442 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 6443 BFDs. We must make a note of this generated mapping symbol
6444 ourselves so that code byteswapping works properly in
6445 elf32_arm_write_section. */
c7b8f16e
JB		 6446 elf32_arm_section_map_add (s, 'a', 0);
6447 }
906e58ca 6448
c7b8f16e
JB		 6449 s->size += VFP11_ERRATUM_VENEER_SIZE;
6450 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
6451 hash_table->num_vfp11_fixes++;
906e58ca 6452
c7b8f16e
JB		 6453 /* The offset of the veneer. */
6454 return val;
6455}
6456
a504d23a
LA		 6457/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6458 veneers need to be handled because used only in Cortex-M. */
6459
6460static bfd_vma
6461record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
6462 elf32_stm32l4xx_erratum_list *branch,
6463 bfd *branch_bfd,
6464 asection *branch_sec,
6465 unsigned int offset,
6466 bfd_size_type veneer_size)
6467{
6468 asection *s;
6469 struct elf32_arm_link_hash_table *hash_table;
6470 char *tmp_name;
6471 struct elf_link_hash_entry *myh;
6472 struct bfd_link_hash_entry *bh;
6473 bfd_vma val;
6474 struct _arm_elf_section_data *sec_data;
6475 elf32_stm32l4xx_erratum_list *newerr;
6476
6477 hash_table = elf32_arm_hash_table (link_info);
6478 BFD_ASSERT (hash_table != NULL);
6479 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
6480
6481 s = bfd_get_linker_section
6482 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6483
6484 BFD_ASSERT (s != NULL);
6485
6486 sec_data = elf32_arm_section_data (s);
6487
6488 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
6489 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
6490
6491 BFD_ASSERT (tmp_name);
6492
6493 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
6494 hash_table->num_stm32l4xx_fixes);
6495
6496 myh = elf_link_hash_lookup
6497 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6498
6499 BFD_ASSERT (myh == NULL);
6500
6501 bh = NULL;
6502 val = hash_table->stm32l4xx_erratum_glue_size;
6503 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
6504 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6505 NULL, TRUE, FALSE, &bh);
6506
6507 myh = (struct elf_link_hash_entry *) bh;
6508 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6509 myh->forced_local = 1;
6510
6511 /* Link veneer back to calling location. */
6512 sec_data->stm32l4xx_erratumcount += 1;
6513 newerr = (elf32_stm32l4xx_erratum_list *)
6514 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
6515
6516 newerr->type = STM32L4XX_ERRATUM_VENEER;
6517 newerr->vma = -1;
6518 newerr->u.v.branch = branch;
6519 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
6520 branch->u.b.veneer = newerr;
6521
6522 newerr->next = sec_data->stm32l4xx_erratumlist;
6523 sec_data->stm32l4xx_erratumlist = newerr;
6524
6525 /* A symbol for the return from the veneer. */
6526 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
6527 hash_table->num_stm32l4xx_fixes);
6528
6529 myh = elf_link_hash_lookup
6530 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6531
6532 if (myh != NULL)
6533 abort ();
6534
6535 bh = NULL;
6536 val = offset + 4;
6537 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6538 branch_sec, val, NULL, TRUE, FALSE, &bh);
6539
6540 myh = (struct elf_link_hash_entry *) bh;
6541 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6542 myh->forced_local = 1;
6543
6544 free (tmp_name);
6545
6546 /* Generate a mapping symbol for the veneer section, and explicitly add an
6547 entry for that symbol to the code/data map for the section. */
6548 if (hash_table->stm32l4xx_erratum_glue_size == 0)
6549 {
6550 bh = NULL;
6551 /* Creates a THUMB symbol since there is no other choice. */
6552 _bfd_generic_link_add_one_symbol (link_info,
6553 hash_table->bfd_of_glue_owner, "$t",
6554 BSF_LOCAL, s, 0, NULL,
6555 TRUE, FALSE, &bh);
6556
6557 myh = (struct elf_link_hash_entry *) bh;
6558 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6559 myh->forced_local = 1;
6560
6561 /* The elf32_arm_init_maps function only cares about symbols from input
6562 BFDs. We must make a note of this generated mapping symbol
6563 ourselves so that code byteswapping works properly in
6564 elf32_arm_write_section. */
6565 elf32_arm_section_map_add (s, 't', 0);
6566 }
6567
6568 s->size += veneer_size;
6569 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
6570 hash_table->num_stm32l4xx_fixes++;
6571
6572 /* The offset of the veneer. */
6573 return val;
6574}
6575
8029a119 6576#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 6577 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6578 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 6579
6580/* Create a fake section for use by the ARM backend of the linker. */
6581
6582static bfd_boolean
6583arm_make_glue_section (bfd * abfd, const char * name)
6584{
6585 asection * sec;
6586
3d4d4302 6587 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 6588 if (sec != NULL)
6589 /* Already made. */
6590 return TRUE;
6591
3d4d4302 6592 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 6593
6594 if (sec == NULL
6595 || !bfd_set_section_alignment (abfd, sec, 2))
6596 return FALSE;
6597
6598 /* Set the gc mark to prevent the section from being removed by garbage
6599 collection, despite the fact that no relocs refer to this section. */
6600 sec->gc_mark = 1;
6601
6602 return TRUE;
6603}
6604
1db37fe6
YG		 6605/* Set size of .plt entries. This function is called from the
6606 linker scripts in ld/emultempl/{armelf}.em. */
6607
6608void
6609bfd_elf32_arm_use_long_plt (void)
6610{
6611 elf32_arm_use_long_plt_entry = TRUE;
6612}
6613
8afb0e02
NC		 6614/* Add the glue sections to ABFD. This function is called from the
6615 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 6616
b34976b6 6617bfd_boolean
57e8b36a
NC		 6618bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
6619 struct bfd_link_info *info)
252b5132 6620{
a504d23a
LA		 6621 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
6622 bfd_boolean dostm32l4xx = globals
6623 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
6624 bfd_boolean addglue;
6625
8afb0e02
NC		 6626 /* If we are only performing a partial
6627 link do not bother adding the glue. */
0e1862bb 6628 if (bfd_link_relocatable (info))
b34976b6 6629 return TRUE;
252b5132 6630
a504d23a 6631 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 6632 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
6633 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
6634 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 6635
6636 if (!dostm32l4xx)
6637 return addglue;
6638
6639 return addglue
6640 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 6641}
6642
daa4adae
TP		 6643/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
6644 ensures they are not marked for deletion by
6645 strip_excluded_output_sections () when veneers are going to be created
6646 later. Not doing so would trigger assert on empty section size in
6647 lang_size_sections_1 (). */
6648
6649void
6650bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
6651{
6652 enum elf32_arm_stub_type stub_type;
6653
6654 /* If we are only performing a partial
6655 link do not bother adding the glue. */
6656 if (bfd_link_relocatable (info))
6657 return;
6658
6659 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6660 {
6661 asection *out_sec;
6662 const char *out_sec_name;
6663
6664 if (!arm_dedicated_stub_output_section_required (stub_type))
6665 continue;
6666
6667 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
6668 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
6669 if (out_sec != NULL)
6670 out_sec->flags |= SEC_KEEP;
6671 }
6672}
6673
8afb0e02
NC		 6674/* Select a BFD to be used to hold the sections used by the glue code.
6675 This function is called from the linker scripts in ld/emultempl/
8029a119 6676 {armelf/pe}.em. */
8afb0e02 6677
b34976b6 6678bfd_boolean
57e8b36a 6679bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 6680{
6681 struct elf32_arm_link_hash_table *globals;
6682
6683 /* If we are only performing a partial link
6684 do not bother getting a bfd to hold the glue. */
0e1862bb 6685 if (bfd_link_relocatable (info))
b34976b6 6686 return TRUE;
8afb0e02 6687
b7693d02
DJ		 6688 /* Make sure we don't attach the glue sections to a dynamic object. */
6689 BFD_ASSERT (!(abfd->flags & DYNAMIC));
6690
8afb0e02 6691 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 6692 BFD_ASSERT (globals != NULL);
6693
6694 if (globals->bfd_of_glue_owner != NULL)
b34976b6 6695 return TRUE;
8afb0e02 6696
252b5132
RH		 6697 /* Save the bfd for later use. */
6698 globals->bfd_of_glue_owner = abfd;
cedb70c5 6699
b34976b6 6700 return TRUE;
252b5132
RH		 6701}
6702
906e58ca
NC		 6703static void
6704check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 6705{
2de70689
MGD		 6706 int cpu_arch;
6707
b38cadfb 6708 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 6709 Tag_CPU_arch);
6710
6711 if (globals->fix_arm1176)
6712 {
6713 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
6714 globals->use_blx = 1;
6715 }
6716 else
6717 {
6718 if (cpu_arch > TAG_CPU_ARCH_V4T)
6719 globals->use_blx = 1;
6720 }
39b41c9c
PB		 6721}
6722
b34976b6 6723bfd_boolean
57e8b36a 6724bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 6725 struct bfd_link_info *link_info)
252b5132
RH		 6726{
6727 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 6728 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 6729 Elf_Internal_Rela *irel, *irelend;
6730 bfd_byte *contents = NULL;
252b5132
RH		 6731
6732 asection *sec;
6733 struct elf32_arm_link_hash_table *globals;
6734
6735 /* If we are only performing a partial link do not bother
6736 to construct any glue. */
0e1862bb 6737 if (bfd_link_relocatable (link_info))
b34976b6 6738 return TRUE;
252b5132 6739
39ce1a6a
NC		 6740 /* Here we have a bfd that is to be included on the link. We have a
6741 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 6742 globals = elf32_arm_hash_table (link_info);
252b5132 6743 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 6744
6745 check_use_blx (globals);
252b5132 6746
d504ffc8 6747 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 6748 {
d003868e
AM		 6749 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
6750 abfd);
e489d0ae
PB		 6751 return FALSE;
6752 }
f21f3fe0 6753
39ce1a6a
NC		 6754 /* PR 5398: If we have not decided to include any loadable sections in
6755 the output then we will not have a glue owner bfd. This is OK, it
6756 just means that there is nothing else for us to do here. */
6757 if (globals->bfd_of_glue_owner == NULL)
6758 return TRUE;
6759
252b5132
RH		 6760 /* Rummage around all the relocs and map the glue vectors. */
6761 sec = abfd->sections;
6762
6763 if (sec == NULL)
b34976b6 6764 return TRUE;
252b5132
RH		 6765
6766 for (; sec != NULL; sec = sec->next)
6767 {
6768 if (sec->reloc_count == 0)
6769 continue;
6770
2f475487
AM		 6771 if ((sec->flags & SEC_EXCLUDE) != 0)
6772 continue;
6773
0ffa91dd 6774 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 6775
9b485d32 6776 /* Load the relocs. */
6cdc0ccc 6777 internal_relocs
906e58ca 6778 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 6779
6cdc0ccc
AM		 6780 if (internal_relocs == NULL)
6781 goto error_return;
252b5132 6782
6cdc0ccc
AM		 6783 irelend = internal_relocs + sec->reloc_count;
6784 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 6785 {
6786 long r_type;
6787 unsigned long r_index;
252b5132
RH		 6788
6789 struct elf_link_hash_entry *h;
6790
6791 r_type = ELF32_R_TYPE (irel->r_info);
6792 r_index = ELF32_R_SYM (irel->r_info);
6793
9b485d32 6794 /* These are the only relocation types we care about. */
ba96a88f 6795 if ( r_type != R_ARM_PC24
845b51d6 6796 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 6797 continue;
6798
6799 /* Get the section contents if we haven't done so already. */
6800 if (contents == NULL)
6801 {
6802 /* Get cached copy if it exists. */
6803 if (elf_section_data (sec)->this_hdr.contents != NULL)
6804 contents = elf_section_data (sec)->this_hdr.contents;
6805 else
6806 {
6807 /* Go get them off disk. */
57e8b36a 6808 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 6809 goto error_return;
6810 }
6811 }
6812
845b51d6
PB		 6813 if (r_type == R_ARM_V4BX)
6814 {
6815 int reg;
6816
6817 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
6818 record_arm_bx_glue (link_info, reg);
6819 continue;
6820 }
6821
a7c10850 6822 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 6823 h = NULL;
6824
9b485d32 6825 /* We don't care about local symbols. */
252b5132
RH		 6826 if (r_index < symtab_hdr->sh_info)
6827 continue;
6828
9b485d32 6829 /* This is an external symbol. */
252b5132
RH		 6830 r_index -= symtab_hdr->sh_info;
6831 h = (struct elf_link_hash_entry *)
6832 elf_sym_hashes (abfd)[r_index];
6833
6834 /* If the relocation is against a static symbol it must be within
6835 the current section and so cannot be a cross ARM/Thumb relocation. */
6836 if (h == NULL)
6837 continue;
6838
d504ffc8
DJ		 6839 /* If the call will go through a PLT entry then we do not need
6840 glue. */
362d30a1 6841 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 6842 continue;
6843
252b5132
RH		 6844 switch (r_type)
6845 {
6846 case R_ARM_PC24:
6847 /* This one is a call from arm code. We need to look up
99059e56
RM		 6848 the target of the call. If it is a thumb target, we
6849 insert glue. */
39d911fc
TP		 6850 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
6851 == ST_BRANCH_TO_THUMB)
252b5132
RH		 6852 record_arm_to_thumb_glue (link_info, h);
6853 break;
6854
252b5132 6855 default:
c6596c5e 6856 abort ();
252b5132
RH		 6857 }
6858 }
6cdc0ccc
AM		 6859
6860 if (contents != NULL
6861 && elf_section_data (sec)->this_hdr.contents != contents)
6862 free (contents);
6863 contents = NULL;
6864
6865 if (internal_relocs != NULL
6866 && elf_section_data (sec)->relocs != internal_relocs)
6867 free (internal_relocs);
6868 internal_relocs = NULL;
252b5132
RH		 6869 }
6870
b34976b6 6871 return TRUE;
9a5aca8c 6872
252b5132 6873error_return:
6cdc0ccc
AM		 6874 if (contents != NULL
6875 && elf_section_data (sec)->this_hdr.contents != contents)
6876 free (contents);
6877 if (internal_relocs != NULL
6878 && elf_section_data (sec)->relocs != internal_relocs)
6879 free (internal_relocs);
9a5aca8c 6880
b34976b6 6881 return FALSE;
252b5132 6882}
7e392df6 6883#endif
252b5132 6884
eb043451 6885
c7b8f16e
JB		 6886/* Initialise maps of ARM/Thumb/data for input BFDs. */
6887
6888void
6889bfd_elf32_arm_init_maps (bfd *abfd)
6890{
6891 Elf_Internal_Sym *isymbuf;
6892 Elf_Internal_Shdr *hdr;
6893 unsigned int i, localsyms;
6894
af1f4419
NC		 6895 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6896 if (! is_arm_elf (abfd))
6897 return;
6898
c7b8f16e
JB		 6899 if ((abfd->flags & DYNAMIC) != 0)
6900 return;
6901
0ffa91dd 6902 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 6903 localsyms = hdr->sh_info;
6904
6905 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6906 should contain the number of local symbols, which should come before any
6907 global symbols. Mapping symbols are always local. */
6908 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
6909 NULL);
6910
6911 /* No internal symbols read? Skip this BFD. */
6912 if (isymbuf == NULL)
6913 return;
6914
6915 for (i = 0; i < localsyms; i++)
6916 {
6917 Elf_Internal_Sym *isym = &isymbuf[i];
6918 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
6919 const char *name;
906e58ca 6920
c7b8f16e 6921 if (sec != NULL
99059e56
RM		 6922 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
6923 {
6924 name = bfd_elf_string_from_elf_section (abfd,
6925 hdr->sh_link, isym->st_name);
906e58ca 6926
99059e56 6927 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 6928 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 6929 elf32_arm_section_map_add (sec, name[1], isym->st_value);
6930 }
c7b8f16e
JB		 6931 }
6932}
6933
6934
48229727
JB		 6935/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6936 say what they wanted. */
6937
6938void
6939bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
6940{
6941 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6942 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6943
4dfe6ac6
NC		 6944 if (globals == NULL)
6945 return;
6946
48229727
JB		 6947 if (globals->fix_cortex_a8 == -1)
6948 {
6949 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6950 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
6951 && (out_attr[Tag_CPU_arch_profile].i == 'A'
6952 || out_attr[Tag_CPU_arch_profile].i == 0))
6953 globals->fix_cortex_a8 = 1;
6954 else
6955 globals->fix_cortex_a8 = 0;
6956 }
6957}
6958
6959
c7b8f16e
JB		 6960void
6961bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
6962{
6963 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 6964 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 6965
4dfe6ac6
NC		 6966 if (globals == NULL)
6967 return;
c7b8f16e
JB		 6968 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6969 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
6970 {
6971 switch (globals->vfp11_fix)
99059e56
RM		 6972 {
6973 case BFD_ARM_VFP11_FIX_DEFAULT:
6974 case BFD_ARM_VFP11_FIX_NONE:
6975 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6976 break;
6977
6978 default:
6979 /* Give a warning, but do as the user requests anyway. */
6980 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
6981 "workaround is not necessary for target architecture"), obfd);
6982 }
c7b8f16e
JB		 6983 }
6984 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
6985 /* For earlier architectures, we might need the workaround, but do not
6986 enable it by default. If users is running with broken hardware, they
6987 must enable the erratum fix explicitly. */
6988 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6989}
6990
a504d23a
LA		 6991void
6992bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
6993{
6994 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6995 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6996
6997 if (globals == NULL)
6998 return;
6999
7000 /* We assume only Cortex-M4 may require the fix. */
7001 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7002 || out_attr[Tag_CPU_arch_profile].i != 'M')
7003 {
7004 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7005 /* Give a warning, but do as the user requests anyway. */
7006 (*_bfd_error_handler)
7007 (_("%B: warning: selected STM32L4XX erratum "
7008 "workaround is not necessary for target architecture"), obfd);
7009 }
7010}
c7b8f16e 7011
906e58ca
NC		 7012enum bfd_arm_vfp11_pipe
7013{
c7b8f16e
JB		 7014 VFP11_FMAC,
7015 VFP11_LS,
7016 VFP11_DS,
7017 VFP11_BAD
7018};
7019
7020/* Return a VFP register number. This is encoded as RX:X for single-precision
7021 registers, or X:RX for double-precision registers, where RX is the group of
7022 four bits in the instruction encoding and X is the single extension bit.
7023 RX and X fields are specified using their lowest (starting) bit. The return
7024 value is:
7025
7026 0...31: single-precision registers s0...s31
7027 32...63: double-precision registers d0...d31.
906e58ca 7028
c7b8f16e
JB		 7029 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7030 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7031
c7b8f16e
JB		 7032static unsigned int
7033bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7034 unsigned int x)
c7b8f16e
JB		 7035{
7036 if (is_double)
7037 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7038 else
7039 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7040}
7041
7042/* Set bits in *WMASK according to a register number REG as encoded by
7043 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7044
7045static void
7046bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7047{
7048 if (reg < 32)
7049 *wmask |= 1 << reg;
7050 else if (reg < 48)
7051 *wmask |= 3 << ((reg - 32) * 2);
7052}
7053
7054/* Return TRUE if WMASK overwrites anything in REGS. */
7055
7056static bfd_boolean
7057bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7058{
7059 int i;
906e58ca 7060
c7b8f16e
JB		 7061 for (i = 0; i < numregs; i++)
7062 {
7063 unsigned int reg = regs[i];
7064
7065 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7066 return TRUE;
906e58ca 7067
c7b8f16e
JB		 7068 reg -= 32;
7069
7070 if (reg >= 16)
99059e56 7071 continue;
906e58ca 7072
c7b8f16e 7073 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7074 return TRUE;
c7b8f16e 7075 }
906e58ca 7076
c7b8f16e
JB		 7077 return FALSE;
7078}
7079
7080/* In this function, we're interested in two things: finding input registers
7081 for VFP data-processing instructions, and finding the set of registers which
7082 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7083 hold the written set, so FLDM etc. are easy to deal with (we're only
7084 interested in 32 SP registers or 16 dp registers, due to the VFP version
7085 implemented by the chip in question). DP registers are marked by setting
7086 both SP registers in the write mask). */
7087
7088static enum bfd_arm_vfp11_pipe
7089bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7090 int *numregs)
c7b8f16e 7091{
91d6fa6a 7092 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7093 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7094
7095 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7096 {
7097 unsigned int pqrs;
7098 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7099 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7100
7101 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7102 | ((insn & 0x00300000) >> 19)
7103 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7104
7105 switch (pqrs)
99059e56
RM		 7106 {
7107 case 0: /* fmac[sd]. */
7108 case 1: /* fnmac[sd]. */
7109 case 2: /* fmsc[sd]. */
7110 case 3: /* fnmsc[sd]. */
7111 vpipe = VFP11_FMAC;
7112 bfd_arm_vfp11_write_mask (destmask, fd);
7113 regs[0] = fd;
7114 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7115 regs[2] = fm;
7116 *numregs = 3;
7117 break;
7118
7119 case 4: /* fmul[sd]. */
7120 case 5: /* fnmul[sd]. */
7121 case 6: /* fadd[sd]. */
7122 case 7: /* fsub[sd]. */
7123 vpipe = VFP11_FMAC;
7124 goto vfp_binop;
7125
7126 case 8: /* fdiv[sd]. */
7127 vpipe = VFP11_DS;
7128 vfp_binop:
7129 bfd_arm_vfp11_write_mask (destmask, fd);
7130 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7131 regs[1] = fm;
7132 *numregs = 2;
7133 break;
7134
7135 case 15: /* extended opcode. */
7136 {
7137 unsigned int extn = ((insn >> 15) & 0x1e)
7138 | ((insn >> 7) & 1);
7139
7140 switch (extn)
7141 {
7142 case 0: /* fcpy[sd]. */
7143 case 1: /* fabs[sd]. */
7144 case 2: /* fneg[sd]. */
7145 case 8: /* fcmp[sd]. */
7146 case 9: /* fcmpe[sd]. */
7147 case 10: /* fcmpz[sd]. */
7148 case 11: /* fcmpez[sd]. */
7149 case 16: /* fuito[sd]. */
7150 case 17: /* fsito[sd]. */
7151 case 24: /* ftoui[sd]. */
7152 case 25: /* ftouiz[sd]. */
7153 case 26: /* ftosi[sd]. */
7154 case 27: /* ftosiz[sd]. */
7155 /* These instructions will not bounce due to underflow. */
7156 *numregs = 0;
7157 vpipe = VFP11_FMAC;
7158 break;
7159
7160 case 3: /* fsqrt[sd]. */
7161 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7162 registers to cause the erratum in previous instructions. */
7163 bfd_arm_vfp11_write_mask (destmask, fd);
7164 vpipe = VFP11_DS;
7165 break;
7166
7167 case 15: /* fcvt{ds,sd}. */
7168 {
7169 int rnum = 0;
7170
7171 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7172
7173 /* Only FCVTSD can underflow. */
99059e56
RM		 7174 if ((insn & 0x100) != 0)
7175 regs[rnum++] = fm;
c7b8f16e 7176
99059e56 7177 *numregs = rnum;
c7b8f16e 7178
99059e56
RM		 7179 vpipe = VFP11_FMAC;
7180 }
7181 break;
c7b8f16e 7182
99059e56
RM		 7183 default:
7184 return VFP11_BAD;
7185 }
7186 }
7187 break;
c7b8f16e 7188
99059e56
RM		 7189 default:
7190 return VFP11_BAD;
7191 }
c7b8f16e
JB		 7192 }
7193 /* Two-register transfer. */
7194 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7195 {
7196 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7197
c7b8f16e
JB		 7198 if ((insn & 0x100000) == 0)
7199 {
99059e56
RM		 7200 if (is_double)
7201 bfd_arm_vfp11_write_mask (destmask, fm);
7202 else
7203 {
7204 bfd_arm_vfp11_write_mask (destmask, fm);
7205 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7206 }
c7b8f16e
JB		 7207 }
7208
91d6fa6a 7209 vpipe = VFP11_LS;
c7b8f16e
JB		 7210 }
7211 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7212 {
7213 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7214 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7215
c7b8f16e 7216 switch (puw)
99059e56
RM		 7217 {
7218 case 0: /* Two-reg transfer. We should catch these above. */
7219 abort ();
906e58ca 7220
99059e56
RM		 7221 case 2: /* fldm[sdx]. */
7222 case 3:
7223 case 5:
7224 {
7225 unsigned int i, offset = insn & 0xff;
c7b8f16e 7226
99059e56
RM		 7227 if (is_double)
7228 offset >>= 1;
c7b8f16e 7229
99059e56
RM		 7230 for (i = fd; i < fd + offset; i++)
7231 bfd_arm_vfp11_write_mask (destmask, i);
7232 }
7233 break;
906e58ca 7234
99059e56
RM		 7235 case 4: /* fld[sd]. */
7236 case 6:
7237 bfd_arm_vfp11_write_mask (destmask, fd);
7238 break;
906e58ca 7239
99059e56
RM		 7240 default:
7241 return VFP11_BAD;
7242 }
c7b8f16e 7243
91d6fa6a 7244 vpipe = VFP11_LS;
c7b8f16e
JB		 7245 }
7246 /* Single-register transfer. Note L==0. */
7247 else if ((insn & 0x0f100e10) == 0x0e000a10)
7248 {
7249 unsigned int opcode = (insn >> 21) & 7;
7250 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
7251
7252 switch (opcode)
99059e56
RM		 7253 {
7254 case 0: /* fmsr/fmdlr. */
7255 case 1: /* fmdhr. */
7256 /* Mark fmdhr and fmdlr as writing to the whole of the DP
7257 destination register. I don't know if this is exactly right,
7258 but it is the conservative choice. */
7259 bfd_arm_vfp11_write_mask (destmask, fn);
7260 break;
7261
7262 case 7: /* fmxr. */
7263 break;
7264 }
c7b8f16e 7265
91d6fa6a 7266 vpipe = VFP11_LS;
c7b8f16e
JB		 7267 }
7268
91d6fa6a 7269 return vpipe;
c7b8f16e
JB		 7270}
7271
7272
7273static int elf32_arm_compare_mapping (const void * a, const void * b);
7274
7275
7276/* Look for potentially-troublesome code sequences which might trigger the
7277 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
7278 (available from ARM) for details of the erratum. A short version is
7279 described in ld.texinfo. */
7280
7281bfd_boolean
7282bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
7283{
7284 asection *sec;
7285 bfd_byte *contents = NULL;
7286 int state = 0;
7287 int regs[3], numregs = 0;
7288 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7289 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 7290
4dfe6ac6
NC		 7291 if (globals == NULL)
7292 return FALSE;
7293
c7b8f16e
JB		 7294 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
7295 The states transition as follows:
906e58ca 7296
c7b8f16e 7297 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 7298 A VFP FMAC-pipeline instruction has been seen. Fill
7299 regs[0]..regs[numregs-1] with its input operands. Remember this
7300 instruction in 'first_fmac'.
c7b8f16e
JB		 7301
7302 1 -> 2
99059e56
RM		 7303 Any instruction, except for a VFP instruction which overwrites
7304 regs[*].
906e58ca 7305
c7b8f16e
JB		 7306 1 -> 3 [ -> 0 ] or
7307 2 -> 3 [ -> 0 ]
99059e56
RM		 7308 A VFP instruction has been seen which overwrites any of regs[*].
7309 We must make a veneer! Reset state to 0 before examining next
7310 instruction.
906e58ca 7311
c7b8f16e 7312 2 -> 0
99059e56
RM		 7313 If we fail to match anything in state 2, reset to state 0 and reset
7314 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 7315
7316 If the VFP11 vector mode is in use, there must be at least two unrelated
7317 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 7318 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 7319
7320 /* If we are only performing a partial link do not bother
7321 to construct any glue. */
0e1862bb 7322 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 7323 return TRUE;
7324
0ffa91dd
NC		 7325 /* Skip if this bfd does not correspond to an ELF image. */
7326 if (! is_arm_elf (abfd))
7327 return TRUE;
906e58ca 7328
c7b8f16e
JB		 7329 /* We should have chosen a fix type by the time we get here. */
7330 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
7331
7332 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
7333 return TRUE;
2e6030b9 7334
33a7ffc2
JM		 7335 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7336 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7337 return TRUE;
7338
c7b8f16e
JB		 7339 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7340 {
7341 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
7342 struct _arm_elf_section_data *sec_data;
7343
7344 /* If we don't have executable progbits, we're not interested in this
99059e56 7345 section. Also skip if section is to be excluded. */
c7b8f16e 7346 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 7347 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7348 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 7349 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 7350 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 7351 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
7352 continue;
c7b8f16e
JB		 7353
7354 sec_data = elf32_arm_section_data (sec);
906e58ca 7355
c7b8f16e 7356 if (sec_data->mapcount == 0)
99059e56 7357 continue;
906e58ca 7358
c7b8f16e
JB		 7359 if (elf_section_data (sec)->this_hdr.contents != NULL)
7360 contents = elf_section_data (sec)->this_hdr.contents;
7361 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7362 goto error_return;
7363
7364 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7365 elf32_arm_compare_mapping);
7366
7367 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 7368 {
7369 unsigned int span_start = sec_data->map[span].vma;
7370 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 7371 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 7372 char span_type = sec_data->map[span].type;
7373
7374 /* FIXME: Only ARM mode is supported at present. We may need to
7375 support Thumb-2 mode also at some point. */
7376 if (span_type != 'a')
7377 continue;
7378
7379 for (i = span_start; i < span_end;)
7380 {
7381 unsigned int next_i = i + 4;
7382 unsigned int insn = bfd_big_endian (abfd)
7383 ? (contents[i] << 24)
7384 | (contents[i + 1] << 16)
7385 | (contents[i + 2] << 8)
7386 | contents[i + 3]
7387 : (contents[i + 3] << 24)
7388 | (contents[i + 2] << 16)
7389 | (contents[i + 1] << 8)
7390 | contents[i];
7391 unsigned int writemask = 0;
7392 enum bfd_arm_vfp11_pipe vpipe;
7393
7394 switch (state)
7395 {
7396 case 0:
7397 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
7398 &numregs);
7399 /* I'm assuming the VFP11 erratum can trigger with denorm
7400 operands on either the FMAC or the DS pipeline. This might
7401 lead to slightly overenthusiastic veneer insertion. */
7402 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
7403 {
7404 state = use_vector ? 1 : 2;
7405 first_fmac = i;
7406 veneer_of_insn = insn;
7407 }
7408 break;
7409
7410 case 1:
7411 {
7412 int other_regs[3], other_numregs;
7413 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7414 other_regs,
99059e56
RM		 7415 &other_numregs);
7416 if (vpipe != VFP11_BAD
7417 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7418 numregs))
99059e56
RM		 7419 state = 3;
7420 else
7421 state = 2;
7422 }
7423 break;
7424
7425 case 2:
7426 {
7427 int other_regs[3], other_numregs;
7428 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7429 other_regs,
99059e56
RM		 7430 &other_numregs);
7431 if (vpipe != VFP11_BAD
7432 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7433 numregs))
99059e56
RM		 7434 state = 3;
7435 else
7436 {
7437 state = 0;
7438 next_i = first_fmac + 4;
7439 }
7440 }
7441 break;
7442
7443 case 3:
7444 abort (); /* Should be unreachable. */
7445 }
7446
7447 if (state == 3)
7448 {
7449 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
7450 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7451
7452 elf32_arm_section_data (sec)->erratumcount += 1;
7453
7454 newerr->u.b.vfp_insn = veneer_of_insn;
7455
7456 switch (span_type)
7457 {
7458 case 'a':
7459 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
7460 break;
7461
7462 default:
7463 abort ();
7464 }
7465
7466 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 7467 first_fmac);
7468
99059e56 7469 newerr->vma = -1;
c7b8f16e 7470
99059e56
RM		 7471 newerr->next = sec_data->erratumlist;
7472 sec_data->erratumlist = newerr;
c7b8f16e 7473
99059e56
RM		 7474 state = 0;
7475 }
c7b8f16e 7476
99059e56
RM		 7477 i = next_i;
7478 }
7479 }
906e58ca 7480
c7b8f16e 7481 if (contents != NULL
99059e56
RM		 7482 && elf_section_data (sec)->this_hdr.contents != contents)
7483 free (contents);
c7b8f16e
JB		 7484 contents = NULL;
7485 }
7486
7487 return TRUE;
7488
7489error_return:
7490 if (contents != NULL
7491 && elf_section_data (sec)->this_hdr.contents != contents)
7492 free (contents);
906e58ca 7493
c7b8f16e
JB		 7494 return FALSE;
7495}
7496
7497/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7498 after sections have been laid out, using specially-named symbols. */
7499
7500void
7501bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
7502 struct bfd_link_info *link_info)
7503{
7504 asection *sec;
7505 struct elf32_arm_link_hash_table *globals;
7506 char *tmp_name;
906e58ca 7507
0e1862bb 7508 if (bfd_link_relocatable (link_info))
c7b8f16e 7509 return;
2e6030b9
MS		 7510
7511 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 7512 if (! is_arm_elf (abfd))
2e6030b9
MS		 7513 return;
7514
c7b8f16e 7515 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7516 if (globals == NULL)
7517 return;
906e58ca 7518
21d799b5 7519 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7520 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 7521
7522 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7523 {
7524 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7525 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 7526
c7b8f16e 7527 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 7528 {
7529 struct elf_link_hash_entry *myh;
7530 bfd_vma vma;
7531
7532 switch (errnode->type)
7533 {
7534 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
7535 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
7536 /* Find veneer symbol. */
7537 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 7538 errnode->u.b.veneer->u.v.id);
7539
99059e56
RM		 7540 myh = elf_link_hash_lookup
7541 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 7542
a504d23a
LA		 7543 if (myh == NULL)
7544 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7545 "`%s'"), abfd, tmp_name);
7546
7547 vma = myh->root.u.def.section->output_section->vma
7548 + myh->root.u.def.section->output_offset
7549 + myh->root.u.def.value;
7550
7551 errnode->u.b.veneer->vma = vma;
7552 break;
7553
7554 case VFP11_ERRATUM_ARM_VENEER:
7555 case VFP11_ERRATUM_THUMB_VENEER:
7556 /* Find return location. */
7557 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7558 errnode->u.v.id);
7559
7560 myh = elf_link_hash_lookup
7561 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7562
7563 if (myh == NULL)
7564 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7565 "`%s'"), abfd, tmp_name);
7566
7567 vma = myh->root.u.def.section->output_section->vma
7568 + myh->root.u.def.section->output_offset
7569 + myh->root.u.def.value;
7570
7571 errnode->u.v.branch->vma = vma;
7572 break;
7573
7574 default:
7575 abort ();
7576 }
7577 }
7578 }
7579
7580 free (tmp_name);
7581}
7582
7583/* Find virtual-memory addresses for STM32L4XX erratum veneers and
7584 return locations after sections have been laid out, using
7585 specially-named symbols. */
7586
7587void
7588bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
7589 struct bfd_link_info *link_info)
7590{
7591 asection *sec;
7592 struct elf32_arm_link_hash_table *globals;
7593 char *tmp_name;
7594
7595 if (bfd_link_relocatable (link_info))
7596 return;
7597
7598 /* Skip if this bfd does not correspond to an ELF image. */
7599 if (! is_arm_elf (abfd))
7600 return;
7601
7602 globals = elf32_arm_hash_table (link_info);
7603 if (globals == NULL)
7604 return;
7605
7606 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7607 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7608
7609 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7610 {
7611 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7612 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
7613
7614 for (; errnode != NULL; errnode = errnode->next)
7615 {
7616 struct elf_link_hash_entry *myh;
7617 bfd_vma vma;
7618
7619 switch (errnode->type)
7620 {
7621 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
7622 /* Find veneer symbol. */
7623 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7624 errnode->u.b.veneer->u.v.id);
7625
7626 myh = elf_link_hash_lookup
7627 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7628
7629 if (myh == NULL)
7630 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7631 "`%s'"), abfd, tmp_name);
7632
7633 vma = myh->root.u.def.section->output_section->vma
7634 + myh->root.u.def.section->output_offset
7635 + myh->root.u.def.value;
7636
7637 errnode->u.b.veneer->vma = vma;
7638 break;
7639
7640 case STM32L4XX_ERRATUM_VENEER:
7641 /* Find return location. */
7642 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7643 errnode->u.v.id);
7644
7645 myh = elf_link_hash_lookup
7646 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7647
7648 if (myh == NULL)
7649 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7650 "`%s'"), abfd, tmp_name);
7651
7652 vma = myh->root.u.def.section->output_section->vma
7653 + myh->root.u.def.section->output_offset
7654 + myh->root.u.def.value;
7655
7656 errnode->u.v.branch->vma = vma;
7657 break;
7658
7659 default:
7660 abort ();
7661 }
7662 }
7663 }
7664
7665 free (tmp_name);
7666}
7667
7668static inline bfd_boolean
7669is_thumb2_ldmia (const insn32 insn)
7670{
7671 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
7672 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
7673 return (insn & 0xffd02000) == 0xe8900000;
7674}
7675
7676static inline bfd_boolean
7677is_thumb2_ldmdb (const insn32 insn)
7678{
7679 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
7680 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
7681 return (insn & 0xffd02000) == 0xe9100000;
7682}
7683
7684static inline bfd_boolean
7685is_thumb2_vldm (const insn32 insn)
7686{
7687 /* A6.5 Extension register load or store instruction
7688 A7.7.229
9239bbd3
CM		 7689 We look for SP 32-bit and DP 64-bit registers.
7690 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
7691 <list> is consecutive 64-bit registers
7692 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 7693 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
7694 <list> is consecutive 32-bit registers
7695 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
7696 if P==0 && U==1 && W==1 && Rn=1101 VPOP
7697 if PUW=010 || PUW=011 || PUW=101 VLDM. */
7698 return
9239bbd3
CM		 7699 (((insn & 0xfe100f00) == 0xec100b00) ||
7700 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 7701 && /* (IA without !). */
7702 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 7703 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 7704 || ((((insn << 7) >> 28) & 0xd) == 0x5)
7705 /* (DB with !). */
7706 || ((((insn << 7) >> 28) & 0xd) == 0x9));
7707}
7708
7709/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
7710 VLDM opcode and:
7711 - computes the number and the mode of memory accesses
7712 - decides if the replacement should be done:
7713 . replaces only if > 8-word accesses
7714 . or (testing purposes only) replaces all accesses. */
7715
7716static bfd_boolean
7717stm32l4xx_need_create_replacing_stub (const insn32 insn,
7718 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
7719{
9239bbd3 7720 int nb_words = 0;
a504d23a
LA		 7721
7722 /* The field encoding the register list is the same for both LDMIA
7723 and LDMDB encodings. */
7724 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 7725 nb_words = popcount (insn & 0x0000ffff);
a504d23a 7726 else if (is_thumb2_vldm (insn))
9239bbd3 7727 nb_words = (insn & 0xff);
a504d23a
LA		 7728
7729 /* DEFAULT mode accounts for the real bug condition situation,
7730 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
7731 return
9239bbd3 7732 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 7733 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
7734}
7735
7736/* Look for potentially-troublesome code sequences which might trigger
7737 the STM STM32L4XX erratum. */
7738
7739bfd_boolean
7740bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
7741 struct bfd_link_info *link_info)
7742{
7743 asection *sec;
7744 bfd_byte *contents = NULL;
7745 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7746
7747 if (globals == NULL)
7748 return FALSE;
7749
7750 /* If we are only performing a partial link do not bother
7751 to construct any glue. */
7752 if (bfd_link_relocatable (link_info))
7753 return TRUE;
7754
7755 /* Skip if this bfd does not correspond to an ELF image. */
7756 if (! is_arm_elf (abfd))
7757 return TRUE;
7758
7759 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
7760 return TRUE;
7761
7762 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7763 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7764 return TRUE;
7765
7766 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7767 {
7768 unsigned int i, span;
7769 struct _arm_elf_section_data *sec_data;
7770
7771 /* If we don't have executable progbits, we're not interested in this
7772 section. Also skip if section is to be excluded. */
7773 if (elf_section_type (sec) != SHT_PROGBITS
7774 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7775 || (sec->flags & SEC_EXCLUDE) != 0
7776 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
7777 || sec->output_section == bfd_abs_section_ptr
7778 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
7779 continue;
7780
7781 sec_data = elf32_arm_section_data (sec);
c7b8f16e 7782
a504d23a
LA		 7783 if (sec_data->mapcount == 0)
7784 continue;
c7b8f16e 7785
a504d23a
LA		 7786 if (elf_section_data (sec)->this_hdr.contents != NULL)
7787 contents = elf_section_data (sec)->this_hdr.contents;
7788 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7789 goto error_return;
c7b8f16e 7790
a504d23a
LA		 7791 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7792 elf32_arm_compare_mapping);
c7b8f16e 7793
a504d23a
LA		 7794 for (span = 0; span < sec_data->mapcount; span++)
7795 {
7796 unsigned int span_start = sec_data->map[span].vma;
7797 unsigned int span_end = (span == sec_data->mapcount - 1)
7798 ? sec->size : sec_data->map[span + 1].vma;
7799 char span_type = sec_data->map[span].type;
7800 int itblock_current_pos = 0;
c7b8f16e 7801
a504d23a
LA		 7802 /* Only Thumb2 mode need be supported with this CM4 specific
7803 code, we should not encounter any arm mode eg span_type
7804 != 'a'. */
7805 if (span_type != 't')
7806 continue;
c7b8f16e 7807
a504d23a
LA		 7808 for (i = span_start; i < span_end;)
7809 {
7810 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
7811 bfd_boolean insn_32bit = FALSE;
7812 bfd_boolean is_ldm = FALSE;
7813 bfd_boolean is_vldm = FALSE;
7814 bfd_boolean is_not_last_in_it_block = FALSE;
7815
7816 /* The first 16-bits of all 32-bit thumb2 instructions start
7817 with opcode[15..13]=0b111 and the encoded op1 can be anything
7818 except opcode[12..11]!=0b00.
7819 See 32-bit Thumb instruction encoding. */
7820 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
7821 insn_32bit = TRUE;
c7b8f16e 7822
a504d23a
LA		 7823 /* Compute the predicate that tells if the instruction
7824 is concerned by the IT block
7825 - Creates an error if there is a ldm that is not
7826 last in the IT block thus cannot be replaced
7827 - Otherwise we can create a branch at the end of the
7828 IT block, it will be controlled naturally by IT
7829 with the proper pseudo-predicate
7830 - So the only interesting predicate is the one that
7831 tells that we are not on the last item of an IT
7832 block. */
7833 if (itblock_current_pos != 0)
7834 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 7835
a504d23a
LA		 7836 if (insn_32bit)
7837 {
7838 /* Load the rest of the insn (in manual-friendly order). */
7839 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
7840 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
7841 is_vldm = is_thumb2_vldm (insn);
7842
7843 /* Veneers are created for (v)ldm depending on
7844 option flags and memory accesses conditions; but
7845 if the instruction is not the last instruction of
7846 an IT block, we cannot create a jump there, so we
7847 bail out. */
7848 if ((is_ldm || is_vldm) &&
7849 stm32l4xx_need_create_replacing_stub
7850 (insn, globals->stm32l4xx_fix))
7851 {
7852 if (is_not_last_in_it_block)
7853 {
7854 (*_bfd_error_handler)
7855 /* Note - overlong line used here to allow for translation. */
7856 (_("\
7857%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
7858 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
7859 abfd, sec, (long)i);
7860 }
7861 else
7862 {
7863 elf32_stm32l4xx_erratum_list *newerr =
7864 (elf32_stm32l4xx_erratum_list *)
7865 bfd_zmalloc
7866 (sizeof (elf32_stm32l4xx_erratum_list));
7867
7868 elf32_arm_section_data (sec)
7869 ->stm32l4xx_erratumcount += 1;
7870 newerr->u.b.insn = insn;
7871 /* We create only thumb branches. */
7872 newerr->type =
7873 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
7874 record_stm32l4xx_erratum_veneer
7875 (link_info, newerr, abfd, sec,
7876 i,
7877 is_ldm ?
7878 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
7879 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
7880 newerr->vma = -1;
7881 newerr->next = sec_data->stm32l4xx_erratumlist;
7882 sec_data->stm32l4xx_erratumlist = newerr;
7883 }
7884 }
7885 }
7886 else
7887 {
7888 /* A7.7.37 IT p208
7889 IT blocks are only encoded in T1
7890 Encoding T1: IT{x{y{z}}} <firstcond>
7891 1 0 1 1 - 1 1 1 1 - firstcond - mask
7892 if mask = '0000' then see 'related encodings'
7893 We don't deal with UNPREDICTABLE, just ignore these.
7894 There can be no nested IT blocks so an IT block
7895 is naturally a new one for which it is worth
7896 computing its size. */
7897 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
7898 ((insn & 0x000f) != 0x0000);
7899 /* If we have a new IT block we compute its size. */
7900 if (is_newitblock)
7901 {
7902 /* Compute the number of instructions controlled
7903 by the IT block, it will be used to decide
7904 whether we are inside an IT block or not. */
7905 unsigned int mask = insn & 0x000f;
7906 itblock_current_pos = 4 - ctz (mask);
7907 }
7908 }
7909
7910 i += insn_32bit ? 4 : 2;
99059e56
RM		 7911 }
7912 }
a504d23a
LA		 7913
7914 if (contents != NULL
7915 && elf_section_data (sec)->this_hdr.contents != contents)
7916 free (contents);
7917 contents = NULL;
c7b8f16e 7918 }
906e58ca 7919
a504d23a
LA		 7920 return TRUE;
7921
7922error_return:
7923 if (contents != NULL
7924 && elf_section_data (sec)->this_hdr.contents != contents)
7925 free (contents);
c7b8f16e 7926
a504d23a
LA		 7927 return FALSE;
7928}
c7b8f16e 7929
eb043451
PB		 7930/* Set target relocation values needed during linking. */
7931
7932void
bf21ed78
MS		 7933bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
7934 struct bfd_link_info *link_info,
eb043451 7935 int target1_is_rel,
319850b4 7936 char * target2_type,
99059e56 7937 int fix_v4bx,
c7b8f16e 7938 int use_blx,
99059e56 7939 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 7940 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 7941 int no_enum_warn, int no_wchar_warn,
2de70689
MGD		 7942 int pic_veneer, int fix_cortex_a8,
7943 int fix_arm1176)
eb043451
PB		 7944{
7945 struct elf32_arm_link_hash_table *globals;
7946
7947 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7948 if (globals == NULL)
7949 return;
eb043451
PB		 7950
7951 globals->target1_is_rel = target1_is_rel;
7952 if (strcmp (target2_type, "rel") == 0)
7953 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 7954 else if (strcmp (target2_type, "abs") == 0)
7955 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 7956 else if (strcmp (target2_type, "got-rel") == 0)
7957 globals->target2_reloc = R_ARM_GOT_PREL;
7958 else
7959 {
7960 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
7961 target2_type);
7962 }
319850b4 7963 globals->fix_v4bx = fix_v4bx;
33bfe774 7964 globals->use_blx |= use_blx;
c7b8f16e 7965 globals->vfp11_fix = vfp11_fix;
a504d23a 7966 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 7967 globals->pic_veneer = pic_veneer;
48229727 7968 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 7969 globals->fix_arm1176 = fix_arm1176;
bf21ed78 7970
0ffa91dd
NC		 7971 BFD_ASSERT (is_arm_elf (output_bfd));
7972 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 7973 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 7974}
eb043451 7975
12a0a0fd 7976/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 7977
12a0a0fd
PB		 7978static void
7979insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
7980{
7981 bfd_vma upper;
7982 bfd_vma lower;
7983 int reloc_sign;
7984
7985 BFD_ASSERT ((offset & 1) == 0);
7986
7987 upper = bfd_get_16 (abfd, insn);
7988 lower = bfd_get_16 (abfd, insn + 2);
7989 reloc_sign = (offset < 0) ? 1 : 0;
7990 upper = (upper & ~(bfd_vma) 0x7ff)
7991 | ((offset >> 12) & 0x3ff)
7992 | (reloc_sign << 10);
906e58ca 7993 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 7994 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
7995 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
7996 | ((offset >> 1) & 0x7ff);
7997 bfd_put_16 (abfd, upper, insn);
7998 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 7999}
8000
9b485d32
NC		 8001/* Thumb code calling an ARM function. */
8002
252b5132 8003static int
57e8b36a
NC		 8004elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8005 const char * name,
8006 bfd * input_bfd,
8007 bfd * output_bfd,
8008 asection * input_section,
8009 bfd_byte * hit_data,
8010 asection * sym_sec,
8011 bfd_vma offset,
8012 bfd_signed_vma addend,
f2a9dd69
DJ		 8013 bfd_vma val,
8014 char **error_message)
252b5132 8015{
bcbdc74c 8016 asection * s = 0;
dc810e39 8017 bfd_vma my_offset;
252b5132 8018 long int ret_offset;
bcbdc74c
NC		 8019 struct elf_link_hash_entry * myh;
8020 struct elf32_arm_link_hash_table * globals;
252b5132 8021
f2a9dd69 8022 myh = find_thumb_glue (info, name, error_message);
252b5132 8023 if (myh == NULL)
b34976b6 8024 return FALSE;
252b5132
RH		 8025
8026 globals = elf32_arm_hash_table (info);
252b5132
RH		 8027 BFD_ASSERT (globals != NULL);
8028 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8029
8030 my_offset = myh->root.u.def.value;
8031
3d4d4302
AM		 8032 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8033 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8034
8035 BFD_ASSERT (s != NULL);
8036 BFD_ASSERT (s->contents != NULL);
8037 BFD_ASSERT (s->output_section != NULL);
8038
8039 if ((my_offset & 0x01) == 0x01)
8040 {
8041 if (sym_sec != NULL
8042 && sym_sec->owner != NULL
8043 && !INTERWORK_FLAG (sym_sec->owner))
8044 {
8f615d07 8045 (*_bfd_error_handler)
d003868e 8046 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8047 " first occurrence: %B: Thumb call to ARM"),
d003868e 8048 sym_sec->owner, input_bfd, name);
252b5132 8049
b34976b6 8050 return FALSE;
252b5132
RH		 8051 }
8052
8053 --my_offset;
8054 myh->root.u.def.value = my_offset;
8055
52ab56c2
PB		 8056 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8057 s->contents + my_offset);
252b5132 8058
52ab56c2
PB		 8059 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8060 s->contents + my_offset + 2);
252b5132
RH		 8061
8062 ret_offset =
9b485d32
NC		 8063 /* Address of destination of the stub. */
8064 ((bfd_signed_vma) val)
252b5132 8065 - ((bfd_signed_vma)
57e8b36a
NC		 8066 /* Offset from the start of the current section
8067 to the start of the stubs. */
9b485d32
NC		 8068 (s->output_offset
8069 /* Offset of the start of this stub from the start of the stubs. */
8070 + my_offset
8071 /* Address of the start of the current section. */
8072 + s->output_section->vma)
8073 /* The branch instruction is 4 bytes into the stub. */
8074 + 4
8075 /* ARM branches work from the pc of the instruction + 8. */
8076 + 8);
252b5132 8077
52ab56c2
PB		 8078 put_arm_insn (globals, output_bfd,
8079 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8080 s->contents + my_offset + 4);
252b5132
RH		 8081 }
8082
8083 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8084
427bfd90
NC		 8085 /* Now go back and fix up the original BL insn to point to here. */
8086 ret_offset =
8087 /* Address of where the stub is located. */
8088 (s->output_section->vma + s->output_offset + my_offset)
8089 /* Address of where the BL is located. */
57e8b36a
NC		 8090 - (input_section->output_section->vma + input_section->output_offset
8091 + offset)
427bfd90
NC		 8092 /* Addend in the relocation. */
8093 - addend
8094 /* Biassing for PC-relative addressing. */
8095 - 8;
252b5132 8096
12a0a0fd 8097 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8098
b34976b6 8099 return TRUE;
252b5132
RH		 8100}
8101
a4fd1a8e 8102/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8103
a4fd1a8e
PB		 8104static struct elf_link_hash_entry *
8105elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8106 const char * name,
8107 bfd * input_bfd,
8108 bfd * output_bfd,
8109 asection * sym_sec,
8110 bfd_vma val,
8029a119
NC		 8111 asection * s,
8112 char ** error_message)
252b5132 8113{
dc810e39 8114 bfd_vma my_offset;
252b5132 8115 long int ret_offset;
bcbdc74c
NC		 8116 struct elf_link_hash_entry * myh;
8117 struct elf32_arm_link_hash_table * globals;
252b5132 8118
f2a9dd69 8119 myh = find_arm_glue (info, name, error_message);
252b5132 8120 if (myh == NULL)
a4fd1a8e 8121 return NULL;
252b5132
RH		 8122
8123 globals = elf32_arm_hash_table (info);
252b5132
RH		 8124 BFD_ASSERT (globals != NULL);
8125 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8126
8127 my_offset = myh->root.u.def.value;
252b5132
RH		 8128
8129 if ((my_offset & 0x01) == 0x01)
8130 {
8131 if (sym_sec != NULL
8132 && sym_sec->owner != NULL
8133 && !INTERWORK_FLAG (sym_sec->owner))
8134 {
8f615d07 8135 (*_bfd_error_handler)
d003868e
AM		 8136 (_("%B(%s): warning: interworking not enabled.\n"
8137 " first occurrence: %B: arm call to thumb"),
8138 sym_sec->owner, input_bfd, name);
252b5132 8139 }
9b485d32 8140
252b5132
RH		 8141 --my_offset;
8142 myh->root.u.def.value = my_offset;
8143
0e1862bb
L		 8144 if (bfd_link_pic (info)
8145 || globals->root.is_relocatable_executable
27e55c4d 8146 || globals->pic_veneer)
8f6277f5
PB		 8147 {
8148 /* For relocatable objects we can't use absolute addresses,
8149 so construct the address from a relative offset. */
8150 /* TODO: If the offset is small it's probably worth
8151 constructing the address with adds. */
52ab56c2
PB		 8152 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8153 s->contents + my_offset);
8154 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8155 s->contents + my_offset + 4);
8156 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8157 s->contents + my_offset + 8);
8f6277f5
PB		 8158 /* Adjust the offset by 4 for the position of the add,
8159 and 8 for the pipeline offset. */
8160 ret_offset = (val - (s->output_offset
8161 + s->output_section->vma
8162 + my_offset + 12))
8163 | 1;
8164 bfd_put_32 (output_bfd, ret_offset,
8165 s->contents + my_offset + 12);
8166 }
26079076
PB		 8167 else if (globals->use_blx)
8168 {
8169 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8170 s->contents + my_offset);
8171
8172 /* It's a thumb address. Add the low order bit. */
8173 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8174 s->contents + my_offset + 4);
8175 }
8f6277f5
PB		 8176 else
8177 {
52ab56c2
PB		 8178 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8179 s->contents + my_offset);
252b5132 8180
52ab56c2
PB		 8181 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8182 s->contents + my_offset + 4);
252b5132 8183
8f6277f5
PB		 8184 /* It's a thumb address. Add the low order bit. */
8185 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8186 s->contents + my_offset + 8);
8029a119
NC		 8187
8188 my_offset += 12;
8f6277f5 8189 }
252b5132
RH		 8190 }
8191
8192 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8193
a4fd1a8e
PB		 8194 return myh;
8195}
8196
8197/* Arm code calling a Thumb function. */
8198
8199static int
8200elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8201 const char * name,
8202 bfd * input_bfd,
8203 bfd * output_bfd,
8204 asection * input_section,
8205 bfd_byte * hit_data,
8206 asection * sym_sec,
8207 bfd_vma offset,
8208 bfd_signed_vma addend,
f2a9dd69
DJ		 8209 bfd_vma val,
8210 char **error_message)
a4fd1a8e
PB		 8211{
8212 unsigned long int tmp;
8213 bfd_vma my_offset;
8214 asection * s;
8215 long int ret_offset;
8216 struct elf_link_hash_entry * myh;
8217 struct elf32_arm_link_hash_table * globals;
8218
8219 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8220 BFD_ASSERT (globals != NULL);
8221 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8222
3d4d4302
AM		 8223 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8224 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8225 BFD_ASSERT (s != NULL);
8226 BFD_ASSERT (s->contents != NULL);
8227 BFD_ASSERT (s->output_section != NULL);
8228
8229 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8230 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8231 if (!myh)
8232 return FALSE;
8233
8234 my_offset = myh->root.u.def.value;
252b5132
RH		 8235 tmp = bfd_get_32 (input_bfd, hit_data);
8236 tmp = tmp & 0xFF000000;
8237
9b485d32 8238 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 8239 ret_offset = (s->output_offset
8240 + my_offset
8241 + s->output_section->vma
8242 - (input_section->output_offset
8243 + input_section->output_section->vma
8244 + offset + addend)
8245 - 8);
9a5aca8c 8246
252b5132
RH		 8247 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
8248
dc810e39 8249 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 8250
b34976b6 8251 return TRUE;
252b5132
RH		 8252}
8253
a4fd1a8e
PB		 8254/* Populate Arm stub for an exported Thumb function. */
8255
8256static bfd_boolean
8257elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
8258{
8259 struct bfd_link_info * info = (struct bfd_link_info *) inf;
8260 asection * s;
8261 struct elf_link_hash_entry * myh;
8262 struct elf32_arm_link_hash_entry *eh;
8263 struct elf32_arm_link_hash_table * globals;
8264 asection *sec;
8265 bfd_vma val;
f2a9dd69 8266 char *error_message;
a4fd1a8e 8267
906e58ca 8268 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 8269 /* Allocate stubs for exported Thumb functions on v4t. */
8270 if (eh->export_glue == NULL)
8271 return TRUE;
8272
8273 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8274 BFD_ASSERT (globals != NULL);
8275 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8276
3d4d4302
AM		 8277 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8278 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8279 BFD_ASSERT (s != NULL);
8280 BFD_ASSERT (s->contents != NULL);
8281 BFD_ASSERT (s->output_section != NULL);
8282
8283 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 8284
8285 BFD_ASSERT (sec->output_section != NULL);
8286
a4fd1a8e
PB		 8287 val = eh->export_glue->root.u.def.value + sec->output_offset
8288 + sec->output_section->vma;
8029a119 8289
a4fd1a8e
PB		 8290 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
8291 h->root.u.def.section->owner,
f2a9dd69
DJ		 8292 globals->obfd, sec, val, s,
8293 &error_message);
a4fd1a8e
PB		 8294 BFD_ASSERT (myh);
8295 return TRUE;
8296}
8297
845b51d6
PB		 8298/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
8299
8300static bfd_vma
8301elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
8302{
8303 bfd_byte *p;
8304 bfd_vma glue_addr;
8305 asection *s;
8306 struct elf32_arm_link_hash_table *globals;
8307
8308 globals = elf32_arm_hash_table (info);
845b51d6
PB		 8309 BFD_ASSERT (globals != NULL);
8310 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8311
3d4d4302
AM		 8312 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8313 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 8314 BFD_ASSERT (s != NULL);
8315 BFD_ASSERT (s->contents != NULL);
8316 BFD_ASSERT (s->output_section != NULL);
8317
8318 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
8319
8320 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
8321
8322 if ((globals->bx_glue_offset[reg] & 1) == 0)
8323 {
8324 p = s->contents + glue_addr;
8325 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
8326 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
8327 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
8328 globals->bx_glue_offset[reg] |= 1;
8329 }
8330
8331 return glue_addr + s->output_section->vma + s->output_offset;
8332}
8333
a4fd1a8e
PB		 8334/* Generate Arm stubs for exported Thumb symbols. */
8335static void
906e58ca 8336elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 8337 struct bfd_link_info *link_info)
8338{
8339 struct elf32_arm_link_hash_table * globals;
8340
8029a119
NC		 8341 if (link_info == NULL)
8342 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 8343 return;
8344
8345 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8346 if (globals == NULL)
8347 return;
8348
84c08195
PB		 8349 /* If blx is available then exported Thumb symbols are OK and there is
8350 nothing to do. */
a4fd1a8e
PB		 8351 if (globals->use_blx)
8352 return;
8353
8354 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
8355 link_info);
8356}
8357
47beaa6a
RS		 8358/* Reserve space for COUNT dynamic relocations in relocation selection
8359 SRELOC. */
8360
8361static void
8362elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
8363 bfd_size_type count)
8364{
8365 struct elf32_arm_link_hash_table *htab;
8366
8367 htab = elf32_arm_hash_table (info);
8368 BFD_ASSERT (htab->root.dynamic_sections_created);
8369 if (sreloc == NULL)
8370 abort ();
8371 sreloc->size += RELOC_SIZE (htab) * count;
8372}
8373
34e77a92
RS		 8374/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8375 dynamic, the relocations should go in SRELOC, otherwise they should
8376 go in the special .rel.iplt section. */
8377
8378static void
8379elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
8380 bfd_size_type count)
8381{
8382 struct elf32_arm_link_hash_table *htab;
8383
8384 htab = elf32_arm_hash_table (info);
8385 if (!htab->root.dynamic_sections_created)
8386 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
8387 else
8388 {
8389 BFD_ASSERT (sreloc != NULL);
8390 sreloc->size += RELOC_SIZE (htab) * count;
8391 }
8392}
8393
47beaa6a
RS		 8394/* Add relocation REL to the end of relocation section SRELOC. */
8395
8396static void
8397elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
8398 asection *sreloc, Elf_Internal_Rela *rel)
8399{
8400 bfd_byte *loc;
8401 struct elf32_arm_link_hash_table *htab;
8402
8403 htab = elf32_arm_hash_table (info);
34e77a92
RS		 8404 if (!htab->root.dynamic_sections_created
8405 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
8406 sreloc = htab->root.irelplt;
47beaa6a
RS		 8407 if (sreloc == NULL)
8408 abort ();
8409 loc = sreloc->contents;
8410 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
8411 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
8412 abort ();
8413 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
8414}
8415
34e77a92
RS		 8416/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8417 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8418 to .plt. */
8419
8420static void
8421elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
8422 bfd_boolean is_iplt_entry,
8423 union gotplt_union *root_plt,
8424 struct arm_plt_info *arm_plt)
8425{
8426 struct elf32_arm_link_hash_table *htab;
8427 asection *splt;
8428 asection *sgotplt;
8429
8430 htab = elf32_arm_hash_table (info);
8431
8432 if (is_iplt_entry)
8433 {
8434 splt = htab->root.iplt;
8435 sgotplt = htab->root.igotplt;
8436
99059e56
RM		 8437 /* NaCl uses a special first entry in .iplt too. */
8438 if (htab->nacl_p && splt->size == 0)
8439 splt->size += htab->plt_header_size;
8440
34e77a92
RS		 8441 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8442 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
8443 }
8444 else
8445 {
8446 splt = htab->root.splt;
8447 sgotplt = htab->root.sgotplt;
8448
8449 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8450 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
8451
8452 /* If this is the first .plt entry, make room for the special
8453 first entry. */
8454 if (splt->size == 0)
8455 splt->size += htab->plt_header_size;
9f19ab6d
WN		 8456
8457 htab->next_tls_desc_index++;
34e77a92
RS		 8458 }
8459
8460 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8461 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8462 splt->size += PLT_THUMB_STUB_SIZE;
8463 root_plt->offset = splt->size;
8464 splt->size += htab->plt_entry_size;
8465
8466 if (!htab->symbian_p)
8467 {
8468 /* We also need to make an entry in the .got.plt section, which
8469 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 8470 if (is_iplt_entry)
8471 arm_plt->got_offset = sgotplt->size;
8472 else
8473 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 8474 sgotplt->size += 4;
8475 }
8476}
8477
b38cadfb
NC		 8478static bfd_vma
8479arm_movw_immediate (bfd_vma value)
8480{
8481 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
8482}
8483
8484static bfd_vma
8485arm_movt_immediate (bfd_vma value)
8486{
8487 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
8488}
8489
34e77a92
RS		 8490/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8491 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8492 Otherwise, DYNINDX is the index of the symbol in the dynamic
8493 symbol table and SYM_VALUE is undefined.
8494
8495 ROOT_PLT points to the offset of the PLT entry from the start of its
8496 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 8497 bookkeeping information.
34e77a92 8498
57460bcf
NC		 8499 Returns FALSE if there was a problem. */
8500
8501static bfd_boolean
34e77a92
RS		 8502elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
8503 union gotplt_union *root_plt,
8504 struct arm_plt_info *arm_plt,
8505 int dynindx, bfd_vma sym_value)
8506{
8507 struct elf32_arm_link_hash_table *htab;
8508 asection *sgot;
8509 asection *splt;
8510 asection *srel;
8511 bfd_byte *loc;
8512 bfd_vma plt_index;
8513 Elf_Internal_Rela rel;
8514 bfd_vma plt_header_size;
8515 bfd_vma got_header_size;
8516
8517 htab = elf32_arm_hash_table (info);
8518
8519 /* Pick the appropriate sections and sizes. */
8520 if (dynindx == -1)
8521 {
8522 splt = htab->root.iplt;
8523 sgot = htab->root.igotplt;
8524 srel = htab->root.irelplt;
8525
8526 /* There are no reserved entries in .igot.plt, and no special
8527 first entry in .iplt. */
8528 got_header_size = 0;
8529 plt_header_size = 0;
8530 }
8531 else
8532 {
8533 splt = htab->root.splt;
8534 sgot = htab->root.sgotplt;
8535 srel = htab->root.srelplt;
8536
8537 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
8538 plt_header_size = htab->plt_header_size;
8539 }
8540 BFD_ASSERT (splt != NULL && srel != NULL);
8541
8542 /* Fill in the entry in the procedure linkage table. */
8543 if (htab->symbian_p)
8544 {
8545 BFD_ASSERT (dynindx >= 0);
8546 put_arm_insn (htab, output_bfd,
8547 elf32_arm_symbian_plt_entry[0],
8548 splt->contents + root_plt->offset);
8549 bfd_put_32 (output_bfd,
8550 elf32_arm_symbian_plt_entry[1],
8551 splt->contents + root_plt->offset + 4);
8552
8553 /* Fill in the entry in the .rel.plt section. */
8554 rel.r_offset = (splt->output_section->vma
8555 + splt->output_offset
8556 + root_plt->offset + 4);
8557 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
8558
8559 /* Get the index in the procedure linkage table which
8560 corresponds to this symbol. This is the index of this symbol
8561 in all the symbols for which we are making plt entries. The
8562 first entry in the procedure linkage table is reserved. */
8563 plt_index = ((root_plt->offset - plt_header_size)
8564 / htab->plt_entry_size);
8565 }
8566 else
8567 {
8568 bfd_vma got_offset, got_address, plt_address;
8569 bfd_vma got_displacement, initial_got_entry;
8570 bfd_byte * ptr;
8571
8572 BFD_ASSERT (sgot != NULL);
8573
8574 /* Get the offset into the .(i)got.plt table of the entry that
8575 corresponds to this function. */
8576 got_offset = (arm_plt->got_offset & -2);
8577
8578 /* Get the index in the procedure linkage table which
8579 corresponds to this symbol. This is the index of this symbol
8580 in all the symbols for which we are making plt entries.
8581 After the reserved .got.plt entries, all symbols appear in
8582 the same order as in .plt. */
8583 plt_index = (got_offset - got_header_size) / 4;
8584
8585 /* Calculate the address of the GOT entry. */
8586 got_address = (sgot->output_section->vma
8587 + sgot->output_offset
8588 + got_offset);
8589
8590 /* ...and the address of the PLT entry. */
8591 plt_address = (splt->output_section->vma
8592 + splt->output_offset
8593 + root_plt->offset);
8594
8595 ptr = splt->contents + root_plt->offset;
0e1862bb 8596 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 8597 {
8598 unsigned int i;
8599 bfd_vma val;
8600
8601 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8602 {
8603 val = elf32_arm_vxworks_shared_plt_entry[i];
8604 if (i == 2)
8605 val |= got_address - sgot->output_section->vma;
8606 if (i == 5)
8607 val |= plt_index * RELOC_SIZE (htab);
8608 if (i == 2 || i == 5)
8609 bfd_put_32 (output_bfd, val, ptr);
8610 else
8611 put_arm_insn (htab, output_bfd, val, ptr);
8612 }
8613 }
8614 else if (htab->vxworks_p)
8615 {
8616 unsigned int i;
8617 bfd_vma val;
8618
8619 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8620 {
8621 val = elf32_arm_vxworks_exec_plt_entry[i];
8622 if (i == 2)
8623 val |= got_address;
8624 if (i == 4)
8625 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
8626 if (i == 5)
8627 val |= plt_index * RELOC_SIZE (htab);
8628 if (i == 2 || i == 5)
8629 bfd_put_32 (output_bfd, val, ptr);
8630 else
8631 put_arm_insn (htab, output_bfd, val, ptr);
8632 }
8633
8634 loc = (htab->srelplt2->contents
8635 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
8636
8637 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
8638 referencing the GOT for this PLT entry. */
8639 rel.r_offset = plt_address + 8;
8640 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
8641 rel.r_addend = got_offset;
8642 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8643 loc += RELOC_SIZE (htab);
8644
8645 /* Create the R_ARM_ABS32 relocation referencing the
8646 beginning of the PLT for this GOT entry. */
8647 rel.r_offset = got_address;
8648 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
8649 rel.r_addend = 0;
8650 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8651 }
b38cadfb
NC		 8652 else if (htab->nacl_p)
8653 {
8654 /* Calculate the displacement between the PLT slot and the
8655 common tail that's part of the special initial PLT slot. */
6034aab8 8656 int32_t tail_displacement
b38cadfb
NC		 8657 = ((splt->output_section->vma + splt->output_offset
8658 + ARM_NACL_PLT_TAIL_OFFSET)
8659 - (plt_address + htab->plt_entry_size + 4));
8660 BFD_ASSERT ((tail_displacement & 3) == 0);
8661 tail_displacement >>= 2;
8662
8663 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
8664 || (-tail_displacement & 0xff000000) == 0);
8665
8666 /* Calculate the displacement between the PLT slot and the entry
8667 in the GOT. The offset accounts for the value produced by
8668 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 8669 got_displacement = (got_address
99059e56 8670 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 8671
8672 /* NaCl does not support interworking at all. */
8673 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
8674
8675 put_arm_insn (htab, output_bfd,
8676 elf32_arm_nacl_plt_entry[0]
8677 | arm_movw_immediate (got_displacement),
8678 ptr + 0);
8679 put_arm_insn (htab, output_bfd,
8680 elf32_arm_nacl_plt_entry[1]
8681 | arm_movt_immediate (got_displacement),
8682 ptr + 4);
8683 put_arm_insn (htab, output_bfd,
8684 elf32_arm_nacl_plt_entry[2],
8685 ptr + 8);
8686 put_arm_insn (htab, output_bfd,
8687 elf32_arm_nacl_plt_entry[3]
8688 | (tail_displacement & 0x00ffffff),
8689 ptr + 12);
8690 }
57460bcf
NC		 8691 else if (using_thumb_only (htab))
8692 {
eed94f8f 8693 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 8694 if (!using_thumb2 (htab))
eed94f8f
NC		 8695 {
8696 /* FIXME: We ought to be able to generate thumb-1 PLT
8697 instructions... */
8698 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
8699 output_bfd);
8700 return FALSE;
8701 }
57460bcf 8702
eed94f8f
NC		 8703 /* Calculate the displacement between the PLT slot and the entry in
8704 the GOT. The 12-byte offset accounts for the value produced by
8705 adding to pc in the 3rd instruction of the PLT stub. */
8706 got_displacement = got_address - (plt_address + 12);
8707
8708 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
8709 instead of 'put_thumb_insn'. */
8710 put_arm_insn (htab, output_bfd,
8711 elf32_thumb2_plt_entry[0]
8712 | ((got_displacement & 0x000000ff) << 16)
8713 | ((got_displacement & 0x00000700) << 20)
8714 | ((got_displacement & 0x00000800) >> 1)
8715 | ((got_displacement & 0x0000f000) >> 12),
8716 ptr + 0);
8717 put_arm_insn (htab, output_bfd,
8718 elf32_thumb2_plt_entry[1]
8719 | ((got_displacement & 0x00ff0000) )
8720 | ((got_displacement & 0x07000000) << 4)
8721 | ((got_displacement & 0x08000000) >> 17)
8722 | ((got_displacement & 0xf0000000) >> 28),
8723 ptr + 4);
8724 put_arm_insn (htab, output_bfd,
8725 elf32_thumb2_plt_entry[2],
8726 ptr + 8);
8727 put_arm_insn (htab, output_bfd,
8728 elf32_thumb2_plt_entry[3],
8729 ptr + 12);
57460bcf 8730 }
34e77a92
RS		 8731 else
8732 {
8733 /* Calculate the displacement between the PLT slot and the
8734 entry in the GOT. The eight-byte offset accounts for the
8735 value produced by adding to pc in the first instruction
8736 of the PLT stub. */
8737 got_displacement = got_address - (plt_address + 8);
8738
34e77a92
RS		 8739 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8740 {
8741 put_thumb_insn (htab, output_bfd,
8742 elf32_arm_plt_thumb_stub[0], ptr - 4);
8743 put_thumb_insn (htab, output_bfd,
8744 elf32_arm_plt_thumb_stub[1], ptr - 2);
8745 }
8746
1db37fe6
YG		 8747 if (!elf32_arm_use_long_plt_entry)
8748 {
8749 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
8750
8751 put_arm_insn (htab, output_bfd,
8752 elf32_arm_plt_entry_short[0]
8753 | ((got_displacement & 0x0ff00000) >> 20),
8754 ptr + 0);
8755 put_arm_insn (htab, output_bfd,
8756 elf32_arm_plt_entry_short[1]
8757 | ((got_displacement & 0x000ff000) >> 12),
8758 ptr+ 4);
8759 put_arm_insn (htab, output_bfd,
8760 elf32_arm_plt_entry_short[2]
8761 | (got_displacement & 0x00000fff),
8762 ptr + 8);
34e77a92 8763#ifdef FOUR_WORD_PLT
1db37fe6 8764 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 8765#endif
1db37fe6
YG		 8766 }
8767 else
8768 {
8769 put_arm_insn (htab, output_bfd,
8770 elf32_arm_plt_entry_long[0]
8771 | ((got_displacement & 0xf0000000) >> 28),
8772 ptr + 0);
8773 put_arm_insn (htab, output_bfd,
8774 elf32_arm_plt_entry_long[1]
8775 | ((got_displacement & 0x0ff00000) >> 20),
8776 ptr + 4);
8777 put_arm_insn (htab, output_bfd,
8778 elf32_arm_plt_entry_long[2]
8779 | ((got_displacement & 0x000ff000) >> 12),
8780 ptr+ 8);
8781 put_arm_insn (htab, output_bfd,
8782 elf32_arm_plt_entry_long[3]
8783 | (got_displacement & 0x00000fff),
8784 ptr + 12);
8785 }
34e77a92
RS		 8786 }
8787
8788 /* Fill in the entry in the .rel(a).(i)plt section. */
8789 rel.r_offset = got_address;
8790 rel.r_addend = 0;
8791 if (dynindx == -1)
8792 {
8793 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
8794 The dynamic linker or static executable then calls SYM_VALUE
8795 to determine the correct run-time value of the .igot.plt entry. */
8796 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
8797 initial_got_entry = sym_value;
8798 }
8799 else
8800 {
8801 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
8802 initial_got_entry = (splt->output_section->vma
8803 + splt->output_offset);
8804 }
8805
8806 /* Fill in the entry in the global offset table. */
8807 bfd_put_32 (output_bfd, initial_got_entry,
8808 sgot->contents + got_offset);
8809 }
8810
aba8c3de
WN		 8811 if (dynindx == -1)
8812 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
8813 else
8814 {
8815 loc = srel->contents + plt_index * RELOC_SIZE (htab);
8816 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8817 }
57460bcf
NC		 8818
8819 return TRUE;
34e77a92
RS		 8820}
8821
eb043451
PB		 8822/* Some relocations map to different relocations depending on the
8823 target. Return the real relocation. */
8029a119 8824
eb043451
PB		 8825static int
8826arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
8827 int r_type)
8828{
8829 switch (r_type)
8830 {
8831 case R_ARM_TARGET1:
8832 if (globals->target1_is_rel)
8833 return R_ARM_REL32;
8834 else
8835 return R_ARM_ABS32;
8836
8837 case R_ARM_TARGET2:
8838 return globals->target2_reloc;
8839
8840 default:
8841 return r_type;
8842 }
8843}
eb043451 8844
ba93b8ac
DJ		 8845/* Return the base VMA address which should be subtracted from real addresses
8846 when resolving @dtpoff relocation.
8847 This is PT_TLS segment p_vaddr. */
8848
8849static bfd_vma
8850dtpoff_base (struct bfd_link_info *info)
8851{
8852 /* If tls_sec is NULL, we should have signalled an error already. */
8853 if (elf_hash_table (info)->tls_sec == NULL)
8854 return 0;
8855 return elf_hash_table (info)->tls_sec->vma;
8856}
8857
8858/* Return the relocation value for @tpoff relocation
8859 if STT_TLS virtual address is ADDRESS. */
8860
8861static bfd_vma
8862tpoff (struct bfd_link_info *info, bfd_vma address)
8863{
8864 struct elf_link_hash_table *htab = elf_hash_table (info);
8865 bfd_vma base;
8866
8867 /* If tls_sec is NULL, we should have signalled an error already. */
8868 if (htab->tls_sec == NULL)
8869 return 0;
8870 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
8871 return address - htab->tls_sec->vma + base;
8872}
8873
00a97672
RS		 8874/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
8875 VALUE is the relocation value. */
8876
8877static bfd_reloc_status_type
8878elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
8879{
8880 if (value > 0xfff)
8881 return bfd_reloc_overflow;
8882
8883 value |= bfd_get_32 (abfd, data) & 0xfffff000;
8884 bfd_put_32 (abfd, value, data);
8885 return bfd_reloc_ok;
8886}
8887
0855e32b
NS		 8888/* Handle TLS relaxations. Relaxing is possible for symbols that use
8889 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
8890 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
8891
8892 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
8893 is to then call final_link_relocate. Return other values in the
62672b10
NS		 8894 case of error.
8895
8896 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
8897 the pre-relaxed code. It would be nice if the relocs were updated
8898 to match the optimization. */
0855e32b 8899
b38cadfb 8900static bfd_reloc_status_type
0855e32b 8901elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 8902 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 8903 Elf_Internal_Rela *rel, unsigned long is_local)
8904{
8905 unsigned long insn;
b38cadfb 8906
0855e32b
NS		 8907 switch (ELF32_R_TYPE (rel->r_info))
8908 {
8909 default:
8910 return bfd_reloc_notsupported;
b38cadfb 8911
0855e32b
NS		 8912 case R_ARM_TLS_GOTDESC:
8913 if (is_local)
8914 insn = 0;
8915 else
8916 {
8917 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8918 if (insn & 1)
8919 insn -= 5; /* THUMB */
8920 else
8921 insn -= 8; /* ARM */
8922 }
8923 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8924 return bfd_reloc_continue;
8925
8926 case R_ARM_THM_TLS_DESCSEQ:
8927 /* Thumb insn. */
8928 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
8929 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
8930 {
8931 if (is_local)
8932 /* nop */
8933 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8934 }
8935 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
8936 {
8937 if (is_local)
8938 /* nop */
8939 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8940 else
8941 /* ldr rx,[ry] */
8942 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
8943 }
8944 else if ((insn & 0xff87) == 0x4780) /* blx rx */
8945 {
8946 if (is_local)
8947 /* nop */
8948 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8949 else
8950 /* mov r0, rx */
8951 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
8952 contents + rel->r_offset);
8953 }
8954 else
8955 {
8956 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
8957 /* It's a 32 bit instruction, fetch the rest of it for
8958 error generation. */
8959 insn = (insn << 16)
8960 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
8961 (*_bfd_error_handler)
8962 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
8963 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8964 return bfd_reloc_notsupported;
8965 }
8966 break;
b38cadfb 8967
0855e32b
NS		 8968 case R_ARM_TLS_DESCSEQ:
8969 /* arm insn. */
8970 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8971 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
8972 {
8973 if (is_local)
8974 /* mov rx, ry */
8975 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
8976 contents + rel->r_offset);
8977 }
8978 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
8979 {
8980 if (is_local)
8981 /* nop */
8982 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8983 else
8984 /* ldr rx,[ry] */
8985 bfd_put_32 (input_bfd, insn & 0xfffff000,
8986 contents + rel->r_offset);
8987 }
8988 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
8989 {
8990 if (is_local)
8991 /* nop */
8992 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8993 else
8994 /* mov r0, rx */
8995 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
8996 contents + rel->r_offset);
8997 }
8998 else
8999 {
9000 (*_bfd_error_handler)
9001 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
9002 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9003 return bfd_reloc_notsupported;
9004 }
9005 break;
9006
9007 case R_ARM_TLS_CALL:
9008 /* GD->IE relaxation, turn the instruction into 'nop' or
9009 'ldr r0, [pc,r0]' */
9010 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9011 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9012 break;
b38cadfb 9013
0855e32b 9014 case R_ARM_THM_TLS_CALL:
6a631e86 9015 /* GD->IE relaxation. */
0855e32b
NS		 9016 if (!is_local)
9017 /* add r0,pc; ldr r0, [r0] */
9018 insn = 0x44786800;
60a019a0 9019 else if (using_thumb2 (globals))
0855e32b
NS		 9020 /* nop.w */
9021 insn = 0xf3af8000;
9022 else
9023 /* nop; nop */
9024 insn = 0xbf00bf00;
b38cadfb 9025
0855e32b
NS		 9026 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9027 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9028 break;
9029 }
9030 return bfd_reloc_ok;
9031}
9032
4962c51a
MS		 9033/* For a given value of n, calculate the value of G_n as required to
9034 deal with group relocations. We return it in the form of an
9035 encoded constant-and-rotation, together with the final residual. If n is
9036 specified as less than zero, then final_residual is filled with the
9037 input value and no further action is performed. */
9038
9039static bfd_vma
9040calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9041{
9042 int current_n;
9043 bfd_vma g_n;
9044 bfd_vma encoded_g_n = 0;
9045 bfd_vma residual = value; /* Also known as Y_n. */
9046
9047 for (current_n = 0; current_n <= n; current_n++)
9048 {
9049 int shift;
9050
9051 /* Calculate which part of the value to mask. */
9052 if (residual == 0)
99059e56 9053 shift = 0;
4962c51a 9054 else
99059e56
RM		 9055 {
9056 int msb;
9057
9058 /* Determine the most significant bit in the residual and
9059 align the resulting value to a 2-bit boundary. */
9060 for (msb = 30; msb >= 0; msb -= 2)
9061 if (residual & (3 << msb))
9062 break;
9063
9064 /* The desired shift is now (msb - 6), or zero, whichever
9065 is the greater. */
9066 shift = msb - 6;
9067 if (shift < 0)
9068 shift = 0;
9069 }
4962c51a
MS		 9070
9071 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9072 g_n = residual & (0xff << shift);
9073 encoded_g_n = (g_n >> shift)
99059e56 9074 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9075
9076 /* Calculate the residual for the next time around. */
9077 residual &= ~g_n;
9078 }
9079
9080 *final_residual = residual;
9081
9082 return encoded_g_n;
9083}
9084
9085/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9086 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9087
4962c51a 9088static int
906e58ca 9089identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9090{
9091 int opcode = insn & 0x1e00000;
9092
9093 if (opcode == 1 << 23) /* ADD */
9094 return 1;
9095
9096 if (opcode == 1 << 22) /* SUB */
9097 return -1;
9098
9099 return 0;
9100}
9101
252b5132 9102/* Perform a relocation as part of a final link. */
9b485d32 9103
252b5132 9104static bfd_reloc_status_type
57e8b36a
NC		 9105elf32_arm_final_link_relocate (reloc_howto_type * howto,
9106 bfd * input_bfd,
9107 bfd * output_bfd,
9108 asection * input_section,
9109 bfd_byte * contents,
9110 Elf_Internal_Rela * rel,
9111 bfd_vma value,
9112 struct bfd_link_info * info,
9113 asection * sym_sec,
9114 const char * sym_name,
34e77a92
RS		 9115 unsigned char st_type,
9116 enum arm_st_branch_type branch_type,
0945cdfd 9117 struct elf_link_hash_entry * h,
f2a9dd69 9118 bfd_boolean * unresolved_reloc_p,
8029a119 9119 char ** error_message)
252b5132
RH		 9120{
9121 unsigned long r_type = howto->type;
9122 unsigned long r_symndx;
9123 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9124 bfd_vma * local_got_offsets;
0855e32b 9125 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9126 asection * sgot;
9127 asection * splt;
252b5132 9128 asection * sreloc = NULL;
362d30a1 9129 asection * srelgot;
252b5132 9130 bfd_vma addend;
ba96a88f 9131 bfd_signed_vma signed_addend;
34e77a92
RS		 9132 unsigned char dynreloc_st_type;
9133 bfd_vma dynreloc_value;
ba96a88f 9134 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9135 struct elf32_arm_link_hash_entry *eh;
9136 union gotplt_union *root_plt;
9137 struct arm_plt_info *arm_plt;
9138 bfd_vma plt_offset;
9139 bfd_vma gotplt_offset;
9140 bfd_boolean has_iplt_entry;
f21f3fe0 9141
9c504268 9142 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9143 if (globals == NULL)
9144 return bfd_reloc_notsupported;
9c504268 9145
0ffa91dd
NC		 9146 BFD_ASSERT (is_arm_elf (input_bfd));
9147
9148 /* Some relocation types map to different relocations depending on the
9c504268 9149 target. We pick the right one here. */
eb043451 9150 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9151
9152 /* It is possible to have linker relaxations on some TLS access
9153 models. Update our information here. */
9154 r_type = elf32_arm_tls_transition (info, r_type, h);
9155
eb043451
PB		 9156 if (r_type != howto->type)
9157 howto = elf32_arm_howto_from_type (r_type);
9c504268 9158
34e77a92 9159 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9160 sgot = globals->root.sgot;
252b5132 9161 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9162 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9163
34e77a92
RS		 9164 if (globals->root.dynamic_sections_created)
9165 srelgot = globals->root.srelgot;
9166 else
9167 srelgot = NULL;
9168
252b5132
RH		 9169 r_symndx = ELF32_R_SYM (rel->r_info);
9170
4e7fd91e 9171 if (globals->use_rel)
ba96a88f 9172 {
4e7fd91e
PB		 9173 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9174
9175 if (addend & ((howto->src_mask + 1) >> 1))
9176 {
9177 signed_addend = -1;
9178 signed_addend &= ~ howto->src_mask;
9179 signed_addend |= addend;
9180 }
9181 else
9182 signed_addend = addend;
ba96a88f
NC		 9183 }
9184 else
4e7fd91e 9185 addend = signed_addend = rel->r_addend;
f21f3fe0 9186
39f21624
NC		 9187 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9188 are resolving a function call relocation. */
9189 if (using_thumb_only (globals)
9190 && (r_type == R_ARM_THM_CALL
9191 || r_type == R_ARM_THM_JUMP24)
9192 && branch_type == ST_BRANCH_TO_ARM)
9193 branch_type = ST_BRANCH_TO_THUMB;
9194
34e77a92
RS		 9195 /* Record the symbol information that should be used in dynamic
9196 relocations. */
9197 dynreloc_st_type = st_type;
9198 dynreloc_value = value;
9199 if (branch_type == ST_BRANCH_TO_THUMB)
9200 dynreloc_value |= 1;
9201
9202 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9203 VALUE appropriately for relocations that we resolve at link time. */
9204 has_iplt_entry = FALSE;
9205 if (elf32_arm_get_plt_info (input_bfd, eh, r_symndx, &root_plt, &arm_plt)
9206 && root_plt->offset != (bfd_vma) -1)
9207 {
9208 plt_offset = root_plt->offset;
9209 gotplt_offset = arm_plt->got_offset;
9210
9211 if (h == NULL || eh->is_iplt)
9212 {
9213 has_iplt_entry = TRUE;
9214 splt = globals->root.iplt;
9215
9216 /* Populate .iplt entries here, because not all of them will
9217 be seen by finish_dynamic_symbol. The lower bit is set if
9218 we have already populated the entry. */
9219 if (plt_offset & 1)
9220 plt_offset--;
9221 else
9222 {
57460bcf
NC		 9223 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9224 -1, dynreloc_value))
9225 root_plt->offset |= 1;
9226 else
9227 return bfd_reloc_notsupported;
34e77a92
RS		 9228 }
9229
9230 /* Static relocations always resolve to the .iplt entry. */
9231 st_type = STT_FUNC;
9232 value = (splt->output_section->vma
9233 + splt->output_offset
9234 + plt_offset);
9235 branch_type = ST_BRANCH_TO_ARM;
9236
9237 /* If there are non-call relocations that resolve to the .iplt
9238 entry, then all dynamic ones must too. */
9239 if (arm_plt->noncall_refcount != 0)
9240 {
9241 dynreloc_st_type = st_type;
9242 dynreloc_value = value;
9243 }
9244 }
9245 else
9246 /* We populate the .plt entry in finish_dynamic_symbol. */
9247 splt = globals->root.splt;
9248 }
9249 else
9250 {
9251 splt = NULL;
9252 plt_offset = (bfd_vma) -1;
9253 gotplt_offset = (bfd_vma) -1;
9254 }
9255
252b5132
RH		 9256 switch (r_type)
9257 {
9258 case R_ARM_NONE:
28a094c2
DJ		 9259 /* We don't need to find a value for this symbol. It's just a
9260 marker. */
9261 *unresolved_reloc_p = FALSE;
252b5132
RH		 9262 return bfd_reloc_ok;
9263
00a97672
RS		 9264 case R_ARM_ABS12:
9265 if (!globals->vxworks_p)
9266 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9267
252b5132
RH		 9268 case R_ARM_PC24:
9269 case R_ARM_ABS32:
bb224fc3 9270 case R_ARM_ABS32_NOI:
252b5132 9271 case R_ARM_REL32:
bb224fc3 9272 case R_ARM_REL32_NOI:
5b5bb741
PB		 9273 case R_ARM_CALL:
9274 case R_ARM_JUMP24:
dfc5f959 9275 case R_ARM_XPC25:
eb043451 9276 case R_ARM_PREL31:
7359ea65 9277 case R_ARM_PLT32:
7359ea65
DJ		 9278 /* Handle relocations which should use the PLT entry. ABS32/REL32
9279 will use the symbol's value, which may point to a PLT entry, but we
9280 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 9281 branches in this object should go to it, except if the PLT is too
9282 far away, in which case a long branch stub should be inserted. */
bb224fc3 9283 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 9284 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 9285 && r_type != R_ARM_CALL
9286 && r_type != R_ARM_JUMP24
9287 && r_type != R_ARM_PLT32)
34e77a92 9288 && plt_offset != (bfd_vma) -1)
7359ea65 9289 {
34e77a92
RS		 9290 /* If we've created a .plt section, and assigned a PLT entry
9291 to this function, it must either be a STT_GNU_IFUNC reference
9292 or not be known to bind locally. In other cases, we should
9293 have cleared the PLT entry by now. */
9294 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 9295
9296 value = (splt->output_section->vma
9297 + splt->output_offset
34e77a92 9298 + plt_offset);
0945cdfd 9299 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 9300 return _bfd_final_link_relocate (howto, input_bfd, input_section,
9301 contents, rel->r_offset, value,
00a97672 9302 rel->r_addend);
7359ea65
DJ		 9303 }
9304
67687978
PB		 9305 /* When generating a shared object or relocatable executable, these
9306 relocations are copied into the output file to be resolved at
9307 run time. */
0e1862bb
L		 9308 if ((bfd_link_pic (info)
9309 || globals->root.is_relocatable_executable)
7359ea65 9310 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 9311 && !(globals->vxworks_p
3348747a
NS		 9312 && strcmp (input_section->output_section->name,
9313 ".tls_vars") == 0)
bb224fc3 9314 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 9315 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 9316 && !(input_bfd == globals->stub_bfd
9317 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 9318 && (h == NULL
9319 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
9320 || h->root.type != bfd_link_hash_undefweak)
9321 && r_type != R_ARM_PC24
5b5bb741
PB		 9322 && r_type != R_ARM_CALL
9323 && r_type != R_ARM_JUMP24
ee06dc07 9324 && r_type != R_ARM_PREL31
7359ea65 9325 && r_type != R_ARM_PLT32)
252b5132 9326 {
947216bf 9327 Elf_Internal_Rela outrel;
b34976b6 9328 bfd_boolean skip, relocate;
f21f3fe0 9329
52db4ec2
JW		 9330 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
9331 && !h->def_regular)
9332 {
9333 char *v = _("shared object");
9334
0e1862bb 9335 if (bfd_link_executable (info))
52db4ec2
JW		 9336 v = _("PIE executable");
9337
9338 (*_bfd_error_handler)
9339 (_("%B: relocation %s against external or undefined symbol `%s'"
9340 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
9341 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
9342 return bfd_reloc_notsupported;
9343 }
9344
0945cdfd
DJ		 9345 *unresolved_reloc_p = FALSE;
9346
34e77a92 9347 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 9348 {
83bac4b0
NC		 9349 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
9350 ! globals->use_rel);
f21f3fe0 9351
83bac4b0 9352 if (sreloc == NULL)
252b5132 9353 return bfd_reloc_notsupported;
252b5132 9354 }
f21f3fe0 9355
b34976b6
AM		 9356 skip = FALSE;
9357 relocate = FALSE;
f21f3fe0 9358
00a97672 9359 outrel.r_addend = addend;
c629eae0
JJ		 9360 outrel.r_offset =
9361 _bfd_elf_section_offset (output_bfd, info, input_section,
9362 rel->r_offset);
9363 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 9364 skip = TRUE;
0bb2d96a 9365 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 9366 skip = TRUE, relocate = TRUE;
252b5132
RH		 9367 outrel.r_offset += (input_section->output_section->vma
9368 + input_section->output_offset);
f21f3fe0 9369
252b5132 9370 if (skip)
0bb2d96a 9371 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 9372 else if (h != NULL
9373 && h->dynindx != -1
0e1862bb 9374 && (!bfd_link_pic (info)
a496fbc8 9375 || !SYMBOLIC_BIND (info, h)
f5385ebf 9376 || !h->def_regular))
5e681ec4 9377 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 9378 else
9379 {
a16385dc
MM		 9380 int symbol;
9381
5e681ec4 9382 /* This symbol is local, or marked to become local. */
34e77a92 9383 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 9384 if (globals->symbian_p)
6366ff1e 9385 {
74541ad4
AM		 9386 asection *osec;
9387
6366ff1e
MM		 9388 /* On Symbian OS, the data segment and text segement
9389 can be relocated independently. Therefore, we
9390 must indicate the segment to which this
9391 relocation is relative. The BPABI allows us to
9392 use any symbol in the right segment; we just use
9393 the section symbol as it is convenient. (We
9394 cannot use the symbol given by "h" directly as it
74541ad4
AM		 9395 will not appear in the dynamic symbol table.)
9396
9397 Note that the dynamic linker ignores the section
9398 symbol value, so we don't subtract osec->vma
9399 from the emitted reloc addend. */
10dbd1f3 9400 if (sym_sec)
74541ad4 9401 osec = sym_sec->output_section;
10dbd1f3 9402 else
74541ad4
AM		 9403 osec = input_section->output_section;
9404 symbol = elf_section_data (osec)->dynindx;
9405 if (symbol == 0)
9406 {
9407 struct elf_link_hash_table *htab = elf_hash_table (info);
9408
9409 if ((osec->flags & SEC_READONLY) == 0
9410 && htab->data_index_section != NULL)
9411 osec = htab->data_index_section;
9412 else
9413 osec = htab->text_index_section;
9414 symbol = elf_section_data (osec)->dynindx;
9415 }
6366ff1e
MM		 9416 BFD_ASSERT (symbol != 0);
9417 }
a16385dc
MM		 9418 else
9419 /* On SVR4-ish systems, the dynamic loader cannot
9420 relocate the text and data segments independently,
9421 so the symbol does not matter. */
9422 symbol = 0;
34e77a92
RS		 9423 if (dynreloc_st_type == STT_GNU_IFUNC)
9424 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9425 to the .iplt entry. Instead, every non-call reference
9426 must use an R_ARM_IRELATIVE relocation to obtain the
9427 correct run-time address. */
9428 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
9429 else
9430 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 9431 if (globals->use_rel)
9432 relocate = TRUE;
9433 else
34e77a92 9434 outrel.r_addend += dynreloc_value;
252b5132 9435 }
f21f3fe0 9436
47beaa6a 9437 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 9438
f21f3fe0 9439 /* If this reloc is against an external symbol, we do not want to
252b5132 9440 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 9441 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 9442 if (! relocate)
9443 return bfd_reloc_ok;
9a5aca8c 9444
f21f3fe0 9445 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 9446 contents, rel->r_offset,
9447 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 9448 }
9449 else switch (r_type)
9450 {
00a97672
RS		 9451 case R_ARM_ABS12:
9452 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9453
dfc5f959 9454 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 9455 case R_ARM_CALL:
9456 case R_ARM_JUMP24:
8029a119 9457 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 9458 case R_ARM_PLT32:
906e58ca 9459 {
906e58ca
NC		 9460 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
9461
dfc5f959 9462 if (r_type == R_ARM_XPC25)
252b5132 9463 {
dfc5f959
NC		 9464 /* Check for Arm calling Arm function. */
9465 /* FIXME: Should we translate the instruction into a BL
9466 instruction instead ? */
35fc36a8 9467 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 9468 (*_bfd_error_handler)
9469 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
9470 input_bfd,
9471 h ? h->root.root.string : "(local)");
dfc5f959 9472 }
155d87d7 9473 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 9474 {
9475 /* Check for Arm calling Thumb function. */
35fc36a8 9476 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 9477 {
f2a9dd69
DJ		 9478 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
9479 output_bfd, input_section,
9480 hit_data, sym_sec, rel->r_offset,
9481 signed_addend, value,
9482 error_message))
9483 return bfd_reloc_ok;
9484 else
9485 return bfd_reloc_dangerous;
dfc5f959 9486 }
252b5132 9487 }
ba96a88f 9488
906e58ca 9489 /* Check if a stub has to be inserted because the
8029a119 9490 destination is too far or we are changing mode. */
155d87d7
CL		 9491 if ( r_type == R_ARM_CALL
9492 || r_type == R_ARM_JUMP24
9493 || r_type == R_ARM_PLT32)
906e58ca 9494 {
fe33d2fa
CL		 9495 enum elf32_arm_stub_type stub_type = arm_stub_none;
9496 struct elf32_arm_link_hash_entry *hash;
9497
9498 hash = (struct elf32_arm_link_hash_entry *) h;
9499 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9500 st_type, &branch_type,
9501 hash, value, sym_sec,
fe33d2fa 9502 input_bfd, sym_name);
5fa9e92f 9503
fe33d2fa 9504 if (stub_type != arm_stub_none)
906e58ca
NC		 9505 {
9506 /* The target is out of reach, so redirect the
9507 branch to the local stub for this function. */
906e58ca
NC		 9508 stub_entry = elf32_arm_get_stub_entry (input_section,
9509 sym_sec, h,
fe33d2fa
CL		 9510 rel, globals,
9511 stub_type);
9cd3e4e5
NC		 9512 {
9513 if (stub_entry != NULL)
9514 value = (stub_entry->stub_offset
9515 + stub_entry->stub_sec->output_offset
9516 + stub_entry->stub_sec->output_section->vma);
9517
9518 if (plt_offset != (bfd_vma) -1)
9519 *unresolved_reloc_p = FALSE;
9520 }
906e58ca 9521 }
fe33d2fa
CL		 9522 else
9523 {
9524 /* If the call goes through a PLT entry, make sure to
9525 check distance to the right destination address. */
34e77a92 9526 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9527 {
9528 value = (splt->output_section->vma
9529 + splt->output_offset
34e77a92 9530 + plt_offset);
fe33d2fa
CL		 9531 *unresolved_reloc_p = FALSE;
9532 /* The PLT entry is in ARM mode, regardless of the
9533 target function. */
35fc36a8 9534 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9535 }
9536 }
906e58ca
NC		 9537 }
9538
dea514f5
PB		 9539 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9540 where:
9541 S is the address of the symbol in the relocation.
9542 P is address of the instruction being relocated.
9543 A is the addend (extracted from the instruction) in bytes.
9544
9545 S is held in 'value'.
9546 P is the base address of the section containing the
9547 instruction plus the offset of the reloc into that
9548 section, ie:
9549 (input_section->output_section->vma +
9550 input_section->output_offset +
9551 rel->r_offset).
9552 A is the addend, converted into bytes, ie:
9553 (signed_addend * 4)
9554
9555 Note: None of these operations have knowledge of the pipeline
9556 size of the processor, thus it is up to the assembler to
9557 encode this information into the addend. */
9558 value -= (input_section->output_section->vma
9559 + input_section->output_offset);
9560 value -= rel->r_offset;
4e7fd91e
PB		 9561 if (globals->use_rel)
9562 value += (signed_addend << howto->size);
9563 else
9564 /* RELA addends do not have to be adjusted by howto->size. */
9565 value += signed_addend;
23080146 9566
dcb5e6e6
NC		 9567 signed_addend = value;
9568 signed_addend >>= howto->rightshift;
9a5aca8c 9569
5ab79981 9570 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 9571 the next instruction unless a PLT entry will be created.
77b4f08f 9572 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 9573 The jump to the next instruction is optimized as a NOP depending
9574 on the architecture. */
ffcb4889 9575 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 9576 && plt_offset == (bfd_vma) -1)
77b4f08f 9577 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 9578 {
cd1dac3d
DG		 9579 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
9580
9581 if (arch_has_arm_nop (globals))
9582 value |= 0x0320f000;
9583 else
9584 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 9585 }
9586 else
59f2c4e7 9587 {
9b485d32 9588 /* Perform a signed range check. */
dcb5e6e6 9589 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 9590 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
9591 return bfd_reloc_overflow;
9a5aca8c 9592
5ab79981 9593 addend = (value & 2);
39b41c9c 9594
5ab79981
PB		 9595 value = (signed_addend & howto->dst_mask)
9596 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 9597
5ab79981
PB		 9598 if (r_type == R_ARM_CALL)
9599 {
155d87d7 9600 /* Set the H bit in the BLX instruction. */
35fc36a8 9601 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 9602 {
9603 if (addend)
9604 value |= (1 << 24);
9605 else
9606 value &= ~(bfd_vma)(1 << 24);
9607 }
9608
5ab79981 9609 /* Select the correct instruction (BL or BLX). */
906e58ca 9610 /* Only if we are not handling a BL to a stub. In this
8029a119 9611 case, mode switching is performed by the stub. */
35fc36a8 9612 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 9613 value |= (1 << 28);
63e1a0fc 9614 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 9615 {
9616 value &= ~(bfd_vma)(1 << 28);
9617 value |= (1 << 24);
9618 }
39b41c9c
PB		 9619 }
9620 }
906e58ca 9621 }
252b5132 9622 break;
f21f3fe0 9623
252b5132
RH		 9624 case R_ARM_ABS32:
9625 value += addend;
35fc36a8 9626 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 9627 value |= 1;
9628 break;
f21f3fe0 9629
bb224fc3
MS		 9630 case R_ARM_ABS32_NOI:
9631 value += addend;
9632 break;
9633
252b5132 9634 case R_ARM_REL32:
a8bc6c78 9635 value += addend;
35fc36a8 9636 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 9637 value |= 1;
252b5132 9638 value -= (input_section->output_section->vma
62efb346 9639 + input_section->output_offset + rel->r_offset);
252b5132 9640 break;
eb043451 9641
bb224fc3
MS		 9642 case R_ARM_REL32_NOI:
9643 value += addend;
9644 value -= (input_section->output_section->vma
9645 + input_section->output_offset + rel->r_offset);
9646 break;
9647
eb043451
PB		 9648 case R_ARM_PREL31:
9649 value -= (input_section->output_section->vma
9650 + input_section->output_offset + rel->r_offset);
9651 value += signed_addend;
9652 if (! h || h->root.type != bfd_link_hash_undefweak)
9653 {
8029a119 9654 /* Check for overflow. */
eb043451
PB		 9655 if ((value ^ (value >> 1)) & (1 << 30))
9656 return bfd_reloc_overflow;
9657 }
9658 value &= 0x7fffffff;
9659 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 9660 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 9661 value |= 1;
9662 break;
252b5132 9663 }
f21f3fe0 9664
252b5132
RH		 9665 bfd_put_32 (input_bfd, value, hit_data);
9666 return bfd_reloc_ok;
9667
9668 case R_ARM_ABS8:
fd0fd00c
MJ		 9669 /* PR 16202: Refectch the addend using the correct size. */
9670 if (globals->use_rel)
9671 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 9672 value += addend;
4e67d4ca
DG		 9673
9674 /* There is no way to tell whether the user intended to use a signed or
9675 unsigned addend. When checking for overflow we accept either,
9676 as specified by the AAELF. */
9677 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 9678 return bfd_reloc_overflow;
9679
9680 bfd_put_8 (input_bfd, value, hit_data);
9681 return bfd_reloc_ok;
9682
9683 case R_ARM_ABS16:
fd0fd00c
MJ		 9684 /* PR 16202: Refectch the addend using the correct size. */
9685 if (globals->use_rel)
9686 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 9687 value += addend;
9688
4e67d4ca
DG		 9689 /* See comment for R_ARM_ABS8. */
9690 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 9691 return bfd_reloc_overflow;
9692
9693 bfd_put_16 (input_bfd, value, hit_data);
9694 return bfd_reloc_ok;
9695
252b5132 9696 case R_ARM_THM_ABS5:
9b485d32 9697 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 9698 if (globals->use_rel)
9699 {
9700 /* Need to refetch addend. */
9701 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9702 /* ??? Need to determine shift amount from operand size. */
9703 addend >>= howto->rightshift;
9704 }
252b5132
RH		 9705 value += addend;
9706
9707 /* ??? Isn't value unsigned? */
9708 if ((long) value > 0x1f || (long) value < -0x10)
9709 return bfd_reloc_overflow;
9710
9711 /* ??? Value needs to be properly shifted into place first. */
9712 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
9713 bfd_put_16 (input_bfd, value, hit_data);
9714 return bfd_reloc_ok;
9715
2cab6cc3
MS		 9716 case R_ARM_THM_ALU_PREL_11_0:
9717 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
9718 {
9719 bfd_vma insn;
9720 bfd_signed_vma relocation;
9721
9722 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9723 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9724
99059e56
RM		 9725 if (globals->use_rel)
9726 {
9727 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
9728 | ((insn & (1 << 26)) >> 15);
9729 if (insn & 0xf00000)
9730 signed_addend = -signed_addend;
9731 }
2cab6cc3
MS		 9732
9733 relocation = value + signed_addend;
79f08007 9734 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9735 + input_section->output_offset
9736 + rel->r_offset);
2cab6cc3 9737
b6518b38 9738 value = relocation;
2cab6cc3 9739
99059e56
RM		 9740 if (value >= 0x1000)
9741 return bfd_reloc_overflow;
2cab6cc3
MS		 9742
9743 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 9744 | ((value & 0x700) << 4)
9745 | ((value & 0x800) << 15);
9746 if (relocation < 0)
9747 insn |= 0xa00000;
2cab6cc3
MS		 9748
9749 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9750 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9751
99059e56 9752 return bfd_reloc_ok;
2cab6cc3
MS		 9753 }
9754
e1ec24c6
NC		 9755 case R_ARM_THM_PC8:
9756 /* PR 10073: This reloc is not generated by the GNU toolchain,
9757 but it is supported for compatibility with third party libraries
9758 generated by other compilers, specifically the ARM/IAR. */
9759 {
9760 bfd_vma insn;
9761 bfd_signed_vma relocation;
9762
9763 insn = bfd_get_16 (input_bfd, hit_data);
9764
99059e56 9765 if (globals->use_rel)
79f08007 9766 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 9767
9768 relocation = value + addend;
79f08007 9769 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9770 + input_section->output_offset
9771 + rel->r_offset);
e1ec24c6 9772
b6518b38 9773 value = relocation;
e1ec24c6
NC		 9774
9775 /* We do not check for overflow of this reloc. Although strictly
9776 speaking this is incorrect, it appears to be necessary in order
9777 to work with IAR generated relocs. Since GCC and GAS do not
9778 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
9779 a problem for them. */
9780 value &= 0x3fc;
9781
9782 insn = (insn & 0xff00) | (value >> 2);
9783
9784 bfd_put_16 (input_bfd, insn, hit_data);
9785
99059e56 9786 return bfd_reloc_ok;
e1ec24c6
NC		 9787 }
9788
2cab6cc3
MS		 9789 case R_ARM_THM_PC12:
9790 /* Corresponds to: ldr.w reg, [pc, #offset]. */
9791 {
9792 bfd_vma insn;
9793 bfd_signed_vma relocation;
9794
9795 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9796 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9797
99059e56
RM		 9798 if (globals->use_rel)
9799 {
9800 signed_addend = insn & 0xfff;
9801 if (!(insn & (1 << 23)))
9802 signed_addend = -signed_addend;
9803 }
2cab6cc3
MS		 9804
9805 relocation = value + signed_addend;
79f08007 9806 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9807 + input_section->output_offset
9808 + rel->r_offset);
2cab6cc3 9809
b6518b38 9810 value = relocation;
2cab6cc3 9811
99059e56
RM		 9812 if (value >= 0x1000)
9813 return bfd_reloc_overflow;
2cab6cc3
MS		 9814
9815 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 9816 if (relocation >= 0)
9817 insn |= (1 << 23);
2cab6cc3
MS		 9818
9819 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9820 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9821
99059e56 9822 return bfd_reloc_ok;
2cab6cc3
MS		 9823 }
9824
dfc5f959 9825 case R_ARM_THM_XPC22:
c19d1205 9826 case R_ARM_THM_CALL:
bd97cb95 9827 case R_ARM_THM_JUMP24:
dfc5f959 9828 /* Thumb BL (branch long instruction). */
252b5132 9829 {
b34976b6 9830 bfd_vma relocation;
99059e56 9831 bfd_vma reloc_sign;
b34976b6
AM		 9832 bfd_boolean overflow = FALSE;
9833 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9834 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 9835 bfd_signed_vma reloc_signed_max;
9836 bfd_signed_vma reloc_signed_min;
b34976b6 9837 bfd_vma check;
252b5132 9838 bfd_signed_vma signed_check;
e95de063 9839 int bitsize;
cd1dac3d 9840 const int thumb2 = using_thumb2 (globals);
252b5132 9841
5ab79981 9842 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 9843 the next instruction unless a PLT entry will be created.
9844 The jump to the next instruction is optimized as a NOP.W for
9845 Thumb-2 enabled architectures. */
19540007 9846 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 9847 && plt_offset == (bfd_vma) -1)
5ab79981 9848 {
60a019a0 9849 if (thumb2)
cd1dac3d
DG		 9850 {
9851 bfd_put_16 (input_bfd, 0xf3af, hit_data);
9852 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
9853 }
9854 else
9855 {
9856 bfd_put_16 (input_bfd, 0xe000, hit_data);
9857 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
9858 }
5ab79981
PB		 9859 return bfd_reloc_ok;
9860 }
9861
e95de063 9862 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 9863 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 9864 if (globals->use_rel)
9865 {
99059e56
RM		 9866 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
9867 bfd_vma upper = upper_insn & 0x3ff;
9868 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 9869 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
9870 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 9871 bfd_vma i1 = j1 ^ s ? 0 : 1;
9872 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 9873
99059e56
RM		 9874 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
9875 /* Sign extend. */
9876 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 9877
4e7fd91e
PB		 9878 signed_addend = addend;
9879 }
cb1afa5c 9880
dfc5f959
NC		 9881 if (r_type == R_ARM_THM_XPC22)
9882 {
9883 /* Check for Thumb to Thumb call. */
9884 /* FIXME: Should we translate the instruction into a BL
9885 instruction instead ? */
35fc36a8 9886 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 9887 (*_bfd_error_handler)
9888 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
9889 input_bfd,
9890 h ? h->root.root.string : "(local)");
dfc5f959
NC		 9891 }
9892 else
252b5132 9893 {
dfc5f959
NC		 9894 /* If it is not a call to Thumb, assume call to Arm.
9895 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 9896 function call at all, but rather a long jump. Calls through
9897 the PLT do not require stubs. */
34e77a92 9898 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 9899 {
bd97cb95 9900 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9901 {
9902 /* Convert BL to BLX. */
9903 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9904 }
155d87d7
CL		 9905 else if (( r_type != R_ARM_THM_CALL)
9906 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 9907 {
9908 if (elf32_thumb_to_arm_stub
9909 (info, sym_name, input_bfd, output_bfd, input_section,
9910 hit_data, sym_sec, rel->r_offset, signed_addend, value,
9911 error_message))
9912 return bfd_reloc_ok;
9913 else
9914 return bfd_reloc_dangerous;
9915 }
da5938a2 9916 }
35fc36a8
RS		 9917 else if (branch_type == ST_BRANCH_TO_THUMB
9918 && globals->use_blx
bd97cb95 9919 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9920 {
9921 /* Make sure this is a BL. */
9922 lower_insn |= 0x1800;
9923 }
252b5132 9924 }
f21f3fe0 9925
fe33d2fa 9926 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 9927 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 9928 {
9929 /* Check if a stub has to be inserted because the destination
8029a119 9930 is too far. */
fe33d2fa
CL		 9931 struct elf32_arm_stub_hash_entry *stub_entry;
9932 struct elf32_arm_link_hash_entry *hash;
9933
9934 hash = (struct elf32_arm_link_hash_entry *) h;
9935
9936 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9937 st_type, &branch_type,
9938 hash, value, sym_sec,
fe33d2fa
CL		 9939 input_bfd, sym_name);
9940
9941 if (stub_type != arm_stub_none)
906e58ca
NC		 9942 {
9943 /* The target is out of reach or we are changing modes, so
9944 redirect the branch to the local stub for this
9945 function. */
9946 stub_entry = elf32_arm_get_stub_entry (input_section,
9947 sym_sec, h,
fe33d2fa
CL		 9948 rel, globals,
9949 stub_type);
906e58ca 9950 if (stub_entry != NULL)
9cd3e4e5
NC		 9951 {
9952 value = (stub_entry->stub_offset
9953 + stub_entry->stub_sec->output_offset
9954 + stub_entry->stub_sec->output_section->vma);
9955
9956 if (plt_offset != (bfd_vma) -1)
9957 *unresolved_reloc_p = FALSE;
9958 }
906e58ca 9959
f4ac8484 9960 /* If this call becomes a call to Arm, force BLX. */
155d87d7 9961 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 9962 {
9963 if ((stub_entry
9964 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 9965 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 9966 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9967 }
906e58ca
NC		 9968 }
9969 }
9970
fe33d2fa 9971 /* Handle calls via the PLT. */
34e77a92 9972 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9973 {
9974 value = (splt->output_section->vma
9975 + splt->output_offset
34e77a92 9976 + plt_offset);
fe33d2fa 9977
eed94f8f
NC		 9978 if (globals->use_blx
9979 && r_type == R_ARM_THM_CALL
9980 && ! using_thumb_only (globals))
fe33d2fa
CL		 9981 {
9982 /* If the Thumb BLX instruction is available, convert
9983 the BL to a BLX instruction to call the ARM-mode
9984 PLT entry. */
9985 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 9986 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9987 }
9988 else
9989 {
eed94f8f
NC		 9990 if (! using_thumb_only (globals))
9991 /* Target the Thumb stub before the ARM PLT entry. */
9992 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 9993 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 9994 }
9995 *unresolved_reloc_p = FALSE;
9996 }
9997
ba96a88f 9998 relocation = value + signed_addend;
f21f3fe0 9999
252b5132 10000 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10001 + input_section->output_offset
10002 + rel->r_offset);
9a5aca8c 10003
252b5132
RH		 10004 check = relocation >> howto->rightshift;
10005
10006 /* If this is a signed value, the rightshift just dropped
10007 leading 1 bits (assuming twos complement). */
10008 if ((bfd_signed_vma) relocation >= 0)
10009 signed_check = check;
10010 else
10011 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10012
e95de063
MS		 10013 /* Calculate the permissable maximum and minimum values for
10014 this relocation according to whether we're relocating for
10015 Thumb-2 or not. */
10016 bitsize = howto->bitsize;
10017 if (!thumb2)
10018 bitsize -= 2;
f6ebfac0 10019 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10020 reloc_signed_min = ~reloc_signed_max;
10021
252b5132 10022 /* Assumes two's complement. */
ba96a88f 10023 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10024 overflow = TRUE;
252b5132 10025
bd97cb95 10026 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10027 /* For a BLX instruction, make sure that the relocation is rounded up
10028 to a word boundary. This follows the semantics of the instruction
10029 which specifies that bit 1 of the target address will come from bit
10030 1 of the base address. */
10031 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10032
e95de063
MS		 10033 /* Put RELOCATION back into the insn. Assumes two's complement.
10034 We use the Thumb-2 encoding, which is safe even if dealing with
10035 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10036 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10037 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10038 | ((relocation >> 12) & 0x3ff)
10039 | (reloc_sign << 10);
906e58ca 10040 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10041 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10042 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10043 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10044
252b5132
RH		 10045 /* Put the relocated value back in the object file: */
10046 bfd_put_16 (input_bfd, upper_insn, hit_data);
10047 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10048
10049 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10050 }
10051 break;
10052
c19d1205
ZW		 10053 case R_ARM_THM_JUMP19:
10054 /* Thumb32 conditional branch instruction. */
10055 {
10056 bfd_vma relocation;
10057 bfd_boolean overflow = FALSE;
10058 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10059 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10060 bfd_signed_vma reloc_signed_max = 0xffffe;
10061 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10062 bfd_signed_vma signed_check;
c5423981
TG		 10063 enum elf32_arm_stub_type stub_type = arm_stub_none;
10064 struct elf32_arm_stub_hash_entry *stub_entry;
10065 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10066
10067 /* Need to refetch the addend, reconstruct the top three bits,
10068 and squish the two 11 bit pieces together. */
10069 if (globals->use_rel)
10070 {
10071 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10072 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10073 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10074 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10075 bfd_vma lower = (lower_insn & 0x07ff);
10076
a00a1f35
MS		 10077 upper |= J1 << 6;
10078 upper |= J2 << 7;
10079 upper |= (!S) << 8;
c19d1205
ZW		 10080 upper -= 0x0100; /* Sign extend. */
10081
10082 addend = (upper << 12) | (lower << 1);
10083 signed_addend = addend;
10084 }
10085
bd97cb95 10086 /* Handle calls via the PLT. */
34e77a92 10087 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10088 {
10089 value = (splt->output_section->vma
10090 + splt->output_offset
34e77a92 10091 + plt_offset);
bd97cb95
DJ		 10092 /* Target the Thumb stub before the ARM PLT entry. */
10093 value -= PLT_THUMB_STUB_SIZE;
10094 *unresolved_reloc_p = FALSE;
10095 }
10096
c5423981
TG		 10097 hash = (struct elf32_arm_link_hash_entry *)h;
10098
10099 stub_type = arm_type_of_stub (info, input_section, rel,
10100 st_type, &branch_type,
10101 hash, value, sym_sec,
10102 input_bfd, sym_name);
10103 if (stub_type != arm_stub_none)
10104 {
10105 stub_entry = elf32_arm_get_stub_entry (input_section,
10106 sym_sec, h,
10107 rel, globals,
10108 stub_type);
10109 if (stub_entry != NULL)
10110 {
10111 value = (stub_entry->stub_offset
10112 + stub_entry->stub_sec->output_offset
10113 + stub_entry->stub_sec->output_section->vma);
10114 }
10115 }
c19d1205 10116
99059e56 10117 relocation = value + signed_addend;
c19d1205
ZW		 10118 relocation -= (input_section->output_section->vma
10119 + input_section->output_offset
10120 + rel->r_offset);
a00a1f35 10121 signed_check = (bfd_signed_vma) relocation;
c19d1205 10122
c19d1205
ZW		 10123 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10124 overflow = TRUE;
10125
10126 /* Put RELOCATION back into the insn. */
10127 {
10128 bfd_vma S = (relocation & 0x00100000) >> 20;
10129 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10130 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10131 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10132 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10133
a00a1f35 10134 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10135 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10136 }
10137
10138 /* Put the relocated value back in the object file: */
10139 bfd_put_16 (input_bfd, upper_insn, hit_data);
10140 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10141
10142 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10143 }
10144
10145 case R_ARM_THM_JUMP11:
10146 case R_ARM_THM_JUMP8:
10147 case R_ARM_THM_JUMP6:
51c5503b
NC		 10148 /* Thumb B (branch) instruction). */
10149 {
6cf9e9fe 10150 bfd_signed_vma relocation;
51c5503b
NC		 10151 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10152 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10153 bfd_signed_vma signed_check;
10154
c19d1205
ZW		 10155 /* CZB cannot jump backward. */
10156 if (r_type == R_ARM_THM_JUMP6)
10157 reloc_signed_min = 0;
10158
4e7fd91e 10159 if (globals->use_rel)
6cf9e9fe 10160 {
4e7fd91e
PB		 10161 /* Need to refetch addend. */
10162 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10163 if (addend & ((howto->src_mask + 1) >> 1))
10164 {
10165 signed_addend = -1;
10166 signed_addend &= ~ howto->src_mask;
10167 signed_addend |= addend;
10168 }
10169 else
10170 signed_addend = addend;
10171 /* The value in the insn has been right shifted. We need to
10172 undo this, so that we can perform the address calculation
10173 in terms of bytes. */
10174 signed_addend <<= howto->rightshift;
6cf9e9fe 10175 }
6cf9e9fe 10176 relocation = value + signed_addend;
51c5503b
NC		 10177
10178 relocation -= (input_section->output_section->vma
10179 + input_section->output_offset
10180 + rel->r_offset);
10181
6cf9e9fe
NC		 10182 relocation >>= howto->rightshift;
10183 signed_check = relocation;
c19d1205
ZW		 10184
10185 if (r_type == R_ARM_THM_JUMP6)
10186 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10187 else
10188 relocation &= howto->dst_mask;
51c5503b 10189 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10190
51c5503b
NC		 10191 bfd_put_16 (input_bfd, relocation, hit_data);
10192
10193 /* Assumes two's complement. */
10194 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10195 return bfd_reloc_overflow;
10196
10197 return bfd_reloc_ok;
10198 }
cedb70c5 10199
8375c36b
PB		 10200 case R_ARM_ALU_PCREL7_0:
10201 case R_ARM_ALU_PCREL15_8:
10202 case R_ARM_ALU_PCREL23_15:
10203 {
10204 bfd_vma insn;
10205 bfd_vma relocation;
10206
10207 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10208 if (globals->use_rel)
10209 {
10210 /* Extract the addend. */
10211 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10212 signed_addend = addend;
10213 }
8375c36b
PB		 10214 relocation = value + signed_addend;
10215
10216 relocation -= (input_section->output_section->vma
10217 + input_section->output_offset
10218 + rel->r_offset);
10219 insn = (insn & ~0xfff)
10220 | ((howto->bitpos << 7) & 0xf00)
10221 | ((relocation >> howto->bitpos) & 0xff);
10222 bfd_put_32 (input_bfd, value, hit_data);
10223 }
10224 return bfd_reloc_ok;
10225
252b5132
RH		 10226 case R_ARM_GNU_VTINHERIT:
10227 case R_ARM_GNU_VTENTRY:
10228 return bfd_reloc_ok;
10229
c19d1205 10230 case R_ARM_GOTOFF32:
252b5132 10231 /* Relocation is relative to the start of the
99059e56 10232 global offset table. */
252b5132
RH		 10233
10234 BFD_ASSERT (sgot != NULL);
10235 if (sgot == NULL)
99059e56 10236 return bfd_reloc_notsupported;
9a5aca8c 10237
cedb70c5 10238 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 10239 address by one, so that attempts to call the function pointer will
10240 correctly interpret it as Thumb code. */
35fc36a8 10241 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 10242 value += 1;
10243
252b5132 10244 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 10245 calculation. We always want the start of .got. If we
10246 define _GLOBAL_OFFSET_TABLE in a different way, as is
10247 permitted by the ABI, we might have to change this
10248 calculation. */
252b5132 10249 value -= sgot->output_section->vma;
f21f3fe0 10250 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10251 contents, rel->r_offset, value,
00a97672 10252 rel->r_addend);
252b5132
RH		 10253
10254 case R_ARM_GOTPC:
a7c10850 10255 /* Use global offset table as symbol value. */
252b5132 10256 BFD_ASSERT (sgot != NULL);
f21f3fe0 10257
252b5132 10258 if (sgot == NULL)
99059e56 10259 return bfd_reloc_notsupported;
252b5132 10260
0945cdfd 10261 *unresolved_reloc_p = FALSE;
252b5132 10262 value = sgot->output_section->vma;
f21f3fe0 10263 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10264 contents, rel->r_offset, value,
00a97672 10265 rel->r_addend);
f21f3fe0 10266
252b5132 10267 case R_ARM_GOT32:
eb043451 10268 case R_ARM_GOT_PREL:
252b5132 10269 /* Relocation is to the entry for this symbol in the
99059e56 10270 global offset table. */
252b5132
RH		 10271 if (sgot == NULL)
10272 return bfd_reloc_notsupported;
f21f3fe0 10273
34e77a92
RS		 10274 if (dynreloc_st_type == STT_GNU_IFUNC
10275 && plt_offset != (bfd_vma) -1
10276 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
10277 {
10278 /* We have a relocation against a locally-binding STT_GNU_IFUNC
10279 symbol, and the relocation resolves directly to the runtime
10280 target rather than to the .iplt entry. This means that any
10281 .got entry would be the same value as the .igot.plt entry,
10282 so there's no point creating both. */
10283 sgot = globals->root.igotplt;
10284 value = sgot->output_offset + gotplt_offset;
10285 }
10286 else if (h != NULL)
252b5132
RH		 10287 {
10288 bfd_vma off;
f21f3fe0 10289
252b5132
RH		 10290 off = h->got.offset;
10291 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 10292 if ((off & 1) != 0)
252b5132 10293 {
b436d854
RS		 10294 /* We have already processsed one GOT relocation against
10295 this symbol. */
10296 off &= ~1;
10297 if (globals->root.dynamic_sections_created
10298 && !SYMBOL_REFERENCES_LOCAL (info, h))
10299 *unresolved_reloc_p = FALSE;
10300 }
10301 else
10302 {
10303 Elf_Internal_Rela outrel;
10304
6f820c85 10305 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 10306 {
10307 /* If the symbol doesn't resolve locally in a static
10308 object, we have an undefined reference. If the
10309 symbol doesn't resolve locally in a dynamic object,
10310 it should be resolved by the dynamic linker. */
10311 if (globals->root.dynamic_sections_created)
10312 {
10313 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
10314 *unresolved_reloc_p = FALSE;
10315 }
10316 else
10317 outrel.r_info = 0;
10318 outrel.r_addend = 0;
10319 }
252b5132
RH		 10320 else
10321 {
34e77a92 10322 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10323 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 10324 else if (bfd_link_pic (info) &&
31943882
WN		 10325 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10326 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 10327 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
10328 else
10329 outrel.r_info = 0;
34e77a92 10330 outrel.r_addend = dynreloc_value;
b436d854 10331 }
ee29b9fb 10332
b436d854
RS		 10333 /* The GOT entry is initialized to zero by default.
10334 See if we should install a different value. */
10335 if (outrel.r_addend != 0
10336 && (outrel.r_info == 0 || globals->use_rel))
10337 {
10338 bfd_put_32 (output_bfd, outrel.r_addend,
10339 sgot->contents + off);
10340 outrel.r_addend = 0;
252b5132 10341 }
f21f3fe0 10342
b436d854
RS		 10343 if (outrel.r_info != 0)
10344 {
10345 outrel.r_offset = (sgot->output_section->vma
10346 + sgot->output_offset
10347 + off);
10348 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
10349 }
10350 h->got.offset |= 1;
10351 }
252b5132
RH		 10352 value = sgot->output_offset + off;
10353 }
10354 else
10355 {
10356 bfd_vma off;
f21f3fe0 10357
252b5132
RH		 10358 BFD_ASSERT (local_got_offsets != NULL &&
10359 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 10360
252b5132 10361 off = local_got_offsets[r_symndx];
f21f3fe0 10362
252b5132
RH		 10363 /* The offset must always be a multiple of 4. We use the
10364 least significant bit to record whether we have already
9b485d32 10365 generated the necessary reloc. */
252b5132
RH		 10366 if ((off & 1) != 0)
10367 off &= ~1;
10368 else
10369 {
00a97672 10370 if (globals->use_rel)
34e77a92 10371 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 10372
0e1862bb 10373 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 10374 {
947216bf 10375 Elf_Internal_Rela outrel;
f21f3fe0 10376
34e77a92 10377 outrel.r_addend = addend + dynreloc_value;
252b5132 10378 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 10379 + sgot->output_offset
252b5132 10380 + off);
34e77a92 10381 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10382 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 10383 else
10384 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 10385 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 10386 }
f21f3fe0 10387
252b5132
RH		 10388 local_got_offsets[r_symndx] |= 1;
10389 }
f21f3fe0 10390
252b5132
RH		 10391 value = sgot->output_offset + off;
10392 }
eb043451
PB		 10393 if (r_type != R_ARM_GOT32)
10394 value += sgot->output_section->vma;
9a5aca8c 10395
f21f3fe0 10396 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10397 contents, rel->r_offset, value,
00a97672 10398 rel->r_addend);
f21f3fe0 10399
ba93b8ac
DJ		 10400 case R_ARM_TLS_LDO32:
10401 value = value - dtpoff_base (info);
10402
10403 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10404 contents, rel->r_offset, value,
10405 rel->r_addend);
ba93b8ac
DJ		 10406
10407 case R_ARM_TLS_LDM32:
10408 {
10409 bfd_vma off;
10410
362d30a1 10411 if (sgot == NULL)
ba93b8ac
DJ		 10412 abort ();
10413
10414 off = globals->tls_ldm_got.offset;
10415
10416 if ((off & 1) != 0)
10417 off &= ~1;
10418 else
10419 {
10420 /* If we don't know the module number, create a relocation
10421 for it. */
0e1862bb 10422 if (bfd_link_pic (info))
ba93b8ac
DJ		 10423 {
10424 Elf_Internal_Rela outrel;
ba93b8ac 10425
362d30a1 10426 if (srelgot == NULL)
ba93b8ac
DJ		 10427 abort ();
10428
00a97672 10429 outrel.r_addend = 0;
362d30a1
RS		 10430 outrel.r_offset = (sgot->output_section->vma
10431 + sgot->output_offset + off);
ba93b8ac
DJ		 10432 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
10433
00a97672
RS		 10434 if (globals->use_rel)
10435 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10436 sgot->contents + off);
ba93b8ac 10437
47beaa6a 10438 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10439 }
10440 else
362d30a1 10441 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 10442
10443 globals->tls_ldm_got.offset |= 1;
10444 }
10445
362d30a1 10446 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 10447 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
10448
10449 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10450 contents, rel->r_offset, value,
00a97672 10451 rel->r_addend);
ba93b8ac
DJ		 10452 }
10453
0855e32b
NS		 10454 case R_ARM_TLS_CALL:
10455 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 10456 case R_ARM_TLS_GD32:
10457 case R_ARM_TLS_IE32:
0855e32b
NS		 10458 case R_ARM_TLS_GOTDESC:
10459 case R_ARM_TLS_DESCSEQ:
10460 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 10461 {
0855e32b
NS		 10462 bfd_vma off, offplt;
10463 int indx = 0;
ba93b8ac
DJ		 10464 char tls_type;
10465
0855e32b 10466 BFD_ASSERT (sgot != NULL);
ba93b8ac 10467
ba93b8ac
DJ		 10468 if (h != NULL)
10469 {
10470 bfd_boolean dyn;
10471 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 10472 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
10473 bfd_link_pic (info),
10474 h)
10475 && (!bfd_link_pic (info)
ba93b8ac
DJ		 10476 || !SYMBOL_REFERENCES_LOCAL (info, h)))
10477 {
10478 *unresolved_reloc_p = FALSE;
10479 indx = h->dynindx;
10480 }
10481 off = h->got.offset;
0855e32b 10482 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 10483 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
10484 }
10485 else
10486 {
0855e32b 10487 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 10488 off = local_got_offsets[r_symndx];
0855e32b 10489 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 10490 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
10491 }
10492
0855e32b 10493 /* Linker relaxations happens from one of the
b38cadfb 10494 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 10495 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 10496 tls_type = GOT_TLS_IE;
0855e32b
NS		 10497
10498 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 10499
10500 if ((off & 1) != 0)
10501 off &= ~1;
10502 else
10503 {
10504 bfd_boolean need_relocs = FALSE;
10505 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 10506 int cur_off = off;
10507
10508 /* The GOT entries have not been initialized yet. Do it
10509 now, and emit any relocations. If both an IE GOT and a
10510 GD GOT are necessary, we emit the GD first. */
10511
0e1862bb 10512 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 10513 && (h == NULL
10514 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10515 || h->root.type != bfd_link_hash_undefweak))
10516 {
10517 need_relocs = TRUE;
0855e32b 10518 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 10519 }
10520
0855e32b
NS		 10521 if (tls_type & GOT_TLS_GDESC)
10522 {
47beaa6a
RS		 10523 bfd_byte *loc;
10524
0855e32b
NS		 10525 /* We should have relaxed, unless this is an undefined
10526 weak symbol. */
10527 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 10528 || bfd_link_pic (info));
0855e32b 10529 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 10530 <= globals->root.sgotplt->size);
0855e32b
NS		 10531
10532 outrel.r_addend = 0;
10533 outrel.r_offset = (globals->root.sgotplt->output_section->vma
10534 + globals->root.sgotplt->output_offset
10535 + offplt
10536 + globals->sgotplt_jump_table_size);
b38cadfb 10537
0855e32b
NS		 10538 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
10539 sreloc = globals->root.srelplt;
10540 loc = sreloc->contents;
10541 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
10542 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 10543 <= sreloc->contents + sreloc->size);
0855e32b
NS		 10544
10545 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
10546
10547 /* For globals, the first word in the relocation gets
10548 the relocation index and the top bit set, or zero,
10549 if we're binding now. For locals, it gets the
10550 symbol's offset in the tls section. */
99059e56 10551 bfd_put_32 (output_bfd,
0855e32b
NS		 10552 !h ? value - elf_hash_table (info)->tls_sec->vma
10553 : info->flags & DF_BIND_NOW ? 0
10554 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 10555 globals->root.sgotplt->contents + offplt
10556 + globals->sgotplt_jump_table_size);
10557
0855e32b 10558 /* Second word in the relocation is always zero. */
99059e56 10559 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 10560 globals->root.sgotplt->contents + offplt
10561 + globals->sgotplt_jump_table_size + 4);
0855e32b 10562 }
ba93b8ac
DJ		 10563 if (tls_type & GOT_TLS_GD)
10564 {
10565 if (need_relocs)
10566 {
00a97672 10567 outrel.r_addend = 0;
362d30a1
RS		 10568 outrel.r_offset = (sgot->output_section->vma
10569 + sgot->output_offset
00a97672 10570 + cur_off);
ba93b8ac 10571 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 10572
00a97672
RS		 10573 if (globals->use_rel)
10574 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10575 sgot->contents + cur_off);
00a97672 10576
47beaa6a 10577 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10578
10579 if (indx == 0)
10580 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10581 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10582 else
10583 {
00a97672 10584 outrel.r_addend = 0;
ba93b8ac
DJ		 10585 outrel.r_info = ELF32_R_INFO (indx,
10586 R_ARM_TLS_DTPOFF32);
10587 outrel.r_offset += 4;
00a97672
RS		 10588
10589 if (globals->use_rel)
10590 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10591 sgot->contents + cur_off + 4);
00a97672 10592
47beaa6a
RS		 10593 elf32_arm_add_dynreloc (output_bfd, info,
10594 srelgot, &outrel);
ba93b8ac
DJ		 10595 }
10596 }
10597 else
10598 {
10599 /* If we are not emitting relocations for a
10600 general dynamic reference, then we must be in a
10601 static link or an executable link with the
10602 symbol binding locally. Mark it as belonging
10603 to module 1, the executable. */
10604 bfd_put_32 (output_bfd, 1,
362d30a1 10605 sgot->contents + cur_off);
ba93b8ac 10606 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10607 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10608 }
10609
10610 cur_off += 8;
10611 }
10612
10613 if (tls_type & GOT_TLS_IE)
10614 {
10615 if (need_relocs)
10616 {
00a97672
RS		 10617 if (indx == 0)
10618 outrel.r_addend = value - dtpoff_base (info);
10619 else
10620 outrel.r_addend = 0;
362d30a1
RS		 10621 outrel.r_offset = (sgot->output_section->vma
10622 + sgot->output_offset
ba93b8ac
DJ		 10623 + cur_off);
10624 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
10625
00a97672
RS		 10626 if (globals->use_rel)
10627 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10628 sgot->contents + cur_off);
ba93b8ac 10629
47beaa6a 10630 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10631 }
10632 else
10633 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 10634 sgot->contents + cur_off);
ba93b8ac
DJ		 10635 cur_off += 4;
10636 }
10637
10638 if (h != NULL)
10639 h->got.offset |= 1;
10640 else
10641 local_got_offsets[r_symndx] |= 1;
10642 }
10643
10644 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
10645 off += 8;
0855e32b
NS		 10646 else if (tls_type & GOT_TLS_GDESC)
10647 off = offplt;
10648
10649 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
10650 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
10651 {
10652 bfd_signed_vma offset;
12352d3f
PB		 10653 /* TLS stubs are arm mode. The original symbol is a
10654 data object, so branch_type is bogus. */
10655 branch_type = ST_BRANCH_TO_ARM;
0855e32b 10656 enum elf32_arm_stub_type stub_type
34e77a92
RS		 10657 = arm_type_of_stub (info, input_section, rel,
10658 st_type, &branch_type,
0855e32b
NS		 10659 (struct elf32_arm_link_hash_entry *)h,
10660 globals->tls_trampoline, globals->root.splt,
10661 input_bfd, sym_name);
10662
10663 if (stub_type != arm_stub_none)
10664 {
10665 struct elf32_arm_stub_hash_entry *stub_entry
10666 = elf32_arm_get_stub_entry
10667 (input_section, globals->root.splt, 0, rel,
10668 globals, stub_type);
10669 offset = (stub_entry->stub_offset
10670 + stub_entry->stub_sec->output_offset
10671 + stub_entry->stub_sec->output_section->vma);
10672 }
10673 else
10674 offset = (globals->root.splt->output_section->vma
10675 + globals->root.splt->output_offset
10676 + globals->tls_trampoline);
10677
10678 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
10679 {
10680 unsigned long inst;
b38cadfb
NC		 10681
10682 offset -= (input_section->output_section->vma
10683 + input_section->output_offset
10684 + rel->r_offset + 8);
0855e32b
NS		 10685
10686 inst = offset >> 2;
10687 inst &= 0x00ffffff;
10688 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
10689 }
10690 else
10691 {
10692 /* Thumb blx encodes the offset in a complicated
10693 fashion. */
10694 unsigned upper_insn, lower_insn;
10695 unsigned neg;
10696
b38cadfb
NC		 10697 offset -= (input_section->output_section->vma
10698 + input_section->output_offset
0855e32b 10699 + rel->r_offset + 4);
b38cadfb 10700
12352d3f
PB		 10701 if (stub_type != arm_stub_none
10702 && arm_stub_is_thumb (stub_type))
10703 {
10704 lower_insn = 0xd000;
10705 }
10706 else
10707 {
10708 lower_insn = 0xc000;
6a631e86 10709 /* Round up the offset to a word boundary. */
12352d3f
PB		 10710 offset = (offset + 2) & ~2;
10711 }
10712
0855e32b
NS		 10713 neg = offset < 0;
10714 upper_insn = (0xf000
10715 | ((offset >> 12) & 0x3ff)
10716 | (neg << 10));
12352d3f 10717 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 10718 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 10719 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 10720 bfd_put_16 (input_bfd, upper_insn, hit_data);
10721 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10722 return bfd_reloc_ok;
10723 }
10724 }
10725 /* These relocations needs special care, as besides the fact
10726 they point somewhere in .gotplt, the addend must be
10727 adjusted accordingly depending on the type of instruction
6a631e86 10728 we refer to. */
0855e32b
NS		 10729 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
10730 {
10731 unsigned long data, insn;
10732 unsigned thumb;
b38cadfb 10733
0855e32b
NS		 10734 data = bfd_get_32 (input_bfd, hit_data);
10735 thumb = data & 1;
10736 data &= ~1u;
b38cadfb 10737
0855e32b
NS		 10738 if (thumb)
10739 {
10740 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
10741 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10742 insn = (insn << 16)
10743 | bfd_get_16 (input_bfd,
10744 contents + rel->r_offset - data + 2);
10745 if ((insn & 0xf800c000) == 0xf000c000)
10746 /* bl/blx */
10747 value = -6;
10748 else if ((insn & 0xffffff00) == 0x4400)
10749 /* add */
10750 value = -5;
10751 else
10752 {
10753 (*_bfd_error_handler)
10754 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
10755 input_bfd, input_section,
10756 (unsigned long)rel->r_offset, insn);
10757 return bfd_reloc_notsupported;
10758 }
10759 }
10760 else
10761 {
10762 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
10763
10764 switch (insn >> 24)
10765 {
10766 case 0xeb: /* bl */
10767 case 0xfa: /* blx */
10768 value = -4;
10769 break;
10770
10771 case 0xe0: /* add */
10772 value = -8;
10773 break;
b38cadfb 10774
0855e32b
NS		 10775 default:
10776 (*_bfd_error_handler)
10777 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
10778 input_bfd, input_section,
10779 (unsigned long)rel->r_offset, insn);
10780 return bfd_reloc_notsupported;
10781 }
10782 }
b38cadfb 10783
0855e32b
NS		 10784 value += ((globals->root.sgotplt->output_section->vma
10785 + globals->root.sgotplt->output_offset + off)
10786 - (input_section->output_section->vma
10787 + input_section->output_offset
10788 + rel->r_offset)
10789 + globals->sgotplt_jump_table_size);
10790 }
10791 else
10792 value = ((globals->root.sgot->output_section->vma
10793 + globals->root.sgot->output_offset + off)
10794 - (input_section->output_section->vma
10795 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 10796
10797 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10798 contents, rel->r_offset, value,
00a97672 10799 rel->r_addend);
ba93b8ac
DJ		 10800 }
10801
10802 case R_ARM_TLS_LE32:
3cbc1e5e 10803 if (bfd_link_dll (info))
ba93b8ac
DJ		 10804 {
10805 (*_bfd_error_handler)
10806 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
10807 input_bfd, input_section,
10808 (long) rel->r_offset, howto->name);
46691134 10809 return bfd_reloc_notsupported;
ba93b8ac
DJ		 10810 }
10811 else
10812 value = tpoff (info, value);
906e58ca 10813
ba93b8ac 10814 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10815 contents, rel->r_offset, value,
10816 rel->r_addend);
ba93b8ac 10817
319850b4
JB		 10818 case R_ARM_V4BX:
10819 if (globals->fix_v4bx)
845b51d6
PB		 10820 {
10821 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 10822
845b51d6
PB		 10823 /* Ensure that we have a BX instruction. */
10824 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 10825
845b51d6
PB		 10826 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
10827 {
10828 /* Branch to veneer. */
10829 bfd_vma glue_addr;
10830 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
10831 glue_addr -= input_section->output_section->vma
10832 + input_section->output_offset
10833 + rel->r_offset + 8;
10834 insn = (insn & 0xf0000000) | 0x0a000000
10835 | ((glue_addr >> 2) & 0x00ffffff);
10836 }
10837 else
10838 {
10839 /* Preserve Rm (lowest four bits) and the condition code
10840 (highest four bits). Other bits encode MOV PC,Rm. */
10841 insn = (insn & 0xf000000f) | 0x01a0f000;
10842 }
319850b4 10843
845b51d6
PB		 10844 bfd_put_32 (input_bfd, insn, hit_data);
10845 }
319850b4
JB		 10846 return bfd_reloc_ok;
10847
b6895b4f
PB		 10848 case R_ARM_MOVW_ABS_NC:
10849 case R_ARM_MOVT_ABS:
10850 case R_ARM_MOVW_PREL_NC:
10851 case R_ARM_MOVT_PREL:
92f5d02b
MS		 10852 /* Until we properly support segment-base-relative addressing then
10853 we assume the segment base to be zero, as for the group relocations.
10854 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
10855 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
10856 case R_ARM_MOVW_BREL_NC:
10857 case R_ARM_MOVW_BREL:
10858 case R_ARM_MOVT_BREL:
b6895b4f
PB		 10859 {
10860 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
10861
10862 if (globals->use_rel)
10863 {
10864 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 10865 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10866 }
92f5d02b 10867
b6895b4f 10868 value += signed_addend;
b6895b4f
PB		 10869
10870 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
10871 value -= (input_section->output_section->vma
10872 + input_section->output_offset + rel->r_offset);
10873
92f5d02b 10874 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 10875 return bfd_reloc_overflow;
92f5d02b 10876
35fc36a8 10877 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10878 value |= 1;
10879
10880 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 10881 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 10882 value >>= 16;
10883
10884 insn &= 0xfff0f000;
10885 insn |= value & 0xfff;
10886 insn |= (value & 0xf000) << 4;
10887 bfd_put_32 (input_bfd, insn, hit_data);
10888 }
10889 return bfd_reloc_ok;
10890
10891 case R_ARM_THM_MOVW_ABS_NC:
10892 case R_ARM_THM_MOVT_ABS:
10893 case R_ARM_THM_MOVW_PREL_NC:
10894 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 10895 /* Until we properly support segment-base-relative addressing then
10896 we assume the segment base to be zero, as for the above relocations.
10897 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
10898 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
10899 as R_ARM_THM_MOVT_ABS. */
10900 case R_ARM_THM_MOVW_BREL_NC:
10901 case R_ARM_THM_MOVW_BREL:
10902 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 10903 {
10904 bfd_vma insn;
906e58ca 10905
b6895b4f
PB		 10906 insn = bfd_get_16 (input_bfd, hit_data) << 16;
10907 insn |= bfd_get_16 (input_bfd, hit_data + 2);
10908
10909 if (globals->use_rel)
10910 {
10911 addend = ((insn >> 4) & 0xf000)
10912 | ((insn >> 15) & 0x0800)
10913 | ((insn >> 4) & 0x0700)
10914 | (insn & 0x00ff);
39623e12 10915 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10916 }
92f5d02b 10917
b6895b4f 10918 value += signed_addend;
b6895b4f
PB		 10919
10920 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
10921 value -= (input_section->output_section->vma
10922 + input_section->output_offset + rel->r_offset);
10923
92f5d02b 10924 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 10925 return bfd_reloc_overflow;
92f5d02b 10926
35fc36a8 10927 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10928 value |= 1;
10929
10930 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 10931 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 10932 value >>= 16;
10933
10934 insn &= 0xfbf08f00;
10935 insn |= (value & 0xf000) << 4;
10936 insn |= (value & 0x0800) << 15;
10937 insn |= (value & 0x0700) << 4;
10938 insn |= (value & 0x00ff);
10939
10940 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10941 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10942 }
10943 return bfd_reloc_ok;
10944
4962c51a
MS		 10945 case R_ARM_ALU_PC_G0_NC:
10946 case R_ARM_ALU_PC_G1_NC:
10947 case R_ARM_ALU_PC_G0:
10948 case R_ARM_ALU_PC_G1:
10949 case R_ARM_ALU_PC_G2:
10950 case R_ARM_ALU_SB_G0_NC:
10951 case R_ARM_ALU_SB_G1_NC:
10952 case R_ARM_ALU_SB_G0:
10953 case R_ARM_ALU_SB_G1:
10954 case R_ARM_ALU_SB_G2:
10955 {
10956 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10957 bfd_vma pc = input_section->output_section->vma
4962c51a 10958 + input_section->output_offset + rel->r_offset;
31a91d61 10959 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10960 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 10961 bfd_vma residual;
10962 bfd_vma g_n;
4962c51a 10963 bfd_signed_vma signed_value;
99059e56
RM		 10964 int group = 0;
10965
10966 /* Determine which group of bits to select. */
10967 switch (r_type)
10968 {
10969 case R_ARM_ALU_PC_G0_NC:
10970 case R_ARM_ALU_PC_G0:
10971 case R_ARM_ALU_SB_G0_NC:
10972 case R_ARM_ALU_SB_G0:
10973 group = 0;
10974 break;
10975
10976 case R_ARM_ALU_PC_G1_NC:
10977 case R_ARM_ALU_PC_G1:
10978 case R_ARM_ALU_SB_G1_NC:
10979 case R_ARM_ALU_SB_G1:
10980 group = 1;
10981 break;
10982
10983 case R_ARM_ALU_PC_G2:
10984 case R_ARM_ALU_SB_G2:
10985 group = 2;
10986 break;
10987
10988 default:
10989 abort ();
10990 }
10991
10992 /* If REL, extract the addend from the insn. If RELA, it will
10993 have already been fetched for us. */
4962c51a 10994 if (globals->use_rel)
99059e56
RM		 10995 {
10996 int negative;
10997 bfd_vma constant = insn & 0xff;
10998 bfd_vma rotation = (insn & 0xf00) >> 8;
10999
11000 if (rotation == 0)
11001 signed_addend = constant;
11002 else
11003 {
11004 /* Compensate for the fact that in the instruction, the
11005 rotation is stored in multiples of 2 bits. */
11006 rotation *= 2;
11007
11008 /* Rotate "constant" right by "rotation" bits. */
11009 signed_addend = (constant >> rotation) |
11010 (constant << (8 * sizeof (bfd_vma) - rotation));
11011 }
11012
11013 /* Determine if the instruction is an ADD or a SUB.
11014 (For REL, this determines the sign of the addend.) */
11015 negative = identify_add_or_sub (insn);
11016 if (negative == 0)
11017 {
11018 (*_bfd_error_handler)
11019 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11020 input_bfd, input_section,
11021 (long) rel->r_offset, howto->name);
11022 return bfd_reloc_overflow;
11023 }
11024
11025 signed_addend *= negative;
11026 }
4962c51a
MS		 11027
11028 /* Compute the value (X) to go in the place. */
99059e56
RM		 11029 if (r_type == R_ARM_ALU_PC_G0_NC
11030 || r_type == R_ARM_ALU_PC_G1_NC
11031 || r_type == R_ARM_ALU_PC_G0
11032 || r_type == R_ARM_ALU_PC_G1
11033 || r_type == R_ARM_ALU_PC_G2)
11034 /* PC relative. */
11035 signed_value = value - pc + signed_addend;
11036 else
11037 /* Section base relative. */
11038 signed_value = value - sb + signed_addend;
11039
11040 /* If the target symbol is a Thumb function, then set the
11041 Thumb bit in the address. */
35fc36a8 11042 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11043 signed_value |= 1;
11044
99059e56
RM		 11045 /* Calculate the value of the relevant G_n, in encoded
11046 constant-with-rotation format. */
b6518b38
NC		 11047 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11048 group, &residual);
99059e56
RM		 11049
11050 /* Check for overflow if required. */
11051 if ((r_type == R_ARM_ALU_PC_G0
11052 || r_type == R_ARM_ALU_PC_G1
11053 || r_type == R_ARM_ALU_PC_G2
11054 || r_type == R_ARM_ALU_SB_G0
11055 || r_type == R_ARM_ALU_SB_G1
11056 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11057 {
11058 (*_bfd_error_handler)
11059 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11060 input_bfd, input_section,
b6518b38
NC		 11061 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11062 howto->name);
99059e56
RM		 11063 return bfd_reloc_overflow;
11064 }
11065
11066 /* Mask out the value and the ADD/SUB part of the opcode; take care
11067 not to destroy the S bit. */
11068 insn &= 0xff1ff000;
11069
11070 /* Set the opcode according to whether the value to go in the
11071 place is negative. */
11072 if (signed_value < 0)
11073 insn |= 1 << 22;
11074 else
11075 insn |= 1 << 23;
11076
11077 /* Encode the offset. */
11078 insn |= g_n;
4962c51a
MS		 11079
11080 bfd_put_32 (input_bfd, insn, hit_data);
11081 }
11082 return bfd_reloc_ok;
11083
11084 case R_ARM_LDR_PC_G0:
11085 case R_ARM_LDR_PC_G1:
11086 case R_ARM_LDR_PC_G2:
11087 case R_ARM_LDR_SB_G0:
11088 case R_ARM_LDR_SB_G1:
11089 case R_ARM_LDR_SB_G2:
11090 {
11091 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11092 bfd_vma pc = input_section->output_section->vma
4962c51a 11093 + input_section->output_offset + rel->r_offset;
31a91d61 11094 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11095 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11096 bfd_vma residual;
4962c51a 11097 bfd_signed_vma signed_value;
99059e56
RM		 11098 int group = 0;
11099
11100 /* Determine which groups of bits to calculate. */
11101 switch (r_type)
11102 {
11103 case R_ARM_LDR_PC_G0:
11104 case R_ARM_LDR_SB_G0:
11105 group = 0;
11106 break;
11107
11108 case R_ARM_LDR_PC_G1:
11109 case R_ARM_LDR_SB_G1:
11110 group = 1;
11111 break;
11112
11113 case R_ARM_LDR_PC_G2:
11114 case R_ARM_LDR_SB_G2:
11115 group = 2;
11116 break;
11117
11118 default:
11119 abort ();
11120 }
11121
11122 /* If REL, extract the addend from the insn. If RELA, it will
11123 have already been fetched for us. */
4962c51a 11124 if (globals->use_rel)
99059e56
RM		 11125 {
11126 int negative = (insn & (1 << 23)) ? 1 : -1;
11127 signed_addend = negative * (insn & 0xfff);
11128 }
4962c51a
MS		 11129
11130 /* Compute the value (X) to go in the place. */
99059e56
RM		 11131 if (r_type == R_ARM_LDR_PC_G0
11132 || r_type == R_ARM_LDR_PC_G1
11133 || r_type == R_ARM_LDR_PC_G2)
11134 /* PC relative. */
11135 signed_value = value - pc + signed_addend;
11136 else
11137 /* Section base relative. */
11138 signed_value = value - sb + signed_addend;
11139
11140 /* Calculate the value of the relevant G_{n-1} to obtain
11141 the residual at that stage. */
b6518b38
NC		 11142 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11143 group - 1, &residual);
99059e56
RM		 11144
11145 /* Check for overflow. */
11146 if (residual >= 0x1000)
11147 {
11148 (*_bfd_error_handler)
11149 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11150 input_bfd, input_section,
11151 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11152 return bfd_reloc_overflow;
11153 }
11154
11155 /* Mask out the value and U bit. */
11156 insn &= 0xff7ff000;
11157
11158 /* Set the U bit if the value to go in the place is non-negative. */
11159 if (signed_value >= 0)
11160 insn |= 1 << 23;
11161
11162 /* Encode the offset. */
11163 insn |= residual;
4962c51a
MS		 11164
11165 bfd_put_32 (input_bfd, insn, hit_data);
11166 }
11167 return bfd_reloc_ok;
11168
11169 case R_ARM_LDRS_PC_G0:
11170 case R_ARM_LDRS_PC_G1:
11171 case R_ARM_LDRS_PC_G2:
11172 case R_ARM_LDRS_SB_G0:
11173 case R_ARM_LDRS_SB_G1:
11174 case R_ARM_LDRS_SB_G2:
11175 {
11176 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11177 bfd_vma pc = input_section->output_section->vma
4962c51a 11178 + input_section->output_offset + rel->r_offset;
31a91d61 11179 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11180 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11181 bfd_vma residual;
4962c51a 11182 bfd_signed_vma signed_value;
99059e56
RM		 11183 int group = 0;
11184
11185 /* Determine which groups of bits to calculate. */
11186 switch (r_type)
11187 {
11188 case R_ARM_LDRS_PC_G0:
11189 case R_ARM_LDRS_SB_G0:
11190 group = 0;
11191 break;
11192
11193 case R_ARM_LDRS_PC_G1:
11194 case R_ARM_LDRS_SB_G1:
11195 group = 1;
11196 break;
11197
11198 case R_ARM_LDRS_PC_G2:
11199 case R_ARM_LDRS_SB_G2:
11200 group = 2;
11201 break;
11202
11203 default:
11204 abort ();
11205 }
11206
11207 /* If REL, extract the addend from the insn. If RELA, it will
11208 have already been fetched for us. */
4962c51a 11209 if (globals->use_rel)
99059e56
RM		 11210 {
11211 int negative = (insn & (1 << 23)) ? 1 : -1;
11212 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11213 }
4962c51a
MS		 11214
11215 /* Compute the value (X) to go in the place. */
99059e56
RM		 11216 if (r_type == R_ARM_LDRS_PC_G0
11217 || r_type == R_ARM_LDRS_PC_G1
11218 || r_type == R_ARM_LDRS_PC_G2)
11219 /* PC relative. */
11220 signed_value = value - pc + signed_addend;
11221 else
11222 /* Section base relative. */
11223 signed_value = value - sb + signed_addend;
11224
11225 /* Calculate the value of the relevant G_{n-1} to obtain
11226 the residual at that stage. */
b6518b38
NC		 11227 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11228 group - 1, &residual);
99059e56
RM		 11229
11230 /* Check for overflow. */
11231 if (residual >= 0x100)
11232 {
11233 (*_bfd_error_handler)
11234 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11235 input_bfd, input_section,
11236 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11237 return bfd_reloc_overflow;
11238 }
11239
11240 /* Mask out the value and U bit. */
11241 insn &= 0xff7ff0f0;
11242
11243 /* Set the U bit if the value to go in the place is non-negative. */
11244 if (signed_value >= 0)
11245 insn |= 1 << 23;
11246
11247 /* Encode the offset. */
11248 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 11249
11250 bfd_put_32 (input_bfd, insn, hit_data);
11251 }
11252 return bfd_reloc_ok;
11253
11254 case R_ARM_LDC_PC_G0:
11255 case R_ARM_LDC_PC_G1:
11256 case R_ARM_LDC_PC_G2:
11257 case R_ARM_LDC_SB_G0:
11258 case R_ARM_LDC_SB_G1:
11259 case R_ARM_LDC_SB_G2:
11260 {
11261 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11262 bfd_vma pc = input_section->output_section->vma
4962c51a 11263 + input_section->output_offset + rel->r_offset;
31a91d61 11264 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11265 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11266 bfd_vma residual;
4962c51a 11267 bfd_signed_vma signed_value;
99059e56
RM		 11268 int group = 0;
11269
11270 /* Determine which groups of bits to calculate. */
11271 switch (r_type)
11272 {
11273 case R_ARM_LDC_PC_G0:
11274 case R_ARM_LDC_SB_G0:
11275 group = 0;
11276 break;
11277
11278 case R_ARM_LDC_PC_G1:
11279 case R_ARM_LDC_SB_G1:
11280 group = 1;
11281 break;
11282
11283 case R_ARM_LDC_PC_G2:
11284 case R_ARM_LDC_SB_G2:
11285 group = 2;
11286 break;
11287
11288 default:
11289 abort ();
11290 }
11291
11292 /* If REL, extract the addend from the insn. If RELA, it will
11293 have already been fetched for us. */
4962c51a 11294 if (globals->use_rel)
99059e56
RM		 11295 {
11296 int negative = (insn & (1 << 23)) ? 1 : -1;
11297 signed_addend = negative * ((insn & 0xff) << 2);
11298 }
4962c51a
MS		 11299
11300 /* Compute the value (X) to go in the place. */
99059e56
RM		 11301 if (r_type == R_ARM_LDC_PC_G0
11302 || r_type == R_ARM_LDC_PC_G1
11303 || r_type == R_ARM_LDC_PC_G2)
11304 /* PC relative. */
11305 signed_value = value - pc + signed_addend;
11306 else
11307 /* Section base relative. */
11308 signed_value = value - sb + signed_addend;
11309
11310 /* Calculate the value of the relevant G_{n-1} to obtain
11311 the residual at that stage. */
b6518b38
NC		 11312 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11313 group - 1, &residual);
99059e56
RM		 11314
11315 /* Check for overflow. (The absolute value to go in the place must be
11316 divisible by four and, after having been divided by four, must
11317 fit in eight bits.) */
11318 if ((residual & 0x3) != 0 || residual >= 0x400)
11319 {
11320 (*_bfd_error_handler)
11321 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11322 input_bfd, input_section,
b6518b38 11323 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11324 return bfd_reloc_overflow;
11325 }
11326
11327 /* Mask out the value and U bit. */
11328 insn &= 0xff7fff00;
11329
11330 /* Set the U bit if the value to go in the place is non-negative. */
11331 if (signed_value >= 0)
11332 insn |= 1 << 23;
11333
11334 /* Encode the offset. */
11335 insn |= residual >> 2;
4962c51a
MS		 11336
11337 bfd_put_32 (input_bfd, insn, hit_data);
11338 }
11339 return bfd_reloc_ok;
11340
72d98d16
MG		 11341 case R_ARM_THM_ALU_ABS_G0_NC:
11342 case R_ARM_THM_ALU_ABS_G1_NC:
11343 case R_ARM_THM_ALU_ABS_G2_NC:
11344 case R_ARM_THM_ALU_ABS_G3_NC:
11345 {
11346 const int shift_array[4] = {0, 8, 16, 24};
11347 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
11348 bfd_vma addr = value;
11349 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
11350
11351 /* Compute address. */
11352 if (globals->use_rel)
11353 signed_addend = insn & 0xff;
11354 addr += signed_addend;
11355 if (branch_type == ST_BRANCH_TO_THUMB)
11356 addr |= 1;
11357 /* Clean imm8 insn. */
11358 insn &= 0xff00;
11359 /* And update with correct part of address. */
11360 insn |= (addr >> shift) & 0xff;
11361 /* Update insn. */
11362 bfd_put_16 (input_bfd, insn, hit_data);
11363 }
11364
11365 *unresolved_reloc_p = FALSE;
11366 return bfd_reloc_ok;
11367
252b5132
RH		 11368 default:
11369 return bfd_reloc_notsupported;
11370 }
11371}
11372
98c1d4aa
NC		 11373/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11374static void
57e8b36a
NC		 11375arm_add_to_rel (bfd * abfd,
11376 bfd_byte * address,
11377 reloc_howto_type * howto,
11378 bfd_signed_vma increment)
98c1d4aa 11379{
98c1d4aa
NC		 11380 bfd_signed_vma addend;
11381
bd97cb95
DJ		 11382 if (howto->type == R_ARM_THM_CALL
11383 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 11384 {
9a5aca8c
AM		 11385 int upper_insn, lower_insn;
11386 int upper, lower;
98c1d4aa 11387
9a5aca8c
AM		 11388 upper_insn = bfd_get_16 (abfd, address);
11389 lower_insn = bfd_get_16 (abfd, address + 2);
11390 upper = upper_insn & 0x7ff;
11391 lower = lower_insn & 0x7ff;
11392
11393 addend = (upper << 12) | (lower << 1);
ddda4409 11394 addend += increment;
9a5aca8c 11395 addend >>= 1;
98c1d4aa 11396
9a5aca8c
AM		 11397 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
11398 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
11399
dc810e39
AM		 11400 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
11401 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 11402 }
11403 else
11404 {
11405 bfd_vma contents;
11406
11407 contents = bfd_get_32 (abfd, address);
11408
11409 /* Get the (signed) value from the instruction. */
11410 addend = contents & howto->src_mask;
11411 if (addend & ((howto->src_mask + 1) >> 1))
11412 {
11413 bfd_signed_vma mask;
11414
11415 mask = -1;
11416 mask &= ~ howto->src_mask;
11417 addend |= mask;
11418 }
11419
11420 /* Add in the increment, (which is a byte value). */
11421 switch (howto->type)
11422 {
11423 default:
11424 addend += increment;
11425 break;
11426
11427 case R_ARM_PC24:
c6596c5e 11428 case R_ARM_PLT32:
5b5bb741
PB		 11429 case R_ARM_CALL:
11430 case R_ARM_JUMP24:
9a5aca8c 11431 addend <<= howto->size;
dc810e39 11432 addend += increment;
9a5aca8c
AM		 11433
11434 /* Should we check for overflow here ? */
11435
11436 /* Drop any undesired bits. */
11437 addend >>= howto->rightshift;
11438 break;
11439 }
11440
11441 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
11442
11443 bfd_put_32 (abfd, contents, address);
ddda4409 11444 }
98c1d4aa 11445}
252b5132 11446
ba93b8ac
DJ		 11447#define IS_ARM_TLS_RELOC(R_TYPE) \
11448 ((R_TYPE) == R_ARM_TLS_GD32 \
11449 || (R_TYPE) == R_ARM_TLS_LDO32 \
11450 || (R_TYPE) == R_ARM_TLS_LDM32 \
11451 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11452 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11453 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11454 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 11455 || (R_TYPE) == R_ARM_TLS_IE32 \
11456 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11457
11458/* Specific set of relocations for the gnu tls dialect. */
11459#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11460 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11461 || (R_TYPE) == R_ARM_TLS_CALL \
11462 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11463 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11464 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 11465
252b5132 11466/* Relocate an ARM ELF section. */
906e58ca 11467
b34976b6 11468static bfd_boolean
57e8b36a
NC		 11469elf32_arm_relocate_section (bfd * output_bfd,
11470 struct bfd_link_info * info,
11471 bfd * input_bfd,
11472 asection * input_section,
11473 bfd_byte * contents,
11474 Elf_Internal_Rela * relocs,
11475 Elf_Internal_Sym * local_syms,
11476 asection ** local_sections)
252b5132 11477{
b34976b6
AM		 11478 Elf_Internal_Shdr *symtab_hdr;
11479 struct elf_link_hash_entry **sym_hashes;
11480 Elf_Internal_Rela *rel;
11481 Elf_Internal_Rela *relend;
11482 const char *name;
b32d3aa2 11483 struct elf32_arm_link_hash_table * globals;
252b5132 11484
4e7fd91e 11485 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 11486 if (globals == NULL)
11487 return FALSE;
b491616a 11488
0ffa91dd 11489 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 11490 sym_hashes = elf_sym_hashes (input_bfd);
11491
11492 rel = relocs;
11493 relend = relocs + input_section->reloc_count;
11494 for (; rel < relend; rel++)
11495 {
ba96a88f
NC		 11496 int r_type;
11497 reloc_howto_type * howto;
11498 unsigned long r_symndx;
11499 Elf_Internal_Sym * sym;
11500 asection * sec;
252b5132 11501 struct elf_link_hash_entry * h;
ba96a88f
NC		 11502 bfd_vma relocation;
11503 bfd_reloc_status_type r;
11504 arelent bfd_reloc;
ba93b8ac 11505 char sym_type;
0945cdfd 11506 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 11507 char *error_message = NULL;
f21f3fe0 11508
252b5132 11509 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 11510 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 11511 r_type = arm_real_reloc_type (globals, r_type);
252b5132 11512
ba96a88f 11513 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 11514 || r_type == R_ARM_GNU_VTINHERIT)
11515 continue;
252b5132 11516
b32d3aa2 11517 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 11518 howto = bfd_reloc.howto;
252b5132 11519
252b5132
RH		 11520 h = NULL;
11521 sym = NULL;
11522 sec = NULL;
9b485d32 11523
252b5132
RH		 11524 if (r_symndx < symtab_hdr->sh_info)
11525 {
11526 sym = local_syms + r_symndx;
ba93b8ac 11527 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 11528 sec = local_sections[r_symndx];
ffcb4889
NS		 11529
11530 /* An object file might have a reference to a local
11531 undefined symbol. This is a daft object file, but we
11532 should at least do something about it. V4BX & NONE
11533 relocations do not use the symbol and are explicitly
77b4f08f
TS		 11534 allowed to use the undefined symbol, so allow those.
11535 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 11536 if (r_type != R_ARM_V4BX
11537 && r_type != R_ARM_NONE
77b4f08f 11538 && r_symndx != STN_UNDEF
ffcb4889
NS		 11539 && bfd_is_und_section (sec)
11540 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 11541 (*info->callbacks->undefined_symbol)
11542 (info, bfd_elf_string_from_elf_section
11543 (input_bfd, symtab_hdr->sh_link, sym->st_name),
11544 input_bfd, input_section,
11545 rel->r_offset, TRUE);
b38cadfb 11546
4e7fd91e 11547 if (globals->use_rel)
f8df10f4 11548 {
4e7fd91e
PB		 11549 relocation = (sec->output_section->vma
11550 + sec->output_offset
11551 + sym->st_value);
0e1862bb 11552 if (!bfd_link_relocatable (info)
ab96bf03
AM		 11553 && (sec->flags & SEC_MERGE)
11554 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 11555 {
4e7fd91e
PB		 11556 asection *msec;
11557 bfd_vma addend, value;
11558
39623e12 11559 switch (r_type)
4e7fd91e 11560 {
39623e12
PB		 11561 case R_ARM_MOVW_ABS_NC:
11562 case R_ARM_MOVT_ABS:
11563 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11564 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
11565 addend = (addend ^ 0x8000) - 0x8000;
11566 break;
f8df10f4 11567
39623e12
PB		 11568 case R_ARM_THM_MOVW_ABS_NC:
11569 case R_ARM_THM_MOVT_ABS:
11570 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
11571 << 16;
11572 value |= bfd_get_16 (input_bfd,
11573 contents + rel->r_offset + 2);
11574 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
11575 | ((value & 0x04000000) >> 15);
11576 addend = (addend ^ 0x8000) - 0x8000;
11577 break;
f8df10f4 11578
39623e12
PB		 11579 default:
11580 if (howto->rightshift
11581 || (howto->src_mask & (howto->src_mask + 1)))
11582 {
11583 (*_bfd_error_handler)
11584 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
11585 input_bfd, input_section,
11586 (long) rel->r_offset, howto->name);
11587 return FALSE;
11588 }
11589
11590 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11591
11592 /* Get the (signed) value from the instruction. */
11593 addend = value & howto->src_mask;
11594 if (addend & ((howto->src_mask + 1) >> 1))
11595 {
11596 bfd_signed_vma mask;
11597
11598 mask = -1;
11599 mask &= ~ howto->src_mask;
11600 addend |= mask;
11601 }
11602 break;
4e7fd91e 11603 }
39623e12 11604
4e7fd91e
PB		 11605 msec = sec;
11606 addend =
11607 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
11608 - relocation;
11609 addend += msec->output_section->vma + msec->output_offset;
39623e12 11610
cc643b88 11611 /* Cases here must match those in the preceding
39623e12
PB		 11612 switch statement. */
11613 switch (r_type)
11614 {
11615 case R_ARM_MOVW_ABS_NC:
11616 case R_ARM_MOVT_ABS:
11617 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
11618 | (addend & 0xfff);
11619 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11620 break;
11621
11622 case R_ARM_THM_MOVW_ABS_NC:
11623 case R_ARM_THM_MOVT_ABS:
11624 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
11625 | (addend & 0xff) | ((addend & 0x0800) << 15);
11626 bfd_put_16 (input_bfd, value >> 16,
11627 contents + rel->r_offset);
11628 bfd_put_16 (input_bfd, value,
11629 contents + rel->r_offset + 2);
11630 break;
11631
11632 default:
11633 value = (value & ~ howto->dst_mask)
11634 | (addend & howto->dst_mask);
11635 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11636 break;
11637 }
f8df10f4 11638 }
f8df10f4 11639 }
4e7fd91e
PB		 11640 else
11641 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 11642 }
11643 else
11644 {
62d887d4 11645 bfd_boolean warned, ignored;
560e09e9 11646
b2a8e766
AM		 11647 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
11648 r_symndx, symtab_hdr, sym_hashes,
11649 h, sec, relocation,
62d887d4 11650 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 11651
11652 sym_type = h->type;
252b5132
RH		 11653 }
11654
dbaa2011 11655 if (sec != NULL && discarded_section (sec))
e4067dbb 11656 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 11657 rel, 1, relend, howto, 0, contents);
ab96bf03 11658
0e1862bb 11659 if (bfd_link_relocatable (info))
ab96bf03
AM		 11660 {
11661 /* This is a relocatable link. We don't have to change
11662 anything, unless the reloc is against a section symbol,
11663 in which case we have to adjust according to where the
11664 section symbol winds up in the output section. */
11665 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
11666 {
11667 if (globals->use_rel)
11668 arm_add_to_rel (input_bfd, contents + rel->r_offset,
11669 howto, (bfd_signed_vma) sec->output_offset);
11670 else
11671 rel->r_addend += sec->output_offset;
11672 }
11673 continue;
11674 }
11675
252b5132
RH		 11676 if (h != NULL)
11677 name = h->root.root.string;
11678 else
11679 {
11680 name = (bfd_elf_string_from_elf_section
11681 (input_bfd, symtab_hdr->sh_link, sym->st_name));
11682 if (name == NULL || *name == '\0')
11683 name = bfd_section_name (input_bfd, sec);
11684 }
f21f3fe0 11685
cf35638d 11686 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 11687 && r_type != R_ARM_NONE
11688 && (h == NULL
11689 || h->root.type == bfd_link_hash_defined
11690 || h->root.type == bfd_link_hash_defweak)
11691 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
11692 {
11693 (*_bfd_error_handler)
11694 ((sym_type == STT_TLS
11695 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
11696 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
11697 input_bfd,
11698 input_section,
11699 (long) rel->r_offset,
11700 howto->name,
11701 name);
11702 }
11703
0855e32b 11704 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 11705 done, i.e., the relaxation produced the final output we want,
11706 and we won't let anybody mess with it. Also, we have to do
11707 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 11708 both in relaxed and non-relaxed cases. */
39d911fc
TP		 11709 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
11710 || (IS_ARM_TLS_GNU_RELOC (r_type)
11711 && !((h ? elf32_arm_hash_entry (h)->tls_type :
11712 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
11713 & GOT_TLS_GDESC)))
11714 {
11715 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
11716 contents, rel, h == NULL);
11717 /* This may have been marked unresolved because it came from
11718 a shared library. But we've just dealt with that. */
11719 unresolved_reloc = 0;
11720 }
11721 else
11722 r = bfd_reloc_continue;
b38cadfb 11723
39d911fc
TP		 11724 if (r == bfd_reloc_continue)
11725 {
11726 unsigned char branch_type =
11727 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
11728 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
11729
11730 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
11731 input_section, contents, rel,
11732 relocation, info, sec, name,
11733 sym_type, branch_type, h,
11734 &unresolved_reloc,
11735 &error_message);
11736 }
0945cdfd
DJ		 11737
11738 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
11739 because such sections are not SEC_ALLOC and thus ld.so will
11740 not process them. */
11741 if (unresolved_reloc
99059e56
RM		 11742 && !((input_section->flags & SEC_DEBUGGING) != 0
11743 && h->def_dynamic)
1d5316ab
AM		 11744 && _bfd_elf_section_offset (output_bfd, info, input_section,
11745 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 11746 {
11747 (*_bfd_error_handler)
843fe662
L		 11748 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
11749 input_bfd,
11750 input_section,
11751 (long) rel->r_offset,
11752 howto->name,
11753 h->root.root.string);
0945cdfd
DJ		 11754 return FALSE;
11755 }
252b5132
RH		 11756
11757 if (r != bfd_reloc_ok)
11758 {
252b5132
RH		 11759 switch (r)
11760 {
11761 case bfd_reloc_overflow:
cf919dfd
PB		 11762 /* If the overflowing reloc was to an undefined symbol,
11763 we have already printed one error message and there
11764 is no point complaining again. */
1a72702b
AM		 11765 if (!h || h->root.type != bfd_link_hash_undefined)
11766 (*info->callbacks->reloc_overflow)
11767 (info, (h ? &h->root : NULL), name, howto->name,
11768 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 11769 break;
11770
11771 case bfd_reloc_undefined:
1a72702b
AM		 11772 (*info->callbacks->undefined_symbol)
11773 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 11774 break;
11775
11776 case bfd_reloc_outofrange:
f2a9dd69 11777 error_message = _("out of range");
252b5132
RH		 11778 goto common_error;
11779
11780 case bfd_reloc_notsupported:
f2a9dd69 11781 error_message = _("unsupported relocation");
252b5132
RH		 11782 goto common_error;
11783
11784 case bfd_reloc_dangerous:
f2a9dd69 11785 /* error_message should already be set. */
252b5132
RH		 11786 goto common_error;
11787
11788 default:
f2a9dd69 11789 error_message = _("unknown error");
8029a119 11790 /* Fall through. */
252b5132
RH		 11791
11792 common_error:
f2a9dd69 11793 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 11794 (*info->callbacks->reloc_dangerous)
11795 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 11796 break;
11797 }
11798 }
11799 }
11800
b34976b6 11801 return TRUE;
252b5132
RH		 11802}
11803
91d6fa6a 11804/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 11805 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 11806 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 11807 maintaining that condition). */
11808
11809static void
11810add_unwind_table_edit (arm_unwind_table_edit **head,
11811 arm_unwind_table_edit **tail,
11812 arm_unwind_edit_type type,
11813 asection *linked_section,
91d6fa6a 11814 unsigned int tindex)
2468f9c9 11815{
21d799b5
NC		 11816 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
11817 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 11818
2468f9c9
PB		 11819 new_edit->type = type;
11820 new_edit->linked_section = linked_section;
91d6fa6a 11821 new_edit->index = tindex;
b38cadfb 11822
91d6fa6a 11823 if (tindex > 0)
2468f9c9
PB		 11824 {
11825 new_edit->next = NULL;
11826
11827 if (*tail)
11828 (*tail)->next = new_edit;
11829
11830 (*tail) = new_edit;
11831
11832 if (!*head)
11833 (*head) = new_edit;
11834 }
11835 else
11836 {
11837 new_edit->next = *head;
11838
11839 if (!*tail)
11840 *tail = new_edit;
11841
11842 *head = new_edit;
11843 }
11844}
11845
11846static _arm_elf_section_data *get_arm_elf_section_data (asection *);
11847
11848/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
11849static void
11850adjust_exidx_size(asection *exidx_sec, int adjust)
11851{
11852 asection *out_sec;
11853
11854 if (!exidx_sec->rawsize)
11855 exidx_sec->rawsize = exidx_sec->size;
11856
11857 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
11858 out_sec = exidx_sec->output_section;
11859 /* Adjust size of output section. */
11860 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
11861}
11862
11863/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
11864static void
11865insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
11866{
11867 struct _arm_elf_section_data *exidx_arm_data;
11868
11869 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11870 add_unwind_table_edit (
11871 &exidx_arm_data->u.exidx.unwind_edit_list,
11872 &exidx_arm_data->u.exidx.unwind_edit_tail,
11873 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
11874
491d01d3
YU		 11875 exidx_arm_data->additional_reloc_count++;
11876
2468f9c9
PB		 11877 adjust_exidx_size(exidx_sec, 8);
11878}
11879
11880/* Scan .ARM.exidx tables, and create a list describing edits which should be
11881 made to those tables, such that:
b38cadfb 11882
2468f9c9
PB		 11883 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
11884 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 11885 codes which have been inlined into the index).
2468f9c9 11886
85fdf906
AH		 11887 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
11888
2468f9c9 11889 The edits are applied when the tables are written
b38cadfb 11890 (in elf32_arm_write_section). */
2468f9c9
PB		 11891
11892bfd_boolean
11893elf32_arm_fix_exidx_coverage (asection **text_section_order,
11894 unsigned int num_text_sections,
85fdf906
AH		 11895 struct bfd_link_info *info,
11896 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 11897{
11898 bfd *inp;
11899 unsigned int last_second_word = 0, i;
11900 asection *last_exidx_sec = NULL;
11901 asection *last_text_sec = NULL;
11902 int last_unwind_type = -1;
11903
11904 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
11905 text sections. */
c72f2fb2 11906 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 11907 {
11908 asection *sec;
b38cadfb 11909
2468f9c9 11910 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 11911 {
2468f9c9
PB		 11912 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
11913 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 11914
dec9d5df 11915 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 11916 continue;
b38cadfb 11917
2468f9c9
PB		 11918 if (elf_sec->linked_to)
11919 {
11920 Elf_Internal_Shdr *linked_hdr
99059e56 11921 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 11922 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 11923 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 11924
11925 if (linked_sec_arm_data == NULL)
99059e56 11926 continue;
2468f9c9
PB		 11927
11928 /* Link this .ARM.exidx section back from the text section it
99059e56 11929 describes. */
2468f9c9
PB		 11930 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
11931 }
11932 }
11933 }
11934
11935 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
11936 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 11937 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 11938
11939 for (i = 0; i < num_text_sections; i++)
11940 {
11941 asection *sec = text_section_order[i];
11942 asection *exidx_sec;
11943 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
11944 struct _arm_elf_section_data *exidx_arm_data;
11945 bfd_byte *contents = NULL;
11946 int deleted_exidx_bytes = 0;
11947 bfd_vma j;
11948 arm_unwind_table_edit *unwind_edit_head = NULL;
11949 arm_unwind_table_edit *unwind_edit_tail = NULL;
11950 Elf_Internal_Shdr *hdr;
11951 bfd *ibfd;
11952
11953 if (arm_data == NULL)
99059e56 11954 continue;
2468f9c9
PB		 11955
11956 exidx_sec = arm_data->u.text.arm_exidx_sec;
11957 if (exidx_sec == NULL)
11958 {
11959 /* Section has no unwind data. */
11960 if (last_unwind_type == 0 || !last_exidx_sec)
11961 continue;
11962
11963 /* Ignore zero sized sections. */
11964 if (sec->size == 0)
11965 continue;
11966
11967 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11968 last_unwind_type = 0;
11969 continue;
11970 }
11971
22a8f80e
PB		 11972 /* Skip /DISCARD/ sections. */
11973 if (bfd_is_abs_section (exidx_sec->output_section))
11974 continue;
11975
2468f9c9
PB		 11976 hdr = &elf_section_data (exidx_sec)->this_hdr;
11977 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 11978 continue;
b38cadfb 11979
2468f9c9
PB		 11980 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11981 if (exidx_arm_data == NULL)
99059e56 11982 continue;
b38cadfb 11983
2468f9c9 11984 ibfd = exidx_sec->owner;
b38cadfb 11985
2468f9c9
PB		 11986 if (hdr->contents != NULL)
11987 contents = hdr->contents;
11988 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
11989 /* An error? */
11990 continue;
11991
ac06903d
YU		 11992 if (last_unwind_type > 0)
11993 {
11994 unsigned int first_word = bfd_get_32 (ibfd, contents);
11995 /* Add cantunwind if first unwind item does not match section
11996 start. */
11997 if (first_word != sec->vma)
11998 {
11999 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12000 last_unwind_type = 0;
12001 }
12002 }
12003
2468f9c9
PB		 12004 for (j = 0; j < hdr->sh_size; j += 8)
12005 {
12006 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12007 int unwind_type;
12008 int elide = 0;
12009
12010 /* An EXIDX_CANTUNWIND entry. */
12011 if (second_word == 1)
12012 {
12013 if (last_unwind_type == 0)
12014 elide = 1;
12015 unwind_type = 0;
12016 }
12017 /* Inlined unwinding data. Merge if equal to previous. */
12018 else if ((second_word & 0x80000000) != 0)
12019 {
85fdf906
AH		 12020 if (merge_exidx_entries
12021 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12022 elide = 1;
12023 unwind_type = 1;
12024 last_second_word = second_word;
12025 }
12026 /* Normal table entry. In theory we could merge these too,
12027 but duplicate entries are likely to be much less common. */
12028 else
12029 unwind_type = 2;
12030
491d01d3 12031 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12032 {
12033 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12034 DELETE_EXIDX_ENTRY, NULL, j / 8);
12035
12036 deleted_exidx_bytes += 8;
12037 }
12038
12039 last_unwind_type = unwind_type;
12040 }
12041
12042 /* Free contents if we allocated it ourselves. */
12043 if (contents != hdr->contents)
99059e56 12044 free (contents);
2468f9c9
PB		 12045
12046 /* Record edits to be applied later (in elf32_arm_write_section). */
12047 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12048 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12049
2468f9c9
PB		 12050 if (deleted_exidx_bytes > 0)
12051 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12052
12053 last_exidx_sec = exidx_sec;
12054 last_text_sec = sec;
12055 }
12056
12057 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12058 if (!bfd_link_relocatable (info) && last_exidx_sec
12059 && last_unwind_type != 0)
2468f9c9
PB		 12060 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12061
12062 return TRUE;
12063}
12064
3e6b1042
DJ		 12065static bfd_boolean
12066elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12067 bfd *ibfd, const char *name)
12068{
12069 asection *sec, *osec;
12070
3d4d4302 12071 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12072 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12073 return TRUE;
12074
12075 osec = sec->output_section;
12076 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12077 return TRUE;
12078
12079 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12080 sec->output_offset, sec->size))
12081 return FALSE;
12082
12083 return TRUE;
12084}
12085
12086static bfd_boolean
12087elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12088{
12089 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12090 asection *sec, *osec;
3e6b1042 12091
4dfe6ac6
NC		 12092 if (globals == NULL)
12093 return FALSE;
12094
3e6b1042
DJ		 12095 /* Invoke the regular ELF backend linker to do all the work. */
12096 if (!bfd_elf_final_link (abfd, info))
12097 return FALSE;
12098
fe33d2fa
CL		 12099 /* Process stub sections (eg BE8 encoding, ...). */
12100 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12101 unsigned int i;
cdb21a0a
NS		 12102 for (i=0; i<htab->top_id; i++)
12103 {
12104 sec = htab->stub_group[i].stub_sec;
12105 /* Only process it once, in its link_sec slot. */
12106 if (sec && i == htab->stub_group[i].link_sec->id)
12107 {
12108 osec = sec->output_section;
12109 elf32_arm_write_section (abfd, info, sec, sec->contents);
12110 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12111 sec->output_offset, sec->size))
12112 return FALSE;
12113 }
fe33d2fa 12114 }
fe33d2fa 12115
3e6b1042
DJ		 12116 /* Write out any glue sections now that we have created all the
12117 stubs. */
12118 if (globals->bfd_of_glue_owner != NULL)
12119 {
12120 if (! elf32_arm_output_glue_section (info, abfd,
12121 globals->bfd_of_glue_owner,
12122 ARM2THUMB_GLUE_SECTION_NAME))
12123 return FALSE;
12124
12125 if (! elf32_arm_output_glue_section (info, abfd,
12126 globals->bfd_of_glue_owner,
12127 THUMB2ARM_GLUE_SECTION_NAME))
12128 return FALSE;
12129
12130 if (! elf32_arm_output_glue_section (info, abfd,
12131 globals->bfd_of_glue_owner,
12132 VFP11_ERRATUM_VENEER_SECTION_NAME))
12133 return FALSE;
12134
a504d23a
LA		 12135 if (! elf32_arm_output_glue_section (info, abfd,
12136 globals->bfd_of_glue_owner,
12137 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12138 return FALSE;
12139
3e6b1042
DJ		 12140 if (! elf32_arm_output_glue_section (info, abfd,
12141 globals->bfd_of_glue_owner,
12142 ARM_BX_GLUE_SECTION_NAME))
12143 return FALSE;
12144 }
12145
12146 return TRUE;
12147}
12148
5968a7b8
NC		 12149/* Return a best guess for the machine number based on the attributes. */
12150
12151static unsigned int
12152bfd_arm_get_mach_from_attributes (bfd * abfd)
12153{
12154 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12155
12156 switch (arch)
12157 {
12158 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12159 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12160 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12161
12162 case TAG_CPU_ARCH_V5TE:
12163 {
12164 char * name;
12165
12166 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12167 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12168
12169 if (name)
12170 {
12171 if (strcmp (name, "IWMMXT2") == 0)
12172 return bfd_mach_arm_iWMMXt2;
12173
12174 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12175 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12176
12177 if (strcmp (name, "XSCALE") == 0)
12178 {
12179 int wmmx;
12180
12181 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12182 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12183 switch (wmmx)
12184 {
12185 case 1: return bfd_mach_arm_iWMMXt;
12186 case 2: return bfd_mach_arm_iWMMXt2;
12187 default: return bfd_mach_arm_XScale;
12188 }
12189 }
5968a7b8
NC		 12190 }
12191
12192 return bfd_mach_arm_5TE;
12193 }
12194
12195 default:
12196 return bfd_mach_arm_unknown;
12197 }
12198}
12199
c178919b
NC		 12200/* Set the right machine number. */
12201
12202static bfd_boolean
57e8b36a 12203elf32_arm_object_p (bfd *abfd)
c178919b 12204{
5a6c6817 12205 unsigned int mach;
57e8b36a 12206
5a6c6817 12207 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12208
5968a7b8
NC		 12209 if (mach == bfd_mach_arm_unknown)
12210 {
12211 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12212 mach = bfd_mach_arm_ep9312;
12213 else
12214 mach = bfd_arm_get_mach_from_attributes (abfd);
12215 }
c178919b 12216
5968a7b8 12217 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 12218 return TRUE;
12219}
12220
fc830a83 12221/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 12222
b34976b6 12223static bfd_boolean
57e8b36a 12224elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 12225{
12226 if (elf_flags_init (abfd)
12227 && elf_elfheader (abfd)->e_flags != flags)
12228 {
fc830a83
NC		 12229 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
12230 {
fd2ec330 12231 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 12232 (*_bfd_error_handler)
12233 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
12234 abfd);
fc830a83 12235 else
d003868e
AM		 12236 _bfd_error_handler
12237 (_("Warning: Clearing the interworking flag of %B due to outside request"),
12238 abfd);
fc830a83 12239 }
252b5132
RH		 12240 }
12241 else
12242 {
12243 elf_elfheader (abfd)->e_flags = flags;
b34976b6 12244 elf_flags_init (abfd) = TRUE;
252b5132
RH		 12245 }
12246
b34976b6 12247 return TRUE;
252b5132
RH		 12248}
12249
fc830a83 12250/* Copy backend specific data from one object module to another. */
9b485d32 12251
b34976b6 12252static bfd_boolean
57e8b36a 12253elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 12254{
12255 flagword in_flags;
12256 flagword out_flags;
12257
0ffa91dd 12258 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 12259 return TRUE;
252b5132 12260
fc830a83 12261 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 12262 out_flags = elf_elfheader (obfd)->e_flags;
12263
fc830a83
NC		 12264 if (elf_flags_init (obfd)
12265 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
12266 && in_flags != out_flags)
252b5132 12267 {
252b5132 12268 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 12269 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 12270 return FALSE;
252b5132
RH		 12271
12272 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 12273 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 12274 return FALSE;
252b5132
RH		 12275
12276 /* If the src and dest have different interworking flags
99059e56 12277 then turn off the interworking bit. */
fd2ec330 12278 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 12279 {
fd2ec330 12280 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 12281 _bfd_error_handler
12282 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
12283 obfd, ibfd);
252b5132 12284
fd2ec330 12285 in_flags &= ~EF_ARM_INTERWORK;
252b5132 12286 }
1006ba19
PB		 12287
12288 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 12289 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
12290 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 12291 }
12292
12293 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 12294 elf_flags_init (obfd) = TRUE;
252b5132 12295
e2349352 12296 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 12297}
12298
12299/* Values for Tag_ABI_PCS_R9_use. */
12300enum
12301{
12302 AEABI_R9_V6,
12303 AEABI_R9_SB,
12304 AEABI_R9_TLS,
12305 AEABI_R9_unused
12306};
12307
12308/* Values for Tag_ABI_PCS_RW_data. */
12309enum
12310{
12311 AEABI_PCS_RW_data_absolute,
12312 AEABI_PCS_RW_data_PCrel,
12313 AEABI_PCS_RW_data_SBrel,
12314 AEABI_PCS_RW_data_unused
12315};
12316
12317/* Values for Tag_ABI_enum_size. */
12318enum
12319{
12320 AEABI_enum_unused,
12321 AEABI_enum_short,
12322 AEABI_enum_wide,
12323 AEABI_enum_forced_wide
12324};
12325
104d59d1
JM		 12326/* Determine whether an object attribute tag takes an integer, a
12327 string or both. */
906e58ca 12328
104d59d1
JM		 12329static int
12330elf32_arm_obj_attrs_arg_type (int tag)
12331{
12332 if (tag == Tag_compatibility)
3483fe2e 12333 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 12334 else if (tag == Tag_nodefaults)
3483fe2e
AS		 12335 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
12336 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
12337 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 12338 else if (tag < 32)
3483fe2e 12339 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 12340 else
3483fe2e 12341 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 12342}
12343
5aa6ff7c
AS		 12344/* The ABI defines that Tag_conformance should be emitted first, and that
12345 Tag_nodefaults should be second (if either is defined). This sets those
12346 two positions, and bumps up the position of all the remaining tags to
12347 compensate. */
12348static int
12349elf32_arm_obj_attrs_order (int num)
12350{
3de4a297 12351 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 12352 return Tag_conformance;
3de4a297 12353 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 12354 return Tag_nodefaults;
12355 if ((num - 2) < Tag_nodefaults)
12356 return num - 2;
12357 if ((num - 1) < Tag_conformance)
12358 return num - 1;
12359 return num;
12360}
12361
e8b36cd1
JM		 12362/* Attribute numbers >=64 (mod 128) can be safely ignored. */
12363static bfd_boolean
12364elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
12365{
12366 if ((tag & 127) < 64)
12367 {
12368 _bfd_error_handler
12369 (_("%B: Unknown mandatory EABI object attribute %d"),
12370 abfd, tag);
12371 bfd_set_error (bfd_error_bad_value);
12372 return FALSE;
12373 }
12374 else
12375 {
12376 _bfd_error_handler
12377 (_("Warning: %B: Unknown EABI object attribute %d"),
12378 abfd, tag);
12379 return TRUE;
12380 }
12381}
12382
91e22acd
AS		 12383/* Read the architecture from the Tag_also_compatible_with attribute, if any.
12384 Returns -1 if no architecture could be read. */
12385
12386static int
12387get_secondary_compatible_arch (bfd *abfd)
12388{
12389 obj_attribute *attr =
12390 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
12391
12392 /* Note: the tag and its argument below are uleb128 values, though
12393 currently-defined values fit in one byte for each. */
12394 if (attr->s
12395 && attr->s[0] == Tag_CPU_arch
12396 && (attr->s[1] & 128) != 128
12397 && attr->s[2] == 0)
12398 return attr->s[1];
12399
12400 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12401 return -1;
12402}
12403
12404/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12405 The tag is removed if ARCH is -1. */
12406
8e79c3df 12407static void
91e22acd 12408set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 12409{
91e22acd
AS		 12410 obj_attribute *attr =
12411 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 12412
91e22acd
AS		 12413 if (arch == -1)
12414 {
12415 attr->s = NULL;
12416 return;
8e79c3df 12417 }
91e22acd
AS		 12418
12419 /* Note: the tag and its argument below are uleb128 values, though
12420 currently-defined values fit in one byte for each. */
12421 if (!attr->s)
21d799b5 12422 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 12423 attr->s[0] = Tag_CPU_arch;
12424 attr->s[1] = arch;
12425 attr->s[2] = '\0';
8e79c3df
CM		 12426}
12427
91e22acd
AS		 12428/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12429 into account. */
12430
12431static int
12432tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
12433 int newtag, int secondary_compat)
8e79c3df 12434{
91e22acd
AS		 12435#define T(X) TAG_CPU_ARCH_##X
12436 int tagl, tagh, result;
12437 const int v6t2[] =
12438 {
12439 T(V6T2), /* PRE_V4. */
12440 T(V6T2), /* V4. */
12441 T(V6T2), /* V4T. */
12442 T(V6T2), /* V5T. */
12443 T(V6T2), /* V5TE. */
12444 T(V6T2), /* V5TEJ. */
12445 T(V6T2), /* V6. */
12446 T(V7), /* V6KZ. */
12447 T(V6T2) /* V6T2. */
12448 };
12449 const int v6k[] =
12450 {
12451 T(V6K), /* PRE_V4. */
12452 T(V6K), /* V4. */
12453 T(V6K), /* V4T. */
12454 T(V6K), /* V5T. */
12455 T(V6K), /* V5TE. */
12456 T(V6K), /* V5TEJ. */
12457 T(V6K), /* V6. */
12458 T(V6KZ), /* V6KZ. */
12459 T(V7), /* V6T2. */
12460 T(V6K) /* V6K. */
12461 };
12462 const int v7[] =
12463 {
12464 T(V7), /* PRE_V4. */
12465 T(V7), /* V4. */
12466 T(V7), /* V4T. */
12467 T(V7), /* V5T. */
12468 T(V7), /* V5TE. */
12469 T(V7), /* V5TEJ. */
12470 T(V7), /* V6. */
12471 T(V7), /* V6KZ. */
12472 T(V7), /* V6T2. */
12473 T(V7), /* V6K. */
12474 T(V7) /* V7. */
12475 };
12476 const int v6_m[] =
12477 {
12478 -1, /* PRE_V4. */
12479 -1, /* V4. */
12480 T(V6K), /* V4T. */
12481 T(V6K), /* V5T. */
12482 T(V6K), /* V5TE. */
12483 T(V6K), /* V5TEJ. */
12484 T(V6K), /* V6. */
12485 T(V6KZ), /* V6KZ. */
12486 T(V7), /* V6T2. */
12487 T(V6K), /* V6K. */
12488 T(V7), /* V7. */
12489 T(V6_M) /* V6_M. */
12490 };
12491 const int v6s_m[] =
12492 {
12493 -1, /* PRE_V4. */
12494 -1, /* V4. */
12495 T(V6K), /* V4T. */
12496 T(V6K), /* V5T. */
12497 T(V6K), /* V5TE. */
12498 T(V6K), /* V5TEJ. */
12499 T(V6K), /* V6. */
12500 T(V6KZ), /* V6KZ. */
12501 T(V7), /* V6T2. */
12502 T(V6K), /* V6K. */
12503 T(V7), /* V7. */
12504 T(V6S_M), /* V6_M. */
12505 T(V6S_M) /* V6S_M. */
12506 };
9e3c6df6
PB		 12507 const int v7e_m[] =
12508 {
12509 -1, /* PRE_V4. */
12510 -1, /* V4. */
12511 T(V7E_M), /* V4T. */
12512 T(V7E_M), /* V5T. */
12513 T(V7E_M), /* V5TE. */
12514 T(V7E_M), /* V5TEJ. */
12515 T(V7E_M), /* V6. */
12516 T(V7E_M), /* V6KZ. */
12517 T(V7E_M), /* V6T2. */
12518 T(V7E_M), /* V6K. */
12519 T(V7E_M), /* V7. */
12520 T(V7E_M), /* V6_M. */
12521 T(V7E_M), /* V6S_M. */
12522 T(V7E_M) /* V7E_M. */
12523 };
bca38921
MGD		 12524 const int v8[] =
12525 {
12526 T(V8), /* PRE_V4. */
12527 T(V8), /* V4. */
12528 T(V8), /* V4T. */
12529 T(V8), /* V5T. */
12530 T(V8), /* V5TE. */
12531 T(V8), /* V5TEJ. */
12532 T(V8), /* V6. */
12533 T(V8), /* V6KZ. */
12534 T(V8), /* V6T2. */
12535 T(V8), /* V6K. */
12536 T(V8), /* V7. */
12537 T(V8), /* V6_M. */
12538 T(V8), /* V6S_M. */
12539 T(V8), /* V7E_M. */
12540 T(V8) /* V8. */
12541 };
2fd158eb
TP		 12542 const int v8m_baseline[] =
12543 {
12544 -1, /* PRE_V4. */
12545 -1, /* V4. */
12546 -1, /* V4T. */
12547 -1, /* V5T. */
12548 -1, /* V5TE. */
12549 -1, /* V5TEJ. */
12550 -1, /* V6. */
12551 -1, /* V6KZ. */
12552 -1, /* V6T2. */
12553 -1, /* V6K. */
12554 -1, /* V7. */
12555 T(V8M_BASE), /* V6_M. */
12556 T(V8M_BASE), /* V6S_M. */
12557 -1, /* V7E_M. */
12558 -1, /* V8. */
12559 -1,
12560 T(V8M_BASE) /* V8-M BASELINE. */
12561 };
12562 const int v8m_mainline[] =
12563 {
12564 -1, /* PRE_V4. */
12565 -1, /* V4. */
12566 -1, /* V4T. */
12567 -1, /* V5T. */
12568 -1, /* V5TE. */
12569 -1, /* V5TEJ. */
12570 -1, /* V6. */
12571 -1, /* V6KZ. */
12572 -1, /* V6T2. */
12573 -1, /* V6K. */
12574 T(V8M_MAIN), /* V7. */
12575 T(V8M_MAIN), /* V6_M. */
12576 T(V8M_MAIN), /* V6S_M. */
12577 T(V8M_MAIN), /* V7E_M. */
12578 -1, /* V8. */
12579 -1,
12580 T(V8M_MAIN), /* V8-M BASELINE. */
12581 T(V8M_MAIN) /* V8-M MAINLINE. */
12582 };
91e22acd
AS		 12583 const int v4t_plus_v6_m[] =
12584 {
12585 -1, /* PRE_V4. */
12586 -1, /* V4. */
12587 T(V4T), /* V4T. */
12588 T(V5T), /* V5T. */
12589 T(V5TE), /* V5TE. */
12590 T(V5TEJ), /* V5TEJ. */
12591 T(V6), /* V6. */
12592 T(V6KZ), /* V6KZ. */
12593 T(V6T2), /* V6T2. */
12594 T(V6K), /* V6K. */
12595 T(V7), /* V7. */
12596 T(V6_M), /* V6_M. */
12597 T(V6S_M), /* V6S_M. */
9e3c6df6 12598 T(V7E_M), /* V7E_M. */
bca38921 12599 T(V8), /* V8. */
4ed7ed8d 12600 -1, /* Unused. */
2fd158eb
TP		 12601 T(V8M_BASE), /* V8-M BASELINE. */
12602 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 12603 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
12604 };
12605 const int *comb[] =
12606 {
12607 v6t2,
12608 v6k,
12609 v7,
12610 v6_m,
12611 v6s_m,
9e3c6df6 12612 v7e_m,
bca38921 12613 v8,
4ed7ed8d 12614 NULL,
2fd158eb
TP		 12615 v8m_baseline,
12616 v8m_mainline,
91e22acd
AS		 12617 /* Pseudo-architecture. */
12618 v4t_plus_v6_m
12619 };
12620
12621 /* Check we've not got a higher architecture than we know about. */
12622
9e3c6df6 12623 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 12624 {
3895f852 12625 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 12626 return -1;
12627 }
12628
12629 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12630
12631 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
12632 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
12633 oldtag = T(V4T_PLUS_V6_M);
12634
12635 /* And override the new tag if we have a Tag_also_compatible_with on the
12636 input. */
12637
12638 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
12639 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
12640 newtag = T(V4T_PLUS_V6_M);
12641
12642 tagl = (oldtag < newtag) ? oldtag : newtag;
12643 result = tagh = (oldtag > newtag) ? oldtag : newtag;
12644
12645 /* Architectures before V6KZ add features monotonically. */
12646 if (tagh <= TAG_CPU_ARCH_V6KZ)
12647 return result;
12648
4ed7ed8d 12649 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 12650
12651 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
12652 as the canonical version. */
12653 if (result == T(V4T_PLUS_V6_M))
12654 {
12655 result = T(V4T);
12656 *secondary_compat_out = T(V6_M);
12657 }
12658 else
12659 *secondary_compat_out = -1;
12660
12661 if (result == -1)
12662 {
3895f852 12663 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 12664 ibfd, oldtag, newtag);
12665 return -1;
12666 }
12667
12668 return result;
12669#undef T
8e79c3df
CM		 12670}
12671
ac56ee8f
MGD		 12672/* Query attributes object to see if integer divide instructions may be
12673 present in an object. */
12674static bfd_boolean
12675elf32_arm_attributes_accept_div (const obj_attribute *attr)
12676{
12677 int arch = attr[Tag_CPU_arch].i;
12678 int profile = attr[Tag_CPU_arch_profile].i;
12679
12680 switch (attr[Tag_DIV_use].i)
12681 {
12682 case 0:
12683 /* Integer divide allowed if instruction contained in archetecture. */
12684 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
12685 return TRUE;
12686 else if (arch >= TAG_CPU_ARCH_V7E_M)
12687 return TRUE;
12688 else
12689 return FALSE;
12690
12691 case 1:
12692 /* Integer divide explicitly prohibited. */
12693 return FALSE;
12694
12695 default:
12696 /* Unrecognised case - treat as allowing divide everywhere. */
12697 case 2:
12698 /* Integer divide allowed in ARM state. */
12699 return TRUE;
12700 }
12701}
12702
12703/* Query attributes object to see if integer divide instructions are
12704 forbidden to be in the object. This is not the inverse of
12705 elf32_arm_attributes_accept_div. */
12706static bfd_boolean
12707elf32_arm_attributes_forbid_div (const obj_attribute *attr)
12708{
12709 return attr[Tag_DIV_use].i == 1;
12710}
12711
ee065d83
PB		 12712/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
12713 are conflicting attributes. */
906e58ca 12714
ee065d83
PB		 12715static bfd_boolean
12716elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
12717{
104d59d1
JM		 12718 obj_attribute *in_attr;
12719 obj_attribute *out_attr;
ee065d83
PB		 12720 /* Some tags have 0 = don't care, 1 = strong requirement,
12721 2 = weak requirement. */
91e22acd 12722 static const int order_021[3] = {0, 2, 1};
ee065d83 12723 int i;
91e22acd 12724 bfd_boolean result = TRUE;
9274e9de 12725 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 12726
3e6b1042
DJ		 12727 /* Skip the linker stubs file. This preserves previous behavior
12728 of accepting unknown attributes in the first input file - but
12729 is that a bug? */
12730 if (ibfd->flags & BFD_LINKER_CREATED)
12731 return TRUE;
12732
9274e9de
TG		 12733 /* Skip any input that hasn't attribute section.
12734 This enables to link object files without attribute section with
12735 any others. */
12736 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
12737 return TRUE;
12738
104d59d1 12739 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 12740 {
12741 /* This is the first object. Copy the attributes. */
104d59d1 12742 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 12743
cd21e546
MGD		 12744 out_attr = elf_known_obj_attributes_proc (obfd);
12745
004ae526
PB		 12746 /* Use the Tag_null value to indicate the attributes have been
12747 initialized. */
cd21e546 12748 out_attr[0].i = 1;
004ae526 12749
cd21e546
MGD		 12750 /* We do not output objects with Tag_MPextension_use_legacy - we move
12751 the attribute's value to Tag_MPextension_use. */
12752 if (out_attr[Tag_MPextension_use_legacy].i != 0)
12753 {
12754 if (out_attr[Tag_MPextension_use].i != 0
12755 && out_attr[Tag_MPextension_use_legacy].i
99059e56 12756 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 12757 {
12758 _bfd_error_handler
12759 (_("Error: %B has both the current and legacy "
12760 "Tag_MPextension_use attributes"), ibfd);
12761 result = FALSE;
12762 }
12763
12764 out_attr[Tag_MPextension_use] =
12765 out_attr[Tag_MPextension_use_legacy];
12766 out_attr[Tag_MPextension_use_legacy].type = 0;
12767 out_attr[Tag_MPextension_use_legacy].i = 0;
12768 }
12769
12770 return result;
ee065d83
PB		 12771 }
12772
104d59d1
JM		 12773 in_attr = elf_known_obj_attributes_proc (ibfd);
12774 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 12775 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
12776 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
12777 {
5c294fee
TG		 12778 /* Ignore mismatches if the object doesn't use floating point or is
12779 floating point ABI independent. */
12780 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
12781 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12782 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 12783 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 12784 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12785 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 12786 {
12787 _bfd_error_handler
3895f852 12788 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 12789 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
12790 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 12791 result = FALSE;
ee065d83
PB		 12792 }
12793 }
12794
3de4a297 12795 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 12796 {
12797 /* Merge this attribute with existing attributes. */
12798 switch (i)
12799 {
12800 case Tag_CPU_raw_name:
12801 case Tag_CPU_name:
6a631e86 12802 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 12803 break;
12804
12805 case Tag_ABI_optimization_goals:
12806 case Tag_ABI_FP_optimization_goals:
12807 /* Use the first value seen. */
12808 break;
12809
12810 case Tag_CPU_arch:
91e22acd
AS		 12811 {
12812 int secondary_compat = -1, secondary_compat_out = -1;
12813 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 12814 int arch_attr;
12815 static const char *name_table[] =
12816 {
91e22acd
AS		 12817 /* These aren't real CPU names, but we can't guess
12818 that from the architecture version alone. */
12819 "Pre v4",
12820 "ARM v4",
12821 "ARM v4T",
12822 "ARM v5T",
12823 "ARM v5TE",
12824 "ARM v5TEJ",
12825 "ARM v6",
12826 "ARM v6KZ",
12827 "ARM v6T2",
12828 "ARM v6K",
12829 "ARM v7",
12830 "ARM v6-M",
bca38921 12831 "ARM v6S-M",
2fd158eb
TP		 12832 "ARM v8",
12833 "",
12834 "ARM v8-M.baseline",
12835 "ARM v8-M.mainline",
91e22acd
AS		 12836 };
12837
12838 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
12839 secondary_compat = get_secondary_compatible_arch (ibfd);
12840 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 12841 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
12842 &secondary_compat_out,
12843 in_attr[i].i,
12844 secondary_compat);
12845
12846 /* Return with error if failed to merge. */
12847 if (arch_attr == -1)
12848 return FALSE;
12849
12850 out_attr[i].i = arch_attr;
12851
91e22acd
AS		 12852 set_secondary_compatible_arch (obfd, secondary_compat_out);
12853
12854 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
12855 if (out_attr[i].i == saved_out_attr)
12856 ; /* Leave the names alone. */
12857 else if (out_attr[i].i == in_attr[i].i)
12858 {
12859 /* The output architecture has been changed to match the
12860 input architecture. Use the input names. */
12861 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
12862 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
12863 : NULL;
12864 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
12865 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
12866 : NULL;
12867 }
12868 else
12869 {
12870 out_attr[Tag_CPU_name].s = NULL;
12871 out_attr[Tag_CPU_raw_name].s = NULL;
12872 }
12873
12874 /* If we still don't have a value for Tag_CPU_name,
12875 make one up now. Tag_CPU_raw_name remains blank. */
12876 if (out_attr[Tag_CPU_name].s == NULL
12877 && out_attr[i].i < ARRAY_SIZE (name_table))
12878 out_attr[Tag_CPU_name].s =
12879 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
12880 }
12881 break;
12882
ee065d83
PB		 12883 case Tag_ARM_ISA_use:
12884 case Tag_THUMB_ISA_use:
ee065d83 12885 case Tag_WMMX_arch:
91e22acd
AS		 12886 case Tag_Advanced_SIMD_arch:
12887 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 12888 case Tag_ABI_FP_rounding:
ee065d83
PB		 12889 case Tag_ABI_FP_exceptions:
12890 case Tag_ABI_FP_user_exceptions:
12891 case Tag_ABI_FP_number_model:
75375b3e 12892 case Tag_FP_HP_extension:
91e22acd
AS		 12893 case Tag_CPU_unaligned_access:
12894 case Tag_T2EE_use:
91e22acd 12895 case Tag_MPextension_use:
ee065d83
PB		 12896 /* Use the largest value specified. */
12897 if (in_attr[i].i > out_attr[i].i)
12898 out_attr[i].i = in_attr[i].i;
12899 break;
12900
75375b3e 12901 case Tag_ABI_align_preserved:
91e22acd
AS		 12902 case Tag_ABI_PCS_RO_data:
12903 /* Use the smallest value specified. */
12904 if (in_attr[i].i < out_attr[i].i)
12905 out_attr[i].i = in_attr[i].i;
12906 break;
12907
75375b3e 12908 case Tag_ABI_align_needed:
91e22acd 12909 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 12910 && (in_attr[Tag_ABI_align_preserved].i == 0
12911 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 12912 {
91e22acd
AS		 12913 /* This error message should be enabled once all non-conformant
12914 binaries in the toolchain have had the attributes set
12915 properly.
ee065d83 12916 _bfd_error_handler
3895f852 12917 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 12918 obfd, ibfd);
12919 result = FALSE; */
ee065d83 12920 }
91e22acd
AS		 12921 /* Fall through. */
12922 case Tag_ABI_FP_denormal:
12923 case Tag_ABI_PCS_GOT_use:
12924 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
12925 value if greater than 2 (for future-proofing). */
12926 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
12927 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
12928 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 12929 out_attr[i].i = in_attr[i].i;
12930 break;
91e22acd 12931
75375b3e
MGD		 12932 case Tag_Virtualization_use:
12933 /* The virtualization tag effectively stores two bits of
12934 information: the intended use of TrustZone (in bit 0), and the
12935 intended use of Virtualization (in bit 1). */
12936 if (out_attr[i].i == 0)
12937 out_attr[i].i = in_attr[i].i;
12938 else if (in_attr[i].i != 0
12939 && in_attr[i].i != out_attr[i].i)
12940 {
12941 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
12942 out_attr[i].i = 3;
12943 else
12944 {
12945 _bfd_error_handler
12946 (_("error: %B: unable to merge virtualization attributes "
12947 "with %B"),
12948 obfd, ibfd);
12949 result = FALSE;
12950 }
12951 }
12952 break;
91e22acd
AS		 12953
12954 case Tag_CPU_arch_profile:
12955 if (out_attr[i].i != in_attr[i].i)
12956 {
12957 /* 0 will merge with anything.
12958 'A' and 'S' merge to 'A'.
12959 'R' and 'S' merge to 'R'.
99059e56 12960 'M' and 'A|R|S' is an error. */
91e22acd
AS		 12961 if (out_attr[i].i == 0
12962 || (out_attr[i].i == 'S'
12963 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
12964 out_attr[i].i = in_attr[i].i;
12965 else if (in_attr[i].i == 0
12966 || (in_attr[i].i == 'S'
12967 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 12968 ; /* Do nothing. */
91e22acd
AS		 12969 else
12970 {
12971 _bfd_error_handler
3895f852 12972 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 12973 ibfd,
12974 in_attr[i].i ? in_attr[i].i : '0',
12975 out_attr[i].i ? out_attr[i].i : '0');
12976 result = FALSE;
12977 }
12978 }
12979 break;
15afaa63
TP		 12980
12981 case Tag_DSP_extension:
12982 /* No need to change output value if any of:
12983 - pre (<=) ARMv5T input architecture (do not have DSP)
12984 - M input profile not ARMv7E-M and do not have DSP. */
12985 if (in_attr[Tag_CPU_arch].i <= 3
12986 || (in_attr[Tag_CPU_arch_profile].i == 'M'
12987 && in_attr[Tag_CPU_arch].i != 13
12988 && in_attr[i].i == 0))
12989 ; /* Do nothing. */
12990 /* Output value should be 0 if DSP part of architecture, ie.
12991 - post (>=) ARMv5te architecture output
12992 - A, R or S profile output or ARMv7E-M output architecture. */
12993 else if (out_attr[Tag_CPU_arch].i >= 4
12994 && (out_attr[Tag_CPU_arch_profile].i == 'A'
12995 || out_attr[Tag_CPU_arch_profile].i == 'R'
12996 || out_attr[Tag_CPU_arch_profile].i == 'S'
12997 || out_attr[Tag_CPU_arch].i == 13))
12998 out_attr[i].i = 0;
12999 /* Otherwise, DSP instructions are added and not part of output
13000 architecture. */
13001 else
13002 out_attr[i].i = 1;
13003 break;
13004
75375b3e 13005 case Tag_FP_arch:
62f3b8c8 13006 {
4547cb56
NC		 13007 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13008 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13009 when it's 0. It might mean absence of FP hardware if
99654aaf 13010 Tag_FP_arch is zero. */
4547cb56 13011
a715796b 13012#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13013 static const struct
13014 {
13015 int ver;
13016 int regs;
bca38921 13017 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13018 {
13019 {0, 0},
13020 {1, 16},
13021 {2, 16},
13022 {3, 32},
13023 {3, 16},
13024 {4, 32},
bca38921 13025 {4, 16},
a715796b
TG		 13026 {8, 32},
13027 {8, 16}
62f3b8c8
PB		 13028 };
13029 int ver;
13030 int regs;
13031 int newval;
13032
4547cb56
NC		 13033 /* If the output has no requirement about FP hardware,
13034 follow the requirement of the input. */
13035 if (out_attr[i].i == 0)
13036 {
13037 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13038 out_attr[i].i = in_attr[i].i;
13039 out_attr[Tag_ABI_HardFP_use].i
13040 = in_attr[Tag_ABI_HardFP_use].i;
13041 break;
13042 }
13043 /* If the input has no requirement about FP hardware, do
13044 nothing. */
13045 else if (in_attr[i].i == 0)
13046 {
13047 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
13048 break;
13049 }
13050
13051 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13052 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13053
13054 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13055 do nothing. */
13056 if (in_attr[Tag_ABI_HardFP_use].i == 0
13057 && out_attr[Tag_ABI_HardFP_use].i == 0)
13058 ;
13059 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13060 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13061 else if (in_attr[Tag_ABI_HardFP_use].i
13062 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13063 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13064
13065 /* Now we can handle Tag_FP_arch. */
13066
bca38921
MGD		 13067 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13068 pick the biggest. */
13069 if (in_attr[i].i >= VFP_VERSION_COUNT
13070 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13071 {
13072 out_attr[i] = in_attr[i];
13073 break;
13074 }
13075 /* The output uses the superset of input features
13076 (ISA version) and registers. */
13077 ver = vfp_versions[in_attr[i].i].ver;
13078 if (ver < vfp_versions[out_attr[i].i].ver)
13079 ver = vfp_versions[out_attr[i].i].ver;
13080 regs = vfp_versions[in_attr[i].i].regs;
13081 if (regs < vfp_versions[out_attr[i].i].regs)
13082 regs = vfp_versions[out_attr[i].i].regs;
13083 /* This assumes all possible supersets are also a valid
99059e56 13084 options. */
bca38921 13085 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13086 {
13087 if (regs == vfp_versions[newval].regs
13088 && ver == vfp_versions[newval].ver)
13089 break;
13090 }
13091 out_attr[i].i = newval;
13092 }
b1cc4aeb 13093 break;
ee065d83
PB		 13094 case Tag_PCS_config:
13095 if (out_attr[i].i == 0)
13096 out_attr[i].i = in_attr[i].i;
b6009aca 13097 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13098 {
13099 /* It's sometimes ok to mix different configs, so this is only
99059e56 13100 a warning. */
ee065d83
PB		 13101 _bfd_error_handler
13102 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13103 }
13104 break;
13105 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13106 if (in_attr[i].i != out_attr[i].i
13107 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13108 && in_attr[i].i != AEABI_R9_unused)
13109 {
13110 _bfd_error_handler
3895f852 13111 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13112 result = FALSE;
ee065d83
PB		 13113 }
13114 if (out_attr[i].i == AEABI_R9_unused)
13115 out_attr[i].i = in_attr[i].i;
13116 break;
13117 case Tag_ABI_PCS_RW_data:
13118 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13119 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13120 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13121 {
13122 _bfd_error_handler
3895f852 13123 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13124 ibfd);
91e22acd 13125 result = FALSE;
ee065d83
PB		 13126 }
13127 /* Use the smallest value specified. */
13128 if (in_attr[i].i < out_attr[i].i)
13129 out_attr[i].i = in_attr[i].i;
13130 break;
ee065d83 13131 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13132 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13133 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13134 {
13135 _bfd_error_handler
a9dc9481
JM		 13136 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13137 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13138 }
a9dc9481 13139 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13140 out_attr[i].i = in_attr[i].i;
13141 break;
ee065d83
PB		 13142 case Tag_ABI_enum_size:
13143 if (in_attr[i].i != AEABI_enum_unused)
13144 {
13145 if (out_attr[i].i == AEABI_enum_unused
13146 || out_attr[i].i == AEABI_enum_forced_wide)
13147 {
13148 /* The existing object is compatible with anything.
13149 Use whatever requirements the new object has. */
13150 out_attr[i].i = in_attr[i].i;
13151 }
13152 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13153 && out_attr[i].i != in_attr[i].i
0ffa91dd 13154 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13155 {
91e22acd 13156 static const char *aeabi_enum_names[] =
bf21ed78 13157 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13158 const char *in_name =
13159 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13160 ? aeabi_enum_names[in_attr[i].i]
13161 : "<unknown>";
13162 const char *out_name =
13163 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13164 ? aeabi_enum_names[out_attr[i].i]
13165 : "<unknown>";
ee065d83 13166 _bfd_error_handler
bf21ed78 13167 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13168 ibfd, in_name, out_name);
ee065d83
PB		 13169 }
13170 }
13171 break;
13172 case Tag_ABI_VFP_args:
13173 /* Aready done. */
13174 break;
13175 case Tag_ABI_WMMX_args:
13176 if (in_attr[i].i != out_attr[i].i)
13177 {
13178 _bfd_error_handler
3895f852 13179 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13180 ibfd, obfd);
91e22acd 13181 result = FALSE;
ee065d83
PB		 13182 }
13183 break;
7b86a9fa
AS		 13184 case Tag_compatibility:
13185 /* Merged in target-independent code. */
13186 break;
91e22acd 13187 case Tag_ABI_HardFP_use:
4547cb56 13188 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13189 break;
13190 case Tag_ABI_FP_16bit_format:
13191 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13192 {
13193 if (in_attr[i].i != out_attr[i].i)
13194 {
13195 _bfd_error_handler
3895f852 13196 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13197 ibfd, obfd);
13198 result = FALSE;
13199 }
13200 }
13201 if (in_attr[i].i != 0)
13202 out_attr[i].i = in_attr[i].i;
13203 break;
7b86a9fa 13204
cd21e546 13205 case Tag_DIV_use:
ac56ee8f
MGD		 13206 /* A value of zero on input means that the divide instruction may
13207 be used if available in the base architecture as specified via
13208 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
13209 the user did not want divide instructions. A value of 2
13210 explicitly means that divide instructions were allowed in ARM
13211 and Thumb state. */
13212 if (in_attr[i].i == out_attr[i].i)
13213 /* Do nothing. */ ;
13214 else if (elf32_arm_attributes_forbid_div (in_attr)
13215 && !elf32_arm_attributes_accept_div (out_attr))
13216 out_attr[i].i = 1;
13217 else if (elf32_arm_attributes_forbid_div (out_attr)
13218 && elf32_arm_attributes_accept_div (in_attr))
13219 out_attr[i].i = in_attr[i].i;
13220 else if (in_attr[i].i == 2)
13221 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 13222 break;
13223
13224 case Tag_MPextension_use_legacy:
13225 /* We don't output objects with Tag_MPextension_use_legacy - we
13226 move the value to Tag_MPextension_use. */
13227 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
13228 {
13229 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
13230 {
13231 _bfd_error_handler
13232 (_("%B has has both the current and legacy "
b38cadfb 13233 "Tag_MPextension_use attributes"),
cd21e546
MGD		 13234 ibfd);
13235 result = FALSE;
13236 }
13237 }
13238
13239 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
13240 out_attr[Tag_MPextension_use] = in_attr[i];
13241
13242 break;
13243
91e22acd 13244 case Tag_nodefaults:
2d0bb761
AS		 13245 /* This tag is set if it exists, but the value is unused (and is
13246 typically zero). We don't actually need to do anything here -
13247 the merge happens automatically when the type flags are merged
13248 below. */
91e22acd
AS		 13249 break;
13250 case Tag_also_compatible_with:
13251 /* Already done in Tag_CPU_arch. */
13252 break;
13253 case Tag_conformance:
13254 /* Keep the attribute if it matches. Throw it away otherwise.
13255 No attribute means no claim to conform. */
13256 if (!in_attr[i].s || !out_attr[i].s
13257 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
13258 out_attr[i].s = NULL;
13259 break;
3cfad14c 13260
91e22acd 13261 default:
e8b36cd1
JM		 13262 result
13263 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 13264 }
13265
13266 /* If out_attr was copied from in_attr then it won't have a type yet. */
13267 if (in_attr[i].type && !out_attr[i].type)
13268 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 13269 }
13270
104d59d1 13271 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 13272 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
13273 return FALSE;
ee065d83 13274
104d59d1 13275 /* Check for any attributes not known on ARM. */
e8b36cd1 13276 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 13277
91e22acd 13278 return result;
252b5132
RH		 13279}
13280
3a4a14e9
PB		 13281
13282/* Return TRUE if the two EABI versions are incompatible. */
13283
13284static bfd_boolean
13285elf32_arm_versions_compatible (unsigned iver, unsigned over)
13286{
13287 /* v4 and v5 are the same spec before and after it was released,
13288 so allow mixing them. */
13289 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
13290 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
13291 return TRUE;
13292
13293 return (iver == over);
13294}
13295
252b5132
RH		 13296/* Merge backend specific data from an object file to the output
13297 object file when linking. */
9b485d32 13298
b34976b6 13299static bfd_boolean
21d799b5 13300elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 13301
9b485d32
NC		 13302/* Display the flags field. */
13303
b34976b6 13304static bfd_boolean
57e8b36a 13305elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 13306{
fc830a83
NC		 13307 FILE * file = (FILE *) ptr;
13308 unsigned long flags;
252b5132
RH		 13309
13310 BFD_ASSERT (abfd != NULL && ptr != NULL);
13311
13312 /* Print normal ELF private data. */
13313 _bfd_elf_print_private_bfd_data (abfd, ptr);
13314
fc830a83 13315 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 13316 /* Ignore init flag - it may not be set, despite the flags field
13317 containing valid data. */
252b5132
RH		 13318
13319 /* xgettext:c-format */
9b485d32 13320 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 13321
fc830a83
NC		 13322 switch (EF_ARM_EABI_VERSION (flags))
13323 {
13324 case EF_ARM_EABI_UNKNOWN:
4cc11e76 13325 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 13326 official ARM ELF extended ABI. Hence they are only decoded if
13327 the EABI version is not set. */
fd2ec330 13328 if (flags & EF_ARM_INTERWORK)
9b485d32 13329 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 13330
fd2ec330 13331 if (flags & EF_ARM_APCS_26)
6c571f00 13332 fprintf (file, " [APCS-26]");
fc830a83 13333 else
6c571f00 13334 fprintf (file, " [APCS-32]");
9a5aca8c 13335
96a846ea
RE		 13336 if (flags & EF_ARM_VFP_FLOAT)
13337 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 13338 else if (flags & EF_ARM_MAVERICK_FLOAT)
13339 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 13340 else
13341 fprintf (file, _(" [FPA float format]"));
13342
fd2ec330 13343 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 13344 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 13345
fd2ec330 13346 if (flags & EF_ARM_PIC)
9b485d32 13347 fprintf (file, _(" [position independent]"));
fc830a83 13348
fd2ec330 13349 if (flags & EF_ARM_NEW_ABI)
9b485d32 13350 fprintf (file, _(" [new ABI]"));
9a5aca8c 13351
fd2ec330 13352 if (flags & EF_ARM_OLD_ABI)
9b485d32 13353 fprintf (file, _(" [old ABI]"));
9a5aca8c 13354
fd2ec330 13355 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 13356 fprintf (file, _(" [software FP]"));
9a5aca8c 13357
96a846ea
RE		 13358 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
13359 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 13360 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
13361 | EF_ARM_MAVERICK_FLOAT);
fc830a83 13362 break;
9a5aca8c 13363
fc830a83 13364 case EF_ARM_EABI_VER1:
9b485d32 13365 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 13366
fc830a83 13367 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 13368 fprintf (file, _(" [sorted symbol table]"));
fc830a83 13369 else
9b485d32 13370 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 13371
fc830a83
NC		 13372 flags &= ~ EF_ARM_SYMSARESORTED;
13373 break;
9a5aca8c 13374
fd2ec330
PB		 13375 case EF_ARM_EABI_VER2:
13376 fprintf (file, _(" [Version2 EABI]"));
13377
13378 if (flags & EF_ARM_SYMSARESORTED)
13379 fprintf (file, _(" [sorted symbol table]"));
13380 else
13381 fprintf (file, _(" [unsorted symbol table]"));
13382
13383 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
13384 fprintf (file, _(" [dynamic symbols use segment index]"));
13385
13386 if (flags & EF_ARM_MAPSYMSFIRST)
13387 fprintf (file, _(" [mapping symbols precede others]"));
13388
99e4ae17 13389 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 13390 | EF_ARM_MAPSYMSFIRST);
13391 break;
13392
d507cf36
PB		 13393 case EF_ARM_EABI_VER3:
13394 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 13395 break;
13396
13397 case EF_ARM_EABI_VER4:
13398 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 13399 goto eabi;
d507cf36 13400
3a4a14e9
PB		 13401 case EF_ARM_EABI_VER5:
13402 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 13403
13404 if (flags & EF_ARM_ABI_FLOAT_SOFT)
13405 fprintf (file, _(" [soft-float ABI]"));
13406
13407 if (flags & EF_ARM_ABI_FLOAT_HARD)
13408 fprintf (file, _(" [hard-float ABI]"));
13409
13410 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
13411
3a4a14e9 13412 eabi:
d507cf36
PB		 13413 if (flags & EF_ARM_BE8)
13414 fprintf (file, _(" [BE8]"));
13415
13416 if (flags & EF_ARM_LE8)
13417 fprintf (file, _(" [LE8]"));
13418
13419 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
13420 break;
13421
fc830a83 13422 default:
9b485d32 13423 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 13424 break;
13425 }
252b5132 13426
fc830a83 13427 flags &= ~ EF_ARM_EABIMASK;
252b5132 13428
fc830a83 13429 if (flags & EF_ARM_RELEXEC)
9b485d32 13430 fprintf (file, _(" [relocatable executable]"));
252b5132 13431
a5721edd 13432 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 13433
13434 if (flags)
9b485d32 13435 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 13436
252b5132
RH		 13437 fputc ('\n', file);
13438
b34976b6 13439 return TRUE;
252b5132
RH		 13440}
13441
13442static int
57e8b36a 13443elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 13444{
2f0ca46a
NC		 13445 switch (ELF_ST_TYPE (elf_sym->st_info))
13446 {
13447 case STT_ARM_TFUNC:
13448 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 13449
2f0ca46a
NC		 13450 case STT_ARM_16BIT:
13451 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13452 This allows us to distinguish between data used by Thumb instructions
13453 and non-data (which is probably code) inside Thumb regions of an
13454 executable. */
1a0eb693 13455 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 13456 return ELF_ST_TYPE (elf_sym->st_info);
13457 break;
9a5aca8c 13458
ce855c42
NC		 13459 default:
13460 break;
2f0ca46a
NC		 13461 }
13462
13463 return type;
252b5132 13464}
f21f3fe0 13465
252b5132 13466static asection *
07adf181
AM		 13467elf32_arm_gc_mark_hook (asection *sec,
13468 struct bfd_link_info *info,
13469 Elf_Internal_Rela *rel,
13470 struct elf_link_hash_entry *h,
13471 Elf_Internal_Sym *sym)
252b5132
RH		 13472{
13473 if (h != NULL)
07adf181 13474 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 13475 {
13476 case R_ARM_GNU_VTINHERIT:
13477 case R_ARM_GNU_VTENTRY:
07adf181
AM		 13478 return NULL;
13479 }
9ad5cbcf 13480
07adf181 13481 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 13482}
13483
780a67af
NC		 13484/* Update the got entry reference counts for the section being removed. */
13485
b34976b6 13486static bfd_boolean
ba93b8ac
DJ		 13487elf32_arm_gc_sweep_hook (bfd * abfd,
13488 struct bfd_link_info * info,
13489 asection * sec,
13490 const Elf_Internal_Rela * relocs)
252b5132 13491{
5e681ec4
PB		 13492 Elf_Internal_Shdr *symtab_hdr;
13493 struct elf_link_hash_entry **sym_hashes;
13494 bfd_signed_vma *local_got_refcounts;
13495 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 13496 struct elf32_arm_link_hash_table * globals;
13497
0e1862bb 13498 if (bfd_link_relocatable (info))
7dda2462
TG		 13499 return TRUE;
13500
eb043451 13501 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13502 if (globals == NULL)
13503 return FALSE;
5e681ec4
PB		 13504
13505 elf_section_data (sec)->local_dynrel = NULL;
13506
0ffa91dd 13507 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 13508 sym_hashes = elf_sym_hashes (abfd);
13509 local_got_refcounts = elf_local_got_refcounts (abfd);
13510
906e58ca 13511 check_use_blx (globals);
bd97cb95 13512
5e681ec4
PB		 13513 relend = relocs + sec->reloc_count;
13514 for (rel = relocs; rel < relend; rel++)
eb043451 13515 {
3eb128b2
AM		 13516 unsigned long r_symndx;
13517 struct elf_link_hash_entry *h = NULL;
f6e32f6d 13518 struct elf32_arm_link_hash_entry *eh;
eb043451 13519 int r_type;
34e77a92 13520 bfd_boolean call_reloc_p;
f6e32f6d
RS		 13521 bfd_boolean may_become_dynamic_p;
13522 bfd_boolean may_need_local_target_p;
34e77a92
RS		 13523 union gotplt_union *root_plt;
13524 struct arm_plt_info *arm_plt;
5e681ec4 13525
3eb128b2
AM		 13526 r_symndx = ELF32_R_SYM (rel->r_info);
13527 if (r_symndx >= symtab_hdr->sh_info)
13528 {
13529 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13530 while (h->root.type == bfd_link_hash_indirect
13531 || h->root.type == bfd_link_hash_warning)
13532 h = (struct elf_link_hash_entry *) h->root.u.i.link;
13533 }
f6e32f6d
RS		 13534 eh = (struct elf32_arm_link_hash_entry *) h;
13535
34e77a92 13536 call_reloc_p = FALSE;
f6e32f6d
RS		 13537 may_become_dynamic_p = FALSE;
13538 may_need_local_target_p = FALSE;
3eb128b2 13539
eb043451 13540 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13541 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 13542 switch (r_type)
13543 {
13544 case R_ARM_GOT32:
eb043451 13545 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13546 case R_ARM_TLS_GD32:
13547 case R_ARM_TLS_IE32:
3eb128b2 13548 if (h != NULL)
eb043451 13549 {
eb043451
PB		 13550 if (h->got.refcount > 0)
13551 h->got.refcount -= 1;
13552 }
13553 else if (local_got_refcounts != NULL)
13554 {
13555 if (local_got_refcounts[r_symndx] > 0)
13556 local_got_refcounts[r_symndx] -= 1;
13557 }
13558 break;
13559
ba93b8ac 13560 case R_ARM_TLS_LDM32:
4dfe6ac6 13561 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 13562 break;
13563
eb043451
PB		 13564 case R_ARM_PC24:
13565 case R_ARM_PLT32:
5b5bb741
PB		 13566 case R_ARM_CALL:
13567 case R_ARM_JUMP24:
eb043451 13568 case R_ARM_PREL31:
c19d1205 13569 case R_ARM_THM_CALL:
bd97cb95
DJ		 13570 case R_ARM_THM_JUMP24:
13571 case R_ARM_THM_JUMP19:
34e77a92 13572 call_reloc_p = TRUE;
f6e32f6d
RS		 13573 may_need_local_target_p = TRUE;
13574 break;
13575
13576 case R_ARM_ABS12:
13577 if (!globals->vxworks_p)
13578 {
13579 may_need_local_target_p = TRUE;
13580 break;
13581 }
13582 /* Fall through. */
13583 case R_ARM_ABS32:
13584 case R_ARM_ABS32_NOI:
13585 case R_ARM_REL32:
13586 case R_ARM_REL32_NOI:
b6895b4f
PB		 13587 case R_ARM_MOVW_ABS_NC:
13588 case R_ARM_MOVT_ABS:
13589 case R_ARM_MOVW_PREL_NC:
13590 case R_ARM_MOVT_PREL:
13591 case R_ARM_THM_MOVW_ABS_NC:
13592 case R_ARM_THM_MOVT_ABS:
13593 case R_ARM_THM_MOVW_PREL_NC:
13594 case R_ARM_THM_MOVT_PREL:
b7693d02 13595 /* Should the interworking branches be here also? */
0e1862bb 13596 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 13597 && (sec->flags & SEC_ALLOC) != 0)
13598 {
13599 if (h == NULL
469a3493 13600 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13601 {
13602 call_reloc_p = TRUE;
13603 may_need_local_target_p = TRUE;
13604 }
13605 else
13606 may_become_dynamic_p = TRUE;
13607 }
f6e32f6d
RS		 13608 else
13609 may_need_local_target_p = TRUE;
13610 break;
b7693d02 13611
f6e32f6d
RS		 13612 default:
13613 break;
13614 }
5e681ec4 13615
34e77a92
RS		 13616 if (may_need_local_target_p
13617 && elf32_arm_get_plt_info (abfd, eh, r_symndx, &root_plt, &arm_plt))
f6e32f6d 13618 {
27586251
HPN		 13619 /* If PLT refcount book-keeping is wrong and too low, we'll
13620 see a zero value (going to -1) for the root PLT reference
13621 count. */
13622 if (root_plt->refcount >= 0)
13623 {
13624 BFD_ASSERT (root_plt->refcount != 0);
13625 root_plt->refcount -= 1;
13626 }
13627 else
13628 /* A value of -1 means the symbol has become local, forced
13629 or seeing a hidden definition. Any other negative value
13630 is an error. */
13631 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 13632
13633 if (!call_reloc_p)
13634 arm_plt->noncall_refcount--;
5e681ec4 13635
f6e32f6d 13636 if (r_type == R_ARM_THM_CALL)
34e77a92 13637 arm_plt->maybe_thumb_refcount--;
bd97cb95 13638
f6e32f6d
RS		 13639 if (r_type == R_ARM_THM_JUMP24
13640 || r_type == R_ARM_THM_JUMP19)
34e77a92 13641 arm_plt->thumb_refcount--;
f6e32f6d 13642 }
5e681ec4 13643
34e77a92 13644 if (may_become_dynamic_p)
f6e32f6d
RS		 13645 {
13646 struct elf_dyn_relocs **pp;
13647 struct elf_dyn_relocs *p;
5e681ec4 13648
34e77a92 13649 if (h != NULL)
9c489990 13650 pp = &(eh->dyn_relocs);
34e77a92
RS		 13651 else
13652 {
13653 Elf_Internal_Sym *isym;
13654
13655 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
13656 abfd, r_symndx);
13657 if (isym == NULL)
13658 return FALSE;
13659 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13660 if (pp == NULL)
13661 return FALSE;
13662 }
9c489990 13663 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 13664 if (p->sec == sec)
13665 {
13666 /* Everything must go for SEC. */
13667 *pp = p->next;
13668 break;
13669 }
eb043451
PB		 13670 }
13671 }
5e681ec4 13672
b34976b6 13673 return TRUE;
252b5132
RH		 13674}
13675
780a67af
NC		 13676/* Look through the relocs for a section during the first phase. */
13677
b34976b6 13678static bfd_boolean
57e8b36a
NC		 13679elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
13680 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 13681{
b34976b6
AM		 13682 Elf_Internal_Shdr *symtab_hdr;
13683 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 13684 const Elf_Internal_Rela *rel;
13685 const Elf_Internal_Rela *rel_end;
13686 bfd *dynobj;
5e681ec4 13687 asection *sreloc;
5e681ec4 13688 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 13689 bfd_boolean call_reloc_p;
13690 bfd_boolean may_become_dynamic_p;
13691 bfd_boolean may_need_local_target_p;
ce98a316 13692 unsigned long nsyms;
9a5aca8c 13693
0e1862bb 13694 if (bfd_link_relocatable (info))
b34976b6 13695 return TRUE;
9a5aca8c 13696
0ffa91dd
NC		 13697 BFD_ASSERT (is_arm_elf (abfd));
13698
5e681ec4 13699 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13700 if (htab == NULL)
13701 return FALSE;
13702
5e681ec4 13703 sreloc = NULL;
9a5aca8c 13704
67687978
PB		 13705 /* Create dynamic sections for relocatable executables so that we can
13706 copy relocations. */
13707 if (htab->root.is_relocatable_executable
13708 && ! htab->root.dynamic_sections_created)
13709 {
13710 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
13711 return FALSE;
13712 }
13713
cbc704f3
RS		 13714 if (htab->root.dynobj == NULL)
13715 htab->root.dynobj = abfd;
34e77a92
RS		 13716 if (!create_ifunc_sections (info))
13717 return FALSE;
cbc704f3
RS		 13718
13719 dynobj = htab->root.dynobj;
13720
0ffa91dd 13721 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 13722 sym_hashes = elf_sym_hashes (abfd);
ce98a316 13723 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 13724
252b5132
RH		 13725 rel_end = relocs + sec->reloc_count;
13726 for (rel = relocs; rel < rel_end; rel++)
13727 {
34e77a92 13728 Elf_Internal_Sym *isym;
252b5132 13729 struct elf_link_hash_entry *h;
b7693d02 13730 struct elf32_arm_link_hash_entry *eh;
252b5132 13731 unsigned long r_symndx;
eb043451 13732 int r_type;
9a5aca8c 13733
252b5132 13734 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 13735 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13736 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 13737
ce98a316
NC		 13738 if (r_symndx >= nsyms
13739 /* PR 9934: It is possible to have relocations that do not
13740 refer to symbols, thus it is also possible to have an
13741 object file containing relocations but no symbol table. */
cf35638d 13742 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 13743 {
13744 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 13745 r_symndx);
ba93b8ac
DJ		 13746 return FALSE;
13747 }
13748
34e77a92
RS		 13749 h = NULL;
13750 isym = NULL;
13751 if (nsyms > 0)
973a3492 13752 {
34e77a92
RS		 13753 if (r_symndx < symtab_hdr->sh_info)
13754 {
13755 /* A local symbol. */
13756 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
13757 abfd, r_symndx);
13758 if (isym == NULL)
13759 return FALSE;
13760 }
13761 else
13762 {
13763 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13764 while (h->root.type == bfd_link_hash_indirect
13765 || h->root.type == bfd_link_hash_warning)
13766 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 13767
13768 /* PR15323, ref flags aren't set for references in the
13769 same object. */
13770 h->root.non_ir_ref = 1;
34e77a92 13771 }
973a3492 13772 }
9a5aca8c 13773
b7693d02
DJ		 13774 eh = (struct elf32_arm_link_hash_entry *) h;
13775
f6e32f6d
RS		 13776 call_reloc_p = FALSE;
13777 may_become_dynamic_p = FALSE;
13778 may_need_local_target_p = FALSE;
13779
0855e32b
NS		 13780 /* Could be done earlier, if h were already available. */
13781 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 13782 switch (r_type)
99059e56 13783 {
5e681ec4 13784 case R_ARM_GOT32:
eb043451 13785 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13786 case R_ARM_TLS_GD32:
13787 case R_ARM_TLS_IE32:
0855e32b
NS		 13788 case R_ARM_TLS_GOTDESC:
13789 case R_ARM_TLS_DESCSEQ:
13790 case R_ARM_THM_TLS_DESCSEQ:
13791 case R_ARM_TLS_CALL:
13792 case R_ARM_THM_TLS_CALL:
5e681ec4 13793 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 13794 {
13795 int tls_type, old_tls_type;
5e681ec4 13796
ba93b8ac
DJ		 13797 switch (r_type)
13798 {
13799 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 13800
ba93b8ac 13801 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 13802
0855e32b
NS		 13803 case R_ARM_TLS_GOTDESC:
13804 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
13805 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
13806 tls_type = GOT_TLS_GDESC; break;
b38cadfb 13807
ba93b8ac
DJ		 13808 default: tls_type = GOT_NORMAL; break;
13809 }
252b5132 13810
0e1862bb 13811 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 13812 info->flags |= DF_STATIC_TLS;
13813
ba93b8ac
DJ		 13814 if (h != NULL)
13815 {
13816 h->got.refcount++;
13817 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
13818 }
13819 else
13820 {
ba93b8ac 13821 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 13822 if (!elf32_arm_allocate_local_sym_info (abfd))
13823 return FALSE;
13824 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 13825 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
13826 }
13827
0855e32b 13828 /* If a variable is accessed with both tls methods, two
99059e56 13829 slots may be created. */
0855e32b
NS		 13830 if (GOT_TLS_GD_ANY_P (old_tls_type)
13831 && GOT_TLS_GD_ANY_P (tls_type))
13832 tls_type |= old_tls_type;
13833
13834 /* We will already have issued an error message if there
13835 is a TLS/non-TLS mismatch, based on the symbol
13836 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 13837 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
13838 && tls_type != GOT_NORMAL)
13839 tls_type |= old_tls_type;
13840
0855e32b 13841 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 13842 method, we're able to relax. Turn off the GDESC flag,
13843 without messing up with any other kind of tls types
6a631e86 13844 that may be involved. */
0855e32b
NS		 13845 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
13846 tls_type &= ~GOT_TLS_GDESC;
13847
ba93b8ac
DJ		 13848 if (old_tls_type != tls_type)
13849 {
13850 if (h != NULL)
13851 elf32_arm_hash_entry (h)->tls_type = tls_type;
13852 else
13853 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
13854 }
13855 }
8029a119 13856 /* Fall through. */
ba93b8ac
DJ		 13857
13858 case R_ARM_TLS_LDM32:
13859 if (r_type == R_ARM_TLS_LDM32)
13860 htab->tls_ldm_got.refcount++;
8029a119 13861 /* Fall through. */
252b5132 13862
c19d1205 13863 case R_ARM_GOTOFF32:
5e681ec4 13864 case R_ARM_GOTPC:
cbc704f3
RS		 13865 if (htab->root.sgot == NULL
13866 && !create_got_section (htab->root.dynobj, info))
13867 return FALSE;
252b5132
RH		 13868 break;
13869
252b5132 13870 case R_ARM_PC24:
7359ea65 13871 case R_ARM_PLT32:
5b5bb741
PB		 13872 case R_ARM_CALL:
13873 case R_ARM_JUMP24:
eb043451 13874 case R_ARM_PREL31:
c19d1205 13875 case R_ARM_THM_CALL:
bd97cb95
DJ		 13876 case R_ARM_THM_JUMP24:
13877 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 13878 call_reloc_p = TRUE;
13879 may_need_local_target_p = TRUE;
13880 break;
13881
13882 case R_ARM_ABS12:
13883 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
13884 ldr __GOTT_INDEX__ offsets. */
13885 if (!htab->vxworks_p)
13886 {
13887 may_need_local_target_p = TRUE;
13888 break;
13889 }
aebf9be7
NC		 13890 else goto jump_over;
13891
f6e32f6d 13892 /* Fall through. */
39623e12 13893
96c23d59
JM		 13894 case R_ARM_MOVW_ABS_NC:
13895 case R_ARM_MOVT_ABS:
13896 case R_ARM_THM_MOVW_ABS_NC:
13897 case R_ARM_THM_MOVT_ABS:
0e1862bb 13898 if (bfd_link_pic (info))
96c23d59
JM		 13899 {
13900 (*_bfd_error_handler)
13901 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
13902 abfd, elf32_arm_howto_table_1[r_type].name,
13903 (h) ? h->root.root.string : "a local symbol");
13904 bfd_set_error (bfd_error_bad_value);
13905 return FALSE;
13906 }
13907
13908 /* Fall through. */
39623e12
PB		 13909 case R_ARM_ABS32:
13910 case R_ARM_ABS32_NOI:
aebf9be7 13911 jump_over:
0e1862bb 13912 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 13913 {
13914 h->pointer_equality_needed = 1;
13915 }
13916 /* Fall through. */
39623e12
PB		 13917 case R_ARM_REL32:
13918 case R_ARM_REL32_NOI:
b6895b4f
PB		 13919 case R_ARM_MOVW_PREL_NC:
13920 case R_ARM_MOVT_PREL:
b6895b4f
PB		 13921 case R_ARM_THM_MOVW_PREL_NC:
13922 case R_ARM_THM_MOVT_PREL:
39623e12 13923
b7693d02 13924 /* Should the interworking branches be listed here? */
0e1862bb 13925 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 13926 && (sec->flags & SEC_ALLOC) != 0)
13927 {
13928 if (h == NULL
469a3493 13929 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13930 {
13931 /* In shared libraries and relocatable executables,
13932 we treat local relative references as calls;
13933 see the related SYMBOL_CALLS_LOCAL code in
13934 allocate_dynrelocs. */
13935 call_reloc_p = TRUE;
13936 may_need_local_target_p = TRUE;
13937 }
13938 else
13939 /* We are creating a shared library or relocatable
13940 executable, and this is a reloc against a global symbol,
13941 or a non-PC-relative reloc against a local symbol.
13942 We may need to copy the reloc into the output. */
13943 may_become_dynamic_p = TRUE;
13944 }
f6e32f6d
RS		 13945 else
13946 may_need_local_target_p = TRUE;
252b5132
RH		 13947 break;
13948
99059e56
RM		 13949 /* This relocation describes the C++ object vtable hierarchy.
13950 Reconstruct it for later use during GC. */
13951 case R_ARM_GNU_VTINHERIT:
13952 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
13953 return FALSE;
13954 break;
13955
13956 /* This relocation describes which C++ vtable entries are actually
13957 used. Record for later use during GC. */
13958 case R_ARM_GNU_VTENTRY:
13959 BFD_ASSERT (h != NULL);
13960 if (h != NULL
13961 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
13962 return FALSE;
13963 break;
13964 }
f6e32f6d
RS		 13965
13966 if (h != NULL)
13967 {
13968 if (call_reloc_p)
13969 /* We may need a .plt entry if the function this reloc
13970 refers to is in a different object, regardless of the
13971 symbol's type. We can't tell for sure yet, because
13972 something later might force the symbol local. */
13973 h->needs_plt = 1;
13974 else if (may_need_local_target_p)
13975 /* If this reloc is in a read-only section, we might
13976 need a copy reloc. We can't check reliably at this
13977 stage whether the section is read-only, as input
13978 sections have not yet been mapped to output sections.
13979 Tentatively set the flag for now, and correct in
13980 adjust_dynamic_symbol. */
13981 h->non_got_ref = 1;
13982 }
13983
34e77a92
RS		 13984 if (may_need_local_target_p
13985 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 13986 {
34e77a92
RS		 13987 union gotplt_union *root_plt;
13988 struct arm_plt_info *arm_plt;
13989 struct arm_local_iplt_info *local_iplt;
13990
13991 if (h != NULL)
13992 {
13993 root_plt = &h->plt;
13994 arm_plt = &eh->plt;
13995 }
13996 else
13997 {
13998 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
13999 if (local_iplt == NULL)
14000 return FALSE;
14001 root_plt = &local_iplt->root;
14002 arm_plt = &local_iplt->arm;
14003 }
14004
f6e32f6d
RS		 14005 /* If the symbol is a function that doesn't bind locally,
14006 this relocation will need a PLT entry. */
a8c887dd
NC		 14007 if (root_plt->refcount != -1)
14008 root_plt->refcount += 1;
34e77a92
RS		 14009
14010 if (!call_reloc_p)
14011 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14012
14013 /* It's too early to use htab->use_blx here, so we have to
14014 record possible blx references separately from
14015 relocs that definitely need a thumb stub. */
14016
14017 if (r_type == R_ARM_THM_CALL)
34e77a92 14018 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14019
14020 if (r_type == R_ARM_THM_JUMP24
14021 || r_type == R_ARM_THM_JUMP19)
34e77a92 14022 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14023 }
14024
14025 if (may_become_dynamic_p)
14026 {
14027 struct elf_dyn_relocs *p, **head;
14028
14029 /* Create a reloc section in dynobj. */
14030 if (sreloc == NULL)
14031 {
14032 sreloc = _bfd_elf_make_dynamic_reloc_section
14033 (sec, dynobj, 2, abfd, ! htab->use_rel);
14034
14035 if (sreloc == NULL)
14036 return FALSE;
14037
14038 /* BPABI objects never have dynamic relocations mapped. */
14039 if (htab->symbian_p)
14040 {
14041 flagword flags;
14042
14043 flags = bfd_get_section_flags (dynobj, sreloc);
14044 flags &= ~(SEC_LOAD | SEC_ALLOC);
14045 bfd_set_section_flags (dynobj, sreloc, flags);
14046 }
14047 }
14048
14049 /* If this is a global symbol, count the number of
14050 relocations we need for this symbol. */
14051 if (h != NULL)
14052 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14053 else
14054 {
34e77a92
RS		 14055 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14056 if (head == NULL)
f6e32f6d 14057 return FALSE;
f6e32f6d
RS		 14058 }
14059
14060 p = *head;
14061 if (p == NULL || p->sec != sec)
14062 {
14063 bfd_size_type amt = sizeof *p;
14064
14065 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14066 if (p == NULL)
14067 return FALSE;
14068 p->next = *head;
14069 *head = p;
14070 p->sec = sec;
14071 p->count = 0;
14072 p->pc_count = 0;
14073 }
14074
469a3493 14075 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14076 p->pc_count += 1;
14077 p->count += 1;
14078 }
252b5132 14079 }
f21f3fe0 14080
b34976b6 14081 return TRUE;
252b5132
RH		 14082}
14083
6a5bb875
PB		 14084/* Unwinding tables are not referenced directly. This pass marks them as
14085 required if the corresponding code section is marked. */
14086
14087static bfd_boolean
906e58ca
NC		 14088elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
14089 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 14090{
14091 bfd *sub;
14092 Elf_Internal_Shdr **elf_shdrp;
14093 bfd_boolean again;
14094
7f6ab9f8
AM		 14095 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
14096
6a5bb875
PB		 14097 /* Marking EH data may cause additional code sections to be marked,
14098 requiring multiple passes. */
14099 again = TRUE;
14100 while (again)
14101 {
14102 again = FALSE;
c72f2fb2 14103 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 14104 {
14105 asection *o;
14106
0ffa91dd 14107 if (! is_arm_elf (sub))
6a5bb875
PB		 14108 continue;
14109
14110 elf_shdrp = elf_elfsections (sub);
14111 for (o = sub->sections; o != NULL; o = o->next)
14112 {
14113 Elf_Internal_Shdr *hdr;
0ffa91dd 14114
6a5bb875 14115 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 14116 if (hdr->sh_type == SHT_ARM_EXIDX
14117 && hdr->sh_link
14118 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 14119 && !o->gc_mark
14120 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
14121 {
14122 again = TRUE;
14123 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
14124 return FALSE;
14125 }
14126 }
14127 }
14128 }
14129
14130 return TRUE;
14131}
14132
3c9458e9
NC		 14133/* Treat mapping symbols as special target symbols. */
14134
14135static bfd_boolean
14136elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
14137{
b0796911
PB		 14138 return bfd_is_arm_special_symbol_name (sym->name,
14139 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 14140}
14141
0367ecfb
NC		 14142/* This is a copy of elf_find_function() from elf.c except that
14143 ARM mapping symbols are ignored when looking for function names
14144 and STT_ARM_TFUNC is considered to a function type. */
252b5132 14145
0367ecfb
NC		 14146static bfd_boolean
14147arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 14148 asymbol ** symbols,
fb167eb2 14149 asection * section,
0367ecfb
NC		 14150 bfd_vma offset,
14151 const char ** filename_ptr,
14152 const char ** functionname_ptr)
14153{
14154 const char * filename = NULL;
14155 asymbol * func = NULL;
14156 bfd_vma low_func = 0;
14157 asymbol ** p;
252b5132
RH		 14158
14159 for (p = symbols; *p != NULL; p++)
14160 {
14161 elf_symbol_type *q;
14162
14163 q = (elf_symbol_type *) *p;
14164
252b5132
RH		 14165 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
14166 {
14167 default:
14168 break;
14169 case STT_FILE:
14170 filename = bfd_asymbol_name (&q->symbol);
14171 break;
252b5132
RH		 14172 case STT_FUNC:
14173 case STT_ARM_TFUNC:
9d2da7ca 14174 case STT_NOTYPE:
b0796911 14175 /* Skip mapping symbols. */
0367ecfb 14176 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 14177 && bfd_is_arm_special_symbol_name (q->symbol.name,
14178 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 14179 continue;
14180 /* Fall through. */
6b40fcba 14181 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 14182 && q->symbol.value >= low_func
14183 && q->symbol.value <= offset)
14184 {
14185 func = (asymbol *) q;
14186 low_func = q->symbol.value;
14187 }
14188 break;
14189 }
14190 }
14191
14192 if (func == NULL)
b34976b6 14193 return FALSE;
252b5132 14194
0367ecfb
NC		 14195 if (filename_ptr)
14196 *filename_ptr = filename;
14197 if (functionname_ptr)
14198 *functionname_ptr = bfd_asymbol_name (func);
14199
14200 return TRUE;
906e58ca 14201}
0367ecfb
NC		 14202
14203
14204/* Find the nearest line to a particular section and offset, for error
14205 reporting. This code is a duplicate of the code in elf.c, except
14206 that it uses arm_elf_find_function. */
14207
14208static bfd_boolean
14209elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 14210 asymbol ** symbols,
fb167eb2 14211 asection * section,
0367ecfb
NC		 14212 bfd_vma offset,
14213 const char ** filename_ptr,
14214 const char ** functionname_ptr,
fb167eb2
AM		 14215 unsigned int * line_ptr,
14216 unsigned int * discriminator_ptr)
0367ecfb
NC		 14217{
14218 bfd_boolean found = FALSE;
14219
fb167eb2 14220 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 14221 filename_ptr, functionname_ptr,
fb167eb2
AM		 14222 line_ptr, discriminator_ptr,
14223 dwarf_debug_sections, 0,
0367ecfb
NC		 14224 & elf_tdata (abfd)->dwarf2_find_line_info))
14225 {
14226 if (!*functionname_ptr)
fb167eb2 14227 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14228 *filename_ptr ? NULL : filename_ptr,
14229 functionname_ptr);
f21f3fe0 14230
0367ecfb
NC		 14231 return TRUE;
14232 }
14233
fb167eb2
AM		 14234 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
14235 uses DWARF1. */
14236
0367ecfb
NC		 14237 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
14238 & found, filename_ptr,
14239 functionname_ptr, line_ptr,
14240 & elf_tdata (abfd)->line_info))
14241 return FALSE;
14242
14243 if (found && (*functionname_ptr || *line_ptr))
14244 return TRUE;
14245
14246 if (symbols == NULL)
14247 return FALSE;
14248
fb167eb2 14249 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14250 filename_ptr, functionname_ptr))
14251 return FALSE;
14252
14253 *line_ptr = 0;
b34976b6 14254 return TRUE;
252b5132
RH		 14255}
14256
4ab527b0
FF		 14257static bfd_boolean
14258elf32_arm_find_inliner_info (bfd * abfd,
14259 const char ** filename_ptr,
14260 const char ** functionname_ptr,
14261 unsigned int * line_ptr)
14262{
14263 bfd_boolean found;
14264 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
14265 functionname_ptr, line_ptr,
14266 & elf_tdata (abfd)->dwarf2_find_line_info);
14267 return found;
14268}
14269
252b5132
RH		 14270/* Adjust a symbol defined by a dynamic object and referenced by a
14271 regular object. The current definition is in some section of the
14272 dynamic object, but we're not including those sections. We have to
14273 change the definition to something the rest of the link can
14274 understand. */
14275
b34976b6 14276static bfd_boolean
57e8b36a
NC		 14277elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
14278 struct elf_link_hash_entry * h)
252b5132
RH		 14279{
14280 bfd * dynobj;
14281 asection * s;
b7693d02 14282 struct elf32_arm_link_hash_entry * eh;
67687978 14283 struct elf32_arm_link_hash_table *globals;
252b5132 14284
67687978 14285 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14286 if (globals == NULL)
14287 return FALSE;
14288
252b5132
RH		 14289 dynobj = elf_hash_table (info)->dynobj;
14290
14291 /* Make sure we know what is going on here. */
14292 BFD_ASSERT (dynobj != NULL
f5385ebf 14293 && (h->needs_plt
34e77a92 14294 || h->type == STT_GNU_IFUNC
f6e332e6 14295 || h->u.weakdef != NULL
f5385ebf
AM		 14296 || (h->def_dynamic
14297 && h->ref_regular
14298 && !h->def_regular)));
252b5132 14299
b7693d02
DJ		 14300 eh = (struct elf32_arm_link_hash_entry *) h;
14301
252b5132
RH		 14302 /* If this is a function, put it in the procedure linkage table. We
14303 will fill in the contents of the procedure linkage table later,
14304 when we know the address of the .got section. */
34e77a92 14305 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 14306 {
34e77a92
RS		 14307 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
14308 symbol binds locally. */
5e681ec4 14309 if (h->plt.refcount <= 0
34e77a92
RS		 14310 || (h->type != STT_GNU_IFUNC
14311 && (SYMBOL_CALLS_LOCAL (info, h)
14312 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
14313 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 14314 {
14315 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 14316 file, but the symbol was never referred to by a dynamic
14317 object, or if all references were garbage collected. In
14318 such a case, we don't actually need to build a procedure
14319 linkage table, and we can just do a PC24 reloc instead. */
14320 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14321 eh->plt.thumb_refcount = 0;
14322 eh->plt.maybe_thumb_refcount = 0;
14323 eh->plt.noncall_refcount = 0;
f5385ebf 14324 h->needs_plt = 0;
252b5132
RH		 14325 }
14326
b34976b6 14327 return TRUE;
252b5132 14328 }
5e681ec4 14329 else
b7693d02
DJ		 14330 {
14331 /* It's possible that we incorrectly decided a .plt reloc was
14332 needed for an R_ARM_PC24 or similar reloc to a non-function sym
14333 in check_relocs. We can't decide accurately between function
14334 and non-function syms in check-relocs; Objects loaded later in
14335 the link may change h->type. So fix it now. */
14336 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14337 eh->plt.thumb_refcount = 0;
14338 eh->plt.maybe_thumb_refcount = 0;
14339 eh->plt.noncall_refcount = 0;
b7693d02 14340 }
252b5132
RH		 14341
14342 /* If this is a weak symbol, and there is a real definition, the
14343 processor independent code will have arranged for us to see the
14344 real definition first, and we can just use the same value. */
f6e332e6 14345 if (h->u.weakdef != NULL)
252b5132 14346 {
f6e332e6
AM		 14347 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
14348 || h->u.weakdef->root.type == bfd_link_hash_defweak);
14349 h->root.u.def.section = h->u.weakdef->root.u.def.section;
14350 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 14351 return TRUE;
252b5132
RH		 14352 }
14353
ba93b8ac
DJ		 14354 /* If there are no non-GOT references, we do not need a copy
14355 relocation. */
14356 if (!h->non_got_ref)
14357 return TRUE;
14358
252b5132
RH		 14359 /* This is a reference to a symbol defined by a dynamic object which
14360 is not a function. */
14361
14362 /* If we are creating a shared library, we must presume that the
14363 only references to the symbol are via the global offset table.
14364 For such cases we need not do anything here; the relocations will
67687978
PB		 14365 be handled correctly by relocate_section. Relocatable executables
14366 can reference data in shared objects directly, so we don't need to
14367 do anything here. */
0e1862bb 14368 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 14369 return TRUE;
252b5132
RH		 14370
14371 /* We must allocate the symbol in our .dynbss section, which will
14372 become part of the .bss section of the executable. There will be
14373 an entry for this symbol in the .dynsym section. The dynamic
14374 object will contain position independent code, so all references
14375 from the dynamic object to this symbol will go through the global
14376 offset table. The dynamic linker will use the .dynsym entry to
14377 determine the address it must put in the global offset table, so
14378 both the dynamic object and the regular object will refer to the
14379 same memory location for the variable. */
3d4d4302 14380 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 14381 BFD_ASSERT (s != NULL);
14382
5522f910
NC		 14383 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
14384 linker to copy the initial value out of the dynamic object and into
14385 the runtime process image. We need to remember the offset into the
00a97672 14386 .rel(a).bss section we are going to use. */
5522f910
NC		 14387 if (info->nocopyreloc == 0
14388 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 14389 && h->size != 0)
252b5132
RH		 14390 {
14391 asection *srel;
14392
3d4d4302 14393 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 14394 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 14395 h->needs_copy = 1;
252b5132
RH		 14396 }
14397
6cabe1ea 14398 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 14399}
14400
5e681ec4
PB		 14401/* Allocate space in .plt, .got and associated reloc sections for
14402 dynamic relocs. */
14403
14404static bfd_boolean
47beaa6a 14405allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 14406{
14407 struct bfd_link_info *info;
14408 struct elf32_arm_link_hash_table *htab;
14409 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 14410 struct elf_dyn_relocs *p;
5e681ec4
PB		 14411
14412 if (h->root.type == bfd_link_hash_indirect)
14413 return TRUE;
14414
e6a6bb22
AM		 14415 eh = (struct elf32_arm_link_hash_entry *) h;
14416
5e681ec4
PB		 14417 info = (struct bfd_link_info *) inf;
14418 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14419 if (htab == NULL)
14420 return FALSE;
5e681ec4 14421
34e77a92 14422 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 14423 && h->plt.refcount > 0)
14424 {
14425 /* Make sure this symbol is output as a dynamic symbol.
14426 Undefined weak syms won't yet be marked as dynamic. */
14427 if (h->dynindx == -1
f5385ebf 14428 && !h->forced_local)
5e681ec4 14429 {
c152c796 14430 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14431 return FALSE;
14432 }
14433
34e77a92
RS		 14434 /* If the call in the PLT entry binds locally, the associated
14435 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14436 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14437 than the .plt section. */
14438 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
14439 {
14440 eh->is_iplt = 1;
14441 if (eh->plt.noncall_refcount == 0
14442 && SYMBOL_REFERENCES_LOCAL (info, h))
14443 /* All non-call references can be resolved directly.
14444 This means that they can (and in some cases, must)
14445 resolve directly to the run-time target, rather than
14446 to the PLT. That in turns means that any .got entry
14447 would be equal to the .igot.plt entry, so there's
14448 no point having both. */
14449 h->got.refcount = 0;
14450 }
14451
0e1862bb 14452 if (bfd_link_pic (info)
34e77a92 14453 || eh->is_iplt
7359ea65 14454 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 14455 {
34e77a92 14456 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 14457
5e681ec4
PB		 14458 /* If this symbol is not defined in a regular file, and we are
14459 not generating a shared library, then set the symbol to this
14460 location in the .plt. This is required to make function
14461 pointers compare as equal between the normal executable and
14462 the shared library. */
0e1862bb 14463 if (! bfd_link_pic (info)
f5385ebf 14464 && !h->def_regular)
5e681ec4 14465 {
34e77a92 14466 h->root.u.def.section = htab->root.splt;
5e681ec4 14467 h->root.u.def.value = h->plt.offset;
5e681ec4 14468
67d74e43
DJ		 14469 /* Make sure the function is not marked as Thumb, in case
14470 it is the target of an ABS32 relocation, which will
14471 point to the PLT entry. */
39d911fc 14472 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 14473 }
022f8312 14474
00a97672
RS		 14475 /* VxWorks executables have a second set of relocations for
14476 each PLT entry. They go in a separate relocation section,
14477 which is processed by the kernel loader. */
0e1862bb 14478 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 14479 {
14480 /* There is a relocation for the initial PLT entry:
14481 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14482 if (h->plt.offset == htab->plt_header_size)
47beaa6a 14483 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 14484
14485 /* There are two extra relocations for each subsequent
14486 PLT entry: an R_ARM_32 relocation for the GOT entry,
14487 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 14488 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 14489 }
5e681ec4
PB		 14490 }
14491 else
14492 {
14493 h->plt.offset = (bfd_vma) -1;
f5385ebf 14494 h->needs_plt = 0;
5e681ec4
PB		 14495 }
14496 }
14497 else
14498 {
14499 h->plt.offset = (bfd_vma) -1;
f5385ebf 14500 h->needs_plt = 0;
5e681ec4
PB		 14501 }
14502
0855e32b
NS		 14503 eh = (struct elf32_arm_link_hash_entry *) h;
14504 eh->tlsdesc_got = (bfd_vma) -1;
14505
5e681ec4
PB		 14506 if (h->got.refcount > 0)
14507 {
14508 asection *s;
14509 bfd_boolean dyn;
ba93b8ac
DJ		 14510 int tls_type = elf32_arm_hash_entry (h)->tls_type;
14511 int indx;
5e681ec4
PB		 14512
14513 /* Make sure this symbol is output as a dynamic symbol.
14514 Undefined weak syms won't yet be marked as dynamic. */
14515 if (h->dynindx == -1
f5385ebf 14516 && !h->forced_local)
5e681ec4 14517 {
c152c796 14518 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14519 return FALSE;
14520 }
14521
e5a52504
MM		 14522 if (!htab->symbian_p)
14523 {
362d30a1 14524 s = htab->root.sgot;
e5a52504 14525 h->got.offset = s->size;
ba93b8ac
DJ		 14526
14527 if (tls_type == GOT_UNKNOWN)
14528 abort ();
14529
14530 if (tls_type == GOT_NORMAL)
14531 /* Non-TLS symbols need one GOT slot. */
14532 s->size += 4;
14533 else
14534 {
99059e56
RM		 14535 if (tls_type & GOT_TLS_GDESC)
14536 {
0855e32b 14537 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 14538 eh->tlsdesc_got
0855e32b
NS		 14539 = (htab->root.sgotplt->size
14540 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 14541 htab->root.sgotplt->size += 8;
14542 h->got.offset = (bfd_vma) -2;
34e77a92 14543 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14544 reloc in the middle of .got.plt. */
99059e56
RM		 14545 htab->num_tls_desc++;
14546 }
0855e32b 14547
ba93b8ac 14548 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 14549 {
14550 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14551 the symbol is both GD and GDESC, got.offset may
14552 have been overwritten. */
14553 h->got.offset = s->size;
14554 s->size += 8;
14555 }
14556
ba93b8ac
DJ		 14557 if (tls_type & GOT_TLS_IE)
14558 /* R_ARM_TLS_IE32 needs one GOT slot. */
14559 s->size += 4;
14560 }
14561
e5a52504 14562 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 14563
14564 indx = 0;
0e1862bb
L		 14565 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
14566 bfd_link_pic (info),
14567 h)
14568 && (!bfd_link_pic (info)
ba93b8ac
DJ		 14569 || !SYMBOL_REFERENCES_LOCAL (info, h)))
14570 indx = h->dynindx;
14571
14572 if (tls_type != GOT_NORMAL
0e1862bb 14573 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 14574 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14575 || h->root.type != bfd_link_hash_undefweak))
14576 {
14577 if (tls_type & GOT_TLS_IE)
47beaa6a 14578 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14579
14580 if (tls_type & GOT_TLS_GD)
47beaa6a 14581 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14582
b38cadfb 14583 if (tls_type & GOT_TLS_GDESC)
0855e32b 14584 {
47beaa6a 14585 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 14586 /* GDESC needs a trampoline to jump to. */
14587 htab->tls_trampoline = -1;
14588 }
14589
14590 /* Only GD needs it. GDESC just emits one relocation per
14591 2 entries. */
b38cadfb 14592 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 14593 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14594 }
6f820c85 14595 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 14596 {
14597 if (htab->root.dynamic_sections_created)
14598 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
14599 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
14600 }
34e77a92
RS		 14601 else if (h->type == STT_GNU_IFUNC
14602 && eh->plt.noncall_refcount == 0)
14603 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
14604 they all resolve dynamically instead. Reserve room for the
14605 GOT entry's R_ARM_IRELATIVE relocation. */
14606 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 14607 else if (bfd_link_pic (info)
14608 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14609 || h->root.type != bfd_link_hash_undefweak))
b436d854 14610 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 14611 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 14612 }
5e681ec4
PB		 14613 }
14614 else
14615 h->got.offset = (bfd_vma) -1;
14616
a4fd1a8e
PB		 14617 /* Allocate stubs for exported Thumb functions on v4t. */
14618 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 14619 && h->def_regular
39d911fc 14620 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 14621 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
14622 {
14623 struct elf_link_hash_entry * th;
14624 struct bfd_link_hash_entry * bh;
14625 struct elf_link_hash_entry * myh;
14626 char name[1024];
14627 asection *s;
14628 bh = NULL;
14629 /* Create a new symbol to regist the real location of the function. */
14630 s = h->root.u.def.section;
906e58ca 14631 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 14632 _bfd_generic_link_add_one_symbol (info, s->owner,
14633 name, BSF_GLOBAL, s,
14634 h->root.u.def.value,
14635 NULL, TRUE, FALSE, &bh);
14636
14637 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 14638 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 14639 myh->forced_local = 1;
39d911fc 14640 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 14641 eh->export_glue = myh;
14642 th = record_arm_to_thumb_glue (info, h);
14643 /* Point the symbol at the stub. */
14644 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 14645 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 14646 h->root.u.def.section = th->root.u.def.section;
14647 h->root.u.def.value = th->root.u.def.value & ~1;
14648 }
14649
0bdcacaf 14650 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 14651 return TRUE;
14652
14653 /* In the shared -Bsymbolic case, discard space allocated for
14654 dynamic pc-relative relocs against symbols which turn out to be
14655 defined in regular objects. For the normal shared case, discard
14656 space for pc-relative relocs that have become local due to symbol
14657 visibility changes. */
14658
0e1862bb 14659 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 14660 {
469a3493
RM		 14661 /* Relocs that use pc_count are PC-relative forms, which will appear
14662 on something like ".long foo - ." or "movw REG, foo - .". We want
14663 calls to protected symbols to resolve directly to the function
14664 rather than going via the plt. If people want function pointer
14665 comparisons to work as expected then they should avoid writing
14666 assembly like ".long foo - .". */
ba93b8ac
DJ		 14667 if (SYMBOL_CALLS_LOCAL (info, h))
14668 {
0bdcacaf 14669 struct elf_dyn_relocs **pp;
ba93b8ac 14670
0bdcacaf 14671 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 14672 {
14673 p->count -= p->pc_count;
14674 p->pc_count = 0;
14675 if (p->count == 0)
14676 *pp = p->next;
14677 else
14678 pp = &p->next;
14679 }
14680 }
14681
4dfe6ac6 14682 if (htab->vxworks_p)
3348747a 14683 {
0bdcacaf 14684 struct elf_dyn_relocs **pp;
3348747a 14685
0bdcacaf 14686 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 14687 {
0bdcacaf 14688 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 14689 *pp = p->next;
14690 else
14691 pp = &p->next;
14692 }
14693 }
14694
ba93b8ac 14695 /* Also discard relocs on undefined weak syms with non-default
99059e56 14696 visibility. */
0bdcacaf 14697 if (eh->dyn_relocs != NULL
5e681ec4 14698 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 14699 {
14700 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 14701 eh->dyn_relocs = NULL;
22d606e9
AM		 14702
14703 /* Make sure undefined weak symbols are output as a dynamic
14704 symbol in PIEs. */
14705 else if (h->dynindx == -1
14706 && !h->forced_local)
14707 {
14708 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14709 return FALSE;
14710 }
14711 }
14712
67687978
PB		 14713 else if (htab->root.is_relocatable_executable && h->dynindx == -1
14714 && h->root.type == bfd_link_hash_new)
14715 {
14716 /* Output absolute symbols so that we can create relocations
14717 against them. For normal symbols we output a relocation
14718 against the section that contains them. */
14719 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14720 return FALSE;
14721 }
14722
5e681ec4
PB		 14723 }
14724 else
14725 {
14726 /* For the non-shared case, discard space for relocs against
14727 symbols which turn out to need copy relocs or are not
14728 dynamic. */
14729
f5385ebf
AM		 14730 if (!h->non_got_ref
14731 && ((h->def_dynamic
14732 && !h->def_regular)
5e681ec4
PB		 14733 || (htab->root.dynamic_sections_created
14734 && (h->root.type == bfd_link_hash_undefweak
14735 || h->root.type == bfd_link_hash_undefined))))
14736 {
14737 /* Make sure this symbol is output as a dynamic symbol.
14738 Undefined weak syms won't yet be marked as dynamic. */
14739 if (h->dynindx == -1
f5385ebf 14740 && !h->forced_local)
5e681ec4 14741 {
c152c796 14742 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14743 return FALSE;
14744 }
14745
14746 /* If that succeeded, we know we'll be keeping all the
14747 relocs. */
14748 if (h->dynindx != -1)
14749 goto keep;
14750 }
14751
0bdcacaf 14752 eh->dyn_relocs = NULL;
5e681ec4
PB		 14753
14754 keep: ;
14755 }
14756
14757 /* Finally, allocate space. */
0bdcacaf 14758 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 14759 {
0bdcacaf 14760 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 14761 if (h->type == STT_GNU_IFUNC
14762 && eh->plt.noncall_refcount == 0
14763 && SYMBOL_REFERENCES_LOCAL (info, h))
14764 elf32_arm_allocate_irelocs (info, sreloc, p->count);
14765 else
14766 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 14767 }
14768
14769 return TRUE;
14770}
14771
08d1f311
DJ		 14772/* Find any dynamic relocs that apply to read-only sections. */
14773
14774static bfd_boolean
8029a119 14775elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 14776{
8029a119 14777 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 14778 struct elf_dyn_relocs * p;
08d1f311 14779
08d1f311 14780 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 14781 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 14782 {
0bdcacaf 14783 asection *s = p->sec;
08d1f311
DJ		 14784
14785 if (s != NULL && (s->flags & SEC_READONLY) != 0)
14786 {
14787 struct bfd_link_info *info = (struct bfd_link_info *) inf;
14788
14789 info->flags |= DF_TEXTREL;
14790
14791 /* Not an error, just cut short the traversal. */
14792 return FALSE;
14793 }
14794 }
14795 return TRUE;
14796}
14797
d504ffc8
DJ		 14798void
14799bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
14800 int byteswap_code)
14801{
14802 struct elf32_arm_link_hash_table *globals;
14803
14804 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14805 if (globals == NULL)
14806 return;
14807
d504ffc8
DJ		 14808 globals->byteswap_code = byteswap_code;
14809}
14810
252b5132
RH		 14811/* Set the sizes of the dynamic sections. */
14812
b34976b6 14813static bfd_boolean
57e8b36a
NC		 14814elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
14815 struct bfd_link_info * info)
252b5132
RH		 14816{
14817 bfd * dynobj;
14818 asection * s;
b34976b6
AM		 14819 bfd_boolean plt;
14820 bfd_boolean relocs;
5e681ec4
PB		 14821 bfd *ibfd;
14822 struct elf32_arm_link_hash_table *htab;
252b5132 14823
5e681ec4 14824 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14825 if (htab == NULL)
14826 return FALSE;
14827
252b5132
RH		 14828 dynobj = elf_hash_table (info)->dynobj;
14829 BFD_ASSERT (dynobj != NULL);
39b41c9c 14830 check_use_blx (htab);
252b5132
RH		 14831
14832 if (elf_hash_table (info)->dynamic_sections_created)
14833 {
14834 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 14835 if (bfd_link_executable (info) && !info->nointerp)
252b5132 14836 {
3d4d4302 14837 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 14838 BFD_ASSERT (s != NULL);
eea6121a 14839 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 14840 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
14841 }
14842 }
5e681ec4
PB		 14843
14844 /* Set up .got offsets for local syms, and space for local dynamic
14845 relocs. */
c72f2fb2 14846 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 14847 {
5e681ec4
PB		 14848 bfd_signed_vma *local_got;
14849 bfd_signed_vma *end_local_got;
34e77a92 14850 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 14851 char *local_tls_type;
0855e32b 14852 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 14853 bfd_size_type locsymcount;
14854 Elf_Internal_Shdr *symtab_hdr;
14855 asection *srel;
4dfe6ac6 14856 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 14857 unsigned int symndx;
5e681ec4 14858
0ffa91dd 14859 if (! is_arm_elf (ibfd))
5e681ec4
PB		 14860 continue;
14861
14862 for (s = ibfd->sections; s != NULL; s = s->next)
14863 {
0bdcacaf 14864 struct elf_dyn_relocs *p;
5e681ec4 14865
0bdcacaf 14866 for (p = (struct elf_dyn_relocs *)
99059e56 14867 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 14868 {
0bdcacaf
RS		 14869 if (!bfd_is_abs_section (p->sec)
14870 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 14871 {
14872 /* Input section has been discarded, either because
14873 it is a copy of a linkonce section or due to
14874 linker script /DISCARD/, so we'll be discarding
14875 the relocs too. */
14876 }
3348747a 14877 else if (is_vxworks
0bdcacaf 14878 && strcmp (p->sec->output_section->name,
3348747a
NS		 14879 ".tls_vars") == 0)
14880 {
14881 /* Relocations in vxworks .tls_vars sections are
14882 handled specially by the loader. */
14883 }
5e681ec4
PB		 14884 else if (p->count != 0)
14885 {
0bdcacaf 14886 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 14887 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 14888 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 14889 info->flags |= DF_TEXTREL;
14890 }
14891 }
14892 }
14893
14894 local_got = elf_local_got_refcounts (ibfd);
14895 if (!local_got)
14896 continue;
14897
0ffa91dd 14898 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 14899 locsymcount = symtab_hdr->sh_info;
14900 end_local_got = local_got + locsymcount;
34e77a92 14901 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 14902 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 14903 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 14904 symndx = 0;
362d30a1
RS		 14905 s = htab->root.sgot;
14906 srel = htab->root.srelgot;
0855e32b 14907 for (; local_got < end_local_got;
34e77a92
RS		 14908 ++local_got, ++local_iplt_ptr, ++local_tls_type,
14909 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 14910 {
0855e32b 14911 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 14912 local_iplt = *local_iplt_ptr;
14913 if (local_iplt != NULL)
14914 {
14915 struct elf_dyn_relocs *p;
14916
14917 if (local_iplt->root.refcount > 0)
14918 {
14919 elf32_arm_allocate_plt_entry (info, TRUE,
14920 &local_iplt->root,
14921 &local_iplt->arm);
14922 if (local_iplt->arm.noncall_refcount == 0)
14923 /* All references to the PLT are calls, so all
14924 non-call references can resolve directly to the
14925 run-time target. This means that the .got entry
14926 would be the same as the .igot.plt entry, so there's
14927 no point creating both. */
14928 *local_got = 0;
14929 }
14930 else
14931 {
14932 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
14933 local_iplt->root.offset = (bfd_vma) -1;
14934 }
14935
14936 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
14937 {
14938 asection *psrel;
14939
14940 psrel = elf_section_data (p->sec)->sreloc;
14941 if (local_iplt->arm.noncall_refcount == 0)
14942 elf32_arm_allocate_irelocs (info, psrel, p->count);
14943 else
14944 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
14945 }
14946 }
5e681ec4
PB		 14947 if (*local_got > 0)
14948 {
34e77a92
RS		 14949 Elf_Internal_Sym *isym;
14950
eea6121a 14951 *local_got = s->size;
ba93b8ac
DJ		 14952 if (*local_tls_type & GOT_TLS_GD)
14953 /* TLS_GD relocs need an 8-byte structure in the GOT. */
14954 s->size += 8;
0855e32b
NS		 14955 if (*local_tls_type & GOT_TLS_GDESC)
14956 {
14957 *local_tlsdesc_gotent = htab->root.sgotplt->size
14958 - elf32_arm_compute_jump_table_size (htab);
14959 htab->root.sgotplt->size += 8;
14960 *local_got = (bfd_vma) -2;
34e77a92 14961 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14962 reloc in the middle of .got.plt. */
99059e56 14963 htab->num_tls_desc++;
0855e32b 14964 }
ba93b8ac
DJ		 14965 if (*local_tls_type & GOT_TLS_IE)
14966 s->size += 4;
ba93b8ac 14967
0855e32b
NS		 14968 if (*local_tls_type & GOT_NORMAL)
14969 {
14970 /* If the symbol is both GD and GDESC, *local_got
14971 may have been overwritten. */
14972 *local_got = s->size;
14973 s->size += 4;
14974 }
14975
34e77a92
RS		 14976 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
14977 if (isym == NULL)
14978 return FALSE;
14979
14980 /* If all references to an STT_GNU_IFUNC PLT are calls,
14981 then all non-call references, including this GOT entry,
14982 resolve directly to the run-time target. */
14983 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
14984 && (local_iplt == NULL
14985 || local_iplt->arm.noncall_refcount == 0))
14986 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 14987 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 14988 {
0e1862bb 14989 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 14990 || *local_tls_type & GOT_TLS_GD)
14991 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 14992
0e1862bb 14993 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 14994 {
14995 elf32_arm_allocate_dynrelocs (info,
14996 htab->root.srelplt, 1);
14997 htab->tls_trampoline = -1;
14998 }
0855e32b 14999 }
5e681ec4
PB		 15000 }
15001 else
15002 *local_got = (bfd_vma) -1;
15003 }
252b5132
RH		 15004 }
15005
ba93b8ac
DJ		 15006 if (htab->tls_ldm_got.refcount > 0)
15007 {
15008 /* Allocate two GOT entries and one dynamic relocation (if necessary)
15009 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 15010 htab->tls_ldm_got.offset = htab->root.sgot->size;
15011 htab->root.sgot->size += 8;
0e1862bb 15012 if (bfd_link_pic (info))
47beaa6a 15013 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15014 }
15015 else
15016 htab->tls_ldm_got.offset = -1;
15017
5e681ec4
PB		 15018 /* Allocate global sym .plt and .got entries, and space for global
15019 sym dynamic relocs. */
47beaa6a 15020 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 15021
d504ffc8 15022 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 15023 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 15024 {
0ffa91dd 15025 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 15026 continue;
15027
c7b8f16e
JB		 15028 /* Initialise mapping tables for code/data. */
15029 bfd_elf32_arm_init_maps (ibfd);
906e58ca 15030
c7b8f16e 15031 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 15032 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
15033 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 15034 /* xgettext:c-format */
15035 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 15036 ibfd->filename);
15037 }
d504ffc8 15038
3e6b1042
DJ		 15039 /* Allocate space for the glue sections now that we've sized them. */
15040 bfd_elf32_arm_allocate_interworking_sections (info);
15041
0855e32b
NS		 15042 /* For every jump slot reserved in the sgotplt, reloc_count is
15043 incremented. However, when we reserve space for TLS descriptors,
15044 it's not incremented, so in order to compute the space reserved
15045 for them, it suffices to multiply the reloc count by the jump
15046 slot size. */
15047 if (htab->root.srelplt)
15048 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
15049
15050 if (htab->tls_trampoline)
15051 {
15052 if (htab->root.splt->size == 0)
15053 htab->root.splt->size += htab->plt_header_size;
b38cadfb 15054
0855e32b
NS		 15055 htab->tls_trampoline = htab->root.splt->size;
15056 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 15057
0855e32b 15058 /* If we're not using lazy TLS relocations, don't generate the
99059e56 15059 PLT and GOT entries they require. */
0855e32b
NS		 15060 if (!(info->flags & DF_BIND_NOW))
15061 {
15062 htab->dt_tlsdesc_got = htab->root.sgot->size;
15063 htab->root.sgot->size += 4;
15064
15065 htab->dt_tlsdesc_plt = htab->root.splt->size;
15066 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
15067 }
15068 }
15069
252b5132
RH		 15070 /* The check_relocs and adjust_dynamic_symbol entry points have
15071 determined the sizes of the various dynamic sections. Allocate
15072 memory for them. */
b34976b6
AM		 15073 plt = FALSE;
15074 relocs = FALSE;
252b5132
RH		 15075 for (s = dynobj->sections; s != NULL; s = s->next)
15076 {
15077 const char * name;
252b5132
RH		 15078
15079 if ((s->flags & SEC_LINKER_CREATED) == 0)
15080 continue;
15081
15082 /* It's OK to base decisions on the section name, because none
15083 of the dynobj section names depend upon the input files. */
15084 name = bfd_get_section_name (dynobj, s);
15085
34e77a92 15086 if (s == htab->root.splt)
252b5132 15087 {
c456f082
AM		 15088 /* Remember whether there is a PLT. */
15089 plt = s->size != 0;
252b5132 15090 }
0112cd26 15091 else if (CONST_STRNEQ (name, ".rel"))
252b5132 15092 {
c456f082 15093 if (s->size != 0)
252b5132 15094 {
252b5132 15095 /* Remember whether there are any reloc sections other
00a97672 15096 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 15097 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 15098 relocs = TRUE;
252b5132
RH		 15099
15100 /* We use the reloc_count field as a counter if we need
15101 to copy relocs into the output file. */
15102 s->reloc_count = 0;
15103 }
15104 }
34e77a92
RS		 15105 else if (s != htab->root.sgot
15106 && s != htab->root.sgotplt
15107 && s != htab->root.iplt
15108 && s != htab->root.igotplt
15109 && s != htab->sdynbss)
252b5132
RH		 15110 {
15111 /* It's not one of our sections, so don't allocate space. */
15112 continue;
15113 }
15114
c456f082 15115 if (s->size == 0)
252b5132 15116 {
c456f082 15117 /* If we don't need this section, strip it from the
00a97672
RS		 15118 output file. This is mostly to handle .rel(a).bss and
15119 .rel(a).plt. We must create both sections in
c456f082
AM		 15120 create_dynamic_sections, because they must be created
15121 before the linker maps input sections to output
15122 sections. The linker does that before
15123 adjust_dynamic_symbol is called, and it is that
15124 function which decides whether anything needs to go
15125 into these sections. */
8423293d 15126 s->flags |= SEC_EXCLUDE;
252b5132
RH		 15127 continue;
15128 }
15129
c456f082
AM		 15130 if ((s->flags & SEC_HAS_CONTENTS) == 0)
15131 continue;
15132
252b5132 15133 /* Allocate memory for the section contents. */
21d799b5 15134 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 15135 if (s->contents == NULL)
b34976b6 15136 return FALSE;
252b5132
RH		 15137 }
15138
15139 if (elf_hash_table (info)->dynamic_sections_created)
15140 {
15141 /* Add some entries to the .dynamic section. We fill in the
15142 values later, in elf32_arm_finish_dynamic_sections, but we
15143 must add the entries now so that we get the correct size for
15144 the .dynamic section. The DT_DEBUG entry is filled in by the
15145 dynamic linker and used by the debugger. */
dc810e39 15146#define add_dynamic_entry(TAG, VAL) \
5a580b3a 15147 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 15148
0e1862bb 15149 if (bfd_link_executable (info))
252b5132 15150 {
dc810e39 15151 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 15152 return FALSE;
252b5132
RH		 15153 }
15154
15155 if (plt)
15156 {
dc810e39
AM		 15157 if ( !add_dynamic_entry (DT_PLTGOT, 0)
15158 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 15159 || !add_dynamic_entry (DT_PLTREL,
15160 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 15161 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 15162 return FALSE;
0855e32b
NS		 15163
15164 if (htab->dt_tlsdesc_plt &&
b38cadfb 15165 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 15166 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 15167 return FALSE;
252b5132
RH		 15168 }
15169
15170 if (relocs)
15171 {
00a97672
RS		 15172 if (htab->use_rel)
15173 {
15174 if (!add_dynamic_entry (DT_REL, 0)
15175 || !add_dynamic_entry (DT_RELSZ, 0)
15176 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
15177 return FALSE;
15178 }
15179 else
15180 {
15181 if (!add_dynamic_entry (DT_RELA, 0)
15182 || !add_dynamic_entry (DT_RELASZ, 0)
15183 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
15184 return FALSE;
15185 }
252b5132
RH		 15186 }
15187
08d1f311
DJ		 15188 /* If any dynamic relocs apply to a read-only section,
15189 then we need a DT_TEXTREL entry. */
15190 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 15191 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
15192 info);
08d1f311 15193
99e4ae17 15194 if ((info->flags & DF_TEXTREL) != 0)
252b5132 15195 {
dc810e39 15196 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 15197 return FALSE;
252b5132 15198 }
7a2b07ff
NS		 15199 if (htab->vxworks_p
15200 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
15201 return FALSE;
252b5132 15202 }
8532796c 15203#undef add_dynamic_entry
252b5132 15204
b34976b6 15205 return TRUE;
252b5132
RH		 15206}
15207
0855e32b
NS		 15208/* Size sections even though they're not dynamic. We use it to setup
15209 _TLS_MODULE_BASE_, if needed. */
15210
15211static bfd_boolean
15212elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 15213 struct bfd_link_info *info)
0855e32b
NS		 15214{
15215 asection *tls_sec;
15216
0e1862bb 15217 if (bfd_link_relocatable (info))
0855e32b
NS		 15218 return TRUE;
15219
15220 tls_sec = elf_hash_table (info)->tls_sec;
15221
15222 if (tls_sec)
15223 {
15224 struct elf_link_hash_entry *tlsbase;
15225
15226 tlsbase = elf_link_hash_lookup
15227 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
15228
15229 if (tlsbase)
99059e56
RM		 15230 {
15231 struct bfd_link_hash_entry *bh = NULL;
0855e32b 15232 const struct elf_backend_data *bed
99059e56 15233 = get_elf_backend_data (output_bfd);
0855e32b 15234
99059e56 15235 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 15236 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
15237 tls_sec, 0, NULL, FALSE,
15238 bed->collect, &bh)))
15239 return FALSE;
b38cadfb 15240
99059e56
RM		 15241 tlsbase->type = STT_TLS;
15242 tlsbase = (struct elf_link_hash_entry *)bh;
15243 tlsbase->def_regular = 1;
15244 tlsbase->other = STV_HIDDEN;
15245 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 15246 }
15247 }
15248 return TRUE;
15249}
15250
252b5132
RH		 15251/* Finish up dynamic symbol handling. We set the contents of various
15252 dynamic sections here. */
15253
b34976b6 15254static bfd_boolean
906e58ca
NC		 15255elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
15256 struct bfd_link_info * info,
15257 struct elf_link_hash_entry * h,
15258 Elf_Internal_Sym * sym)
252b5132 15259{
e5a52504 15260 struct elf32_arm_link_hash_table *htab;
b7693d02 15261 struct elf32_arm_link_hash_entry *eh;
252b5132 15262
e5a52504 15263 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15264 if (htab == NULL)
15265 return FALSE;
15266
b7693d02 15267 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 15268
15269 if (h->plt.offset != (bfd_vma) -1)
15270 {
34e77a92 15271 if (!eh->is_iplt)
e5a52504 15272 {
34e77a92 15273 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 15274 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
15275 h->dynindx, 0))
15276 return FALSE;
e5a52504 15277 }
57e8b36a 15278
f5385ebf 15279 if (!h->def_regular)
252b5132
RH		 15280 {
15281 /* Mark the symbol as undefined, rather than as defined in
3a635617 15282 the .plt section. */
252b5132 15283 sym->st_shndx = SHN_UNDEF;
3a635617 15284 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 15285 Otherwise, the PLT entry would provide a definition for
15286 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 15287 and so the symbol would never be NULL. Leave the value if
15288 there were any relocations where pointer equality matters
15289 (this is a clue for the dynamic linker, to make function
15290 pointer comparisons work between an application and shared
15291 library). */
97323ad1 15292 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 15293 sym->st_value = 0;
252b5132 15294 }
34e77a92
RS		 15295 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
15296 {
15297 /* At least one non-call relocation references this .iplt entry,
15298 so the .iplt entry is the function's canonical address. */
15299 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 15300 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 15301 sym->st_shndx = (_bfd_elf_section_from_bfd_section
15302 (output_bfd, htab->root.iplt->output_section));
15303 sym->st_value = (h->plt.offset
15304 + htab->root.iplt->output_section->vma
15305 + htab->root.iplt->output_offset);
15306 }
252b5132
RH		 15307 }
15308
f5385ebf 15309 if (h->needs_copy)
252b5132
RH		 15310 {
15311 asection * s;
947216bf 15312 Elf_Internal_Rela rel;
252b5132
RH		 15313
15314 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 15315 BFD_ASSERT (h->dynindx != -1
15316 && (h->root.type == bfd_link_hash_defined
15317 || h->root.type == bfd_link_hash_defweak));
15318
362d30a1 15319 s = htab->srelbss;
252b5132
RH		 15320 BFD_ASSERT (s != NULL);
15321
00a97672 15322 rel.r_addend = 0;
252b5132
RH		 15323 rel.r_offset = (h->root.u.def.value
15324 + h->root.u.def.section->output_section->vma
15325 + h->root.u.def.section->output_offset);
15326 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 15327 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 15328 }
15329
00a97672
RS		 15330 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
15331 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
15332 to the ".got" section. */
9637f6ef 15333 if (h == htab->root.hdynamic
00a97672 15334 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 15335 sym->st_shndx = SHN_ABS;
15336
b34976b6 15337 return TRUE;
252b5132
RH		 15338}
15339
0855e32b
NS		 15340static void
15341arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15342 void *contents,
15343 const unsigned long *template, unsigned count)
15344{
15345 unsigned ix;
b38cadfb 15346
0855e32b
NS		 15347 for (ix = 0; ix != count; ix++)
15348 {
15349 unsigned long insn = template[ix];
15350
15351 /* Emit mov pc,rx if bx is not permitted. */
15352 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
15353 insn = (insn & 0xf000000f) | 0x01a0f000;
15354 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
15355 }
15356}
15357
99059e56
RM		 15358/* Install the special first PLT entry for elf32-arm-nacl. Unlike
15359 other variants, NaCl needs this entry in a static executable's
15360 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
15361 zero. For .iplt really only the last bundle is useful, and .iplt
15362 could have a shorter first entry, with each individual PLT entry's
15363 relative branch calculated differently so it targets the last
15364 bundle instead of the instruction before it (labelled .Lplt_tail
15365 above). But it's simpler to keep the size and layout of PLT0
15366 consistent with the dynamic case, at the cost of some dead code at
15367 the start of .iplt and the one dead store to the stack at the start
15368 of .Lplt_tail. */
15369static void
15370arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15371 asection *plt, bfd_vma got_displacement)
15372{
15373 unsigned int i;
15374
15375 put_arm_insn (htab, output_bfd,
15376 elf32_arm_nacl_plt0_entry[0]
15377 | arm_movw_immediate (got_displacement),
15378 plt->contents + 0);
15379 put_arm_insn (htab, output_bfd,
15380 elf32_arm_nacl_plt0_entry[1]
15381 | arm_movt_immediate (got_displacement),
15382 plt->contents + 4);
15383
15384 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
15385 put_arm_insn (htab, output_bfd,
15386 elf32_arm_nacl_plt0_entry[i],
15387 plt->contents + (i * 4));
15388}
15389
252b5132
RH		 15390/* Finish up the dynamic sections. */
15391
b34976b6 15392static bfd_boolean
57e8b36a 15393elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 15394{
15395 bfd * dynobj;
15396 asection * sgot;
15397 asection * sdyn;
4dfe6ac6
NC		 15398 struct elf32_arm_link_hash_table *htab;
15399
15400 htab = elf32_arm_hash_table (info);
15401 if (htab == NULL)
15402 return FALSE;
252b5132
RH		 15403
15404 dynobj = elf_hash_table (info)->dynobj;
15405
362d30a1 15406 sgot = htab->root.sgotplt;
894891db
NC		 15407 /* A broken linker script might have discarded the dynamic sections.
15408 Catch this here so that we do not seg-fault later on. */
15409 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
15410 return FALSE;
3d4d4302 15411 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 15412
15413 if (elf_hash_table (info)->dynamic_sections_created)
15414 {
15415 asection *splt;
15416 Elf32_External_Dyn *dyncon, *dynconend;
15417
362d30a1 15418 splt = htab->root.splt;
24a1ba0f 15419 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 15420 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 15421
15422 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 15423 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 15424
252b5132
RH		 15425 for (; dyncon < dynconend; dyncon++)
15426 {
15427 Elf_Internal_Dyn dyn;
15428 const char * name;
15429 asection * s;
15430
15431 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
15432
15433 switch (dyn.d_tag)
15434 {
229fcec5
MM		 15435 unsigned int type;
15436
252b5132 15437 default:
7a2b07ff
NS		 15438 if (htab->vxworks_p
15439 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
15440 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 15441 break;
15442
229fcec5
MM		 15443 case DT_HASH:
15444 name = ".hash";
15445 goto get_vma_if_bpabi;
15446 case DT_STRTAB:
15447 name = ".dynstr";
15448 goto get_vma_if_bpabi;
15449 case DT_SYMTAB:
15450 name = ".dynsym";
15451 goto get_vma_if_bpabi;
c0042f5d
MM		 15452 case DT_VERSYM:
15453 name = ".gnu.version";
15454 goto get_vma_if_bpabi;
15455 case DT_VERDEF:
15456 name = ".gnu.version_d";
15457 goto get_vma_if_bpabi;
15458 case DT_VERNEED:
15459 name = ".gnu.version_r";
15460 goto get_vma_if_bpabi;
15461
252b5132 15462 case DT_PLTGOT:
4ade44b7 15463 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 15464 goto get_vma;
15465 case DT_JMPREL:
00a97672 15466 name = RELOC_SECTION (htab, ".plt");
252b5132 15467 get_vma:
4ade44b7 15468 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 15469 if (s == NULL)
15470 {
05456594 15471 (*_bfd_error_handler)
4ade44b7 15472 (_("could not find section %s"), name);
05456594
NC		 15473 bfd_set_error (bfd_error_invalid_operation);
15474 return FALSE;
15475 }
229fcec5 15476 if (!htab->symbian_p)
4ade44b7 15477 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 15478 else
15479 /* In the BPABI, tags in the PT_DYNAMIC section point
15480 at the file offset, not the memory address, for the
15481 convenience of the post linker. */
4ade44b7 15482 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 15483 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15484 break;
15485
229fcec5
MM		 15486 get_vma_if_bpabi:
15487 if (htab->symbian_p)
15488 goto get_vma;
15489 break;
15490
252b5132 15491 case DT_PLTRELSZ:
362d30a1 15492 s = htab->root.srelplt;
252b5132 15493 BFD_ASSERT (s != NULL);
eea6121a 15494 dyn.d_un.d_val = s->size;
252b5132
RH		 15495 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15496 break;
906e58ca 15497
252b5132 15498 case DT_RELSZ:
00a97672 15499 case DT_RELASZ:
229fcec5
MM		 15500 if (!htab->symbian_p)
15501 {
15502 /* My reading of the SVR4 ABI indicates that the
15503 procedure linkage table relocs (DT_JMPREL) should be
15504 included in the overall relocs (DT_REL). This is
15505 what Solaris does. However, UnixWare can not handle
15506 that case. Therefore, we override the DT_RELSZ entry
15507 here to make it not include the JMPREL relocs. Since
00a97672 15508 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 15509 other relocation sections, we don't have to worry
15510 about changing the DT_REL entry. */
362d30a1 15511 s = htab->root.srelplt;
229fcec5
MM		 15512 if (s != NULL)
15513 dyn.d_un.d_val -= s->size;
15514 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15515 break;
15516 }
8029a119 15517 /* Fall through. */
229fcec5
MM		 15518
15519 case DT_REL:
15520 case DT_RELA:
229fcec5
MM		 15521 /* In the BPABI, the DT_REL tag must point at the file
15522 offset, not the VMA, of the first relocation
15523 section. So, we use code similar to that in
15524 elflink.c, but do not check for SHF_ALLOC on the
15525 relcoation section, since relocations sections are
15526 never allocated under the BPABI. The comments above
15527 about Unixware notwithstanding, we include all of the
15528 relocations here. */
15529 if (htab->symbian_p)
15530 {
15531 unsigned int i;
15532 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
15533 ? SHT_REL : SHT_RELA);
15534 dyn.d_un.d_val = 0;
15535 for (i = 1; i < elf_numsections (output_bfd); i++)
15536 {
906e58ca 15537 Elf_Internal_Shdr *hdr
229fcec5
MM		 15538 = elf_elfsections (output_bfd)[i];
15539 if (hdr->sh_type == type)
15540 {
906e58ca 15541 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 15542 || dyn.d_tag == DT_RELASZ)
15543 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 15544 else if ((ufile_ptr) hdr->sh_offset
15545 <= dyn.d_un.d_val - 1)
229fcec5
MM		 15546 dyn.d_un.d_val = hdr->sh_offset;
15547 }
15548 }
15549 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15550 }
252b5132 15551 break;
88f7bcd5 15552
0855e32b 15553 case DT_TLSDESC_PLT:
99059e56 15554 s = htab->root.splt;
0855e32b
NS		 15555 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
15556 + htab->dt_tlsdesc_plt);
15557 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15558 break;
15559
15560 case DT_TLSDESC_GOT:
99059e56 15561 s = htab->root.sgot;
0855e32b 15562 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 15563 + htab->dt_tlsdesc_got);
0855e32b
NS		 15564 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15565 break;
15566
88f7bcd5
NC		 15567 /* Set the bottom bit of DT_INIT/FINI if the
15568 corresponding function is Thumb. */
15569 case DT_INIT:
15570 name = info->init_function;
15571 goto get_sym;
15572 case DT_FINI:
15573 name = info->fini_function;
15574 get_sym:
15575 /* If it wasn't set by elf_bfd_final_link
4cc11e76 15576 then there is nothing to adjust. */
88f7bcd5
NC		 15577 if (dyn.d_un.d_val != 0)
15578 {
15579 struct elf_link_hash_entry * eh;
15580
15581 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 15582 FALSE, FALSE, TRUE);
39d911fc
TP		 15583 if (eh != NULL
15584 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
15585 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 15586 {
15587 dyn.d_un.d_val |= 1;
b34976b6 15588 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 15589 }
15590 }
15591 break;
252b5132
RH		 15592 }
15593 }
15594
24a1ba0f 15595 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 15596 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 15597 {
00a97672
RS		 15598 const bfd_vma *plt0_entry;
15599 bfd_vma got_address, plt_address, got_displacement;
15600
15601 /* Calculate the addresses of the GOT and PLT. */
15602 got_address = sgot->output_section->vma + sgot->output_offset;
15603 plt_address = splt->output_section->vma + splt->output_offset;
15604
15605 if (htab->vxworks_p)
15606 {
15607 /* The VxWorks GOT is relocated by the dynamic linker.
15608 Therefore, we must emit relocations rather than simply
15609 computing the values now. */
15610 Elf_Internal_Rela rel;
15611
15612 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 15613 put_arm_insn (htab, output_bfd, plt0_entry[0],
15614 splt->contents + 0);
15615 put_arm_insn (htab, output_bfd, plt0_entry[1],
15616 splt->contents + 4);
15617 put_arm_insn (htab, output_bfd, plt0_entry[2],
15618 splt->contents + 8);
00a97672
RS		 15619 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
15620
8029a119 15621 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 15622 rel.r_offset = plt_address + 12;
15623 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15624 rel.r_addend = 0;
15625 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
15626 htab->srelplt2->contents);
15627 }
b38cadfb 15628 else if (htab->nacl_p)
99059e56
RM		 15629 arm_nacl_put_plt0 (htab, output_bfd, splt,
15630 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 15631 else if (using_thumb_only (htab))
15632 {
15633 got_displacement = got_address - (plt_address + 12);
15634
15635 plt0_entry = elf32_thumb2_plt0_entry;
15636 put_arm_insn (htab, output_bfd, plt0_entry[0],
15637 splt->contents + 0);
15638 put_arm_insn (htab, output_bfd, plt0_entry[1],
15639 splt->contents + 4);
15640 put_arm_insn (htab, output_bfd, plt0_entry[2],
15641 splt->contents + 8);
15642
15643 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
15644 }
00a97672
RS		 15645 else
15646 {
15647 got_displacement = got_address - (plt_address + 16);
15648
15649 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 15650 put_arm_insn (htab, output_bfd, plt0_entry[0],
15651 splt->contents + 0);
15652 put_arm_insn (htab, output_bfd, plt0_entry[1],
15653 splt->contents + 4);
15654 put_arm_insn (htab, output_bfd, plt0_entry[2],
15655 splt->contents + 8);
15656 put_arm_insn (htab, output_bfd, plt0_entry[3],
15657 splt->contents + 12);
5e681ec4 15658
5e681ec4 15659#ifdef FOUR_WORD_PLT
00a97672
RS		 15660 /* The displacement value goes in the otherwise-unused
15661 last word of the second entry. */
15662 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 15663#else
00a97672 15664 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 15665#endif
00a97672 15666 }
f7a74f8c 15667 }
252b5132
RH		 15668
15669 /* UnixWare sets the entsize of .plt to 4, although that doesn't
15670 really seem like the right value. */
74541ad4
AM		 15671 if (splt->output_section->owner == output_bfd)
15672 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 15673
0855e32b
NS		 15674 if (htab->dt_tlsdesc_plt)
15675 {
15676 bfd_vma got_address
15677 = sgot->output_section->vma + sgot->output_offset;
15678 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
15679 + htab->root.sgot->output_offset);
15680 bfd_vma plt_address
15681 = splt->output_section->vma + splt->output_offset;
15682
b38cadfb 15683 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15684 splt->contents + htab->dt_tlsdesc_plt,
15685 dl_tlsdesc_lazy_trampoline, 6);
15686
15687 bfd_put_32 (output_bfd,
15688 gotplt_address + htab->dt_tlsdesc_got
15689 - (plt_address + htab->dt_tlsdesc_plt)
15690 - dl_tlsdesc_lazy_trampoline[6],
15691 splt->contents + htab->dt_tlsdesc_plt + 24);
15692 bfd_put_32 (output_bfd,
15693 got_address - (plt_address + htab->dt_tlsdesc_plt)
15694 - dl_tlsdesc_lazy_trampoline[7],
15695 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
15696 }
15697
15698 if (htab->tls_trampoline)
15699 {
b38cadfb 15700 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15701 splt->contents + htab->tls_trampoline,
15702 tls_trampoline, 3);
15703#ifdef FOUR_WORD_PLT
15704 bfd_put_32 (output_bfd, 0x00000000,
15705 splt->contents + htab->tls_trampoline + 12);
b38cadfb 15706#endif
0855e32b
NS		 15707 }
15708
0e1862bb
L		 15709 if (htab->vxworks_p
15710 && !bfd_link_pic (info)
15711 && htab->root.splt->size > 0)
00a97672
RS		 15712 {
15713 /* Correct the .rel(a).plt.unloaded relocations. They will have
15714 incorrect symbol indexes. */
15715 int num_plts;
eed62c48 15716 unsigned char *p;
00a97672 15717
362d30a1 15718 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 15719 / htab->plt_entry_size);
15720 p = htab->srelplt2->contents + RELOC_SIZE (htab);
15721
15722 for (; num_plts; num_plts--)
15723 {
15724 Elf_Internal_Rela rel;
15725
15726 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15727 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15728 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15729 p += RELOC_SIZE (htab);
15730
15731 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15732 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
15733 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15734 p += RELOC_SIZE (htab);
15735 }
15736 }
252b5132
RH		 15737 }
15738
99059e56
RM		 15739 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
15740 /* NaCl uses a special first entry in .iplt too. */
15741 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
15742
252b5132 15743 /* Fill in the first three entries in the global offset table. */
229fcec5 15744 if (sgot)
252b5132 15745 {
229fcec5
MM		 15746 if (sgot->size > 0)
15747 {
15748 if (sdyn == NULL)
15749 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
15750 else
15751 bfd_put_32 (output_bfd,
15752 sdyn->output_section->vma + sdyn->output_offset,
15753 sgot->contents);
15754 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
15755 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
15756 }
252b5132 15757
229fcec5
MM		 15758 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
15759 }
252b5132 15760
b34976b6 15761 return TRUE;
252b5132
RH		 15762}
15763
ba96a88f 15764static void
57e8b36a 15765elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 15766{
9b485d32 15767 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 15768 struct elf32_arm_link_hash_table *globals;
ac4c9b04 15769 struct elf_segment_map *m;
ba96a88f
NC		 15770
15771 i_ehdrp = elf_elfheader (abfd);
15772
94a3258f
PB		 15773 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
15774 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
15775 else
7394f108 15776 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 15777 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 15778
93204d3a
PB		 15779 if (link_info)
15780 {
15781 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 15782 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 15783 i_ehdrp->e_flags |= EF_ARM_BE8;
15784 }
3bfcb652
NC		 15785
15786 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
15787 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
15788 {
15789 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 15790 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 15791 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
15792 else
15793 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
15794 }
ac4c9b04
MG		 15795
15796 /* Scan segment to set p_flags attribute if it contains only sections with
15797 SHF_ARM_NOREAD flag. */
15798 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
15799 {
15800 unsigned int j;
15801
15802 if (m->count == 0)
15803 continue;
15804 for (j = 0; j < m->count; j++)
15805 {
15806 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_NOREAD))
15807 break;
15808 }
15809 if (j == m->count)
15810 {
15811 m->p_flags = PF_X;
15812 m->p_flags_valid = 1;
15813 }
15814 }
ba96a88f
NC		 15815}
15816
99e4ae17 15817static enum elf_reloc_type_class
7e612e98
AM		 15818elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
15819 const asection *rel_sec ATTRIBUTE_UNUSED,
15820 const Elf_Internal_Rela *rela)
99e4ae17 15821{
f51e552e 15822 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 15823 {
15824 case R_ARM_RELATIVE:
15825 return reloc_class_relative;
15826 case R_ARM_JUMP_SLOT:
15827 return reloc_class_plt;
15828 case R_ARM_COPY:
15829 return reloc_class_copy;
109575d7
JW		 15830 case R_ARM_IRELATIVE:
15831 return reloc_class_ifunc;
99e4ae17
AJ		 15832 default:
15833 return reloc_class_normal;
15834 }
15835}
15836
e489d0ae 15837static void
57e8b36a 15838elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 15839{
5a6c6817 15840 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 15841}
15842
40a18ebd
NC		 15843/* Return TRUE if this is an unwinding table entry. */
15844
15845static bfd_boolean
15846is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
15847{
0112cd26
NC		 15848 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
15849 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 15850}
15851
15852
15853/* Set the type and flags for an ARM section. We do this by
15854 the section name, which is a hack, but ought to work. */
15855
15856static bfd_boolean
15857elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
15858{
15859 const char * name;
15860
15861 name = bfd_get_section_name (abfd, sec);
15862
15863 if (is_arm_elf_unwind_section_name (abfd, name))
15864 {
15865 hdr->sh_type = SHT_ARM_EXIDX;
15866 hdr->sh_flags |= SHF_LINK_ORDER;
15867 }
ac4c9b04
MG		 15868
15869 if (sec->flags & SEC_ELF_NOREAD)
15870 hdr->sh_flags |= SHF_ARM_NOREAD;
15871
40a18ebd
NC		 15872 return TRUE;
15873}
15874
6dc132d9
L		 15875/* Handle an ARM specific section when reading an object file. This is
15876 called when bfd_section_from_shdr finds a section with an unknown
15877 type. */
40a18ebd
NC		 15878
15879static bfd_boolean
15880elf32_arm_section_from_shdr (bfd *abfd,
15881 Elf_Internal_Shdr * hdr,
6dc132d9
L		 15882 const char *name,
15883 int shindex)
40a18ebd
NC		 15884{
15885 /* There ought to be a place to keep ELF backend specific flags, but
15886 at the moment there isn't one. We just keep track of the
15887 sections by their name, instead. Fortunately, the ABI gives
15888 names for all the ARM specific sections, so we will probably get
15889 away with this. */
15890 switch (hdr->sh_type)
15891 {
15892 case SHT_ARM_EXIDX:
0951f019
RE		 15893 case SHT_ARM_PREEMPTMAP:
15894 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 15895 break;
15896
15897 default:
15898 return FALSE;
15899 }
15900
6dc132d9 15901 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 15902 return FALSE;
15903
15904 return TRUE;
15905}
e489d0ae 15906
44444f50
NC		 15907static _arm_elf_section_data *
15908get_arm_elf_section_data (asection * sec)
15909{
47b2e99c
JZ		 15910 if (sec && sec->owner && is_arm_elf (sec->owner))
15911 return elf32_arm_section_data (sec);
44444f50
NC		 15912 else
15913 return NULL;
8e3de13a
NC		 15914}
15915
4e617b1e
PB		 15916typedef struct
15917{
57402f1e 15918 void *flaginfo;
4e617b1e 15919 struct bfd_link_info *info;
91a5743d
PB		 15920 asection *sec;
15921 int sec_shndx;
6e0b88f1
AM		 15922 int (*func) (void *, const char *, Elf_Internal_Sym *,
15923 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 15924} output_arch_syminfo;
15925
15926enum map_symbol_type
15927{
15928 ARM_MAP_ARM,
15929 ARM_MAP_THUMB,
15930 ARM_MAP_DATA
15931};
15932
15933
7413f23f 15934/* Output a single mapping symbol. */
4e617b1e
PB		 15935
15936static bfd_boolean
7413f23f
DJ		 15937elf32_arm_output_map_sym (output_arch_syminfo *osi,
15938 enum map_symbol_type type,
15939 bfd_vma offset)
4e617b1e
PB		 15940{
15941 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 15942 Elf_Internal_Sym sym;
15943
91a5743d
PB		 15944 sym.st_value = osi->sec->output_section->vma
15945 + osi->sec->output_offset
15946 + offset;
4e617b1e
PB		 15947 sym.st_size = 0;
15948 sym.st_other = 0;
15949 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 15950 sym.st_shndx = osi->sec_shndx;
35fc36a8 15951 sym.st_target_internal = 0;
fe33d2fa 15952 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 15953 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 15954}
15955
34e77a92
RS		 15956/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
15957 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 15958
15959static bfd_boolean
34e77a92
RS		 15960elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
15961 bfd_boolean is_iplt_entry_p,
15962 union gotplt_union *root_plt,
15963 struct arm_plt_info *arm_plt)
4e617b1e 15964{
4e617b1e 15965 struct elf32_arm_link_hash_table *htab;
34e77a92 15966 bfd_vma addr, plt_header_size;
4e617b1e 15967
34e77a92 15968 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 15969 return TRUE;
15970
4dfe6ac6
NC		 15971 htab = elf32_arm_hash_table (osi->info);
15972 if (htab == NULL)
15973 return FALSE;
15974
34e77a92
RS		 15975 if (is_iplt_entry_p)
15976 {
15977 osi->sec = htab->root.iplt;
15978 plt_header_size = 0;
15979 }
15980 else
15981 {
15982 osi->sec = htab->root.splt;
15983 plt_header_size = htab->plt_header_size;
15984 }
15985 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
15986 (osi->info->output_bfd, osi->sec->output_section));
15987
15988 addr = root_plt->offset & -2;
4e617b1e
PB		 15989 if (htab->symbian_p)
15990 {
7413f23f 15991 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15992 return FALSE;
7413f23f 15993 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 15994 return FALSE;
15995 }
15996 else if (htab->vxworks_p)
15997 {
7413f23f 15998 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15999 return FALSE;
7413f23f 16000 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16001 return FALSE;
7413f23f 16002 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16003 return FALSE;
7413f23f 16004 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16005 return FALSE;
16006 }
b38cadfb
NC		 16007 else if (htab->nacl_p)
16008 {
16009 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16010 return FALSE;
16011 }
eed94f8f
NC		 16012 else if (using_thumb_only (htab))
16013 {
16014 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16015 return FALSE;
6a631e86 16016 }
4e617b1e
PB		 16017 else
16018 {
34e77a92 16019 bfd_boolean thumb_stub_p;
bd97cb95 16020
34e77a92
RS		 16021 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16022 if (thumb_stub_p)
4e617b1e 16023 {
7413f23f 16024 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16025 return FALSE;
16026 }
16027#ifdef FOUR_WORD_PLT
7413f23f 16028 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16029 return FALSE;
7413f23f 16030 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 16031 return FALSE;
16032#else
906e58ca 16033 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 16034 so only need to output a mapping symbol for the first PLT entry and
16035 entries with thumb thunks. */
34e77a92 16036 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 16037 {
7413f23f 16038 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 16039 return FALSE;
16040 }
16041#endif
16042 }
16043
16044 return TRUE;
16045}
16046
34e77a92
RS		 16047/* Output mapping symbols for PLT entries associated with H. */
16048
16049static bfd_boolean
16050elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
16051{
16052 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
16053 struct elf32_arm_link_hash_entry *eh;
16054
16055 if (h->root.type == bfd_link_hash_indirect)
16056 return TRUE;
16057
16058 if (h->root.type == bfd_link_hash_warning)
16059 /* When warning symbols are created, they **replace** the "real"
16060 entry in the hash table, thus we never get to see the real
16061 symbol in a hash traversal. So look at it now. */
16062 h = (struct elf_link_hash_entry *) h->root.u.i.link;
16063
16064 eh = (struct elf32_arm_link_hash_entry *) h;
16065 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
16066 &h->plt, &eh->plt);
16067}
16068
4f4faa4d
TP		 16069/* Bind a veneered symbol to its veneer identified by its hash entry
16070 STUB_ENTRY. The veneered location thus loose its symbol. */
16071
16072static void
16073arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
16074{
16075 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
16076
16077 BFD_ASSERT (hash);
16078 hash->root.root.u.def.section = stub_entry->stub_sec;
16079 hash->root.root.u.def.value = stub_entry->stub_offset;
16080 hash->root.size = stub_entry->stub_size;
16081}
16082
7413f23f
DJ		 16083/* Output a single local symbol for a generated stub. */
16084
16085static bfd_boolean
16086elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
16087 bfd_vma offset, bfd_vma size)
16088{
7413f23f
DJ		 16089 Elf_Internal_Sym sym;
16090
7413f23f
DJ		 16091 sym.st_value = osi->sec->output_section->vma
16092 + osi->sec->output_offset
16093 + offset;
16094 sym.st_size = size;
16095 sym.st_other = 0;
16096 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
16097 sym.st_shndx = osi->sec_shndx;
35fc36a8 16098 sym.st_target_internal = 0;
57402f1e 16099 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 16100}
4e617b1e 16101
da5938a2 16102static bfd_boolean
8029a119
NC		 16103arm_map_one_stub (struct bfd_hash_entry * gen_entry,
16104 void * in_arg)
da5938a2
NC		 16105{
16106 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 16107 asection *stub_sec;
16108 bfd_vma addr;
7413f23f 16109 char *stub_name;
9a008db3 16110 output_arch_syminfo *osi;
d3ce72d0 16111 const insn_sequence *template_sequence;
461a49ca
DJ		 16112 enum stub_insn_type prev_type;
16113 int size;
16114 int i;
16115 enum map_symbol_type sym_type;
da5938a2
NC		 16116
16117 /* Massage our args to the form they really have. */
16118 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 16119 osi = (output_arch_syminfo *) in_arg;
da5938a2 16120
da5938a2
NC		 16121 stub_sec = stub_entry->stub_sec;
16122
16123 /* Ensure this stub is attached to the current section being
7413f23f 16124 processed. */
da5938a2
NC		 16125 if (stub_sec != osi->sec)
16126 return TRUE;
16127
7413f23f 16128 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 16129 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 16130
16131 if (arm_stub_sym_claimed (stub_entry->stub_type))
16132 arm_stub_claim_sym (stub_entry);
16133 else
7413f23f 16134 {
4f4faa4d
TP		 16135 stub_name = stub_entry->output_name;
16136 switch (template_sequence[0].type)
16137 {
16138 case ARM_TYPE:
16139 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
16140 stub_entry->stub_size))
16141 return FALSE;
16142 break;
16143 case THUMB16_TYPE:
16144 case THUMB32_TYPE:
16145 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
16146 stub_entry->stub_size))
16147 return FALSE;
16148 break;
16149 default:
16150 BFD_FAIL ();
16151 return 0;
16152 }
7413f23f 16153 }
da5938a2 16154
461a49ca
DJ		 16155 prev_type = DATA_TYPE;
16156 size = 0;
16157 for (i = 0; i < stub_entry->stub_template_size; i++)
16158 {
d3ce72d0 16159 switch (template_sequence[i].type)
461a49ca
DJ		 16160 {
16161 case ARM_TYPE:
16162 sym_type = ARM_MAP_ARM;
16163 break;
16164
16165 case THUMB16_TYPE:
48229727 16166 case THUMB32_TYPE:
461a49ca
DJ		 16167 sym_type = ARM_MAP_THUMB;
16168 break;
16169
16170 case DATA_TYPE:
16171 sym_type = ARM_MAP_DATA;
16172 break;
16173
16174 default:
16175 BFD_FAIL ();
4e31c731 16176 return FALSE;
461a49ca
DJ		 16177 }
16178
d3ce72d0 16179 if (template_sequence[i].type != prev_type)
461a49ca 16180 {
d3ce72d0 16181 prev_type = template_sequence[i].type;
461a49ca
DJ		 16182 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
16183 return FALSE;
16184 }
16185
d3ce72d0 16186 switch (template_sequence[i].type)
461a49ca
DJ		 16187 {
16188 case ARM_TYPE:
48229727 16189 case THUMB32_TYPE:
461a49ca
DJ		 16190 size += 4;
16191 break;
16192
16193 case THUMB16_TYPE:
16194 size += 2;
16195 break;
16196
16197 case DATA_TYPE:
16198 size += 4;
16199 break;
16200
16201 default:
16202 BFD_FAIL ();
4e31c731 16203 return FALSE;
461a49ca
DJ		 16204 }
16205 }
16206
da5938a2
NC		 16207 return TRUE;
16208}
16209
33811162
DG		 16210/* Output mapping symbols for linker generated sections,
16211 and for those data-only sections that do not have a
16212 $d. */
4e617b1e
PB		 16213
16214static bfd_boolean
16215elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 16216 struct bfd_link_info *info,
57402f1e 16217 void *flaginfo,
6e0b88f1
AM		 16218 int (*func) (void *, const char *,
16219 Elf_Internal_Sym *,
16220 asection *,
16221 struct elf_link_hash_entry *))
4e617b1e
PB		 16222{
16223 output_arch_syminfo osi;
16224 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 16225 bfd_vma offset;
16226 bfd_size_type size;
33811162 16227 bfd *input_bfd;
4e617b1e
PB		 16228
16229 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16230 if (htab == NULL)
16231 return FALSE;
16232
906e58ca 16233 check_use_blx (htab);
91a5743d 16234
57402f1e 16235 osi.flaginfo = flaginfo;
4e617b1e
PB		 16236 osi.info = info;
16237 osi.func = func;
906e58ca 16238
33811162
DG		 16239 /* Add a $d mapping symbol to data-only sections that
16240 don't have any mapping symbol. This may result in (harmless) redundant
16241 mapping symbols. */
16242 for (input_bfd = info->input_bfds;
16243 input_bfd != NULL;
c72f2fb2 16244 input_bfd = input_bfd->link.next)
33811162
DG		 16245 {
16246 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
16247 for (osi.sec = input_bfd->sections;
16248 osi.sec != NULL;
16249 osi.sec = osi.sec->next)
16250 {
16251 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 16252 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
16253 != 0)
33811162
DG		 16254 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
16255 == SEC_HAS_CONTENTS
16256 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 16257 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 16258 && osi.sec->size > 0
16259 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 16260 {
16261 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16262 (output_bfd, osi.sec->output_section);
16263 if (osi.sec_shndx != (int)SHN_BAD)
16264 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
16265 }
16266 }
16267 }
16268
91a5743d
PB		 16269 /* ARM->Thumb glue. */
16270 if (htab->arm_glue_size > 0)
16271 {
3d4d4302
AM		 16272 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16273 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 16274
16275 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16276 (output_bfd, osi.sec->output_section);
0e1862bb 16277 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 16278 || htab->pic_veneer)
16279 size = ARM2THUMB_PIC_GLUE_SIZE;
16280 else if (htab->use_blx)
16281 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
16282 else
16283 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 16284
91a5743d
PB		 16285 for (offset = 0; offset < htab->arm_glue_size; offset += size)
16286 {
7413f23f
DJ		 16287 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
16288 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 16289 }
16290 }
16291
16292 /* Thumb->ARM glue. */
16293 if (htab->thumb_glue_size > 0)
16294 {
3d4d4302
AM		 16295 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16296 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 16297
16298 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16299 (output_bfd, osi.sec->output_section);
16300 size = THUMB2ARM_GLUE_SIZE;
16301
16302 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
16303 {
7413f23f
DJ		 16304 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
16305 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 16306 }
16307 }
16308
845b51d6
PB		 16309 /* ARMv4 BX veneers. */
16310 if (htab->bx_glue_size > 0)
16311 {
3d4d4302
AM		 16312 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16313 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 16314
16315 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16316 (output_bfd, osi.sec->output_section);
16317
7413f23f 16318 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 16319 }
16320
8029a119
NC		 16321 /* Long calls stubs. */
16322 if (htab->stub_bfd && htab->stub_bfd->sections)
16323 {
da5938a2 16324 asection* stub_sec;
8029a119 16325
da5938a2
NC		 16326 for (stub_sec = htab->stub_bfd->sections;
16327 stub_sec != NULL;
8029a119
NC		 16328 stub_sec = stub_sec->next)
16329 {
16330 /* Ignore non-stub sections. */
16331 if (!strstr (stub_sec->name, STUB_SUFFIX))
16332 continue;
da5938a2 16333
8029a119 16334 osi.sec = stub_sec;
da5938a2 16335
8029a119
NC		 16336 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16337 (output_bfd, osi.sec->output_section);
da5938a2 16338
8029a119
NC		 16339 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
16340 }
16341 }
da5938a2 16342
91a5743d 16343 /* Finally, output mapping symbols for the PLT. */
34e77a92 16344 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 16345 {
34e77a92
RS		 16346 osi.sec = htab->root.splt;
16347 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16348 (output_bfd, osi.sec->output_section));
16349
16350 /* Output mapping symbols for the plt header. SymbianOS does not have a
16351 plt header. */
16352 if (htab->vxworks_p)
16353 {
16354 /* VxWorks shared libraries have no PLT header. */
0e1862bb 16355 if (!bfd_link_pic (info))
34e77a92
RS		 16356 {
16357 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16358 return FALSE;
16359 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16360 return FALSE;
16361 }
16362 }
b38cadfb
NC		 16363 else if (htab->nacl_p)
16364 {
16365 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16366 return FALSE;
16367 }
eed94f8f
NC		 16368 else if (using_thumb_only (htab))
16369 {
16370 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
16371 return FALSE;
16372 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16373 return FALSE;
16374 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
16375 return FALSE;
16376 }
34e77a92 16377 else if (!htab->symbian_p)
4e617b1e 16378 {
7413f23f 16379 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 16380 return FALSE;
34e77a92
RS		 16381#ifndef FOUR_WORD_PLT
16382 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 16383 return FALSE;
34e77a92 16384#endif
4e617b1e
PB		 16385 }
16386 }
99059e56
RM		 16387 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
16388 {
16389 /* NaCl uses a special first entry in .iplt too. */
16390 osi.sec = htab->root.iplt;
16391 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16392 (output_bfd, osi.sec->output_section));
16393 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16394 return FALSE;
16395 }
34e77a92
RS		 16396 if ((htab->root.splt && htab->root.splt->size > 0)
16397 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 16398 {
34e77a92
RS		 16399 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
16400 for (input_bfd = info->input_bfds;
16401 input_bfd != NULL;
c72f2fb2 16402 input_bfd = input_bfd->link.next)
34e77a92
RS		 16403 {
16404 struct arm_local_iplt_info **local_iplt;
16405 unsigned int i, num_syms;
4e617b1e 16406
34e77a92
RS		 16407 local_iplt = elf32_arm_local_iplt (input_bfd);
16408 if (local_iplt != NULL)
16409 {
16410 num_syms = elf_symtab_hdr (input_bfd).sh_info;
16411 for (i = 0; i < num_syms; i++)
16412 if (local_iplt[i] != NULL
16413 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
16414 &local_iplt[i]->root,
16415 &local_iplt[i]->arm))
16416 return FALSE;
16417 }
16418 }
16419 }
0855e32b
NS		 16420 if (htab->dt_tlsdesc_plt != 0)
16421 {
16422 /* Mapping symbols for the lazy tls trampoline. */
16423 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
16424 return FALSE;
b38cadfb 16425
0855e32b
NS		 16426 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16427 htab->dt_tlsdesc_plt + 24))
16428 return FALSE;
16429 }
16430 if (htab->tls_trampoline != 0)
16431 {
16432 /* Mapping symbols for the tls trampoline. */
16433 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
16434 return FALSE;
16435#ifdef FOUR_WORD_PLT
16436 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16437 htab->tls_trampoline + 12))
16438 return FALSE;
b38cadfb 16439#endif
0855e32b 16440 }
b38cadfb 16441
4e617b1e
PB		 16442 return TRUE;
16443}
16444
e489d0ae
PB		 16445/* Allocate target specific section data. */
16446
16447static bfd_boolean
16448elf32_arm_new_section_hook (bfd *abfd, asection *sec)
16449{
f592407e
AM		 16450 if (!sec->used_by_bfd)
16451 {
16452 _arm_elf_section_data *sdata;
16453 bfd_size_type amt = sizeof (*sdata);
e489d0ae 16454
21d799b5 16455 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 16456 if (sdata == NULL)
16457 return FALSE;
16458 sec->used_by_bfd = sdata;
16459 }
e489d0ae
PB		 16460
16461 return _bfd_elf_new_section_hook (abfd, sec);
16462}
16463
16464
16465/* Used to order a list of mapping symbols by address. */
16466
16467static int
16468elf32_arm_compare_mapping (const void * a, const void * b)
16469{
7f6a71ff
JM		 16470 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
16471 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
16472
16473 if (amap->vma > bmap->vma)
16474 return 1;
16475 else if (amap->vma < bmap->vma)
16476 return -1;
16477 else if (amap->type > bmap->type)
16478 /* Ensure results do not depend on the host qsort for objects with
16479 multiple mapping symbols at the same address by sorting on type
16480 after vma. */
16481 return 1;
16482 else if (amap->type < bmap->type)
16483 return -1;
16484 else
16485 return 0;
e489d0ae
PB		 16486}
16487
2468f9c9
PB		 16488/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16489
16490static unsigned long
16491offset_prel31 (unsigned long addr, bfd_vma offset)
16492{
16493 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
16494}
16495
16496/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16497 relocations. */
16498
16499static void
16500copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
16501{
16502 unsigned long first_word = bfd_get_32 (output_bfd, from);
16503 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 16504
2468f9c9
PB		 16505 /* High bit of first word is supposed to be zero. */
16506 if ((first_word & 0x80000000ul) == 0)
16507 first_word = offset_prel31 (first_word, offset);
b38cadfb 16508
2468f9c9
PB		 16509 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16510 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16511 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
16512 second_word = offset_prel31 (second_word, offset);
b38cadfb 16513
2468f9c9
PB		 16514 bfd_put_32 (output_bfd, first_word, to);
16515 bfd_put_32 (output_bfd, second_word, to + 4);
16516}
e489d0ae 16517
48229727
JB		 16518/* Data for make_branch_to_a8_stub(). */
16519
b38cadfb
NC		 16520struct a8_branch_to_stub_data
16521{
48229727
JB		 16522 asection *writing_section;
16523 bfd_byte *contents;
16524};
16525
16526
16527/* Helper to insert branches to Cortex-A8 erratum stubs in the right
16528 places for a particular section. */
16529
16530static bfd_boolean
16531make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 16532 void *in_arg)
48229727
JB		 16533{
16534 struct elf32_arm_stub_hash_entry *stub_entry;
16535 struct a8_branch_to_stub_data *data;
16536 bfd_byte *contents;
16537 unsigned long branch_insn;
16538 bfd_vma veneered_insn_loc, veneer_entry_loc;
16539 bfd_signed_vma branch_offset;
16540 bfd *abfd;
8d9d9490 16541 unsigned int loc;
48229727
JB		 16542
16543 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
16544 data = (struct a8_branch_to_stub_data *) in_arg;
16545
16546 if (stub_entry->target_section != data->writing_section
4563a860 16547 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 16548 return TRUE;
16549
16550 contents = data->contents;
16551
8d9d9490
TP		 16552 /* We use target_section as Cortex-A8 erratum workaround stubs are only
16553 generated when both source and target are in the same section. */
48229727
JB		 16554 veneered_insn_loc = stub_entry->target_section->output_section->vma
16555 + stub_entry->target_section->output_offset
8d9d9490 16556 + stub_entry->source_value;
48229727
JB		 16557
16558 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
16559 + stub_entry->stub_sec->output_offset
16560 + stub_entry->stub_offset;
16561
16562 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
16563 veneered_insn_loc &= ~3u;
16564
16565 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
16566
16567 abfd = stub_entry->target_section->owner;
8d9d9490 16568 loc = stub_entry->source_value;
48229727
JB		 16569
16570 /* We attempt to avoid this condition by setting stubs_always_after_branch
16571 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16572 This check is just to be on the safe side... */
16573 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
16574 {
16575 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
16576 "allocated in unsafe location"), abfd);
16577 return FALSE;
16578 }
16579
16580 switch (stub_entry->stub_type)
16581 {
16582 case arm_stub_a8_veneer_b:
16583 case arm_stub_a8_veneer_b_cond:
16584 branch_insn = 0xf0009000;
16585 goto jump24;
16586
16587 case arm_stub_a8_veneer_blx:
16588 branch_insn = 0xf000e800;
16589 goto jump24;
16590
16591 case arm_stub_a8_veneer_bl:
16592 {
16593 unsigned int i1, j1, i2, j2, s;
16594
16595 branch_insn = 0xf000d000;
16596
16597 jump24:
16598 if (branch_offset < -16777216 || branch_offset > 16777214)
16599 {
16600 /* There's not much we can do apart from complain if this
16601 happens. */
16602 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
16603 "of range (input file too large)"), abfd);
16604 return FALSE;
16605 }
16606
16607 /* i1 = not(j1 eor s), so:
16608 not i1 = j1 eor s
16609 j1 = (not i1) eor s. */
16610
16611 branch_insn |= (branch_offset >> 1) & 0x7ff;
16612 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
16613 i2 = (branch_offset >> 22) & 1;
16614 i1 = (branch_offset >> 23) & 1;
16615 s = (branch_offset >> 24) & 1;
16616 j1 = (!i1) ^ s;
16617 j2 = (!i2) ^ s;
16618 branch_insn |= j2 << 11;
16619 branch_insn |= j1 << 13;
16620 branch_insn |= s << 26;
16621 }
16622 break;
16623
16624 default:
16625 BFD_FAIL ();
16626 return FALSE;
16627 }
16628
8d9d9490
TP		 16629 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
16630 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 16631
16632 return TRUE;
16633}
16634
a504d23a
LA		 16635/* Beginning of stm32l4xx work-around. */
16636
16637/* Functions encoding instructions necessary for the emission of the
16638 fix-stm32l4xx-629360.
16639 Encoding is extracted from the
16640 ARM (C) Architecture Reference Manual
16641 ARMv7-A and ARMv7-R edition
16642 ARM DDI 0406C.b (ID072512). */
16643
16644static inline bfd_vma
82188b29 16645create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 16646{
16647 /* A8.8.18 B (A8-334)
16648 B target_address (Encoding T4). */
16649 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
16650 /* jump offset is: S:I1:I2:imm10:imm11:0. */
16651 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
16652
a504d23a
LA		 16653 int s = ((branch_offset & 0x1000000) >> 24);
16654 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
16655 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
16656
16657 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
16658 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
16659
16660 bfd_vma patched_inst = 0xf0009000
16661 | s << 26 /* S. */
16662 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
16663 | j1 << 13 /* J1. */
16664 | j2 << 11 /* J2. */
16665 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
16666
16667 return patched_inst;
16668}
16669
16670static inline bfd_vma
16671create_instruction_ldmia (int base_reg, int wback, int reg_mask)
16672{
16673 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
16674 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
16675 bfd_vma patched_inst = 0xe8900000
16676 | (/*W=*/wback << 21)
16677 | (base_reg << 16)
16678 | (reg_mask & 0x0000ffff);
16679
16680 return patched_inst;
16681}
16682
16683static inline bfd_vma
16684create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
16685{
16686 /* A8.8.60 LDMDB/LDMEA (A8-402)
16687 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
16688 bfd_vma patched_inst = 0xe9100000
16689 | (/*W=*/wback << 21)
16690 | (base_reg << 16)
16691 | (reg_mask & 0x0000ffff);
16692
16693 return patched_inst;
16694}
16695
16696static inline bfd_vma
16697create_instruction_mov (int target_reg, int source_reg)
16698{
16699 /* A8.8.103 MOV (register) (A8-486)
16700 MOV Rd, Rm (Encoding T1). */
16701 bfd_vma patched_inst = 0x4600
16702 | (target_reg & 0x7)
16703 | ((target_reg & 0x8) >> 3) << 7
16704 | (source_reg << 3);
16705
16706 return patched_inst;
16707}
16708
16709static inline bfd_vma
16710create_instruction_sub (int target_reg, int source_reg, int value)
16711{
16712 /* A8.8.221 SUB (immediate) (A8-708)
16713 SUB Rd, Rn, #value (Encoding T3). */
16714 bfd_vma patched_inst = 0xf1a00000
16715 | (target_reg << 8)
16716 | (source_reg << 16)
16717 | (/*S=*/0 << 20)
16718 | ((value & 0x800) >> 11) << 26
16719 | ((value & 0x700) >> 8) << 12
16720 | (value & 0x0ff);
16721
16722 return patched_inst;
16723}
16724
16725static inline bfd_vma
9239bbd3 16726create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 16727 int first_reg)
16728{
16729 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16730 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
16731 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 16732 | (/*W=*/wback << 21)
16733 | (base_reg << 16)
9239bbd3
CM		 16734 | (num_words & 0x000000ff)
16735 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 16736 | (first_reg & 0x00000001) << 22;
16737
16738 return patched_inst;
16739}
16740
16741static inline bfd_vma
9239bbd3
CM		 16742create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
16743 int first_reg)
a504d23a
LA		 16744{
16745 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16746 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
16747 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 16748 | (base_reg << 16)
9239bbd3
CM		 16749 | (num_words & 0x000000ff)
16750 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 16751 | (first_reg & 0x00000001) << 22;
16752
16753 return patched_inst;
16754}
16755
16756static inline bfd_vma
16757create_instruction_udf_w (int value)
16758{
16759 /* A8.8.247 UDF (A8-758)
16760 Undefined (Encoding T2). */
16761 bfd_vma patched_inst = 0xf7f0a000
16762 | (value & 0x00000fff)
16763 | (value & 0x000f0000) << 16;
16764
16765 return patched_inst;
16766}
16767
16768static inline bfd_vma
16769create_instruction_udf (int value)
16770{
16771 /* A8.8.247 UDF (A8-758)
16772 Undefined (Encoding T1). */
16773 bfd_vma patched_inst = 0xde00
16774 | (value & 0xff);
16775
16776 return patched_inst;
16777}
16778
16779/* Functions writing an instruction in memory, returning the next
16780 memory position to write to. */
16781
16782static inline bfd_byte *
16783push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
16784 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16785{
16786 put_thumb2_insn (htab, output_bfd, insn, pt);
16787 return pt + 4;
16788}
16789
16790static inline bfd_byte *
16791push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
16792 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16793{
16794 put_thumb_insn (htab, output_bfd, insn, pt);
16795 return pt + 2;
16796}
16797
16798/* Function filling up a region in memory with T1 and T2 UDFs taking
16799 care of alignment. */
16800
16801static bfd_byte *
16802stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
16803 bfd * output_bfd,
16804 const bfd_byte * const base_stub_contents,
16805 bfd_byte * const from_stub_contents,
16806 const bfd_byte * const end_stub_contents)
16807{
16808 bfd_byte *current_stub_contents = from_stub_contents;
16809
16810 /* Fill the remaining of the stub with deterministic contents : UDF
16811 instructions.
16812 Check if realignment is needed on modulo 4 frontier using T1, to
16813 further use T2. */
16814 if ((current_stub_contents < end_stub_contents)
16815 && !((current_stub_contents - base_stub_contents) % 2)
16816 && ((current_stub_contents - base_stub_contents) % 4))
16817 current_stub_contents =
16818 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16819 create_instruction_udf (0));
16820
16821 for (; current_stub_contents < end_stub_contents;)
16822 current_stub_contents =
16823 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16824 create_instruction_udf_w (0));
16825
16826 return current_stub_contents;
16827}
16828
16829/* Functions writing the stream of instructions equivalent to the
16830 derived sequence for ldmia, ldmdb, vldm respectively. */
16831
16832static void
16833stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
16834 bfd * output_bfd,
16835 const insn32 initial_insn,
16836 const bfd_byte *const initial_insn_addr,
16837 bfd_byte *const base_stub_contents)
16838{
16839 int wback = (initial_insn & 0x00200000) >> 21;
16840 int ri, rn = (initial_insn & 0x000F0000) >> 16;
16841 int insn_all_registers = initial_insn & 0x0000ffff;
16842 int insn_low_registers, insn_high_registers;
16843 int usable_register_mask;
16844 int nb_registers = popcount (insn_all_registers);
16845 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16846 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16847 bfd_byte *current_stub_contents = base_stub_contents;
16848
16849 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
16850
16851 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16852 smaller than 8 registers load sequences that do not cause the
16853 hardware issue. */
16854 if (nb_registers <= 8)
16855 {
16856 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16857 current_stub_contents =
16858 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16859 initial_insn);
16860
16861 /* B initial_insn_addr+4. */
16862 if (!restore_pc)
16863 current_stub_contents =
16864 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16865 create_instruction_branch_absolute
82188b29
NC		 16866 (initial_insn_addr - current_stub_contents));
16867
a504d23a
LA		 16868
16869 /* Fill the remaining of the stub with deterministic contents. */
16870 current_stub_contents =
16871 stm32l4xx_fill_stub_udf (htab, output_bfd,
16872 base_stub_contents, current_stub_contents,
16873 base_stub_contents +
16874 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16875
16876 return;
16877 }
16878
16879 /* - reg_list[13] == 0. */
16880 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
16881
16882 /* - reg_list[14] & reg_list[15] != 1. */
16883 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16884
16885 /* - if (wback==1) reg_list[rn] == 0. */
16886 BFD_ASSERT (!wback || !restore_rn);
16887
16888 /* - nb_registers > 8. */
16889 BFD_ASSERT (popcount (insn_all_registers) > 8);
16890
16891 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16892
16893 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
16894 - One with the 7 lowest registers (register mask 0x007F)
16895 This LDM will finally contain between 2 and 7 registers
16896 - One with the 7 highest registers (register mask 0xDF80)
16897 This ldm will finally contain between 2 and 7 registers. */
16898 insn_low_registers = insn_all_registers & 0x007F;
16899 insn_high_registers = insn_all_registers & 0xDF80;
16900
16901 /* A spare register may be needed during this veneer to temporarily
16902 handle the base register. This register will be restored with the
16903 last LDM operation.
16904 The usable register may be any general purpose register (that
16905 excludes PC, SP, LR : register mask is 0x1FFF). */
16906 usable_register_mask = 0x1FFF;
16907
16908 /* Generate the stub function. */
16909 if (wback)
16910 {
16911 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
16912 current_stub_contents =
16913 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16914 create_instruction_ldmia
16915 (rn, /*wback=*/1, insn_low_registers));
16916
16917 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
16918 current_stub_contents =
16919 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16920 create_instruction_ldmia
16921 (rn, /*wback=*/1, insn_high_registers));
16922 if (!restore_pc)
16923 {
16924 /* B initial_insn_addr+4. */
16925 current_stub_contents =
16926 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16927 create_instruction_branch_absolute
82188b29 16928 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16929 }
16930 }
16931 else /* if (!wback). */
16932 {
16933 ri = rn;
16934
16935 /* If Rn is not part of the high-register-list, move it there. */
16936 if (!(insn_high_registers & (1 << rn)))
16937 {
16938 /* Choose a Ri in the high-register-list that will be restored. */
16939 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16940
16941 /* MOV Ri, Rn. */
16942 current_stub_contents =
16943 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16944 create_instruction_mov (ri, rn));
16945 }
16946
16947 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
16948 current_stub_contents =
16949 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16950 create_instruction_ldmia
16951 (ri, /*wback=*/1, insn_low_registers));
16952
16953 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
16954 current_stub_contents =
16955 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16956 create_instruction_ldmia
16957 (ri, /*wback=*/0, insn_high_registers));
16958
16959 if (!restore_pc)
16960 {
16961 /* B initial_insn_addr+4. */
16962 current_stub_contents =
16963 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16964 create_instruction_branch_absolute
82188b29 16965 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16966 }
16967 }
16968
16969 /* Fill the remaining of the stub with deterministic contents. */
16970 current_stub_contents =
16971 stm32l4xx_fill_stub_udf (htab, output_bfd,
16972 base_stub_contents, current_stub_contents,
16973 base_stub_contents +
16974 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16975}
16976
16977static void
16978stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
16979 bfd * output_bfd,
16980 const insn32 initial_insn,
16981 const bfd_byte *const initial_insn_addr,
16982 bfd_byte *const base_stub_contents)
16983{
16984 int wback = (initial_insn & 0x00200000) >> 21;
16985 int ri, rn = (initial_insn & 0x000f0000) >> 16;
16986 int insn_all_registers = initial_insn & 0x0000ffff;
16987 int insn_low_registers, insn_high_registers;
16988 int usable_register_mask;
16989 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16990 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16991 int nb_registers = popcount (insn_all_registers);
16992 bfd_byte *current_stub_contents = base_stub_contents;
16993
16994 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
16995
16996 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16997 smaller than 8 registers load sequences that do not cause the
16998 hardware issue. */
16999 if (nb_registers <= 8)
17000 {
17001 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17002 current_stub_contents =
17003 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17004 initial_insn);
17005
17006 /* B initial_insn_addr+4. */
17007 current_stub_contents =
17008 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17009 create_instruction_branch_absolute
82188b29 17010 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17011
17012 /* Fill the remaining of the stub with deterministic contents. */
17013 current_stub_contents =
17014 stm32l4xx_fill_stub_udf (htab, output_bfd,
17015 base_stub_contents, current_stub_contents,
17016 base_stub_contents +
17017 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17018
17019 return;
17020 }
17021
17022 /* - reg_list[13] == 0. */
17023 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
17024
17025 /* - reg_list[14] & reg_list[15] != 1. */
17026 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17027
17028 /* - if (wback==1) reg_list[rn] == 0. */
17029 BFD_ASSERT (!wback || !restore_rn);
17030
17031 /* - nb_registers > 8. */
17032 BFD_ASSERT (popcount (insn_all_registers) > 8);
17033
17034 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17035
17036 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
17037 - One with the 7 lowest registers (register mask 0x007F)
17038 This LDM will finally contain between 2 and 7 registers
17039 - One with the 7 highest registers (register mask 0xDF80)
17040 This ldm will finally contain between 2 and 7 registers. */
17041 insn_low_registers = insn_all_registers & 0x007F;
17042 insn_high_registers = insn_all_registers & 0xDF80;
17043
17044 /* A spare register may be needed during this veneer to temporarily
17045 handle the base register. This register will be restored with
17046 the last LDM operation.
17047 The usable register may be any general purpose register (that excludes
17048 PC, SP, LR : register mask is 0x1FFF). */
17049 usable_register_mask = 0x1FFF;
17050
17051 /* Generate the stub function. */
17052 if (!wback && !restore_pc && !restore_rn)
17053 {
17054 /* Choose a Ri in the low-register-list that will be restored. */
17055 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
17056
17057 /* MOV Ri, Rn. */
17058 current_stub_contents =
17059 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17060 create_instruction_mov (ri, rn));
17061
17062 /* LDMDB Ri!, {R-high-register-list}. */
17063 current_stub_contents =
17064 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17065 create_instruction_ldmdb
17066 (ri, /*wback=*/1, insn_high_registers));
17067
17068 /* LDMDB Ri, {R-low-register-list}. */
17069 current_stub_contents =
17070 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17071 create_instruction_ldmdb
17072 (ri, /*wback=*/0, insn_low_registers));
17073
17074 /* B initial_insn_addr+4. */
17075 current_stub_contents =
17076 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17077 create_instruction_branch_absolute
82188b29 17078 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17079 }
17080 else if (wback && !restore_pc && !restore_rn)
17081 {
17082 /* LDMDB Rn!, {R-high-register-list}. */
17083 current_stub_contents =
17084 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17085 create_instruction_ldmdb
17086 (rn, /*wback=*/1, insn_high_registers));
17087
17088 /* LDMDB Rn!, {R-low-register-list}. */
17089 current_stub_contents =
17090 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17091 create_instruction_ldmdb
17092 (rn, /*wback=*/1, insn_low_registers));
17093
17094 /* B initial_insn_addr+4. */
17095 current_stub_contents =
17096 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17097 create_instruction_branch_absolute
82188b29 17098 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17099 }
17100 else if (!wback && restore_pc && !restore_rn)
17101 {
17102 /* Choose a Ri in the high-register-list that will be restored. */
17103 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17104
17105 /* SUB Ri, Rn, #(4*nb_registers). */
17106 current_stub_contents =
17107 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17108 create_instruction_sub (ri, rn, (4 * nb_registers)));
17109
17110 /* LDMIA Ri!, {R-low-register-list}. */
17111 current_stub_contents =
17112 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17113 create_instruction_ldmia
17114 (ri, /*wback=*/1, insn_low_registers));
17115
17116 /* LDMIA Ri, {R-high-register-list}. */
17117 current_stub_contents =
17118 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17119 create_instruction_ldmia
17120 (ri, /*wback=*/0, insn_high_registers));
17121 }
17122 else if (wback && restore_pc && !restore_rn)
17123 {
17124 /* Choose a Ri in the high-register-list that will be restored. */
17125 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17126
17127 /* SUB Rn, Rn, #(4*nb_registers) */
17128 current_stub_contents =
17129 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17130 create_instruction_sub (rn, rn, (4 * nb_registers)));
17131
17132 /* MOV Ri, Rn. */
17133 current_stub_contents =
17134 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17135 create_instruction_mov (ri, rn));
17136
17137 /* LDMIA Ri!, {R-low-register-list}. */
17138 current_stub_contents =
17139 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17140 create_instruction_ldmia
17141 (ri, /*wback=*/1, insn_low_registers));
17142
17143 /* LDMIA Ri, {R-high-register-list}. */
17144 current_stub_contents =
17145 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17146 create_instruction_ldmia
17147 (ri, /*wback=*/0, insn_high_registers));
17148 }
17149 else if (!wback && !restore_pc && restore_rn)
17150 {
17151 ri = rn;
17152 if (!(insn_low_registers & (1 << rn)))
17153 {
17154 /* Choose a Ri in the low-register-list that will be restored. */
17155 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
17156
17157 /* MOV Ri, Rn. */
17158 current_stub_contents =
17159 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17160 create_instruction_mov (ri, rn));
17161 }
17162
17163 /* LDMDB Ri!, {R-high-register-list}. */
17164 current_stub_contents =
17165 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17166 create_instruction_ldmdb
17167 (ri, /*wback=*/1, insn_high_registers));
17168
17169 /* LDMDB Ri, {R-low-register-list}. */
17170 current_stub_contents =
17171 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17172 create_instruction_ldmdb
17173 (ri, /*wback=*/0, insn_low_registers));
17174
17175 /* B initial_insn_addr+4. */
17176 current_stub_contents =
17177 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17178 create_instruction_branch_absolute
82188b29 17179 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17180 }
17181 else if (!wback && restore_pc && restore_rn)
17182 {
17183 ri = rn;
17184 if (!(insn_high_registers & (1 << rn)))
17185 {
17186 /* Choose a Ri in the high-register-list that will be restored. */
17187 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17188 }
17189
17190 /* SUB Ri, Rn, #(4*nb_registers). */
17191 current_stub_contents =
17192 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17193 create_instruction_sub (ri, rn, (4 * nb_registers)));
17194
17195 /* LDMIA Ri!, {R-low-register-list}. */
17196 current_stub_contents =
17197 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17198 create_instruction_ldmia
17199 (ri, /*wback=*/1, insn_low_registers));
17200
17201 /* LDMIA Ri, {R-high-register-list}. */
17202 current_stub_contents =
17203 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17204 create_instruction_ldmia
17205 (ri, /*wback=*/0, insn_high_registers));
17206 }
17207 else if (wback && restore_rn)
17208 {
17209 /* The assembler should not have accepted to encode this. */
17210 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
17211 "undefined behavior.\n");
17212 }
17213
17214 /* Fill the remaining of the stub with deterministic contents. */
17215 current_stub_contents =
17216 stm32l4xx_fill_stub_udf (htab, output_bfd,
17217 base_stub_contents, current_stub_contents,
17218 base_stub_contents +
17219 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17220
17221}
17222
17223static void
17224stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
17225 bfd * output_bfd,
17226 const insn32 initial_insn,
17227 const bfd_byte *const initial_insn_addr,
17228 bfd_byte *const base_stub_contents)
17229{
9239bbd3 17230 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 17231 bfd_byte *current_stub_contents = base_stub_contents;
17232
17233 BFD_ASSERT (is_thumb2_vldm (initial_insn));
17234
17235 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 17236 smaller than 8 words load sequences that do not cause the
a504d23a 17237 hardware issue. */
9239bbd3 17238 if (num_words <= 8)
a504d23a
LA		 17239 {
17240 /* Untouched instruction. */
17241 current_stub_contents =
17242 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17243 initial_insn);
17244
17245 /* B initial_insn_addr+4. */
17246 current_stub_contents =
17247 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17248 create_instruction_branch_absolute
82188b29 17249 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17250 }
17251 else
17252 {
9239bbd3
CM		 17253 bfd_boolean is_dp = /* DP encoding. */
17254 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 17255 bfd_boolean is_ia_nobang = /* (IA without !). */
17256 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
17257 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
17258 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
17259 bfd_boolean is_db_bang = /* (DB with !). */
17260 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 17261 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 17262 /* d = UInt (Vd:D);. */
9239bbd3 17263 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 17264 | (((unsigned int)initial_insn << 9) >> 31);
17265
9239bbd3
CM		 17266 /* Compute the number of 8-words chunks needed to split. */
17267 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 17268 int chunk;
17269
17270 /* The test coverage has been done assuming the following
17271 hypothesis that exactly one of the previous is_ predicates is
17272 true. */
9239bbd3
CM		 17273 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
17274 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 17275
9239bbd3 17276 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 17277 cases, then we emit the adjustments:
17278
17279 vldm rx, {...}
17280 -> vldm rx!, {8_words_or_less} for each needed 8_word
17281 -> sub rx, rx, #size (list)
17282
17283 vldm rx!, {...}
17284 -> vldm rx!, {8_words_or_less} for each needed 8_word
17285 This also handles vpop instruction (when rx is sp)
17286
17287 vldmd rx!, {...}
17288 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 17289 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 17290 {
9239bbd3
CM		 17291 bfd_vma new_insn = 0;
17292
a504d23a
LA		 17293 if (is_ia_nobang || is_ia_bang)
17294 {
9239bbd3
CM		 17295 new_insn = create_instruction_vldmia
17296 (base_reg,
17297 is_dp,
17298 /*wback= . */1,
17299 chunks - (chunk + 1) ?
17300 8 : num_words - chunk * 8,
17301 first_reg + chunk * 8);
a504d23a
LA		 17302 }
17303 else if (is_db_bang)
17304 {
9239bbd3
CM		 17305 new_insn = create_instruction_vldmdb
17306 (base_reg,
17307 is_dp,
17308 chunks - (chunk + 1) ?
17309 8 : num_words - chunk * 8,
17310 first_reg + chunk * 8);
a504d23a 17311 }
9239bbd3
CM		 17312
17313 if (new_insn)
17314 current_stub_contents =
17315 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17316 new_insn);
a504d23a
LA		 17317 }
17318
17319 /* Only this case requires the base register compensation
17320 subtract. */
17321 if (is_ia_nobang)
17322 {
17323 current_stub_contents =
17324 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17325 create_instruction_sub
9239bbd3 17326 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 17327 }
17328
17329 /* B initial_insn_addr+4. */
17330 current_stub_contents =
17331 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17332 create_instruction_branch_absolute
82188b29 17333 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17334 }
17335
17336 /* Fill the remaining of the stub with deterministic contents. */
17337 current_stub_contents =
17338 stm32l4xx_fill_stub_udf (htab, output_bfd,
17339 base_stub_contents, current_stub_contents,
17340 base_stub_contents +
17341 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
17342}
17343
17344static void
17345stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
17346 bfd * output_bfd,
17347 const insn32 wrong_insn,
17348 const bfd_byte *const wrong_insn_addr,
17349 bfd_byte *const stub_contents)
17350{
17351 if (is_thumb2_ldmia (wrong_insn))
17352 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
17353 wrong_insn, wrong_insn_addr,
17354 stub_contents);
17355 else if (is_thumb2_ldmdb (wrong_insn))
17356 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
17357 wrong_insn, wrong_insn_addr,
17358 stub_contents);
17359 else if (is_thumb2_vldm (wrong_insn))
17360 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
17361 wrong_insn, wrong_insn_addr,
17362 stub_contents);
17363}
17364
17365/* End of stm32l4xx work-around. */
17366
17367
491d01d3
YU		 17368static void
17369elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
17370 asection *output_sec, Elf_Internal_Rela *rel)
17371{
17372 BFD_ASSERT (output_sec && rel);
17373 struct bfd_elf_section_reloc_data *output_reldata;
17374 struct elf32_arm_link_hash_table *htab;
17375 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
17376 Elf_Internal_Shdr *rel_hdr;
17377
17378
17379 if (oesd->rel.hdr)
17380 {
17381 rel_hdr = oesd->rel.hdr;
17382 output_reldata = &(oesd->rel);
17383 }
17384 else if (oesd->rela.hdr)
17385 {
17386 rel_hdr = oesd->rela.hdr;
17387 output_reldata = &(oesd->rela);
17388 }
17389 else
17390 {
17391 abort ();
17392 }
17393
17394 bfd_byte *erel = rel_hdr->contents;
17395 erel += output_reldata->count * rel_hdr->sh_entsize;
17396 htab = elf32_arm_hash_table (info);
17397 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
17398 output_reldata->count++;
17399}
17400
e489d0ae
PB		 17401/* Do code byteswapping. Return FALSE afterwards so that the section is
17402 written out as normal. */
17403
17404static bfd_boolean
c7b8f16e 17405elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 17406 struct bfd_link_info *link_info,
17407 asection *sec,
e489d0ae
PB		 17408 bfd_byte *contents)
17409{
48229727 17410 unsigned int mapcount, errcount;
8e3de13a 17411 _arm_elf_section_data *arm_data;
c7b8f16e 17412 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 17413 elf32_arm_section_map *map;
c7b8f16e 17414 elf32_vfp11_erratum_list *errnode;
a504d23a 17415 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 17416 bfd_vma ptr;
17417 bfd_vma end;
c7b8f16e 17418 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 17419 bfd_byte tmp;
48229727 17420 unsigned int i;
57e8b36a 17421
4dfe6ac6
NC		 17422 if (globals == NULL)
17423 return FALSE;
17424
8e3de13a
NC		 17425 /* If this section has not been allocated an _arm_elf_section_data
17426 structure then we cannot record anything. */
17427 arm_data = get_arm_elf_section_data (sec);
17428 if (arm_data == NULL)
17429 return FALSE;
17430
17431 mapcount = arm_data->mapcount;
17432 map = arm_data->map;
c7b8f16e
JB		 17433 errcount = arm_data->erratumcount;
17434
17435 if (errcount != 0)
17436 {
17437 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
17438
17439 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 17440 errnode = errnode->next)
17441 {
17442 bfd_vma target = errnode->vma - offset;
17443
17444 switch (errnode->type)
17445 {
17446 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
17447 {
17448 bfd_vma branch_to_veneer;
17449 /* Original condition code of instruction, plus bit mask for
17450 ARM B instruction. */
17451 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
17452 | 0x0a000000;
c7b8f16e
JB		 17453
17454 /* The instruction is before the label. */
91d6fa6a 17455 target -= 4;
c7b8f16e
JB		 17456
17457 /* Above offset included in -4 below. */
17458 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 17459 - errnode->vma - 4;
c7b8f16e
JB		 17460
17461 if ((signed) branch_to_veneer < -(1 << 25)
17462 || (signed) branch_to_veneer >= (1 << 25))
17463 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17464 "range"), output_bfd);
17465
99059e56
RM		 17466 insn |= (branch_to_veneer >> 2) & 0xffffff;
17467 contents[endianflip ^ target] = insn & 0xff;
17468 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17469 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17470 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17471 }
17472 break;
c7b8f16e
JB		 17473
17474 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 17475 {
17476 bfd_vma branch_from_veneer;
17477 unsigned int insn;
c7b8f16e 17478
99059e56
RM		 17479 /* Take size of veneer into account. */
17480 branch_from_veneer = errnode->u.v.branch->vma
17481 - errnode->vma - 12;
c7b8f16e
JB		 17482
17483 if ((signed) branch_from_veneer < -(1 << 25)
17484 || (signed) branch_from_veneer >= (1 << 25))
17485 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17486 "range"), output_bfd);
17487
99059e56
RM		 17488 /* Original instruction. */
17489 insn = errnode->u.v.branch->u.b.vfp_insn;
17490 contents[endianflip ^ target] = insn & 0xff;
17491 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17492 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17493 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17494
17495 /* Branch back to insn after original insn. */
17496 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
17497 contents[endianflip ^ (target + 4)] = insn & 0xff;
17498 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
17499 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
17500 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
17501 }
17502 break;
c7b8f16e 17503
99059e56
RM		 17504 default:
17505 abort ();
17506 }
17507 }
c7b8f16e 17508 }
e489d0ae 17509
a504d23a
LA		 17510 if (arm_data->stm32l4xx_erratumcount != 0)
17511 {
17512 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
17513 stm32l4xx_errnode != 0;
17514 stm32l4xx_errnode = stm32l4xx_errnode->next)
17515 {
17516 bfd_vma target = stm32l4xx_errnode->vma - offset;
17517
17518 switch (stm32l4xx_errnode->type)
17519 {
17520 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
17521 {
17522 unsigned int insn;
17523 bfd_vma branch_to_veneer =
17524 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
17525
17526 if ((signed) branch_to_veneer < -(1 << 24)
17527 || (signed) branch_to_veneer >= (1 << 24))
17528 {
17529 bfd_vma out_of_range =
17530 ((signed) branch_to_veneer < -(1 << 24)) ?
17531 - branch_to_veneer - (1 << 24) :
17532 ((signed) branch_to_veneer >= (1 << 24)) ?
17533 branch_to_veneer - (1 << 24) : 0;
17534
17535 (*_bfd_error_handler)
17536 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 17537 "Jump out of range by %ld bytes. "
a504d23a
LA		 17538 "Cannot encode branch instruction. "),
17539 output_bfd,
eee926f2 17540 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 17541 out_of_range);
17542 continue;
17543 }
17544
17545 insn = create_instruction_branch_absolute
82188b29 17546 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 17547
17548 /* The instruction is before the label. */
17549 target -= 4;
17550
17551 put_thumb2_insn (globals, output_bfd,
17552 (bfd_vma) insn, contents + target);
17553 }
17554 break;
17555
17556 case STM32L4XX_ERRATUM_VENEER:
17557 {
82188b29
NC		 17558 bfd_byte * veneer;
17559 bfd_byte * veneer_r;
a504d23a
LA		 17560 unsigned int insn;
17561
82188b29
NC		 17562 veneer = contents + target;
17563 veneer_r = veneer
17564 + stm32l4xx_errnode->u.b.veneer->vma
17565 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 17566
17567 if ((signed) (veneer_r - veneer -
17568 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17569 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17570 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17571 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
17572 || (signed) (veneer_r - veneer) >= (1 << 24))
17573 {
17574 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
17575 "veneer."), output_bfd);
17576 continue;
17577 }
17578
17579 /* Original instruction. */
17580 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
17581
17582 stm32l4xx_create_replacing_stub
17583 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
17584 }
17585 break;
17586
17587 default:
17588 abort ();
17589 }
17590 }
17591 }
17592
2468f9c9
PB		 17593 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
17594 {
17595 arm_unwind_table_edit *edit_node
99059e56 17596 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 17597 /* Now, sec->size is the size of the section we will write. The original
99059e56 17598 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 17599 markers) was sec->rawsize. (This isn't the case if we perform no
17600 edits, then rawsize will be zero and we should use size). */
21d799b5 17601 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 17602 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
17603 unsigned int in_index, out_index;
17604 bfd_vma add_to_offsets = 0;
17605
17606 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 17607 {
2468f9c9
PB		 17608 if (edit_node)
17609 {
17610 unsigned int edit_index = edit_node->index;
b38cadfb 17611
2468f9c9 17612 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 17613 {
2468f9c9
PB		 17614 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17615 contents + in_index * 8, add_to_offsets);
17616 out_index++;
17617 in_index++;
17618 }
17619 else if (in_index == edit_index
17620 || (in_index * 8 >= input_size
17621 && edit_index == UINT_MAX))
99059e56 17622 {
2468f9c9
PB		 17623 switch (edit_node->type)
17624 {
17625 case DELETE_EXIDX_ENTRY:
17626 in_index++;
17627 add_to_offsets += 8;
17628 break;
b38cadfb 17629
2468f9c9
PB		 17630 case INSERT_EXIDX_CANTUNWIND_AT_END:
17631 {
99059e56 17632 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 17633 bfd_vma text_offset = text_sec->output_section->vma
17634 + text_sec->output_offset
17635 + text_sec->size;
17636 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 17637 unsigned long prel31_offset;
2468f9c9
PB		 17638
17639 /* Note: this is meant to be equivalent to an
17640 R_ARM_PREL31 relocation. These synthetic
17641 EXIDX_CANTUNWIND markers are not relocated by the
17642 usual BFD method. */
17643 prel31_offset = (text_offset - exidx_offset)
17644 & 0x7ffffffful;
491d01d3
YU		 17645 if (bfd_link_relocatable (link_info))
17646 {
17647 /* Here relocation for new EXIDX_CANTUNWIND is
17648 created, so there is no need to
17649 adjust offset by hand. */
17650 prel31_offset = text_sec->output_offset
17651 + text_sec->size;
17652
17653 /* New relocation entity. */
17654 asection *text_out = text_sec->output_section;
17655 Elf_Internal_Rela rel;
17656 rel.r_addend = 0;
17657 rel.r_offset = exidx_offset;
17658 rel.r_info = ELF32_R_INFO (text_out->target_index,
17659 R_ARM_PREL31);
17660
17661 elf32_arm_add_relocation (output_bfd, link_info,
17662 sec->output_section,
17663 &rel);
17664 }
2468f9c9
PB		 17665
17666 /* First address we can't unwind. */
17667 bfd_put_32 (output_bfd, prel31_offset,
17668 &edited_contents[out_index * 8]);
17669
17670 /* Code for EXIDX_CANTUNWIND. */
17671 bfd_put_32 (output_bfd, 0x1,
17672 &edited_contents[out_index * 8 + 4]);
17673
17674 out_index++;
17675 add_to_offsets -= 8;
17676 }
17677 break;
17678 }
b38cadfb 17679
2468f9c9
PB		 17680 edit_node = edit_node->next;
17681 }
17682 }
17683 else
17684 {
17685 /* No more edits, copy remaining entries verbatim. */
17686 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17687 contents + in_index * 8, add_to_offsets);
17688 out_index++;
17689 in_index++;
17690 }
17691 }
17692
17693 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
17694 bfd_set_section_contents (output_bfd, sec->output_section,
17695 edited_contents,
17696 (file_ptr) sec->output_offset, sec->size);
17697
17698 return TRUE;
17699 }
17700
48229727
JB		 17701 /* Fix code to point to Cortex-A8 erratum stubs. */
17702 if (globals->fix_cortex_a8)
17703 {
17704 struct a8_branch_to_stub_data data;
17705
17706 data.writing_section = sec;
17707 data.contents = contents;
17708
a504d23a
LA		 17709 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
17710 & data);
48229727
JB		 17711 }
17712
e489d0ae
PB		 17713 if (mapcount == 0)
17714 return FALSE;
17715
c7b8f16e 17716 if (globals->byteswap_code)
e489d0ae 17717 {
c7b8f16e 17718 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 17719
c7b8f16e
JB		 17720 ptr = map[0].vma;
17721 for (i = 0; i < mapcount; i++)
99059e56
RM		 17722 {
17723 if (i == mapcount - 1)
c7b8f16e 17724 end = sec->size;
99059e56
RM		 17725 else
17726 end = map[i + 1].vma;
e489d0ae 17727
99059e56 17728 switch (map[i].type)
e489d0ae 17729 {
c7b8f16e
JB		 17730 case 'a':
17731 /* Byte swap code words. */
17732 while (ptr + 3 < end)
99059e56
RM		 17733 {
17734 tmp = contents[ptr];
17735 contents[ptr] = contents[ptr + 3];
17736 contents[ptr + 3] = tmp;
17737 tmp = contents[ptr + 1];
17738 contents[ptr + 1] = contents[ptr + 2];
17739 contents[ptr + 2] = tmp;
17740 ptr += 4;
17741 }
c7b8f16e 17742 break;
e489d0ae 17743
c7b8f16e
JB		 17744 case 't':
17745 /* Byte swap code halfwords. */
17746 while (ptr + 1 < end)
99059e56
RM		 17747 {
17748 tmp = contents[ptr];
17749 contents[ptr] = contents[ptr + 1];
17750 contents[ptr + 1] = tmp;
17751 ptr += 2;
17752 }
c7b8f16e
JB		 17753 break;
17754
17755 case 'd':
17756 /* Leave data alone. */
17757 break;
17758 }
99059e56
RM		 17759 ptr = end;
17760 }
e489d0ae 17761 }
8e3de13a 17762
93204d3a 17763 free (map);
47b2e99c 17764 arm_data->mapcount = -1;
c7b8f16e 17765 arm_data->mapsize = 0;
8e3de13a 17766 arm_data->map = NULL;
8e3de13a 17767
e489d0ae
PB		 17768 return FALSE;
17769}
17770
0beaef2b
PB		 17771/* Mangle thumb function symbols as we read them in. */
17772
8384fb8f 17773static bfd_boolean
0beaef2b
PB		 17774elf32_arm_swap_symbol_in (bfd * abfd,
17775 const void *psrc,
17776 const void *pshn,
17777 Elf_Internal_Sym *dst)
17778{
8384fb8f
AM		 17779 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
17780 return FALSE;
39d911fc 17781 dst->st_target_internal = 0;
0beaef2b
PB		 17782
17783 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 17784 the address. */
63e1a0fc
PB		 17785 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
17786 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 17787 {
63e1a0fc
PB		 17788 if (dst->st_value & 1)
17789 {
17790 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 17791 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
17792 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 17793 }
17794 else
39d911fc 17795 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 17796 }
17797 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
17798 {
17799 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 17800 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 17801 }
35fc36a8 17802 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 17803 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 17804 else
39d911fc 17805 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 17806
8384fb8f 17807 return TRUE;
0beaef2b
PB		 17808}
17809
17810
17811/* Mangle thumb function symbols as we write them out. */
17812
17813static void
17814elf32_arm_swap_symbol_out (bfd *abfd,
17815 const Elf_Internal_Sym *src,
17816 void *cdst,
17817 void *shndx)
17818{
17819 Elf_Internal_Sym newsym;
17820
17821 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
17822 of the address set, as per the new EABI. We do this unconditionally
17823 because objcopy does not set the elf header flags until after
17824 it writes out the symbol table. */
39d911fc 17825 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 17826 {
17827 newsym = *src;
34e77a92
RS		 17828 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
17829 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 17830 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 17831 {
17832 /* Do this only for defined symbols. At link type, the static
17833 linker will simulate the work of dynamic linker of resolving
17834 symbols and will carry over the thumbness of found symbols to
17835 the output symbol table. It's not clear how it happens, but
17836 the thumbness of undefined symbols can well be different at
17837 runtime, and writing '1' for them will be confusing for users
17838 and possibly for dynamic linker itself.
17839 */
17840 newsym.st_value |= 1;
17841 }
906e58ca 17842
0beaef2b
PB		 17843 src = &newsym;
17844 }
17845 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
17846}
17847
b294bdf8
MM		 17848/* Add the PT_ARM_EXIDX program header. */
17849
17850static bfd_boolean
906e58ca 17851elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 17852 struct bfd_link_info *info ATTRIBUTE_UNUSED)
17853{
17854 struct elf_segment_map *m;
17855 asection *sec;
17856
17857 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17858 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17859 {
17860 /* If there is already a PT_ARM_EXIDX header, then we do not
17861 want to add another one. This situation arises when running
17862 "strip"; the input binary already has the header. */
12bd6957 17863 m = elf_seg_map (abfd);
b294bdf8
MM		 17864 while (m && m->p_type != PT_ARM_EXIDX)
17865 m = m->next;
17866 if (!m)
17867 {
21d799b5 17868 m = (struct elf_segment_map *)
99059e56 17869 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 17870 if (m == NULL)
17871 return FALSE;
17872 m->p_type = PT_ARM_EXIDX;
17873 m->count = 1;
17874 m->sections[0] = sec;
17875
12bd6957
AM		 17876 m->next = elf_seg_map (abfd);
17877 elf_seg_map (abfd) = m;
b294bdf8
MM		 17878 }
17879 }
17880
17881 return TRUE;
17882}
17883
17884/* We may add a PT_ARM_EXIDX program header. */
17885
17886static int
a6b96beb
AM		 17887elf32_arm_additional_program_headers (bfd *abfd,
17888 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 17889{
17890 asection *sec;
17891
17892 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17893 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17894 return 1;
17895 else
17896 return 0;
17897}
17898
34e77a92
RS		 17899/* Hook called by the linker routine which adds symbols from an object
17900 file. */
17901
17902static bfd_boolean
17903elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
17904 Elf_Internal_Sym *sym, const char **namep,
17905 flagword *flagsp, asection **secp, bfd_vma *valp)
17906{
a43942db 17907 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 17908 && (abfd->flags & DYNAMIC) == 0
17909 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 17910 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 17911
c792917c
NC		 17912 if (elf32_arm_hash_table (info) == NULL)
17913 return FALSE;
17914
34e77a92
RS		 17915 if (elf32_arm_hash_table (info)->vxworks_p
17916 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
17917 flagsp, secp, valp))
17918 return FALSE;
17919
17920 return TRUE;
17921}
17922
0beaef2b 17923/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 17924const struct elf_size_info elf32_arm_size_info =
17925{
0beaef2b
PB		 17926 sizeof (Elf32_External_Ehdr),
17927 sizeof (Elf32_External_Phdr),
17928 sizeof (Elf32_External_Shdr),
17929 sizeof (Elf32_External_Rel),
17930 sizeof (Elf32_External_Rela),
17931 sizeof (Elf32_External_Sym),
17932 sizeof (Elf32_External_Dyn),
17933 sizeof (Elf_External_Note),
17934 4,
17935 1,
17936 32, 2,
17937 ELFCLASS32, EV_CURRENT,
17938 bfd_elf32_write_out_phdrs,
17939 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 17940 bfd_elf32_checksum_contents,
0beaef2b
PB		 17941 bfd_elf32_write_relocs,
17942 elf32_arm_swap_symbol_in,
17943 elf32_arm_swap_symbol_out,
17944 bfd_elf32_slurp_reloc_table,
17945 bfd_elf32_slurp_symbol_table,
17946 bfd_elf32_swap_dyn_in,
17947 bfd_elf32_swap_dyn_out,
17948 bfd_elf32_swap_reloc_in,
17949 bfd_elf32_swap_reloc_out,
17950 bfd_elf32_swap_reloca_in,
17951 bfd_elf32_swap_reloca_out
17952};
17953
685e70ae
VK		 17954static bfd_vma
17955read_code32 (const bfd *abfd, const bfd_byte *addr)
17956{
17957 /* V7 BE8 code is always little endian. */
17958 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17959 return bfd_getl32 (addr);
17960
17961 return bfd_get_32 (abfd, addr);
17962}
17963
17964static bfd_vma
17965read_code16 (const bfd *abfd, const bfd_byte *addr)
17966{
17967 /* V7 BE8 code is always little endian. */
17968 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17969 return bfd_getl16 (addr);
17970
17971 return bfd_get_16 (abfd, addr);
17972}
17973
6a631e86
YG		 17974/* Return size of plt0 entry starting at ADDR
17975 or (bfd_vma) -1 if size can not be determined. */
17976
17977static bfd_vma
17978elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
17979{
17980 bfd_vma first_word;
17981 bfd_vma plt0_size;
17982
685e70ae 17983 first_word = read_code32 (abfd, addr);
6a631e86
YG		 17984
17985 if (first_word == elf32_arm_plt0_entry[0])
17986 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
17987 else if (first_word == elf32_thumb2_plt0_entry[0])
17988 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
17989 else
17990 /* We don't yet handle this PLT format. */
17991 return (bfd_vma) -1;
17992
17993 return plt0_size;
17994}
17995
17996/* Return size of plt entry starting at offset OFFSET
17997 of plt section located at address START
17998 or (bfd_vma) -1 if size can not be determined. */
17999
18000static bfd_vma
18001elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
18002{
18003 bfd_vma first_insn;
18004 bfd_vma plt_size = 0;
18005 const bfd_byte *addr = start + offset;
18006
18007 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 18008 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 18009 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
18010
18011 /* Respect Thumb stub if necessary. */
685e70ae 18012 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 18013 {
18014 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
18015 }
18016
18017 /* Strip immediate from first add. */
685e70ae 18018 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 18019
18020#ifdef FOUR_WORD_PLT
18021 if (first_insn == elf32_arm_plt_entry[0])
18022 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
18023#else
18024 if (first_insn == elf32_arm_plt_entry_long[0])
18025 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
18026 else if (first_insn == elf32_arm_plt_entry_short[0])
18027 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
18028#endif
18029 else
18030 /* We don't yet handle this PLT format. */
18031 return (bfd_vma) -1;
18032
18033 return plt_size;
18034}
18035
18036/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
18037
18038static long
18039elf32_arm_get_synthetic_symtab (bfd *abfd,
18040 long symcount ATTRIBUTE_UNUSED,
18041 asymbol **syms ATTRIBUTE_UNUSED,
18042 long dynsymcount,
18043 asymbol **dynsyms,
18044 asymbol **ret)
18045{
18046 asection *relplt;
18047 asymbol *s;
18048 arelent *p;
18049 long count, i, n;
18050 size_t size;
18051 Elf_Internal_Shdr *hdr;
18052 char *names;
18053 asection *plt;
18054 bfd_vma offset;
18055 bfd_byte *data;
18056
18057 *ret = NULL;
18058
18059 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
18060 return 0;
18061
18062 if (dynsymcount <= 0)
18063 return 0;
18064
18065 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
18066 if (relplt == NULL)
18067 return 0;
18068
18069 hdr = &elf_section_data (relplt)->this_hdr;
18070 if (hdr->sh_link != elf_dynsymtab (abfd)
18071 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
18072 return 0;
18073
18074 plt = bfd_get_section_by_name (abfd, ".plt");
18075 if (plt == NULL)
18076 return 0;
18077
18078 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
18079 return -1;
18080
18081 data = plt->contents;
18082 if (data == NULL)
18083 {
18084 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
18085 return -1;
18086 bfd_cache_section_contents((asection *) plt, data);
18087 }
18088
18089 count = relplt->size / hdr->sh_entsize;
18090 size = count * sizeof (asymbol);
18091 p = relplt->relocation;
18092 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
18093 {
18094 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
18095 if (p->addend != 0)
18096 size += sizeof ("+0x") - 1 + 8;
18097 }
18098
18099 s = *ret = (asymbol *) bfd_malloc (size);
18100 if (s == NULL)
18101 return -1;
18102
18103 offset = elf32_arm_plt0_size (abfd, data);
18104 if (offset == (bfd_vma) -1)
18105 return -1;
18106
18107 names = (char *) (s + count);
18108 p = relplt->relocation;
18109 n = 0;
18110 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
18111 {
18112 size_t len;
18113
18114 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
18115 if (plt_size == (bfd_vma) -1)
18116 break;
18117
18118 *s = **p->sym_ptr_ptr;
18119 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
18120 we are defining a symbol, ensure one of them is set. */
18121 if ((s->flags & BSF_LOCAL) == 0)
18122 s->flags |= BSF_GLOBAL;
18123 s->flags |= BSF_SYNTHETIC;
18124 s->section = plt;
18125 s->value = offset;
18126 s->name = names;
18127 s->udata.p = NULL;
18128 len = strlen ((*p->sym_ptr_ptr)->name);
18129 memcpy (names, (*p->sym_ptr_ptr)->name, len);
18130 names += len;
18131 if (p->addend != 0)
18132 {
18133 char buf[30], *a;
18134
18135 memcpy (names, "+0x", sizeof ("+0x") - 1);
18136 names += sizeof ("+0x") - 1;
18137 bfd_sprintf_vma (abfd, buf, p->addend);
18138 for (a = buf; *a == '0'; ++a)
18139 ;
18140 len = strlen (a);
18141 memcpy (names, a, len);
18142 names += len;
18143 }
18144 memcpy (names, "@plt", sizeof ("@plt"));
18145 names += sizeof ("@plt");
18146 ++s, ++n;
18147 offset += plt_size;
18148 }
18149
18150 return n;
18151}
18152
ac4c9b04
MG		 18153static bfd_boolean
18154elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
18155{
18156 if (hdr->sh_flags & SHF_ARM_NOREAD)
18157 *flags |= SEC_ELF_NOREAD;
18158 return TRUE;
18159}
18160
18161static flagword
18162elf32_arm_lookup_section_flags (char *flag_name)
18163{
18164 if (!strcmp (flag_name, "SHF_ARM_NOREAD"))
18165 return SHF_ARM_NOREAD;
18166
18167 return SEC_NO_FLAGS;
18168}
18169
491d01d3
YU		 18170static unsigned int
18171elf32_arm_count_additional_relocs (asection *sec)
18172{
18173 struct _arm_elf_section_data *arm_data;
18174 arm_data = get_arm_elf_section_data (sec);
18175 return arm_data->additional_reloc_count;
18176}
18177
5522f910
NC		 18178/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
18179 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
18180 FALSE otherwise. ISECTION is the best guess matching section from the
18181 input bfd IBFD, but it might be NULL. */
18182
18183static bfd_boolean
18184elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
18185 bfd *obfd ATTRIBUTE_UNUSED,
18186 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
18187 Elf_Internal_Shdr *osection)
18188{
18189 switch (osection->sh_type)
18190 {
18191 case SHT_ARM_EXIDX:
18192 {
18193 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
18194 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
18195 unsigned i = 0;
18196
18197 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
18198 osection->sh_info = 0;
18199
18200 /* The sh_link field must be set to the text section associated with
18201 this index section. Unfortunately the ARM EHABI does not specify
18202 exactly how to determine this association. Our caller does try
18203 to match up OSECTION with its corresponding input section however
18204 so that is a good first guess. */
18205 if (isection != NULL
18206 && osection->bfd_section != NULL
18207 && isection->bfd_section != NULL
18208 && isection->bfd_section->output_section != NULL
18209 && isection->bfd_section->output_section == osection->bfd_section
18210 && iheaders != NULL
18211 && isection->sh_link > 0
18212 && isection->sh_link < elf_numsections (ibfd)
18213 && iheaders[isection->sh_link]->bfd_section != NULL
18214 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
18215 )
18216 {
18217 for (i = elf_numsections (obfd); i-- > 0;)
18218 if (oheaders[i]->bfd_section
18219 == iheaders[isection->sh_link]->bfd_section->output_section)
18220 break;
18221 }
18222
18223 if (i == 0)
18224 {
18225 /* Failing that we have to find a matching section ourselves. If
18226 we had the output section name available we could compare that
18227 with input section names. Unfortunately we don't. So instead
18228 we use a simple heuristic and look for the nearest executable
18229 section before this one. */
18230 for (i = elf_numsections (obfd); i-- > 0;)
18231 if (oheaders[i] == osection)
18232 break;
18233 if (i == 0)
18234 break;
18235
18236 while (i-- > 0)
18237 if (oheaders[i]->sh_type == SHT_PROGBITS
18238 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
18239 == (SHF_ALLOC | SHF_EXECINSTR))
18240 break;
18241 }
18242
18243 if (i)
18244 {
18245 osection->sh_link = i;
18246 /* If the text section was part of a group
18247 then the index section should be too. */
18248 if (oheaders[i]->sh_flags & SHF_GROUP)
18249 osection->sh_flags |= SHF_GROUP;
18250 return TRUE;
18251 }
18252 }
18253 break;
18254
18255 case SHT_ARM_PREEMPTMAP:
18256 osection->sh_flags = SHF_ALLOC;
18257 break;
18258
18259 case SHT_ARM_ATTRIBUTES:
18260 case SHT_ARM_DEBUGOVERLAY:
18261 case SHT_ARM_OVERLAYSECTION:
18262 default:
18263 break;
18264 }
18265
18266 return FALSE;
18267}
18268
d691934d
NC		 18269/* Returns TRUE if NAME is an ARM mapping symbol.
18270 Traditionally the symbols $a, $d and $t have been used.
18271 The ARM ELF standard also defines $x (for A64 code). It also allows a
18272 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
18273 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
18274 not support them here. $t.x indicates the start of ThumbEE instructions. */
18275
18276static bfd_boolean
18277is_arm_mapping_symbol (const char * name)
18278{
18279 return name != NULL /* Paranoia. */
18280 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
18281 the mapping symbols could have acquired a prefix.
18282 We do not support this here, since such symbols no
18283 longer conform to the ARM ELF ABI. */
18284 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
18285 && (name[2] == 0 || name[2] == '.');
18286 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
18287 any characters that follow the period are legal characters for the body
18288 of a symbol's name. For now we just assume that this is the case. */
18289}
18290
fca2a38f
NC		 18291/* Make sure that mapping symbols in object files are not removed via the
18292 "strip --strip-unneeded" tool. These symbols are needed in order to
18293 correctly generate interworking veneers, and for byte swapping code
18294 regions. Once an object file has been linked, it is safe to remove the
18295 symbols as they will no longer be needed. */
18296
18297static void
18298elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
18299{
18300 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 18301 && sym->section != bfd_abs_section_ptr
d691934d 18302 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 18303 sym->flags |= BSF_KEEP;
18304}
18305
5522f910
NC		 18306#undef elf_backend_copy_special_section_fields
18307#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
18308
252b5132 18309#define ELF_ARCH bfd_arch_arm
ae95ffa6 18310#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 18311#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 18312#ifdef __QNXTARGET__
18313#define ELF_MAXPAGESIZE 0x1000
18314#else
7572ca89 18315#define ELF_MAXPAGESIZE 0x10000
d0facd1b 18316#endif
b1342370 18317#define ELF_MINPAGESIZE 0x1000
24718e3b 18318#define ELF_COMMONPAGESIZE 0x1000
252b5132 18319
ba93b8ac
DJ		 18320#define bfd_elf32_mkobject elf32_arm_mkobject
18321
99e4ae17
AJ		 18322#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
18323#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 18324#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
18325#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
18326#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 18327#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 18328#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 18329#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 18330#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 18331#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 18332#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 18333#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 18334#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 18335
18336#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
18337#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 18338#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 18339#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
18340#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 18341#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 18342#define elf_backend_write_section elf32_arm_write_section
252b5132 18343#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 18344#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 18345#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
18346#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
18347#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 18348#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 18349#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 18350#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 18351#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 18352#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 18353#define elf_backend_fake_sections elf32_arm_fake_sections
18354#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 18355#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 18356#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 18357#define elf_backend_size_info elf32_arm_size_info
b294bdf8 18358#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 18359#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
18360#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
18361#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 18362#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 18363#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 18364#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 18365
18366#define elf_backend_can_refcount 1
18367#define elf_backend_can_gc_sections 1
18368#define elf_backend_plt_readonly 1
18369#define elf_backend_want_got_plt 1
18370#define elf_backend_want_plt_sym 0
18371#define elf_backend_may_use_rel_p 1
18372#define elf_backend_may_use_rela_p 0
4e7fd91e 18373#define elf_backend_default_use_rela_p 0
252b5132 18374
04f7c78d 18375#define elf_backend_got_header_size 12
b68a20d6 18376#define elf_backend_extern_protected_data 1
04f7c78d 18377
906e58ca
NC		 18378#undef elf_backend_obj_attrs_vendor
18379#define elf_backend_obj_attrs_vendor "aeabi"
18380#undef elf_backend_obj_attrs_section
18381#define elf_backend_obj_attrs_section ".ARM.attributes"
18382#undef elf_backend_obj_attrs_arg_type
18383#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
18384#undef elf_backend_obj_attrs_section_type
104d59d1 18385#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 18386#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
18387#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 18388
ac4c9b04
MG		 18389#undef elf_backend_section_flags
18390#define elf_backend_section_flags elf32_arm_section_flags
18391#undef elf_backend_lookup_section_flags_hook
18392#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
18393
252b5132 18394#include "elf32-target.h"
7f266840 18395
b38cadfb
NC		 18396/* Native Client targets. */
18397
18398#undef TARGET_LITTLE_SYM
6d00b590 18399#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 18400#undef TARGET_LITTLE_NAME
18401#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
18402#undef TARGET_BIG_SYM
6d00b590 18403#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 18404#undef TARGET_BIG_NAME
18405#define TARGET_BIG_NAME "elf32-bigarm-nacl"
18406
18407/* Like elf32_arm_link_hash_table_create -- but overrides
18408 appropriately for NaCl. */
18409
18410static struct bfd_link_hash_table *
18411elf32_arm_nacl_link_hash_table_create (bfd *abfd)
18412{
18413 struct bfd_link_hash_table *ret;
18414
18415 ret = elf32_arm_link_hash_table_create (abfd);
18416 if (ret)
18417 {
18418 struct elf32_arm_link_hash_table *htab
18419 = (struct elf32_arm_link_hash_table *) ret;
18420
18421 htab->nacl_p = 1;
18422
18423 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
18424 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
18425 }
18426 return ret;
18427}
18428
18429/* Since NaCl doesn't use the ARM-specific unwind format, we don't
18430 really need to use elf32_arm_modify_segment_map. But we do it
18431 anyway just to reduce gratuitous differences with the stock ARM backend. */
18432
18433static bfd_boolean
18434elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
18435{
18436 return (elf32_arm_modify_segment_map (abfd, info)
18437 && nacl_modify_segment_map (abfd, info));
18438}
18439
887badb3
RM		 18440static void
18441elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
18442{
18443 elf32_arm_final_write_processing (abfd, linker);
18444 nacl_final_write_processing (abfd, linker);
18445}
18446
6a631e86
YG		 18447static bfd_vma
18448elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
18449 const arelent *rel ATTRIBUTE_UNUSED)
18450{
18451 return plt->vma
18452 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
18453 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
18454}
887badb3 18455
b38cadfb 18456#undef elf32_bed
6a631e86 18457#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 18458#undef bfd_elf32_bfd_link_hash_table_create
18459#define bfd_elf32_bfd_link_hash_table_create \
18460 elf32_arm_nacl_link_hash_table_create
18461#undef elf_backend_plt_alignment
6a631e86 18462#define elf_backend_plt_alignment 4
b38cadfb
NC		 18463#undef elf_backend_modify_segment_map
18464#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
18465#undef elf_backend_modify_program_headers
18466#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 18467#undef elf_backend_final_write_processing
18468#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 18469#undef bfd_elf32_get_synthetic_symtab
18470#undef elf_backend_plt_sym_val
18471#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 18472#undef elf_backend_copy_special_section_fields
b38cadfb 18473
887badb3
RM		 18474#undef ELF_MINPAGESIZE
18475#undef ELF_COMMONPAGESIZE
18476
b38cadfb
NC		 18477
18478#include "elf32-target.h"
18479
18480/* Reset to defaults. */
18481#undef elf_backend_plt_alignment
18482#undef elf_backend_modify_segment_map
18483#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
18484#undef elf_backend_modify_program_headers
887badb3
RM		 18485#undef elf_backend_final_write_processing
18486#define elf_backend_final_write_processing elf32_arm_final_write_processing
18487#undef ELF_MINPAGESIZE
18488#define ELF_MINPAGESIZE 0x1000
18489#undef ELF_COMMONPAGESIZE
18490#define ELF_COMMONPAGESIZE 0x1000
18491
b38cadfb 18492
906e58ca 18493/* VxWorks Targets. */
4e7fd91e 18494
906e58ca 18495#undef TARGET_LITTLE_SYM
6d00b590 18496#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 18497#undef TARGET_LITTLE_NAME
4e7fd91e 18498#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 18499#undef TARGET_BIG_SYM
6d00b590 18500#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 18501#undef TARGET_BIG_NAME
4e7fd91e
PB		 18502#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
18503
18504/* Like elf32_arm_link_hash_table_create -- but overrides
18505 appropriately for VxWorks. */
906e58ca 18506
4e7fd91e
PB		 18507static struct bfd_link_hash_table *
18508elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
18509{
18510 struct bfd_link_hash_table *ret;
18511
18512 ret = elf32_arm_link_hash_table_create (abfd);
18513 if (ret)
18514 {
18515 struct elf32_arm_link_hash_table *htab
00a97672 18516 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 18517 htab->use_rel = 0;
00a97672 18518 htab->vxworks_p = 1;
4e7fd91e
PB		 18519 }
18520 return ret;
906e58ca 18521}
4e7fd91e 18522
00a97672
RS		 18523static void
18524elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
18525{
18526 elf32_arm_final_write_processing (abfd, linker);
18527 elf_vxworks_final_write_processing (abfd, linker);
18528}
18529
906e58ca 18530#undef elf32_bed
4e7fd91e
PB		 18531#define elf32_bed elf32_arm_vxworks_bed
18532
906e58ca
NC		 18533#undef bfd_elf32_bfd_link_hash_table_create
18534#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 18535#undef elf_backend_final_write_processing
18536#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
18537#undef elf_backend_emit_relocs
18538#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 18539
906e58ca 18540#undef elf_backend_may_use_rel_p
00a97672 18541#define elf_backend_may_use_rel_p 0
906e58ca 18542#undef elf_backend_may_use_rela_p
00a97672 18543#define elf_backend_may_use_rela_p 1
906e58ca 18544#undef elf_backend_default_use_rela_p
00a97672 18545#define elf_backend_default_use_rela_p 1
906e58ca 18546#undef elf_backend_want_plt_sym
00a97672 18547#define elf_backend_want_plt_sym 1
906e58ca 18548#undef ELF_MAXPAGESIZE
00a97672 18549#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 18550
18551#include "elf32-target.h"
18552
18553
21d799b5
NC		 18554/* Merge backend specific data from an object file to the output
18555 object file when linking. */
18556
18557static bfd_boolean
18558elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
18559{
18560 flagword out_flags;
18561 flagword in_flags;
18562 bfd_boolean flags_compatible = TRUE;
18563 asection *sec;
18564
cc643b88 18565 /* Check if we have the same endianness. */
21d799b5
NC		 18566 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
18567 return FALSE;
18568
18569 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
18570 return TRUE;
18571
18572 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
18573 return FALSE;
18574
18575 /* The input BFD must have had its flags initialised. */
18576 /* The following seems bogus to me -- The flags are initialized in
18577 the assembler but I don't think an elf_flags_init field is
18578 written into the object. */
18579 /* BFD_ASSERT (elf_flags_init (ibfd)); */
18580
18581 in_flags = elf_elfheader (ibfd)->e_flags;
18582 out_flags = elf_elfheader (obfd)->e_flags;
18583
18584 /* In theory there is no reason why we couldn't handle this. However
18585 in practice it isn't even close to working and there is no real
18586 reason to want it. */
18587 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
18588 && !(ibfd->flags & DYNAMIC)
18589 && (in_flags & EF_ARM_BE8))
18590 {
18591 _bfd_error_handler (_("error: %B is already in final BE8 format"),
18592 ibfd);
18593 return FALSE;
18594 }
18595
18596 if (!elf_flags_init (obfd))
18597 {
18598 /* If the input is the default architecture and had the default
18599 flags then do not bother setting the flags for the output
18600 architecture, instead allow future merges to do this. If no
18601 future merges ever set these flags then they will retain their
99059e56
RM		 18602 uninitialised values, which surprise surprise, correspond
18603 to the default values. */
21d799b5
NC		 18604 if (bfd_get_arch_info (ibfd)->the_default
18605 && elf_elfheader (ibfd)->e_flags == 0)
18606 return TRUE;
18607
18608 elf_flags_init (obfd) = TRUE;
18609 elf_elfheader (obfd)->e_flags = in_flags;
18610
18611 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
18612 && bfd_get_arch_info (obfd)->the_default)
18613 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
18614
18615 return TRUE;
18616 }
18617
18618 /* Determine what should happen if the input ARM architecture
18619 does not match the output ARM architecture. */
18620 if (! bfd_arm_merge_machines (ibfd, obfd))
18621 return FALSE;
18622
18623 /* Identical flags must be compatible. */
18624 if (in_flags == out_flags)
18625 return TRUE;
18626
18627 /* Check to see if the input BFD actually contains any sections. If
18628 not, its flags may not have been initialised either, but it
18629 cannot actually cause any incompatiblity. Do not short-circuit
18630 dynamic objects; their section list may be emptied by
18631 elf_link_add_object_symbols.
18632
18633 Also check to see if there are no code sections in the input.
18634 In this case there is no need to check for code specific flags.
18635 XXX - do we need to worry about floating-point format compatability
18636 in data sections ? */
18637 if (!(ibfd->flags & DYNAMIC))
18638 {
18639 bfd_boolean null_input_bfd = TRUE;
18640 bfd_boolean only_data_sections = TRUE;
18641
18642 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
18643 {
18644 /* Ignore synthetic glue sections. */
18645 if (strcmp (sec->name, ".glue_7")
18646 && strcmp (sec->name, ".glue_7t"))
18647 {
18648 if ((bfd_get_section_flags (ibfd, sec)
18649 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
18650 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 18651 only_data_sections = FALSE;
21d799b5
NC		 18652
18653 null_input_bfd = FALSE;
18654 break;
18655 }
18656 }
18657
18658 if (null_input_bfd || only_data_sections)
18659 return TRUE;
18660 }
18661
18662 /* Complain about various flag mismatches. */
18663 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
18664 EF_ARM_EABI_VERSION (out_flags)))
18665 {
18666 _bfd_error_handler
18667 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
18668 ibfd, obfd,
18669 (in_flags & EF_ARM_EABIMASK) >> 24,
18670 (out_flags & EF_ARM_EABIMASK) >> 24);
18671 return FALSE;
18672 }
18673
18674 /* Not sure what needs to be checked for EABI versions >= 1. */
18675 /* VxWorks libraries do not use these flags. */
18676 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
18677 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
18678 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
18679 {
18680 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
18681 {
18682 _bfd_error_handler
18683 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
18684 ibfd, obfd,
18685 in_flags & EF_ARM_APCS_26 ? 26 : 32,
18686 out_flags & EF_ARM_APCS_26 ? 26 : 32);
18687 flags_compatible = FALSE;
18688 }
18689
18690 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
18691 {
18692 if (in_flags & EF_ARM_APCS_FLOAT)
18693 _bfd_error_handler
18694 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
18695 ibfd, obfd);
18696 else
18697 _bfd_error_handler
18698 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
18699 ibfd, obfd);
18700
18701 flags_compatible = FALSE;
18702 }
18703
18704 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
18705 {
18706 if (in_flags & EF_ARM_VFP_FLOAT)
18707 _bfd_error_handler
18708 (_("error: %B uses VFP instructions, whereas %B does not"),
18709 ibfd, obfd);
18710 else
18711 _bfd_error_handler
18712 (_("error: %B uses FPA instructions, whereas %B does not"),
18713 ibfd, obfd);
18714
18715 flags_compatible = FALSE;
18716 }
18717
18718 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
18719 {
18720 if (in_flags & EF_ARM_MAVERICK_FLOAT)
18721 _bfd_error_handler
18722 (_("error: %B uses Maverick instructions, whereas %B does not"),
18723 ibfd, obfd);
18724 else
18725 _bfd_error_handler
18726 (_("error: %B does not use Maverick instructions, whereas %B does"),
18727 ibfd, obfd);
18728
18729 flags_compatible = FALSE;
18730 }
18731
18732#ifdef EF_ARM_SOFT_FLOAT
18733 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
18734 {
18735 /* We can allow interworking between code that is VFP format
18736 layout, and uses either soft float or integer regs for
18737 passing floating point arguments and results. We already
18738 know that the APCS_FLOAT flags match; similarly for VFP
18739 flags. */
18740 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
18741 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
18742 {
18743 if (in_flags & EF_ARM_SOFT_FLOAT)
18744 _bfd_error_handler
18745 (_("error: %B uses software FP, whereas %B uses hardware FP"),
18746 ibfd, obfd);
18747 else
18748 _bfd_error_handler
18749 (_("error: %B uses hardware FP, whereas %B uses software FP"),
18750 ibfd, obfd);
18751
18752 flags_compatible = FALSE;
18753 }
18754 }
18755#endif
18756
18757 /* Interworking mismatch is only a warning. */
18758 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
18759 {
18760 if (in_flags & EF_ARM_INTERWORK)
18761 {
18762 _bfd_error_handler
18763 (_("Warning: %B supports interworking, whereas %B does not"),
18764 ibfd, obfd);
18765 }
18766 else
18767 {
18768 _bfd_error_handler
18769 (_("Warning: %B does not support interworking, whereas %B does"),
18770 ibfd, obfd);
18771 }
18772 }
18773 }
18774
18775 return flags_compatible;
18776}
18777
18778
906e58ca 18779/* Symbian OS Targets. */
7f266840 18780
906e58ca 18781#undef TARGET_LITTLE_SYM
6d00b590 18782#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 18783#undef TARGET_LITTLE_NAME
7f266840 18784#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 18785#undef TARGET_BIG_SYM
6d00b590 18786#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 18787#undef TARGET_BIG_NAME
7f266840
DJ		 18788#define TARGET_BIG_NAME "elf32-bigarm-symbian"
18789
18790/* Like elf32_arm_link_hash_table_create -- but overrides
18791 appropriately for Symbian OS. */
906e58ca 18792
7f266840
DJ		 18793static struct bfd_link_hash_table *
18794elf32_arm_symbian_link_hash_table_create (bfd *abfd)
18795{
18796 struct bfd_link_hash_table *ret;
18797
18798 ret = elf32_arm_link_hash_table_create (abfd);
18799 if (ret)
18800 {
18801 struct elf32_arm_link_hash_table *htab
18802 = (struct elf32_arm_link_hash_table *)ret;
18803 /* There is no PLT header for Symbian OS. */
18804 htab->plt_header_size = 0;
95720a86
DJ		 18805 /* The PLT entries are each one instruction and one word. */
18806 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 18807 htab->symbian_p = 1;
33bfe774
JB		 18808 /* Symbian uses armv5t or above, so use_blx is always true. */
18809 htab->use_blx = 1;
67687978 18810 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 18811 }
18812 return ret;
906e58ca 18813}
7f266840 18814
b35d266b 18815static const struct bfd_elf_special_section
551b43fd 18816elf32_arm_symbian_special_sections[] =
7f266840 18817{
5cd3778d
MM		 18818 /* In a BPABI executable, the dynamic linking sections do not go in
18819 the loadable read-only segment. The post-linker may wish to
18820 refer to these sections, but they are not part of the final
18821 program image. */
0112cd26
NC		 18822 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
18823 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
18824 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
18825 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
18826 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 18827 /* These sections do not need to be writable as the SymbianOS
18828 postlinker will arrange things so that no dynamic relocation is
18829 required. */
0112cd26
NC		 18830 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
18831 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
18832 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
18833 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 18834};
18835
c3c76620 18836static void
906e58ca 18837elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 18838 struct bfd_link_info *link_info)
c3c76620
MM		 18839{
18840 /* BPABI objects are never loaded directly by an OS kernel; they are
18841 processed by a postlinker first, into an OS-specific format. If
18842 the D_PAGED bit is set on the file, BFD will align segments on
18843 page boundaries, so that an OS can directly map the file. With
18844 BPABI objects, that just results in wasted space. In addition,
18845 because we clear the D_PAGED bit, map_sections_to_segments will
18846 recognize that the program headers should not be mapped into any
18847 loadable segment. */
18848 abfd->flags &= ~D_PAGED;
906e58ca 18849 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 18850}
7f266840
DJ		 18851
18852static bfd_boolean
906e58ca 18853elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 18854 struct bfd_link_info *info)
7f266840
DJ		 18855{
18856 struct elf_segment_map *m;
18857 asection *dynsec;
18858
7f266840
DJ		 18859 /* BPABI shared libraries and executables should have a PT_DYNAMIC
18860 segment. However, because the .dynamic section is not marked
18861 with SEC_LOAD, the generic ELF code will not create such a
18862 segment. */
18863 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
18864 if (dynsec)
18865 {
12bd6957 18866 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 18867 if (m->p_type == PT_DYNAMIC)
18868 break;
18869
18870 if (m == NULL)
18871 {
18872 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 18873 m->next = elf_seg_map (abfd);
18874 elf_seg_map (abfd) = m;
8ded5a0f 18875 }
7f266840
DJ		 18876 }
18877
b294bdf8
MM		 18878 /* Also call the generic arm routine. */
18879 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 18880}
18881
95720a86
DJ		 18882/* Return address for Ith PLT stub in section PLT, for relocation REL
18883 or (bfd_vma) -1 if it should not be included. */
18884
18885static bfd_vma
18886elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
18887 const arelent *rel ATTRIBUTE_UNUSED)
18888{
18889 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
18890}
18891
8029a119 18892#undef elf32_bed
7f266840
DJ		 18893#define elf32_bed elf32_arm_symbian_bed
18894
18895/* The dynamic sections are not allocated on SymbianOS; the postlinker
18896 will process them and then discard them. */
906e58ca 18897#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 18898#define ELF_DYNAMIC_SEC_FLAGS \
18899 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
18900
00a97672 18901#undef elf_backend_emit_relocs
c3c76620 18902
906e58ca
NC		 18903#undef bfd_elf32_bfd_link_hash_table_create
18904#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
18905#undef elf_backend_special_sections
18906#define elf_backend_special_sections elf32_arm_symbian_special_sections
18907#undef elf_backend_begin_write_processing
18908#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
18909#undef elf_backend_final_write_processing
18910#define elf_backend_final_write_processing elf32_arm_final_write_processing
18911
18912#undef elf_backend_modify_segment_map
7f266840
DJ		 18913#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
18914
18915/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 18916#undef elf_backend_got_header_size
7f266840
DJ		 18917#define elf_backend_got_header_size 0
18918
18919/* Similarly, there is no .got.plt section. */
906e58ca 18920#undef elf_backend_want_got_plt
7f266840
DJ		 18921#define elf_backend_want_got_plt 0
18922
906e58ca 18923#undef elf_backend_plt_sym_val
95720a86
DJ		 18924#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
18925
906e58ca 18926#undef elf_backend_may_use_rel_p
00a97672 18927#define elf_backend_may_use_rel_p 1
906e58ca 18928#undef elf_backend_may_use_rela_p
00a97672 18929#define elf_backend_may_use_rela_p 0
906e58ca 18930#undef elf_backend_default_use_rela_p
00a97672 18931#define elf_backend_default_use_rela_p 0
906e58ca 18932#undef elf_backend_want_plt_sym
00a97672 18933#define elf_backend_want_plt_sym 0
906e58ca 18934#undef ELF_MAXPAGESIZE
00a97672 18935#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 18936
7f266840 18937#include "elf32-target.h"
GDB Binutils - Deliverables
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