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Fix snafu parsing $ORIGIN.
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca 3161 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3162 asection *sdynbss;
3163 asection *srelbss;
5e681ec4 3164
906e58ca
NC		 3165 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3166 asection *srelplt2;
00a97672 3167
0855e32b
NS		 3168 /* The offset into splt of the PLT entry for the TLS descriptor
3169 resolver. Special values are 0, if not necessary (or not found
3170 to be necessary yet), and -1 if needed but not determined
3171 yet. */
3172 bfd_vma dt_tlsdesc_plt;
3173
3174 /* The offset into sgot of the GOT entry used by the PLT entry
3175 above. */
b38cadfb 3176 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3177
3178 /* Offset in .plt section of tls_arm_trampoline. */
3179 bfd_vma tls_trampoline;
3180
906e58ca
NC		 3181 /* Data for R_ARM_TLS_LDM32 relocations. */
3182 union
3183 {
3184 bfd_signed_vma refcount;
3185 bfd_vma offset;
3186 } tls_ldm_got;
b7693d02 3187
87d72d41
AM		 3188 /* Small local sym cache. */
3189 struct sym_cache sym_cache;
906e58ca
NC		 3190
3191 /* For convenience in allocate_dynrelocs. */
3192 bfd * obfd;
3193
0855e32b
NS		 3194 /* The amount of space used by the reserved portion of the sgotplt
3195 section, plus whatever space is used by the jump slots. */
3196 bfd_vma sgotplt_jump_table_size;
3197
906e58ca
NC		 3198 /* The stub hash table. */
3199 struct bfd_hash_table stub_hash_table;
3200
3201 /* Linker stub bfd. */
3202 bfd *stub_bfd;
3203
3204 /* Linker call-backs. */
6bde4c52
TP		 3205 asection * (*add_stub_section) (const char *, asection *, asection *,
3206 unsigned int);
906e58ca
NC		 3207 void (*layout_sections_again) (void);
3208
3209 /* Array to keep track of which stub sections have been created, and
3210 information on stub grouping. */
21d799b5 3211 struct map_stub *stub_group;
906e58ca 3212
4ba2ef8f
TP		 3213 /* Input stub section holding secure gateway veneers. */
3214 asection *cmse_stub_sec;
3215
0955507f
TP		 3216 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3217 start to be allocated. */
3218 bfd_vma new_cmse_stub_offset;
3219
fe33d2fa 3220 /* Number of elements in stub_group. */
7292b3ac 3221 unsigned int top_id;
fe33d2fa 3222
906e58ca
NC		 3223 /* Assorted information used by elf32_arm_size_stubs. */
3224 unsigned int bfd_count;
7292b3ac 3225 unsigned int top_index;
906e58ca
NC		 3226 asection **input_list;
3227};
252b5132 3228
a504d23a
LA		 3229static inline int
3230ctz (unsigned int mask)
3231{
3232#if GCC_VERSION >= 3004
3233 return __builtin_ctz (mask);
3234#else
3235 unsigned int i;
3236
3237 for (i = 0; i < 8 * sizeof (mask); i++)
3238 {
3239 if (mask & 0x1)
3240 break;
3241 mask = (mask >> 1);
3242 }
3243 return i;
3244#endif
3245}
3246
3247static inline int
3248popcount (unsigned int mask)
3249{
3250#if GCC_VERSION >= 3004
3251 return __builtin_popcount (mask);
3252#else
3253 unsigned int i, sum = 0;
3254
3255 for (i = 0; i < 8 * sizeof (mask); i++)
3256 {
3257 if (mask & 0x1)
3258 sum++;
3259 mask = (mask >> 1);
3260 }
3261 return sum;
3262#endif
3263}
3264
780a67af
NC		 3265/* Create an entry in an ARM ELF linker hash table. */
3266
3267static struct bfd_hash_entry *
57e8b36a 3268elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3269 struct bfd_hash_table * table,
3270 const char * string)
780a67af
NC		 3271{
3272 struct elf32_arm_link_hash_entry * ret =
3273 (struct elf32_arm_link_hash_entry *) entry;
3274
3275 /* Allocate the structure if it has not already been allocated by a
3276 subclass. */
906e58ca 3277 if (ret == NULL)
21d799b5 3278 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3279 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3280 if (ret == NULL)
780a67af
NC		 3281 return (struct bfd_hash_entry *) ret;
3282
3283 /* Call the allocation method of the superclass. */
3284 ret = ((struct elf32_arm_link_hash_entry *)
3285 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3286 table, string));
57e8b36a 3287 if (ret != NULL)
b7693d02 3288 {
0bdcacaf 3289 ret->dyn_relocs = NULL;
ba93b8ac 3290 ret->tls_type = GOT_UNKNOWN;
0855e32b 3291 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3292 ret->plt.thumb_refcount = 0;
3293 ret->plt.maybe_thumb_refcount = 0;
3294 ret->plt.noncall_refcount = 0;
3295 ret->plt.got_offset = -1;
3296 ret->is_iplt = FALSE;
a4fd1a8e 3297 ret->export_glue = NULL;
906e58ca
NC		 3298
3299 ret->stub_cache = NULL;
b7693d02 3300 }
780a67af
NC		 3301
3302 return (struct bfd_hash_entry *) ret;
3303}
3304
34e77a92
RS		 3305/* Ensure that we have allocated bookkeeping structures for ABFD's local
3306 symbols. */
3307
3308static bfd_boolean
3309elf32_arm_allocate_local_sym_info (bfd *abfd)
3310{
3311 if (elf_local_got_refcounts (abfd) == NULL)
3312 {
3313 bfd_size_type num_syms;
3314 bfd_size_type size;
3315 char *data;
3316
3317 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3318 size = num_syms * (sizeof (bfd_signed_vma)
3319 + sizeof (struct arm_local_iplt_info *)
3320 + sizeof (bfd_vma)
3321 + sizeof (char));
3322 data = bfd_zalloc (abfd, size);
3323 if (data == NULL)
3324 return FALSE;
3325
3326 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3327 data += num_syms * sizeof (bfd_signed_vma);
3328
3329 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3330 data += num_syms * sizeof (struct arm_local_iplt_info *);
3331
3332 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3333 data += num_syms * sizeof (bfd_vma);
3334
3335 elf32_arm_local_got_tls_type (abfd) = data;
3336 }
3337 return TRUE;
3338}
3339
3340/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3341 to input bfd ABFD. Create the information if it doesn't already exist.
3342 Return null if an allocation fails. */
3343
3344static struct arm_local_iplt_info *
3345elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3346{
3347 struct arm_local_iplt_info **ptr;
3348
3349 if (!elf32_arm_allocate_local_sym_info (abfd))
3350 return NULL;
3351
3352 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3353 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3354 if (*ptr == NULL)
3355 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3356 return *ptr;
3357}
3358
3359/* Try to obtain PLT information for the symbol with index R_SYMNDX
3360 in ABFD's symbol table. If the symbol is global, H points to its
3361 hash table entry, otherwise H is null.
3362
3363 Return true if the symbol does have PLT information. When returning
3364 true, point *ROOT_PLT at the target-independent reference count/offset
3365 union and *ARM_PLT at the ARM-specific information. */
3366
3367static bfd_boolean
4ba2ef8f
TP		 3368elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3369 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3370 unsigned long r_symndx, union gotplt_union **root_plt,
3371 struct arm_plt_info **arm_plt)
3372{
3373 struct arm_local_iplt_info *local_iplt;
3374
4ba2ef8f
TP		 3375 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3376 return FALSE;
3377
34e77a92
RS		 3378 if (h != NULL)
3379 {
3380 *root_plt = &h->root.plt;
3381 *arm_plt = &h->plt;
3382 return TRUE;
3383 }
3384
3385 if (elf32_arm_local_iplt (abfd) == NULL)
3386 return FALSE;
3387
3388 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3389 if (local_iplt == NULL)
3390 return FALSE;
3391
3392 *root_plt = &local_iplt->root;
3393 *arm_plt = &local_iplt->arm;
3394 return TRUE;
3395}
3396
3397/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3398 before it. */
3399
3400static bfd_boolean
3401elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3402 struct arm_plt_info *arm_plt)
3403{
3404 struct elf32_arm_link_hash_table *htab;
3405
3406 htab = elf32_arm_hash_table (info);
3407 return (arm_plt->thumb_refcount != 0
3408 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3409}
3410
3411/* Return a pointer to the head of the dynamic reloc list that should
3412 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3413 ABFD's symbol table. Return null if an error occurs. */
3414
3415static struct elf_dyn_relocs **
3416elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3417 Elf_Internal_Sym *isym)
3418{
3419 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3420 {
3421 struct arm_local_iplt_info *local_iplt;
3422
3423 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3424 if (local_iplt == NULL)
3425 return NULL;
3426 return &local_iplt->dyn_relocs;
3427 }
3428 else
3429 {
3430 /* Track dynamic relocs needed for local syms too.
3431 We really need local syms available to do this
3432 easily. Oh well. */
3433 asection *s;
3434 void *vpp;
3435
3436 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3437 if (s == NULL)
3438 abort ();
3439
3440 vpp = &elf_section_data (s)->local_dynrel;
3441 return (struct elf_dyn_relocs **) vpp;
3442 }
3443}
3444
906e58ca
NC		 3445/* Initialize an entry in the stub hash table. */
3446
3447static struct bfd_hash_entry *
3448stub_hash_newfunc (struct bfd_hash_entry *entry,
3449 struct bfd_hash_table *table,
3450 const char *string)
3451{
3452 /* Allocate the structure if it has not already been allocated by a
3453 subclass. */
3454 if (entry == NULL)
3455 {
21d799b5 3456 entry = (struct bfd_hash_entry *)
99059e56 3457 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3458 if (entry == NULL)
3459 return entry;
3460 }
3461
3462 /* Call the allocation method of the superclass. */
3463 entry = bfd_hash_newfunc (entry, table, string);
3464 if (entry != NULL)
3465 {
3466 struct elf32_arm_stub_hash_entry *eh;
3467
3468 /* Initialize the local fields. */
3469 eh = (struct elf32_arm_stub_hash_entry *) entry;
3470 eh->stub_sec = NULL;
0955507f 3471 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3472 eh->source_value = 0;
906e58ca
NC		 3473 eh->target_value = 0;
3474 eh->target_section = NULL;
cedfb179 3475 eh->orig_insn = 0;
906e58ca 3476 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3477 eh->stub_size = 0;
3478 eh->stub_template = NULL;
0955507f 3479 eh->stub_template_size = -1;
906e58ca
NC		 3480 eh->h = NULL;
3481 eh->id_sec = NULL;
d8d2f433 3482 eh->output_name = NULL;
906e58ca
NC		 3483 }
3484
3485 return entry;
3486}
3487
00a97672 3488/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3489 shortcuts to them in our hash table. */
3490
3491static bfd_boolean
57e8b36a 3492create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3493{
3494 struct elf32_arm_link_hash_table *htab;
3495
e5a52504 3496 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3497 if (htab == NULL)
3498 return FALSE;
3499
e5a52504
MM		 3500 /* BPABI objects never have a GOT, or associated sections. */
3501 if (htab->symbian_p)
3502 return TRUE;
3503
5e681ec4
PB		 3504 if (! _bfd_elf_create_got_section (dynobj, info))
3505 return FALSE;
3506
5e681ec4
PB		 3507 return TRUE;
3508}
3509
34e77a92
RS		 3510/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3511
3512static bfd_boolean
3513create_ifunc_sections (struct bfd_link_info *info)
3514{
3515 struct elf32_arm_link_hash_table *htab;
3516 const struct elf_backend_data *bed;
3517 bfd *dynobj;
3518 asection *s;
3519 flagword flags;
b38cadfb 3520
34e77a92
RS		 3521 htab = elf32_arm_hash_table (info);
3522 dynobj = htab->root.dynobj;
3523 bed = get_elf_backend_data (dynobj);
3524 flags = bed->dynamic_sec_flags;
3525
3526 if (htab->root.iplt == NULL)
3527 {
3d4d4302
AM		 3528 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3529 flags | SEC_READONLY | SEC_CODE);
34e77a92 3530 if (s == NULL
a0f49396 3531 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3532 return FALSE;
3533 htab->root.iplt = s;
3534 }
3535
3536 if (htab->root.irelplt == NULL)
3537 {
3d4d4302
AM		 3538 s = bfd_make_section_anyway_with_flags (dynobj,
3539 RELOC_SECTION (htab, ".iplt"),
3540 flags | SEC_READONLY);
34e77a92 3541 if (s == NULL
a0f49396 3542 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3543 return FALSE;
3544 htab->root.irelplt = s;
3545 }
3546
3547 if (htab->root.igotplt == NULL)
3548 {
3d4d4302 3549 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3550 if (s == NULL
3551 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3552 return FALSE;
3553 htab->root.igotplt = s;
3554 }
3555 return TRUE;
3556}
3557
eed94f8f
NC		 3558/* Determine if we're dealing with a Thumb only architecture. */
3559
3560static bfd_boolean
3561using_thumb_only (struct elf32_arm_link_hash_table *globals)
3562{
2fd158eb
TP		 3563 int arch;
3564 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3565 Tag_CPU_arch_profile);
eed94f8f 3566
2fd158eb
TP		 3567 if (profile)
3568 return profile == 'M';
eed94f8f 3569
2fd158eb 3570 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3571
60a019a0
TP		 3572 /* Force return logic to be reviewed for each new architecture. */
3573 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3574 || arch == TAG_CPU_ARCH_V8M_BASE
3575 || arch == TAG_CPU_ARCH_V8M_MAIN);
3576
2fd158eb
TP		 3577 if (arch == TAG_CPU_ARCH_V6_M
3578 || arch == TAG_CPU_ARCH_V6S_M
3579 || arch == TAG_CPU_ARCH_V7E_M
3580 || arch == TAG_CPU_ARCH_V8M_BASE
3581 || arch == TAG_CPU_ARCH_V8M_MAIN)
3582 return TRUE;
eed94f8f 3583
2fd158eb 3584 return FALSE;
eed94f8f
NC		 3585}
3586
3587/* Determine if we're dealing with a Thumb-2 object. */
3588
3589static bfd_boolean
3590using_thumb2 (struct elf32_arm_link_hash_table *globals)
3591{
60a019a0
TP		 3592 int arch;
3593 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3594 Tag_THUMB_ISA_use);
3595
3596 if (thumb_isa)
3597 return thumb_isa == 2;
3598
3599 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3600
3601 /* Force return logic to be reviewed for each new architecture. */
3602 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3603 || arch == TAG_CPU_ARCH_V8M_BASE
3604 || arch == TAG_CPU_ARCH_V8M_MAIN);
3605
3606 return (arch == TAG_CPU_ARCH_V6T2
3607 || arch == TAG_CPU_ARCH_V7
3608 || arch == TAG_CPU_ARCH_V7E_M
3609 || arch == TAG_CPU_ARCH_V8
3610 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3611}
3612
5e866f5a
TP		 3613/* Determine whether Thumb-2 BL instruction is available. */
3614
3615static bfd_boolean
3616using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3617{
3618 int arch =
3619 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3620
3621 /* Force return logic to be reviewed for each new architecture. */
3622 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3623 || arch == TAG_CPU_ARCH_V8M_BASE
3624 || arch == TAG_CPU_ARCH_V8M_MAIN);
3625
3626 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3627 return (arch == TAG_CPU_ARCH_V6T2
3628 || arch >= TAG_CPU_ARCH_V7);
3629}
3630
00a97672
RS		 3631/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3632 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3633 hash table. */
3634
3635static bfd_boolean
57e8b36a 3636elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3637{
3638 struct elf32_arm_link_hash_table *htab;
3639
3640 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3641 if (htab == NULL)
3642 return FALSE;
3643
362d30a1 3644 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3645 return FALSE;
3646
3647 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3648 return FALSE;
3649
3d4d4302 3650 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3651 if (!bfd_link_pic (info))
3d4d4302
AM		 3652 htab->srelbss = bfd_get_linker_section (dynobj,
3653 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3654
3655 if (htab->vxworks_p)
3656 {
3657 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3658 return FALSE;
3659
0e1862bb 3660 if (bfd_link_pic (info))
00a97672
RS		 3661 {
3662 htab->plt_header_size = 0;
3663 htab->plt_entry_size
3664 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3665 }
3666 else
3667 {
3668 htab->plt_header_size
3669 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3670 htab->plt_entry_size
3671 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3672 }
aebf9be7
NC		 3673
3674 if (elf_elfheader (dynobj))
3675 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3676 }
eed94f8f
NC		 3677 else
3678 {
3679 /* PR ld/16017
3680 Test for thumb only architectures. Note - we cannot just call
3681 using_thumb_only() as the attributes in the output bfd have not been
3682 initialised at this point, so instead we use the input bfd. */
3683 bfd * saved_obfd = htab->obfd;
3684
3685 htab->obfd = dynobj;
3686 if (using_thumb_only (htab))
3687 {
3688 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3689 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3690 }
3691 htab->obfd = saved_obfd;
3692 }
5e681ec4 3693
362d30a1
RS		 3694 if (!htab->root.splt
3695 || !htab->root.srelplt
e5a52504 3696 || !htab->sdynbss
0e1862bb 3697 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3698 abort ();
3699
3700 return TRUE;
3701}
3702
906e58ca
NC		 3703/* Copy the extra info we tack onto an elf_link_hash_entry. */
3704
3705static void
3706elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3707 struct elf_link_hash_entry *dir,
3708 struct elf_link_hash_entry *ind)
3709{
3710 struct elf32_arm_link_hash_entry *edir, *eind;
3711
3712 edir = (struct elf32_arm_link_hash_entry *) dir;
3713 eind = (struct elf32_arm_link_hash_entry *) ind;
3714
0bdcacaf 3715 if (eind->dyn_relocs != NULL)
906e58ca 3716 {
0bdcacaf 3717 if (edir->dyn_relocs != NULL)
906e58ca 3718 {
0bdcacaf
RS		 3719 struct elf_dyn_relocs **pp;
3720 struct elf_dyn_relocs *p;
906e58ca
NC		 3721
3722 /* Add reloc counts against the indirect sym to the direct sym
3723 list. Merge any entries against the same section. */
0bdcacaf 3724 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3725 {
0bdcacaf 3726 struct elf_dyn_relocs *q;
906e58ca 3727
0bdcacaf
RS		 3728 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3729 if (q->sec == p->sec)
906e58ca
NC		 3730 {
3731 q->pc_count += p->pc_count;
3732 q->count += p->count;
3733 *pp = p->next;
3734 break;
3735 }
3736 if (q == NULL)
3737 pp = &p->next;
3738 }
0bdcacaf 3739 *pp = edir->dyn_relocs;
906e58ca
NC		 3740 }
3741
0bdcacaf
RS		 3742 edir->dyn_relocs = eind->dyn_relocs;
3743 eind->dyn_relocs = NULL;
906e58ca
NC		 3744 }
3745
3746 if (ind->root.type == bfd_link_hash_indirect)
3747 {
3748 /* Copy over PLT info. */
34e77a92
RS		 3749 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3750 eind->plt.thumb_refcount = 0;
3751 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3752 eind->plt.maybe_thumb_refcount = 0;
3753 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3754 eind->plt.noncall_refcount = 0;
3755
3756 /* We should only allocate a function to .iplt once the final
3757 symbol information is known. */
3758 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3759
3760 if (dir->got.refcount <= 0)
3761 {
3762 edir->tls_type = eind->tls_type;
3763 eind->tls_type = GOT_UNKNOWN;
3764 }
3765 }
3766
3767 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3768}
3769
68faa637
AM		 3770/* Destroy an ARM elf linker hash table. */
3771
3772static void
d495ab0d 3773elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3774{
3775 struct elf32_arm_link_hash_table *ret
d495ab0d 3776 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3777
3778 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3779 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3780}
3781
906e58ca
NC		 3782/* Create an ARM elf linker hash table. */
3783
3784static struct bfd_link_hash_table *
3785elf32_arm_link_hash_table_create (bfd *abfd)
3786{
3787 struct elf32_arm_link_hash_table *ret;
3788 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3789
7bf52ea2 3790 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3791 if (ret == NULL)
3792 return NULL;
3793
3794 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3795 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3796 sizeof (struct elf32_arm_link_hash_entry),
3797 ARM_ELF_DATA))
906e58ca
NC		 3798 {
3799 free (ret);
3800 return NULL;
3801 }
3802
906e58ca 3803 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3804 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3805#ifdef FOUR_WORD_PLT
3806 ret->plt_header_size = 16;
3807 ret->plt_entry_size = 16;
3808#else
3809 ret->plt_header_size = 20;
1db37fe6 3810 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3811#endif
906e58ca 3812 ret->use_rel = 1;
906e58ca 3813 ret->obfd = abfd;
906e58ca
NC		 3814
3815 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3816 sizeof (struct elf32_arm_stub_hash_entry)))
3817 {
d495ab0d 3818 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3819 return NULL;
3820 }
d495ab0d 3821 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3822
3823 return &ret->root.root;
3824}
3825
cd1dac3d
DG		 3826/* Determine what kind of NOPs are available. */
3827
3828static bfd_boolean
3829arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3830{
3831 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3832 Tag_CPU_arch);
cd1dac3d 3833
60a019a0
TP		 3834 /* Force return logic to be reviewed for each new architecture. */
3835 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3836 || arch == TAG_CPU_ARCH_V8M_BASE
3837 || arch == TAG_CPU_ARCH_V8M_MAIN);
3838
3839 return (arch == TAG_CPU_ARCH_V6T2
3840 || arch == TAG_CPU_ARCH_V6K
3841 || arch == TAG_CPU_ARCH_V7
3842 || arch == TAG_CPU_ARCH_V8);
cd1dac3d
DG		 3843}
3844
f4ac8484
DJ		 3845static bfd_boolean
3846arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3847{
3848 switch (stub_type)
3849 {
fea2b4d6 3850 case arm_stub_long_branch_thumb_only:
80c135e5 3851 case arm_stub_long_branch_thumb2_only:
d5a67c02 3852 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3853 case arm_stub_long_branch_v4t_thumb_arm:
3854 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3855 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3856 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3857 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3858 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3859 return TRUE;
3860 case arm_stub_none:
3861 BFD_FAIL ();
3862 return FALSE;
3863 break;
3864 default:
3865 return FALSE;
3866 }
3867}
3868
906e58ca
NC		 3869/* Determine the type of stub needed, if any, for a call. */
3870
3871static enum elf32_arm_stub_type
3872arm_type_of_stub (struct bfd_link_info *info,
3873 asection *input_sec,
3874 const Elf_Internal_Rela *rel,
34e77a92 3875 unsigned char st_type,
35fc36a8 3876 enum arm_st_branch_type *actual_branch_type,
906e58ca 3877 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3878 bfd_vma destination,
3879 asection *sym_sec,
3880 bfd *input_bfd,
3881 const char *name)
906e58ca
NC		 3882{
3883 bfd_vma location;
3884 bfd_signed_vma branch_offset;
3885 unsigned int r_type;
3886 struct elf32_arm_link_hash_table * globals;
5e866f5a 3887 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3888 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3889 int use_plt = 0;
35fc36a8 3890 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3891 union gotplt_union *root_plt;
3892 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3893 int arch;
3894 int thumb2_movw;
906e58ca 3895
35fc36a8 3896 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3897 return stub_type;
3898
906e58ca 3899 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3900 if (globals == NULL)
3901 return stub_type;
906e58ca
NC		 3902
3903 thumb_only = using_thumb_only (globals);
906e58ca 3904 thumb2 = using_thumb2 (globals);
5e866f5a 3905 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3906
d5a67c02
AV		 3907 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3908
3909 /* True for architectures that implement the thumb2 movw instruction. */
3910 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3911
906e58ca
NC		 3912 /* Determine where the call point is. */
3913 location = (input_sec->output_offset
3914 + input_sec->output_section->vma
3915 + rel->r_offset);
3916
906e58ca
NC		 3917 r_type = ELF32_R_TYPE (rel->r_info);
3918
39f21624
NC		 3919 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3920 are considering a function call relocation. */
c5423981
TG		 3921 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3922 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3923 && branch_type == ST_BRANCH_TO_ARM)
3924 branch_type = ST_BRANCH_TO_THUMB;
3925
34e77a92
RS		 3926 /* For TLS call relocs, it is the caller's responsibility to provide
3927 the address of the appropriate trampoline. */
3928 if (r_type != R_ARM_TLS_CALL
3929 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3930 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3931 ELF32_R_SYM (rel->r_info), &root_plt,
3932 &arm_plt)
34e77a92 3933 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3934 {
34e77a92 3935 asection *splt;
fe33d2fa 3936
34e77a92
RS		 3937 if (hash == NULL || hash->is_iplt)
3938 splt = globals->root.iplt;
3939 else
3940 splt = globals->root.splt;
3941 if (splt != NULL)
b38cadfb 3942 {
34e77a92
RS		 3943 use_plt = 1;
3944
3945 /* Note when dealing with PLT entries: the main PLT stub is in
3946 ARM mode, so if the branch is in Thumb mode, another
3947 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3948 PLT stub. If a long branch stub is needed, we'll add a
3949 Thumb->Arm one and branch directly to the ARM PLT entry.
3950 Here, we have to check if a pre-PLT Thumb->ARM stub
3951 is needed and if it will be close enough. */
34e77a92
RS		 3952
3953 destination = (splt->output_section->vma
3954 + splt->output_offset
3955 + root_plt->offset);
3956 st_type = STT_FUNC;
2df2751d
CL		 3957
3958 /* Thumb branch/call to PLT: it can become a branch to ARM
3959 or to Thumb. We must perform the same checks and
3960 corrections as in elf32_arm_final_link_relocate. */
3961 if ((r_type == R_ARM_THM_CALL)
3962 || (r_type == R_ARM_THM_JUMP24))
3963 {
3964 if (globals->use_blx
3965 && r_type == R_ARM_THM_CALL
3966 && !thumb_only)
3967 {
3968 /* If the Thumb BLX instruction is available, convert
3969 the BL to a BLX instruction to call the ARM-mode
3970 PLT entry. */
3971 branch_type = ST_BRANCH_TO_ARM;
3972 }
3973 else
3974 {
3975 if (!thumb_only)
3976 /* Target the Thumb stub before the ARM PLT entry. */
3977 destination -= PLT_THUMB_STUB_SIZE;
3978 branch_type = ST_BRANCH_TO_THUMB;
3979 }
3980 }
3981 else
3982 {
3983 branch_type = ST_BRANCH_TO_ARM;
3984 }
34e77a92 3985 }
5fa9e92f 3986 }
34e77a92
RS		 3987 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3988 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3989
fe33d2fa
CL		 3990 branch_offset = (bfd_signed_vma)(destination - location);
3991
0855e32b 3992 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3993 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3994 {
5fa9e92f
CL		 3995 /* Handle cases where:
3996 - this call goes too far (different Thumb/Thumb2 max
99059e56 3997 distance)
155d87d7 3998 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3999 Thumb->Arm branch (not bl). A stub is needed in this case,
4000 but only if this call is not through a PLT entry. Indeed,
695344c0 4001 PLT stubs handle mode switching already. */
5e866f5a 4002 if ((!thumb2_bl
906e58ca
NC		 4003 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4004 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4005 || (thumb2_bl
906e58ca
NC		 4006 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4007 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4008 || (thumb2
4009 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4010 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4011 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4012 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4013 && (((r_type == R_ARM_THM_CALL
4014 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 4015 || (r_type == R_ARM_THM_JUMP24)
4016 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4017 && !use_plt))
906e58ca 4018 {
2df2751d
CL		 4019 /* If we need to insert a Thumb-Thumb long branch stub to a
4020 PLT, use one that branches directly to the ARM PLT
4021 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4022 stub, undo this now. */
695344c0
NC		 4023 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4024 {
4025 branch_type = ST_BRANCH_TO_ARM;
4026 branch_offset += PLT_THUMB_STUB_SIZE;
4027 }
2df2751d 4028
35fc36a8 4029 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4030 {
4031 /* Thumb to thumb. */
4032 if (!thumb_only)
4033 {
d5a67c02 4034 if (input_sec->flags & SEC_ELF_PURECODE)
695344c0
NC		 4035 _bfd_error_handler (_("\
4036%B(%A): warning: long branch veneers used in section with SHF_ARM_PURECODE section \
4037attribute is only supported for M-profile targets that implement the movw instruction."),
4038 input_sec);
d5a67c02 4039
0e1862bb 4040 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4041 /* PIC stubs. */
155d87d7 4042 ? ((globals->use_blx
9553db3c 4043 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4044 /* V5T and above. Stub starts with ARM code, so
4045 we must be able to switch mode before
4046 reaching it, which is only possible for 'bl'
4047 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4048 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4049 /* On V4T, use Thumb code only. */
d3626fb0 4050 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4051
4052 /* non-PIC stubs. */
155d87d7 4053 : ((globals->use_blx
9553db3c 4054 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4055 /* V5T and above. */
4056 ? arm_stub_long_branch_any_any
4057 /* V4T. */
d3626fb0 4058 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4059 }
4060 else
4061 {
d5a67c02
AV		 4062 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4063 stub_type = arm_stub_long_branch_thumb2_only_pure;
4064 else
4065 {
4066 if (input_sec->flags & SEC_ELF_PURECODE)
695344c0
NC		 4067 _bfd_error_handler (_("\
4068%B(%A): warning: long branch veneers used in section with SHF_ARM_PURECODE section \
4069attribute is only supported for M-profile targets that implement the movw instruction."),
4070 input_sec);
d5a67c02
AV		 4071
4072 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4073 /* PIC stub. */
4074 ? arm_stub_long_branch_thumb_only_pic
4075 /* non-PIC stub. */
4076 : (thumb2 ? arm_stub_long_branch_thumb2_only
4077 : arm_stub_long_branch_thumb_only);
4078 }
906e58ca
NC		 4079 }
4080 }
4081 else
4082 {
d5a67c02 4083 if (input_sec->flags & SEC_ELF_PURECODE)
4eca0228
AM		 4084 _bfd_error_handler (_("%B(%s): warning: long branch "
4085 " veneers used in section with "
4086 "SHF_ARM_PURECODE section "
4087 "attribute is only supported"
4088 " for M-profile targets that "
4089 "implement the movw "
4090 "instruction."));
d5a67c02 4091
906e58ca 4092 /* Thumb to arm. */
c820be07
NC		 4093 if (sym_sec != NULL
4094 && sym_sec->owner != NULL
4095 && !INTERWORK_FLAG (sym_sec->owner))
4096 {
4eca0228 4097 _bfd_error_handler
c820be07
NC		 4098 (_("%B(%s): warning: interworking not enabled.\n"
4099 " first occurrence: %B: Thumb call to ARM"),
4100 sym_sec->owner, input_bfd, name);
4101 }
4102
0855e32b 4103 stub_type =
0e1862bb 4104 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4105 /* PIC stubs. */
0855e32b 4106 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4107 /* TLS PIC stubs. */
0855e32b
NS		 4108 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4109 : arm_stub_long_branch_v4t_thumb_tls_pic)
4110 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4111 /* V5T PIC and above. */
4112 ? arm_stub_long_branch_any_arm_pic
4113 /* V4T PIC stub. */
4114 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4115
4116 /* non-PIC stubs. */
0855e32b 4117 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4118 /* V5T and above. */
4119 ? arm_stub_long_branch_any_any
4120 /* V4T. */
4121 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4122
4123 /* Handle v4t short branches. */
fea2b4d6 4124 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4125 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4126 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4127 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4128 }
4129 }
4130 }
fe33d2fa
CL		 4131 else if (r_type == R_ARM_CALL
4132 || r_type == R_ARM_JUMP24
0855e32b
NS		 4133 || r_type == R_ARM_PLT32
4134 || r_type == R_ARM_TLS_CALL)
906e58ca 4135 {
d5a67c02 4136 if (input_sec->flags & SEC_ELF_PURECODE)
4eca0228
AM		 4137 _bfd_error_handler (_("%B(%s): warning: long branch "
4138 " veneers used in section with "
4139 "SHF_ARM_PURECODE section "
4140 "attribute is only supported"
4141 " for M-profile targets that "
4142 "implement the movw "
4143 "instruction."));
35fc36a8 4144 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4145 {
4146 /* Arm to thumb. */
c820be07
NC		 4147
4148 if (sym_sec != NULL
4149 && sym_sec->owner != NULL
4150 && !INTERWORK_FLAG (sym_sec->owner))
4151 {
4eca0228 4152 _bfd_error_handler
c820be07 4153 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4154 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 4155 sym_sec->owner, input_bfd, name);
4156 }
4157
4158 /* We have an extra 2-bytes reach because of
4159 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4160 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4161 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4162 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4163 || (r_type == R_ARM_JUMP24)
4164 || (r_type == R_ARM_PLT32))
906e58ca 4165 {
0e1862bb 4166 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4167 /* PIC stubs. */
ebe24dd4
CL		 4168 ? ((globals->use_blx)
4169 /* V5T and above. */
4170 ? arm_stub_long_branch_any_thumb_pic
4171 /* V4T stub. */
4172 : arm_stub_long_branch_v4t_arm_thumb_pic)
4173
c2b4a39d
CL		 4174 /* non-PIC stubs. */
4175 : ((globals->use_blx)
4176 /* V5T and above. */
4177 ? arm_stub_long_branch_any_any
4178 /* V4T. */
4179 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4180 }
4181 }
4182 else
4183 {
4184 /* Arm to arm. */
4185 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4186 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4187 {
0855e32b 4188 stub_type =
0e1862bb 4189 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4190 /* PIC stubs. */
0855e32b 4191 ? (r_type == R_ARM_TLS_CALL
6a631e86 4192 /* TLS PIC Stub. */
0855e32b 4193 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4194 : (globals->nacl_p
4195 ? arm_stub_long_branch_arm_nacl_pic
4196 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4197 /* non-PIC stubs. */
7a89b94e
NC		 4198 : (globals->nacl_p
4199 ? arm_stub_long_branch_arm_nacl
4200 : arm_stub_long_branch_any_any);
906e58ca
NC		 4201 }
4202 }
4203 }
4204
fe33d2fa
CL		 4205 /* If a stub is needed, record the actual destination type. */
4206 if (stub_type != arm_stub_none)
35fc36a8 4207 *actual_branch_type = branch_type;
fe33d2fa 4208
906e58ca
NC		 4209 return stub_type;
4210}
4211
4212/* Build a name for an entry in the stub hash table. */
4213
4214static char *
4215elf32_arm_stub_name (const asection *input_section,
4216 const asection *sym_sec,
4217 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4218 const Elf_Internal_Rela *rel,
4219 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4220{
4221 char *stub_name;
4222 bfd_size_type len;
4223
4224 if (hash)
4225 {
fe33d2fa 4226 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4227 stub_name = (char *) bfd_malloc (len);
906e58ca 4228 if (stub_name != NULL)
fe33d2fa 4229 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4230 input_section->id & 0xffffffff,
4231 hash->root.root.root.string,
fe33d2fa
CL		 4232 (int) rel->r_addend & 0xffffffff,
4233 (int) stub_type);
906e58ca
NC		 4234 }
4235 else
4236 {
fe33d2fa 4237 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4238 stub_name = (char *) bfd_malloc (len);
906e58ca 4239 if (stub_name != NULL)
fe33d2fa 4240 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4241 input_section->id & 0xffffffff,
4242 sym_sec->id & 0xffffffff,
0855e32b
NS		 4243 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4244 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4245 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4246 (int) rel->r_addend & 0xffffffff,
4247 (int) stub_type);
906e58ca
NC		 4248 }
4249
4250 return stub_name;
4251}
4252
4253/* Look up an entry in the stub hash. Stub entries are cached because
4254 creating the stub name takes a bit of time. */
4255
4256static struct elf32_arm_stub_hash_entry *
4257elf32_arm_get_stub_entry (const asection *input_section,
4258 const asection *sym_sec,
4259 struct elf_link_hash_entry *hash,
4260 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4261 struct elf32_arm_link_hash_table *htab,
4262 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4263{
4264 struct elf32_arm_stub_hash_entry *stub_entry;
4265 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4266 const asection *id_sec;
4267
4268 if ((input_section->flags & SEC_CODE) == 0)
4269 return NULL;
4270
4271 /* If this input section is part of a group of sections sharing one
4272 stub section, then use the id of the first section in the group.
4273 Stub names need to include a section id, as there may well be
4274 more than one stub used to reach say, printf, and we need to
4275 distinguish between them. */
c2abbbeb 4276 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4277 id_sec = htab->stub_group[input_section->id].link_sec;
4278
4279 if (h != NULL && h->stub_cache != NULL
4280 && h->stub_cache->h == h
fe33d2fa
CL		 4281 && h->stub_cache->id_sec == id_sec
4282 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4283 {
4284 stub_entry = h->stub_cache;
4285 }
4286 else
4287 {
4288 char *stub_name;
4289
fe33d2fa 4290 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4291 if (stub_name == NULL)
4292 return NULL;
4293
4294 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4295 stub_name, FALSE, FALSE);
4296 if (h != NULL)
4297 h->stub_cache = stub_entry;
4298
4299 free (stub_name);
4300 }
4301
4302 return stub_entry;
4303}
4304
daa4adae
TP		 4305/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4306 section. */
4307
4308static bfd_boolean
4309arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4310{
4311 if (stub_type >= max_stub_type)
4312 abort (); /* Should be unreachable. */
4313
4ba2ef8f
TP		 4314 switch (stub_type)
4315 {
4316 case arm_stub_cmse_branch_thumb_only:
4317 return TRUE;
4318
4319 default:
4320 return FALSE;
4321 }
4322
4323 abort (); /* Should be unreachable. */
daa4adae
TP		 4324}
4325
4326/* Required alignment (as a power of 2) for the dedicated section holding
4327 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4328 with input sections. */
4329
4330static int
4331arm_dedicated_stub_output_section_required_alignment
4332 (enum elf32_arm_stub_type stub_type)
4333{
4334 if (stub_type >= max_stub_type)
4335 abort (); /* Should be unreachable. */
4336
4ba2ef8f
TP		 4337 switch (stub_type)
4338 {
4339 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4340 boundary. */
4341 case arm_stub_cmse_branch_thumb_only:
4342 return 5;
4343
4344 default:
4345 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4346 return 0;
4347 }
4348
4349 abort (); /* Should be unreachable. */
daa4adae
TP		 4350}
4351
4352/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4353 NULL if veneers of this type are interspersed with input sections. */
4354
4355static const char *
4356arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4357{
4358 if (stub_type >= max_stub_type)
4359 abort (); /* Should be unreachable. */
4360
4ba2ef8f
TP		 4361 switch (stub_type)
4362 {
4363 case arm_stub_cmse_branch_thumb_only:
4364 return ".gnu.sgstubs";
4365
4366 default:
4367 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4368 return NULL;
4369 }
4370
4371 abort (); /* Should be unreachable. */
daa4adae
TP		 4372}
4373
4374/* If veneers of type STUB_TYPE should go in a dedicated output section,
4375 returns the address of the hash table field in HTAB holding a pointer to the
4376 corresponding input section. Otherwise, returns NULL. */
4377
4378static asection **
4ba2ef8f
TP		 4379arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4380 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4381{
4382 if (stub_type >= max_stub_type)
4383 abort (); /* Should be unreachable. */
4384
4ba2ef8f
TP		 4385 switch (stub_type)
4386 {
4387 case arm_stub_cmse_branch_thumb_only:
4388 return &htab->cmse_stub_sec;
4389
4390 default:
4391 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4392 return NULL;
4393 }
4394
4395 abort (); /* Should be unreachable. */
daa4adae
TP		 4396}
4397
4398/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4399 is the section that branch into veneer and can be NULL if stub should go in
4400 a dedicated output section. Returns a pointer to the stub section, and the
4401 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4402 LINK_SEC_P may be NULL. */
906e58ca 4403
48229727
JB		 4404static asection *
4405elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4406 struct elf32_arm_link_hash_table *htab,
4407 enum elf32_arm_stub_type stub_type)
906e58ca 4408{
daa4adae
TP		 4409 asection *link_sec, *out_sec, **stub_sec_p;
4410 const char *stub_sec_prefix;
4411 bfd_boolean dedicated_output_section =
4412 arm_dedicated_stub_output_section_required (stub_type);
4413 int align;
906e58ca 4414
daa4adae 4415 if (dedicated_output_section)
906e58ca 4416 {
daa4adae
TP		 4417 bfd *output_bfd = htab->obfd;
4418 const char *out_sec_name =
4419 arm_dedicated_stub_output_section_name (stub_type);
4420 link_sec = NULL;
4421 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4422 stub_sec_prefix = out_sec_name;
4423 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4424 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4425 if (out_sec == NULL)
906e58ca 4426 {
4eca0228
AM		 4427 _bfd_error_handler (_("No address assigned to the veneers output "
4428 "section %s"), out_sec_name);
daa4adae 4429 return NULL;
906e58ca 4430 }
daa4adae
TP		 4431 }
4432 else
4433 {
c2abbbeb 4434 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4435 link_sec = htab->stub_group[section->id].link_sec;
4436 BFD_ASSERT (link_sec != NULL);
4437 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4438 if (*stub_sec_p == NULL)
4439 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4440 stub_sec_prefix = link_sec->name;
4441 out_sec = link_sec->output_section;
4442 align = htab->nacl_p ? 4 : 3;
906e58ca 4443 }
b38cadfb 4444
daa4adae
TP		 4445 if (*stub_sec_p == NULL)
4446 {
4447 size_t namelen;
4448 bfd_size_type len;
4449 char *s_name;
4450
4451 namelen = strlen (stub_sec_prefix);
4452 len = namelen + sizeof (STUB_SUFFIX);
4453 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4454 if (s_name == NULL)
4455 return NULL;
4456
4457 memcpy (s_name, stub_sec_prefix, namelen);
4458 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4459 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4460 align);
4461 if (*stub_sec_p == NULL)
4462 return NULL;
4463
4464 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4465 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4466 | SEC_KEEP;
4467 }
4468
4469 if (!dedicated_output_section)
4470 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4471
48229727
JB		 4472 if (link_sec_p)
4473 *link_sec_p = link_sec;
b38cadfb 4474
daa4adae 4475 return *stub_sec_p;
48229727
JB		 4476}
4477
4478/* Add a new stub entry to the stub hash. Not all fields of the new
4479 stub entry are initialised. */
4480
4481static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4482elf32_arm_add_stub (const char *stub_name, asection *section,
4483 struct elf32_arm_link_hash_table *htab,
4484 enum elf32_arm_stub_type stub_type)
48229727
JB		 4485{
4486 asection *link_sec;
4487 asection *stub_sec;
4488 struct elf32_arm_stub_hash_entry *stub_entry;
4489
daa4adae
TP		 4490 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4491 stub_type);
48229727
JB		 4492 if (stub_sec == NULL)
4493 return NULL;
906e58ca
NC		 4494
4495 /* Enter this entry into the linker stub hash table. */
4496 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4497 TRUE, FALSE);
4498 if (stub_entry == NULL)
4499 {
6bde4c52
TP		 4500 if (section == NULL)
4501 section = stub_sec;
4eca0228
AM		 4502 _bfd_error_handler (_("%s: cannot create stub entry %s"),
4503 section->owner, stub_name);
906e58ca
NC		 4504 return NULL;
4505 }
4506
4507 stub_entry->stub_sec = stub_sec;
0955507f 4508 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4509 stub_entry->id_sec = link_sec;
4510
906e58ca
NC		 4511 return stub_entry;
4512}
4513
4514/* Store an Arm insn into an output section not processed by
4515 elf32_arm_write_section. */
4516
4517static void
8029a119
NC		 4518put_arm_insn (struct elf32_arm_link_hash_table * htab,
4519 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4520{
4521 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4522 bfd_putl32 (val, ptr);
4523 else
4524 bfd_putb32 (val, ptr);
4525}
4526
4527/* Store a 16-bit Thumb insn into an output section not processed by
4528 elf32_arm_write_section. */
4529
4530static void
8029a119
NC		 4531put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4532 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4533{
4534 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4535 bfd_putl16 (val, ptr);
4536 else
4537 bfd_putb16 (val, ptr);
4538}
4539
a504d23a
LA		 4540/* Store a Thumb2 insn into an output section not processed by
4541 elf32_arm_write_section. */
4542
4543static void
4544put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4545 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4546{
4547 /* T2 instructions are 16-bit streamed. */
4548 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4549 {
4550 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4551 bfd_putl16 ((val & 0xffff), ptr + 2);
4552 }
4553 else
4554 {
4555 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4556 bfd_putb16 ((val & 0xffff), ptr + 2);
4557 }
4558}
4559
0855e32b
NS		 4560/* If it's possible to change R_TYPE to a more efficient access
4561 model, return the new reloc type. */
4562
4563static unsigned
b38cadfb 4564elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4565 struct elf_link_hash_entry *h)
4566{
4567 int is_local = (h == NULL);
4568
0e1862bb
L		 4569 if (bfd_link_pic (info)
4570 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4571 return r_type;
4572
b38cadfb 4573 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4574 switch (r_type)
4575 {
4576 case R_ARM_TLS_GOTDESC:
4577 case R_ARM_TLS_CALL:
4578 case R_ARM_THM_TLS_CALL:
4579 case R_ARM_TLS_DESCSEQ:
4580 case R_ARM_THM_TLS_DESCSEQ:
4581 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4582 }
4583
4584 return r_type;
4585}
4586
48229727
JB		 4587static bfd_reloc_status_type elf32_arm_final_link_relocate
4588 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4589 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4590 const char *, unsigned char, enum arm_st_branch_type,
4591 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4592
4563a860
JB		 4593static unsigned int
4594arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4595{
4596 switch (stub_type)
4597 {
4598 case arm_stub_a8_veneer_b_cond:
4599 case arm_stub_a8_veneer_b:
4600 case arm_stub_a8_veneer_bl:
4601 return 2;
4602
4603 case arm_stub_long_branch_any_any:
4604 case arm_stub_long_branch_v4t_arm_thumb:
4605 case arm_stub_long_branch_thumb_only:
80c135e5 4606 case arm_stub_long_branch_thumb2_only:
d5a67c02 4607 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4608 case arm_stub_long_branch_v4t_thumb_thumb:
4609 case arm_stub_long_branch_v4t_thumb_arm:
4610 case arm_stub_short_branch_v4t_thumb_arm:
4611 case arm_stub_long_branch_any_arm_pic:
4612 case arm_stub_long_branch_any_thumb_pic:
4613 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4614 case arm_stub_long_branch_v4t_arm_thumb_pic:
4615 case arm_stub_long_branch_v4t_thumb_arm_pic:
4616 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4617 case arm_stub_long_branch_any_tls_pic:
4618 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4619 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4620 case arm_stub_a8_veneer_blx:
4621 return 4;
b38cadfb 4622
7a89b94e
NC		 4623 case arm_stub_long_branch_arm_nacl:
4624 case arm_stub_long_branch_arm_nacl_pic:
4625 return 16;
4626
4563a860
JB		 4627 default:
4628 abort (); /* Should be unreachable. */
4629 }
4630}
4631
4f4faa4d
TP		 4632/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4633 veneering (TRUE) or have their own symbol (FALSE). */
4634
4635static bfd_boolean
4636arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4637{
4638 if (stub_type >= max_stub_type)
4639 abort (); /* Should be unreachable. */
4640
4ba2ef8f
TP		 4641 switch (stub_type)
4642 {
4643 case arm_stub_cmse_branch_thumb_only:
4644 return TRUE;
4645
4646 default:
4647 return FALSE;
4648 }
4649
4650 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4651}
4652
d7c5bd02
TP		 4653/* Returns the padding needed for the dedicated section used stubs of type
4654 STUB_TYPE. */
4655
4656static int
4657arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4658{
4659 if (stub_type >= max_stub_type)
4660 abort (); /* Should be unreachable. */
4661
4ba2ef8f
TP		 4662 switch (stub_type)
4663 {
4664 case arm_stub_cmse_branch_thumb_only:
4665 return 32;
4666
4667 default:
4668 return 0;
4669 }
4670
4671 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4672}
4673
0955507f
TP		 4674/* If veneers of type STUB_TYPE should go in a dedicated output section,
4675 returns the address of the hash table field in HTAB holding the offset at
4676 which new veneers should be layed out in the stub section. */
4677
4678static bfd_vma*
4679arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4680 enum elf32_arm_stub_type stub_type)
4681{
4682 switch (stub_type)
4683 {
4684 case arm_stub_cmse_branch_thumb_only:
4685 return &htab->new_cmse_stub_offset;
4686
4687 default:
4688 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4689 return NULL;
4690 }
4691}
4692
906e58ca
NC		 4693static bfd_boolean
4694arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4695 void * in_arg)
4696{
7a89b94e 4697#define MAXRELOCS 3
0955507f 4698 bfd_boolean removed_sg_veneer;
906e58ca 4699 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4700 struct elf32_arm_link_hash_table *globals;
906e58ca 4701 struct bfd_link_info *info;
906e58ca
NC		 4702 asection *stub_sec;
4703 bfd *stub_bfd;
906e58ca
NC		 4704 bfd_byte *loc;
4705 bfd_vma sym_value;
4706 int template_size;
4707 int size;
d3ce72d0 4708 const insn_sequence *template_sequence;
906e58ca 4709 int i;
48229727
JB		 4710 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4711 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4712 int nrelocs = 0;
0955507f 4713 int just_allocated = 0;
906e58ca
NC		 4714
4715 /* Massage our args to the form they really have. */
4716 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4717 info = (struct bfd_link_info *) in_arg;
4718
4719 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4720 if (globals == NULL)
4721 return FALSE;
906e58ca 4722
906e58ca
NC		 4723 stub_sec = stub_entry->stub_sec;
4724
4dfe6ac6 4725 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4726 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4727 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4728 return TRUE;
fe33d2fa 4729
0955507f
TP		 4730 /* Assign a slot at the end of section if none assigned yet. */
4731 if (stub_entry->stub_offset == (bfd_vma) -1)
4732 {
4733 stub_entry->stub_offset = stub_sec->size;
4734 just_allocated = 1;
4735 }
906e58ca
NC		 4736 loc = stub_sec->contents + stub_entry->stub_offset;
4737
4738 stub_bfd = stub_sec->owner;
4739
906e58ca
NC		 4740 /* This is the address of the stub destination. */
4741 sym_value = (stub_entry->target_value
4742 + stub_entry->target_section->output_offset
4743 + stub_entry->target_section->output_section->vma);
4744
d3ce72d0 4745 template_sequence = stub_entry->stub_template;
461a49ca 4746 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4747
4748 size = 0;
461a49ca 4749 for (i = 0; i < template_size; i++)
906e58ca 4750 {
d3ce72d0 4751 switch (template_sequence[i].type)
461a49ca
DJ		 4752 {
4753 case THUMB16_TYPE:
48229727 4754 {
d3ce72d0
NC		 4755 bfd_vma data = (bfd_vma) template_sequence[i].data;
4756 if (template_sequence[i].reloc_addend != 0)
48229727 4757 {
99059e56
RM		 4758 /* We've borrowed the reloc_addend field to mean we should
4759 insert a condition code into this (Thumb-1 branch)
4760 instruction. See THUMB16_BCOND_INSN. */
4761 BFD_ASSERT ((data & 0xff00) == 0xd000);
4762 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4763 }
fe33d2fa 4764 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4765 size += 2;
4766 }
461a49ca 4767 break;
906e58ca 4768
48229727 4769 case THUMB32_TYPE:
fe33d2fa
CL		 4770 bfd_put_16 (stub_bfd,
4771 (template_sequence[i].data >> 16) & 0xffff,
4772 loc + size);
4773 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4774 loc + size + 2);
99059e56
RM		 4775 if (template_sequence[i].r_type != R_ARM_NONE)
4776 {
4777 stub_reloc_idx[nrelocs] = i;
4778 stub_reloc_offset[nrelocs++] = size;
4779 }
4780 size += 4;
4781 break;
48229727 4782
461a49ca 4783 case ARM_TYPE:
fe33d2fa
CL		 4784 bfd_put_32 (stub_bfd, template_sequence[i].data,
4785 loc + size);
461a49ca
DJ		 4786 /* Handle cases where the target is encoded within the
4787 instruction. */
d3ce72d0 4788 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4789 {
48229727
JB		 4790 stub_reloc_idx[nrelocs] = i;
4791 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4792 }
4793 size += 4;
4794 break;
4795
4796 case DATA_TYPE:
d3ce72d0 4797 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4798 stub_reloc_idx[nrelocs] = i;
4799 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4800 size += 4;
4801 break;
4802
4803 default:
4804 BFD_FAIL ();
4805 return FALSE;
4806 }
906e58ca 4807 }
461a49ca 4808
0955507f
TP		 4809 if (just_allocated)
4810 stub_sec->size += size;
906e58ca 4811
461a49ca
DJ		 4812 /* Stub size has already been computed in arm_size_one_stub. Check
4813 consistency. */
4814 BFD_ASSERT (size == stub_entry->stub_size);
4815
906e58ca 4816 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4817 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4818 sym_value |= 1;
4819
0955507f
TP		 4820 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4821 to relocate in each stub. */
4822 removed_sg_veneer =
4823 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4824 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4825
48229727 4826 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4827 {
4828 Elf_Internal_Rela rel;
4829 bfd_boolean unresolved_reloc;
4830 char *error_message;
4831 bfd_vma points_to =
4832 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4833
4834 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4835 rel.r_info = ELF32_R_INFO (0,
4836 template_sequence[stub_reloc_idx[i]].r_type);
4837 rel.r_addend = 0;
4838
4839 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4840 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4841 template should refer back to the instruction after the original
4842 branch. We use target_section as Cortex-A8 erratum workaround stubs
4843 are only generated when both source and target are in the same
4844 section. */
4845 points_to = stub_entry->target_section->output_section->vma
4846 + stub_entry->target_section->output_offset
4847 + stub_entry->source_value;
4848
4849 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4850 (template_sequence[stub_reloc_idx[i]].r_type),
4851 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4852 points_to, info, stub_entry->target_section, "", STT_FUNC,
4853 stub_entry->branch_type,
4854 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4855 &error_message);
4856 }
906e58ca
NC		 4857
4858 return TRUE;
48229727 4859#undef MAXRELOCS
906e58ca
NC		 4860}
4861
48229727
JB		 4862/* Calculate the template, template size and instruction size for a stub.
4863 Return value is the instruction size. */
906e58ca 4864
48229727
JB		 4865static unsigned int
4866find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4867 const insn_sequence **stub_template,
4868 int *stub_template_size)
906e58ca 4869{
d3ce72d0 4870 const insn_sequence *template_sequence = NULL;
48229727
JB		 4871 int template_size = 0, i;
4872 unsigned int size;
906e58ca 4873
d3ce72d0 4874 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4875 if (stub_template)
4876 *stub_template = template_sequence;
4877
48229727 4878 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4879 if (stub_template_size)
4880 *stub_template_size = template_size;
906e58ca
NC		 4881
4882 size = 0;
461a49ca
DJ		 4883 for (i = 0; i < template_size; i++)
4884 {
d3ce72d0 4885 switch (template_sequence[i].type)
461a49ca
DJ		 4886 {
4887 case THUMB16_TYPE:
4888 size += 2;
4889 break;
4890
4891 case ARM_TYPE:
48229727 4892 case THUMB32_TYPE:
461a49ca
DJ		 4893 case DATA_TYPE:
4894 size += 4;
4895 break;
4896
4897 default:
4898 BFD_FAIL ();
2a229407 4899 return 0;
461a49ca
DJ		 4900 }
4901 }
4902
48229727
JB		 4903 return size;
4904}
4905
4906/* As above, but don't actually build the stub. Just bump offset so
4907 we know stub section sizes. */
4908
4909static bfd_boolean
4910arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4911 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4912{
4913 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4914 const insn_sequence *template_sequence;
48229727
JB		 4915 int template_size, size;
4916
4917 /* Massage our args to the form they really have. */
4918 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4919
4920 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4921 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4922
d3ce72d0 4923 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4924 &template_size);
4925
0955507f
TP		 4926 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4927 if (stub_entry->stub_template_size)
4928 {
4929 stub_entry->stub_size = size;
4930 stub_entry->stub_template = template_sequence;
4931 stub_entry->stub_template_size = template_size;
4932 }
4933
4934 /* Already accounted for. */
4935 if (stub_entry->stub_offset != (bfd_vma) -1)
4936 return TRUE;
461a49ca 4937
906e58ca
NC		 4938 size = (size + 7) & ~7;
4939 stub_entry->stub_sec->size += size;
461a49ca 4940
906e58ca
NC		 4941 return TRUE;
4942}
4943
4944/* External entry points for sizing and building linker stubs. */
4945
4946/* Set up various things so that we can make a list of input sections
4947 for each output section included in the link. Returns -1 on error,
4948 0 when no stubs will be needed, and 1 on success. */
4949
4950int
4951elf32_arm_setup_section_lists (bfd *output_bfd,
4952 struct bfd_link_info *info)
4953{
4954 bfd *input_bfd;
4955 unsigned int bfd_count;
7292b3ac 4956 unsigned int top_id, top_index;
906e58ca
NC		 4957 asection *section;
4958 asection **input_list, **list;
4959 bfd_size_type amt;
4960 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4961
4dfe6ac6
NC		 4962 if (htab == NULL)
4963 return 0;
906e58ca
NC		 4964 if (! is_elf_hash_table (htab))
4965 return 0;
4966
4967 /* Count the number of input BFDs and find the top input section id. */
4968 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4969 input_bfd != NULL;
c72f2fb2 4970 input_bfd = input_bfd->link.next)
906e58ca
NC		 4971 {
4972 bfd_count += 1;
4973 for (section = input_bfd->sections;
4974 section != NULL;
4975 section = section->next)
4976 {
4977 if (top_id < section->id)
4978 top_id = section->id;
4979 }
4980 }
4981 htab->bfd_count = bfd_count;
4982
4983 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4984 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4985 if (htab->stub_group == NULL)
4986 return -1;
fe33d2fa 4987 htab->top_id = top_id;
906e58ca
NC		 4988
4989 /* We can't use output_bfd->section_count here to find the top output
4990 section index as some sections may have been removed, and
4991 _bfd_strip_section_from_output doesn't renumber the indices. */
4992 for (section = output_bfd->sections, top_index = 0;
4993 section != NULL;
4994 section = section->next)
4995 {
4996 if (top_index < section->index)
4997 top_index = section->index;
4998 }
4999
5000 htab->top_index = top_index;
5001 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5002 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5003 htab->input_list = input_list;
5004 if (input_list == NULL)
5005 return -1;
5006
5007 /* For sections we aren't interested in, mark their entries with a
5008 value we can check later. */
5009 list = input_list + top_index;
5010 do
5011 *list = bfd_abs_section_ptr;
5012 while (list-- != input_list);
5013
5014 for (section = output_bfd->sections;
5015 section != NULL;
5016 section = section->next)
5017 {
5018 if ((section->flags & SEC_CODE) != 0)
5019 input_list[section->index] = NULL;
5020 }
5021
5022 return 1;
5023}
5024
5025/* The linker repeatedly calls this function for each input section,
5026 in the order that input sections are linked into output sections.
5027 Build lists of input sections to determine groupings between which
5028 we may insert linker stubs. */
5029
5030void
5031elf32_arm_next_input_section (struct bfd_link_info *info,
5032 asection *isec)
5033{
5034 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5035
4dfe6ac6
NC		 5036 if (htab == NULL)
5037 return;
5038
906e58ca
NC		 5039 if (isec->output_section->index <= htab->top_index)
5040 {
5041 asection **list = htab->input_list + isec->output_section->index;
5042
a7470592 5043 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5044 {
5045 /* Steal the link_sec pointer for our list. */
5046#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5047 /* This happens to make the list in reverse order,
07d72278 5048 which we reverse later. */
906e58ca
NC		 5049 PREV_SEC (isec) = *list;
5050 *list = isec;
5051 }
5052 }
5053}
5054
5055/* See whether we can group stub sections together. Grouping stub
5056 sections may result in fewer stubs. More importantly, we need to
07d72278 5057 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5058 .fini output sections respectively, because glibc splits the
5059 _init and _fini functions into multiple parts. Putting a stub in
5060 the middle of a function is not a good idea. */
5061
5062static void
5063group_sections (struct elf32_arm_link_hash_table *htab,
5064 bfd_size_type stub_group_size,
07d72278 5065 bfd_boolean stubs_always_after_branch)
906e58ca 5066{
07d72278 5067 asection **list = htab->input_list;
906e58ca
NC		 5068
5069 do
5070 {
5071 asection *tail = *list;
07d72278 5072 asection *head;
906e58ca
NC		 5073
5074 if (tail == bfd_abs_section_ptr)
5075 continue;
5076
07d72278
DJ		 5077 /* Reverse the list: we must avoid placing stubs at the
5078 beginning of the section because the beginning of the text
5079 section may be required for an interrupt vector in bare metal
5080 code. */
5081#define NEXT_SEC PREV_SEC
e780aef2
CL		 5082 head = NULL;
5083 while (tail != NULL)
99059e56
RM		 5084 {
5085 /* Pop from tail. */
5086 asection *item = tail;
5087 tail = PREV_SEC (item);
e780aef2 5088
99059e56
RM		 5089 /* Push on head. */
5090 NEXT_SEC (item) = head;
5091 head = item;
5092 }
07d72278
DJ		 5093
5094 while (head != NULL)
906e58ca
NC		 5095 {
5096 asection *curr;
07d72278 5097 asection *next;
e780aef2
CL		 5098 bfd_vma stub_group_start = head->output_offset;
5099 bfd_vma end_of_next;
906e58ca 5100
07d72278 5101 curr = head;
e780aef2 5102 while (NEXT_SEC (curr) != NULL)
8cd931b7 5103 {
e780aef2
CL		 5104 next = NEXT_SEC (curr);
5105 end_of_next = next->output_offset + next->size;
5106 if (end_of_next - stub_group_start >= stub_group_size)
5107 /* End of NEXT is too far from start, so stop. */
8cd931b7 5108 break;
e780aef2
CL		 5109 /* Add NEXT to the group. */
5110 curr = next;
8cd931b7 5111 }
906e58ca 5112
07d72278 5113 /* OK, the size from the start to the start of CURR is less
906e58ca 5114 than stub_group_size and thus can be handled by one stub
07d72278 5115 section. (Or the head section is itself larger than
906e58ca
NC		 5116 stub_group_size, in which case we may be toast.)
5117 We should really be keeping track of the total size of
5118 stubs added here, as stubs contribute to the final output
7fb9f789 5119 section size. */
906e58ca
NC		 5120 do
5121 {
07d72278 5122 next = NEXT_SEC (head);
906e58ca 5123 /* Set up this stub group. */
07d72278 5124 htab->stub_group[head->id].link_sec = curr;
906e58ca 5125 }
07d72278 5126 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5127
5128 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5129 bytes after the stub section can be handled by it too. */
5130 if (!stubs_always_after_branch)
906e58ca 5131 {
e780aef2
CL		 5132 stub_group_start = curr->output_offset + curr->size;
5133
8cd931b7 5134 while (next != NULL)
906e58ca 5135 {
e780aef2
CL		 5136 end_of_next = next->output_offset + next->size;
5137 if (end_of_next - stub_group_start >= stub_group_size)
5138 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5139 break;
e780aef2 5140 /* Add NEXT to the stub group. */
07d72278
DJ		 5141 head = next;
5142 next = NEXT_SEC (head);
5143 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5144 }
5145 }
07d72278 5146 head = next;
906e58ca
NC		 5147 }
5148 }
07d72278 5149 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5150
5151 free (htab->input_list);
5152#undef PREV_SEC
07d72278 5153#undef NEXT_SEC
906e58ca
NC		 5154}
5155
48229727
JB		 5156/* Comparison function for sorting/searching relocations relating to Cortex-A8
5157 erratum fix. */
5158
5159static int
5160a8_reloc_compare (const void *a, const void *b)
5161{
21d799b5
NC		 5162 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5163 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5164
5165 if (ra->from < rb->from)
5166 return -1;
5167 else if (ra->from > rb->from)
5168 return 1;
5169 else
5170 return 0;
5171}
5172
5173static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5174 const char *, char **);
5175
5176/* Helper function to scan code for sequences which might trigger the Cortex-A8
5177 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5178 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5179 otherwise. */
5180
81694485
NC		 5181static bfd_boolean
5182cortex_a8_erratum_scan (bfd *input_bfd,
5183 struct bfd_link_info *info,
48229727
JB		 5184 struct a8_erratum_fix **a8_fixes_p,
5185 unsigned int *num_a8_fixes_p,
5186 unsigned int *a8_fix_table_size_p,
5187 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5188 unsigned int num_a8_relocs,
5189 unsigned prev_num_a8_fixes,
5190 bfd_boolean *stub_changed_p)
48229727
JB		 5191{
5192 asection *section;
5193 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5194 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5195 unsigned int num_a8_fixes = *num_a8_fixes_p;
5196 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5197
4dfe6ac6
NC		 5198 if (htab == NULL)
5199 return FALSE;
5200
48229727
JB		 5201 for (section = input_bfd->sections;
5202 section != NULL;
5203 section = section->next)
5204 {
5205 bfd_byte *contents = NULL;
5206 struct _arm_elf_section_data *sec_data;
5207 unsigned int span;
5208 bfd_vma base_vma;
5209
5210 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5211 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5212 || (section->flags & SEC_EXCLUDE) != 0
5213 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5214 || (section->output_section == bfd_abs_section_ptr))
5215 continue;
48229727
JB		 5216
5217 base_vma = section->output_section->vma + section->output_offset;
5218
5219 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5220 contents = elf_section_data (section)->this_hdr.contents;
48229727 5221 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5222 return TRUE;
48229727
JB		 5223
5224 sec_data = elf32_arm_section_data (section);
5225
5226 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5227 {
5228 unsigned int span_start = sec_data->map[span].vma;
5229 unsigned int span_end = (span == sec_data->mapcount - 1)
5230 ? section->size : sec_data->map[span + 1].vma;
5231 unsigned int i;
5232 char span_type = sec_data->map[span].type;
5233 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5234
5235 if (span_type != 't')
5236 continue;
5237
5238 /* Span is entirely within a single 4KB region: skip scanning. */
5239 if (((base_vma + span_start) & ~0xfff)
48229727 5240 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5241 continue;
5242
5243 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5244
5245 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5246 * The branch target is in the same 4KB region as the
5247 first half of the branch.
5248 * The instruction before the branch is a 32-bit
5249 length non-branch instruction. */
5250 for (i = span_start; i < span_end;)
5251 {
5252 unsigned int insn = bfd_getl16 (&contents[i]);
5253 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5254 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5255
99059e56
RM		 5256 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5257 insn_32bit = TRUE;
48229727
JB		 5258
5259 if (insn_32bit)
99059e56
RM		 5260 {
5261 /* Load the rest of the insn (in manual-friendly order). */
5262 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5263
5264 /* Encoding T4: B<c>.W. */
5265 is_b = (insn & 0xf800d000) == 0xf0009000;
5266 /* Encoding T1: BL<c>.W. */
5267 is_bl = (insn & 0xf800d000) == 0xf000d000;
5268 /* Encoding T2: BLX<c>.W. */
5269 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5270 /* Encoding T3: B<c>.W (not permitted in IT block). */
5271 is_bcc = (insn & 0xf800d000) == 0xf0008000
5272 && (insn & 0x07f00000) != 0x03800000;
5273 }
5274
5275 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5276
99059e56 5277 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5278 && insn_32bit
5279 && is_32bit_branch
5280 && last_was_32bit
5281 && ! last_was_branch)
99059e56
RM		 5282 {
5283 bfd_signed_vma offset = 0;
5284 bfd_boolean force_target_arm = FALSE;
48229727 5285 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5286 bfd_vma target;
5287 enum elf32_arm_stub_type stub_type = arm_stub_none;
5288 struct a8_erratum_reloc key, *found;
5289 bfd_boolean use_plt = FALSE;
48229727 5290
99059e56
RM		 5291 key.from = base_vma + i;
5292 found = (struct a8_erratum_reloc *)
5293 bsearch (&key, a8_relocs, num_a8_relocs,
5294 sizeof (struct a8_erratum_reloc),
5295 &a8_reloc_compare);
48229727
JB		 5296
5297 if (found)
5298 {
5299 char *error_message = NULL;
5300 struct elf_link_hash_entry *entry;
5301
5302 /* We don't care about the error returned from this
99059e56 5303 function, only if there is glue or not. */
48229727
JB		 5304 entry = find_thumb_glue (info, found->sym_name,
5305 &error_message);
5306
5307 if (entry)
5308 found->non_a8_stub = TRUE;
5309
92750f34 5310 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5311 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5312 && found->hash->root.plt.offset != (bfd_vma) -1)
5313 use_plt = TRUE;
5314
5315 if (found->r_type == R_ARM_THM_CALL)
5316 {
35fc36a8
RS		 5317 if (found->branch_type == ST_BRANCH_TO_ARM
5318 || use_plt)
92750f34
DJ		 5319 force_target_arm = TRUE;
5320 else
5321 force_target_thumb = TRUE;
5322 }
48229727
JB		 5323 }
5324
99059e56 5325 /* Check if we have an offending branch instruction. */
48229727
JB		 5326
5327 if (found && found->non_a8_stub)
5328 /* We've already made a stub for this instruction, e.g.
5329 it's a long branch or a Thumb->ARM stub. Assume that
5330 stub will suffice to work around the A8 erratum (see
5331 setting of always_after_branch above). */
5332 ;
99059e56
RM		 5333 else if (is_bcc)
5334 {
5335 offset = (insn & 0x7ff) << 1;
5336 offset |= (insn & 0x3f0000) >> 4;
5337 offset |= (insn & 0x2000) ? 0x40000 : 0;
5338 offset |= (insn & 0x800) ? 0x80000 : 0;
5339 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5340 if (offset & 0x100000)
5341 offset |= ~ ((bfd_signed_vma) 0xfffff);
5342 stub_type = arm_stub_a8_veneer_b_cond;
5343 }
5344 else if (is_b || is_bl || is_blx)
5345 {
5346 int s = (insn & 0x4000000) != 0;
5347 int j1 = (insn & 0x2000) != 0;
5348 int j2 = (insn & 0x800) != 0;
5349 int i1 = !(j1 ^ s);
5350 int i2 = !(j2 ^ s);
5351
5352 offset = (insn & 0x7ff) << 1;
5353 offset |= (insn & 0x3ff0000) >> 4;
5354 offset |= i2 << 22;
5355 offset |= i1 << 23;
5356 offset |= s << 24;
5357 if (offset & 0x1000000)
5358 offset |= ~ ((bfd_signed_vma) 0xffffff);
5359
5360 if (is_blx)
5361 offset &= ~ ((bfd_signed_vma) 3);
5362
5363 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5364 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5365 }
5366
5367 if (stub_type != arm_stub_none)
5368 {
5369 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5370
5371 /* The original instruction is a BL, but the target is
99059e56 5372 an ARM instruction. If we were not making a stub,
48229727
JB		 5373 the BL would have been converted to a BLX. Use the
5374 BLX stub instead in that case. */
5375 if (htab->use_blx && force_target_arm
5376 && stub_type == arm_stub_a8_veneer_bl)
5377 {
5378 stub_type = arm_stub_a8_veneer_blx;
5379 is_blx = TRUE;
5380 is_bl = FALSE;
5381 }
5382 /* Conversely, if the original instruction was
5383 BLX but the target is Thumb mode, use the BL
5384 stub. */
5385 else if (force_target_thumb
5386 && stub_type == arm_stub_a8_veneer_blx)
5387 {
5388 stub_type = arm_stub_a8_veneer_bl;
5389 is_blx = FALSE;
5390 is_bl = TRUE;
5391 }
5392
99059e56
RM		 5393 if (is_blx)
5394 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5395
99059e56
RM		 5396 /* If we found a relocation, use the proper destination,
5397 not the offset in the (unrelocated) instruction.
48229727
JB		 5398 Note this is always done if we switched the stub type
5399 above. */
99059e56
RM		 5400 if (found)
5401 offset =
81694485 5402 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5403
99059e56
RM		 5404 /* If the stub will use a Thumb-mode branch to a
5405 PLT target, redirect it to the preceding Thumb
5406 entry point. */
5407 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5408 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5409
99059e56 5410 target = pc_for_insn + offset;
48229727 5411
99059e56
RM		 5412 /* The BLX stub is ARM-mode code. Adjust the offset to
5413 take the different PC value (+8 instead of +4) into
48229727 5414 account. */
99059e56
RM		 5415 if (stub_type == arm_stub_a8_veneer_blx)
5416 offset += 4;
5417
5418 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5419 {
5420 char *stub_name = NULL;
5421
5422 if (num_a8_fixes == a8_fix_table_size)
5423 {
5424 a8_fix_table_size *= 2;
5425 a8_fixes = (struct a8_erratum_fix *)
5426 bfd_realloc (a8_fixes,
5427 sizeof (struct a8_erratum_fix)
5428 * a8_fix_table_size);
5429 }
48229727 5430
eb7c4339
NS		 5431 if (num_a8_fixes < prev_num_a8_fixes)
5432 {
5433 /* If we're doing a subsequent scan,
5434 check if we've found the same fix as
5435 before, and try and reuse the stub
5436 name. */
5437 stub_name = a8_fixes[num_a8_fixes].stub_name;
5438 if ((a8_fixes[num_a8_fixes].section != section)
5439 || (a8_fixes[num_a8_fixes].offset != i))
5440 {
5441 free (stub_name);
5442 stub_name = NULL;
5443 *stub_changed_p = TRUE;
5444 }
5445 }
5446
5447 if (!stub_name)
5448 {
21d799b5 5449 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5450 if (stub_name != NULL)
5451 sprintf (stub_name, "%x:%x", section->id, i);
5452 }
48229727 5453
99059e56
RM		 5454 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5455 a8_fixes[num_a8_fixes].section = section;
5456 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5457 a8_fixes[num_a8_fixes].target_offset =
5458 target - base_vma;
99059e56
RM		 5459 a8_fixes[num_a8_fixes].orig_insn = insn;
5460 a8_fixes[num_a8_fixes].stub_name = stub_name;
5461 a8_fixes[num_a8_fixes].stub_type = stub_type;
5462 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5463 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5464
99059e56
RM		 5465 num_a8_fixes++;
5466 }
5467 }
5468 }
48229727 5469
99059e56
RM		 5470 i += insn_32bit ? 4 : 2;
5471 last_was_32bit = insn_32bit;
48229727 5472 last_was_branch = is_32bit_branch;
99059e56
RM		 5473 }
5474 }
48229727
JB		 5475
5476 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5477 free (contents);
48229727 5478 }
fe33d2fa 5479
48229727
JB		 5480 *a8_fixes_p = a8_fixes;
5481 *num_a8_fixes_p = num_a8_fixes;
5482 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5483
81694485 5484 return FALSE;
48229727
JB		 5485}
5486
b715f643
TP		 5487/* Create or update a stub entry depending on whether the stub can already be
5488 found in HTAB. The stub is identified by:
5489 - its type STUB_TYPE
5490 - its source branch (note that several can share the same stub) whose
5491 section and relocation (if any) are given by SECTION and IRELA
5492 respectively
5493 - its target symbol whose input section, hash, name, value and branch type
5494 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5495 respectively
5496
5497 If found, the value of the stub's target symbol is updated from SYM_VALUE
5498 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5499 TRUE and the stub entry is initialized.
5500
0955507f
TP		 5501 Returns the stub that was created or updated, or NULL if an error
5502 occurred. */
b715f643 5503
0955507f 5504static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5505elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5506 enum elf32_arm_stub_type stub_type, asection *section,
5507 Elf_Internal_Rela *irela, asection *sym_sec,
5508 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5509 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5510 bfd_boolean *new_stub)
5511{
5512 const asection *id_sec;
5513 char *stub_name;
5514 struct elf32_arm_stub_hash_entry *stub_entry;
5515 unsigned int r_type;
4f4faa4d 5516 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5517
5518 BFD_ASSERT (stub_type != arm_stub_none);
5519 *new_stub = FALSE;
5520
4f4faa4d
TP		 5521 if (sym_claimed)
5522 stub_name = sym_name;
5523 else
5524 {
5525 BFD_ASSERT (irela);
5526 BFD_ASSERT (section);
c2abbbeb 5527 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5528
4f4faa4d
TP		 5529 /* Support for grouping stub sections. */
5530 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5531
4f4faa4d
TP		 5532 /* Get the name of this stub. */
5533 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5534 stub_type);
5535 if (!stub_name)
0955507f 5536 return NULL;
4f4faa4d 5537 }
b715f643
TP		 5538
5539 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5540 FALSE);
5541 /* The proper stub has already been created, just update its value. */
5542 if (stub_entry != NULL)
5543 {
4f4faa4d
TP		 5544 if (!sym_claimed)
5545 free (stub_name);
b715f643 5546 stub_entry->target_value = sym_value;
0955507f 5547 return stub_entry;
b715f643
TP		 5548 }
5549
daa4adae 5550 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5551 if (stub_entry == NULL)
5552 {
4f4faa4d
TP		 5553 if (!sym_claimed)
5554 free (stub_name);
0955507f 5555 return NULL;
b715f643
TP		 5556 }
5557
5558 stub_entry->target_value = sym_value;
5559 stub_entry->target_section = sym_sec;
5560 stub_entry->stub_type = stub_type;
5561 stub_entry->h = hash;
5562 stub_entry->branch_type = branch_type;
5563
4f4faa4d
TP		 5564 if (sym_claimed)
5565 stub_entry->output_name = sym_name;
5566 else
b715f643 5567 {
4f4faa4d
TP		 5568 if (sym_name == NULL)
5569 sym_name = "unnamed";
5570 stub_entry->output_name = (char *)
5571 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5572 + strlen (sym_name));
5573 if (stub_entry->output_name == NULL)
5574 {
5575 free (stub_name);
0955507f 5576 return NULL;
4f4faa4d 5577 }
b715f643 5578
4f4faa4d
TP		 5579 /* For historical reasons, use the existing names for ARM-to-Thumb and
5580 Thumb-to-ARM stubs. */
5581 r_type = ELF32_R_TYPE (irela->r_info);
5582 if ((r_type == (unsigned int) R_ARM_THM_CALL
5583 || r_type == (unsigned int) R_ARM_THM_JUMP24
5584 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5585 && branch_type == ST_BRANCH_TO_ARM)
5586 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5587 else if ((r_type == (unsigned int) R_ARM_CALL
5588 || r_type == (unsigned int) R_ARM_JUMP24)
5589 && branch_type == ST_BRANCH_TO_THUMB)
5590 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5591 else
5592 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5593 }
b715f643
TP		 5594
5595 *new_stub = TRUE;
0955507f 5596 return stub_entry;
b715f643
TP		 5597}
5598
4ba2ef8f
TP		 5599/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5600 gateway veneer to transition from non secure to secure state and create them
5601 accordingly.
5602
5603 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5604 defines the conditions that govern Secure Gateway veneer creation for a
5605 given symbol <SYM> as follows:
5606 - it has function type
5607 - it has non local binding
5608 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5609 same type, binding and value as <SYM> (called normal symbol).
5610 An entry function can handle secure state transition itself in which case
5611 its special symbol would have a different value from the normal symbol.
5612
5613 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5614 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5615 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5616 created.
4ba2ef8f 5617
0955507f 5618 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5619
5620static bfd_boolean
5621cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5622 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5623 int *cmse_stub_created)
4ba2ef8f
TP		 5624{
5625 const struct elf_backend_data *bed;
5626 Elf_Internal_Shdr *symtab_hdr;
5627 unsigned i, j, sym_count, ext_start;
5628 Elf_Internal_Sym *cmse_sym, *local_syms;
5629 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5630 enum arm_st_branch_type branch_type;
5631 char *sym_name, *lsym_name;
5632 bfd_vma sym_value;
5633 asection *section;
0955507f
TP		 5634 struct elf32_arm_stub_hash_entry *stub_entry;
5635 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5636
5637 bed = get_elf_backend_data (input_bfd);
5638 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5639 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5640 ext_start = symtab_hdr->sh_info;
5641 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5642 && out_attr[Tag_CPU_arch_profile].i == 'M');
5643
5644 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5645 if (local_syms == NULL)
5646 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5647 symtab_hdr->sh_info, 0, NULL, NULL,
5648 NULL);
5649 if (symtab_hdr->sh_info && local_syms == NULL)
5650 return FALSE;
5651
5652 /* Scan symbols. */
5653 for (i = 0; i < sym_count; i++)
5654 {
5655 cmse_invalid = FALSE;
5656
5657 if (i < ext_start)
5658 {
5659 cmse_sym = &local_syms[i];
5660 /* Not a special symbol. */
5661 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5662 continue;
5663 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5664 symtab_hdr->sh_link,
5665 cmse_sym->st_name);
5666 /* Special symbol with local binding. */
5667 cmse_invalid = TRUE;
5668 }
5669 else
5670 {
5671 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5672 sym_name = (char *) cmse_hash->root.root.root.string;
5673
5674 /* Not a special symbol. */
5675 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5676 continue;
5677
5678 /* Special symbol has incorrect binding or type. */
5679 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5680 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5681 || cmse_hash->root.type != STT_FUNC)
5682 cmse_invalid = TRUE;
5683 }
5684
5685 if (!is_v8m)
5686 {
4eca0228
AM		 5687 _bfd_error_handler (_("%B: Special symbol `%s' only allowed for "
5688 "ARMv8-M architecture or later."),
5689 input_bfd, sym_name);
4ba2ef8f
TP		 5690 is_v8m = TRUE; /* Avoid multiple warning. */
5691 ret = FALSE;
5692 }
5693
5694 if (cmse_invalid)
5695 {
4eca0228
AM		 5696 _bfd_error_handler (_("%B: invalid special symbol `%s'."),
5697 input_bfd, sym_name);
5698 _bfd_error_handler (_("It must be a global or weak function "
5699 "symbol."));
4ba2ef8f
TP		 5700 ret = FALSE;
5701 if (i < ext_start)
5702 continue;
5703 }
5704
5705 sym_name += strlen (CMSE_PREFIX);
5706 hash = (struct elf32_arm_link_hash_entry *)
5707 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5708
5709 /* No associated normal symbol or it is neither global nor weak. */
5710 if (!hash
5711 || (hash->root.root.type != bfd_link_hash_defined
5712 && hash->root.root.type != bfd_link_hash_defweak)
5713 || hash->root.type != STT_FUNC)
5714 {
5715 /* Initialize here to avoid warning about use of possibly
5716 uninitialized variable. */
5717 j = 0;
5718
5719 if (!hash)
5720 {
5721 /* Searching for a normal symbol with local binding. */
5722 for (; j < ext_start; j++)
5723 {
5724 lsym_name =
5725 bfd_elf_string_from_elf_section (input_bfd,
5726 symtab_hdr->sh_link,
5727 local_syms[j].st_name);
5728 if (!strcmp (sym_name, lsym_name))
5729 break;
5730 }
5731 }
5732
5733 if (hash || j < ext_start)
5734 {
4eca0228 5735 _bfd_error_handler
4ba2ef8f 5736 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
4eca0228 5737 _bfd_error_handler
4ba2ef8f
TP		 5738 (_("It must be a global or weak function symbol."));
5739 }
5740 else
4eca0228 5741 _bfd_error_handler
4ba2ef8f
TP		 5742 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5743 ret = FALSE;
5744 if (!hash)
5745 continue;
5746 }
5747
5748 sym_value = hash->root.root.u.def.value;
5749 section = hash->root.root.u.def.section;
5750
5751 if (cmse_hash->root.root.u.def.section != section)
5752 {
4eca0228 5753 _bfd_error_handler
4ba2ef8f
TP		 5754 (_("%B: `%s' and its special symbol are in different sections."),
5755 input_bfd, sym_name);
5756 ret = FALSE;
5757 }
5758 if (cmse_hash->root.root.u.def.value != sym_value)
5759 continue; /* Ignore: could be an entry function starting with SG. */
5760
5761 /* If this section is a link-once section that will be discarded, then
5762 don't create any stubs. */
5763 if (section->output_section == NULL)
5764 {
4eca0228 5765 _bfd_error_handler
4ba2ef8f
TP		 5766 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5767 continue;
5768 }
5769
5770 if (hash->root.size == 0)
5771 {
4eca0228 5772 _bfd_error_handler
4ba2ef8f
TP		 5773 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5774 ret = FALSE;
5775 }
5776
5777 if (!ret)
5778 continue;
5779 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5780 stub_entry
4ba2ef8f
TP		 5781 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5782 NULL, NULL, section, hash, sym_name,
5783 sym_value, branch_type, &new_stub);
5784
0955507f 5785 if (stub_entry == NULL)
4ba2ef8f
TP		 5786 ret = FALSE;
5787 else
5788 {
5789 BFD_ASSERT (new_stub);
0955507f 5790 (*cmse_stub_created)++;
4ba2ef8f
TP		 5791 }
5792 }
5793
5794 if (!symtab_hdr->contents)
5795 free (local_syms);
5796 return ret;
5797}
5798
0955507f
TP		 5799/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5800 code entry function, ie can be called from non secure code without using a
5801 veneer. */
5802
5803static bfd_boolean
5804cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5805{
42484486 5806 bfd_byte contents[4];
0955507f
TP		 5807 uint32_t first_insn;
5808 asection *section;
5809 file_ptr offset;
5810 bfd *abfd;
5811
5812 /* Defined symbol of function type. */
5813 if (hash->root.root.type != bfd_link_hash_defined
5814 && hash->root.root.type != bfd_link_hash_defweak)
5815 return FALSE;
5816 if (hash->root.type != STT_FUNC)
5817 return FALSE;
5818
5819 /* Read first instruction. */
5820 section = hash->root.root.u.def.section;
5821 abfd = section->owner;
5822 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5823 if (!bfd_get_section_contents (abfd, section, contents, offset,
5824 sizeof (contents)))
0955507f
TP		 5825 return FALSE;
5826
42484486
TP		 5827 first_insn = bfd_get_32 (abfd, contents);
5828
5829 /* Starts by SG instruction. */
0955507f
TP		 5830 return first_insn == 0xe97fe97f;
5831}
5832
5833/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5834 secure gateway veneers (ie. the veneers was not in the input import library)
5835 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5836
5837static bfd_boolean
5838arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5839{
5840 struct elf32_arm_stub_hash_entry *stub_entry;
5841 struct bfd_link_info *info;
5842
5843 /* Massage our args to the form they really have. */
5844 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5845 info = (struct bfd_link_info *) gen_info;
5846
5847 if (info->out_implib_bfd)
5848 return TRUE;
5849
5850 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5851 return TRUE;
5852
5853 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5854 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5855
5856 return TRUE;
5857}
5858
5859/* Set offset of each secure gateway veneers so that its address remain
5860 identical to the one in the input import library referred by
5861 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5862 (present in input import library but absent from the executable being
5863 linked) or if new veneers appeared and there is no output import library
5864 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5865 number of secure gateway veneers found in the input import library.
5866
5867 The function returns whether an error occurred. If no error occurred,
5868 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5869 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5870 veneer observed set for new veneers to be layed out after. */
5871
5872static bfd_boolean
5873set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5874 struct elf32_arm_link_hash_table *htab,
5875 int *cmse_stub_created)
5876{
5877 long symsize;
5878 char *sym_name;
5879 flagword flags;
5880 long i, symcount;
5881 bfd *in_implib_bfd;
5882 asection *stub_out_sec;
5883 bfd_boolean ret = TRUE;
5884 Elf_Internal_Sym *intsym;
5885 const char *out_sec_name;
5886 bfd_size_type cmse_stub_size;
5887 asymbol **sympp = NULL, *sym;
5888 struct elf32_arm_link_hash_entry *hash;
5889 const insn_sequence *cmse_stub_template;
5890 struct elf32_arm_stub_hash_entry *stub_entry;
5891 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5892 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5893 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5894
5895 /* No input secure gateway import library. */
5896 if (!htab->in_implib_bfd)
5897 return TRUE;
5898
5899 in_implib_bfd = htab->in_implib_bfd;
5900 if (!htab->cmse_implib)
5901 {
4eca0228
AM		 5902 _bfd_error_handler (_("%B: --in-implib only supported for Secure "
5903 "Gateway import libraries."), in_implib_bfd);
0955507f
TP		 5904 return FALSE;
5905 }
5906
5907 /* Get symbol table size. */
5908 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5909 if (symsize < 0)
5910 return FALSE;
5911
5912 /* Read in the input secure gateway import library's symbol table. */
5913 sympp = (asymbol **) xmalloc (symsize);
5914 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5915 if (symcount < 0)
5916 {
5917 ret = FALSE;
5918 goto free_sym_buf;
5919 }
5920
5921 htab->new_cmse_stub_offset = 0;
5922 cmse_stub_size =
5923 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5924 &cmse_stub_template,
5925 &cmse_stub_template_size);
5926 out_sec_name =
5927 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5928 stub_out_sec =
5929 bfd_get_section_by_name (htab->obfd, out_sec_name);
5930 if (stub_out_sec != NULL)
5931 cmse_stub_sec_vma = stub_out_sec->vma;
5932
5933 /* Set addresses of veneers mentionned in input secure gateway import
5934 library's symbol table. */
5935 for (i = 0; i < symcount; i++)
5936 {
5937 sym = sympp[i];
5938 flags = sym->flags;
5939 sym_name = (char *) bfd_asymbol_name (sym);
5940 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5941
5942 if (sym->section != bfd_abs_section_ptr
5943 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5944 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5945 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5946 != ST_BRANCH_TO_THUMB))
5947 {
4eca0228
AM		 5948 _bfd_error_handler (_("%B: invalid import library entry: `%s'."),
5949 in_implib_bfd, sym_name);
5950 _bfd_error_handler (_("Symbol should be absolute, global and "
5951 "refer to Thumb functions."));
0955507f
TP		 5952 ret = FALSE;
5953 continue;
5954 }
5955
5956 veneer_value = bfd_asymbol_value (sym);
5957 stub_offset = veneer_value - cmse_stub_sec_vma;
5958 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5959 FALSE, FALSE);
5960 hash = (struct elf32_arm_link_hash_entry *)
5961 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5962
5963 /* Stub entry should have been created by cmse_scan or the symbol be of
5964 a secure function callable from non secure code. */
5965 if (!stub_entry && !hash)
5966 {
5967 bfd_boolean new_stub;
5968
4eca0228 5969 _bfd_error_handler
0955507f
TP		 5970 (_("Entry function `%s' disappeared from secure code."), sym_name);
5971 hash = (struct elf32_arm_link_hash_entry *)
5972 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5973 stub_entry
5974 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5975 NULL, NULL, bfd_abs_section_ptr, hash,
5976 sym_name, veneer_value,
5977 ST_BRANCH_TO_THUMB, &new_stub);
5978 if (stub_entry == NULL)
5979 ret = FALSE;
5980 else
5981 {
5982 BFD_ASSERT (new_stub);
5983 new_cmse_stubs_created++;
5984 (*cmse_stub_created)++;
5985 }
5986 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5987 stub_entry->stub_offset = stub_offset;
5988 }
5989 /* Symbol found is not callable from non secure code. */
5990 else if (!stub_entry)
5991 {
5992 if (!cmse_entry_fct_p (hash))
5993 {
4eca0228
AM		 5994 _bfd_error_handler (_("`%s' refers to a non entry function."),
5995 sym_name);
0955507f
TP		 5996 ret = FALSE;
5997 }
5998 continue;
5999 }
6000 else
6001 {
6002 /* Only stubs for SG veneers should have been created. */
6003 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6004
6005 /* Check visibility hasn't changed. */
6006 if (!!(flags & BSF_GLOBAL)
6007 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6008 _bfd_error_handler
0955507f
TP		 6009 (_("%B: visibility of symbol `%s' has changed."), in_implib_bfd,
6010 sym_name);
6011
6012 stub_entry->stub_offset = stub_offset;
6013 }
6014
6015 /* Size should match that of a SG veneer. */
6016 if (intsym->st_size != cmse_stub_size)
6017 {
4eca0228
AM		 6018 _bfd_error_handler (_("%B: incorrect size for symbol `%s'."),
6019 in_implib_bfd, sym_name);
0955507f
TP		 6020 ret = FALSE;
6021 }
6022
6023 /* Previous veneer address is before current SG veneer section. */
6024 if (veneer_value < cmse_stub_sec_vma)
6025 {
6026 /* Avoid offset underflow. */
6027 if (stub_entry)
6028 stub_entry->stub_offset = 0;
6029 stub_offset = 0;
6030 ret = FALSE;
6031 }
6032
6033 /* Complain if stub offset not a multiple of stub size. */
6034 if (stub_offset % cmse_stub_size)
6035 {
4eca0228 6036 _bfd_error_handler
0955507f
TP		 6037 (_("Offset of veneer for entry function `%s' not a multiple of "
6038 "its size."), sym_name);
6039 ret = FALSE;
6040 }
6041
6042 if (!ret)
6043 continue;
6044
6045 new_cmse_stubs_created--;
6046 if (veneer_value < cmse_stub_array_start)
6047 cmse_stub_array_start = veneer_value;
6048 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6049 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6050 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6051 }
6052
6053 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6054 {
6055 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6056 _bfd_error_handler
0955507f
TP		 6057 (_("new entry function(s) introduced but no output import library "
6058 "specified:"));
6059 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6060 }
6061
6062 if (cmse_stub_array_start != cmse_stub_sec_vma)
6063 {
4eca0228 6064 _bfd_error_handler
0955507f
TP		 6065 (_("Start address of `%s' is different from previous link."),
6066 out_sec_name);
6067 ret = FALSE;
6068 }
6069
6070free_sym_buf:
6071 free (sympp);
6072 return ret;
6073}
6074
906e58ca
NC		 6075/* Determine and set the size of the stub section for a final link.
6076
6077 The basic idea here is to examine all the relocations looking for
6078 PC-relative calls to a target that is unreachable with a "bl"
6079 instruction. */
6080
6081bfd_boolean
6082elf32_arm_size_stubs (bfd *output_bfd,
6083 bfd *stub_bfd,
6084 struct bfd_link_info *info,
6085 bfd_signed_vma group_size,
7a89b94e 6086 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6087 asection *,
7a89b94e 6088 unsigned int),
906e58ca
NC		 6089 void (*layout_sections_again) (void))
6090{
0955507f 6091 bfd_boolean ret = TRUE;
4ba2ef8f 6092 obj_attribute *out_attr;
0955507f 6093 int cmse_stub_created = 0;
906e58ca 6094 bfd_size_type stub_group_size;
4ba2ef8f 6095 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6096 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6097 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6098 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6099 struct a8_erratum_reloc *a8_relocs = NULL;
6100 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6101
4dfe6ac6
NC		 6102 if (htab == NULL)
6103 return FALSE;
6104
48229727
JB		 6105 if (htab->fix_cortex_a8)
6106 {
21d799b5 6107 a8_fixes = (struct a8_erratum_fix *)
99059e56 6108 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6109 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6110 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6111 }
906e58ca
NC		 6112
6113 /* Propagate mach to stub bfd, because it may not have been
6114 finalized when we created stub_bfd. */
6115 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6116 bfd_get_mach (output_bfd));
6117
6118 /* Stash our params away. */
6119 htab->stub_bfd = stub_bfd;
6120 htab->add_stub_section = add_stub_section;
6121 htab->layout_sections_again = layout_sections_again;
07d72278 6122 stubs_always_after_branch = group_size < 0;
48229727 6123
4ba2ef8f
TP		 6124 out_attr = elf_known_obj_attributes_proc (output_bfd);
6125 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6126
48229727
JB		 6127 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6128 as the first half of a 32-bit branch straddling two 4K pages. This is a
6129 crude way of enforcing that. */
6130 if (htab->fix_cortex_a8)
6131 stubs_always_after_branch = 1;
6132
906e58ca
NC		 6133 if (group_size < 0)
6134 stub_group_size = -group_size;
6135 else
6136 stub_group_size = group_size;
6137
6138 if (stub_group_size == 1)
6139 {
6140 /* Default values. */
6141 /* Thumb branch range is +-4MB has to be used as the default
6142 maximum size (a given section can contain both ARM and Thumb
6143 code, so the worst case has to be taken into account).
6144
6145 This value is 24K less than that, which allows for 2025
6146 12-byte stubs. If we exceed that, then we will fail to link.
6147 The user will have to relink with an explicit group size
6148 option. */
6149 stub_group_size = 4170000;
6150 }
6151
07d72278 6152 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6153
3ae046cc
NS		 6154 /* If we're applying the cortex A8 fix, we need to determine the
6155 program header size now, because we cannot change it later --
6156 that could alter section placements. Notice the A8 erratum fix
6157 ends up requiring the section addresses to remain unchanged
6158 modulo the page size. That's something we cannot represent
6159 inside BFD, and we don't want to force the section alignment to
6160 be the page size. */
6161 if (htab->fix_cortex_a8)
6162 (*htab->layout_sections_again) ();
6163
906e58ca
NC		 6164 while (1)
6165 {
6166 bfd *input_bfd;
6167 unsigned int bfd_indx;
6168 asection *stub_sec;
d7c5bd02 6169 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6170 bfd_boolean stub_changed = FALSE;
6171 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6172
48229727 6173 num_a8_fixes = 0;
906e58ca
NC		 6174 for (input_bfd = info->input_bfds, bfd_indx = 0;
6175 input_bfd != NULL;
c72f2fb2 6176 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6177 {
6178 Elf_Internal_Shdr *symtab_hdr;
6179 asection *section;
6180 Elf_Internal_Sym *local_syms = NULL;
6181
99059e56
RM		 6182 if (!is_arm_elf (input_bfd))
6183 continue;
adbcc655 6184
48229727
JB		 6185 num_a8_relocs = 0;
6186
906e58ca
NC		 6187 /* We'll need the symbol table in a second. */
6188 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6189 if (symtab_hdr->sh_info == 0)
6190 continue;
6191
4ba2ef8f
TP		 6192 /* Limit scan of symbols to object file whose profile is
6193 Microcontroller to not hinder performance in the general case. */
6194 if (m_profile && first_veneer_scan)
6195 {
6196 struct elf_link_hash_entry **sym_hashes;
6197
6198 sym_hashes = elf_sym_hashes (input_bfd);
6199 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6200 &cmse_stub_created))
4ba2ef8f 6201 goto error_ret_free_local;
0955507f
TP		 6202
6203 if (cmse_stub_created != 0)
6204 stub_changed = TRUE;
4ba2ef8f
TP		 6205 }
6206
906e58ca
NC		 6207 /* Walk over each section attached to the input bfd. */
6208 for (section = input_bfd->sections;
6209 section != NULL;
6210 section = section->next)
6211 {
6212 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6213
6214 /* If there aren't any relocs, then there's nothing more
6215 to do. */
6216 if ((section->flags & SEC_RELOC) == 0
6217 || section->reloc_count == 0
6218 || (section->flags & SEC_CODE) == 0)
6219 continue;
6220
6221 /* If this section is a link-once section that will be
6222 discarded, then don't create any stubs. */
6223 if (section->output_section == NULL
6224 || section->output_section->owner != output_bfd)
6225 continue;
6226
6227 /* Get the relocs. */
6228 internal_relocs
6229 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6230 NULL, info->keep_memory);
6231 if (internal_relocs == NULL)
6232 goto error_ret_free_local;
6233
6234 /* Now examine each relocation. */
6235 irela = internal_relocs;
6236 irelaend = irela + section->reloc_count;
6237 for (; irela < irelaend; irela++)
6238 {
6239 unsigned int r_type, r_indx;
906e58ca
NC		 6240 asection *sym_sec;
6241 bfd_vma sym_value;
6242 bfd_vma destination;
6243 struct elf32_arm_link_hash_entry *hash;
7413f23f 6244 const char *sym_name;
34e77a92 6245 unsigned char st_type;
35fc36a8 6246 enum arm_st_branch_type branch_type;
48229727 6247 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6248
6249 r_type = ELF32_R_TYPE (irela->r_info);
6250 r_indx = ELF32_R_SYM (irela->r_info);
6251
6252 if (r_type >= (unsigned int) R_ARM_max)
6253 {
6254 bfd_set_error (bfd_error_bad_value);
6255 error_ret_free_internal:
6256 if (elf_section_data (section)->relocs == NULL)
6257 free (internal_relocs);
15dd01b1
TP		 6258 /* Fall through. */
6259 error_ret_free_local:
6260 if (local_syms != NULL
6261 && (symtab_hdr->contents
6262 != (unsigned char *) local_syms))
6263 free (local_syms);
6264 return FALSE;
906e58ca 6265 }
b38cadfb 6266
0855e32b
NS		 6267 hash = NULL;
6268 if (r_indx >= symtab_hdr->sh_info)
6269 hash = elf32_arm_hash_entry
6270 (elf_sym_hashes (input_bfd)
6271 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6272
0855e32b
NS		 6273 /* Only look for stubs on branch instructions, or
6274 non-relaxed TLSCALL */
906e58ca 6275 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6276 && (r_type != (unsigned int) R_ARM_THM_CALL)
6277 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6278 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6279 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6280 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6281 && (r_type != (unsigned int) R_ARM_PLT32)
6282 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6283 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6284 && r_type == elf32_arm_tls_transition
6285 (info, r_type, &hash->root)
6286 && ((hash ? hash->tls_type
6287 : (elf32_arm_local_got_tls_type
6288 (input_bfd)[r_indx]))
6289 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6290 continue;
6291
6292 /* Now determine the call target, its name, value,
6293 section. */
6294 sym_sec = NULL;
6295 sym_value = 0;
6296 destination = 0;
7413f23f 6297 sym_name = NULL;
b38cadfb 6298
0855e32b
NS		 6299 if (r_type == (unsigned int) R_ARM_TLS_CALL
6300 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6301 {
6302 /* A non-relaxed TLS call. The target is the
6303 plt-resident trampoline and nothing to do
6304 with the symbol. */
6305 BFD_ASSERT (htab->tls_trampoline > 0);
6306 sym_sec = htab->root.splt;
6307 sym_value = htab->tls_trampoline;
6308 hash = 0;
34e77a92 6309 st_type = STT_FUNC;
35fc36a8 6310 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6311 }
6312 else if (!hash)
906e58ca
NC		 6313 {
6314 /* It's a local symbol. */
6315 Elf_Internal_Sym *sym;
906e58ca
NC		 6316
6317 if (local_syms == NULL)
6318 {
6319 local_syms
6320 = (Elf_Internal_Sym *) symtab_hdr->contents;
6321 if (local_syms == NULL)
6322 local_syms
6323 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6324 symtab_hdr->sh_info, 0,
6325 NULL, NULL, NULL);
6326 if (local_syms == NULL)
6327 goto error_ret_free_internal;
6328 }
6329
6330 sym = local_syms + r_indx;
f6d250ce
TS		 6331 if (sym->st_shndx == SHN_UNDEF)
6332 sym_sec = bfd_und_section_ptr;
6333 else if (sym->st_shndx == SHN_ABS)
6334 sym_sec = bfd_abs_section_ptr;
6335 else if (sym->st_shndx == SHN_COMMON)
6336 sym_sec = bfd_com_section_ptr;
6337 else
6338 sym_sec =
6339 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6340
ffcb4889
NS		 6341 if (!sym_sec)
6342 /* This is an undefined symbol. It can never
6a631e86 6343 be resolved. */
ffcb4889 6344 continue;
fe33d2fa 6345
906e58ca
NC		 6346 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6347 sym_value = sym->st_value;
6348 destination = (sym_value + irela->r_addend
6349 + sym_sec->output_offset
6350 + sym_sec->output_section->vma);
34e77a92 6351 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6352 branch_type =
6353 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6354 sym_name
6355 = bfd_elf_string_from_elf_section (input_bfd,
6356 symtab_hdr->sh_link,
6357 sym->st_name);
906e58ca
NC		 6358 }
6359 else
6360 {
6361 /* It's an external symbol. */
906e58ca
NC		 6362 while (hash->root.root.type == bfd_link_hash_indirect
6363 || hash->root.root.type == bfd_link_hash_warning)
6364 hash = ((struct elf32_arm_link_hash_entry *)
6365 hash->root.root.u.i.link);
6366
6367 if (hash->root.root.type == bfd_link_hash_defined
6368 || hash->root.root.type == bfd_link_hash_defweak)
6369 {
6370 sym_sec = hash->root.root.u.def.section;
6371 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6372
6373 struct elf32_arm_link_hash_table *globals =
6374 elf32_arm_hash_table (info);
6375
6376 /* For a destination in a shared library,
6377 use the PLT stub as target address to
6378 decide whether a branch stub is
6379 needed. */
4dfe6ac6 6380 if (globals != NULL
362d30a1 6381 && globals->root.splt != NULL
4dfe6ac6 6382 && hash != NULL
022f8312
CL		 6383 && hash->root.plt.offset != (bfd_vma) -1)
6384 {
362d30a1 6385 sym_sec = globals->root.splt;
022f8312
CL		 6386 sym_value = hash->root.plt.offset;
6387 if (sym_sec->output_section != NULL)
6388 destination = (sym_value
6389 + sym_sec->output_offset
6390 + sym_sec->output_section->vma);
6391 }
6392 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6393 destination = (sym_value + irela->r_addend
6394 + sym_sec->output_offset
6395 + sym_sec->output_section->vma);
6396 }
69c5861e
CL		 6397 else if ((hash->root.root.type == bfd_link_hash_undefined)
6398 || (hash->root.root.type == bfd_link_hash_undefweak))
6399 {
6400 /* For a shared library, use the PLT stub as
6401 target address to decide whether a long
6402 branch stub is needed.
6403 For absolute code, they cannot be handled. */
6404 struct elf32_arm_link_hash_table *globals =
6405 elf32_arm_hash_table (info);
6406
4dfe6ac6 6407 if (globals != NULL
362d30a1 6408 && globals->root.splt != NULL
4dfe6ac6 6409 && hash != NULL
69c5861e
CL		 6410 && hash->root.plt.offset != (bfd_vma) -1)
6411 {
362d30a1 6412 sym_sec = globals->root.splt;
69c5861e
CL		 6413 sym_value = hash->root.plt.offset;
6414 if (sym_sec->output_section != NULL)
6415 destination = (sym_value
6416 + sym_sec->output_offset
6417 + sym_sec->output_section->vma);
6418 }
6419 else
6420 continue;
6421 }
906e58ca
NC		 6422 else
6423 {
6424 bfd_set_error (bfd_error_bad_value);
6425 goto error_ret_free_internal;
6426 }
34e77a92 6427 st_type = hash->root.type;
39d911fc
TP		 6428 branch_type =
6429 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6430 sym_name = hash->root.root.root.string;
906e58ca
NC		 6431 }
6432
48229727 6433 do
7413f23f 6434 {
b715f643 6435 bfd_boolean new_stub;
0955507f 6436 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6437
48229727
JB		 6438 /* Determine what (if any) linker stub is needed. */
6439 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6440 st_type, &branch_type,
6441 hash, destination, sym_sec,
48229727
JB		 6442 input_bfd, sym_name);
6443 if (stub_type == arm_stub_none)
6444 break;
6445
48229727
JB		 6446 /* We've either created a stub for this reloc already,
6447 or we are about to. */
0955507f 6448 stub_entry =
b715f643
TP		 6449 elf32_arm_create_stub (htab, stub_type, section, irela,
6450 sym_sec, hash,
6451 (char *) sym_name, sym_value,
6452 branch_type, &new_stub);
7413f23f 6453
0955507f 6454 created_stub = stub_entry != NULL;
b715f643
TP		 6455 if (!created_stub)
6456 goto error_ret_free_internal;
6457 else if (!new_stub)
6458 break;
99059e56 6459 else
b715f643 6460 stub_changed = TRUE;
99059e56
RM		 6461 }
6462 while (0);
6463
6464 /* Look for relocations which might trigger Cortex-A8
6465 erratum. */
6466 if (htab->fix_cortex_a8
6467 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6468 || r_type == (unsigned int) R_ARM_THM_JUMP19
6469 || r_type == (unsigned int) R_ARM_THM_CALL
6470 || r_type == (unsigned int) R_ARM_THM_XPC22))
6471 {
6472 bfd_vma from = section->output_section->vma
6473 + section->output_offset
6474 + irela->r_offset;
6475
6476 if ((from & 0xfff) == 0xffe)
6477 {
6478 /* Found a candidate. Note we haven't checked the
6479 destination is within 4K here: if we do so (and
6480 don't create an entry in a8_relocs) we can't tell
6481 that a branch should have been relocated when
6482 scanning later. */
6483 if (num_a8_relocs == a8_reloc_table_size)
6484 {
6485 a8_reloc_table_size *= 2;
6486 a8_relocs = (struct a8_erratum_reloc *)
6487 bfd_realloc (a8_relocs,
6488 sizeof (struct a8_erratum_reloc)
6489 * a8_reloc_table_size);
6490 }
6491
6492 a8_relocs[num_a8_relocs].from = from;
6493 a8_relocs[num_a8_relocs].destination = destination;
6494 a8_relocs[num_a8_relocs].r_type = r_type;
6495 a8_relocs[num_a8_relocs].branch_type = branch_type;
6496 a8_relocs[num_a8_relocs].sym_name = sym_name;
6497 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6498 a8_relocs[num_a8_relocs].hash = hash;
6499
6500 num_a8_relocs++;
6501 }
6502 }
906e58ca
NC		 6503 }
6504
99059e56
RM		 6505 /* We're done with the internal relocs, free them. */
6506 if (elf_section_data (section)->relocs == NULL)
6507 free (internal_relocs);
6508 }
48229727 6509
99059e56 6510 if (htab->fix_cortex_a8)
48229727 6511 {
99059e56
RM		 6512 /* Sort relocs which might apply to Cortex-A8 erratum. */
6513 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6514 sizeof (struct a8_erratum_reloc),
99059e56 6515 &a8_reloc_compare);
48229727 6516
99059e56
RM		 6517 /* Scan for branches which might trigger Cortex-A8 erratum. */
6518 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6519 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6520 a8_relocs, num_a8_relocs,
6521 prev_num_a8_fixes, &stub_changed)
6522 != 0)
48229727 6523 goto error_ret_free_local;
5e681ec4 6524 }
7f991970
AM		 6525
6526 if (local_syms != NULL
6527 && symtab_hdr->contents != (unsigned char *) local_syms)
6528 {
6529 if (!info->keep_memory)
6530 free (local_syms);
6531 else
6532 symtab_hdr->contents = (unsigned char *) local_syms;
6533 }
5e681ec4
PB		 6534 }
6535
0955507f
TP		 6536 if (first_veneer_scan
6537 && !set_cmse_veneer_addr_from_implib (info, htab,
6538 &cmse_stub_created))
6539 ret = FALSE;
6540
eb7c4339 6541 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6542 stub_changed = TRUE;
48229727 6543
906e58ca
NC		 6544 if (!stub_changed)
6545 break;
5e681ec4 6546
906e58ca
NC		 6547 /* OK, we've added some stubs. Find out the new size of the
6548 stub sections. */
6549 for (stub_sec = htab->stub_bfd->sections;
6550 stub_sec != NULL;
6551 stub_sec = stub_sec->next)
3e6b1042
DJ		 6552 {
6553 /* Ignore non-stub sections. */
6554 if (!strstr (stub_sec->name, STUB_SUFFIX))
6555 continue;
6556
6557 stub_sec->size = 0;
6558 }
b34b2d70 6559
0955507f
TP		 6560 /* Add new SG veneers after those already in the input import
6561 library. */
6562 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6563 stub_type++)
6564 {
6565 bfd_vma *start_offset_p;
6566 asection **stub_sec_p;
6567
6568 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6569 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6570 if (start_offset_p == NULL)
6571 continue;
6572
6573 BFD_ASSERT (stub_sec_p != NULL);
6574 if (*stub_sec_p != NULL)
6575 (*stub_sec_p)->size = *start_offset_p;
6576 }
6577
d7c5bd02 6578 /* Compute stub section size, considering padding. */
906e58ca 6579 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6580 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6581 stub_type++)
6582 {
6583 int size, padding;
6584 asection **stub_sec_p;
6585
6586 padding = arm_dedicated_stub_section_padding (stub_type);
6587 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6588 /* Skip if no stub input section or no stub section padding
6589 required. */
6590 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6591 continue;
6592 /* Stub section padding required but no dedicated section. */
6593 BFD_ASSERT (stub_sec_p);
6594
6595 size = (*stub_sec_p)->size;
6596 size = (size + padding - 1) & ~(padding - 1);
6597 (*stub_sec_p)->size = size;
6598 }
906e58ca 6599
48229727
JB		 6600 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6601 if (htab->fix_cortex_a8)
99059e56
RM		 6602 for (i = 0; i < num_a8_fixes; i++)
6603 {
48229727 6604 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6605 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6606
6607 if (stub_sec == NULL)
7f991970 6608 return FALSE;
48229727 6609
99059e56
RM		 6610 stub_sec->size
6611 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6612 NULL);
6613 }
48229727
JB		 6614
6615
906e58ca
NC		 6616 /* Ask the linker to do its stuff. */
6617 (*htab->layout_sections_again) ();
4ba2ef8f 6618 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6619 }
6620
48229727
JB		 6621 /* Add stubs for Cortex-A8 erratum fixes now. */
6622 if (htab->fix_cortex_a8)
6623 {
6624 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6625 {
6626 struct elf32_arm_stub_hash_entry *stub_entry;
6627 char *stub_name = a8_fixes[i].stub_name;
6628 asection *section = a8_fixes[i].section;
6629 unsigned int section_id = a8_fixes[i].section->id;
6630 asection *link_sec = htab->stub_group[section_id].link_sec;
6631 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6632 const insn_sequence *template_sequence;
6633 int template_size, size = 0;
6634
6635 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6636 TRUE, FALSE);
6637 if (stub_entry == NULL)
6638 {
4eca0228
AM		 6639 _bfd_error_handler (_("%s: cannot create stub entry %s"),
6640 section->owner, stub_name);
99059e56
RM		 6641 return FALSE;
6642 }
6643
6644 stub_entry->stub_sec = stub_sec;
0955507f 6645 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6646 stub_entry->id_sec = link_sec;
6647 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6648 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6649 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6650 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6651 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6652 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6653
99059e56
RM		 6654 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6655 &template_sequence,
6656 &template_size);
48229727 6657
99059e56
RM		 6658 stub_entry->stub_size = size;
6659 stub_entry->stub_template = template_sequence;
6660 stub_entry->stub_template_size = template_size;
6661 }
48229727
JB		 6662
6663 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6664 elf32_arm_write_section(). */
48229727
JB		 6665 htab->a8_erratum_fixes = a8_fixes;
6666 htab->num_a8_erratum_fixes = num_a8_fixes;
6667 }
6668 else
6669 {
6670 htab->a8_erratum_fixes = NULL;
6671 htab->num_a8_erratum_fixes = 0;
6672 }
0955507f 6673 return ret;
5e681ec4
PB		 6674}
6675
906e58ca
NC		 6676/* Build all the stubs associated with the current output file. The
6677 stubs are kept in a hash table attached to the main linker hash
6678 table. We also set up the .plt entries for statically linked PIC
6679 functions here. This function is called via arm_elf_finish in the
6680 linker. */
252b5132 6681
906e58ca
NC		 6682bfd_boolean
6683elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6684{
906e58ca
NC		 6685 asection *stub_sec;
6686 struct bfd_hash_table *table;
0955507f 6687 enum elf32_arm_stub_type stub_type;
906e58ca 6688 struct elf32_arm_link_hash_table *htab;
252b5132 6689
906e58ca 6690 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6691 if (htab == NULL)
6692 return FALSE;
252b5132 6693
906e58ca
NC		 6694 for (stub_sec = htab->stub_bfd->sections;
6695 stub_sec != NULL;
6696 stub_sec = stub_sec->next)
252b5132 6697 {
906e58ca
NC		 6698 bfd_size_type size;
6699
8029a119 6700 /* Ignore non-stub sections. */
906e58ca
NC		 6701 if (!strstr (stub_sec->name, STUB_SUFFIX))
6702 continue;
6703
d7c5bd02 6704 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6705 must at least be done for stub section requiring padding and for SG
6706 veneers to ensure that a non secure code branching to a removed SG
6707 veneer causes an error. */
906e58ca 6708 size = stub_sec->size;
21d799b5 6709 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6710 if (stub_sec->contents == NULL && size != 0)
6711 return FALSE;
0955507f 6712
906e58ca 6713 stub_sec->size = 0;
252b5132
RH		 6714 }
6715
0955507f
TP		 6716 /* Add new SG veneers after those already in the input import library. */
6717 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6718 {
6719 bfd_vma *start_offset_p;
6720 asection **stub_sec_p;
6721
6722 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6723 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6724 if (start_offset_p == NULL)
6725 continue;
6726
6727 BFD_ASSERT (stub_sec_p != NULL);
6728 if (*stub_sec_p != NULL)
6729 (*stub_sec_p)->size = *start_offset_p;
6730 }
6731
906e58ca
NC		 6732 /* Build the stubs as directed by the stub hash table. */
6733 table = &htab->stub_hash_table;
6734 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6735 if (htab->fix_cortex_a8)
6736 {
6737 /* Place the cortex a8 stubs last. */
6738 htab->fix_cortex_a8 = -1;
6739 bfd_hash_traverse (table, arm_build_one_stub, info);
6740 }
252b5132 6741
906e58ca 6742 return TRUE;
252b5132
RH		 6743}
6744
9b485d32
NC		 6745/* Locate the Thumb encoded calling stub for NAME. */
6746
252b5132 6747static struct elf_link_hash_entry *
57e8b36a
NC		 6748find_thumb_glue (struct bfd_link_info *link_info,
6749 const char *name,
f2a9dd69 6750 char **error_message)
252b5132
RH		 6751{
6752 char *tmp_name;
6753 struct elf_link_hash_entry *hash;
6754 struct elf32_arm_link_hash_table *hash_table;
6755
6756 /* We need a pointer to the armelf specific hash table. */
6757 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6758 if (hash_table == NULL)
6759 return NULL;
252b5132 6760
21d799b5 6761 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6762 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6763
6764 BFD_ASSERT (tmp_name);
6765
6766 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6767
6768 hash = elf_link_hash_lookup
b34976b6 6769 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6770
b1657152
AM		 6771 if (hash == NULL
6772 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6773 tmp_name, name) == -1)
6774 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6775
6776 free (tmp_name);
6777
6778 return hash;
6779}
6780
9b485d32
NC		 6781/* Locate the ARM encoded calling stub for NAME. */
6782
252b5132 6783static struct elf_link_hash_entry *
57e8b36a
NC		 6784find_arm_glue (struct bfd_link_info *link_info,
6785 const char *name,
f2a9dd69 6786 char **error_message)
252b5132
RH		 6787{
6788 char *tmp_name;
6789 struct elf_link_hash_entry *myh;
6790 struct elf32_arm_link_hash_table *hash_table;
6791
6792 /* We need a pointer to the elfarm specific hash table. */
6793 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6794 if (hash_table == NULL)
6795 return NULL;
252b5132 6796
21d799b5 6797 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6798 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6799
6800 BFD_ASSERT (tmp_name);
6801
6802 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6803
6804 myh = elf_link_hash_lookup
b34976b6 6805 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6806
b1657152
AM		 6807 if (myh == NULL
6808 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6809 tmp_name, name) == -1)
6810 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6811
6812 free (tmp_name);
6813
6814 return myh;
6815}
6816
8f6277f5 6817/* ARM->Thumb glue (static images):
252b5132
RH		 6818
6819 .arm
6820 __func_from_arm:
6821 ldr r12, __func_addr
6822 bx r12
6823 __func_addr:
906e58ca 6824 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6825
26079076
PB		 6826 (v5t static images)
6827 .arm
6828 __func_from_arm:
6829 ldr pc, __func_addr
6830 __func_addr:
906e58ca 6831 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6832
8f6277f5
PB		 6833 (relocatable images)
6834 .arm
6835 __func_from_arm:
6836 ldr r12, __func_offset
6837 add r12, r12, pc
6838 bx r12
6839 __func_offset:
8029a119 6840 .word func - . */
8f6277f5
PB		 6841
6842#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6843static const insn32 a2t1_ldr_insn = 0xe59fc000;
6844static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6845static const insn32 a2t3_func_addr_insn = 0x00000001;
6846
26079076
PB		 6847#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6848static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6849static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6850
8f6277f5
PB		 6851#define ARM2THUMB_PIC_GLUE_SIZE 16
6852static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6853static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6854static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6855
9b485d32 6856/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6857
8029a119
NC		 6858 .thumb .thumb
6859 .align 2 .align 2
6860 __func_from_thumb: __func_from_thumb:
6861 bx pc push {r6, lr}
6862 nop ldr r6, __func_addr
6863 .arm mov lr, pc
6864 b func bx r6
99059e56
RM		 6865 .arm
6866 ;; back_to_thumb
6867 ldmia r13! {r6, lr}
6868 bx lr
6869 __func_addr:
6870 .word func */
252b5132
RH		 6871
6872#define THUMB2ARM_GLUE_SIZE 8
6873static const insn16 t2a1_bx_pc_insn = 0x4778;
6874static const insn16 t2a2_noop_insn = 0x46c0;
6875static const insn32 t2a3_b_insn = 0xea000000;
6876
c7b8f16e 6877#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6878#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6879#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6880
845b51d6
PB		 6881#define ARM_BX_VENEER_SIZE 12
6882static const insn32 armbx1_tst_insn = 0xe3100001;
6883static const insn32 armbx2_moveq_insn = 0x01a0f000;
6884static const insn32 armbx3_bx_insn = 0xe12fff10;
6885
7e392df6 6886#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6887static void
6888arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6889{
6890 asection * s;
8029a119 6891 bfd_byte * contents;
252b5132 6892
8029a119 6893 if (size == 0)
3e6b1042
DJ		 6894 {
6895 /* Do not include empty glue sections in the output. */
6896 if (abfd != NULL)
6897 {
3d4d4302 6898 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6899 if (s != NULL)
6900 s->flags |= SEC_EXCLUDE;
6901 }
6902 return;
6903 }
252b5132 6904
8029a119 6905 BFD_ASSERT (abfd != NULL);
252b5132 6906
3d4d4302 6907 s = bfd_get_linker_section (abfd, name);
8029a119 6908 BFD_ASSERT (s != NULL);
252b5132 6909
21d799b5 6910 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6911
8029a119
NC		 6912 BFD_ASSERT (s->size == size);
6913 s->contents = contents;
6914}
906e58ca 6915
8029a119
NC		 6916bfd_boolean
6917bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6918{
6919 struct elf32_arm_link_hash_table * globals;
906e58ca 6920
8029a119
NC		 6921 globals = elf32_arm_hash_table (info);
6922 BFD_ASSERT (globals != NULL);
906e58ca 6923
8029a119
NC		 6924 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6925 globals->arm_glue_size,
6926 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6927
8029a119
NC		 6928 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6929 globals->thumb_glue_size,
6930 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6931
8029a119
NC		 6932 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6933 globals->vfp11_erratum_glue_size,
6934 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6935
a504d23a
LA		 6936 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6937 globals->stm32l4xx_erratum_glue_size,
6938 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6939
8029a119
NC		 6940 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6941 globals->bx_glue_size,
845b51d6
PB		 6942 ARM_BX_GLUE_SECTION_NAME);
6943
b34976b6 6944 return TRUE;
252b5132
RH		 6945}
6946
a4fd1a8e 6947/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6948 returns the symbol identifying the stub. */
6949
a4fd1a8e 6950static struct elf_link_hash_entry *
57e8b36a
NC		 6951record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6952 struct elf_link_hash_entry * h)
252b5132
RH		 6953{
6954 const char * name = h->root.root.string;
63b0f745 6955 asection * s;
252b5132
RH		 6956 char * tmp_name;
6957 struct elf_link_hash_entry * myh;
14a793b2 6958 struct bfd_link_hash_entry * bh;
252b5132 6959 struct elf32_arm_link_hash_table * globals;
dc810e39 6960 bfd_vma val;
2f475487 6961 bfd_size_type size;
252b5132
RH		 6962
6963 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6964 BFD_ASSERT (globals != NULL);
6965 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6966
3d4d4302 6967 s = bfd_get_linker_section
252b5132
RH		 6968 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6969
252b5132
RH		 6970 BFD_ASSERT (s != NULL);
6971
21d799b5 6972 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6973 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6974
6975 BFD_ASSERT (tmp_name);
6976
6977 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6978
6979 myh = elf_link_hash_lookup
b34976b6 6980 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6981
6982 if (myh != NULL)
6983 {
9b485d32 6984 /* We've already seen this guy. */
252b5132 6985 free (tmp_name);
a4fd1a8e 6986 return myh;
252b5132
RH		 6987 }
6988
57e8b36a
NC		 6989 /* The only trick here is using hash_table->arm_glue_size as the value.
6990 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6991 putting it. The +1 on the value marks that the stub has not been
6992 output yet - not that it is a Thumb function. */
14a793b2 6993 bh = NULL;
dc810e39
AM		 6994 val = globals->arm_glue_size + 1;
6995 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6996 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6997 NULL, TRUE, FALSE, &bh);
252b5132 6998
b7693d02
DJ		 6999 myh = (struct elf_link_hash_entry *) bh;
7000 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7001 myh->forced_local = 1;
7002
252b5132
RH		 7003 free (tmp_name);
7004
0e1862bb
L		 7005 if (bfd_link_pic (link_info)
7006 || globals->root.is_relocatable_executable
27e55c4d 7007 || globals->pic_veneer)
2f475487 7008 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7009 else if (globals->use_blx)
7010 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7011 else
2f475487
AM		 7012 size = ARM2THUMB_STATIC_GLUE_SIZE;
7013
7014 s->size += size;
7015 globals->arm_glue_size += size;
252b5132 7016
a4fd1a8e 7017 return myh;
252b5132
RH		 7018}
7019
845b51d6
PB		 7020/* Allocate space for ARMv4 BX veneers. */
7021
7022static void
7023record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7024{
7025 asection * s;
7026 struct elf32_arm_link_hash_table *globals;
7027 char *tmp_name;
7028 struct elf_link_hash_entry *myh;
7029 struct bfd_link_hash_entry *bh;
7030 bfd_vma val;
7031
7032 /* BX PC does not need a veneer. */
7033 if (reg == 15)
7034 return;
7035
7036 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7037 BFD_ASSERT (globals != NULL);
7038 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7039
7040 /* Check if this veneer has already been allocated. */
7041 if (globals->bx_glue_offset[reg])
7042 return;
7043
3d4d4302 7044 s = bfd_get_linker_section
845b51d6
PB		 7045 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7046
7047 BFD_ASSERT (s != NULL);
7048
7049 /* Add symbol for veneer. */
21d799b5
NC		 7050 tmp_name = (char *)
7051 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7052
845b51d6 7053 BFD_ASSERT (tmp_name);
906e58ca 7054
845b51d6 7055 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7056
845b51d6
PB		 7057 myh = elf_link_hash_lookup
7058 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7059
845b51d6 7060 BFD_ASSERT (myh == NULL);
906e58ca 7061
845b51d6
PB		 7062 bh = NULL;
7063 val = globals->bx_glue_size;
7064 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7065 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7066 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7067
7068 myh = (struct elf_link_hash_entry *) bh;
7069 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7070 myh->forced_local = 1;
7071
7072 s->size += ARM_BX_VENEER_SIZE;
7073 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7074 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7075}
7076
7077
c7b8f16e
JB		 7078/* Add an entry to the code/data map for section SEC. */
7079
7080static void
7081elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7082{
7083 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7084 unsigned int newidx;
906e58ca 7085
c7b8f16e
JB		 7086 if (sec_data->map == NULL)
7087 {
21d799b5 7088 sec_data->map = (elf32_arm_section_map *)
99059e56 7089 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7090 sec_data->mapcount = 0;
7091 sec_data->mapsize = 1;
7092 }
906e58ca 7093
c7b8f16e 7094 newidx = sec_data->mapcount++;
906e58ca 7095
c7b8f16e
JB		 7096 if (sec_data->mapcount > sec_data->mapsize)
7097 {
7098 sec_data->mapsize *= 2;
21d799b5 7099 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7100 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7101 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7102 }
7103
7104 if (sec_data->map)
7105 {
7106 sec_data->map[newidx].vma = vma;
7107 sec_data->map[newidx].type = type;
c7b8f16e 7108 }
c7b8f16e
JB		 7109}
7110
7111
7112/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7113 veneers are handled for now. */
7114
7115static bfd_vma
7116record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7117 elf32_vfp11_erratum_list *branch,
7118 bfd *branch_bfd,
7119 asection *branch_sec,
7120 unsigned int offset)
c7b8f16e
JB		 7121{
7122 asection *s;
7123 struct elf32_arm_link_hash_table *hash_table;
7124 char *tmp_name;
7125 struct elf_link_hash_entry *myh;
7126 struct bfd_link_hash_entry *bh;
7127 bfd_vma val;
7128 struct _arm_elf_section_data *sec_data;
c7b8f16e 7129 elf32_vfp11_erratum_list *newerr;
906e58ca 7130
c7b8f16e 7131 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7132 BFD_ASSERT (hash_table != NULL);
7133 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7134
3d4d4302 7135 s = bfd_get_linker_section
c7b8f16e 7136 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7137
c7b8f16e 7138 sec_data = elf32_arm_section_data (s);
906e58ca 7139
c7b8f16e 7140 BFD_ASSERT (s != NULL);
906e58ca 7141
21d799b5 7142 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7143 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7144
c7b8f16e 7145 BFD_ASSERT (tmp_name);
906e58ca 7146
c7b8f16e
JB		 7147 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7148 hash_table->num_vfp11_fixes);
906e58ca 7149
c7b8f16e
JB		 7150 myh = elf_link_hash_lookup
7151 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7152
c7b8f16e 7153 BFD_ASSERT (myh == NULL);
906e58ca 7154
c7b8f16e
JB		 7155 bh = NULL;
7156 val = hash_table->vfp11_erratum_glue_size;
7157 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7158 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7159 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7160
7161 myh = (struct elf_link_hash_entry *) bh;
7162 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7163 myh->forced_local = 1;
7164
7165 /* Link veneer back to calling location. */
c7e2358a 7166 sec_data->erratumcount += 1;
21d799b5
NC		 7167 newerr = (elf32_vfp11_erratum_list *)
7168 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7169
c7b8f16e
JB		 7170 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7171 newerr->vma = -1;
7172 newerr->u.v.branch = branch;
7173 newerr->u.v.id = hash_table->num_vfp11_fixes;
7174 branch->u.b.veneer = newerr;
7175
7176 newerr->next = sec_data->erratumlist;
7177 sec_data->erratumlist = newerr;
7178
7179 /* A symbol for the return from the veneer. */
7180 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7181 hash_table->num_vfp11_fixes);
7182
7183 myh = elf_link_hash_lookup
7184 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7185
c7b8f16e
JB		 7186 if (myh != NULL)
7187 abort ();
7188
7189 bh = NULL;
7190 val = offset + 4;
7191 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7192 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7193
c7b8f16e
JB		 7194 myh = (struct elf_link_hash_entry *) bh;
7195 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7196 myh->forced_local = 1;
7197
7198 free (tmp_name);
906e58ca 7199
c7b8f16e
JB		 7200 /* Generate a mapping symbol for the veneer section, and explicitly add an
7201 entry for that symbol to the code/data map for the section. */
7202 if (hash_table->vfp11_erratum_glue_size == 0)
7203 {
7204 bh = NULL;
7205 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7206 ever requires this erratum fix. */
c7b8f16e
JB		 7207 _bfd_generic_link_add_one_symbol (link_info,
7208 hash_table->bfd_of_glue_owner, "$a",
7209 BSF_LOCAL, s, 0, NULL,
99059e56 7210 TRUE, FALSE, &bh);
c7b8f16e
JB		 7211
7212 myh = (struct elf_link_hash_entry *) bh;
7213 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7214 myh->forced_local = 1;
906e58ca 7215
c7b8f16e 7216 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7217 BFDs. We must make a note of this generated mapping symbol
7218 ourselves so that code byteswapping works properly in
7219 elf32_arm_write_section. */
c7b8f16e
JB		 7220 elf32_arm_section_map_add (s, 'a', 0);
7221 }
906e58ca 7222
c7b8f16e
JB		 7223 s->size += VFP11_ERRATUM_VENEER_SIZE;
7224 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7225 hash_table->num_vfp11_fixes++;
906e58ca 7226
c7b8f16e
JB		 7227 /* The offset of the veneer. */
7228 return val;
7229}
7230
a504d23a
LA		 7231/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7232 veneers need to be handled because used only in Cortex-M. */
7233
7234static bfd_vma
7235record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7236 elf32_stm32l4xx_erratum_list *branch,
7237 bfd *branch_bfd,
7238 asection *branch_sec,
7239 unsigned int offset,
7240 bfd_size_type veneer_size)
7241{
7242 asection *s;
7243 struct elf32_arm_link_hash_table *hash_table;
7244 char *tmp_name;
7245 struct elf_link_hash_entry *myh;
7246 struct bfd_link_hash_entry *bh;
7247 bfd_vma val;
7248 struct _arm_elf_section_data *sec_data;
7249 elf32_stm32l4xx_erratum_list *newerr;
7250
7251 hash_table = elf32_arm_hash_table (link_info);
7252 BFD_ASSERT (hash_table != NULL);
7253 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7254
7255 s = bfd_get_linker_section
7256 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7257
7258 BFD_ASSERT (s != NULL);
7259
7260 sec_data = elf32_arm_section_data (s);
7261
7262 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7263 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7264
7265 BFD_ASSERT (tmp_name);
7266
7267 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7268 hash_table->num_stm32l4xx_fixes);
7269
7270 myh = elf_link_hash_lookup
7271 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7272
7273 BFD_ASSERT (myh == NULL);
7274
7275 bh = NULL;
7276 val = hash_table->stm32l4xx_erratum_glue_size;
7277 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7278 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7279 NULL, TRUE, FALSE, &bh);
7280
7281 myh = (struct elf_link_hash_entry *) bh;
7282 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7283 myh->forced_local = 1;
7284
7285 /* Link veneer back to calling location. */
7286 sec_data->stm32l4xx_erratumcount += 1;
7287 newerr = (elf32_stm32l4xx_erratum_list *)
7288 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7289
7290 newerr->type = STM32L4XX_ERRATUM_VENEER;
7291 newerr->vma = -1;
7292 newerr->u.v.branch = branch;
7293 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7294 branch->u.b.veneer = newerr;
7295
7296 newerr->next = sec_data->stm32l4xx_erratumlist;
7297 sec_data->stm32l4xx_erratumlist = newerr;
7298
7299 /* A symbol for the return from the veneer. */
7300 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7301 hash_table->num_stm32l4xx_fixes);
7302
7303 myh = elf_link_hash_lookup
7304 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7305
7306 if (myh != NULL)
7307 abort ();
7308
7309 bh = NULL;
7310 val = offset + 4;
7311 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7312 branch_sec, val, NULL, TRUE, FALSE, &bh);
7313
7314 myh = (struct elf_link_hash_entry *) bh;
7315 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7316 myh->forced_local = 1;
7317
7318 free (tmp_name);
7319
7320 /* Generate a mapping symbol for the veneer section, and explicitly add an
7321 entry for that symbol to the code/data map for the section. */
7322 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7323 {
7324 bh = NULL;
7325 /* Creates a THUMB symbol since there is no other choice. */
7326 _bfd_generic_link_add_one_symbol (link_info,
7327 hash_table->bfd_of_glue_owner, "$t",
7328 BSF_LOCAL, s, 0, NULL,
7329 TRUE, FALSE, &bh);
7330
7331 myh = (struct elf_link_hash_entry *) bh;
7332 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7333 myh->forced_local = 1;
7334
7335 /* The elf32_arm_init_maps function only cares about symbols from input
7336 BFDs. We must make a note of this generated mapping symbol
7337 ourselves so that code byteswapping works properly in
7338 elf32_arm_write_section. */
7339 elf32_arm_section_map_add (s, 't', 0);
7340 }
7341
7342 s->size += veneer_size;
7343 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7344 hash_table->num_stm32l4xx_fixes++;
7345
7346 /* The offset of the veneer. */
7347 return val;
7348}
7349
8029a119 7350#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7351 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7352 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7353
7354/* Create a fake section for use by the ARM backend of the linker. */
7355
7356static bfd_boolean
7357arm_make_glue_section (bfd * abfd, const char * name)
7358{
7359 asection * sec;
7360
3d4d4302 7361 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7362 if (sec != NULL)
7363 /* Already made. */
7364 return TRUE;
7365
3d4d4302 7366 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7367
7368 if (sec == NULL
7369 || !bfd_set_section_alignment (abfd, sec, 2))
7370 return FALSE;
7371
7372 /* Set the gc mark to prevent the section from being removed by garbage
7373 collection, despite the fact that no relocs refer to this section. */
7374 sec->gc_mark = 1;
7375
7376 return TRUE;
7377}
7378
1db37fe6
YG		 7379/* Set size of .plt entries. This function is called from the
7380 linker scripts in ld/emultempl/{armelf}.em. */
7381
7382void
7383bfd_elf32_arm_use_long_plt (void)
7384{
7385 elf32_arm_use_long_plt_entry = TRUE;
7386}
7387
8afb0e02
NC		 7388/* Add the glue sections to ABFD. This function is called from the
7389 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7390
b34976b6 7391bfd_boolean
57e8b36a
NC		 7392bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7393 struct bfd_link_info *info)
252b5132 7394{
a504d23a
LA		 7395 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7396 bfd_boolean dostm32l4xx = globals
7397 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7398 bfd_boolean addglue;
7399
8afb0e02
NC		 7400 /* If we are only performing a partial
7401 link do not bother adding the glue. */
0e1862bb 7402 if (bfd_link_relocatable (info))
b34976b6 7403 return TRUE;
252b5132 7404
a504d23a 7405 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7406 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7407 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7408 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7409
7410 if (!dostm32l4xx)
7411 return addglue;
7412
7413 return addglue
7414 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7415}
7416
daa4adae
TP		 7417/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7418 ensures they are not marked for deletion by
7419 strip_excluded_output_sections () when veneers are going to be created
7420 later. Not doing so would trigger assert on empty section size in
7421 lang_size_sections_1 (). */
7422
7423void
7424bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7425{
7426 enum elf32_arm_stub_type stub_type;
7427
7428 /* If we are only performing a partial
7429 link do not bother adding the glue. */
7430 if (bfd_link_relocatable (info))
7431 return;
7432
7433 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7434 {
7435 asection *out_sec;
7436 const char *out_sec_name;
7437
7438 if (!arm_dedicated_stub_output_section_required (stub_type))
7439 continue;
7440
7441 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7442 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7443 if (out_sec != NULL)
7444 out_sec->flags |= SEC_KEEP;
7445 }
7446}
7447
8afb0e02
NC		 7448/* Select a BFD to be used to hold the sections used by the glue code.
7449 This function is called from the linker scripts in ld/emultempl/
8029a119 7450 {armelf/pe}.em. */
8afb0e02 7451
b34976b6 7452bfd_boolean
57e8b36a 7453bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7454{
7455 struct elf32_arm_link_hash_table *globals;
7456
7457 /* If we are only performing a partial link
7458 do not bother getting a bfd to hold the glue. */
0e1862bb 7459 if (bfd_link_relocatable (info))
b34976b6 7460 return TRUE;
8afb0e02 7461
b7693d02
DJ		 7462 /* Make sure we don't attach the glue sections to a dynamic object. */
7463 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7464
8afb0e02 7465 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7466 BFD_ASSERT (globals != NULL);
7467
7468 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7469 return TRUE;
8afb0e02 7470
252b5132
RH		 7471 /* Save the bfd for later use. */
7472 globals->bfd_of_glue_owner = abfd;
cedb70c5 7473
b34976b6 7474 return TRUE;
252b5132
RH		 7475}
7476
906e58ca
NC		 7477static void
7478check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7479{
2de70689
MGD		 7480 int cpu_arch;
7481
b38cadfb 7482 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7483 Tag_CPU_arch);
7484
7485 if (globals->fix_arm1176)
7486 {
7487 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7488 globals->use_blx = 1;
7489 }
7490 else
7491 {
7492 if (cpu_arch > TAG_CPU_ARCH_V4T)
7493 globals->use_blx = 1;
7494 }
39b41c9c
PB		 7495}
7496
b34976b6 7497bfd_boolean
57e8b36a 7498bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7499 struct bfd_link_info *link_info)
252b5132
RH		 7500{
7501 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7502 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7503 Elf_Internal_Rela *irel, *irelend;
7504 bfd_byte *contents = NULL;
252b5132
RH		 7505
7506 asection *sec;
7507 struct elf32_arm_link_hash_table *globals;
7508
7509 /* If we are only performing a partial link do not bother
7510 to construct any glue. */
0e1862bb 7511 if (bfd_link_relocatable (link_info))
b34976b6 7512 return TRUE;
252b5132 7513
39ce1a6a
NC		 7514 /* Here we have a bfd that is to be included on the link. We have a
7515 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7516 globals = elf32_arm_hash_table (link_info);
252b5132 7517 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7518
7519 check_use_blx (globals);
252b5132 7520
d504ffc8 7521 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7522 {
d003868e
AM		 7523 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7524 abfd);
e489d0ae
PB		 7525 return FALSE;
7526 }
f21f3fe0 7527
39ce1a6a
NC		 7528 /* PR 5398: If we have not decided to include any loadable sections in
7529 the output then we will not have a glue owner bfd. This is OK, it
7530 just means that there is nothing else for us to do here. */
7531 if (globals->bfd_of_glue_owner == NULL)
7532 return TRUE;
7533
252b5132
RH		 7534 /* Rummage around all the relocs and map the glue vectors. */
7535 sec = abfd->sections;
7536
7537 if (sec == NULL)
b34976b6 7538 return TRUE;
252b5132
RH		 7539
7540 for (; sec != NULL; sec = sec->next)
7541 {
7542 if (sec->reloc_count == 0)
7543 continue;
7544
2f475487
AM		 7545 if ((sec->flags & SEC_EXCLUDE) != 0)
7546 continue;
7547
0ffa91dd 7548 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7549
9b485d32 7550 /* Load the relocs. */
6cdc0ccc 7551 internal_relocs
906e58ca 7552 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7553
6cdc0ccc
AM		 7554 if (internal_relocs == NULL)
7555 goto error_return;
252b5132 7556
6cdc0ccc
AM		 7557 irelend = internal_relocs + sec->reloc_count;
7558 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7559 {
7560 long r_type;
7561 unsigned long r_index;
252b5132
RH		 7562
7563 struct elf_link_hash_entry *h;
7564
7565 r_type = ELF32_R_TYPE (irel->r_info);
7566 r_index = ELF32_R_SYM (irel->r_info);
7567
9b485d32 7568 /* These are the only relocation types we care about. */
ba96a88f 7569 if ( r_type != R_ARM_PC24
845b51d6 7570 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7571 continue;
7572
7573 /* Get the section contents if we haven't done so already. */
7574 if (contents == NULL)
7575 {
7576 /* Get cached copy if it exists. */
7577 if (elf_section_data (sec)->this_hdr.contents != NULL)
7578 contents = elf_section_data (sec)->this_hdr.contents;
7579 else
7580 {
7581 /* Go get them off disk. */
57e8b36a 7582 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7583 goto error_return;
7584 }
7585 }
7586
845b51d6
PB		 7587 if (r_type == R_ARM_V4BX)
7588 {
7589 int reg;
7590
7591 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7592 record_arm_bx_glue (link_info, reg);
7593 continue;
7594 }
7595
a7c10850 7596 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7597 h = NULL;
7598
9b485d32 7599 /* We don't care about local symbols. */
252b5132
RH		 7600 if (r_index < symtab_hdr->sh_info)
7601 continue;
7602
9b485d32 7603 /* This is an external symbol. */
252b5132
RH		 7604 r_index -= symtab_hdr->sh_info;
7605 h = (struct elf_link_hash_entry *)
7606 elf_sym_hashes (abfd)[r_index];
7607
7608 /* If the relocation is against a static symbol it must be within
7609 the current section and so cannot be a cross ARM/Thumb relocation. */
7610 if (h == NULL)
7611 continue;
7612
d504ffc8
DJ		 7613 /* If the call will go through a PLT entry then we do not need
7614 glue. */
362d30a1 7615 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7616 continue;
7617
252b5132
RH		 7618 switch (r_type)
7619 {
7620 case R_ARM_PC24:
7621 /* This one is a call from arm code. We need to look up
99059e56
RM		 7622 the target of the call. If it is a thumb target, we
7623 insert glue. */
39d911fc
TP		 7624 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7625 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7626 record_arm_to_thumb_glue (link_info, h);
7627 break;
7628
252b5132 7629 default:
c6596c5e 7630 abort ();
252b5132
RH		 7631 }
7632 }
6cdc0ccc
AM		 7633
7634 if (contents != NULL
7635 && elf_section_data (sec)->this_hdr.contents != contents)
7636 free (contents);
7637 contents = NULL;
7638
7639 if (internal_relocs != NULL
7640 && elf_section_data (sec)->relocs != internal_relocs)
7641 free (internal_relocs);
7642 internal_relocs = NULL;
252b5132
RH		 7643 }
7644
b34976b6 7645 return TRUE;
9a5aca8c 7646
252b5132 7647error_return:
6cdc0ccc
AM		 7648 if (contents != NULL
7649 && elf_section_data (sec)->this_hdr.contents != contents)
7650 free (contents);
7651 if (internal_relocs != NULL
7652 && elf_section_data (sec)->relocs != internal_relocs)
7653 free (internal_relocs);
9a5aca8c 7654
b34976b6 7655 return FALSE;
252b5132 7656}
7e392df6 7657#endif
252b5132 7658
eb043451 7659
c7b8f16e
JB		 7660/* Initialise maps of ARM/Thumb/data for input BFDs. */
7661
7662void
7663bfd_elf32_arm_init_maps (bfd *abfd)
7664{
7665 Elf_Internal_Sym *isymbuf;
7666 Elf_Internal_Shdr *hdr;
7667 unsigned int i, localsyms;
7668
af1f4419
NC		 7669 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7670 if (! is_arm_elf (abfd))
7671 return;
7672
c7b8f16e
JB		 7673 if ((abfd->flags & DYNAMIC) != 0)
7674 return;
7675
0ffa91dd 7676 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7677 localsyms = hdr->sh_info;
7678
7679 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7680 should contain the number of local symbols, which should come before any
7681 global symbols. Mapping symbols are always local. */
7682 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7683 NULL);
7684
7685 /* No internal symbols read? Skip this BFD. */
7686 if (isymbuf == NULL)
7687 return;
7688
7689 for (i = 0; i < localsyms; i++)
7690 {
7691 Elf_Internal_Sym *isym = &isymbuf[i];
7692 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7693 const char *name;
906e58ca 7694
c7b8f16e 7695 if (sec != NULL
99059e56
RM		 7696 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7697 {
7698 name = bfd_elf_string_from_elf_section (abfd,
7699 hdr->sh_link, isym->st_name);
906e58ca 7700
99059e56 7701 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7702 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7703 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7704 }
c7b8f16e
JB		 7705 }
7706}
7707
7708
48229727
JB		 7709/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7710 say what they wanted. */
7711
7712void
7713bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7714{
7715 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7716 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7717
4dfe6ac6
NC		 7718 if (globals == NULL)
7719 return;
7720
48229727
JB		 7721 if (globals->fix_cortex_a8 == -1)
7722 {
7723 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7724 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7725 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7726 || out_attr[Tag_CPU_arch_profile].i == 0))
7727 globals->fix_cortex_a8 = 1;
7728 else
7729 globals->fix_cortex_a8 = 0;
7730 }
7731}
7732
7733
c7b8f16e
JB		 7734void
7735bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7736{
7737 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7738 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7739
4dfe6ac6
NC		 7740 if (globals == NULL)
7741 return;
c7b8f16e
JB		 7742 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7743 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7744 {
7745 switch (globals->vfp11_fix)
99059e56
RM		 7746 {
7747 case BFD_ARM_VFP11_FIX_DEFAULT:
7748 case BFD_ARM_VFP11_FIX_NONE:
7749 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7750 break;
7751
7752 default:
7753 /* Give a warning, but do as the user requests anyway. */
4eca0228 7754 _bfd_error_handler (_("%B: warning: selected VFP11 erratum "
99059e56
RM		 7755 "workaround is not necessary for target architecture"), obfd);
7756 }
c7b8f16e
JB		 7757 }
7758 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7759 /* For earlier architectures, we might need the workaround, but do not
7760 enable it by default. If users is running with broken hardware, they
7761 must enable the erratum fix explicitly. */
7762 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7763}
7764
a504d23a
LA		 7765void
7766bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7767{
7768 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7769 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7770
7771 if (globals == NULL)
7772 return;
7773
7774 /* We assume only Cortex-M4 may require the fix. */
7775 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7776 || out_attr[Tag_CPU_arch_profile].i != 'M')
7777 {
7778 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7779 /* Give a warning, but do as the user requests anyway. */
4eca0228 7780 _bfd_error_handler
a504d23a
LA		 7781 (_("%B: warning: selected STM32L4XX erratum "
7782 "workaround is not necessary for target architecture"), obfd);
7783 }
7784}
c7b8f16e 7785
906e58ca
NC		 7786enum bfd_arm_vfp11_pipe
7787{
c7b8f16e
JB		 7788 VFP11_FMAC,
7789 VFP11_LS,
7790 VFP11_DS,
7791 VFP11_BAD
7792};
7793
7794/* Return a VFP register number. This is encoded as RX:X for single-precision
7795 registers, or X:RX for double-precision registers, where RX is the group of
7796 four bits in the instruction encoding and X is the single extension bit.
7797 RX and X fields are specified using their lowest (starting) bit. The return
7798 value is:
7799
7800 0...31: single-precision registers s0...s31
7801 32...63: double-precision registers d0...d31.
906e58ca 7802
c7b8f16e
JB		 7803 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7804 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7805
c7b8f16e
JB		 7806static unsigned int
7807bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7808 unsigned int x)
c7b8f16e
JB		 7809{
7810 if (is_double)
7811 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7812 else
7813 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7814}
7815
7816/* Set bits in *WMASK according to a register number REG as encoded by
7817 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7818
7819static void
7820bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7821{
7822 if (reg < 32)
7823 *wmask |= 1 << reg;
7824 else if (reg < 48)
7825 *wmask |= 3 << ((reg - 32) * 2);
7826}
7827
7828/* Return TRUE if WMASK overwrites anything in REGS. */
7829
7830static bfd_boolean
7831bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7832{
7833 int i;
906e58ca 7834
c7b8f16e
JB		 7835 for (i = 0; i < numregs; i++)
7836 {
7837 unsigned int reg = regs[i];
7838
7839 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7840 return TRUE;
906e58ca 7841
c7b8f16e
JB		 7842 reg -= 32;
7843
7844 if (reg >= 16)
99059e56 7845 continue;
906e58ca 7846
c7b8f16e 7847 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7848 return TRUE;
c7b8f16e 7849 }
906e58ca 7850
c7b8f16e
JB		 7851 return FALSE;
7852}
7853
7854/* In this function, we're interested in two things: finding input registers
7855 for VFP data-processing instructions, and finding the set of registers which
7856 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7857 hold the written set, so FLDM etc. are easy to deal with (we're only
7858 interested in 32 SP registers or 16 dp registers, due to the VFP version
7859 implemented by the chip in question). DP registers are marked by setting
7860 both SP registers in the write mask). */
7861
7862static enum bfd_arm_vfp11_pipe
7863bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7864 int *numregs)
c7b8f16e 7865{
91d6fa6a 7866 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7867 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7868
7869 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7870 {
7871 unsigned int pqrs;
7872 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7873 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7874
7875 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7876 | ((insn & 0x00300000) >> 19)
7877 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7878
7879 switch (pqrs)
99059e56
RM		 7880 {
7881 case 0: /* fmac[sd]. */
7882 case 1: /* fnmac[sd]. */
7883 case 2: /* fmsc[sd]. */
7884 case 3: /* fnmsc[sd]. */
7885 vpipe = VFP11_FMAC;
7886 bfd_arm_vfp11_write_mask (destmask, fd);
7887 regs[0] = fd;
7888 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7889 regs[2] = fm;
7890 *numregs = 3;
7891 break;
7892
7893 case 4: /* fmul[sd]. */
7894 case 5: /* fnmul[sd]. */
7895 case 6: /* fadd[sd]. */
7896 case 7: /* fsub[sd]. */
7897 vpipe = VFP11_FMAC;
7898 goto vfp_binop;
7899
7900 case 8: /* fdiv[sd]. */
7901 vpipe = VFP11_DS;
7902 vfp_binop:
7903 bfd_arm_vfp11_write_mask (destmask, fd);
7904 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7905 regs[1] = fm;
7906 *numregs = 2;
7907 break;
7908
7909 case 15: /* extended opcode. */
7910 {
7911 unsigned int extn = ((insn >> 15) & 0x1e)
7912 | ((insn >> 7) & 1);
7913
7914 switch (extn)
7915 {
7916 case 0: /* fcpy[sd]. */
7917 case 1: /* fabs[sd]. */
7918 case 2: /* fneg[sd]. */
7919 case 8: /* fcmp[sd]. */
7920 case 9: /* fcmpe[sd]. */
7921 case 10: /* fcmpz[sd]. */
7922 case 11: /* fcmpez[sd]. */
7923 case 16: /* fuito[sd]. */
7924 case 17: /* fsito[sd]. */
7925 case 24: /* ftoui[sd]. */
7926 case 25: /* ftouiz[sd]. */
7927 case 26: /* ftosi[sd]. */
7928 case 27: /* ftosiz[sd]. */
7929 /* These instructions will not bounce due to underflow. */
7930 *numregs = 0;
7931 vpipe = VFP11_FMAC;
7932 break;
7933
7934 case 3: /* fsqrt[sd]. */
7935 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7936 registers to cause the erratum in previous instructions. */
7937 bfd_arm_vfp11_write_mask (destmask, fd);
7938 vpipe = VFP11_DS;
7939 break;
7940
7941 case 15: /* fcvt{ds,sd}. */
7942 {
7943 int rnum = 0;
7944
7945 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7946
7947 /* Only FCVTSD can underflow. */
99059e56
RM		 7948 if ((insn & 0x100) != 0)
7949 regs[rnum++] = fm;
c7b8f16e 7950
99059e56 7951 *numregs = rnum;
c7b8f16e 7952
99059e56
RM		 7953 vpipe = VFP11_FMAC;
7954 }
7955 break;
c7b8f16e 7956
99059e56
RM		 7957 default:
7958 return VFP11_BAD;
7959 }
7960 }
7961 break;
c7b8f16e 7962
99059e56
RM		 7963 default:
7964 return VFP11_BAD;
7965 }
c7b8f16e
JB		 7966 }
7967 /* Two-register transfer. */
7968 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7969 {
7970 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7971
c7b8f16e
JB		 7972 if ((insn & 0x100000) == 0)
7973 {
99059e56
RM		 7974 if (is_double)
7975 bfd_arm_vfp11_write_mask (destmask, fm);
7976 else
7977 {
7978 bfd_arm_vfp11_write_mask (destmask, fm);
7979 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7980 }
c7b8f16e
JB		 7981 }
7982
91d6fa6a 7983 vpipe = VFP11_LS;
c7b8f16e
JB		 7984 }
7985 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7986 {
7987 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7988 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7989
c7b8f16e 7990 switch (puw)
99059e56
RM		 7991 {
7992 case 0: /* Two-reg transfer. We should catch these above. */
7993 abort ();
906e58ca 7994
99059e56
RM		 7995 case 2: /* fldm[sdx]. */
7996 case 3:
7997 case 5:
7998 {
7999 unsigned int i, offset = insn & 0xff;
c7b8f16e 8000
99059e56
RM		 8001 if (is_double)
8002 offset >>= 1;
c7b8f16e 8003
99059e56
RM		 8004 for (i = fd; i < fd + offset; i++)
8005 bfd_arm_vfp11_write_mask (destmask, i);
8006 }
8007 break;
906e58ca 8008
99059e56
RM		 8009 case 4: /* fld[sd]. */
8010 case 6:
8011 bfd_arm_vfp11_write_mask (destmask, fd);
8012 break;
906e58ca 8013
99059e56
RM		 8014 default:
8015 return VFP11_BAD;
8016 }
c7b8f16e 8017
91d6fa6a 8018 vpipe = VFP11_LS;
c7b8f16e
JB		 8019 }
8020 /* Single-register transfer. Note L==0. */
8021 else if ((insn & 0x0f100e10) == 0x0e000a10)
8022 {
8023 unsigned int opcode = (insn >> 21) & 7;
8024 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8025
8026 switch (opcode)
99059e56
RM		 8027 {
8028 case 0: /* fmsr/fmdlr. */
8029 case 1: /* fmdhr. */
8030 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8031 destination register. I don't know if this is exactly right,
8032 but it is the conservative choice. */
8033 bfd_arm_vfp11_write_mask (destmask, fn);
8034 break;
8035
8036 case 7: /* fmxr. */
8037 break;
8038 }
c7b8f16e 8039
91d6fa6a 8040 vpipe = VFP11_LS;
c7b8f16e
JB		 8041 }
8042
91d6fa6a 8043 return vpipe;
c7b8f16e
JB		 8044}
8045
8046
8047static int elf32_arm_compare_mapping (const void * a, const void * b);
8048
8049
8050/* Look for potentially-troublesome code sequences which might trigger the
8051 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8052 (available from ARM) for details of the erratum. A short version is
8053 described in ld.texinfo. */
8054
8055bfd_boolean
8056bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8057{
8058 asection *sec;
8059 bfd_byte *contents = NULL;
8060 int state = 0;
8061 int regs[3], numregs = 0;
8062 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8063 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8064
4dfe6ac6
NC		 8065 if (globals == NULL)
8066 return FALSE;
8067
c7b8f16e
JB		 8068 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8069 The states transition as follows:
906e58ca 8070
c7b8f16e 8071 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8072 A VFP FMAC-pipeline instruction has been seen. Fill
8073 regs[0]..regs[numregs-1] with its input operands. Remember this
8074 instruction in 'first_fmac'.
c7b8f16e
JB		 8075
8076 1 -> 2
99059e56
RM		 8077 Any instruction, except for a VFP instruction which overwrites
8078 regs[*].
906e58ca 8079
c7b8f16e
JB		 8080 1 -> 3 [ -> 0 ] or
8081 2 -> 3 [ -> 0 ]
99059e56
RM		 8082 A VFP instruction has been seen which overwrites any of regs[*].
8083 We must make a veneer! Reset state to 0 before examining next
8084 instruction.
906e58ca 8085
c7b8f16e 8086 2 -> 0
99059e56
RM		 8087 If we fail to match anything in state 2, reset to state 0 and reset
8088 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8089
8090 If the VFP11 vector mode is in use, there must be at least two unrelated
8091 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8092 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8093
8094 /* If we are only performing a partial link do not bother
8095 to construct any glue. */
0e1862bb 8096 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8097 return TRUE;
8098
0ffa91dd
NC		 8099 /* Skip if this bfd does not correspond to an ELF image. */
8100 if (! is_arm_elf (abfd))
8101 return TRUE;
906e58ca 8102
c7b8f16e
JB		 8103 /* We should have chosen a fix type by the time we get here. */
8104 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8105
8106 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8107 return TRUE;
2e6030b9 8108
33a7ffc2
JM		 8109 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8110 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8111 return TRUE;
8112
c7b8f16e
JB		 8113 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8114 {
8115 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8116 struct _arm_elf_section_data *sec_data;
8117
8118 /* If we don't have executable progbits, we're not interested in this
99059e56 8119 section. Also skip if section is to be excluded. */
c7b8f16e 8120 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8121 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8122 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8123 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8124 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8125 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8126 continue;
c7b8f16e
JB		 8127
8128 sec_data = elf32_arm_section_data (sec);
906e58ca 8129
c7b8f16e 8130 if (sec_data->mapcount == 0)
99059e56 8131 continue;
906e58ca 8132
c7b8f16e
JB		 8133 if (elf_section_data (sec)->this_hdr.contents != NULL)
8134 contents = elf_section_data (sec)->this_hdr.contents;
8135 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8136 goto error_return;
8137
8138 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8139 elf32_arm_compare_mapping);
8140
8141 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8142 {
8143 unsigned int span_start = sec_data->map[span].vma;
8144 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8145 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8146 char span_type = sec_data->map[span].type;
8147
8148 /* FIXME: Only ARM mode is supported at present. We may need to
8149 support Thumb-2 mode also at some point. */
8150 if (span_type != 'a')
8151 continue;
8152
8153 for (i = span_start; i < span_end;)
8154 {
8155 unsigned int next_i = i + 4;
8156 unsigned int insn = bfd_big_endian (abfd)
8157 ? (contents[i] << 24)
8158 | (contents[i + 1] << 16)
8159 | (contents[i + 2] << 8)
8160 | contents[i + 3]
8161 : (contents[i + 3] << 24)
8162 | (contents[i + 2] << 16)
8163 | (contents[i + 1] << 8)
8164 | contents[i];
8165 unsigned int writemask = 0;
8166 enum bfd_arm_vfp11_pipe vpipe;
8167
8168 switch (state)
8169 {
8170 case 0:
8171 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8172 &numregs);
8173 /* I'm assuming the VFP11 erratum can trigger with denorm
8174 operands on either the FMAC or the DS pipeline. This might
8175 lead to slightly overenthusiastic veneer insertion. */
8176 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8177 {
8178 state = use_vector ? 1 : 2;
8179 first_fmac = i;
8180 veneer_of_insn = insn;
8181 }
8182 break;
8183
8184 case 1:
8185 {
8186 int other_regs[3], other_numregs;
8187 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8188 other_regs,
99059e56
RM		 8189 &other_numregs);
8190 if (vpipe != VFP11_BAD
8191 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8192 numregs))
99059e56
RM		 8193 state = 3;
8194 else
8195 state = 2;
8196 }
8197 break;
8198
8199 case 2:
8200 {
8201 int other_regs[3], other_numregs;
8202 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8203 other_regs,
99059e56
RM		 8204 &other_numregs);
8205 if (vpipe != VFP11_BAD
8206 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8207 numregs))
99059e56
RM		 8208 state = 3;
8209 else
8210 {
8211 state = 0;
8212 next_i = first_fmac + 4;
8213 }
8214 }
8215 break;
8216
8217 case 3:
8218 abort (); /* Should be unreachable. */
8219 }
8220
8221 if (state == 3)
8222 {
8223 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8224 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8225
8226 elf32_arm_section_data (sec)->erratumcount += 1;
8227
8228 newerr->u.b.vfp_insn = veneer_of_insn;
8229
8230 switch (span_type)
8231 {
8232 case 'a':
8233 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8234 break;
8235
8236 default:
8237 abort ();
8238 }
8239
8240 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8241 first_fmac);
8242
99059e56 8243 newerr->vma = -1;
c7b8f16e 8244
99059e56
RM		 8245 newerr->next = sec_data->erratumlist;
8246 sec_data->erratumlist = newerr;
c7b8f16e 8247
99059e56
RM		 8248 state = 0;
8249 }
c7b8f16e 8250
99059e56
RM		 8251 i = next_i;
8252 }
8253 }
906e58ca 8254
c7b8f16e 8255 if (contents != NULL
99059e56
RM		 8256 && elf_section_data (sec)->this_hdr.contents != contents)
8257 free (contents);
c7b8f16e
JB		 8258 contents = NULL;
8259 }
8260
8261 return TRUE;
8262
8263error_return:
8264 if (contents != NULL
8265 && elf_section_data (sec)->this_hdr.contents != contents)
8266 free (contents);
906e58ca 8267
c7b8f16e
JB		 8268 return FALSE;
8269}
8270
8271/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8272 after sections have been laid out, using specially-named symbols. */
8273
8274void
8275bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8276 struct bfd_link_info *link_info)
8277{
8278 asection *sec;
8279 struct elf32_arm_link_hash_table *globals;
8280 char *tmp_name;
906e58ca 8281
0e1862bb 8282 if (bfd_link_relocatable (link_info))
c7b8f16e 8283 return;
2e6030b9
MS		 8284
8285 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8286 if (! is_arm_elf (abfd))
2e6030b9
MS		 8287 return;
8288
c7b8f16e 8289 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8290 if (globals == NULL)
8291 return;
906e58ca 8292
21d799b5 8293 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8294 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8295
8296 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8297 {
8298 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8299 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8300
c7b8f16e 8301 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8302 {
8303 struct elf_link_hash_entry *myh;
8304 bfd_vma vma;
8305
8306 switch (errnode->type)
8307 {
8308 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8309 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8310 /* Find veneer symbol. */
8311 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8312 errnode->u.b.veneer->u.v.id);
8313
99059e56
RM		 8314 myh = elf_link_hash_lookup
8315 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8316
a504d23a 8317 if (myh == NULL)
4eca0228
AM		 8318 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8319 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8320
8321 vma = myh->root.u.def.section->output_section->vma
8322 + myh->root.u.def.section->output_offset
8323 + myh->root.u.def.value;
8324
8325 errnode->u.b.veneer->vma = vma;
8326 break;
8327
8328 case VFP11_ERRATUM_ARM_VENEER:
8329 case VFP11_ERRATUM_THUMB_VENEER:
8330 /* Find return location. */
8331 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8332 errnode->u.v.id);
8333
8334 myh = elf_link_hash_lookup
8335 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8336
8337 if (myh == NULL)
4eca0228
AM		 8338 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8339 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8340
8341 vma = myh->root.u.def.section->output_section->vma
8342 + myh->root.u.def.section->output_offset
8343 + myh->root.u.def.value;
8344
8345 errnode->u.v.branch->vma = vma;
8346 break;
8347
8348 default:
8349 abort ();
8350 }
8351 }
8352 }
8353
8354 free (tmp_name);
8355}
8356
8357/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8358 return locations after sections have been laid out, using
8359 specially-named symbols. */
8360
8361void
8362bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8363 struct bfd_link_info *link_info)
8364{
8365 asection *sec;
8366 struct elf32_arm_link_hash_table *globals;
8367 char *tmp_name;
8368
8369 if (bfd_link_relocatable (link_info))
8370 return;
8371
8372 /* Skip if this bfd does not correspond to an ELF image. */
8373 if (! is_arm_elf (abfd))
8374 return;
8375
8376 globals = elf32_arm_hash_table (link_info);
8377 if (globals == NULL)
8378 return;
8379
8380 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8381 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8382
8383 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8384 {
8385 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8386 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8387
8388 for (; errnode != NULL; errnode = errnode->next)
8389 {
8390 struct elf_link_hash_entry *myh;
8391 bfd_vma vma;
8392
8393 switch (errnode->type)
8394 {
8395 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8396 /* Find veneer symbol. */
8397 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8398 errnode->u.b.veneer->u.v.id);
8399
8400 myh = elf_link_hash_lookup
8401 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8402
8403 if (myh == NULL)
4eca0228
AM		 8404 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8405 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8406
8407 vma = myh->root.u.def.section->output_section->vma
8408 + myh->root.u.def.section->output_offset
8409 + myh->root.u.def.value;
8410
8411 errnode->u.b.veneer->vma = vma;
8412 break;
8413
8414 case STM32L4XX_ERRATUM_VENEER:
8415 /* Find return location. */
8416 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8417 errnode->u.v.id);
8418
8419 myh = elf_link_hash_lookup
8420 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8421
8422 if (myh == NULL)
4eca0228
AM		 8423 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8424 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8425
8426 vma = myh->root.u.def.section->output_section->vma
8427 + myh->root.u.def.section->output_offset
8428 + myh->root.u.def.value;
8429
8430 errnode->u.v.branch->vma = vma;
8431 break;
8432
8433 default:
8434 abort ();
8435 }
8436 }
8437 }
8438
8439 free (tmp_name);
8440}
8441
8442static inline bfd_boolean
8443is_thumb2_ldmia (const insn32 insn)
8444{
8445 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8446 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8447 return (insn & 0xffd02000) == 0xe8900000;
8448}
8449
8450static inline bfd_boolean
8451is_thumb2_ldmdb (const insn32 insn)
8452{
8453 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8454 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8455 return (insn & 0xffd02000) == 0xe9100000;
8456}
8457
8458static inline bfd_boolean
8459is_thumb2_vldm (const insn32 insn)
8460{
8461 /* A6.5 Extension register load or store instruction
8462 A7.7.229
9239bbd3
CM		 8463 We look for SP 32-bit and DP 64-bit registers.
8464 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8465 <list> is consecutive 64-bit registers
8466 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8467 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8468 <list> is consecutive 32-bit registers
8469 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8470 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8471 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8472 return
9239bbd3
CM		 8473 (((insn & 0xfe100f00) == 0xec100b00) ||
8474 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8475 && /* (IA without !). */
8476 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8477 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8478 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8479 /* (DB with !). */
8480 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8481}
8482
8483/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8484 VLDM opcode and:
8485 - computes the number and the mode of memory accesses
8486 - decides if the replacement should be done:
8487 . replaces only if > 8-word accesses
8488 . or (testing purposes only) replaces all accesses. */
8489
8490static bfd_boolean
8491stm32l4xx_need_create_replacing_stub (const insn32 insn,
8492 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8493{
9239bbd3 8494 int nb_words = 0;
a504d23a
LA		 8495
8496 /* The field encoding the register list is the same for both LDMIA
8497 and LDMDB encodings. */
8498 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 8499 nb_words = popcount (insn & 0x0000ffff);
a504d23a 8500 else if (is_thumb2_vldm (insn))
9239bbd3 8501 nb_words = (insn & 0xff);
a504d23a
LA		 8502
8503 /* DEFAULT mode accounts for the real bug condition situation,
8504 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8505 return
9239bbd3 8506 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8507 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8508}
8509
8510/* Look for potentially-troublesome code sequences which might trigger
8511 the STM STM32L4XX erratum. */
8512
8513bfd_boolean
8514bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8515 struct bfd_link_info *link_info)
8516{
8517 asection *sec;
8518 bfd_byte *contents = NULL;
8519 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8520
8521 if (globals == NULL)
8522 return FALSE;
8523
8524 /* If we are only performing a partial link do not bother
8525 to construct any glue. */
8526 if (bfd_link_relocatable (link_info))
8527 return TRUE;
8528
8529 /* Skip if this bfd does not correspond to an ELF image. */
8530 if (! is_arm_elf (abfd))
8531 return TRUE;
8532
8533 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8534 return TRUE;
8535
8536 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8537 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8538 return TRUE;
8539
8540 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8541 {
8542 unsigned int i, span;
8543 struct _arm_elf_section_data *sec_data;
8544
8545 /* If we don't have executable progbits, we're not interested in this
8546 section. Also skip if section is to be excluded. */
8547 if (elf_section_type (sec) != SHT_PROGBITS
8548 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8549 || (sec->flags & SEC_EXCLUDE) != 0
8550 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8551 || sec->output_section == bfd_abs_section_ptr
8552 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8553 continue;
8554
8555 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8556
a504d23a
LA		 8557 if (sec_data->mapcount == 0)
8558 continue;
c7b8f16e 8559
a504d23a
LA		 8560 if (elf_section_data (sec)->this_hdr.contents != NULL)
8561 contents = elf_section_data (sec)->this_hdr.contents;
8562 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8563 goto error_return;
c7b8f16e 8564
a504d23a
LA		 8565 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8566 elf32_arm_compare_mapping);
c7b8f16e 8567
a504d23a
LA		 8568 for (span = 0; span < sec_data->mapcount; span++)
8569 {
8570 unsigned int span_start = sec_data->map[span].vma;
8571 unsigned int span_end = (span == sec_data->mapcount - 1)
8572 ? sec->size : sec_data->map[span + 1].vma;
8573 char span_type = sec_data->map[span].type;
8574 int itblock_current_pos = 0;
c7b8f16e 8575
a504d23a
LA		 8576 /* Only Thumb2 mode need be supported with this CM4 specific
8577 code, we should not encounter any arm mode eg span_type
8578 != 'a'. */
8579 if (span_type != 't')
8580 continue;
c7b8f16e 8581
a504d23a
LA		 8582 for (i = span_start; i < span_end;)
8583 {
8584 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8585 bfd_boolean insn_32bit = FALSE;
8586 bfd_boolean is_ldm = FALSE;
8587 bfd_boolean is_vldm = FALSE;
8588 bfd_boolean is_not_last_in_it_block = FALSE;
8589
8590 /* The first 16-bits of all 32-bit thumb2 instructions start
8591 with opcode[15..13]=0b111 and the encoded op1 can be anything
8592 except opcode[12..11]!=0b00.
8593 See 32-bit Thumb instruction encoding. */
8594 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8595 insn_32bit = TRUE;
c7b8f16e 8596
a504d23a
LA		 8597 /* Compute the predicate that tells if the instruction
8598 is concerned by the IT block
8599 - Creates an error if there is a ldm that is not
8600 last in the IT block thus cannot be replaced
8601 - Otherwise we can create a branch at the end of the
8602 IT block, it will be controlled naturally by IT
8603 with the proper pseudo-predicate
8604 - So the only interesting predicate is the one that
8605 tells that we are not on the last item of an IT
8606 block. */
8607 if (itblock_current_pos != 0)
8608 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8609
a504d23a
LA		 8610 if (insn_32bit)
8611 {
8612 /* Load the rest of the insn (in manual-friendly order). */
8613 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8614 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8615 is_vldm = is_thumb2_vldm (insn);
8616
8617 /* Veneers are created for (v)ldm depending on
8618 option flags and memory accesses conditions; but
8619 if the instruction is not the last instruction of
8620 an IT block, we cannot create a jump there, so we
8621 bail out. */
5025eb7c
AO		 8622 if ((is_ldm || is_vldm)
8623 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8624 (insn, globals->stm32l4xx_fix))
8625 {
8626 if (is_not_last_in_it_block)
8627 {
4eca0228 8628 _bfd_error_handler
a504d23a 8629 /* Note - overlong line used here to allow for translation. */
695344c0 8630 /* xgettext:c-format */
a504d23a
LA		 8631 (_("\
8632%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
8633 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
695344c0 8634 abfd, sec, (long) i);
a504d23a
LA		 8635 }
8636 else
8637 {
8638 elf32_stm32l4xx_erratum_list *newerr =
8639 (elf32_stm32l4xx_erratum_list *)
8640 bfd_zmalloc
8641 (sizeof (elf32_stm32l4xx_erratum_list));
8642
8643 elf32_arm_section_data (sec)
8644 ->stm32l4xx_erratumcount += 1;
8645 newerr->u.b.insn = insn;
8646 /* We create only thumb branches. */
8647 newerr->type =
8648 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8649 record_stm32l4xx_erratum_veneer
8650 (link_info, newerr, abfd, sec,
8651 i,
8652 is_ldm ?
8653 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8654 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8655 newerr->vma = -1;
8656 newerr->next = sec_data->stm32l4xx_erratumlist;
8657 sec_data->stm32l4xx_erratumlist = newerr;
8658 }
8659 }
8660 }
8661 else
8662 {
8663 /* A7.7.37 IT p208
8664 IT blocks are only encoded in T1
8665 Encoding T1: IT{x{y{z}}} <firstcond>
8666 1 0 1 1 - 1 1 1 1 - firstcond - mask
8667 if mask = '0000' then see 'related encodings'
8668 We don't deal with UNPREDICTABLE, just ignore these.
8669 There can be no nested IT blocks so an IT block
8670 is naturally a new one for which it is worth
8671 computing its size. */
5025eb7c
AO		 8672 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8673 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8674 /* If we have a new IT block we compute its size. */
8675 if (is_newitblock)
8676 {
8677 /* Compute the number of instructions controlled
8678 by the IT block, it will be used to decide
8679 whether we are inside an IT block or not. */
8680 unsigned int mask = insn & 0x000f;
8681 itblock_current_pos = 4 - ctz (mask);
8682 }
8683 }
8684
8685 i += insn_32bit ? 4 : 2;
99059e56
RM		 8686 }
8687 }
a504d23a
LA		 8688
8689 if (contents != NULL
8690 && elf_section_data (sec)->this_hdr.contents != contents)
8691 free (contents);
8692 contents = NULL;
c7b8f16e 8693 }
906e58ca 8694
a504d23a
LA		 8695 return TRUE;
8696
8697error_return:
8698 if (contents != NULL
8699 && elf_section_data (sec)->this_hdr.contents != contents)
8700 free (contents);
c7b8f16e 8701
a504d23a
LA		 8702 return FALSE;
8703}
c7b8f16e 8704
eb043451
PB		 8705/* Set target relocation values needed during linking. */
8706
8707void
68c39892 8708bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8709 struct bfd_link_info *link_info,
68c39892 8710 struct elf32_arm_params *params)
eb043451
PB		 8711{
8712 struct elf32_arm_link_hash_table *globals;
8713
8714 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8715 if (globals == NULL)
8716 return;
eb043451 8717
68c39892
TP		 8718 globals->target1_is_rel = params->target1_is_rel;
8719 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8720 globals->target2_reloc = R_ARM_REL32;
68c39892 8721 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8722 globals->target2_reloc = R_ARM_ABS32;
68c39892 8723 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8724 globals->target2_reloc = R_ARM_GOT_PREL;
8725 else
8726 {
8727 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
68c39892 8728 params->target2_type);
eb043451 8729 }
68c39892
TP		 8730 globals->fix_v4bx = params->fix_v4bx;
8731 globals->use_blx |= params->use_blx;
8732 globals->vfp11_fix = params->vfp11_denorm_fix;
8733 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8734 globals->pic_veneer = params->pic_veneer;
8735 globals->fix_cortex_a8 = params->fix_cortex_a8;
8736 globals->fix_arm1176 = params->fix_arm1176;
8737 globals->cmse_implib = params->cmse_implib;
8738 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8739
0ffa91dd 8740 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8741 elf_arm_tdata (output_bfd)->no_enum_size_warning
8742 = params->no_enum_size_warning;
8743 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8744 = params->no_wchar_size_warning;
eb043451 8745}
eb043451 8746
12a0a0fd 8747/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8748
12a0a0fd
PB		 8749static void
8750insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8751{
8752 bfd_vma upper;
8753 bfd_vma lower;
8754 int reloc_sign;
8755
8756 BFD_ASSERT ((offset & 1) == 0);
8757
8758 upper = bfd_get_16 (abfd, insn);
8759 lower = bfd_get_16 (abfd, insn + 2);
8760 reloc_sign = (offset < 0) ? 1 : 0;
8761 upper = (upper & ~(bfd_vma) 0x7ff)
8762 | ((offset >> 12) & 0x3ff)
8763 | (reloc_sign << 10);
906e58ca 8764 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8765 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8766 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8767 | ((offset >> 1) & 0x7ff);
8768 bfd_put_16 (abfd, upper, insn);
8769 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8770}
8771
9b485d32
NC		 8772/* Thumb code calling an ARM function. */
8773
252b5132 8774static int
57e8b36a
NC		 8775elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8776 const char * name,
8777 bfd * input_bfd,
8778 bfd * output_bfd,
8779 asection * input_section,
8780 bfd_byte * hit_data,
8781 asection * sym_sec,
8782 bfd_vma offset,
8783 bfd_signed_vma addend,
f2a9dd69
DJ		 8784 bfd_vma val,
8785 char **error_message)
252b5132 8786{
bcbdc74c 8787 asection * s = 0;
dc810e39 8788 bfd_vma my_offset;
252b5132 8789 long int ret_offset;
bcbdc74c
NC		 8790 struct elf_link_hash_entry * myh;
8791 struct elf32_arm_link_hash_table * globals;
252b5132 8792
f2a9dd69 8793 myh = find_thumb_glue (info, name, error_message);
252b5132 8794 if (myh == NULL)
b34976b6 8795 return FALSE;
252b5132
RH		 8796
8797 globals = elf32_arm_hash_table (info);
252b5132
RH		 8798 BFD_ASSERT (globals != NULL);
8799 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8800
8801 my_offset = myh->root.u.def.value;
8802
3d4d4302
AM		 8803 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8804 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8805
8806 BFD_ASSERT (s != NULL);
8807 BFD_ASSERT (s->contents != NULL);
8808 BFD_ASSERT (s->output_section != NULL);
8809
8810 if ((my_offset & 0x01) == 0x01)
8811 {
8812 if (sym_sec != NULL
8813 && sym_sec->owner != NULL
8814 && !INTERWORK_FLAG (sym_sec->owner))
8815 {
4eca0228 8816 _bfd_error_handler
d003868e 8817 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8818 " first occurrence: %B: Thumb call to ARM"),
d003868e 8819 sym_sec->owner, input_bfd, name);
252b5132 8820
b34976b6 8821 return FALSE;
252b5132
RH		 8822 }
8823
8824 --my_offset;
8825 myh->root.u.def.value = my_offset;
8826
52ab56c2
PB		 8827 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8828 s->contents + my_offset);
252b5132 8829
52ab56c2
PB		 8830 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8831 s->contents + my_offset + 2);
252b5132
RH		 8832
8833 ret_offset =
9b485d32
NC		 8834 /* Address of destination of the stub. */
8835 ((bfd_signed_vma) val)
252b5132 8836 - ((bfd_signed_vma)
57e8b36a
NC		 8837 /* Offset from the start of the current section
8838 to the start of the stubs. */
9b485d32
NC		 8839 (s->output_offset
8840 /* Offset of the start of this stub from the start of the stubs. */
8841 + my_offset
8842 /* Address of the start of the current section. */
8843 + s->output_section->vma)
8844 /* The branch instruction is 4 bytes into the stub. */
8845 + 4
8846 /* ARM branches work from the pc of the instruction + 8. */
8847 + 8);
252b5132 8848
52ab56c2
PB		 8849 put_arm_insn (globals, output_bfd,
8850 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8851 s->contents + my_offset + 4);
252b5132
RH		 8852 }
8853
8854 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8855
427bfd90
NC		 8856 /* Now go back and fix up the original BL insn to point to here. */
8857 ret_offset =
8858 /* Address of where the stub is located. */
8859 (s->output_section->vma + s->output_offset + my_offset)
8860 /* Address of where the BL is located. */
57e8b36a
NC		 8861 - (input_section->output_section->vma + input_section->output_offset
8862 + offset)
427bfd90
NC		 8863 /* Addend in the relocation. */
8864 - addend
8865 /* Biassing for PC-relative addressing. */
8866 - 8;
252b5132 8867
12a0a0fd 8868 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8869
b34976b6 8870 return TRUE;
252b5132
RH		 8871}
8872
a4fd1a8e 8873/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8874
a4fd1a8e
PB		 8875static struct elf_link_hash_entry *
8876elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8877 const char * name,
8878 bfd * input_bfd,
8879 bfd * output_bfd,
8880 asection * sym_sec,
8881 bfd_vma val,
8029a119
NC		 8882 asection * s,
8883 char ** error_message)
252b5132 8884{
dc810e39 8885 bfd_vma my_offset;
252b5132 8886 long int ret_offset;
bcbdc74c
NC		 8887 struct elf_link_hash_entry * myh;
8888 struct elf32_arm_link_hash_table * globals;
252b5132 8889
f2a9dd69 8890 myh = find_arm_glue (info, name, error_message);
252b5132 8891 if (myh == NULL)
a4fd1a8e 8892 return NULL;
252b5132
RH		 8893
8894 globals = elf32_arm_hash_table (info);
252b5132
RH		 8895 BFD_ASSERT (globals != NULL);
8896 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8897
8898 my_offset = myh->root.u.def.value;
252b5132
RH		 8899
8900 if ((my_offset & 0x01) == 0x01)
8901 {
8902 if (sym_sec != NULL
8903 && sym_sec->owner != NULL
8904 && !INTERWORK_FLAG (sym_sec->owner))
8905 {
4eca0228 8906 _bfd_error_handler
d003868e
AM		 8907 (_("%B(%s): warning: interworking not enabled.\n"
8908 " first occurrence: %B: arm call to thumb"),
8909 sym_sec->owner, input_bfd, name);
252b5132 8910 }
9b485d32 8911
252b5132
RH		 8912 --my_offset;
8913 myh->root.u.def.value = my_offset;
8914
0e1862bb
L		 8915 if (bfd_link_pic (info)
8916 || globals->root.is_relocatable_executable
27e55c4d 8917 || globals->pic_veneer)
8f6277f5
PB		 8918 {
8919 /* For relocatable objects we can't use absolute addresses,
8920 so construct the address from a relative offset. */
8921 /* TODO: If the offset is small it's probably worth
8922 constructing the address with adds. */
52ab56c2
PB		 8923 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8924 s->contents + my_offset);
8925 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8926 s->contents + my_offset + 4);
8927 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8928 s->contents + my_offset + 8);
8f6277f5
PB		 8929 /* Adjust the offset by 4 for the position of the add,
8930 and 8 for the pipeline offset. */
8931 ret_offset = (val - (s->output_offset
8932 + s->output_section->vma
8933 + my_offset + 12))
8934 | 1;
8935 bfd_put_32 (output_bfd, ret_offset,
8936 s->contents + my_offset + 12);
8937 }
26079076
PB		 8938 else if (globals->use_blx)
8939 {
8940 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8941 s->contents + my_offset);
8942
8943 /* It's a thumb address. Add the low order bit. */
8944 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8945 s->contents + my_offset + 4);
8946 }
8f6277f5
PB		 8947 else
8948 {
52ab56c2
PB		 8949 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8950 s->contents + my_offset);
252b5132 8951
52ab56c2
PB		 8952 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8953 s->contents + my_offset + 4);
252b5132 8954
8f6277f5
PB		 8955 /* It's a thumb address. Add the low order bit. */
8956 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8957 s->contents + my_offset + 8);
8029a119
NC		 8958
8959 my_offset += 12;
8f6277f5 8960 }
252b5132
RH		 8961 }
8962
8963 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8964
a4fd1a8e
PB		 8965 return myh;
8966}
8967
8968/* Arm code calling a Thumb function. */
8969
8970static int
8971elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8972 const char * name,
8973 bfd * input_bfd,
8974 bfd * output_bfd,
8975 asection * input_section,
8976 bfd_byte * hit_data,
8977 asection * sym_sec,
8978 bfd_vma offset,
8979 bfd_signed_vma addend,
f2a9dd69
DJ		 8980 bfd_vma val,
8981 char **error_message)
a4fd1a8e
PB		 8982{
8983 unsigned long int tmp;
8984 bfd_vma my_offset;
8985 asection * s;
8986 long int ret_offset;
8987 struct elf_link_hash_entry * myh;
8988 struct elf32_arm_link_hash_table * globals;
8989
8990 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8991 BFD_ASSERT (globals != NULL);
8992 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8993
3d4d4302
AM		 8994 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8995 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8996 BFD_ASSERT (s != NULL);
8997 BFD_ASSERT (s->contents != NULL);
8998 BFD_ASSERT (s->output_section != NULL);
8999
9000 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9001 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9002 if (!myh)
9003 return FALSE;
9004
9005 my_offset = myh->root.u.def.value;
252b5132
RH		 9006 tmp = bfd_get_32 (input_bfd, hit_data);
9007 tmp = tmp & 0xFF000000;
9008
9b485d32 9009 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9010 ret_offset = (s->output_offset
9011 + my_offset
9012 + s->output_section->vma
9013 - (input_section->output_offset
9014 + input_section->output_section->vma
9015 + offset + addend)
9016 - 8);
9a5aca8c 9017
252b5132
RH		 9018 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9019
dc810e39 9020 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9021
b34976b6 9022 return TRUE;
252b5132
RH		 9023}
9024
a4fd1a8e
PB		 9025/* Populate Arm stub for an exported Thumb function. */
9026
9027static bfd_boolean
9028elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9029{
9030 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9031 asection * s;
9032 struct elf_link_hash_entry * myh;
9033 struct elf32_arm_link_hash_entry *eh;
9034 struct elf32_arm_link_hash_table * globals;
9035 asection *sec;
9036 bfd_vma val;
f2a9dd69 9037 char *error_message;
a4fd1a8e 9038
906e58ca 9039 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9040 /* Allocate stubs for exported Thumb functions on v4t. */
9041 if (eh->export_glue == NULL)
9042 return TRUE;
9043
9044 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9045 BFD_ASSERT (globals != NULL);
9046 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9047
3d4d4302
AM		 9048 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9049 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9050 BFD_ASSERT (s != NULL);
9051 BFD_ASSERT (s->contents != NULL);
9052 BFD_ASSERT (s->output_section != NULL);
9053
9054 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9055
9056 BFD_ASSERT (sec->output_section != NULL);
9057
a4fd1a8e
PB		 9058 val = eh->export_glue->root.u.def.value + sec->output_offset
9059 + sec->output_section->vma;
8029a119 9060
a4fd1a8e
PB		 9061 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9062 h->root.u.def.section->owner,
f2a9dd69
DJ		 9063 globals->obfd, sec, val, s,
9064 &error_message);
a4fd1a8e
PB		 9065 BFD_ASSERT (myh);
9066 return TRUE;
9067}
9068
845b51d6
PB		 9069/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9070
9071static bfd_vma
9072elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9073{
9074 bfd_byte *p;
9075 bfd_vma glue_addr;
9076 asection *s;
9077 struct elf32_arm_link_hash_table *globals;
9078
9079 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9080 BFD_ASSERT (globals != NULL);
9081 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9082
3d4d4302
AM		 9083 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9084 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9085 BFD_ASSERT (s != NULL);
9086 BFD_ASSERT (s->contents != NULL);
9087 BFD_ASSERT (s->output_section != NULL);
9088
9089 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9090
9091 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9092
9093 if ((globals->bx_glue_offset[reg] & 1) == 0)
9094 {
9095 p = s->contents + glue_addr;
9096 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9097 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9098 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9099 globals->bx_glue_offset[reg] |= 1;
9100 }
9101
9102 return glue_addr + s->output_section->vma + s->output_offset;
9103}
9104
a4fd1a8e
PB		 9105/* Generate Arm stubs for exported Thumb symbols. */
9106static void
906e58ca 9107elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9108 struct bfd_link_info *link_info)
9109{
9110 struct elf32_arm_link_hash_table * globals;
9111
8029a119
NC		 9112 if (link_info == NULL)
9113 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9114 return;
9115
9116 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9117 if (globals == NULL)
9118 return;
9119
84c08195
PB		 9120 /* If blx is available then exported Thumb symbols are OK and there is
9121 nothing to do. */
a4fd1a8e
PB		 9122 if (globals->use_blx)
9123 return;
9124
9125 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9126 link_info);
9127}
9128
47beaa6a
RS		 9129/* Reserve space for COUNT dynamic relocations in relocation selection
9130 SRELOC. */
9131
9132static void
9133elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9134 bfd_size_type count)
9135{
9136 struct elf32_arm_link_hash_table *htab;
9137
9138 htab = elf32_arm_hash_table (info);
9139 BFD_ASSERT (htab->root.dynamic_sections_created);
9140 if (sreloc == NULL)
9141 abort ();
9142 sreloc->size += RELOC_SIZE (htab) * count;
9143}
9144
34e77a92
RS		 9145/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9146 dynamic, the relocations should go in SRELOC, otherwise they should
9147 go in the special .rel.iplt section. */
9148
9149static void
9150elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9151 bfd_size_type count)
9152{
9153 struct elf32_arm_link_hash_table *htab;
9154
9155 htab = elf32_arm_hash_table (info);
9156 if (!htab->root.dynamic_sections_created)
9157 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9158 else
9159 {
9160 BFD_ASSERT (sreloc != NULL);
9161 sreloc->size += RELOC_SIZE (htab) * count;
9162 }
9163}
9164
47beaa6a
RS		 9165/* Add relocation REL to the end of relocation section SRELOC. */
9166
9167static void
9168elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9169 asection *sreloc, Elf_Internal_Rela *rel)
9170{
9171 bfd_byte *loc;
9172 struct elf32_arm_link_hash_table *htab;
9173
9174 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9175 if (!htab->root.dynamic_sections_created
9176 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9177 sreloc = htab->root.irelplt;
47beaa6a
RS		 9178 if (sreloc == NULL)
9179 abort ();
9180 loc = sreloc->contents;
9181 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9182 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9183 abort ();
9184 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9185}
9186
34e77a92
RS		 9187/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9188 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9189 to .plt. */
9190
9191static void
9192elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9193 bfd_boolean is_iplt_entry,
9194 union gotplt_union *root_plt,
9195 struct arm_plt_info *arm_plt)
9196{
9197 struct elf32_arm_link_hash_table *htab;
9198 asection *splt;
9199 asection *sgotplt;
9200
9201 htab = elf32_arm_hash_table (info);
9202
9203 if (is_iplt_entry)
9204 {
9205 splt = htab->root.iplt;
9206 sgotplt = htab->root.igotplt;
9207
99059e56
RM		 9208 /* NaCl uses a special first entry in .iplt too. */
9209 if (htab->nacl_p && splt->size == 0)
9210 splt->size += htab->plt_header_size;
9211
34e77a92
RS		 9212 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9213 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9214 }
9215 else
9216 {
9217 splt = htab->root.splt;
9218 sgotplt = htab->root.sgotplt;
9219
9220 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9221 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9222
9223 /* If this is the first .plt entry, make room for the special
9224 first entry. */
9225 if (splt->size == 0)
9226 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9227
9228 htab->next_tls_desc_index++;
34e77a92
RS		 9229 }
9230
9231 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9232 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9233 splt->size += PLT_THUMB_STUB_SIZE;
9234 root_plt->offset = splt->size;
9235 splt->size += htab->plt_entry_size;
9236
9237 if (!htab->symbian_p)
9238 {
9239 /* We also need to make an entry in the .got.plt section, which
9240 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9241 if (is_iplt_entry)
9242 arm_plt->got_offset = sgotplt->size;
9243 else
9244 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9245 sgotplt->size += 4;
9246 }
9247}
9248
b38cadfb
NC		 9249static bfd_vma
9250arm_movw_immediate (bfd_vma value)
9251{
9252 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9253}
9254
9255static bfd_vma
9256arm_movt_immediate (bfd_vma value)
9257{
9258 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9259}
9260
34e77a92
RS		 9261/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9262 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9263 Otherwise, DYNINDX is the index of the symbol in the dynamic
9264 symbol table and SYM_VALUE is undefined.
9265
9266 ROOT_PLT points to the offset of the PLT entry from the start of its
9267 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9268 bookkeeping information.
34e77a92 9269
57460bcf
NC		 9270 Returns FALSE if there was a problem. */
9271
9272static bfd_boolean
34e77a92
RS		 9273elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9274 union gotplt_union *root_plt,
9275 struct arm_plt_info *arm_plt,
9276 int dynindx, bfd_vma sym_value)
9277{
9278 struct elf32_arm_link_hash_table *htab;
9279 asection *sgot;
9280 asection *splt;
9281 asection *srel;
9282 bfd_byte *loc;
9283 bfd_vma plt_index;
9284 Elf_Internal_Rela rel;
9285 bfd_vma plt_header_size;
9286 bfd_vma got_header_size;
9287
9288 htab = elf32_arm_hash_table (info);
9289
9290 /* Pick the appropriate sections and sizes. */
9291 if (dynindx == -1)
9292 {
9293 splt = htab->root.iplt;
9294 sgot = htab->root.igotplt;
9295 srel = htab->root.irelplt;
9296
9297 /* There are no reserved entries in .igot.plt, and no special
9298 first entry in .iplt. */
9299 got_header_size = 0;
9300 plt_header_size = 0;
9301 }
9302 else
9303 {
9304 splt = htab->root.splt;
9305 sgot = htab->root.sgotplt;
9306 srel = htab->root.srelplt;
9307
9308 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9309 plt_header_size = htab->plt_header_size;
9310 }
9311 BFD_ASSERT (splt != NULL && srel != NULL);
9312
9313 /* Fill in the entry in the procedure linkage table. */
9314 if (htab->symbian_p)
9315 {
9316 BFD_ASSERT (dynindx >= 0);
9317 put_arm_insn (htab, output_bfd,
9318 elf32_arm_symbian_plt_entry[0],
9319 splt->contents + root_plt->offset);
9320 bfd_put_32 (output_bfd,
9321 elf32_arm_symbian_plt_entry[1],
9322 splt->contents + root_plt->offset + 4);
9323
9324 /* Fill in the entry in the .rel.plt section. */
9325 rel.r_offset = (splt->output_section->vma
9326 + splt->output_offset
9327 + root_plt->offset + 4);
9328 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9329
9330 /* Get the index in the procedure linkage table which
9331 corresponds to this symbol. This is the index of this symbol
9332 in all the symbols for which we are making plt entries. The
9333 first entry in the procedure linkage table is reserved. */
9334 plt_index = ((root_plt->offset - plt_header_size)
9335 / htab->plt_entry_size);
9336 }
9337 else
9338 {
9339 bfd_vma got_offset, got_address, plt_address;
9340 bfd_vma got_displacement, initial_got_entry;
9341 bfd_byte * ptr;
9342
9343 BFD_ASSERT (sgot != NULL);
9344
9345 /* Get the offset into the .(i)got.plt table of the entry that
9346 corresponds to this function. */
9347 got_offset = (arm_plt->got_offset & -2);
9348
9349 /* Get the index in the procedure linkage table which
9350 corresponds to this symbol. This is the index of this symbol
9351 in all the symbols for which we are making plt entries.
9352 After the reserved .got.plt entries, all symbols appear in
9353 the same order as in .plt. */
9354 plt_index = (got_offset - got_header_size) / 4;
9355
9356 /* Calculate the address of the GOT entry. */
9357 got_address = (sgot->output_section->vma
9358 + sgot->output_offset
9359 + got_offset);
9360
9361 /* ...and the address of the PLT entry. */
9362 plt_address = (splt->output_section->vma
9363 + splt->output_offset
9364 + root_plt->offset);
9365
9366 ptr = splt->contents + root_plt->offset;
0e1862bb 9367 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9368 {
9369 unsigned int i;
9370 bfd_vma val;
9371
9372 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9373 {
9374 val = elf32_arm_vxworks_shared_plt_entry[i];
9375 if (i == 2)
9376 val |= got_address - sgot->output_section->vma;
9377 if (i == 5)
9378 val |= plt_index * RELOC_SIZE (htab);
9379 if (i == 2 || i == 5)
9380 bfd_put_32 (output_bfd, val, ptr);
9381 else
9382 put_arm_insn (htab, output_bfd, val, ptr);
9383 }
9384 }
9385 else if (htab->vxworks_p)
9386 {
9387 unsigned int i;
9388 bfd_vma val;
9389
9390 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9391 {
9392 val = elf32_arm_vxworks_exec_plt_entry[i];
9393 if (i == 2)
9394 val |= got_address;
9395 if (i == 4)
9396 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9397 if (i == 5)
9398 val |= plt_index * RELOC_SIZE (htab);
9399 if (i == 2 || i == 5)
9400 bfd_put_32 (output_bfd, val, ptr);
9401 else
9402 put_arm_insn (htab, output_bfd, val, ptr);
9403 }
9404
9405 loc = (htab->srelplt2->contents
9406 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9407
9408 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9409 referencing the GOT for this PLT entry. */
9410 rel.r_offset = plt_address + 8;
9411 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9412 rel.r_addend = got_offset;
9413 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9414 loc += RELOC_SIZE (htab);
9415
9416 /* Create the R_ARM_ABS32 relocation referencing the
9417 beginning of the PLT for this GOT entry. */
9418 rel.r_offset = got_address;
9419 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9420 rel.r_addend = 0;
9421 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9422 }
b38cadfb
NC		 9423 else if (htab->nacl_p)
9424 {
9425 /* Calculate the displacement between the PLT slot and the
9426 common tail that's part of the special initial PLT slot. */
6034aab8 9427 int32_t tail_displacement
b38cadfb
NC		 9428 = ((splt->output_section->vma + splt->output_offset
9429 + ARM_NACL_PLT_TAIL_OFFSET)
9430 - (plt_address + htab->plt_entry_size + 4));
9431 BFD_ASSERT ((tail_displacement & 3) == 0);
9432 tail_displacement >>= 2;
9433
9434 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9435 || (-tail_displacement & 0xff000000) == 0);
9436
9437 /* Calculate the displacement between the PLT slot and the entry
9438 in the GOT. The offset accounts for the value produced by
9439 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9440 got_displacement = (got_address
99059e56 9441 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9442
9443 /* NaCl does not support interworking at all. */
9444 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9445
9446 put_arm_insn (htab, output_bfd,
9447 elf32_arm_nacl_plt_entry[0]
9448 | arm_movw_immediate (got_displacement),
9449 ptr + 0);
9450 put_arm_insn (htab, output_bfd,
9451 elf32_arm_nacl_plt_entry[1]
9452 | arm_movt_immediate (got_displacement),
9453 ptr + 4);
9454 put_arm_insn (htab, output_bfd,
9455 elf32_arm_nacl_plt_entry[2],
9456 ptr + 8);
9457 put_arm_insn (htab, output_bfd,
9458 elf32_arm_nacl_plt_entry[3]
9459 | (tail_displacement & 0x00ffffff),
9460 ptr + 12);
9461 }
57460bcf
NC		 9462 else if (using_thumb_only (htab))
9463 {
eed94f8f 9464 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9465 if (!using_thumb2 (htab))
eed94f8f
NC		 9466 {
9467 /* FIXME: We ought to be able to generate thumb-1 PLT
9468 instructions... */
9469 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9470 output_bfd);
9471 return FALSE;
9472 }
57460bcf 9473
eed94f8f
NC		 9474 /* Calculate the displacement between the PLT slot and the entry in
9475 the GOT. The 12-byte offset accounts for the value produced by
9476 adding to pc in the 3rd instruction of the PLT stub. */
9477 got_displacement = got_address - (plt_address + 12);
9478
9479 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9480 instead of 'put_thumb_insn'. */
9481 put_arm_insn (htab, output_bfd,
9482 elf32_thumb2_plt_entry[0]
9483 | ((got_displacement & 0x000000ff) << 16)
9484 | ((got_displacement & 0x00000700) << 20)
9485 | ((got_displacement & 0x00000800) >> 1)
9486 | ((got_displacement & 0x0000f000) >> 12),
9487 ptr + 0);
9488 put_arm_insn (htab, output_bfd,
9489 elf32_thumb2_plt_entry[1]
9490 | ((got_displacement & 0x00ff0000) )
9491 | ((got_displacement & 0x07000000) << 4)
9492 | ((got_displacement & 0x08000000) >> 17)
9493 | ((got_displacement & 0xf0000000) >> 28),
9494 ptr + 4);
9495 put_arm_insn (htab, output_bfd,
9496 elf32_thumb2_plt_entry[2],
9497 ptr + 8);
9498 put_arm_insn (htab, output_bfd,
9499 elf32_thumb2_plt_entry[3],
9500 ptr + 12);
57460bcf 9501 }
34e77a92
RS		 9502 else
9503 {
9504 /* Calculate the displacement between the PLT slot and the
9505 entry in the GOT. The eight-byte offset accounts for the
9506 value produced by adding to pc in the first instruction
9507 of the PLT stub. */
9508 got_displacement = got_address - (plt_address + 8);
9509
34e77a92
RS		 9510 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9511 {
9512 put_thumb_insn (htab, output_bfd,
9513 elf32_arm_plt_thumb_stub[0], ptr - 4);
9514 put_thumb_insn (htab, output_bfd,
9515 elf32_arm_plt_thumb_stub[1], ptr - 2);
9516 }
9517
1db37fe6
YG		 9518 if (!elf32_arm_use_long_plt_entry)
9519 {
9520 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9521
9522 put_arm_insn (htab, output_bfd,
9523 elf32_arm_plt_entry_short[0]
9524 | ((got_displacement & 0x0ff00000) >> 20),
9525 ptr + 0);
9526 put_arm_insn (htab, output_bfd,
9527 elf32_arm_plt_entry_short[1]
9528 | ((got_displacement & 0x000ff000) >> 12),
9529 ptr+ 4);
9530 put_arm_insn (htab, output_bfd,
9531 elf32_arm_plt_entry_short[2]
9532 | (got_displacement & 0x00000fff),
9533 ptr + 8);
34e77a92 9534#ifdef FOUR_WORD_PLT
1db37fe6 9535 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9536#endif
1db37fe6
YG		 9537 }
9538 else
9539 {
9540 put_arm_insn (htab, output_bfd,
9541 elf32_arm_plt_entry_long[0]
9542 | ((got_displacement & 0xf0000000) >> 28),
9543 ptr + 0);
9544 put_arm_insn (htab, output_bfd,
9545 elf32_arm_plt_entry_long[1]
9546 | ((got_displacement & 0x0ff00000) >> 20),
9547 ptr + 4);
9548 put_arm_insn (htab, output_bfd,
9549 elf32_arm_plt_entry_long[2]
9550 | ((got_displacement & 0x000ff000) >> 12),
9551 ptr+ 8);
9552 put_arm_insn (htab, output_bfd,
9553 elf32_arm_plt_entry_long[3]
9554 | (got_displacement & 0x00000fff),
9555 ptr + 12);
9556 }
34e77a92
RS		 9557 }
9558
9559 /* Fill in the entry in the .rel(a).(i)plt section. */
9560 rel.r_offset = got_address;
9561 rel.r_addend = 0;
9562 if (dynindx == -1)
9563 {
9564 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9565 The dynamic linker or static executable then calls SYM_VALUE
9566 to determine the correct run-time value of the .igot.plt entry. */
9567 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9568 initial_got_entry = sym_value;
9569 }
9570 else
9571 {
9572 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9573 initial_got_entry = (splt->output_section->vma
9574 + splt->output_offset);
9575 }
9576
9577 /* Fill in the entry in the global offset table. */
9578 bfd_put_32 (output_bfd, initial_got_entry,
9579 sgot->contents + got_offset);
9580 }
9581
aba8c3de
WN		 9582 if (dynindx == -1)
9583 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9584 else
9585 {
9586 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9587 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9588 }
57460bcf
NC		 9589
9590 return TRUE;
34e77a92
RS		 9591}
9592
eb043451
PB		 9593/* Some relocations map to different relocations depending on the
9594 target. Return the real relocation. */
8029a119 9595
eb043451
PB		 9596static int
9597arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9598 int r_type)
9599{
9600 switch (r_type)
9601 {
9602 case R_ARM_TARGET1:
9603 if (globals->target1_is_rel)
9604 return R_ARM_REL32;
9605 else
9606 return R_ARM_ABS32;
9607
9608 case R_ARM_TARGET2:
9609 return globals->target2_reloc;
9610
9611 default:
9612 return r_type;
9613 }
9614}
eb043451 9615
ba93b8ac
DJ		 9616/* Return the base VMA address which should be subtracted from real addresses
9617 when resolving @dtpoff relocation.
9618 This is PT_TLS segment p_vaddr. */
9619
9620static bfd_vma
9621dtpoff_base (struct bfd_link_info *info)
9622{
9623 /* If tls_sec is NULL, we should have signalled an error already. */
9624 if (elf_hash_table (info)->tls_sec == NULL)
9625 return 0;
9626 return elf_hash_table (info)->tls_sec->vma;
9627}
9628
9629/* Return the relocation value for @tpoff relocation
9630 if STT_TLS virtual address is ADDRESS. */
9631
9632static bfd_vma
9633tpoff (struct bfd_link_info *info, bfd_vma address)
9634{
9635 struct elf_link_hash_table *htab = elf_hash_table (info);
9636 bfd_vma base;
9637
9638 /* If tls_sec is NULL, we should have signalled an error already. */
9639 if (htab->tls_sec == NULL)
9640 return 0;
9641 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9642 return address - htab->tls_sec->vma + base;
9643}
9644
00a97672
RS		 9645/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9646 VALUE is the relocation value. */
9647
9648static bfd_reloc_status_type
9649elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9650{
9651 if (value > 0xfff)
9652 return bfd_reloc_overflow;
9653
9654 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9655 bfd_put_32 (abfd, value, data);
9656 return bfd_reloc_ok;
9657}
9658
0855e32b
NS		 9659/* Handle TLS relaxations. Relaxing is possible for symbols that use
9660 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9661 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9662
9663 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9664 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9665 case of error.
9666
9667 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9668 the pre-relaxed code. It would be nice if the relocs were updated
9669 to match the optimization. */
0855e32b 9670
b38cadfb 9671static bfd_reloc_status_type
0855e32b 9672elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9673 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9674 Elf_Internal_Rela *rel, unsigned long is_local)
9675{
9676 unsigned long insn;
b38cadfb 9677
0855e32b
NS		 9678 switch (ELF32_R_TYPE (rel->r_info))
9679 {
9680 default:
9681 return bfd_reloc_notsupported;
b38cadfb 9682
0855e32b
NS		 9683 case R_ARM_TLS_GOTDESC:
9684 if (is_local)
9685 insn = 0;
9686 else
9687 {
9688 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9689 if (insn & 1)
9690 insn -= 5; /* THUMB */
9691 else
9692 insn -= 8; /* ARM */
9693 }
9694 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9695 return bfd_reloc_continue;
9696
9697 case R_ARM_THM_TLS_DESCSEQ:
9698 /* Thumb insn. */
9699 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9700 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9701 {
9702 if (is_local)
9703 /* nop */
9704 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9705 }
9706 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9707 {
9708 if (is_local)
9709 /* nop */
9710 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9711 else
9712 /* ldr rx,[ry] */
9713 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9714 }
9715 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9716 {
9717 if (is_local)
9718 /* nop */
9719 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9720 else
9721 /* mov r0, rx */
9722 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9723 contents + rel->r_offset);
9724 }
9725 else
9726 {
9727 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9728 /* It's a 32 bit instruction, fetch the rest of it for
9729 error generation. */
9730 insn = (insn << 16)
9731 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9732 _bfd_error_handler
695344c0
NC		 9733 /* xgettext:c-format */
9734 (_("%B(%A+0x%lx): unexpected Thumb instruction '0x%x' in TLS trampoline"),
0855e32b
NS		 9735 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9736 return bfd_reloc_notsupported;
9737 }
9738 break;
b38cadfb 9739
0855e32b
NS		 9740 case R_ARM_TLS_DESCSEQ:
9741 /* arm insn. */
9742 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9743 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9744 {
9745 if (is_local)
9746 /* mov rx, ry */
9747 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9748 contents + rel->r_offset);
9749 }
9750 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9751 {
9752 if (is_local)
9753 /* nop */
9754 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9755 else
9756 /* ldr rx,[ry] */
9757 bfd_put_32 (input_bfd, insn & 0xfffff000,
9758 contents + rel->r_offset);
9759 }
9760 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9761 {
9762 if (is_local)
9763 /* nop */
9764 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9765 else
9766 /* mov r0, rx */
9767 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9768 contents + rel->r_offset);
9769 }
9770 else
9771 {
4eca0228 9772 _bfd_error_handler
695344c0
NC		 9773 /* xgettext:c-format */
9774 (_("%B(%A+0x%lx): unexpected ARM instruction '0x%x' in TLS trampoline"),
0855e32b
NS		 9775 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9776 return bfd_reloc_notsupported;
9777 }
9778 break;
9779
9780 case R_ARM_TLS_CALL:
9781 /* GD->IE relaxation, turn the instruction into 'nop' or
9782 'ldr r0, [pc,r0]' */
9783 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9784 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9785 break;
b38cadfb 9786
0855e32b 9787 case R_ARM_THM_TLS_CALL:
6a631e86 9788 /* GD->IE relaxation. */
0855e32b
NS		 9789 if (!is_local)
9790 /* add r0,pc; ldr r0, [r0] */
9791 insn = 0x44786800;
60a019a0 9792 else if (using_thumb2 (globals))
0855e32b
NS		 9793 /* nop.w */
9794 insn = 0xf3af8000;
9795 else
9796 /* nop; nop */
9797 insn = 0xbf00bf00;
b38cadfb 9798
0855e32b
NS		 9799 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9800 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9801 break;
9802 }
9803 return bfd_reloc_ok;
9804}
9805
4962c51a
MS		 9806/* For a given value of n, calculate the value of G_n as required to
9807 deal with group relocations. We return it in the form of an
9808 encoded constant-and-rotation, together with the final residual. If n is
9809 specified as less than zero, then final_residual is filled with the
9810 input value and no further action is performed. */
9811
9812static bfd_vma
9813calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9814{
9815 int current_n;
9816 bfd_vma g_n;
9817 bfd_vma encoded_g_n = 0;
9818 bfd_vma residual = value; /* Also known as Y_n. */
9819
9820 for (current_n = 0; current_n <= n; current_n++)
9821 {
9822 int shift;
9823
9824 /* Calculate which part of the value to mask. */
9825 if (residual == 0)
99059e56 9826 shift = 0;
4962c51a 9827 else
99059e56
RM		 9828 {
9829 int msb;
9830
9831 /* Determine the most significant bit in the residual and
9832 align the resulting value to a 2-bit boundary. */
9833 for (msb = 30; msb >= 0; msb -= 2)
9834 if (residual & (3 << msb))
9835 break;
9836
9837 /* The desired shift is now (msb - 6), or zero, whichever
9838 is the greater. */
9839 shift = msb - 6;
9840 if (shift < 0)
9841 shift = 0;
9842 }
4962c51a
MS		 9843
9844 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9845 g_n = residual & (0xff << shift);
9846 encoded_g_n = (g_n >> shift)
99059e56 9847 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9848
9849 /* Calculate the residual for the next time around. */
9850 residual &= ~g_n;
9851 }
9852
9853 *final_residual = residual;
9854
9855 return encoded_g_n;
9856}
9857
9858/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9859 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9860
4962c51a 9861static int
906e58ca 9862identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9863{
9864 int opcode = insn & 0x1e00000;
9865
9866 if (opcode == 1 << 23) /* ADD */
9867 return 1;
9868
9869 if (opcode == 1 << 22) /* SUB */
9870 return -1;
9871
9872 return 0;
9873}
9874
252b5132 9875/* Perform a relocation as part of a final link. */
9b485d32 9876
252b5132 9877static bfd_reloc_status_type
57e8b36a
NC		 9878elf32_arm_final_link_relocate (reloc_howto_type * howto,
9879 bfd * input_bfd,
9880 bfd * output_bfd,
9881 asection * input_section,
9882 bfd_byte * contents,
9883 Elf_Internal_Rela * rel,
9884 bfd_vma value,
9885 struct bfd_link_info * info,
9886 asection * sym_sec,
9887 const char * sym_name,
34e77a92
RS		 9888 unsigned char st_type,
9889 enum arm_st_branch_type branch_type,
0945cdfd 9890 struct elf_link_hash_entry * h,
f2a9dd69 9891 bfd_boolean * unresolved_reloc_p,
8029a119 9892 char ** error_message)
252b5132
RH		 9893{
9894 unsigned long r_type = howto->type;
9895 unsigned long r_symndx;
9896 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9897 bfd_vma * local_got_offsets;
0855e32b 9898 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9899 asection * sgot;
9900 asection * splt;
252b5132 9901 asection * sreloc = NULL;
362d30a1 9902 asection * srelgot;
252b5132 9903 bfd_vma addend;
ba96a88f 9904 bfd_signed_vma signed_addend;
34e77a92
RS		 9905 unsigned char dynreloc_st_type;
9906 bfd_vma dynreloc_value;
ba96a88f 9907 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9908 struct elf32_arm_link_hash_entry *eh;
9909 union gotplt_union *root_plt;
9910 struct arm_plt_info *arm_plt;
9911 bfd_vma plt_offset;
9912 bfd_vma gotplt_offset;
9913 bfd_boolean has_iplt_entry;
f21f3fe0 9914
9c504268 9915 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9916 if (globals == NULL)
9917 return bfd_reloc_notsupported;
9c504268 9918
0ffa91dd
NC		 9919 BFD_ASSERT (is_arm_elf (input_bfd));
9920
9921 /* Some relocation types map to different relocations depending on the
9c504268 9922 target. We pick the right one here. */
eb043451 9923 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9924
9925 /* It is possible to have linker relaxations on some TLS access
9926 models. Update our information here. */
9927 r_type = elf32_arm_tls_transition (info, r_type, h);
9928
eb043451
PB		 9929 if (r_type != howto->type)
9930 howto = elf32_arm_howto_from_type (r_type);
9c504268 9931
34e77a92 9932 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9933 sgot = globals->root.sgot;
252b5132 9934 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9935 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9936
34e77a92
RS		 9937 if (globals->root.dynamic_sections_created)
9938 srelgot = globals->root.srelgot;
9939 else
9940 srelgot = NULL;
9941
252b5132
RH		 9942 r_symndx = ELF32_R_SYM (rel->r_info);
9943
4e7fd91e 9944 if (globals->use_rel)
ba96a88f 9945 {
4e7fd91e
PB		 9946 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9947
9948 if (addend & ((howto->src_mask + 1) >> 1))
9949 {
9950 signed_addend = -1;
9951 signed_addend &= ~ howto->src_mask;
9952 signed_addend |= addend;
9953 }
9954 else
9955 signed_addend = addend;
ba96a88f
NC		 9956 }
9957 else
4e7fd91e 9958 addend = signed_addend = rel->r_addend;
f21f3fe0 9959
39f21624
NC		 9960 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9961 are resolving a function call relocation. */
9962 if (using_thumb_only (globals)
9963 && (r_type == R_ARM_THM_CALL
9964 || r_type == R_ARM_THM_JUMP24)
9965 && branch_type == ST_BRANCH_TO_ARM)
9966 branch_type = ST_BRANCH_TO_THUMB;
9967
34e77a92
RS		 9968 /* Record the symbol information that should be used in dynamic
9969 relocations. */
9970 dynreloc_st_type = st_type;
9971 dynreloc_value = value;
9972 if (branch_type == ST_BRANCH_TO_THUMB)
9973 dynreloc_value |= 1;
9974
9975 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9976 VALUE appropriately for relocations that we resolve at link time. */
9977 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9978 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9979 &arm_plt)
34e77a92
RS		 9980 && root_plt->offset != (bfd_vma) -1)
9981 {
9982 plt_offset = root_plt->offset;
9983 gotplt_offset = arm_plt->got_offset;
9984
9985 if (h == NULL || eh->is_iplt)
9986 {
9987 has_iplt_entry = TRUE;
9988 splt = globals->root.iplt;
9989
9990 /* Populate .iplt entries here, because not all of them will
9991 be seen by finish_dynamic_symbol. The lower bit is set if
9992 we have already populated the entry. */
9993 if (plt_offset & 1)
9994 plt_offset--;
9995 else
9996 {
57460bcf
NC		 9997 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9998 -1, dynreloc_value))
9999 root_plt->offset |= 1;
10000 else
10001 return bfd_reloc_notsupported;
34e77a92
RS		 10002 }
10003
10004 /* Static relocations always resolve to the .iplt entry. */
10005 st_type = STT_FUNC;
10006 value = (splt->output_section->vma
10007 + splt->output_offset
10008 + plt_offset);
10009 branch_type = ST_BRANCH_TO_ARM;
10010
10011 /* If there are non-call relocations that resolve to the .iplt
10012 entry, then all dynamic ones must too. */
10013 if (arm_plt->noncall_refcount != 0)
10014 {
10015 dynreloc_st_type = st_type;
10016 dynreloc_value = value;
10017 }
10018 }
10019 else
10020 /* We populate the .plt entry in finish_dynamic_symbol. */
10021 splt = globals->root.splt;
10022 }
10023 else
10024 {
10025 splt = NULL;
10026 plt_offset = (bfd_vma) -1;
10027 gotplt_offset = (bfd_vma) -1;
10028 }
10029
252b5132
RH		 10030 switch (r_type)
10031 {
10032 case R_ARM_NONE:
28a094c2
DJ		 10033 /* We don't need to find a value for this symbol. It's just a
10034 marker. */
10035 *unresolved_reloc_p = FALSE;
252b5132
RH		 10036 return bfd_reloc_ok;
10037
00a97672
RS		 10038 case R_ARM_ABS12:
10039 if (!globals->vxworks_p)
10040 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10041 /* Fall through. */
00a97672 10042
252b5132
RH		 10043 case R_ARM_PC24:
10044 case R_ARM_ABS32:
bb224fc3 10045 case R_ARM_ABS32_NOI:
252b5132 10046 case R_ARM_REL32:
bb224fc3 10047 case R_ARM_REL32_NOI:
5b5bb741
PB		 10048 case R_ARM_CALL:
10049 case R_ARM_JUMP24:
dfc5f959 10050 case R_ARM_XPC25:
eb043451 10051 case R_ARM_PREL31:
7359ea65 10052 case R_ARM_PLT32:
7359ea65
DJ		 10053 /* Handle relocations which should use the PLT entry. ABS32/REL32
10054 will use the symbol's value, which may point to a PLT entry, but we
10055 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10056 branches in this object should go to it, except if the PLT is too
10057 far away, in which case a long branch stub should be inserted. */
bb224fc3 10058 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10059 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10060 && r_type != R_ARM_CALL
10061 && r_type != R_ARM_JUMP24
10062 && r_type != R_ARM_PLT32)
34e77a92 10063 && plt_offset != (bfd_vma) -1)
7359ea65 10064 {
34e77a92
RS		 10065 /* If we've created a .plt section, and assigned a PLT entry
10066 to this function, it must either be a STT_GNU_IFUNC reference
10067 or not be known to bind locally. In other cases, we should
10068 have cleared the PLT entry by now. */
10069 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10070
10071 value = (splt->output_section->vma
10072 + splt->output_offset
34e77a92 10073 + plt_offset);
0945cdfd 10074 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10075 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10076 contents, rel->r_offset, value,
00a97672 10077 rel->r_addend);
7359ea65
DJ		 10078 }
10079
67687978
PB		 10080 /* When generating a shared object or relocatable executable, these
10081 relocations are copied into the output file to be resolved at
10082 run time. */
0e1862bb
L		 10083 if ((bfd_link_pic (info)
10084 || globals->root.is_relocatable_executable)
7359ea65 10085 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10086 && !(globals->vxworks_p
3348747a
NS		 10087 && strcmp (input_section->output_section->name,
10088 ".tls_vars") == 0)
bb224fc3 10089 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10090 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10091 && !(input_bfd == globals->stub_bfd
10092 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 10093 && (h == NULL
10094 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10095 || h->root.type != bfd_link_hash_undefweak)
10096 && r_type != R_ARM_PC24
5b5bb741
PB		 10097 && r_type != R_ARM_CALL
10098 && r_type != R_ARM_JUMP24
ee06dc07 10099 && r_type != R_ARM_PREL31
7359ea65 10100 && r_type != R_ARM_PLT32)
252b5132 10101 {
947216bf 10102 Elf_Internal_Rela outrel;
b34976b6 10103 bfd_boolean skip, relocate;
f21f3fe0 10104
52db4ec2
JW		 10105 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10106 && !h->def_regular)
10107 {
10108 char *v = _("shared object");
10109
0e1862bb 10110 if (bfd_link_executable (info))
52db4ec2
JW		 10111 v = _("PIE executable");
10112
4eca0228 10113 _bfd_error_handler
52db4ec2
JW		 10114 (_("%B: relocation %s against external or undefined symbol `%s'"
10115 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10116 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10117 return bfd_reloc_notsupported;
10118 }
10119
0945cdfd
DJ		 10120 *unresolved_reloc_p = FALSE;
10121
34e77a92 10122 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10123 {
83bac4b0
NC		 10124 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10125 ! globals->use_rel);
f21f3fe0 10126
83bac4b0 10127 if (sreloc == NULL)
252b5132 10128 return bfd_reloc_notsupported;
252b5132 10129 }
f21f3fe0 10130
b34976b6
AM		 10131 skip = FALSE;
10132 relocate = FALSE;
f21f3fe0 10133
00a97672 10134 outrel.r_addend = addend;
c629eae0
JJ		 10135 outrel.r_offset =
10136 _bfd_elf_section_offset (output_bfd, info, input_section,
10137 rel->r_offset);
10138 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10139 skip = TRUE;
0bb2d96a 10140 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10141 skip = TRUE, relocate = TRUE;
252b5132
RH		 10142 outrel.r_offset += (input_section->output_section->vma
10143 + input_section->output_offset);
f21f3fe0 10144
252b5132 10145 if (skip)
0bb2d96a 10146 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10147 else if (h != NULL
10148 && h->dynindx != -1
0e1862bb 10149 && (!bfd_link_pic (info)
a496fbc8 10150 || !SYMBOLIC_BIND (info, h)
f5385ebf 10151 || !h->def_regular))
5e681ec4 10152 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10153 else
10154 {
a16385dc
MM		 10155 int symbol;
10156
5e681ec4 10157 /* This symbol is local, or marked to become local. */
34e77a92 10158 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10159 if (globals->symbian_p)
6366ff1e 10160 {
74541ad4
AM		 10161 asection *osec;
10162
6366ff1e
MM		 10163 /* On Symbian OS, the data segment and text segement
10164 can be relocated independently. Therefore, we
10165 must indicate the segment to which this
10166 relocation is relative. The BPABI allows us to
10167 use any symbol in the right segment; we just use
10168 the section symbol as it is convenient. (We
10169 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10170 will not appear in the dynamic symbol table.)
10171
10172 Note that the dynamic linker ignores the section
10173 symbol value, so we don't subtract osec->vma
10174 from the emitted reloc addend. */
10dbd1f3 10175 if (sym_sec)
74541ad4 10176 osec = sym_sec->output_section;
10dbd1f3 10177 else
74541ad4
AM		 10178 osec = input_section->output_section;
10179 symbol = elf_section_data (osec)->dynindx;
10180 if (symbol == 0)
10181 {
10182 struct elf_link_hash_table *htab = elf_hash_table (info);
10183
10184 if ((osec->flags & SEC_READONLY) == 0
10185 && htab->data_index_section != NULL)
10186 osec = htab->data_index_section;
10187 else
10188 osec = htab->text_index_section;
10189 symbol = elf_section_data (osec)->dynindx;
10190 }
6366ff1e
MM		 10191 BFD_ASSERT (symbol != 0);
10192 }
a16385dc
MM		 10193 else
10194 /* On SVR4-ish systems, the dynamic loader cannot
10195 relocate the text and data segments independently,
10196 so the symbol does not matter. */
10197 symbol = 0;
34e77a92
RS		 10198 if (dynreloc_st_type == STT_GNU_IFUNC)
10199 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10200 to the .iplt entry. Instead, every non-call reference
10201 must use an R_ARM_IRELATIVE relocation to obtain the
10202 correct run-time address. */
10203 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10204 else
10205 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10206 if (globals->use_rel)
10207 relocate = TRUE;
10208 else
34e77a92 10209 outrel.r_addend += dynreloc_value;
252b5132 10210 }
f21f3fe0 10211
47beaa6a 10212 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10213
f21f3fe0 10214 /* If this reloc is against an external symbol, we do not want to
252b5132 10215 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10216 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10217 if (! relocate)
10218 return bfd_reloc_ok;
9a5aca8c 10219
f21f3fe0 10220 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10221 contents, rel->r_offset,
10222 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10223 }
10224 else switch (r_type)
10225 {
00a97672
RS		 10226 case R_ARM_ABS12:
10227 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10228
dfc5f959 10229 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10230 case R_ARM_CALL:
10231 case R_ARM_JUMP24:
8029a119 10232 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10233 case R_ARM_PLT32:
906e58ca 10234 {
906e58ca
NC		 10235 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10236
dfc5f959 10237 if (r_type == R_ARM_XPC25)
252b5132 10238 {
dfc5f959
NC		 10239 /* Check for Arm calling Arm function. */
10240 /* FIXME: Should we translate the instruction into a BL
10241 instruction instead ? */
35fc36a8 10242 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10243 _bfd_error_handler
d003868e
AM		 10244 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
10245 input_bfd,
10246 h ? h->root.root.string : "(local)");
dfc5f959 10247 }
155d87d7 10248 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10249 {
10250 /* Check for Arm calling Thumb function. */
35fc36a8 10251 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10252 {
f2a9dd69
DJ		 10253 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10254 output_bfd, input_section,
10255 hit_data, sym_sec, rel->r_offset,
10256 signed_addend, value,
10257 error_message))
10258 return bfd_reloc_ok;
10259 else
10260 return bfd_reloc_dangerous;
dfc5f959 10261 }
252b5132 10262 }
ba96a88f 10263
906e58ca 10264 /* Check if a stub has to be inserted because the
8029a119 10265 destination is too far or we are changing mode. */
155d87d7
CL		 10266 if ( r_type == R_ARM_CALL
10267 || r_type == R_ARM_JUMP24
10268 || r_type == R_ARM_PLT32)
906e58ca 10269 {
fe33d2fa
CL		 10270 enum elf32_arm_stub_type stub_type = arm_stub_none;
10271 struct elf32_arm_link_hash_entry *hash;
10272
10273 hash = (struct elf32_arm_link_hash_entry *) h;
10274 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10275 st_type, &branch_type,
10276 hash, value, sym_sec,
fe33d2fa 10277 input_bfd, sym_name);
5fa9e92f 10278
fe33d2fa 10279 if (stub_type != arm_stub_none)
906e58ca
NC		 10280 {
10281 /* The target is out of reach, so redirect the
10282 branch to the local stub for this function. */
906e58ca
NC		 10283 stub_entry = elf32_arm_get_stub_entry (input_section,
10284 sym_sec, h,
fe33d2fa
CL		 10285 rel, globals,
10286 stub_type);
9cd3e4e5
NC		 10287 {
10288 if (stub_entry != NULL)
10289 value = (stub_entry->stub_offset
10290 + stub_entry->stub_sec->output_offset
10291 + stub_entry->stub_sec->output_section->vma);
10292
10293 if (plt_offset != (bfd_vma) -1)
10294 *unresolved_reloc_p = FALSE;
10295 }
906e58ca 10296 }
fe33d2fa
CL		 10297 else
10298 {
10299 /* If the call goes through a PLT entry, make sure to
10300 check distance to the right destination address. */
34e77a92 10301 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10302 {
10303 value = (splt->output_section->vma
10304 + splt->output_offset
34e77a92 10305 + plt_offset);
fe33d2fa
CL		 10306 *unresolved_reloc_p = FALSE;
10307 /* The PLT entry is in ARM mode, regardless of the
10308 target function. */
35fc36a8 10309 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10310 }
10311 }
906e58ca
NC		 10312 }
10313
dea514f5
PB		 10314 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10315 where:
10316 S is the address of the symbol in the relocation.
10317 P is address of the instruction being relocated.
10318 A is the addend (extracted from the instruction) in bytes.
10319
10320 S is held in 'value'.
10321 P is the base address of the section containing the
10322 instruction plus the offset of the reloc into that
10323 section, ie:
10324 (input_section->output_section->vma +
10325 input_section->output_offset +
10326 rel->r_offset).
10327 A is the addend, converted into bytes, ie:
10328 (signed_addend * 4)
10329
10330 Note: None of these operations have knowledge of the pipeline
10331 size of the processor, thus it is up to the assembler to
10332 encode this information into the addend. */
10333 value -= (input_section->output_section->vma
10334 + input_section->output_offset);
10335 value -= rel->r_offset;
4e7fd91e
PB		 10336 if (globals->use_rel)
10337 value += (signed_addend << howto->size);
10338 else
10339 /* RELA addends do not have to be adjusted by howto->size. */
10340 value += signed_addend;
23080146 10341
dcb5e6e6
NC		 10342 signed_addend = value;
10343 signed_addend >>= howto->rightshift;
9a5aca8c 10344
5ab79981 10345 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10346 the next instruction unless a PLT entry will be created.
77b4f08f 10347 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10348 The jump to the next instruction is optimized as a NOP depending
10349 on the architecture. */
ffcb4889 10350 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10351 && plt_offset == (bfd_vma) -1)
77b4f08f 10352 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10353 {
cd1dac3d
DG		 10354 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10355
10356 if (arch_has_arm_nop (globals))
10357 value |= 0x0320f000;
10358 else
10359 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10360 }
10361 else
59f2c4e7 10362 {
9b485d32 10363 /* Perform a signed range check. */
dcb5e6e6 10364 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10365 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10366 return bfd_reloc_overflow;
9a5aca8c 10367
5ab79981 10368 addend = (value & 2);
39b41c9c 10369
5ab79981
PB		 10370 value = (signed_addend & howto->dst_mask)
10371 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10372
5ab79981
PB		 10373 if (r_type == R_ARM_CALL)
10374 {
155d87d7 10375 /* Set the H bit in the BLX instruction. */
35fc36a8 10376 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10377 {
10378 if (addend)
10379 value |= (1 << 24);
10380 else
10381 value &= ~(bfd_vma)(1 << 24);
10382 }
10383
5ab79981 10384 /* Select the correct instruction (BL or BLX). */
906e58ca 10385 /* Only if we are not handling a BL to a stub. In this
8029a119 10386 case, mode switching is performed by the stub. */
35fc36a8 10387 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10388 value |= (1 << 28);
63e1a0fc 10389 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10390 {
10391 value &= ~(bfd_vma)(1 << 28);
10392 value |= (1 << 24);
10393 }
39b41c9c
PB		 10394 }
10395 }
906e58ca 10396 }
252b5132 10397 break;
f21f3fe0 10398
252b5132
RH		 10399 case R_ARM_ABS32:
10400 value += addend;
35fc36a8 10401 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10402 value |= 1;
10403 break;
f21f3fe0 10404
bb224fc3
MS		 10405 case R_ARM_ABS32_NOI:
10406 value += addend;
10407 break;
10408
252b5132 10409 case R_ARM_REL32:
a8bc6c78 10410 value += addend;
35fc36a8 10411 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10412 value |= 1;
252b5132 10413 value -= (input_section->output_section->vma
62efb346 10414 + input_section->output_offset + rel->r_offset);
252b5132 10415 break;
eb043451 10416
bb224fc3
MS		 10417 case R_ARM_REL32_NOI:
10418 value += addend;
10419 value -= (input_section->output_section->vma
10420 + input_section->output_offset + rel->r_offset);
10421 break;
10422
eb043451
PB		 10423 case R_ARM_PREL31:
10424 value -= (input_section->output_section->vma
10425 + input_section->output_offset + rel->r_offset);
10426 value += signed_addend;
10427 if (! h || h->root.type != bfd_link_hash_undefweak)
10428 {
8029a119 10429 /* Check for overflow. */
eb043451
PB		 10430 if ((value ^ (value >> 1)) & (1 << 30))
10431 return bfd_reloc_overflow;
10432 }
10433 value &= 0x7fffffff;
10434 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10435 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10436 value |= 1;
10437 break;
252b5132 10438 }
f21f3fe0 10439
252b5132
RH		 10440 bfd_put_32 (input_bfd, value, hit_data);
10441 return bfd_reloc_ok;
10442
10443 case R_ARM_ABS8:
fd0fd00c
MJ		 10444 /* PR 16202: Refectch the addend using the correct size. */
10445 if (globals->use_rel)
10446 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10447 value += addend;
4e67d4ca
DG		 10448
10449 /* There is no way to tell whether the user intended to use a signed or
10450 unsigned addend. When checking for overflow we accept either,
10451 as specified by the AAELF. */
10452 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10453 return bfd_reloc_overflow;
10454
10455 bfd_put_8 (input_bfd, value, hit_data);
10456 return bfd_reloc_ok;
10457
10458 case R_ARM_ABS16:
fd0fd00c
MJ		 10459 /* PR 16202: Refectch the addend using the correct size. */
10460 if (globals->use_rel)
10461 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10462 value += addend;
10463
4e67d4ca
DG		 10464 /* See comment for R_ARM_ABS8. */
10465 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10466 return bfd_reloc_overflow;
10467
10468 bfd_put_16 (input_bfd, value, hit_data);
10469 return bfd_reloc_ok;
10470
252b5132 10471 case R_ARM_THM_ABS5:
9b485d32 10472 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10473 if (globals->use_rel)
10474 {
10475 /* Need to refetch addend. */
10476 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10477 /* ??? Need to determine shift amount from operand size. */
10478 addend >>= howto->rightshift;
10479 }
252b5132
RH		 10480 value += addend;
10481
10482 /* ??? Isn't value unsigned? */
10483 if ((long) value > 0x1f || (long) value < -0x10)
10484 return bfd_reloc_overflow;
10485
10486 /* ??? Value needs to be properly shifted into place first. */
10487 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10488 bfd_put_16 (input_bfd, value, hit_data);
10489 return bfd_reloc_ok;
10490
2cab6cc3
MS		 10491 case R_ARM_THM_ALU_PREL_11_0:
10492 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10493 {
10494 bfd_vma insn;
10495 bfd_signed_vma relocation;
10496
10497 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10498 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10499
99059e56
RM		 10500 if (globals->use_rel)
10501 {
10502 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10503 | ((insn & (1 << 26)) >> 15);
10504 if (insn & 0xf00000)
10505 signed_addend = -signed_addend;
10506 }
2cab6cc3
MS		 10507
10508 relocation = value + signed_addend;
79f08007 10509 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10510 + input_section->output_offset
10511 + rel->r_offset);
2cab6cc3 10512
b6518b38 10513 value = relocation;
2cab6cc3 10514
99059e56
RM		 10515 if (value >= 0x1000)
10516 return bfd_reloc_overflow;
2cab6cc3
MS		 10517
10518 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10519 | ((value & 0x700) << 4)
10520 | ((value & 0x800) << 15);
10521 if (relocation < 0)
10522 insn |= 0xa00000;
2cab6cc3
MS		 10523
10524 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10525 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10526
99059e56 10527 return bfd_reloc_ok;
2cab6cc3
MS		 10528 }
10529
e1ec24c6
NC		 10530 case R_ARM_THM_PC8:
10531 /* PR 10073: This reloc is not generated by the GNU toolchain,
10532 but it is supported for compatibility with third party libraries
10533 generated by other compilers, specifically the ARM/IAR. */
10534 {
10535 bfd_vma insn;
10536 bfd_signed_vma relocation;
10537
10538 insn = bfd_get_16 (input_bfd, hit_data);
10539
99059e56 10540 if (globals->use_rel)
79f08007 10541 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10542
10543 relocation = value + addend;
79f08007 10544 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10545 + input_section->output_offset
10546 + rel->r_offset);
e1ec24c6 10547
b6518b38 10548 value = relocation;
e1ec24c6
NC		 10549
10550 /* We do not check for overflow of this reloc. Although strictly
10551 speaking this is incorrect, it appears to be necessary in order
10552 to work with IAR generated relocs. Since GCC and GAS do not
10553 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10554 a problem for them. */
10555 value &= 0x3fc;
10556
10557 insn = (insn & 0xff00) | (value >> 2);
10558
10559 bfd_put_16 (input_bfd, insn, hit_data);
10560
99059e56 10561 return bfd_reloc_ok;
e1ec24c6
NC		 10562 }
10563
2cab6cc3
MS		 10564 case R_ARM_THM_PC12:
10565 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10566 {
10567 bfd_vma insn;
10568 bfd_signed_vma relocation;
10569
10570 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10571 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10572
99059e56
RM		 10573 if (globals->use_rel)
10574 {
10575 signed_addend = insn & 0xfff;
10576 if (!(insn & (1 << 23)))
10577 signed_addend = -signed_addend;
10578 }
2cab6cc3
MS		 10579
10580 relocation = value + signed_addend;
79f08007 10581 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10582 + input_section->output_offset
10583 + rel->r_offset);
2cab6cc3 10584
b6518b38 10585 value = relocation;
2cab6cc3 10586
99059e56
RM		 10587 if (value >= 0x1000)
10588 return bfd_reloc_overflow;
2cab6cc3
MS		 10589
10590 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10591 if (relocation >= 0)
10592 insn |= (1 << 23);
2cab6cc3
MS		 10593
10594 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10595 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10596
99059e56 10597 return bfd_reloc_ok;
2cab6cc3
MS		 10598 }
10599
dfc5f959 10600 case R_ARM_THM_XPC22:
c19d1205 10601 case R_ARM_THM_CALL:
bd97cb95 10602 case R_ARM_THM_JUMP24:
dfc5f959 10603 /* Thumb BL (branch long instruction). */
252b5132 10604 {
b34976b6 10605 bfd_vma relocation;
99059e56 10606 bfd_vma reloc_sign;
b34976b6
AM		 10607 bfd_boolean overflow = FALSE;
10608 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10609 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10610 bfd_signed_vma reloc_signed_max;
10611 bfd_signed_vma reloc_signed_min;
b34976b6 10612 bfd_vma check;
252b5132 10613 bfd_signed_vma signed_check;
e95de063 10614 int bitsize;
cd1dac3d 10615 const int thumb2 = using_thumb2 (globals);
5e866f5a 10616 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10617
5ab79981 10618 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10619 the next instruction unless a PLT entry will be created.
10620 The jump to the next instruction is optimized as a NOP.W for
10621 Thumb-2 enabled architectures. */
19540007 10622 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10623 && plt_offset == (bfd_vma) -1)
5ab79981 10624 {
60a019a0 10625 if (thumb2)
cd1dac3d
DG		 10626 {
10627 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10628 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10629 }
10630 else
10631 {
10632 bfd_put_16 (input_bfd, 0xe000, hit_data);
10633 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10634 }
5ab79981
PB		 10635 return bfd_reloc_ok;
10636 }
10637
e95de063 10638 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10639 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10640 if (globals->use_rel)
10641 {
99059e56
RM		 10642 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10643 bfd_vma upper = upper_insn & 0x3ff;
10644 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10645 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10646 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10647 bfd_vma i1 = j1 ^ s ? 0 : 1;
10648 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10649
99059e56
RM		 10650 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10651 /* Sign extend. */
10652 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10653
4e7fd91e
PB		 10654 signed_addend = addend;
10655 }
cb1afa5c 10656
dfc5f959
NC		 10657 if (r_type == R_ARM_THM_XPC22)
10658 {
10659 /* Check for Thumb to Thumb call. */
10660 /* FIXME: Should we translate the instruction into a BL
10661 instruction instead ? */
35fc36a8 10662 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10663 _bfd_error_handler
d003868e
AM		 10664 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10665 input_bfd,
10666 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10667 }
10668 else
252b5132 10669 {
dfc5f959
NC		 10670 /* If it is not a call to Thumb, assume call to Arm.
10671 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10672 function call at all, but rather a long jump. Calls through
10673 the PLT do not require stubs. */
34e77a92 10674 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10675 {
bd97cb95 10676 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10677 {
10678 /* Convert BL to BLX. */
10679 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10680 }
155d87d7
CL		 10681 else if (( r_type != R_ARM_THM_CALL)
10682 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10683 {
10684 if (elf32_thumb_to_arm_stub
10685 (info, sym_name, input_bfd, output_bfd, input_section,
10686 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10687 error_message))
10688 return bfd_reloc_ok;
10689 else
10690 return bfd_reloc_dangerous;
10691 }
da5938a2 10692 }
35fc36a8
RS		 10693 else if (branch_type == ST_BRANCH_TO_THUMB
10694 && globals->use_blx
bd97cb95 10695 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10696 {
10697 /* Make sure this is a BL. */
10698 lower_insn |= 0x1800;
10699 }
252b5132 10700 }
f21f3fe0 10701
fe33d2fa 10702 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10703 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10704 {
10705 /* Check if a stub has to be inserted because the destination
8029a119 10706 is too far. */
fe33d2fa
CL		 10707 struct elf32_arm_stub_hash_entry *stub_entry;
10708 struct elf32_arm_link_hash_entry *hash;
10709
10710 hash = (struct elf32_arm_link_hash_entry *) h;
10711
10712 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10713 st_type, &branch_type,
10714 hash, value, sym_sec,
fe33d2fa
CL		 10715 input_bfd, sym_name);
10716
10717 if (stub_type != arm_stub_none)
906e58ca
NC		 10718 {
10719 /* The target is out of reach or we are changing modes, so
10720 redirect the branch to the local stub for this
10721 function. */
10722 stub_entry = elf32_arm_get_stub_entry (input_section,
10723 sym_sec, h,
fe33d2fa
CL		 10724 rel, globals,
10725 stub_type);
906e58ca 10726 if (stub_entry != NULL)
9cd3e4e5
NC		 10727 {
10728 value = (stub_entry->stub_offset
10729 + stub_entry->stub_sec->output_offset
10730 + stub_entry->stub_sec->output_section->vma);
10731
10732 if (plt_offset != (bfd_vma) -1)
10733 *unresolved_reloc_p = FALSE;
10734 }
906e58ca 10735
f4ac8484 10736 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10737 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10738 {
10739 if ((stub_entry
10740 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10741 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10742 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10743 }
906e58ca
NC		 10744 }
10745 }
10746
fe33d2fa 10747 /* Handle calls via the PLT. */
34e77a92 10748 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10749 {
10750 value = (splt->output_section->vma
10751 + splt->output_offset
34e77a92 10752 + plt_offset);
fe33d2fa 10753
eed94f8f
NC		 10754 if (globals->use_blx
10755 && r_type == R_ARM_THM_CALL
10756 && ! using_thumb_only (globals))
fe33d2fa
CL		 10757 {
10758 /* If the Thumb BLX instruction is available, convert
10759 the BL to a BLX instruction to call the ARM-mode
10760 PLT entry. */
10761 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10762 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10763 }
10764 else
10765 {
eed94f8f
NC		 10766 if (! using_thumb_only (globals))
10767 /* Target the Thumb stub before the ARM PLT entry. */
10768 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10769 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10770 }
10771 *unresolved_reloc_p = FALSE;
10772 }
10773
ba96a88f 10774 relocation = value + signed_addend;
f21f3fe0 10775
252b5132 10776 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10777 + input_section->output_offset
10778 + rel->r_offset);
9a5aca8c 10779
252b5132
RH		 10780 check = relocation >> howto->rightshift;
10781
10782 /* If this is a signed value, the rightshift just dropped
10783 leading 1 bits (assuming twos complement). */
10784 if ((bfd_signed_vma) relocation >= 0)
10785 signed_check = check;
10786 else
10787 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10788
e95de063
MS		 10789 /* Calculate the permissable maximum and minimum values for
10790 this relocation according to whether we're relocating for
10791 Thumb-2 or not. */
10792 bitsize = howto->bitsize;
5e866f5a 10793 if (!thumb2_bl)
e95de063 10794 bitsize -= 2;
f6ebfac0 10795 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10796 reloc_signed_min = ~reloc_signed_max;
10797
252b5132 10798 /* Assumes two's complement. */
ba96a88f 10799 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10800 overflow = TRUE;
252b5132 10801
bd97cb95 10802 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10803 /* For a BLX instruction, make sure that the relocation is rounded up
10804 to a word boundary. This follows the semantics of the instruction
10805 which specifies that bit 1 of the target address will come from bit
10806 1 of the base address. */
10807 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10808
e95de063
MS		 10809 /* Put RELOCATION back into the insn. Assumes two's complement.
10810 We use the Thumb-2 encoding, which is safe even if dealing with
10811 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10812 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10813 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10814 | ((relocation >> 12) & 0x3ff)
10815 | (reloc_sign << 10);
906e58ca 10816 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10817 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10818 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10819 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10820
252b5132
RH		 10821 /* Put the relocated value back in the object file: */
10822 bfd_put_16 (input_bfd, upper_insn, hit_data);
10823 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10824
10825 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10826 }
10827 break;
10828
c19d1205
ZW		 10829 case R_ARM_THM_JUMP19:
10830 /* Thumb32 conditional branch instruction. */
10831 {
10832 bfd_vma relocation;
10833 bfd_boolean overflow = FALSE;
10834 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10835 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10836 bfd_signed_vma reloc_signed_max = 0xffffe;
10837 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10838 bfd_signed_vma signed_check;
c5423981
TG		 10839 enum elf32_arm_stub_type stub_type = arm_stub_none;
10840 struct elf32_arm_stub_hash_entry *stub_entry;
10841 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10842
10843 /* Need to refetch the addend, reconstruct the top three bits,
10844 and squish the two 11 bit pieces together. */
10845 if (globals->use_rel)
10846 {
10847 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10848 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10849 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10850 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10851 bfd_vma lower = (lower_insn & 0x07ff);
10852
a00a1f35
MS		 10853 upper |= J1 << 6;
10854 upper |= J2 << 7;
10855 upper |= (!S) << 8;
c19d1205
ZW		 10856 upper -= 0x0100; /* Sign extend. */
10857
10858 addend = (upper << 12) | (lower << 1);
10859 signed_addend = addend;
10860 }
10861
bd97cb95 10862 /* Handle calls via the PLT. */
34e77a92 10863 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10864 {
10865 value = (splt->output_section->vma
10866 + splt->output_offset
34e77a92 10867 + plt_offset);
bd97cb95
DJ		 10868 /* Target the Thumb stub before the ARM PLT entry. */
10869 value -= PLT_THUMB_STUB_SIZE;
10870 *unresolved_reloc_p = FALSE;
10871 }
10872
c5423981
TG		 10873 hash = (struct elf32_arm_link_hash_entry *)h;
10874
10875 stub_type = arm_type_of_stub (info, input_section, rel,
10876 st_type, &branch_type,
10877 hash, value, sym_sec,
10878 input_bfd, sym_name);
10879 if (stub_type != arm_stub_none)
10880 {
10881 stub_entry = elf32_arm_get_stub_entry (input_section,
10882 sym_sec, h,
10883 rel, globals,
10884 stub_type);
10885 if (stub_entry != NULL)
10886 {
10887 value = (stub_entry->stub_offset
10888 + stub_entry->stub_sec->output_offset
10889 + stub_entry->stub_sec->output_section->vma);
10890 }
10891 }
c19d1205 10892
99059e56 10893 relocation = value + signed_addend;
c19d1205
ZW		 10894 relocation -= (input_section->output_section->vma
10895 + input_section->output_offset
10896 + rel->r_offset);
a00a1f35 10897 signed_check = (bfd_signed_vma) relocation;
c19d1205 10898
c19d1205
ZW		 10899 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10900 overflow = TRUE;
10901
10902 /* Put RELOCATION back into the insn. */
10903 {
10904 bfd_vma S = (relocation & 0x00100000) >> 20;
10905 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10906 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10907 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10908 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10909
a00a1f35 10910 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10911 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10912 }
10913
10914 /* Put the relocated value back in the object file: */
10915 bfd_put_16 (input_bfd, upper_insn, hit_data);
10916 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10917
10918 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10919 }
10920
10921 case R_ARM_THM_JUMP11:
10922 case R_ARM_THM_JUMP8:
10923 case R_ARM_THM_JUMP6:
51c5503b
NC		 10924 /* Thumb B (branch) instruction). */
10925 {
6cf9e9fe 10926 bfd_signed_vma relocation;
51c5503b
NC		 10927 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10928 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10929 bfd_signed_vma signed_check;
10930
c19d1205
ZW		 10931 /* CZB cannot jump backward. */
10932 if (r_type == R_ARM_THM_JUMP6)
10933 reloc_signed_min = 0;
10934
4e7fd91e 10935 if (globals->use_rel)
6cf9e9fe 10936 {
4e7fd91e
PB		 10937 /* Need to refetch addend. */
10938 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10939 if (addend & ((howto->src_mask + 1) >> 1))
10940 {
10941 signed_addend = -1;
10942 signed_addend &= ~ howto->src_mask;
10943 signed_addend |= addend;
10944 }
10945 else
10946 signed_addend = addend;
10947 /* The value in the insn has been right shifted. We need to
10948 undo this, so that we can perform the address calculation
10949 in terms of bytes. */
10950 signed_addend <<= howto->rightshift;
6cf9e9fe 10951 }
6cf9e9fe 10952 relocation = value + signed_addend;
51c5503b
NC		 10953
10954 relocation -= (input_section->output_section->vma
10955 + input_section->output_offset
10956 + rel->r_offset);
10957
6cf9e9fe
NC		 10958 relocation >>= howto->rightshift;
10959 signed_check = relocation;
c19d1205
ZW		 10960
10961 if (r_type == R_ARM_THM_JUMP6)
10962 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10963 else
10964 relocation &= howto->dst_mask;
51c5503b 10965 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10966
51c5503b
NC		 10967 bfd_put_16 (input_bfd, relocation, hit_data);
10968
10969 /* Assumes two's complement. */
10970 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10971 return bfd_reloc_overflow;
10972
10973 return bfd_reloc_ok;
10974 }
cedb70c5 10975
8375c36b
PB		 10976 case R_ARM_ALU_PCREL7_0:
10977 case R_ARM_ALU_PCREL15_8:
10978 case R_ARM_ALU_PCREL23_15:
10979 {
10980 bfd_vma insn;
10981 bfd_vma relocation;
10982
10983 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10984 if (globals->use_rel)
10985 {
10986 /* Extract the addend. */
10987 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10988 signed_addend = addend;
10989 }
8375c36b
PB		 10990 relocation = value + signed_addend;
10991
10992 relocation -= (input_section->output_section->vma
10993 + input_section->output_offset
10994 + rel->r_offset);
10995 insn = (insn & ~0xfff)
10996 | ((howto->bitpos << 7) & 0xf00)
10997 | ((relocation >> howto->bitpos) & 0xff);
10998 bfd_put_32 (input_bfd, value, hit_data);
10999 }
11000 return bfd_reloc_ok;
11001
252b5132
RH		 11002 case R_ARM_GNU_VTINHERIT:
11003 case R_ARM_GNU_VTENTRY:
11004 return bfd_reloc_ok;
11005
c19d1205 11006 case R_ARM_GOTOFF32:
252b5132 11007 /* Relocation is relative to the start of the
99059e56 11008 global offset table. */
252b5132
RH		 11009
11010 BFD_ASSERT (sgot != NULL);
11011 if (sgot == NULL)
99059e56 11012 return bfd_reloc_notsupported;
9a5aca8c 11013
cedb70c5 11014 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11015 address by one, so that attempts to call the function pointer will
11016 correctly interpret it as Thumb code. */
35fc36a8 11017 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11018 value += 1;
11019
252b5132 11020 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11021 calculation. We always want the start of .got. If we
11022 define _GLOBAL_OFFSET_TABLE in a different way, as is
11023 permitted by the ABI, we might have to change this
11024 calculation. */
252b5132 11025 value -= sgot->output_section->vma;
f21f3fe0 11026 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11027 contents, rel->r_offset, value,
00a97672 11028 rel->r_addend);
252b5132
RH		 11029
11030 case R_ARM_GOTPC:
a7c10850 11031 /* Use global offset table as symbol value. */
252b5132 11032 BFD_ASSERT (sgot != NULL);
f21f3fe0 11033
252b5132 11034 if (sgot == NULL)
99059e56 11035 return bfd_reloc_notsupported;
252b5132 11036
0945cdfd 11037 *unresolved_reloc_p = FALSE;
252b5132 11038 value = sgot->output_section->vma;
f21f3fe0 11039 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11040 contents, rel->r_offset, value,
00a97672 11041 rel->r_addend);
f21f3fe0 11042
252b5132 11043 case R_ARM_GOT32:
eb043451 11044 case R_ARM_GOT_PREL:
252b5132 11045 /* Relocation is to the entry for this symbol in the
99059e56 11046 global offset table. */
252b5132
RH		 11047 if (sgot == NULL)
11048 return bfd_reloc_notsupported;
f21f3fe0 11049
34e77a92
RS		 11050 if (dynreloc_st_type == STT_GNU_IFUNC
11051 && plt_offset != (bfd_vma) -1
11052 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11053 {
11054 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11055 symbol, and the relocation resolves directly to the runtime
11056 target rather than to the .iplt entry. This means that any
11057 .got entry would be the same value as the .igot.plt entry,
11058 so there's no point creating both. */
11059 sgot = globals->root.igotplt;
11060 value = sgot->output_offset + gotplt_offset;
11061 }
11062 else if (h != NULL)
252b5132
RH		 11063 {
11064 bfd_vma off;
f21f3fe0 11065
252b5132
RH		 11066 off = h->got.offset;
11067 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11068 if ((off & 1) != 0)
252b5132 11069 {
b436d854
RS		 11070 /* We have already processsed one GOT relocation against
11071 this symbol. */
11072 off &= ~1;
11073 if (globals->root.dynamic_sections_created
11074 && !SYMBOL_REFERENCES_LOCAL (info, h))
11075 *unresolved_reloc_p = FALSE;
11076 }
11077 else
11078 {
11079 Elf_Internal_Rela outrel;
11080
6f820c85 11081 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11082 {
11083 /* If the symbol doesn't resolve locally in a static
11084 object, we have an undefined reference. If the
11085 symbol doesn't resolve locally in a dynamic object,
11086 it should be resolved by the dynamic linker. */
11087 if (globals->root.dynamic_sections_created)
11088 {
11089 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11090 *unresolved_reloc_p = FALSE;
11091 }
11092 else
11093 outrel.r_info = 0;
11094 outrel.r_addend = 0;
11095 }
252b5132
RH		 11096 else
11097 {
34e77a92 11098 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11099 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11100 else if (bfd_link_pic (info)
11101 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11102 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11103 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11104 else
11105 outrel.r_info = 0;
34e77a92 11106 outrel.r_addend = dynreloc_value;
b436d854 11107 }
ee29b9fb 11108
b436d854
RS		 11109 /* The GOT entry is initialized to zero by default.
11110 See if we should install a different value. */
11111 if (outrel.r_addend != 0
11112 && (outrel.r_info == 0 || globals->use_rel))
11113 {
11114 bfd_put_32 (output_bfd, outrel.r_addend,
11115 sgot->contents + off);
11116 outrel.r_addend = 0;
252b5132 11117 }
f21f3fe0 11118
b436d854
RS		 11119 if (outrel.r_info != 0)
11120 {
11121 outrel.r_offset = (sgot->output_section->vma
11122 + sgot->output_offset
11123 + off);
11124 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11125 }
11126 h->got.offset |= 1;
11127 }
252b5132
RH		 11128 value = sgot->output_offset + off;
11129 }
11130 else
11131 {
11132 bfd_vma off;
f21f3fe0 11133
5025eb7c
AO		 11134 BFD_ASSERT (local_got_offsets != NULL
11135 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11136
252b5132 11137 off = local_got_offsets[r_symndx];
f21f3fe0 11138
252b5132
RH		 11139 /* The offset must always be a multiple of 4. We use the
11140 least significant bit to record whether we have already
9b485d32 11141 generated the necessary reloc. */
252b5132
RH		 11142 if ((off & 1) != 0)
11143 off &= ~1;
11144 else
11145 {
00a97672 11146 if (globals->use_rel)
34e77a92 11147 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11148
0e1862bb 11149 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11150 {
947216bf 11151 Elf_Internal_Rela outrel;
f21f3fe0 11152
34e77a92 11153 outrel.r_addend = addend + dynreloc_value;
252b5132 11154 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11155 + sgot->output_offset
252b5132 11156 + off);
34e77a92 11157 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11158 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11159 else
11160 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11161 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11162 }
f21f3fe0 11163
252b5132
RH		 11164 local_got_offsets[r_symndx] |= 1;
11165 }
f21f3fe0 11166
252b5132
RH		 11167 value = sgot->output_offset + off;
11168 }
eb043451
PB		 11169 if (r_type != R_ARM_GOT32)
11170 value += sgot->output_section->vma;
9a5aca8c 11171
f21f3fe0 11172 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11173 contents, rel->r_offset, value,
00a97672 11174 rel->r_addend);
f21f3fe0 11175
ba93b8ac
DJ		 11176 case R_ARM_TLS_LDO32:
11177 value = value - dtpoff_base (info);
11178
11179 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11180 contents, rel->r_offset, value,
11181 rel->r_addend);
ba93b8ac
DJ		 11182
11183 case R_ARM_TLS_LDM32:
11184 {
11185 bfd_vma off;
11186
362d30a1 11187 if (sgot == NULL)
ba93b8ac
DJ		 11188 abort ();
11189
11190 off = globals->tls_ldm_got.offset;
11191
11192 if ((off & 1) != 0)
11193 off &= ~1;
11194 else
11195 {
11196 /* If we don't know the module number, create a relocation
11197 for it. */
0e1862bb 11198 if (bfd_link_pic (info))
ba93b8ac
DJ		 11199 {
11200 Elf_Internal_Rela outrel;
ba93b8ac 11201
362d30a1 11202 if (srelgot == NULL)
ba93b8ac
DJ		 11203 abort ();
11204
00a97672 11205 outrel.r_addend = 0;
362d30a1
RS		 11206 outrel.r_offset = (sgot->output_section->vma
11207 + sgot->output_offset + off);
ba93b8ac
DJ		 11208 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11209
00a97672
RS		 11210 if (globals->use_rel)
11211 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11212 sgot->contents + off);
ba93b8ac 11213
47beaa6a 11214 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11215 }
11216 else
362d30a1 11217 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11218
11219 globals->tls_ldm_got.offset |= 1;
11220 }
11221
362d30a1 11222 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11223 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11224
11225 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11226 contents, rel->r_offset, value,
00a97672 11227 rel->r_addend);
ba93b8ac
DJ		 11228 }
11229
0855e32b
NS		 11230 case R_ARM_TLS_CALL:
11231 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11232 case R_ARM_TLS_GD32:
11233 case R_ARM_TLS_IE32:
0855e32b
NS		 11234 case R_ARM_TLS_GOTDESC:
11235 case R_ARM_TLS_DESCSEQ:
11236 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11237 {
0855e32b
NS		 11238 bfd_vma off, offplt;
11239 int indx = 0;
ba93b8ac
DJ		 11240 char tls_type;
11241
0855e32b 11242 BFD_ASSERT (sgot != NULL);
ba93b8ac 11243
ba93b8ac
DJ		 11244 if (h != NULL)
11245 {
11246 bfd_boolean dyn;
11247 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11248 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11249 bfd_link_pic (info),
11250 h)
11251 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11252 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11253 {
11254 *unresolved_reloc_p = FALSE;
11255 indx = h->dynindx;
11256 }
11257 off = h->got.offset;
0855e32b 11258 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11259 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11260 }
11261 else
11262 {
0855e32b 11263 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11264 off = local_got_offsets[r_symndx];
0855e32b 11265 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11266 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11267 }
11268
0855e32b 11269 /* Linker relaxations happens from one of the
b38cadfb 11270 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11271 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11272 tls_type = GOT_TLS_IE;
0855e32b
NS		 11273
11274 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11275
11276 if ((off & 1) != 0)
11277 off &= ~1;
11278 else
11279 {
11280 bfd_boolean need_relocs = FALSE;
11281 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11282 int cur_off = off;
11283
11284 /* The GOT entries have not been initialized yet. Do it
11285 now, and emit any relocations. If both an IE GOT and a
11286 GD GOT are necessary, we emit the GD first. */
11287
0e1862bb 11288 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 11289 && (h == NULL
11290 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11291 || h->root.type != bfd_link_hash_undefweak))
11292 {
11293 need_relocs = TRUE;
0855e32b 11294 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11295 }
11296
0855e32b
NS		 11297 if (tls_type & GOT_TLS_GDESC)
11298 {
47beaa6a
RS		 11299 bfd_byte *loc;
11300
0855e32b
NS		 11301 /* We should have relaxed, unless this is an undefined
11302 weak symbol. */
11303 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11304 || bfd_link_pic (info));
0855e32b 11305 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11306 <= globals->root.sgotplt->size);
0855e32b
NS		 11307
11308 outrel.r_addend = 0;
11309 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11310 + globals->root.sgotplt->output_offset
11311 + offplt
11312 + globals->sgotplt_jump_table_size);
b38cadfb 11313
0855e32b
NS		 11314 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11315 sreloc = globals->root.srelplt;
11316 loc = sreloc->contents;
11317 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11318 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11319 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11320
11321 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11322
11323 /* For globals, the first word in the relocation gets
11324 the relocation index and the top bit set, or zero,
11325 if we're binding now. For locals, it gets the
11326 symbol's offset in the tls section. */
99059e56 11327 bfd_put_32 (output_bfd,
0855e32b
NS		 11328 !h ? value - elf_hash_table (info)->tls_sec->vma
11329 : info->flags & DF_BIND_NOW ? 0
11330 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11331 globals->root.sgotplt->contents + offplt
11332 + globals->sgotplt_jump_table_size);
11333
0855e32b 11334 /* Second word in the relocation is always zero. */
99059e56 11335 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11336 globals->root.sgotplt->contents + offplt
11337 + globals->sgotplt_jump_table_size + 4);
0855e32b 11338 }
ba93b8ac
DJ		 11339 if (tls_type & GOT_TLS_GD)
11340 {
11341 if (need_relocs)
11342 {
00a97672 11343 outrel.r_addend = 0;
362d30a1
RS		 11344 outrel.r_offset = (sgot->output_section->vma
11345 + sgot->output_offset
00a97672 11346 + cur_off);
ba93b8ac 11347 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11348
00a97672
RS		 11349 if (globals->use_rel)
11350 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11351 sgot->contents + cur_off);
00a97672 11352
47beaa6a 11353 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11354
11355 if (indx == 0)
11356 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11357 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11358 else
11359 {
00a97672 11360 outrel.r_addend = 0;
ba93b8ac
DJ		 11361 outrel.r_info = ELF32_R_INFO (indx,
11362 R_ARM_TLS_DTPOFF32);
11363 outrel.r_offset += 4;
00a97672
RS		 11364
11365 if (globals->use_rel)
11366 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11367 sgot->contents + cur_off + 4);
00a97672 11368
47beaa6a
RS		 11369 elf32_arm_add_dynreloc (output_bfd, info,
11370 srelgot, &outrel);
ba93b8ac
DJ		 11371 }
11372 }
11373 else
11374 {
11375 /* If we are not emitting relocations for a
11376 general dynamic reference, then we must be in a
11377 static link or an executable link with the
11378 symbol binding locally. Mark it as belonging
11379 to module 1, the executable. */
11380 bfd_put_32 (output_bfd, 1,
362d30a1 11381 sgot->contents + cur_off);
ba93b8ac 11382 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11383 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11384 }
11385
11386 cur_off += 8;
11387 }
11388
11389 if (tls_type & GOT_TLS_IE)
11390 {
11391 if (need_relocs)
11392 {
00a97672
RS		 11393 if (indx == 0)
11394 outrel.r_addend = value - dtpoff_base (info);
11395 else
11396 outrel.r_addend = 0;
362d30a1
RS		 11397 outrel.r_offset = (sgot->output_section->vma
11398 + sgot->output_offset
ba93b8ac
DJ		 11399 + cur_off);
11400 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11401
00a97672
RS		 11402 if (globals->use_rel)
11403 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11404 sgot->contents + cur_off);
ba93b8ac 11405
47beaa6a 11406 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11407 }
11408 else
11409 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11410 sgot->contents + cur_off);
ba93b8ac
DJ		 11411 cur_off += 4;
11412 }
11413
11414 if (h != NULL)
11415 h->got.offset |= 1;
11416 else
11417 local_got_offsets[r_symndx] |= 1;
11418 }
11419
11420 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11421 off += 8;
0855e32b
NS		 11422 else if (tls_type & GOT_TLS_GDESC)
11423 off = offplt;
11424
11425 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11426 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11427 {
11428 bfd_signed_vma offset;
12352d3f
PB		 11429 /* TLS stubs are arm mode. The original symbol is a
11430 data object, so branch_type is bogus. */
11431 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11432 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11433 = arm_type_of_stub (info, input_section, rel,
11434 st_type, &branch_type,
0855e32b
NS		 11435 (struct elf32_arm_link_hash_entry *)h,
11436 globals->tls_trampoline, globals->root.splt,
11437 input_bfd, sym_name);
11438
11439 if (stub_type != arm_stub_none)
11440 {
11441 struct elf32_arm_stub_hash_entry *stub_entry
11442 = elf32_arm_get_stub_entry
11443 (input_section, globals->root.splt, 0, rel,
11444 globals, stub_type);
11445 offset = (stub_entry->stub_offset
11446 + stub_entry->stub_sec->output_offset
11447 + stub_entry->stub_sec->output_section->vma);
11448 }
11449 else
11450 offset = (globals->root.splt->output_section->vma
11451 + globals->root.splt->output_offset
11452 + globals->tls_trampoline);
11453
11454 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11455 {
11456 unsigned long inst;
b38cadfb
NC		 11457
11458 offset -= (input_section->output_section->vma
11459 + input_section->output_offset
11460 + rel->r_offset + 8);
0855e32b
NS		 11461
11462 inst = offset >> 2;
11463 inst &= 0x00ffffff;
11464 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11465 }
11466 else
11467 {
11468 /* Thumb blx encodes the offset in a complicated
11469 fashion. */
11470 unsigned upper_insn, lower_insn;
11471 unsigned neg;
11472
b38cadfb
NC		 11473 offset -= (input_section->output_section->vma
11474 + input_section->output_offset
0855e32b 11475 + rel->r_offset + 4);
b38cadfb 11476
12352d3f
PB		 11477 if (stub_type != arm_stub_none
11478 && arm_stub_is_thumb (stub_type))
11479 {
11480 lower_insn = 0xd000;
11481 }
11482 else
11483 {
11484 lower_insn = 0xc000;
6a631e86 11485 /* Round up the offset to a word boundary. */
12352d3f
PB		 11486 offset = (offset + 2) & ~2;
11487 }
11488
0855e32b
NS		 11489 neg = offset < 0;
11490 upper_insn = (0xf000
11491 | ((offset >> 12) & 0x3ff)
11492 | (neg << 10));
12352d3f 11493 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11494 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11495 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11496 bfd_put_16 (input_bfd, upper_insn, hit_data);
11497 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11498 return bfd_reloc_ok;
11499 }
11500 }
11501 /* These relocations needs special care, as besides the fact
11502 they point somewhere in .gotplt, the addend must be
11503 adjusted accordingly depending on the type of instruction
6a631e86 11504 we refer to. */
0855e32b
NS		 11505 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11506 {
11507 unsigned long data, insn;
11508 unsigned thumb;
b38cadfb 11509
0855e32b
NS		 11510 data = bfd_get_32 (input_bfd, hit_data);
11511 thumb = data & 1;
11512 data &= ~1u;
b38cadfb 11513
0855e32b
NS		 11514 if (thumb)
11515 {
11516 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11517 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11518 insn = (insn << 16)
11519 | bfd_get_16 (input_bfd,
11520 contents + rel->r_offset - data + 2);
11521 if ((insn & 0xf800c000) == 0xf000c000)
11522 /* bl/blx */
11523 value = -6;
11524 else if ((insn & 0xffffff00) == 0x4400)
11525 /* add */
11526 value = -5;
11527 else
11528 {
4eca0228 11529 _bfd_error_handler
695344c0
NC		 11530 /* xgettext:c-format */
11531 (_("%B(%A+0x%lx): unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
0855e32b
NS		 11532 input_bfd, input_section,
11533 (unsigned long)rel->r_offset, insn);
11534 return bfd_reloc_notsupported;
11535 }
11536 }
11537 else
11538 {
11539 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11540
11541 switch (insn >> 24)
11542 {
11543 case 0xeb: /* bl */
11544 case 0xfa: /* blx */
11545 value = -4;
11546 break;
11547
11548 case 0xe0: /* add */
11549 value = -8;
11550 break;
b38cadfb 11551
0855e32b 11552 default:
4eca0228 11553 _bfd_error_handler
695344c0
NC		 11554 /* xgettext:c-format */
11555 (_("%B(%A+0x%lx): unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
0855e32b
NS		 11556 input_bfd, input_section,
11557 (unsigned long)rel->r_offset, insn);
11558 return bfd_reloc_notsupported;
11559 }
11560 }
b38cadfb 11561
0855e32b
NS		 11562 value += ((globals->root.sgotplt->output_section->vma
11563 + globals->root.sgotplt->output_offset + off)
11564 - (input_section->output_section->vma
11565 + input_section->output_offset
11566 + rel->r_offset)
11567 + globals->sgotplt_jump_table_size);
11568 }
11569 else
11570 value = ((globals->root.sgot->output_section->vma
11571 + globals->root.sgot->output_offset + off)
11572 - (input_section->output_section->vma
11573 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11574
11575 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11576 contents, rel->r_offset, value,
00a97672 11577 rel->r_addend);
ba93b8ac
DJ		 11578 }
11579
11580 case R_ARM_TLS_LE32:
3cbc1e5e 11581 if (bfd_link_dll (info))
ba93b8ac 11582 {
4eca0228 11583 _bfd_error_handler
695344c0 11584 /* xgettext:c-format */
ba93b8ac
DJ		 11585 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
11586 input_bfd, input_section,
11587 (long) rel->r_offset, howto->name);
46691134 11588 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11589 }
11590 else
11591 value = tpoff (info, value);
906e58ca 11592
ba93b8ac 11593 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11594 contents, rel->r_offset, value,
11595 rel->r_addend);
ba93b8ac 11596
319850b4
JB		 11597 case R_ARM_V4BX:
11598 if (globals->fix_v4bx)
845b51d6
PB		 11599 {
11600 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11601
845b51d6
PB		 11602 /* Ensure that we have a BX instruction. */
11603 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11604
845b51d6
PB		 11605 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11606 {
11607 /* Branch to veneer. */
11608 bfd_vma glue_addr;
11609 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11610 glue_addr -= input_section->output_section->vma
11611 + input_section->output_offset
11612 + rel->r_offset + 8;
11613 insn = (insn & 0xf0000000) | 0x0a000000
11614 | ((glue_addr >> 2) & 0x00ffffff);
11615 }
11616 else
11617 {
11618 /* Preserve Rm (lowest four bits) and the condition code
11619 (highest four bits). Other bits encode MOV PC,Rm. */
11620 insn = (insn & 0xf000000f) | 0x01a0f000;
11621 }
319850b4 11622
845b51d6
PB		 11623 bfd_put_32 (input_bfd, insn, hit_data);
11624 }
319850b4
JB		 11625 return bfd_reloc_ok;
11626
b6895b4f
PB		 11627 case R_ARM_MOVW_ABS_NC:
11628 case R_ARM_MOVT_ABS:
11629 case R_ARM_MOVW_PREL_NC:
11630 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11631 /* Until we properly support segment-base-relative addressing then
11632 we assume the segment base to be zero, as for the group relocations.
11633 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11634 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11635 case R_ARM_MOVW_BREL_NC:
11636 case R_ARM_MOVW_BREL:
11637 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11638 {
11639 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11640
11641 if (globals->use_rel)
11642 {
11643 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11644 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11645 }
92f5d02b 11646
b6895b4f 11647 value += signed_addend;
b6895b4f
PB		 11648
11649 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11650 value -= (input_section->output_section->vma
11651 + input_section->output_offset + rel->r_offset);
11652
92f5d02b 11653 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11654 return bfd_reloc_overflow;
92f5d02b 11655
35fc36a8 11656 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11657 value |= 1;
11658
11659 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11660 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11661 value >>= 16;
11662
11663 insn &= 0xfff0f000;
11664 insn |= value & 0xfff;
11665 insn |= (value & 0xf000) << 4;
11666 bfd_put_32 (input_bfd, insn, hit_data);
11667 }
11668 return bfd_reloc_ok;
11669
11670 case R_ARM_THM_MOVW_ABS_NC:
11671 case R_ARM_THM_MOVT_ABS:
11672 case R_ARM_THM_MOVW_PREL_NC:
11673 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11674 /* Until we properly support segment-base-relative addressing then
11675 we assume the segment base to be zero, as for the above relocations.
11676 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11677 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11678 as R_ARM_THM_MOVT_ABS. */
11679 case R_ARM_THM_MOVW_BREL_NC:
11680 case R_ARM_THM_MOVW_BREL:
11681 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11682 {
11683 bfd_vma insn;
906e58ca 11684
b6895b4f
PB		 11685 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11686 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11687
11688 if (globals->use_rel)
11689 {
11690 addend = ((insn >> 4) & 0xf000)
11691 | ((insn >> 15) & 0x0800)
11692 | ((insn >> 4) & 0x0700)
11693 | (insn & 0x00ff);
39623e12 11694 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11695 }
92f5d02b 11696
b6895b4f 11697 value += signed_addend;
b6895b4f
PB		 11698
11699 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11700 value -= (input_section->output_section->vma
11701 + input_section->output_offset + rel->r_offset);
11702
92f5d02b 11703 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11704 return bfd_reloc_overflow;
92f5d02b 11705
35fc36a8 11706 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11707 value |= 1;
11708
11709 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11710 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11711 value >>= 16;
11712
11713 insn &= 0xfbf08f00;
11714 insn |= (value & 0xf000) << 4;
11715 insn |= (value & 0x0800) << 15;
11716 insn |= (value & 0x0700) << 4;
11717 insn |= (value & 0x00ff);
11718
11719 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11720 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11721 }
11722 return bfd_reloc_ok;
11723
4962c51a
MS		 11724 case R_ARM_ALU_PC_G0_NC:
11725 case R_ARM_ALU_PC_G1_NC:
11726 case R_ARM_ALU_PC_G0:
11727 case R_ARM_ALU_PC_G1:
11728 case R_ARM_ALU_PC_G2:
11729 case R_ARM_ALU_SB_G0_NC:
11730 case R_ARM_ALU_SB_G1_NC:
11731 case R_ARM_ALU_SB_G0:
11732 case R_ARM_ALU_SB_G1:
11733 case R_ARM_ALU_SB_G2:
11734 {
11735 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11736 bfd_vma pc = input_section->output_section->vma
4962c51a 11737 + input_section->output_offset + rel->r_offset;
31a91d61 11738 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11739 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11740 bfd_vma residual;
11741 bfd_vma g_n;
4962c51a 11742 bfd_signed_vma signed_value;
99059e56
RM		 11743 int group = 0;
11744
11745 /* Determine which group of bits to select. */
11746 switch (r_type)
11747 {
11748 case R_ARM_ALU_PC_G0_NC:
11749 case R_ARM_ALU_PC_G0:
11750 case R_ARM_ALU_SB_G0_NC:
11751 case R_ARM_ALU_SB_G0:
11752 group = 0;
11753 break;
11754
11755 case R_ARM_ALU_PC_G1_NC:
11756 case R_ARM_ALU_PC_G1:
11757 case R_ARM_ALU_SB_G1_NC:
11758 case R_ARM_ALU_SB_G1:
11759 group = 1;
11760 break;
11761
11762 case R_ARM_ALU_PC_G2:
11763 case R_ARM_ALU_SB_G2:
11764 group = 2;
11765 break;
11766
11767 default:
11768 abort ();
11769 }
11770
11771 /* If REL, extract the addend from the insn. If RELA, it will
11772 have already been fetched for us. */
4962c51a 11773 if (globals->use_rel)
99059e56
RM		 11774 {
11775 int negative;
11776 bfd_vma constant = insn & 0xff;
11777 bfd_vma rotation = (insn & 0xf00) >> 8;
11778
11779 if (rotation == 0)
11780 signed_addend = constant;
11781 else
11782 {
11783 /* Compensate for the fact that in the instruction, the
11784 rotation is stored in multiples of 2 bits. */
11785 rotation *= 2;
11786
11787 /* Rotate "constant" right by "rotation" bits. */
11788 signed_addend = (constant >> rotation) |
11789 (constant << (8 * sizeof (bfd_vma) - rotation));
11790 }
11791
11792 /* Determine if the instruction is an ADD or a SUB.
11793 (For REL, this determines the sign of the addend.) */
11794 negative = identify_add_or_sub (insn);
11795 if (negative == 0)
11796 {
4eca0228 11797 _bfd_error_handler
695344c0 11798 /* xgettext:c-format */
99059e56
RM		 11799 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11800 input_bfd, input_section,
11801 (long) rel->r_offset, howto->name);
11802 return bfd_reloc_overflow;
11803 }
11804
11805 signed_addend *= negative;
11806 }
4962c51a
MS		 11807
11808 /* Compute the value (X) to go in the place. */
99059e56
RM		 11809 if (r_type == R_ARM_ALU_PC_G0_NC
11810 || r_type == R_ARM_ALU_PC_G1_NC
11811 || r_type == R_ARM_ALU_PC_G0
11812 || r_type == R_ARM_ALU_PC_G1
11813 || r_type == R_ARM_ALU_PC_G2)
11814 /* PC relative. */
11815 signed_value = value - pc + signed_addend;
11816 else
11817 /* Section base relative. */
11818 signed_value = value - sb + signed_addend;
11819
11820 /* If the target symbol is a Thumb function, then set the
11821 Thumb bit in the address. */
35fc36a8 11822 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11823 signed_value |= 1;
11824
99059e56
RM		 11825 /* Calculate the value of the relevant G_n, in encoded
11826 constant-with-rotation format. */
b6518b38
NC		 11827 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11828 group, &residual);
99059e56
RM		 11829
11830 /* Check for overflow if required. */
11831 if ((r_type == R_ARM_ALU_PC_G0
11832 || r_type == R_ARM_ALU_PC_G1
11833 || r_type == R_ARM_ALU_PC_G2
11834 || r_type == R_ARM_ALU_SB_G0
11835 || r_type == R_ARM_ALU_SB_G1
11836 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11837 {
4eca0228 11838 _bfd_error_handler
695344c0 11839 /* xgettext:c-format */
99059e56
RM		 11840 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11841 input_bfd, input_section,
b6518b38
NC		 11842 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11843 howto->name);
99059e56
RM		 11844 return bfd_reloc_overflow;
11845 }
11846
11847 /* Mask out the value and the ADD/SUB part of the opcode; take care
11848 not to destroy the S bit. */
11849 insn &= 0xff1ff000;
11850
11851 /* Set the opcode according to whether the value to go in the
11852 place is negative. */
11853 if (signed_value < 0)
11854 insn |= 1 << 22;
11855 else
11856 insn |= 1 << 23;
11857
11858 /* Encode the offset. */
11859 insn |= g_n;
4962c51a
MS		 11860
11861 bfd_put_32 (input_bfd, insn, hit_data);
11862 }
11863 return bfd_reloc_ok;
11864
11865 case R_ARM_LDR_PC_G0:
11866 case R_ARM_LDR_PC_G1:
11867 case R_ARM_LDR_PC_G2:
11868 case R_ARM_LDR_SB_G0:
11869 case R_ARM_LDR_SB_G1:
11870 case R_ARM_LDR_SB_G2:
11871 {
11872 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11873 bfd_vma pc = input_section->output_section->vma
4962c51a 11874 + input_section->output_offset + rel->r_offset;
31a91d61 11875 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11876 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11877 bfd_vma residual;
4962c51a 11878 bfd_signed_vma signed_value;
99059e56
RM		 11879 int group = 0;
11880
11881 /* Determine which groups of bits to calculate. */
11882 switch (r_type)
11883 {
11884 case R_ARM_LDR_PC_G0:
11885 case R_ARM_LDR_SB_G0:
11886 group = 0;
11887 break;
11888
11889 case R_ARM_LDR_PC_G1:
11890 case R_ARM_LDR_SB_G1:
11891 group = 1;
11892 break;
11893
11894 case R_ARM_LDR_PC_G2:
11895 case R_ARM_LDR_SB_G2:
11896 group = 2;
11897 break;
11898
11899 default:
11900 abort ();
11901 }
11902
11903 /* If REL, extract the addend from the insn. If RELA, it will
11904 have already been fetched for us. */
4962c51a 11905 if (globals->use_rel)
99059e56
RM		 11906 {
11907 int negative = (insn & (1 << 23)) ? 1 : -1;
11908 signed_addend = negative * (insn & 0xfff);
11909 }
4962c51a
MS		 11910
11911 /* Compute the value (X) to go in the place. */
99059e56
RM		 11912 if (r_type == R_ARM_LDR_PC_G0
11913 || r_type == R_ARM_LDR_PC_G1
11914 || r_type == R_ARM_LDR_PC_G2)
11915 /* PC relative. */
11916 signed_value = value - pc + signed_addend;
11917 else
11918 /* Section base relative. */
11919 signed_value = value - sb + signed_addend;
11920
11921 /* Calculate the value of the relevant G_{n-1} to obtain
11922 the residual at that stage. */
b6518b38
NC		 11923 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11924 group - 1, &residual);
99059e56
RM		 11925
11926 /* Check for overflow. */
11927 if (residual >= 0x1000)
11928 {
4eca0228 11929 _bfd_error_handler
695344c0 11930 /* xgettext:c-format */
99059e56 11931 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11932 input_bfd, input_section,
11933 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11934 return bfd_reloc_overflow;
11935 }
11936
11937 /* Mask out the value and U bit. */
11938 insn &= 0xff7ff000;
11939
11940 /* Set the U bit if the value to go in the place is non-negative. */
11941 if (signed_value >= 0)
11942 insn |= 1 << 23;
11943
11944 /* Encode the offset. */
11945 insn |= residual;
4962c51a
MS		 11946
11947 bfd_put_32 (input_bfd, insn, hit_data);
11948 }
11949 return bfd_reloc_ok;
11950
11951 case R_ARM_LDRS_PC_G0:
11952 case R_ARM_LDRS_PC_G1:
11953 case R_ARM_LDRS_PC_G2:
11954 case R_ARM_LDRS_SB_G0:
11955 case R_ARM_LDRS_SB_G1:
11956 case R_ARM_LDRS_SB_G2:
11957 {
11958 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11959 bfd_vma pc = input_section->output_section->vma
4962c51a 11960 + input_section->output_offset + rel->r_offset;
31a91d61 11961 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11962 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11963 bfd_vma residual;
4962c51a 11964 bfd_signed_vma signed_value;
99059e56
RM		 11965 int group = 0;
11966
11967 /* Determine which groups of bits to calculate. */
11968 switch (r_type)
11969 {
11970 case R_ARM_LDRS_PC_G0:
11971 case R_ARM_LDRS_SB_G0:
11972 group = 0;
11973 break;
11974
11975 case R_ARM_LDRS_PC_G1:
11976 case R_ARM_LDRS_SB_G1:
11977 group = 1;
11978 break;
11979
11980 case R_ARM_LDRS_PC_G2:
11981 case R_ARM_LDRS_SB_G2:
11982 group = 2;
11983 break;
11984
11985 default:
11986 abort ();
11987 }
11988
11989 /* If REL, extract the addend from the insn. If RELA, it will
11990 have already been fetched for us. */
4962c51a 11991 if (globals->use_rel)
99059e56
RM		 11992 {
11993 int negative = (insn & (1 << 23)) ? 1 : -1;
11994 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11995 }
4962c51a
MS		 11996
11997 /* Compute the value (X) to go in the place. */
99059e56
RM		 11998 if (r_type == R_ARM_LDRS_PC_G0
11999 || r_type == R_ARM_LDRS_PC_G1
12000 || r_type == R_ARM_LDRS_PC_G2)
12001 /* PC relative. */
12002 signed_value = value - pc + signed_addend;
12003 else
12004 /* Section base relative. */
12005 signed_value = value - sb + signed_addend;
12006
12007 /* Calculate the value of the relevant G_{n-1} to obtain
12008 the residual at that stage. */
b6518b38
NC		 12009 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12010 group - 1, &residual);
99059e56
RM		 12011
12012 /* Check for overflow. */
12013 if (residual >= 0x100)
12014 {
4eca0228 12015 _bfd_error_handler
695344c0 12016 /* xgettext:c-format */
99059e56 12017 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 12018 input_bfd, input_section,
12019 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12020 return bfd_reloc_overflow;
12021 }
12022
12023 /* Mask out the value and U bit. */
12024 insn &= 0xff7ff0f0;
12025
12026 /* Set the U bit if the value to go in the place is non-negative. */
12027 if (signed_value >= 0)
12028 insn |= 1 << 23;
12029
12030 /* Encode the offset. */
12031 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12032
12033 bfd_put_32 (input_bfd, insn, hit_data);
12034 }
12035 return bfd_reloc_ok;
12036
12037 case R_ARM_LDC_PC_G0:
12038 case R_ARM_LDC_PC_G1:
12039 case R_ARM_LDC_PC_G2:
12040 case R_ARM_LDC_SB_G0:
12041 case R_ARM_LDC_SB_G1:
12042 case R_ARM_LDC_SB_G2:
12043 {
12044 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12045 bfd_vma pc = input_section->output_section->vma
4962c51a 12046 + input_section->output_offset + rel->r_offset;
31a91d61 12047 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12048 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12049 bfd_vma residual;
4962c51a 12050 bfd_signed_vma signed_value;
99059e56
RM		 12051 int group = 0;
12052
12053 /* Determine which groups of bits to calculate. */
12054 switch (r_type)
12055 {
12056 case R_ARM_LDC_PC_G0:
12057 case R_ARM_LDC_SB_G0:
12058 group = 0;
12059 break;
12060
12061 case R_ARM_LDC_PC_G1:
12062 case R_ARM_LDC_SB_G1:
12063 group = 1;
12064 break;
12065
12066 case R_ARM_LDC_PC_G2:
12067 case R_ARM_LDC_SB_G2:
12068 group = 2;
12069 break;
12070
12071 default:
12072 abort ();
12073 }
12074
12075 /* If REL, extract the addend from the insn. If RELA, it will
12076 have already been fetched for us. */
4962c51a 12077 if (globals->use_rel)
99059e56
RM		 12078 {
12079 int negative = (insn & (1 << 23)) ? 1 : -1;
12080 signed_addend = negative * ((insn & 0xff) << 2);
12081 }
4962c51a
MS		 12082
12083 /* Compute the value (X) to go in the place. */
99059e56
RM		 12084 if (r_type == R_ARM_LDC_PC_G0
12085 || r_type == R_ARM_LDC_PC_G1
12086 || r_type == R_ARM_LDC_PC_G2)
12087 /* PC relative. */
12088 signed_value = value - pc + signed_addend;
12089 else
12090 /* Section base relative. */
12091 signed_value = value - sb + signed_addend;
12092
12093 /* Calculate the value of the relevant G_{n-1} to obtain
12094 the residual at that stage. */
b6518b38
NC		 12095 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12096 group - 1, &residual);
99059e56
RM		 12097
12098 /* Check for overflow. (The absolute value to go in the place must be
12099 divisible by four and, after having been divided by four, must
12100 fit in eight bits.) */
12101 if ((residual & 0x3) != 0 || residual >= 0x400)
12102 {
4eca0228 12103 _bfd_error_handler
695344c0 12104 /* xgettext:c-format */
99059e56
RM		 12105 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
12106 input_bfd, input_section,
b6518b38 12107 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12108 return bfd_reloc_overflow;
12109 }
12110
12111 /* Mask out the value and U bit. */
12112 insn &= 0xff7fff00;
12113
12114 /* Set the U bit if the value to go in the place is non-negative. */
12115 if (signed_value >= 0)
12116 insn |= 1 << 23;
12117
12118 /* Encode the offset. */
12119 insn |= residual >> 2;
4962c51a
MS		 12120
12121 bfd_put_32 (input_bfd, insn, hit_data);
12122 }
12123 return bfd_reloc_ok;
12124
72d98d16
MG		 12125 case R_ARM_THM_ALU_ABS_G0_NC:
12126 case R_ARM_THM_ALU_ABS_G1_NC:
12127 case R_ARM_THM_ALU_ABS_G2_NC:
12128 case R_ARM_THM_ALU_ABS_G3_NC:
12129 {
12130 const int shift_array[4] = {0, 8, 16, 24};
12131 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12132 bfd_vma addr = value;
12133 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12134
12135 /* Compute address. */
12136 if (globals->use_rel)
12137 signed_addend = insn & 0xff;
12138 addr += signed_addend;
12139 if (branch_type == ST_BRANCH_TO_THUMB)
12140 addr |= 1;
12141 /* Clean imm8 insn. */
12142 insn &= 0xff00;
12143 /* And update with correct part of address. */
12144 insn |= (addr >> shift) & 0xff;
12145 /* Update insn. */
12146 bfd_put_16 (input_bfd, insn, hit_data);
12147 }
12148
12149 *unresolved_reloc_p = FALSE;
12150 return bfd_reloc_ok;
12151
252b5132
RH		 12152 default:
12153 return bfd_reloc_notsupported;
12154 }
12155}
12156
98c1d4aa
NC		 12157/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12158static void
57e8b36a
NC		 12159arm_add_to_rel (bfd * abfd,
12160 bfd_byte * address,
12161 reloc_howto_type * howto,
12162 bfd_signed_vma increment)
98c1d4aa 12163{
98c1d4aa
NC		 12164 bfd_signed_vma addend;
12165
bd97cb95
DJ		 12166 if (howto->type == R_ARM_THM_CALL
12167 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12168 {
9a5aca8c
AM		 12169 int upper_insn, lower_insn;
12170 int upper, lower;
98c1d4aa 12171
9a5aca8c
AM		 12172 upper_insn = bfd_get_16 (abfd, address);
12173 lower_insn = bfd_get_16 (abfd, address + 2);
12174 upper = upper_insn & 0x7ff;
12175 lower = lower_insn & 0x7ff;
12176
12177 addend = (upper << 12) | (lower << 1);
ddda4409 12178 addend += increment;
9a5aca8c 12179 addend >>= 1;
98c1d4aa 12180
9a5aca8c
AM		 12181 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12182 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12183
dc810e39
AM		 12184 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12185 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12186 }
12187 else
12188 {
12189 bfd_vma contents;
12190
12191 contents = bfd_get_32 (abfd, address);
12192
12193 /* Get the (signed) value from the instruction. */
12194 addend = contents & howto->src_mask;
12195 if (addend & ((howto->src_mask + 1) >> 1))
12196 {
12197 bfd_signed_vma mask;
12198
12199 mask = -1;
12200 mask &= ~ howto->src_mask;
12201 addend |= mask;
12202 }
12203
12204 /* Add in the increment, (which is a byte value). */
12205 switch (howto->type)
12206 {
12207 default:
12208 addend += increment;
12209 break;
12210
12211 case R_ARM_PC24:
c6596c5e 12212 case R_ARM_PLT32:
5b5bb741
PB		 12213 case R_ARM_CALL:
12214 case R_ARM_JUMP24:
9a5aca8c 12215 addend <<= howto->size;
dc810e39 12216 addend += increment;
9a5aca8c
AM		 12217
12218 /* Should we check for overflow here ? */
12219
12220 /* Drop any undesired bits. */
12221 addend >>= howto->rightshift;
12222 break;
12223 }
12224
12225 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12226
12227 bfd_put_32 (abfd, contents, address);
ddda4409 12228 }
98c1d4aa 12229}
252b5132 12230
ba93b8ac
DJ		 12231#define IS_ARM_TLS_RELOC(R_TYPE) \
12232 ((R_TYPE) == R_ARM_TLS_GD32 \
12233 || (R_TYPE) == R_ARM_TLS_LDO32 \
12234 || (R_TYPE) == R_ARM_TLS_LDM32 \
12235 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12236 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12237 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12238 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12239 || (R_TYPE) == R_ARM_TLS_IE32 \
12240 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12241
12242/* Specific set of relocations for the gnu tls dialect. */
12243#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12244 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12245 || (R_TYPE) == R_ARM_TLS_CALL \
12246 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12247 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12248 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12249
252b5132 12250/* Relocate an ARM ELF section. */
906e58ca 12251
b34976b6 12252static bfd_boolean
57e8b36a
NC		 12253elf32_arm_relocate_section (bfd * output_bfd,
12254 struct bfd_link_info * info,
12255 bfd * input_bfd,
12256 asection * input_section,
12257 bfd_byte * contents,
12258 Elf_Internal_Rela * relocs,
12259 Elf_Internal_Sym * local_syms,
12260 asection ** local_sections)
252b5132 12261{
b34976b6
AM		 12262 Elf_Internal_Shdr *symtab_hdr;
12263 struct elf_link_hash_entry **sym_hashes;
12264 Elf_Internal_Rela *rel;
12265 Elf_Internal_Rela *relend;
12266 const char *name;
b32d3aa2 12267 struct elf32_arm_link_hash_table * globals;
252b5132 12268
4e7fd91e 12269 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12270 if (globals == NULL)
12271 return FALSE;
b491616a 12272
0ffa91dd 12273 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12274 sym_hashes = elf_sym_hashes (input_bfd);
12275
12276 rel = relocs;
12277 relend = relocs + input_section->reloc_count;
12278 for (; rel < relend; rel++)
12279 {
ba96a88f
NC		 12280 int r_type;
12281 reloc_howto_type * howto;
12282 unsigned long r_symndx;
12283 Elf_Internal_Sym * sym;
12284 asection * sec;
252b5132 12285 struct elf_link_hash_entry * h;
ba96a88f
NC		 12286 bfd_vma relocation;
12287 bfd_reloc_status_type r;
12288 arelent bfd_reloc;
ba93b8ac 12289 char sym_type;
0945cdfd 12290 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12291 char *error_message = NULL;
f21f3fe0 12292
252b5132 12293 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12294 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12295 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12296
ba96a88f 12297 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12298 || r_type == R_ARM_GNU_VTINHERIT)
12299 continue;
252b5132 12300
b32d3aa2 12301 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 12302 howto = bfd_reloc.howto;
252b5132 12303
252b5132
RH		 12304 h = NULL;
12305 sym = NULL;
12306 sec = NULL;
9b485d32 12307
252b5132
RH		 12308 if (r_symndx < symtab_hdr->sh_info)
12309 {
12310 sym = local_syms + r_symndx;
ba93b8ac 12311 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12312 sec = local_sections[r_symndx];
ffcb4889
NS		 12313
12314 /* An object file might have a reference to a local
12315 undefined symbol. This is a daft object file, but we
12316 should at least do something about it. V4BX & NONE
12317 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12318 allowed to use the undefined symbol, so allow those.
12319 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12320 if (r_type != R_ARM_V4BX
12321 && r_type != R_ARM_NONE
77b4f08f 12322 && r_symndx != STN_UNDEF
ffcb4889
NS		 12323 && bfd_is_und_section (sec)
12324 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12325 (*info->callbacks->undefined_symbol)
12326 (info, bfd_elf_string_from_elf_section
12327 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12328 input_bfd, input_section,
12329 rel->r_offset, TRUE);
b38cadfb 12330
4e7fd91e 12331 if (globals->use_rel)
f8df10f4 12332 {
4e7fd91e
PB		 12333 relocation = (sec->output_section->vma
12334 + sec->output_offset
12335 + sym->st_value);
0e1862bb 12336 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12337 && (sec->flags & SEC_MERGE)
12338 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12339 {
4e7fd91e
PB		 12340 asection *msec;
12341 bfd_vma addend, value;
12342
39623e12 12343 switch (r_type)
4e7fd91e 12344 {
39623e12
PB		 12345 case R_ARM_MOVW_ABS_NC:
12346 case R_ARM_MOVT_ABS:
12347 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12348 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12349 addend = (addend ^ 0x8000) - 0x8000;
12350 break;
f8df10f4 12351
39623e12
PB		 12352 case R_ARM_THM_MOVW_ABS_NC:
12353 case R_ARM_THM_MOVT_ABS:
12354 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12355 << 16;
12356 value |= bfd_get_16 (input_bfd,
12357 contents + rel->r_offset + 2);
12358 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12359 | ((value & 0x04000000) >> 15);
12360 addend = (addend ^ 0x8000) - 0x8000;
12361 break;
f8df10f4 12362
39623e12
PB		 12363 default:
12364 if (howto->rightshift
12365 || (howto->src_mask & (howto->src_mask + 1)))
12366 {
4eca0228 12367 _bfd_error_handler
695344c0 12368 /* xgettext:c-format */
39623e12
PB		 12369 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
12370 input_bfd, input_section,
12371 (long) rel->r_offset, howto->name);
12372 return FALSE;
12373 }
12374
12375 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12376
12377 /* Get the (signed) value from the instruction. */
12378 addend = value & howto->src_mask;
12379 if (addend & ((howto->src_mask + 1) >> 1))
12380 {
12381 bfd_signed_vma mask;
12382
12383 mask = -1;
12384 mask &= ~ howto->src_mask;
12385 addend |= mask;
12386 }
12387 break;
4e7fd91e 12388 }
39623e12 12389
4e7fd91e
PB		 12390 msec = sec;
12391 addend =
12392 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12393 - relocation;
12394 addend += msec->output_section->vma + msec->output_offset;
39623e12 12395
cc643b88 12396 /* Cases here must match those in the preceding
39623e12
PB		 12397 switch statement. */
12398 switch (r_type)
12399 {
12400 case R_ARM_MOVW_ABS_NC:
12401 case R_ARM_MOVT_ABS:
12402 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12403 | (addend & 0xfff);
12404 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12405 break;
12406
12407 case R_ARM_THM_MOVW_ABS_NC:
12408 case R_ARM_THM_MOVT_ABS:
12409 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12410 | (addend & 0xff) | ((addend & 0x0800) << 15);
12411 bfd_put_16 (input_bfd, value >> 16,
12412 contents + rel->r_offset);
12413 bfd_put_16 (input_bfd, value,
12414 contents + rel->r_offset + 2);
12415 break;
12416
12417 default:
12418 value = (value & ~ howto->dst_mask)
12419 | (addend & howto->dst_mask);
12420 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12421 break;
12422 }
f8df10f4 12423 }
f8df10f4 12424 }
4e7fd91e
PB		 12425 else
12426 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12427 }
12428 else
12429 {
62d887d4 12430 bfd_boolean warned, ignored;
560e09e9 12431
b2a8e766
AM		 12432 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12433 r_symndx, symtab_hdr, sym_hashes,
12434 h, sec, relocation,
62d887d4 12435 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12436
12437 sym_type = h->type;
252b5132
RH		 12438 }
12439
dbaa2011 12440 if (sec != NULL && discarded_section (sec))
e4067dbb 12441 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12442 rel, 1, relend, howto, 0, contents);
ab96bf03 12443
0e1862bb 12444 if (bfd_link_relocatable (info))
ab96bf03
AM		 12445 {
12446 /* This is a relocatable link. We don't have to change
12447 anything, unless the reloc is against a section symbol,
12448 in which case we have to adjust according to where the
12449 section symbol winds up in the output section. */
12450 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12451 {
12452 if (globals->use_rel)
12453 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12454 howto, (bfd_signed_vma) sec->output_offset);
12455 else
12456 rel->r_addend += sec->output_offset;
12457 }
12458 continue;
12459 }
12460
252b5132
RH		 12461 if (h != NULL)
12462 name = h->root.root.string;
12463 else
12464 {
12465 name = (bfd_elf_string_from_elf_section
12466 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12467 if (name == NULL || *name == '\0')
12468 name = bfd_section_name (input_bfd, sec);
12469 }
f21f3fe0 12470
cf35638d 12471 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12472 && r_type != R_ARM_NONE
12473 && (h == NULL
12474 || h->root.type == bfd_link_hash_defined
12475 || h->root.type == bfd_link_hash_defweak)
12476 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12477 {
4eca0228 12478 _bfd_error_handler
ba93b8ac 12479 ((sym_type == STT_TLS
695344c0 12480 /* xgettext:c-format */
ba93b8ac 12481 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
695344c0 12482 /* xgettext:c-format */
ba93b8ac
DJ		 12483 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
12484 input_bfd,
12485 input_section,
12486 (long) rel->r_offset,
12487 howto->name,
12488 name);
12489 }
12490
0855e32b 12491 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12492 done, i.e., the relaxation produced the final output we want,
12493 and we won't let anybody mess with it. Also, we have to do
12494 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12495 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12496 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12497 || (IS_ARM_TLS_GNU_RELOC (r_type)
12498 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12499 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12500 & GOT_TLS_GDESC)))
12501 {
12502 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12503 contents, rel, h == NULL);
12504 /* This may have been marked unresolved because it came from
12505 a shared library. But we've just dealt with that. */
12506 unresolved_reloc = 0;
12507 }
12508 else
12509 r = bfd_reloc_continue;
b38cadfb 12510
39d911fc
TP		 12511 if (r == bfd_reloc_continue)
12512 {
12513 unsigned char branch_type =
12514 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12515 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12516
12517 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12518 input_section, contents, rel,
12519 relocation, info, sec, name,
12520 sym_type, branch_type, h,
12521 &unresolved_reloc,
12522 &error_message);
12523 }
0945cdfd
DJ		 12524
12525 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12526 because such sections are not SEC_ALLOC and thus ld.so will
12527 not process them. */
12528 if (unresolved_reloc
99059e56
RM		 12529 && !((input_section->flags & SEC_DEBUGGING) != 0
12530 && h->def_dynamic)
1d5316ab
AM		 12531 && _bfd_elf_section_offset (output_bfd, info, input_section,
12532 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12533 {
4eca0228 12534 _bfd_error_handler
695344c0 12535 /* xgettext:c-format */
843fe662
L		 12536 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
12537 input_bfd,
12538 input_section,
12539 (long) rel->r_offset,
12540 howto->name,
12541 h->root.root.string);
0945cdfd
DJ		 12542 return FALSE;
12543 }
252b5132
RH		 12544
12545 if (r != bfd_reloc_ok)
12546 {
252b5132
RH		 12547 switch (r)
12548 {
12549 case bfd_reloc_overflow:
cf919dfd
PB		 12550 /* If the overflowing reloc was to an undefined symbol,
12551 we have already printed one error message and there
12552 is no point complaining again. */
1a72702b
AM		 12553 if (!h || h->root.type != bfd_link_hash_undefined)
12554 (*info->callbacks->reloc_overflow)
12555 (info, (h ? &h->root : NULL), name, howto->name,
12556 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12557 break;
12558
12559 case bfd_reloc_undefined:
1a72702b
AM		 12560 (*info->callbacks->undefined_symbol)
12561 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12562 break;
12563
12564 case bfd_reloc_outofrange:
f2a9dd69 12565 error_message = _("out of range");
252b5132
RH		 12566 goto common_error;
12567
12568 case bfd_reloc_notsupported:
f2a9dd69 12569 error_message = _("unsupported relocation");
252b5132
RH		 12570 goto common_error;
12571
12572 case bfd_reloc_dangerous:
f2a9dd69 12573 /* error_message should already be set. */
252b5132
RH		 12574 goto common_error;
12575
12576 default:
f2a9dd69 12577 error_message = _("unknown error");
8029a119 12578 /* Fall through. */
252b5132
RH		 12579
12580 common_error:
f2a9dd69 12581 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12582 (*info->callbacks->reloc_dangerous)
12583 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12584 break;
12585 }
12586 }
12587 }
12588
b34976b6 12589 return TRUE;
252b5132
RH		 12590}
12591
91d6fa6a 12592/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12593 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12594 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12595 maintaining that condition). */
12596
12597static void
12598add_unwind_table_edit (arm_unwind_table_edit **head,
12599 arm_unwind_table_edit **tail,
12600 arm_unwind_edit_type type,
12601 asection *linked_section,
91d6fa6a 12602 unsigned int tindex)
2468f9c9 12603{
21d799b5
NC		 12604 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12605 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12606
2468f9c9
PB		 12607 new_edit->type = type;
12608 new_edit->linked_section = linked_section;
91d6fa6a 12609 new_edit->index = tindex;
b38cadfb 12610
91d6fa6a 12611 if (tindex > 0)
2468f9c9
PB		 12612 {
12613 new_edit->next = NULL;
12614
12615 if (*tail)
12616 (*tail)->next = new_edit;
12617
12618 (*tail) = new_edit;
12619
12620 if (!*head)
12621 (*head) = new_edit;
12622 }
12623 else
12624 {
12625 new_edit->next = *head;
12626
12627 if (!*tail)
12628 *tail = new_edit;
12629
12630 *head = new_edit;
12631 }
12632}
12633
12634static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12635
12636/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12637static void
12638adjust_exidx_size(asection *exidx_sec, int adjust)
12639{
12640 asection *out_sec;
12641
12642 if (!exidx_sec->rawsize)
12643 exidx_sec->rawsize = exidx_sec->size;
12644
12645 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12646 out_sec = exidx_sec->output_section;
12647 /* Adjust size of output section. */
12648 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12649}
12650
12651/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12652static void
12653insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12654{
12655 struct _arm_elf_section_data *exidx_arm_data;
12656
12657 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12658 add_unwind_table_edit (
12659 &exidx_arm_data->u.exidx.unwind_edit_list,
12660 &exidx_arm_data->u.exidx.unwind_edit_tail,
12661 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12662
491d01d3
YU		 12663 exidx_arm_data->additional_reloc_count++;
12664
2468f9c9
PB		 12665 adjust_exidx_size(exidx_sec, 8);
12666}
12667
12668/* Scan .ARM.exidx tables, and create a list describing edits which should be
12669 made to those tables, such that:
b38cadfb 12670
2468f9c9
PB		 12671 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12672 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12673 codes which have been inlined into the index).
2468f9c9 12674
85fdf906
AH		 12675 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12676
2468f9c9 12677 The edits are applied when the tables are written
b38cadfb 12678 (in elf32_arm_write_section). */
2468f9c9
PB		 12679
12680bfd_boolean
12681elf32_arm_fix_exidx_coverage (asection **text_section_order,
12682 unsigned int num_text_sections,
85fdf906
AH		 12683 struct bfd_link_info *info,
12684 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12685{
12686 bfd *inp;
12687 unsigned int last_second_word = 0, i;
12688 asection *last_exidx_sec = NULL;
12689 asection *last_text_sec = NULL;
12690 int last_unwind_type = -1;
12691
12692 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12693 text sections. */
c72f2fb2 12694 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12695 {
12696 asection *sec;
b38cadfb 12697
2468f9c9 12698 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12699 {
2468f9c9
PB		 12700 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12701 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12702
dec9d5df 12703 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12704 continue;
b38cadfb 12705
2468f9c9
PB		 12706 if (elf_sec->linked_to)
12707 {
12708 Elf_Internal_Shdr *linked_hdr
99059e56 12709 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12710 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12711 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12712
12713 if (linked_sec_arm_data == NULL)
99059e56 12714 continue;
2468f9c9
PB		 12715
12716 /* Link this .ARM.exidx section back from the text section it
99059e56 12717 describes. */
2468f9c9
PB		 12718 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12719 }
12720 }
12721 }
12722
12723 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12724 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12725 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12726
12727 for (i = 0; i < num_text_sections; i++)
12728 {
12729 asection *sec = text_section_order[i];
12730 asection *exidx_sec;
12731 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12732 struct _arm_elf_section_data *exidx_arm_data;
12733 bfd_byte *contents = NULL;
12734 int deleted_exidx_bytes = 0;
12735 bfd_vma j;
12736 arm_unwind_table_edit *unwind_edit_head = NULL;
12737 arm_unwind_table_edit *unwind_edit_tail = NULL;
12738 Elf_Internal_Shdr *hdr;
12739 bfd *ibfd;
12740
12741 if (arm_data == NULL)
99059e56 12742 continue;
2468f9c9
PB		 12743
12744 exidx_sec = arm_data->u.text.arm_exidx_sec;
12745 if (exidx_sec == NULL)
12746 {
12747 /* Section has no unwind data. */
12748 if (last_unwind_type == 0 || !last_exidx_sec)
12749 continue;
12750
12751 /* Ignore zero sized sections. */
12752 if (sec->size == 0)
12753 continue;
12754
12755 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12756 last_unwind_type = 0;
12757 continue;
12758 }
12759
22a8f80e
PB		 12760 /* Skip /DISCARD/ sections. */
12761 if (bfd_is_abs_section (exidx_sec->output_section))
12762 continue;
12763
2468f9c9
PB		 12764 hdr = &elf_section_data (exidx_sec)->this_hdr;
12765 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12766 continue;
b38cadfb 12767
2468f9c9
PB		 12768 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12769 if (exidx_arm_data == NULL)
99059e56 12770 continue;
b38cadfb 12771
2468f9c9 12772 ibfd = exidx_sec->owner;
b38cadfb 12773
2468f9c9
PB		 12774 if (hdr->contents != NULL)
12775 contents = hdr->contents;
12776 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12777 /* An error? */
12778 continue;
12779
ac06903d
YU		 12780 if (last_unwind_type > 0)
12781 {
12782 unsigned int first_word = bfd_get_32 (ibfd, contents);
12783 /* Add cantunwind if first unwind item does not match section
12784 start. */
12785 if (first_word != sec->vma)
12786 {
12787 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12788 last_unwind_type = 0;
12789 }
12790 }
12791
2468f9c9
PB		 12792 for (j = 0; j < hdr->sh_size; j += 8)
12793 {
12794 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12795 int unwind_type;
12796 int elide = 0;
12797
12798 /* An EXIDX_CANTUNWIND entry. */
12799 if (second_word == 1)
12800 {
12801 if (last_unwind_type == 0)
12802 elide = 1;
12803 unwind_type = 0;
12804 }
12805 /* Inlined unwinding data. Merge if equal to previous. */
12806 else if ((second_word & 0x80000000) != 0)
12807 {
85fdf906
AH		 12808 if (merge_exidx_entries
12809 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12810 elide = 1;
12811 unwind_type = 1;
12812 last_second_word = second_word;
12813 }
12814 /* Normal table entry. In theory we could merge these too,
12815 but duplicate entries are likely to be much less common. */
12816 else
12817 unwind_type = 2;
12818
491d01d3 12819 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12820 {
12821 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12822 DELETE_EXIDX_ENTRY, NULL, j / 8);
12823
12824 deleted_exidx_bytes += 8;
12825 }
12826
12827 last_unwind_type = unwind_type;
12828 }
12829
12830 /* Free contents if we allocated it ourselves. */
12831 if (contents != hdr->contents)
99059e56 12832 free (contents);
2468f9c9
PB		 12833
12834 /* Record edits to be applied later (in elf32_arm_write_section). */
12835 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12836 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12837
2468f9c9
PB		 12838 if (deleted_exidx_bytes > 0)
12839 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12840
12841 last_exidx_sec = exidx_sec;
12842 last_text_sec = sec;
12843 }
12844
12845 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12846 if (!bfd_link_relocatable (info) && last_exidx_sec
12847 && last_unwind_type != 0)
2468f9c9
PB		 12848 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12849
12850 return TRUE;
12851}
12852
3e6b1042
DJ		 12853static bfd_boolean
12854elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12855 bfd *ibfd, const char *name)
12856{
12857 asection *sec, *osec;
12858
3d4d4302 12859 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12860 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12861 return TRUE;
12862
12863 osec = sec->output_section;
12864 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12865 return TRUE;
12866
12867 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12868 sec->output_offset, sec->size))
12869 return FALSE;
12870
12871 return TRUE;
12872}
12873
12874static bfd_boolean
12875elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12876{
12877 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12878 asection *sec, *osec;
3e6b1042 12879
4dfe6ac6
NC		 12880 if (globals == NULL)
12881 return FALSE;
12882
3e6b1042
DJ		 12883 /* Invoke the regular ELF backend linker to do all the work. */
12884 if (!bfd_elf_final_link (abfd, info))
12885 return FALSE;
12886
fe33d2fa
CL		 12887 /* Process stub sections (eg BE8 encoding, ...). */
12888 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12889 unsigned int i;
cdb21a0a
NS		 12890 for (i=0; i<htab->top_id; i++)
12891 {
12892 sec = htab->stub_group[i].stub_sec;
12893 /* Only process it once, in its link_sec slot. */
12894 if (sec && i == htab->stub_group[i].link_sec->id)
12895 {
12896 osec = sec->output_section;
12897 elf32_arm_write_section (abfd, info, sec, sec->contents);
12898 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12899 sec->output_offset, sec->size))
12900 return FALSE;
12901 }
fe33d2fa 12902 }
fe33d2fa 12903
3e6b1042
DJ		 12904 /* Write out any glue sections now that we have created all the
12905 stubs. */
12906 if (globals->bfd_of_glue_owner != NULL)
12907 {
12908 if (! elf32_arm_output_glue_section (info, abfd,
12909 globals->bfd_of_glue_owner,
12910 ARM2THUMB_GLUE_SECTION_NAME))
12911 return FALSE;
12912
12913 if (! elf32_arm_output_glue_section (info, abfd,
12914 globals->bfd_of_glue_owner,
12915 THUMB2ARM_GLUE_SECTION_NAME))
12916 return FALSE;
12917
12918 if (! elf32_arm_output_glue_section (info, abfd,
12919 globals->bfd_of_glue_owner,
12920 VFP11_ERRATUM_VENEER_SECTION_NAME))
12921 return FALSE;
12922
a504d23a
LA		 12923 if (! elf32_arm_output_glue_section (info, abfd,
12924 globals->bfd_of_glue_owner,
12925 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12926 return FALSE;
12927
3e6b1042
DJ		 12928 if (! elf32_arm_output_glue_section (info, abfd,
12929 globals->bfd_of_glue_owner,
12930 ARM_BX_GLUE_SECTION_NAME))
12931 return FALSE;
12932 }
12933
12934 return TRUE;
12935}
12936
5968a7b8
NC		 12937/* Return a best guess for the machine number based on the attributes. */
12938
12939static unsigned int
12940bfd_arm_get_mach_from_attributes (bfd * abfd)
12941{
12942 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12943
12944 switch (arch)
12945 {
12946 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12947 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12948 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12949
12950 case TAG_CPU_ARCH_V5TE:
12951 {
12952 char * name;
12953
12954 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12955 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12956
12957 if (name)
12958 {
12959 if (strcmp (name, "IWMMXT2") == 0)
12960 return bfd_mach_arm_iWMMXt2;
12961
12962 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12963 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12964
12965 if (strcmp (name, "XSCALE") == 0)
12966 {
12967 int wmmx;
12968
12969 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12970 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12971 switch (wmmx)
12972 {
12973 case 1: return bfd_mach_arm_iWMMXt;
12974 case 2: return bfd_mach_arm_iWMMXt2;
12975 default: return bfd_mach_arm_XScale;
12976 }
12977 }
5968a7b8
NC		 12978 }
12979
12980 return bfd_mach_arm_5TE;
12981 }
12982
12983 default:
12984 return bfd_mach_arm_unknown;
12985 }
12986}
12987
c178919b
NC		 12988/* Set the right machine number. */
12989
12990static bfd_boolean
57e8b36a 12991elf32_arm_object_p (bfd *abfd)
c178919b 12992{
5a6c6817 12993 unsigned int mach;
57e8b36a 12994
5a6c6817 12995 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12996
5968a7b8
NC		 12997 if (mach == bfd_mach_arm_unknown)
12998 {
12999 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13000 mach = bfd_mach_arm_ep9312;
13001 else
13002 mach = bfd_arm_get_mach_from_attributes (abfd);
13003 }
c178919b 13004
5968a7b8 13005 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13006 return TRUE;
13007}
13008
fc830a83 13009/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13010
b34976b6 13011static bfd_boolean
57e8b36a 13012elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13013{
13014 if (elf_flags_init (abfd)
13015 && elf_elfheader (abfd)->e_flags != flags)
13016 {
fc830a83
NC		 13017 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13018 {
fd2ec330 13019 if (flags & EF_ARM_INTERWORK)
4eca0228 13020 _bfd_error_handler
d003868e
AM		 13021 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
13022 abfd);
fc830a83 13023 else
d003868e
AM		 13024 _bfd_error_handler
13025 (_("Warning: Clearing the interworking flag of %B due to outside request"),
13026 abfd);
fc830a83 13027 }
252b5132
RH		 13028 }
13029 else
13030 {
13031 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13032 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13033 }
13034
b34976b6 13035 return TRUE;
252b5132
RH		 13036}
13037
fc830a83 13038/* Copy backend specific data from one object module to another. */
9b485d32 13039
b34976b6 13040static bfd_boolean
57e8b36a 13041elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13042{
13043 flagword in_flags;
13044 flagword out_flags;
13045
0ffa91dd 13046 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13047 return TRUE;
252b5132 13048
fc830a83 13049 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13050 out_flags = elf_elfheader (obfd)->e_flags;
13051
fc830a83
NC		 13052 if (elf_flags_init (obfd)
13053 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13054 && in_flags != out_flags)
252b5132 13055 {
252b5132 13056 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13057 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13058 return FALSE;
252b5132
RH		 13059
13060 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13061 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13062 return FALSE;
252b5132
RH		 13063
13064 /* If the src and dest have different interworking flags
99059e56 13065 then turn off the interworking bit. */
fd2ec330 13066 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13067 {
fd2ec330 13068 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 13069 _bfd_error_handler
13070 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
13071 obfd, ibfd);
252b5132 13072
fd2ec330 13073 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13074 }
1006ba19
PB		 13075
13076 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13077 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13078 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13079 }
13080
13081 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13082 elf_flags_init (obfd) = TRUE;
252b5132 13083
e2349352 13084 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13085}
13086
13087/* Values for Tag_ABI_PCS_R9_use. */
13088enum
13089{
13090 AEABI_R9_V6,
13091 AEABI_R9_SB,
13092 AEABI_R9_TLS,
13093 AEABI_R9_unused
13094};
13095
13096/* Values for Tag_ABI_PCS_RW_data. */
13097enum
13098{
13099 AEABI_PCS_RW_data_absolute,
13100 AEABI_PCS_RW_data_PCrel,
13101 AEABI_PCS_RW_data_SBrel,
13102 AEABI_PCS_RW_data_unused
13103};
13104
13105/* Values for Tag_ABI_enum_size. */
13106enum
13107{
13108 AEABI_enum_unused,
13109 AEABI_enum_short,
13110 AEABI_enum_wide,
13111 AEABI_enum_forced_wide
13112};
13113
104d59d1
JM		 13114/* Determine whether an object attribute tag takes an integer, a
13115 string or both. */
906e58ca 13116
104d59d1
JM		 13117static int
13118elf32_arm_obj_attrs_arg_type (int tag)
13119{
13120 if (tag == Tag_compatibility)
3483fe2e 13121 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13122 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13123 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13124 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13125 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13126 else if (tag < 32)
3483fe2e 13127 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13128 else
3483fe2e 13129 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13130}
13131
5aa6ff7c
AS		 13132/* The ABI defines that Tag_conformance should be emitted first, and that
13133 Tag_nodefaults should be second (if either is defined). This sets those
13134 two positions, and bumps up the position of all the remaining tags to
13135 compensate. */
13136static int
13137elf32_arm_obj_attrs_order (int num)
13138{
3de4a297 13139 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13140 return Tag_conformance;
3de4a297 13141 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13142 return Tag_nodefaults;
13143 if ((num - 2) < Tag_nodefaults)
13144 return num - 2;
13145 if ((num - 1) < Tag_conformance)
13146 return num - 1;
13147 return num;
13148}
13149
e8b36cd1
JM		 13150/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13151static bfd_boolean
13152elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13153{
13154 if ((tag & 127) < 64)
13155 {
13156 _bfd_error_handler
13157 (_("%B: Unknown mandatory EABI object attribute %d"),
13158 abfd, tag);
13159 bfd_set_error (bfd_error_bad_value);
13160 return FALSE;
13161 }
13162 else
13163 {
13164 _bfd_error_handler
13165 (_("Warning: %B: Unknown EABI object attribute %d"),
13166 abfd, tag);
13167 return TRUE;
13168 }
13169}
13170
91e22acd
AS		 13171/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13172 Returns -1 if no architecture could be read. */
13173
13174static int
13175get_secondary_compatible_arch (bfd *abfd)
13176{
13177 obj_attribute *attr =
13178 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13179
13180 /* Note: the tag and its argument below are uleb128 values, though
13181 currently-defined values fit in one byte for each. */
13182 if (attr->s
13183 && attr->s[0] == Tag_CPU_arch
13184 && (attr->s[1] & 128) != 128
13185 && attr->s[2] == 0)
13186 return attr->s[1];
13187
13188 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13189 return -1;
13190}
13191
13192/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13193 The tag is removed if ARCH is -1. */
13194
8e79c3df 13195static void
91e22acd 13196set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13197{
91e22acd
AS		 13198 obj_attribute *attr =
13199 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13200
91e22acd
AS		 13201 if (arch == -1)
13202 {
13203 attr->s = NULL;
13204 return;
8e79c3df 13205 }
91e22acd
AS		 13206
13207 /* Note: the tag and its argument below are uleb128 values, though
13208 currently-defined values fit in one byte for each. */
13209 if (!attr->s)
21d799b5 13210 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13211 attr->s[0] = Tag_CPU_arch;
13212 attr->s[1] = arch;
13213 attr->s[2] = '\0';
8e79c3df
CM		 13214}
13215
91e22acd
AS		 13216/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13217 into account. */
13218
13219static int
13220tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13221 int newtag, int secondary_compat)
8e79c3df 13222{
91e22acd
AS		 13223#define T(X) TAG_CPU_ARCH_##X
13224 int tagl, tagh, result;
13225 const int v6t2[] =
13226 {
13227 T(V6T2), /* PRE_V4. */
13228 T(V6T2), /* V4. */
13229 T(V6T2), /* V4T. */
13230 T(V6T2), /* V5T. */
13231 T(V6T2), /* V5TE. */
13232 T(V6T2), /* V5TEJ. */
13233 T(V6T2), /* V6. */
13234 T(V7), /* V6KZ. */
13235 T(V6T2) /* V6T2. */
13236 };
13237 const int v6k[] =
13238 {
13239 T(V6K), /* PRE_V4. */
13240 T(V6K), /* V4. */
13241 T(V6K), /* V4T. */
13242 T(V6K), /* V5T. */
13243 T(V6K), /* V5TE. */
13244 T(V6K), /* V5TEJ. */
13245 T(V6K), /* V6. */
13246 T(V6KZ), /* V6KZ. */
13247 T(V7), /* V6T2. */
13248 T(V6K) /* V6K. */
13249 };
13250 const int v7[] =
13251 {
13252 T(V7), /* PRE_V4. */
13253 T(V7), /* V4. */
13254 T(V7), /* V4T. */
13255 T(V7), /* V5T. */
13256 T(V7), /* V5TE. */
13257 T(V7), /* V5TEJ. */
13258 T(V7), /* V6. */
13259 T(V7), /* V6KZ. */
13260 T(V7), /* V6T2. */
13261 T(V7), /* V6K. */
13262 T(V7) /* V7. */
13263 };
13264 const int v6_m[] =
13265 {
13266 -1, /* PRE_V4. */
13267 -1, /* V4. */
13268 T(V6K), /* V4T. */
13269 T(V6K), /* V5T. */
13270 T(V6K), /* V5TE. */
13271 T(V6K), /* V5TEJ. */
13272 T(V6K), /* V6. */
13273 T(V6KZ), /* V6KZ. */
13274 T(V7), /* V6T2. */
13275 T(V6K), /* V6K. */
13276 T(V7), /* V7. */
13277 T(V6_M) /* V6_M. */
13278 };
13279 const int v6s_m[] =
13280 {
13281 -1, /* PRE_V4. */
13282 -1, /* V4. */
13283 T(V6K), /* V4T. */
13284 T(V6K), /* V5T. */
13285 T(V6K), /* V5TE. */
13286 T(V6K), /* V5TEJ. */
13287 T(V6K), /* V6. */
13288 T(V6KZ), /* V6KZ. */
13289 T(V7), /* V6T2. */
13290 T(V6K), /* V6K. */
13291 T(V7), /* V7. */
13292 T(V6S_M), /* V6_M. */
13293 T(V6S_M) /* V6S_M. */
13294 };
9e3c6df6
PB		 13295 const int v7e_m[] =
13296 {
13297 -1, /* PRE_V4. */
13298 -1, /* V4. */
13299 T(V7E_M), /* V4T. */
13300 T(V7E_M), /* V5T. */
13301 T(V7E_M), /* V5TE. */
13302 T(V7E_M), /* V5TEJ. */
13303 T(V7E_M), /* V6. */
13304 T(V7E_M), /* V6KZ. */
13305 T(V7E_M), /* V6T2. */
13306 T(V7E_M), /* V6K. */
13307 T(V7E_M), /* V7. */
13308 T(V7E_M), /* V6_M. */
13309 T(V7E_M), /* V6S_M. */
13310 T(V7E_M) /* V7E_M. */
13311 };
bca38921
MGD		 13312 const int v8[] =
13313 {
13314 T(V8), /* PRE_V4. */
13315 T(V8), /* V4. */
13316 T(V8), /* V4T. */
13317 T(V8), /* V5T. */
13318 T(V8), /* V5TE. */
13319 T(V8), /* V5TEJ. */
13320 T(V8), /* V6. */
13321 T(V8), /* V6KZ. */
13322 T(V8), /* V6T2. */
13323 T(V8), /* V6K. */
13324 T(V8), /* V7. */
13325 T(V8), /* V6_M. */
13326 T(V8), /* V6S_M. */
13327 T(V8), /* V7E_M. */
13328 T(V8) /* V8. */
13329 };
2fd158eb
TP		 13330 const int v8m_baseline[] =
13331 {
13332 -1, /* PRE_V4. */
13333 -1, /* V4. */
13334 -1, /* V4T. */
13335 -1, /* V5T. */
13336 -1, /* V5TE. */
13337 -1, /* V5TEJ. */
13338 -1, /* V6. */
13339 -1, /* V6KZ. */
13340 -1, /* V6T2. */
13341 -1, /* V6K. */
13342 -1, /* V7. */
13343 T(V8M_BASE), /* V6_M. */
13344 T(V8M_BASE), /* V6S_M. */
13345 -1, /* V7E_M. */
13346 -1, /* V8. */
13347 -1,
13348 T(V8M_BASE) /* V8-M BASELINE. */
13349 };
13350 const int v8m_mainline[] =
13351 {
13352 -1, /* PRE_V4. */
13353 -1, /* V4. */
13354 -1, /* V4T. */
13355 -1, /* V5T. */
13356 -1, /* V5TE. */
13357 -1, /* V5TEJ. */
13358 -1, /* V6. */
13359 -1, /* V6KZ. */
13360 -1, /* V6T2. */
13361 -1, /* V6K. */
13362 T(V8M_MAIN), /* V7. */
13363 T(V8M_MAIN), /* V6_M. */
13364 T(V8M_MAIN), /* V6S_M. */
13365 T(V8M_MAIN), /* V7E_M. */
13366 -1, /* V8. */
13367 -1,
13368 T(V8M_MAIN), /* V8-M BASELINE. */
13369 T(V8M_MAIN) /* V8-M MAINLINE. */
13370 };
91e22acd
AS		 13371 const int v4t_plus_v6_m[] =
13372 {
13373 -1, /* PRE_V4. */
13374 -1, /* V4. */
13375 T(V4T), /* V4T. */
13376 T(V5T), /* V5T. */
13377 T(V5TE), /* V5TE. */
13378 T(V5TEJ), /* V5TEJ. */
13379 T(V6), /* V6. */
13380 T(V6KZ), /* V6KZ. */
13381 T(V6T2), /* V6T2. */
13382 T(V6K), /* V6K. */
13383 T(V7), /* V7. */
13384 T(V6_M), /* V6_M. */
13385 T(V6S_M), /* V6S_M. */
9e3c6df6 13386 T(V7E_M), /* V7E_M. */
bca38921 13387 T(V8), /* V8. */
4ed7ed8d 13388 -1, /* Unused. */
2fd158eb
TP		 13389 T(V8M_BASE), /* V8-M BASELINE. */
13390 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13391 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13392 };
13393 const int *comb[] =
13394 {
13395 v6t2,
13396 v6k,
13397 v7,
13398 v6_m,
13399 v6s_m,
9e3c6df6 13400 v7e_m,
bca38921 13401 v8,
4ed7ed8d 13402 NULL,
2fd158eb
TP		 13403 v8m_baseline,
13404 v8m_mainline,
91e22acd
AS		 13405 /* Pseudo-architecture. */
13406 v4t_plus_v6_m
13407 };
13408
13409 /* Check we've not got a higher architecture than we know about. */
13410
9e3c6df6 13411 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13412 {
3895f852 13413 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 13414 return -1;
13415 }
13416
13417 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13418
13419 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13420 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13421 oldtag = T(V4T_PLUS_V6_M);
13422
13423 /* And override the new tag if we have a Tag_also_compatible_with on the
13424 input. */
13425
13426 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13427 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13428 newtag = T(V4T_PLUS_V6_M);
13429
13430 tagl = (oldtag < newtag) ? oldtag : newtag;
13431 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13432
13433 /* Architectures before V6KZ add features monotonically. */
13434 if (tagh <= TAG_CPU_ARCH_V6KZ)
13435 return result;
13436
4ed7ed8d 13437 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13438
13439 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13440 as the canonical version. */
13441 if (result == T(V4T_PLUS_V6_M))
13442 {
13443 result = T(V4T);
13444 *secondary_compat_out = T(V6_M);
13445 }
13446 else
13447 *secondary_compat_out = -1;
13448
13449 if (result == -1)
13450 {
3895f852 13451 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13452 ibfd, oldtag, newtag);
13453 return -1;
13454 }
13455
13456 return result;
13457#undef T
8e79c3df
CM		 13458}
13459
ac56ee8f
MGD		 13460/* Query attributes object to see if integer divide instructions may be
13461 present in an object. */
13462static bfd_boolean
13463elf32_arm_attributes_accept_div (const obj_attribute *attr)
13464{
13465 int arch = attr[Tag_CPU_arch].i;
13466 int profile = attr[Tag_CPU_arch_profile].i;
13467
13468 switch (attr[Tag_DIV_use].i)
13469 {
13470 case 0:
13471 /* Integer divide allowed if instruction contained in archetecture. */
13472 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13473 return TRUE;
13474 else if (arch >= TAG_CPU_ARCH_V7E_M)
13475 return TRUE;
13476 else
13477 return FALSE;
13478
13479 case 1:
13480 /* Integer divide explicitly prohibited. */
13481 return FALSE;
13482
13483 default:
13484 /* Unrecognised case - treat as allowing divide everywhere. */
13485 case 2:
13486 /* Integer divide allowed in ARM state. */
13487 return TRUE;
13488 }
13489}
13490
13491/* Query attributes object to see if integer divide instructions are
13492 forbidden to be in the object. This is not the inverse of
13493 elf32_arm_attributes_accept_div. */
13494static bfd_boolean
13495elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13496{
13497 return attr[Tag_DIV_use].i == 1;
13498}
13499
ee065d83
PB		 13500/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13501 are conflicting attributes. */
906e58ca 13502
ee065d83 13503static bfd_boolean
50e03d47 13504elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 13505{
50e03d47 13506 bfd *obfd = info->output_bfd;
104d59d1
JM		 13507 obj_attribute *in_attr;
13508 obj_attribute *out_attr;
ee065d83
PB		 13509 /* Some tags have 0 = don't care, 1 = strong requirement,
13510 2 = weak requirement. */
91e22acd 13511 static const int order_021[3] = {0, 2, 1};
ee065d83 13512 int i;
91e22acd 13513 bfd_boolean result = TRUE;
9274e9de 13514 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13515
3e6b1042
DJ		 13516 /* Skip the linker stubs file. This preserves previous behavior
13517 of accepting unknown attributes in the first input file - but
13518 is that a bug? */
13519 if (ibfd->flags & BFD_LINKER_CREATED)
13520 return TRUE;
13521
9274e9de
TG		 13522 /* Skip any input that hasn't attribute section.
13523 This enables to link object files without attribute section with
13524 any others. */
13525 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13526 return TRUE;
13527
104d59d1 13528 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13529 {
13530 /* This is the first object. Copy the attributes. */
104d59d1 13531 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13532
cd21e546
MGD		 13533 out_attr = elf_known_obj_attributes_proc (obfd);
13534
004ae526
PB		 13535 /* Use the Tag_null value to indicate the attributes have been
13536 initialized. */
cd21e546 13537 out_attr[0].i = 1;
004ae526 13538
cd21e546
MGD		 13539 /* We do not output objects with Tag_MPextension_use_legacy - we move
13540 the attribute's value to Tag_MPextension_use. */
13541 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13542 {
13543 if (out_attr[Tag_MPextension_use].i != 0
13544 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13545 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13546 {
13547 _bfd_error_handler
13548 (_("Error: %B has both the current and legacy "
13549 "Tag_MPextension_use attributes"), ibfd);
13550 result = FALSE;
13551 }
13552
13553 out_attr[Tag_MPextension_use] =
13554 out_attr[Tag_MPextension_use_legacy];
13555 out_attr[Tag_MPextension_use_legacy].type = 0;
13556 out_attr[Tag_MPextension_use_legacy].i = 0;
13557 }
13558
13559 return result;
ee065d83
PB		 13560 }
13561
104d59d1
JM		 13562 in_attr = elf_known_obj_attributes_proc (ibfd);
13563 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13564 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13565 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13566 {
5c294fee
TG		 13567 /* Ignore mismatches if the object doesn't use floating point or is
13568 floating point ABI independent. */
13569 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13570 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13571 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13572 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13573 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13574 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13575 {
13576 _bfd_error_handler
3895f852 13577 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13578 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13579 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13580 result = FALSE;
ee065d83
PB		 13581 }
13582 }
13583
3de4a297 13584 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13585 {
13586 /* Merge this attribute with existing attributes. */
13587 switch (i)
13588 {
13589 case Tag_CPU_raw_name:
13590 case Tag_CPU_name:
6a631e86 13591 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13592 break;
13593
13594 case Tag_ABI_optimization_goals:
13595 case Tag_ABI_FP_optimization_goals:
13596 /* Use the first value seen. */
13597 break;
13598
13599 case Tag_CPU_arch:
91e22acd
AS		 13600 {
13601 int secondary_compat = -1, secondary_compat_out = -1;
13602 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13603 int arch_attr;
13604 static const char *name_table[] =
13605 {
91e22acd
AS		 13606 /* These aren't real CPU names, but we can't guess
13607 that from the architecture version alone. */
13608 "Pre v4",
13609 "ARM v4",
13610 "ARM v4T",
13611 "ARM v5T",
13612 "ARM v5TE",
13613 "ARM v5TEJ",
13614 "ARM v6",
13615 "ARM v6KZ",
13616 "ARM v6T2",
13617 "ARM v6K",
13618 "ARM v7",
13619 "ARM v6-M",
bca38921 13620 "ARM v6S-M",
2fd158eb
TP		 13621 "ARM v8",
13622 "",
13623 "ARM v8-M.baseline",
13624 "ARM v8-M.mainline",
91e22acd
AS		 13625 };
13626
13627 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13628 secondary_compat = get_secondary_compatible_arch (ibfd);
13629 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13630 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13631 &secondary_compat_out,
13632 in_attr[i].i,
13633 secondary_compat);
13634
13635 /* Return with error if failed to merge. */
13636 if (arch_attr == -1)
13637 return FALSE;
13638
13639 out_attr[i].i = arch_attr;
13640
91e22acd
AS		 13641 set_secondary_compatible_arch (obfd, secondary_compat_out);
13642
13643 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13644 if (out_attr[i].i == saved_out_attr)
13645 ; /* Leave the names alone. */
13646 else if (out_attr[i].i == in_attr[i].i)
13647 {
13648 /* The output architecture has been changed to match the
13649 input architecture. Use the input names. */
13650 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13651 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13652 : NULL;
13653 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13654 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13655 : NULL;
13656 }
13657 else
13658 {
13659 out_attr[Tag_CPU_name].s = NULL;
13660 out_attr[Tag_CPU_raw_name].s = NULL;
13661 }
13662
13663 /* If we still don't have a value for Tag_CPU_name,
13664 make one up now. Tag_CPU_raw_name remains blank. */
13665 if (out_attr[Tag_CPU_name].s == NULL
13666 && out_attr[i].i < ARRAY_SIZE (name_table))
13667 out_attr[Tag_CPU_name].s =
13668 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13669 }
13670 break;
13671
ee065d83
PB		 13672 case Tag_ARM_ISA_use:
13673 case Tag_THUMB_ISA_use:
ee065d83 13674 case Tag_WMMX_arch:
91e22acd
AS		 13675 case Tag_Advanced_SIMD_arch:
13676 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13677 case Tag_ABI_FP_rounding:
ee065d83
PB		 13678 case Tag_ABI_FP_exceptions:
13679 case Tag_ABI_FP_user_exceptions:
13680 case Tag_ABI_FP_number_model:
75375b3e 13681 case Tag_FP_HP_extension:
91e22acd
AS		 13682 case Tag_CPU_unaligned_access:
13683 case Tag_T2EE_use:
91e22acd 13684 case Tag_MPextension_use:
ee065d83
PB		 13685 /* Use the largest value specified. */
13686 if (in_attr[i].i > out_attr[i].i)
13687 out_attr[i].i = in_attr[i].i;
13688 break;
13689
75375b3e 13690 case Tag_ABI_align_preserved:
91e22acd
AS		 13691 case Tag_ABI_PCS_RO_data:
13692 /* Use the smallest value specified. */
13693 if (in_attr[i].i < out_attr[i].i)
13694 out_attr[i].i = in_attr[i].i;
13695 break;
13696
75375b3e 13697 case Tag_ABI_align_needed:
91e22acd 13698 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13699 && (in_attr[Tag_ABI_align_preserved].i == 0
13700 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13701 {
91e22acd
AS		 13702 /* This error message should be enabled once all non-conformant
13703 binaries in the toolchain have had the attributes set
13704 properly.
ee065d83 13705 _bfd_error_handler
3895f852 13706 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13707 obfd, ibfd);
13708 result = FALSE; */
ee065d83 13709 }
91e22acd
AS		 13710 /* Fall through. */
13711 case Tag_ABI_FP_denormal:
13712 case Tag_ABI_PCS_GOT_use:
13713 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13714 value if greater than 2 (for future-proofing). */
13715 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13716 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13717 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13718 out_attr[i].i = in_attr[i].i;
13719 break;
91e22acd 13720
75375b3e
MGD		 13721 case Tag_Virtualization_use:
13722 /* The virtualization tag effectively stores two bits of
13723 information: the intended use of TrustZone (in bit 0), and the
13724 intended use of Virtualization (in bit 1). */
13725 if (out_attr[i].i == 0)
13726 out_attr[i].i = in_attr[i].i;
13727 else if (in_attr[i].i != 0
13728 && in_attr[i].i != out_attr[i].i)
13729 {
13730 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13731 out_attr[i].i = 3;
13732 else
13733 {
13734 _bfd_error_handler
13735 (_("error: %B: unable to merge virtualization attributes "
13736 "with %B"),
13737 obfd, ibfd);
13738 result = FALSE;
13739 }
13740 }
13741 break;
91e22acd
AS		 13742
13743 case Tag_CPU_arch_profile:
13744 if (out_attr[i].i != in_attr[i].i)
13745 {
13746 /* 0 will merge with anything.
13747 'A' and 'S' merge to 'A'.
13748 'R' and 'S' merge to 'R'.
99059e56 13749 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13750 if (out_attr[i].i == 0
13751 || (out_attr[i].i == 'S'
13752 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13753 out_attr[i].i = in_attr[i].i;
13754 else if (in_attr[i].i == 0
13755 || (in_attr[i].i == 'S'
13756 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13757 ; /* Do nothing. */
91e22acd
AS		 13758 else
13759 {
13760 _bfd_error_handler
3895f852 13761 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13762 ibfd,
13763 in_attr[i].i ? in_attr[i].i : '0',
13764 out_attr[i].i ? out_attr[i].i : '0');
13765 result = FALSE;
13766 }
13767 }
13768 break;
15afaa63
TP		 13769
13770 case Tag_DSP_extension:
13771 /* No need to change output value if any of:
13772 - pre (<=) ARMv5T input architecture (do not have DSP)
13773 - M input profile not ARMv7E-M and do not have DSP. */
13774 if (in_attr[Tag_CPU_arch].i <= 3
13775 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13776 && in_attr[Tag_CPU_arch].i != 13
13777 && in_attr[i].i == 0))
13778 ; /* Do nothing. */
13779 /* Output value should be 0 if DSP part of architecture, ie.
13780 - post (>=) ARMv5te architecture output
13781 - A, R or S profile output or ARMv7E-M output architecture. */
13782 else if (out_attr[Tag_CPU_arch].i >= 4
13783 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13784 || out_attr[Tag_CPU_arch_profile].i == 'R'
13785 || out_attr[Tag_CPU_arch_profile].i == 'S'
13786 || out_attr[Tag_CPU_arch].i == 13))
13787 out_attr[i].i = 0;
13788 /* Otherwise, DSP instructions are added and not part of output
13789 architecture. */
13790 else
13791 out_attr[i].i = 1;
13792 break;
13793
75375b3e 13794 case Tag_FP_arch:
62f3b8c8 13795 {
4547cb56
NC		 13796 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13797 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13798 when it's 0. It might mean absence of FP hardware if
99654aaf 13799 Tag_FP_arch is zero. */
4547cb56 13800
a715796b 13801#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13802 static const struct
13803 {
13804 int ver;
13805 int regs;
bca38921 13806 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13807 {
13808 {0, 0},
13809 {1, 16},
13810 {2, 16},
13811 {3, 32},
13812 {3, 16},
13813 {4, 32},
bca38921 13814 {4, 16},
a715796b
TG		 13815 {8, 32},
13816 {8, 16}
62f3b8c8
PB		 13817 };
13818 int ver;
13819 int regs;
13820 int newval;
13821
4547cb56
NC		 13822 /* If the output has no requirement about FP hardware,
13823 follow the requirement of the input. */
13824 if (out_attr[i].i == 0)
13825 {
13826 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13827 out_attr[i].i = in_attr[i].i;
13828 out_attr[Tag_ABI_HardFP_use].i
13829 = in_attr[Tag_ABI_HardFP_use].i;
13830 break;
13831 }
13832 /* If the input has no requirement about FP hardware, do
13833 nothing. */
13834 else if (in_attr[i].i == 0)
13835 {
13836 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
13837 break;
13838 }
13839
13840 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13841 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13842
13843 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13844 do nothing. */
13845 if (in_attr[Tag_ABI_HardFP_use].i == 0
13846 && out_attr[Tag_ABI_HardFP_use].i == 0)
13847 ;
13848 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13849 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13850 else if (in_attr[Tag_ABI_HardFP_use].i
13851 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13852 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13853
13854 /* Now we can handle Tag_FP_arch. */
13855
bca38921
MGD		 13856 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13857 pick the biggest. */
13858 if (in_attr[i].i >= VFP_VERSION_COUNT
13859 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13860 {
13861 out_attr[i] = in_attr[i];
13862 break;
13863 }
13864 /* The output uses the superset of input features
13865 (ISA version) and registers. */
13866 ver = vfp_versions[in_attr[i].i].ver;
13867 if (ver < vfp_versions[out_attr[i].i].ver)
13868 ver = vfp_versions[out_attr[i].i].ver;
13869 regs = vfp_versions[in_attr[i].i].regs;
13870 if (regs < vfp_versions[out_attr[i].i].regs)
13871 regs = vfp_versions[out_attr[i].i].regs;
13872 /* This assumes all possible supersets are also a valid
99059e56 13873 options. */
bca38921 13874 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13875 {
13876 if (regs == vfp_versions[newval].regs
13877 && ver == vfp_versions[newval].ver)
13878 break;
13879 }
13880 out_attr[i].i = newval;
13881 }
b1cc4aeb 13882 break;
ee065d83
PB		 13883 case Tag_PCS_config:
13884 if (out_attr[i].i == 0)
13885 out_attr[i].i = in_attr[i].i;
b6009aca 13886 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13887 {
13888 /* It's sometimes ok to mix different configs, so this is only
99059e56 13889 a warning. */
ee065d83
PB		 13890 _bfd_error_handler
13891 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13892 }
13893 break;
13894 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13895 if (in_attr[i].i != out_attr[i].i
13896 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13897 && in_attr[i].i != AEABI_R9_unused)
13898 {
13899 _bfd_error_handler
3895f852 13900 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13901 result = FALSE;
ee065d83
PB		 13902 }
13903 if (out_attr[i].i == AEABI_R9_unused)
13904 out_attr[i].i = in_attr[i].i;
13905 break;
13906 case Tag_ABI_PCS_RW_data:
13907 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13908 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13909 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13910 {
13911 _bfd_error_handler
3895f852 13912 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13913 ibfd);
91e22acd 13914 result = FALSE;
ee065d83
PB		 13915 }
13916 /* Use the smallest value specified. */
13917 if (in_attr[i].i < out_attr[i].i)
13918 out_attr[i].i = in_attr[i].i;
13919 break;
ee065d83 13920 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13921 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13922 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13923 {
13924 _bfd_error_handler
a9dc9481
JM		 13925 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13926 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13927 }
a9dc9481 13928 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13929 out_attr[i].i = in_attr[i].i;
13930 break;
ee065d83
PB		 13931 case Tag_ABI_enum_size:
13932 if (in_attr[i].i != AEABI_enum_unused)
13933 {
13934 if (out_attr[i].i == AEABI_enum_unused
13935 || out_attr[i].i == AEABI_enum_forced_wide)
13936 {
13937 /* The existing object is compatible with anything.
13938 Use whatever requirements the new object has. */
13939 out_attr[i].i = in_attr[i].i;
13940 }
13941 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13942 && out_attr[i].i != in_attr[i].i
0ffa91dd 13943 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13944 {
91e22acd 13945 static const char *aeabi_enum_names[] =
bf21ed78 13946 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13947 const char *in_name =
13948 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13949 ? aeabi_enum_names[in_attr[i].i]
13950 : "<unknown>";
13951 const char *out_name =
13952 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13953 ? aeabi_enum_names[out_attr[i].i]
13954 : "<unknown>";
ee065d83 13955 _bfd_error_handler
bf21ed78 13956 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13957 ibfd, in_name, out_name);
ee065d83
PB		 13958 }
13959 }
13960 break;
13961 case Tag_ABI_VFP_args:
13962 /* Aready done. */
13963 break;
13964 case Tag_ABI_WMMX_args:
13965 if (in_attr[i].i != out_attr[i].i)
13966 {
13967 _bfd_error_handler
3895f852 13968 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13969 ibfd, obfd);
91e22acd 13970 result = FALSE;
ee065d83
PB		 13971 }
13972 break;
7b86a9fa
AS		 13973 case Tag_compatibility:
13974 /* Merged in target-independent code. */
13975 break;
91e22acd 13976 case Tag_ABI_HardFP_use:
4547cb56 13977 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13978 break;
13979 case Tag_ABI_FP_16bit_format:
13980 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13981 {
13982 if (in_attr[i].i != out_attr[i].i)
13983 {
13984 _bfd_error_handler
3895f852 13985 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13986 ibfd, obfd);
13987 result = FALSE;
13988 }
13989 }
13990 if (in_attr[i].i != 0)
13991 out_attr[i].i = in_attr[i].i;
13992 break;
7b86a9fa 13993
cd21e546 13994 case Tag_DIV_use:
ac56ee8f
MGD		 13995 /* A value of zero on input means that the divide instruction may
13996 be used if available in the base architecture as specified via
13997 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
13998 the user did not want divide instructions. A value of 2
13999 explicitly means that divide instructions were allowed in ARM
14000 and Thumb state. */
14001 if (in_attr[i].i == out_attr[i].i)
14002 /* Do nothing. */ ;
14003 else if (elf32_arm_attributes_forbid_div (in_attr)
14004 && !elf32_arm_attributes_accept_div (out_attr))
14005 out_attr[i].i = 1;
14006 else if (elf32_arm_attributes_forbid_div (out_attr)
14007 && elf32_arm_attributes_accept_div (in_attr))
14008 out_attr[i].i = in_attr[i].i;
14009 else if (in_attr[i].i == 2)
14010 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14011 break;
14012
14013 case Tag_MPextension_use_legacy:
14014 /* We don't output objects with Tag_MPextension_use_legacy - we
14015 move the value to Tag_MPextension_use. */
14016 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14017 {
14018 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14019 {
14020 _bfd_error_handler
14021 (_("%B has has both the current and legacy "
b38cadfb 14022 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14023 ibfd);
14024 result = FALSE;
14025 }
14026 }
14027
14028 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14029 out_attr[Tag_MPextension_use] = in_attr[i];
14030
14031 break;
14032
91e22acd 14033 case Tag_nodefaults:
2d0bb761
AS		 14034 /* This tag is set if it exists, but the value is unused (and is
14035 typically zero). We don't actually need to do anything here -
14036 the merge happens automatically when the type flags are merged
14037 below. */
91e22acd
AS		 14038 break;
14039 case Tag_also_compatible_with:
14040 /* Already done in Tag_CPU_arch. */
14041 break;
14042 case Tag_conformance:
14043 /* Keep the attribute if it matches. Throw it away otherwise.
14044 No attribute means no claim to conform. */
14045 if (!in_attr[i].s || !out_attr[i].s
14046 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14047 out_attr[i].s = NULL;
14048 break;
3cfad14c 14049
91e22acd 14050 default:
e8b36cd1
JM		 14051 result
14052 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14053 }
14054
14055 /* If out_attr was copied from in_attr then it won't have a type yet. */
14056 if (in_attr[i].type && !out_attr[i].type)
14057 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14058 }
14059
104d59d1 14060 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14061 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14062 return FALSE;
ee065d83 14063
104d59d1 14064 /* Check for any attributes not known on ARM. */
e8b36cd1 14065 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14066
91e22acd 14067 return result;
252b5132
RH		 14068}
14069
3a4a14e9
PB		 14070
14071/* Return TRUE if the two EABI versions are incompatible. */
14072
14073static bfd_boolean
14074elf32_arm_versions_compatible (unsigned iver, unsigned over)
14075{
14076 /* v4 and v5 are the same spec before and after it was released,
14077 so allow mixing them. */
14078 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14079 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14080 return TRUE;
14081
14082 return (iver == over);
14083}
14084
252b5132
RH		 14085/* Merge backend specific data from an object file to the output
14086 object file when linking. */
9b485d32 14087
b34976b6 14088static bfd_boolean
50e03d47 14089elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14090
9b485d32
NC		 14091/* Display the flags field. */
14092
b34976b6 14093static bfd_boolean
57e8b36a 14094elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14095{
fc830a83
NC		 14096 FILE * file = (FILE *) ptr;
14097 unsigned long flags;
252b5132
RH		 14098
14099 BFD_ASSERT (abfd != NULL && ptr != NULL);
14100
14101 /* Print normal ELF private data. */
14102 _bfd_elf_print_private_bfd_data (abfd, ptr);
14103
fc830a83 14104 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14105 /* Ignore init flag - it may not be set, despite the flags field
14106 containing valid data. */
252b5132 14107
9b485d32 14108 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14109
fc830a83
NC		 14110 switch (EF_ARM_EABI_VERSION (flags))
14111 {
14112 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14113 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14114 official ARM ELF extended ABI. Hence they are only decoded if
14115 the EABI version is not set. */
fd2ec330 14116 if (flags & EF_ARM_INTERWORK)
9b485d32 14117 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14118
fd2ec330 14119 if (flags & EF_ARM_APCS_26)
6c571f00 14120 fprintf (file, " [APCS-26]");
fc830a83 14121 else
6c571f00 14122 fprintf (file, " [APCS-32]");
9a5aca8c 14123
96a846ea
RE		 14124 if (flags & EF_ARM_VFP_FLOAT)
14125 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14126 else if (flags & EF_ARM_MAVERICK_FLOAT)
14127 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14128 else
14129 fprintf (file, _(" [FPA float format]"));
14130
fd2ec330 14131 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14132 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14133
fd2ec330 14134 if (flags & EF_ARM_PIC)
9b485d32 14135 fprintf (file, _(" [position independent]"));
fc830a83 14136
fd2ec330 14137 if (flags & EF_ARM_NEW_ABI)
9b485d32 14138 fprintf (file, _(" [new ABI]"));
9a5aca8c 14139
fd2ec330 14140 if (flags & EF_ARM_OLD_ABI)
9b485d32 14141 fprintf (file, _(" [old ABI]"));
9a5aca8c 14142
fd2ec330 14143 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14144 fprintf (file, _(" [software FP]"));
9a5aca8c 14145
96a846ea
RE		 14146 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14147 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14148 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14149 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14150 break;
9a5aca8c 14151
fc830a83 14152 case EF_ARM_EABI_VER1:
9b485d32 14153 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14154
fc830a83 14155 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14156 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14157 else
9b485d32 14158 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14159
fc830a83
NC		 14160 flags &= ~ EF_ARM_SYMSARESORTED;
14161 break;
9a5aca8c 14162
fd2ec330
PB		 14163 case EF_ARM_EABI_VER2:
14164 fprintf (file, _(" [Version2 EABI]"));
14165
14166 if (flags & EF_ARM_SYMSARESORTED)
14167 fprintf (file, _(" [sorted symbol table]"));
14168 else
14169 fprintf (file, _(" [unsorted symbol table]"));
14170
14171 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14172 fprintf (file, _(" [dynamic symbols use segment index]"));
14173
14174 if (flags & EF_ARM_MAPSYMSFIRST)
14175 fprintf (file, _(" [mapping symbols precede others]"));
14176
99e4ae17 14177 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14178 | EF_ARM_MAPSYMSFIRST);
14179 break;
14180
d507cf36
PB		 14181 case EF_ARM_EABI_VER3:
14182 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14183 break;
14184
14185 case EF_ARM_EABI_VER4:
14186 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14187 goto eabi;
d507cf36 14188
3a4a14e9
PB		 14189 case EF_ARM_EABI_VER5:
14190 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14191
14192 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14193 fprintf (file, _(" [soft-float ABI]"));
14194
14195 if (flags & EF_ARM_ABI_FLOAT_HARD)
14196 fprintf (file, _(" [hard-float ABI]"));
14197
14198 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14199
3a4a14e9 14200 eabi:
d507cf36
PB		 14201 if (flags & EF_ARM_BE8)
14202 fprintf (file, _(" [BE8]"));
14203
14204 if (flags & EF_ARM_LE8)
14205 fprintf (file, _(" [LE8]"));
14206
14207 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14208 break;
14209
fc830a83 14210 default:
9b485d32 14211 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14212 break;
14213 }
252b5132 14214
fc830a83 14215 flags &= ~ EF_ARM_EABIMASK;
252b5132 14216
fc830a83 14217 if (flags & EF_ARM_RELEXEC)
9b485d32 14218 fprintf (file, _(" [relocatable executable]"));
252b5132 14219
a5721edd 14220 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14221
14222 if (flags)
9b485d32 14223 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14224
252b5132
RH		 14225 fputc ('\n', file);
14226
b34976b6 14227 return TRUE;
252b5132
RH		 14228}
14229
14230static int
57e8b36a 14231elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14232{
2f0ca46a
NC		 14233 switch (ELF_ST_TYPE (elf_sym->st_info))
14234 {
14235 case STT_ARM_TFUNC:
14236 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14237
2f0ca46a
NC		 14238 case STT_ARM_16BIT:
14239 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14240 This allows us to distinguish between data used by Thumb instructions
14241 and non-data (which is probably code) inside Thumb regions of an
14242 executable. */
1a0eb693 14243 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14244 return ELF_ST_TYPE (elf_sym->st_info);
14245 break;
9a5aca8c 14246
ce855c42
NC		 14247 default:
14248 break;
2f0ca46a
NC		 14249 }
14250
14251 return type;
252b5132 14252}
f21f3fe0 14253
252b5132 14254static asection *
07adf181
AM		 14255elf32_arm_gc_mark_hook (asection *sec,
14256 struct bfd_link_info *info,
14257 Elf_Internal_Rela *rel,
14258 struct elf_link_hash_entry *h,
14259 Elf_Internal_Sym *sym)
252b5132
RH		 14260{
14261 if (h != NULL)
07adf181 14262 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14263 {
14264 case R_ARM_GNU_VTINHERIT:
14265 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14266 return NULL;
14267 }
9ad5cbcf 14268
07adf181 14269 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14270}
14271
780a67af
NC		 14272/* Update the got entry reference counts for the section being removed. */
14273
b34976b6 14274static bfd_boolean
ba93b8ac
DJ		 14275elf32_arm_gc_sweep_hook (bfd * abfd,
14276 struct bfd_link_info * info,
14277 asection * sec,
14278 const Elf_Internal_Rela * relocs)
252b5132 14279{
5e681ec4
PB		 14280 Elf_Internal_Shdr *symtab_hdr;
14281 struct elf_link_hash_entry **sym_hashes;
14282 bfd_signed_vma *local_got_refcounts;
14283 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 14284 struct elf32_arm_link_hash_table * globals;
14285
0e1862bb 14286 if (bfd_link_relocatable (info))
7dda2462
TG		 14287 return TRUE;
14288
eb043451 14289 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14290 if (globals == NULL)
14291 return FALSE;
5e681ec4
PB		 14292
14293 elf_section_data (sec)->local_dynrel = NULL;
14294
0ffa91dd 14295 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 14296 sym_hashes = elf_sym_hashes (abfd);
14297 local_got_refcounts = elf_local_got_refcounts (abfd);
14298
906e58ca 14299 check_use_blx (globals);
bd97cb95 14300
5e681ec4
PB		 14301 relend = relocs + sec->reloc_count;
14302 for (rel = relocs; rel < relend; rel++)
eb043451 14303 {
3eb128b2
AM		 14304 unsigned long r_symndx;
14305 struct elf_link_hash_entry *h = NULL;
f6e32f6d 14306 struct elf32_arm_link_hash_entry *eh;
eb043451 14307 int r_type;
34e77a92 14308 bfd_boolean call_reloc_p;
f6e32f6d
RS		 14309 bfd_boolean may_become_dynamic_p;
14310 bfd_boolean may_need_local_target_p;
34e77a92
RS		 14311 union gotplt_union *root_plt;
14312 struct arm_plt_info *arm_plt;
5e681ec4 14313
3eb128b2
AM		 14314 r_symndx = ELF32_R_SYM (rel->r_info);
14315 if (r_symndx >= symtab_hdr->sh_info)
14316 {
14317 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14318 while (h->root.type == bfd_link_hash_indirect
14319 || h->root.type == bfd_link_hash_warning)
14320 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14321 }
f6e32f6d
RS		 14322 eh = (struct elf32_arm_link_hash_entry *) h;
14323
34e77a92 14324 call_reloc_p = FALSE;
f6e32f6d
RS		 14325 may_become_dynamic_p = FALSE;
14326 may_need_local_target_p = FALSE;
3eb128b2 14327
eb043451 14328 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14329 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 14330 switch (r_type)
14331 {
14332 case R_ARM_GOT32:
eb043451 14333 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14334 case R_ARM_TLS_GD32:
14335 case R_ARM_TLS_IE32:
3eb128b2 14336 if (h != NULL)
eb043451 14337 {
eb043451
PB		 14338 if (h->got.refcount > 0)
14339 h->got.refcount -= 1;
14340 }
14341 else if (local_got_refcounts != NULL)
14342 {
14343 if (local_got_refcounts[r_symndx] > 0)
14344 local_got_refcounts[r_symndx] -= 1;
14345 }
14346 break;
14347
ba93b8ac 14348 case R_ARM_TLS_LDM32:
4dfe6ac6 14349 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 14350 break;
14351
eb043451
PB		 14352 case R_ARM_PC24:
14353 case R_ARM_PLT32:
5b5bb741
PB		 14354 case R_ARM_CALL:
14355 case R_ARM_JUMP24:
eb043451 14356 case R_ARM_PREL31:
c19d1205 14357 case R_ARM_THM_CALL:
bd97cb95
DJ		 14358 case R_ARM_THM_JUMP24:
14359 case R_ARM_THM_JUMP19:
34e77a92 14360 call_reloc_p = TRUE;
f6e32f6d
RS		 14361 may_need_local_target_p = TRUE;
14362 break;
14363
14364 case R_ARM_ABS12:
14365 if (!globals->vxworks_p)
14366 {
14367 may_need_local_target_p = TRUE;
14368 break;
14369 }
14370 /* Fall through. */
14371 case R_ARM_ABS32:
14372 case R_ARM_ABS32_NOI:
14373 case R_ARM_REL32:
14374 case R_ARM_REL32_NOI:
b6895b4f
PB		 14375 case R_ARM_MOVW_ABS_NC:
14376 case R_ARM_MOVT_ABS:
14377 case R_ARM_MOVW_PREL_NC:
14378 case R_ARM_MOVT_PREL:
14379 case R_ARM_THM_MOVW_ABS_NC:
14380 case R_ARM_THM_MOVT_ABS:
14381 case R_ARM_THM_MOVW_PREL_NC:
14382 case R_ARM_THM_MOVT_PREL:
b7693d02 14383 /* Should the interworking branches be here also? */
0e1862bb 14384 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 14385 && (sec->flags & SEC_ALLOC) != 0)
14386 {
14387 if (h == NULL
469a3493 14388 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14389 {
14390 call_reloc_p = TRUE;
14391 may_need_local_target_p = TRUE;
14392 }
14393 else
14394 may_become_dynamic_p = TRUE;
14395 }
f6e32f6d
RS		 14396 else
14397 may_need_local_target_p = TRUE;
14398 break;
b7693d02 14399
f6e32f6d
RS		 14400 default:
14401 break;
14402 }
5e681ec4 14403
34e77a92 14404 if (may_need_local_target_p
4ba2ef8f
TP		 14405 && elf32_arm_get_plt_info (abfd, globals, eh, r_symndx, &root_plt,
14406 &arm_plt))
f6e32f6d 14407 {
27586251
HPN		 14408 /* If PLT refcount book-keeping is wrong and too low, we'll
14409 see a zero value (going to -1) for the root PLT reference
14410 count. */
14411 if (root_plt->refcount >= 0)
14412 {
14413 BFD_ASSERT (root_plt->refcount != 0);
14414 root_plt->refcount -= 1;
14415 }
14416 else
14417 /* A value of -1 means the symbol has become local, forced
14418 or seeing a hidden definition. Any other negative value
14419 is an error. */
14420 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 14421
14422 if (!call_reloc_p)
14423 arm_plt->noncall_refcount--;
5e681ec4 14424
f6e32f6d 14425 if (r_type == R_ARM_THM_CALL)
34e77a92 14426 arm_plt->maybe_thumb_refcount--;
bd97cb95 14427
f6e32f6d
RS		 14428 if (r_type == R_ARM_THM_JUMP24
14429 || r_type == R_ARM_THM_JUMP19)
34e77a92 14430 arm_plt->thumb_refcount--;
f6e32f6d 14431 }
5e681ec4 14432
34e77a92 14433 if (may_become_dynamic_p)
f6e32f6d
RS		 14434 {
14435 struct elf_dyn_relocs **pp;
14436 struct elf_dyn_relocs *p;
5e681ec4 14437
34e77a92 14438 if (h != NULL)
9c489990 14439 pp = &(eh->dyn_relocs);
34e77a92
RS		 14440 else
14441 {
14442 Elf_Internal_Sym *isym;
14443
14444 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
14445 abfd, r_symndx);
14446 if (isym == NULL)
14447 return FALSE;
14448 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14449 if (pp == NULL)
14450 return FALSE;
14451 }
9c489990 14452 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 14453 if (p->sec == sec)
14454 {
14455 /* Everything must go for SEC. */
14456 *pp = p->next;
14457 break;
14458 }
eb043451
PB		 14459 }
14460 }
5e681ec4 14461
b34976b6 14462 return TRUE;
252b5132
RH		 14463}
14464
780a67af
NC		 14465/* Look through the relocs for a section during the first phase. */
14466
b34976b6 14467static bfd_boolean
57e8b36a
NC		 14468elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14469 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14470{
b34976b6
AM		 14471 Elf_Internal_Shdr *symtab_hdr;
14472 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14473 const Elf_Internal_Rela *rel;
14474 const Elf_Internal_Rela *rel_end;
14475 bfd *dynobj;
5e681ec4 14476 asection *sreloc;
5e681ec4 14477 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14478 bfd_boolean call_reloc_p;
14479 bfd_boolean may_become_dynamic_p;
14480 bfd_boolean may_need_local_target_p;
ce98a316 14481 unsigned long nsyms;
9a5aca8c 14482
0e1862bb 14483 if (bfd_link_relocatable (info))
b34976b6 14484 return TRUE;
9a5aca8c 14485
0ffa91dd
NC		 14486 BFD_ASSERT (is_arm_elf (abfd));
14487
5e681ec4 14488 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14489 if (htab == NULL)
14490 return FALSE;
14491
5e681ec4 14492 sreloc = NULL;
9a5aca8c 14493
67687978
PB		 14494 /* Create dynamic sections for relocatable executables so that we can
14495 copy relocations. */
14496 if (htab->root.is_relocatable_executable
14497 && ! htab->root.dynamic_sections_created)
14498 {
14499 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14500 return FALSE;
14501 }
14502
cbc704f3
RS		 14503 if (htab->root.dynobj == NULL)
14504 htab->root.dynobj = abfd;
34e77a92
RS		 14505 if (!create_ifunc_sections (info))
14506 return FALSE;
cbc704f3
RS		 14507
14508 dynobj = htab->root.dynobj;
14509
0ffa91dd 14510 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14511 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14512 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14513
252b5132
RH		 14514 rel_end = relocs + sec->reloc_count;
14515 for (rel = relocs; rel < rel_end; rel++)
14516 {
34e77a92 14517 Elf_Internal_Sym *isym;
252b5132 14518 struct elf_link_hash_entry *h;
b7693d02 14519 struct elf32_arm_link_hash_entry *eh;
252b5132 14520 unsigned long r_symndx;
eb043451 14521 int r_type;
9a5aca8c 14522
252b5132 14523 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14524 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14525 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14526
ce98a316
NC		 14527 if (r_symndx >= nsyms
14528 /* PR 9934: It is possible to have relocations that do not
14529 refer to symbols, thus it is also possible to have an
14530 object file containing relocations but no symbol table. */
cf35638d 14531 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14532 {
4eca0228
AM		 14533 _bfd_error_handler (_("%B: bad symbol index: %d"), abfd,
14534 r_symndx);
ba93b8ac
DJ		 14535 return FALSE;
14536 }
14537
34e77a92
RS		 14538 h = NULL;
14539 isym = NULL;
14540 if (nsyms > 0)
973a3492 14541 {
34e77a92
RS		 14542 if (r_symndx < symtab_hdr->sh_info)
14543 {
14544 /* A local symbol. */
14545 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14546 abfd, r_symndx);
14547 if (isym == NULL)
14548 return FALSE;
14549 }
14550 else
14551 {
14552 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14553 while (h->root.type == bfd_link_hash_indirect
14554 || h->root.type == bfd_link_hash_warning)
14555 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 14556
14557 /* PR15323, ref flags aren't set for references in the
14558 same object. */
14559 h->root.non_ir_ref = 1;
34e77a92 14560 }
973a3492 14561 }
9a5aca8c 14562
b7693d02
DJ		 14563 eh = (struct elf32_arm_link_hash_entry *) h;
14564
f6e32f6d
RS		 14565 call_reloc_p = FALSE;
14566 may_become_dynamic_p = FALSE;
14567 may_need_local_target_p = FALSE;
14568
0855e32b
NS		 14569 /* Could be done earlier, if h were already available. */
14570 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14571 switch (r_type)
99059e56 14572 {
5e681ec4 14573 case R_ARM_GOT32:
eb043451 14574 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14575 case R_ARM_TLS_GD32:
14576 case R_ARM_TLS_IE32:
0855e32b
NS		 14577 case R_ARM_TLS_GOTDESC:
14578 case R_ARM_TLS_DESCSEQ:
14579 case R_ARM_THM_TLS_DESCSEQ:
14580 case R_ARM_TLS_CALL:
14581 case R_ARM_THM_TLS_CALL:
5e681ec4 14582 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14583 {
14584 int tls_type, old_tls_type;
5e681ec4 14585
ba93b8ac
DJ		 14586 switch (r_type)
14587 {
14588 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14589
ba93b8ac 14590 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14591
0855e32b
NS		 14592 case R_ARM_TLS_GOTDESC:
14593 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14594 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14595 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14596
ba93b8ac
DJ		 14597 default: tls_type = GOT_NORMAL; break;
14598 }
252b5132 14599
0e1862bb 14600 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14601 info->flags |= DF_STATIC_TLS;
14602
ba93b8ac
DJ		 14603 if (h != NULL)
14604 {
14605 h->got.refcount++;
14606 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14607 }
14608 else
14609 {
ba93b8ac 14610 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14611 if (!elf32_arm_allocate_local_sym_info (abfd))
14612 return FALSE;
14613 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14614 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14615 }
14616
0855e32b 14617 /* If a variable is accessed with both tls methods, two
99059e56 14618 slots may be created. */
0855e32b
NS		 14619 if (GOT_TLS_GD_ANY_P (old_tls_type)
14620 && GOT_TLS_GD_ANY_P (tls_type))
14621 tls_type |= old_tls_type;
14622
14623 /* We will already have issued an error message if there
14624 is a TLS/non-TLS mismatch, based on the symbol
14625 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14626 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14627 && tls_type != GOT_NORMAL)
14628 tls_type |= old_tls_type;
14629
0855e32b 14630 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14631 method, we're able to relax. Turn off the GDESC flag,
14632 without messing up with any other kind of tls types
6a631e86 14633 that may be involved. */
0855e32b
NS		 14634 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14635 tls_type &= ~GOT_TLS_GDESC;
14636
ba93b8ac
DJ		 14637 if (old_tls_type != tls_type)
14638 {
14639 if (h != NULL)
14640 elf32_arm_hash_entry (h)->tls_type = tls_type;
14641 else
14642 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14643 }
14644 }
8029a119 14645 /* Fall through. */
ba93b8ac
DJ		 14646
14647 case R_ARM_TLS_LDM32:
14648 if (r_type == R_ARM_TLS_LDM32)
14649 htab->tls_ldm_got.refcount++;
8029a119 14650 /* Fall through. */
252b5132 14651
c19d1205 14652 case R_ARM_GOTOFF32:
5e681ec4 14653 case R_ARM_GOTPC:
cbc704f3
RS		 14654 if (htab->root.sgot == NULL
14655 && !create_got_section (htab->root.dynobj, info))
14656 return FALSE;
252b5132
RH		 14657 break;
14658
252b5132 14659 case R_ARM_PC24:
7359ea65 14660 case R_ARM_PLT32:
5b5bb741
PB		 14661 case R_ARM_CALL:
14662 case R_ARM_JUMP24:
eb043451 14663 case R_ARM_PREL31:
c19d1205 14664 case R_ARM_THM_CALL:
bd97cb95
DJ		 14665 case R_ARM_THM_JUMP24:
14666 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14667 call_reloc_p = TRUE;
14668 may_need_local_target_p = TRUE;
14669 break;
14670
14671 case R_ARM_ABS12:
14672 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14673 ldr __GOTT_INDEX__ offsets. */
14674 if (!htab->vxworks_p)
14675 {
14676 may_need_local_target_p = TRUE;
14677 break;
14678 }
aebf9be7 14679 else goto jump_over;
9eaff861 14680
f6e32f6d 14681 /* Fall through. */
39623e12 14682
96c23d59
JM		 14683 case R_ARM_MOVW_ABS_NC:
14684 case R_ARM_MOVT_ABS:
14685 case R_ARM_THM_MOVW_ABS_NC:
14686 case R_ARM_THM_MOVT_ABS:
0e1862bb 14687 if (bfd_link_pic (info))
96c23d59 14688 {
4eca0228 14689 _bfd_error_handler
96c23d59
JM		 14690 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14691 abfd, elf32_arm_howto_table_1[r_type].name,
14692 (h) ? h->root.root.string : "a local symbol");
14693 bfd_set_error (bfd_error_bad_value);
14694 return FALSE;
14695 }
14696
14697 /* Fall through. */
39623e12
PB		 14698 case R_ARM_ABS32:
14699 case R_ARM_ABS32_NOI:
aebf9be7 14700 jump_over:
0e1862bb 14701 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14702 {
14703 h->pointer_equality_needed = 1;
14704 }
14705 /* Fall through. */
39623e12
PB		 14706 case R_ARM_REL32:
14707 case R_ARM_REL32_NOI:
b6895b4f
PB		 14708 case R_ARM_MOVW_PREL_NC:
14709 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14710 case R_ARM_THM_MOVW_PREL_NC:
14711 case R_ARM_THM_MOVT_PREL:
39623e12 14712
b7693d02 14713 /* Should the interworking branches be listed here? */
0e1862bb 14714 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14715 && (sec->flags & SEC_ALLOC) != 0)
14716 {
14717 if (h == NULL
469a3493 14718 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14719 {
14720 /* In shared libraries and relocatable executables,
14721 we treat local relative references as calls;
14722 see the related SYMBOL_CALLS_LOCAL code in
14723 allocate_dynrelocs. */
14724 call_reloc_p = TRUE;
14725 may_need_local_target_p = TRUE;
14726 }
14727 else
14728 /* We are creating a shared library or relocatable
14729 executable, and this is a reloc against a global symbol,
14730 or a non-PC-relative reloc against a local symbol.
14731 We may need to copy the reloc into the output. */
14732 may_become_dynamic_p = TRUE;
14733 }
f6e32f6d
RS		 14734 else
14735 may_need_local_target_p = TRUE;
252b5132
RH		 14736 break;
14737
99059e56
RM		 14738 /* This relocation describes the C++ object vtable hierarchy.
14739 Reconstruct it for later use during GC. */
14740 case R_ARM_GNU_VTINHERIT:
14741 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14742 return FALSE;
14743 break;
14744
14745 /* This relocation describes which C++ vtable entries are actually
14746 used. Record for later use during GC. */
14747 case R_ARM_GNU_VTENTRY:
14748 BFD_ASSERT (h != NULL);
14749 if (h != NULL
14750 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14751 return FALSE;
14752 break;
14753 }
f6e32f6d
RS		 14754
14755 if (h != NULL)
14756 {
14757 if (call_reloc_p)
14758 /* We may need a .plt entry if the function this reloc
14759 refers to is in a different object, regardless of the
14760 symbol's type. We can't tell for sure yet, because
14761 something later might force the symbol local. */
14762 h->needs_plt = 1;
14763 else if (may_need_local_target_p)
14764 /* If this reloc is in a read-only section, we might
14765 need a copy reloc. We can't check reliably at this
14766 stage whether the section is read-only, as input
14767 sections have not yet been mapped to output sections.
14768 Tentatively set the flag for now, and correct in
14769 adjust_dynamic_symbol. */
14770 h->non_got_ref = 1;
14771 }
14772
34e77a92
RS		 14773 if (may_need_local_target_p
14774 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14775 {
34e77a92
RS		 14776 union gotplt_union *root_plt;
14777 struct arm_plt_info *arm_plt;
14778 struct arm_local_iplt_info *local_iplt;
14779
14780 if (h != NULL)
14781 {
14782 root_plt = &h->plt;
14783 arm_plt = &eh->plt;
14784 }
14785 else
14786 {
14787 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14788 if (local_iplt == NULL)
14789 return FALSE;
14790 root_plt = &local_iplt->root;
14791 arm_plt = &local_iplt->arm;
14792 }
14793
f6e32f6d
RS		 14794 /* If the symbol is a function that doesn't bind locally,
14795 this relocation will need a PLT entry. */
a8c887dd
NC		 14796 if (root_plt->refcount != -1)
14797 root_plt->refcount += 1;
34e77a92
RS		 14798
14799 if (!call_reloc_p)
14800 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14801
14802 /* It's too early to use htab->use_blx here, so we have to
14803 record possible blx references separately from
14804 relocs that definitely need a thumb stub. */
14805
14806 if (r_type == R_ARM_THM_CALL)
34e77a92 14807 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14808
14809 if (r_type == R_ARM_THM_JUMP24
14810 || r_type == R_ARM_THM_JUMP19)
34e77a92 14811 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14812 }
14813
14814 if (may_become_dynamic_p)
14815 {
14816 struct elf_dyn_relocs *p, **head;
14817
14818 /* Create a reloc section in dynobj. */
14819 if (sreloc == NULL)
14820 {
14821 sreloc = _bfd_elf_make_dynamic_reloc_section
14822 (sec, dynobj, 2, abfd, ! htab->use_rel);
14823
14824 if (sreloc == NULL)
14825 return FALSE;
14826
14827 /* BPABI objects never have dynamic relocations mapped. */
14828 if (htab->symbian_p)
14829 {
14830 flagword flags;
14831
14832 flags = bfd_get_section_flags (dynobj, sreloc);
14833 flags &= ~(SEC_LOAD | SEC_ALLOC);
14834 bfd_set_section_flags (dynobj, sreloc, flags);
14835 }
14836 }
14837
14838 /* If this is a global symbol, count the number of
14839 relocations we need for this symbol. */
14840 if (h != NULL)
14841 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14842 else
14843 {
34e77a92
RS		 14844 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14845 if (head == NULL)
f6e32f6d 14846 return FALSE;
f6e32f6d
RS		 14847 }
14848
14849 p = *head;
14850 if (p == NULL || p->sec != sec)
14851 {
14852 bfd_size_type amt = sizeof *p;
14853
14854 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14855 if (p == NULL)
14856 return FALSE;
14857 p->next = *head;
14858 *head = p;
14859 p->sec = sec;
14860 p->count = 0;
14861 p->pc_count = 0;
14862 }
14863
469a3493 14864 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14865 p->pc_count += 1;
14866 p->count += 1;
14867 }
252b5132 14868 }
f21f3fe0 14869
b34976b6 14870 return TRUE;
252b5132
RH		 14871}
14872
9eaff861
AO		 14873static void
14874elf32_arm_update_relocs (asection *o,
14875 struct bfd_elf_section_reloc_data *reldata)
14876{
14877 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14878 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14879 const struct elf_backend_data *bed;
14880 _arm_elf_section_data *eado;
14881 struct bfd_link_order *p;
14882 bfd_byte *erela_head, *erela;
14883 Elf_Internal_Rela *irela_head, *irela;
14884 Elf_Internal_Shdr *rel_hdr;
14885 bfd *abfd;
14886 unsigned int count;
14887
14888 eado = get_arm_elf_section_data (o);
14889
14890 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14891 return;
14892
14893 abfd = o->owner;
14894 bed = get_elf_backend_data (abfd);
14895 rel_hdr = reldata->hdr;
14896
14897 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14898 {
14899 swap_in = bed->s->swap_reloc_in;
14900 swap_out = bed->s->swap_reloc_out;
14901 }
14902 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14903 {
14904 swap_in = bed->s->swap_reloca_in;
14905 swap_out = bed->s->swap_reloca_out;
14906 }
14907 else
14908 abort ();
14909
14910 erela_head = rel_hdr->contents;
14911 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14912 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14913
14914 erela = erela_head;
14915 irela = irela_head;
14916 count = 0;
14917
14918 for (p = o->map_head.link_order; p; p = p->next)
14919 {
14920 if (p->type == bfd_section_reloc_link_order
14921 || p->type == bfd_symbol_reloc_link_order)
14922 {
14923 (*swap_in) (abfd, erela, irela);
14924 erela += rel_hdr->sh_entsize;
14925 irela++;
14926 count++;
14927 }
14928 else if (p->type == bfd_indirect_link_order)
14929 {
14930 struct bfd_elf_section_reloc_data *input_reldata;
14931 arm_unwind_table_edit *edit_list, *edit_tail;
14932 _arm_elf_section_data *eadi;
14933 bfd_size_type j;
14934 bfd_vma offset;
14935 asection *i;
14936
14937 i = p->u.indirect.section;
14938
14939 eadi = get_arm_elf_section_data (i);
14940 edit_list = eadi->u.exidx.unwind_edit_list;
14941 edit_tail = eadi->u.exidx.unwind_edit_tail;
14942 offset = o->vma + i->output_offset;
14943
14944 if (eadi->elf.rel.hdr &&
14945 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14946 input_reldata = &eadi->elf.rel;
14947 else if (eadi->elf.rela.hdr &&
14948 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14949 input_reldata = &eadi->elf.rela;
14950 else
14951 abort ();
14952
14953 if (edit_list)
14954 {
14955 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14956 {
14957 arm_unwind_table_edit *edit_node, *edit_next;
14958 bfd_vma bias;
c48182bf 14959 bfd_vma reloc_index;
9eaff861
AO		 14960
14961 (*swap_in) (abfd, erela, irela);
c48182bf 14962 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 14963
14964 bias = 0;
14965 edit_node = edit_list;
14966 for (edit_next = edit_list;
c48182bf 14967 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 14968 edit_next = edit_node->next)
14969 {
14970 bias++;
14971 edit_node = edit_next;
14972 }
14973
14974 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 14975 || edit_node->index != reloc_index)
9eaff861
AO		 14976 {
14977 irela->r_offset -= bias * 8;
14978 irela++;
14979 count++;
14980 }
14981
14982 erela += rel_hdr->sh_entsize;
14983 }
14984
14985 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
14986 {
14987 /* New relocation entity. */
14988 asection *text_sec = edit_tail->linked_section;
14989 asection *text_out = text_sec->output_section;
14990 bfd_vma exidx_offset = offset + i->size - 8;
14991
14992 irela->r_addend = 0;
14993 irela->r_offset = exidx_offset;
14994 irela->r_info = ELF32_R_INFO
14995 (text_out->target_index, R_ARM_PREL31);
14996 irela++;
14997 count++;
14998 }
14999 }
15000 else
15001 {
15002 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15003 {
15004 (*swap_in) (abfd, erela, irela);
15005 erela += rel_hdr->sh_entsize;
15006 irela++;
15007 }
15008
15009 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15010 }
15011 }
15012 }
15013
15014 reldata->count = count;
15015 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15016
15017 erela = erela_head;
15018 irela = irela_head;
15019 while (count > 0)
15020 {
15021 (*swap_out) (abfd, irela, erela);
15022 erela += rel_hdr->sh_entsize;
15023 irela++;
15024 count--;
15025 }
15026
15027 free (irela_head);
15028
15029 /* Hashes are no longer valid. */
15030 free (reldata->hashes);
15031 reldata->hashes = NULL;
15032}
15033
6a5bb875 15034/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15035 required if the corresponding code section is marked. Similarly, ARMv8-M
15036 secure entry functions can only be referenced by SG veneers which are
15037 created after the GC process. They need to be marked in case they reside in
15038 their own section (as would be the case if code was compiled with
15039 -ffunction-sections). */
6a5bb875
PB		 15040
15041static bfd_boolean
906e58ca
NC		 15042elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15043 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15044{
15045 bfd *sub;
15046 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15047 asection *cmse_sec;
15048 obj_attribute *out_attr;
15049 Elf_Internal_Shdr *symtab_hdr;
15050 unsigned i, sym_count, ext_start;
15051 const struct elf_backend_data *bed;
15052 struct elf_link_hash_entry **sym_hashes;
15053 struct elf32_arm_link_hash_entry *cmse_hash;
15054 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15055
7f6ab9f8
AM		 15056 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15057
4ba2ef8f
TP		 15058 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15059 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15060 && out_attr[Tag_CPU_arch_profile].i == 'M';
15061
6a5bb875
PB		 15062 /* Marking EH data may cause additional code sections to be marked,
15063 requiring multiple passes. */
15064 again = TRUE;
15065 while (again)
15066 {
15067 again = FALSE;
c72f2fb2 15068 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15069 {
15070 asection *o;
15071
0ffa91dd 15072 if (! is_arm_elf (sub))
6a5bb875
PB		 15073 continue;
15074
15075 elf_shdrp = elf_elfsections (sub);
15076 for (o = sub->sections; o != NULL; o = o->next)
15077 {
15078 Elf_Internal_Shdr *hdr;
0ffa91dd 15079
6a5bb875 15080 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15081 if (hdr->sh_type == SHT_ARM_EXIDX
15082 && hdr->sh_link
15083 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15084 && !o->gc_mark
15085 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15086 {
15087 again = TRUE;
15088 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15089 return FALSE;
15090 }
15091 }
4ba2ef8f
TP		 15092
15093 /* Mark section holding ARMv8-M secure entry functions. We mark all
15094 of them so no need for a second browsing. */
15095 if (is_v8m && first_bfd_browse)
15096 {
15097 sym_hashes = elf_sym_hashes (sub);
15098 bed = get_elf_backend_data (sub);
15099 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15100 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15101 ext_start = symtab_hdr->sh_info;
15102
15103 /* Scan symbols. */
15104 for (i = ext_start; i < sym_count; i++)
15105 {
15106 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15107
15108 /* Assume it is a special symbol. If not, cmse_scan will
15109 warn about it and user can do something about it. */
15110 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15111 {
15112 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15113 if (!cmse_sec->gc_mark
15114 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15115 return FALSE;
15116 }
15117 }
15118 }
6a5bb875 15119 }
4ba2ef8f 15120 first_bfd_browse = FALSE;
6a5bb875
PB		 15121 }
15122
15123 return TRUE;
15124}
15125
3c9458e9
NC		 15126/* Treat mapping symbols as special target symbols. */
15127
15128static bfd_boolean
15129elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15130{
b0796911
PB		 15131 return bfd_is_arm_special_symbol_name (sym->name,
15132 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15133}
15134
0367ecfb
NC		 15135/* This is a copy of elf_find_function() from elf.c except that
15136 ARM mapping symbols are ignored when looking for function names
15137 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15138
0367ecfb
NC		 15139static bfd_boolean
15140arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15141 asymbol ** symbols,
fb167eb2 15142 asection * section,
0367ecfb
NC		 15143 bfd_vma offset,
15144 const char ** filename_ptr,
15145 const char ** functionname_ptr)
15146{
15147 const char * filename = NULL;
15148 asymbol * func = NULL;
15149 bfd_vma low_func = 0;
15150 asymbol ** p;
252b5132
RH		 15151
15152 for (p = symbols; *p != NULL; p++)
15153 {
15154 elf_symbol_type *q;
15155
15156 q = (elf_symbol_type *) *p;
15157
252b5132
RH		 15158 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15159 {
15160 default:
15161 break;
15162 case STT_FILE:
15163 filename = bfd_asymbol_name (&q->symbol);
15164 break;
252b5132
RH		 15165 case STT_FUNC:
15166 case STT_ARM_TFUNC:
9d2da7ca 15167 case STT_NOTYPE:
b0796911 15168 /* Skip mapping symbols. */
0367ecfb 15169 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15170 && bfd_is_arm_special_symbol_name (q->symbol.name,
15171 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15172 continue;
15173 /* Fall through. */
6b40fcba 15174 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15175 && q->symbol.value >= low_func
15176 && q->symbol.value <= offset)
15177 {
15178 func = (asymbol *) q;
15179 low_func = q->symbol.value;
15180 }
15181 break;
15182 }
15183 }
15184
15185 if (func == NULL)
b34976b6 15186 return FALSE;
252b5132 15187
0367ecfb
NC		 15188 if (filename_ptr)
15189 *filename_ptr = filename;
15190 if (functionname_ptr)
15191 *functionname_ptr = bfd_asymbol_name (func);
15192
15193 return TRUE;
906e58ca 15194}
0367ecfb
NC		 15195
15196
15197/* Find the nearest line to a particular section and offset, for error
15198 reporting. This code is a duplicate of the code in elf.c, except
15199 that it uses arm_elf_find_function. */
15200
15201static bfd_boolean
15202elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 15203 asymbol ** symbols,
fb167eb2 15204 asection * section,
0367ecfb
NC		 15205 bfd_vma offset,
15206 const char ** filename_ptr,
15207 const char ** functionname_ptr,
fb167eb2
AM		 15208 unsigned int * line_ptr,
15209 unsigned int * discriminator_ptr)
0367ecfb
NC		 15210{
15211 bfd_boolean found = FALSE;
15212
fb167eb2 15213 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15214 filename_ptr, functionname_ptr,
fb167eb2
AM		 15215 line_ptr, discriminator_ptr,
15216 dwarf_debug_sections, 0,
0367ecfb
NC		 15217 & elf_tdata (abfd)->dwarf2_find_line_info))
15218 {
15219 if (!*functionname_ptr)
fb167eb2 15220 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15221 *filename_ptr ? NULL : filename_ptr,
15222 functionname_ptr);
f21f3fe0 15223
0367ecfb
NC		 15224 return TRUE;
15225 }
15226
fb167eb2
AM		 15227 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15228 uses DWARF1. */
15229
0367ecfb
NC		 15230 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15231 & found, filename_ptr,
15232 functionname_ptr, line_ptr,
15233 & elf_tdata (abfd)->line_info))
15234 return FALSE;
15235
15236 if (found && (*functionname_ptr || *line_ptr))
15237 return TRUE;
15238
15239 if (symbols == NULL)
15240 return FALSE;
15241
fb167eb2 15242 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15243 filename_ptr, functionname_ptr))
15244 return FALSE;
15245
15246 *line_ptr = 0;
b34976b6 15247 return TRUE;
252b5132
RH		 15248}
15249
4ab527b0
FF		 15250static bfd_boolean
15251elf32_arm_find_inliner_info (bfd * abfd,
15252 const char ** filename_ptr,
15253 const char ** functionname_ptr,
15254 unsigned int * line_ptr)
15255{
15256 bfd_boolean found;
15257 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15258 functionname_ptr, line_ptr,
15259 & elf_tdata (abfd)->dwarf2_find_line_info);
15260 return found;
15261}
15262
252b5132
RH		 15263/* Adjust a symbol defined by a dynamic object and referenced by a
15264 regular object. The current definition is in some section of the
15265 dynamic object, but we're not including those sections. We have to
15266 change the definition to something the rest of the link can
15267 understand. */
15268
b34976b6 15269static bfd_boolean
57e8b36a
NC		 15270elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15271 struct elf_link_hash_entry * h)
252b5132
RH		 15272{
15273 bfd * dynobj;
15274 asection * s;
b7693d02 15275 struct elf32_arm_link_hash_entry * eh;
67687978 15276 struct elf32_arm_link_hash_table *globals;
252b5132 15277
67687978 15278 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15279 if (globals == NULL)
15280 return FALSE;
15281
252b5132
RH		 15282 dynobj = elf_hash_table (info)->dynobj;
15283
15284 /* Make sure we know what is going on here. */
15285 BFD_ASSERT (dynobj != NULL
f5385ebf 15286 && (h->needs_plt
34e77a92 15287 || h->type == STT_GNU_IFUNC
f6e332e6 15288 || h->u.weakdef != NULL
f5385ebf
AM		 15289 || (h->def_dynamic
15290 && h->ref_regular
15291 && !h->def_regular)));
252b5132 15292
b7693d02
DJ		 15293 eh = (struct elf32_arm_link_hash_entry *) h;
15294
252b5132
RH		 15295 /* If this is a function, put it in the procedure linkage table. We
15296 will fill in the contents of the procedure linkage table later,
15297 when we know the address of the .got section. */
34e77a92 15298 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15299 {
34e77a92
RS		 15300 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15301 symbol binds locally. */
5e681ec4 15302 if (h->plt.refcount <= 0
34e77a92
RS		 15303 || (h->type != STT_GNU_IFUNC
15304 && (SYMBOL_CALLS_LOCAL (info, h)
15305 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15306 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15307 {
15308 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15309 file, but the symbol was never referred to by a dynamic
15310 object, or if all references were garbage collected. In
15311 such a case, we don't actually need to build a procedure
15312 linkage table, and we can just do a PC24 reloc instead. */
15313 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15314 eh->plt.thumb_refcount = 0;
15315 eh->plt.maybe_thumb_refcount = 0;
15316 eh->plt.noncall_refcount = 0;
f5385ebf 15317 h->needs_plt = 0;
252b5132
RH		 15318 }
15319
b34976b6 15320 return TRUE;
252b5132 15321 }
5e681ec4 15322 else
b7693d02
DJ		 15323 {
15324 /* It's possible that we incorrectly decided a .plt reloc was
15325 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15326 in check_relocs. We can't decide accurately between function
15327 and non-function syms in check-relocs; Objects loaded later in
15328 the link may change h->type. So fix it now. */
15329 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15330 eh->plt.thumb_refcount = 0;
15331 eh->plt.maybe_thumb_refcount = 0;
15332 eh->plt.noncall_refcount = 0;
b7693d02 15333 }
252b5132
RH		 15334
15335 /* If this is a weak symbol, and there is a real definition, the
15336 processor independent code will have arranged for us to see the
15337 real definition first, and we can just use the same value. */
f6e332e6 15338 if (h->u.weakdef != NULL)
252b5132 15339 {
f6e332e6
AM		 15340 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
15341 || h->u.weakdef->root.type == bfd_link_hash_defweak);
15342 h->root.u.def.section = h->u.weakdef->root.u.def.section;
15343 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 15344 return TRUE;
252b5132
RH		 15345 }
15346
ba93b8ac
DJ		 15347 /* If there are no non-GOT references, we do not need a copy
15348 relocation. */
15349 if (!h->non_got_ref)
15350 return TRUE;
15351
252b5132
RH		 15352 /* This is a reference to a symbol defined by a dynamic object which
15353 is not a function. */
15354
15355 /* If we are creating a shared library, we must presume that the
15356 only references to the symbol are via the global offset table.
15357 For such cases we need not do anything here; the relocations will
67687978
PB		 15358 be handled correctly by relocate_section. Relocatable executables
15359 can reference data in shared objects directly, so we don't need to
15360 do anything here. */
0e1862bb 15361 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15362 return TRUE;
252b5132
RH		 15363
15364 /* We must allocate the symbol in our .dynbss section, which will
15365 become part of the .bss section of the executable. There will be
15366 an entry for this symbol in the .dynsym section. The dynamic
15367 object will contain position independent code, so all references
15368 from the dynamic object to this symbol will go through the global
15369 offset table. The dynamic linker will use the .dynsym entry to
15370 determine the address it must put in the global offset table, so
15371 both the dynamic object and the regular object will refer to the
15372 same memory location for the variable. */
3d4d4302 15373 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 15374 BFD_ASSERT (s != NULL);
15375
5522f910
NC		 15376 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15377 linker to copy the initial value out of the dynamic object and into
15378 the runtime process image. We need to remember the offset into the
00a97672 15379 .rel(a).bss section we are going to use. */
5522f910
NC		 15380 if (info->nocopyreloc == 0
15381 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15382 && h->size != 0)
252b5132
RH		 15383 {
15384 asection *srel;
15385
3d4d4302 15386 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 15387 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15388 h->needs_copy = 1;
252b5132
RH		 15389 }
15390
6cabe1ea 15391 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15392}
15393
5e681ec4
PB		 15394/* Allocate space in .plt, .got and associated reloc sections for
15395 dynamic relocs. */
15396
15397static bfd_boolean
47beaa6a 15398allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15399{
15400 struct bfd_link_info *info;
15401 struct elf32_arm_link_hash_table *htab;
15402 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15403 struct elf_dyn_relocs *p;
5e681ec4
PB		 15404
15405 if (h->root.type == bfd_link_hash_indirect)
15406 return TRUE;
15407
e6a6bb22
AM		 15408 eh = (struct elf32_arm_link_hash_entry *) h;
15409
5e681ec4
PB		 15410 info = (struct bfd_link_info *) inf;
15411 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15412 if (htab == NULL)
15413 return FALSE;
5e681ec4 15414
34e77a92 15415 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15416 && h->plt.refcount > 0)
15417 {
15418 /* Make sure this symbol is output as a dynamic symbol.
15419 Undefined weak syms won't yet be marked as dynamic. */
15420 if (h->dynindx == -1
f5385ebf 15421 && !h->forced_local)
5e681ec4 15422 {
c152c796 15423 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15424 return FALSE;
15425 }
15426
34e77a92
RS		 15427 /* If the call in the PLT entry binds locally, the associated
15428 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15429 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15430 than the .plt section. */
15431 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15432 {
15433 eh->is_iplt = 1;
15434 if (eh->plt.noncall_refcount == 0
15435 && SYMBOL_REFERENCES_LOCAL (info, h))
15436 /* All non-call references can be resolved directly.
15437 This means that they can (and in some cases, must)
15438 resolve directly to the run-time target, rather than
15439 to the PLT. That in turns means that any .got entry
15440 would be equal to the .igot.plt entry, so there's
15441 no point having both. */
15442 h->got.refcount = 0;
15443 }
15444
0e1862bb 15445 if (bfd_link_pic (info)
34e77a92 15446 || eh->is_iplt
7359ea65 15447 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15448 {
34e77a92 15449 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15450
5e681ec4
PB		 15451 /* If this symbol is not defined in a regular file, and we are
15452 not generating a shared library, then set the symbol to this
15453 location in the .plt. This is required to make function
15454 pointers compare as equal between the normal executable and
15455 the shared library. */
0e1862bb 15456 if (! bfd_link_pic (info)
f5385ebf 15457 && !h->def_regular)
5e681ec4 15458 {
34e77a92 15459 h->root.u.def.section = htab->root.splt;
5e681ec4 15460 h->root.u.def.value = h->plt.offset;
5e681ec4 15461
67d74e43
DJ		 15462 /* Make sure the function is not marked as Thumb, in case
15463 it is the target of an ABS32 relocation, which will
15464 point to the PLT entry. */
39d911fc 15465 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15466 }
022f8312 15467
00a97672
RS		 15468 /* VxWorks executables have a second set of relocations for
15469 each PLT entry. They go in a separate relocation section,
15470 which is processed by the kernel loader. */
0e1862bb 15471 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15472 {
15473 /* There is a relocation for the initial PLT entry:
15474 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15475 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15476 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15477
15478 /* There are two extra relocations for each subsequent
15479 PLT entry: an R_ARM_32 relocation for the GOT entry,
15480 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15481 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15482 }
5e681ec4
PB		 15483 }
15484 else
15485 {
15486 h->plt.offset = (bfd_vma) -1;
f5385ebf 15487 h->needs_plt = 0;
5e681ec4
PB		 15488 }
15489 }
15490 else
15491 {
15492 h->plt.offset = (bfd_vma) -1;
f5385ebf 15493 h->needs_plt = 0;
5e681ec4
PB		 15494 }
15495
0855e32b
NS		 15496 eh = (struct elf32_arm_link_hash_entry *) h;
15497 eh->tlsdesc_got = (bfd_vma) -1;
15498
5e681ec4
PB		 15499 if (h->got.refcount > 0)
15500 {
15501 asection *s;
15502 bfd_boolean dyn;
ba93b8ac
DJ		 15503 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15504 int indx;
5e681ec4
PB		 15505
15506 /* Make sure this symbol is output as a dynamic symbol.
15507 Undefined weak syms won't yet be marked as dynamic. */
15508 if (h->dynindx == -1
f5385ebf 15509 && !h->forced_local)
5e681ec4 15510 {
c152c796 15511 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15512 return FALSE;
15513 }
15514
e5a52504
MM		 15515 if (!htab->symbian_p)
15516 {
362d30a1 15517 s = htab->root.sgot;
e5a52504 15518 h->got.offset = s->size;
ba93b8ac
DJ		 15519
15520 if (tls_type == GOT_UNKNOWN)
15521 abort ();
15522
15523 if (tls_type == GOT_NORMAL)
15524 /* Non-TLS symbols need one GOT slot. */
15525 s->size += 4;
15526 else
15527 {
99059e56
RM		 15528 if (tls_type & GOT_TLS_GDESC)
15529 {
0855e32b 15530 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15531 eh->tlsdesc_got
0855e32b
NS		 15532 = (htab->root.sgotplt->size
15533 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15534 htab->root.sgotplt->size += 8;
15535 h->got.offset = (bfd_vma) -2;
34e77a92 15536 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15537 reloc in the middle of .got.plt. */
99059e56
RM		 15538 htab->num_tls_desc++;
15539 }
0855e32b 15540
ba93b8ac 15541 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15542 {
15543 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15544 the symbol is both GD and GDESC, got.offset may
15545 have been overwritten. */
15546 h->got.offset = s->size;
15547 s->size += 8;
15548 }
15549
ba93b8ac
DJ		 15550 if (tls_type & GOT_TLS_IE)
15551 /* R_ARM_TLS_IE32 needs one GOT slot. */
15552 s->size += 4;
15553 }
15554
e5a52504 15555 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15556
15557 indx = 0;
0e1862bb
L		 15558 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15559 bfd_link_pic (info),
15560 h)
15561 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15562 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15563 indx = h->dynindx;
15564
15565 if (tls_type != GOT_NORMAL
0e1862bb 15566 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15567 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15568 || h->root.type != bfd_link_hash_undefweak))
15569 {
15570 if (tls_type & GOT_TLS_IE)
47beaa6a 15571 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15572
15573 if (tls_type & GOT_TLS_GD)
47beaa6a 15574 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15575
b38cadfb 15576 if (tls_type & GOT_TLS_GDESC)
0855e32b 15577 {
47beaa6a 15578 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15579 /* GDESC needs a trampoline to jump to. */
15580 htab->tls_trampoline = -1;
15581 }
15582
15583 /* Only GD needs it. GDESC just emits one relocation per
15584 2 entries. */
b38cadfb 15585 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15586 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15587 }
6f820c85 15588 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15589 {
15590 if (htab->root.dynamic_sections_created)
15591 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15592 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15593 }
34e77a92
RS		 15594 else if (h->type == STT_GNU_IFUNC
15595 && eh->plt.noncall_refcount == 0)
15596 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15597 they all resolve dynamically instead. Reserve room for the
15598 GOT entry's R_ARM_IRELATIVE relocation. */
15599 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15600 else if (bfd_link_pic (info)
15601 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15602 || h->root.type != bfd_link_hash_undefweak))
b436d854 15603 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15604 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15605 }
5e681ec4
PB		 15606 }
15607 else
15608 h->got.offset = (bfd_vma) -1;
15609
a4fd1a8e
PB		 15610 /* Allocate stubs for exported Thumb functions on v4t. */
15611 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15612 && h->def_regular
39d911fc 15613 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15614 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15615 {
15616 struct elf_link_hash_entry * th;
15617 struct bfd_link_hash_entry * bh;
15618 struct elf_link_hash_entry * myh;
15619 char name[1024];
15620 asection *s;
15621 bh = NULL;
15622 /* Create a new symbol to regist the real location of the function. */
15623 s = h->root.u.def.section;
906e58ca 15624 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15625 _bfd_generic_link_add_one_symbol (info, s->owner,
15626 name, BSF_GLOBAL, s,
15627 h->root.u.def.value,
15628 NULL, TRUE, FALSE, &bh);
15629
15630 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15631 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15632 myh->forced_local = 1;
39d911fc 15633 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15634 eh->export_glue = myh;
15635 th = record_arm_to_thumb_glue (info, h);
15636 /* Point the symbol at the stub. */
15637 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15638 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15639 h->root.u.def.section = th->root.u.def.section;
15640 h->root.u.def.value = th->root.u.def.value & ~1;
15641 }
15642
0bdcacaf 15643 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15644 return TRUE;
15645
15646 /* In the shared -Bsymbolic case, discard space allocated for
15647 dynamic pc-relative relocs against symbols which turn out to be
15648 defined in regular objects. For the normal shared case, discard
15649 space for pc-relative relocs that have become local due to symbol
15650 visibility changes. */
15651
0e1862bb 15652 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15653 {
469a3493
RM		 15654 /* Relocs that use pc_count are PC-relative forms, which will appear
15655 on something like ".long foo - ." or "movw REG, foo - .". We want
15656 calls to protected symbols to resolve directly to the function
15657 rather than going via the plt. If people want function pointer
15658 comparisons to work as expected then they should avoid writing
15659 assembly like ".long foo - .". */
ba93b8ac
DJ		 15660 if (SYMBOL_CALLS_LOCAL (info, h))
15661 {
0bdcacaf 15662 struct elf_dyn_relocs **pp;
ba93b8ac 15663
0bdcacaf 15664 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15665 {
15666 p->count -= p->pc_count;
15667 p->pc_count = 0;
15668 if (p->count == 0)
15669 *pp = p->next;
15670 else
15671 pp = &p->next;
15672 }
15673 }
15674
4dfe6ac6 15675 if (htab->vxworks_p)
3348747a 15676 {
0bdcacaf 15677 struct elf_dyn_relocs **pp;
3348747a 15678
0bdcacaf 15679 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15680 {
0bdcacaf 15681 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15682 *pp = p->next;
15683 else
15684 pp = &p->next;
15685 }
15686 }
15687
ba93b8ac 15688 /* Also discard relocs on undefined weak syms with non-default
99059e56 15689 visibility. */
0bdcacaf 15690 if (eh->dyn_relocs != NULL
5e681ec4 15691 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 15692 {
15693 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 15694 eh->dyn_relocs = NULL;
22d606e9
AM		 15695
15696 /* Make sure undefined weak symbols are output as a dynamic
15697 symbol in PIEs. */
15698 else if (h->dynindx == -1
15699 && !h->forced_local)
15700 {
15701 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15702 return FALSE;
15703 }
15704 }
15705
67687978
PB		 15706 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15707 && h->root.type == bfd_link_hash_new)
15708 {
15709 /* Output absolute symbols so that we can create relocations
15710 against them. For normal symbols we output a relocation
15711 against the section that contains them. */
15712 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15713 return FALSE;
15714 }
15715
5e681ec4
PB		 15716 }
15717 else
15718 {
15719 /* For the non-shared case, discard space for relocs against
15720 symbols which turn out to need copy relocs or are not
15721 dynamic. */
15722
f5385ebf
AM		 15723 if (!h->non_got_ref
15724 && ((h->def_dynamic
15725 && !h->def_regular)
5e681ec4
PB		 15726 || (htab->root.dynamic_sections_created
15727 && (h->root.type == bfd_link_hash_undefweak
15728 || h->root.type == bfd_link_hash_undefined))))
15729 {
15730 /* Make sure this symbol is output as a dynamic symbol.
15731 Undefined weak syms won't yet be marked as dynamic. */
15732 if (h->dynindx == -1
f5385ebf 15733 && !h->forced_local)
5e681ec4 15734 {
c152c796 15735 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15736 return FALSE;
15737 }
15738
15739 /* If that succeeded, we know we'll be keeping all the
15740 relocs. */
15741 if (h->dynindx != -1)
15742 goto keep;
15743 }
15744
0bdcacaf 15745 eh->dyn_relocs = NULL;
5e681ec4
PB		 15746
15747 keep: ;
15748 }
15749
15750 /* Finally, allocate space. */
0bdcacaf 15751 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15752 {
0bdcacaf 15753 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15754 if (h->type == STT_GNU_IFUNC
15755 && eh->plt.noncall_refcount == 0
15756 && SYMBOL_REFERENCES_LOCAL (info, h))
15757 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15758 else
15759 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15760 }
15761
15762 return TRUE;
15763}
15764
08d1f311
DJ		 15765/* Find any dynamic relocs that apply to read-only sections. */
15766
15767static bfd_boolean
8029a119 15768elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15769{
8029a119 15770 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15771 struct elf_dyn_relocs * p;
08d1f311 15772
08d1f311 15773 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15774 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15775 {
0bdcacaf 15776 asection *s = p->sec;
08d1f311
DJ		 15777
15778 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15779 {
15780 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15781
15782 info->flags |= DF_TEXTREL;
15783
15784 /* Not an error, just cut short the traversal. */
15785 return FALSE;
15786 }
15787 }
15788 return TRUE;
15789}
15790
d504ffc8
DJ		 15791void
15792bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15793 int byteswap_code)
15794{
15795 struct elf32_arm_link_hash_table *globals;
15796
15797 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15798 if (globals == NULL)
15799 return;
15800
d504ffc8
DJ		 15801 globals->byteswap_code = byteswap_code;
15802}
15803
252b5132
RH		 15804/* Set the sizes of the dynamic sections. */
15805
b34976b6 15806static bfd_boolean
57e8b36a
NC		 15807elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15808 struct bfd_link_info * info)
252b5132
RH		 15809{
15810 bfd * dynobj;
15811 asection * s;
b34976b6
AM		 15812 bfd_boolean plt;
15813 bfd_boolean relocs;
5e681ec4
PB		 15814 bfd *ibfd;
15815 struct elf32_arm_link_hash_table *htab;
252b5132 15816
5e681ec4 15817 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15818 if (htab == NULL)
15819 return FALSE;
15820
252b5132
RH		 15821 dynobj = elf_hash_table (info)->dynobj;
15822 BFD_ASSERT (dynobj != NULL);
39b41c9c 15823 check_use_blx (htab);
252b5132
RH		 15824
15825 if (elf_hash_table (info)->dynamic_sections_created)
15826 {
15827 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15828 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15829 {
3d4d4302 15830 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15831 BFD_ASSERT (s != NULL);
eea6121a 15832 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15833 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15834 }
15835 }
5e681ec4
PB		 15836
15837 /* Set up .got offsets for local syms, and space for local dynamic
15838 relocs. */
c72f2fb2 15839 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15840 {
5e681ec4
PB		 15841 bfd_signed_vma *local_got;
15842 bfd_signed_vma *end_local_got;
34e77a92 15843 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15844 char *local_tls_type;
0855e32b 15845 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15846 bfd_size_type locsymcount;
15847 Elf_Internal_Shdr *symtab_hdr;
15848 asection *srel;
4dfe6ac6 15849 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15850 unsigned int symndx;
5e681ec4 15851
0ffa91dd 15852 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15853 continue;
15854
15855 for (s = ibfd->sections; s != NULL; s = s->next)
15856 {
0bdcacaf 15857 struct elf_dyn_relocs *p;
5e681ec4 15858
0bdcacaf 15859 for (p = (struct elf_dyn_relocs *)
99059e56 15860 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15861 {
0bdcacaf
RS		 15862 if (!bfd_is_abs_section (p->sec)
15863 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15864 {
15865 /* Input section has been discarded, either because
15866 it is a copy of a linkonce section or due to
15867 linker script /DISCARD/, so we'll be discarding
15868 the relocs too. */
15869 }
3348747a 15870 else if (is_vxworks
0bdcacaf 15871 && strcmp (p->sec->output_section->name,
3348747a
NS		 15872 ".tls_vars") == 0)
15873 {
15874 /* Relocations in vxworks .tls_vars sections are
15875 handled specially by the loader. */
15876 }
5e681ec4
PB		 15877 else if (p->count != 0)
15878 {
0bdcacaf 15879 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15880 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15881 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15882 info->flags |= DF_TEXTREL;
15883 }
15884 }
15885 }
15886
15887 local_got = elf_local_got_refcounts (ibfd);
15888 if (!local_got)
15889 continue;
15890
0ffa91dd 15891 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15892 locsymcount = symtab_hdr->sh_info;
15893 end_local_got = local_got + locsymcount;
34e77a92 15894 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15895 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15896 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15897 symndx = 0;
362d30a1
RS		 15898 s = htab->root.sgot;
15899 srel = htab->root.srelgot;
0855e32b 15900 for (; local_got < end_local_got;
34e77a92
RS		 15901 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15902 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15903 {
0855e32b 15904 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15905 local_iplt = *local_iplt_ptr;
15906 if (local_iplt != NULL)
15907 {
15908 struct elf_dyn_relocs *p;
15909
15910 if (local_iplt->root.refcount > 0)
15911 {
15912 elf32_arm_allocate_plt_entry (info, TRUE,
15913 &local_iplt->root,
15914 &local_iplt->arm);
15915 if (local_iplt->arm.noncall_refcount == 0)
15916 /* All references to the PLT are calls, so all
15917 non-call references can resolve directly to the
15918 run-time target. This means that the .got entry
15919 would be the same as the .igot.plt entry, so there's
15920 no point creating both. */
15921 *local_got = 0;
15922 }
15923 else
15924 {
15925 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15926 local_iplt->root.offset = (bfd_vma) -1;
15927 }
15928
15929 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15930 {
15931 asection *psrel;
15932
15933 psrel = elf_section_data (p->sec)->sreloc;
15934 if (local_iplt->arm.noncall_refcount == 0)
15935 elf32_arm_allocate_irelocs (info, psrel, p->count);
15936 else
15937 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15938 }
15939 }
5e681ec4
PB		 15940 if (*local_got > 0)
15941 {
34e77a92
RS		 15942 Elf_Internal_Sym *isym;
15943
eea6121a 15944 *local_got = s->size;
ba93b8ac
DJ		 15945 if (*local_tls_type & GOT_TLS_GD)
15946 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15947 s->size += 8;
0855e32b
NS		 15948 if (*local_tls_type & GOT_TLS_GDESC)
15949 {
15950 *local_tlsdesc_gotent = htab->root.sgotplt->size
15951 - elf32_arm_compute_jump_table_size (htab);
15952 htab->root.sgotplt->size += 8;
15953 *local_got = (bfd_vma) -2;
34e77a92 15954 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15955 reloc in the middle of .got.plt. */
99059e56 15956 htab->num_tls_desc++;
0855e32b 15957 }
ba93b8ac
DJ		 15958 if (*local_tls_type & GOT_TLS_IE)
15959 s->size += 4;
ba93b8ac 15960
0855e32b
NS		 15961 if (*local_tls_type & GOT_NORMAL)
15962 {
15963 /* If the symbol is both GD and GDESC, *local_got
15964 may have been overwritten. */
15965 *local_got = s->size;
15966 s->size += 4;
15967 }
15968
34e77a92
RS		 15969 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15970 if (isym == NULL)
15971 return FALSE;
15972
15973 /* If all references to an STT_GNU_IFUNC PLT are calls,
15974 then all non-call references, including this GOT entry,
15975 resolve directly to the run-time target. */
15976 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15977 && (local_iplt == NULL
15978 || local_iplt->arm.noncall_refcount == 0))
15979 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15980 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15981 {
0e1862bb 15982 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15983 || *local_tls_type & GOT_TLS_GD)
15984 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15985
0e1862bb 15986 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15987 {
15988 elf32_arm_allocate_dynrelocs (info,
15989 htab->root.srelplt, 1);
15990 htab->tls_trampoline = -1;
15991 }
0855e32b 15992 }
5e681ec4
PB		 15993 }
15994 else
15995 *local_got = (bfd_vma) -1;
15996 }
252b5132
RH		 15997 }
15998
ba93b8ac
DJ		 15999 if (htab->tls_ldm_got.refcount > 0)
16000 {
16001 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16002 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 16003 htab->tls_ldm_got.offset = htab->root.sgot->size;
16004 htab->root.sgot->size += 8;
0e1862bb 16005 if (bfd_link_pic (info))
47beaa6a 16006 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16007 }
16008 else
16009 htab->tls_ldm_got.offset = -1;
16010
5e681ec4
PB		 16011 /* Allocate global sym .plt and .got entries, and space for global
16012 sym dynamic relocs. */
47beaa6a 16013 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16014
d504ffc8 16015 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16016 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16017 {
0ffa91dd 16018 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16019 continue;
16020
c7b8f16e
JB		 16021 /* Initialise mapping tables for code/data. */
16022 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16023
c7b8f16e 16024 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16025 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16026 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56 16027 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 16028 ibfd->filename);
16029 }
d504ffc8 16030
3e6b1042
DJ		 16031 /* Allocate space for the glue sections now that we've sized them. */
16032 bfd_elf32_arm_allocate_interworking_sections (info);
16033
0855e32b
NS		 16034 /* For every jump slot reserved in the sgotplt, reloc_count is
16035 incremented. However, when we reserve space for TLS descriptors,
16036 it's not incremented, so in order to compute the space reserved
16037 for them, it suffices to multiply the reloc count by the jump
16038 slot size. */
16039 if (htab->root.srelplt)
16040 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16041
16042 if (htab->tls_trampoline)
16043 {
16044 if (htab->root.splt->size == 0)
16045 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16046
0855e32b
NS		 16047 htab->tls_trampoline = htab->root.splt->size;
16048 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16049
0855e32b 16050 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16051 PLT and GOT entries they require. */
0855e32b
NS		 16052 if (!(info->flags & DF_BIND_NOW))
16053 {
16054 htab->dt_tlsdesc_got = htab->root.sgot->size;
16055 htab->root.sgot->size += 4;
16056
16057 htab->dt_tlsdesc_plt = htab->root.splt->size;
16058 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16059 }
16060 }
16061
252b5132
RH		 16062 /* The check_relocs and adjust_dynamic_symbol entry points have
16063 determined the sizes of the various dynamic sections. Allocate
16064 memory for them. */
b34976b6
AM		 16065 plt = FALSE;
16066 relocs = FALSE;
252b5132
RH		 16067 for (s = dynobj->sections; s != NULL; s = s->next)
16068 {
16069 const char * name;
252b5132
RH		 16070
16071 if ((s->flags & SEC_LINKER_CREATED) == 0)
16072 continue;
16073
16074 /* It's OK to base decisions on the section name, because none
16075 of the dynobj section names depend upon the input files. */
16076 name = bfd_get_section_name (dynobj, s);
16077
34e77a92 16078 if (s == htab->root.splt)
252b5132 16079 {
c456f082
AM		 16080 /* Remember whether there is a PLT. */
16081 plt = s->size != 0;
252b5132 16082 }
0112cd26 16083 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16084 {
c456f082 16085 if (s->size != 0)
252b5132 16086 {
252b5132 16087 /* Remember whether there are any reloc sections other
00a97672 16088 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16089 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16090 relocs = TRUE;
252b5132
RH		 16091
16092 /* We use the reloc_count field as a counter if we need
16093 to copy relocs into the output file. */
16094 s->reloc_count = 0;
16095 }
16096 }
34e77a92
RS		 16097 else if (s != htab->root.sgot
16098 && s != htab->root.sgotplt
16099 && s != htab->root.iplt
16100 && s != htab->root.igotplt
16101 && s != htab->sdynbss)
252b5132
RH		 16102 {
16103 /* It's not one of our sections, so don't allocate space. */
16104 continue;
16105 }
16106
c456f082 16107 if (s->size == 0)
252b5132 16108 {
c456f082 16109 /* If we don't need this section, strip it from the
00a97672
RS		 16110 output file. This is mostly to handle .rel(a).bss and
16111 .rel(a).plt. We must create both sections in
c456f082
AM		 16112 create_dynamic_sections, because they must be created
16113 before the linker maps input sections to output
16114 sections. The linker does that before
16115 adjust_dynamic_symbol is called, and it is that
16116 function which decides whether anything needs to go
16117 into these sections. */
8423293d 16118 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16119 continue;
16120 }
16121
c456f082
AM		 16122 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16123 continue;
16124
252b5132 16125 /* Allocate memory for the section contents. */
21d799b5 16126 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16127 if (s->contents == NULL)
b34976b6 16128 return FALSE;
252b5132
RH		 16129 }
16130
16131 if (elf_hash_table (info)->dynamic_sections_created)
16132 {
16133 /* Add some entries to the .dynamic section. We fill in the
16134 values later, in elf32_arm_finish_dynamic_sections, but we
16135 must add the entries now so that we get the correct size for
16136 the .dynamic section. The DT_DEBUG entry is filled in by the
16137 dynamic linker and used by the debugger. */
dc810e39 16138#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16139 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16140
0e1862bb 16141 if (bfd_link_executable (info))
252b5132 16142 {
dc810e39 16143 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16144 return FALSE;
252b5132
RH		 16145 }
16146
16147 if (plt)
16148 {
dc810e39
AM		 16149 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16150 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16151 || !add_dynamic_entry (DT_PLTREL,
16152 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16153 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16154 return FALSE;
0855e32b 16155
5025eb7c
AO		 16156 if (htab->dt_tlsdesc_plt
16157 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16158 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16159 return FALSE;
252b5132
RH		 16160 }
16161
16162 if (relocs)
16163 {
00a97672
RS		 16164 if (htab->use_rel)
16165 {
16166 if (!add_dynamic_entry (DT_REL, 0)
16167 || !add_dynamic_entry (DT_RELSZ, 0)
16168 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16169 return FALSE;
16170 }
16171 else
16172 {
16173 if (!add_dynamic_entry (DT_RELA, 0)
16174 || !add_dynamic_entry (DT_RELASZ, 0)
16175 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16176 return FALSE;
16177 }
252b5132
RH		 16178 }
16179
08d1f311
DJ		 16180 /* If any dynamic relocs apply to a read-only section,
16181 then we need a DT_TEXTREL entry. */
16182 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 16183 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
16184 info);
08d1f311 16185
99e4ae17 16186 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16187 {
dc810e39 16188 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16189 return FALSE;
252b5132 16190 }
7a2b07ff
NS		 16191 if (htab->vxworks_p
16192 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16193 return FALSE;
252b5132 16194 }
8532796c 16195#undef add_dynamic_entry
252b5132 16196
b34976b6 16197 return TRUE;
252b5132
RH		 16198}
16199
0855e32b
NS		 16200/* Size sections even though they're not dynamic. We use it to setup
16201 _TLS_MODULE_BASE_, if needed. */
16202
16203static bfd_boolean
16204elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16205 struct bfd_link_info *info)
0855e32b
NS		 16206{
16207 asection *tls_sec;
16208
0e1862bb 16209 if (bfd_link_relocatable (info))
0855e32b
NS		 16210 return TRUE;
16211
16212 tls_sec = elf_hash_table (info)->tls_sec;
16213
16214 if (tls_sec)
16215 {
16216 struct elf_link_hash_entry *tlsbase;
16217
16218 tlsbase = elf_link_hash_lookup
16219 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16220
16221 if (tlsbase)
99059e56
RM		 16222 {
16223 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16224 const struct elf_backend_data *bed
99059e56 16225 = get_elf_backend_data (output_bfd);
0855e32b 16226
99059e56 16227 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16228 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16229 tls_sec, 0, NULL, FALSE,
16230 bed->collect, &bh)))
16231 return FALSE;
b38cadfb 16232
99059e56
RM		 16233 tlsbase->type = STT_TLS;
16234 tlsbase = (struct elf_link_hash_entry *)bh;
16235 tlsbase->def_regular = 1;
16236 tlsbase->other = STV_HIDDEN;
16237 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16238 }
16239 }
16240 return TRUE;
16241}
16242
252b5132
RH		 16243/* Finish up dynamic symbol handling. We set the contents of various
16244 dynamic sections here. */
16245
b34976b6 16246static bfd_boolean
906e58ca
NC		 16247elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16248 struct bfd_link_info * info,
16249 struct elf_link_hash_entry * h,
16250 Elf_Internal_Sym * sym)
252b5132 16251{
e5a52504 16252 struct elf32_arm_link_hash_table *htab;
b7693d02 16253 struct elf32_arm_link_hash_entry *eh;
252b5132 16254
e5a52504 16255 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16256 if (htab == NULL)
16257 return FALSE;
16258
b7693d02 16259 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16260
16261 if (h->plt.offset != (bfd_vma) -1)
16262 {
34e77a92 16263 if (!eh->is_iplt)
e5a52504 16264 {
34e77a92 16265 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16266 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16267 h->dynindx, 0))
16268 return FALSE;
e5a52504 16269 }
57e8b36a 16270
f5385ebf 16271 if (!h->def_regular)
252b5132
RH		 16272 {
16273 /* Mark the symbol as undefined, rather than as defined in
3a635617 16274 the .plt section. */
252b5132 16275 sym->st_shndx = SHN_UNDEF;
3a635617 16276 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16277 Otherwise, the PLT entry would provide a definition for
16278 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16279 and so the symbol would never be NULL. Leave the value if
16280 there were any relocations where pointer equality matters
16281 (this is a clue for the dynamic linker, to make function
16282 pointer comparisons work between an application and shared
16283 library). */
97323ad1 16284 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16285 sym->st_value = 0;
252b5132 16286 }
34e77a92
RS		 16287 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16288 {
16289 /* At least one non-call relocation references this .iplt entry,
16290 so the .iplt entry is the function's canonical address. */
16291 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16292 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16293 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16294 (output_bfd, htab->root.iplt->output_section));
16295 sym->st_value = (h->plt.offset
16296 + htab->root.iplt->output_section->vma
16297 + htab->root.iplt->output_offset);
16298 }
252b5132
RH		 16299 }
16300
f5385ebf 16301 if (h->needs_copy)
252b5132
RH		 16302 {
16303 asection * s;
947216bf 16304 Elf_Internal_Rela rel;
252b5132
RH		 16305
16306 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16307 BFD_ASSERT (h->dynindx != -1
16308 && (h->root.type == bfd_link_hash_defined
16309 || h->root.type == bfd_link_hash_defweak));
16310
362d30a1 16311 s = htab->srelbss;
252b5132
RH		 16312 BFD_ASSERT (s != NULL);
16313
00a97672 16314 rel.r_addend = 0;
252b5132
RH		 16315 rel.r_offset = (h->root.u.def.value
16316 + h->root.u.def.section->output_section->vma
16317 + h->root.u.def.section->output_offset);
16318 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 16319 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16320 }
16321
00a97672
RS		 16322 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16323 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16324 to the ".got" section. */
9637f6ef 16325 if (h == htab->root.hdynamic
00a97672 16326 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16327 sym->st_shndx = SHN_ABS;
16328
b34976b6 16329 return TRUE;
252b5132
RH		 16330}
16331
0855e32b
NS		 16332static void
16333arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16334 void *contents,
16335 const unsigned long *template, unsigned count)
16336{
16337 unsigned ix;
b38cadfb 16338
0855e32b
NS		 16339 for (ix = 0; ix != count; ix++)
16340 {
16341 unsigned long insn = template[ix];
16342
16343 /* Emit mov pc,rx if bx is not permitted. */
16344 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16345 insn = (insn & 0xf000000f) | 0x01a0f000;
16346 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16347 }
16348}
16349
99059e56
RM		 16350/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16351 other variants, NaCl needs this entry in a static executable's
16352 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16353 zero. For .iplt really only the last bundle is useful, and .iplt
16354 could have a shorter first entry, with each individual PLT entry's
16355 relative branch calculated differently so it targets the last
16356 bundle instead of the instruction before it (labelled .Lplt_tail
16357 above). But it's simpler to keep the size and layout of PLT0
16358 consistent with the dynamic case, at the cost of some dead code at
16359 the start of .iplt and the one dead store to the stack at the start
16360 of .Lplt_tail. */
16361static void
16362arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16363 asection *plt, bfd_vma got_displacement)
16364{
16365 unsigned int i;
16366
16367 put_arm_insn (htab, output_bfd,
16368 elf32_arm_nacl_plt0_entry[0]
16369 | arm_movw_immediate (got_displacement),
16370 plt->contents + 0);
16371 put_arm_insn (htab, output_bfd,
16372 elf32_arm_nacl_plt0_entry[1]
16373 | arm_movt_immediate (got_displacement),
16374 plt->contents + 4);
16375
16376 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16377 put_arm_insn (htab, output_bfd,
16378 elf32_arm_nacl_plt0_entry[i],
16379 plt->contents + (i * 4));
16380}
16381
252b5132
RH		 16382/* Finish up the dynamic sections. */
16383
b34976b6 16384static bfd_boolean
57e8b36a 16385elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16386{
16387 bfd * dynobj;
16388 asection * sgot;
16389 asection * sdyn;
4dfe6ac6
NC		 16390 struct elf32_arm_link_hash_table *htab;
16391
16392 htab = elf32_arm_hash_table (info);
16393 if (htab == NULL)
16394 return FALSE;
252b5132
RH		 16395
16396 dynobj = elf_hash_table (info)->dynobj;
16397
362d30a1 16398 sgot = htab->root.sgotplt;
894891db
NC		 16399 /* A broken linker script might have discarded the dynamic sections.
16400 Catch this here so that we do not seg-fault later on. */
16401 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16402 return FALSE;
3d4d4302 16403 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16404
16405 if (elf_hash_table (info)->dynamic_sections_created)
16406 {
16407 asection *splt;
16408 Elf32_External_Dyn *dyncon, *dynconend;
16409
362d30a1 16410 splt = htab->root.splt;
24a1ba0f 16411 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16412 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16413
16414 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16415 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16416
252b5132
RH		 16417 for (; dyncon < dynconend; dyncon++)
16418 {
16419 Elf_Internal_Dyn dyn;
16420 const char * name;
16421 asection * s;
16422
16423 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16424
16425 switch (dyn.d_tag)
16426 {
229fcec5
MM		 16427 unsigned int type;
16428
252b5132 16429 default:
7a2b07ff
NS		 16430 if (htab->vxworks_p
16431 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16432 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16433 break;
16434
229fcec5
MM		 16435 case DT_HASH:
16436 name = ".hash";
16437 goto get_vma_if_bpabi;
16438 case DT_STRTAB:
16439 name = ".dynstr";
16440 goto get_vma_if_bpabi;
16441 case DT_SYMTAB:
16442 name = ".dynsym";
16443 goto get_vma_if_bpabi;
c0042f5d
MM		 16444 case DT_VERSYM:
16445 name = ".gnu.version";
16446 goto get_vma_if_bpabi;
16447 case DT_VERDEF:
16448 name = ".gnu.version_d";
16449 goto get_vma_if_bpabi;
16450 case DT_VERNEED:
16451 name = ".gnu.version_r";
16452 goto get_vma_if_bpabi;
16453
252b5132 16454 case DT_PLTGOT:
4ade44b7 16455 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16456 goto get_vma;
16457 case DT_JMPREL:
00a97672 16458 name = RELOC_SECTION (htab, ".plt");
252b5132 16459 get_vma:
4ade44b7 16460 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16461 if (s == NULL)
16462 {
4eca0228 16463 _bfd_error_handler
4ade44b7 16464 (_("could not find section %s"), name);
05456594
NC		 16465 bfd_set_error (bfd_error_invalid_operation);
16466 return FALSE;
16467 }
229fcec5 16468 if (!htab->symbian_p)
4ade44b7 16469 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16470 else
16471 /* In the BPABI, tags in the PT_DYNAMIC section point
16472 at the file offset, not the memory address, for the
16473 convenience of the post linker. */
4ade44b7 16474 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16475 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16476 break;
16477
229fcec5
MM		 16478 get_vma_if_bpabi:
16479 if (htab->symbian_p)
16480 goto get_vma;
16481 break;
16482
252b5132 16483 case DT_PLTRELSZ:
362d30a1 16484 s = htab->root.srelplt;
252b5132 16485 BFD_ASSERT (s != NULL);
eea6121a 16486 dyn.d_un.d_val = s->size;
252b5132
RH		 16487 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16488 break;
906e58ca 16489
252b5132 16490 case DT_RELSZ:
00a97672 16491 case DT_RELASZ:
229fcec5
MM		 16492 case DT_REL:
16493 case DT_RELA:
229fcec5
MM		 16494 /* In the BPABI, the DT_REL tag must point at the file
16495 offset, not the VMA, of the first relocation
16496 section. So, we use code similar to that in
16497 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 16498 relocation section, since relocation sections are
16499 never allocated under the BPABI. PLT relocs are also
16500 included. */
229fcec5
MM		 16501 if (htab->symbian_p)
16502 {
16503 unsigned int i;
16504 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16505 ? SHT_REL : SHT_RELA);
16506 dyn.d_un.d_val = 0;
16507 for (i = 1; i < elf_numsections (output_bfd); i++)
16508 {
906e58ca 16509 Elf_Internal_Shdr *hdr
229fcec5
MM		 16510 = elf_elfsections (output_bfd)[i];
16511 if (hdr->sh_type == type)
16512 {
906e58ca 16513 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16514 || dyn.d_tag == DT_RELASZ)
16515 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16516 else if ((ufile_ptr) hdr->sh_offset
16517 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16518 dyn.d_un.d_val = hdr->sh_offset;
16519 }
16520 }
16521 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16522 }
252b5132 16523 break;
88f7bcd5 16524
0855e32b 16525 case DT_TLSDESC_PLT:
99059e56 16526 s = htab->root.splt;
0855e32b
NS		 16527 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16528 + htab->dt_tlsdesc_plt);
16529 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16530 break;
16531
16532 case DT_TLSDESC_GOT:
99059e56 16533 s = htab->root.sgot;
0855e32b 16534 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16535 + htab->dt_tlsdesc_got);
0855e32b
NS		 16536 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16537 break;
16538
88f7bcd5
NC		 16539 /* Set the bottom bit of DT_INIT/FINI if the
16540 corresponding function is Thumb. */
16541 case DT_INIT:
16542 name = info->init_function;
16543 goto get_sym;
16544 case DT_FINI:
16545 name = info->fini_function;
16546 get_sym:
16547 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16548 then there is nothing to adjust. */
88f7bcd5
NC		 16549 if (dyn.d_un.d_val != 0)
16550 {
16551 struct elf_link_hash_entry * eh;
16552
16553 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16554 FALSE, FALSE, TRUE);
39d911fc
TP		 16555 if (eh != NULL
16556 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16557 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16558 {
16559 dyn.d_un.d_val |= 1;
b34976b6 16560 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16561 }
16562 }
16563 break;
252b5132
RH		 16564 }
16565 }
16566
24a1ba0f 16567 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16568 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16569 {
00a97672
RS		 16570 const bfd_vma *plt0_entry;
16571 bfd_vma got_address, plt_address, got_displacement;
16572
16573 /* Calculate the addresses of the GOT and PLT. */
16574 got_address = sgot->output_section->vma + sgot->output_offset;
16575 plt_address = splt->output_section->vma + splt->output_offset;
16576
16577 if (htab->vxworks_p)
16578 {
16579 /* The VxWorks GOT is relocated by the dynamic linker.
16580 Therefore, we must emit relocations rather than simply
16581 computing the values now. */
16582 Elf_Internal_Rela rel;
16583
16584 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16585 put_arm_insn (htab, output_bfd, plt0_entry[0],
16586 splt->contents + 0);
16587 put_arm_insn (htab, output_bfd, plt0_entry[1],
16588 splt->contents + 4);
16589 put_arm_insn (htab, output_bfd, plt0_entry[2],
16590 splt->contents + 8);
00a97672
RS		 16591 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16592
8029a119 16593 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16594 rel.r_offset = plt_address + 12;
16595 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16596 rel.r_addend = 0;
16597 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16598 htab->srelplt2->contents);
16599 }
b38cadfb 16600 else if (htab->nacl_p)
99059e56
RM		 16601 arm_nacl_put_plt0 (htab, output_bfd, splt,
16602 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16603 else if (using_thumb_only (htab))
16604 {
16605 got_displacement = got_address - (plt_address + 12);
16606
16607 plt0_entry = elf32_thumb2_plt0_entry;
16608 put_arm_insn (htab, output_bfd, plt0_entry[0],
16609 splt->contents + 0);
16610 put_arm_insn (htab, output_bfd, plt0_entry[1],
16611 splt->contents + 4);
16612 put_arm_insn (htab, output_bfd, plt0_entry[2],
16613 splt->contents + 8);
16614
16615 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16616 }
00a97672
RS		 16617 else
16618 {
16619 got_displacement = got_address - (plt_address + 16);
16620
16621 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16622 put_arm_insn (htab, output_bfd, plt0_entry[0],
16623 splt->contents + 0);
16624 put_arm_insn (htab, output_bfd, plt0_entry[1],
16625 splt->contents + 4);
16626 put_arm_insn (htab, output_bfd, plt0_entry[2],
16627 splt->contents + 8);
16628 put_arm_insn (htab, output_bfd, plt0_entry[3],
16629 splt->contents + 12);
5e681ec4 16630
5e681ec4 16631#ifdef FOUR_WORD_PLT
00a97672
RS		 16632 /* The displacement value goes in the otherwise-unused
16633 last word of the second entry. */
16634 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16635#else
00a97672 16636 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16637#endif
00a97672 16638 }
f7a74f8c 16639 }
252b5132
RH		 16640
16641 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16642 really seem like the right value. */
74541ad4
AM		 16643 if (splt->output_section->owner == output_bfd)
16644 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16645
0855e32b
NS		 16646 if (htab->dt_tlsdesc_plt)
16647 {
16648 bfd_vma got_address
16649 = sgot->output_section->vma + sgot->output_offset;
16650 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16651 + htab->root.sgot->output_offset);
16652 bfd_vma plt_address
16653 = splt->output_section->vma + splt->output_offset;
16654
b38cadfb 16655 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16656 splt->contents + htab->dt_tlsdesc_plt,
16657 dl_tlsdesc_lazy_trampoline, 6);
16658
16659 bfd_put_32 (output_bfd,
16660 gotplt_address + htab->dt_tlsdesc_got
16661 - (plt_address + htab->dt_tlsdesc_plt)
16662 - dl_tlsdesc_lazy_trampoline[6],
16663 splt->contents + htab->dt_tlsdesc_plt + 24);
16664 bfd_put_32 (output_bfd,
16665 got_address - (plt_address + htab->dt_tlsdesc_plt)
16666 - dl_tlsdesc_lazy_trampoline[7],
16667 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16668 }
16669
16670 if (htab->tls_trampoline)
16671 {
b38cadfb 16672 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16673 splt->contents + htab->tls_trampoline,
16674 tls_trampoline, 3);
16675#ifdef FOUR_WORD_PLT
16676 bfd_put_32 (output_bfd, 0x00000000,
16677 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16678#endif
0855e32b
NS		 16679 }
16680
0e1862bb
L		 16681 if (htab->vxworks_p
16682 && !bfd_link_pic (info)
16683 && htab->root.splt->size > 0)
00a97672
RS		 16684 {
16685 /* Correct the .rel(a).plt.unloaded relocations. They will have
16686 incorrect symbol indexes. */
16687 int num_plts;
eed62c48 16688 unsigned char *p;
00a97672 16689
362d30a1 16690 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16691 / htab->plt_entry_size);
16692 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16693
16694 for (; num_plts; num_plts--)
16695 {
16696 Elf_Internal_Rela rel;
16697
16698 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16699 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16700 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16701 p += RELOC_SIZE (htab);
16702
16703 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16704 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16705 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16706 p += RELOC_SIZE (htab);
16707 }
16708 }
252b5132
RH		 16709 }
16710
99059e56
RM		 16711 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16712 /* NaCl uses a special first entry in .iplt too. */
16713 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16714
252b5132 16715 /* Fill in the first three entries in the global offset table. */
229fcec5 16716 if (sgot)
252b5132 16717 {
229fcec5
MM		 16718 if (sgot->size > 0)
16719 {
16720 if (sdyn == NULL)
16721 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16722 else
16723 bfd_put_32 (output_bfd,
16724 sdyn->output_section->vma + sdyn->output_offset,
16725 sgot->contents);
16726 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16727 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16728 }
252b5132 16729
229fcec5
MM		 16730 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16731 }
252b5132 16732
b34976b6 16733 return TRUE;
252b5132
RH		 16734}
16735
ba96a88f 16736static void
57e8b36a 16737elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16738{
9b485d32 16739 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16740 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16741 struct elf_segment_map *m;
ba96a88f
NC		 16742
16743 i_ehdrp = elf_elfheader (abfd);
16744
94a3258f
PB		 16745 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16746 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16747 else
7394f108 16748 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16749 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16750
93204d3a
PB		 16751 if (link_info)
16752 {
16753 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16754 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16755 i_ehdrp->e_flags |= EF_ARM_BE8;
16756 }
3bfcb652
NC		 16757
16758 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16759 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16760 {
16761 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16762 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16763 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16764 else
16765 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16766 }
ac4c9b04
MG		 16767
16768 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16769 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16770 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16771 {
16772 unsigned int j;
16773
16774 if (m->count == 0)
16775 continue;
16776 for (j = 0; j < m->count; j++)
16777 {
f0728ee3 16778 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16779 break;
16780 }
16781 if (j == m->count)
16782 {
16783 m->p_flags = PF_X;
16784 m->p_flags_valid = 1;
16785 }
16786 }
ba96a88f
NC		 16787}
16788
99e4ae17 16789static enum elf_reloc_type_class
7e612e98
AM		 16790elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16791 const asection *rel_sec ATTRIBUTE_UNUSED,
16792 const Elf_Internal_Rela *rela)
99e4ae17 16793{
f51e552e 16794 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16795 {
16796 case R_ARM_RELATIVE:
16797 return reloc_class_relative;
16798 case R_ARM_JUMP_SLOT:
16799 return reloc_class_plt;
16800 case R_ARM_COPY:
16801 return reloc_class_copy;
109575d7
JW		 16802 case R_ARM_IRELATIVE:
16803 return reloc_class_ifunc;
99e4ae17
AJ		 16804 default:
16805 return reloc_class_normal;
16806 }
16807}
16808
e489d0ae 16809static void
57e8b36a 16810elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16811{
5a6c6817 16812 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16813}
16814
40a18ebd
NC		 16815/* Return TRUE if this is an unwinding table entry. */
16816
16817static bfd_boolean
16818is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16819{
0112cd26
NC		 16820 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16821 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16822}
16823
16824
16825/* Set the type and flags for an ARM section. We do this by
16826 the section name, which is a hack, but ought to work. */
16827
16828static bfd_boolean
16829elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16830{
16831 const char * name;
16832
16833 name = bfd_get_section_name (abfd, sec);
16834
16835 if (is_arm_elf_unwind_section_name (abfd, name))
16836 {
16837 hdr->sh_type = SHT_ARM_EXIDX;
16838 hdr->sh_flags |= SHF_LINK_ORDER;
16839 }
ac4c9b04 16840
f0728ee3
AV		 16841 if (sec->flags & SEC_ELF_PURECODE)
16842 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16843
40a18ebd
NC		 16844 return TRUE;
16845}
16846
6dc132d9
L		 16847/* Handle an ARM specific section when reading an object file. This is
16848 called when bfd_section_from_shdr finds a section with an unknown
16849 type. */
40a18ebd
NC		 16850
16851static bfd_boolean
16852elf32_arm_section_from_shdr (bfd *abfd,
16853 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16854 const char *name,
16855 int shindex)
40a18ebd
NC		 16856{
16857 /* There ought to be a place to keep ELF backend specific flags, but
16858 at the moment there isn't one. We just keep track of the
16859 sections by their name, instead. Fortunately, the ABI gives
16860 names for all the ARM specific sections, so we will probably get
16861 away with this. */
16862 switch (hdr->sh_type)
16863 {
16864 case SHT_ARM_EXIDX:
0951f019
RE		 16865 case SHT_ARM_PREEMPTMAP:
16866 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16867 break;
16868
16869 default:
16870 return FALSE;
16871 }
16872
6dc132d9 16873 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16874 return FALSE;
16875
16876 return TRUE;
16877}
e489d0ae 16878
44444f50
NC		 16879static _arm_elf_section_data *
16880get_arm_elf_section_data (asection * sec)
16881{
47b2e99c
JZ		 16882 if (sec && sec->owner && is_arm_elf (sec->owner))
16883 return elf32_arm_section_data (sec);
44444f50
NC		 16884 else
16885 return NULL;
8e3de13a
NC		 16886}
16887
4e617b1e
PB		 16888typedef struct
16889{
57402f1e 16890 void *flaginfo;
4e617b1e 16891 struct bfd_link_info *info;
91a5743d
PB		 16892 asection *sec;
16893 int sec_shndx;
6e0b88f1
AM		 16894 int (*func) (void *, const char *, Elf_Internal_Sym *,
16895 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16896} output_arch_syminfo;
16897
16898enum map_symbol_type
16899{
16900 ARM_MAP_ARM,
16901 ARM_MAP_THUMB,
16902 ARM_MAP_DATA
16903};
16904
16905
7413f23f 16906/* Output a single mapping symbol. */
4e617b1e
PB		 16907
16908static bfd_boolean
7413f23f
DJ		 16909elf32_arm_output_map_sym (output_arch_syminfo *osi,
16910 enum map_symbol_type type,
16911 bfd_vma offset)
4e617b1e
PB		 16912{
16913 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16914 Elf_Internal_Sym sym;
16915
91a5743d
PB		 16916 sym.st_value = osi->sec->output_section->vma
16917 + osi->sec->output_offset
16918 + offset;
4e617b1e
PB		 16919 sym.st_size = 0;
16920 sym.st_other = 0;
16921 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16922 sym.st_shndx = osi->sec_shndx;
35fc36a8 16923 sym.st_target_internal = 0;
fe33d2fa 16924 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16925 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16926}
16927
34e77a92
RS		 16928/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16929 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16930
16931static bfd_boolean
34e77a92
RS		 16932elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16933 bfd_boolean is_iplt_entry_p,
16934 union gotplt_union *root_plt,
16935 struct arm_plt_info *arm_plt)
4e617b1e 16936{
4e617b1e 16937 struct elf32_arm_link_hash_table *htab;
34e77a92 16938 bfd_vma addr, plt_header_size;
4e617b1e 16939
34e77a92 16940 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16941 return TRUE;
16942
4dfe6ac6
NC		 16943 htab = elf32_arm_hash_table (osi->info);
16944 if (htab == NULL)
16945 return FALSE;
16946
34e77a92
RS		 16947 if (is_iplt_entry_p)
16948 {
16949 osi->sec = htab->root.iplt;
16950 plt_header_size = 0;
16951 }
16952 else
16953 {
16954 osi->sec = htab->root.splt;
16955 plt_header_size = htab->plt_header_size;
16956 }
16957 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16958 (osi->info->output_bfd, osi->sec->output_section));
16959
16960 addr = root_plt->offset & -2;
4e617b1e
PB		 16961 if (htab->symbian_p)
16962 {
7413f23f 16963 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16964 return FALSE;
7413f23f 16965 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16966 return FALSE;
16967 }
16968 else if (htab->vxworks_p)
16969 {
7413f23f 16970 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16971 return FALSE;
7413f23f 16972 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16973 return FALSE;
7413f23f 16974 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16975 return FALSE;
7413f23f 16976 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16977 return FALSE;
16978 }
b38cadfb
NC		 16979 else if (htab->nacl_p)
16980 {
16981 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16982 return FALSE;
16983 }
eed94f8f
NC		 16984 else if (using_thumb_only (htab))
16985 {
16986 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16987 return FALSE;
6a631e86 16988 }
4e617b1e
PB		 16989 else
16990 {
34e77a92 16991 bfd_boolean thumb_stub_p;
bd97cb95 16992
34e77a92
RS		 16993 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16994 if (thumb_stub_p)
4e617b1e 16995 {
7413f23f 16996 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16997 return FALSE;
16998 }
16999#ifdef FOUR_WORD_PLT
7413f23f 17000 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17001 return FALSE;
7413f23f 17002 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17003 return FALSE;
17004#else
906e58ca 17005 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17006 so only need to output a mapping symbol for the first PLT entry and
17007 entries with thumb thunks. */
34e77a92 17008 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17009 {
7413f23f 17010 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17011 return FALSE;
17012 }
17013#endif
17014 }
17015
17016 return TRUE;
17017}
17018
34e77a92
RS		 17019/* Output mapping symbols for PLT entries associated with H. */
17020
17021static bfd_boolean
17022elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17023{
17024 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17025 struct elf32_arm_link_hash_entry *eh;
17026
17027 if (h->root.type == bfd_link_hash_indirect)
17028 return TRUE;
17029
17030 if (h->root.type == bfd_link_hash_warning)
17031 /* When warning symbols are created, they **replace** the "real"
17032 entry in the hash table, thus we never get to see the real
17033 symbol in a hash traversal. So look at it now. */
17034 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17035
17036 eh = (struct elf32_arm_link_hash_entry *) h;
17037 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17038 &h->plt, &eh->plt);
17039}
17040
4f4faa4d
TP		 17041/* Bind a veneered symbol to its veneer identified by its hash entry
17042 STUB_ENTRY. The veneered location thus loose its symbol. */
17043
17044static void
17045arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17046{
17047 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17048
17049 BFD_ASSERT (hash);
17050 hash->root.root.u.def.section = stub_entry->stub_sec;
17051 hash->root.root.u.def.value = stub_entry->stub_offset;
17052 hash->root.size = stub_entry->stub_size;
17053}
17054
7413f23f
DJ		 17055/* Output a single local symbol for a generated stub. */
17056
17057static bfd_boolean
17058elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17059 bfd_vma offset, bfd_vma size)
17060{
7413f23f
DJ		 17061 Elf_Internal_Sym sym;
17062
7413f23f
DJ		 17063 sym.st_value = osi->sec->output_section->vma
17064 + osi->sec->output_offset
17065 + offset;
17066 sym.st_size = size;
17067 sym.st_other = 0;
17068 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17069 sym.st_shndx = osi->sec_shndx;
35fc36a8 17070 sym.st_target_internal = 0;
57402f1e 17071 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17072}
4e617b1e 17073
da5938a2 17074static bfd_boolean
8029a119
NC		 17075arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17076 void * in_arg)
da5938a2
NC		 17077{
17078 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17079 asection *stub_sec;
17080 bfd_vma addr;
7413f23f 17081 char *stub_name;
9a008db3 17082 output_arch_syminfo *osi;
d3ce72d0 17083 const insn_sequence *template_sequence;
461a49ca
DJ		 17084 enum stub_insn_type prev_type;
17085 int size;
17086 int i;
17087 enum map_symbol_type sym_type;
da5938a2
NC		 17088
17089 /* Massage our args to the form they really have. */
17090 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17091 osi = (output_arch_syminfo *) in_arg;
da5938a2 17092
da5938a2
NC		 17093 stub_sec = stub_entry->stub_sec;
17094
17095 /* Ensure this stub is attached to the current section being
7413f23f 17096 processed. */
da5938a2
NC		 17097 if (stub_sec != osi->sec)
17098 return TRUE;
17099
7413f23f 17100 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17101 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17102
17103 if (arm_stub_sym_claimed (stub_entry->stub_type))
17104 arm_stub_claim_sym (stub_entry);
17105 else
7413f23f 17106 {
4f4faa4d
TP		 17107 stub_name = stub_entry->output_name;
17108 switch (template_sequence[0].type)
17109 {
17110 case ARM_TYPE:
17111 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17112 stub_entry->stub_size))
17113 return FALSE;
17114 break;
17115 case THUMB16_TYPE:
17116 case THUMB32_TYPE:
17117 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17118 stub_entry->stub_size))
17119 return FALSE;
17120 break;
17121 default:
17122 BFD_FAIL ();
17123 return 0;
17124 }
7413f23f 17125 }
da5938a2 17126
461a49ca
DJ		 17127 prev_type = DATA_TYPE;
17128 size = 0;
17129 for (i = 0; i < stub_entry->stub_template_size; i++)
17130 {
d3ce72d0 17131 switch (template_sequence[i].type)
461a49ca
DJ		 17132 {
17133 case ARM_TYPE:
17134 sym_type = ARM_MAP_ARM;
17135 break;
17136
17137 case THUMB16_TYPE:
48229727 17138 case THUMB32_TYPE:
461a49ca
DJ		 17139 sym_type = ARM_MAP_THUMB;
17140 break;
17141
17142 case DATA_TYPE:
17143 sym_type = ARM_MAP_DATA;
17144 break;
17145
17146 default:
17147 BFD_FAIL ();
4e31c731 17148 return FALSE;
461a49ca
DJ		 17149 }
17150
d3ce72d0 17151 if (template_sequence[i].type != prev_type)
461a49ca 17152 {
d3ce72d0 17153 prev_type = template_sequence[i].type;
461a49ca
DJ		 17154 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17155 return FALSE;
17156 }
17157
d3ce72d0 17158 switch (template_sequence[i].type)
461a49ca
DJ		 17159 {
17160 case ARM_TYPE:
48229727 17161 case THUMB32_TYPE:
461a49ca
DJ		 17162 size += 4;
17163 break;
17164
17165 case THUMB16_TYPE:
17166 size += 2;
17167 break;
17168
17169 case DATA_TYPE:
17170 size += 4;
17171 break;
17172
17173 default:
17174 BFD_FAIL ();
4e31c731 17175 return FALSE;
461a49ca
DJ		 17176 }
17177 }
17178
da5938a2
NC		 17179 return TRUE;
17180}
17181
33811162
DG		 17182/* Output mapping symbols for linker generated sections,
17183 and for those data-only sections that do not have a
17184 $d. */
4e617b1e
PB		 17185
17186static bfd_boolean
17187elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17188 struct bfd_link_info *info,
57402f1e 17189 void *flaginfo,
6e0b88f1
AM		 17190 int (*func) (void *, const char *,
17191 Elf_Internal_Sym *,
17192 asection *,
17193 struct elf_link_hash_entry *))
4e617b1e
PB		 17194{
17195 output_arch_syminfo osi;
17196 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17197 bfd_vma offset;
17198 bfd_size_type size;
33811162 17199 bfd *input_bfd;
4e617b1e
PB		 17200
17201 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17202 if (htab == NULL)
17203 return FALSE;
17204
906e58ca 17205 check_use_blx (htab);
91a5743d 17206
57402f1e 17207 osi.flaginfo = flaginfo;
4e617b1e
PB		 17208 osi.info = info;
17209 osi.func = func;
906e58ca 17210
33811162
DG		 17211 /* Add a $d mapping symbol to data-only sections that
17212 don't have any mapping symbol. This may result in (harmless) redundant
17213 mapping symbols. */
17214 for (input_bfd = info->input_bfds;
17215 input_bfd != NULL;
c72f2fb2 17216 input_bfd = input_bfd->link.next)
33811162
DG		 17217 {
17218 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17219 for (osi.sec = input_bfd->sections;
17220 osi.sec != NULL;
17221 osi.sec = osi.sec->next)
17222 {
17223 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17224 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17225 != 0)
33811162
DG		 17226 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17227 == SEC_HAS_CONTENTS
17228 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17229 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17230 && osi.sec->size > 0
17231 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17232 {
17233 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17234 (output_bfd, osi.sec->output_section);
17235 if (osi.sec_shndx != (int)SHN_BAD)
17236 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17237 }
17238 }
17239 }
17240
91a5743d
PB		 17241 /* ARM->Thumb glue. */
17242 if (htab->arm_glue_size > 0)
17243 {
3d4d4302
AM		 17244 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17245 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17246
17247 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17248 (output_bfd, osi.sec->output_section);
0e1862bb 17249 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17250 || htab->pic_veneer)
17251 size = ARM2THUMB_PIC_GLUE_SIZE;
17252 else if (htab->use_blx)
17253 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17254 else
17255 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17256
91a5743d
PB		 17257 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17258 {
7413f23f
DJ		 17259 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17260 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17261 }
17262 }
17263
17264 /* Thumb->ARM glue. */
17265 if (htab->thumb_glue_size > 0)
17266 {
3d4d4302
AM		 17267 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17268 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17269
17270 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17271 (output_bfd, osi.sec->output_section);
17272 size = THUMB2ARM_GLUE_SIZE;
17273
17274 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17275 {
7413f23f
DJ		 17276 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17277 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17278 }
17279 }
17280
845b51d6
PB		 17281 /* ARMv4 BX veneers. */
17282 if (htab->bx_glue_size > 0)
17283 {
3d4d4302
AM		 17284 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17285 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17286
17287 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17288 (output_bfd, osi.sec->output_section);
17289
7413f23f 17290 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17291 }
17292
8029a119
NC		 17293 /* Long calls stubs. */
17294 if (htab->stub_bfd && htab->stub_bfd->sections)
17295 {
da5938a2 17296 asection* stub_sec;
8029a119 17297
da5938a2
NC		 17298 for (stub_sec = htab->stub_bfd->sections;
17299 stub_sec != NULL;
8029a119
NC		 17300 stub_sec = stub_sec->next)
17301 {
17302 /* Ignore non-stub sections. */
17303 if (!strstr (stub_sec->name, STUB_SUFFIX))
17304 continue;
da5938a2 17305
8029a119 17306 osi.sec = stub_sec;
da5938a2 17307
8029a119
NC		 17308 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17309 (output_bfd, osi.sec->output_section);
da5938a2 17310
8029a119
NC		 17311 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17312 }
17313 }
da5938a2 17314
91a5743d 17315 /* Finally, output mapping symbols for the PLT. */
34e77a92 17316 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17317 {
34e77a92
RS		 17318 osi.sec = htab->root.splt;
17319 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17320 (output_bfd, osi.sec->output_section));
17321
17322 /* Output mapping symbols for the plt header. SymbianOS does not have a
17323 plt header. */
17324 if (htab->vxworks_p)
17325 {
17326 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17327 if (!bfd_link_pic (info))
34e77a92
RS		 17328 {
17329 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17330 return FALSE;
17331 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17332 return FALSE;
17333 }
17334 }
b38cadfb
NC		 17335 else if (htab->nacl_p)
17336 {
17337 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17338 return FALSE;
17339 }
eed94f8f
NC		 17340 else if (using_thumb_only (htab))
17341 {
17342 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17343 return FALSE;
17344 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17345 return FALSE;
17346 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17347 return FALSE;
17348 }
34e77a92 17349 else if (!htab->symbian_p)
4e617b1e 17350 {
7413f23f 17351 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17352 return FALSE;
34e77a92
RS		 17353#ifndef FOUR_WORD_PLT
17354 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17355 return FALSE;
34e77a92 17356#endif
4e617b1e
PB		 17357 }
17358 }
99059e56
RM		 17359 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17360 {
17361 /* NaCl uses a special first entry in .iplt too. */
17362 osi.sec = htab->root.iplt;
17363 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17364 (output_bfd, osi.sec->output_section));
17365 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17366 return FALSE;
17367 }
34e77a92
RS		 17368 if ((htab->root.splt && htab->root.splt->size > 0)
17369 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17370 {
34e77a92
RS		 17371 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17372 for (input_bfd = info->input_bfds;
17373 input_bfd != NULL;
c72f2fb2 17374 input_bfd = input_bfd->link.next)
34e77a92
RS		 17375 {
17376 struct arm_local_iplt_info **local_iplt;
17377 unsigned int i, num_syms;
4e617b1e 17378
34e77a92
RS		 17379 local_iplt = elf32_arm_local_iplt (input_bfd);
17380 if (local_iplt != NULL)
17381 {
17382 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17383 for (i = 0; i < num_syms; i++)
17384 if (local_iplt[i] != NULL
17385 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17386 &local_iplt[i]->root,
17387 &local_iplt[i]->arm))
17388 return FALSE;
17389 }
17390 }
17391 }
0855e32b
NS		 17392 if (htab->dt_tlsdesc_plt != 0)
17393 {
17394 /* Mapping symbols for the lazy tls trampoline. */
17395 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17396 return FALSE;
b38cadfb 17397
0855e32b
NS		 17398 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17399 htab->dt_tlsdesc_plt + 24))
17400 return FALSE;
17401 }
17402 if (htab->tls_trampoline != 0)
17403 {
17404 /* Mapping symbols for the tls trampoline. */
17405 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17406 return FALSE;
17407#ifdef FOUR_WORD_PLT
17408 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17409 htab->tls_trampoline + 12))
17410 return FALSE;
b38cadfb 17411#endif
0855e32b 17412 }
b38cadfb 17413
4e617b1e
PB		 17414 return TRUE;
17415}
17416
54ddd295
TP		 17417/* Filter normal symbols of CMSE entry functions of ABFD to include in
17418 the import library. All SYMCOUNT symbols of ABFD can be examined
17419 from their pointers in SYMS. Pointers of symbols to keep should be
17420 stored continuously at the beginning of that array.
17421
17422 Returns the number of symbols to keep. */
17423
17424static unsigned int
17425elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17426 struct bfd_link_info *info,
17427 asymbol **syms, long symcount)
17428{
17429 size_t maxnamelen;
17430 char *cmse_name;
17431 long src_count, dst_count = 0;
17432 struct elf32_arm_link_hash_table *htab;
17433
17434 htab = elf32_arm_hash_table (info);
17435 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17436 symcount = 0;
17437
17438 maxnamelen = 128;
17439 cmse_name = (char *) bfd_malloc (maxnamelen);
17440 for (src_count = 0; src_count < symcount; src_count++)
17441 {
17442 struct elf32_arm_link_hash_entry *cmse_hash;
17443 asymbol *sym;
17444 flagword flags;
17445 char *name;
17446 size_t namelen;
17447
17448 sym = syms[src_count];
17449 flags = sym->flags;
17450 name = (char *) bfd_asymbol_name (sym);
17451
17452 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17453 continue;
17454 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17455 continue;
17456
17457 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17458 if (namelen > maxnamelen)
17459 {
17460 cmse_name = (char *)
17461 bfd_realloc (cmse_name, namelen);
17462 maxnamelen = namelen;
17463 }
17464 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17465 cmse_hash = (struct elf32_arm_link_hash_entry *)
17466 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17467
17468 if (!cmse_hash
17469 || (cmse_hash->root.root.type != bfd_link_hash_defined
17470 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17471 || cmse_hash->root.type != STT_FUNC)
17472 continue;
17473
17474 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17475 continue;
17476
17477 syms[dst_count++] = sym;
17478 }
17479 free (cmse_name);
17480
17481 syms[dst_count] = NULL;
17482
17483 return dst_count;
17484}
17485
17486/* Filter symbols of ABFD to include in the import library. All
17487 SYMCOUNT symbols of ABFD can be examined from their pointers in
17488 SYMS. Pointers of symbols to keep should be stored continuously at
17489 the beginning of that array.
17490
17491 Returns the number of symbols to keep. */
17492
17493static unsigned int
17494elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17495 struct bfd_link_info *info,
17496 asymbol **syms, long symcount)
17497{
17498 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17499
17500 if (globals->cmse_implib)
17501 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17502 else
17503 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17504}
17505
e489d0ae
PB		 17506/* Allocate target specific section data. */
17507
17508static bfd_boolean
17509elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17510{
f592407e
AM		 17511 if (!sec->used_by_bfd)
17512 {
17513 _arm_elf_section_data *sdata;
17514 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17515
21d799b5 17516 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17517 if (sdata == NULL)
17518 return FALSE;
17519 sec->used_by_bfd = sdata;
17520 }
e489d0ae
PB		 17521
17522 return _bfd_elf_new_section_hook (abfd, sec);
17523}
17524
17525
17526/* Used to order a list of mapping symbols by address. */
17527
17528static int
17529elf32_arm_compare_mapping (const void * a, const void * b)
17530{
7f6a71ff
JM		 17531 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17532 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17533
17534 if (amap->vma > bmap->vma)
17535 return 1;
17536 else if (amap->vma < bmap->vma)
17537 return -1;
17538 else if (amap->type > bmap->type)
17539 /* Ensure results do not depend on the host qsort for objects with
17540 multiple mapping symbols at the same address by sorting on type
17541 after vma. */
17542 return 1;
17543 else if (amap->type < bmap->type)
17544 return -1;
17545 else
17546 return 0;
e489d0ae
PB		 17547}
17548
2468f9c9
PB		 17549/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17550
17551static unsigned long
17552offset_prel31 (unsigned long addr, bfd_vma offset)
17553{
17554 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17555}
17556
17557/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17558 relocations. */
17559
17560static void
17561copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17562{
17563 unsigned long first_word = bfd_get_32 (output_bfd, from);
17564 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17565
2468f9c9
PB		 17566 /* High bit of first word is supposed to be zero. */
17567 if ((first_word & 0x80000000ul) == 0)
17568 first_word = offset_prel31 (first_word, offset);
b38cadfb 17569
2468f9c9
PB		 17570 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17571 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17572 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17573 second_word = offset_prel31 (second_word, offset);
b38cadfb 17574
2468f9c9
PB		 17575 bfd_put_32 (output_bfd, first_word, to);
17576 bfd_put_32 (output_bfd, second_word, to + 4);
17577}
e489d0ae 17578
48229727
JB		 17579/* Data for make_branch_to_a8_stub(). */
17580
b38cadfb
NC		 17581struct a8_branch_to_stub_data
17582{
48229727
JB		 17583 asection *writing_section;
17584 bfd_byte *contents;
17585};
17586
17587
17588/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17589 places for a particular section. */
17590
17591static bfd_boolean
17592make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17593 void *in_arg)
48229727
JB		 17594{
17595 struct elf32_arm_stub_hash_entry *stub_entry;
17596 struct a8_branch_to_stub_data *data;
17597 bfd_byte *contents;
17598 unsigned long branch_insn;
17599 bfd_vma veneered_insn_loc, veneer_entry_loc;
17600 bfd_signed_vma branch_offset;
17601 bfd *abfd;
8d9d9490 17602 unsigned int loc;
48229727
JB		 17603
17604 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17605 data = (struct a8_branch_to_stub_data *) in_arg;
17606
17607 if (stub_entry->target_section != data->writing_section
4563a860 17608 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17609 return TRUE;
17610
17611 contents = data->contents;
17612
8d9d9490
TP		 17613 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17614 generated when both source and target are in the same section. */
48229727
JB		 17615 veneered_insn_loc = stub_entry->target_section->output_section->vma
17616 + stub_entry->target_section->output_offset
8d9d9490 17617 + stub_entry->source_value;
48229727
JB		 17618
17619 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17620 + stub_entry->stub_sec->output_offset
17621 + stub_entry->stub_offset;
17622
17623 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17624 veneered_insn_loc &= ~3u;
17625
17626 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17627
17628 abfd = stub_entry->target_section->owner;
8d9d9490 17629 loc = stub_entry->source_value;
48229727
JB		 17630
17631 /* We attempt to avoid this condition by setting stubs_always_after_branch
17632 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17633 This check is just to be on the safe side... */
17634 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17635 {
4eca0228
AM		 17636 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub is "
17637 "allocated in unsafe location"), abfd);
48229727
JB		 17638 return FALSE;
17639 }
17640
17641 switch (stub_entry->stub_type)
17642 {
17643 case arm_stub_a8_veneer_b:
17644 case arm_stub_a8_veneer_b_cond:
17645 branch_insn = 0xf0009000;
17646 goto jump24;
17647
17648 case arm_stub_a8_veneer_blx:
17649 branch_insn = 0xf000e800;
17650 goto jump24;
17651
17652 case arm_stub_a8_veneer_bl:
17653 {
17654 unsigned int i1, j1, i2, j2, s;
17655
17656 branch_insn = 0xf000d000;
17657
17658 jump24:
17659 if (branch_offset < -16777216 || branch_offset > 16777214)
17660 {
17661 /* There's not much we can do apart from complain if this
17662 happens. */
4eca0228
AM		 17663 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub out "
17664 "of range (input file too large)"), abfd);
48229727
JB		 17665 return FALSE;
17666 }
17667
17668 /* i1 = not(j1 eor s), so:
17669 not i1 = j1 eor s
17670 j1 = (not i1) eor s. */
17671
17672 branch_insn |= (branch_offset >> 1) & 0x7ff;
17673 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17674 i2 = (branch_offset >> 22) & 1;
17675 i1 = (branch_offset >> 23) & 1;
17676 s = (branch_offset >> 24) & 1;
17677 j1 = (!i1) ^ s;
17678 j2 = (!i2) ^ s;
17679 branch_insn |= j2 << 11;
17680 branch_insn |= j1 << 13;
17681 branch_insn |= s << 26;
17682 }
17683 break;
17684
17685 default:
17686 BFD_FAIL ();
17687 return FALSE;
17688 }
17689
8d9d9490
TP		 17690 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17691 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17692
17693 return TRUE;
17694}
17695
a504d23a
LA		 17696/* Beginning of stm32l4xx work-around. */
17697
17698/* Functions encoding instructions necessary for the emission of the
17699 fix-stm32l4xx-629360.
17700 Encoding is extracted from the
17701 ARM (C) Architecture Reference Manual
17702 ARMv7-A and ARMv7-R edition
17703 ARM DDI 0406C.b (ID072512). */
17704
17705static inline bfd_vma
82188b29 17706create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17707{
17708 /* A8.8.18 B (A8-334)
17709 B target_address (Encoding T4). */
17710 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17711 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17712 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17713
a504d23a
LA		 17714 int s = ((branch_offset & 0x1000000) >> 24);
17715 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17716 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17717
17718 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17719 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17720
17721 bfd_vma patched_inst = 0xf0009000
17722 | s << 26 /* S. */
17723 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17724 | j1 << 13 /* J1. */
17725 | j2 << 11 /* J2. */
17726 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17727
17728 return patched_inst;
17729}
17730
17731static inline bfd_vma
17732create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17733{
17734 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17735 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17736 bfd_vma patched_inst = 0xe8900000
17737 | (/*W=*/wback << 21)
17738 | (base_reg << 16)
17739 | (reg_mask & 0x0000ffff);
17740
17741 return patched_inst;
17742}
17743
17744static inline bfd_vma
17745create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17746{
17747 /* A8.8.60 LDMDB/LDMEA (A8-402)
17748 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17749 bfd_vma patched_inst = 0xe9100000
17750 | (/*W=*/wback << 21)
17751 | (base_reg << 16)
17752 | (reg_mask & 0x0000ffff);
17753
17754 return patched_inst;
17755}
17756
17757static inline bfd_vma
17758create_instruction_mov (int target_reg, int source_reg)
17759{
17760 /* A8.8.103 MOV (register) (A8-486)
17761 MOV Rd, Rm (Encoding T1). */
17762 bfd_vma patched_inst = 0x4600
17763 | (target_reg & 0x7)
17764 | ((target_reg & 0x8) >> 3) << 7
17765 | (source_reg << 3);
17766
17767 return patched_inst;
17768}
17769
17770static inline bfd_vma
17771create_instruction_sub (int target_reg, int source_reg, int value)
17772{
17773 /* A8.8.221 SUB (immediate) (A8-708)
17774 SUB Rd, Rn, #value (Encoding T3). */
17775 bfd_vma patched_inst = 0xf1a00000
17776 | (target_reg << 8)
17777 | (source_reg << 16)
17778 | (/*S=*/0 << 20)
17779 | ((value & 0x800) >> 11) << 26
17780 | ((value & 0x700) >> 8) << 12
17781 | (value & 0x0ff);
17782
17783 return patched_inst;
17784}
17785
17786static inline bfd_vma
9239bbd3 17787create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17788 int first_reg)
17789{
17790 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17791 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17792 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17793 | (/*W=*/wback << 21)
17794 | (base_reg << 16)
9239bbd3
CM		 17795 | (num_words & 0x000000ff)
17796 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17797 | (first_reg & 0x00000001) << 22;
17798
17799 return patched_inst;
17800}
17801
17802static inline bfd_vma
9239bbd3
CM		 17803create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17804 int first_reg)
a504d23a
LA		 17805{
17806 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17807 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17808 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17809 | (base_reg << 16)
9239bbd3
CM		 17810 | (num_words & 0x000000ff)
17811 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17812 | (first_reg & 0x00000001) << 22;
17813
17814 return patched_inst;
17815}
17816
17817static inline bfd_vma
17818create_instruction_udf_w (int value)
17819{
17820 /* A8.8.247 UDF (A8-758)
17821 Undefined (Encoding T2). */
17822 bfd_vma patched_inst = 0xf7f0a000
17823 | (value & 0x00000fff)
17824 | (value & 0x000f0000) << 16;
17825
17826 return patched_inst;
17827}
17828
17829static inline bfd_vma
17830create_instruction_udf (int value)
17831{
17832 /* A8.8.247 UDF (A8-758)
17833 Undefined (Encoding T1). */
17834 bfd_vma patched_inst = 0xde00
17835 | (value & 0xff);
17836
17837 return patched_inst;
17838}
17839
17840/* Functions writing an instruction in memory, returning the next
17841 memory position to write to. */
17842
17843static inline bfd_byte *
17844push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17845 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17846{
17847 put_thumb2_insn (htab, output_bfd, insn, pt);
17848 return pt + 4;
17849}
17850
17851static inline bfd_byte *
17852push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17853 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17854{
17855 put_thumb_insn (htab, output_bfd, insn, pt);
17856 return pt + 2;
17857}
17858
17859/* Function filling up a region in memory with T1 and T2 UDFs taking
17860 care of alignment. */
17861
17862static bfd_byte *
17863stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17864 bfd * output_bfd,
17865 const bfd_byte * const base_stub_contents,
17866 bfd_byte * const from_stub_contents,
17867 const bfd_byte * const end_stub_contents)
17868{
17869 bfd_byte *current_stub_contents = from_stub_contents;
17870
17871 /* Fill the remaining of the stub with deterministic contents : UDF
17872 instructions.
17873 Check if realignment is needed on modulo 4 frontier using T1, to
17874 further use T2. */
17875 if ((current_stub_contents < end_stub_contents)
17876 && !((current_stub_contents - base_stub_contents) % 2)
17877 && ((current_stub_contents - base_stub_contents) % 4))
17878 current_stub_contents =
17879 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17880 create_instruction_udf (0));
17881
17882 for (; current_stub_contents < end_stub_contents;)
17883 current_stub_contents =
17884 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17885 create_instruction_udf_w (0));
17886
17887 return current_stub_contents;
17888}
17889
17890/* Functions writing the stream of instructions equivalent to the
17891 derived sequence for ldmia, ldmdb, vldm respectively. */
17892
17893static void
17894stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17895 bfd * output_bfd,
17896 const insn32 initial_insn,
17897 const bfd_byte *const initial_insn_addr,
17898 bfd_byte *const base_stub_contents)
17899{
17900 int wback = (initial_insn & 0x00200000) >> 21;
17901 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17902 int insn_all_registers = initial_insn & 0x0000ffff;
17903 int insn_low_registers, insn_high_registers;
17904 int usable_register_mask;
17905 int nb_registers = popcount (insn_all_registers);
17906 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17907 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17908 bfd_byte *current_stub_contents = base_stub_contents;
17909
17910 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17911
17912 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17913 smaller than 8 registers load sequences that do not cause the
17914 hardware issue. */
17915 if (nb_registers <= 8)
17916 {
17917 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17918 current_stub_contents =
17919 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17920 initial_insn);
17921
17922 /* B initial_insn_addr+4. */
17923 if (!restore_pc)
17924 current_stub_contents =
17925 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17926 create_instruction_branch_absolute
82188b29 17927 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17928
17929 /* Fill the remaining of the stub with deterministic contents. */
17930 current_stub_contents =
17931 stm32l4xx_fill_stub_udf (htab, output_bfd,
17932 base_stub_contents, current_stub_contents,
17933 base_stub_contents +
17934 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17935
17936 return;
17937 }
17938
17939 /* - reg_list[13] == 0. */
17940 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17941
17942 /* - reg_list[14] & reg_list[15] != 1. */
17943 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17944
17945 /* - if (wback==1) reg_list[rn] == 0. */
17946 BFD_ASSERT (!wback || !restore_rn);
17947
17948 /* - nb_registers > 8. */
17949 BFD_ASSERT (popcount (insn_all_registers) > 8);
17950
17951 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17952
17953 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17954 - One with the 7 lowest registers (register mask 0x007F)
17955 This LDM will finally contain between 2 and 7 registers
17956 - One with the 7 highest registers (register mask 0xDF80)
17957 This ldm will finally contain between 2 and 7 registers. */
17958 insn_low_registers = insn_all_registers & 0x007F;
17959 insn_high_registers = insn_all_registers & 0xDF80;
17960
17961 /* A spare register may be needed during this veneer to temporarily
17962 handle the base register. This register will be restored with the
17963 last LDM operation.
17964 The usable register may be any general purpose register (that
17965 excludes PC, SP, LR : register mask is 0x1FFF). */
17966 usable_register_mask = 0x1FFF;
17967
17968 /* Generate the stub function. */
17969 if (wback)
17970 {
17971 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17972 current_stub_contents =
17973 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17974 create_instruction_ldmia
17975 (rn, /*wback=*/1, insn_low_registers));
17976
17977 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17978 current_stub_contents =
17979 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17980 create_instruction_ldmia
17981 (rn, /*wback=*/1, insn_high_registers));
17982 if (!restore_pc)
17983 {
17984 /* B initial_insn_addr+4. */
17985 current_stub_contents =
17986 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17987 create_instruction_branch_absolute
82188b29 17988 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17989 }
17990 }
17991 else /* if (!wback). */
17992 {
17993 ri = rn;
17994
17995 /* If Rn is not part of the high-register-list, move it there. */
17996 if (!(insn_high_registers & (1 << rn)))
17997 {
17998 /* Choose a Ri in the high-register-list that will be restored. */
17999 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18000
18001 /* MOV Ri, Rn. */
18002 current_stub_contents =
18003 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18004 create_instruction_mov (ri, rn));
18005 }
18006
18007 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18008 current_stub_contents =
18009 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18010 create_instruction_ldmia
18011 (ri, /*wback=*/1, insn_low_registers));
18012
18013 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18014 current_stub_contents =
18015 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18016 create_instruction_ldmia
18017 (ri, /*wback=*/0, insn_high_registers));
18018
18019 if (!restore_pc)
18020 {
18021 /* B initial_insn_addr+4. */
18022 current_stub_contents =
18023 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18024 create_instruction_branch_absolute
82188b29 18025 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18026 }
18027 }
18028
18029 /* Fill the remaining of the stub with deterministic contents. */
18030 current_stub_contents =
18031 stm32l4xx_fill_stub_udf (htab, output_bfd,
18032 base_stub_contents, current_stub_contents,
18033 base_stub_contents +
18034 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18035}
18036
18037static void
18038stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18039 bfd * output_bfd,
18040 const insn32 initial_insn,
18041 const bfd_byte *const initial_insn_addr,
18042 bfd_byte *const base_stub_contents)
18043{
18044 int wback = (initial_insn & 0x00200000) >> 21;
18045 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18046 int insn_all_registers = initial_insn & 0x0000ffff;
18047 int insn_low_registers, insn_high_registers;
18048 int usable_register_mask;
18049 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18050 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18051 int nb_registers = popcount (insn_all_registers);
18052 bfd_byte *current_stub_contents = base_stub_contents;
18053
18054 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18055
18056 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18057 smaller than 8 registers load sequences that do not cause the
18058 hardware issue. */
18059 if (nb_registers <= 8)
18060 {
18061 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18062 current_stub_contents =
18063 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18064 initial_insn);
18065
18066 /* B initial_insn_addr+4. */
18067 current_stub_contents =
18068 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18069 create_instruction_branch_absolute
82188b29 18070 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18071
18072 /* Fill the remaining of the stub with deterministic contents. */
18073 current_stub_contents =
18074 stm32l4xx_fill_stub_udf (htab, output_bfd,
18075 base_stub_contents, current_stub_contents,
18076 base_stub_contents +
18077 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18078
18079 return;
18080 }
18081
18082 /* - reg_list[13] == 0. */
18083 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18084
18085 /* - reg_list[14] & reg_list[15] != 1. */
18086 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18087
18088 /* - if (wback==1) reg_list[rn] == 0. */
18089 BFD_ASSERT (!wback || !restore_rn);
18090
18091 /* - nb_registers > 8. */
18092 BFD_ASSERT (popcount (insn_all_registers) > 8);
18093
18094 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18095
18096 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18097 - One with the 7 lowest registers (register mask 0x007F)
18098 This LDM will finally contain between 2 and 7 registers
18099 - One with the 7 highest registers (register mask 0xDF80)
18100 This ldm will finally contain between 2 and 7 registers. */
18101 insn_low_registers = insn_all_registers & 0x007F;
18102 insn_high_registers = insn_all_registers & 0xDF80;
18103
18104 /* A spare register may be needed during this veneer to temporarily
18105 handle the base register. This register will be restored with
18106 the last LDM operation.
18107 The usable register may be any general purpose register (that excludes
18108 PC, SP, LR : register mask is 0x1FFF). */
18109 usable_register_mask = 0x1FFF;
18110
18111 /* Generate the stub function. */
18112 if (!wback && !restore_pc && !restore_rn)
18113 {
18114 /* Choose a Ri in the low-register-list that will be restored. */
18115 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18116
18117 /* MOV Ri, Rn. */
18118 current_stub_contents =
18119 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18120 create_instruction_mov (ri, rn));
18121
18122 /* LDMDB Ri!, {R-high-register-list}. */
18123 current_stub_contents =
18124 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18125 create_instruction_ldmdb
18126 (ri, /*wback=*/1, insn_high_registers));
18127
18128 /* LDMDB Ri, {R-low-register-list}. */
18129 current_stub_contents =
18130 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18131 create_instruction_ldmdb
18132 (ri, /*wback=*/0, insn_low_registers));
18133
18134 /* B initial_insn_addr+4. */
18135 current_stub_contents =
18136 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18137 create_instruction_branch_absolute
82188b29 18138 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18139 }
18140 else if (wback && !restore_pc && !restore_rn)
18141 {
18142 /* LDMDB Rn!, {R-high-register-list}. */
18143 current_stub_contents =
18144 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18145 create_instruction_ldmdb
18146 (rn, /*wback=*/1, insn_high_registers));
18147
18148 /* LDMDB Rn!, {R-low-register-list}. */
18149 current_stub_contents =
18150 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18151 create_instruction_ldmdb
18152 (rn, /*wback=*/1, insn_low_registers));
18153
18154 /* B initial_insn_addr+4. */
18155 current_stub_contents =
18156 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18157 create_instruction_branch_absolute
82188b29 18158 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18159 }
18160 else if (!wback && restore_pc && !restore_rn)
18161 {
18162 /* Choose a Ri in the high-register-list that will be restored. */
18163 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18164
18165 /* SUB Ri, Rn, #(4*nb_registers). */
18166 current_stub_contents =
18167 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18168 create_instruction_sub (ri, rn, (4 * nb_registers)));
18169
18170 /* LDMIA Ri!, {R-low-register-list}. */
18171 current_stub_contents =
18172 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18173 create_instruction_ldmia
18174 (ri, /*wback=*/1, insn_low_registers));
18175
18176 /* LDMIA Ri, {R-high-register-list}. */
18177 current_stub_contents =
18178 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18179 create_instruction_ldmia
18180 (ri, /*wback=*/0, insn_high_registers));
18181 }
18182 else if (wback && restore_pc && !restore_rn)
18183 {
18184 /* Choose a Ri in the high-register-list that will be restored. */
18185 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18186
18187 /* SUB Rn, Rn, #(4*nb_registers) */
18188 current_stub_contents =
18189 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18190 create_instruction_sub (rn, rn, (4 * nb_registers)));
18191
18192 /* MOV Ri, Rn. */
18193 current_stub_contents =
18194 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18195 create_instruction_mov (ri, rn));
18196
18197 /* LDMIA Ri!, {R-low-register-list}. */
18198 current_stub_contents =
18199 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18200 create_instruction_ldmia
18201 (ri, /*wback=*/1, insn_low_registers));
18202
18203 /* LDMIA Ri, {R-high-register-list}. */
18204 current_stub_contents =
18205 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18206 create_instruction_ldmia
18207 (ri, /*wback=*/0, insn_high_registers));
18208 }
18209 else if (!wback && !restore_pc && restore_rn)
18210 {
18211 ri = rn;
18212 if (!(insn_low_registers & (1 << rn)))
18213 {
18214 /* Choose a Ri in the low-register-list that will be restored. */
18215 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18216
18217 /* MOV Ri, Rn. */
18218 current_stub_contents =
18219 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18220 create_instruction_mov (ri, rn));
18221 }
18222
18223 /* LDMDB Ri!, {R-high-register-list}. */
18224 current_stub_contents =
18225 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18226 create_instruction_ldmdb
18227 (ri, /*wback=*/1, insn_high_registers));
18228
18229 /* LDMDB Ri, {R-low-register-list}. */
18230 current_stub_contents =
18231 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18232 create_instruction_ldmdb
18233 (ri, /*wback=*/0, insn_low_registers));
18234
18235 /* B initial_insn_addr+4. */
18236 current_stub_contents =
18237 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18238 create_instruction_branch_absolute
82188b29 18239 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18240 }
18241 else if (!wback && restore_pc && restore_rn)
18242 {
18243 ri = rn;
18244 if (!(insn_high_registers & (1 << rn)))
18245 {
18246 /* Choose a Ri in the high-register-list that will be restored. */
18247 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18248 }
18249
18250 /* SUB Ri, Rn, #(4*nb_registers). */
18251 current_stub_contents =
18252 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18253 create_instruction_sub (ri, rn, (4 * nb_registers)));
18254
18255 /* LDMIA Ri!, {R-low-register-list}. */
18256 current_stub_contents =
18257 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18258 create_instruction_ldmia
18259 (ri, /*wback=*/1, insn_low_registers));
18260
18261 /* LDMIA Ri, {R-high-register-list}. */
18262 current_stub_contents =
18263 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18264 create_instruction_ldmia
18265 (ri, /*wback=*/0, insn_high_registers));
18266 }
18267 else if (wback && restore_rn)
18268 {
18269 /* The assembler should not have accepted to encode this. */
18270 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18271 "undefined behavior.\n");
18272 }
18273
18274 /* Fill the remaining of the stub with deterministic contents. */
18275 current_stub_contents =
18276 stm32l4xx_fill_stub_udf (htab, output_bfd,
18277 base_stub_contents, current_stub_contents,
18278 base_stub_contents +
18279 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18280
18281}
18282
18283static void
18284stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18285 bfd * output_bfd,
18286 const insn32 initial_insn,
18287 const bfd_byte *const initial_insn_addr,
18288 bfd_byte *const base_stub_contents)
18289{
9239bbd3 18290 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18291 bfd_byte *current_stub_contents = base_stub_contents;
18292
18293 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18294
18295 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18296 smaller than 8 words load sequences that do not cause the
a504d23a 18297 hardware issue. */
9239bbd3 18298 if (num_words <= 8)
a504d23a
LA		 18299 {
18300 /* Untouched instruction. */
18301 current_stub_contents =
18302 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18303 initial_insn);
18304
18305 /* B initial_insn_addr+4. */
18306 current_stub_contents =
18307 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18308 create_instruction_branch_absolute
82188b29 18309 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18310 }
18311 else
18312 {
9eaff861 18313 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18314 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18315 bfd_boolean is_ia_nobang = /* (IA without !). */
18316 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18317 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18318 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18319 bfd_boolean is_db_bang = /* (DB with !). */
18320 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18321 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18322 /* d = UInt (Vd:D);. */
9239bbd3 18323 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18324 | (((unsigned int)initial_insn << 9) >> 31);
18325
9239bbd3
CM		 18326 /* Compute the number of 8-words chunks needed to split. */
18327 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18328 int chunk;
18329
18330 /* The test coverage has been done assuming the following
18331 hypothesis that exactly one of the previous is_ predicates is
18332 true. */
9239bbd3
CM		 18333 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18334 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18335
9239bbd3 18336 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18337 cases, then we emit the adjustments:
18338
18339 vldm rx, {...}
18340 -> vldm rx!, {8_words_or_less} for each needed 8_word
18341 -> sub rx, rx, #size (list)
18342
18343 vldm rx!, {...}
18344 -> vldm rx!, {8_words_or_less} for each needed 8_word
18345 This also handles vpop instruction (when rx is sp)
18346
18347 vldmd rx!, {...}
18348 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18349 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18350 {
9239bbd3
CM		 18351 bfd_vma new_insn = 0;
18352
a504d23a
LA		 18353 if (is_ia_nobang || is_ia_bang)
18354 {
9239bbd3
CM		 18355 new_insn = create_instruction_vldmia
18356 (base_reg,
18357 is_dp,
18358 /*wback= . */1,
18359 chunks - (chunk + 1) ?
18360 8 : num_words - chunk * 8,
18361 first_reg + chunk * 8);
a504d23a
LA		 18362 }
18363 else if (is_db_bang)
18364 {
9239bbd3
CM		 18365 new_insn = create_instruction_vldmdb
18366 (base_reg,
18367 is_dp,
18368 chunks - (chunk + 1) ?
18369 8 : num_words - chunk * 8,
18370 first_reg + chunk * 8);
a504d23a 18371 }
9239bbd3
CM		 18372
18373 if (new_insn)
18374 current_stub_contents =
18375 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18376 new_insn);
a504d23a
LA		 18377 }
18378
18379 /* Only this case requires the base register compensation
18380 subtract. */
18381 if (is_ia_nobang)
18382 {
18383 current_stub_contents =
18384 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18385 create_instruction_sub
9239bbd3 18386 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18387 }
18388
18389 /* B initial_insn_addr+4. */
18390 current_stub_contents =
18391 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18392 create_instruction_branch_absolute
82188b29 18393 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18394 }
18395
18396 /* Fill the remaining of the stub with deterministic contents. */
18397 current_stub_contents =
18398 stm32l4xx_fill_stub_udf (htab, output_bfd,
18399 base_stub_contents, current_stub_contents,
18400 base_stub_contents +
18401 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18402}
18403
18404static void
18405stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18406 bfd * output_bfd,
18407 const insn32 wrong_insn,
18408 const bfd_byte *const wrong_insn_addr,
18409 bfd_byte *const stub_contents)
18410{
18411 if (is_thumb2_ldmia (wrong_insn))
18412 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18413 wrong_insn, wrong_insn_addr,
18414 stub_contents);
18415 else if (is_thumb2_ldmdb (wrong_insn))
18416 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18417 wrong_insn, wrong_insn_addr,
18418 stub_contents);
18419 else if (is_thumb2_vldm (wrong_insn))
18420 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18421 wrong_insn, wrong_insn_addr,
18422 stub_contents);
18423}
18424
18425/* End of stm32l4xx work-around. */
18426
18427
e489d0ae
PB		 18428/* Do code byteswapping. Return FALSE afterwards so that the section is
18429 written out as normal. */
18430
18431static bfd_boolean
c7b8f16e 18432elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18433 struct bfd_link_info *link_info,
18434 asection *sec,
e489d0ae
PB		 18435 bfd_byte *contents)
18436{
48229727 18437 unsigned int mapcount, errcount;
8e3de13a 18438 _arm_elf_section_data *arm_data;
c7b8f16e 18439 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18440 elf32_arm_section_map *map;
c7b8f16e 18441 elf32_vfp11_erratum_list *errnode;
a504d23a 18442 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18443 bfd_vma ptr;
18444 bfd_vma end;
c7b8f16e 18445 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18446 bfd_byte tmp;
48229727 18447 unsigned int i;
57e8b36a 18448
4dfe6ac6
NC		 18449 if (globals == NULL)
18450 return FALSE;
18451
8e3de13a
NC		 18452 /* If this section has not been allocated an _arm_elf_section_data
18453 structure then we cannot record anything. */
18454 arm_data = get_arm_elf_section_data (sec);
18455 if (arm_data == NULL)
18456 return FALSE;
18457
18458 mapcount = arm_data->mapcount;
18459 map = arm_data->map;
c7b8f16e
JB		 18460 errcount = arm_data->erratumcount;
18461
18462 if (errcount != 0)
18463 {
18464 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18465
18466 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18467 errnode = errnode->next)
18468 {
18469 bfd_vma target = errnode->vma - offset;
18470
18471 switch (errnode->type)
18472 {
18473 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18474 {
18475 bfd_vma branch_to_veneer;
18476 /* Original condition code of instruction, plus bit mask for
18477 ARM B instruction. */
18478 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18479 | 0x0a000000;
c7b8f16e
JB		 18480
18481 /* The instruction is before the label. */
91d6fa6a 18482 target -= 4;
c7b8f16e
JB		 18483
18484 /* Above offset included in -4 below. */
18485 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18486 - errnode->vma - 4;
c7b8f16e
JB		 18487
18488 if ((signed) branch_to_veneer < -(1 << 25)
18489 || (signed) branch_to_veneer >= (1 << 25))
4eca0228
AM		 18490 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18491 "range"), output_bfd);
c7b8f16e 18492
99059e56
RM		 18493 insn |= (branch_to_veneer >> 2) & 0xffffff;
18494 contents[endianflip ^ target] = insn & 0xff;
18495 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18496 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18497 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18498 }
18499 break;
c7b8f16e
JB		 18500
18501 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18502 {
18503 bfd_vma branch_from_veneer;
18504 unsigned int insn;
c7b8f16e 18505
99059e56
RM		 18506 /* Take size of veneer into account. */
18507 branch_from_veneer = errnode->u.v.branch->vma
18508 - errnode->vma - 12;
c7b8f16e
JB		 18509
18510 if ((signed) branch_from_veneer < -(1 << 25)
18511 || (signed) branch_from_veneer >= (1 << 25))
4eca0228
AM		 18512 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18513 "range"), output_bfd);
c7b8f16e 18514
99059e56
RM		 18515 /* Original instruction. */
18516 insn = errnode->u.v.branch->u.b.vfp_insn;
18517 contents[endianflip ^ target] = insn & 0xff;
18518 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18519 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18520 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18521
18522 /* Branch back to insn after original insn. */
18523 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18524 contents[endianflip ^ (target + 4)] = insn & 0xff;
18525 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18526 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18527 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18528 }
18529 break;
c7b8f16e 18530
99059e56
RM		 18531 default:
18532 abort ();
18533 }
18534 }
c7b8f16e 18535 }
e489d0ae 18536
a504d23a
LA		 18537 if (arm_data->stm32l4xx_erratumcount != 0)
18538 {
18539 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18540 stm32l4xx_errnode != 0;
18541 stm32l4xx_errnode = stm32l4xx_errnode->next)
18542 {
18543 bfd_vma target = stm32l4xx_errnode->vma - offset;
18544
18545 switch (stm32l4xx_errnode->type)
18546 {
18547 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18548 {
18549 unsigned int insn;
18550 bfd_vma branch_to_veneer =
18551 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18552
18553 if ((signed) branch_to_veneer < -(1 << 24)
18554 || (signed) branch_to_veneer >= (1 << 24))
18555 {
18556 bfd_vma out_of_range =
18557 ((signed) branch_to_veneer < -(1 << 24)) ?
18558 - branch_to_veneer - (1 << 24) :
18559 ((signed) branch_to_veneer >= (1 << 24)) ?
18560 branch_to_veneer - (1 << 24) : 0;
18561
4eca0228 18562 _bfd_error_handler
a504d23a 18563 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 18564 "Jump out of range by %ld bytes. "
a504d23a
LA		 18565 "Cannot encode branch instruction. "),
18566 output_bfd,
eee926f2 18567 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 18568 out_of_range);
18569 continue;
18570 }
18571
18572 insn = create_instruction_branch_absolute
82188b29 18573 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18574
18575 /* The instruction is before the label. */
18576 target -= 4;
18577
18578 put_thumb2_insn (globals, output_bfd,
18579 (bfd_vma) insn, contents + target);
18580 }
18581 break;
18582
18583 case STM32L4XX_ERRATUM_VENEER:
18584 {
82188b29
NC		 18585 bfd_byte * veneer;
18586 bfd_byte * veneer_r;
a504d23a
LA		 18587 unsigned int insn;
18588
82188b29
NC		 18589 veneer = contents + target;
18590 veneer_r = veneer
18591 + stm32l4xx_errnode->u.b.veneer->vma
18592 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18593
18594 if ((signed) (veneer_r - veneer -
18595 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18596 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18597 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18598 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18599 || (signed) (veneer_r - veneer) >= (1 << 24))
18600 {
4eca0228
AM		 18601 _bfd_error_handler (_("%B: error: Cannot create STM32L4XX "
18602 "veneer."), output_bfd);
a504d23a
LA		 18603 continue;
18604 }
18605
18606 /* Original instruction. */
18607 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18608
18609 stm32l4xx_create_replacing_stub
18610 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18611 }
18612 break;
18613
18614 default:
18615 abort ();
18616 }
18617 }
18618 }
18619
2468f9c9
PB		 18620 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18621 {
18622 arm_unwind_table_edit *edit_node
99059e56 18623 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18624 /* Now, sec->size is the size of the section we will write. The original
99059e56 18625 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18626 markers) was sec->rawsize. (This isn't the case if we perform no
18627 edits, then rawsize will be zero and we should use size). */
21d799b5 18628 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18629 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18630 unsigned int in_index, out_index;
18631 bfd_vma add_to_offsets = 0;
18632
18633 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18634 {
2468f9c9
PB		 18635 if (edit_node)
18636 {
18637 unsigned int edit_index = edit_node->index;
b38cadfb 18638
2468f9c9 18639 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18640 {
2468f9c9
PB		 18641 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18642 contents + in_index * 8, add_to_offsets);
18643 out_index++;
18644 in_index++;
18645 }
18646 else if (in_index == edit_index
18647 || (in_index * 8 >= input_size
18648 && edit_index == UINT_MAX))
99059e56 18649 {
2468f9c9
PB		 18650 switch (edit_node->type)
18651 {
18652 case DELETE_EXIDX_ENTRY:
18653 in_index++;
18654 add_to_offsets += 8;
18655 break;
b38cadfb 18656
2468f9c9
PB		 18657 case INSERT_EXIDX_CANTUNWIND_AT_END:
18658 {
99059e56 18659 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18660 bfd_vma text_offset = text_sec->output_section->vma
18661 + text_sec->output_offset
18662 + text_sec->size;
18663 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18664 unsigned long prel31_offset;
2468f9c9
PB		 18665
18666 /* Note: this is meant to be equivalent to an
18667 R_ARM_PREL31 relocation. These synthetic
18668 EXIDX_CANTUNWIND markers are not relocated by the
18669 usual BFD method. */
18670 prel31_offset = (text_offset - exidx_offset)
18671 & 0x7ffffffful;
491d01d3
YU		 18672 if (bfd_link_relocatable (link_info))
18673 {
18674 /* Here relocation for new EXIDX_CANTUNWIND is
18675 created, so there is no need to
18676 adjust offset by hand. */
18677 prel31_offset = text_sec->output_offset
18678 + text_sec->size;
491d01d3 18679 }
2468f9c9
PB		 18680
18681 /* First address we can't unwind. */
18682 bfd_put_32 (output_bfd, prel31_offset,
18683 &edited_contents[out_index * 8]);
18684
18685 /* Code for EXIDX_CANTUNWIND. */
18686 bfd_put_32 (output_bfd, 0x1,
18687 &edited_contents[out_index * 8 + 4]);
18688
18689 out_index++;
18690 add_to_offsets -= 8;
18691 }
18692 break;
18693 }
b38cadfb 18694
2468f9c9
PB		 18695 edit_node = edit_node->next;
18696 }
18697 }
18698 else
18699 {
18700 /* No more edits, copy remaining entries verbatim. */
18701 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18702 contents + in_index * 8, add_to_offsets);
18703 out_index++;
18704 in_index++;
18705 }
18706 }
18707
18708 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18709 bfd_set_section_contents (output_bfd, sec->output_section,
18710 edited_contents,
18711 (file_ptr) sec->output_offset, sec->size);
18712
18713 return TRUE;
18714 }
18715
48229727
JB		 18716 /* Fix code to point to Cortex-A8 erratum stubs. */
18717 if (globals->fix_cortex_a8)
18718 {
18719 struct a8_branch_to_stub_data data;
18720
18721 data.writing_section = sec;
18722 data.contents = contents;
18723
a504d23a
LA		 18724 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18725 & data);
48229727
JB		 18726 }
18727
e489d0ae
PB		 18728 if (mapcount == 0)
18729 return FALSE;
18730
c7b8f16e 18731 if (globals->byteswap_code)
e489d0ae 18732 {
c7b8f16e 18733 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18734
c7b8f16e
JB		 18735 ptr = map[0].vma;
18736 for (i = 0; i < mapcount; i++)
99059e56
RM		 18737 {
18738 if (i == mapcount - 1)
c7b8f16e 18739 end = sec->size;
99059e56
RM		 18740 else
18741 end = map[i + 1].vma;
e489d0ae 18742
99059e56 18743 switch (map[i].type)
e489d0ae 18744 {
c7b8f16e
JB		 18745 case 'a':
18746 /* Byte swap code words. */
18747 while (ptr + 3 < end)
99059e56
RM		 18748 {
18749 tmp = contents[ptr];
18750 contents[ptr] = contents[ptr + 3];
18751 contents[ptr + 3] = tmp;
18752 tmp = contents[ptr + 1];
18753 contents[ptr + 1] = contents[ptr + 2];
18754 contents[ptr + 2] = tmp;
18755 ptr += 4;
18756 }
c7b8f16e 18757 break;
e489d0ae 18758
c7b8f16e
JB		 18759 case 't':
18760 /* Byte swap code halfwords. */
18761 while (ptr + 1 < end)
99059e56
RM		 18762 {
18763 tmp = contents[ptr];
18764 contents[ptr] = contents[ptr + 1];
18765 contents[ptr + 1] = tmp;
18766 ptr += 2;
18767 }
c7b8f16e
JB		 18768 break;
18769
18770 case 'd':
18771 /* Leave data alone. */
18772 break;
18773 }
99059e56
RM		 18774 ptr = end;
18775 }
e489d0ae 18776 }
8e3de13a 18777
93204d3a 18778 free (map);
47b2e99c 18779 arm_data->mapcount = -1;
c7b8f16e 18780 arm_data->mapsize = 0;
8e3de13a 18781 arm_data->map = NULL;
8e3de13a 18782
e489d0ae
PB		 18783 return FALSE;
18784}
18785
0beaef2b
PB		 18786/* Mangle thumb function symbols as we read them in. */
18787
8384fb8f 18788static bfd_boolean
0beaef2b
PB		 18789elf32_arm_swap_symbol_in (bfd * abfd,
18790 const void *psrc,
18791 const void *pshn,
18792 Elf_Internal_Sym *dst)
18793{
4ba2ef8f
TP		 18794 Elf_Internal_Shdr *symtab_hdr;
18795 const char *name = NULL;
18796
8384fb8f
AM		 18797 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18798 return FALSE;
39d911fc 18799 dst->st_target_internal = 0;
0beaef2b
PB		 18800
18801 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18802 the address. */
63e1a0fc
PB		 18803 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18804 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18805 {
63e1a0fc
PB		 18806 if (dst->st_value & 1)
18807 {
18808 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18809 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18810 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18811 }
18812 else
39d911fc 18813 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18814 }
18815 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18816 {
18817 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18818 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18819 }
35fc36a8 18820 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18821 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18822 else
39d911fc 18823 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18824
4ba2ef8f
TP		 18825 /* Mark CMSE special symbols. */
18826 symtab_hdr = & elf_symtab_hdr (abfd);
18827 if (symtab_hdr->sh_size)
18828 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18829 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18830 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18831
8384fb8f 18832 return TRUE;
0beaef2b
PB		 18833}
18834
18835
18836/* Mangle thumb function symbols as we write them out. */
18837
18838static void
18839elf32_arm_swap_symbol_out (bfd *abfd,
18840 const Elf_Internal_Sym *src,
18841 void *cdst,
18842 void *shndx)
18843{
18844 Elf_Internal_Sym newsym;
18845
18846 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18847 of the address set, as per the new EABI. We do this unconditionally
18848 because objcopy does not set the elf header flags until after
18849 it writes out the symbol table. */
39d911fc 18850 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18851 {
18852 newsym = *src;
34e77a92
RS		 18853 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18854 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18855 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18856 {
18857 /* Do this only for defined symbols. At link type, the static
18858 linker will simulate the work of dynamic linker of resolving
18859 symbols and will carry over the thumbness of found symbols to
18860 the output symbol table. It's not clear how it happens, but
18861 the thumbness of undefined symbols can well be different at
18862 runtime, and writing '1' for them will be confusing for users
18863 and possibly for dynamic linker itself.
18864 */
18865 newsym.st_value |= 1;
18866 }
906e58ca 18867
0beaef2b
PB		 18868 src = &newsym;
18869 }
18870 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18871}
18872
b294bdf8
MM		 18873/* Add the PT_ARM_EXIDX program header. */
18874
18875static bfd_boolean
906e58ca 18876elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18877 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18878{
18879 struct elf_segment_map *m;
18880 asection *sec;
18881
18882 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18883 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18884 {
18885 /* If there is already a PT_ARM_EXIDX header, then we do not
18886 want to add another one. This situation arises when running
18887 "strip"; the input binary already has the header. */
12bd6957 18888 m = elf_seg_map (abfd);
b294bdf8
MM		 18889 while (m && m->p_type != PT_ARM_EXIDX)
18890 m = m->next;
18891 if (!m)
18892 {
21d799b5 18893 m = (struct elf_segment_map *)
99059e56 18894 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18895 if (m == NULL)
18896 return FALSE;
18897 m->p_type = PT_ARM_EXIDX;
18898 m->count = 1;
18899 m->sections[0] = sec;
18900
12bd6957
AM		 18901 m->next = elf_seg_map (abfd);
18902 elf_seg_map (abfd) = m;
b294bdf8
MM		 18903 }
18904 }
18905
18906 return TRUE;
18907}
18908
18909/* We may add a PT_ARM_EXIDX program header. */
18910
18911static int
a6b96beb
AM		 18912elf32_arm_additional_program_headers (bfd *abfd,
18913 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18914{
18915 asection *sec;
18916
18917 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18918 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18919 return 1;
18920 else
18921 return 0;
18922}
18923
34e77a92
RS		 18924/* Hook called by the linker routine which adds symbols from an object
18925 file. */
18926
18927static bfd_boolean
18928elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18929 Elf_Internal_Sym *sym, const char **namep,
18930 flagword *flagsp, asection **secp, bfd_vma *valp)
18931{
a43942db 18932 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18933 && (abfd->flags & DYNAMIC) == 0
18934 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18935 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18936
c792917c
NC		 18937 if (elf32_arm_hash_table (info) == NULL)
18938 return FALSE;
18939
34e77a92
RS		 18940 if (elf32_arm_hash_table (info)->vxworks_p
18941 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18942 flagsp, secp, valp))
18943 return FALSE;
18944
18945 return TRUE;
18946}
18947
0beaef2b 18948/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18949const struct elf_size_info elf32_arm_size_info =
18950{
0beaef2b
PB		 18951 sizeof (Elf32_External_Ehdr),
18952 sizeof (Elf32_External_Phdr),
18953 sizeof (Elf32_External_Shdr),
18954 sizeof (Elf32_External_Rel),
18955 sizeof (Elf32_External_Rela),
18956 sizeof (Elf32_External_Sym),
18957 sizeof (Elf32_External_Dyn),
18958 sizeof (Elf_External_Note),
18959 4,
18960 1,
18961 32, 2,
18962 ELFCLASS32, EV_CURRENT,
18963 bfd_elf32_write_out_phdrs,
18964 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18965 bfd_elf32_checksum_contents,
0beaef2b
PB		 18966 bfd_elf32_write_relocs,
18967 elf32_arm_swap_symbol_in,
18968 elf32_arm_swap_symbol_out,
18969 bfd_elf32_slurp_reloc_table,
18970 bfd_elf32_slurp_symbol_table,
18971 bfd_elf32_swap_dyn_in,
18972 bfd_elf32_swap_dyn_out,
18973 bfd_elf32_swap_reloc_in,
18974 bfd_elf32_swap_reloc_out,
18975 bfd_elf32_swap_reloca_in,
18976 bfd_elf32_swap_reloca_out
18977};
18978
685e70ae
VK		 18979static bfd_vma
18980read_code32 (const bfd *abfd, const bfd_byte *addr)
18981{
18982 /* V7 BE8 code is always little endian. */
18983 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18984 return bfd_getl32 (addr);
18985
18986 return bfd_get_32 (abfd, addr);
18987}
18988
18989static bfd_vma
18990read_code16 (const bfd *abfd, const bfd_byte *addr)
18991{
18992 /* V7 BE8 code is always little endian. */
18993 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18994 return bfd_getl16 (addr);
18995
18996 return bfd_get_16 (abfd, addr);
18997}
18998
6a631e86
YG		 18999/* Return size of plt0 entry starting at ADDR
19000 or (bfd_vma) -1 if size can not be determined. */
19001
19002static bfd_vma
19003elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19004{
19005 bfd_vma first_word;
19006 bfd_vma plt0_size;
19007
685e70ae 19008 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19009
19010 if (first_word == elf32_arm_plt0_entry[0])
19011 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19012 else if (first_word == elf32_thumb2_plt0_entry[0])
19013 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19014 else
19015 /* We don't yet handle this PLT format. */
19016 return (bfd_vma) -1;
19017
19018 return plt0_size;
19019}
19020
19021/* Return size of plt entry starting at offset OFFSET
19022 of plt section located at address START
19023 or (bfd_vma) -1 if size can not be determined. */
19024
19025static bfd_vma
19026elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19027{
19028 bfd_vma first_insn;
19029 bfd_vma plt_size = 0;
19030 const bfd_byte *addr = start + offset;
19031
19032 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19033 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19034 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19035
19036 /* Respect Thumb stub if necessary. */
685e70ae 19037 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19038 {
19039 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19040 }
19041
19042 /* Strip immediate from first add. */
685e70ae 19043 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19044
19045#ifdef FOUR_WORD_PLT
19046 if (first_insn == elf32_arm_plt_entry[0])
19047 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19048#else
19049 if (first_insn == elf32_arm_plt_entry_long[0])
19050 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19051 else if (first_insn == elf32_arm_plt_entry_short[0])
19052 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19053#endif
19054 else
19055 /* We don't yet handle this PLT format. */
19056 return (bfd_vma) -1;
19057
19058 return plt_size;
19059}
19060
19061/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19062
19063static long
19064elf32_arm_get_synthetic_symtab (bfd *abfd,
19065 long symcount ATTRIBUTE_UNUSED,
19066 asymbol **syms ATTRIBUTE_UNUSED,
19067 long dynsymcount,
19068 asymbol **dynsyms,
19069 asymbol **ret)
19070{
19071 asection *relplt;
19072 asymbol *s;
19073 arelent *p;
19074 long count, i, n;
19075 size_t size;
19076 Elf_Internal_Shdr *hdr;
19077 char *names;
19078 asection *plt;
19079 bfd_vma offset;
19080 bfd_byte *data;
19081
19082 *ret = NULL;
19083
19084 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19085 return 0;
19086
19087 if (dynsymcount <= 0)
19088 return 0;
19089
19090 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19091 if (relplt == NULL)
19092 return 0;
19093
19094 hdr = &elf_section_data (relplt)->this_hdr;
19095 if (hdr->sh_link != elf_dynsymtab (abfd)
19096 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19097 return 0;
19098
19099 plt = bfd_get_section_by_name (abfd, ".plt");
19100 if (plt == NULL)
19101 return 0;
19102
19103 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19104 return -1;
19105
19106 data = plt->contents;
19107 if (data == NULL)
19108 {
19109 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19110 return -1;
19111 bfd_cache_section_contents((asection *) plt, data);
19112 }
19113
19114 count = relplt->size / hdr->sh_entsize;
19115 size = count * sizeof (asymbol);
19116 p = relplt->relocation;
19117 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19118 {
19119 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19120 if (p->addend != 0)
19121 size += sizeof ("+0x") - 1 + 8;
19122 }
19123
19124 s = *ret = (asymbol *) bfd_malloc (size);
19125 if (s == NULL)
19126 return -1;
19127
19128 offset = elf32_arm_plt0_size (abfd, data);
19129 if (offset == (bfd_vma) -1)
19130 return -1;
19131
19132 names = (char *) (s + count);
19133 p = relplt->relocation;
19134 n = 0;
19135 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19136 {
19137 size_t len;
19138
19139 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19140 if (plt_size == (bfd_vma) -1)
19141 break;
19142
19143 *s = **p->sym_ptr_ptr;
19144 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19145 we are defining a symbol, ensure one of them is set. */
19146 if ((s->flags & BSF_LOCAL) == 0)
19147 s->flags |= BSF_GLOBAL;
19148 s->flags |= BSF_SYNTHETIC;
19149 s->section = plt;
19150 s->value = offset;
19151 s->name = names;
19152 s->udata.p = NULL;
19153 len = strlen ((*p->sym_ptr_ptr)->name);
19154 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19155 names += len;
19156 if (p->addend != 0)
19157 {
19158 char buf[30], *a;
19159
19160 memcpy (names, "+0x", sizeof ("+0x") - 1);
19161 names += sizeof ("+0x") - 1;
19162 bfd_sprintf_vma (abfd, buf, p->addend);
19163 for (a = buf; *a == '0'; ++a)
19164 ;
19165 len = strlen (a);
19166 memcpy (names, a, len);
19167 names += len;
19168 }
19169 memcpy (names, "@plt", sizeof ("@plt"));
19170 names += sizeof ("@plt");
19171 ++s, ++n;
19172 offset += plt_size;
19173 }
19174
19175 return n;
19176}
19177
ac4c9b04
MG		 19178static bfd_boolean
19179elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19180{
f0728ee3
AV		 19181 if (hdr->sh_flags & SHF_ARM_PURECODE)
19182 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19183 return TRUE;
19184}
19185
19186static flagword
19187elf32_arm_lookup_section_flags (char *flag_name)
19188{
f0728ee3
AV		 19189 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19190 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19191
19192 return SEC_NO_FLAGS;
19193}
19194
491d01d3
YU		 19195static unsigned int
19196elf32_arm_count_additional_relocs (asection *sec)
19197{
19198 struct _arm_elf_section_data *arm_data;
19199 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19200
6342be70 19201 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19202}
19203
5522f910 19204/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19205 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19206 FALSE otherwise. ISECTION is the best guess matching section from the
19207 input bfd IBFD, but it might be NULL. */
19208
19209static bfd_boolean
19210elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19211 bfd *obfd ATTRIBUTE_UNUSED,
19212 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19213 Elf_Internal_Shdr *osection)
19214{
19215 switch (osection->sh_type)
19216 {
19217 case SHT_ARM_EXIDX:
19218 {
19219 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19220 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19221 unsigned i = 0;
19222
19223 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19224 osection->sh_info = 0;
19225
19226 /* The sh_link field must be set to the text section associated with
19227 this index section. Unfortunately the ARM EHABI does not specify
19228 exactly how to determine this association. Our caller does try
19229 to match up OSECTION with its corresponding input section however
19230 so that is a good first guess. */
19231 if (isection != NULL
19232 && osection->bfd_section != NULL
19233 && isection->bfd_section != NULL
19234 && isection->bfd_section->output_section != NULL
19235 && isection->bfd_section->output_section == osection->bfd_section
19236 && iheaders != NULL
19237 && isection->sh_link > 0
19238 && isection->sh_link < elf_numsections (ibfd)
19239 && iheaders[isection->sh_link]->bfd_section != NULL
19240 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19241 )
19242 {
19243 for (i = elf_numsections (obfd); i-- > 0;)
19244 if (oheaders[i]->bfd_section
19245 == iheaders[isection->sh_link]->bfd_section->output_section)
19246 break;
19247 }
9eaff861 19248
5522f910
NC		 19249 if (i == 0)
19250 {
19251 /* Failing that we have to find a matching section ourselves. If
19252 we had the output section name available we could compare that
19253 with input section names. Unfortunately we don't. So instead
19254 we use a simple heuristic and look for the nearest executable
19255 section before this one. */
19256 for (i = elf_numsections (obfd); i-- > 0;)
19257 if (oheaders[i] == osection)
19258 break;
19259 if (i == 0)
19260 break;
19261
19262 while (i-- > 0)
19263 if (oheaders[i]->sh_type == SHT_PROGBITS
19264 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19265 == (SHF_ALLOC | SHF_EXECINSTR))
19266 break;
19267 }
19268
19269 if (i)
19270 {
19271 osection->sh_link = i;
19272 /* If the text section was part of a group
19273 then the index section should be too. */
19274 if (oheaders[i]->sh_flags & SHF_GROUP)
19275 osection->sh_flags |= SHF_GROUP;
19276 return TRUE;
19277 }
19278 }
19279 break;
19280
19281 case SHT_ARM_PREEMPTMAP:
19282 osection->sh_flags = SHF_ALLOC;
19283 break;
19284
19285 case SHT_ARM_ATTRIBUTES:
19286 case SHT_ARM_DEBUGOVERLAY:
19287 case SHT_ARM_OVERLAYSECTION:
19288 default:
19289 break;
19290 }
19291
19292 return FALSE;
19293}
19294
d691934d
NC		 19295/* Returns TRUE if NAME is an ARM mapping symbol.
19296 Traditionally the symbols $a, $d and $t have been used.
19297 The ARM ELF standard also defines $x (for A64 code). It also allows a
19298 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19299 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19300 not support them here. $t.x indicates the start of ThumbEE instructions. */
19301
19302static bfd_boolean
19303is_arm_mapping_symbol (const char * name)
19304{
19305 return name != NULL /* Paranoia. */
19306 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19307 the mapping symbols could have acquired a prefix.
19308 We do not support this here, since such symbols no
19309 longer conform to the ARM ELF ABI. */
19310 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19311 && (name[2] == 0 || name[2] == '.');
19312 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19313 any characters that follow the period are legal characters for the body
19314 of a symbol's name. For now we just assume that this is the case. */
19315}
19316
fca2a38f
NC		 19317/* Make sure that mapping symbols in object files are not removed via the
19318 "strip --strip-unneeded" tool. These symbols are needed in order to
19319 correctly generate interworking veneers, and for byte swapping code
19320 regions. Once an object file has been linked, it is safe to remove the
19321 symbols as they will no longer be needed. */
19322
19323static void
19324elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19325{
19326 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19327 && sym->section != bfd_abs_section_ptr
d691934d 19328 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19329 sym->flags |= BSF_KEEP;
19330}
19331
5522f910
NC		 19332#undef elf_backend_copy_special_section_fields
19333#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19334
252b5132 19335#define ELF_ARCH bfd_arch_arm
ae95ffa6 19336#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19337#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19338#ifdef __QNXTARGET__
19339#define ELF_MAXPAGESIZE 0x1000
19340#else
7572ca89 19341#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19342#endif
b1342370 19343#define ELF_MINPAGESIZE 0x1000
24718e3b 19344#define ELF_COMMONPAGESIZE 0x1000
252b5132 19345
ba93b8ac
DJ		 19346#define bfd_elf32_mkobject elf32_arm_mkobject
19347
99e4ae17
AJ		 19348#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19349#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19350#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19351#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
19352#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19353#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19354#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 19355#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 19356#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19357#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19358#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19359#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 19360#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 19361
19362#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19363#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19364#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 19365#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
19366#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19367#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19368#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19369#define elf_backend_write_section elf32_arm_write_section
252b5132 19370#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 19371#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19372#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19373#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19374#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19375#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19376#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19377#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19378#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19379#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 19380#define elf_backend_fake_sections elf32_arm_fake_sections
19381#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 19382#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 19383#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19384#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19385#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 19386#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19387#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19388#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
906e58ca 19389#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19390#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19391#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19392#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19393
19394#define elf_backend_can_refcount 1
19395#define elf_backend_can_gc_sections 1
19396#define elf_backend_plt_readonly 1
19397#define elf_backend_want_got_plt 1
19398#define elf_backend_want_plt_sym 0
19399#define elf_backend_may_use_rel_p 1
19400#define elf_backend_may_use_rela_p 0
4e7fd91e 19401#define elf_backend_default_use_rela_p 0
64f52338 19402#define elf_backend_dtrel_excludes_plt 1
252b5132 19403
04f7c78d 19404#define elf_backend_got_header_size 12
b68a20d6 19405#define elf_backend_extern_protected_data 1
04f7c78d 19406
906e58ca
NC		 19407#undef elf_backend_obj_attrs_vendor
19408#define elf_backend_obj_attrs_vendor "aeabi"
19409#undef elf_backend_obj_attrs_section
19410#define elf_backend_obj_attrs_section ".ARM.attributes"
19411#undef elf_backend_obj_attrs_arg_type
19412#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
19413#undef elf_backend_obj_attrs_section_type
104d59d1 19414#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 19415#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
19416#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19417
5025eb7c 19418#undef elf_backend_section_flags
ac4c9b04 19419#define elf_backend_section_flags elf32_arm_section_flags
5025eb7c 19420#undef elf_backend_lookup_section_flags_hook
ac4c9b04
MG		 19421#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
19422
252b5132 19423#include "elf32-target.h"
7f266840 19424
b38cadfb
NC		 19425/* Native Client targets. */
19426
19427#undef TARGET_LITTLE_SYM
6d00b590 19428#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19429#undef TARGET_LITTLE_NAME
19430#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19431#undef TARGET_BIG_SYM
6d00b590 19432#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19433#undef TARGET_BIG_NAME
19434#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19435
19436/* Like elf32_arm_link_hash_table_create -- but overrides
19437 appropriately for NaCl. */
19438
19439static struct bfd_link_hash_table *
19440elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19441{
19442 struct bfd_link_hash_table *ret;
19443
19444 ret = elf32_arm_link_hash_table_create (abfd);
19445 if (ret)
19446 {
19447 struct elf32_arm_link_hash_table *htab
19448 = (struct elf32_arm_link_hash_table *) ret;
19449
19450 htab->nacl_p = 1;
19451
19452 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19453 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19454 }
19455 return ret;
19456}
19457
19458/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19459 really need to use elf32_arm_modify_segment_map. But we do it
19460 anyway just to reduce gratuitous differences with the stock ARM backend. */
19461
19462static bfd_boolean
19463elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19464{
19465 return (elf32_arm_modify_segment_map (abfd, info)
19466 && nacl_modify_segment_map (abfd, info));
19467}
19468
887badb3
RM		 19469static void
19470elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19471{
19472 elf32_arm_final_write_processing (abfd, linker);
19473 nacl_final_write_processing (abfd, linker);
19474}
19475
6a631e86
YG		 19476static bfd_vma
19477elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19478 const arelent *rel ATTRIBUTE_UNUSED)
19479{
19480 return plt->vma
19481 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19482 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19483}
887badb3 19484
b38cadfb 19485#undef elf32_bed
6a631e86 19486#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19487#undef bfd_elf32_bfd_link_hash_table_create
19488#define bfd_elf32_bfd_link_hash_table_create \
19489 elf32_arm_nacl_link_hash_table_create
19490#undef elf_backend_plt_alignment
6a631e86 19491#define elf_backend_plt_alignment 4
b38cadfb
NC		 19492#undef elf_backend_modify_segment_map
19493#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19494#undef elf_backend_modify_program_headers
19495#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19496#undef elf_backend_final_write_processing
19497#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19498#undef bfd_elf32_get_synthetic_symtab
19499#undef elf_backend_plt_sym_val
19500#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19501#undef elf_backend_copy_special_section_fields
b38cadfb 19502
887badb3
RM		 19503#undef ELF_MINPAGESIZE
19504#undef ELF_COMMONPAGESIZE
19505
b38cadfb
NC		 19506
19507#include "elf32-target.h"
19508
19509/* Reset to defaults. */
19510#undef elf_backend_plt_alignment
19511#undef elf_backend_modify_segment_map
19512#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19513#undef elf_backend_modify_program_headers
887badb3
RM		 19514#undef elf_backend_final_write_processing
19515#define elf_backend_final_write_processing elf32_arm_final_write_processing
19516#undef ELF_MINPAGESIZE
19517#define ELF_MINPAGESIZE 0x1000
19518#undef ELF_COMMONPAGESIZE
19519#define ELF_COMMONPAGESIZE 0x1000
19520
b38cadfb 19521
906e58ca 19522/* VxWorks Targets. */
4e7fd91e 19523
906e58ca 19524#undef TARGET_LITTLE_SYM
6d00b590 19525#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 19526#undef TARGET_LITTLE_NAME
4e7fd91e 19527#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 19528#undef TARGET_BIG_SYM
6d00b590 19529#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 19530#undef TARGET_BIG_NAME
4e7fd91e
PB		 19531#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
19532
19533/* Like elf32_arm_link_hash_table_create -- but overrides
19534 appropriately for VxWorks. */
906e58ca 19535
4e7fd91e
PB		 19536static struct bfd_link_hash_table *
19537elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19538{
19539 struct bfd_link_hash_table *ret;
19540
19541 ret = elf32_arm_link_hash_table_create (abfd);
19542 if (ret)
19543 {
19544 struct elf32_arm_link_hash_table *htab
00a97672 19545 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19546 htab->use_rel = 0;
00a97672 19547 htab->vxworks_p = 1;
4e7fd91e
PB		 19548 }
19549 return ret;
906e58ca 19550}
4e7fd91e 19551
00a97672
RS		 19552static void
19553elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19554{
19555 elf32_arm_final_write_processing (abfd, linker);
19556 elf_vxworks_final_write_processing (abfd, linker);
19557}
19558
906e58ca 19559#undef elf32_bed
4e7fd91e
PB		 19560#define elf32_bed elf32_arm_vxworks_bed
19561
906e58ca
NC		 19562#undef bfd_elf32_bfd_link_hash_table_create
19563#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19564#undef elf_backend_final_write_processing
19565#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19566#undef elf_backend_emit_relocs
9eaff861 19567#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19568
906e58ca 19569#undef elf_backend_may_use_rel_p
00a97672 19570#define elf_backend_may_use_rel_p 0
906e58ca 19571#undef elf_backend_may_use_rela_p
00a97672 19572#define elf_backend_may_use_rela_p 1
906e58ca 19573#undef elf_backend_default_use_rela_p
00a97672 19574#define elf_backend_default_use_rela_p 1
906e58ca 19575#undef elf_backend_want_plt_sym
00a97672 19576#define elf_backend_want_plt_sym 1
906e58ca 19577#undef ELF_MAXPAGESIZE
00a97672 19578#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19579
19580#include "elf32-target.h"
19581
19582
21d799b5
NC		 19583/* Merge backend specific data from an object file to the output
19584 object file when linking. */
19585
19586static bfd_boolean
50e03d47 19587elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 19588{
50e03d47 19589 bfd *obfd = info->output_bfd;
21d799b5
NC		 19590 flagword out_flags;
19591 flagword in_flags;
19592 bfd_boolean flags_compatible = TRUE;
19593 asection *sec;
19594
cc643b88 19595 /* Check if we have the same endianness. */
50e03d47 19596 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 19597 return FALSE;
19598
19599 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19600 return TRUE;
19601
50e03d47 19602 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 19603 return FALSE;
19604
19605 /* The input BFD must have had its flags initialised. */
19606 /* The following seems bogus to me -- The flags are initialized in
19607 the assembler but I don't think an elf_flags_init field is
19608 written into the object. */
19609 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19610
19611 in_flags = elf_elfheader (ibfd)->e_flags;
19612 out_flags = elf_elfheader (obfd)->e_flags;
19613
19614 /* In theory there is no reason why we couldn't handle this. However
19615 in practice it isn't even close to working and there is no real
19616 reason to want it. */
19617 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19618 && !(ibfd->flags & DYNAMIC)
19619 && (in_flags & EF_ARM_BE8))
19620 {
19621 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19622 ibfd);
19623 return FALSE;
19624 }
19625
19626 if (!elf_flags_init (obfd))
19627 {
19628 /* If the input is the default architecture and had the default
19629 flags then do not bother setting the flags for the output
19630 architecture, instead allow future merges to do this. If no
19631 future merges ever set these flags then they will retain their
99059e56
RM		 19632 uninitialised values, which surprise surprise, correspond
19633 to the default values. */
21d799b5
NC		 19634 if (bfd_get_arch_info (ibfd)->the_default
19635 && elf_elfheader (ibfd)->e_flags == 0)
19636 return TRUE;
19637
19638 elf_flags_init (obfd) = TRUE;
19639 elf_elfheader (obfd)->e_flags = in_flags;
19640
19641 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19642 && bfd_get_arch_info (obfd)->the_default)
19643 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19644
19645 return TRUE;
19646 }
19647
19648 /* Determine what should happen if the input ARM architecture
19649 does not match the output ARM architecture. */
19650 if (! bfd_arm_merge_machines (ibfd, obfd))
19651 return FALSE;
19652
19653 /* Identical flags must be compatible. */
19654 if (in_flags == out_flags)
19655 return TRUE;
19656
19657 /* Check to see if the input BFD actually contains any sections. If
19658 not, its flags may not have been initialised either, but it
19659 cannot actually cause any incompatiblity. Do not short-circuit
19660 dynamic objects; their section list may be emptied by
19661 elf_link_add_object_symbols.
19662
19663 Also check to see if there are no code sections in the input.
19664 In this case there is no need to check for code specific flags.
19665 XXX - do we need to worry about floating-point format compatability
19666 in data sections ? */
19667 if (!(ibfd->flags & DYNAMIC))
19668 {
19669 bfd_boolean null_input_bfd = TRUE;
19670 bfd_boolean only_data_sections = TRUE;
19671
19672 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19673 {
19674 /* Ignore synthetic glue sections. */
19675 if (strcmp (sec->name, ".glue_7")
19676 && strcmp (sec->name, ".glue_7t"))
19677 {
19678 if ((bfd_get_section_flags (ibfd, sec)
19679 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19680 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19681 only_data_sections = FALSE;
21d799b5
NC		 19682
19683 null_input_bfd = FALSE;
19684 break;
19685 }
19686 }
19687
19688 if (null_input_bfd || only_data_sections)
19689 return TRUE;
19690 }
19691
19692 /* Complain about various flag mismatches. */
19693 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19694 EF_ARM_EABI_VERSION (out_flags)))
19695 {
19696 _bfd_error_handler
19697 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
19698 ibfd, obfd,
19699 (in_flags & EF_ARM_EABIMASK) >> 24,
19700 (out_flags & EF_ARM_EABIMASK) >> 24);
19701 return FALSE;
19702 }
19703
19704 /* Not sure what needs to be checked for EABI versions >= 1. */
19705 /* VxWorks libraries do not use these flags. */
19706 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19707 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19708 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19709 {
19710 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19711 {
19712 _bfd_error_handler
19713 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
19714 ibfd, obfd,
19715 in_flags & EF_ARM_APCS_26 ? 26 : 32,
19716 out_flags & EF_ARM_APCS_26 ? 26 : 32);
19717 flags_compatible = FALSE;
19718 }
19719
19720 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19721 {
19722 if (in_flags & EF_ARM_APCS_FLOAT)
19723 _bfd_error_handler
19724 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19725 ibfd, obfd);
19726 else
19727 _bfd_error_handler
19728 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19729 ibfd, obfd);
19730
19731 flags_compatible = FALSE;
19732 }
19733
19734 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19735 {
19736 if (in_flags & EF_ARM_VFP_FLOAT)
19737 _bfd_error_handler
19738 (_("error: %B uses VFP instructions, whereas %B does not"),
19739 ibfd, obfd);
19740 else
19741 _bfd_error_handler
19742 (_("error: %B uses FPA instructions, whereas %B does not"),
19743 ibfd, obfd);
19744
19745 flags_compatible = FALSE;
19746 }
19747
19748 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19749 {
19750 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19751 _bfd_error_handler
19752 (_("error: %B uses Maverick instructions, whereas %B does not"),
19753 ibfd, obfd);
19754 else
19755 _bfd_error_handler
19756 (_("error: %B does not use Maverick instructions, whereas %B does"),
19757 ibfd, obfd);
19758
19759 flags_compatible = FALSE;
19760 }
19761
19762#ifdef EF_ARM_SOFT_FLOAT
19763 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19764 {
19765 /* We can allow interworking between code that is VFP format
19766 layout, and uses either soft float or integer regs for
19767 passing floating point arguments and results. We already
19768 know that the APCS_FLOAT flags match; similarly for VFP
19769 flags. */
19770 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19771 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19772 {
19773 if (in_flags & EF_ARM_SOFT_FLOAT)
19774 _bfd_error_handler
19775 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19776 ibfd, obfd);
19777 else
19778 _bfd_error_handler
19779 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19780 ibfd, obfd);
19781
19782 flags_compatible = FALSE;
19783 }
19784 }
19785#endif
19786
19787 /* Interworking mismatch is only a warning. */
19788 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19789 {
19790 if (in_flags & EF_ARM_INTERWORK)
19791 {
19792 _bfd_error_handler
19793 (_("Warning: %B supports interworking, whereas %B does not"),
19794 ibfd, obfd);
19795 }
19796 else
19797 {
19798 _bfd_error_handler
19799 (_("Warning: %B does not support interworking, whereas %B does"),
19800 ibfd, obfd);
19801 }
19802 }
19803 }
19804
19805 return flags_compatible;
19806}
19807
19808
906e58ca 19809/* Symbian OS Targets. */
7f266840 19810
906e58ca 19811#undef TARGET_LITTLE_SYM
6d00b590 19812#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19813#undef TARGET_LITTLE_NAME
7f266840 19814#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19815#undef TARGET_BIG_SYM
6d00b590 19816#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19817#undef TARGET_BIG_NAME
7f266840
DJ		 19818#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19819
19820/* Like elf32_arm_link_hash_table_create -- but overrides
19821 appropriately for Symbian OS. */
906e58ca 19822
7f266840
DJ		 19823static struct bfd_link_hash_table *
19824elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19825{
19826 struct bfd_link_hash_table *ret;
19827
19828 ret = elf32_arm_link_hash_table_create (abfd);
19829 if (ret)
19830 {
19831 struct elf32_arm_link_hash_table *htab
19832 = (struct elf32_arm_link_hash_table *)ret;
19833 /* There is no PLT header for Symbian OS. */
19834 htab->plt_header_size = 0;
95720a86
DJ		 19835 /* The PLT entries are each one instruction and one word. */
19836 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19837 htab->symbian_p = 1;
33bfe774
JB		 19838 /* Symbian uses armv5t or above, so use_blx is always true. */
19839 htab->use_blx = 1;
67687978 19840 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19841 }
19842 return ret;
906e58ca 19843}
7f266840 19844
b35d266b 19845static const struct bfd_elf_special_section
551b43fd 19846elf32_arm_symbian_special_sections[] =
7f266840 19847{
5cd3778d
MM		 19848 /* In a BPABI executable, the dynamic linking sections do not go in
19849 the loadable read-only segment. The post-linker may wish to
19850 refer to these sections, but they are not part of the final
19851 program image. */
0112cd26
NC		 19852 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19853 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19854 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19855 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19856 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19857 /* These sections do not need to be writable as the SymbianOS
19858 postlinker will arrange things so that no dynamic relocation is
19859 required. */
0112cd26
NC		 19860 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19861 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19862 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19863 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19864};
19865
c3c76620 19866static void
906e58ca 19867elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19868 struct bfd_link_info *link_info)
c3c76620
MM		 19869{
19870 /* BPABI objects are never loaded directly by an OS kernel; they are
19871 processed by a postlinker first, into an OS-specific format. If
19872 the D_PAGED bit is set on the file, BFD will align segments on
19873 page boundaries, so that an OS can directly map the file. With
19874 BPABI objects, that just results in wasted space. In addition,
19875 because we clear the D_PAGED bit, map_sections_to_segments will
19876 recognize that the program headers should not be mapped into any
19877 loadable segment. */
19878 abfd->flags &= ~D_PAGED;
906e58ca 19879 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19880}
7f266840
DJ		 19881
19882static bfd_boolean
906e58ca 19883elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19884 struct bfd_link_info *info)
7f266840
DJ		 19885{
19886 struct elf_segment_map *m;
19887 asection *dynsec;
19888
7f266840
DJ		 19889 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19890 segment. However, because the .dynamic section is not marked
19891 with SEC_LOAD, the generic ELF code will not create such a
19892 segment. */
19893 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19894 if (dynsec)
19895 {
12bd6957 19896 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19897 if (m->p_type == PT_DYNAMIC)
19898 break;
19899
19900 if (m == NULL)
19901 {
19902 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19903 m->next = elf_seg_map (abfd);
19904 elf_seg_map (abfd) = m;
8ded5a0f 19905 }
7f266840
DJ		 19906 }
19907
b294bdf8
MM		 19908 /* Also call the generic arm routine. */
19909 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19910}
19911
95720a86
DJ		 19912/* Return address for Ith PLT stub in section PLT, for relocation REL
19913 or (bfd_vma) -1 if it should not be included. */
19914
19915static bfd_vma
19916elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19917 const arelent *rel ATTRIBUTE_UNUSED)
19918{
19919 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19920}
19921
8029a119 19922#undef elf32_bed
7f266840
DJ		 19923#define elf32_bed elf32_arm_symbian_bed
19924
19925/* The dynamic sections are not allocated on SymbianOS; the postlinker
19926 will process them and then discard them. */
906e58ca 19927#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19928#define ELF_DYNAMIC_SEC_FLAGS \
19929 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19930
9eaff861 19931#undef elf_backend_emit_relocs
c3c76620 19932
906e58ca
NC		 19933#undef bfd_elf32_bfd_link_hash_table_create
19934#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19935#undef elf_backend_special_sections
19936#define elf_backend_special_sections elf32_arm_symbian_special_sections
19937#undef elf_backend_begin_write_processing
19938#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19939#undef elf_backend_final_write_processing
19940#define elf_backend_final_write_processing elf32_arm_final_write_processing
19941
19942#undef elf_backend_modify_segment_map
7f266840
DJ		 19943#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19944
19945/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19946#undef elf_backend_got_header_size
7f266840
DJ		 19947#define elf_backend_got_header_size 0
19948
19949/* Similarly, there is no .got.plt section. */
906e58ca 19950#undef elf_backend_want_got_plt
7f266840
DJ		 19951#define elf_backend_want_got_plt 0
19952
906e58ca 19953#undef elf_backend_plt_sym_val
95720a86
DJ		 19954#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19955
906e58ca 19956#undef elf_backend_may_use_rel_p
00a97672 19957#define elf_backend_may_use_rel_p 1
906e58ca 19958#undef elf_backend_may_use_rela_p
00a97672 19959#define elf_backend_may_use_rela_p 0
906e58ca 19960#undef elf_backend_default_use_rela_p
00a97672 19961#define elf_backend_default_use_rela_p 0
906e58ca 19962#undef elf_backend_want_plt_sym
00a97672 19963#define elf_backend_want_plt_sym 0
64f52338
AM		 19964#undef elf_backend_dtrel_excludes_plt
19965#define elf_backend_dtrel_excludes_plt 0
906e58ca 19966#undef ELF_MAXPAGESIZE
00a97672 19967#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19968
7f266840 19969#include "elf32-target.h"
GDB Binutils - Deliverables
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