projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Automatic date update in version.in
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
82704155 2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
7f266840 31
00a97672
RS		 32/* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34#define RELOC_SECTION(HTAB, NAME) \
35 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
36
37/* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39#define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
43
44/* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46#define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
50
51/* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53#define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
57
f3185997 58#define elf_info_to_howto NULL
07d6d2b8 59#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 60
61#define ARM_ELF_ABI_VERSION 0
62#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
63
79f08007
YZ		 64/* The Adjusted Place, as defined by AAELF. */
65#define Pa(X) ((X) & 0xfffffffc)
66
3e6b1042
DJ		 67static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
68 struct bfd_link_info *link_info,
69 asection *sec,
70 bfd_byte *contents);
71
7f266840
DJ		 72/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
73 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
74 in that slot. */
75
c19d1205 76static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 77{
8029a119 78 /* No relocation. */
7f266840
DJ		 79 HOWTO (R_ARM_NONE, /* type */
80 0, /* rightshift */
6346d5ca 81 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 82 0, /* bitsize */
83 FALSE, /* pc_relative */
84 0, /* bitpos */
85 complain_overflow_dont,/* complain_on_overflow */
86 bfd_elf_generic_reloc, /* special_function */
87 "R_ARM_NONE", /* name */
88 FALSE, /* partial_inplace */
89 0, /* src_mask */
90 0, /* dst_mask */
91 FALSE), /* pcrel_offset */
92
93 HOWTO (R_ARM_PC24, /* type */
94 2, /* rightshift */
95 2, /* size (0 = byte, 1 = short, 2 = long) */
96 24, /* bitsize */
97 TRUE, /* pc_relative */
98 0, /* bitpos */
99 complain_overflow_signed,/* complain_on_overflow */
100 bfd_elf_generic_reloc, /* special_function */
101 "R_ARM_PC24", /* name */
102 FALSE, /* partial_inplace */
103 0x00ffffff, /* src_mask */
104 0x00ffffff, /* dst_mask */
105 TRUE), /* pcrel_offset */
106
107 /* 32 bit absolute */
108 HOWTO (R_ARM_ABS32, /* type */
109 0, /* rightshift */
110 2, /* size (0 = byte, 1 = short, 2 = long) */
111 32, /* bitsize */
112 FALSE, /* pc_relative */
113 0, /* bitpos */
114 complain_overflow_bitfield,/* complain_on_overflow */
115 bfd_elf_generic_reloc, /* special_function */
116 "R_ARM_ABS32", /* name */
117 FALSE, /* partial_inplace */
118 0xffffffff, /* src_mask */
119 0xffffffff, /* dst_mask */
120 FALSE), /* pcrel_offset */
121
122 /* standard 32bit pc-relative reloc */
123 HOWTO (R_ARM_REL32, /* type */
124 0, /* rightshift */
125 2, /* size (0 = byte, 1 = short, 2 = long) */
126 32, /* bitsize */
127 TRUE, /* pc_relative */
128 0, /* bitpos */
129 complain_overflow_bitfield,/* complain_on_overflow */
130 bfd_elf_generic_reloc, /* special_function */
131 "R_ARM_REL32", /* name */
132 FALSE, /* partial_inplace */
133 0xffffffff, /* src_mask */
134 0xffffffff, /* dst_mask */
135 TRUE), /* pcrel_offset */
136
c19d1205 137 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 138 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 139 0, /* rightshift */
140 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 141 32, /* bitsize */
142 TRUE, /* pc_relative */
7f266840 143 0, /* bitpos */
4962c51a 144 complain_overflow_dont,/* complain_on_overflow */
7f266840 145 bfd_elf_generic_reloc, /* special_function */
4962c51a 146 "R_ARM_LDR_PC_G0", /* name */
7f266840 147 FALSE, /* partial_inplace */
4962c51a
MS		 148 0xffffffff, /* src_mask */
149 0xffffffff, /* dst_mask */
150 TRUE), /* pcrel_offset */
7f266840
DJ		 151
152 /* 16 bit absolute */
153 HOWTO (R_ARM_ABS16, /* type */
154 0, /* rightshift */
155 1, /* size (0 = byte, 1 = short, 2 = long) */
156 16, /* bitsize */
157 FALSE, /* pc_relative */
158 0, /* bitpos */
159 complain_overflow_bitfield,/* complain_on_overflow */
160 bfd_elf_generic_reloc, /* special_function */
161 "R_ARM_ABS16", /* name */
162 FALSE, /* partial_inplace */
163 0x0000ffff, /* src_mask */
164 0x0000ffff, /* dst_mask */
165 FALSE), /* pcrel_offset */
166
167 /* 12 bit absolute */
168 HOWTO (R_ARM_ABS12, /* type */
169 0, /* rightshift */
170 2, /* size (0 = byte, 1 = short, 2 = long) */
171 12, /* bitsize */
172 FALSE, /* pc_relative */
173 0, /* bitpos */
174 complain_overflow_bitfield,/* complain_on_overflow */
175 bfd_elf_generic_reloc, /* special_function */
176 "R_ARM_ABS12", /* name */
177 FALSE, /* partial_inplace */
00a97672
RS		 178 0x00000fff, /* src_mask */
179 0x00000fff, /* dst_mask */
7f266840
DJ		 180 FALSE), /* pcrel_offset */
181
182 HOWTO (R_ARM_THM_ABS5, /* type */
183 6, /* rightshift */
184 1, /* size (0 = byte, 1 = short, 2 = long) */
185 5, /* bitsize */
186 FALSE, /* pc_relative */
187 0, /* bitpos */
188 complain_overflow_bitfield,/* complain_on_overflow */
189 bfd_elf_generic_reloc, /* special_function */
190 "R_ARM_THM_ABS5", /* name */
191 FALSE, /* partial_inplace */
192 0x000007e0, /* src_mask */
193 0x000007e0, /* dst_mask */
194 FALSE), /* pcrel_offset */
195
196 /* 8 bit absolute */
197 HOWTO (R_ARM_ABS8, /* type */
198 0, /* rightshift */
199 0, /* size (0 = byte, 1 = short, 2 = long) */
200 8, /* bitsize */
201 FALSE, /* pc_relative */
202 0, /* bitpos */
203 complain_overflow_bitfield,/* complain_on_overflow */
204 bfd_elf_generic_reloc, /* special_function */
205 "R_ARM_ABS8", /* name */
206 FALSE, /* partial_inplace */
207 0x000000ff, /* src_mask */
208 0x000000ff, /* dst_mask */
209 FALSE), /* pcrel_offset */
210
211 HOWTO (R_ARM_SBREL32, /* type */
212 0, /* rightshift */
213 2, /* size (0 = byte, 1 = short, 2 = long) */
214 32, /* bitsize */
215 FALSE, /* pc_relative */
216 0, /* bitpos */
217 complain_overflow_dont,/* complain_on_overflow */
218 bfd_elf_generic_reloc, /* special_function */
219 "R_ARM_SBREL32", /* name */
220 FALSE, /* partial_inplace */
221 0xffffffff, /* src_mask */
222 0xffffffff, /* dst_mask */
223 FALSE), /* pcrel_offset */
224
c19d1205 225 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 226 1, /* rightshift */
227 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 228 24, /* bitsize */
7f266840
DJ		 229 TRUE, /* pc_relative */
230 0, /* bitpos */
231 complain_overflow_signed,/* complain_on_overflow */
232 bfd_elf_generic_reloc, /* special_function */
c19d1205 233 "R_ARM_THM_CALL", /* name */
7f266840 234 FALSE, /* partial_inplace */
7f6ab9f8
AM		 235 0x07ff2fff, /* src_mask */
236 0x07ff2fff, /* dst_mask */
7f266840
DJ		 237 TRUE), /* pcrel_offset */
238
07d6d2b8 239 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 240 1, /* rightshift */
241 1, /* size (0 = byte, 1 = short, 2 = long) */
242 8, /* bitsize */
243 TRUE, /* pc_relative */
244 0, /* bitpos */
245 complain_overflow_signed,/* complain_on_overflow */
246 bfd_elf_generic_reloc, /* special_function */
247 "R_ARM_THM_PC8", /* name */
248 FALSE, /* partial_inplace */
249 0x000000ff, /* src_mask */
250 0x000000ff, /* dst_mask */
251 TRUE), /* pcrel_offset */
252
c19d1205 253 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 254 1, /* rightshift */
255 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 256 32, /* bitsize */
257 FALSE, /* pc_relative */
7f266840
DJ		 258 0, /* bitpos */
259 complain_overflow_signed,/* complain_on_overflow */
260 bfd_elf_generic_reloc, /* special_function */
c19d1205 261 "R_ARM_BREL_ADJ", /* name */
7f266840 262 FALSE, /* partial_inplace */
c19d1205
ZW		 263 0xffffffff, /* src_mask */
264 0xffffffff, /* dst_mask */
265 FALSE), /* pcrel_offset */
7f266840 266
0855e32b 267 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 268 0, /* rightshift */
0855e32b
NS		 269 2, /* size (0 = byte, 1 = short, 2 = long) */
270 32, /* bitsize */
7f266840
DJ		 271 FALSE, /* pc_relative */
272 0, /* bitpos */
0855e32b 273 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 274 bfd_elf_generic_reloc, /* special_function */
0855e32b 275 "R_ARM_TLS_DESC", /* name */
7f266840 276 FALSE, /* partial_inplace */
0855e32b
NS		 277 0xffffffff, /* src_mask */
278 0xffffffff, /* dst_mask */
7f266840
DJ		 279 FALSE), /* pcrel_offset */
280
281 HOWTO (R_ARM_THM_SWI8, /* type */
282 0, /* rightshift */
283 0, /* size (0 = byte, 1 = short, 2 = long) */
284 0, /* bitsize */
285 FALSE, /* pc_relative */
286 0, /* bitpos */
287 complain_overflow_signed,/* complain_on_overflow */
288 bfd_elf_generic_reloc, /* special_function */
289 "R_ARM_SWI8", /* name */
290 FALSE, /* partial_inplace */
291 0x00000000, /* src_mask */
292 0x00000000, /* dst_mask */
293 FALSE), /* pcrel_offset */
294
295 /* BLX instruction for the ARM. */
296 HOWTO (R_ARM_XPC25, /* type */
297 2, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 299 24, /* bitsize */
7f266840
DJ		 300 TRUE, /* pc_relative */
301 0, /* bitpos */
302 complain_overflow_signed,/* complain_on_overflow */
303 bfd_elf_generic_reloc, /* special_function */
304 "R_ARM_XPC25", /* name */
305 FALSE, /* partial_inplace */
306 0x00ffffff, /* src_mask */
307 0x00ffffff, /* dst_mask */
308 TRUE), /* pcrel_offset */
309
310 /* BLX instruction for the Thumb. */
311 HOWTO (R_ARM_THM_XPC22, /* type */
312 2, /* rightshift */
313 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 314 24, /* bitsize */
7f266840
DJ		 315 TRUE, /* pc_relative */
316 0, /* bitpos */
317 complain_overflow_signed,/* complain_on_overflow */
318 bfd_elf_generic_reloc, /* special_function */
319 "R_ARM_THM_XPC22", /* name */
320 FALSE, /* partial_inplace */
7f6ab9f8
AM		 321 0x07ff2fff, /* src_mask */
322 0x07ff2fff, /* dst_mask */
7f266840
DJ		 323 TRUE), /* pcrel_offset */
324
ba93b8ac 325 /* Dynamic TLS relocations. */
7f266840 326
ba93b8ac 327 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 328 0, /* rightshift */
329 2, /* size (0 = byte, 1 = short, 2 = long) */
330 32, /* bitsize */
331 FALSE, /* pc_relative */
332 0, /* bitpos */
99059e56
RM		 333 complain_overflow_bitfield,/* complain_on_overflow */
334 bfd_elf_generic_reloc, /* special_function */
335 "R_ARM_TLS_DTPMOD32", /* name */
336 TRUE, /* partial_inplace */
337 0xffffffff, /* src_mask */
338 0xffffffff, /* dst_mask */
07d6d2b8 339 FALSE), /* pcrel_offset */
7f266840 340
ba93b8ac 341 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 342 0, /* rightshift */
343 2, /* size (0 = byte, 1 = short, 2 = long) */
344 32, /* bitsize */
345 FALSE, /* pc_relative */
346 0, /* bitpos */
99059e56
RM		 347 complain_overflow_bitfield,/* complain_on_overflow */
348 bfd_elf_generic_reloc, /* special_function */
349 "R_ARM_TLS_DTPOFF32", /* name */
350 TRUE, /* partial_inplace */
351 0xffffffff, /* src_mask */
352 0xffffffff, /* dst_mask */
07d6d2b8 353 FALSE), /* pcrel_offset */
7f266840 354
ba93b8ac 355 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 356 0, /* rightshift */
357 2, /* size (0 = byte, 1 = short, 2 = long) */
358 32, /* bitsize */
359 FALSE, /* pc_relative */
360 0, /* bitpos */
99059e56
RM		 361 complain_overflow_bitfield,/* complain_on_overflow */
362 bfd_elf_generic_reloc, /* special_function */
363 "R_ARM_TLS_TPOFF32", /* name */
364 TRUE, /* partial_inplace */
365 0xffffffff, /* src_mask */
366 0xffffffff, /* dst_mask */
07d6d2b8 367 FALSE), /* pcrel_offset */
7f266840
DJ		 368
369 /* Relocs used in ARM Linux */
370
371 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 372 0, /* rightshift */
373 2, /* size (0 = byte, 1 = short, 2 = long) */
374 32, /* bitsize */
375 FALSE, /* pc_relative */
376 0, /* bitpos */
99059e56
RM		 377 complain_overflow_bitfield,/* complain_on_overflow */
378 bfd_elf_generic_reloc, /* special_function */
379 "R_ARM_COPY", /* name */
380 TRUE, /* partial_inplace */
381 0xffffffff, /* src_mask */
382 0xffffffff, /* dst_mask */
07d6d2b8 383 FALSE), /* pcrel_offset */
7f266840
DJ		 384
385 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 386 0, /* rightshift */
387 2, /* size (0 = byte, 1 = short, 2 = long) */
388 32, /* bitsize */
389 FALSE, /* pc_relative */
390 0, /* bitpos */
99059e56
RM		 391 complain_overflow_bitfield,/* complain_on_overflow */
392 bfd_elf_generic_reloc, /* special_function */
393 "R_ARM_GLOB_DAT", /* name */
394 TRUE, /* partial_inplace */
395 0xffffffff, /* src_mask */
396 0xffffffff, /* dst_mask */
07d6d2b8 397 FALSE), /* pcrel_offset */
7f266840
DJ		 398
399 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 400 0, /* rightshift */
401 2, /* size (0 = byte, 1 = short, 2 = long) */
402 32, /* bitsize */
403 FALSE, /* pc_relative */
404 0, /* bitpos */
99059e56
RM		 405 complain_overflow_bitfield,/* complain_on_overflow */
406 bfd_elf_generic_reloc, /* special_function */
407 "R_ARM_JUMP_SLOT", /* name */
408 TRUE, /* partial_inplace */
409 0xffffffff, /* src_mask */
410 0xffffffff, /* dst_mask */
07d6d2b8 411 FALSE), /* pcrel_offset */
7f266840
DJ		 412
413 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 414 0, /* rightshift */
415 2, /* size (0 = byte, 1 = short, 2 = long) */
416 32, /* bitsize */
417 FALSE, /* pc_relative */
418 0, /* bitpos */
99059e56
RM		 419 complain_overflow_bitfield,/* complain_on_overflow */
420 bfd_elf_generic_reloc, /* special_function */
421 "R_ARM_RELATIVE", /* name */
422 TRUE, /* partial_inplace */
423 0xffffffff, /* src_mask */
424 0xffffffff, /* dst_mask */
07d6d2b8 425 FALSE), /* pcrel_offset */
7f266840 426
c19d1205 427 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 428 0, /* rightshift */
429 2, /* size (0 = byte, 1 = short, 2 = long) */
430 32, /* bitsize */
431 FALSE, /* pc_relative */
432 0, /* bitpos */
99059e56
RM		 433 complain_overflow_bitfield,/* complain_on_overflow */
434 bfd_elf_generic_reloc, /* special_function */
435 "R_ARM_GOTOFF32", /* name */
436 TRUE, /* partial_inplace */
437 0xffffffff, /* src_mask */
438 0xffffffff, /* dst_mask */
07d6d2b8 439 FALSE), /* pcrel_offset */
7f266840
DJ		 440
441 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 442 0, /* rightshift */
443 2, /* size (0 = byte, 1 = short, 2 = long) */
444 32, /* bitsize */
99059e56 445 TRUE, /* pc_relative */
07d6d2b8 446 0, /* bitpos */
99059e56
RM		 447 complain_overflow_bitfield,/* complain_on_overflow */
448 bfd_elf_generic_reloc, /* special_function */
449 "R_ARM_GOTPC", /* name */
450 TRUE, /* partial_inplace */
451 0xffffffff, /* src_mask */
452 0xffffffff, /* dst_mask */
453 TRUE), /* pcrel_offset */
7f266840
DJ		 454
455 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 456 0, /* rightshift */
457 2, /* size (0 = byte, 1 = short, 2 = long) */
458 32, /* bitsize */
99059e56 459 FALSE, /* pc_relative */
07d6d2b8 460 0, /* bitpos */
99059e56
RM		 461 complain_overflow_bitfield,/* complain_on_overflow */
462 bfd_elf_generic_reloc, /* special_function */
463 "R_ARM_GOT32", /* name */
464 TRUE, /* partial_inplace */
465 0xffffffff, /* src_mask */
466 0xffffffff, /* dst_mask */
467 FALSE), /* pcrel_offset */
7f266840
DJ		 468
469 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 470 2, /* rightshift */
471 2, /* size (0 = byte, 1 = short, 2 = long) */
472 24, /* bitsize */
99059e56 473 TRUE, /* pc_relative */
07d6d2b8 474 0, /* bitpos */
99059e56
RM		 475 complain_overflow_bitfield,/* complain_on_overflow */
476 bfd_elf_generic_reloc, /* special_function */
477 "R_ARM_PLT32", /* name */
478 FALSE, /* partial_inplace */
479 0x00ffffff, /* src_mask */
480 0x00ffffff, /* dst_mask */
481 TRUE), /* pcrel_offset */
7f266840
DJ		 482
483 HOWTO (R_ARM_CALL, /* type */
484 2, /* rightshift */
485 2, /* size (0 = byte, 1 = short, 2 = long) */
486 24, /* bitsize */
487 TRUE, /* pc_relative */
488 0, /* bitpos */
489 complain_overflow_signed,/* complain_on_overflow */
490 bfd_elf_generic_reloc, /* special_function */
491 "R_ARM_CALL", /* name */
492 FALSE, /* partial_inplace */
493 0x00ffffff, /* src_mask */
494 0x00ffffff, /* dst_mask */
495 TRUE), /* pcrel_offset */
496
497 HOWTO (R_ARM_JUMP24, /* type */
498 2, /* rightshift */
499 2, /* size (0 = byte, 1 = short, 2 = long) */
500 24, /* bitsize */
501 TRUE, /* pc_relative */
502 0, /* bitpos */
503 complain_overflow_signed,/* complain_on_overflow */
504 bfd_elf_generic_reloc, /* special_function */
505 "R_ARM_JUMP24", /* name */
506 FALSE, /* partial_inplace */
507 0x00ffffff, /* src_mask */
508 0x00ffffff, /* dst_mask */
509 TRUE), /* pcrel_offset */
510
c19d1205
ZW		 511 HOWTO (R_ARM_THM_JUMP24, /* type */
512 1, /* rightshift */
513 2, /* size (0 = byte, 1 = short, 2 = long) */
514 24, /* bitsize */
515 TRUE, /* pc_relative */
7f266840 516 0, /* bitpos */
c19d1205 517 complain_overflow_signed,/* complain_on_overflow */
7f266840 518 bfd_elf_generic_reloc, /* special_function */
c19d1205 519 "R_ARM_THM_JUMP24", /* name */
7f266840 520 FALSE, /* partial_inplace */
c19d1205
ZW		 521 0x07ff2fff, /* src_mask */
522 0x07ff2fff, /* dst_mask */
523 TRUE), /* pcrel_offset */
7f266840 524
c19d1205 525 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 526 0, /* rightshift */
c19d1205
ZW		 527 2, /* size (0 = byte, 1 = short, 2 = long) */
528 32, /* bitsize */
7f266840
DJ		 529 FALSE, /* pc_relative */
530 0, /* bitpos */
531 complain_overflow_dont,/* complain_on_overflow */
532 bfd_elf_generic_reloc, /* special_function */
c19d1205 533 "R_ARM_BASE_ABS", /* name */
7f266840 534 FALSE, /* partial_inplace */
c19d1205
ZW		 535 0xffffffff, /* src_mask */
536 0xffffffff, /* dst_mask */
7f266840
DJ		 537 FALSE), /* pcrel_offset */
538
539 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
540 0, /* rightshift */
541 2, /* size (0 = byte, 1 = short, 2 = long) */
542 12, /* bitsize */
543 TRUE, /* pc_relative */
544 0, /* bitpos */
545 complain_overflow_dont,/* complain_on_overflow */
546 bfd_elf_generic_reloc, /* special_function */
547 "R_ARM_ALU_PCREL_7_0", /* name */
548 FALSE, /* partial_inplace */
549 0x00000fff, /* src_mask */
550 0x00000fff, /* dst_mask */
551 TRUE), /* pcrel_offset */
552
553 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
554 0, /* rightshift */
555 2, /* size (0 = byte, 1 = short, 2 = long) */
556 12, /* bitsize */
557 TRUE, /* pc_relative */
558 8, /* bitpos */
559 complain_overflow_dont,/* complain_on_overflow */
560 bfd_elf_generic_reloc, /* special_function */
561 "R_ARM_ALU_PCREL_15_8",/* name */
562 FALSE, /* partial_inplace */
563 0x00000fff, /* src_mask */
564 0x00000fff, /* dst_mask */
565 TRUE), /* pcrel_offset */
566
567 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
568 0, /* rightshift */
569 2, /* size (0 = byte, 1 = short, 2 = long) */
570 12, /* bitsize */
571 TRUE, /* pc_relative */
572 16, /* bitpos */
573 complain_overflow_dont,/* complain_on_overflow */
574 bfd_elf_generic_reloc, /* special_function */
575 "R_ARM_ALU_PCREL_23_15",/* name */
576 FALSE, /* partial_inplace */
577 0x00000fff, /* src_mask */
578 0x00000fff, /* dst_mask */
579 TRUE), /* pcrel_offset */
580
581 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
582 0, /* rightshift */
583 2, /* size (0 = byte, 1 = short, 2 = long) */
584 12, /* bitsize */
585 FALSE, /* pc_relative */
586 0, /* bitpos */
587 complain_overflow_dont,/* complain_on_overflow */
588 bfd_elf_generic_reloc, /* special_function */
589 "R_ARM_LDR_SBREL_11_0",/* name */
590 FALSE, /* partial_inplace */
591 0x00000fff, /* src_mask */
592 0x00000fff, /* dst_mask */
593 FALSE), /* pcrel_offset */
594
595 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
596 0, /* rightshift */
597 2, /* size (0 = byte, 1 = short, 2 = long) */
598 8, /* bitsize */
599 FALSE, /* pc_relative */
600 12, /* bitpos */
601 complain_overflow_dont,/* complain_on_overflow */
602 bfd_elf_generic_reloc, /* special_function */
603 "R_ARM_ALU_SBREL_19_12",/* name */
604 FALSE, /* partial_inplace */
605 0x000ff000, /* src_mask */
606 0x000ff000, /* dst_mask */
607 FALSE), /* pcrel_offset */
608
609 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
610 0, /* rightshift */
611 2, /* size (0 = byte, 1 = short, 2 = long) */
612 8, /* bitsize */
613 FALSE, /* pc_relative */
614 20, /* bitpos */
615 complain_overflow_dont,/* complain_on_overflow */
616 bfd_elf_generic_reloc, /* special_function */
617 "R_ARM_ALU_SBREL_27_20",/* name */
618 FALSE, /* partial_inplace */
619 0x0ff00000, /* src_mask */
620 0x0ff00000, /* dst_mask */
621 FALSE), /* pcrel_offset */
622
623 HOWTO (R_ARM_TARGET1, /* type */
624 0, /* rightshift */
625 2, /* size (0 = byte, 1 = short, 2 = long) */
626 32, /* bitsize */
627 FALSE, /* pc_relative */
628 0, /* bitpos */
629 complain_overflow_dont,/* complain_on_overflow */
630 bfd_elf_generic_reloc, /* special_function */
631 "R_ARM_TARGET1", /* name */
632 FALSE, /* partial_inplace */
633 0xffffffff, /* src_mask */
634 0xffffffff, /* dst_mask */
635 FALSE), /* pcrel_offset */
636
637 HOWTO (R_ARM_ROSEGREL32, /* type */
638 0, /* rightshift */
639 2, /* size (0 = byte, 1 = short, 2 = long) */
640 32, /* bitsize */
641 FALSE, /* pc_relative */
642 0, /* bitpos */
643 complain_overflow_dont,/* complain_on_overflow */
644 bfd_elf_generic_reloc, /* special_function */
645 "R_ARM_ROSEGREL32", /* name */
646 FALSE, /* partial_inplace */
647 0xffffffff, /* src_mask */
648 0xffffffff, /* dst_mask */
649 FALSE), /* pcrel_offset */
650
651 HOWTO (R_ARM_V4BX, /* type */
652 0, /* rightshift */
653 2, /* size (0 = byte, 1 = short, 2 = long) */
654 32, /* bitsize */
655 FALSE, /* pc_relative */
656 0, /* bitpos */
657 complain_overflow_dont,/* complain_on_overflow */
658 bfd_elf_generic_reloc, /* special_function */
659 "R_ARM_V4BX", /* name */
660 FALSE, /* partial_inplace */
661 0xffffffff, /* src_mask */
662 0xffffffff, /* dst_mask */
663 FALSE), /* pcrel_offset */
664
665 HOWTO (R_ARM_TARGET2, /* type */
666 0, /* rightshift */
667 2, /* size (0 = byte, 1 = short, 2 = long) */
668 32, /* bitsize */
669 FALSE, /* pc_relative */
670 0, /* bitpos */
671 complain_overflow_signed,/* complain_on_overflow */
672 bfd_elf_generic_reloc, /* special_function */
673 "R_ARM_TARGET2", /* name */
674 FALSE, /* partial_inplace */
675 0xffffffff, /* src_mask */
676 0xffffffff, /* dst_mask */
677 TRUE), /* pcrel_offset */
678
679 HOWTO (R_ARM_PREL31, /* type */
680 0, /* rightshift */
681 2, /* size (0 = byte, 1 = short, 2 = long) */
682 31, /* bitsize */
683 TRUE, /* pc_relative */
684 0, /* bitpos */
685 complain_overflow_signed,/* complain_on_overflow */
686 bfd_elf_generic_reloc, /* special_function */
687 "R_ARM_PREL31", /* name */
688 FALSE, /* partial_inplace */
689 0x7fffffff, /* src_mask */
690 0x7fffffff, /* dst_mask */
691 TRUE), /* pcrel_offset */
c19d1205
ZW		 692
693 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
694 0, /* rightshift */
695 2, /* size (0 = byte, 1 = short, 2 = long) */
696 16, /* bitsize */
697 FALSE, /* pc_relative */
698 0, /* bitpos */
699 complain_overflow_dont,/* complain_on_overflow */
700 bfd_elf_generic_reloc, /* special_function */
701 "R_ARM_MOVW_ABS_NC", /* name */
702 FALSE, /* partial_inplace */
39623e12
PB		 703 0x000f0fff, /* src_mask */
704 0x000f0fff, /* dst_mask */
c19d1205
ZW		 705 FALSE), /* pcrel_offset */
706
707 HOWTO (R_ARM_MOVT_ABS, /* type */
708 0, /* rightshift */
709 2, /* size (0 = byte, 1 = short, 2 = long) */
710 16, /* bitsize */
711 FALSE, /* pc_relative */
712 0, /* bitpos */
713 complain_overflow_bitfield,/* complain_on_overflow */
714 bfd_elf_generic_reloc, /* special_function */
715 "R_ARM_MOVT_ABS", /* name */
716 FALSE, /* partial_inplace */
39623e12
PB		 717 0x000f0fff, /* src_mask */
718 0x000f0fff, /* dst_mask */
c19d1205
ZW		 719 FALSE), /* pcrel_offset */
720
721 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
722 0, /* rightshift */
723 2, /* size (0 = byte, 1 = short, 2 = long) */
724 16, /* bitsize */
725 TRUE, /* pc_relative */
726 0, /* bitpos */
727 complain_overflow_dont,/* complain_on_overflow */
728 bfd_elf_generic_reloc, /* special_function */
729 "R_ARM_MOVW_PREL_NC", /* name */
730 FALSE, /* partial_inplace */
39623e12
PB		 731 0x000f0fff, /* src_mask */
732 0x000f0fff, /* dst_mask */
c19d1205
ZW		 733 TRUE), /* pcrel_offset */
734
735 HOWTO (R_ARM_MOVT_PREL, /* type */
736 0, /* rightshift */
737 2, /* size (0 = byte, 1 = short, 2 = long) */
738 16, /* bitsize */
739 TRUE, /* pc_relative */
740 0, /* bitpos */
741 complain_overflow_bitfield,/* complain_on_overflow */
742 bfd_elf_generic_reloc, /* special_function */
743 "R_ARM_MOVT_PREL", /* name */
744 FALSE, /* partial_inplace */
39623e12
PB		 745 0x000f0fff, /* src_mask */
746 0x000f0fff, /* dst_mask */
c19d1205
ZW		 747 TRUE), /* pcrel_offset */
748
749 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
750 0, /* rightshift */
751 2, /* size (0 = byte, 1 = short, 2 = long) */
752 16, /* bitsize */
753 FALSE, /* pc_relative */
754 0, /* bitpos */
755 complain_overflow_dont,/* complain_on_overflow */
756 bfd_elf_generic_reloc, /* special_function */
757 "R_ARM_THM_MOVW_ABS_NC",/* name */
758 FALSE, /* partial_inplace */
759 0x040f70ff, /* src_mask */
760 0x040f70ff, /* dst_mask */
761 FALSE), /* pcrel_offset */
762
763 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
764 0, /* rightshift */
765 2, /* size (0 = byte, 1 = short, 2 = long) */
766 16, /* bitsize */
767 FALSE, /* pc_relative */
768 0, /* bitpos */
769 complain_overflow_bitfield,/* complain_on_overflow */
770 bfd_elf_generic_reloc, /* special_function */
771 "R_ARM_THM_MOVT_ABS", /* name */
772 FALSE, /* partial_inplace */
773 0x040f70ff, /* src_mask */
774 0x040f70ff, /* dst_mask */
775 FALSE), /* pcrel_offset */
776
777 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
778 0, /* rightshift */
779 2, /* size (0 = byte, 1 = short, 2 = long) */
780 16, /* bitsize */
781 TRUE, /* pc_relative */
782 0, /* bitpos */
783 complain_overflow_dont,/* complain_on_overflow */
784 bfd_elf_generic_reloc, /* special_function */
785 "R_ARM_THM_MOVW_PREL_NC",/* name */
786 FALSE, /* partial_inplace */
787 0x040f70ff, /* src_mask */
788 0x040f70ff, /* dst_mask */
789 TRUE), /* pcrel_offset */
790
791 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
792 0, /* rightshift */
793 2, /* size (0 = byte, 1 = short, 2 = long) */
794 16, /* bitsize */
795 TRUE, /* pc_relative */
796 0, /* bitpos */
797 complain_overflow_bitfield,/* complain_on_overflow */
798 bfd_elf_generic_reloc, /* special_function */
799 "R_ARM_THM_MOVT_PREL", /* name */
800 FALSE, /* partial_inplace */
801 0x040f70ff, /* src_mask */
802 0x040f70ff, /* dst_mask */
803 TRUE), /* pcrel_offset */
804
805 HOWTO (R_ARM_THM_JUMP19, /* type */
806 1, /* rightshift */
807 2, /* size (0 = byte, 1 = short, 2 = long) */
808 19, /* bitsize */
809 TRUE, /* pc_relative */
810 0, /* bitpos */
811 complain_overflow_signed,/* complain_on_overflow */
812 bfd_elf_generic_reloc, /* special_function */
813 "R_ARM_THM_JUMP19", /* name */
814 FALSE, /* partial_inplace */
815 0x043f2fff, /* src_mask */
816 0x043f2fff, /* dst_mask */
817 TRUE), /* pcrel_offset */
818
819 HOWTO (R_ARM_THM_JUMP6, /* type */
820 1, /* rightshift */
821 1, /* size (0 = byte, 1 = short, 2 = long) */
822 6, /* bitsize */
823 TRUE, /* pc_relative */
824 0, /* bitpos */
825 complain_overflow_unsigned,/* complain_on_overflow */
826 bfd_elf_generic_reloc, /* special_function */
827 "R_ARM_THM_JUMP6", /* name */
828 FALSE, /* partial_inplace */
829 0x02f8, /* src_mask */
830 0x02f8, /* dst_mask */
831 TRUE), /* pcrel_offset */
832
833 /* These are declared as 13-bit signed relocations because we can
834 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
835 versa. */
836 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
837 0, /* rightshift */
838 2, /* size (0 = byte, 1 = short, 2 = long) */
839 13, /* bitsize */
840 TRUE, /* pc_relative */
841 0, /* bitpos */
2cab6cc3 842 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 843 bfd_elf_generic_reloc, /* special_function */
844 "R_ARM_THM_ALU_PREL_11_0",/* name */
845 FALSE, /* partial_inplace */
2cab6cc3
MS		 846 0xffffffff, /* src_mask */
847 0xffffffff, /* dst_mask */
c19d1205
ZW		 848 TRUE), /* pcrel_offset */
849
850 HOWTO (R_ARM_THM_PC12, /* type */
851 0, /* rightshift */
852 2, /* size (0 = byte, 1 = short, 2 = long) */
853 13, /* bitsize */
854 TRUE, /* pc_relative */
855 0, /* bitpos */
2cab6cc3 856 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 857 bfd_elf_generic_reloc, /* special_function */
858 "R_ARM_THM_PC12", /* name */
859 FALSE, /* partial_inplace */
2cab6cc3
MS		 860 0xffffffff, /* src_mask */
861 0xffffffff, /* dst_mask */
c19d1205
ZW		 862 TRUE), /* pcrel_offset */
863
864 HOWTO (R_ARM_ABS32_NOI, /* type */
865 0, /* rightshift */
866 2, /* size (0 = byte, 1 = short, 2 = long) */
867 32, /* bitsize */
868 FALSE, /* pc_relative */
869 0, /* bitpos */
870 complain_overflow_dont,/* complain_on_overflow */
871 bfd_elf_generic_reloc, /* special_function */
872 "R_ARM_ABS32_NOI", /* name */
873 FALSE, /* partial_inplace */
874 0xffffffff, /* src_mask */
875 0xffffffff, /* dst_mask */
876 FALSE), /* pcrel_offset */
877
878 HOWTO (R_ARM_REL32_NOI, /* type */
879 0, /* rightshift */
880 2, /* size (0 = byte, 1 = short, 2 = long) */
881 32, /* bitsize */
882 TRUE, /* pc_relative */
883 0, /* bitpos */
884 complain_overflow_dont,/* complain_on_overflow */
885 bfd_elf_generic_reloc, /* special_function */
886 "R_ARM_REL32_NOI", /* name */
887 FALSE, /* partial_inplace */
888 0xffffffff, /* src_mask */
889 0xffffffff, /* dst_mask */
890 FALSE), /* pcrel_offset */
7f266840 891
4962c51a
MS		 892 /* Group relocations. */
893
894 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
895 0, /* rightshift */
896 2, /* size (0 = byte, 1 = short, 2 = long) */
897 32, /* bitsize */
898 TRUE, /* pc_relative */
899 0, /* bitpos */
900 complain_overflow_dont,/* complain_on_overflow */
901 bfd_elf_generic_reloc, /* special_function */
902 "R_ARM_ALU_PC_G0_NC", /* name */
903 FALSE, /* partial_inplace */
904 0xffffffff, /* src_mask */
905 0xffffffff, /* dst_mask */
906 TRUE), /* pcrel_offset */
907
07d6d2b8 908 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 909 0, /* rightshift */
910 2, /* size (0 = byte, 1 = short, 2 = long) */
911 32, /* bitsize */
912 TRUE, /* pc_relative */
913 0, /* bitpos */
914 complain_overflow_dont,/* complain_on_overflow */
915 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 916 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 917 FALSE, /* partial_inplace */
918 0xffffffff, /* src_mask */
919 0xffffffff, /* dst_mask */
920 TRUE), /* pcrel_offset */
921
922 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
923 0, /* rightshift */
924 2, /* size (0 = byte, 1 = short, 2 = long) */
925 32, /* bitsize */
926 TRUE, /* pc_relative */
927 0, /* bitpos */
928 complain_overflow_dont,/* complain_on_overflow */
929 bfd_elf_generic_reloc, /* special_function */
930 "R_ARM_ALU_PC_G1_NC", /* name */
931 FALSE, /* partial_inplace */
932 0xffffffff, /* src_mask */
933 0xffffffff, /* dst_mask */
934 TRUE), /* pcrel_offset */
935
07d6d2b8 936 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 937 0, /* rightshift */
938 2, /* size (0 = byte, 1 = short, 2 = long) */
939 32, /* bitsize */
940 TRUE, /* pc_relative */
941 0, /* bitpos */
942 complain_overflow_dont,/* complain_on_overflow */
943 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 944 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 945 FALSE, /* partial_inplace */
946 0xffffffff, /* src_mask */
947 0xffffffff, /* dst_mask */
948 TRUE), /* pcrel_offset */
949
07d6d2b8 950 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 951 0, /* rightshift */
952 2, /* size (0 = byte, 1 = short, 2 = long) */
953 32, /* bitsize */
954 TRUE, /* pc_relative */
955 0, /* bitpos */
956 complain_overflow_dont,/* complain_on_overflow */
957 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 958 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 959 FALSE, /* partial_inplace */
960 0xffffffff, /* src_mask */
961 0xffffffff, /* dst_mask */
962 TRUE), /* pcrel_offset */
963
07d6d2b8 964 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 965 0, /* rightshift */
966 2, /* size (0 = byte, 1 = short, 2 = long) */
967 32, /* bitsize */
968 TRUE, /* pc_relative */
969 0, /* bitpos */
970 complain_overflow_dont,/* complain_on_overflow */
971 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 972 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 973 FALSE, /* partial_inplace */
974 0xffffffff, /* src_mask */
975 0xffffffff, /* dst_mask */
976 TRUE), /* pcrel_offset */
977
07d6d2b8 978 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 979 0, /* rightshift */
980 2, /* size (0 = byte, 1 = short, 2 = long) */
981 32, /* bitsize */
982 TRUE, /* pc_relative */
983 0, /* bitpos */
984 complain_overflow_dont,/* complain_on_overflow */
985 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 986 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 987 FALSE, /* partial_inplace */
988 0xffffffff, /* src_mask */
989 0xffffffff, /* dst_mask */
990 TRUE), /* pcrel_offset */
991
07d6d2b8 992 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 993 0, /* rightshift */
994 2, /* size (0 = byte, 1 = short, 2 = long) */
995 32, /* bitsize */
996 TRUE, /* pc_relative */
997 0, /* bitpos */
998 complain_overflow_dont,/* complain_on_overflow */
999 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1000 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1001 FALSE, /* partial_inplace */
1002 0xffffffff, /* src_mask */
1003 0xffffffff, /* dst_mask */
1004 TRUE), /* pcrel_offset */
1005
07d6d2b8 1006 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1007 0, /* rightshift */
1008 2, /* size (0 = byte, 1 = short, 2 = long) */
1009 32, /* bitsize */
1010 TRUE, /* pc_relative */
1011 0, /* bitpos */
1012 complain_overflow_dont,/* complain_on_overflow */
1013 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1014 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1015 FALSE, /* partial_inplace */
1016 0xffffffff, /* src_mask */
1017 0xffffffff, /* dst_mask */
1018 TRUE), /* pcrel_offset */
1019
07d6d2b8 1020 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1021 0, /* rightshift */
1022 2, /* size (0 = byte, 1 = short, 2 = long) */
1023 32, /* bitsize */
1024 TRUE, /* pc_relative */
1025 0, /* bitpos */
1026 complain_overflow_dont,/* complain_on_overflow */
1027 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1028 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1029 FALSE, /* partial_inplace */
1030 0xffffffff, /* src_mask */
1031 0xffffffff, /* dst_mask */
1032 TRUE), /* pcrel_offset */
1033
07d6d2b8 1034 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1035 0, /* rightshift */
1036 2, /* size (0 = byte, 1 = short, 2 = long) */
1037 32, /* bitsize */
1038 TRUE, /* pc_relative */
1039 0, /* bitpos */
1040 complain_overflow_dont,/* complain_on_overflow */
1041 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1042 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1043 FALSE, /* partial_inplace */
1044 0xffffffff, /* src_mask */
1045 0xffffffff, /* dst_mask */
1046 TRUE), /* pcrel_offset */
1047
07d6d2b8 1048 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1049 0, /* rightshift */
1050 2, /* size (0 = byte, 1 = short, 2 = long) */
1051 32, /* bitsize */
1052 TRUE, /* pc_relative */
1053 0, /* bitpos */
1054 complain_overflow_dont,/* complain_on_overflow */
1055 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1056 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1057 FALSE, /* partial_inplace */
1058 0xffffffff, /* src_mask */
1059 0xffffffff, /* dst_mask */
1060 TRUE), /* pcrel_offset */
1061
07d6d2b8 1062 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1063 0, /* rightshift */
1064 2, /* size (0 = byte, 1 = short, 2 = long) */
1065 32, /* bitsize */
1066 TRUE, /* pc_relative */
1067 0, /* bitpos */
1068 complain_overflow_dont,/* complain_on_overflow */
1069 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1070 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1071 FALSE, /* partial_inplace */
1072 0xffffffff, /* src_mask */
1073 0xffffffff, /* dst_mask */
1074 TRUE), /* pcrel_offset */
1075
07d6d2b8 1076 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1077 0, /* rightshift */
1078 2, /* size (0 = byte, 1 = short, 2 = long) */
1079 32, /* bitsize */
1080 TRUE, /* pc_relative */
1081 0, /* bitpos */
1082 complain_overflow_dont,/* complain_on_overflow */
1083 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1084 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1085 FALSE, /* partial_inplace */
1086 0xffffffff, /* src_mask */
1087 0xffffffff, /* dst_mask */
1088 TRUE), /* pcrel_offset */
1089
07d6d2b8 1090 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1091 0, /* rightshift */
1092 2, /* size (0 = byte, 1 = short, 2 = long) */
1093 32, /* bitsize */
1094 TRUE, /* pc_relative */
1095 0, /* bitpos */
1096 complain_overflow_dont,/* complain_on_overflow */
1097 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1098 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1099 FALSE, /* partial_inplace */
1100 0xffffffff, /* src_mask */
1101 0xffffffff, /* dst_mask */
1102 TRUE), /* pcrel_offset */
1103
07d6d2b8 1104 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1105 0, /* rightshift */
1106 2, /* size (0 = byte, 1 = short, 2 = long) */
1107 32, /* bitsize */
1108 TRUE, /* pc_relative */
1109 0, /* bitpos */
1110 complain_overflow_dont,/* complain_on_overflow */
1111 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1112 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1113 FALSE, /* partial_inplace */
1114 0xffffffff, /* src_mask */
1115 0xffffffff, /* dst_mask */
1116 TRUE), /* pcrel_offset */
1117
07d6d2b8 1118 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1119 0, /* rightshift */
1120 2, /* size (0 = byte, 1 = short, 2 = long) */
1121 32, /* bitsize */
1122 TRUE, /* pc_relative */
1123 0, /* bitpos */
1124 complain_overflow_dont,/* complain_on_overflow */
1125 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1126 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1127 FALSE, /* partial_inplace */
1128 0xffffffff, /* src_mask */
1129 0xffffffff, /* dst_mask */
1130 TRUE), /* pcrel_offset */
1131
07d6d2b8 1132 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1133 0, /* rightshift */
1134 2, /* size (0 = byte, 1 = short, 2 = long) */
1135 32, /* bitsize */
1136 TRUE, /* pc_relative */
1137 0, /* bitpos */
1138 complain_overflow_dont,/* complain_on_overflow */
1139 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1140 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1141 FALSE, /* partial_inplace */
1142 0xffffffff, /* src_mask */
1143 0xffffffff, /* dst_mask */
1144 TRUE), /* pcrel_offset */
1145
07d6d2b8 1146 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1147 0, /* rightshift */
1148 2, /* size (0 = byte, 1 = short, 2 = long) */
1149 32, /* bitsize */
1150 TRUE, /* pc_relative */
1151 0, /* bitpos */
1152 complain_overflow_dont,/* complain_on_overflow */
1153 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1154 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1155 FALSE, /* partial_inplace */
1156 0xffffffff, /* src_mask */
1157 0xffffffff, /* dst_mask */
1158 TRUE), /* pcrel_offset */
1159
07d6d2b8 1160 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1161 0, /* rightshift */
1162 2, /* size (0 = byte, 1 = short, 2 = long) */
1163 32, /* bitsize */
1164 TRUE, /* pc_relative */
1165 0, /* bitpos */
1166 complain_overflow_dont,/* complain_on_overflow */
1167 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1168 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1169 FALSE, /* partial_inplace */
1170 0xffffffff, /* src_mask */
1171 0xffffffff, /* dst_mask */
1172 TRUE), /* pcrel_offset */
1173
07d6d2b8 1174 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1175 0, /* rightshift */
1176 2, /* size (0 = byte, 1 = short, 2 = long) */
1177 32, /* bitsize */
1178 TRUE, /* pc_relative */
1179 0, /* bitpos */
1180 complain_overflow_dont,/* complain_on_overflow */
1181 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1182 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1183 FALSE, /* partial_inplace */
1184 0xffffffff, /* src_mask */
1185 0xffffffff, /* dst_mask */
1186 TRUE), /* pcrel_offset */
1187
07d6d2b8 1188 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1189 0, /* rightshift */
1190 2, /* size (0 = byte, 1 = short, 2 = long) */
1191 32, /* bitsize */
1192 TRUE, /* pc_relative */
1193 0, /* bitpos */
1194 complain_overflow_dont,/* complain_on_overflow */
1195 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1196 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1197 FALSE, /* partial_inplace */
1198 0xffffffff, /* src_mask */
1199 0xffffffff, /* dst_mask */
1200 TRUE), /* pcrel_offset */
1201
07d6d2b8 1202 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1203 0, /* rightshift */
1204 2, /* size (0 = byte, 1 = short, 2 = long) */
1205 32, /* bitsize */
1206 TRUE, /* pc_relative */
1207 0, /* bitpos */
1208 complain_overflow_dont,/* complain_on_overflow */
1209 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1210 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1211 FALSE, /* partial_inplace */
1212 0xffffffff, /* src_mask */
1213 0xffffffff, /* dst_mask */
1214 TRUE), /* pcrel_offset */
1215
07d6d2b8 1216 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1217 0, /* rightshift */
1218 2, /* size (0 = byte, 1 = short, 2 = long) */
1219 32, /* bitsize */
1220 TRUE, /* pc_relative */
1221 0, /* bitpos */
1222 complain_overflow_dont,/* complain_on_overflow */
1223 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1224 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1225 FALSE, /* partial_inplace */
1226 0xffffffff, /* src_mask */
1227 0xffffffff, /* dst_mask */
1228 TRUE), /* pcrel_offset */
1229
07d6d2b8 1230 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1231 0, /* rightshift */
1232 2, /* size (0 = byte, 1 = short, 2 = long) */
1233 32, /* bitsize */
1234 TRUE, /* pc_relative */
1235 0, /* bitpos */
1236 complain_overflow_dont,/* complain_on_overflow */
1237 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1238 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1239 FALSE, /* partial_inplace */
1240 0xffffffff, /* src_mask */
1241 0xffffffff, /* dst_mask */
1242 TRUE), /* pcrel_offset */
1243
07d6d2b8 1244 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1245 0, /* rightshift */
1246 2, /* size (0 = byte, 1 = short, 2 = long) */
1247 32, /* bitsize */
1248 TRUE, /* pc_relative */
1249 0, /* bitpos */
1250 complain_overflow_dont,/* complain_on_overflow */
1251 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1252 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1253 FALSE, /* partial_inplace */
1254 0xffffffff, /* src_mask */
1255 0xffffffff, /* dst_mask */
1256 TRUE), /* pcrel_offset */
1257
07d6d2b8 1258 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1259 0, /* rightshift */
1260 2, /* size (0 = byte, 1 = short, 2 = long) */
1261 32, /* bitsize */
1262 TRUE, /* pc_relative */
1263 0, /* bitpos */
1264 complain_overflow_dont,/* complain_on_overflow */
1265 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1266 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1267 FALSE, /* partial_inplace */
1268 0xffffffff, /* src_mask */
1269 0xffffffff, /* dst_mask */
1270 TRUE), /* pcrel_offset */
1271
1272 /* End of group relocations. */
c19d1205 1273
c19d1205
ZW		 1274 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1275 0, /* rightshift */
1276 2, /* size (0 = byte, 1 = short, 2 = long) */
1277 16, /* bitsize */
1278 FALSE, /* pc_relative */
1279 0, /* bitpos */
1280 complain_overflow_dont,/* complain_on_overflow */
1281 bfd_elf_generic_reloc, /* special_function */
1282 "R_ARM_MOVW_BREL_NC", /* name */
1283 FALSE, /* partial_inplace */
1284 0x0000ffff, /* src_mask */
1285 0x0000ffff, /* dst_mask */
1286 FALSE), /* pcrel_offset */
1287
1288 HOWTO (R_ARM_MOVT_BREL, /* type */
1289 0, /* rightshift */
1290 2, /* size (0 = byte, 1 = short, 2 = long) */
1291 16, /* bitsize */
1292 FALSE, /* pc_relative */
1293 0, /* bitpos */
1294 complain_overflow_bitfield,/* complain_on_overflow */
1295 bfd_elf_generic_reloc, /* special_function */
1296 "R_ARM_MOVT_BREL", /* name */
1297 FALSE, /* partial_inplace */
1298 0x0000ffff, /* src_mask */
1299 0x0000ffff, /* dst_mask */
1300 FALSE), /* pcrel_offset */
1301
1302 HOWTO (R_ARM_MOVW_BREL, /* type */
1303 0, /* rightshift */
1304 2, /* size (0 = byte, 1 = short, 2 = long) */
1305 16, /* bitsize */
1306 FALSE, /* pc_relative */
1307 0, /* bitpos */
1308 complain_overflow_dont,/* complain_on_overflow */
1309 bfd_elf_generic_reloc, /* special_function */
1310 "R_ARM_MOVW_BREL", /* name */
1311 FALSE, /* partial_inplace */
1312 0x0000ffff, /* src_mask */
1313 0x0000ffff, /* dst_mask */
1314 FALSE), /* pcrel_offset */
1315
1316 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1317 0, /* rightshift */
1318 2, /* size (0 = byte, 1 = short, 2 = long) */
1319 16, /* bitsize */
1320 FALSE, /* pc_relative */
1321 0, /* bitpos */
1322 complain_overflow_dont,/* complain_on_overflow */
1323 bfd_elf_generic_reloc, /* special_function */
1324 "R_ARM_THM_MOVW_BREL_NC",/* name */
1325 FALSE, /* partial_inplace */
1326 0x040f70ff, /* src_mask */
1327 0x040f70ff, /* dst_mask */
1328 FALSE), /* pcrel_offset */
1329
1330 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1331 0, /* rightshift */
1332 2, /* size (0 = byte, 1 = short, 2 = long) */
1333 16, /* bitsize */
1334 FALSE, /* pc_relative */
1335 0, /* bitpos */
1336 complain_overflow_bitfield,/* complain_on_overflow */
1337 bfd_elf_generic_reloc, /* special_function */
1338 "R_ARM_THM_MOVT_BREL", /* name */
1339 FALSE, /* partial_inplace */
1340 0x040f70ff, /* src_mask */
1341 0x040f70ff, /* dst_mask */
1342 FALSE), /* pcrel_offset */
1343
1344 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1345 0, /* rightshift */
1346 2, /* size (0 = byte, 1 = short, 2 = long) */
1347 16, /* bitsize */
1348 FALSE, /* pc_relative */
1349 0, /* bitpos */
1350 complain_overflow_dont,/* complain_on_overflow */
1351 bfd_elf_generic_reloc, /* special_function */
1352 "R_ARM_THM_MOVW_BREL", /* name */
1353 FALSE, /* partial_inplace */
1354 0x040f70ff, /* src_mask */
1355 0x040f70ff, /* dst_mask */
1356 FALSE), /* pcrel_offset */
1357
0855e32b
NS		 1358 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1359 0, /* rightshift */
1360 2, /* size (0 = byte, 1 = short, 2 = long) */
1361 32, /* bitsize */
1362 FALSE, /* pc_relative */
1363 0, /* bitpos */
1364 complain_overflow_bitfield,/* complain_on_overflow */
1365 NULL, /* special_function */
1366 "R_ARM_TLS_GOTDESC", /* name */
1367 TRUE, /* partial_inplace */
1368 0xffffffff, /* src_mask */
1369 0xffffffff, /* dst_mask */
1370 FALSE), /* pcrel_offset */
1371
1372 HOWTO (R_ARM_TLS_CALL, /* type */
1373 0, /* rightshift */
1374 2, /* size (0 = byte, 1 = short, 2 = long) */
1375 24, /* bitsize */
1376 FALSE, /* pc_relative */
1377 0, /* bitpos */
1378 complain_overflow_dont,/* complain_on_overflow */
1379 bfd_elf_generic_reloc, /* special_function */
1380 "R_ARM_TLS_CALL", /* name */
1381 FALSE, /* partial_inplace */
1382 0x00ffffff, /* src_mask */
1383 0x00ffffff, /* dst_mask */
1384 FALSE), /* pcrel_offset */
1385
1386 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1387 0, /* rightshift */
1388 2, /* size (0 = byte, 1 = short, 2 = long) */
1389 0, /* bitsize */
1390 FALSE, /* pc_relative */
1391 0, /* bitpos */
1392 complain_overflow_bitfield,/* complain_on_overflow */
1393 bfd_elf_generic_reloc, /* special_function */
1394 "R_ARM_TLS_DESCSEQ", /* name */
1395 FALSE, /* partial_inplace */
1396 0x00000000, /* src_mask */
1397 0x00000000, /* dst_mask */
1398 FALSE), /* pcrel_offset */
1399
1400 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1401 0, /* rightshift */
1402 2, /* size (0 = byte, 1 = short, 2 = long) */
1403 24, /* bitsize */
1404 FALSE, /* pc_relative */
1405 0, /* bitpos */
1406 complain_overflow_dont,/* complain_on_overflow */
1407 bfd_elf_generic_reloc, /* special_function */
1408 "R_ARM_THM_TLS_CALL", /* name */
1409 FALSE, /* partial_inplace */
1410 0x07ff07ff, /* src_mask */
1411 0x07ff07ff, /* dst_mask */
1412 FALSE), /* pcrel_offset */
c19d1205
ZW		 1413
1414 HOWTO (R_ARM_PLT32_ABS, /* type */
1415 0, /* rightshift */
1416 2, /* size (0 = byte, 1 = short, 2 = long) */
1417 32, /* bitsize */
1418 FALSE, /* pc_relative */
1419 0, /* bitpos */
1420 complain_overflow_dont,/* complain_on_overflow */
1421 bfd_elf_generic_reloc, /* special_function */
1422 "R_ARM_PLT32_ABS", /* name */
1423 FALSE, /* partial_inplace */
1424 0xffffffff, /* src_mask */
1425 0xffffffff, /* dst_mask */
1426 FALSE), /* pcrel_offset */
1427
1428 HOWTO (R_ARM_GOT_ABS, /* type */
1429 0, /* rightshift */
1430 2, /* size (0 = byte, 1 = short, 2 = long) */
1431 32, /* bitsize */
1432 FALSE, /* pc_relative */
1433 0, /* bitpos */
1434 complain_overflow_dont,/* complain_on_overflow */
1435 bfd_elf_generic_reloc, /* special_function */
1436 "R_ARM_GOT_ABS", /* name */
1437 FALSE, /* partial_inplace */
1438 0xffffffff, /* src_mask */
1439 0xffffffff, /* dst_mask */
1440 FALSE), /* pcrel_offset */
1441
1442 HOWTO (R_ARM_GOT_PREL, /* type */
1443 0, /* rightshift */
1444 2, /* size (0 = byte, 1 = short, 2 = long) */
1445 32, /* bitsize */
1446 TRUE, /* pc_relative */
1447 0, /* bitpos */
1448 complain_overflow_dont, /* complain_on_overflow */
1449 bfd_elf_generic_reloc, /* special_function */
1450 "R_ARM_GOT_PREL", /* name */
1451 FALSE, /* partial_inplace */
1452 0xffffffff, /* src_mask */
1453 0xffffffff, /* dst_mask */
1454 TRUE), /* pcrel_offset */
1455
1456 HOWTO (R_ARM_GOT_BREL12, /* type */
1457 0, /* rightshift */
1458 2, /* size (0 = byte, 1 = short, 2 = long) */
1459 12, /* bitsize */
1460 FALSE, /* pc_relative */
1461 0, /* bitpos */
1462 complain_overflow_bitfield,/* complain_on_overflow */
1463 bfd_elf_generic_reloc, /* special_function */
1464 "R_ARM_GOT_BREL12", /* name */
1465 FALSE, /* partial_inplace */
1466 0x00000fff, /* src_mask */
1467 0x00000fff, /* dst_mask */
1468 FALSE), /* pcrel_offset */
1469
1470 HOWTO (R_ARM_GOTOFF12, /* type */
1471 0, /* rightshift */
1472 2, /* size (0 = byte, 1 = short, 2 = long) */
1473 12, /* bitsize */
1474 FALSE, /* pc_relative */
1475 0, /* bitpos */
1476 complain_overflow_bitfield,/* complain_on_overflow */
1477 bfd_elf_generic_reloc, /* special_function */
1478 "R_ARM_GOTOFF12", /* name */
1479 FALSE, /* partial_inplace */
1480 0x00000fff, /* src_mask */
1481 0x00000fff, /* dst_mask */
1482 FALSE), /* pcrel_offset */
1483
07d6d2b8 1484 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1485
1486 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1487 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1488 0, /* rightshift */
1489 2, /* size (0 = byte, 1 = short, 2 = long) */
1490 0, /* bitsize */
1491 FALSE, /* pc_relative */
1492 0, /* bitpos */
99059e56 1493 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1494 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1495 "R_ARM_GNU_VTENTRY", /* name */
1496 FALSE, /* partial_inplace */
1497 0, /* src_mask */
1498 0, /* dst_mask */
1499 FALSE), /* pcrel_offset */
c19d1205
ZW		 1500
1501 /* GNU extension to record C++ vtable hierarchy */
1502 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1503 0, /* rightshift */
1504 2, /* size (0 = byte, 1 = short, 2 = long) */
1505 0, /* bitsize */
1506 FALSE, /* pc_relative */
1507 0, /* bitpos */
99059e56 1508 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1509 NULL, /* special_function */
99059e56 1510 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1511 FALSE, /* partial_inplace */
1512 0, /* src_mask */
1513 0, /* dst_mask */
1514 FALSE), /* pcrel_offset */
c19d1205
ZW		 1515
1516 HOWTO (R_ARM_THM_JUMP11, /* type */
1517 1, /* rightshift */
1518 1, /* size (0 = byte, 1 = short, 2 = long) */
1519 11, /* bitsize */
1520 TRUE, /* pc_relative */
1521 0, /* bitpos */
1522 complain_overflow_signed, /* complain_on_overflow */
1523 bfd_elf_generic_reloc, /* special_function */
1524 "R_ARM_THM_JUMP11", /* name */
1525 FALSE, /* partial_inplace */
1526 0x000007ff, /* src_mask */
1527 0x000007ff, /* dst_mask */
1528 TRUE), /* pcrel_offset */
1529
1530 HOWTO (R_ARM_THM_JUMP8, /* type */
1531 1, /* rightshift */
1532 1, /* size (0 = byte, 1 = short, 2 = long) */
1533 8, /* bitsize */
1534 TRUE, /* pc_relative */
1535 0, /* bitpos */
1536 complain_overflow_signed, /* complain_on_overflow */
1537 bfd_elf_generic_reloc, /* special_function */
1538 "R_ARM_THM_JUMP8", /* name */
1539 FALSE, /* partial_inplace */
1540 0x000000ff, /* src_mask */
1541 0x000000ff, /* dst_mask */
1542 TRUE), /* pcrel_offset */
ba93b8ac 1543
c19d1205
ZW		 1544 /* TLS relocations */
1545 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1546 0, /* rightshift */
1547 2, /* size (0 = byte, 1 = short, 2 = long) */
1548 32, /* bitsize */
1549 FALSE, /* pc_relative */
1550 0, /* bitpos */
99059e56
RM		 1551 complain_overflow_bitfield,/* complain_on_overflow */
1552 NULL, /* special_function */
1553 "R_ARM_TLS_GD32", /* name */
1554 TRUE, /* partial_inplace */
1555 0xffffffff, /* src_mask */
1556 0xffffffff, /* dst_mask */
07d6d2b8 1557 FALSE), /* pcrel_offset */
ba93b8ac 1558
ba93b8ac 1559 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1560 0, /* rightshift */
1561 2, /* size (0 = byte, 1 = short, 2 = long) */
1562 32, /* bitsize */
1563 FALSE, /* pc_relative */
1564 0, /* bitpos */
99059e56
RM		 1565 complain_overflow_bitfield,/* complain_on_overflow */
1566 bfd_elf_generic_reloc, /* special_function */
1567 "R_ARM_TLS_LDM32", /* name */
1568 TRUE, /* partial_inplace */
1569 0xffffffff, /* src_mask */
1570 0xffffffff, /* dst_mask */
07d6d2b8 1571 FALSE), /* pcrel_offset */
ba93b8ac 1572
c19d1205 1573 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1574 0, /* rightshift */
1575 2, /* size (0 = byte, 1 = short, 2 = long) */
1576 32, /* bitsize */
1577 FALSE, /* pc_relative */
1578 0, /* bitpos */
99059e56
RM		 1579 complain_overflow_bitfield,/* complain_on_overflow */
1580 bfd_elf_generic_reloc, /* special_function */
1581 "R_ARM_TLS_LDO32", /* name */
1582 TRUE, /* partial_inplace */
1583 0xffffffff, /* src_mask */
1584 0xffffffff, /* dst_mask */
07d6d2b8 1585 FALSE), /* pcrel_offset */
ba93b8ac 1586
ba93b8ac 1587 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1588 0, /* rightshift */
1589 2, /* size (0 = byte, 1 = short, 2 = long) */
1590 32, /* bitsize */
1591 FALSE, /* pc_relative */
1592 0, /* bitpos */
99059e56
RM		 1593 complain_overflow_bitfield,/* complain_on_overflow */
1594 NULL, /* special_function */
1595 "R_ARM_TLS_IE32", /* name */
1596 TRUE, /* partial_inplace */
1597 0xffffffff, /* src_mask */
1598 0xffffffff, /* dst_mask */
07d6d2b8 1599 FALSE), /* pcrel_offset */
7f266840 1600
c19d1205 1601 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1602 0, /* rightshift */
1603 2, /* size (0 = byte, 1 = short, 2 = long) */
1604 32, /* bitsize */
1605 FALSE, /* pc_relative */
1606 0, /* bitpos */
99059e56 1607 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1608 NULL, /* special_function */
99059e56
RM		 1609 "R_ARM_TLS_LE32", /* name */
1610 TRUE, /* partial_inplace */
1611 0xffffffff, /* src_mask */
1612 0xffffffff, /* dst_mask */
07d6d2b8 1613 FALSE), /* pcrel_offset */
7f266840 1614
c19d1205
ZW		 1615 HOWTO (R_ARM_TLS_LDO12, /* type */
1616 0, /* rightshift */
1617 2, /* size (0 = byte, 1 = short, 2 = long) */
1618 12, /* bitsize */
1619 FALSE, /* pc_relative */
7f266840 1620 0, /* bitpos */
c19d1205 1621 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1622 bfd_elf_generic_reloc, /* special_function */
c19d1205 1623 "R_ARM_TLS_LDO12", /* name */
7f266840 1624 FALSE, /* partial_inplace */
c19d1205
ZW		 1625 0x00000fff, /* src_mask */
1626 0x00000fff, /* dst_mask */
1627 FALSE), /* pcrel_offset */
7f266840 1628
c19d1205
ZW		 1629 HOWTO (R_ARM_TLS_LE12, /* type */
1630 0, /* rightshift */
1631 2, /* size (0 = byte, 1 = short, 2 = long) */
1632 12, /* bitsize */
1633 FALSE, /* pc_relative */
7f266840 1634 0, /* bitpos */
c19d1205 1635 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1636 bfd_elf_generic_reloc, /* special_function */
c19d1205 1637 "R_ARM_TLS_LE12", /* name */
7f266840 1638 FALSE, /* partial_inplace */
c19d1205
ZW		 1639 0x00000fff, /* src_mask */
1640 0x00000fff, /* dst_mask */
1641 FALSE), /* pcrel_offset */
7f266840 1642
c19d1205 1643 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1644 0, /* rightshift */
1645 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1646 12, /* bitsize */
1647 FALSE, /* pc_relative */
7f266840 1648 0, /* bitpos */
c19d1205 1649 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1650 bfd_elf_generic_reloc, /* special_function */
c19d1205 1651 "R_ARM_TLS_IE12GP", /* name */
7f266840 1652 FALSE, /* partial_inplace */
c19d1205
ZW		 1653 0x00000fff, /* src_mask */
1654 0x00000fff, /* dst_mask */
1655 FALSE), /* pcrel_offset */
0855e32b 1656
34e77a92 1657 /* 112-127 private relocations. */
0855e32b
NS		 1658 EMPTY_HOWTO (112),
1659 EMPTY_HOWTO (113),
1660 EMPTY_HOWTO (114),
1661 EMPTY_HOWTO (115),
1662 EMPTY_HOWTO (116),
1663 EMPTY_HOWTO (117),
1664 EMPTY_HOWTO (118),
1665 EMPTY_HOWTO (119),
1666 EMPTY_HOWTO (120),
1667 EMPTY_HOWTO (121),
1668 EMPTY_HOWTO (122),
1669 EMPTY_HOWTO (123),
1670 EMPTY_HOWTO (124),
1671 EMPTY_HOWTO (125),
1672 EMPTY_HOWTO (126),
1673 EMPTY_HOWTO (127),
34e77a92
RS		 1674
1675 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1676 EMPTY_HOWTO (128),
1677
1678 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1679 0, /* rightshift */
1680 1, /* size (0 = byte, 1 = short, 2 = long) */
1681 0, /* bitsize */
1682 FALSE, /* pc_relative */
1683 0, /* bitpos */
1684 complain_overflow_bitfield,/* complain_on_overflow */
1685 bfd_elf_generic_reloc, /* special_function */
1686 "R_ARM_THM_TLS_DESCSEQ",/* name */
1687 FALSE, /* partial_inplace */
1688 0x00000000, /* src_mask */
1689 0x00000000, /* dst_mask */
1690 FALSE), /* pcrel_offset */
72d98d16
MG		 1691 EMPTY_HOWTO (130),
1692 EMPTY_HOWTO (131),
1693 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1694 0, /* rightshift. */
1695 1, /* size (0 = byte, 1 = short, 2 = long). */
1696 16, /* bitsize. */
1697 FALSE, /* pc_relative. */
1698 0, /* bitpos. */
1699 complain_overflow_bitfield,/* complain_on_overflow. */
1700 bfd_elf_generic_reloc, /* special_function. */
1701 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1702 FALSE, /* partial_inplace. */
1703 0x00000000, /* src_mask. */
1704 0x00000000, /* dst_mask. */
1705 FALSE), /* pcrel_offset. */
1706 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1707 0, /* rightshift. */
1708 1, /* size (0 = byte, 1 = short, 2 = long). */
1709 16, /* bitsize. */
1710 FALSE, /* pc_relative. */
1711 0, /* bitpos. */
1712 complain_overflow_bitfield,/* complain_on_overflow. */
1713 bfd_elf_generic_reloc, /* special_function. */
1714 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1715 FALSE, /* partial_inplace. */
1716 0x00000000, /* src_mask. */
1717 0x00000000, /* dst_mask. */
1718 FALSE), /* pcrel_offset. */
1719 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1720 0, /* rightshift. */
1721 1, /* size (0 = byte, 1 = short, 2 = long). */
1722 16, /* bitsize. */
1723 FALSE, /* pc_relative. */
1724 0, /* bitpos. */
1725 complain_overflow_bitfield,/* complain_on_overflow. */
1726 bfd_elf_generic_reloc, /* special_function. */
1727 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1728 FALSE, /* partial_inplace. */
1729 0x00000000, /* src_mask. */
1730 0x00000000, /* dst_mask. */
1731 FALSE), /* pcrel_offset. */
1732 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1733 0, /* rightshift. */
1734 1, /* size (0 = byte, 1 = short, 2 = long). */
1735 16, /* bitsize. */
1736 FALSE, /* pc_relative. */
1737 0, /* bitpos. */
1738 complain_overflow_bitfield,/* complain_on_overflow. */
1739 bfd_elf_generic_reloc, /* special_function. */
1740 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1741 FALSE, /* partial_inplace. */
1742 0x00000000, /* src_mask. */
1743 0x00000000, /* dst_mask. */
1744 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1745 /* Relocations for Armv8.1-M Mainline. */
1746 HOWTO (R_ARM_THM_BF16, /* type. */
1747 0, /* rightshift. */
1748 1, /* size (0 = byte, 1 = short, 2 = long). */
1749 16, /* bitsize. */
1750 TRUE, /* pc_relative. */
1751 0, /* bitpos. */
1752 complain_overflow_dont,/* do not complain_on_overflow. */
1753 bfd_elf_generic_reloc, /* special_function. */
1754 "R_ARM_THM_BF16", /* name. */
1755 FALSE, /* partial_inplace. */
1756 0x001f0ffe, /* src_mask. */
1757 0x001f0ffe, /* dst_mask. */
1758 TRUE), /* pcrel_offset. */
1889da70
AV		 1759 HOWTO (R_ARM_THM_BF12, /* type. */
1760 0, /* rightshift. */
1761 1, /* size (0 = byte, 1 = short, 2 = long). */
1762 12, /* bitsize. */
1763 TRUE, /* pc_relative. */
1764 0, /* bitpos. */
1765 complain_overflow_dont,/* do not complain_on_overflow. */
1766 bfd_elf_generic_reloc, /* special_function. */
1767 "R_ARM_THM_BF12", /* name. */
1768 FALSE, /* partial_inplace. */
1769 0x00010ffe, /* src_mask. */
1770 0x00010ffe, /* dst_mask. */
1771 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1772 HOWTO (R_ARM_THM_BF18, /* type. */
1773 0, /* rightshift. */
1774 1, /* size (0 = byte, 1 = short, 2 = long). */
1775 18, /* bitsize. */
1776 TRUE, /* pc_relative. */
1777 0, /* bitpos. */
1778 complain_overflow_dont,/* do not complain_on_overflow. */
1779 bfd_elf_generic_reloc, /* special_function. */
1780 "R_ARM_THM_BF18", /* name. */
1781 FALSE, /* partial_inplace. */
1782 0x007f0ffe, /* src_mask. */
1783 0x007f0ffe, /* dst_mask. */
1784 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1785};
1786
34e77a92 1787/* 160 onwards: */
5c5a4843 1788static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1789{
1790 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1791 0, /* rightshift */
1792 2, /* size (0 = byte, 1 = short, 2 = long) */
1793 32, /* bitsize */
1794 FALSE, /* pc_relative */
1795 0, /* bitpos */
99059e56
RM		 1796 complain_overflow_bitfield,/* complain_on_overflow */
1797 bfd_elf_generic_reloc, /* special_function */
1798 "R_ARM_IRELATIVE", /* name */
1799 TRUE, /* partial_inplace */
1800 0xffffffff, /* src_mask */
1801 0xffffffff, /* dst_mask */
188fd7ae
CL		 1802 FALSE), /* pcrel_offset */
1803 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1804 0, /* rightshift */
1805 2, /* size (0 = byte, 1 = short, 2 = long) */
1806 32, /* bitsize */
1807 FALSE, /* pc_relative */
1808 0, /* bitpos */
1809 complain_overflow_bitfield,/* complain_on_overflow */
1810 bfd_elf_generic_reloc, /* special_function */
1811 "R_ARM_GOTFUNCDESC", /* name */
1812 FALSE, /* partial_inplace */
1813 0, /* src_mask */
1814 0xffffffff, /* dst_mask */
1815 FALSE), /* pcrel_offset */
1816 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1817 0, /* rightshift */
1818 2, /* size (0 = byte, 1 = short, 2 = long) */
1819 32, /* bitsize */
1820 FALSE, /* pc_relative */
1821 0, /* bitpos */
1822 complain_overflow_bitfield,/* complain_on_overflow */
1823 bfd_elf_generic_reloc, /* special_function */
1824 "R_ARM_GOTOFFFUNCDESC",/* name */
1825 FALSE, /* partial_inplace */
1826 0, /* src_mask */
1827 0xffffffff, /* dst_mask */
1828 FALSE), /* pcrel_offset */
1829 HOWTO (R_ARM_FUNCDESC, /* type */
1830 0, /* rightshift */
1831 2, /* size (0 = byte, 1 = short, 2 = long) */
1832 32, /* bitsize */
1833 FALSE, /* pc_relative */
1834 0, /* bitpos */
1835 complain_overflow_bitfield,/* complain_on_overflow */
1836 bfd_elf_generic_reloc, /* special_function */
1837 "R_ARM_FUNCDESC", /* name */
1838 FALSE, /* partial_inplace */
1839 0, /* src_mask */
1840 0xffffffff, /* dst_mask */
1841 FALSE), /* pcrel_offset */
1842 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1843 0, /* rightshift */
1844 2, /* size (0 = byte, 1 = short, 2 = long) */
1845 64, /* bitsize */
1846 FALSE, /* pc_relative */
1847 0, /* bitpos */
1848 complain_overflow_bitfield,/* complain_on_overflow */
1849 bfd_elf_generic_reloc, /* special_function */
1850 "R_ARM_FUNCDESC_VALUE",/* name */
1851 FALSE, /* partial_inplace */
1852 0, /* src_mask */
1853 0xffffffff, /* dst_mask */
1854 FALSE), /* pcrel_offset */
5c5a4843
CL		 1855 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1856 0, /* rightshift */
1857 2, /* size (0 = byte, 1 = short, 2 = long) */
1858 32, /* bitsize */
1859 FALSE, /* pc_relative */
1860 0, /* bitpos */
1861 complain_overflow_bitfield,/* complain_on_overflow */
1862 bfd_elf_generic_reloc, /* special_function */
1863 "R_ARM_TLS_GD32_FDPIC",/* name */
1864 FALSE, /* partial_inplace */
1865 0, /* src_mask */
1866 0xffffffff, /* dst_mask */
1867 FALSE), /* pcrel_offset */
1868 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1869 0, /* rightshift */
1870 2, /* size (0 = byte, 1 = short, 2 = long) */
1871 32, /* bitsize */
1872 FALSE, /* pc_relative */
1873 0, /* bitpos */
1874 complain_overflow_bitfield,/* complain_on_overflow */
1875 bfd_elf_generic_reloc, /* special_function */
1876 "R_ARM_TLS_LDM32_FDPIC",/* name */
1877 FALSE, /* partial_inplace */
1878 0, /* src_mask */
1879 0xffffffff, /* dst_mask */
1880 FALSE), /* pcrel_offset */
1881 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1882 0, /* rightshift */
1883 2, /* size (0 = byte, 1 = short, 2 = long) */
1884 32, /* bitsize */
1885 FALSE, /* pc_relative */
1886 0, /* bitpos */
1887 complain_overflow_bitfield,/* complain_on_overflow */
1888 bfd_elf_generic_reloc, /* special_function */
1889 "R_ARM_TLS_IE32_FDPIC",/* name */
1890 FALSE, /* partial_inplace */
1891 0, /* src_mask */
1892 0xffffffff, /* dst_mask */
1893 FALSE), /* pcrel_offset */
34e77a92 1894};
c19d1205 1895
34e77a92
RS		 1896/* 249-255 extended, currently unused, relocations: */
1897static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1898{
1899 HOWTO (R_ARM_RREL32, /* type */
1900 0, /* rightshift */
1901 0, /* size (0 = byte, 1 = short, 2 = long) */
1902 0, /* bitsize */
1903 FALSE, /* pc_relative */
1904 0, /* bitpos */
1905 complain_overflow_dont,/* complain_on_overflow */
1906 bfd_elf_generic_reloc, /* special_function */
1907 "R_ARM_RREL32", /* name */
1908 FALSE, /* partial_inplace */
1909 0, /* src_mask */
1910 0, /* dst_mask */
1911 FALSE), /* pcrel_offset */
1912
1913 HOWTO (R_ARM_RABS32, /* type */
1914 0, /* rightshift */
1915 0, /* size (0 = byte, 1 = short, 2 = long) */
1916 0, /* bitsize */
1917 FALSE, /* pc_relative */
1918 0, /* bitpos */
1919 complain_overflow_dont,/* complain_on_overflow */
1920 bfd_elf_generic_reloc, /* special_function */
1921 "R_ARM_RABS32", /* name */
1922 FALSE, /* partial_inplace */
1923 0, /* src_mask */
1924 0, /* dst_mask */
1925 FALSE), /* pcrel_offset */
1926
1927 HOWTO (R_ARM_RPC24, /* type */
1928 0, /* rightshift */
1929 0, /* size (0 = byte, 1 = short, 2 = long) */
1930 0, /* bitsize */
1931 FALSE, /* pc_relative */
1932 0, /* bitpos */
1933 complain_overflow_dont,/* complain_on_overflow */
1934 bfd_elf_generic_reloc, /* special_function */
1935 "R_ARM_RPC24", /* name */
1936 FALSE, /* partial_inplace */
1937 0, /* src_mask */
1938 0, /* dst_mask */
1939 FALSE), /* pcrel_offset */
1940
1941 HOWTO (R_ARM_RBASE, /* type */
1942 0, /* rightshift */
1943 0, /* size (0 = byte, 1 = short, 2 = long) */
1944 0, /* bitsize */
1945 FALSE, /* pc_relative */
1946 0, /* bitpos */
1947 complain_overflow_dont,/* complain_on_overflow */
1948 bfd_elf_generic_reloc, /* special_function */
1949 "R_ARM_RBASE", /* name */
1950 FALSE, /* partial_inplace */
1951 0, /* src_mask */
1952 0, /* dst_mask */
1953 FALSE) /* pcrel_offset */
1954};
1955
1956static reloc_howto_type *
1957elf32_arm_howto_from_type (unsigned int r_type)
1958{
906e58ca 1959 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1960 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1961
188fd7ae
CL		 1962 if (r_type >= R_ARM_IRELATIVE
1963 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1964 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1965
c19d1205 1966 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1967 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1968 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1969
c19d1205 1970 return NULL;
7f266840
DJ		 1971}
1972
f3185997
NC		 1973static bfd_boolean
1974elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1975 Elf_Internal_Rela * elf_reloc)
1976{
1977 unsigned int r_type;
1978
1979 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1980 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1981 {
1982 /* xgettext:c-format */
1983 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1984 abfd, r_type);
1985 bfd_set_error (bfd_error_bad_value);
1986 return FALSE;
1987 }
1988 return TRUE;
7f266840
DJ		 1989}
1990
1991struct elf32_arm_reloc_map
1992 {
1993 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1994 unsigned char elf_reloc_val;
7f266840
DJ		 1995 };
1996
1997/* All entries in this list must also be present in elf32_arm_howto_table. */
1998static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1999 {
07d6d2b8 2000 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2001 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2002 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2003 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2004 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2005 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2006 {BFD_RELOC_32, R_ARM_ABS32},
2007 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2008 {BFD_RELOC_8, R_ARM_ABS8},
2009 {BFD_RELOC_16, R_ARM_ABS16},
2010 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2011 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2012 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2013 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2014 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2018 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2019 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2020 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2021 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2022 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2023 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2024 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2025 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2026 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2027 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2028 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2029 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2030 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2031 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2032 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2033 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2034 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2035 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2038 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2039 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2040 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2041 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2042 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2043 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2044 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2045 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2046 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2047 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2048 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2049 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2050 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2051 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2052 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2053 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2054 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2055 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2056 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2057 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2058 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2059 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2060 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2061 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2062 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2064 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2065 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2066 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2068 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2069 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2070 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2071 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2072 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2073 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2074 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2075 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2076 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2077 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2078 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2079 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2080 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2082 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2083 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2084 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2085 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2086 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2087 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2088 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2089 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2090 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2091 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2092 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2093 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2094 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2097 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2098 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2100 };
2101
2102static reloc_howto_type *
f1c71a59
ZW		 2103elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2104 bfd_reloc_code_real_type code)
7f266840
DJ		 2105{
2106 unsigned int i;
8029a119 2107
906e58ca 2108 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2109 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2110 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2111
c19d1205 2112 return NULL;
7f266840
DJ		 2113}
2114
157090f7
AM		 2115static reloc_howto_type *
2116elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2117 const char *r_name)
2118{
2119 unsigned int i;
2120
906e58ca 2121 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2122 if (elf32_arm_howto_table_1[i].name != NULL
2123 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2124 return &elf32_arm_howto_table_1[i];
2125
906e58ca 2126 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2127 if (elf32_arm_howto_table_2[i].name != NULL
2128 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2129 return &elf32_arm_howto_table_2[i];
2130
34e77a92
RS		 2131 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2132 if (elf32_arm_howto_table_3[i].name != NULL
2133 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2134 return &elf32_arm_howto_table_3[i];
2135
157090f7
AM		 2136 return NULL;
2137}
2138
906e58ca
NC		 2139/* Support for core dump NOTE sections. */
2140
7f266840 2141static bfd_boolean
f1c71a59 2142elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2143{
2144 int offset;
2145 size_t size;
2146
2147 switch (note->descsz)
2148 {
2149 default:
2150 return FALSE;
2151
8029a119 2152 case 148: /* Linux/ARM 32-bit. */
7f266840 2153 /* pr_cursig */
228e534f 2154 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2155
2156 /* pr_pid */
228e534f 2157 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2158
2159 /* pr_reg */
2160 offset = 72;
2161 size = 72;
2162
2163 break;
2164 }
2165
2166 /* Make a ".reg/999" section. */
2167 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2168 size, note->descpos + offset);
2169}
2170
2171static bfd_boolean
f1c71a59 2172elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2173{
2174 switch (note->descsz)
2175 {
2176 default:
2177 return FALSE;
2178
8029a119 2179 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2180 elf_tdata (abfd)->core->pid
4395ee08 2181 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2182 elf_tdata (abfd)->core->program
7f266840 2183 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2184 elf_tdata (abfd)->core->command
7f266840
DJ		 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2186 }
2187
2188 /* Note that for some reason, a spurious space is tacked
2189 onto the end of the args in some (at least one anyway)
2190 implementations, so strip it off if it exists. */
7f266840 2191 {
228e534f 2192 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2193 int n = strlen (command);
2194
2195 if (0 < n && command[n - 1] == ' ')
2196 command[n - 1] = '\0';
2197 }
2198
2199 return TRUE;
2200}
2201
1f20dca5
UW		 2202static char *
2203elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2204 int note_type, ...)
2205{
2206 switch (note_type)
2207 {
2208 default:
2209 return NULL;
2210
2211 case NT_PRPSINFO:
2212 {
602f1657 2213 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2214 va_list ap;
2215
2216 va_start (ap, note_type);
2217 memset (data, 0, sizeof (data));
2218 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2219#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2220 DIAGNOSTIC_PUSH;
be3e27bb 2221 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2222 -Wstringop-truncation:
2223 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2224 */
95da9854
L		 2225 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2226#endif
1f20dca5 2227 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2228#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2229 DIAGNOSTIC_POP;
fe75810f 2230#endif
1f20dca5
UW		 2231 va_end (ap);
2232
2233 return elfcore_write_note (abfd, buf, bufsiz,
2234 "CORE", note_type, data, sizeof (data));
2235 }
2236
2237 case NT_PRSTATUS:
2238 {
2239 char data[148];
2240 va_list ap;
2241 long pid;
2242 int cursig;
2243 const void *greg;
2244
2245 va_start (ap, note_type);
2246 memset (data, 0, sizeof (data));
2247 pid = va_arg (ap, long);
2248 bfd_put_32 (abfd, pid, data + 24);
2249 cursig = va_arg (ap, int);
2250 bfd_put_16 (abfd, cursig, data + 12);
2251 greg = va_arg (ap, const void *);
2252 memcpy (data + 72, greg, 72);
2253 va_end (ap);
2254
2255 return elfcore_write_note (abfd, buf, bufsiz,
2256 "CORE", note_type, data, sizeof (data));
2257 }
2258 }
2259}
2260
07d6d2b8
AM		 2261#define TARGET_LITTLE_SYM arm_elf32_le_vec
2262#define TARGET_LITTLE_NAME "elf32-littlearm"
2263#define TARGET_BIG_SYM arm_elf32_be_vec
2264#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2265
2266#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2267#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2268#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2269
252b5132
RH		 2270typedef unsigned long int insn32;
2271typedef unsigned short int insn16;
2272
3a4a14e9
PB		 2273/* In lieu of proper flags, assume all EABIv4 or later objects are
2274 interworkable. */
57e8b36a 2275#define INTERWORK_FLAG(abfd) \
3a4a14e9 2276 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2277 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2278 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2279
252b5132
RH		 2280/* The linker script knows the section names for placement.
2281 The entry_names are used to do simple name mangling on the stubs.
2282 Given a function name, and its type, the stub can be found. The
9b485d32 2283 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2284#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2285#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2286
2287#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2288#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2289
c7b8f16e
JB		 2290#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2291#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2292
a504d23a
LA		 2293#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2294#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2295
845b51d6
PB		 2296#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2297#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2298
7413f23f
DJ		 2299#define STUB_ENTRY_NAME "__%s_veneer"
2300
4ba2ef8f
TP		 2301#define CMSE_PREFIX "__acle_se_"
2302
4d83e8d9
CL		 2303#define CMSE_STUB_NAME ".gnu.sgstubs"
2304
252b5132
RH		 2305/* The name of the dynamic interpreter. This is put in the .interp
2306 section. */
2307#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2308
cb10292c
CL		 2309/* FDPIC default stack size. */
2310#define DEFAULT_STACK_SIZE 0x8000
2311
0855e32b 2312static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2313{
2314 0xe08e0000, /* add r0, lr, r0 */
2315 0xe5901004, /* ldr r1, [r0,#4] */
2316 0xe12fff11, /* bx r1 */
2317};
0855e32b
NS		 2318
2319static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2320{
2321 0xe52d2004, /* push {r2} */
2322 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2323 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2324 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2325 0xe081100f, /* 2: add r1, pc */
2326 0xe12fff12, /* bx r2 */
2327 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2328 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2329 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2330};
0855e32b 2331
b4e87f2c
TC		 2332/* NOTE: [Thumb nop sequence]
2333 When adding code that transitions from Thumb to Arm the instruction that
2334 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2335 a nop for performance reasons. */
2336
7801f98f
CL		 2337/* ARM FDPIC PLT entry. */
2338/* The last 5 words contain PLT lazy fragment code and data. */
2339static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2340 {
2341 0xe59fc008, /* ldr r12, .L1 */
2342 0xe08cc009, /* add r12, r12, r9 */
2343 0xe59c9004, /* ldr r9, [r12, #4] */
2344 0xe59cf000, /* ldr pc, [r12] */
2345 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2346 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2347 0xe51fc00c, /* ldr r12, [pc, #-12] */
2348 0xe92d1000, /* push {r12} */
2349 0xe599c004, /* ldr r12, [r9, #4] */
2350 0xe599f000, /* ldr pc, [r9] */
2351 };
2352
59029f57
CL		 2353/* Thumb FDPIC PLT entry. */
2354/* The last 5 words contain PLT lazy fragment code and data. */
2355static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2356 {
2357 0xc00cf8df, /* ldr.w r12, .L1 */
2358 0x0c09eb0c, /* add.w r12, r12, r9 */
2359 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2360 0xf000f8dc, /* ldr.w pc, [r12] */
2361 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2362 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2363 0xc008f85f, /* ldr.w r12, .L2 */
2364 0xcd04f84d, /* push {r12} */
2365 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2366 0xf000f8d9, /* ldr.w pc, [r9] */
2367 };
2368
5e681ec4
PB		 2369#ifdef FOUR_WORD_PLT
2370
252b5132
RH		 2371/* The first entry in a procedure linkage table looks like
2372 this. It is set up so that any shared library function that is
59f2c4e7 2373 called before the relocation has been set up calls the dynamic
9b485d32 2374 linker first. */
e5a52504 2375static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2376{
2377 0xe52de004, /* str lr, [sp, #-4]! */
2378 0xe59fe010, /* ldr lr, [pc, #16] */
2379 0xe08fe00e, /* add lr, pc, lr */
2380 0xe5bef008, /* ldr pc, [lr, #8]! */
2381};
5e681ec4
PB		 2382
2383/* Subsequent entries in a procedure linkage table look like
2384 this. */
e5a52504 2385static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2386{
2387 0xe28fc600, /* add ip, pc, #NN */
2388 0xe28cca00, /* add ip, ip, #NN */
2389 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2390 0x00000000, /* unused */
2391};
5e681ec4 2392
eed94f8f 2393#else /* not FOUR_WORD_PLT */
5e681ec4 2394
5e681ec4
PB		 2395/* The first entry in a procedure linkage table looks like
2396 this. It is set up so that any shared library function that is
2397 called before the relocation has been set up calls the dynamic
2398 linker first. */
e5a52504 2399static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2400{
07d6d2b8
AM		 2401 0xe52de004, /* str lr, [sp, #-4]! */
2402 0xe59fe004, /* ldr lr, [pc, #4] */
2403 0xe08fe00e, /* add lr, pc, lr */
2404 0xe5bef008, /* ldr pc, [lr, #8]! */
2405 0x00000000, /* &GOT[0] - . */
b38cadfb 2406};
252b5132 2407
1db37fe6
YG		 2408/* By default subsequent entries in a procedure linkage table look like
2409 this. Offsets that don't fit into 28 bits will cause link error. */
2410static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2411{
2412 0xe28fc600, /* add ip, pc, #0xNN00000 */
2413 0xe28cca00, /* add ip, ip, #0xNN000 */
2414 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2415};
5e681ec4 2416
1db37fe6
YG		 2417/* When explicitly asked, we'll use this "long" entry format
2418 which can cope with arbitrary displacements. */
2419static const bfd_vma elf32_arm_plt_entry_long [] =
2420{
07d6d2b8
AM		 2421 0xe28fc200, /* add ip, pc, #0xN0000000 */
2422 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2423 0xe28cca00, /* add ip, ip, #0xNN000 */
2424 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2425};
2426
2427static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2428
eed94f8f
NC		 2429#endif /* not FOUR_WORD_PLT */
2430
2431/* The first entry in a procedure linkage table looks like this.
2432 It is set up so that any shared library function that is called before the
2433 relocation has been set up calls the dynamic linker first. */
2434static const bfd_vma elf32_thumb2_plt0_entry [] =
2435{
2436 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2437 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2438 0xf8dfb500, /* push {lr} */
2439 0x44fee008, /* ldr.w lr, [pc, #8] */
2440 /* add lr, pc */
eed94f8f 2441 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2442 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2443};
2444
2445/* Subsequent entries in a procedure linkage table for thumb only target
2446 look like this. */
2447static const bfd_vma elf32_thumb2_plt_entry [] =
2448{
2449 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2450 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2451 0x0c00f240, /* movw ip, #0xNNNN */
2452 0x0c00f2c0, /* movt ip, #0xNNNN */
2453 0xf8dc44fc, /* add ip, pc */
b4e87f2c
TC		 2454 0xe7fdf000 /* ldr.w pc, [ip] */
2455 /* b .-2 */
eed94f8f 2456};
252b5132 2457
00a97672
RS		 2458/* The format of the first entry in the procedure linkage table
2459 for a VxWorks executable. */
2460static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2461{
07d6d2b8
AM		 2462 0xe52dc008, /* str ip,[sp,#-8]! */
2463 0xe59fc000, /* ldr ip,[pc] */
2464 0xe59cf008, /* ldr pc,[ip,#8] */
2465 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2466};
00a97672
RS		 2467
2468/* The format of subsequent entries in a VxWorks executable. */
2469static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2470{
07d6d2b8
AM		 2471 0xe59fc000, /* ldr ip,[pc] */
2472 0xe59cf000, /* ldr pc,[ip] */
2473 0x00000000, /* .long @got */
2474 0xe59fc000, /* ldr ip,[pc] */
2475 0xea000000, /* b _PLT */
2476 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2477};
00a97672
RS		 2478
2479/* The format of entries in a VxWorks shared library. */
2480static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2481{
07d6d2b8
AM		 2482 0xe59fc000, /* ldr ip,[pc] */
2483 0xe79cf009, /* ldr pc,[ip,r9] */
2484 0x00000000, /* .long @got */
2485 0xe59fc000, /* ldr ip,[pc] */
2486 0xe599f008, /* ldr pc,[r9,#8] */
2487 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2488};
00a97672 2489
b7693d02
DJ		 2490/* An initial stub used if the PLT entry is referenced from Thumb code. */
2491#define PLT_THUMB_STUB_SIZE 4
2492static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2493{
2494 0x4778, /* bx pc */
b4e87f2c 2495 0xe7fd /* b .-2 */
b38cadfb 2496};
b7693d02 2497
e5a52504
MM		 2498/* The entries in a PLT when using a DLL-based target with multiple
2499 address spaces. */
906e58ca 2500static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2501{
07d6d2b8
AM		 2502 0xe51ff004, /* ldr pc, [pc, #-4] */
2503 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2504};
2505
2506/* The first entry in a procedure linkage table looks like
2507 this. It is set up so that any shared library function that is
2508 called before the relocation has been set up calls the dynamic
2509 linker first. */
2510static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2511{
2512 /* First bundle: */
2513 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2514 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2515 0xe08cc00f, /* add ip, ip, pc */
2516 0xe52dc008, /* str ip, [sp, #-8]! */
2517 /* Second bundle: */
edccdf7c
RM		 2518 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2519 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2520 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2521 0xe12fff1c, /* bx ip */
b38cadfb 2522 /* Third bundle: */
edccdf7c
RM		 2523 0xe320f000, /* nop */
2524 0xe320f000, /* nop */
2525 0xe320f000, /* nop */
b38cadfb
NC		 2526 /* .Lplt_tail: */
2527 0xe50dc004, /* str ip, [sp, #-4] */
2528 /* Fourth bundle: */
edccdf7c
RM		 2529 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2530 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2531 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2532 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2533};
2534#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2535
2536/* Subsequent entries in a procedure linkage table look like this. */
2537static const bfd_vma elf32_arm_nacl_plt_entry [] =
2538{
2539 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2540 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2541 0xe08cc00f, /* add ip, ip, pc */
2542 0xea000000, /* b .Lplt_tail */
2543};
e5a52504 2544
906e58ca
NC		 2545#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2546#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2547#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2548#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2549#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2550#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2551#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2552#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2553
461a49ca 2554enum stub_insn_type
b38cadfb
NC		 2555{
2556 THUMB16_TYPE = 1,
2557 THUMB32_TYPE,
2558 ARM_TYPE,
2559 DATA_TYPE
2560};
461a49ca 2561
48229727
JB		 2562#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2563/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2564 is inserted in arm_build_one_stub(). */
2565#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2566#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2567#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2568#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2569#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2570#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2571#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2572#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2573
2574typedef struct
2575{
07d6d2b8 2576 bfd_vma data;
b38cadfb 2577 enum stub_insn_type type;
07d6d2b8
AM		 2578 unsigned int r_type;
2579 int reloc_addend;
461a49ca
DJ		 2580} insn_sequence;
2581
b4e87f2c
TC		 2582/* See note [Thumb nop sequence] when adding a veneer. */
2583
fea2b4d6
CL		 2584/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2585 to reach the stub if necessary. */
461a49ca 2586static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2587{
07d6d2b8 2588 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2589 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2590};
906e58ca 2591
fea2b4d6
CL		 2592/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2593 available. */
461a49ca 2594static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2595{
07d6d2b8
AM		 2596 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2597 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2598 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2599};
906e58ca 2600
d3626fb0 2601/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2602static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2603{
07d6d2b8
AM		 2604 THUMB16_INSN (0xb401), /* push {r0} */
2605 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2606 THUMB16_INSN (0x4684), /* mov ip, r0 */
2607 THUMB16_INSN (0xbc01), /* pop {r0} */
2608 THUMB16_INSN (0x4760), /* bx ip */
2609 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2610 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2611};
906e58ca 2612
80c135e5
TP		 2613/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2614static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2615{
07d6d2b8 2616 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2617 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2618};
2619
d5a67c02
AV		 2620/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2621 M-profile architectures. */
2622static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2623{
2624 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2625 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2626 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2627};
2628
d3626fb0
CL		 2629/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2630 allowed. */
2631static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2632{
07d6d2b8 2633 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2634 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2635 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2636 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2637 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2638};
d3626fb0 2639
fea2b4d6
CL		 2640/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2641 available. */
461a49ca 2642static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2643{
07d6d2b8 2644 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2645 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2646 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2647 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2648};
906e58ca 2649
fea2b4d6
CL		 2650/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2651 one, when the destination is close enough. */
461a49ca 2652static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2653{
07d6d2b8 2654 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2655 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2656 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2657};
c820be07 2658
cf3eccff 2659/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2660 blx to reach the stub if necessary. */
cf3eccff 2661static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2662{
07d6d2b8
AM		 2663 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2664 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2665 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2666};
906e58ca 2667
cf3eccff
DJ		 2668/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2669 blx to reach the stub if necessary. We can not add into pc;
2670 it is not guaranteed to mode switch (different in ARMv6 and
2671 ARMv7). */
2672static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2673{
07d6d2b8
AM		 2674 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2675 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2676 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2677 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2678};
cf3eccff 2679
ebe24dd4
CL		 2680/* V4T ARM -> ARM long branch stub, PIC. */
2681static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2682{
07d6d2b8
AM		 2683 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2684 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2685 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2686 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2687};
ebe24dd4
CL		 2688
2689/* V4T Thumb -> ARM long branch stub, PIC. */
2690static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2691{
07d6d2b8 2692 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2693 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2694 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2695 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2696 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2697};
ebe24dd4 2698
d3626fb0
CL		 2699/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2700 architectures. */
ebe24dd4 2701static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2702{
07d6d2b8
AM		 2703 THUMB16_INSN (0xb401), /* push {r0} */
2704 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2705 THUMB16_INSN (0x46fc), /* mov ip, pc */
2706 THUMB16_INSN (0x4484), /* add ip, r0 */
2707 THUMB16_INSN (0xbc01), /* pop {r0} */
2708 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2709 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2710};
ebe24dd4 2711
d3626fb0
CL		 2712/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2713 allowed. */
2714static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2715{
07d6d2b8 2716 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2717 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2718 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2719 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2720 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2721 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2722};
d3626fb0 2723
0855e32b
NS		 2724/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2725 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2726static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2727{
07d6d2b8
AM		 2728 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2729 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2730 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2731};
2732
2733/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2734 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2735static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2736{
07d6d2b8 2737 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2738 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2739 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2740 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2741 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2742};
2743
7a89b94e
NC		 2744/* NaCl ARM -> ARM long branch stub. */
2745static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2746{
2747 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2748 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2749 ARM_INSN (0xe12fff1c), /* bx ip */
2750 ARM_INSN (0xe320f000), /* nop */
2751 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2752 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2753 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2754 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2755};
2756
2757/* NaCl ARM -> ARM long branch stub, PIC. */
2758static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2759{
2760 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2761 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2762 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2763 ARM_INSN (0xe12fff1c), /* bx ip */
2764 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2765 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2766 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2767 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2768};
2769
4ba2ef8f
TP		 2770/* Stub used for transition to secure state (aka SG veneer). */
2771static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2772{
2773 THUMB32_INSN (0xe97fe97f), /* sg. */
2774 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2775};
2776
7a89b94e 2777
48229727
JB		 2778/* Cortex-A8 erratum-workaround stubs. */
2779
2780/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2781 can't use a conditional branch to reach this stub). */
2782
2783static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2784{
07d6d2b8 2785 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2786 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2787 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2788};
48229727
JB		 2789
2790/* Stub used for b.w and bl.w instructions. */
2791
2792static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2793{
2794 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2795};
48229727
JB		 2796
2797static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2798{
2799 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2800};
48229727
JB		 2801
2802/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2803 instruction (which switches to ARM mode) to point to this stub. Jump to the
2804 real destination using an ARM-mode branch. */
2805
2806static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2807{
2808 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2809};
48229727 2810
9553db3c
NC		 2811/* For each section group there can be a specially created linker section
2812 to hold the stubs for that group. The name of the stub section is based
2813 upon the name of another section within that group with the suffix below
2814 applied.
2815
2816 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2817 create what appeared to be a linker stub section when it actually
2818 contained user code/data. For example, consider this fragment:
b38cadfb 2819
9553db3c
NC		 2820 const char * stubborn_problems[] = { "np" };
2821
2822 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2823 section called:
2824
2825 .data.rel.local.stubborn_problems
2826
2827 This then causes problems in arm32_arm_build_stubs() as it triggers:
2828
2829 // Ignore non-stub sections.
2830 if (!strstr (stub_sec->name, STUB_SUFFIX))
2831 continue;
2832
2833 And so the section would be ignored instead of being processed. Hence
2834 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2835 C identifier. */
2836#define STUB_SUFFIX ".__stub"
906e58ca 2837
738a79f6
CL		 2838/* One entry per long/short branch stub defined above. */
2839#define DEF_STUBS \
2840 DEF_STUB(long_branch_any_any) \
2841 DEF_STUB(long_branch_v4t_arm_thumb) \
2842 DEF_STUB(long_branch_thumb_only) \
2843 DEF_STUB(long_branch_v4t_thumb_thumb) \
2844 DEF_STUB(long_branch_v4t_thumb_arm) \
2845 DEF_STUB(short_branch_v4t_thumb_arm) \
2846 DEF_STUB(long_branch_any_arm_pic) \
2847 DEF_STUB(long_branch_any_thumb_pic) \
2848 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2849 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2851 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2852 DEF_STUB(long_branch_any_tls_pic) \
2853 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2854 DEF_STUB(long_branch_arm_nacl) \
2855 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2856 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2857 DEF_STUB(a8_veneer_b_cond) \
2858 DEF_STUB(a8_veneer_b) \
2859 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2860 DEF_STUB(a8_veneer_blx) \
2861 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2862 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2863
2864#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2865enum elf32_arm_stub_type
2866{
906e58ca 2867 arm_stub_none,
738a79f6 2868 DEF_STUBS
4f4faa4d 2869 max_stub_type
738a79f6
CL		 2870};
2871#undef DEF_STUB
2872
8d9d9490
TP		 2873/* Note the first a8_veneer type. */
2874const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2875
738a79f6
CL		 2876typedef struct
2877{
d3ce72d0 2878 const insn_sequence* template_sequence;
738a79f6
CL		 2879 int template_size;
2880} stub_def;
2881
2882#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2883static const stub_def stub_definitions[] =
2884{
738a79f6
CL		 2885 {NULL, 0},
2886 DEF_STUBS
906e58ca
NC		 2887};
2888
2889struct elf32_arm_stub_hash_entry
2890{
2891 /* Base hash table entry structure. */
2892 struct bfd_hash_entry root;
2893
2894 /* The stub section. */
2895 asection *stub_sec;
2896
2897 /* Offset within stub_sec of the beginning of this stub. */
2898 bfd_vma stub_offset;
2899
2900 /* Given the symbol's value and its section we can determine its final
2901 value when building the stubs (so the stub knows where to jump). */
2902 bfd_vma target_value;
2903 asection *target_section;
2904
8d9d9490
TP		 2905 /* Same as above but for the source of the branch to the stub. Used for
2906 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2907 such, source section does not need to be recorded since Cortex-A8 erratum
2908 workaround stubs are only generated when both source and target are in the
2909 same section. */
2910 bfd_vma source_value;
48229727
JB		 2911
2912 /* The instruction which caused this stub to be generated (only valid for
2913 Cortex-A8 erratum workaround stubs at present). */
2914 unsigned long orig_insn;
2915
461a49ca 2916 /* The stub type. */
906e58ca 2917 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2918 /* Its encoding size in bytes. */
2919 int stub_size;
2920 /* Its template. */
2921 const insn_sequence *stub_template;
2922 /* The size of the template (number of entries). */
2923 int stub_template_size;
906e58ca
NC		 2924
2925 /* The symbol table entry, if any, that this was derived from. */
2926 struct elf32_arm_link_hash_entry *h;
2927
35fc36a8
RS		 2928 /* Type of branch. */
2929 enum arm_st_branch_type branch_type;
906e58ca
NC		 2930
2931 /* Where this stub is being called from, or, in the case of combined
2932 stub sections, the first input section in the group. */
2933 asection *id_sec;
7413f23f
DJ		 2934
2935 /* The name for the local symbol at the start of this stub. The
2936 stub name in the hash table has to be unique; this does not, so
2937 it can be friendlier. */
2938 char *output_name;
906e58ca
NC		 2939};
2940
e489d0ae
PB		 2941/* Used to build a map of a section. This is required for mixed-endian
2942 code/data. */
2943
2944typedef struct elf32_elf_section_map
2945{
2946 bfd_vma vma;
2947 char type;
2948}
2949elf32_arm_section_map;
2950
c7b8f16e
JB		 2951/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2952
2953typedef enum
2954{
2955 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2956 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2957 VFP11_ERRATUM_ARM_VENEER,
2958 VFP11_ERRATUM_THUMB_VENEER
2959}
2960elf32_vfp11_erratum_type;
2961
2962typedef struct elf32_vfp11_erratum_list
2963{
2964 struct elf32_vfp11_erratum_list *next;
2965 bfd_vma vma;
2966 union
2967 {
2968 struct
2969 {
2970 struct elf32_vfp11_erratum_list *veneer;
2971 unsigned int vfp_insn;
2972 } b;
2973 struct
2974 {
2975 struct elf32_vfp11_erratum_list *branch;
2976 unsigned int id;
2977 } v;
2978 } u;
2979 elf32_vfp11_erratum_type type;
2980}
2981elf32_vfp11_erratum_list;
2982
a504d23a
LA		 2983/* Information about a STM32L4XX erratum veneer, or a branch to such a
2984 veneer. */
2985typedef enum
2986{
2987 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2988 STM32L4XX_ERRATUM_VENEER
2989}
2990elf32_stm32l4xx_erratum_type;
2991
2992typedef struct elf32_stm32l4xx_erratum_list
2993{
2994 struct elf32_stm32l4xx_erratum_list *next;
2995 bfd_vma vma;
2996 union
2997 {
2998 struct
2999 {
3000 struct elf32_stm32l4xx_erratum_list *veneer;
3001 unsigned int insn;
3002 } b;
3003 struct
3004 {
3005 struct elf32_stm32l4xx_erratum_list *branch;
3006 unsigned int id;
3007 } v;
3008 } u;
3009 elf32_stm32l4xx_erratum_type type;
3010}
3011elf32_stm32l4xx_erratum_list;
3012
2468f9c9
PB		 3013typedef enum
3014{
3015 DELETE_EXIDX_ENTRY,
3016 INSERT_EXIDX_CANTUNWIND_AT_END
3017}
3018arm_unwind_edit_type;
3019
3020/* A (sorted) list of edits to apply to an unwind table. */
3021typedef struct arm_unwind_table_edit
3022{
3023 arm_unwind_edit_type type;
3024 /* Note: we sometimes want to insert an unwind entry corresponding to a
3025 section different from the one we're currently writing out, so record the
3026 (text) section this edit relates to here. */
3027 asection *linked_section;
3028 unsigned int index;
3029 struct arm_unwind_table_edit *next;
3030}
3031arm_unwind_table_edit;
3032
8e3de13a 3033typedef struct _arm_elf_section_data
e489d0ae 3034{
2468f9c9 3035 /* Information about mapping symbols. */
e489d0ae 3036 struct bfd_elf_section_data elf;
8e3de13a 3037 unsigned int mapcount;
c7b8f16e 3038 unsigned int mapsize;
e489d0ae 3039 elf32_arm_section_map *map;
2468f9c9 3040 /* Information about CPU errata. */
c7b8f16e
JB		 3041 unsigned int erratumcount;
3042 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3043 unsigned int stm32l4xx_erratumcount;
3044 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3045 unsigned int additional_reloc_count;
2468f9c9
PB		 3046 /* Information about unwind tables. */
3047 union
3048 {
3049 /* Unwind info attached to a text section. */
3050 struct
3051 {
3052 asection *arm_exidx_sec;
3053 } text;
3054
3055 /* Unwind info attached to an .ARM.exidx section. */
3056 struct
3057 {
3058 arm_unwind_table_edit *unwind_edit_list;
3059 arm_unwind_table_edit *unwind_edit_tail;
3060 } exidx;
3061 } u;
8e3de13a
NC		 3062}
3063_arm_elf_section_data;
e489d0ae
PB		 3064
3065#define elf32_arm_section_data(sec) \
8e3de13a 3066 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3067
48229727
JB		 3068/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3069 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3070 so may be created multiple times: we use an array of these entries whilst
3071 relaxing which we can refresh easily, then create stubs for each potentially
3072 erratum-triggering instruction once we've settled on a solution. */
3073
b38cadfb
NC		 3074struct a8_erratum_fix
3075{
48229727
JB		 3076 bfd *input_bfd;
3077 asection *section;
3078 bfd_vma offset;
8d9d9490 3079 bfd_vma target_offset;
48229727
JB		 3080 unsigned long orig_insn;
3081 char *stub_name;
3082 enum elf32_arm_stub_type stub_type;
35fc36a8 3083 enum arm_st_branch_type branch_type;
48229727
JB		 3084};
3085
3086/* A table of relocs applied to branches which might trigger Cortex-A8
3087 erratum. */
3088
b38cadfb
NC		 3089struct a8_erratum_reloc
3090{
48229727
JB		 3091 bfd_vma from;
3092 bfd_vma destination;
92750f34
DJ		 3093 struct elf32_arm_link_hash_entry *hash;
3094 const char *sym_name;
48229727 3095 unsigned int r_type;
35fc36a8 3096 enum arm_st_branch_type branch_type;
48229727
JB		 3097 bfd_boolean non_a8_stub;
3098};
3099
ba93b8ac
DJ		 3100/* The size of the thread control block. */
3101#define TCB_SIZE 8
3102
34e77a92
RS		 3103/* ARM-specific information about a PLT entry, over and above the usual
3104 gotplt_union. */
b38cadfb
NC		 3105struct arm_plt_info
3106{
34e77a92
RS		 3107 /* We reference count Thumb references to a PLT entry separately,
3108 so that we can emit the Thumb trampoline only if needed. */
3109 bfd_signed_vma thumb_refcount;
3110
3111 /* Some references from Thumb code may be eliminated by BL->BLX
3112 conversion, so record them separately. */
3113 bfd_signed_vma maybe_thumb_refcount;
3114
3115 /* How many of the recorded PLT accesses were from non-call relocations.
3116 This information is useful when deciding whether anything takes the
3117 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3118 non-call references to the function should resolve directly to the
3119 real runtime target. */
3120 unsigned int noncall_refcount;
3121
3122 /* Since PLT entries have variable size if the Thumb prologue is
3123 used, we need to record the index into .got.plt instead of
3124 recomputing it from the PLT offset. */
3125 bfd_signed_vma got_offset;
3126};
3127
3128/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3129struct arm_local_iplt_info
3130{
34e77a92
RS		 3131 /* The information that is usually found in the generic ELF part of
3132 the hash table entry. */
3133 union gotplt_union root;
3134
3135 /* The information that is usually found in the ARM-specific part of
3136 the hash table entry. */
3137 struct arm_plt_info arm;
3138
3139 /* A list of all potential dynamic relocations against this symbol. */
3140 struct elf_dyn_relocs *dyn_relocs;
3141};
3142
e8b09b87
CL		 3143/* Structure to handle FDPIC support for local functions. */
3144struct fdpic_local {
3145 unsigned int funcdesc_cnt;
3146 unsigned int gotofffuncdesc_cnt;
3147 int funcdesc_offset;
3148};
3149
0ffa91dd 3150struct elf_arm_obj_tdata
ba93b8ac
DJ		 3151{
3152 struct elf_obj_tdata root;
3153
3154 /* tls_type for each local got entry. */
3155 char *local_got_tls_type;
ee065d83 3156
0855e32b
NS		 3157 /* GOTPLT entries for TLS descriptors. */
3158 bfd_vma *local_tlsdesc_gotent;
3159
34e77a92
RS		 3160 /* Information for local symbols that need entries in .iplt. */
3161 struct arm_local_iplt_info **local_iplt;
3162
bf21ed78
MS		 3163 /* Zero to warn when linking objects with incompatible enum sizes. */
3164 int no_enum_size_warning;
a9dc9481
JM		 3165
3166 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3167 int no_wchar_size_warning;
e8b09b87
CL		 3168
3169 /* Maintains FDPIC counters and funcdesc info. */
3170 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3171};
3172
0ffa91dd
NC		 3173#define elf_arm_tdata(bfd) \
3174 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3175
0ffa91dd
NC		 3176#define elf32_arm_local_got_tls_type(bfd) \
3177 (elf_arm_tdata (bfd)->local_got_tls_type)
3178
0855e32b
NS		 3179#define elf32_arm_local_tlsdesc_gotent(bfd) \
3180 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3181
34e77a92
RS		 3182#define elf32_arm_local_iplt(bfd) \
3183 (elf_arm_tdata (bfd)->local_iplt)
3184
e8b09b87
CL		 3185#define elf32_arm_local_fdpic_cnts(bfd) \
3186 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3187
0ffa91dd
NC		 3188#define is_arm_elf(bfd) \
3189 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3190 && elf_tdata (bfd) != NULL \
4dfe6ac6 3191 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3192
3193static bfd_boolean
3194elf32_arm_mkobject (bfd *abfd)
3195{
0ffa91dd 3196 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3197 ARM_ELF_DATA);
ba93b8ac
DJ		 3198}
3199
ba93b8ac
DJ		 3200#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3201
e8b09b87
CL		 3202/* Structure to handle FDPIC support for extern functions. */
3203struct fdpic_global {
3204 unsigned int gotofffuncdesc_cnt;
3205 unsigned int gotfuncdesc_cnt;
3206 unsigned int funcdesc_cnt;
3207 int funcdesc_offset;
3208 int gotfuncdesc_offset;
3209};
3210
ba96a88f 3211/* Arm ELF linker hash entry. */
252b5132 3212struct elf32_arm_link_hash_entry
b38cadfb
NC		 3213{
3214 struct elf_link_hash_entry root;
252b5132 3215
b38cadfb
NC		 3216 /* Track dynamic relocs copied for this symbol. */
3217 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3218
b38cadfb
NC		 3219 /* ARM-specific PLT information. */
3220 struct arm_plt_info plt;
ba93b8ac
DJ		 3221
3222#define GOT_UNKNOWN 0
3223#define GOT_NORMAL 1
3224#define GOT_TLS_GD 2
3225#define GOT_TLS_IE 4
0855e32b
NS		 3226#define GOT_TLS_GDESC 8
3227#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3228 unsigned int tls_type : 8;
34e77a92 3229
b38cadfb
NC		 3230 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3231 unsigned int is_iplt : 1;
34e77a92 3232
b38cadfb 3233 unsigned int unused : 23;
a4fd1a8e 3234
b38cadfb
NC		 3235 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3236 starting at the end of the jump table. */
3237 bfd_vma tlsdesc_got;
0855e32b 3238
b38cadfb
NC		 3239 /* The symbol marking the real symbol location for exported thumb
3240 symbols with Arm stubs. */
3241 struct elf_link_hash_entry *export_glue;
906e58ca 3242
b38cadfb 3243 /* A pointer to the most recently used stub hash entry against this
8029a119 3244 symbol. */
b38cadfb 3245 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3246
3247 /* Counter for FDPIC relocations against this symbol. */
3248 struct fdpic_global fdpic_cnts;
b38cadfb 3249};
252b5132 3250
252b5132 3251/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3252#define elf32_arm_link_hash_traverse(table, func, info) \
3253 (elf_link_hash_traverse \
3254 (&(table)->root, \
b7693d02 3255 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3256 (info)))
3257
3258/* Get the ARM elf linker hash table from a link_info structure. */
3259#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3260 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3261 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3262
906e58ca
NC		 3263#define arm_stub_hash_lookup(table, string, create, copy) \
3264 ((struct elf32_arm_stub_hash_entry *) \
3265 bfd_hash_lookup ((table), (string), (create), (copy)))
3266
21d799b5
NC		 3267/* Array to keep track of which stub sections have been created, and
3268 information on stub grouping. */
3269struct map_stub
3270{
3271 /* This is the section to which stubs in the group will be
3272 attached. */
3273 asection *link_sec;
3274 /* The stub section. */
3275 asection *stub_sec;
3276};
3277
0855e32b
NS		 3278#define elf32_arm_compute_jump_table_size(htab) \
3279 ((htab)->next_tls_desc_index * 4)
3280
9b485d32 3281/* ARM ELF linker hash table. */
252b5132 3282struct elf32_arm_link_hash_table
906e58ca
NC		 3283{
3284 /* The main hash table. */
3285 struct elf_link_hash_table root;
252b5132 3286
906e58ca
NC		 3287 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3288 bfd_size_type thumb_glue_size;
252b5132 3289
906e58ca
NC		 3290 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3291 bfd_size_type arm_glue_size;
252b5132 3292
906e58ca
NC		 3293 /* The size in bytes of section containing the ARMv4 BX veneers. */
3294 bfd_size_type bx_glue_size;
845b51d6 3295
906e58ca
NC		 3296 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3297 veneer has been populated. */
3298 bfd_vma bx_glue_offset[15];
845b51d6 3299
906e58ca
NC		 3300 /* The size in bytes of the section containing glue for VFP11 erratum
3301 veneers. */
3302 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3303
a504d23a
LA		 3304 /* The size in bytes of the section containing glue for STM32L4XX erratum
3305 veneers. */
3306 bfd_size_type stm32l4xx_erratum_glue_size;
3307
48229727
JB		 3308 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3309 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3310 elf32_arm_write_section(). */
3311 struct a8_erratum_fix *a8_erratum_fixes;
3312 unsigned int num_a8_erratum_fixes;
3313
906e58ca
NC		 3314 /* An arbitrary input BFD chosen to hold the glue sections. */
3315 bfd * bfd_of_glue_owner;
ba96a88f 3316
906e58ca
NC		 3317 /* Nonzero to output a BE8 image. */
3318 int byteswap_code;
e489d0ae 3319
906e58ca
NC		 3320 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3321 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3322 int target1_is_rel;
9c504268 3323
906e58ca
NC		 3324 /* The relocation to use for R_ARM_TARGET2 relocations. */
3325 int target2_reloc;
eb043451 3326
906e58ca
NC		 3327 /* 0 = Ignore R_ARM_V4BX.
3328 1 = Convert BX to MOV PC.
3329 2 = Generate v4 interworing stubs. */
3330 int fix_v4bx;
319850b4 3331
48229727
JB		 3332 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3333 int fix_cortex_a8;
3334
2de70689
MGD		 3335 /* Whether we should fix the ARM1176 BLX immediate issue. */
3336 int fix_arm1176;
3337
906e58ca
NC		 3338 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3339 int use_blx;
33bfe774 3340
906e58ca
NC		 3341 /* What sort of code sequences we should look for which may trigger the
3342 VFP11 denorm erratum. */
3343 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3344
906e58ca
NC		 3345 /* Global counter for the number of fixes we have emitted. */
3346 int num_vfp11_fixes;
c7b8f16e 3347
a504d23a
LA		 3348 /* What sort of code sequences we should look for which may trigger the
3349 STM32L4XX erratum. */
3350 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3351
3352 /* Global counter for the number of fixes we have emitted. */
3353 int num_stm32l4xx_fixes;
3354
906e58ca
NC		 3355 /* Nonzero to force PIC branch veneers. */
3356 int pic_veneer;
27e55c4d 3357
906e58ca
NC		 3358 /* The number of bytes in the initial entry in the PLT. */
3359 bfd_size_type plt_header_size;
e5a52504 3360
906e58ca
NC		 3361 /* The number of bytes in the subsequent PLT etries. */
3362 bfd_size_type plt_entry_size;
e5a52504 3363
906e58ca
NC		 3364 /* True if the target system is VxWorks. */
3365 int vxworks_p;
00a97672 3366
906e58ca
NC		 3367 /* True if the target system is Symbian OS. */
3368 int symbian_p;
e5a52504 3369
b38cadfb
NC		 3370 /* True if the target system is Native Client. */
3371 int nacl_p;
3372
906e58ca 3373 /* True if the target uses REL relocations. */
f3185997 3374 bfd_boolean use_rel;
4e7fd91e 3375
54ddd295
TP		 3376 /* Nonzero if import library must be a secure gateway import library
3377 as per ARMv8-M Security Extensions. */
3378 int cmse_implib;
3379
0955507f
TP		 3380 /* The import library whose symbols' address must remain stable in
3381 the import library generated. */
3382 bfd *in_implib_bfd;
3383
0855e32b
NS		 3384 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3385 bfd_vma next_tls_desc_index;
3386
3387 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3388 bfd_vma num_tls_desc;
3389
906e58ca
NC		 3390 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3391 asection *srelplt2;
00a97672 3392
0855e32b
NS		 3393 /* The offset into splt of the PLT entry for the TLS descriptor
3394 resolver. Special values are 0, if not necessary (or not found
3395 to be necessary yet), and -1 if needed but not determined
3396 yet. */
3397 bfd_vma dt_tlsdesc_plt;
3398
3399 /* The offset into sgot of the GOT entry used by the PLT entry
3400 above. */
b38cadfb 3401 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3402
3403 /* Offset in .plt section of tls_arm_trampoline. */
3404 bfd_vma tls_trampoline;
3405
5c5a4843 3406 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3407 union
3408 {
3409 bfd_signed_vma refcount;
3410 bfd_vma offset;
3411 } tls_ldm_got;
b7693d02 3412
87d72d41
AM		 3413 /* Small local sym cache. */
3414 struct sym_cache sym_cache;
906e58ca
NC		 3415
3416 /* For convenience in allocate_dynrelocs. */
3417 bfd * obfd;
3418
0855e32b
NS		 3419 /* The amount of space used by the reserved portion of the sgotplt
3420 section, plus whatever space is used by the jump slots. */
3421 bfd_vma sgotplt_jump_table_size;
3422
906e58ca
NC		 3423 /* The stub hash table. */
3424 struct bfd_hash_table stub_hash_table;
3425
3426 /* Linker stub bfd. */
3427 bfd *stub_bfd;
3428
3429 /* Linker call-backs. */
6bde4c52
TP		 3430 asection * (*add_stub_section) (const char *, asection *, asection *,
3431 unsigned int);
906e58ca
NC		 3432 void (*layout_sections_again) (void);
3433
3434 /* Array to keep track of which stub sections have been created, and
3435 information on stub grouping. */
21d799b5 3436 struct map_stub *stub_group;
906e58ca 3437
4ba2ef8f
TP		 3438 /* Input stub section holding secure gateway veneers. */
3439 asection *cmse_stub_sec;
3440
0955507f
TP		 3441 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3442 start to be allocated. */
3443 bfd_vma new_cmse_stub_offset;
3444
fe33d2fa 3445 /* Number of elements in stub_group. */
7292b3ac 3446 unsigned int top_id;
fe33d2fa 3447
906e58ca
NC		 3448 /* Assorted information used by elf32_arm_size_stubs. */
3449 unsigned int bfd_count;
7292b3ac 3450 unsigned int top_index;
906e58ca 3451 asection **input_list;
617a5ada
CL		 3452
3453 /* True if the target system uses FDPIC. */
3454 int fdpic_p;
e8b09b87
CL		 3455
3456 /* Fixup section. Used for FDPIC. */
3457 asection *srofixup;
906e58ca 3458};
252b5132 3459
e8b09b87
CL		 3460/* Add an FDPIC read-only fixup. */
3461static void
3462arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3463{
3464 bfd_vma fixup_offset;
3465
3466 fixup_offset = srofixup->reloc_count++ * 4;
3467 BFD_ASSERT (fixup_offset < srofixup->size);
3468 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3469}
3470
a504d23a
LA		 3471static inline int
3472ctz (unsigned int mask)
3473{
3474#if GCC_VERSION >= 3004
3475 return __builtin_ctz (mask);
3476#else
3477 unsigned int i;
3478
3479 for (i = 0; i < 8 * sizeof (mask); i++)
3480 {
3481 if (mask & 0x1)
3482 break;
3483 mask = (mask >> 1);
3484 }
3485 return i;
3486#endif
3487}
3488
3489static inline int
b25e998d 3490elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3491{
3492#if GCC_VERSION >= 3004
3493 return __builtin_popcount (mask);
3494#else
b25e998d
CG		 3495 unsigned int i;
3496 int sum = 0;
a504d23a
LA		 3497
3498 for (i = 0; i < 8 * sizeof (mask); i++)
3499 {
3500 if (mask & 0x1)
3501 sum++;
3502 mask = (mask >> 1);
3503 }
3504 return sum;
3505#endif
3506}
3507
e8b09b87
CL		 3508static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3509 asection *sreloc, Elf_Internal_Rela *rel);
3510
3511static void
3512arm_elf_fill_funcdesc(bfd *output_bfd,
3513 struct bfd_link_info *info,
3514 int *funcdesc_offset,
3515 int dynindx,
3516 int offset,
3517 bfd_vma addr,
3518 bfd_vma dynreloc_value,
3519 bfd_vma seg)
3520{
3521 if ((*funcdesc_offset & 1) == 0)
3522 {
3523 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3524 asection *sgot = globals->root.sgot;
3525
3526 if (bfd_link_pic(info))
3527 {
3528 asection *srelgot = globals->root.srelgot;
3529 Elf_Internal_Rela outrel;
3530
3531 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3532 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3533 outrel.r_addend = 0;
3534
3535 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3536 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3537 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3538 }
3539 else
3540 {
3541 struct elf_link_hash_entry *hgot = globals->root.hgot;
3542 bfd_vma got_value = hgot->root.u.def.value
3543 + hgot->root.u.def.section->output_section->vma
3544 + hgot->root.u.def.section->output_offset;
3545
3546 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3547 sgot->output_section->vma + sgot->output_offset
3548 + offset);
3549 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3550 sgot->output_section->vma + sgot->output_offset
3551 + offset + 4);
3552 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3553 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3554 }
3555 *funcdesc_offset |= 1;
3556 }
3557}
3558
780a67af
NC		 3559/* Create an entry in an ARM ELF linker hash table. */
3560
3561static struct bfd_hash_entry *
57e8b36a 3562elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3563 struct bfd_hash_table * table,
3564 const char * string)
780a67af
NC		 3565{
3566 struct elf32_arm_link_hash_entry * ret =
3567 (struct elf32_arm_link_hash_entry *) entry;
3568
3569 /* Allocate the structure if it has not already been allocated by a
3570 subclass. */
906e58ca 3571 if (ret == NULL)
21d799b5 3572 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3573 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3574 if (ret == NULL)
780a67af
NC		 3575 return (struct bfd_hash_entry *) ret;
3576
3577 /* Call the allocation method of the superclass. */
3578 ret = ((struct elf32_arm_link_hash_entry *)
3579 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3580 table, string));
57e8b36a 3581 if (ret != NULL)
b7693d02 3582 {
0bdcacaf 3583 ret->dyn_relocs = NULL;
ba93b8ac 3584 ret->tls_type = GOT_UNKNOWN;
0855e32b 3585 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3586 ret->plt.thumb_refcount = 0;
3587 ret->plt.maybe_thumb_refcount = 0;
3588 ret->plt.noncall_refcount = 0;
3589 ret->plt.got_offset = -1;
3590 ret->is_iplt = FALSE;
a4fd1a8e 3591 ret->export_glue = NULL;
906e58ca
NC		 3592
3593 ret->stub_cache = NULL;
e8b09b87
CL		 3594
3595 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3596 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3597 ret->fdpic_cnts.funcdesc_cnt = 0;
3598 ret->fdpic_cnts.funcdesc_offset = -1;
3599 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3600 }
780a67af
NC		 3601
3602 return (struct bfd_hash_entry *) ret;
3603}
3604
34e77a92
RS		 3605/* Ensure that we have allocated bookkeeping structures for ABFD's local
3606 symbols. */
3607
3608static bfd_boolean
3609elf32_arm_allocate_local_sym_info (bfd *abfd)
3610{
3611 if (elf_local_got_refcounts (abfd) == NULL)
3612 {
3613 bfd_size_type num_syms;
3614 bfd_size_type size;
3615 char *data;
3616
3617 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3618 size = num_syms * (sizeof (bfd_signed_vma)
3619 + sizeof (struct arm_local_iplt_info *)
3620 + sizeof (bfd_vma)
e8b09b87
CL		 3621 + sizeof (char)
3622 + sizeof (struct fdpic_local));
34e77a92
RS		 3623 data = bfd_zalloc (abfd, size);
3624 if (data == NULL)
3625 return FALSE;
3626
e8b09b87
CL		 3627 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3628 data += num_syms * sizeof (struct fdpic_local);
3629
34e77a92
RS		 3630 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3631 data += num_syms * sizeof (bfd_signed_vma);
3632
3633 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3634 data += num_syms * sizeof (struct arm_local_iplt_info *);
3635
3636 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3637 data += num_syms * sizeof (bfd_vma);
3638
3639 elf32_arm_local_got_tls_type (abfd) = data;
3640 }
3641 return TRUE;
3642}
3643
3644/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3645 to input bfd ABFD. Create the information if it doesn't already exist.
3646 Return null if an allocation fails. */
3647
3648static struct arm_local_iplt_info *
3649elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3650{
3651 struct arm_local_iplt_info **ptr;
3652
3653 if (!elf32_arm_allocate_local_sym_info (abfd))
3654 return NULL;
3655
3656 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3657 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3658 if (*ptr == NULL)
3659 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3660 return *ptr;
3661}
3662
3663/* Try to obtain PLT information for the symbol with index R_SYMNDX
3664 in ABFD's symbol table. If the symbol is global, H points to its
3665 hash table entry, otherwise H is null.
3666
3667 Return true if the symbol does have PLT information. When returning
3668 true, point *ROOT_PLT at the target-independent reference count/offset
3669 union and *ARM_PLT at the ARM-specific information. */
3670
3671static bfd_boolean
4ba2ef8f
TP		 3672elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3673 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3674 unsigned long r_symndx, union gotplt_union **root_plt,
3675 struct arm_plt_info **arm_plt)
3676{
3677 struct arm_local_iplt_info *local_iplt;
3678
4ba2ef8f
TP		 3679 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3680 return FALSE;
3681
34e77a92
RS		 3682 if (h != NULL)
3683 {
3684 *root_plt = &h->root.plt;
3685 *arm_plt = &h->plt;
3686 return TRUE;
3687 }
3688
3689 if (elf32_arm_local_iplt (abfd) == NULL)
3690 return FALSE;
3691
3692 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3693 if (local_iplt == NULL)
3694 return FALSE;
3695
3696 *root_plt = &local_iplt->root;
3697 *arm_plt = &local_iplt->arm;
3698 return TRUE;
3699}
3700
59029f57
CL		 3701static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3702
34e77a92
RS		 3703/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3704 before it. */
3705
3706static bfd_boolean
3707elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3708 struct arm_plt_info *arm_plt)
3709{
3710 struct elf32_arm_link_hash_table *htab;
3711
3712 htab = elf32_arm_hash_table (info);
59029f57
CL		 3713
3714 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3715 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3716}
3717
3718/* Return a pointer to the head of the dynamic reloc list that should
3719 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3720 ABFD's symbol table. Return null if an error occurs. */
3721
3722static struct elf_dyn_relocs **
3723elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3724 Elf_Internal_Sym *isym)
3725{
3726 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3727 {
3728 struct arm_local_iplt_info *local_iplt;
3729
3730 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3731 if (local_iplt == NULL)
3732 return NULL;
3733 return &local_iplt->dyn_relocs;
3734 }
3735 else
3736 {
3737 /* Track dynamic relocs needed for local syms too.
3738 We really need local syms available to do this
3739 easily. Oh well. */
3740 asection *s;
3741 void *vpp;
3742
3743 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3744 if (s == NULL)
3745 abort ();
3746
3747 vpp = &elf_section_data (s)->local_dynrel;
3748 return (struct elf_dyn_relocs **) vpp;
3749 }
3750}
3751
906e58ca
NC		 3752/* Initialize an entry in the stub hash table. */
3753
3754static struct bfd_hash_entry *
3755stub_hash_newfunc (struct bfd_hash_entry *entry,
3756 struct bfd_hash_table *table,
3757 const char *string)
3758{
3759 /* Allocate the structure if it has not already been allocated by a
3760 subclass. */
3761 if (entry == NULL)
3762 {
21d799b5 3763 entry = (struct bfd_hash_entry *)
99059e56 3764 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3765 if (entry == NULL)
3766 return entry;
3767 }
3768
3769 /* Call the allocation method of the superclass. */
3770 entry = bfd_hash_newfunc (entry, table, string);
3771 if (entry != NULL)
3772 {
3773 struct elf32_arm_stub_hash_entry *eh;
3774
3775 /* Initialize the local fields. */
3776 eh = (struct elf32_arm_stub_hash_entry *) entry;
3777 eh->stub_sec = NULL;
0955507f 3778 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3779 eh->source_value = 0;
906e58ca
NC		 3780 eh->target_value = 0;
3781 eh->target_section = NULL;
cedfb179 3782 eh->orig_insn = 0;
906e58ca 3783 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3784 eh->stub_size = 0;
3785 eh->stub_template = NULL;
0955507f 3786 eh->stub_template_size = -1;
906e58ca
NC		 3787 eh->h = NULL;
3788 eh->id_sec = NULL;
d8d2f433 3789 eh->output_name = NULL;
906e58ca
NC		 3790 }
3791
3792 return entry;
3793}
3794
00a97672 3795/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3796 shortcuts to them in our hash table. */
3797
3798static bfd_boolean
57e8b36a 3799create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3800{
3801 struct elf32_arm_link_hash_table *htab;
3802
e5a52504 3803 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3804 if (htab == NULL)
3805 return FALSE;
3806
e5a52504
MM		 3807 /* BPABI objects never have a GOT, or associated sections. */
3808 if (htab->symbian_p)
3809 return TRUE;
3810
5e681ec4
PB		 3811 if (! _bfd_elf_create_got_section (dynobj, info))
3812 return FALSE;
3813
e8b09b87
CL		 3814 /* Also create .rofixup. */
3815 if (htab->fdpic_p)
3816 {
3817 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3818 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3819 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
3820 if (htab->srofixup == NULL || ! bfd_set_section_alignment (dynobj, htab->srofixup, 2))
3821 return FALSE;
3822 }
3823
5e681ec4
PB		 3824 return TRUE;
3825}
3826
34e77a92
RS		 3827/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3828
3829static bfd_boolean
3830create_ifunc_sections (struct bfd_link_info *info)
3831{
3832 struct elf32_arm_link_hash_table *htab;
3833 const struct elf_backend_data *bed;
3834 bfd *dynobj;
3835 asection *s;
3836 flagword flags;
b38cadfb 3837
34e77a92
RS		 3838 htab = elf32_arm_hash_table (info);
3839 dynobj = htab->root.dynobj;
3840 bed = get_elf_backend_data (dynobj);
3841 flags = bed->dynamic_sec_flags;
3842
3843 if (htab->root.iplt == NULL)
3844 {
3d4d4302
AM		 3845 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3846 flags | SEC_READONLY | SEC_CODE);
34e77a92 3847 if (s == NULL
a0f49396 3848 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3849 return FALSE;
3850 htab->root.iplt = s;
3851 }
3852
3853 if (htab->root.irelplt == NULL)
3854 {
3d4d4302
AM		 3855 s = bfd_make_section_anyway_with_flags (dynobj,
3856 RELOC_SECTION (htab, ".iplt"),
3857 flags | SEC_READONLY);
34e77a92 3858 if (s == NULL
a0f49396 3859 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3860 return FALSE;
3861 htab->root.irelplt = s;
3862 }
3863
3864 if (htab->root.igotplt == NULL)
3865 {
3d4d4302 3866 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3867 if (s == NULL
3868 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3869 return FALSE;
3870 htab->root.igotplt = s;
3871 }
3872 return TRUE;
3873}
3874
eed94f8f
NC		 3875/* Determine if we're dealing with a Thumb only architecture. */
3876
3877static bfd_boolean
3878using_thumb_only (struct elf32_arm_link_hash_table *globals)
3879{
2fd158eb
TP		 3880 int arch;
3881 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3882 Tag_CPU_arch_profile);
eed94f8f 3883
2fd158eb
TP		 3884 if (profile)
3885 return profile == 'M';
eed94f8f 3886
2fd158eb 3887 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3888
60a019a0 3889 /* Force return logic to be reviewed for each new architecture. */
031254f2 3890 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3891
2fd158eb
TP		 3892 if (arch == TAG_CPU_ARCH_V6_M
3893 || arch == TAG_CPU_ARCH_V6S_M
3894 || arch == TAG_CPU_ARCH_V7E_M
3895 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3896 || arch == TAG_CPU_ARCH_V8M_MAIN
3897 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3898 return TRUE;
eed94f8f 3899
2fd158eb 3900 return FALSE;
eed94f8f
NC		 3901}
3902
3903/* Determine if we're dealing with a Thumb-2 object. */
3904
3905static bfd_boolean
3906using_thumb2 (struct elf32_arm_link_hash_table *globals)
3907{
60a019a0
TP		 3908 int arch;
3909 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3910 Tag_THUMB_ISA_use);
3911
3912 if (thumb_isa)
3913 return thumb_isa == 2;
3914
3915 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3916
3917 /* Force return logic to be reviewed for each new architecture. */
031254f2 3918 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3919
3920 return (arch == TAG_CPU_ARCH_V6T2
3921 || arch == TAG_CPU_ARCH_V7
3922 || arch == TAG_CPU_ARCH_V7E_M
3923 || arch == TAG_CPU_ARCH_V8
bff0500d 3924 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3925 || arch == TAG_CPU_ARCH_V8M_MAIN
3926 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3927}
3928
5e866f5a
TP		 3929/* Determine whether Thumb-2 BL instruction is available. */
3930
3931static bfd_boolean
3932using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3933{
3934 int arch =
3935 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3936
3937 /* Force return logic to be reviewed for each new architecture. */
031254f2 3938 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3939
3940 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3941 return (arch == TAG_CPU_ARCH_V6T2
3942 || arch >= TAG_CPU_ARCH_V7);
3943}
3944
00a97672
RS		 3945/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3946 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3947 hash table. */
3948
3949static bfd_boolean
57e8b36a 3950elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3951{
3952 struct elf32_arm_link_hash_table *htab;
3953
3954 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3955 if (htab == NULL)
3956 return FALSE;
3957
362d30a1 3958 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3959 return FALSE;
3960
3961 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3962 return FALSE;
3963
00a97672
RS		 3964 if (htab->vxworks_p)
3965 {
3966 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3967 return FALSE;
3968
0e1862bb 3969 if (bfd_link_pic (info))
00a97672
RS		 3970 {
3971 htab->plt_header_size = 0;
3972 htab->plt_entry_size
3973 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3974 }
3975 else
3976 {
3977 htab->plt_header_size
3978 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3979 htab->plt_entry_size
3980 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3981 }
aebf9be7
NC		 3982
3983 if (elf_elfheader (dynobj))
3984 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3985 }
eed94f8f
NC		 3986 else
3987 {
3988 /* PR ld/16017
3989 Test for thumb only architectures. Note - we cannot just call
3990 using_thumb_only() as the attributes in the output bfd have not been
3991 initialised at this point, so instead we use the input bfd. */
3992 bfd * saved_obfd = htab->obfd;
3993
3994 htab->obfd = dynobj;
3995 if (using_thumb_only (htab))
3996 {
3997 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3998 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3999 }
4000 htab->obfd = saved_obfd;
4001 }
5e681ec4 4002
7801f98f
CL		 4003 if (htab->fdpic_p) {
4004 htab->plt_header_size = 0;
4005 if (info->flags & DF_BIND_NOW)
4006 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
4007 else
4008 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
4009 }
4010
362d30a1
RS		 4011 if (!htab->root.splt
4012 || !htab->root.srelplt
9d19e4fd
AM		 4013 || !htab->root.sdynbss
4014 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 4015 abort ();
4016
4017 return TRUE;
4018}
4019
906e58ca
NC		 4020/* Copy the extra info we tack onto an elf_link_hash_entry. */
4021
4022static void
4023elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4024 struct elf_link_hash_entry *dir,
4025 struct elf_link_hash_entry *ind)
4026{
4027 struct elf32_arm_link_hash_entry *edir, *eind;
4028
4029 edir = (struct elf32_arm_link_hash_entry *) dir;
4030 eind = (struct elf32_arm_link_hash_entry *) ind;
4031
0bdcacaf 4032 if (eind->dyn_relocs != NULL)
906e58ca 4033 {
0bdcacaf 4034 if (edir->dyn_relocs != NULL)
906e58ca 4035 {
0bdcacaf
RS		 4036 struct elf_dyn_relocs **pp;
4037 struct elf_dyn_relocs *p;
906e58ca
NC		 4038
4039 /* Add reloc counts against the indirect sym to the direct sym
4040 list. Merge any entries against the same section. */
0bdcacaf 4041 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 4042 {
0bdcacaf 4043 struct elf_dyn_relocs *q;
906e58ca 4044
0bdcacaf
RS		 4045 for (q = edir->dyn_relocs; q != NULL; q = q->next)
4046 if (q->sec == p->sec)
906e58ca
NC		 4047 {
4048 q->pc_count += p->pc_count;
4049 q->count += p->count;
4050 *pp = p->next;
4051 break;
4052 }
4053 if (q == NULL)
4054 pp = &p->next;
4055 }
0bdcacaf 4056 *pp = edir->dyn_relocs;
906e58ca
NC		 4057 }
4058
0bdcacaf
RS		 4059 edir->dyn_relocs = eind->dyn_relocs;
4060 eind->dyn_relocs = NULL;
906e58ca
NC		 4061 }
4062
4063 if (ind->root.type == bfd_link_hash_indirect)
4064 {
4065 /* Copy over PLT info. */
34e77a92
RS		 4066 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4067 eind->plt.thumb_refcount = 0;
4068 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4069 eind->plt.maybe_thumb_refcount = 0;
4070 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4071 eind->plt.noncall_refcount = 0;
4072
e8b09b87
CL		 4073 /* Copy FDPIC counters. */
4074 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4075 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4076 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4077
34e77a92
RS		 4078 /* We should only allocate a function to .iplt once the final
4079 symbol information is known. */
4080 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4081
4082 if (dir->got.refcount <= 0)
4083 {
4084 edir->tls_type = eind->tls_type;
4085 eind->tls_type = GOT_UNKNOWN;
4086 }
4087 }
4088
4089 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4090}
4091
68faa637
AM		 4092/* Destroy an ARM elf linker hash table. */
4093
4094static void
d495ab0d 4095elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4096{
4097 struct elf32_arm_link_hash_table *ret
d495ab0d 4098 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4099
4100 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4101 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4102}
4103
906e58ca
NC		 4104/* Create an ARM elf linker hash table. */
4105
4106static struct bfd_link_hash_table *
4107elf32_arm_link_hash_table_create (bfd *abfd)
4108{
4109 struct elf32_arm_link_hash_table *ret;
4110 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4111
7bf52ea2 4112 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4113 if (ret == NULL)
4114 return NULL;
4115
4116 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4117 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4118 sizeof (struct elf32_arm_link_hash_entry),
4119 ARM_ELF_DATA))
906e58ca
NC		 4120 {
4121 free (ret);
4122 return NULL;
4123 }
4124
906e58ca 4125 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4126 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4127#ifdef FOUR_WORD_PLT
4128 ret->plt_header_size = 16;
4129 ret->plt_entry_size = 16;
4130#else
4131 ret->plt_header_size = 20;
1db37fe6 4132 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4133#endif
f3185997 4134 ret->use_rel = TRUE;
906e58ca 4135 ret->obfd = abfd;
617a5ada 4136 ret->fdpic_p = 0;
906e58ca
NC		 4137
4138 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4139 sizeof (struct elf32_arm_stub_hash_entry)))
4140 {
d495ab0d 4141 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4142 return NULL;
4143 }
d495ab0d 4144 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4145
4146 return &ret->root.root;
4147}
4148
cd1dac3d
DG		 4149/* Determine what kind of NOPs are available. */
4150
4151static bfd_boolean
4152arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4153{
4154 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4155 Tag_CPU_arch);
cd1dac3d 4156
60a019a0 4157 /* Force return logic to be reviewed for each new architecture. */
031254f2 4158 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4159
4160 return (arch == TAG_CPU_ARCH_V6T2
4161 || arch == TAG_CPU_ARCH_V6K
4162 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4163 || arch == TAG_CPU_ARCH_V8
4164 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4165}
4166
f4ac8484
DJ		 4167static bfd_boolean
4168arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4169{
4170 switch (stub_type)
4171 {
fea2b4d6 4172 case arm_stub_long_branch_thumb_only:
80c135e5 4173 case arm_stub_long_branch_thumb2_only:
d5a67c02 4174 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4175 case arm_stub_long_branch_v4t_thumb_arm:
4176 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4177 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4178 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4179 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4180 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4181 return TRUE;
4182 case arm_stub_none:
4183 BFD_FAIL ();
4184 return FALSE;
4185 break;
4186 default:
4187 return FALSE;
4188 }
4189}
4190
906e58ca
NC		 4191/* Determine the type of stub needed, if any, for a call. */
4192
4193static enum elf32_arm_stub_type
4194arm_type_of_stub (struct bfd_link_info *info,
4195 asection *input_sec,
4196 const Elf_Internal_Rela *rel,
34e77a92 4197 unsigned char st_type,
35fc36a8 4198 enum arm_st_branch_type *actual_branch_type,
906e58ca 4199 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4200 bfd_vma destination,
4201 asection *sym_sec,
4202 bfd *input_bfd,
4203 const char *name)
906e58ca
NC		 4204{
4205 bfd_vma location;
4206 bfd_signed_vma branch_offset;
4207 unsigned int r_type;
4208 struct elf32_arm_link_hash_table * globals;
5e866f5a 4209 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4210 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4211 int use_plt = 0;
35fc36a8 4212 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4213 union gotplt_union *root_plt;
4214 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4215 int arch;
4216 int thumb2_movw;
906e58ca 4217
35fc36a8 4218 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4219 return stub_type;
4220
906e58ca 4221 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4222 if (globals == NULL)
4223 return stub_type;
906e58ca
NC		 4224
4225 thumb_only = using_thumb_only (globals);
906e58ca 4226 thumb2 = using_thumb2 (globals);
5e866f5a 4227 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4228
d5a67c02
AV		 4229 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4230
4231 /* True for architectures that implement the thumb2 movw instruction. */
4232 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4233
906e58ca
NC		 4234 /* Determine where the call point is. */
4235 location = (input_sec->output_offset
4236 + input_sec->output_section->vma
4237 + rel->r_offset);
4238
906e58ca
NC		 4239 r_type = ELF32_R_TYPE (rel->r_info);
4240
39f21624
NC		 4241 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4242 are considering a function call relocation. */
c5423981 4243 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4244 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4245 && branch_type == ST_BRANCH_TO_ARM)
4246 branch_type = ST_BRANCH_TO_THUMB;
4247
34e77a92
RS		 4248 /* For TLS call relocs, it is the caller's responsibility to provide
4249 the address of the appropriate trampoline. */
4250 if (r_type != R_ARM_TLS_CALL
4251 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4252 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4253 ELF32_R_SYM (rel->r_info), &root_plt,
4254 &arm_plt)
34e77a92 4255 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4256 {
34e77a92 4257 asection *splt;
fe33d2fa 4258
34e77a92
RS		 4259 if (hash == NULL || hash->is_iplt)
4260 splt = globals->root.iplt;
4261 else
4262 splt = globals->root.splt;
4263 if (splt != NULL)
b38cadfb 4264 {
34e77a92
RS		 4265 use_plt = 1;
4266
4267 /* Note when dealing with PLT entries: the main PLT stub is in
4268 ARM mode, so if the branch is in Thumb mode, another
4269 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4270 PLT stub. If a long branch stub is needed, we'll add a
4271 Thumb->Arm one and branch directly to the ARM PLT entry.
4272 Here, we have to check if a pre-PLT Thumb->ARM stub
4273 is needed and if it will be close enough. */
34e77a92
RS		 4274
4275 destination = (splt->output_section->vma
4276 + splt->output_offset
4277 + root_plt->offset);
4278 st_type = STT_FUNC;
2df2751d
CL		 4279
4280 /* Thumb branch/call to PLT: it can become a branch to ARM
4281 or to Thumb. We must perform the same checks and
4282 corrections as in elf32_arm_final_link_relocate. */
4283 if ((r_type == R_ARM_THM_CALL)
4284 || (r_type == R_ARM_THM_JUMP24))
4285 {
4286 if (globals->use_blx
4287 && r_type == R_ARM_THM_CALL
4288 && !thumb_only)
4289 {
4290 /* If the Thumb BLX instruction is available, convert
4291 the BL to a BLX instruction to call the ARM-mode
4292 PLT entry. */
4293 branch_type = ST_BRANCH_TO_ARM;
4294 }
4295 else
4296 {
4297 if (!thumb_only)
4298 /* Target the Thumb stub before the ARM PLT entry. */
4299 destination -= PLT_THUMB_STUB_SIZE;
4300 branch_type = ST_BRANCH_TO_THUMB;
4301 }
4302 }
4303 else
4304 {
4305 branch_type = ST_BRANCH_TO_ARM;
4306 }
34e77a92 4307 }
5fa9e92f 4308 }
34e77a92
RS		 4309 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4310 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4311
fe33d2fa
CL		 4312 branch_offset = (bfd_signed_vma)(destination - location);
4313
0855e32b 4314 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4315 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4316 {
5fa9e92f
CL		 4317 /* Handle cases where:
4318 - this call goes too far (different Thumb/Thumb2 max
99059e56 4319 distance)
155d87d7 4320 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4321 Thumb->Arm branch (not bl). A stub is needed in this case,
4322 but only if this call is not through a PLT entry. Indeed,
695344c0 4323 PLT stubs handle mode switching already. */
5e866f5a 4324 if ((!thumb2_bl
906e58ca
NC		 4325 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4326 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4327 || (thumb2_bl
906e58ca
NC		 4328 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4329 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4330 || (thumb2
4331 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4332 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4333 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4334 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4335 && (((r_type == R_ARM_THM_CALL
4336 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4337 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4338 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4339 && !use_plt))
906e58ca 4340 {
2df2751d
CL		 4341 /* If we need to insert a Thumb-Thumb long branch stub to a
4342 PLT, use one that branches directly to the ARM PLT
4343 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4344 stub, undo this now. */
695344c0
NC		 4345 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4346 {
4347 branch_type = ST_BRANCH_TO_ARM;
4348 branch_offset += PLT_THUMB_STUB_SIZE;
4349 }
2df2751d 4350
35fc36a8 4351 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4352 {
4353 /* Thumb to thumb. */
4354 if (!thumb_only)
4355 {
d5a67c02 4356 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4357 _bfd_error_handler
871b3ab2 4358 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4359 " section with SHF_ARM_PURECODE section"
4360 " attribute is only supported for M-profile"
90b6238f 4361 " targets that implement the movw instruction"),
10463f39 4362 input_bfd, input_sec);
d5a67c02 4363
0e1862bb 4364 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4365 /* PIC stubs. */
155d87d7 4366 ? ((globals->use_blx
9553db3c 4367 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4368 /* V5T and above. Stub starts with ARM code, so
4369 we must be able to switch mode before
4370 reaching it, which is only possible for 'bl'
4371 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4372 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4373 /* On V4T, use Thumb code only. */
d3626fb0 4374 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4375
4376 /* non-PIC stubs. */
155d87d7 4377 : ((globals->use_blx
9553db3c 4378 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4379 /* V5T and above. */
4380 ? arm_stub_long_branch_any_any
4381 /* V4T. */
d3626fb0 4382 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4383 }
4384 else
4385 {
d5a67c02
AV		 4386 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4387 stub_type = arm_stub_long_branch_thumb2_only_pure;
4388 else
4389 {
4390 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4391 _bfd_error_handler
871b3ab2 4392 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4393 " section with SHF_ARM_PURECODE section"
4394 " attribute is only supported for M-profile"
90b6238f 4395 " targets that implement the movw instruction"),
10463f39 4396 input_bfd, input_sec);
d5a67c02
AV		 4397
4398 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4399 /* PIC stub. */
4400 ? arm_stub_long_branch_thumb_only_pic
4401 /* non-PIC stub. */
4402 : (thumb2 ? arm_stub_long_branch_thumb2_only
4403 : arm_stub_long_branch_thumb_only);
4404 }
906e58ca
NC		 4405 }
4406 }
4407 else
4408 {
d5a67c02 4409 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4410 _bfd_error_handler
871b3ab2 4411 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4412 " section with SHF_ARM_PURECODE section"
4413 " attribute is only supported" " for M-profile"
90b6238f 4414 " targets that implement the movw instruction"),
10463f39 4415 input_bfd, input_sec);
d5a67c02 4416
906e58ca 4417 /* Thumb to arm. */
c820be07
NC		 4418 if (sym_sec != NULL
4419 && sym_sec->owner != NULL
4420 && !INTERWORK_FLAG (sym_sec->owner))
4421 {
4eca0228 4422 _bfd_error_handler
90b6238f
AM		 4423 (_("%pB(%s): warning: interworking not enabled;"
4424 " first occurrence: %pB: %s call to %s"),
4425 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4426 }
4427
0855e32b 4428 stub_type =
0e1862bb 4429 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4430 /* PIC stubs. */
0855e32b 4431 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4432 /* TLS PIC stubs. */
0855e32b
NS		 4433 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4434 : arm_stub_long_branch_v4t_thumb_tls_pic)
4435 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4436 /* V5T PIC and above. */
4437 ? arm_stub_long_branch_any_arm_pic
4438 /* V4T PIC stub. */
4439 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4440
4441 /* non-PIC stubs. */
0855e32b 4442 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4443 /* V5T and above. */
4444 ? arm_stub_long_branch_any_any
4445 /* V4T. */
4446 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4447
4448 /* Handle v4t short branches. */
fea2b4d6 4449 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4450 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4451 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4452 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4453 }
4454 }
4455 }
fe33d2fa
CL		 4456 else if (r_type == R_ARM_CALL
4457 || r_type == R_ARM_JUMP24
0855e32b
NS		 4458 || r_type == R_ARM_PLT32
4459 || r_type == R_ARM_TLS_CALL)
906e58ca 4460 {
d5a67c02 4461 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4462 _bfd_error_handler
871b3ab2 4463 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4464 " section with SHF_ARM_PURECODE section"
4465 " attribute is only supported for M-profile"
90b6238f 4466 " targets that implement the movw instruction"),
10463f39 4467 input_bfd, input_sec);
35fc36a8 4468 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4469 {
4470 /* Arm to thumb. */
c820be07
NC		 4471
4472 if (sym_sec != NULL
4473 && sym_sec->owner != NULL
4474 && !INTERWORK_FLAG (sym_sec->owner))
4475 {
4eca0228 4476 _bfd_error_handler
90b6238f
AM		 4477 (_("%pB(%s): warning: interworking not enabled;"
4478 " first occurrence: %pB: %s call to %s"),
4479 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4480 }
4481
4482 /* We have an extra 2-bytes reach because of
4483 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4484 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4485 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4486 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4487 || (r_type == R_ARM_JUMP24)
4488 || (r_type == R_ARM_PLT32))
906e58ca 4489 {
0e1862bb 4490 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4491 /* PIC stubs. */
ebe24dd4
CL		 4492 ? ((globals->use_blx)
4493 /* V5T and above. */
4494 ? arm_stub_long_branch_any_thumb_pic
4495 /* V4T stub. */
4496 : arm_stub_long_branch_v4t_arm_thumb_pic)
4497
c2b4a39d
CL		 4498 /* non-PIC stubs. */
4499 : ((globals->use_blx)
4500 /* V5T and above. */
4501 ? arm_stub_long_branch_any_any
4502 /* V4T. */
4503 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4504 }
4505 }
4506 else
4507 {
4508 /* Arm to arm. */
4509 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4510 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4511 {
0855e32b 4512 stub_type =
0e1862bb 4513 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4514 /* PIC stubs. */
0855e32b 4515 ? (r_type == R_ARM_TLS_CALL
6a631e86 4516 /* TLS PIC Stub. */
0855e32b 4517 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4518 : (globals->nacl_p
4519 ? arm_stub_long_branch_arm_nacl_pic
4520 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4521 /* non-PIC stubs. */
7a89b94e
NC		 4522 : (globals->nacl_p
4523 ? arm_stub_long_branch_arm_nacl
4524 : arm_stub_long_branch_any_any);
906e58ca
NC		 4525 }
4526 }
4527 }
4528
fe33d2fa
CL		 4529 /* If a stub is needed, record the actual destination type. */
4530 if (stub_type != arm_stub_none)
35fc36a8 4531 *actual_branch_type = branch_type;
fe33d2fa 4532
906e58ca
NC		 4533 return stub_type;
4534}
4535
4536/* Build a name for an entry in the stub hash table. */
4537
4538static char *
4539elf32_arm_stub_name (const asection *input_section,
4540 const asection *sym_sec,
4541 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4542 const Elf_Internal_Rela *rel,
4543 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4544{
4545 char *stub_name;
4546 bfd_size_type len;
4547
4548 if (hash)
4549 {
fe33d2fa 4550 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4551 stub_name = (char *) bfd_malloc (len);
906e58ca 4552 if (stub_name != NULL)
fe33d2fa 4553 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4554 input_section->id & 0xffffffff,
4555 hash->root.root.root.string,
fe33d2fa
CL		 4556 (int) rel->r_addend & 0xffffffff,
4557 (int) stub_type);
906e58ca
NC		 4558 }
4559 else
4560 {
fe33d2fa 4561 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4562 stub_name = (char *) bfd_malloc (len);
906e58ca 4563 if (stub_name != NULL)
fe33d2fa 4564 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4565 input_section->id & 0xffffffff,
4566 sym_sec->id & 0xffffffff,
0855e32b
NS		 4567 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4568 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4569 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4570 (int) rel->r_addend & 0xffffffff,
4571 (int) stub_type);
906e58ca
NC		 4572 }
4573
4574 return stub_name;
4575}
4576
4577/* Look up an entry in the stub hash. Stub entries are cached because
4578 creating the stub name takes a bit of time. */
4579
4580static struct elf32_arm_stub_hash_entry *
4581elf32_arm_get_stub_entry (const asection *input_section,
4582 const asection *sym_sec,
4583 struct elf_link_hash_entry *hash,
4584 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4585 struct elf32_arm_link_hash_table *htab,
4586 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4587{
4588 struct elf32_arm_stub_hash_entry *stub_entry;
4589 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4590 const asection *id_sec;
4591
4592 if ((input_section->flags & SEC_CODE) == 0)
4593 return NULL;
4594
4d83e8d9
CL		 4595 /* If the input section is the CMSE stubs one and it needs a long
4596 branch stub to reach it's final destination, give up with an
4597 error message: this is not supported. See PR ld/24709. */
4598 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4599 {
4600 bfd *output_bfd = htab->obfd;
4601 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4602
4603 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4604 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4605 CMSE_STUB_NAME,
4606 (uint64_t)out_sec->output_section->vma
4607 + out_sec->output_offset,
4608 (uint64_t)sym_sec->output_section->vma
4609 + sym_sec->output_offset
4610 + h->root.root.u.def.value);
4611 /* Exit, rather than leave incompletely processed
4612 relocations. */
4613 xexit(1);
4614 }
4615
906e58ca
NC		 4616 /* If this input section is part of a group of sections sharing one
4617 stub section, then use the id of the first section in the group.
4618 Stub names need to include a section id, as there may well be
4619 more than one stub used to reach say, printf, and we need to
4620 distinguish between them. */
c2abbbeb 4621 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4622 id_sec = htab->stub_group[input_section->id].link_sec;
4623
4624 if (h != NULL && h->stub_cache != NULL
4625 && h->stub_cache->h == h
fe33d2fa
CL		 4626 && h->stub_cache->id_sec == id_sec
4627 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4628 {
4629 stub_entry = h->stub_cache;
4630 }
4631 else
4632 {
4633 char *stub_name;
4634
fe33d2fa 4635 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4636 if (stub_name == NULL)
4637 return NULL;
4638
4639 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4640 stub_name, FALSE, FALSE);
4641 if (h != NULL)
4642 h->stub_cache = stub_entry;
4643
4644 free (stub_name);
4645 }
4646
4647 return stub_entry;
4648}
4649
daa4adae
TP		 4650/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4651 section. */
4652
4653static bfd_boolean
4654arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4655{
4656 if (stub_type >= max_stub_type)
4657 abort (); /* Should be unreachable. */
4658
4ba2ef8f
TP		 4659 switch (stub_type)
4660 {
4661 case arm_stub_cmse_branch_thumb_only:
4662 return TRUE;
4663
4664 default:
4665 return FALSE;
4666 }
4667
4668 abort (); /* Should be unreachable. */
daa4adae
TP		 4669}
4670
4671/* Required alignment (as a power of 2) for the dedicated section holding
4672 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4673 with input sections. */
4674
4675static int
4676arm_dedicated_stub_output_section_required_alignment
4677 (enum elf32_arm_stub_type stub_type)
4678{
4679 if (stub_type >= max_stub_type)
4680 abort (); /* Should be unreachable. */
4681
4ba2ef8f
TP		 4682 switch (stub_type)
4683 {
4684 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4685 boundary. */
4686 case arm_stub_cmse_branch_thumb_only:
4687 return 5;
4688
4689 default:
4690 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4691 return 0;
4692 }
4693
4694 abort (); /* Should be unreachable. */
daa4adae
TP		 4695}
4696
4697/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4698 NULL if veneers of this type are interspersed with input sections. */
4699
4700static const char *
4701arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4702{
4703 if (stub_type >= max_stub_type)
4704 abort (); /* Should be unreachable. */
4705
4ba2ef8f
TP		 4706 switch (stub_type)
4707 {
4708 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4709 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4710
4711 default:
4712 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4713 return NULL;
4714 }
4715
4716 abort (); /* Should be unreachable. */
daa4adae
TP		 4717}
4718
4719/* If veneers of type STUB_TYPE should go in a dedicated output section,
4720 returns the address of the hash table field in HTAB holding a pointer to the
4721 corresponding input section. Otherwise, returns NULL. */
4722
4723static asection **
4ba2ef8f
TP		 4724arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4725 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4726{
4727 if (stub_type >= max_stub_type)
4728 abort (); /* Should be unreachable. */
4729
4ba2ef8f
TP		 4730 switch (stub_type)
4731 {
4732 case arm_stub_cmse_branch_thumb_only:
4733 return &htab->cmse_stub_sec;
4734
4735 default:
4736 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4737 return NULL;
4738 }
4739
4740 abort (); /* Should be unreachable. */
daa4adae
TP		 4741}
4742
4743/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4744 is the section that branch into veneer and can be NULL if stub should go in
4745 a dedicated output section. Returns a pointer to the stub section, and the
4746 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4747 LINK_SEC_P may be NULL. */
906e58ca 4748
48229727
JB		 4749static asection *
4750elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4751 struct elf32_arm_link_hash_table *htab,
4752 enum elf32_arm_stub_type stub_type)
906e58ca 4753{
daa4adae
TP		 4754 asection *link_sec, *out_sec, **stub_sec_p;
4755 const char *stub_sec_prefix;
4756 bfd_boolean dedicated_output_section =
4757 arm_dedicated_stub_output_section_required (stub_type);
4758 int align;
906e58ca 4759
daa4adae 4760 if (dedicated_output_section)
906e58ca 4761 {
daa4adae
TP		 4762 bfd *output_bfd = htab->obfd;
4763 const char *out_sec_name =
4764 arm_dedicated_stub_output_section_name (stub_type);
4765 link_sec = NULL;
4766 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4767 stub_sec_prefix = out_sec_name;
4768 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4769 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4770 if (out_sec == NULL)
906e58ca 4771 {
90b6238f 4772 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4773 "section %s"), out_sec_name);
daa4adae 4774 return NULL;
906e58ca 4775 }
daa4adae
TP		 4776 }
4777 else
4778 {
c2abbbeb 4779 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4780 link_sec = htab->stub_group[section->id].link_sec;
4781 BFD_ASSERT (link_sec != NULL);
4782 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4783 if (*stub_sec_p == NULL)
4784 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4785 stub_sec_prefix = link_sec->name;
4786 out_sec = link_sec->output_section;
4787 align = htab->nacl_p ? 4 : 3;
906e58ca 4788 }
b38cadfb 4789
daa4adae
TP		 4790 if (*stub_sec_p == NULL)
4791 {
4792 size_t namelen;
4793 bfd_size_type len;
4794 char *s_name;
4795
4796 namelen = strlen (stub_sec_prefix);
4797 len = namelen + sizeof (STUB_SUFFIX);
4798 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4799 if (s_name == NULL)
4800 return NULL;
4801
4802 memcpy (s_name, stub_sec_prefix, namelen);
4803 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4804 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4805 align);
4806 if (*stub_sec_p == NULL)
4807 return NULL;
4808
4809 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4810 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4811 | SEC_KEEP;
4812 }
4813
4814 if (!dedicated_output_section)
4815 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4816
48229727
JB		 4817 if (link_sec_p)
4818 *link_sec_p = link_sec;
b38cadfb 4819
daa4adae 4820 return *stub_sec_p;
48229727
JB		 4821}
4822
4823/* Add a new stub entry to the stub hash. Not all fields of the new
4824 stub entry are initialised. */
4825
4826static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4827elf32_arm_add_stub (const char *stub_name, asection *section,
4828 struct elf32_arm_link_hash_table *htab,
4829 enum elf32_arm_stub_type stub_type)
48229727
JB		 4830{
4831 asection *link_sec;
4832 asection *stub_sec;
4833 struct elf32_arm_stub_hash_entry *stub_entry;
4834
daa4adae
TP		 4835 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4836 stub_type);
48229727
JB		 4837 if (stub_sec == NULL)
4838 return NULL;
906e58ca
NC		 4839
4840 /* Enter this entry into the linker stub hash table. */
4841 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4842 TRUE, FALSE);
4843 if (stub_entry == NULL)
4844 {
6bde4c52
TP		 4845 if (section == NULL)
4846 section = stub_sec;
871b3ab2 4847 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4848 section->owner, stub_name);
906e58ca
NC		 4849 return NULL;
4850 }
4851
4852 stub_entry->stub_sec = stub_sec;
0955507f 4853 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4854 stub_entry->id_sec = link_sec;
4855
906e58ca
NC		 4856 return stub_entry;
4857}
4858
4859/* Store an Arm insn into an output section not processed by
4860 elf32_arm_write_section. */
4861
4862static void
8029a119
NC		 4863put_arm_insn (struct elf32_arm_link_hash_table * htab,
4864 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4865{
4866 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4867 bfd_putl32 (val, ptr);
4868 else
4869 bfd_putb32 (val, ptr);
4870}
4871
4872/* Store a 16-bit Thumb insn into an output section not processed by
4873 elf32_arm_write_section. */
4874
4875static void
8029a119
NC		 4876put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4877 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4878{
4879 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4880 bfd_putl16 (val, ptr);
4881 else
4882 bfd_putb16 (val, ptr);
4883}
4884
a504d23a
LA		 4885/* Store a Thumb2 insn into an output section not processed by
4886 elf32_arm_write_section. */
4887
4888static void
4889put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4890 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4891{
4892 /* T2 instructions are 16-bit streamed. */
4893 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4894 {
4895 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4896 bfd_putl16 ((val & 0xffff), ptr + 2);
4897 }
4898 else
4899 {
4900 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4901 bfd_putb16 ((val & 0xffff), ptr + 2);
4902 }
4903}
4904
0855e32b
NS		 4905/* If it's possible to change R_TYPE to a more efficient access
4906 model, return the new reloc type. */
4907
4908static unsigned
b38cadfb 4909elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4910 struct elf_link_hash_entry *h)
4911{
4912 int is_local = (h == NULL);
4913
0e1862bb
L		 4914 if (bfd_link_pic (info)
4915 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4916 return r_type;
4917
b38cadfb 4918 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4919 switch (r_type)
4920 {
4921 case R_ARM_TLS_GOTDESC:
4922 case R_ARM_TLS_CALL:
4923 case R_ARM_THM_TLS_CALL:
4924 case R_ARM_TLS_DESCSEQ:
4925 case R_ARM_THM_TLS_DESCSEQ:
4926 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4927 }
4928
4929 return r_type;
4930}
4931
48229727
JB		 4932static bfd_reloc_status_type elf32_arm_final_link_relocate
4933 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4934 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4935 const char *, unsigned char, enum arm_st_branch_type,
4936 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4937
4563a860
JB		 4938static unsigned int
4939arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4940{
4941 switch (stub_type)
4942 {
4943 case arm_stub_a8_veneer_b_cond:
4944 case arm_stub_a8_veneer_b:
4945 case arm_stub_a8_veneer_bl:
4946 return 2;
4947
4948 case arm_stub_long_branch_any_any:
4949 case arm_stub_long_branch_v4t_arm_thumb:
4950 case arm_stub_long_branch_thumb_only:
80c135e5 4951 case arm_stub_long_branch_thumb2_only:
d5a67c02 4952 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4953 case arm_stub_long_branch_v4t_thumb_thumb:
4954 case arm_stub_long_branch_v4t_thumb_arm:
4955 case arm_stub_short_branch_v4t_thumb_arm:
4956 case arm_stub_long_branch_any_arm_pic:
4957 case arm_stub_long_branch_any_thumb_pic:
4958 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4959 case arm_stub_long_branch_v4t_arm_thumb_pic:
4960 case arm_stub_long_branch_v4t_thumb_arm_pic:
4961 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4962 case arm_stub_long_branch_any_tls_pic:
4963 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4964 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4965 case arm_stub_a8_veneer_blx:
4966 return 4;
b38cadfb 4967
7a89b94e
NC		 4968 case arm_stub_long_branch_arm_nacl:
4969 case arm_stub_long_branch_arm_nacl_pic:
4970 return 16;
4971
4563a860
JB		 4972 default:
4973 abort (); /* Should be unreachable. */
4974 }
4975}
4976
4f4faa4d
TP		 4977/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4978 veneering (TRUE) or have their own symbol (FALSE). */
4979
4980static bfd_boolean
4981arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4982{
4983 if (stub_type >= max_stub_type)
4984 abort (); /* Should be unreachable. */
4985
4ba2ef8f
TP		 4986 switch (stub_type)
4987 {
4988 case arm_stub_cmse_branch_thumb_only:
4989 return TRUE;
4990
4991 default:
4992 return FALSE;
4993 }
4994
4995 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4996}
4997
d7c5bd02
TP		 4998/* Returns the padding needed for the dedicated section used stubs of type
4999 STUB_TYPE. */
5000
5001static int
5002arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
5003{
5004 if (stub_type >= max_stub_type)
5005 abort (); /* Should be unreachable. */
5006
4ba2ef8f
TP		 5007 switch (stub_type)
5008 {
5009 case arm_stub_cmse_branch_thumb_only:
5010 return 32;
5011
5012 default:
5013 return 0;
5014 }
5015
5016 abort (); /* Should be unreachable. */
d7c5bd02
TP		 5017}
5018
0955507f
TP		 5019/* If veneers of type STUB_TYPE should go in a dedicated output section,
5020 returns the address of the hash table field in HTAB holding the offset at
5021 which new veneers should be layed out in the stub section. */
5022
5023static bfd_vma*
5024arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
5025 enum elf32_arm_stub_type stub_type)
5026{
5027 switch (stub_type)
5028 {
5029 case arm_stub_cmse_branch_thumb_only:
5030 return &htab->new_cmse_stub_offset;
5031
5032 default:
5033 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
5034 return NULL;
5035 }
5036}
5037
906e58ca
NC		 5038static bfd_boolean
5039arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5040 void * in_arg)
5041{
7a89b94e 5042#define MAXRELOCS 3
0955507f 5043 bfd_boolean removed_sg_veneer;
906e58ca 5044 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5045 struct elf32_arm_link_hash_table *globals;
906e58ca 5046 struct bfd_link_info *info;
906e58ca
NC		 5047 asection *stub_sec;
5048 bfd *stub_bfd;
906e58ca
NC		 5049 bfd_byte *loc;
5050 bfd_vma sym_value;
5051 int template_size;
5052 int size;
d3ce72d0 5053 const insn_sequence *template_sequence;
906e58ca 5054 int i;
48229727
JB		 5055 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5056 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5057 int nrelocs = 0;
0955507f 5058 int just_allocated = 0;
906e58ca
NC		 5059
5060 /* Massage our args to the form they really have. */
5061 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5062 info = (struct bfd_link_info *) in_arg;
5063
5064 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5065 if (globals == NULL)
5066 return FALSE;
906e58ca 5067
906e58ca
NC		 5068 stub_sec = stub_entry->stub_sec;
5069
4dfe6ac6 5070 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5071 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5072 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5073 return TRUE;
fe33d2fa 5074
0955507f
TP		 5075 /* Assign a slot at the end of section if none assigned yet. */
5076 if (stub_entry->stub_offset == (bfd_vma) -1)
5077 {
5078 stub_entry->stub_offset = stub_sec->size;
5079 just_allocated = 1;
5080 }
906e58ca
NC		 5081 loc = stub_sec->contents + stub_entry->stub_offset;
5082
5083 stub_bfd = stub_sec->owner;
5084
906e58ca
NC		 5085 /* This is the address of the stub destination. */
5086 sym_value = (stub_entry->target_value
5087 + stub_entry->target_section->output_offset
5088 + stub_entry->target_section->output_section->vma);
5089
d3ce72d0 5090 template_sequence = stub_entry->stub_template;
461a49ca 5091 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5092
5093 size = 0;
461a49ca 5094 for (i = 0; i < template_size; i++)
906e58ca 5095 {
d3ce72d0 5096 switch (template_sequence[i].type)
461a49ca
DJ		 5097 {
5098 case THUMB16_TYPE:
48229727 5099 {
d3ce72d0
NC		 5100 bfd_vma data = (bfd_vma) template_sequence[i].data;
5101 if (template_sequence[i].reloc_addend != 0)
48229727 5102 {
99059e56
RM		 5103 /* We've borrowed the reloc_addend field to mean we should
5104 insert a condition code into this (Thumb-1 branch)
5105 instruction. See THUMB16_BCOND_INSN. */
5106 BFD_ASSERT ((data & 0xff00) == 0xd000);
5107 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5108 }
fe33d2fa 5109 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5110 size += 2;
5111 }
461a49ca 5112 break;
906e58ca 5113
48229727 5114 case THUMB32_TYPE:
fe33d2fa
CL		 5115 bfd_put_16 (stub_bfd,
5116 (template_sequence[i].data >> 16) & 0xffff,
5117 loc + size);
5118 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5119 loc + size + 2);
99059e56
RM		 5120 if (template_sequence[i].r_type != R_ARM_NONE)
5121 {
5122 stub_reloc_idx[nrelocs] = i;
5123 stub_reloc_offset[nrelocs++] = size;
5124 }
5125 size += 4;
5126 break;
48229727 5127
461a49ca 5128 case ARM_TYPE:
fe33d2fa
CL		 5129 bfd_put_32 (stub_bfd, template_sequence[i].data,
5130 loc + size);
461a49ca
DJ		 5131 /* Handle cases where the target is encoded within the
5132 instruction. */
d3ce72d0 5133 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5134 {
48229727
JB		 5135 stub_reloc_idx[nrelocs] = i;
5136 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5137 }
5138 size += 4;
5139 break;
5140
5141 case DATA_TYPE:
d3ce72d0 5142 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5143 stub_reloc_idx[nrelocs] = i;
5144 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5145 size += 4;
5146 break;
5147
5148 default:
5149 BFD_FAIL ();
5150 return FALSE;
5151 }
906e58ca 5152 }
461a49ca 5153
0955507f
TP		 5154 if (just_allocated)
5155 stub_sec->size += size;
906e58ca 5156
461a49ca
DJ		 5157 /* Stub size has already been computed in arm_size_one_stub. Check
5158 consistency. */
5159 BFD_ASSERT (size == stub_entry->stub_size);
5160
906e58ca 5161 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5162 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5163 sym_value |= 1;
5164
0955507f
TP		 5165 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5166 to relocate in each stub. */
5167 removed_sg_veneer =
5168 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5169 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5170
48229727 5171 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5172 {
5173 Elf_Internal_Rela rel;
5174 bfd_boolean unresolved_reloc;
5175 char *error_message;
5176 bfd_vma points_to =
5177 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5178
5179 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5180 rel.r_info = ELF32_R_INFO (0,
5181 template_sequence[stub_reloc_idx[i]].r_type);
5182 rel.r_addend = 0;
5183
5184 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5185 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5186 template should refer back to the instruction after the original
5187 branch. We use target_section as Cortex-A8 erratum workaround stubs
5188 are only generated when both source and target are in the same
5189 section. */
5190 points_to = stub_entry->target_section->output_section->vma
5191 + stub_entry->target_section->output_offset
5192 + stub_entry->source_value;
5193
5194 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5195 (template_sequence[stub_reloc_idx[i]].r_type),
5196 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5197 points_to, info, stub_entry->target_section, "", STT_FUNC,
5198 stub_entry->branch_type,
5199 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5200 &error_message);
5201 }
906e58ca
NC		 5202
5203 return TRUE;
48229727 5204#undef MAXRELOCS
906e58ca
NC		 5205}
5206
48229727
JB		 5207/* Calculate the template, template size and instruction size for a stub.
5208 Return value is the instruction size. */
906e58ca 5209
48229727
JB		 5210static unsigned int
5211find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5212 const insn_sequence **stub_template,
5213 int *stub_template_size)
906e58ca 5214{
d3ce72d0 5215 const insn_sequence *template_sequence = NULL;
48229727
JB		 5216 int template_size = 0, i;
5217 unsigned int size;
906e58ca 5218
d3ce72d0 5219 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5220 if (stub_template)
5221 *stub_template = template_sequence;
5222
48229727 5223 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5224 if (stub_template_size)
5225 *stub_template_size = template_size;
906e58ca
NC		 5226
5227 size = 0;
461a49ca
DJ		 5228 for (i = 0; i < template_size; i++)
5229 {
d3ce72d0 5230 switch (template_sequence[i].type)
461a49ca
DJ		 5231 {
5232 case THUMB16_TYPE:
5233 size += 2;
5234 break;
5235
5236 case ARM_TYPE:
48229727 5237 case THUMB32_TYPE:
461a49ca
DJ		 5238 case DATA_TYPE:
5239 size += 4;
5240 break;
5241
5242 default:
5243 BFD_FAIL ();
2a229407 5244 return 0;
461a49ca
DJ		 5245 }
5246 }
5247
48229727
JB		 5248 return size;
5249}
5250
5251/* As above, but don't actually build the stub. Just bump offset so
5252 we know stub section sizes. */
5253
5254static bfd_boolean
5255arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5256 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5257{
5258 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5259 const insn_sequence *template_sequence;
48229727
JB		 5260 int template_size, size;
5261
5262 /* Massage our args to the form they really have. */
5263 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5264
5265 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5266 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5267
d3ce72d0 5268 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5269 &template_size);
5270
0955507f
TP		 5271 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5272 if (stub_entry->stub_template_size)
5273 {
5274 stub_entry->stub_size = size;
5275 stub_entry->stub_template = template_sequence;
5276 stub_entry->stub_template_size = template_size;
5277 }
5278
5279 /* Already accounted for. */
5280 if (stub_entry->stub_offset != (bfd_vma) -1)
5281 return TRUE;
461a49ca 5282
906e58ca
NC		 5283 size = (size + 7) & ~7;
5284 stub_entry->stub_sec->size += size;
461a49ca 5285
906e58ca
NC		 5286 return TRUE;
5287}
5288
5289/* External entry points for sizing and building linker stubs. */
5290
5291/* Set up various things so that we can make a list of input sections
5292 for each output section included in the link. Returns -1 on error,
5293 0 when no stubs will be needed, and 1 on success. */
5294
5295int
5296elf32_arm_setup_section_lists (bfd *output_bfd,
5297 struct bfd_link_info *info)
5298{
5299 bfd *input_bfd;
5300 unsigned int bfd_count;
7292b3ac 5301 unsigned int top_id, top_index;
906e58ca
NC		 5302 asection *section;
5303 asection **input_list, **list;
5304 bfd_size_type amt;
5305 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5306
4dfe6ac6
NC		 5307 if (htab == NULL)
5308 return 0;
906e58ca
NC		 5309 if (! is_elf_hash_table (htab))
5310 return 0;
5311
5312 /* Count the number of input BFDs and find the top input section id. */
5313 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5314 input_bfd != NULL;
c72f2fb2 5315 input_bfd = input_bfd->link.next)
906e58ca
NC		 5316 {
5317 bfd_count += 1;
5318 for (section = input_bfd->sections;
5319 section != NULL;
5320 section = section->next)
5321 {
5322 if (top_id < section->id)
5323 top_id = section->id;
5324 }
5325 }
5326 htab->bfd_count = bfd_count;
5327
5328 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5329 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5330 if (htab->stub_group == NULL)
5331 return -1;
fe33d2fa 5332 htab->top_id = top_id;
906e58ca
NC		 5333
5334 /* We can't use output_bfd->section_count here to find the top output
5335 section index as some sections may have been removed, and
5336 _bfd_strip_section_from_output doesn't renumber the indices. */
5337 for (section = output_bfd->sections, top_index = 0;
5338 section != NULL;
5339 section = section->next)
5340 {
5341 if (top_index < section->index)
5342 top_index = section->index;
5343 }
5344
5345 htab->top_index = top_index;
5346 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5347 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5348 htab->input_list = input_list;
5349 if (input_list == NULL)
5350 return -1;
5351
5352 /* For sections we aren't interested in, mark their entries with a
5353 value we can check later. */
5354 list = input_list + top_index;
5355 do
5356 *list = bfd_abs_section_ptr;
5357 while (list-- != input_list);
5358
5359 for (section = output_bfd->sections;
5360 section != NULL;
5361 section = section->next)
5362 {
5363 if ((section->flags & SEC_CODE) != 0)
5364 input_list[section->index] = NULL;
5365 }
5366
5367 return 1;
5368}
5369
5370/* The linker repeatedly calls this function for each input section,
5371 in the order that input sections are linked into output sections.
5372 Build lists of input sections to determine groupings between which
5373 we may insert linker stubs. */
5374
5375void
5376elf32_arm_next_input_section (struct bfd_link_info *info,
5377 asection *isec)
5378{
5379 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5380
4dfe6ac6
NC		 5381 if (htab == NULL)
5382 return;
5383
906e58ca
NC		 5384 if (isec->output_section->index <= htab->top_index)
5385 {
5386 asection **list = htab->input_list + isec->output_section->index;
5387
a7470592 5388 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5389 {
5390 /* Steal the link_sec pointer for our list. */
5391#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5392 /* This happens to make the list in reverse order,
07d72278 5393 which we reverse later. */
906e58ca
NC		 5394 PREV_SEC (isec) = *list;
5395 *list = isec;
5396 }
5397 }
5398}
5399
5400/* See whether we can group stub sections together. Grouping stub
5401 sections may result in fewer stubs. More importantly, we need to
07d72278 5402 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5403 .fini output sections respectively, because glibc splits the
5404 _init and _fini functions into multiple parts. Putting a stub in
5405 the middle of a function is not a good idea. */
5406
5407static void
5408group_sections (struct elf32_arm_link_hash_table *htab,
5409 bfd_size_type stub_group_size,
07d72278 5410 bfd_boolean stubs_always_after_branch)
906e58ca 5411{
07d72278 5412 asection **list = htab->input_list;
906e58ca
NC		 5413
5414 do
5415 {
5416 asection *tail = *list;
07d72278 5417 asection *head;
906e58ca
NC		 5418
5419 if (tail == bfd_abs_section_ptr)
5420 continue;
5421
07d72278
DJ		 5422 /* Reverse the list: we must avoid placing stubs at the
5423 beginning of the section because the beginning of the text
5424 section may be required for an interrupt vector in bare metal
5425 code. */
5426#define NEXT_SEC PREV_SEC
e780aef2
CL		 5427 head = NULL;
5428 while (tail != NULL)
99059e56
RM		 5429 {
5430 /* Pop from tail. */
5431 asection *item = tail;
5432 tail = PREV_SEC (item);
e780aef2 5433
99059e56
RM		 5434 /* Push on head. */
5435 NEXT_SEC (item) = head;
5436 head = item;
5437 }
07d72278
DJ		 5438
5439 while (head != NULL)
906e58ca
NC		 5440 {
5441 asection *curr;
07d72278 5442 asection *next;
e780aef2
CL		 5443 bfd_vma stub_group_start = head->output_offset;
5444 bfd_vma end_of_next;
906e58ca 5445
07d72278 5446 curr = head;
e780aef2 5447 while (NEXT_SEC (curr) != NULL)
8cd931b7 5448 {
e780aef2
CL		 5449 next = NEXT_SEC (curr);
5450 end_of_next = next->output_offset + next->size;
5451 if (end_of_next - stub_group_start >= stub_group_size)
5452 /* End of NEXT is too far from start, so stop. */
8cd931b7 5453 break;
e780aef2
CL		 5454 /* Add NEXT to the group. */
5455 curr = next;
8cd931b7 5456 }
906e58ca 5457
07d72278 5458 /* OK, the size from the start to the start of CURR is less
906e58ca 5459 than stub_group_size and thus can be handled by one stub
07d72278 5460 section. (Or the head section is itself larger than
906e58ca
NC		 5461 stub_group_size, in which case we may be toast.)
5462 We should really be keeping track of the total size of
5463 stubs added here, as stubs contribute to the final output
7fb9f789 5464 section size. */
906e58ca
NC		 5465 do
5466 {
07d72278 5467 next = NEXT_SEC (head);
906e58ca 5468 /* Set up this stub group. */
07d72278 5469 htab->stub_group[head->id].link_sec = curr;
906e58ca 5470 }
07d72278 5471 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5472
5473 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5474 bytes after the stub section can be handled by it too. */
5475 if (!stubs_always_after_branch)
906e58ca 5476 {
e780aef2
CL		 5477 stub_group_start = curr->output_offset + curr->size;
5478
8cd931b7 5479 while (next != NULL)
906e58ca 5480 {
e780aef2
CL		 5481 end_of_next = next->output_offset + next->size;
5482 if (end_of_next - stub_group_start >= stub_group_size)
5483 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5484 break;
e780aef2 5485 /* Add NEXT to the stub group. */
07d72278
DJ		 5486 head = next;
5487 next = NEXT_SEC (head);
5488 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5489 }
5490 }
07d72278 5491 head = next;
906e58ca
NC		 5492 }
5493 }
07d72278 5494 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5495
5496 free (htab->input_list);
5497#undef PREV_SEC
07d72278 5498#undef NEXT_SEC
906e58ca
NC		 5499}
5500
48229727
JB		 5501/* Comparison function for sorting/searching relocations relating to Cortex-A8
5502 erratum fix. */
5503
5504static int
5505a8_reloc_compare (const void *a, const void *b)
5506{
21d799b5
NC		 5507 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5508 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5509
5510 if (ra->from < rb->from)
5511 return -1;
5512 else if (ra->from > rb->from)
5513 return 1;
5514 else
5515 return 0;
5516}
5517
5518static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5519 const char *, char **);
5520
5521/* Helper function to scan code for sequences which might trigger the Cortex-A8
5522 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5523 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5524 otherwise. */
5525
81694485
NC		 5526static bfd_boolean
5527cortex_a8_erratum_scan (bfd *input_bfd,
5528 struct bfd_link_info *info,
48229727
JB		 5529 struct a8_erratum_fix **a8_fixes_p,
5530 unsigned int *num_a8_fixes_p,
5531 unsigned int *a8_fix_table_size_p,
5532 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5533 unsigned int num_a8_relocs,
5534 unsigned prev_num_a8_fixes,
5535 bfd_boolean *stub_changed_p)
48229727
JB		 5536{
5537 asection *section;
5538 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5539 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5540 unsigned int num_a8_fixes = *num_a8_fixes_p;
5541 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5542
4dfe6ac6
NC		 5543 if (htab == NULL)
5544 return FALSE;
5545
48229727
JB		 5546 for (section = input_bfd->sections;
5547 section != NULL;
5548 section = section->next)
5549 {
5550 bfd_byte *contents = NULL;
5551 struct _arm_elf_section_data *sec_data;
5552 unsigned int span;
5553 bfd_vma base_vma;
5554
5555 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5556 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5557 || (section->flags & SEC_EXCLUDE) != 0
5558 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5559 || (section->output_section == bfd_abs_section_ptr))
5560 continue;
48229727
JB		 5561
5562 base_vma = section->output_section->vma + section->output_offset;
5563
5564 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5565 contents = elf_section_data (section)->this_hdr.contents;
48229727 5566 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5567 return TRUE;
48229727
JB		 5568
5569 sec_data = elf32_arm_section_data (section);
5570
5571 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5572 {
5573 unsigned int span_start = sec_data->map[span].vma;
5574 unsigned int span_end = (span == sec_data->mapcount - 1)
5575 ? section->size : sec_data->map[span + 1].vma;
5576 unsigned int i;
5577 char span_type = sec_data->map[span].type;
5578 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5579
5580 if (span_type != 't')
5581 continue;
5582
5583 /* Span is entirely within a single 4KB region: skip scanning. */
5584 if (((base_vma + span_start) & ~0xfff)
48229727 5585 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5586 continue;
5587
5588 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5589
5590 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5591 * The branch target is in the same 4KB region as the
5592 first half of the branch.
5593 * The instruction before the branch is a 32-bit
5594 length non-branch instruction. */
5595 for (i = span_start; i < span_end;)
5596 {
5597 unsigned int insn = bfd_getl16 (&contents[i]);
5598 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5599 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5600
99059e56
RM		 5601 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5602 insn_32bit = TRUE;
48229727
JB		 5603
5604 if (insn_32bit)
99059e56
RM		 5605 {
5606 /* Load the rest of the insn (in manual-friendly order). */
5607 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5608
5609 /* Encoding T4: B<c>.W. */
5610 is_b = (insn & 0xf800d000) == 0xf0009000;
5611 /* Encoding T1: BL<c>.W. */
5612 is_bl = (insn & 0xf800d000) == 0xf000d000;
5613 /* Encoding T2: BLX<c>.W. */
5614 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5615 /* Encoding T3: B<c>.W (not permitted in IT block). */
5616 is_bcc = (insn & 0xf800d000) == 0xf0008000
5617 && (insn & 0x07f00000) != 0x03800000;
5618 }
5619
5620 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5621
99059e56 5622 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5623 && insn_32bit
5624 && is_32bit_branch
5625 && last_was_32bit
5626 && ! last_was_branch)
99059e56
RM		 5627 {
5628 bfd_signed_vma offset = 0;
5629 bfd_boolean force_target_arm = FALSE;
48229727 5630 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5631 bfd_vma target;
5632 enum elf32_arm_stub_type stub_type = arm_stub_none;
5633 struct a8_erratum_reloc key, *found;
5634 bfd_boolean use_plt = FALSE;
48229727 5635
99059e56
RM		 5636 key.from = base_vma + i;
5637 found = (struct a8_erratum_reloc *)
5638 bsearch (&key, a8_relocs, num_a8_relocs,
5639 sizeof (struct a8_erratum_reloc),
5640 &a8_reloc_compare);
48229727
JB		 5641
5642 if (found)
5643 {
5644 char *error_message = NULL;
5645 struct elf_link_hash_entry *entry;
5646
5647 /* We don't care about the error returned from this
99059e56 5648 function, only if there is glue or not. */
48229727
JB		 5649 entry = find_thumb_glue (info, found->sym_name,
5650 &error_message);
5651
5652 if (entry)
5653 found->non_a8_stub = TRUE;
5654
92750f34 5655 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5656 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5657 && found->hash->root.plt.offset != (bfd_vma) -1)
5658 use_plt = TRUE;
5659
5660 if (found->r_type == R_ARM_THM_CALL)
5661 {
35fc36a8
RS		 5662 if (found->branch_type == ST_BRANCH_TO_ARM
5663 || use_plt)
92750f34
DJ		 5664 force_target_arm = TRUE;
5665 else
5666 force_target_thumb = TRUE;
5667 }
48229727
JB		 5668 }
5669
99059e56 5670 /* Check if we have an offending branch instruction. */
48229727
JB		 5671
5672 if (found && found->non_a8_stub)
5673 /* We've already made a stub for this instruction, e.g.
5674 it's a long branch or a Thumb->ARM stub. Assume that
5675 stub will suffice to work around the A8 erratum (see
5676 setting of always_after_branch above). */
5677 ;
99059e56
RM		 5678 else if (is_bcc)
5679 {
5680 offset = (insn & 0x7ff) << 1;
5681 offset |= (insn & 0x3f0000) >> 4;
5682 offset |= (insn & 0x2000) ? 0x40000 : 0;
5683 offset |= (insn & 0x800) ? 0x80000 : 0;
5684 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5685 if (offset & 0x100000)
5686 offset |= ~ ((bfd_signed_vma) 0xfffff);
5687 stub_type = arm_stub_a8_veneer_b_cond;
5688 }
5689 else if (is_b || is_bl || is_blx)
5690 {
5691 int s = (insn & 0x4000000) != 0;
5692 int j1 = (insn & 0x2000) != 0;
5693 int j2 = (insn & 0x800) != 0;
5694 int i1 = !(j1 ^ s);
5695 int i2 = !(j2 ^ s);
5696
5697 offset = (insn & 0x7ff) << 1;
5698 offset |= (insn & 0x3ff0000) >> 4;
5699 offset |= i2 << 22;
5700 offset |= i1 << 23;
5701 offset |= s << 24;
5702 if (offset & 0x1000000)
5703 offset |= ~ ((bfd_signed_vma) 0xffffff);
5704
5705 if (is_blx)
5706 offset &= ~ ((bfd_signed_vma) 3);
5707
5708 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5709 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5710 }
5711
5712 if (stub_type != arm_stub_none)
5713 {
5714 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5715
5716 /* The original instruction is a BL, but the target is
99059e56 5717 an ARM instruction. If we were not making a stub,
48229727
JB		 5718 the BL would have been converted to a BLX. Use the
5719 BLX stub instead in that case. */
5720 if (htab->use_blx && force_target_arm
5721 && stub_type == arm_stub_a8_veneer_bl)
5722 {
5723 stub_type = arm_stub_a8_veneer_blx;
5724 is_blx = TRUE;
5725 is_bl = FALSE;
5726 }
5727 /* Conversely, if the original instruction was
5728 BLX but the target is Thumb mode, use the BL
5729 stub. */
5730 else if (force_target_thumb
5731 && stub_type == arm_stub_a8_veneer_blx)
5732 {
5733 stub_type = arm_stub_a8_veneer_bl;
5734 is_blx = FALSE;
5735 is_bl = TRUE;
5736 }
5737
99059e56
RM		 5738 if (is_blx)
5739 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5740
99059e56
RM		 5741 /* If we found a relocation, use the proper destination,
5742 not the offset in the (unrelocated) instruction.
48229727
JB		 5743 Note this is always done if we switched the stub type
5744 above. */
99059e56
RM		 5745 if (found)
5746 offset =
81694485 5747 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5748
99059e56
RM		 5749 /* If the stub will use a Thumb-mode branch to a
5750 PLT target, redirect it to the preceding Thumb
5751 entry point. */
5752 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5753 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5754
99059e56 5755 target = pc_for_insn + offset;
48229727 5756
99059e56
RM		 5757 /* The BLX stub is ARM-mode code. Adjust the offset to
5758 take the different PC value (+8 instead of +4) into
48229727 5759 account. */
99059e56
RM		 5760 if (stub_type == arm_stub_a8_veneer_blx)
5761 offset += 4;
5762
5763 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5764 {
5765 char *stub_name = NULL;
5766
5767 if (num_a8_fixes == a8_fix_table_size)
5768 {
5769 a8_fix_table_size *= 2;
5770 a8_fixes = (struct a8_erratum_fix *)
5771 bfd_realloc (a8_fixes,
5772 sizeof (struct a8_erratum_fix)
5773 * a8_fix_table_size);
5774 }
48229727 5775
eb7c4339
NS		 5776 if (num_a8_fixes < prev_num_a8_fixes)
5777 {
5778 /* If we're doing a subsequent scan,
5779 check if we've found the same fix as
5780 before, and try and reuse the stub
5781 name. */
5782 stub_name = a8_fixes[num_a8_fixes].stub_name;
5783 if ((a8_fixes[num_a8_fixes].section != section)
5784 || (a8_fixes[num_a8_fixes].offset != i))
5785 {
5786 free (stub_name);
5787 stub_name = NULL;
5788 *stub_changed_p = TRUE;
5789 }
5790 }
5791
5792 if (!stub_name)
5793 {
21d799b5 5794 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5795 if (stub_name != NULL)
5796 sprintf (stub_name, "%x:%x", section->id, i);
5797 }
48229727 5798
99059e56
RM		 5799 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5800 a8_fixes[num_a8_fixes].section = section;
5801 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5802 a8_fixes[num_a8_fixes].target_offset =
5803 target - base_vma;
99059e56
RM		 5804 a8_fixes[num_a8_fixes].orig_insn = insn;
5805 a8_fixes[num_a8_fixes].stub_name = stub_name;
5806 a8_fixes[num_a8_fixes].stub_type = stub_type;
5807 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5808 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5809
99059e56
RM		 5810 num_a8_fixes++;
5811 }
5812 }
5813 }
48229727 5814
99059e56
RM		 5815 i += insn_32bit ? 4 : 2;
5816 last_was_32bit = insn_32bit;
48229727 5817 last_was_branch = is_32bit_branch;
99059e56
RM		 5818 }
5819 }
48229727
JB		 5820
5821 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5822 free (contents);
48229727 5823 }
fe33d2fa 5824
48229727
JB		 5825 *a8_fixes_p = a8_fixes;
5826 *num_a8_fixes_p = num_a8_fixes;
5827 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5828
81694485 5829 return FALSE;
48229727
JB		 5830}
5831
b715f643
TP		 5832/* Create or update a stub entry depending on whether the stub can already be
5833 found in HTAB. The stub is identified by:
5834 - its type STUB_TYPE
5835 - its source branch (note that several can share the same stub) whose
5836 section and relocation (if any) are given by SECTION and IRELA
5837 respectively
5838 - its target symbol whose input section, hash, name, value and branch type
5839 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5840 respectively
5841
5842 If found, the value of the stub's target symbol is updated from SYM_VALUE
5843 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5844 TRUE and the stub entry is initialized.
5845
0955507f
TP		 5846 Returns the stub that was created or updated, or NULL if an error
5847 occurred. */
b715f643 5848
0955507f 5849static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5850elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5851 enum elf32_arm_stub_type stub_type, asection *section,
5852 Elf_Internal_Rela *irela, asection *sym_sec,
5853 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5854 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5855 bfd_boolean *new_stub)
5856{
5857 const asection *id_sec;
5858 char *stub_name;
5859 struct elf32_arm_stub_hash_entry *stub_entry;
5860 unsigned int r_type;
4f4faa4d 5861 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5862
5863 BFD_ASSERT (stub_type != arm_stub_none);
5864 *new_stub = FALSE;
5865
4f4faa4d
TP		 5866 if (sym_claimed)
5867 stub_name = sym_name;
5868 else
5869 {
5870 BFD_ASSERT (irela);
5871 BFD_ASSERT (section);
c2abbbeb 5872 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5873
4f4faa4d
TP		 5874 /* Support for grouping stub sections. */
5875 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5876
4f4faa4d
TP		 5877 /* Get the name of this stub. */
5878 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5879 stub_type);
5880 if (!stub_name)
0955507f 5881 return NULL;
4f4faa4d 5882 }
b715f643
TP		 5883
5884 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5885 FALSE);
5886 /* The proper stub has already been created, just update its value. */
5887 if (stub_entry != NULL)
5888 {
4f4faa4d
TP		 5889 if (!sym_claimed)
5890 free (stub_name);
b715f643 5891 stub_entry->target_value = sym_value;
0955507f 5892 return stub_entry;
b715f643
TP		 5893 }
5894
daa4adae 5895 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5896 if (stub_entry == NULL)
5897 {
4f4faa4d
TP		 5898 if (!sym_claimed)
5899 free (stub_name);
0955507f 5900 return NULL;
b715f643
TP		 5901 }
5902
5903 stub_entry->target_value = sym_value;
5904 stub_entry->target_section = sym_sec;
5905 stub_entry->stub_type = stub_type;
5906 stub_entry->h = hash;
5907 stub_entry->branch_type = branch_type;
5908
4f4faa4d
TP		 5909 if (sym_claimed)
5910 stub_entry->output_name = sym_name;
5911 else
b715f643 5912 {
4f4faa4d
TP		 5913 if (sym_name == NULL)
5914 sym_name = "unnamed";
5915 stub_entry->output_name = (char *)
5916 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5917 + strlen (sym_name));
5918 if (stub_entry->output_name == NULL)
5919 {
5920 free (stub_name);
0955507f 5921 return NULL;
4f4faa4d 5922 }
b715f643 5923
4f4faa4d
TP		 5924 /* For historical reasons, use the existing names for ARM-to-Thumb and
5925 Thumb-to-ARM stubs. */
5926 r_type = ELF32_R_TYPE (irela->r_info);
5927 if ((r_type == (unsigned int) R_ARM_THM_CALL
5928 || r_type == (unsigned int) R_ARM_THM_JUMP24
5929 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5930 && branch_type == ST_BRANCH_TO_ARM)
5931 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5932 else if ((r_type == (unsigned int) R_ARM_CALL
5933 || r_type == (unsigned int) R_ARM_JUMP24)
5934 && branch_type == ST_BRANCH_TO_THUMB)
5935 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5936 else
5937 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5938 }
b715f643
TP		 5939
5940 *new_stub = TRUE;
0955507f 5941 return stub_entry;
b715f643
TP		 5942}
5943
4ba2ef8f
TP		 5944/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5945 gateway veneer to transition from non secure to secure state and create them
5946 accordingly.
5947
5948 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5949 defines the conditions that govern Secure Gateway veneer creation for a
5950 given symbol <SYM> as follows:
5951 - it has function type
5952 - it has non local binding
5953 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5954 same type, binding and value as <SYM> (called normal symbol).
5955 An entry function can handle secure state transition itself in which case
5956 its special symbol would have a different value from the normal symbol.
5957
5958 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5959 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5960 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5961 created.
4ba2ef8f 5962
0955507f 5963 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5964
5965static bfd_boolean
5966cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5967 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5968 int *cmse_stub_created)
4ba2ef8f
TP		 5969{
5970 const struct elf_backend_data *bed;
5971 Elf_Internal_Shdr *symtab_hdr;
5972 unsigned i, j, sym_count, ext_start;
5973 Elf_Internal_Sym *cmse_sym, *local_syms;
5974 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5975 enum arm_st_branch_type branch_type;
5976 char *sym_name, *lsym_name;
5977 bfd_vma sym_value;
5978 asection *section;
0955507f
TP		 5979 struct elf32_arm_stub_hash_entry *stub_entry;
5980 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5981
5982 bed = get_elf_backend_data (input_bfd);
5983 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5984 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5985 ext_start = symtab_hdr->sh_info;
5986 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5987 && out_attr[Tag_CPU_arch_profile].i == 'M');
5988
5989 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5990 if (local_syms == NULL)
5991 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5992 symtab_hdr->sh_info, 0, NULL, NULL,
5993 NULL);
5994 if (symtab_hdr->sh_info && local_syms == NULL)
5995 return FALSE;
5996
5997 /* Scan symbols. */
5998 for (i = 0; i < sym_count; i++)
5999 {
6000 cmse_invalid = FALSE;
6001
6002 if (i < ext_start)
6003 {
6004 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 6005 sym_name = bfd_elf_string_from_elf_section (input_bfd,
6006 symtab_hdr->sh_link,
6007 cmse_sym->st_name);
baf46cd7
AM		 6008 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
6009 continue;
6010
4ba2ef8f
TP		 6011 /* Special symbol with local binding. */
6012 cmse_invalid = TRUE;
6013 }
6014 else
6015 {
6016 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
6017 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 6018 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 6019 continue;
6020
6021 /* Special symbol has incorrect binding or type. */
6022 if ((cmse_hash->root.root.type != bfd_link_hash_defined
6023 && cmse_hash->root.root.type != bfd_link_hash_defweak)
6024 || cmse_hash->root.type != STT_FUNC)
6025 cmse_invalid = TRUE;
6026 }
6027
6028 if (!is_v8m)
6029 {
90b6238f
AM		 6030 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
6031 "ARMv8-M architecture or later"),
4eca0228 6032 input_bfd, sym_name);
4ba2ef8f
TP		 6033 is_v8m = TRUE; /* Avoid multiple warning. */
6034 ret = FALSE;
6035 }
6036
6037 if (cmse_invalid)
6038 {
90b6238f
AM		 6039 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6040 " a global or weak function symbol"),
4eca0228 6041 input_bfd, sym_name);
4ba2ef8f
TP		 6042 ret = FALSE;
6043 if (i < ext_start)
6044 continue;
6045 }
6046
6047 sym_name += strlen (CMSE_PREFIX);
6048 hash = (struct elf32_arm_link_hash_entry *)
6049 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6050
6051 /* No associated normal symbol or it is neither global nor weak. */
6052 if (!hash
6053 || (hash->root.root.type != bfd_link_hash_defined
6054 && hash->root.root.type != bfd_link_hash_defweak)
6055 || hash->root.type != STT_FUNC)
6056 {
6057 /* Initialize here to avoid warning about use of possibly
6058 uninitialized variable. */
6059 j = 0;
6060
6061 if (!hash)
6062 {
6063 /* Searching for a normal symbol with local binding. */
6064 for (; j < ext_start; j++)
6065 {
6066 lsym_name =
6067 bfd_elf_string_from_elf_section (input_bfd,
6068 symtab_hdr->sh_link,
6069 local_syms[j].st_name);
6070 if (!strcmp (sym_name, lsym_name))
6071 break;
6072 }
6073 }
6074
6075 if (hash || j < ext_start)
6076 {
4eca0228 6077 _bfd_error_handler
90b6238f
AM		 6078 (_("%pB: invalid standard symbol `%s'; it must be "
6079 "a global or weak function symbol"),
6080 input_bfd, sym_name);
4ba2ef8f
TP		 6081 }
6082 else
4eca0228 6083 _bfd_error_handler
90b6238f 6084 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6085 ret = FALSE;
6086 if (!hash)
6087 continue;
6088 }
6089
6090 sym_value = hash->root.root.u.def.value;
6091 section = hash->root.root.u.def.section;
6092
6093 if (cmse_hash->root.root.u.def.section != section)
6094 {
4eca0228 6095 _bfd_error_handler
90b6238f 6096 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6097 input_bfd, sym_name);
6098 ret = FALSE;
6099 }
6100 if (cmse_hash->root.root.u.def.value != sym_value)
6101 continue; /* Ignore: could be an entry function starting with SG. */
6102
6103 /* If this section is a link-once section that will be discarded, then
6104 don't create any stubs. */
6105 if (section->output_section == NULL)
6106 {
4eca0228 6107 _bfd_error_handler
90b6238f 6108 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6109 continue;
6110 }
6111
6112 if (hash->root.size == 0)
6113 {
4eca0228 6114 _bfd_error_handler
90b6238f 6115 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6116 ret = FALSE;
6117 }
6118
6119 if (!ret)
6120 continue;
6121 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6122 stub_entry
4ba2ef8f
TP		 6123 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6124 NULL, NULL, section, hash, sym_name,
6125 sym_value, branch_type, &new_stub);
6126
0955507f 6127 if (stub_entry == NULL)
4ba2ef8f
TP		 6128 ret = FALSE;
6129 else
6130 {
6131 BFD_ASSERT (new_stub);
0955507f 6132 (*cmse_stub_created)++;
4ba2ef8f
TP		 6133 }
6134 }
6135
6136 if (!symtab_hdr->contents)
6137 free (local_syms);
6138 return ret;
6139}
6140
0955507f
TP		 6141/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6142 code entry function, ie can be called from non secure code without using a
6143 veneer. */
6144
6145static bfd_boolean
6146cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6147{
42484486 6148 bfd_byte contents[4];
0955507f
TP		 6149 uint32_t first_insn;
6150 asection *section;
6151 file_ptr offset;
6152 bfd *abfd;
6153
6154 /* Defined symbol of function type. */
6155 if (hash->root.root.type != bfd_link_hash_defined
6156 && hash->root.root.type != bfd_link_hash_defweak)
6157 return FALSE;
6158 if (hash->root.type != STT_FUNC)
6159 return FALSE;
6160
6161 /* Read first instruction. */
6162 section = hash->root.root.u.def.section;
6163 abfd = section->owner;
6164 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6165 if (!bfd_get_section_contents (abfd, section, contents, offset,
6166 sizeof (contents)))
0955507f
TP		 6167 return FALSE;
6168
42484486
TP		 6169 first_insn = bfd_get_32 (abfd, contents);
6170
6171 /* Starts by SG instruction. */
0955507f
TP		 6172 return first_insn == 0xe97fe97f;
6173}
6174
6175/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6176 secure gateway veneers (ie. the veneers was not in the input import library)
6177 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6178
6179static bfd_boolean
6180arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6181{
6182 struct elf32_arm_stub_hash_entry *stub_entry;
6183 struct bfd_link_info *info;
6184
6185 /* Massage our args to the form they really have. */
6186 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6187 info = (struct bfd_link_info *) gen_info;
6188
6189 if (info->out_implib_bfd)
6190 return TRUE;
6191
6192 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6193 return TRUE;
6194
6195 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6196 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6197
6198 return TRUE;
6199}
6200
6201/* Set offset of each secure gateway veneers so that its address remain
6202 identical to the one in the input import library referred by
6203 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6204 (present in input import library but absent from the executable being
6205 linked) or if new veneers appeared and there is no output import library
6206 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6207 number of secure gateway veneers found in the input import library.
6208
6209 The function returns whether an error occurred. If no error occurred,
6210 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6211 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6212 veneer observed set for new veneers to be layed out after. */
6213
6214static bfd_boolean
6215set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6216 struct elf32_arm_link_hash_table *htab,
6217 int *cmse_stub_created)
6218{
6219 long symsize;
6220 char *sym_name;
6221 flagword flags;
6222 long i, symcount;
6223 bfd *in_implib_bfd;
6224 asection *stub_out_sec;
6225 bfd_boolean ret = TRUE;
6226 Elf_Internal_Sym *intsym;
6227 const char *out_sec_name;
6228 bfd_size_type cmse_stub_size;
6229 asymbol **sympp = NULL, *sym;
6230 struct elf32_arm_link_hash_entry *hash;
6231 const insn_sequence *cmse_stub_template;
6232 struct elf32_arm_stub_hash_entry *stub_entry;
6233 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6234 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6235 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6236
6237 /* No input secure gateway import library. */
6238 if (!htab->in_implib_bfd)
6239 return TRUE;
6240
6241 in_implib_bfd = htab->in_implib_bfd;
6242 if (!htab->cmse_implib)
6243 {
871b3ab2 6244 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6245 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6246 return FALSE;
6247 }
6248
6249 /* Get symbol table size. */
6250 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6251 if (symsize < 0)
6252 return FALSE;
6253
6254 /* Read in the input secure gateway import library's symbol table. */
6255 sympp = (asymbol **) xmalloc (symsize);
6256 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6257 if (symcount < 0)
6258 {
6259 ret = FALSE;
6260 goto free_sym_buf;
6261 }
6262
6263 htab->new_cmse_stub_offset = 0;
6264 cmse_stub_size =
6265 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6266 &cmse_stub_template,
6267 &cmse_stub_template_size);
6268 out_sec_name =
6269 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6270 stub_out_sec =
6271 bfd_get_section_by_name (htab->obfd, out_sec_name);
6272 if (stub_out_sec != NULL)
6273 cmse_stub_sec_vma = stub_out_sec->vma;
6274
6275 /* Set addresses of veneers mentionned in input secure gateway import
6276 library's symbol table. */
6277 for (i = 0; i < symcount; i++)
6278 {
6279 sym = sympp[i];
6280 flags = sym->flags;
6281 sym_name = (char *) bfd_asymbol_name (sym);
6282 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6283
6284 if (sym->section != bfd_abs_section_ptr
6285 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6286 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6287 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6288 != ST_BRANCH_TO_THUMB))
6289 {
90b6238f
AM		 6290 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6291 "symbol should be absolute, global and "
6292 "refer to Thumb functions"),
4eca0228 6293 in_implib_bfd, sym_name);
0955507f
TP		 6294 ret = FALSE;
6295 continue;
6296 }
6297
6298 veneer_value = bfd_asymbol_value (sym);
6299 stub_offset = veneer_value - cmse_stub_sec_vma;
6300 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6301 FALSE, FALSE);
6302 hash = (struct elf32_arm_link_hash_entry *)
6303 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6304
6305 /* Stub entry should have been created by cmse_scan or the symbol be of
6306 a secure function callable from non secure code. */
6307 if (!stub_entry && !hash)
6308 {
6309 bfd_boolean new_stub;
6310
4eca0228 6311 _bfd_error_handler
90b6238f 6312 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6313 hash = (struct elf32_arm_link_hash_entry *)
6314 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6315 stub_entry
6316 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6317 NULL, NULL, bfd_abs_section_ptr, hash,
6318 sym_name, veneer_value,
6319 ST_BRANCH_TO_THUMB, &new_stub);
6320 if (stub_entry == NULL)
6321 ret = FALSE;
6322 else
6323 {
6324 BFD_ASSERT (new_stub);
6325 new_cmse_stubs_created++;
6326 (*cmse_stub_created)++;
6327 }
6328 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6329 stub_entry->stub_offset = stub_offset;
6330 }
6331 /* Symbol found is not callable from non secure code. */
6332 else if (!stub_entry)
6333 {
6334 if (!cmse_entry_fct_p (hash))
6335 {
90b6238f 6336 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6337 sym_name);
0955507f
TP		 6338 ret = FALSE;
6339 }
6340 continue;
6341 }
6342 else
6343 {
6344 /* Only stubs for SG veneers should have been created. */
6345 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6346
6347 /* Check visibility hasn't changed. */
6348 if (!!(flags & BSF_GLOBAL)
6349 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6350 _bfd_error_handler
90b6238f 6351 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6352 sym_name);
6353
6354 stub_entry->stub_offset = stub_offset;
6355 }
6356
6357 /* Size should match that of a SG veneer. */
6358 if (intsym->st_size != cmse_stub_size)
6359 {
90b6238f 6360 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6361 in_implib_bfd, sym_name);
0955507f
TP		 6362 ret = FALSE;
6363 }
6364
6365 /* Previous veneer address is before current SG veneer section. */
6366 if (veneer_value < cmse_stub_sec_vma)
6367 {
6368 /* Avoid offset underflow. */
6369 if (stub_entry)
6370 stub_entry->stub_offset = 0;
6371 stub_offset = 0;
6372 ret = FALSE;
6373 }
6374
6375 /* Complain if stub offset not a multiple of stub size. */
6376 if (stub_offset % cmse_stub_size)
6377 {
4eca0228 6378 _bfd_error_handler
90b6238f
AM		 6379 (_("offset of veneer for entry function `%s' not a multiple of "
6380 "its size"), sym_name);
0955507f
TP		 6381 ret = FALSE;
6382 }
6383
6384 if (!ret)
6385 continue;
6386
6387 new_cmse_stubs_created--;
6388 if (veneer_value < cmse_stub_array_start)
6389 cmse_stub_array_start = veneer_value;
6390 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6391 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6392 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6393 }
6394
6395 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6396 {
6397 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6398 _bfd_error_handler
0955507f
TP		 6399 (_("new entry function(s) introduced but no output import library "
6400 "specified:"));
6401 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6402 }
6403
6404 if (cmse_stub_array_start != cmse_stub_sec_vma)
6405 {
4eca0228 6406 _bfd_error_handler
90b6238f 6407 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6408 out_sec_name);
6409 ret = FALSE;
6410 }
6411
6412free_sym_buf:
6413 free (sympp);
6414 return ret;
6415}
6416
906e58ca
NC		 6417/* Determine and set the size of the stub section for a final link.
6418
6419 The basic idea here is to examine all the relocations looking for
6420 PC-relative calls to a target that is unreachable with a "bl"
6421 instruction. */
6422
6423bfd_boolean
6424elf32_arm_size_stubs (bfd *output_bfd,
6425 bfd *stub_bfd,
6426 struct bfd_link_info *info,
6427 bfd_signed_vma group_size,
7a89b94e 6428 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6429 asection *,
7a89b94e 6430 unsigned int),
906e58ca
NC		 6431 void (*layout_sections_again) (void))
6432{
0955507f 6433 bfd_boolean ret = TRUE;
4ba2ef8f 6434 obj_attribute *out_attr;
0955507f 6435 int cmse_stub_created = 0;
906e58ca 6436 bfd_size_type stub_group_size;
4ba2ef8f 6437 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6438 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6439 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6440 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6441 struct a8_erratum_reloc *a8_relocs = NULL;
6442 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6443
4dfe6ac6
NC		 6444 if (htab == NULL)
6445 return FALSE;
6446
48229727
JB		 6447 if (htab->fix_cortex_a8)
6448 {
21d799b5 6449 a8_fixes = (struct a8_erratum_fix *)
99059e56 6450 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6451 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6452 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6453 }
906e58ca
NC		 6454
6455 /* Propagate mach to stub bfd, because it may not have been
6456 finalized when we created stub_bfd. */
6457 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6458 bfd_get_mach (output_bfd));
6459
6460 /* Stash our params away. */
6461 htab->stub_bfd = stub_bfd;
6462 htab->add_stub_section = add_stub_section;
6463 htab->layout_sections_again = layout_sections_again;
07d72278 6464 stubs_always_after_branch = group_size < 0;
48229727 6465
4ba2ef8f
TP		 6466 out_attr = elf_known_obj_attributes_proc (output_bfd);
6467 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6468
48229727
JB		 6469 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6470 as the first half of a 32-bit branch straddling two 4K pages. This is a
6471 crude way of enforcing that. */
6472 if (htab->fix_cortex_a8)
6473 stubs_always_after_branch = 1;
6474
906e58ca
NC		 6475 if (group_size < 0)
6476 stub_group_size = -group_size;
6477 else
6478 stub_group_size = group_size;
6479
6480 if (stub_group_size == 1)
6481 {
6482 /* Default values. */
6483 /* Thumb branch range is +-4MB has to be used as the default
6484 maximum size (a given section can contain both ARM and Thumb
6485 code, so the worst case has to be taken into account).
6486
6487 This value is 24K less than that, which allows for 2025
6488 12-byte stubs. If we exceed that, then we will fail to link.
6489 The user will have to relink with an explicit group size
6490 option. */
6491 stub_group_size = 4170000;
6492 }
6493
07d72278 6494 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6495
3ae046cc
NS		 6496 /* If we're applying the cortex A8 fix, we need to determine the
6497 program header size now, because we cannot change it later --
6498 that could alter section placements. Notice the A8 erratum fix
6499 ends up requiring the section addresses to remain unchanged
6500 modulo the page size. That's something we cannot represent
6501 inside BFD, and we don't want to force the section alignment to
6502 be the page size. */
6503 if (htab->fix_cortex_a8)
6504 (*htab->layout_sections_again) ();
6505
906e58ca
NC		 6506 while (1)
6507 {
6508 bfd *input_bfd;
6509 unsigned int bfd_indx;
6510 asection *stub_sec;
d7c5bd02 6511 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6512 bfd_boolean stub_changed = FALSE;
6513 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6514
48229727 6515 num_a8_fixes = 0;
906e58ca
NC		 6516 for (input_bfd = info->input_bfds, bfd_indx = 0;
6517 input_bfd != NULL;
c72f2fb2 6518 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6519 {
6520 Elf_Internal_Shdr *symtab_hdr;
6521 asection *section;
6522 Elf_Internal_Sym *local_syms = NULL;
6523
8c246a60
AM		 6524 if (!is_arm_elf (input_bfd)
6525 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0)
99059e56 6526 continue;
adbcc655 6527
48229727
JB		 6528 num_a8_relocs = 0;
6529
906e58ca
NC		 6530 /* We'll need the symbol table in a second. */
6531 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6532 if (symtab_hdr->sh_info == 0)
6533 continue;
6534
4ba2ef8f
TP		 6535 /* Limit scan of symbols to object file whose profile is
6536 Microcontroller to not hinder performance in the general case. */
6537 if (m_profile && first_veneer_scan)
6538 {
6539 struct elf_link_hash_entry **sym_hashes;
6540
6541 sym_hashes = elf_sym_hashes (input_bfd);
6542 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6543 &cmse_stub_created))
4ba2ef8f 6544 goto error_ret_free_local;
0955507f
TP		 6545
6546 if (cmse_stub_created != 0)
6547 stub_changed = TRUE;
4ba2ef8f
TP		 6548 }
6549
906e58ca
NC		 6550 /* Walk over each section attached to the input bfd. */
6551 for (section = input_bfd->sections;
6552 section != NULL;
6553 section = section->next)
6554 {
6555 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6556
6557 /* If there aren't any relocs, then there's nothing more
6558 to do. */
6559 if ((section->flags & SEC_RELOC) == 0
6560 || section->reloc_count == 0
6561 || (section->flags & SEC_CODE) == 0)
6562 continue;
6563
6564 /* If this section is a link-once section that will be
6565 discarded, then don't create any stubs. */
6566 if (section->output_section == NULL
6567 || section->output_section->owner != output_bfd)
6568 continue;
6569
6570 /* Get the relocs. */
6571 internal_relocs
6572 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6573 NULL, info->keep_memory);
6574 if (internal_relocs == NULL)
6575 goto error_ret_free_local;
6576
6577 /* Now examine each relocation. */
6578 irela = internal_relocs;
6579 irelaend = irela + section->reloc_count;
6580 for (; irela < irelaend; irela++)
6581 {
6582 unsigned int r_type, r_indx;
906e58ca
NC		 6583 asection *sym_sec;
6584 bfd_vma sym_value;
6585 bfd_vma destination;
6586 struct elf32_arm_link_hash_entry *hash;
7413f23f 6587 const char *sym_name;
34e77a92 6588 unsigned char st_type;
35fc36a8 6589 enum arm_st_branch_type branch_type;
48229727 6590 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6591
6592 r_type = ELF32_R_TYPE (irela->r_info);
6593 r_indx = ELF32_R_SYM (irela->r_info);
6594
6595 if (r_type >= (unsigned int) R_ARM_max)
6596 {
6597 bfd_set_error (bfd_error_bad_value);
6598 error_ret_free_internal:
6599 if (elf_section_data (section)->relocs == NULL)
6600 free (internal_relocs);
15dd01b1
TP		 6601 /* Fall through. */
6602 error_ret_free_local:
6603 if (local_syms != NULL
6604 && (symtab_hdr->contents
6605 != (unsigned char *) local_syms))
6606 free (local_syms);
6607 return FALSE;
906e58ca 6608 }
b38cadfb 6609
0855e32b
NS		 6610 hash = NULL;
6611 if (r_indx >= symtab_hdr->sh_info)
6612 hash = elf32_arm_hash_entry
6613 (elf_sym_hashes (input_bfd)
6614 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6615
0855e32b
NS		 6616 /* Only look for stubs on branch instructions, or
6617 non-relaxed TLSCALL */
906e58ca 6618 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6619 && (r_type != (unsigned int) R_ARM_THM_CALL)
6620 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6621 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6622 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6623 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6624 && (r_type != (unsigned int) R_ARM_PLT32)
6625 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6626 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6627 && r_type == elf32_arm_tls_transition
6628 (info, r_type, &hash->root)
6629 && ((hash ? hash->tls_type
6630 : (elf32_arm_local_got_tls_type
6631 (input_bfd)[r_indx]))
6632 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6633 continue;
6634
6635 /* Now determine the call target, its name, value,
6636 section. */
6637 sym_sec = NULL;
6638 sym_value = 0;
6639 destination = 0;
7413f23f 6640 sym_name = NULL;
b38cadfb 6641
0855e32b
NS		 6642 if (r_type == (unsigned int) R_ARM_TLS_CALL
6643 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6644 {
6645 /* A non-relaxed TLS call. The target is the
6646 plt-resident trampoline and nothing to do
6647 with the symbol. */
6648 BFD_ASSERT (htab->tls_trampoline > 0);
6649 sym_sec = htab->root.splt;
6650 sym_value = htab->tls_trampoline;
6651 hash = 0;
34e77a92 6652 st_type = STT_FUNC;
35fc36a8 6653 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6654 }
6655 else if (!hash)
906e58ca
NC		 6656 {
6657 /* It's a local symbol. */
6658 Elf_Internal_Sym *sym;
906e58ca
NC		 6659
6660 if (local_syms == NULL)
6661 {
6662 local_syms
6663 = (Elf_Internal_Sym *) symtab_hdr->contents;
6664 if (local_syms == NULL)
6665 local_syms
6666 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6667 symtab_hdr->sh_info, 0,
6668 NULL, NULL, NULL);
6669 if (local_syms == NULL)
6670 goto error_ret_free_internal;
6671 }
6672
6673 sym = local_syms + r_indx;
f6d250ce
TS		 6674 if (sym->st_shndx == SHN_UNDEF)
6675 sym_sec = bfd_und_section_ptr;
6676 else if (sym->st_shndx == SHN_ABS)
6677 sym_sec = bfd_abs_section_ptr;
6678 else if (sym->st_shndx == SHN_COMMON)
6679 sym_sec = bfd_com_section_ptr;
6680 else
6681 sym_sec =
6682 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6683
ffcb4889
NS		 6684 if (!sym_sec)
6685 /* This is an undefined symbol. It can never
6a631e86 6686 be resolved. */
ffcb4889 6687 continue;
fe33d2fa 6688
906e58ca
NC		 6689 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6690 sym_value = sym->st_value;
6691 destination = (sym_value + irela->r_addend
6692 + sym_sec->output_offset
6693 + sym_sec->output_section->vma);
34e77a92 6694 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6695 branch_type =
6696 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6697 sym_name
6698 = bfd_elf_string_from_elf_section (input_bfd,
6699 symtab_hdr->sh_link,
6700 sym->st_name);
906e58ca
NC		 6701 }
6702 else
6703 {
6704 /* It's an external symbol. */
906e58ca
NC		 6705 while (hash->root.root.type == bfd_link_hash_indirect
6706 || hash->root.root.type == bfd_link_hash_warning)
6707 hash = ((struct elf32_arm_link_hash_entry *)
6708 hash->root.root.u.i.link);
6709
6710 if (hash->root.root.type == bfd_link_hash_defined
6711 || hash->root.root.type == bfd_link_hash_defweak)
6712 {
6713 sym_sec = hash->root.root.u.def.section;
6714 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6715
6716 struct elf32_arm_link_hash_table *globals =
6717 elf32_arm_hash_table (info);
6718
6719 /* For a destination in a shared library,
6720 use the PLT stub as target address to
6721 decide whether a branch stub is
6722 needed. */
4dfe6ac6 6723 if (globals != NULL
362d30a1 6724 && globals->root.splt != NULL
4dfe6ac6 6725 && hash != NULL
022f8312
CL		 6726 && hash->root.plt.offset != (bfd_vma) -1)
6727 {
362d30a1 6728 sym_sec = globals->root.splt;
022f8312
CL		 6729 sym_value = hash->root.plt.offset;
6730 if (sym_sec->output_section != NULL)
6731 destination = (sym_value
6732 + sym_sec->output_offset
6733 + sym_sec->output_section->vma);
6734 }
6735 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6736 destination = (sym_value + irela->r_addend
6737 + sym_sec->output_offset
6738 + sym_sec->output_section->vma);
6739 }
69c5861e
CL		 6740 else if ((hash->root.root.type == bfd_link_hash_undefined)
6741 || (hash->root.root.type == bfd_link_hash_undefweak))
6742 {
6743 /* For a shared library, use the PLT stub as
6744 target address to decide whether a long
6745 branch stub is needed.
6746 For absolute code, they cannot be handled. */
6747 struct elf32_arm_link_hash_table *globals =
6748 elf32_arm_hash_table (info);
6749
4dfe6ac6 6750 if (globals != NULL
362d30a1 6751 && globals->root.splt != NULL
4dfe6ac6 6752 && hash != NULL
69c5861e
CL		 6753 && hash->root.plt.offset != (bfd_vma) -1)
6754 {
362d30a1 6755 sym_sec = globals->root.splt;
69c5861e
CL		 6756 sym_value = hash->root.plt.offset;
6757 if (sym_sec->output_section != NULL)
6758 destination = (sym_value
6759 + sym_sec->output_offset
6760 + sym_sec->output_section->vma);
6761 }
6762 else
6763 continue;
6764 }
906e58ca
NC		 6765 else
6766 {
6767 bfd_set_error (bfd_error_bad_value);
6768 goto error_ret_free_internal;
6769 }
34e77a92 6770 st_type = hash->root.type;
39d911fc
TP		 6771 branch_type =
6772 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6773 sym_name = hash->root.root.root.string;
906e58ca
NC		 6774 }
6775
48229727 6776 do
7413f23f 6777 {
b715f643 6778 bfd_boolean new_stub;
0955507f 6779 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6780
48229727
JB		 6781 /* Determine what (if any) linker stub is needed. */
6782 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6783 st_type, &branch_type,
6784 hash, destination, sym_sec,
48229727
JB		 6785 input_bfd, sym_name);
6786 if (stub_type == arm_stub_none)
6787 break;
6788
48229727
JB		 6789 /* We've either created a stub for this reloc already,
6790 or we are about to. */
0955507f 6791 stub_entry =
b715f643
TP		 6792 elf32_arm_create_stub (htab, stub_type, section, irela,
6793 sym_sec, hash,
6794 (char *) sym_name, sym_value,
6795 branch_type, &new_stub);
7413f23f 6796
0955507f 6797 created_stub = stub_entry != NULL;
b715f643
TP		 6798 if (!created_stub)
6799 goto error_ret_free_internal;
6800 else if (!new_stub)
6801 break;
99059e56 6802 else
b715f643 6803 stub_changed = TRUE;
99059e56
RM		 6804 }
6805 while (0);
6806
6807 /* Look for relocations which might trigger Cortex-A8
6808 erratum. */
6809 if (htab->fix_cortex_a8
6810 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6811 || r_type == (unsigned int) R_ARM_THM_JUMP19
6812 || r_type == (unsigned int) R_ARM_THM_CALL
6813 || r_type == (unsigned int) R_ARM_THM_XPC22))
6814 {
6815 bfd_vma from = section->output_section->vma
6816 + section->output_offset
6817 + irela->r_offset;
6818
6819 if ((from & 0xfff) == 0xffe)
6820 {
6821 /* Found a candidate. Note we haven't checked the
6822 destination is within 4K here: if we do so (and
6823 don't create an entry in a8_relocs) we can't tell
6824 that a branch should have been relocated when
6825 scanning later. */
6826 if (num_a8_relocs == a8_reloc_table_size)
6827 {
6828 a8_reloc_table_size *= 2;
6829 a8_relocs = (struct a8_erratum_reloc *)
6830 bfd_realloc (a8_relocs,
6831 sizeof (struct a8_erratum_reloc)
6832 * a8_reloc_table_size);
6833 }
6834
6835 a8_relocs[num_a8_relocs].from = from;
6836 a8_relocs[num_a8_relocs].destination = destination;
6837 a8_relocs[num_a8_relocs].r_type = r_type;
6838 a8_relocs[num_a8_relocs].branch_type = branch_type;
6839 a8_relocs[num_a8_relocs].sym_name = sym_name;
6840 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6841 a8_relocs[num_a8_relocs].hash = hash;
6842
6843 num_a8_relocs++;
6844 }
6845 }
906e58ca
NC		 6846 }
6847
99059e56
RM		 6848 /* We're done with the internal relocs, free them. */
6849 if (elf_section_data (section)->relocs == NULL)
6850 free (internal_relocs);
6851 }
48229727 6852
99059e56 6853 if (htab->fix_cortex_a8)
48229727 6854 {
99059e56
RM		 6855 /* Sort relocs which might apply to Cortex-A8 erratum. */
6856 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6857 sizeof (struct a8_erratum_reloc),
99059e56 6858 &a8_reloc_compare);
48229727 6859
99059e56
RM		 6860 /* Scan for branches which might trigger Cortex-A8 erratum. */
6861 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6862 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6863 a8_relocs, num_a8_relocs,
6864 prev_num_a8_fixes, &stub_changed)
6865 != 0)
48229727 6866 goto error_ret_free_local;
5e681ec4 6867 }
7f991970
AM		 6868
6869 if (local_syms != NULL
6870 && symtab_hdr->contents != (unsigned char *) local_syms)
6871 {
6872 if (!info->keep_memory)
6873 free (local_syms);
6874 else
6875 symtab_hdr->contents = (unsigned char *) local_syms;
6876 }
5e681ec4
PB		 6877 }
6878
0955507f
TP		 6879 if (first_veneer_scan
6880 && !set_cmse_veneer_addr_from_implib (info, htab,
6881 &cmse_stub_created))
6882 ret = FALSE;
6883
eb7c4339 6884 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6885 stub_changed = TRUE;
48229727 6886
906e58ca
NC		 6887 if (!stub_changed)
6888 break;
5e681ec4 6889
906e58ca
NC		 6890 /* OK, we've added some stubs. Find out the new size of the
6891 stub sections. */
6892 for (stub_sec = htab->stub_bfd->sections;
6893 stub_sec != NULL;
6894 stub_sec = stub_sec->next)
3e6b1042
DJ		 6895 {
6896 /* Ignore non-stub sections. */
6897 if (!strstr (stub_sec->name, STUB_SUFFIX))
6898 continue;
6899
6900 stub_sec->size = 0;
6901 }
b34b2d70 6902
0955507f
TP		 6903 /* Add new SG veneers after those already in the input import
6904 library. */
6905 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6906 stub_type++)
6907 {
6908 bfd_vma *start_offset_p;
6909 asection **stub_sec_p;
6910
6911 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6912 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6913 if (start_offset_p == NULL)
6914 continue;
6915
6916 BFD_ASSERT (stub_sec_p != NULL);
6917 if (*stub_sec_p != NULL)
6918 (*stub_sec_p)->size = *start_offset_p;
6919 }
6920
d7c5bd02 6921 /* Compute stub section size, considering padding. */
906e58ca 6922 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6923 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6924 stub_type++)
6925 {
6926 int size, padding;
6927 asection **stub_sec_p;
6928
6929 padding = arm_dedicated_stub_section_padding (stub_type);
6930 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6931 /* Skip if no stub input section or no stub section padding
6932 required. */
6933 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6934 continue;
6935 /* Stub section padding required but no dedicated section. */
6936 BFD_ASSERT (stub_sec_p);
6937
6938 size = (*stub_sec_p)->size;
6939 size = (size + padding - 1) & ~(padding - 1);
6940 (*stub_sec_p)->size = size;
6941 }
906e58ca 6942
48229727
JB		 6943 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6944 if (htab->fix_cortex_a8)
99059e56
RM		 6945 for (i = 0; i < num_a8_fixes; i++)
6946 {
48229727 6947 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6948 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6949
6950 if (stub_sec == NULL)
7f991970 6951 return FALSE;
48229727 6952
99059e56
RM		 6953 stub_sec->size
6954 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6955 NULL);
6956 }
48229727
JB		 6957
6958
906e58ca
NC		 6959 /* Ask the linker to do its stuff. */
6960 (*htab->layout_sections_again) ();
4ba2ef8f 6961 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6962 }
6963
48229727
JB		 6964 /* Add stubs for Cortex-A8 erratum fixes now. */
6965 if (htab->fix_cortex_a8)
6966 {
6967 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6968 {
6969 struct elf32_arm_stub_hash_entry *stub_entry;
6970 char *stub_name = a8_fixes[i].stub_name;
6971 asection *section = a8_fixes[i].section;
6972 unsigned int section_id = a8_fixes[i].section->id;
6973 asection *link_sec = htab->stub_group[section_id].link_sec;
6974 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6975 const insn_sequence *template_sequence;
6976 int template_size, size = 0;
6977
6978 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6979 TRUE, FALSE);
6980 if (stub_entry == NULL)
6981 {
871b3ab2 6982 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6983 section->owner, stub_name);
99059e56
RM		 6984 return FALSE;
6985 }
6986
6987 stub_entry->stub_sec = stub_sec;
0955507f 6988 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6989 stub_entry->id_sec = link_sec;
6990 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6991 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6992 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6993 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6994 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6995 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6996
99059e56
RM		 6997 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6998 &template_sequence,
6999 &template_size);
48229727 7000
99059e56
RM		 7001 stub_entry->stub_size = size;
7002 stub_entry->stub_template = template_sequence;
7003 stub_entry->stub_template_size = template_size;
7004 }
48229727
JB		 7005
7006 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 7007 elf32_arm_write_section(). */
48229727
JB		 7008 htab->a8_erratum_fixes = a8_fixes;
7009 htab->num_a8_erratum_fixes = num_a8_fixes;
7010 }
7011 else
7012 {
7013 htab->a8_erratum_fixes = NULL;
7014 htab->num_a8_erratum_fixes = 0;
7015 }
0955507f 7016 return ret;
5e681ec4
PB		 7017}
7018
906e58ca
NC		 7019/* Build all the stubs associated with the current output file. The
7020 stubs are kept in a hash table attached to the main linker hash
7021 table. We also set up the .plt entries for statically linked PIC
7022 functions here. This function is called via arm_elf_finish in the
7023 linker. */
252b5132 7024
906e58ca
NC		 7025bfd_boolean
7026elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 7027{
906e58ca
NC		 7028 asection *stub_sec;
7029 struct bfd_hash_table *table;
0955507f 7030 enum elf32_arm_stub_type stub_type;
906e58ca 7031 struct elf32_arm_link_hash_table *htab;
252b5132 7032
906e58ca 7033 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 7034 if (htab == NULL)
7035 return FALSE;
252b5132 7036
906e58ca
NC		 7037 for (stub_sec = htab->stub_bfd->sections;
7038 stub_sec != NULL;
7039 stub_sec = stub_sec->next)
252b5132 7040 {
906e58ca
NC		 7041 bfd_size_type size;
7042
8029a119 7043 /* Ignore non-stub sections. */
906e58ca
NC		 7044 if (!strstr (stub_sec->name, STUB_SUFFIX))
7045 continue;
7046
d7c5bd02 7047 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7048 must at least be done for stub section requiring padding and for SG
7049 veneers to ensure that a non secure code branching to a removed SG
7050 veneer causes an error. */
906e58ca 7051 size = stub_sec->size;
21d799b5 7052 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7053 if (stub_sec->contents == NULL && size != 0)
7054 return FALSE;
0955507f 7055
906e58ca 7056 stub_sec->size = 0;
252b5132
RH		 7057 }
7058
0955507f
TP		 7059 /* Add new SG veneers after those already in the input import library. */
7060 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7061 {
7062 bfd_vma *start_offset_p;
7063 asection **stub_sec_p;
7064
7065 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7066 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7067 if (start_offset_p == NULL)
7068 continue;
7069
7070 BFD_ASSERT (stub_sec_p != NULL);
7071 if (*stub_sec_p != NULL)
7072 (*stub_sec_p)->size = *start_offset_p;
7073 }
7074
906e58ca
NC		 7075 /* Build the stubs as directed by the stub hash table. */
7076 table = &htab->stub_hash_table;
7077 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7078 if (htab->fix_cortex_a8)
7079 {
7080 /* Place the cortex a8 stubs last. */
7081 htab->fix_cortex_a8 = -1;
7082 bfd_hash_traverse (table, arm_build_one_stub, info);
7083 }
252b5132 7084
906e58ca 7085 return TRUE;
252b5132
RH		 7086}
7087
9b485d32
NC		 7088/* Locate the Thumb encoded calling stub for NAME. */
7089
252b5132 7090static struct elf_link_hash_entry *
57e8b36a
NC		 7091find_thumb_glue (struct bfd_link_info *link_info,
7092 const char *name,
f2a9dd69 7093 char **error_message)
252b5132
RH		 7094{
7095 char *tmp_name;
7096 struct elf_link_hash_entry *hash;
7097 struct elf32_arm_link_hash_table *hash_table;
7098
7099 /* We need a pointer to the armelf specific hash table. */
7100 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7101 if (hash_table == NULL)
7102 return NULL;
252b5132 7103
21d799b5 7104 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7105 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7106
7107 BFD_ASSERT (tmp_name);
7108
7109 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7110
7111 hash = elf_link_hash_lookup
b34976b6 7112 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7113
b1657152 7114 if (hash == NULL
90b6238f
AM		 7115 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7116 "Thumb", tmp_name, name) == -1)
b1657152 7117 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7118
7119 free (tmp_name);
7120
7121 return hash;
7122}
7123
9b485d32
NC		 7124/* Locate the ARM encoded calling stub for NAME. */
7125
252b5132 7126static struct elf_link_hash_entry *
57e8b36a
NC		 7127find_arm_glue (struct bfd_link_info *link_info,
7128 const char *name,
f2a9dd69 7129 char **error_message)
252b5132
RH		 7130{
7131 char *tmp_name;
7132 struct elf_link_hash_entry *myh;
7133 struct elf32_arm_link_hash_table *hash_table;
7134
7135 /* We need a pointer to the elfarm specific hash table. */
7136 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7137 if (hash_table == NULL)
7138 return NULL;
252b5132 7139
21d799b5 7140 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7141 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7142
7143 BFD_ASSERT (tmp_name);
7144
7145 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7146
7147 myh = elf_link_hash_lookup
b34976b6 7148 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7149
b1657152 7150 if (myh == NULL
90b6238f
AM		 7151 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7152 "ARM", tmp_name, name) == -1)
b1657152 7153 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7154
7155 free (tmp_name);
7156
7157 return myh;
7158}
7159
8f6277f5 7160/* ARM->Thumb glue (static images):
252b5132
RH		 7161
7162 .arm
7163 __func_from_arm:
7164 ldr r12, __func_addr
7165 bx r12
7166 __func_addr:
906e58ca 7167 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7168
26079076
PB		 7169 (v5t static images)
7170 .arm
7171 __func_from_arm:
7172 ldr pc, __func_addr
7173 __func_addr:
906e58ca 7174 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7175
8f6277f5
PB		 7176 (relocatable images)
7177 .arm
7178 __func_from_arm:
7179 ldr r12, __func_offset
7180 add r12, r12, pc
7181 bx r12
7182 __func_offset:
8029a119 7183 .word func - . */
8f6277f5
PB		 7184
7185#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7186static const insn32 a2t1_ldr_insn = 0xe59fc000;
7187static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7188static const insn32 a2t3_func_addr_insn = 0x00000001;
7189
26079076
PB		 7190#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7191static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7192static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7193
8f6277f5
PB		 7194#define ARM2THUMB_PIC_GLUE_SIZE 16
7195static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7196static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7197static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7198
07d6d2b8 7199/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7200
07d6d2b8
AM		 7201 .thumb .thumb
7202 .align 2 .align 2
7203 __func_from_thumb: __func_from_thumb:
7204 bx pc push {r6, lr}
7205 nop ldr r6, __func_addr
7206 .arm mov lr, pc
7207 b func bx r6
99059e56
RM		 7208 .arm
7209 ;; back_to_thumb
7210 ldmia r13! {r6, lr}
7211 bx lr
7212 __func_addr:
07d6d2b8 7213 .word func */
252b5132
RH		 7214
7215#define THUMB2ARM_GLUE_SIZE 8
7216static const insn16 t2a1_bx_pc_insn = 0x4778;
7217static const insn16 t2a2_noop_insn = 0x46c0;
7218static const insn32 t2a3_b_insn = 0xea000000;
7219
c7b8f16e 7220#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7221#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7222#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7223
845b51d6
PB		 7224#define ARM_BX_VENEER_SIZE 12
7225static const insn32 armbx1_tst_insn = 0xe3100001;
7226static const insn32 armbx2_moveq_insn = 0x01a0f000;
7227static const insn32 armbx3_bx_insn = 0xe12fff10;
7228
7e392df6 7229#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7230static void
7231arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7232{
7233 asection * s;
8029a119 7234 bfd_byte * contents;
252b5132 7235
8029a119 7236 if (size == 0)
3e6b1042
DJ		 7237 {
7238 /* Do not include empty glue sections in the output. */
7239 if (abfd != NULL)
7240 {
3d4d4302 7241 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7242 if (s != NULL)
7243 s->flags |= SEC_EXCLUDE;
7244 }
7245 return;
7246 }
252b5132 7247
8029a119 7248 BFD_ASSERT (abfd != NULL);
252b5132 7249
3d4d4302 7250 s = bfd_get_linker_section (abfd, name);
8029a119 7251 BFD_ASSERT (s != NULL);
252b5132 7252
b0f4fbf8 7253 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7254
8029a119
NC		 7255 BFD_ASSERT (s->size == size);
7256 s->contents = contents;
7257}
906e58ca 7258
8029a119
NC		 7259bfd_boolean
7260bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7261{
7262 struct elf32_arm_link_hash_table * globals;
906e58ca 7263
8029a119
NC		 7264 globals = elf32_arm_hash_table (info);
7265 BFD_ASSERT (globals != NULL);
906e58ca 7266
8029a119
NC		 7267 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7268 globals->arm_glue_size,
7269 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7270
8029a119
NC		 7271 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7272 globals->thumb_glue_size,
7273 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7274
8029a119
NC		 7275 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7276 globals->vfp11_erratum_glue_size,
7277 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7278
a504d23a
LA		 7279 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7280 globals->stm32l4xx_erratum_glue_size,
7281 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7282
8029a119
NC		 7283 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7284 globals->bx_glue_size,
845b51d6
PB		 7285 ARM_BX_GLUE_SECTION_NAME);
7286
b34976b6 7287 return TRUE;
252b5132
RH		 7288}
7289
a4fd1a8e 7290/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7291 returns the symbol identifying the stub. */
7292
a4fd1a8e 7293static struct elf_link_hash_entry *
57e8b36a
NC		 7294record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7295 struct elf_link_hash_entry * h)
252b5132
RH		 7296{
7297 const char * name = h->root.root.string;
63b0f745 7298 asection * s;
252b5132
RH		 7299 char * tmp_name;
7300 struct elf_link_hash_entry * myh;
14a793b2 7301 struct bfd_link_hash_entry * bh;
252b5132 7302 struct elf32_arm_link_hash_table * globals;
dc810e39 7303 bfd_vma val;
2f475487 7304 bfd_size_type size;
252b5132
RH		 7305
7306 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7307 BFD_ASSERT (globals != NULL);
7308 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7309
3d4d4302 7310 s = bfd_get_linker_section
252b5132
RH		 7311 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7312
252b5132
RH		 7313 BFD_ASSERT (s != NULL);
7314
21d799b5 7315 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7316 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7317
7318 BFD_ASSERT (tmp_name);
7319
7320 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7321
7322 myh = elf_link_hash_lookup
b34976b6 7323 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7324
7325 if (myh != NULL)
7326 {
9b485d32 7327 /* We've already seen this guy. */
252b5132 7328 free (tmp_name);
a4fd1a8e 7329 return myh;
252b5132
RH		 7330 }
7331
57e8b36a
NC		 7332 /* The only trick here is using hash_table->arm_glue_size as the value.
7333 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7334 putting it. The +1 on the value marks that the stub has not been
7335 output yet - not that it is a Thumb function. */
14a793b2 7336 bh = NULL;
dc810e39
AM		 7337 val = globals->arm_glue_size + 1;
7338 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7339 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7340 NULL, TRUE, FALSE, &bh);
252b5132 7341
b7693d02
DJ		 7342 myh = (struct elf_link_hash_entry *) bh;
7343 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7344 myh->forced_local = 1;
7345
252b5132
RH		 7346 free (tmp_name);
7347
0e1862bb
L		 7348 if (bfd_link_pic (link_info)
7349 || globals->root.is_relocatable_executable
27e55c4d 7350 || globals->pic_veneer)
2f475487 7351 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7352 else if (globals->use_blx)
7353 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7354 else
2f475487
AM		 7355 size = ARM2THUMB_STATIC_GLUE_SIZE;
7356
7357 s->size += size;
7358 globals->arm_glue_size += size;
252b5132 7359
a4fd1a8e 7360 return myh;
252b5132
RH		 7361}
7362
845b51d6
PB		 7363/* Allocate space for ARMv4 BX veneers. */
7364
7365static void
7366record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7367{
7368 asection * s;
7369 struct elf32_arm_link_hash_table *globals;
7370 char *tmp_name;
7371 struct elf_link_hash_entry *myh;
7372 struct bfd_link_hash_entry *bh;
7373 bfd_vma val;
7374
7375 /* BX PC does not need a veneer. */
7376 if (reg == 15)
7377 return;
7378
7379 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7380 BFD_ASSERT (globals != NULL);
7381 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7382
7383 /* Check if this veneer has already been allocated. */
7384 if (globals->bx_glue_offset[reg])
7385 return;
7386
3d4d4302 7387 s = bfd_get_linker_section
845b51d6
PB		 7388 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7389
7390 BFD_ASSERT (s != NULL);
7391
7392 /* Add symbol for veneer. */
21d799b5
NC		 7393 tmp_name = (char *)
7394 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7395
845b51d6 7396 BFD_ASSERT (tmp_name);
906e58ca 7397
845b51d6 7398 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7399
845b51d6
PB		 7400 myh = elf_link_hash_lookup
7401 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7402
845b51d6 7403 BFD_ASSERT (myh == NULL);
906e58ca 7404
845b51d6
PB		 7405 bh = NULL;
7406 val = globals->bx_glue_size;
7407 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7408 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7409 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7410
7411 myh = (struct elf_link_hash_entry *) bh;
7412 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7413 myh->forced_local = 1;
7414
7415 s->size += ARM_BX_VENEER_SIZE;
7416 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7417 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7418}
7419
7420
c7b8f16e
JB		 7421/* Add an entry to the code/data map for section SEC. */
7422
7423static void
7424elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7425{
7426 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7427 unsigned int newidx;
906e58ca 7428
c7b8f16e
JB		 7429 if (sec_data->map == NULL)
7430 {
21d799b5 7431 sec_data->map = (elf32_arm_section_map *)
99059e56 7432 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7433 sec_data->mapcount = 0;
7434 sec_data->mapsize = 1;
7435 }
906e58ca 7436
c7b8f16e 7437 newidx = sec_data->mapcount++;
906e58ca 7438
c7b8f16e
JB		 7439 if (sec_data->mapcount > sec_data->mapsize)
7440 {
7441 sec_data->mapsize *= 2;
21d799b5 7442 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7443 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7444 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7445 }
7446
7447 if (sec_data->map)
7448 {
7449 sec_data->map[newidx].vma = vma;
7450 sec_data->map[newidx].type = type;
c7b8f16e 7451 }
c7b8f16e
JB		 7452}
7453
7454
7455/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7456 veneers are handled for now. */
7457
7458static bfd_vma
7459record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7460 elf32_vfp11_erratum_list *branch,
7461 bfd *branch_bfd,
7462 asection *branch_sec,
7463 unsigned int offset)
c7b8f16e
JB		 7464{
7465 asection *s;
7466 struct elf32_arm_link_hash_table *hash_table;
7467 char *tmp_name;
7468 struct elf_link_hash_entry *myh;
7469 struct bfd_link_hash_entry *bh;
7470 bfd_vma val;
7471 struct _arm_elf_section_data *sec_data;
c7b8f16e 7472 elf32_vfp11_erratum_list *newerr;
906e58ca 7473
c7b8f16e 7474 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7475 BFD_ASSERT (hash_table != NULL);
7476 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7477
3d4d4302 7478 s = bfd_get_linker_section
c7b8f16e 7479 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7480
c7b8f16e 7481 sec_data = elf32_arm_section_data (s);
906e58ca 7482
c7b8f16e 7483 BFD_ASSERT (s != NULL);
906e58ca 7484
21d799b5 7485 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7486 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7487
c7b8f16e 7488 BFD_ASSERT (tmp_name);
906e58ca 7489
c7b8f16e
JB		 7490 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7491 hash_table->num_vfp11_fixes);
906e58ca 7492
c7b8f16e
JB		 7493 myh = elf_link_hash_lookup
7494 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7495
c7b8f16e 7496 BFD_ASSERT (myh == NULL);
906e58ca 7497
c7b8f16e
JB		 7498 bh = NULL;
7499 val = hash_table->vfp11_erratum_glue_size;
7500 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7501 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7502 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7503
7504 myh = (struct elf_link_hash_entry *) bh;
7505 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7506 myh->forced_local = 1;
7507
7508 /* Link veneer back to calling location. */
c7e2358a 7509 sec_data->erratumcount += 1;
21d799b5
NC		 7510 newerr = (elf32_vfp11_erratum_list *)
7511 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7512
c7b8f16e
JB		 7513 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7514 newerr->vma = -1;
7515 newerr->u.v.branch = branch;
7516 newerr->u.v.id = hash_table->num_vfp11_fixes;
7517 branch->u.b.veneer = newerr;
7518
7519 newerr->next = sec_data->erratumlist;
7520 sec_data->erratumlist = newerr;
7521
7522 /* A symbol for the return from the veneer. */
7523 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7524 hash_table->num_vfp11_fixes);
7525
7526 myh = elf_link_hash_lookup
7527 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7528
c7b8f16e
JB		 7529 if (myh != NULL)
7530 abort ();
7531
7532 bh = NULL;
7533 val = offset + 4;
7534 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7535 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7536
c7b8f16e
JB		 7537 myh = (struct elf_link_hash_entry *) bh;
7538 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7539 myh->forced_local = 1;
7540
7541 free (tmp_name);
906e58ca 7542
c7b8f16e
JB		 7543 /* Generate a mapping symbol for the veneer section, and explicitly add an
7544 entry for that symbol to the code/data map for the section. */
7545 if (hash_table->vfp11_erratum_glue_size == 0)
7546 {
7547 bh = NULL;
7548 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7549 ever requires this erratum fix. */
c7b8f16e
JB		 7550 _bfd_generic_link_add_one_symbol (link_info,
7551 hash_table->bfd_of_glue_owner, "$a",
7552 BSF_LOCAL, s, 0, NULL,
99059e56 7553 TRUE, FALSE, &bh);
c7b8f16e
JB		 7554
7555 myh = (struct elf_link_hash_entry *) bh;
7556 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7557 myh->forced_local = 1;
906e58ca 7558
c7b8f16e 7559 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7560 BFDs. We must make a note of this generated mapping symbol
7561 ourselves so that code byteswapping works properly in
7562 elf32_arm_write_section. */
c7b8f16e
JB		 7563 elf32_arm_section_map_add (s, 'a', 0);
7564 }
906e58ca 7565
c7b8f16e
JB		 7566 s->size += VFP11_ERRATUM_VENEER_SIZE;
7567 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7568 hash_table->num_vfp11_fixes++;
906e58ca 7569
c7b8f16e
JB		 7570 /* The offset of the veneer. */
7571 return val;
7572}
7573
a504d23a
LA		 7574/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7575 veneers need to be handled because used only in Cortex-M. */
7576
7577static bfd_vma
7578record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7579 elf32_stm32l4xx_erratum_list *branch,
7580 bfd *branch_bfd,
7581 asection *branch_sec,
7582 unsigned int offset,
7583 bfd_size_type veneer_size)
7584{
7585 asection *s;
7586 struct elf32_arm_link_hash_table *hash_table;
7587 char *tmp_name;
7588 struct elf_link_hash_entry *myh;
7589 struct bfd_link_hash_entry *bh;
7590 bfd_vma val;
7591 struct _arm_elf_section_data *sec_data;
7592 elf32_stm32l4xx_erratum_list *newerr;
7593
7594 hash_table = elf32_arm_hash_table (link_info);
7595 BFD_ASSERT (hash_table != NULL);
7596 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7597
7598 s = bfd_get_linker_section
7599 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7600
7601 BFD_ASSERT (s != NULL);
7602
7603 sec_data = elf32_arm_section_data (s);
7604
7605 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7606 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7607
7608 BFD_ASSERT (tmp_name);
7609
7610 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7611 hash_table->num_stm32l4xx_fixes);
7612
7613 myh = elf_link_hash_lookup
7614 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7615
7616 BFD_ASSERT (myh == NULL);
7617
7618 bh = NULL;
7619 val = hash_table->stm32l4xx_erratum_glue_size;
7620 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7621 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7622 NULL, TRUE, FALSE, &bh);
7623
7624 myh = (struct elf_link_hash_entry *) bh;
7625 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7626 myh->forced_local = 1;
7627
7628 /* Link veneer back to calling location. */
7629 sec_data->stm32l4xx_erratumcount += 1;
7630 newerr = (elf32_stm32l4xx_erratum_list *)
7631 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7632
7633 newerr->type = STM32L4XX_ERRATUM_VENEER;
7634 newerr->vma = -1;
7635 newerr->u.v.branch = branch;
7636 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7637 branch->u.b.veneer = newerr;
7638
7639 newerr->next = sec_data->stm32l4xx_erratumlist;
7640 sec_data->stm32l4xx_erratumlist = newerr;
7641
7642 /* A symbol for the return from the veneer. */
7643 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7644 hash_table->num_stm32l4xx_fixes);
7645
7646 myh = elf_link_hash_lookup
7647 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7648
7649 if (myh != NULL)
7650 abort ();
7651
7652 bh = NULL;
7653 val = offset + 4;
7654 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7655 branch_sec, val, NULL, TRUE, FALSE, &bh);
7656
7657 myh = (struct elf_link_hash_entry *) bh;
7658 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7659 myh->forced_local = 1;
7660
7661 free (tmp_name);
7662
7663 /* Generate a mapping symbol for the veneer section, and explicitly add an
7664 entry for that symbol to the code/data map for the section. */
7665 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7666 {
7667 bh = NULL;
7668 /* Creates a THUMB symbol since there is no other choice. */
7669 _bfd_generic_link_add_one_symbol (link_info,
7670 hash_table->bfd_of_glue_owner, "$t",
7671 BSF_LOCAL, s, 0, NULL,
7672 TRUE, FALSE, &bh);
7673
7674 myh = (struct elf_link_hash_entry *) bh;
7675 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7676 myh->forced_local = 1;
7677
7678 /* The elf32_arm_init_maps function only cares about symbols from input
7679 BFDs. We must make a note of this generated mapping symbol
7680 ourselves so that code byteswapping works properly in
7681 elf32_arm_write_section. */
7682 elf32_arm_section_map_add (s, 't', 0);
7683 }
7684
7685 s->size += veneer_size;
7686 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7687 hash_table->num_stm32l4xx_fixes++;
7688
7689 /* The offset of the veneer. */
7690 return val;
7691}
7692
8029a119 7693#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7694 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7695 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7696
7697/* Create a fake section for use by the ARM backend of the linker. */
7698
7699static bfd_boolean
7700arm_make_glue_section (bfd * abfd, const char * name)
7701{
7702 asection * sec;
7703
3d4d4302 7704 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7705 if (sec != NULL)
7706 /* Already made. */
7707 return TRUE;
7708
3d4d4302 7709 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7710
7711 if (sec == NULL
7712 || !bfd_set_section_alignment (abfd, sec, 2))
7713 return FALSE;
7714
7715 /* Set the gc mark to prevent the section from being removed by garbage
7716 collection, despite the fact that no relocs refer to this section. */
7717 sec->gc_mark = 1;
7718
7719 return TRUE;
7720}
7721
1db37fe6
YG		 7722/* Set size of .plt entries. This function is called from the
7723 linker scripts in ld/emultempl/{armelf}.em. */
7724
7725void
7726bfd_elf32_arm_use_long_plt (void)
7727{
7728 elf32_arm_use_long_plt_entry = TRUE;
7729}
7730
8afb0e02
NC		 7731/* Add the glue sections to ABFD. This function is called from the
7732 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7733
b34976b6 7734bfd_boolean
57e8b36a
NC		 7735bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7736 struct bfd_link_info *info)
252b5132 7737{
a504d23a
LA		 7738 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7739 bfd_boolean dostm32l4xx = globals
7740 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7741 bfd_boolean addglue;
7742
8afb0e02
NC		 7743 /* If we are only performing a partial
7744 link do not bother adding the glue. */
0e1862bb 7745 if (bfd_link_relocatable (info))
b34976b6 7746 return TRUE;
252b5132 7747
a504d23a 7748 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7749 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7750 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7751 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7752
7753 if (!dostm32l4xx)
7754 return addglue;
7755
7756 return addglue
7757 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7758}
7759
daa4adae
TP		 7760/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7761 ensures they are not marked for deletion by
7762 strip_excluded_output_sections () when veneers are going to be created
7763 later. Not doing so would trigger assert on empty section size in
7764 lang_size_sections_1 (). */
7765
7766void
7767bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7768{
7769 enum elf32_arm_stub_type stub_type;
7770
7771 /* If we are only performing a partial
7772 link do not bother adding the glue. */
7773 if (bfd_link_relocatable (info))
7774 return;
7775
7776 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7777 {
7778 asection *out_sec;
7779 const char *out_sec_name;
7780
7781 if (!arm_dedicated_stub_output_section_required (stub_type))
7782 continue;
7783
7784 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7785 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7786 if (out_sec != NULL)
7787 out_sec->flags |= SEC_KEEP;
7788 }
7789}
7790
8afb0e02
NC		 7791/* Select a BFD to be used to hold the sections used by the glue code.
7792 This function is called from the linker scripts in ld/emultempl/
8029a119 7793 {armelf/pe}.em. */
8afb0e02 7794
b34976b6 7795bfd_boolean
57e8b36a 7796bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7797{
7798 struct elf32_arm_link_hash_table *globals;
7799
7800 /* If we are only performing a partial link
7801 do not bother getting a bfd to hold the glue. */
0e1862bb 7802 if (bfd_link_relocatable (info))
b34976b6 7803 return TRUE;
8afb0e02 7804
b7693d02
DJ		 7805 /* Make sure we don't attach the glue sections to a dynamic object. */
7806 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7807
8afb0e02 7808 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7809 BFD_ASSERT (globals != NULL);
7810
7811 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7812 return TRUE;
8afb0e02 7813
252b5132
RH		 7814 /* Save the bfd for later use. */
7815 globals->bfd_of_glue_owner = abfd;
cedb70c5 7816
b34976b6 7817 return TRUE;
252b5132
RH		 7818}
7819
906e58ca
NC		 7820static void
7821check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7822{
2de70689
MGD		 7823 int cpu_arch;
7824
b38cadfb 7825 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7826 Tag_CPU_arch);
7827
7828 if (globals->fix_arm1176)
7829 {
7830 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7831 globals->use_blx = 1;
7832 }
7833 else
7834 {
7835 if (cpu_arch > TAG_CPU_ARCH_V4T)
7836 globals->use_blx = 1;
7837 }
39b41c9c
PB		 7838}
7839
b34976b6 7840bfd_boolean
57e8b36a 7841bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7842 struct bfd_link_info *link_info)
252b5132
RH		 7843{
7844 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7845 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7846 Elf_Internal_Rela *irel, *irelend;
7847 bfd_byte *contents = NULL;
252b5132
RH		 7848
7849 asection *sec;
7850 struct elf32_arm_link_hash_table *globals;
7851
7852 /* If we are only performing a partial link do not bother
7853 to construct any glue. */
0e1862bb 7854 if (bfd_link_relocatable (link_info))
b34976b6 7855 return TRUE;
252b5132 7856
39ce1a6a
NC		 7857 /* Here we have a bfd that is to be included on the link. We have a
7858 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7859 globals = elf32_arm_hash_table (link_info);
252b5132 7860 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7861
7862 check_use_blx (globals);
252b5132 7863
d504ffc8 7864 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7865 {
90b6238f 7866 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7867 abfd);
e489d0ae
PB		 7868 return FALSE;
7869 }
f21f3fe0 7870
39ce1a6a
NC		 7871 /* PR 5398: If we have not decided to include any loadable sections in
7872 the output then we will not have a glue owner bfd. This is OK, it
7873 just means that there is nothing else for us to do here. */
7874 if (globals->bfd_of_glue_owner == NULL)
7875 return TRUE;
7876
252b5132
RH		 7877 /* Rummage around all the relocs and map the glue vectors. */
7878 sec = abfd->sections;
7879
7880 if (sec == NULL)
b34976b6 7881 return TRUE;
252b5132
RH		 7882
7883 for (; sec != NULL; sec = sec->next)
7884 {
7885 if (sec->reloc_count == 0)
7886 continue;
7887
2f475487
AM		 7888 if ((sec->flags & SEC_EXCLUDE) != 0)
7889 continue;
7890
0ffa91dd 7891 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7892
9b485d32 7893 /* Load the relocs. */
6cdc0ccc 7894 internal_relocs
906e58ca 7895 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7896
6cdc0ccc
AM		 7897 if (internal_relocs == NULL)
7898 goto error_return;
252b5132 7899
6cdc0ccc
AM		 7900 irelend = internal_relocs + sec->reloc_count;
7901 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7902 {
7903 long r_type;
7904 unsigned long r_index;
252b5132
RH		 7905
7906 struct elf_link_hash_entry *h;
7907
7908 r_type = ELF32_R_TYPE (irel->r_info);
7909 r_index = ELF32_R_SYM (irel->r_info);
7910
9b485d32 7911 /* These are the only relocation types we care about. */
ba96a88f 7912 if ( r_type != R_ARM_PC24
845b51d6 7913 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7914 continue;
7915
7916 /* Get the section contents if we haven't done so already. */
7917 if (contents == NULL)
7918 {
7919 /* Get cached copy if it exists. */
7920 if (elf_section_data (sec)->this_hdr.contents != NULL)
7921 contents = elf_section_data (sec)->this_hdr.contents;
7922 else
7923 {
7924 /* Go get them off disk. */
57e8b36a 7925 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7926 goto error_return;
7927 }
7928 }
7929
845b51d6
PB		 7930 if (r_type == R_ARM_V4BX)
7931 {
7932 int reg;
7933
7934 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7935 record_arm_bx_glue (link_info, reg);
7936 continue;
7937 }
7938
a7c10850 7939 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7940 h = NULL;
7941
9b485d32 7942 /* We don't care about local symbols. */
252b5132
RH		 7943 if (r_index < symtab_hdr->sh_info)
7944 continue;
7945
9b485d32 7946 /* This is an external symbol. */
252b5132
RH		 7947 r_index -= symtab_hdr->sh_info;
7948 h = (struct elf_link_hash_entry *)
7949 elf_sym_hashes (abfd)[r_index];
7950
7951 /* If the relocation is against a static symbol it must be within
7952 the current section and so cannot be a cross ARM/Thumb relocation. */
7953 if (h == NULL)
7954 continue;
7955
d504ffc8
DJ		 7956 /* If the call will go through a PLT entry then we do not need
7957 glue. */
362d30a1 7958 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7959 continue;
7960
252b5132
RH		 7961 switch (r_type)
7962 {
7963 case R_ARM_PC24:
7964 /* This one is a call from arm code. We need to look up
99059e56
RM		 7965 the target of the call. If it is a thumb target, we
7966 insert glue. */
39d911fc
TP		 7967 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7968 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7969 record_arm_to_thumb_glue (link_info, h);
7970 break;
7971
252b5132 7972 default:
c6596c5e 7973 abort ();
252b5132
RH		 7974 }
7975 }
6cdc0ccc
AM		 7976
7977 if (contents != NULL
7978 && elf_section_data (sec)->this_hdr.contents != contents)
7979 free (contents);
7980 contents = NULL;
7981
7982 if (internal_relocs != NULL
7983 && elf_section_data (sec)->relocs != internal_relocs)
7984 free (internal_relocs);
7985 internal_relocs = NULL;
252b5132
RH		 7986 }
7987
b34976b6 7988 return TRUE;
9a5aca8c 7989
252b5132 7990error_return:
6cdc0ccc
AM		 7991 if (contents != NULL
7992 && elf_section_data (sec)->this_hdr.contents != contents)
7993 free (contents);
7994 if (internal_relocs != NULL
7995 && elf_section_data (sec)->relocs != internal_relocs)
7996 free (internal_relocs);
9a5aca8c 7997
b34976b6 7998 return FALSE;
252b5132 7999}
7e392df6 8000#endif
252b5132 8001
eb043451 8002
c7b8f16e
JB		 8003/* Initialise maps of ARM/Thumb/data for input BFDs. */
8004
8005void
8006bfd_elf32_arm_init_maps (bfd *abfd)
8007{
8008 Elf_Internal_Sym *isymbuf;
8009 Elf_Internal_Shdr *hdr;
8010 unsigned int i, localsyms;
8011
af1f4419
NC		 8012 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8013 if (! is_arm_elf (abfd))
8014 return;
8015
c7b8f16e
JB		 8016 if ((abfd->flags & DYNAMIC) != 0)
8017 return;
8018
0ffa91dd 8019 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 8020 localsyms = hdr->sh_info;
8021
8022 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8023 should contain the number of local symbols, which should come before any
8024 global symbols. Mapping symbols are always local. */
8025 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
8026 NULL);
8027
8028 /* No internal symbols read? Skip this BFD. */
8029 if (isymbuf == NULL)
8030 return;
8031
8032 for (i = 0; i < localsyms; i++)
8033 {
8034 Elf_Internal_Sym *isym = &isymbuf[i];
8035 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
8036 const char *name;
906e58ca 8037
c7b8f16e 8038 if (sec != NULL
99059e56
RM		 8039 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8040 {
8041 name = bfd_elf_string_from_elf_section (abfd,
8042 hdr->sh_link, isym->st_name);
906e58ca 8043
99059e56 8044 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8045 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8046 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8047 }
c7b8f16e
JB		 8048 }
8049}
8050
8051
48229727
JB		 8052/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8053 say what they wanted. */
8054
8055void
8056bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8057{
8058 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8059 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8060
4dfe6ac6
NC		 8061 if (globals == NULL)
8062 return;
8063
48229727
JB		 8064 if (globals->fix_cortex_a8 == -1)
8065 {
8066 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8067 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8068 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8069 || out_attr[Tag_CPU_arch_profile].i == 0))
8070 globals->fix_cortex_a8 = 1;
8071 else
8072 globals->fix_cortex_a8 = 0;
8073 }
8074}
8075
8076
c7b8f16e
JB		 8077void
8078bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8079{
8080 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8081 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8082
4dfe6ac6
NC		 8083 if (globals == NULL)
8084 return;
c7b8f16e
JB		 8085 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8086 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8087 {
8088 switch (globals->vfp11_fix)
99059e56
RM		 8089 {
8090 case BFD_ARM_VFP11_FIX_DEFAULT:
8091 case BFD_ARM_VFP11_FIX_NONE:
8092 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8093 break;
8094
8095 default:
8096 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8097 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8098 "workaround is not necessary for target architecture"), obfd);
8099 }
c7b8f16e
JB		 8100 }
8101 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8102 /* For earlier architectures, we might need the workaround, but do not
8103 enable it by default. If users is running with broken hardware, they
8104 must enable the erratum fix explicitly. */
8105 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8106}
8107
a504d23a
LA		 8108void
8109bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8110{
8111 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8112 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8113
8114 if (globals == NULL)
8115 return;
8116
8117 /* We assume only Cortex-M4 may require the fix. */
8118 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8119 || out_attr[Tag_CPU_arch_profile].i != 'M')
8120 {
8121 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8122 /* Give a warning, but do as the user requests anyway. */
4eca0228 8123 _bfd_error_handler
871b3ab2 8124 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8125 "workaround is not necessary for target architecture"), obfd);
8126 }
8127}
c7b8f16e 8128
906e58ca
NC		 8129enum bfd_arm_vfp11_pipe
8130{
c7b8f16e
JB		 8131 VFP11_FMAC,
8132 VFP11_LS,
8133 VFP11_DS,
8134 VFP11_BAD
8135};
8136
8137/* Return a VFP register number. This is encoded as RX:X for single-precision
8138 registers, or X:RX for double-precision registers, where RX is the group of
8139 four bits in the instruction encoding and X is the single extension bit.
8140 RX and X fields are specified using their lowest (starting) bit. The return
8141 value is:
8142
8143 0...31: single-precision registers s0...s31
8144 32...63: double-precision registers d0...d31.
906e58ca 8145
c7b8f16e
JB		 8146 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8147 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8148
c7b8f16e
JB		 8149static unsigned int
8150bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8151 unsigned int x)
c7b8f16e
JB		 8152{
8153 if (is_double)
8154 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8155 else
8156 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8157}
8158
8159/* Set bits in *WMASK according to a register number REG as encoded by
8160 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8161
8162static void
8163bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8164{
8165 if (reg < 32)
8166 *wmask |= 1 << reg;
8167 else if (reg < 48)
8168 *wmask |= 3 << ((reg - 32) * 2);
8169}
8170
8171/* Return TRUE if WMASK overwrites anything in REGS. */
8172
8173static bfd_boolean
8174bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8175{
8176 int i;
906e58ca 8177
c7b8f16e
JB		 8178 for (i = 0; i < numregs; i++)
8179 {
8180 unsigned int reg = regs[i];
8181
8182 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8183 return TRUE;
906e58ca 8184
c7b8f16e
JB		 8185 reg -= 32;
8186
8187 if (reg >= 16)
99059e56 8188 continue;
906e58ca 8189
c7b8f16e 8190 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8191 return TRUE;
c7b8f16e 8192 }
906e58ca 8193
c7b8f16e
JB		 8194 return FALSE;
8195}
8196
8197/* In this function, we're interested in two things: finding input registers
8198 for VFP data-processing instructions, and finding the set of registers which
8199 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8200 hold the written set, so FLDM etc. are easy to deal with (we're only
8201 interested in 32 SP registers or 16 dp registers, due to the VFP version
8202 implemented by the chip in question). DP registers are marked by setting
8203 both SP registers in the write mask). */
8204
8205static enum bfd_arm_vfp11_pipe
8206bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8207 int *numregs)
c7b8f16e 8208{
91d6fa6a 8209 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8210 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8211
8212 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8213 {
8214 unsigned int pqrs;
8215 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8216 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8217
8218 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8219 | ((insn & 0x00300000) >> 19)
8220 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8221
8222 switch (pqrs)
99059e56
RM		 8223 {
8224 case 0: /* fmac[sd]. */
8225 case 1: /* fnmac[sd]. */
8226 case 2: /* fmsc[sd]. */
8227 case 3: /* fnmsc[sd]. */
8228 vpipe = VFP11_FMAC;
8229 bfd_arm_vfp11_write_mask (destmask, fd);
8230 regs[0] = fd;
8231 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8232 regs[2] = fm;
8233 *numregs = 3;
8234 break;
8235
8236 case 4: /* fmul[sd]. */
8237 case 5: /* fnmul[sd]. */
8238 case 6: /* fadd[sd]. */
8239 case 7: /* fsub[sd]. */
8240 vpipe = VFP11_FMAC;
8241 goto vfp_binop;
8242
8243 case 8: /* fdiv[sd]. */
8244 vpipe = VFP11_DS;
8245 vfp_binop:
8246 bfd_arm_vfp11_write_mask (destmask, fd);
8247 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8248 regs[1] = fm;
8249 *numregs = 2;
8250 break;
8251
8252 case 15: /* extended opcode. */
8253 {
8254 unsigned int extn = ((insn >> 15) & 0x1e)
8255 | ((insn >> 7) & 1);
8256
8257 switch (extn)
8258 {
8259 case 0: /* fcpy[sd]. */
8260 case 1: /* fabs[sd]. */
8261 case 2: /* fneg[sd]. */
8262 case 8: /* fcmp[sd]. */
8263 case 9: /* fcmpe[sd]. */
8264 case 10: /* fcmpz[sd]. */
8265 case 11: /* fcmpez[sd]. */
8266 case 16: /* fuito[sd]. */
8267 case 17: /* fsito[sd]. */
8268 case 24: /* ftoui[sd]. */
8269 case 25: /* ftouiz[sd]. */
8270 case 26: /* ftosi[sd]. */
8271 case 27: /* ftosiz[sd]. */
8272 /* These instructions will not bounce due to underflow. */
8273 *numregs = 0;
8274 vpipe = VFP11_FMAC;
8275 break;
8276
8277 case 3: /* fsqrt[sd]. */
8278 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8279 registers to cause the erratum in previous instructions. */
8280 bfd_arm_vfp11_write_mask (destmask, fd);
8281 vpipe = VFP11_DS;
8282 break;
8283
8284 case 15: /* fcvt{ds,sd}. */
8285 {
8286 int rnum = 0;
8287
8288 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8289
8290 /* Only FCVTSD can underflow. */
99059e56
RM		 8291 if ((insn & 0x100) != 0)
8292 regs[rnum++] = fm;
c7b8f16e 8293
99059e56 8294 *numregs = rnum;
c7b8f16e 8295
99059e56
RM		 8296 vpipe = VFP11_FMAC;
8297 }
8298 break;
c7b8f16e 8299
99059e56
RM		 8300 default:
8301 return VFP11_BAD;
8302 }
8303 }
8304 break;
c7b8f16e 8305
99059e56
RM		 8306 default:
8307 return VFP11_BAD;
8308 }
c7b8f16e
JB		 8309 }
8310 /* Two-register transfer. */
8311 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8312 {
8313 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8314
c7b8f16e
JB		 8315 if ((insn & 0x100000) == 0)
8316 {
99059e56
RM		 8317 if (is_double)
8318 bfd_arm_vfp11_write_mask (destmask, fm);
8319 else
8320 {
8321 bfd_arm_vfp11_write_mask (destmask, fm);
8322 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8323 }
c7b8f16e
JB		 8324 }
8325
91d6fa6a 8326 vpipe = VFP11_LS;
c7b8f16e
JB		 8327 }
8328 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8329 {
8330 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8331 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8332
c7b8f16e 8333 switch (puw)
99059e56
RM		 8334 {
8335 case 0: /* Two-reg transfer. We should catch these above. */
8336 abort ();
906e58ca 8337
99059e56
RM		 8338 case 2: /* fldm[sdx]. */
8339 case 3:
8340 case 5:
8341 {
8342 unsigned int i, offset = insn & 0xff;
c7b8f16e 8343
99059e56
RM		 8344 if (is_double)
8345 offset >>= 1;
c7b8f16e 8346
99059e56
RM		 8347 for (i = fd; i < fd + offset; i++)
8348 bfd_arm_vfp11_write_mask (destmask, i);
8349 }
8350 break;
906e58ca 8351
99059e56
RM		 8352 case 4: /* fld[sd]. */
8353 case 6:
8354 bfd_arm_vfp11_write_mask (destmask, fd);
8355 break;
906e58ca 8356
99059e56
RM		 8357 default:
8358 return VFP11_BAD;
8359 }
c7b8f16e 8360
91d6fa6a 8361 vpipe = VFP11_LS;
c7b8f16e
JB		 8362 }
8363 /* Single-register transfer. Note L==0. */
8364 else if ((insn & 0x0f100e10) == 0x0e000a10)
8365 {
8366 unsigned int opcode = (insn >> 21) & 7;
8367 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8368
8369 switch (opcode)
99059e56
RM		 8370 {
8371 case 0: /* fmsr/fmdlr. */
8372 case 1: /* fmdhr. */
8373 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8374 destination register. I don't know if this is exactly right,
8375 but it is the conservative choice. */
8376 bfd_arm_vfp11_write_mask (destmask, fn);
8377 break;
8378
8379 case 7: /* fmxr. */
8380 break;
8381 }
c7b8f16e 8382
91d6fa6a 8383 vpipe = VFP11_LS;
c7b8f16e
JB		 8384 }
8385
91d6fa6a 8386 return vpipe;
c7b8f16e
JB		 8387}
8388
8389
8390static int elf32_arm_compare_mapping (const void * a, const void * b);
8391
8392
8393/* Look for potentially-troublesome code sequences which might trigger the
8394 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8395 (available from ARM) for details of the erratum. A short version is
8396 described in ld.texinfo. */
8397
8398bfd_boolean
8399bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8400{
8401 asection *sec;
8402 bfd_byte *contents = NULL;
8403 int state = 0;
8404 int regs[3], numregs = 0;
8405 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8406 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8407
4dfe6ac6
NC		 8408 if (globals == NULL)
8409 return FALSE;
8410
c7b8f16e
JB		 8411 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8412 The states transition as follows:
906e58ca 8413
c7b8f16e 8414 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8415 A VFP FMAC-pipeline instruction has been seen. Fill
8416 regs[0]..regs[numregs-1] with its input operands. Remember this
8417 instruction in 'first_fmac'.
c7b8f16e
JB		 8418
8419 1 -> 2
99059e56
RM		 8420 Any instruction, except for a VFP instruction which overwrites
8421 regs[*].
906e58ca 8422
c7b8f16e
JB		 8423 1 -> 3 [ -> 0 ] or
8424 2 -> 3 [ -> 0 ]
99059e56
RM		 8425 A VFP instruction has been seen which overwrites any of regs[*].
8426 We must make a veneer! Reset state to 0 before examining next
8427 instruction.
906e58ca 8428
c7b8f16e 8429 2 -> 0
99059e56
RM		 8430 If we fail to match anything in state 2, reset to state 0 and reset
8431 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8432
8433 If the VFP11 vector mode is in use, there must be at least two unrelated
8434 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8435 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8436
8437 /* If we are only performing a partial link do not bother
8438 to construct any glue. */
0e1862bb 8439 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8440 return TRUE;
8441
0ffa91dd
NC		 8442 /* Skip if this bfd does not correspond to an ELF image. */
8443 if (! is_arm_elf (abfd))
8444 return TRUE;
906e58ca 8445
c7b8f16e
JB		 8446 /* We should have chosen a fix type by the time we get here. */
8447 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8448
8449 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8450 return TRUE;
2e6030b9 8451
33a7ffc2
JM		 8452 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8453 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8454 return TRUE;
8455
c7b8f16e
JB		 8456 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8457 {
8458 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8459 struct _arm_elf_section_data *sec_data;
8460
8461 /* If we don't have executable progbits, we're not interested in this
99059e56 8462 section. Also skip if section is to be excluded. */
c7b8f16e 8463 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8464 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8465 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8466 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8467 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8468 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8469 continue;
c7b8f16e
JB		 8470
8471 sec_data = elf32_arm_section_data (sec);
906e58ca 8472
c7b8f16e 8473 if (sec_data->mapcount == 0)
99059e56 8474 continue;
906e58ca 8475
c7b8f16e
JB		 8476 if (elf_section_data (sec)->this_hdr.contents != NULL)
8477 contents = elf_section_data (sec)->this_hdr.contents;
8478 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8479 goto error_return;
8480
8481 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8482 elf32_arm_compare_mapping);
8483
8484 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8485 {
8486 unsigned int span_start = sec_data->map[span].vma;
8487 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8488 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8489 char span_type = sec_data->map[span].type;
8490
8491 /* FIXME: Only ARM mode is supported at present. We may need to
8492 support Thumb-2 mode also at some point. */
8493 if (span_type != 'a')
8494 continue;
8495
8496 for (i = span_start; i < span_end;)
8497 {
8498 unsigned int next_i = i + 4;
8499 unsigned int insn = bfd_big_endian (abfd)
8500 ? (contents[i] << 24)
8501 | (contents[i + 1] << 16)
8502 | (contents[i + 2] << 8)
8503 | contents[i + 3]
8504 : (contents[i + 3] << 24)
8505 | (contents[i + 2] << 16)
8506 | (contents[i + 1] << 8)
8507 | contents[i];
8508 unsigned int writemask = 0;
8509 enum bfd_arm_vfp11_pipe vpipe;
8510
8511 switch (state)
8512 {
8513 case 0:
8514 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8515 &numregs);
8516 /* I'm assuming the VFP11 erratum can trigger with denorm
8517 operands on either the FMAC or the DS pipeline. This might
8518 lead to slightly overenthusiastic veneer insertion. */
8519 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8520 {
8521 state = use_vector ? 1 : 2;
8522 first_fmac = i;
8523 veneer_of_insn = insn;
8524 }
8525 break;
8526
8527 case 1:
8528 {
8529 int other_regs[3], other_numregs;
8530 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8531 other_regs,
99059e56
RM		 8532 &other_numregs);
8533 if (vpipe != VFP11_BAD
8534 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8535 numregs))
99059e56
RM		 8536 state = 3;
8537 else
8538 state = 2;
8539 }
8540 break;
8541
8542 case 2:
8543 {
8544 int other_regs[3], other_numregs;
8545 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8546 other_regs,
99059e56
RM		 8547 &other_numregs);
8548 if (vpipe != VFP11_BAD
8549 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8550 numregs))
99059e56
RM		 8551 state = 3;
8552 else
8553 {
8554 state = 0;
8555 next_i = first_fmac + 4;
8556 }
8557 }
8558 break;
8559
8560 case 3:
8561 abort (); /* Should be unreachable. */
8562 }
8563
8564 if (state == 3)
8565 {
8566 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8567 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8568
8569 elf32_arm_section_data (sec)->erratumcount += 1;
8570
8571 newerr->u.b.vfp_insn = veneer_of_insn;
8572
8573 switch (span_type)
8574 {
8575 case 'a':
8576 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8577 break;
8578
8579 default:
8580 abort ();
8581 }
8582
8583 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8584 first_fmac);
8585
99059e56 8586 newerr->vma = -1;
c7b8f16e 8587
99059e56
RM		 8588 newerr->next = sec_data->erratumlist;
8589 sec_data->erratumlist = newerr;
c7b8f16e 8590
99059e56
RM		 8591 state = 0;
8592 }
c7b8f16e 8593
99059e56
RM		 8594 i = next_i;
8595 }
8596 }
906e58ca 8597
c7b8f16e 8598 if (contents != NULL
99059e56
RM		 8599 && elf_section_data (sec)->this_hdr.contents != contents)
8600 free (contents);
c7b8f16e
JB		 8601 contents = NULL;
8602 }
8603
8604 return TRUE;
8605
8606error_return:
8607 if (contents != NULL
8608 && elf_section_data (sec)->this_hdr.contents != contents)
8609 free (contents);
906e58ca 8610
c7b8f16e
JB		 8611 return FALSE;
8612}
8613
8614/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8615 after sections have been laid out, using specially-named symbols. */
8616
8617void
8618bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8619 struct bfd_link_info *link_info)
8620{
8621 asection *sec;
8622 struct elf32_arm_link_hash_table *globals;
8623 char *tmp_name;
906e58ca 8624
0e1862bb 8625 if (bfd_link_relocatable (link_info))
c7b8f16e 8626 return;
2e6030b9
MS		 8627
8628 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8629 if (! is_arm_elf (abfd))
2e6030b9
MS		 8630 return;
8631
c7b8f16e 8632 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8633 if (globals == NULL)
8634 return;
906e58ca 8635
21d799b5 8636 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8637 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8638
8639 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8640 {
8641 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8642 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8643
c7b8f16e 8644 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8645 {
8646 struct elf_link_hash_entry *myh;
8647 bfd_vma vma;
8648
8649 switch (errnode->type)
8650 {
8651 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8652 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8653 /* Find veneer symbol. */
8654 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8655 errnode->u.b.veneer->u.v.id);
8656
99059e56
RM		 8657 myh = elf_link_hash_lookup
8658 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8659
a504d23a 8660 if (myh == NULL)
90b6238f
AM		 8661 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8662 abfd, "VFP11", tmp_name);
a504d23a
LA		 8663
8664 vma = myh->root.u.def.section->output_section->vma
8665 + myh->root.u.def.section->output_offset
8666 + myh->root.u.def.value;
8667
8668 errnode->u.b.veneer->vma = vma;
8669 break;
8670
8671 case VFP11_ERRATUM_ARM_VENEER:
8672 case VFP11_ERRATUM_THUMB_VENEER:
8673 /* Find return location. */
8674 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8675 errnode->u.v.id);
8676
8677 myh = elf_link_hash_lookup
8678 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8679
8680 if (myh == NULL)
90b6238f
AM		 8681 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8682 abfd, "VFP11", tmp_name);
a504d23a
LA		 8683
8684 vma = myh->root.u.def.section->output_section->vma
8685 + myh->root.u.def.section->output_offset
8686 + myh->root.u.def.value;
8687
8688 errnode->u.v.branch->vma = vma;
8689 break;
8690
8691 default:
8692 abort ();
8693 }
8694 }
8695 }
8696
8697 free (tmp_name);
8698}
8699
8700/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8701 return locations after sections have been laid out, using
8702 specially-named symbols. */
8703
8704void
8705bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8706 struct bfd_link_info *link_info)
8707{
8708 asection *sec;
8709 struct elf32_arm_link_hash_table *globals;
8710 char *tmp_name;
8711
8712 if (bfd_link_relocatable (link_info))
8713 return;
8714
8715 /* Skip if this bfd does not correspond to an ELF image. */
8716 if (! is_arm_elf (abfd))
8717 return;
8718
8719 globals = elf32_arm_hash_table (link_info);
8720 if (globals == NULL)
8721 return;
8722
8723 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8724 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8725
8726 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8727 {
8728 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8729 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8730
8731 for (; errnode != NULL; errnode = errnode->next)
8732 {
8733 struct elf_link_hash_entry *myh;
8734 bfd_vma vma;
8735
8736 switch (errnode->type)
8737 {
8738 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8739 /* Find veneer symbol. */
8740 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8741 errnode->u.b.veneer->u.v.id);
8742
8743 myh = elf_link_hash_lookup
8744 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8745
8746 if (myh == NULL)
90b6238f
AM		 8747 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8748 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8749
8750 vma = myh->root.u.def.section->output_section->vma
8751 + myh->root.u.def.section->output_offset
8752 + myh->root.u.def.value;
8753
8754 errnode->u.b.veneer->vma = vma;
8755 break;
8756
8757 case STM32L4XX_ERRATUM_VENEER:
8758 /* Find return location. */
8759 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8760 errnode->u.v.id);
8761
8762 myh = elf_link_hash_lookup
8763 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8764
8765 if (myh == NULL)
90b6238f
AM		 8766 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8767 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8768
8769 vma = myh->root.u.def.section->output_section->vma
8770 + myh->root.u.def.section->output_offset
8771 + myh->root.u.def.value;
8772
8773 errnode->u.v.branch->vma = vma;
8774 break;
8775
8776 default:
8777 abort ();
8778 }
8779 }
8780 }
8781
8782 free (tmp_name);
8783}
8784
8785static inline bfd_boolean
8786is_thumb2_ldmia (const insn32 insn)
8787{
8788 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8789 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8790 return (insn & 0xffd02000) == 0xe8900000;
8791}
8792
8793static inline bfd_boolean
8794is_thumb2_ldmdb (const insn32 insn)
8795{
8796 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8797 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8798 return (insn & 0xffd02000) == 0xe9100000;
8799}
8800
8801static inline bfd_boolean
8802is_thumb2_vldm (const insn32 insn)
8803{
8804 /* A6.5 Extension register load or store instruction
8805 A7.7.229
9239bbd3
CM		 8806 We look for SP 32-bit and DP 64-bit registers.
8807 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8808 <list> is consecutive 64-bit registers
8809 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8810 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8811 <list> is consecutive 32-bit registers
8812 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8813 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8814 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8815 return
9239bbd3
CM		 8816 (((insn & 0xfe100f00) == 0xec100b00) ||
8817 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8818 && /* (IA without !). */
8819 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8820 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8821 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8822 /* (DB with !). */
8823 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8824}
8825
8826/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8827 VLDM opcode and:
8828 - computes the number and the mode of memory accesses
8829 - decides if the replacement should be done:
8830 . replaces only if > 8-word accesses
8831 . or (testing purposes only) replaces all accesses. */
8832
8833static bfd_boolean
8834stm32l4xx_need_create_replacing_stub (const insn32 insn,
8835 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8836{
9239bbd3 8837 int nb_words = 0;
a504d23a
LA		 8838
8839 /* The field encoding the register list is the same for both LDMIA
8840 and LDMDB encodings. */
8841 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8842 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8843 else if (is_thumb2_vldm (insn))
9239bbd3 8844 nb_words = (insn & 0xff);
a504d23a
LA		 8845
8846 /* DEFAULT mode accounts for the real bug condition situation,
8847 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8848 return
9239bbd3 8849 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8850 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8851}
8852
8853/* Look for potentially-troublesome code sequences which might trigger
8854 the STM STM32L4XX erratum. */
8855
8856bfd_boolean
8857bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8858 struct bfd_link_info *link_info)
8859{
8860 asection *sec;
8861 bfd_byte *contents = NULL;
8862 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8863
8864 if (globals == NULL)
8865 return FALSE;
8866
8867 /* If we are only performing a partial link do not bother
8868 to construct any glue. */
8869 if (bfd_link_relocatable (link_info))
8870 return TRUE;
8871
8872 /* Skip if this bfd does not correspond to an ELF image. */
8873 if (! is_arm_elf (abfd))
8874 return TRUE;
8875
8876 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8877 return TRUE;
8878
8879 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8880 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8881 return TRUE;
8882
8883 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8884 {
8885 unsigned int i, span;
8886 struct _arm_elf_section_data *sec_data;
8887
8888 /* If we don't have executable progbits, we're not interested in this
8889 section. Also skip if section is to be excluded. */
8890 if (elf_section_type (sec) != SHT_PROGBITS
8891 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8892 || (sec->flags & SEC_EXCLUDE) != 0
8893 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8894 || sec->output_section == bfd_abs_section_ptr
8895 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8896 continue;
8897
8898 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8899
a504d23a
LA		 8900 if (sec_data->mapcount == 0)
8901 continue;
c7b8f16e 8902
a504d23a
LA		 8903 if (elf_section_data (sec)->this_hdr.contents != NULL)
8904 contents = elf_section_data (sec)->this_hdr.contents;
8905 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8906 goto error_return;
c7b8f16e 8907
a504d23a
LA		 8908 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8909 elf32_arm_compare_mapping);
c7b8f16e 8910
a504d23a
LA		 8911 for (span = 0; span < sec_data->mapcount; span++)
8912 {
8913 unsigned int span_start = sec_data->map[span].vma;
8914 unsigned int span_end = (span == sec_data->mapcount - 1)
8915 ? sec->size : sec_data->map[span + 1].vma;
8916 char span_type = sec_data->map[span].type;
8917 int itblock_current_pos = 0;
c7b8f16e 8918
a504d23a
LA		 8919 /* Only Thumb2 mode need be supported with this CM4 specific
8920 code, we should not encounter any arm mode eg span_type
8921 != 'a'. */
8922 if (span_type != 't')
8923 continue;
c7b8f16e 8924
a504d23a
LA		 8925 for (i = span_start; i < span_end;)
8926 {
8927 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8928 bfd_boolean insn_32bit = FALSE;
8929 bfd_boolean is_ldm = FALSE;
8930 bfd_boolean is_vldm = FALSE;
8931 bfd_boolean is_not_last_in_it_block = FALSE;
8932
8933 /* The first 16-bits of all 32-bit thumb2 instructions start
8934 with opcode[15..13]=0b111 and the encoded op1 can be anything
8935 except opcode[12..11]!=0b00.
8936 See 32-bit Thumb instruction encoding. */
8937 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8938 insn_32bit = TRUE;
c7b8f16e 8939
a504d23a
LA		 8940 /* Compute the predicate that tells if the instruction
8941 is concerned by the IT block
8942 - Creates an error if there is a ldm that is not
8943 last in the IT block thus cannot be replaced
8944 - Otherwise we can create a branch at the end of the
8945 IT block, it will be controlled naturally by IT
8946 with the proper pseudo-predicate
8947 - So the only interesting predicate is the one that
8948 tells that we are not on the last item of an IT
8949 block. */
8950 if (itblock_current_pos != 0)
8951 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8952
a504d23a
LA		 8953 if (insn_32bit)
8954 {
8955 /* Load the rest of the insn (in manual-friendly order). */
8956 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8957 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8958 is_vldm = is_thumb2_vldm (insn);
8959
8960 /* Veneers are created for (v)ldm depending on
8961 option flags and memory accesses conditions; but
8962 if the instruction is not the last instruction of
8963 an IT block, we cannot create a jump there, so we
8964 bail out. */
5025eb7c
AO		 8965 if ((is_ldm || is_vldm)
8966 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8967 (insn, globals->stm32l4xx_fix))
8968 {
8969 if (is_not_last_in_it_block)
8970 {
4eca0228 8971 _bfd_error_handler
695344c0 8972 /* xgettext:c-format */
871b3ab2 8973 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8974 " in non-last IT block instruction:"
8975 " STM32L4XX veneer cannot be generated; "
8976 "use gcc option -mrestrict-it to generate"
8977 " only one instruction per IT block"),
d42c267e 8978 abfd, sec, i);
a504d23a
LA		 8979 }
8980 else
8981 {
8982 elf32_stm32l4xx_erratum_list *newerr =
8983 (elf32_stm32l4xx_erratum_list *)
8984 bfd_zmalloc
8985 (sizeof (elf32_stm32l4xx_erratum_list));
8986
8987 elf32_arm_section_data (sec)
8988 ->stm32l4xx_erratumcount += 1;
8989 newerr->u.b.insn = insn;
8990 /* We create only thumb branches. */
8991 newerr->type =
8992 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8993 record_stm32l4xx_erratum_veneer
8994 (link_info, newerr, abfd, sec,
8995 i,
8996 is_ldm ?
8997 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8998 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8999 newerr->vma = -1;
9000 newerr->next = sec_data->stm32l4xx_erratumlist;
9001 sec_data->stm32l4xx_erratumlist = newerr;
9002 }
9003 }
9004 }
9005 else
9006 {
9007 /* A7.7.37 IT p208
9008 IT blocks are only encoded in T1
9009 Encoding T1: IT{x{y{z}}} <firstcond>
9010 1 0 1 1 - 1 1 1 1 - firstcond - mask
9011 if mask = '0000' then see 'related encodings'
9012 We don't deal with UNPREDICTABLE, just ignore these.
9013 There can be no nested IT blocks so an IT block
9014 is naturally a new one for which it is worth
9015 computing its size. */
5025eb7c
AO		 9016 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
9017 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 9018 /* If we have a new IT block we compute its size. */
9019 if (is_newitblock)
9020 {
9021 /* Compute the number of instructions controlled
9022 by the IT block, it will be used to decide
9023 whether we are inside an IT block or not. */
9024 unsigned int mask = insn & 0x000f;
9025 itblock_current_pos = 4 - ctz (mask);
9026 }
9027 }
9028
9029 i += insn_32bit ? 4 : 2;
99059e56
RM		 9030 }
9031 }
a504d23a
LA		 9032
9033 if (contents != NULL
9034 && elf_section_data (sec)->this_hdr.contents != contents)
9035 free (contents);
9036 contents = NULL;
c7b8f16e 9037 }
906e58ca 9038
a504d23a
LA		 9039 return TRUE;
9040
9041error_return:
9042 if (contents != NULL
9043 && elf_section_data (sec)->this_hdr.contents != contents)
9044 free (contents);
c7b8f16e 9045
a504d23a
LA		 9046 return FALSE;
9047}
c7b8f16e 9048
eb043451
PB		 9049/* Set target relocation values needed during linking. */
9050
9051void
68c39892 9052bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9053 struct bfd_link_info *link_info,
68c39892 9054 struct elf32_arm_params *params)
eb043451
PB		 9055{
9056 struct elf32_arm_link_hash_table *globals;
9057
9058 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9059 if (globals == NULL)
9060 return;
eb043451 9061
68c39892 9062 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9063 if (globals->fdpic_p)
9064 globals->target2_reloc = R_ARM_GOT32;
9065 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9066 globals->target2_reloc = R_ARM_REL32;
68c39892 9067 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9068 globals->target2_reloc = R_ARM_ABS32;
68c39892 9069 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9070 globals->target2_reloc = R_ARM_GOT_PREL;
9071 else
9072 {
90b6238f 9073 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9074 params->target2_type);
eb043451 9075 }
68c39892
TP		 9076 globals->fix_v4bx = params->fix_v4bx;
9077 globals->use_blx |= params->use_blx;
9078 globals->vfp11_fix = params->vfp11_denorm_fix;
9079 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9080 if (globals->fdpic_p)
9081 globals->pic_veneer = 1;
9082 else
9083 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9084 globals->fix_cortex_a8 = params->fix_cortex_a8;
9085 globals->fix_arm1176 = params->fix_arm1176;
9086 globals->cmse_implib = params->cmse_implib;
9087 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9088
0ffa91dd 9089 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9090 elf_arm_tdata (output_bfd)->no_enum_size_warning
9091 = params->no_enum_size_warning;
9092 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9093 = params->no_wchar_size_warning;
eb043451 9094}
eb043451 9095
12a0a0fd 9096/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9097
12a0a0fd
PB		 9098static void
9099insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9100{
9101 bfd_vma upper;
9102 bfd_vma lower;
9103 int reloc_sign;
9104
9105 BFD_ASSERT ((offset & 1) == 0);
9106
9107 upper = bfd_get_16 (abfd, insn);
9108 lower = bfd_get_16 (abfd, insn + 2);
9109 reloc_sign = (offset < 0) ? 1 : 0;
9110 upper = (upper & ~(bfd_vma) 0x7ff)
9111 | ((offset >> 12) & 0x3ff)
9112 | (reloc_sign << 10);
906e58ca 9113 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9114 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9115 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9116 | ((offset >> 1) & 0x7ff);
9117 bfd_put_16 (abfd, upper, insn);
9118 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9119}
9120
9b485d32
NC		 9121/* Thumb code calling an ARM function. */
9122
252b5132 9123static int
57e8b36a 9124elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9125 const char * name,
9126 bfd * input_bfd,
9127 bfd * output_bfd,
9128 asection * input_section,
9129 bfd_byte * hit_data,
9130 asection * sym_sec,
9131 bfd_vma offset,
9132 bfd_signed_vma addend,
9133 bfd_vma val,
f2a9dd69 9134 char **error_message)
252b5132 9135{
bcbdc74c 9136 asection * s = 0;
dc810e39 9137 bfd_vma my_offset;
252b5132 9138 long int ret_offset;
bcbdc74c
NC		 9139 struct elf_link_hash_entry * myh;
9140 struct elf32_arm_link_hash_table * globals;
252b5132 9141
f2a9dd69 9142 myh = find_thumb_glue (info, name, error_message);
252b5132 9143 if (myh == NULL)
b34976b6 9144 return FALSE;
252b5132
RH		 9145
9146 globals = elf32_arm_hash_table (info);
252b5132
RH		 9147 BFD_ASSERT (globals != NULL);
9148 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9149
9150 my_offset = myh->root.u.def.value;
9151
3d4d4302
AM		 9152 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9153 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9154
9155 BFD_ASSERT (s != NULL);
9156 BFD_ASSERT (s->contents != NULL);
9157 BFD_ASSERT (s->output_section != NULL);
9158
9159 if ((my_offset & 0x01) == 0x01)
9160 {
9161 if (sym_sec != NULL
9162 && sym_sec->owner != NULL
9163 && !INTERWORK_FLAG (sym_sec->owner))
9164 {
4eca0228 9165 _bfd_error_handler
90b6238f
AM		 9166 (_("%pB(%s): warning: interworking not enabled;"
9167 " first occurrence: %pB: %s call to %s"),
9168 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9169
b34976b6 9170 return FALSE;
252b5132
RH		 9171 }
9172
9173 --my_offset;
9174 myh->root.u.def.value = my_offset;
9175
52ab56c2
PB		 9176 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9177 s->contents + my_offset);
252b5132 9178
52ab56c2
PB		 9179 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9180 s->contents + my_offset + 2);
252b5132
RH		 9181
9182 ret_offset =
9b485d32
NC		 9183 /* Address of destination of the stub. */
9184 ((bfd_signed_vma) val)
252b5132 9185 - ((bfd_signed_vma)
57e8b36a
NC		 9186 /* Offset from the start of the current section
9187 to the start of the stubs. */
9b485d32
NC		 9188 (s->output_offset
9189 /* Offset of the start of this stub from the start of the stubs. */
9190 + my_offset
9191 /* Address of the start of the current section. */
9192 + s->output_section->vma)
9193 /* The branch instruction is 4 bytes into the stub. */
9194 + 4
9195 /* ARM branches work from the pc of the instruction + 8. */
9196 + 8);
252b5132 9197
52ab56c2
PB		 9198 put_arm_insn (globals, output_bfd,
9199 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9200 s->contents + my_offset + 4);
252b5132
RH		 9201 }
9202
9203 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9204
427bfd90
NC		 9205 /* Now go back and fix up the original BL insn to point to here. */
9206 ret_offset =
9207 /* Address of where the stub is located. */
9208 (s->output_section->vma + s->output_offset + my_offset)
9209 /* Address of where the BL is located. */
57e8b36a
NC		 9210 - (input_section->output_section->vma + input_section->output_offset
9211 + offset)
427bfd90
NC		 9212 /* Addend in the relocation. */
9213 - addend
9214 /* Biassing for PC-relative addressing. */
9215 - 8;
252b5132 9216
12a0a0fd 9217 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9218
b34976b6 9219 return TRUE;
252b5132
RH		 9220}
9221
a4fd1a8e 9222/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9223
a4fd1a8e
PB		 9224static struct elf_link_hash_entry *
9225elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9226 const char * name,
9227 bfd * input_bfd,
9228 bfd * output_bfd,
9229 asection * sym_sec,
9230 bfd_vma val,
9231 asection * s,
9232 char ** error_message)
252b5132 9233{
dc810e39 9234 bfd_vma my_offset;
252b5132 9235 long int ret_offset;
bcbdc74c
NC		 9236 struct elf_link_hash_entry * myh;
9237 struct elf32_arm_link_hash_table * globals;
252b5132 9238
f2a9dd69 9239 myh = find_arm_glue (info, name, error_message);
252b5132 9240 if (myh == NULL)
a4fd1a8e 9241 return NULL;
252b5132
RH		 9242
9243 globals = elf32_arm_hash_table (info);
252b5132
RH		 9244 BFD_ASSERT (globals != NULL);
9245 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9246
9247 my_offset = myh->root.u.def.value;
252b5132
RH		 9248
9249 if ((my_offset & 0x01) == 0x01)
9250 {
9251 if (sym_sec != NULL
9252 && sym_sec->owner != NULL
9253 && !INTERWORK_FLAG (sym_sec->owner))
9254 {
4eca0228 9255 _bfd_error_handler
90b6238f
AM		 9256 (_("%pB(%s): warning: interworking not enabled;"
9257 " first occurrence: %pB: %s call to %s"),
9258 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9259 }
9b485d32 9260
252b5132
RH		 9261 --my_offset;
9262 myh->root.u.def.value = my_offset;
9263
0e1862bb
L		 9264 if (bfd_link_pic (info)
9265 || globals->root.is_relocatable_executable
27e55c4d 9266 || globals->pic_veneer)
8f6277f5
PB		 9267 {
9268 /* For relocatable objects we can't use absolute addresses,
9269 so construct the address from a relative offset. */
9270 /* TODO: If the offset is small it's probably worth
9271 constructing the address with adds. */
52ab56c2
PB		 9272 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9273 s->contents + my_offset);
9274 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9275 s->contents + my_offset + 4);
9276 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9277 s->contents + my_offset + 8);
8f6277f5
PB		 9278 /* Adjust the offset by 4 for the position of the add,
9279 and 8 for the pipeline offset. */
9280 ret_offset = (val - (s->output_offset
9281 + s->output_section->vma
9282 + my_offset + 12))
9283 | 1;
9284 bfd_put_32 (output_bfd, ret_offset,
9285 s->contents + my_offset + 12);
9286 }
26079076
PB		 9287 else if (globals->use_blx)
9288 {
9289 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9290 s->contents + my_offset);
9291
9292 /* It's a thumb address. Add the low order bit. */
9293 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9294 s->contents + my_offset + 4);
9295 }
8f6277f5
PB		 9296 else
9297 {
52ab56c2
PB		 9298 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9299 s->contents + my_offset);
252b5132 9300
52ab56c2
PB		 9301 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9302 s->contents + my_offset + 4);
252b5132 9303
8f6277f5
PB		 9304 /* It's a thumb address. Add the low order bit. */
9305 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9306 s->contents + my_offset + 8);
8029a119
NC		 9307
9308 my_offset += 12;
8f6277f5 9309 }
252b5132
RH		 9310 }
9311
9312 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9313
a4fd1a8e
PB		 9314 return myh;
9315}
9316
9317/* Arm code calling a Thumb function. */
9318
9319static int
9320elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9321 const char * name,
9322 bfd * input_bfd,
9323 bfd * output_bfd,
9324 asection * input_section,
9325 bfd_byte * hit_data,
9326 asection * sym_sec,
9327 bfd_vma offset,
9328 bfd_signed_vma addend,
9329 bfd_vma val,
f2a9dd69 9330 char **error_message)
a4fd1a8e
PB		 9331{
9332 unsigned long int tmp;
9333 bfd_vma my_offset;
9334 asection * s;
9335 long int ret_offset;
9336 struct elf_link_hash_entry * myh;
9337 struct elf32_arm_link_hash_table * globals;
9338
9339 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9340 BFD_ASSERT (globals != NULL);
9341 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9342
3d4d4302
AM		 9343 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9344 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9345 BFD_ASSERT (s != NULL);
9346 BFD_ASSERT (s->contents != NULL);
9347 BFD_ASSERT (s->output_section != NULL);
9348
9349 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9350 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9351 if (!myh)
9352 return FALSE;
9353
9354 my_offset = myh->root.u.def.value;
252b5132
RH		 9355 tmp = bfd_get_32 (input_bfd, hit_data);
9356 tmp = tmp & 0xFF000000;
9357
9b485d32 9358 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9359 ret_offset = (s->output_offset
9360 + my_offset
9361 + s->output_section->vma
9362 - (input_section->output_offset
9363 + input_section->output_section->vma
9364 + offset + addend)
9365 - 8);
9a5aca8c 9366
252b5132
RH		 9367 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9368
dc810e39 9369 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9370
b34976b6 9371 return TRUE;
252b5132
RH		 9372}
9373
a4fd1a8e
PB		 9374/* Populate Arm stub for an exported Thumb function. */
9375
9376static bfd_boolean
9377elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9378{
9379 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9380 asection * s;
9381 struct elf_link_hash_entry * myh;
9382 struct elf32_arm_link_hash_entry *eh;
9383 struct elf32_arm_link_hash_table * globals;
9384 asection *sec;
9385 bfd_vma val;
f2a9dd69 9386 char *error_message;
a4fd1a8e 9387
906e58ca 9388 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9389 /* Allocate stubs for exported Thumb functions on v4t. */
9390 if (eh->export_glue == NULL)
9391 return TRUE;
9392
9393 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9394 BFD_ASSERT (globals != NULL);
9395 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9396
3d4d4302
AM		 9397 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9398 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9399 BFD_ASSERT (s != NULL);
9400 BFD_ASSERT (s->contents != NULL);
9401 BFD_ASSERT (s->output_section != NULL);
9402
9403 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9404
9405 BFD_ASSERT (sec->output_section != NULL);
9406
a4fd1a8e
PB		 9407 val = eh->export_glue->root.u.def.value + sec->output_offset
9408 + sec->output_section->vma;
8029a119 9409
a4fd1a8e
PB		 9410 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9411 h->root.u.def.section->owner,
f2a9dd69
DJ		 9412 globals->obfd, sec, val, s,
9413 &error_message);
a4fd1a8e
PB		 9414 BFD_ASSERT (myh);
9415 return TRUE;
9416}
9417
845b51d6
PB		 9418/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9419
9420static bfd_vma
9421elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9422{
9423 bfd_byte *p;
9424 bfd_vma glue_addr;
9425 asection *s;
9426 struct elf32_arm_link_hash_table *globals;
9427
9428 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9429 BFD_ASSERT (globals != NULL);
9430 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9431
3d4d4302
AM		 9432 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9433 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9434 BFD_ASSERT (s != NULL);
9435 BFD_ASSERT (s->contents != NULL);
9436 BFD_ASSERT (s->output_section != NULL);
9437
9438 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9439
9440 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9441
9442 if ((globals->bx_glue_offset[reg] & 1) == 0)
9443 {
9444 p = s->contents + glue_addr;
9445 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9446 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9447 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9448 globals->bx_glue_offset[reg] |= 1;
9449 }
9450
9451 return glue_addr + s->output_section->vma + s->output_offset;
9452}
9453
a4fd1a8e
PB		 9454/* Generate Arm stubs for exported Thumb symbols. */
9455static void
906e58ca 9456elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9457 struct bfd_link_info *link_info)
9458{
9459 struct elf32_arm_link_hash_table * globals;
9460
8029a119
NC		 9461 if (link_info == NULL)
9462 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9463 return;
9464
9465 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9466 if (globals == NULL)
9467 return;
9468
84c08195
PB		 9469 /* If blx is available then exported Thumb symbols are OK and there is
9470 nothing to do. */
a4fd1a8e
PB		 9471 if (globals->use_blx)
9472 return;
9473
9474 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9475 link_info);
9476}
9477
47beaa6a
RS		 9478/* Reserve space for COUNT dynamic relocations in relocation selection
9479 SRELOC. */
9480
9481static void
9482elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9483 bfd_size_type count)
9484{
9485 struct elf32_arm_link_hash_table *htab;
9486
9487 htab = elf32_arm_hash_table (info);
9488 BFD_ASSERT (htab->root.dynamic_sections_created);
9489 if (sreloc == NULL)
9490 abort ();
9491 sreloc->size += RELOC_SIZE (htab) * count;
9492}
9493
34e77a92
RS		 9494/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9495 dynamic, the relocations should go in SRELOC, otherwise they should
9496 go in the special .rel.iplt section. */
9497
9498static void
9499elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9500 bfd_size_type count)
9501{
9502 struct elf32_arm_link_hash_table *htab;
9503
9504 htab = elf32_arm_hash_table (info);
9505 if (!htab->root.dynamic_sections_created)
9506 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9507 else
9508 {
9509 BFD_ASSERT (sreloc != NULL);
9510 sreloc->size += RELOC_SIZE (htab) * count;
9511 }
9512}
9513
47beaa6a
RS		 9514/* Add relocation REL to the end of relocation section SRELOC. */
9515
9516static void
9517elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9518 asection *sreloc, Elf_Internal_Rela *rel)
9519{
9520 bfd_byte *loc;
9521 struct elf32_arm_link_hash_table *htab;
9522
9523 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9524 if (!htab->root.dynamic_sections_created
9525 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9526 sreloc = htab->root.irelplt;
47beaa6a
RS		 9527 if (sreloc == NULL)
9528 abort ();
9529 loc = sreloc->contents;
9530 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9531 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9532 abort ();
9533 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9534}
9535
34e77a92
RS		 9536/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9537 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9538 to .plt. */
9539
9540static void
9541elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9542 bfd_boolean is_iplt_entry,
9543 union gotplt_union *root_plt,
9544 struct arm_plt_info *arm_plt)
9545{
9546 struct elf32_arm_link_hash_table *htab;
9547 asection *splt;
9548 asection *sgotplt;
9549
9550 htab = elf32_arm_hash_table (info);
9551
9552 if (is_iplt_entry)
9553 {
9554 splt = htab->root.iplt;
9555 sgotplt = htab->root.igotplt;
9556
99059e56
RM		 9557 /* NaCl uses a special first entry in .iplt too. */
9558 if (htab->nacl_p && splt->size == 0)
9559 splt->size += htab->plt_header_size;
9560
34e77a92
RS		 9561 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9562 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9563 }
9564 else
9565 {
9566 splt = htab->root.splt;
9567 sgotplt = htab->root.sgotplt;
9568
7801f98f
CL		 9569 if (htab->fdpic_p)
9570 {
9571 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9572 /* For lazy binding, relocations will be put into .rel.plt, in
9573 .rel.got otherwise. */
9574 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9575 if (info->flags & DF_BIND_NOW)
9576 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9577 else
9578 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9579 }
9580 else
9581 {
9582 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9583 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9584 }
34e77a92
RS		 9585
9586 /* If this is the first .plt entry, make room for the special
9587 first entry. */
9588 if (splt->size == 0)
9589 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9590
9591 htab->next_tls_desc_index++;
34e77a92
RS		 9592 }
9593
9594 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9595 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9596 splt->size += PLT_THUMB_STUB_SIZE;
9597 root_plt->offset = splt->size;
9598 splt->size += htab->plt_entry_size;
9599
9600 if (!htab->symbian_p)
9601 {
9602 /* We also need to make an entry in the .got.plt section, which
9603 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9604 if (is_iplt_entry)
9605 arm_plt->got_offset = sgotplt->size;
9606 else
9607 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9608 if (htab->fdpic_p)
9609 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9610 sgotplt->size += 8;
7801f98f
CL		 9611 else
9612 sgotplt->size += 4;
34e77a92
RS		 9613 }
9614}
9615
b38cadfb
NC		 9616static bfd_vma
9617arm_movw_immediate (bfd_vma value)
9618{
9619 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9620}
9621
9622static bfd_vma
9623arm_movt_immediate (bfd_vma value)
9624{
9625 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9626}
9627
34e77a92
RS		 9628/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9629 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9630 Otherwise, DYNINDX is the index of the symbol in the dynamic
9631 symbol table and SYM_VALUE is undefined.
9632
9633 ROOT_PLT points to the offset of the PLT entry from the start of its
9634 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9635 bookkeeping information.
34e77a92 9636
57460bcf
NC		 9637 Returns FALSE if there was a problem. */
9638
9639static bfd_boolean
34e77a92
RS		 9640elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9641 union gotplt_union *root_plt,
9642 struct arm_plt_info *arm_plt,
9643 int dynindx, bfd_vma sym_value)
9644{
9645 struct elf32_arm_link_hash_table *htab;
9646 asection *sgot;
9647 asection *splt;
9648 asection *srel;
9649 bfd_byte *loc;
9650 bfd_vma plt_index;
9651 Elf_Internal_Rela rel;
9652 bfd_vma plt_header_size;
9653 bfd_vma got_header_size;
9654
9655 htab = elf32_arm_hash_table (info);
9656
9657 /* Pick the appropriate sections and sizes. */
9658 if (dynindx == -1)
9659 {
9660 splt = htab->root.iplt;
9661 sgot = htab->root.igotplt;
9662 srel = htab->root.irelplt;
9663
9664 /* There are no reserved entries in .igot.plt, and no special
9665 first entry in .iplt. */
9666 got_header_size = 0;
9667 plt_header_size = 0;
9668 }
9669 else
9670 {
9671 splt = htab->root.splt;
9672 sgot = htab->root.sgotplt;
9673 srel = htab->root.srelplt;
9674
9675 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9676 plt_header_size = htab->plt_header_size;
9677 }
9678 BFD_ASSERT (splt != NULL && srel != NULL);
9679
9680 /* Fill in the entry in the procedure linkage table. */
9681 if (htab->symbian_p)
9682 {
9683 BFD_ASSERT (dynindx >= 0);
9684 put_arm_insn (htab, output_bfd,
9685 elf32_arm_symbian_plt_entry[0],
9686 splt->contents + root_plt->offset);
9687 bfd_put_32 (output_bfd,
9688 elf32_arm_symbian_plt_entry[1],
9689 splt->contents + root_plt->offset + 4);
9690
9691 /* Fill in the entry in the .rel.plt section. */
9692 rel.r_offset = (splt->output_section->vma
9693 + splt->output_offset
9694 + root_plt->offset + 4);
9695 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9696
9697 /* Get the index in the procedure linkage table which
9698 corresponds to this symbol. This is the index of this symbol
9699 in all the symbols for which we are making plt entries. The
9700 first entry in the procedure linkage table is reserved. */
9701 plt_index = ((root_plt->offset - plt_header_size)
9702 / htab->plt_entry_size);
9703 }
9704 else
9705 {
9706 bfd_vma got_offset, got_address, plt_address;
9707 bfd_vma got_displacement, initial_got_entry;
9708 bfd_byte * ptr;
9709
9710 BFD_ASSERT (sgot != NULL);
9711
9712 /* Get the offset into the .(i)got.plt table of the entry that
9713 corresponds to this function. */
9714 got_offset = (arm_plt->got_offset & -2);
9715
9716 /* Get the index in the procedure linkage table which
9717 corresponds to this symbol. This is the index of this symbol
9718 in all the symbols for which we are making plt entries.
9719 After the reserved .got.plt entries, all symbols appear in
9720 the same order as in .plt. */
7801f98f 9721 if (htab->fdpic_p)
4b24dd1a
AM		 9722 /* Function descriptor takes 8 bytes. */
9723 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9724 else
4b24dd1a 9725 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9726
9727 /* Calculate the address of the GOT entry. */
9728 got_address = (sgot->output_section->vma
9729 + sgot->output_offset
9730 + got_offset);
9731
9732 /* ...and the address of the PLT entry. */
9733 plt_address = (splt->output_section->vma
9734 + splt->output_offset
9735 + root_plt->offset);
9736
9737 ptr = splt->contents + root_plt->offset;
0e1862bb 9738 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9739 {
9740 unsigned int i;
9741 bfd_vma val;
9742
9743 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9744 {
9745 val = elf32_arm_vxworks_shared_plt_entry[i];
9746 if (i == 2)
9747 val |= got_address - sgot->output_section->vma;
9748 if (i == 5)
9749 val |= plt_index * RELOC_SIZE (htab);
9750 if (i == 2 || i == 5)
9751 bfd_put_32 (output_bfd, val, ptr);
9752 else
9753 put_arm_insn (htab, output_bfd, val, ptr);
9754 }
9755 }
9756 else if (htab->vxworks_p)
9757 {
9758 unsigned int i;
9759 bfd_vma val;
9760
9761 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9762 {
9763 val = elf32_arm_vxworks_exec_plt_entry[i];
9764 if (i == 2)
9765 val |= got_address;
9766 if (i == 4)
9767 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9768 if (i == 5)
9769 val |= plt_index * RELOC_SIZE (htab);
9770 if (i == 2 || i == 5)
9771 bfd_put_32 (output_bfd, val, ptr);
9772 else
9773 put_arm_insn (htab, output_bfd, val, ptr);
9774 }
9775
9776 loc = (htab->srelplt2->contents
9777 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9778
9779 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9780 referencing the GOT for this PLT entry. */
9781 rel.r_offset = plt_address + 8;
9782 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9783 rel.r_addend = got_offset;
9784 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9785 loc += RELOC_SIZE (htab);
9786
9787 /* Create the R_ARM_ABS32 relocation referencing the
9788 beginning of the PLT for this GOT entry. */
9789 rel.r_offset = got_address;
9790 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9791 rel.r_addend = 0;
9792 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9793 }
b38cadfb
NC		 9794 else if (htab->nacl_p)
9795 {
9796 /* Calculate the displacement between the PLT slot and the
9797 common tail that's part of the special initial PLT slot. */
6034aab8 9798 int32_t tail_displacement
b38cadfb
NC		 9799 = ((splt->output_section->vma + splt->output_offset
9800 + ARM_NACL_PLT_TAIL_OFFSET)
9801 - (plt_address + htab->plt_entry_size + 4));
9802 BFD_ASSERT ((tail_displacement & 3) == 0);
9803 tail_displacement >>= 2;
9804
9805 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9806 || (-tail_displacement & 0xff000000) == 0);
9807
9808 /* Calculate the displacement between the PLT slot and the entry
9809 in the GOT. The offset accounts for the value produced by
9810 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9811 got_displacement = (got_address
99059e56 9812 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9813
9814 /* NaCl does not support interworking at all. */
9815 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9816
9817 put_arm_insn (htab, output_bfd,
9818 elf32_arm_nacl_plt_entry[0]
9819 | arm_movw_immediate (got_displacement),
9820 ptr + 0);
9821 put_arm_insn (htab, output_bfd,
9822 elf32_arm_nacl_plt_entry[1]
9823 | arm_movt_immediate (got_displacement),
9824 ptr + 4);
9825 put_arm_insn (htab, output_bfd,
9826 elf32_arm_nacl_plt_entry[2],
9827 ptr + 8);
9828 put_arm_insn (htab, output_bfd,
9829 elf32_arm_nacl_plt_entry[3]
9830 | (tail_displacement & 0x00ffffff),
9831 ptr + 12);
9832 }
7801f98f
CL		 9833 else if (htab->fdpic_p)
9834 {
59029f57
CL		 9835 const bfd_vma *plt_entry = using_thumb_only(htab)
9836 ? elf32_arm_fdpic_thumb_plt_entry
9837 : elf32_arm_fdpic_plt_entry;
9838
7801f98f
CL		 9839 /* Fill-up Thumb stub if needed. */
9840 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9841 {
9842 put_thumb_insn (htab, output_bfd,
9843 elf32_arm_plt_thumb_stub[0], ptr - 4);
9844 put_thumb_insn (htab, output_bfd,
9845 elf32_arm_plt_thumb_stub[1], ptr - 2);
9846 }
59029f57
CL		 9847 /* As we are using 32 bit instructions even for the Thumb
9848 version, we have to use 'put_arm_insn' instead of
9849 'put_thumb_insn'. */
9850 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9851 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9852 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9853 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9854 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9855
9856 if (!(info->flags & DF_BIND_NOW))
9857 {
9858 /* funcdesc_value_reloc_offset. */
9859 bfd_put_32 (output_bfd,
9860 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9861 ptr + 20);
59029f57
CL		 9862 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9863 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9864 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9865 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9866 }
9867 }
57460bcf
NC		 9868 else if (using_thumb_only (htab))
9869 {
eed94f8f 9870 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9871 if (!using_thumb2 (htab))
eed94f8f
NC		 9872 {
9873 /* FIXME: We ought to be able to generate thumb-1 PLT
9874 instructions... */
90b6238f 9875 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9876 output_bfd);
9877 return FALSE;
9878 }
57460bcf 9879
eed94f8f
NC		 9880 /* Calculate the displacement between the PLT slot and the entry in
9881 the GOT. The 12-byte offset accounts for the value produced by
9882 adding to pc in the 3rd instruction of the PLT stub. */
9883 got_displacement = got_address - (plt_address + 12);
9884
9885 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9886 instead of 'put_thumb_insn'. */
9887 put_arm_insn (htab, output_bfd,
9888 elf32_thumb2_plt_entry[0]
9889 | ((got_displacement & 0x000000ff) << 16)
9890 | ((got_displacement & 0x00000700) << 20)
9891 | ((got_displacement & 0x00000800) >> 1)
9892 | ((got_displacement & 0x0000f000) >> 12),
9893 ptr + 0);
9894 put_arm_insn (htab, output_bfd,
9895 elf32_thumb2_plt_entry[1]
9896 | ((got_displacement & 0x00ff0000) )
9897 | ((got_displacement & 0x07000000) << 4)
9898 | ((got_displacement & 0x08000000) >> 17)
9899 | ((got_displacement & 0xf0000000) >> 28),
9900 ptr + 4);
9901 put_arm_insn (htab, output_bfd,
9902 elf32_thumb2_plt_entry[2],
9903 ptr + 8);
9904 put_arm_insn (htab, output_bfd,
9905 elf32_thumb2_plt_entry[3],
9906 ptr + 12);
57460bcf 9907 }
34e77a92
RS		 9908 else
9909 {
9910 /* Calculate the displacement between the PLT slot and the
9911 entry in the GOT. The eight-byte offset accounts for the
9912 value produced by adding to pc in the first instruction
9913 of the PLT stub. */
9914 got_displacement = got_address - (plt_address + 8);
9915
34e77a92
RS		 9916 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9917 {
9918 put_thumb_insn (htab, output_bfd,
9919 elf32_arm_plt_thumb_stub[0], ptr - 4);
9920 put_thumb_insn (htab, output_bfd,
9921 elf32_arm_plt_thumb_stub[1], ptr - 2);
9922 }
9923
1db37fe6
YG		 9924 if (!elf32_arm_use_long_plt_entry)
9925 {
9926 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9927
9928 put_arm_insn (htab, output_bfd,
9929 elf32_arm_plt_entry_short[0]
9930 | ((got_displacement & 0x0ff00000) >> 20),
9931 ptr + 0);
9932 put_arm_insn (htab, output_bfd,
9933 elf32_arm_plt_entry_short[1]
9934 | ((got_displacement & 0x000ff000) >> 12),
9935 ptr+ 4);
9936 put_arm_insn (htab, output_bfd,
9937 elf32_arm_plt_entry_short[2]
9938 | (got_displacement & 0x00000fff),
9939 ptr + 8);
34e77a92 9940#ifdef FOUR_WORD_PLT
1db37fe6 9941 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9942#endif
1db37fe6
YG		 9943 }
9944 else
9945 {
9946 put_arm_insn (htab, output_bfd,
9947 elf32_arm_plt_entry_long[0]
9948 | ((got_displacement & 0xf0000000) >> 28),
9949 ptr + 0);
9950 put_arm_insn (htab, output_bfd,
9951 elf32_arm_plt_entry_long[1]
9952 | ((got_displacement & 0x0ff00000) >> 20),
9953 ptr + 4);
9954 put_arm_insn (htab, output_bfd,
9955 elf32_arm_plt_entry_long[2]
9956 | ((got_displacement & 0x000ff000) >> 12),
9957 ptr+ 8);
9958 put_arm_insn (htab, output_bfd,
9959 elf32_arm_plt_entry_long[3]
9960 | (got_displacement & 0x00000fff),
9961 ptr + 12);
9962 }
34e77a92
RS		 9963 }
9964
9965 /* Fill in the entry in the .rel(a).(i)plt section. */
9966 rel.r_offset = got_address;
9967 rel.r_addend = 0;
9968 if (dynindx == -1)
9969 {
9970 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9971 The dynamic linker or static executable then calls SYM_VALUE
9972 to determine the correct run-time value of the .igot.plt entry. */
9973 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9974 initial_got_entry = sym_value;
9975 }
9976 else
9977 {
7801f98f
CL		 9978 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9979 used by PLT entry. */
9980 if (htab->fdpic_p)
9981 {
9982 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9983 initial_got_entry = 0;
9984 }
9985 else
9986 {
9987 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9988 initial_got_entry = (splt->output_section->vma
9989 + splt->output_offset);
9990 }
34e77a92
RS		 9991 }
9992
9993 /* Fill in the entry in the global offset table. */
9994 bfd_put_32 (output_bfd, initial_got_entry,
9995 sgot->contents + got_offset);
7801f98f
CL		 9996
9997 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9998 {
9999 /* Setup initial funcdesc value. */
10000 /* FIXME: we don't support lazy binding because there is a
10001 race condition between both words getting written and
10002 some other thread attempting to read them. The ARM
10003 architecture does not have an atomic 64 bit load/store
10004 instruction that could be used to prevent it; it is
10005 recommended that threaded FDPIC applications run with the
10006 LD_BIND_NOW environment variable set. */
10007 bfd_put_32(output_bfd, plt_address + 0x18,
10008 sgot->contents + got_offset);
10009 bfd_put_32(output_bfd, -1 /*TODO*/,
10010 sgot->contents + got_offset + 4);
10011 }
34e77a92
RS		 10012 }
10013
aba8c3de
WN		 10014 if (dynindx == -1)
10015 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
10016 else
10017 {
7801f98f
CL		 10018 if (htab->fdpic_p)
10019 {
10020 /* For FDPIC we put PLT relocationss into .rel.got when not
10021 lazy binding otherwise we put them in .rel.plt. For now,
10022 we don't support lazy binding so put it in .rel.got. */
10023 if (info->flags & DF_BIND_NOW)
10024 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
10025 else
10026 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
10027 }
10028 else
10029 {
10030 loc = srel->contents + plt_index * RELOC_SIZE (htab);
10031 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
10032 }
aba8c3de 10033 }
57460bcf
NC		 10034
10035 return TRUE;
34e77a92
RS		 10036}
10037
eb043451
PB		 10038/* Some relocations map to different relocations depending on the
10039 target. Return the real relocation. */
8029a119 10040
eb043451
PB		 10041static int
10042arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10043 int r_type)
10044{
10045 switch (r_type)
10046 {
10047 case R_ARM_TARGET1:
10048 if (globals->target1_is_rel)
10049 return R_ARM_REL32;
10050 else
10051 return R_ARM_ABS32;
10052
10053 case R_ARM_TARGET2:
10054 return globals->target2_reloc;
10055
10056 default:
10057 return r_type;
10058 }
10059}
eb043451 10060
ba93b8ac
DJ		 10061/* Return the base VMA address which should be subtracted from real addresses
10062 when resolving @dtpoff relocation.
10063 This is PT_TLS segment p_vaddr. */
10064
10065static bfd_vma
10066dtpoff_base (struct bfd_link_info *info)
10067{
10068 /* If tls_sec is NULL, we should have signalled an error already. */
10069 if (elf_hash_table (info)->tls_sec == NULL)
10070 return 0;
10071 return elf_hash_table (info)->tls_sec->vma;
10072}
10073
10074/* Return the relocation value for @tpoff relocation
10075 if STT_TLS virtual address is ADDRESS. */
10076
10077static bfd_vma
10078tpoff (struct bfd_link_info *info, bfd_vma address)
10079{
10080 struct elf_link_hash_table *htab = elf_hash_table (info);
10081 bfd_vma base;
10082
10083 /* If tls_sec is NULL, we should have signalled an error already. */
10084 if (htab->tls_sec == NULL)
10085 return 0;
10086 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10087 return address - htab->tls_sec->vma + base;
10088}
10089
00a97672
RS		 10090/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10091 VALUE is the relocation value. */
10092
10093static bfd_reloc_status_type
10094elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10095{
10096 if (value > 0xfff)
10097 return bfd_reloc_overflow;
10098
10099 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10100 bfd_put_32 (abfd, value, data);
10101 return bfd_reloc_ok;
10102}
10103
0855e32b
NS		 10104/* Handle TLS relaxations. Relaxing is possible for symbols that use
10105 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10106 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10107
10108 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10109 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10110 case of error.
10111
10112 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10113 the pre-relaxed code. It would be nice if the relocs were updated
10114 to match the optimization. */
0855e32b 10115
b38cadfb 10116static bfd_reloc_status_type
0855e32b 10117elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10118 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10119 Elf_Internal_Rela *rel, unsigned long is_local)
10120{
10121 unsigned long insn;
b38cadfb 10122
0855e32b
NS		 10123 switch (ELF32_R_TYPE (rel->r_info))
10124 {
10125 default:
10126 return bfd_reloc_notsupported;
b38cadfb 10127
0855e32b
NS		 10128 case R_ARM_TLS_GOTDESC:
10129 if (is_local)
10130 insn = 0;
10131 else
10132 {
10133 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10134 if (insn & 1)
10135 insn -= 5; /* THUMB */
10136 else
10137 insn -= 8; /* ARM */
10138 }
10139 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10140 return bfd_reloc_continue;
10141
10142 case R_ARM_THM_TLS_DESCSEQ:
10143 /* Thumb insn. */
10144 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10145 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10146 {
10147 if (is_local)
10148 /* nop */
10149 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10150 }
10151 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10152 {
10153 if (is_local)
10154 /* nop */
10155 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10156 else
10157 /* ldr rx,[ry] */
10158 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10159 }
10160 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10161 {
10162 if (is_local)
10163 /* nop */
10164 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10165 else
10166 /* mov r0, rx */
10167 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10168 contents + rel->r_offset);
10169 }
10170 else
10171 {
10172 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10173 /* It's a 32 bit instruction, fetch the rest of it for
10174 error generation. */
10175 insn = (insn << 16)
10176 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10177 _bfd_error_handler
695344c0 10178 /* xgettext:c-format */
2dcf00ce 10179 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10180 "unexpected %s instruction '%#lx' in TLS trampoline"),
10181 input_bfd, input_sec, (uint64_t) rel->r_offset,
10182 "Thumb", insn);
0855e32b
NS		 10183 return bfd_reloc_notsupported;
10184 }
10185 break;
b38cadfb 10186
0855e32b
NS		 10187 case R_ARM_TLS_DESCSEQ:
10188 /* arm insn. */
10189 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10190 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10191 {
10192 if (is_local)
10193 /* mov rx, ry */
10194 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10195 contents + rel->r_offset);
10196 }
10197 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10198 {
10199 if (is_local)
10200 /* nop */
10201 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10202 else
10203 /* ldr rx,[ry] */
10204 bfd_put_32 (input_bfd, insn & 0xfffff000,
10205 contents + rel->r_offset);
10206 }
10207 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10208 {
10209 if (is_local)
10210 /* nop */
10211 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10212 else
10213 /* mov r0, rx */
10214 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10215 contents + rel->r_offset);
10216 }
10217 else
10218 {
4eca0228 10219 _bfd_error_handler
695344c0 10220 /* xgettext:c-format */
2dcf00ce 10221 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10222 "unexpected %s instruction '%#lx' in TLS trampoline"),
10223 input_bfd, input_sec, (uint64_t) rel->r_offset,
10224 "ARM", insn);
0855e32b
NS		 10225 return bfd_reloc_notsupported;
10226 }
10227 break;
10228
10229 case R_ARM_TLS_CALL:
10230 /* GD->IE relaxation, turn the instruction into 'nop' or
10231 'ldr r0, [pc,r0]' */
10232 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10233 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10234 break;
b38cadfb 10235
0855e32b 10236 case R_ARM_THM_TLS_CALL:
6a631e86 10237 /* GD->IE relaxation. */
0855e32b
NS		 10238 if (!is_local)
10239 /* add r0,pc; ldr r0, [r0] */
10240 insn = 0x44786800;
60a019a0 10241 else if (using_thumb2 (globals))
0855e32b
NS		 10242 /* nop.w */
10243 insn = 0xf3af8000;
10244 else
10245 /* nop; nop */
10246 insn = 0xbf00bf00;
b38cadfb 10247
0855e32b
NS		 10248 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10249 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10250 break;
10251 }
10252 return bfd_reloc_ok;
10253}
10254
4962c51a
MS		 10255/* For a given value of n, calculate the value of G_n as required to
10256 deal with group relocations. We return it in the form of an
10257 encoded constant-and-rotation, together with the final residual. If n is
10258 specified as less than zero, then final_residual is filled with the
10259 input value and no further action is performed. */
10260
10261static bfd_vma
10262calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10263{
10264 int current_n;
10265 bfd_vma g_n;
10266 bfd_vma encoded_g_n = 0;
10267 bfd_vma residual = value; /* Also known as Y_n. */
10268
10269 for (current_n = 0; current_n <= n; current_n++)
10270 {
10271 int shift;
10272
10273 /* Calculate which part of the value to mask. */
10274 if (residual == 0)
99059e56 10275 shift = 0;
4962c51a 10276 else
99059e56
RM		 10277 {
10278 int msb;
10279
10280 /* Determine the most significant bit in the residual and
10281 align the resulting value to a 2-bit boundary. */
10282 for (msb = 30; msb >= 0; msb -= 2)
10283 if (residual & (3 << msb))
10284 break;
10285
10286 /* The desired shift is now (msb - 6), or zero, whichever
10287 is the greater. */
10288 shift = msb - 6;
10289 if (shift < 0)
10290 shift = 0;
10291 }
4962c51a
MS		 10292
10293 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10294 g_n = residual & (0xff << shift);
10295 encoded_g_n = (g_n >> shift)
99059e56 10296 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10297
10298 /* Calculate the residual for the next time around. */
10299 residual &= ~g_n;
10300 }
10301
10302 *final_residual = residual;
10303
10304 return encoded_g_n;
10305}
10306
10307/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10308 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10309
4962c51a 10310static int
906e58ca 10311identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10312{
10313 int opcode = insn & 0x1e00000;
10314
10315 if (opcode == 1 << 23) /* ADD */
10316 return 1;
10317
10318 if (opcode == 1 << 22) /* SUB */
10319 return -1;
10320
10321 return 0;
10322}
10323
252b5132 10324/* Perform a relocation as part of a final link. */
9b485d32 10325
252b5132 10326static bfd_reloc_status_type
07d6d2b8
AM		 10327elf32_arm_final_link_relocate (reloc_howto_type * howto,
10328 bfd * input_bfd,
10329 bfd * output_bfd,
10330 asection * input_section,
10331 bfd_byte * contents,
10332 Elf_Internal_Rela * rel,
10333 bfd_vma value,
10334 struct bfd_link_info * info,
10335 asection * sym_sec,
10336 const char * sym_name,
10337 unsigned char st_type,
10338 enum arm_st_branch_type branch_type,
0945cdfd 10339 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10340 bfd_boolean * unresolved_reloc_p,
10341 char ** error_message)
10342{
10343 unsigned long r_type = howto->type;
10344 unsigned long r_symndx;
10345 bfd_byte * hit_data = contents + rel->r_offset;
10346 bfd_vma * local_got_offsets;
10347 bfd_vma * local_tlsdesc_gotents;
10348 asection * sgot;
10349 asection * splt;
10350 asection * sreloc = NULL;
10351 asection * srelgot;
10352 bfd_vma addend;
10353 bfd_signed_vma signed_addend;
10354 unsigned char dynreloc_st_type;
10355 bfd_vma dynreloc_value;
ba96a88f 10356 struct elf32_arm_link_hash_table * globals;
34e77a92 10357 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10358 union gotplt_union *root_plt;
10359 struct arm_plt_info *arm_plt;
10360 bfd_vma plt_offset;
10361 bfd_vma gotplt_offset;
10362 bfd_boolean has_iplt_entry;
10363 bfd_boolean resolved_to_zero;
f21f3fe0 10364
9c504268 10365 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10366 if (globals == NULL)
10367 return bfd_reloc_notsupported;
9c504268 10368
0ffa91dd 10369 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10370 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10371
10372 /* Some relocation types map to different relocations depending on the
9c504268 10373 target. We pick the right one here. */
eb043451 10374 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10375
10376 /* It is possible to have linker relaxations on some TLS access
10377 models. Update our information here. */
10378 r_type = elf32_arm_tls_transition (info, r_type, h);
10379
eb043451
PB		 10380 if (r_type != howto->type)
10381 howto = elf32_arm_howto_from_type (r_type);
9c504268 10382
34e77a92 10383 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10384 sgot = globals->root.sgot;
252b5132 10385 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10386 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10387
34e77a92
RS		 10388 if (globals->root.dynamic_sections_created)
10389 srelgot = globals->root.srelgot;
10390 else
10391 srelgot = NULL;
10392
252b5132
RH		 10393 r_symndx = ELF32_R_SYM (rel->r_info);
10394
4e7fd91e 10395 if (globals->use_rel)
ba96a88f 10396 {
4e7fd91e
PB		 10397 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10398
10399 if (addend & ((howto->src_mask + 1) >> 1))
10400 {
10401 signed_addend = -1;
10402 signed_addend &= ~ howto->src_mask;
10403 signed_addend |= addend;
10404 }
10405 else
10406 signed_addend = addend;
ba96a88f
NC		 10407 }
10408 else
4e7fd91e 10409 addend = signed_addend = rel->r_addend;
f21f3fe0 10410
39f21624
NC		 10411 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10412 are resolving a function call relocation. */
10413 if (using_thumb_only (globals)
10414 && (r_type == R_ARM_THM_CALL
10415 || r_type == R_ARM_THM_JUMP24)
10416 && branch_type == ST_BRANCH_TO_ARM)
10417 branch_type = ST_BRANCH_TO_THUMB;
10418
34e77a92
RS		 10419 /* Record the symbol information that should be used in dynamic
10420 relocations. */
10421 dynreloc_st_type = st_type;
10422 dynreloc_value = value;
10423 if (branch_type == ST_BRANCH_TO_THUMB)
10424 dynreloc_value |= 1;
10425
10426 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10427 VALUE appropriately for relocations that we resolve at link time. */
10428 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10429 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10430 &arm_plt)
34e77a92
RS		 10431 && root_plt->offset != (bfd_vma) -1)
10432 {
10433 plt_offset = root_plt->offset;
10434 gotplt_offset = arm_plt->got_offset;
10435
10436 if (h == NULL || eh->is_iplt)
10437 {
10438 has_iplt_entry = TRUE;
10439 splt = globals->root.iplt;
10440
10441 /* Populate .iplt entries here, because not all of them will
10442 be seen by finish_dynamic_symbol. The lower bit is set if
10443 we have already populated the entry. */
10444 if (plt_offset & 1)
10445 plt_offset--;
10446 else
10447 {
57460bcf
NC		 10448 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10449 -1, dynreloc_value))
10450 root_plt->offset |= 1;
10451 else
10452 return bfd_reloc_notsupported;
34e77a92
RS		 10453 }
10454
10455 /* Static relocations always resolve to the .iplt entry. */
10456 st_type = STT_FUNC;
10457 value = (splt->output_section->vma
10458 + splt->output_offset
10459 + plt_offset);
10460 branch_type = ST_BRANCH_TO_ARM;
10461
10462 /* If there are non-call relocations that resolve to the .iplt
10463 entry, then all dynamic ones must too. */
10464 if (arm_plt->noncall_refcount != 0)
10465 {
10466 dynreloc_st_type = st_type;
10467 dynreloc_value = value;
10468 }
10469 }
10470 else
10471 /* We populate the .plt entry in finish_dynamic_symbol. */
10472 splt = globals->root.splt;
10473 }
10474 else
10475 {
10476 splt = NULL;
10477 plt_offset = (bfd_vma) -1;
10478 gotplt_offset = (bfd_vma) -1;
10479 }
10480
95b03e4a
L		 10481 resolved_to_zero = (h != NULL
10482 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10483
252b5132
RH		 10484 switch (r_type)
10485 {
10486 case R_ARM_NONE:
28a094c2
DJ		 10487 /* We don't need to find a value for this symbol. It's just a
10488 marker. */
10489 *unresolved_reloc_p = FALSE;
252b5132
RH		 10490 return bfd_reloc_ok;
10491
00a97672
RS		 10492 case R_ARM_ABS12:
10493 if (!globals->vxworks_p)
10494 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10495 /* Fall through. */
00a97672 10496
252b5132
RH		 10497 case R_ARM_PC24:
10498 case R_ARM_ABS32:
bb224fc3 10499 case R_ARM_ABS32_NOI:
252b5132 10500 case R_ARM_REL32:
bb224fc3 10501 case R_ARM_REL32_NOI:
5b5bb741
PB		 10502 case R_ARM_CALL:
10503 case R_ARM_JUMP24:
dfc5f959 10504 case R_ARM_XPC25:
eb043451 10505 case R_ARM_PREL31:
7359ea65 10506 case R_ARM_PLT32:
7359ea65
DJ		 10507 /* Handle relocations which should use the PLT entry. ABS32/REL32
10508 will use the symbol's value, which may point to a PLT entry, but we
10509 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10510 branches in this object should go to it, except if the PLT is too
10511 far away, in which case a long branch stub should be inserted. */
bb224fc3 10512 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10513 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10514 && r_type != R_ARM_CALL
10515 && r_type != R_ARM_JUMP24
10516 && r_type != R_ARM_PLT32)
34e77a92 10517 && plt_offset != (bfd_vma) -1)
7359ea65 10518 {
34e77a92
RS		 10519 /* If we've created a .plt section, and assigned a PLT entry
10520 to this function, it must either be a STT_GNU_IFUNC reference
10521 or not be known to bind locally. In other cases, we should
10522 have cleared the PLT entry by now. */
10523 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10524
10525 value = (splt->output_section->vma
10526 + splt->output_offset
34e77a92 10527 + plt_offset);
0945cdfd 10528 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10529 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10530 contents, rel->r_offset, value,
00a97672 10531 rel->r_addend);
7359ea65
DJ		 10532 }
10533
67687978
PB		 10534 /* When generating a shared object or relocatable executable, these
10535 relocations are copied into the output file to be resolved at
10536 run time. */
0e1862bb 10537 if ((bfd_link_pic (info)
e8b09b87
CL		 10538 || globals->root.is_relocatable_executable
10539 || globals->fdpic_p)
7359ea65 10540 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10541 && !(globals->vxworks_p
3348747a
NS		 10542 && strcmp (input_section->output_section->name,
10543 ".tls_vars") == 0)
bb224fc3 10544 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10545 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10546 && !(input_bfd == globals->stub_bfd
10547 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10548 && (h == NULL
95b03e4a
L		 10549 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10550 && !resolved_to_zero)
7359ea65
DJ		 10551 || h->root.type != bfd_link_hash_undefweak)
10552 && r_type != R_ARM_PC24
5b5bb741
PB		 10553 && r_type != R_ARM_CALL
10554 && r_type != R_ARM_JUMP24
ee06dc07 10555 && r_type != R_ARM_PREL31
7359ea65 10556 && r_type != R_ARM_PLT32)
252b5132 10557 {
947216bf 10558 Elf_Internal_Rela outrel;
b34976b6 10559 bfd_boolean skip, relocate;
e8b09b87 10560 int isrofixup = 0;
f21f3fe0 10561
52db4ec2
JW		 10562 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10563 && !h->def_regular)
10564 {
10565 char *v = _("shared object");
10566
0e1862bb 10567 if (bfd_link_executable (info))
52db4ec2
JW		 10568 v = _("PIE executable");
10569
4eca0228 10570 _bfd_error_handler
871b3ab2 10571 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10572 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10573 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10574 return bfd_reloc_notsupported;
10575 }
10576
0945cdfd
DJ		 10577 *unresolved_reloc_p = FALSE;
10578
34e77a92 10579 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10580 {
83bac4b0
NC		 10581 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10582 ! globals->use_rel);
f21f3fe0 10583
83bac4b0 10584 if (sreloc == NULL)
252b5132 10585 return bfd_reloc_notsupported;
252b5132 10586 }
f21f3fe0 10587
b34976b6
AM		 10588 skip = FALSE;
10589 relocate = FALSE;
f21f3fe0 10590
00a97672 10591 outrel.r_addend = addend;
c629eae0
JJ		 10592 outrel.r_offset =
10593 _bfd_elf_section_offset (output_bfd, info, input_section,
10594 rel->r_offset);
10595 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10596 skip = TRUE;
0bb2d96a 10597 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10598 skip = TRUE, relocate = TRUE;
252b5132
RH		 10599 outrel.r_offset += (input_section->output_section->vma
10600 + input_section->output_offset);
f21f3fe0 10601
252b5132 10602 if (skip)
0bb2d96a 10603 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10604 else if (h != NULL
10605 && h->dynindx != -1
0e1862bb 10606 && (!bfd_link_pic (info)
1dcb9720
JW		 10607 || !(bfd_link_pie (info)
10608 || SYMBOLIC_BIND (info, h))
f5385ebf 10609 || !h->def_regular))
5e681ec4 10610 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10611 else
10612 {
a16385dc
MM		 10613 int symbol;
10614
5e681ec4 10615 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10616 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10617 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10618 if (globals->symbian_p)
6366ff1e 10619 {
74541ad4
AM		 10620 asection *osec;
10621
6366ff1e
MM		 10622 /* On Symbian OS, the data segment and text segement
10623 can be relocated independently. Therefore, we
10624 must indicate the segment to which this
10625 relocation is relative. The BPABI allows us to
10626 use any symbol in the right segment; we just use
10627 the section symbol as it is convenient. (We
10628 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10629 will not appear in the dynamic symbol table.)
10630
10631 Note that the dynamic linker ignores the section
10632 symbol value, so we don't subtract osec->vma
10633 from the emitted reloc addend. */
10dbd1f3 10634 if (sym_sec)
74541ad4 10635 osec = sym_sec->output_section;
10dbd1f3 10636 else
74541ad4
AM		 10637 osec = input_section->output_section;
10638 symbol = elf_section_data (osec)->dynindx;
10639 if (symbol == 0)
10640 {
10641 struct elf_link_hash_table *htab = elf_hash_table (info);
10642
10643 if ((osec->flags & SEC_READONLY) == 0
10644 && htab->data_index_section != NULL)
10645 osec = htab->data_index_section;
10646 else
10647 osec = htab->text_index_section;
10648 symbol = elf_section_data (osec)->dynindx;
10649 }
6366ff1e
MM		 10650 BFD_ASSERT (symbol != 0);
10651 }
a16385dc
MM		 10652 else
10653 /* On SVR4-ish systems, the dynamic loader cannot
10654 relocate the text and data segments independently,
10655 so the symbol does not matter. */
10656 symbol = 0;
34e77a92
RS		 10657 if (dynreloc_st_type == STT_GNU_IFUNC)
10658 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10659 to the .iplt entry. Instead, every non-call reference
10660 must use an R_ARM_IRELATIVE relocation to obtain the
10661 correct run-time address. */
10662 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10663 else if (globals->fdpic_p && !bfd_link_pic(info))
10664 isrofixup = 1;
34e77a92
RS		 10665 else
10666 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10667 if (globals->use_rel)
10668 relocate = TRUE;
10669 else
34e77a92 10670 outrel.r_addend += dynreloc_value;
252b5132 10671 }
f21f3fe0 10672
e8b09b87
CL		 10673 if (isrofixup)
10674 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10675 else
10676 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10677
f21f3fe0 10678 /* If this reloc is against an external symbol, we do not want to
252b5132 10679 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10680 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10681 if (! relocate)
10682 return bfd_reloc_ok;
9a5aca8c 10683
f21f3fe0 10684 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10685 contents, rel->r_offset,
10686 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10687 }
10688 else switch (r_type)
10689 {
00a97672
RS		 10690 case R_ARM_ABS12:
10691 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10692
dfc5f959 10693 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10694 case R_ARM_CALL:
10695 case R_ARM_JUMP24:
8029a119 10696 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10697 case R_ARM_PLT32:
906e58ca 10698 {
906e58ca
NC		 10699 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10700
dfc5f959 10701 if (r_type == R_ARM_XPC25)
252b5132 10702 {
dfc5f959
NC		 10703 /* Check for Arm calling Arm function. */
10704 /* FIXME: Should we translate the instruction into a BL
10705 instruction instead ? */
35fc36a8 10706 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10707 _bfd_error_handler
90b6238f
AM		 10708 (_("\%pB: warning: %s BLX instruction targets"
10709 " %s function '%s'"),
10710 input_bfd, "ARM",
10711 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10712 }
155d87d7 10713 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10714 {
10715 /* Check for Arm calling Thumb function. */
35fc36a8 10716 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10717 {
f2a9dd69
DJ		 10718 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10719 output_bfd, input_section,
10720 hit_data, sym_sec, rel->r_offset,
10721 signed_addend, value,
10722 error_message))
10723 return bfd_reloc_ok;
10724 else
10725 return bfd_reloc_dangerous;
dfc5f959 10726 }
252b5132 10727 }
ba96a88f 10728
906e58ca 10729 /* Check if a stub has to be inserted because the
8029a119 10730 destination is too far or we are changing mode. */
155d87d7
CL		 10731 if ( r_type == R_ARM_CALL
10732 || r_type == R_ARM_JUMP24
10733 || r_type == R_ARM_PLT32)
906e58ca 10734 {
fe33d2fa
CL		 10735 enum elf32_arm_stub_type stub_type = arm_stub_none;
10736 struct elf32_arm_link_hash_entry *hash;
10737
10738 hash = (struct elf32_arm_link_hash_entry *) h;
10739 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10740 st_type, &branch_type,
10741 hash, value, sym_sec,
fe33d2fa 10742 input_bfd, sym_name);
5fa9e92f 10743
fe33d2fa 10744 if (stub_type != arm_stub_none)
906e58ca
NC		 10745 {
10746 /* The target is out of reach, so redirect the
10747 branch to the local stub for this function. */
906e58ca
NC		 10748 stub_entry = elf32_arm_get_stub_entry (input_section,
10749 sym_sec, h,
fe33d2fa
CL		 10750 rel, globals,
10751 stub_type);
9cd3e4e5
NC		 10752 {
10753 if (stub_entry != NULL)
10754 value = (stub_entry->stub_offset
10755 + stub_entry->stub_sec->output_offset
10756 + stub_entry->stub_sec->output_section->vma);
10757
10758 if (plt_offset != (bfd_vma) -1)
10759 *unresolved_reloc_p = FALSE;
10760 }
906e58ca 10761 }
fe33d2fa
CL		 10762 else
10763 {
10764 /* If the call goes through a PLT entry, make sure to
10765 check distance to the right destination address. */
34e77a92 10766 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10767 {
10768 value = (splt->output_section->vma
10769 + splt->output_offset
34e77a92 10770 + plt_offset);
fe33d2fa
CL		 10771 *unresolved_reloc_p = FALSE;
10772 /* The PLT entry is in ARM mode, regardless of the
10773 target function. */
35fc36a8 10774 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10775 }
10776 }
906e58ca
NC		 10777 }
10778
dea514f5
PB		 10779 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10780 where:
10781 S is the address of the symbol in the relocation.
10782 P is address of the instruction being relocated.
10783 A is the addend (extracted from the instruction) in bytes.
10784
10785 S is held in 'value'.
10786 P is the base address of the section containing the
10787 instruction plus the offset of the reloc into that
10788 section, ie:
10789 (input_section->output_section->vma +
10790 input_section->output_offset +
10791 rel->r_offset).
10792 A is the addend, converted into bytes, ie:
10793 (signed_addend * 4)
10794
10795 Note: None of these operations have knowledge of the pipeline
10796 size of the processor, thus it is up to the assembler to
10797 encode this information into the addend. */
10798 value -= (input_section->output_section->vma
10799 + input_section->output_offset);
10800 value -= rel->r_offset;
4e7fd91e
PB		 10801 if (globals->use_rel)
10802 value += (signed_addend << howto->size);
10803 else
10804 /* RELA addends do not have to be adjusted by howto->size. */
10805 value += signed_addend;
23080146 10806
dcb5e6e6
NC		 10807 signed_addend = value;
10808 signed_addend >>= howto->rightshift;
9a5aca8c 10809
5ab79981 10810 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10811 the next instruction unless a PLT entry will be created.
77b4f08f 10812 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10813 The jump to the next instruction is optimized as a NOP depending
10814 on the architecture. */
ffcb4889 10815 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10816 && plt_offset == (bfd_vma) -1)
77b4f08f 10817 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10818 {
cd1dac3d
DG		 10819 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10820
10821 if (arch_has_arm_nop (globals))
10822 value |= 0x0320f000;
10823 else
10824 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10825 }
10826 else
59f2c4e7 10827 {
9b485d32 10828 /* Perform a signed range check. */
dcb5e6e6 10829 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10830 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10831 return bfd_reloc_overflow;
9a5aca8c 10832
5ab79981 10833 addend = (value & 2);
39b41c9c 10834
5ab79981
PB		 10835 value = (signed_addend & howto->dst_mask)
10836 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10837
5ab79981
PB		 10838 if (r_type == R_ARM_CALL)
10839 {
155d87d7 10840 /* Set the H bit in the BLX instruction. */
35fc36a8 10841 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10842 {
10843 if (addend)
10844 value |= (1 << 24);
10845 else
10846 value &= ~(bfd_vma)(1 << 24);
10847 }
10848
5ab79981 10849 /* Select the correct instruction (BL or BLX). */
906e58ca 10850 /* Only if we are not handling a BL to a stub. In this
8029a119 10851 case, mode switching is performed by the stub. */
35fc36a8 10852 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10853 value |= (1 << 28);
63e1a0fc 10854 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10855 {
10856 value &= ~(bfd_vma)(1 << 28);
10857 value |= (1 << 24);
10858 }
39b41c9c
PB		 10859 }
10860 }
906e58ca 10861 }
252b5132 10862 break;
f21f3fe0 10863
252b5132
RH		 10864 case R_ARM_ABS32:
10865 value += addend;
35fc36a8 10866 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10867 value |= 1;
10868 break;
f21f3fe0 10869
bb224fc3
MS		 10870 case R_ARM_ABS32_NOI:
10871 value += addend;
10872 break;
10873
252b5132 10874 case R_ARM_REL32:
a8bc6c78 10875 value += addend;
35fc36a8 10876 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10877 value |= 1;
252b5132 10878 value -= (input_section->output_section->vma
62efb346 10879 + input_section->output_offset + rel->r_offset);
252b5132 10880 break;
eb043451 10881
bb224fc3
MS		 10882 case R_ARM_REL32_NOI:
10883 value += addend;
10884 value -= (input_section->output_section->vma
10885 + input_section->output_offset + rel->r_offset);
10886 break;
10887
eb043451
PB		 10888 case R_ARM_PREL31:
10889 value -= (input_section->output_section->vma
10890 + input_section->output_offset + rel->r_offset);
10891 value += signed_addend;
10892 if (! h || h->root.type != bfd_link_hash_undefweak)
10893 {
8029a119 10894 /* Check for overflow. */
eb043451
PB		 10895 if ((value ^ (value >> 1)) & (1 << 30))
10896 return bfd_reloc_overflow;
10897 }
10898 value &= 0x7fffffff;
10899 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10900 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10901 value |= 1;
10902 break;
252b5132 10903 }
f21f3fe0 10904
252b5132
RH		 10905 bfd_put_32 (input_bfd, value, hit_data);
10906 return bfd_reloc_ok;
10907
10908 case R_ARM_ABS8:
fd0fd00c
MJ		 10909 /* PR 16202: Refectch the addend using the correct size. */
10910 if (globals->use_rel)
10911 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10912 value += addend;
4e67d4ca
DG		 10913
10914 /* There is no way to tell whether the user intended to use a signed or
10915 unsigned addend. When checking for overflow we accept either,
10916 as specified by the AAELF. */
10917 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10918 return bfd_reloc_overflow;
10919
10920 bfd_put_8 (input_bfd, value, hit_data);
10921 return bfd_reloc_ok;
10922
10923 case R_ARM_ABS16:
fd0fd00c
MJ		 10924 /* PR 16202: Refectch the addend using the correct size. */
10925 if (globals->use_rel)
10926 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10927 value += addend;
10928
4e67d4ca
DG		 10929 /* See comment for R_ARM_ABS8. */
10930 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10931 return bfd_reloc_overflow;
10932
10933 bfd_put_16 (input_bfd, value, hit_data);
10934 return bfd_reloc_ok;
10935
252b5132 10936 case R_ARM_THM_ABS5:
9b485d32 10937 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10938 if (globals->use_rel)
10939 {
10940 /* Need to refetch addend. */
10941 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10942 /* ??? Need to determine shift amount from operand size. */
10943 addend >>= howto->rightshift;
10944 }
252b5132
RH		 10945 value += addend;
10946
10947 /* ??? Isn't value unsigned? */
10948 if ((long) value > 0x1f || (long) value < -0x10)
10949 return bfd_reloc_overflow;
10950
10951 /* ??? Value needs to be properly shifted into place first. */
10952 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10953 bfd_put_16 (input_bfd, value, hit_data);
10954 return bfd_reloc_ok;
10955
2cab6cc3
MS		 10956 case R_ARM_THM_ALU_PREL_11_0:
10957 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10958 {
10959 bfd_vma insn;
10960 bfd_signed_vma relocation;
10961
10962 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10963 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10964
99059e56
RM		 10965 if (globals->use_rel)
10966 {
10967 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10968 | ((insn & (1 << 26)) >> 15);
10969 if (insn & 0xf00000)
10970 signed_addend = -signed_addend;
10971 }
2cab6cc3
MS		 10972
10973 relocation = value + signed_addend;
79f08007 10974 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10975 + input_section->output_offset
10976 + rel->r_offset);
2cab6cc3 10977
8c65b54f
CS		 10978 /* PR 21523: Use an absolute value. The user of this reloc will
10979 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10980 value = llabs (relocation);
2cab6cc3 10981
99059e56
RM		 10982 if (value >= 0x1000)
10983 return bfd_reloc_overflow;
2cab6cc3 10984
e645cf40
AG		 10985 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10986 if (branch_type == ST_BRANCH_TO_THUMB)
10987 value |= 1;
10988
2cab6cc3 10989 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10990 | ((value & 0x700) << 4)
10991 | ((value & 0x800) << 15);
10992 if (relocation < 0)
10993 insn |= 0xa00000;
2cab6cc3
MS		 10994
10995 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10996 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10997
99059e56 10998 return bfd_reloc_ok;
2cab6cc3
MS		 10999 }
11000
e1ec24c6
NC		 11001 case R_ARM_THM_PC8:
11002 /* PR 10073: This reloc is not generated by the GNU toolchain,
11003 but it is supported for compatibility with third party libraries
11004 generated by other compilers, specifically the ARM/IAR. */
11005 {
11006 bfd_vma insn;
11007 bfd_signed_vma relocation;
11008
11009 insn = bfd_get_16 (input_bfd, hit_data);
11010
99059e56 11011 if (globals->use_rel)
79f08007 11012 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 11013
11014 relocation = value + addend;
79f08007 11015 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11016 + input_section->output_offset
11017 + rel->r_offset);
e1ec24c6 11018
b6518b38 11019 value = relocation;
e1ec24c6
NC		 11020
11021 /* We do not check for overflow of this reloc. Although strictly
11022 speaking this is incorrect, it appears to be necessary in order
11023 to work with IAR generated relocs. Since GCC and GAS do not
11024 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11025 a problem for them. */
11026 value &= 0x3fc;
11027
11028 insn = (insn & 0xff00) | (value >> 2);
11029
11030 bfd_put_16 (input_bfd, insn, hit_data);
11031
99059e56 11032 return bfd_reloc_ok;
e1ec24c6
NC		 11033 }
11034
2cab6cc3
MS		 11035 case R_ARM_THM_PC12:
11036 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11037 {
11038 bfd_vma insn;
11039 bfd_signed_vma relocation;
11040
11041 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11042 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11043
99059e56
RM		 11044 if (globals->use_rel)
11045 {
11046 signed_addend = insn & 0xfff;
11047 if (!(insn & (1 << 23)))
11048 signed_addend = -signed_addend;
11049 }
2cab6cc3
MS		 11050
11051 relocation = value + signed_addend;
79f08007 11052 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11053 + input_section->output_offset
11054 + rel->r_offset);
2cab6cc3 11055
b6518b38 11056 value = relocation;
2cab6cc3 11057
99059e56
RM		 11058 if (value >= 0x1000)
11059 return bfd_reloc_overflow;
2cab6cc3
MS		 11060
11061 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11062 if (relocation >= 0)
11063 insn |= (1 << 23);
2cab6cc3
MS		 11064
11065 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11066 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11067
99059e56 11068 return bfd_reloc_ok;
2cab6cc3
MS		 11069 }
11070
dfc5f959 11071 case R_ARM_THM_XPC22:
c19d1205 11072 case R_ARM_THM_CALL:
bd97cb95 11073 case R_ARM_THM_JUMP24:
dfc5f959 11074 /* Thumb BL (branch long instruction). */
252b5132 11075 {
b34976b6 11076 bfd_vma relocation;
99059e56 11077 bfd_vma reloc_sign;
b34976b6
AM		 11078 bfd_boolean overflow = FALSE;
11079 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11080 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11081 bfd_signed_vma reloc_signed_max;
11082 bfd_signed_vma reloc_signed_min;
b34976b6 11083 bfd_vma check;
252b5132 11084 bfd_signed_vma signed_check;
e95de063 11085 int bitsize;
cd1dac3d 11086 const int thumb2 = using_thumb2 (globals);
5e866f5a 11087 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11088
5ab79981 11089 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11090 the next instruction unless a PLT entry will be created.
11091 The jump to the next instruction is optimized as a NOP.W for
11092 Thumb-2 enabled architectures. */
19540007 11093 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11094 && plt_offset == (bfd_vma) -1)
5ab79981 11095 {
60a019a0 11096 if (thumb2)
cd1dac3d
DG		 11097 {
11098 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11099 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11100 }
11101 else
11102 {
11103 bfd_put_16 (input_bfd, 0xe000, hit_data);
11104 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11105 }
5ab79981
PB		 11106 return bfd_reloc_ok;
11107 }
11108
e95de063 11109 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11110 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11111 if (globals->use_rel)
11112 {
99059e56
RM		 11113 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11114 bfd_vma upper = upper_insn & 0x3ff;
11115 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11116 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11117 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11118 bfd_vma i1 = j1 ^ s ? 0 : 1;
11119 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11120
99059e56
RM		 11121 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11122 /* Sign extend. */
11123 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11124
4e7fd91e
PB		 11125 signed_addend = addend;
11126 }
cb1afa5c 11127
dfc5f959
NC		 11128 if (r_type == R_ARM_THM_XPC22)
11129 {
11130 /* Check for Thumb to Thumb call. */
11131 /* FIXME: Should we translate the instruction into a BL
11132 instruction instead ? */
35fc36a8 11133 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11134 _bfd_error_handler
90b6238f
AM		 11135 (_("%pB: warning: %s BLX instruction targets"
11136 " %s function '%s'"),
11137 input_bfd, "Thumb",
11138 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11139 }
11140 else
252b5132 11141 {
dfc5f959
NC		 11142 /* If it is not a call to Thumb, assume call to Arm.
11143 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11144 function call at all, but rather a long jump. Calls through
11145 the PLT do not require stubs. */
34e77a92 11146 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11147 {
bd97cb95 11148 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11149 {
11150 /* Convert BL to BLX. */
11151 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11152 }
155d87d7
CL		 11153 else if (( r_type != R_ARM_THM_CALL)
11154 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11155 {
11156 if (elf32_thumb_to_arm_stub
11157 (info, sym_name, input_bfd, output_bfd, input_section,
11158 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11159 error_message))
11160 return bfd_reloc_ok;
11161 else
11162 return bfd_reloc_dangerous;
11163 }
da5938a2 11164 }
35fc36a8
RS		 11165 else if (branch_type == ST_BRANCH_TO_THUMB
11166 && globals->use_blx
bd97cb95 11167 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11168 {
11169 /* Make sure this is a BL. */
11170 lower_insn |= 0x1800;
11171 }
252b5132 11172 }
f21f3fe0 11173
fe33d2fa 11174 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11175 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11176 {
11177 /* Check if a stub has to be inserted because the destination
8029a119 11178 is too far. */
fe33d2fa
CL		 11179 struct elf32_arm_stub_hash_entry *stub_entry;
11180 struct elf32_arm_link_hash_entry *hash;
11181
11182 hash = (struct elf32_arm_link_hash_entry *) h;
11183
11184 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11185 st_type, &branch_type,
11186 hash, value, sym_sec,
fe33d2fa
CL		 11187 input_bfd, sym_name);
11188
11189 if (stub_type != arm_stub_none)
906e58ca
NC		 11190 {
11191 /* The target is out of reach or we are changing modes, so
11192 redirect the branch to the local stub for this
11193 function. */
11194 stub_entry = elf32_arm_get_stub_entry (input_section,
11195 sym_sec, h,
fe33d2fa
CL		 11196 rel, globals,
11197 stub_type);
906e58ca 11198 if (stub_entry != NULL)
9cd3e4e5
NC		 11199 {
11200 value = (stub_entry->stub_offset
11201 + stub_entry->stub_sec->output_offset
11202 + stub_entry->stub_sec->output_section->vma);
11203
11204 if (plt_offset != (bfd_vma) -1)
11205 *unresolved_reloc_p = FALSE;
11206 }
906e58ca 11207
f4ac8484 11208 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11209 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11210 {
11211 if ((stub_entry
11212 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11213 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11214 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11215 }
906e58ca
NC		 11216 }
11217 }
11218
fe33d2fa 11219 /* Handle calls via the PLT. */
34e77a92 11220 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11221 {
11222 value = (splt->output_section->vma
11223 + splt->output_offset
34e77a92 11224 + plt_offset);
fe33d2fa 11225
eed94f8f
NC		 11226 if (globals->use_blx
11227 && r_type == R_ARM_THM_CALL
11228 && ! using_thumb_only (globals))
fe33d2fa
CL		 11229 {
11230 /* If the Thumb BLX instruction is available, convert
11231 the BL to a BLX instruction to call the ARM-mode
11232 PLT entry. */
11233 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11234 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11235 }
11236 else
11237 {
eed94f8f
NC		 11238 if (! using_thumb_only (globals))
11239 /* Target the Thumb stub before the ARM PLT entry. */
11240 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11241 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11242 }
11243 *unresolved_reloc_p = FALSE;
11244 }
11245
ba96a88f 11246 relocation = value + signed_addend;
f21f3fe0 11247
252b5132 11248 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11249 + input_section->output_offset
11250 + rel->r_offset);
9a5aca8c 11251
252b5132
RH		 11252 check = relocation >> howto->rightshift;
11253
11254 /* If this is a signed value, the rightshift just dropped
11255 leading 1 bits (assuming twos complement). */
11256 if ((bfd_signed_vma) relocation >= 0)
11257 signed_check = check;
11258 else
11259 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11260
e95de063
MS		 11261 /* Calculate the permissable maximum and minimum values for
11262 this relocation according to whether we're relocating for
11263 Thumb-2 or not. */
11264 bitsize = howto->bitsize;
5e866f5a 11265 if (!thumb2_bl)
e95de063 11266 bitsize -= 2;
f6ebfac0 11267 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11268 reloc_signed_min = ~reloc_signed_max;
11269
252b5132 11270 /* Assumes two's complement. */
ba96a88f 11271 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11272 overflow = TRUE;
252b5132 11273
bd97cb95 11274 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11275 /* For a BLX instruction, make sure that the relocation is rounded up
11276 to a word boundary. This follows the semantics of the instruction
11277 which specifies that bit 1 of the target address will come from bit
11278 1 of the base address. */
11279 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11280
e95de063
MS		 11281 /* Put RELOCATION back into the insn. Assumes two's complement.
11282 We use the Thumb-2 encoding, which is safe even if dealing with
11283 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11284 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11285 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11286 | ((relocation >> 12) & 0x3ff)
11287 | (reloc_sign << 10);
906e58ca 11288 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11289 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11290 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11291 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11292
252b5132
RH		 11293 /* Put the relocated value back in the object file: */
11294 bfd_put_16 (input_bfd, upper_insn, hit_data);
11295 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11296
11297 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11298 }
11299 break;
11300
c19d1205
ZW		 11301 case R_ARM_THM_JUMP19:
11302 /* Thumb32 conditional branch instruction. */
11303 {
11304 bfd_vma relocation;
11305 bfd_boolean overflow = FALSE;
11306 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11307 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11308 bfd_signed_vma reloc_signed_max = 0xffffe;
11309 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11310 bfd_signed_vma signed_check;
07d6d2b8 11311 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11312 struct elf32_arm_stub_hash_entry *stub_entry;
11313 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11314
11315 /* Need to refetch the addend, reconstruct the top three bits,
11316 and squish the two 11 bit pieces together. */
11317 if (globals->use_rel)
11318 {
11319 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11320 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11321 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11322 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11323 bfd_vma lower = (lower_insn & 0x07ff);
11324
a00a1f35
MS		 11325 upper |= J1 << 6;
11326 upper |= J2 << 7;
11327 upper |= (!S) << 8;
c19d1205
ZW		 11328 upper -= 0x0100; /* Sign extend. */
11329
11330 addend = (upper << 12) | (lower << 1);
11331 signed_addend = addend;
11332 }
11333
bd97cb95 11334 /* Handle calls via the PLT. */
34e77a92 11335 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11336 {
11337 value = (splt->output_section->vma
11338 + splt->output_offset
34e77a92 11339 + plt_offset);
bd97cb95
DJ		 11340 /* Target the Thumb stub before the ARM PLT entry. */
11341 value -= PLT_THUMB_STUB_SIZE;
11342 *unresolved_reloc_p = FALSE;
11343 }
11344
c5423981
TG		 11345 hash = (struct elf32_arm_link_hash_entry *)h;
11346
11347 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11348 st_type, &branch_type,
11349 hash, value, sym_sec,
11350 input_bfd, sym_name);
c5423981
TG		 11351 if (stub_type != arm_stub_none)
11352 {
11353 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11354 sym_sec, h,
11355 rel, globals,
11356 stub_type);
c5423981
TG		 11357 if (stub_entry != NULL)
11358 {
07d6d2b8
AM		 11359 value = (stub_entry->stub_offset
11360 + stub_entry->stub_sec->output_offset
11361 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11362 }
11363 }
c19d1205 11364
99059e56 11365 relocation = value + signed_addend;
c19d1205
ZW		 11366 relocation -= (input_section->output_section->vma
11367 + input_section->output_offset
11368 + rel->r_offset);
a00a1f35 11369 signed_check = (bfd_signed_vma) relocation;
c19d1205 11370
c19d1205
ZW		 11371 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11372 overflow = TRUE;
11373
11374 /* Put RELOCATION back into the insn. */
11375 {
11376 bfd_vma S = (relocation & 0x00100000) >> 20;
11377 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11378 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11379 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11380 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11381
a00a1f35 11382 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11383 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11384 }
11385
11386 /* Put the relocated value back in the object file: */
11387 bfd_put_16 (input_bfd, upper_insn, hit_data);
11388 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11389
11390 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11391 }
11392
11393 case R_ARM_THM_JUMP11:
11394 case R_ARM_THM_JUMP8:
11395 case R_ARM_THM_JUMP6:
51c5503b
NC		 11396 /* Thumb B (branch) instruction). */
11397 {
6cf9e9fe 11398 bfd_signed_vma relocation;
51c5503b
NC		 11399 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11400 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11401 bfd_signed_vma signed_check;
11402
c19d1205
ZW		 11403 /* CZB cannot jump backward. */
11404 if (r_type == R_ARM_THM_JUMP6)
11405 reloc_signed_min = 0;
11406
4e7fd91e 11407 if (globals->use_rel)
6cf9e9fe 11408 {
4e7fd91e
PB		 11409 /* Need to refetch addend. */
11410 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11411 if (addend & ((howto->src_mask + 1) >> 1))
11412 {
11413 signed_addend = -1;
11414 signed_addend &= ~ howto->src_mask;
11415 signed_addend |= addend;
11416 }
11417 else
11418 signed_addend = addend;
11419 /* The value in the insn has been right shifted. We need to
11420 undo this, so that we can perform the address calculation
11421 in terms of bytes. */
11422 signed_addend <<= howto->rightshift;
6cf9e9fe 11423 }
6cf9e9fe 11424 relocation = value + signed_addend;
51c5503b
NC		 11425
11426 relocation -= (input_section->output_section->vma
11427 + input_section->output_offset
11428 + rel->r_offset);
11429
6cf9e9fe
NC		 11430 relocation >>= howto->rightshift;
11431 signed_check = relocation;
c19d1205
ZW		 11432
11433 if (r_type == R_ARM_THM_JUMP6)
11434 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11435 else
11436 relocation &= howto->dst_mask;
51c5503b 11437 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11438
51c5503b
NC		 11439 bfd_put_16 (input_bfd, relocation, hit_data);
11440
11441 /* Assumes two's complement. */
11442 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11443 return bfd_reloc_overflow;
11444
11445 return bfd_reloc_ok;
11446 }
cedb70c5 11447
8375c36b
PB		 11448 case R_ARM_ALU_PCREL7_0:
11449 case R_ARM_ALU_PCREL15_8:
11450 case R_ARM_ALU_PCREL23_15:
11451 {
11452 bfd_vma insn;
11453 bfd_vma relocation;
11454
11455 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11456 if (globals->use_rel)
11457 {
11458 /* Extract the addend. */
11459 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11460 signed_addend = addend;
11461 }
8375c36b
PB		 11462 relocation = value + signed_addend;
11463
11464 relocation -= (input_section->output_section->vma
11465 + input_section->output_offset
11466 + rel->r_offset);
11467 insn = (insn & ~0xfff)
11468 | ((howto->bitpos << 7) & 0xf00)
11469 | ((relocation >> howto->bitpos) & 0xff);
11470 bfd_put_32 (input_bfd, value, hit_data);
11471 }
11472 return bfd_reloc_ok;
11473
252b5132
RH		 11474 case R_ARM_GNU_VTINHERIT:
11475 case R_ARM_GNU_VTENTRY:
11476 return bfd_reloc_ok;
11477
c19d1205 11478 case R_ARM_GOTOFF32:
252b5132 11479 /* Relocation is relative to the start of the
99059e56 11480 global offset table. */
252b5132
RH		 11481
11482 BFD_ASSERT (sgot != NULL);
11483 if (sgot == NULL)
99059e56 11484 return bfd_reloc_notsupported;
9a5aca8c 11485
cedb70c5 11486 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11487 address by one, so that attempts to call the function pointer will
11488 correctly interpret it as Thumb code. */
35fc36a8 11489 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11490 value += 1;
11491
252b5132 11492 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11493 calculation. We always want the start of .got. If we
11494 define _GLOBAL_OFFSET_TABLE in a different way, as is
11495 permitted by the ABI, we might have to change this
11496 calculation. */
252b5132 11497 value -= sgot->output_section->vma;
f21f3fe0 11498 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11499 contents, rel->r_offset, value,
00a97672 11500 rel->r_addend);
252b5132
RH		 11501
11502 case R_ARM_GOTPC:
a7c10850 11503 /* Use global offset table as symbol value. */
252b5132 11504 BFD_ASSERT (sgot != NULL);
f21f3fe0 11505
252b5132 11506 if (sgot == NULL)
99059e56 11507 return bfd_reloc_notsupported;
252b5132 11508
0945cdfd 11509 *unresolved_reloc_p = FALSE;
252b5132 11510 value = sgot->output_section->vma;
f21f3fe0 11511 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11512 contents, rel->r_offset, value,
00a97672 11513 rel->r_addend);
f21f3fe0 11514
252b5132 11515 case R_ARM_GOT32:
eb043451 11516 case R_ARM_GOT_PREL:
252b5132 11517 /* Relocation is to the entry for this symbol in the
99059e56 11518 global offset table. */
252b5132
RH		 11519 if (sgot == NULL)
11520 return bfd_reloc_notsupported;
f21f3fe0 11521
34e77a92
RS		 11522 if (dynreloc_st_type == STT_GNU_IFUNC
11523 && plt_offset != (bfd_vma) -1
11524 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11525 {
11526 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11527 symbol, and the relocation resolves directly to the runtime
11528 target rather than to the .iplt entry. This means that any
11529 .got entry would be the same value as the .igot.plt entry,
11530 so there's no point creating both. */
11531 sgot = globals->root.igotplt;
11532 value = sgot->output_offset + gotplt_offset;
11533 }
11534 else if (h != NULL)
252b5132
RH		 11535 {
11536 bfd_vma off;
f21f3fe0 11537
252b5132
RH		 11538 off = h->got.offset;
11539 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11540 if ((off & 1) != 0)
252b5132 11541 {
b436d854
RS		 11542 /* We have already processsed one GOT relocation against
11543 this symbol. */
11544 off &= ~1;
11545 if (globals->root.dynamic_sections_created
11546 && !SYMBOL_REFERENCES_LOCAL (info, h))
11547 *unresolved_reloc_p = FALSE;
11548 }
11549 else
11550 {
11551 Elf_Internal_Rela outrel;
e8b09b87 11552 int isrofixup = 0;
b436d854 11553
e8b09b87
CL		 11554 if (((h->dynindx != -1) || globals->fdpic_p)
11555 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11556 {
11557 /* If the symbol doesn't resolve locally in a static
11558 object, we have an undefined reference. If the
11559 symbol doesn't resolve locally in a dynamic object,
11560 it should be resolved by the dynamic linker. */
11561 if (globals->root.dynamic_sections_created)
11562 {
11563 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11564 *unresolved_reloc_p = FALSE;
11565 }
11566 else
11567 outrel.r_info = 0;
11568 outrel.r_addend = 0;
11569 }
252b5132
RH		 11570 else
11571 {
34e77a92 11572 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11573 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11574 else if (bfd_link_pic (info)
11575 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11576 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11577 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11578 else
2376f038
EB		 11579 {
11580 outrel.r_info = 0;
11581 if (globals->fdpic_p)
11582 isrofixup = 1;
11583 }
34e77a92 11584 outrel.r_addend = dynreloc_value;
b436d854 11585 }
ee29b9fb 11586
b436d854
RS		 11587 /* The GOT entry is initialized to zero by default.
11588 See if we should install a different value. */
11589 if (outrel.r_addend != 0
2376f038 11590 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11591 {
11592 bfd_put_32 (output_bfd, outrel.r_addend,
11593 sgot->contents + off);
11594 outrel.r_addend = 0;
252b5132 11595 }
f21f3fe0 11596
2376f038
EB		 11597 if (isrofixup)
11598 arm_elf_add_rofixup (output_bfd,
11599 elf32_arm_hash_table(info)->srofixup,
11600 sgot->output_section->vma
11601 + sgot->output_offset + off);
11602
11603 else if (outrel.r_info != 0)
b436d854
RS		 11604 {
11605 outrel.r_offset = (sgot->output_section->vma
11606 + sgot->output_offset
11607 + off);
11608 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11609 }
2376f038 11610
b436d854
RS		 11611 h->got.offset |= 1;
11612 }
252b5132
RH		 11613 value = sgot->output_offset + off;
11614 }
11615 else
11616 {
11617 bfd_vma off;
f21f3fe0 11618
5025eb7c
AO		 11619 BFD_ASSERT (local_got_offsets != NULL
11620 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11621
252b5132 11622 off = local_got_offsets[r_symndx];
f21f3fe0 11623
252b5132
RH		 11624 /* The offset must always be a multiple of 4. We use the
11625 least significant bit to record whether we have already
9b485d32 11626 generated the necessary reloc. */
252b5132
RH		 11627 if ((off & 1) != 0)
11628 off &= ~1;
11629 else
11630 {
2376f038
EB		 11631 Elf_Internal_Rela outrel;
11632 int isrofixup = 0;
f21f3fe0 11633
2376f038
EB		 11634 if (dynreloc_st_type == STT_GNU_IFUNC)
11635 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11636 else if (bfd_link_pic (info))
11637 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11638 else
252b5132 11639 {
2376f038
EB		 11640 outrel.r_info = 0;
11641 if (globals->fdpic_p)
11642 isrofixup = 1;
11643 }
11644
11645 /* The GOT entry is initialized to zero by default.
11646 See if we should install a different value. */
11647 if (globals->use_rel || outrel.r_info == 0)
11648 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11649
11650 if (isrofixup)
11651 arm_elf_add_rofixup (output_bfd,
11652 globals->srofixup,
11653 sgot->output_section->vma
11654 + sgot->output_offset + off);
f21f3fe0 11655
2376f038
EB		 11656 else if (outrel.r_info != 0)
11657 {
34e77a92 11658 outrel.r_addend = addend + dynreloc_value;
252b5132 11659 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11660 + sgot->output_offset
252b5132 11661 + off);
47beaa6a 11662 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11663 }
f21f3fe0 11664
252b5132
RH		 11665 local_got_offsets[r_symndx] |= 1;
11666 }
f21f3fe0 11667
252b5132
RH		 11668 value = sgot->output_offset + off;
11669 }
eb043451
PB		 11670 if (r_type != R_ARM_GOT32)
11671 value += sgot->output_section->vma;
9a5aca8c 11672
f21f3fe0 11673 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11674 contents, rel->r_offset, value,
00a97672 11675 rel->r_addend);
f21f3fe0 11676
ba93b8ac
DJ		 11677 case R_ARM_TLS_LDO32:
11678 value = value - dtpoff_base (info);
11679
11680 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11681 contents, rel->r_offset, value,
11682 rel->r_addend);
ba93b8ac
DJ		 11683
11684 case R_ARM_TLS_LDM32:
5c5a4843 11685 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11686 {
11687 bfd_vma off;
11688
362d30a1 11689 if (sgot == NULL)
ba93b8ac
DJ		 11690 abort ();
11691
11692 off = globals->tls_ldm_got.offset;
11693
11694 if ((off & 1) != 0)
11695 off &= ~1;
11696 else
11697 {
11698 /* If we don't know the module number, create a relocation
11699 for it. */
0e1862bb 11700 if (bfd_link_pic (info))
ba93b8ac
DJ		 11701 {
11702 Elf_Internal_Rela outrel;
ba93b8ac 11703
362d30a1 11704 if (srelgot == NULL)
ba93b8ac
DJ		 11705 abort ();
11706
00a97672 11707 outrel.r_addend = 0;
362d30a1
RS		 11708 outrel.r_offset = (sgot->output_section->vma
11709 + sgot->output_offset + off);
ba93b8ac
DJ		 11710 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11711
00a97672
RS		 11712 if (globals->use_rel)
11713 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11714 sgot->contents + off);
ba93b8ac 11715
47beaa6a 11716 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11717 }
11718 else
362d30a1 11719 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11720
11721 globals->tls_ldm_got.offset |= 1;
11722 }
11723
5c5a4843 11724 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11725 {
11726 bfd_put_32(output_bfd,
11727 globals->root.sgot->output_offset + off,
11728 contents + rel->r_offset);
11729
11730 return bfd_reloc_ok;
11731 }
11732 else
11733 {
11734 value = sgot->output_section->vma + sgot->output_offset + off
11735 - (input_section->output_section->vma
11736 + input_section->output_offset + rel->r_offset);
ba93b8ac 11737
e8b09b87
CL		 11738 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11739 contents, rel->r_offset, value,
11740 rel->r_addend);
11741 }
ba93b8ac
DJ		 11742 }
11743
0855e32b
NS		 11744 case R_ARM_TLS_CALL:
11745 case R_ARM_THM_TLS_CALL:
ba93b8ac 11746 case R_ARM_TLS_GD32:
5c5a4843 11747 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11748 case R_ARM_TLS_IE32:
5c5a4843 11749 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11750 case R_ARM_TLS_GOTDESC:
11751 case R_ARM_TLS_DESCSEQ:
11752 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11753 {
0855e32b
NS		 11754 bfd_vma off, offplt;
11755 int indx = 0;
ba93b8ac
DJ		 11756 char tls_type;
11757
0855e32b 11758 BFD_ASSERT (sgot != NULL);
ba93b8ac 11759
ba93b8ac
DJ		 11760 if (h != NULL)
11761 {
11762 bfd_boolean dyn;
11763 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11764 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11765 bfd_link_pic (info),
11766 h)
11767 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11768 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11769 {
11770 *unresolved_reloc_p = FALSE;
11771 indx = h->dynindx;
11772 }
11773 off = h->got.offset;
0855e32b 11774 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11775 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11776 }
11777 else
11778 {
0855e32b 11779 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11780 off = local_got_offsets[r_symndx];
0855e32b 11781 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11782 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11783 }
11784
0855e32b 11785 /* Linker relaxations happens from one of the
b38cadfb 11786 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11787 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11788 tls_type = GOT_TLS_IE;
0855e32b
NS		 11789
11790 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11791
11792 if ((off & 1) != 0)
11793 off &= ~1;
11794 else
11795 {
11796 bfd_boolean need_relocs = FALSE;
11797 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11798 int cur_off = off;
11799
11800 /* The GOT entries have not been initialized yet. Do it
11801 now, and emit any relocations. If both an IE GOT and a
11802 GD GOT are necessary, we emit the GD first. */
11803
0e1862bb 11804 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11805 && (h == NULL
95b03e4a
L		 11806 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11807 && !resolved_to_zero)
ba93b8ac
DJ		 11808 || h->root.type != bfd_link_hash_undefweak))
11809 {
11810 need_relocs = TRUE;
0855e32b 11811 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11812 }
11813
0855e32b
NS		 11814 if (tls_type & GOT_TLS_GDESC)
11815 {
47beaa6a
RS		 11816 bfd_byte *loc;
11817
0855e32b
NS		 11818 /* We should have relaxed, unless this is an undefined
11819 weak symbol. */
11820 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11821 || bfd_link_pic (info));
0855e32b 11822 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11823 <= globals->root.sgotplt->size);
0855e32b
NS		 11824
11825 outrel.r_addend = 0;
11826 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11827 + globals->root.sgotplt->output_offset
11828 + offplt
11829 + globals->sgotplt_jump_table_size);
b38cadfb 11830
0855e32b
NS		 11831 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11832 sreloc = globals->root.srelplt;
11833 loc = sreloc->contents;
11834 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11835 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11836 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11837
11838 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11839
11840 /* For globals, the first word in the relocation gets
11841 the relocation index and the top bit set, or zero,
11842 if we're binding now. For locals, it gets the
11843 symbol's offset in the tls section. */
99059e56 11844 bfd_put_32 (output_bfd,
0855e32b
NS		 11845 !h ? value - elf_hash_table (info)->tls_sec->vma
11846 : info->flags & DF_BIND_NOW ? 0
11847 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11848 globals->root.sgotplt->contents + offplt
11849 + globals->sgotplt_jump_table_size);
11850
0855e32b 11851 /* Second word in the relocation is always zero. */
99059e56 11852 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11853 globals->root.sgotplt->contents + offplt
11854 + globals->sgotplt_jump_table_size + 4);
0855e32b 11855 }
ba93b8ac
DJ		 11856 if (tls_type & GOT_TLS_GD)
11857 {
11858 if (need_relocs)
11859 {
00a97672 11860 outrel.r_addend = 0;
362d30a1
RS		 11861 outrel.r_offset = (sgot->output_section->vma
11862 + sgot->output_offset
00a97672 11863 + cur_off);
ba93b8ac 11864 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11865
00a97672
RS		 11866 if (globals->use_rel)
11867 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11868 sgot->contents + cur_off);
00a97672 11869
47beaa6a 11870 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11871
11872 if (indx == 0)
11873 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11874 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11875 else
11876 {
00a97672 11877 outrel.r_addend = 0;
ba93b8ac
DJ		 11878 outrel.r_info = ELF32_R_INFO (indx,
11879 R_ARM_TLS_DTPOFF32);
11880 outrel.r_offset += 4;
00a97672
RS		 11881
11882 if (globals->use_rel)
11883 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11884 sgot->contents + cur_off + 4);
00a97672 11885
47beaa6a
RS		 11886 elf32_arm_add_dynreloc (output_bfd, info,
11887 srelgot, &outrel);
ba93b8ac
DJ		 11888 }
11889 }
11890 else
11891 {
11892 /* If we are not emitting relocations for a
11893 general dynamic reference, then we must be in a
11894 static link or an executable link with the
11895 symbol binding locally. Mark it as belonging
11896 to module 1, the executable. */
11897 bfd_put_32 (output_bfd, 1,
362d30a1 11898 sgot->contents + cur_off);
ba93b8ac 11899 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11900 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11901 }
11902
11903 cur_off += 8;
11904 }
11905
11906 if (tls_type & GOT_TLS_IE)
11907 {
11908 if (need_relocs)
11909 {
00a97672
RS		 11910 if (indx == 0)
11911 outrel.r_addend = value - dtpoff_base (info);
11912 else
11913 outrel.r_addend = 0;
362d30a1
RS		 11914 outrel.r_offset = (sgot->output_section->vma
11915 + sgot->output_offset
ba93b8ac
DJ		 11916 + cur_off);
11917 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11918
00a97672
RS		 11919 if (globals->use_rel)
11920 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11921 sgot->contents + cur_off);
ba93b8ac 11922
47beaa6a 11923 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11924 }
11925 else
11926 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11927 sgot->contents + cur_off);
ba93b8ac
DJ		 11928 cur_off += 4;
11929 }
11930
11931 if (h != NULL)
11932 h->got.offset |= 1;
11933 else
11934 local_got_offsets[r_symndx] |= 1;
11935 }
11936
5c5a4843 11937 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11938 off += 8;
0855e32b
NS		 11939 else if (tls_type & GOT_TLS_GDESC)
11940 off = offplt;
11941
11942 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11943 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11944 {
11945 bfd_signed_vma offset;
12352d3f
PB		 11946 /* TLS stubs are arm mode. The original symbol is a
11947 data object, so branch_type is bogus. */
11948 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11949 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11950 = arm_type_of_stub (info, input_section, rel,
11951 st_type, &branch_type,
0855e32b
NS		 11952 (struct elf32_arm_link_hash_entry *)h,
11953 globals->tls_trampoline, globals->root.splt,
11954 input_bfd, sym_name);
11955
11956 if (stub_type != arm_stub_none)
11957 {
11958 struct elf32_arm_stub_hash_entry *stub_entry
11959 = elf32_arm_get_stub_entry
11960 (input_section, globals->root.splt, 0, rel,
11961 globals, stub_type);
11962 offset = (stub_entry->stub_offset
11963 + stub_entry->stub_sec->output_offset
11964 + stub_entry->stub_sec->output_section->vma);
11965 }
11966 else
11967 offset = (globals->root.splt->output_section->vma
11968 + globals->root.splt->output_offset
11969 + globals->tls_trampoline);
11970
11971 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11972 {
11973 unsigned long inst;
b38cadfb
NC		 11974
11975 offset -= (input_section->output_section->vma
11976 + input_section->output_offset
11977 + rel->r_offset + 8);
0855e32b
NS		 11978
11979 inst = offset >> 2;
11980 inst &= 0x00ffffff;
11981 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11982 }
11983 else
11984 {
11985 /* Thumb blx encodes the offset in a complicated
11986 fashion. */
11987 unsigned upper_insn, lower_insn;
11988 unsigned neg;
11989
b38cadfb
NC		 11990 offset -= (input_section->output_section->vma
11991 + input_section->output_offset
0855e32b 11992 + rel->r_offset + 4);
b38cadfb 11993
12352d3f
PB		 11994 if (stub_type != arm_stub_none
11995 && arm_stub_is_thumb (stub_type))
11996 {
11997 lower_insn = 0xd000;
11998 }
11999 else
12000 {
12001 lower_insn = 0xc000;
6a631e86 12002 /* Round up the offset to a word boundary. */
12352d3f
PB		 12003 offset = (offset + 2) & ~2;
12004 }
12005
0855e32b
NS		 12006 neg = offset < 0;
12007 upper_insn = (0xf000
12008 | ((offset >> 12) & 0x3ff)
12009 | (neg << 10));
12352d3f 12010 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 12011 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 12012 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 12013 bfd_put_16 (input_bfd, upper_insn, hit_data);
12014 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12015 return bfd_reloc_ok;
12016 }
12017 }
12018 /* These relocations needs special care, as besides the fact
12019 they point somewhere in .gotplt, the addend must be
12020 adjusted accordingly depending on the type of instruction
6a631e86 12021 we refer to. */
0855e32b
NS		 12022 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
12023 {
12024 unsigned long data, insn;
12025 unsigned thumb;
b38cadfb 12026
0855e32b
NS		 12027 data = bfd_get_32 (input_bfd, hit_data);
12028 thumb = data & 1;
12029 data &= ~1u;
b38cadfb 12030
0855e32b
NS		 12031 if (thumb)
12032 {
12033 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
12034 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
12035 insn = (insn << 16)
12036 | bfd_get_16 (input_bfd,
12037 contents + rel->r_offset - data + 2);
12038 if ((insn & 0xf800c000) == 0xf000c000)
12039 /* bl/blx */
12040 value = -6;
12041 else if ((insn & 0xffffff00) == 0x4400)
12042 /* add */
12043 value = -5;
12044 else
12045 {
4eca0228 12046 _bfd_error_handler
695344c0 12047 /* xgettext:c-format */
2dcf00ce 12048 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12049 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12050 "referenced by TLS_GOTDESC"),
12051 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12052 "Thumb", insn);
0855e32b
NS		 12053 return bfd_reloc_notsupported;
12054 }
12055 }
12056 else
12057 {
12058 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12059
12060 switch (insn >> 24)
12061 {
12062 case 0xeb: /* bl */
12063 case 0xfa: /* blx */
12064 value = -4;
12065 break;
12066
12067 case 0xe0: /* add */
12068 value = -8;
12069 break;
b38cadfb 12070
0855e32b 12071 default:
4eca0228 12072 _bfd_error_handler
695344c0 12073 /* xgettext:c-format */
2dcf00ce 12074 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12075 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12076 "referenced by TLS_GOTDESC"),
12077 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12078 "ARM", insn);
0855e32b
NS		 12079 return bfd_reloc_notsupported;
12080 }
12081 }
b38cadfb 12082
0855e32b
NS		 12083 value += ((globals->root.sgotplt->output_section->vma
12084 + globals->root.sgotplt->output_offset + off)
12085 - (input_section->output_section->vma
12086 + input_section->output_offset
12087 + rel->r_offset)
12088 + globals->sgotplt_jump_table_size);
12089 }
12090 else
12091 value = ((globals->root.sgot->output_section->vma
12092 + globals->root.sgot->output_offset + off)
12093 - (input_section->output_section->vma
12094 + input_section->output_offset + rel->r_offset));
ba93b8ac 12095
5c5a4843
CL		 12096 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12097 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12098 {
12099 /* For FDPIC relocations, resolve to the offset of the GOT
12100 entry from the start of GOT. */
12101 bfd_put_32(output_bfd,
12102 globals->root.sgot->output_offset + off,
12103 contents + rel->r_offset);
12104
12105 return bfd_reloc_ok;
12106 }
12107 else
12108 {
12109 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12110 contents, rel->r_offset, value,
12111 rel->r_addend);
12112 }
ba93b8ac
DJ		 12113 }
12114
12115 case R_ARM_TLS_LE32:
3cbc1e5e 12116 if (bfd_link_dll (info))
ba93b8ac 12117 {
4eca0228 12118 _bfd_error_handler
695344c0 12119 /* xgettext:c-format */
2dcf00ce
AM		 12120 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12121 "in shared object"),
12122 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12123 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12124 }
12125 else
12126 value = tpoff (info, value);
906e58ca 12127
ba93b8ac 12128 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12129 contents, rel->r_offset, value,
12130 rel->r_addend);
ba93b8ac 12131
319850b4
JB		 12132 case R_ARM_V4BX:
12133 if (globals->fix_v4bx)
845b51d6
PB		 12134 {
12135 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12136
845b51d6
PB		 12137 /* Ensure that we have a BX instruction. */
12138 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12139
845b51d6
PB		 12140 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12141 {
12142 /* Branch to veneer. */
12143 bfd_vma glue_addr;
12144 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12145 glue_addr -= input_section->output_section->vma
12146 + input_section->output_offset
12147 + rel->r_offset + 8;
12148 insn = (insn & 0xf0000000) | 0x0a000000
12149 | ((glue_addr >> 2) & 0x00ffffff);
12150 }
12151 else
12152 {
12153 /* Preserve Rm (lowest four bits) and the condition code
12154 (highest four bits). Other bits encode MOV PC,Rm. */
12155 insn = (insn & 0xf000000f) | 0x01a0f000;
12156 }
319850b4 12157
845b51d6
PB		 12158 bfd_put_32 (input_bfd, insn, hit_data);
12159 }
319850b4
JB		 12160 return bfd_reloc_ok;
12161
b6895b4f
PB		 12162 case R_ARM_MOVW_ABS_NC:
12163 case R_ARM_MOVT_ABS:
12164 case R_ARM_MOVW_PREL_NC:
12165 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12166 /* Until we properly support segment-base-relative addressing then
12167 we assume the segment base to be zero, as for the group relocations.
12168 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12169 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12170 case R_ARM_MOVW_BREL_NC:
12171 case R_ARM_MOVW_BREL:
12172 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12173 {
12174 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12175
12176 if (globals->use_rel)
12177 {
12178 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12179 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12180 }
92f5d02b 12181
b6895b4f 12182 value += signed_addend;
b6895b4f
PB		 12183
12184 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12185 value -= (input_section->output_section->vma
12186 + input_section->output_offset + rel->r_offset);
12187
92f5d02b 12188 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12189 return bfd_reloc_overflow;
92f5d02b 12190
35fc36a8 12191 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12192 value |= 1;
12193
12194 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12195 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12196 value >>= 16;
12197
12198 insn &= 0xfff0f000;
12199 insn |= value & 0xfff;
12200 insn |= (value & 0xf000) << 4;
12201 bfd_put_32 (input_bfd, insn, hit_data);
12202 }
12203 return bfd_reloc_ok;
12204
12205 case R_ARM_THM_MOVW_ABS_NC:
12206 case R_ARM_THM_MOVT_ABS:
12207 case R_ARM_THM_MOVW_PREL_NC:
12208 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12209 /* Until we properly support segment-base-relative addressing then
12210 we assume the segment base to be zero, as for the above relocations.
12211 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12212 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12213 as R_ARM_THM_MOVT_ABS. */
12214 case R_ARM_THM_MOVW_BREL_NC:
12215 case R_ARM_THM_MOVW_BREL:
12216 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12217 {
12218 bfd_vma insn;
906e58ca 12219
b6895b4f
PB		 12220 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12221 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12222
12223 if (globals->use_rel)
12224 {
12225 addend = ((insn >> 4) & 0xf000)
12226 | ((insn >> 15) & 0x0800)
12227 | ((insn >> 4) & 0x0700)
07d6d2b8 12228 | (insn & 0x00ff);
39623e12 12229 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12230 }
92f5d02b 12231
b6895b4f 12232 value += signed_addend;
b6895b4f
PB		 12233
12234 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12235 value -= (input_section->output_section->vma
12236 + input_section->output_offset + rel->r_offset);
12237
92f5d02b 12238 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12239 return bfd_reloc_overflow;
92f5d02b 12240
35fc36a8 12241 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12242 value |= 1;
12243
12244 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12245 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12246 value >>= 16;
12247
12248 insn &= 0xfbf08f00;
12249 insn |= (value & 0xf000) << 4;
12250 insn |= (value & 0x0800) << 15;
12251 insn |= (value & 0x0700) << 4;
12252 insn |= (value & 0x00ff);
12253
12254 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12255 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12256 }
12257 return bfd_reloc_ok;
12258
4962c51a
MS		 12259 case R_ARM_ALU_PC_G0_NC:
12260 case R_ARM_ALU_PC_G1_NC:
12261 case R_ARM_ALU_PC_G0:
12262 case R_ARM_ALU_PC_G1:
12263 case R_ARM_ALU_PC_G2:
12264 case R_ARM_ALU_SB_G0_NC:
12265 case R_ARM_ALU_SB_G1_NC:
12266 case R_ARM_ALU_SB_G0:
12267 case R_ARM_ALU_SB_G1:
12268 case R_ARM_ALU_SB_G2:
12269 {
12270 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12271 bfd_vma pc = input_section->output_section->vma
4962c51a 12272 + input_section->output_offset + rel->r_offset;
31a91d61 12273 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12274 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12275 bfd_vma residual;
12276 bfd_vma g_n;
4962c51a 12277 bfd_signed_vma signed_value;
99059e56
RM		 12278 int group = 0;
12279
12280 /* Determine which group of bits to select. */
12281 switch (r_type)
12282 {
12283 case R_ARM_ALU_PC_G0_NC:
12284 case R_ARM_ALU_PC_G0:
12285 case R_ARM_ALU_SB_G0_NC:
12286 case R_ARM_ALU_SB_G0:
12287 group = 0;
12288 break;
12289
12290 case R_ARM_ALU_PC_G1_NC:
12291 case R_ARM_ALU_PC_G1:
12292 case R_ARM_ALU_SB_G1_NC:
12293 case R_ARM_ALU_SB_G1:
12294 group = 1;
12295 break;
12296
12297 case R_ARM_ALU_PC_G2:
12298 case R_ARM_ALU_SB_G2:
12299 group = 2;
12300 break;
12301
12302 default:
12303 abort ();
12304 }
12305
12306 /* If REL, extract the addend from the insn. If RELA, it will
12307 have already been fetched for us. */
4962c51a 12308 if (globals->use_rel)
99059e56
RM		 12309 {
12310 int negative;
12311 bfd_vma constant = insn & 0xff;
12312 bfd_vma rotation = (insn & 0xf00) >> 8;
12313
12314 if (rotation == 0)
12315 signed_addend = constant;
12316 else
12317 {
12318 /* Compensate for the fact that in the instruction, the
12319 rotation is stored in multiples of 2 bits. */
12320 rotation *= 2;
12321
12322 /* Rotate "constant" right by "rotation" bits. */
12323 signed_addend = (constant >> rotation) |
12324 (constant << (8 * sizeof (bfd_vma) - rotation));
12325 }
12326
12327 /* Determine if the instruction is an ADD or a SUB.
12328 (For REL, this determines the sign of the addend.) */
12329 negative = identify_add_or_sub (insn);
12330 if (negative == 0)
12331 {
4eca0228 12332 _bfd_error_handler
695344c0 12333 /* xgettext:c-format */
90b6238f 12334 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12335 "are allowed for ALU group relocations"),
12336 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12337 return bfd_reloc_overflow;
12338 }
12339
12340 signed_addend *= negative;
12341 }
4962c51a
MS		 12342
12343 /* Compute the value (X) to go in the place. */
99059e56
RM		 12344 if (r_type == R_ARM_ALU_PC_G0_NC
12345 || r_type == R_ARM_ALU_PC_G1_NC
12346 || r_type == R_ARM_ALU_PC_G0
12347 || r_type == R_ARM_ALU_PC_G1
12348 || r_type == R_ARM_ALU_PC_G2)
12349 /* PC relative. */
12350 signed_value = value - pc + signed_addend;
12351 else
12352 /* Section base relative. */
12353 signed_value = value - sb + signed_addend;
12354
12355 /* If the target symbol is a Thumb function, then set the
12356 Thumb bit in the address. */
35fc36a8 12357 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12358 signed_value |= 1;
12359
99059e56
RM		 12360 /* Calculate the value of the relevant G_n, in encoded
12361 constant-with-rotation format. */
b6518b38
NC		 12362 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12363 group, &residual);
99059e56
RM		 12364
12365 /* Check for overflow if required. */
12366 if ((r_type == R_ARM_ALU_PC_G0
12367 || r_type == R_ARM_ALU_PC_G1
12368 || r_type == R_ARM_ALU_PC_G2
12369 || r_type == R_ARM_ALU_SB_G0
12370 || r_type == R_ARM_ALU_SB_G1
12371 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12372 {
4eca0228 12373 _bfd_error_handler
695344c0 12374 /* xgettext:c-format */
90b6238f 12375 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12376 "splitting %#" PRIx64 " for group relocation %s"),
12377 input_bfd, input_section, (uint64_t) rel->r_offset,
12378 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12379 howto->name);
99059e56
RM		 12380 return bfd_reloc_overflow;
12381 }
12382
12383 /* Mask out the value and the ADD/SUB part of the opcode; take care
12384 not to destroy the S bit. */
12385 insn &= 0xff1ff000;
12386
12387 /* Set the opcode according to whether the value to go in the
12388 place is negative. */
12389 if (signed_value < 0)
12390 insn |= 1 << 22;
12391 else
12392 insn |= 1 << 23;
12393
12394 /* Encode the offset. */
12395 insn |= g_n;
4962c51a
MS		 12396
12397 bfd_put_32 (input_bfd, insn, hit_data);
12398 }
12399 return bfd_reloc_ok;
12400
12401 case R_ARM_LDR_PC_G0:
12402 case R_ARM_LDR_PC_G1:
12403 case R_ARM_LDR_PC_G2:
12404 case R_ARM_LDR_SB_G0:
12405 case R_ARM_LDR_SB_G1:
12406 case R_ARM_LDR_SB_G2:
12407 {
12408 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12409 bfd_vma pc = input_section->output_section->vma
4962c51a 12410 + input_section->output_offset + rel->r_offset;
31a91d61 12411 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12412 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12413 bfd_vma residual;
4962c51a 12414 bfd_signed_vma signed_value;
99059e56
RM		 12415 int group = 0;
12416
12417 /* Determine which groups of bits to calculate. */
12418 switch (r_type)
12419 {
12420 case R_ARM_LDR_PC_G0:
12421 case R_ARM_LDR_SB_G0:
12422 group = 0;
12423 break;
12424
12425 case R_ARM_LDR_PC_G1:
12426 case R_ARM_LDR_SB_G1:
12427 group = 1;
12428 break;
12429
12430 case R_ARM_LDR_PC_G2:
12431 case R_ARM_LDR_SB_G2:
12432 group = 2;
12433 break;
12434
12435 default:
12436 abort ();
12437 }
12438
12439 /* If REL, extract the addend from the insn. If RELA, it will
12440 have already been fetched for us. */
4962c51a 12441 if (globals->use_rel)
99059e56
RM		 12442 {
12443 int negative = (insn & (1 << 23)) ? 1 : -1;
12444 signed_addend = negative * (insn & 0xfff);
12445 }
4962c51a
MS		 12446
12447 /* Compute the value (X) to go in the place. */
99059e56
RM		 12448 if (r_type == R_ARM_LDR_PC_G0
12449 || r_type == R_ARM_LDR_PC_G1
12450 || r_type == R_ARM_LDR_PC_G2)
12451 /* PC relative. */
12452 signed_value = value - pc + signed_addend;
12453 else
12454 /* Section base relative. */
12455 signed_value = value - sb + signed_addend;
12456
12457 /* Calculate the value of the relevant G_{n-1} to obtain
12458 the residual at that stage. */
b6518b38
NC		 12459 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12460 group - 1, &residual);
99059e56
RM		 12461
12462 /* Check for overflow. */
12463 if (residual >= 0x1000)
12464 {
4eca0228 12465 _bfd_error_handler
695344c0 12466 /* xgettext:c-format */
90b6238f 12467 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12468 "splitting %#" PRIx64 " for group relocation %s"),
12469 input_bfd, input_section, (uint64_t) rel->r_offset,
12470 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12471 howto->name);
99059e56
RM		 12472 return bfd_reloc_overflow;
12473 }
12474
12475 /* Mask out the value and U bit. */
12476 insn &= 0xff7ff000;
12477
12478 /* Set the U bit if the value to go in the place is non-negative. */
12479 if (signed_value >= 0)
12480 insn |= 1 << 23;
12481
12482 /* Encode the offset. */
12483 insn |= residual;
4962c51a
MS		 12484
12485 bfd_put_32 (input_bfd, insn, hit_data);
12486 }
12487 return bfd_reloc_ok;
12488
12489 case R_ARM_LDRS_PC_G0:
12490 case R_ARM_LDRS_PC_G1:
12491 case R_ARM_LDRS_PC_G2:
12492 case R_ARM_LDRS_SB_G0:
12493 case R_ARM_LDRS_SB_G1:
12494 case R_ARM_LDRS_SB_G2:
12495 {
12496 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12497 bfd_vma pc = input_section->output_section->vma
4962c51a 12498 + input_section->output_offset + rel->r_offset;
31a91d61 12499 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12500 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12501 bfd_vma residual;
4962c51a 12502 bfd_signed_vma signed_value;
99059e56
RM		 12503 int group = 0;
12504
12505 /* Determine which groups of bits to calculate. */
12506 switch (r_type)
12507 {
12508 case R_ARM_LDRS_PC_G0:
12509 case R_ARM_LDRS_SB_G0:
12510 group = 0;
12511 break;
12512
12513 case R_ARM_LDRS_PC_G1:
12514 case R_ARM_LDRS_SB_G1:
12515 group = 1;
12516 break;
12517
12518 case R_ARM_LDRS_PC_G2:
12519 case R_ARM_LDRS_SB_G2:
12520 group = 2;
12521 break;
12522
12523 default:
12524 abort ();
12525 }
12526
12527 /* If REL, extract the addend from the insn. If RELA, it will
12528 have already been fetched for us. */
4962c51a 12529 if (globals->use_rel)
99059e56
RM		 12530 {
12531 int negative = (insn & (1 << 23)) ? 1 : -1;
12532 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12533 }
4962c51a
MS		 12534
12535 /* Compute the value (X) to go in the place. */
99059e56
RM		 12536 if (r_type == R_ARM_LDRS_PC_G0
12537 || r_type == R_ARM_LDRS_PC_G1
12538 || r_type == R_ARM_LDRS_PC_G2)
12539 /* PC relative. */
12540 signed_value = value - pc + signed_addend;
12541 else
12542 /* Section base relative. */
12543 signed_value = value - sb + signed_addend;
12544
12545 /* Calculate the value of the relevant G_{n-1} to obtain
12546 the residual at that stage. */
b6518b38
NC		 12547 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12548 group - 1, &residual);
99059e56
RM		 12549
12550 /* Check for overflow. */
12551 if (residual >= 0x100)
12552 {
4eca0228 12553 _bfd_error_handler
695344c0 12554 /* xgettext:c-format */
90b6238f 12555 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12556 "splitting %#" PRIx64 " for group relocation %s"),
12557 input_bfd, input_section, (uint64_t) rel->r_offset,
12558 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12559 howto->name);
99059e56
RM		 12560 return bfd_reloc_overflow;
12561 }
12562
12563 /* Mask out the value and U bit. */
12564 insn &= 0xff7ff0f0;
12565
12566 /* Set the U bit if the value to go in the place is non-negative. */
12567 if (signed_value >= 0)
12568 insn |= 1 << 23;
12569
12570 /* Encode the offset. */
12571 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12572
12573 bfd_put_32 (input_bfd, insn, hit_data);
12574 }
12575 return bfd_reloc_ok;
12576
12577 case R_ARM_LDC_PC_G0:
12578 case R_ARM_LDC_PC_G1:
12579 case R_ARM_LDC_PC_G2:
12580 case R_ARM_LDC_SB_G0:
12581 case R_ARM_LDC_SB_G1:
12582 case R_ARM_LDC_SB_G2:
12583 {
12584 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12585 bfd_vma pc = input_section->output_section->vma
4962c51a 12586 + input_section->output_offset + rel->r_offset;
31a91d61 12587 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12588 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12589 bfd_vma residual;
4962c51a 12590 bfd_signed_vma signed_value;
99059e56
RM		 12591 int group = 0;
12592
12593 /* Determine which groups of bits to calculate. */
12594 switch (r_type)
12595 {
12596 case R_ARM_LDC_PC_G0:
12597 case R_ARM_LDC_SB_G0:
12598 group = 0;
12599 break;
12600
12601 case R_ARM_LDC_PC_G1:
12602 case R_ARM_LDC_SB_G1:
12603 group = 1;
12604 break;
12605
12606 case R_ARM_LDC_PC_G2:
12607 case R_ARM_LDC_SB_G2:
12608 group = 2;
12609 break;
12610
12611 default:
12612 abort ();
12613 }
12614
12615 /* If REL, extract the addend from the insn. If RELA, it will
12616 have already been fetched for us. */
4962c51a 12617 if (globals->use_rel)
99059e56
RM		 12618 {
12619 int negative = (insn & (1 << 23)) ? 1 : -1;
12620 signed_addend = negative * ((insn & 0xff) << 2);
12621 }
4962c51a
MS		 12622
12623 /* Compute the value (X) to go in the place. */
99059e56
RM		 12624 if (r_type == R_ARM_LDC_PC_G0
12625 || r_type == R_ARM_LDC_PC_G1
12626 || r_type == R_ARM_LDC_PC_G2)
12627 /* PC relative. */
12628 signed_value = value - pc + signed_addend;
12629 else
12630 /* Section base relative. */
12631 signed_value = value - sb + signed_addend;
12632
12633 /* Calculate the value of the relevant G_{n-1} to obtain
12634 the residual at that stage. */
b6518b38
NC		 12635 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12636 group - 1, &residual);
99059e56
RM		 12637
12638 /* Check for overflow. (The absolute value to go in the place must be
12639 divisible by four and, after having been divided by four, must
12640 fit in eight bits.) */
12641 if ((residual & 0x3) != 0 || residual >= 0x400)
12642 {
4eca0228 12643 _bfd_error_handler
695344c0 12644 /* xgettext:c-format */
90b6238f 12645 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12646 "splitting %#" PRIx64 " for group relocation %s"),
12647 input_bfd, input_section, (uint64_t) rel->r_offset,
12648 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12649 howto->name);
99059e56
RM		 12650 return bfd_reloc_overflow;
12651 }
12652
12653 /* Mask out the value and U bit. */
12654 insn &= 0xff7fff00;
12655
12656 /* Set the U bit if the value to go in the place is non-negative. */
12657 if (signed_value >= 0)
12658 insn |= 1 << 23;
12659
12660 /* Encode the offset. */
12661 insn |= residual >> 2;
4962c51a
MS		 12662
12663 bfd_put_32 (input_bfd, insn, hit_data);
12664 }
12665 return bfd_reloc_ok;
12666
72d98d16
MG		 12667 case R_ARM_THM_ALU_ABS_G0_NC:
12668 case R_ARM_THM_ALU_ABS_G1_NC:
12669 case R_ARM_THM_ALU_ABS_G2_NC:
12670 case R_ARM_THM_ALU_ABS_G3_NC:
12671 {
12672 const int shift_array[4] = {0, 8, 16, 24};
12673 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12674 bfd_vma addr = value;
12675 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12676
12677 /* Compute address. */
12678 if (globals->use_rel)
12679 signed_addend = insn & 0xff;
12680 addr += signed_addend;
12681 if (branch_type == ST_BRANCH_TO_THUMB)
12682 addr |= 1;
12683 /* Clean imm8 insn. */
12684 insn &= 0xff00;
12685 /* And update with correct part of address. */
12686 insn |= (addr >> shift) & 0xff;
12687 /* Update insn. */
12688 bfd_put_16 (input_bfd, insn, hit_data);
12689 }
12690
12691 *unresolved_reloc_p = FALSE;
12692 return bfd_reloc_ok;
12693
e8b09b87
CL		 12694 case R_ARM_GOTOFFFUNCDESC:
12695 {
4b24dd1a 12696 if (h == NULL)
e8b09b87
CL		 12697 {
12698 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12699 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12700 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12701 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12702 bfd_vma seg = -1;
12703
12704 if (bfd_link_pic(info) && dynindx == 0)
12705 abort();
12706
12707 /* Resolve relocation. */
12708 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12709 , contents + rel->r_offset);
12710 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12711 not done yet. */
12712 arm_elf_fill_funcdesc(output_bfd, info,
12713 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12714 dynindx, offset, addr, dynreloc_value, seg);
12715 }
12716 else
12717 {
12718 int dynindx;
12719 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12720 bfd_vma addr;
12721 bfd_vma seg = -1;
12722
12723 /* For static binaries, sym_sec can be null. */
12724 if (sym_sec)
12725 {
12726 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12727 addr = dynreloc_value - sym_sec->output_section->vma;
12728 }
12729 else
12730 {
12731 dynindx = 0;
12732 addr = 0;
12733 }
12734
12735 if (bfd_link_pic(info) && dynindx == 0)
12736 abort();
12737
12738 /* This case cannot occur since funcdesc is allocated by
12739 the dynamic loader so we cannot resolve the relocation. */
12740 if (h->dynindx != -1)
12741 abort();
12742
12743 /* Resolve relocation. */
12744 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12745 contents + rel->r_offset);
12746 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12747 arm_elf_fill_funcdesc(output_bfd, info,
12748 &eh->fdpic_cnts.funcdesc_offset,
12749 dynindx, offset, addr, dynreloc_value, seg);
12750 }
12751 }
12752 *unresolved_reloc_p = FALSE;
12753 return bfd_reloc_ok;
12754
12755 case R_ARM_GOTFUNCDESC:
12756 {
4b24dd1a 12757 if (h != NULL)
e8b09b87
CL		 12758 {
12759 Elf_Internal_Rela outrel;
12760
12761 /* Resolve relocation. */
12762 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12763 + sgot->output_offset),
12764 contents + rel->r_offset);
12765 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12766 if(h->dynindx == -1)
12767 {
12768 int dynindx;
12769 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12770 bfd_vma addr;
12771 bfd_vma seg = -1;
12772
12773 /* For static binaries sym_sec can be null. */
12774 if (sym_sec)
12775 {
12776 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12777 addr = dynreloc_value - sym_sec->output_section->vma;
12778 }
12779 else
12780 {
12781 dynindx = 0;
12782 addr = 0;
12783 }
12784
12785 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12786 arm_elf_fill_funcdesc(output_bfd, info,
12787 &eh->fdpic_cnts.funcdesc_offset,
12788 dynindx, offset, addr, dynreloc_value, seg);
12789 }
12790
12791 /* Add a dynamic relocation on GOT entry if not already done. */
12792 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12793 {
12794 if (h->dynindx == -1)
12795 {
12796 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12797 if (h->root.type == bfd_link_hash_undefweak)
12798 bfd_put_32(output_bfd, 0, sgot->contents
12799 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12800 else
12801 bfd_put_32(output_bfd, sgot->output_section->vma
12802 + sgot->output_offset
12803 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12804 sgot->contents
12805 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12806 }
12807 else
12808 {
12809 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12810 }
12811 outrel.r_offset = sgot->output_section->vma
12812 + sgot->output_offset
12813 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12814 outrel.r_addend = 0;
12815 if (h->dynindx == -1 && !bfd_link_pic(info))
12816 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12817 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12818 else
4b24dd1a
AM		 12819 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12820 outrel.r_offset);
e8b09b87
CL		 12821 else
12822 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12823 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12824 }
12825 }
12826 else
12827 {
12828 /* Such relocation on static function should not have been
12829 emitted by the compiler. */
12830 abort();
12831 }
12832 }
12833 *unresolved_reloc_p = FALSE;
12834 return bfd_reloc_ok;
12835
12836 case R_ARM_FUNCDESC:
12837 {
4b24dd1a 12838 if (h == NULL)
e8b09b87
CL		 12839 {
12840 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12841 Elf_Internal_Rela outrel;
12842 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12843 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12844 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12845 bfd_vma seg = -1;
12846
12847 if (bfd_link_pic(info) && dynindx == 0)
12848 abort();
12849
12850 /* Replace static FUNCDESC relocation with a
12851 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12852 executable. */
12853 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12854 outrel.r_offset = input_section->output_section->vma
12855 + input_section->output_offset + rel->r_offset;
12856 outrel.r_addend = 0;
12857 if (bfd_link_pic(info))
12858 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12859 else
12860 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12861
12862 bfd_put_32 (input_bfd, sgot->output_section->vma
12863 + sgot->output_offset + offset, hit_data);
12864
12865 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12866 arm_elf_fill_funcdesc(output_bfd, info,
12867 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12868 dynindx, offset, addr, dynreloc_value, seg);
12869 }
12870 else
12871 {
12872 if (h->dynindx == -1)
12873 {
12874 int dynindx;
12875 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12876 bfd_vma addr;
12877 bfd_vma seg = -1;
12878 Elf_Internal_Rela outrel;
12879
12880 /* For static binaries sym_sec can be null. */
12881 if (sym_sec)
12882 {
12883 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12884 addr = dynreloc_value - sym_sec->output_section->vma;
12885 }
12886 else
12887 {
12888 dynindx = 0;
12889 addr = 0;
12890 }
12891
12892 if (bfd_link_pic(info) && dynindx == 0)
12893 abort();
12894
12895 /* Replace static FUNCDESC relocation with a
12896 R_ARM_RELATIVE dynamic relocation. */
12897 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12898 outrel.r_offset = input_section->output_section->vma
12899 + input_section->output_offset + rel->r_offset;
12900 outrel.r_addend = 0;
12901 if (bfd_link_pic(info))
12902 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12903 else
12904 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12905
12906 bfd_put_32 (input_bfd, sgot->output_section->vma
12907 + sgot->output_offset + offset, hit_data);
12908
12909 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12910 arm_elf_fill_funcdesc(output_bfd, info,
12911 &eh->fdpic_cnts.funcdesc_offset,
12912 dynindx, offset, addr, dynreloc_value, seg);
12913 }
12914 else
12915 {
12916 Elf_Internal_Rela outrel;
12917
12918 /* Add a dynamic relocation. */
12919 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12920 outrel.r_offset = input_section->output_section->vma
12921 + input_section->output_offset + rel->r_offset;
12922 outrel.r_addend = 0;
12923 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12924 }
12925 }
12926 }
12927 *unresolved_reloc_p = FALSE;
12928 return bfd_reloc_ok;
12929
e5d6e09e
AV		 12930 case R_ARM_THM_BF16:
12931 {
12932 bfd_vma relocation;
12933 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12934 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12935
12936 if (globals->use_rel)
12937 {
12938 bfd_vma immA = (upper_insn & 0x001f);
12939 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12940 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12941 addend = (immA << 12);
12942 addend |= (immB << 2);
12943 addend |= (immC << 1);
12944 addend |= 1;
12945 /* Sign extend. */
e6f65e75 12946 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12947 }
12948
e6f65e75 12949 relocation = value + signed_addend;
e5d6e09e
AV		 12950 relocation -= (input_section->output_section->vma
12951 + input_section->output_offset
12952 + rel->r_offset);
12953
12954 /* Put RELOCATION back into the insn. */
12955 {
12956 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12957 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12958 bfd_vma immC = (relocation & 0x00000002) >> 1;
12959
12960 upper_insn = (upper_insn & 0xffe0) | immA;
12961 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12962 }
12963
12964 /* Put the relocated value back in the object file: */
12965 bfd_put_16 (input_bfd, upper_insn, hit_data);
12966 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12967
12968 return bfd_reloc_ok;
12969 }
12970
1889da70
AV		 12971 case R_ARM_THM_BF12:
12972 {
12973 bfd_vma relocation;
12974 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12975 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12976
12977 if (globals->use_rel)
12978 {
12979 bfd_vma immA = (upper_insn & 0x0001);
12980 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12981 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12982 addend = (immA << 12);
12983 addend |= (immB << 2);
12984 addend |= (immC << 1);
12985 addend |= 1;
12986 /* Sign extend. */
12987 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 12988 signed_addend = addend;
1889da70
AV		 12989 }
12990
e6f65e75 12991 relocation = value + signed_addend;
1889da70
AV		 12992 relocation -= (input_section->output_section->vma
12993 + input_section->output_offset
12994 + rel->r_offset);
12995
12996 /* Put RELOCATION back into the insn. */
12997 {
12998 bfd_vma immA = (relocation & 0x00001000) >> 12;
12999 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13000 bfd_vma immC = (relocation & 0x00000002) >> 1;
13001
13002 upper_insn = (upper_insn & 0xfffe) | immA;
13003 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13004 }
13005
13006 /* Put the relocated value back in the object file: */
13007 bfd_put_16 (input_bfd, upper_insn, hit_data);
13008 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13009
13010 return bfd_reloc_ok;
13011 }
13012
1caf72a5
AV		 13013 case R_ARM_THM_BF18:
13014 {
13015 bfd_vma relocation;
13016 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
13017 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
13018
13019 if (globals->use_rel)
13020 {
13021 bfd_vma immA = (upper_insn & 0x007f);
13022 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
13023 bfd_vma immC = (lower_insn & 0x0800) >> 11;
13024 addend = (immA << 12);
13025 addend |= (immB << 2);
13026 addend |= (immC << 1);
13027 addend |= 1;
13028 /* Sign extend. */
13029 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 13030 signed_addend = addend;
1caf72a5
AV		 13031 }
13032
e6f65e75 13033 relocation = value + signed_addend;
1caf72a5
AV		 13034 relocation -= (input_section->output_section->vma
13035 + input_section->output_offset
13036 + rel->r_offset);
13037
13038 /* Put RELOCATION back into the insn. */
13039 {
13040 bfd_vma immA = (relocation & 0x0007f000) >> 12;
13041 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13042 bfd_vma immC = (relocation & 0x00000002) >> 1;
13043
13044 upper_insn = (upper_insn & 0xff80) | immA;
13045 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13046 }
13047
13048 /* Put the relocated value back in the object file: */
13049 bfd_put_16 (input_bfd, upper_insn, hit_data);
13050 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13051
13052 return bfd_reloc_ok;
13053 }
13054
252b5132
RH		 13055 default:
13056 return bfd_reloc_notsupported;
13057 }
13058}
13059
98c1d4aa
NC		 13060/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13061static void
07d6d2b8
AM		 13062arm_add_to_rel (bfd * abfd,
13063 bfd_byte * address,
57e8b36a 13064 reloc_howto_type * howto,
07d6d2b8 13065 bfd_signed_vma increment)
98c1d4aa 13066{
98c1d4aa
NC		 13067 bfd_signed_vma addend;
13068
bd97cb95
DJ		 13069 if (howto->type == R_ARM_THM_CALL
13070 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13071 {
9a5aca8c
AM		 13072 int upper_insn, lower_insn;
13073 int upper, lower;
98c1d4aa 13074
9a5aca8c
AM		 13075 upper_insn = bfd_get_16 (abfd, address);
13076 lower_insn = bfd_get_16 (abfd, address + 2);
13077 upper = upper_insn & 0x7ff;
13078 lower = lower_insn & 0x7ff;
13079
13080 addend = (upper << 12) | (lower << 1);
ddda4409 13081 addend += increment;
9a5aca8c 13082 addend >>= 1;
98c1d4aa 13083
9a5aca8c
AM		 13084 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13085 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13086
dc810e39
AM		 13087 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13088 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13089 }
13090 else
13091 {
07d6d2b8 13092 bfd_vma contents;
9a5aca8c
AM		 13093
13094 contents = bfd_get_32 (abfd, address);
13095
13096 /* Get the (signed) value from the instruction. */
13097 addend = contents & howto->src_mask;
13098 if (addend & ((howto->src_mask + 1) >> 1))
13099 {
13100 bfd_signed_vma mask;
13101
13102 mask = -1;
13103 mask &= ~ howto->src_mask;
13104 addend |= mask;
13105 }
13106
13107 /* Add in the increment, (which is a byte value). */
13108 switch (howto->type)
13109 {
13110 default:
13111 addend += increment;
13112 break;
13113
13114 case R_ARM_PC24:
c6596c5e 13115 case R_ARM_PLT32:
5b5bb741
PB		 13116 case R_ARM_CALL:
13117 case R_ARM_JUMP24:
9a5aca8c 13118 addend <<= howto->size;
dc810e39 13119 addend += increment;
9a5aca8c
AM		 13120
13121 /* Should we check for overflow here ? */
13122
13123 /* Drop any undesired bits. */
13124 addend >>= howto->rightshift;
13125 break;
13126 }
13127
13128 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13129
13130 bfd_put_32 (abfd, contents, address);
ddda4409 13131 }
98c1d4aa 13132}
252b5132 13133
ba93b8ac
DJ		 13134#define IS_ARM_TLS_RELOC(R_TYPE) \
13135 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13136 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13137 || (R_TYPE) == R_ARM_TLS_LDO32 \
13138 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13139 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13140 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13141 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13142 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13143 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13144 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13145 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13146 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13147
13148/* Specific set of relocations for the gnu tls dialect. */
13149#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13150 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13151 || (R_TYPE) == R_ARM_TLS_CALL \
13152 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13153 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13154 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13155
252b5132 13156/* Relocate an ARM ELF section. */
906e58ca 13157
b34976b6 13158static bfd_boolean
07d6d2b8 13159elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13160 struct bfd_link_info * info,
07d6d2b8
AM		 13161 bfd * input_bfd,
13162 asection * input_section,
13163 bfd_byte * contents,
13164 Elf_Internal_Rela * relocs,
13165 Elf_Internal_Sym * local_syms,
13166 asection ** local_sections)
252b5132 13167{
b34976b6
AM		 13168 Elf_Internal_Shdr *symtab_hdr;
13169 struct elf_link_hash_entry **sym_hashes;
13170 Elf_Internal_Rela *rel;
13171 Elf_Internal_Rela *relend;
13172 const char *name;
b32d3aa2 13173 struct elf32_arm_link_hash_table * globals;
252b5132 13174
4e7fd91e 13175 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13176 if (globals == NULL)
13177 return FALSE;
b491616a 13178
0ffa91dd 13179 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13180 sym_hashes = elf_sym_hashes (input_bfd);
13181
13182 rel = relocs;
13183 relend = relocs + input_section->reloc_count;
13184 for (; rel < relend; rel++)
13185 {
07d6d2b8
AM		 13186 int r_type;
13187 reloc_howto_type * howto;
13188 unsigned long r_symndx;
13189 Elf_Internal_Sym * sym;
13190 asection * sec;
252b5132 13191 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13192 bfd_vma relocation;
13193 bfd_reloc_status_type r;
13194 arelent bfd_reloc;
13195 char sym_type;
13196 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13197 char *error_message = NULL;
f21f3fe0 13198
252b5132 13199 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13200 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13201 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13202
ba96a88f 13203 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13204 || r_type == R_ARM_GNU_VTINHERIT)
13205 continue;
252b5132 13206
47aeb64c
NC		 13207 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13208
13209 if (howto == NULL)
13210 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13211
252b5132
RH		 13212 h = NULL;
13213 sym = NULL;
13214 sec = NULL;
9b485d32 13215
252b5132
RH		 13216 if (r_symndx < symtab_hdr->sh_info)
13217 {
13218 sym = local_syms + r_symndx;
ba93b8ac 13219 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13220 sec = local_sections[r_symndx];
ffcb4889
NS		 13221
13222 /* An object file might have a reference to a local
13223 undefined symbol. This is a daft object file, but we
13224 should at least do something about it. V4BX & NONE
13225 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13226 allowed to use the undefined symbol, so allow those.
13227 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13228 if (r_type != R_ARM_V4BX
13229 && r_type != R_ARM_NONE
77b4f08f 13230 && r_symndx != STN_UNDEF
ffcb4889
NS		 13231 && bfd_is_und_section (sec)
13232 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13233 (*info->callbacks->undefined_symbol)
13234 (info, bfd_elf_string_from_elf_section
13235 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13236 input_bfd, input_section,
13237 rel->r_offset, TRUE);
b38cadfb 13238
4e7fd91e 13239 if (globals->use_rel)
f8df10f4 13240 {
4e7fd91e
PB		 13241 relocation = (sec->output_section->vma
13242 + sec->output_offset
13243 + sym->st_value);
0e1862bb 13244 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13245 && (sec->flags & SEC_MERGE)
13246 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13247 {
4e7fd91e
PB		 13248 asection *msec;
13249 bfd_vma addend, value;
13250
39623e12 13251 switch (r_type)
4e7fd91e 13252 {
39623e12
PB		 13253 case R_ARM_MOVW_ABS_NC:
13254 case R_ARM_MOVT_ABS:
13255 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13256 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13257 addend = (addend ^ 0x8000) - 0x8000;
13258 break;
f8df10f4 13259
39623e12
PB		 13260 case R_ARM_THM_MOVW_ABS_NC:
13261 case R_ARM_THM_MOVT_ABS:
13262 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13263 << 16;
13264 value |= bfd_get_16 (input_bfd,
13265 contents + rel->r_offset + 2);
13266 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13267 | ((value & 0x04000000) >> 15);
13268 addend = (addend ^ 0x8000) - 0x8000;
13269 break;
f8df10f4 13270
39623e12
PB		 13271 default:
13272 if (howto->rightshift
13273 || (howto->src_mask & (howto->src_mask + 1)))
13274 {
4eca0228 13275 _bfd_error_handler
695344c0 13276 /* xgettext:c-format */
2dcf00ce
AM		 13277 (_("%pB(%pA+%#" PRIx64 "): "
13278 "%s relocation against SEC_MERGE section"),
39623e12 13279 input_bfd, input_section,
2dcf00ce 13280 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13281 return FALSE;
13282 }
13283
13284 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13285
13286 /* Get the (signed) value from the instruction. */
13287 addend = value & howto->src_mask;
13288 if (addend & ((howto->src_mask + 1) >> 1))
13289 {
13290 bfd_signed_vma mask;
13291
13292 mask = -1;
13293 mask &= ~ howto->src_mask;
13294 addend |= mask;
13295 }
13296 break;
4e7fd91e 13297 }
39623e12 13298
4e7fd91e
PB		 13299 msec = sec;
13300 addend =
13301 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13302 - relocation;
13303 addend += msec->output_section->vma + msec->output_offset;
39623e12 13304
cc643b88 13305 /* Cases here must match those in the preceding
39623e12
PB		 13306 switch statement. */
13307 switch (r_type)
13308 {
13309 case R_ARM_MOVW_ABS_NC:
13310 case R_ARM_MOVT_ABS:
13311 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13312 | (addend & 0xfff);
13313 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13314 break;
13315
13316 case R_ARM_THM_MOVW_ABS_NC:
13317 case R_ARM_THM_MOVT_ABS:
13318 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13319 | (addend & 0xff) | ((addend & 0x0800) << 15);
13320 bfd_put_16 (input_bfd, value >> 16,
13321 contents + rel->r_offset);
13322 bfd_put_16 (input_bfd, value,
13323 contents + rel->r_offset + 2);
13324 break;
13325
13326 default:
13327 value = (value & ~ howto->dst_mask)
13328 | (addend & howto->dst_mask);
13329 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13330 break;
13331 }
f8df10f4 13332 }
f8df10f4 13333 }
4e7fd91e
PB		 13334 else
13335 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13336 }
13337 else
13338 {
62d887d4 13339 bfd_boolean warned, ignored;
560e09e9 13340
b2a8e766
AM		 13341 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13342 r_symndx, symtab_hdr, sym_hashes,
13343 h, sec, relocation,
62d887d4 13344 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13345
13346 sym_type = h->type;
252b5132
RH		 13347 }
13348
dbaa2011 13349 if (sec != NULL && discarded_section (sec))
e4067dbb 13350 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13351 rel, 1, relend, howto, 0, contents);
ab96bf03 13352
0e1862bb 13353 if (bfd_link_relocatable (info))
ab96bf03
AM		 13354 {
13355 /* This is a relocatable link. We don't have to change
13356 anything, unless the reloc is against a section symbol,
13357 in which case we have to adjust according to where the
13358 section symbol winds up in the output section. */
13359 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13360 {
13361 if (globals->use_rel)
13362 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13363 howto, (bfd_signed_vma) sec->output_offset);
13364 else
13365 rel->r_addend += sec->output_offset;
13366 }
13367 continue;
13368 }
13369
252b5132
RH		 13370 if (h != NULL)
13371 name = h->root.root.string;
13372 else
13373 {
13374 name = (bfd_elf_string_from_elf_section
13375 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13376 if (name == NULL || *name == '\0')
13377 name = bfd_section_name (input_bfd, sec);
13378 }
f21f3fe0 13379
cf35638d 13380 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13381 && r_type != R_ARM_NONE
13382 && (h == NULL
13383 || h->root.type == bfd_link_hash_defined
13384 || h->root.type == bfd_link_hash_defweak)
13385 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13386 {
4eca0228 13387 _bfd_error_handler
ba93b8ac 13388 ((sym_type == STT_TLS
695344c0 13389 /* xgettext:c-format */
2dcf00ce 13390 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13391 /* xgettext:c-format */
2dcf00ce 13392 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13393 input_bfd,
13394 input_section,
2dcf00ce 13395 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13396 howto->name,
13397 name);
13398 }
13399
0855e32b 13400 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13401 done, i.e., the relaxation produced the final output we want,
13402 and we won't let anybody mess with it. Also, we have to do
13403 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13404 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13405 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13406 || (IS_ARM_TLS_GNU_RELOC (r_type)
13407 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13408 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13409 & GOT_TLS_GDESC)))
13410 {
13411 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13412 contents, rel, h == NULL);
13413 /* This may have been marked unresolved because it came from
13414 a shared library. But we've just dealt with that. */
13415 unresolved_reloc = 0;
13416 }
13417 else
13418 r = bfd_reloc_continue;
b38cadfb 13419
39d911fc
TP		 13420 if (r == bfd_reloc_continue)
13421 {
13422 unsigned char branch_type =
13423 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13424 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13425
13426 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13427 input_section, contents, rel,
13428 relocation, info, sec, name,
13429 sym_type, branch_type, h,
13430 &unresolved_reloc,
13431 &error_message);
13432 }
0945cdfd
DJ		 13433
13434 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13435 because such sections are not SEC_ALLOC and thus ld.so will
13436 not process them. */
13437 if (unresolved_reloc
99059e56
RM		 13438 && !((input_section->flags & SEC_DEBUGGING) != 0
13439 && h->def_dynamic)
1d5316ab
AM		 13440 && _bfd_elf_section_offset (output_bfd, info, input_section,
13441 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13442 {
4eca0228 13443 _bfd_error_handler
695344c0 13444 /* xgettext:c-format */
2dcf00ce
AM		 13445 (_("%pB(%pA+%#" PRIx64 "): "
13446 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13447 input_bfd,
13448 input_section,
2dcf00ce 13449 (uint64_t) rel->r_offset,
843fe662
L		 13450 howto->name,
13451 h->root.root.string);
0945cdfd
DJ		 13452 return FALSE;
13453 }
252b5132
RH		 13454
13455 if (r != bfd_reloc_ok)
13456 {
252b5132
RH		 13457 switch (r)
13458 {
13459 case bfd_reloc_overflow:
cf919dfd
PB		 13460 /* If the overflowing reloc was to an undefined symbol,
13461 we have already printed one error message and there
13462 is no point complaining again. */
1a72702b
AM		 13463 if (!h || h->root.type != bfd_link_hash_undefined)
13464 (*info->callbacks->reloc_overflow)
13465 (info, (h ? &h->root : NULL), name, howto->name,
13466 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13467 break;
13468
13469 case bfd_reloc_undefined:
1a72702b
AM		 13470 (*info->callbacks->undefined_symbol)
13471 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13472 break;
13473
13474 case bfd_reloc_outofrange:
f2a9dd69 13475 error_message = _("out of range");
252b5132
RH		 13476 goto common_error;
13477
13478 case bfd_reloc_notsupported:
f2a9dd69 13479 error_message = _("unsupported relocation");
252b5132
RH		 13480 goto common_error;
13481
13482 case bfd_reloc_dangerous:
f2a9dd69 13483 /* error_message should already be set. */
252b5132
RH		 13484 goto common_error;
13485
13486 default:
f2a9dd69 13487 error_message = _("unknown error");
8029a119 13488 /* Fall through. */
252b5132
RH		 13489
13490 common_error:
f2a9dd69 13491 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13492 (*info->callbacks->reloc_dangerous)
13493 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13494 break;
13495 }
13496 }
13497 }
13498
b34976b6 13499 return TRUE;
252b5132
RH		 13500}
13501
91d6fa6a 13502/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13503 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13504 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13505 maintaining that condition). */
13506
13507static void
13508add_unwind_table_edit (arm_unwind_table_edit **head,
13509 arm_unwind_table_edit **tail,
13510 arm_unwind_edit_type type,
13511 asection *linked_section,
91d6fa6a 13512 unsigned int tindex)
2468f9c9 13513{
21d799b5
NC		 13514 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13515 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13516
2468f9c9
PB		 13517 new_edit->type = type;
13518 new_edit->linked_section = linked_section;
91d6fa6a 13519 new_edit->index = tindex;
b38cadfb 13520
91d6fa6a 13521 if (tindex > 0)
2468f9c9
PB		 13522 {
13523 new_edit->next = NULL;
13524
13525 if (*tail)
13526 (*tail)->next = new_edit;
13527
13528 (*tail) = new_edit;
13529
13530 if (!*head)
13531 (*head) = new_edit;
13532 }
13533 else
13534 {
13535 new_edit->next = *head;
13536
13537 if (!*tail)
13538 *tail = new_edit;
13539
13540 *head = new_edit;
13541 }
13542}
13543
13544static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13545
13546/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13547static void
13548adjust_exidx_size(asection *exidx_sec, int adjust)
13549{
13550 asection *out_sec;
13551
13552 if (!exidx_sec->rawsize)
13553 exidx_sec->rawsize = exidx_sec->size;
13554
13555 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
13556 out_sec = exidx_sec->output_section;
13557 /* Adjust size of output section. */
13558 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
13559}
13560
13561/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13562static void
13563insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13564{
13565 struct _arm_elf_section_data *exidx_arm_data;
13566
13567 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13568 add_unwind_table_edit (
13569 &exidx_arm_data->u.exidx.unwind_edit_list,
13570 &exidx_arm_data->u.exidx.unwind_edit_tail,
13571 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13572
491d01d3
YU		 13573 exidx_arm_data->additional_reloc_count++;
13574
2468f9c9
PB		 13575 adjust_exidx_size(exidx_sec, 8);
13576}
13577
13578/* Scan .ARM.exidx tables, and create a list describing edits which should be
13579 made to those tables, such that:
b38cadfb 13580
2468f9c9
PB		 13581 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13582 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13583 codes which have been inlined into the index).
2468f9c9 13584
85fdf906
AH		 13585 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13586
2468f9c9 13587 The edits are applied when the tables are written
b38cadfb 13588 (in elf32_arm_write_section). */
2468f9c9
PB		 13589
13590bfd_boolean
13591elf32_arm_fix_exidx_coverage (asection **text_section_order,
13592 unsigned int num_text_sections,
85fdf906
AH		 13593 struct bfd_link_info *info,
13594 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13595{
13596 bfd *inp;
13597 unsigned int last_second_word = 0, i;
13598 asection *last_exidx_sec = NULL;
13599 asection *last_text_sec = NULL;
13600 int last_unwind_type = -1;
13601
13602 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13603 text sections. */
c72f2fb2 13604 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13605 {
13606 asection *sec;
b38cadfb 13607
2468f9c9 13608 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13609 {
2468f9c9
PB		 13610 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13611 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13612
dec9d5df 13613 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13614 continue;
b38cadfb 13615
2468f9c9
PB		 13616 if (elf_sec->linked_to)
13617 {
13618 Elf_Internal_Shdr *linked_hdr
99059e56 13619 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13620 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13621 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13622
13623 if (linked_sec_arm_data == NULL)
99059e56 13624 continue;
2468f9c9
PB		 13625
13626 /* Link this .ARM.exidx section back from the text section it
99059e56 13627 describes. */
2468f9c9
PB		 13628 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13629 }
13630 }
13631 }
13632
13633 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13634 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13635 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13636
13637 for (i = 0; i < num_text_sections; i++)
13638 {
13639 asection *sec = text_section_order[i];
13640 asection *exidx_sec;
13641 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13642 struct _arm_elf_section_data *exidx_arm_data;
13643 bfd_byte *contents = NULL;
13644 int deleted_exidx_bytes = 0;
13645 bfd_vma j;
13646 arm_unwind_table_edit *unwind_edit_head = NULL;
13647 arm_unwind_table_edit *unwind_edit_tail = NULL;
13648 Elf_Internal_Shdr *hdr;
13649 bfd *ibfd;
13650
13651 if (arm_data == NULL)
99059e56 13652 continue;
2468f9c9
PB		 13653
13654 exidx_sec = arm_data->u.text.arm_exidx_sec;
13655 if (exidx_sec == NULL)
13656 {
13657 /* Section has no unwind data. */
13658 if (last_unwind_type == 0 || !last_exidx_sec)
13659 continue;
13660
13661 /* Ignore zero sized sections. */
13662 if (sec->size == 0)
13663 continue;
13664
13665 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13666 last_unwind_type = 0;
13667 continue;
13668 }
13669
22a8f80e
PB		 13670 /* Skip /DISCARD/ sections. */
13671 if (bfd_is_abs_section (exidx_sec->output_section))
13672 continue;
13673
2468f9c9
PB		 13674 hdr = &elf_section_data (exidx_sec)->this_hdr;
13675 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13676 continue;
b38cadfb 13677
2468f9c9
PB		 13678 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13679 if (exidx_arm_data == NULL)
99059e56 13680 continue;
b38cadfb 13681
2468f9c9 13682 ibfd = exidx_sec->owner;
b38cadfb 13683
2468f9c9
PB		 13684 if (hdr->contents != NULL)
13685 contents = hdr->contents;
13686 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13687 /* An error? */
13688 continue;
13689
ac06903d
YU		 13690 if (last_unwind_type > 0)
13691 {
13692 unsigned int first_word = bfd_get_32 (ibfd, contents);
13693 /* Add cantunwind if first unwind item does not match section
13694 start. */
13695 if (first_word != sec->vma)
13696 {
13697 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13698 last_unwind_type = 0;
13699 }
13700 }
13701
2468f9c9
PB		 13702 for (j = 0; j < hdr->sh_size; j += 8)
13703 {
13704 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13705 int unwind_type;
13706 int elide = 0;
13707
13708 /* An EXIDX_CANTUNWIND entry. */
13709 if (second_word == 1)
13710 {
13711 if (last_unwind_type == 0)
13712 elide = 1;
13713 unwind_type = 0;
13714 }
13715 /* Inlined unwinding data. Merge if equal to previous. */
13716 else if ((second_word & 0x80000000) != 0)
13717 {
85fdf906
AH		 13718 if (merge_exidx_entries
13719 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13720 elide = 1;
13721 unwind_type = 1;
13722 last_second_word = second_word;
13723 }
13724 /* Normal table entry. In theory we could merge these too,
13725 but duplicate entries are likely to be much less common. */
13726 else
13727 unwind_type = 2;
13728
491d01d3 13729 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13730 {
13731 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13732 DELETE_EXIDX_ENTRY, NULL, j / 8);
13733
13734 deleted_exidx_bytes += 8;
13735 }
13736
13737 last_unwind_type = unwind_type;
13738 }
13739
13740 /* Free contents if we allocated it ourselves. */
13741 if (contents != hdr->contents)
99059e56 13742 free (contents);
2468f9c9
PB		 13743
13744 /* Record edits to be applied later (in elf32_arm_write_section). */
13745 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13746 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13747
2468f9c9
PB		 13748 if (deleted_exidx_bytes > 0)
13749 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13750
13751 last_exidx_sec = exidx_sec;
13752 last_text_sec = sec;
13753 }
13754
13755 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13756 if (!bfd_link_relocatable (info) && last_exidx_sec
13757 && last_unwind_type != 0)
2468f9c9
PB		 13758 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13759
13760 return TRUE;
13761}
13762
3e6b1042
DJ		 13763static bfd_boolean
13764elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13765 bfd *ibfd, const char *name)
13766{
13767 asection *sec, *osec;
13768
3d4d4302 13769 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13770 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13771 return TRUE;
13772
13773 osec = sec->output_section;
13774 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13775 return TRUE;
13776
13777 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13778 sec->output_offset, sec->size))
13779 return FALSE;
13780
13781 return TRUE;
13782}
13783
13784static bfd_boolean
13785elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13786{
13787 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13788 asection *sec, *osec;
3e6b1042 13789
4dfe6ac6
NC		 13790 if (globals == NULL)
13791 return FALSE;
13792
3e6b1042
DJ		 13793 /* Invoke the regular ELF backend linker to do all the work. */
13794 if (!bfd_elf_final_link (abfd, info))
13795 return FALSE;
13796
fe33d2fa
CL		 13797 /* Process stub sections (eg BE8 encoding, ...). */
13798 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13799 unsigned int i;
cdb21a0a
NS		 13800 for (i=0; i<htab->top_id; i++)
13801 {
13802 sec = htab->stub_group[i].stub_sec;
13803 /* Only process it once, in its link_sec slot. */
13804 if (sec && i == htab->stub_group[i].link_sec->id)
13805 {
13806 osec = sec->output_section;
13807 elf32_arm_write_section (abfd, info, sec, sec->contents);
13808 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13809 sec->output_offset, sec->size))
13810 return FALSE;
13811 }
fe33d2fa 13812 }
fe33d2fa 13813
3e6b1042
DJ		 13814 /* Write out any glue sections now that we have created all the
13815 stubs. */
13816 if (globals->bfd_of_glue_owner != NULL)
13817 {
13818 if (! elf32_arm_output_glue_section (info, abfd,
13819 globals->bfd_of_glue_owner,
13820 ARM2THUMB_GLUE_SECTION_NAME))
13821 return FALSE;
13822
13823 if (! elf32_arm_output_glue_section (info, abfd,
13824 globals->bfd_of_glue_owner,
13825 THUMB2ARM_GLUE_SECTION_NAME))
13826 return FALSE;
13827
13828 if (! elf32_arm_output_glue_section (info, abfd,
13829 globals->bfd_of_glue_owner,
13830 VFP11_ERRATUM_VENEER_SECTION_NAME))
13831 return FALSE;
13832
a504d23a
LA		 13833 if (! elf32_arm_output_glue_section (info, abfd,
13834 globals->bfd_of_glue_owner,
13835 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13836 return FALSE;
13837
3e6b1042
DJ		 13838 if (! elf32_arm_output_glue_section (info, abfd,
13839 globals->bfd_of_glue_owner,
13840 ARM_BX_GLUE_SECTION_NAME))
13841 return FALSE;
13842 }
13843
13844 return TRUE;
13845}
13846
5968a7b8
NC		 13847/* Return a best guess for the machine number based on the attributes. */
13848
13849static unsigned int
13850bfd_arm_get_mach_from_attributes (bfd * abfd)
13851{
13852 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13853
13854 switch (arch)
13855 {
c0c468d5 13856 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13857 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13858 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13859 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13860
13861 case TAG_CPU_ARCH_V5TE:
13862 {
13863 char * name;
13864
13865 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13866 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13867
13868 if (name)
13869 {
13870 if (strcmp (name, "IWMMXT2") == 0)
13871 return bfd_mach_arm_iWMMXt2;
13872
13873 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13874 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13875
13876 if (strcmp (name, "XSCALE") == 0)
13877 {
13878 int wmmx;
13879
13880 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13881 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13882 switch (wmmx)
13883 {
13884 case 1: return bfd_mach_arm_iWMMXt;
13885 case 2: return bfd_mach_arm_iWMMXt2;
13886 default: return bfd_mach_arm_XScale;
13887 }
13888 }
5968a7b8
NC		 13889 }
13890
13891 return bfd_mach_arm_5TE;
13892 }
13893
c0c468d5
TP		 13894 case TAG_CPU_ARCH_V5TEJ:
13895 return bfd_mach_arm_5TEJ;
13896 case TAG_CPU_ARCH_V6:
13897 return bfd_mach_arm_6;
13898 case TAG_CPU_ARCH_V6KZ:
13899 return bfd_mach_arm_6KZ;
13900 case TAG_CPU_ARCH_V6T2:
13901 return bfd_mach_arm_6T2;
13902 case TAG_CPU_ARCH_V6K:
13903 return bfd_mach_arm_6K;
13904 case TAG_CPU_ARCH_V7:
13905 return bfd_mach_arm_7;
13906 case TAG_CPU_ARCH_V6_M:
13907 return bfd_mach_arm_6M;
13908 case TAG_CPU_ARCH_V6S_M:
13909 return bfd_mach_arm_6SM;
13910 case TAG_CPU_ARCH_V7E_M:
13911 return bfd_mach_arm_7EM;
13912 case TAG_CPU_ARCH_V8:
13913 return bfd_mach_arm_8;
13914 case TAG_CPU_ARCH_V8R:
13915 return bfd_mach_arm_8R;
13916 case TAG_CPU_ARCH_V8M_BASE:
13917 return bfd_mach_arm_8M_BASE;
13918 case TAG_CPU_ARCH_V8M_MAIN:
13919 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13920 case TAG_CPU_ARCH_V8_1M_MAIN:
13921 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13922
5968a7b8 13923 default:
c0c468d5
TP		 13924 /* Force entry to be added for any new known Tag_CPU_arch value. */
13925 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13926
13927 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13928 return bfd_mach_arm_unknown;
13929 }
13930}
13931
c178919b
NC		 13932/* Set the right machine number. */
13933
13934static bfd_boolean
57e8b36a 13935elf32_arm_object_p (bfd *abfd)
c178919b 13936{
5a6c6817 13937 unsigned int mach;
57e8b36a 13938
5a6c6817 13939 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13940
5968a7b8
NC		 13941 if (mach == bfd_mach_arm_unknown)
13942 {
13943 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13944 mach = bfd_mach_arm_ep9312;
13945 else
13946 mach = bfd_arm_get_mach_from_attributes (abfd);
13947 }
c178919b 13948
5968a7b8 13949 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13950 return TRUE;
13951}
13952
fc830a83 13953/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13954
b34976b6 13955static bfd_boolean
57e8b36a 13956elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13957{
13958 if (elf_flags_init (abfd)
13959 && elf_elfheader (abfd)->e_flags != flags)
13960 {
fc830a83
NC		 13961 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13962 {
fd2ec330 13963 if (flags & EF_ARM_INTERWORK)
4eca0228 13964 _bfd_error_handler
90b6238f 13965 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13966 abfd);
fc830a83 13967 else
d003868e 13968 _bfd_error_handler
90b6238f 13969 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13970 abfd);
fc830a83 13971 }
252b5132
RH		 13972 }
13973 else
13974 {
13975 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13976 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13977 }
13978
b34976b6 13979 return TRUE;
252b5132
RH		 13980}
13981
fc830a83 13982/* Copy backend specific data from one object module to another. */
9b485d32 13983
b34976b6 13984static bfd_boolean
57e8b36a 13985elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13986{
13987 flagword in_flags;
13988 flagword out_flags;
13989
0ffa91dd 13990 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13991 return TRUE;
252b5132 13992
fc830a83 13993 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13994 out_flags = elf_elfheader (obfd)->e_flags;
13995
fc830a83
NC		 13996 if (elf_flags_init (obfd)
13997 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13998 && in_flags != out_flags)
252b5132 13999 {
252b5132 14000 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 14001 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 14002 return FALSE;
252b5132
RH		 14003
14004 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 14005 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 14006 return FALSE;
252b5132
RH		 14007
14008 /* If the src and dest have different interworking flags
99059e56 14009 then turn off the interworking bit. */
fd2ec330 14010 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 14011 {
fd2ec330 14012 if (out_flags & EF_ARM_INTERWORK)
d003868e 14013 _bfd_error_handler
90b6238f 14014 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 14015 obfd, ibfd);
252b5132 14016
fd2ec330 14017 in_flags &= ~EF_ARM_INTERWORK;
252b5132 14018 }
1006ba19
PB		 14019
14020 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 14021 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
14022 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 14023 }
14024
14025 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 14026 elf_flags_init (obfd) = TRUE;
252b5132 14027
e2349352 14028 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 14029}
14030
14031/* Values for Tag_ABI_PCS_R9_use. */
14032enum
14033{
14034 AEABI_R9_V6,
14035 AEABI_R9_SB,
14036 AEABI_R9_TLS,
14037 AEABI_R9_unused
14038};
14039
14040/* Values for Tag_ABI_PCS_RW_data. */
14041enum
14042{
14043 AEABI_PCS_RW_data_absolute,
14044 AEABI_PCS_RW_data_PCrel,
14045 AEABI_PCS_RW_data_SBrel,
14046 AEABI_PCS_RW_data_unused
14047};
14048
14049/* Values for Tag_ABI_enum_size. */
14050enum
14051{
14052 AEABI_enum_unused,
14053 AEABI_enum_short,
14054 AEABI_enum_wide,
14055 AEABI_enum_forced_wide
14056};
14057
104d59d1
JM		 14058/* Determine whether an object attribute tag takes an integer, a
14059 string or both. */
906e58ca 14060
104d59d1
JM		 14061static int
14062elf32_arm_obj_attrs_arg_type (int tag)
14063{
14064 if (tag == Tag_compatibility)
3483fe2e 14065 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14066 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14067 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14068 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14069 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14070 else if (tag < 32)
3483fe2e 14071 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14072 else
3483fe2e 14073 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14074}
14075
5aa6ff7c
AS		 14076/* The ABI defines that Tag_conformance should be emitted first, and that
14077 Tag_nodefaults should be second (if either is defined). This sets those
14078 two positions, and bumps up the position of all the remaining tags to
14079 compensate. */
14080static int
14081elf32_arm_obj_attrs_order (int num)
14082{
3de4a297 14083 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14084 return Tag_conformance;
3de4a297 14085 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14086 return Tag_nodefaults;
14087 if ((num - 2) < Tag_nodefaults)
14088 return num - 2;
14089 if ((num - 1) < Tag_conformance)
14090 return num - 1;
14091 return num;
14092}
14093
e8b36cd1
JM		 14094/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14095static bfd_boolean
14096elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14097{
14098 if ((tag & 127) < 64)
14099 {
14100 _bfd_error_handler
90b6238f 14101 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14102 abfd, tag);
14103 bfd_set_error (bfd_error_bad_value);
14104 return FALSE;
14105 }
14106 else
14107 {
14108 _bfd_error_handler
90b6238f 14109 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14110 abfd, tag);
14111 return TRUE;
14112 }
14113}
14114
91e22acd
AS		 14115/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14116 Returns -1 if no architecture could be read. */
14117
14118static int
14119get_secondary_compatible_arch (bfd *abfd)
14120{
14121 obj_attribute *attr =
14122 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14123
14124 /* Note: the tag and its argument below are uleb128 values, though
14125 currently-defined values fit in one byte for each. */
14126 if (attr->s
14127 && attr->s[0] == Tag_CPU_arch
14128 && (attr->s[1] & 128) != 128
14129 && attr->s[2] == 0)
14130 return attr->s[1];
14131
14132 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14133 return -1;
14134}
14135
14136/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14137 The tag is removed if ARCH is -1. */
14138
8e79c3df 14139static void
91e22acd 14140set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14141{
91e22acd
AS		 14142 obj_attribute *attr =
14143 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14144
91e22acd
AS		 14145 if (arch == -1)
14146 {
14147 attr->s = NULL;
14148 return;
8e79c3df 14149 }
91e22acd
AS		 14150
14151 /* Note: the tag and its argument below are uleb128 values, though
14152 currently-defined values fit in one byte for each. */
14153 if (!attr->s)
21d799b5 14154 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14155 attr->s[0] = Tag_CPU_arch;
14156 attr->s[1] = arch;
14157 attr->s[2] = '\0';
8e79c3df
CM		 14158}
14159
91e22acd
AS		 14160/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14161 into account. */
14162
14163static int
14164tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14165 int newtag, int secondary_compat)
8e79c3df 14166{
91e22acd
AS		 14167#define T(X) TAG_CPU_ARCH_##X
14168 int tagl, tagh, result;
14169 const int v6t2[] =
14170 {
14171 T(V6T2), /* PRE_V4. */
14172 T(V6T2), /* V4. */
14173 T(V6T2), /* V4T. */
14174 T(V6T2), /* V5T. */
14175 T(V6T2), /* V5TE. */
14176 T(V6T2), /* V5TEJ. */
14177 T(V6T2), /* V6. */
14178 T(V7), /* V6KZ. */
14179 T(V6T2) /* V6T2. */
14180 };
14181 const int v6k[] =
14182 {
14183 T(V6K), /* PRE_V4. */
14184 T(V6K), /* V4. */
14185 T(V6K), /* V4T. */
14186 T(V6K), /* V5T. */
14187 T(V6K), /* V5TE. */
14188 T(V6K), /* V5TEJ. */
14189 T(V6K), /* V6. */
14190 T(V6KZ), /* V6KZ. */
14191 T(V7), /* V6T2. */
14192 T(V6K) /* V6K. */
14193 };
14194 const int v7[] =
14195 {
14196 T(V7), /* PRE_V4. */
14197 T(V7), /* V4. */
14198 T(V7), /* V4T. */
14199 T(V7), /* V5T. */
14200 T(V7), /* V5TE. */
14201 T(V7), /* V5TEJ. */
14202 T(V7), /* V6. */
14203 T(V7), /* V6KZ. */
14204 T(V7), /* V6T2. */
14205 T(V7), /* V6K. */
14206 T(V7) /* V7. */
14207 };
14208 const int v6_m[] =
14209 {
07d6d2b8
AM		 14210 -1, /* PRE_V4. */
14211 -1, /* V4. */
91e22acd
AS		 14212 T(V6K), /* V4T. */
14213 T(V6K), /* V5T. */
14214 T(V6K), /* V5TE. */
14215 T(V6K), /* V5TEJ. */
14216 T(V6K), /* V6. */
14217 T(V6KZ), /* V6KZ. */
14218 T(V7), /* V6T2. */
14219 T(V6K), /* V6K. */
14220 T(V7), /* V7. */
14221 T(V6_M) /* V6_M. */
14222 };
14223 const int v6s_m[] =
14224 {
07d6d2b8
AM		 14225 -1, /* PRE_V4. */
14226 -1, /* V4. */
91e22acd
AS		 14227 T(V6K), /* V4T. */
14228 T(V6K), /* V5T. */
14229 T(V6K), /* V5TE. */
14230 T(V6K), /* V5TEJ. */
14231 T(V6K), /* V6. */
14232 T(V6KZ), /* V6KZ. */
14233 T(V7), /* V6T2. */
14234 T(V6K), /* V6K. */
14235 T(V7), /* V7. */
14236 T(V6S_M), /* V6_M. */
14237 T(V6S_M) /* V6S_M. */
14238 };
9e3c6df6
PB		 14239 const int v7e_m[] =
14240 {
07d6d2b8
AM		 14241 -1, /* PRE_V4. */
14242 -1, /* V4. */
9e3c6df6
PB		 14243 T(V7E_M), /* V4T. */
14244 T(V7E_M), /* V5T. */
14245 T(V7E_M), /* V5TE. */
14246 T(V7E_M), /* V5TEJ. */
14247 T(V7E_M), /* V6. */
14248 T(V7E_M), /* V6KZ. */
14249 T(V7E_M), /* V6T2. */
14250 T(V7E_M), /* V6K. */
14251 T(V7E_M), /* V7. */
14252 T(V7E_M), /* V6_M. */
14253 T(V7E_M), /* V6S_M. */
14254 T(V7E_M) /* V7E_M. */
14255 };
bca38921
MGD		 14256 const int v8[] =
14257 {
14258 T(V8), /* PRE_V4. */
14259 T(V8), /* V4. */
14260 T(V8), /* V4T. */
14261 T(V8), /* V5T. */
14262 T(V8), /* V5TE. */
14263 T(V8), /* V5TEJ. */
14264 T(V8), /* V6. */
14265 T(V8), /* V6KZ. */
14266 T(V8), /* V6T2. */
14267 T(V8), /* V6K. */
14268 T(V8), /* V7. */
14269 T(V8), /* V6_M. */
14270 T(V8), /* V6S_M. */
14271 T(V8), /* V7E_M. */
14272 T(V8) /* V8. */
14273 };
bff0500d
TP		 14274 const int v8r[] =
14275 {
14276 T(V8R), /* PRE_V4. */
14277 T(V8R), /* V4. */
14278 T(V8R), /* V4T. */
14279 T(V8R), /* V5T. */
14280 T(V8R), /* V5TE. */
14281 T(V8R), /* V5TEJ. */
14282 T(V8R), /* V6. */
14283 T(V8R), /* V6KZ. */
14284 T(V8R), /* V6T2. */
14285 T(V8R), /* V6K. */
14286 T(V8R), /* V7. */
14287 T(V8R), /* V6_M. */
14288 T(V8R), /* V6S_M. */
14289 T(V8R), /* V7E_M. */
14290 T(V8), /* V8. */
14291 T(V8R), /* V8R. */
14292 };
2fd158eb
TP		 14293 const int v8m_baseline[] =
14294 {
14295 -1, /* PRE_V4. */
14296 -1, /* V4. */
14297 -1, /* V4T. */
14298 -1, /* V5T. */
14299 -1, /* V5TE. */
14300 -1, /* V5TEJ. */
14301 -1, /* V6. */
14302 -1, /* V6KZ. */
14303 -1, /* V6T2. */
14304 -1, /* V6K. */
14305 -1, /* V7. */
14306 T(V8M_BASE), /* V6_M. */
14307 T(V8M_BASE), /* V6S_M. */
14308 -1, /* V7E_M. */
14309 -1, /* V8. */
bff0500d 14310 -1, /* V8R. */
2fd158eb
TP		 14311 T(V8M_BASE) /* V8-M BASELINE. */
14312 };
14313 const int v8m_mainline[] =
14314 {
14315 -1, /* PRE_V4. */
14316 -1, /* V4. */
14317 -1, /* V4T. */
14318 -1, /* V5T. */
14319 -1, /* V5TE. */
14320 -1, /* V5TEJ. */
14321 -1, /* V6. */
14322 -1, /* V6KZ. */
14323 -1, /* V6T2. */
14324 -1, /* V6K. */
14325 T(V8M_MAIN), /* V7. */
14326 T(V8M_MAIN), /* V6_M. */
14327 T(V8M_MAIN), /* V6S_M. */
14328 T(V8M_MAIN), /* V7E_M. */
14329 -1, /* V8. */
bff0500d 14330 -1, /* V8R. */
2fd158eb
TP		 14331 T(V8M_MAIN), /* V8-M BASELINE. */
14332 T(V8M_MAIN) /* V8-M MAINLINE. */
14333 };
031254f2
AV		 14334 const int v8_1m_mainline[] =
14335 {
14336 -1, /* PRE_V4. */
14337 -1, /* V4. */
14338 -1, /* V4T. */
14339 -1, /* V5T. */
14340 -1, /* V5TE. */
14341 -1, /* V5TEJ. */
14342 -1, /* V6. */
14343 -1, /* V6KZ. */
14344 -1, /* V6T2. */
14345 -1, /* V6K. */
14346 T(V8_1M_MAIN), /* V7. */
14347 T(V8_1M_MAIN), /* V6_M. */
14348 T(V8_1M_MAIN), /* V6S_M. */
14349 T(V8_1M_MAIN), /* V7E_M. */
14350 -1, /* V8. */
14351 -1, /* V8R. */
14352 T(V8_1M_MAIN), /* V8-M BASELINE. */
14353 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14354 -1, /* Unused (18). */
14355 -1, /* Unused (19). */
14356 -1, /* Unused (20). */
14357 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14358 };
91e22acd
AS		 14359 const int v4t_plus_v6_m[] =
14360 {
14361 -1, /* PRE_V4. */
14362 -1, /* V4. */
14363 T(V4T), /* V4T. */
14364 T(V5T), /* V5T. */
14365 T(V5TE), /* V5TE. */
14366 T(V5TEJ), /* V5TEJ. */
14367 T(V6), /* V6. */
14368 T(V6KZ), /* V6KZ. */
14369 T(V6T2), /* V6T2. */
14370 T(V6K), /* V6K. */
14371 T(V7), /* V7. */
14372 T(V6_M), /* V6_M. */
14373 T(V6S_M), /* V6S_M. */
9e3c6df6 14374 T(V7E_M), /* V7E_M. */
bca38921 14375 T(V8), /* V8. */
bff0500d 14376 -1, /* V8R. */
2fd158eb
TP		 14377 T(V8M_BASE), /* V8-M BASELINE. */
14378 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14379 -1, /* Unused (18). */
14380 -1, /* Unused (19). */
14381 -1, /* Unused (20). */
14382 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14383 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14384 };
14385 const int *comb[] =
14386 {
14387 v6t2,
14388 v6k,
14389 v7,
14390 v6_m,
14391 v6s_m,
9e3c6df6 14392 v7e_m,
bca38921 14393 v8,
bff0500d 14394 v8r,
2fd158eb
TP		 14395 v8m_baseline,
14396 v8m_mainline,
031254f2
AV		 14397 NULL,
14398 NULL,
14399 NULL,
14400 v8_1m_mainline,
91e22acd
AS		 14401 /* Pseudo-architecture. */
14402 v4t_plus_v6_m
14403 };
14404
14405 /* Check we've not got a higher architecture than we know about. */
14406
9e3c6df6 14407 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14408 {
90b6238f 14409 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14410 return -1;
14411 }
14412
14413 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14414
14415 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14416 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14417 oldtag = T(V4T_PLUS_V6_M);
14418
14419 /* And override the new tag if we have a Tag_also_compatible_with on the
14420 input. */
14421
14422 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14423 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14424 newtag = T(V4T_PLUS_V6_M);
14425
14426 tagl = (oldtag < newtag) ? oldtag : newtag;
14427 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14428
14429 /* Architectures before V6KZ add features monotonically. */
14430 if (tagh <= TAG_CPU_ARCH_V6KZ)
14431 return result;
14432
4ed7ed8d 14433 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14434
14435 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14436 as the canonical version. */
14437 if (result == T(V4T_PLUS_V6_M))
14438 {
14439 result = T(V4T);
14440 *secondary_compat_out = T(V6_M);
14441 }
14442 else
14443 *secondary_compat_out = -1;
14444
14445 if (result == -1)
14446 {
90b6238f 14447 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14448 ibfd, oldtag, newtag);
14449 return -1;
14450 }
14451
14452 return result;
14453#undef T
8e79c3df
CM		 14454}
14455
ac56ee8f
MGD		 14456/* Query attributes object to see if integer divide instructions may be
14457 present in an object. */
14458static bfd_boolean
14459elf32_arm_attributes_accept_div (const obj_attribute *attr)
14460{
14461 int arch = attr[Tag_CPU_arch].i;
14462 int profile = attr[Tag_CPU_arch_profile].i;
14463
14464 switch (attr[Tag_DIV_use].i)
14465 {
14466 case 0:
14467 /* Integer divide allowed if instruction contained in archetecture. */
14468 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14469 return TRUE;
14470 else if (arch >= TAG_CPU_ARCH_V7E_M)
14471 return TRUE;
14472 else
14473 return FALSE;
14474
14475 case 1:
14476 /* Integer divide explicitly prohibited. */
14477 return FALSE;
14478
14479 default:
14480 /* Unrecognised case - treat as allowing divide everywhere. */
14481 case 2:
14482 /* Integer divide allowed in ARM state. */
14483 return TRUE;
14484 }
14485}
14486
14487/* Query attributes object to see if integer divide instructions are
14488 forbidden to be in the object. This is not the inverse of
14489 elf32_arm_attributes_accept_div. */
14490static bfd_boolean
14491elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14492{
14493 return attr[Tag_DIV_use].i == 1;
14494}
14495
ee065d83
PB		 14496/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14497 are conflicting attributes. */
906e58ca 14498
ee065d83 14499static bfd_boolean
50e03d47 14500elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14501{
50e03d47 14502 bfd *obfd = info->output_bfd;
104d59d1
JM		 14503 obj_attribute *in_attr;
14504 obj_attribute *out_attr;
ee065d83
PB		 14505 /* Some tags have 0 = don't care, 1 = strong requirement,
14506 2 = weak requirement. */
91e22acd 14507 static const int order_021[3] = {0, 2, 1};
ee065d83 14508 int i;
91e22acd 14509 bfd_boolean result = TRUE;
9274e9de 14510 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14511
3e6b1042
DJ		 14512 /* Skip the linker stubs file. This preserves previous behavior
14513 of accepting unknown attributes in the first input file - but
14514 is that a bug? */
14515 if (ibfd->flags & BFD_LINKER_CREATED)
14516 return TRUE;
14517
9274e9de
TG		 14518 /* Skip any input that hasn't attribute section.
14519 This enables to link object files without attribute section with
14520 any others. */
14521 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14522 return TRUE;
14523
104d59d1 14524 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14525 {
14526 /* This is the first object. Copy the attributes. */
104d59d1 14527 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14528
cd21e546
MGD		 14529 out_attr = elf_known_obj_attributes_proc (obfd);
14530
004ae526
PB		 14531 /* Use the Tag_null value to indicate the attributes have been
14532 initialized. */
cd21e546 14533 out_attr[0].i = 1;
004ae526 14534
cd21e546
MGD		 14535 /* We do not output objects with Tag_MPextension_use_legacy - we move
14536 the attribute's value to Tag_MPextension_use. */
14537 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14538 {
14539 if (out_attr[Tag_MPextension_use].i != 0
14540 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14541 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14542 {
14543 _bfd_error_handler
871b3ab2 14544 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14545 "Tag_MPextension_use attributes"), ibfd);
14546 result = FALSE;
14547 }
14548
14549 out_attr[Tag_MPextension_use] =
14550 out_attr[Tag_MPextension_use_legacy];
14551 out_attr[Tag_MPextension_use_legacy].type = 0;
14552 out_attr[Tag_MPextension_use_legacy].i = 0;
14553 }
14554
14555 return result;
ee065d83
PB		 14556 }
14557
104d59d1
JM		 14558 in_attr = elf_known_obj_attributes_proc (ibfd);
14559 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14560 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14561 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14562 {
5c294fee
TG		 14563 /* Ignore mismatches if the object doesn't use floating point or is
14564 floating point ABI independent. */
14565 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14566 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14567 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14568 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14569 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14570 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14571 {
14572 _bfd_error_handler
871b3ab2 14573 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14574 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14575 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14576 result = FALSE;
ee065d83
PB		 14577 }
14578 }
14579
3de4a297 14580 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14581 {
14582 /* Merge this attribute with existing attributes. */
14583 switch (i)
14584 {
14585 case Tag_CPU_raw_name:
14586 case Tag_CPU_name:
6a631e86 14587 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14588 break;
14589
14590 case Tag_ABI_optimization_goals:
14591 case Tag_ABI_FP_optimization_goals:
14592 /* Use the first value seen. */
14593 break;
14594
14595 case Tag_CPU_arch:
91e22acd
AS		 14596 {
14597 int secondary_compat = -1, secondary_compat_out = -1;
14598 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14599 int arch_attr;
14600 static const char *name_table[] =
14601 {
91e22acd
AS		 14602 /* These aren't real CPU names, but we can't guess
14603 that from the architecture version alone. */
14604 "Pre v4",
14605 "ARM v4",
14606 "ARM v4T",
14607 "ARM v5T",
14608 "ARM v5TE",
14609 "ARM v5TEJ",
14610 "ARM v6",
14611 "ARM v6KZ",
14612 "ARM v6T2",
14613 "ARM v6K",
14614 "ARM v7",
14615 "ARM v6-M",
bca38921 14616 "ARM v6S-M",
2fd158eb
TP		 14617 "ARM v8",
14618 "",
14619 "ARM v8-M.baseline",
14620 "ARM v8-M.mainline",
91e22acd
AS		 14621 };
14622
14623 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14624 secondary_compat = get_secondary_compatible_arch (ibfd);
14625 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14626 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14627 &secondary_compat_out,
14628 in_attr[i].i,
14629 secondary_compat);
14630
14631 /* Return with error if failed to merge. */
14632 if (arch_attr == -1)
14633 return FALSE;
14634
14635 out_attr[i].i = arch_attr;
14636
91e22acd
AS		 14637 set_secondary_compatible_arch (obfd, secondary_compat_out);
14638
14639 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14640 if (out_attr[i].i == saved_out_attr)
14641 ; /* Leave the names alone. */
14642 else if (out_attr[i].i == in_attr[i].i)
14643 {
14644 /* The output architecture has been changed to match the
14645 input architecture. Use the input names. */
14646 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14647 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14648 : NULL;
14649 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14650 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14651 : NULL;
14652 }
14653 else
14654 {
14655 out_attr[Tag_CPU_name].s = NULL;
14656 out_attr[Tag_CPU_raw_name].s = NULL;
14657 }
14658
14659 /* If we still don't have a value for Tag_CPU_name,
14660 make one up now. Tag_CPU_raw_name remains blank. */
14661 if (out_attr[Tag_CPU_name].s == NULL
14662 && out_attr[i].i < ARRAY_SIZE (name_table))
14663 out_attr[Tag_CPU_name].s =
14664 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14665 }
14666 break;
14667
ee065d83
PB		 14668 case Tag_ARM_ISA_use:
14669 case Tag_THUMB_ISA_use:
ee065d83 14670 case Tag_WMMX_arch:
91e22acd
AS		 14671 case Tag_Advanced_SIMD_arch:
14672 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14673 case Tag_ABI_FP_rounding:
ee065d83
PB		 14674 case Tag_ABI_FP_exceptions:
14675 case Tag_ABI_FP_user_exceptions:
14676 case Tag_ABI_FP_number_model:
75375b3e 14677 case Tag_FP_HP_extension:
91e22acd
AS		 14678 case Tag_CPU_unaligned_access:
14679 case Tag_T2EE_use:
91e22acd 14680 case Tag_MPextension_use:
a7ad558c 14681 case Tag_MVE_arch:
ee065d83
PB		 14682 /* Use the largest value specified. */
14683 if (in_attr[i].i > out_attr[i].i)
14684 out_attr[i].i = in_attr[i].i;
14685 break;
14686
75375b3e 14687 case Tag_ABI_align_preserved:
91e22acd
AS		 14688 case Tag_ABI_PCS_RO_data:
14689 /* Use the smallest value specified. */
14690 if (in_attr[i].i < out_attr[i].i)
14691 out_attr[i].i = in_attr[i].i;
14692 break;
14693
75375b3e 14694 case Tag_ABI_align_needed:
91e22acd 14695 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14696 && (in_attr[Tag_ABI_align_preserved].i == 0
14697 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14698 {
91e22acd
AS		 14699 /* This error message should be enabled once all non-conformant
14700 binaries in the toolchain have had the attributes set
14701 properly.
ee065d83 14702 _bfd_error_handler
871b3ab2 14703 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14704 obfd, ibfd);
14705 result = FALSE; */
ee065d83 14706 }
91e22acd
AS		 14707 /* Fall through. */
14708 case Tag_ABI_FP_denormal:
14709 case Tag_ABI_PCS_GOT_use:
14710 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14711 value if greater than 2 (for future-proofing). */
14712 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14713 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14714 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14715 out_attr[i].i = in_attr[i].i;
14716 break;
91e22acd 14717
75375b3e
MGD		 14718 case Tag_Virtualization_use:
14719 /* The virtualization tag effectively stores two bits of
14720 information: the intended use of TrustZone (in bit 0), and the
14721 intended use of Virtualization (in bit 1). */
14722 if (out_attr[i].i == 0)
14723 out_attr[i].i = in_attr[i].i;
14724 else if (in_attr[i].i != 0
14725 && in_attr[i].i != out_attr[i].i)
14726 {
14727 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14728 out_attr[i].i = 3;
14729 else
14730 {
14731 _bfd_error_handler
871b3ab2
AM		 14732 (_("error: %pB: unable to merge virtualization attributes "
14733 "with %pB"),
75375b3e
MGD		 14734 obfd, ibfd);
14735 result = FALSE;
14736 }
14737 }
14738 break;
91e22acd
AS		 14739
14740 case Tag_CPU_arch_profile:
14741 if (out_attr[i].i != in_attr[i].i)
14742 {
14743 /* 0 will merge with anything.
14744 'A' and 'S' merge to 'A'.
14745 'R' and 'S' merge to 'R'.
99059e56 14746 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14747 if (out_attr[i].i == 0
14748 || (out_attr[i].i == 'S'
14749 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14750 out_attr[i].i = in_attr[i].i;
14751 else if (in_attr[i].i == 0
14752 || (in_attr[i].i == 'S'
14753 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14754 ; /* Do nothing. */
91e22acd
AS		 14755 else
14756 {
14757 _bfd_error_handler
90b6238f 14758 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14759 ibfd,
14760 in_attr[i].i ? in_attr[i].i : '0',
14761 out_attr[i].i ? out_attr[i].i : '0');
14762 result = FALSE;
14763 }
14764 }
14765 break;
15afaa63
TP		 14766
14767 case Tag_DSP_extension:
14768 /* No need to change output value if any of:
14769 - pre (<=) ARMv5T input architecture (do not have DSP)
14770 - M input profile not ARMv7E-M and do not have DSP. */
14771 if (in_attr[Tag_CPU_arch].i <= 3
14772 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14773 && in_attr[Tag_CPU_arch].i != 13
14774 && in_attr[i].i == 0))
14775 ; /* Do nothing. */
14776 /* Output value should be 0 if DSP part of architecture, ie.
14777 - post (>=) ARMv5te architecture output
14778 - A, R or S profile output or ARMv7E-M output architecture. */
14779 else if (out_attr[Tag_CPU_arch].i >= 4
14780 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14781 || out_attr[Tag_CPU_arch_profile].i == 'R'
14782 || out_attr[Tag_CPU_arch_profile].i == 'S'
14783 || out_attr[Tag_CPU_arch].i == 13))
14784 out_attr[i].i = 0;
14785 /* Otherwise, DSP instructions are added and not part of output
14786 architecture. */
14787 else
14788 out_attr[i].i = 1;
14789 break;
14790
75375b3e 14791 case Tag_FP_arch:
62f3b8c8 14792 {
4547cb56
NC		 14793 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14794 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14795 when it's 0. It might mean absence of FP hardware if
99654aaf 14796 Tag_FP_arch is zero. */
4547cb56 14797
a715796b 14798#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14799 static const struct
14800 {
14801 int ver;
14802 int regs;
bca38921 14803 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14804 {
14805 {0, 0},
14806 {1, 16},
14807 {2, 16},
14808 {3, 32},
14809 {3, 16},
14810 {4, 32},
bca38921 14811 {4, 16},
a715796b
TG		 14812 {8, 32},
14813 {8, 16}
62f3b8c8
PB		 14814 };
14815 int ver;
14816 int regs;
14817 int newval;
14818
4547cb56
NC		 14819 /* If the output has no requirement about FP hardware,
14820 follow the requirement of the input. */
14821 if (out_attr[i].i == 0)
14822 {
4ec192e6
RE		 14823 /* This assert is still reasonable, we shouldn't
14824 produce the suspicious build attribute
14825 combination (See below for in_attr). */
4547cb56
NC		 14826 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14827 out_attr[i].i = in_attr[i].i;
14828 out_attr[Tag_ABI_HardFP_use].i
14829 = in_attr[Tag_ABI_HardFP_use].i;
14830 break;
14831 }
14832 /* If the input has no requirement about FP hardware, do
14833 nothing. */
14834 else if (in_attr[i].i == 0)
14835 {
4ec192e6
RE		 14836 /* We used to assert that Tag_ABI_HardFP_use was
14837 zero here, but we should never assert when
14838 consuming an object file that has suspicious
14839 build attributes. The single precision variant
14840 of 'no FP architecture' is still 'no FP
14841 architecture', so we just ignore the tag in this
14842 case. */
4547cb56
NC		 14843 break;
14844 }
14845
14846 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14847 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14848
14849 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14850 do nothing. */
14851 if (in_attr[Tag_ABI_HardFP_use].i == 0
14852 && out_attr[Tag_ABI_HardFP_use].i == 0)
14853 ;
14854 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14855 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14856 else if (in_attr[Tag_ABI_HardFP_use].i
14857 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14858 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14859
14860 /* Now we can handle Tag_FP_arch. */
14861
bca38921
MGD		 14862 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14863 pick the biggest. */
14864 if (in_attr[i].i >= VFP_VERSION_COUNT
14865 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14866 {
14867 out_attr[i] = in_attr[i];
14868 break;
14869 }
14870 /* The output uses the superset of input features
14871 (ISA version) and registers. */
14872 ver = vfp_versions[in_attr[i].i].ver;
14873 if (ver < vfp_versions[out_attr[i].i].ver)
14874 ver = vfp_versions[out_attr[i].i].ver;
14875 regs = vfp_versions[in_attr[i].i].regs;
14876 if (regs < vfp_versions[out_attr[i].i].regs)
14877 regs = vfp_versions[out_attr[i].i].regs;
14878 /* This assumes all possible supersets are also a valid
99059e56 14879 options. */
bca38921 14880 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14881 {
14882 if (regs == vfp_versions[newval].regs
14883 && ver == vfp_versions[newval].ver)
14884 break;
14885 }
14886 out_attr[i].i = newval;
14887 }
b1cc4aeb 14888 break;
ee065d83
PB		 14889 case Tag_PCS_config:
14890 if (out_attr[i].i == 0)
14891 out_attr[i].i = in_attr[i].i;
b6009aca 14892 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14893 {
14894 /* It's sometimes ok to mix different configs, so this is only
99059e56 14895 a warning. */
ee065d83 14896 _bfd_error_handler
90b6238f 14897 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14898 }
14899 break;
14900 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14901 if (in_attr[i].i != out_attr[i].i
14902 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14903 && in_attr[i].i != AEABI_R9_unused)
14904 {
14905 _bfd_error_handler
90b6238f 14906 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14907 result = FALSE;
ee065d83
PB		 14908 }
14909 if (out_attr[i].i == AEABI_R9_unused)
14910 out_attr[i].i = in_attr[i].i;
14911 break;
14912 case Tag_ABI_PCS_RW_data:
14913 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14914 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14915 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14916 {
14917 _bfd_error_handler
871b3ab2 14918 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14919 ibfd);
91e22acd 14920 result = FALSE;
ee065d83
PB		 14921 }
14922 /* Use the smallest value specified. */
14923 if (in_attr[i].i < out_attr[i].i)
14924 out_attr[i].i = in_attr[i].i;
14925 break;
ee065d83 14926 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14927 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14928 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14929 {
14930 _bfd_error_handler
871b3ab2 14931 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14932 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14933 }
a9dc9481 14934 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14935 out_attr[i].i = in_attr[i].i;
14936 break;
ee065d83
PB		 14937 case Tag_ABI_enum_size:
14938 if (in_attr[i].i != AEABI_enum_unused)
14939 {
14940 if (out_attr[i].i == AEABI_enum_unused
14941 || out_attr[i].i == AEABI_enum_forced_wide)
14942 {
14943 /* The existing object is compatible with anything.
14944 Use whatever requirements the new object has. */
14945 out_attr[i].i = in_attr[i].i;
14946 }
14947 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14948 && out_attr[i].i != in_attr[i].i
0ffa91dd 14949 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14950 {
91e22acd 14951 static const char *aeabi_enum_names[] =
bf21ed78 14952 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14953 const char *in_name =
14954 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14955 ? aeabi_enum_names[in_attr[i].i]
14956 : "<unknown>";
14957 const char *out_name =
14958 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14959 ? aeabi_enum_names[out_attr[i].i]
14960 : "<unknown>";
ee065d83 14961 _bfd_error_handler
871b3ab2 14962 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14963 ibfd, in_name, out_name);
ee065d83
PB		 14964 }
14965 }
14966 break;
14967 case Tag_ABI_VFP_args:
14968 /* Aready done. */
14969 break;
14970 case Tag_ABI_WMMX_args:
14971 if (in_attr[i].i != out_attr[i].i)
14972 {
14973 _bfd_error_handler
871b3ab2 14974 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14975 ibfd, obfd);
91e22acd 14976 result = FALSE;
ee065d83
PB		 14977 }
14978 break;
7b86a9fa
AS		 14979 case Tag_compatibility:
14980 /* Merged in target-independent code. */
14981 break;
91e22acd 14982 case Tag_ABI_HardFP_use:
4547cb56 14983 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14984 break;
14985 case Tag_ABI_FP_16bit_format:
14986 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14987 {
14988 if (in_attr[i].i != out_attr[i].i)
14989 {
14990 _bfd_error_handler
871b3ab2 14991 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14992 ibfd, obfd);
14993 result = FALSE;
14994 }
14995 }
14996 if (in_attr[i].i != 0)
14997 out_attr[i].i = in_attr[i].i;
14998 break;
7b86a9fa 14999
cd21e546 15000 case Tag_DIV_use:
ac56ee8f
MGD		 15001 /* A value of zero on input means that the divide instruction may
15002 be used if available in the base architecture as specified via
15003 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15004 the user did not want divide instructions. A value of 2
15005 explicitly means that divide instructions were allowed in ARM
15006 and Thumb state. */
15007 if (in_attr[i].i == out_attr[i].i)
15008 /* Do nothing. */ ;
15009 else if (elf32_arm_attributes_forbid_div (in_attr)
15010 && !elf32_arm_attributes_accept_div (out_attr))
15011 out_attr[i].i = 1;
15012 else if (elf32_arm_attributes_forbid_div (out_attr)
15013 && elf32_arm_attributes_accept_div (in_attr))
15014 out_attr[i].i = in_attr[i].i;
15015 else if (in_attr[i].i == 2)
15016 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 15017 break;
15018
15019 case Tag_MPextension_use_legacy:
15020 /* We don't output objects with Tag_MPextension_use_legacy - we
15021 move the value to Tag_MPextension_use. */
15022 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
15023 {
15024 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
15025 {
15026 _bfd_error_handler
871b3ab2 15027 (_("%pB has both the current and legacy "
b38cadfb 15028 "Tag_MPextension_use attributes"),
cd21e546
MGD		 15029 ibfd);
15030 result = FALSE;
15031 }
15032 }
15033
15034 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15035 out_attr[Tag_MPextension_use] = in_attr[i];
15036
15037 break;
15038
91e22acd 15039 case Tag_nodefaults:
2d0bb761
AS		 15040 /* This tag is set if it exists, but the value is unused (and is
15041 typically zero). We don't actually need to do anything here -
15042 the merge happens automatically when the type flags are merged
15043 below. */
91e22acd
AS		 15044 break;
15045 case Tag_also_compatible_with:
15046 /* Already done in Tag_CPU_arch. */
15047 break;
15048 case Tag_conformance:
15049 /* Keep the attribute if it matches. Throw it away otherwise.
15050 No attribute means no claim to conform. */
15051 if (!in_attr[i].s || !out_attr[i].s
15052 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15053 out_attr[i].s = NULL;
15054 break;
3cfad14c 15055
91e22acd 15056 default:
e8b36cd1
JM		 15057 result
15058 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15059 }
15060
15061 /* If out_attr was copied from in_attr then it won't have a type yet. */
15062 if (in_attr[i].type && !out_attr[i].type)
15063 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15064 }
15065
104d59d1 15066 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15067 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15068 return FALSE;
ee065d83 15069
104d59d1 15070 /* Check for any attributes not known on ARM. */
e8b36cd1 15071 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15072
91e22acd 15073 return result;
252b5132
RH		 15074}
15075
3a4a14e9
PB		 15076
15077/* Return TRUE if the two EABI versions are incompatible. */
15078
15079static bfd_boolean
15080elf32_arm_versions_compatible (unsigned iver, unsigned over)
15081{
15082 /* v4 and v5 are the same spec before and after it was released,
15083 so allow mixing them. */
15084 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15085 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15086 return TRUE;
15087
15088 return (iver == over);
15089}
15090
252b5132
RH		 15091/* Merge backend specific data from an object file to the output
15092 object file when linking. */
9b485d32 15093
b34976b6 15094static bfd_boolean
50e03d47 15095elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15096
9b485d32
NC		 15097/* Display the flags field. */
15098
b34976b6 15099static bfd_boolean
57e8b36a 15100elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15101{
fc830a83
NC		 15102 FILE * file = (FILE *) ptr;
15103 unsigned long flags;
252b5132
RH		 15104
15105 BFD_ASSERT (abfd != NULL && ptr != NULL);
15106
15107 /* Print normal ELF private data. */
15108 _bfd_elf_print_private_bfd_data (abfd, ptr);
15109
fc830a83 15110 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15111 /* Ignore init flag - it may not be set, despite the flags field
15112 containing valid data. */
252b5132 15113
9b485d32 15114 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15115
fc830a83
NC		 15116 switch (EF_ARM_EABI_VERSION (flags))
15117 {
15118 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15119 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15120 official ARM ELF extended ABI. Hence they are only decoded if
15121 the EABI version is not set. */
fd2ec330 15122 if (flags & EF_ARM_INTERWORK)
9b485d32 15123 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15124
fd2ec330 15125 if (flags & EF_ARM_APCS_26)
6c571f00 15126 fprintf (file, " [APCS-26]");
fc830a83 15127 else
6c571f00 15128 fprintf (file, " [APCS-32]");
9a5aca8c 15129
96a846ea
RE		 15130 if (flags & EF_ARM_VFP_FLOAT)
15131 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15132 else if (flags & EF_ARM_MAVERICK_FLOAT)
15133 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15134 else
15135 fprintf (file, _(" [FPA float format]"));
15136
fd2ec330 15137 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15138 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15139
fd2ec330 15140 if (flags & EF_ARM_PIC)
9b485d32 15141 fprintf (file, _(" [position independent]"));
fc830a83 15142
fd2ec330 15143 if (flags & EF_ARM_NEW_ABI)
9b485d32 15144 fprintf (file, _(" [new ABI]"));
9a5aca8c 15145
fd2ec330 15146 if (flags & EF_ARM_OLD_ABI)
9b485d32 15147 fprintf (file, _(" [old ABI]"));
9a5aca8c 15148
fd2ec330 15149 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15150 fprintf (file, _(" [software FP]"));
9a5aca8c 15151
96a846ea
RE		 15152 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15153 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15154 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15155 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15156 break;
9a5aca8c 15157
fc830a83 15158 case EF_ARM_EABI_VER1:
9b485d32 15159 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15160
fc830a83 15161 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15162 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15163 else
9b485d32 15164 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15165
fc830a83
NC		 15166 flags &= ~ EF_ARM_SYMSARESORTED;
15167 break;
9a5aca8c 15168
fd2ec330
PB		 15169 case EF_ARM_EABI_VER2:
15170 fprintf (file, _(" [Version2 EABI]"));
15171
15172 if (flags & EF_ARM_SYMSARESORTED)
15173 fprintf (file, _(" [sorted symbol table]"));
15174 else
15175 fprintf (file, _(" [unsorted symbol table]"));
15176
15177 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15178 fprintf (file, _(" [dynamic symbols use segment index]"));
15179
15180 if (flags & EF_ARM_MAPSYMSFIRST)
15181 fprintf (file, _(" [mapping symbols precede others]"));
15182
99e4ae17 15183 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15184 | EF_ARM_MAPSYMSFIRST);
15185 break;
15186
d507cf36
PB		 15187 case EF_ARM_EABI_VER3:
15188 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15189 break;
15190
15191 case EF_ARM_EABI_VER4:
15192 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15193 goto eabi;
d507cf36 15194
3a4a14e9
PB		 15195 case EF_ARM_EABI_VER5:
15196 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15197
15198 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15199 fprintf (file, _(" [soft-float ABI]"));
15200
15201 if (flags & EF_ARM_ABI_FLOAT_HARD)
15202 fprintf (file, _(" [hard-float ABI]"));
15203
15204 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15205
3a4a14e9 15206 eabi:
d507cf36
PB		 15207 if (flags & EF_ARM_BE8)
15208 fprintf (file, _(" [BE8]"));
15209
15210 if (flags & EF_ARM_LE8)
15211 fprintf (file, _(" [LE8]"));
15212
15213 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15214 break;
15215
fc830a83 15216 default:
9b485d32 15217 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15218 break;
15219 }
252b5132 15220
fc830a83 15221 flags &= ~ EF_ARM_EABIMASK;
252b5132 15222
fc830a83 15223 if (flags & EF_ARM_RELEXEC)
9b485d32 15224 fprintf (file, _(" [relocatable executable]"));
252b5132 15225
18a20338
CL		 15226 if (flags & EF_ARM_PIC)
15227 fprintf (file, _(" [position independent]"));
15228
15229 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15230 fprintf (file, _(" [FDPIC ABI supplement]"));
15231
15232 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15233
15234 if (flags)
9b485d32 15235 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15236
252b5132
RH		 15237 fputc ('\n', file);
15238
b34976b6 15239 return TRUE;
252b5132
RH		 15240}
15241
15242static int
57e8b36a 15243elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15244{
2f0ca46a
NC		 15245 switch (ELF_ST_TYPE (elf_sym->st_info))
15246 {
15247 case STT_ARM_TFUNC:
15248 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15249
2f0ca46a
NC		 15250 case STT_ARM_16BIT:
15251 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15252 This allows us to distinguish between data used by Thumb instructions
15253 and non-data (which is probably code) inside Thumb regions of an
15254 executable. */
1a0eb693 15255 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15256 return ELF_ST_TYPE (elf_sym->st_info);
15257 break;
9a5aca8c 15258
ce855c42
NC		 15259 default:
15260 break;
2f0ca46a
NC		 15261 }
15262
15263 return type;
252b5132 15264}
f21f3fe0 15265
252b5132 15266static asection *
07adf181
AM		 15267elf32_arm_gc_mark_hook (asection *sec,
15268 struct bfd_link_info *info,
15269 Elf_Internal_Rela *rel,
15270 struct elf_link_hash_entry *h,
15271 Elf_Internal_Sym *sym)
252b5132
RH		 15272{
15273 if (h != NULL)
07adf181 15274 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15275 {
15276 case R_ARM_GNU_VTINHERIT:
15277 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15278 return NULL;
15279 }
9ad5cbcf 15280
07adf181 15281 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15282}
15283
780a67af
NC		 15284/* Look through the relocs for a section during the first phase. */
15285
b34976b6 15286static bfd_boolean
57e8b36a
NC		 15287elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15288 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15289{
b34976b6
AM		 15290 Elf_Internal_Shdr *symtab_hdr;
15291 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15292 const Elf_Internal_Rela *rel;
15293 const Elf_Internal_Rela *rel_end;
15294 bfd *dynobj;
5e681ec4 15295 asection *sreloc;
5e681ec4 15296 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15297 bfd_boolean call_reloc_p;
15298 bfd_boolean may_become_dynamic_p;
15299 bfd_boolean may_need_local_target_p;
ce98a316 15300 unsigned long nsyms;
9a5aca8c 15301
0e1862bb 15302 if (bfd_link_relocatable (info))
b34976b6 15303 return TRUE;
9a5aca8c 15304
0ffa91dd
NC		 15305 BFD_ASSERT (is_arm_elf (abfd));
15306
5e681ec4 15307 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15308 if (htab == NULL)
15309 return FALSE;
15310
5e681ec4 15311 sreloc = NULL;
9a5aca8c 15312
67687978
PB		 15313 /* Create dynamic sections for relocatable executables so that we can
15314 copy relocations. */
15315 if (htab->root.is_relocatable_executable
15316 && ! htab->root.dynamic_sections_created)
15317 {
15318 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15319 return FALSE;
15320 }
15321
cbc704f3
RS		 15322 if (htab->root.dynobj == NULL)
15323 htab->root.dynobj = abfd;
34e77a92
RS		 15324 if (!create_ifunc_sections (info))
15325 return FALSE;
cbc704f3
RS		 15326
15327 dynobj = htab->root.dynobj;
15328
0ffa91dd 15329 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15330 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15331 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15332
252b5132
RH		 15333 rel_end = relocs + sec->reloc_count;
15334 for (rel = relocs; rel < rel_end; rel++)
15335 {
34e77a92 15336 Elf_Internal_Sym *isym;
252b5132 15337 struct elf_link_hash_entry *h;
b7693d02 15338 struct elf32_arm_link_hash_entry *eh;
d42c267e 15339 unsigned int r_symndx;
eb043451 15340 int r_type;
9a5aca8c 15341
252b5132 15342 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15343 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15344 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15345
ce98a316
NC		 15346 if (r_symndx >= nsyms
15347 /* PR 9934: It is possible to have relocations that do not
15348 refer to symbols, thus it is also possible to have an
15349 object file containing relocations but no symbol table. */
cf35638d 15350 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15351 {
871b3ab2 15352 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15353 r_symndx);
ba93b8ac
DJ		 15354 return FALSE;
15355 }
15356
34e77a92
RS		 15357 h = NULL;
15358 isym = NULL;
15359 if (nsyms > 0)
973a3492 15360 {
34e77a92
RS		 15361 if (r_symndx < symtab_hdr->sh_info)
15362 {
15363 /* A local symbol. */
15364 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15365 abfd, r_symndx);
15366 if (isym == NULL)
15367 return FALSE;
15368 }
15369 else
15370 {
15371 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15372 while (h->root.type == bfd_link_hash_indirect
15373 || h->root.type == bfd_link_hash_warning)
15374 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15375 }
973a3492 15376 }
9a5aca8c 15377
b7693d02
DJ		 15378 eh = (struct elf32_arm_link_hash_entry *) h;
15379
f6e32f6d
RS		 15380 call_reloc_p = FALSE;
15381 may_become_dynamic_p = FALSE;
15382 may_need_local_target_p = FALSE;
15383
0855e32b
NS		 15384 /* Could be done earlier, if h were already available. */
15385 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15386 switch (r_type)
99059e56 15387 {
e8b09b87
CL		 15388 case R_ARM_GOTOFFFUNCDESC:
15389 {
15390 if (h == NULL)
15391 {
15392 if (!elf32_arm_allocate_local_sym_info (abfd))
15393 return FALSE;
15394 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15395 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15396 }
15397 else
15398 {
15399 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15400 }
15401 }
15402 break;
15403
15404 case R_ARM_GOTFUNCDESC:
15405 {
15406 if (h == NULL)
15407 {
15408 /* Such a relocation is not supposed to be generated
15409 by gcc on a static function. */
15410 /* Anyway if needed it could be handled. */
15411 abort();
15412 }
15413 else
15414 {
15415 eh->fdpic_cnts.gotfuncdesc_cnt++;
15416 }
15417 }
15418 break;
15419
15420 case R_ARM_FUNCDESC:
15421 {
15422 if (h == NULL)
15423 {
15424 if (!elf32_arm_allocate_local_sym_info (abfd))
15425 return FALSE;
15426 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15427 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15428 }
15429 else
15430 {
15431 eh->fdpic_cnts.funcdesc_cnt++;
15432 }
15433 }
15434 break;
15435
5e681ec4 15436 case R_ARM_GOT32:
eb043451 15437 case R_ARM_GOT_PREL:
ba93b8ac 15438 case R_ARM_TLS_GD32:
5c5a4843 15439 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15440 case R_ARM_TLS_IE32:
5c5a4843 15441 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15442 case R_ARM_TLS_GOTDESC:
15443 case R_ARM_TLS_DESCSEQ:
15444 case R_ARM_THM_TLS_DESCSEQ:
15445 case R_ARM_TLS_CALL:
15446 case R_ARM_THM_TLS_CALL:
5e681ec4 15447 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15448 {
15449 int tls_type, old_tls_type;
5e681ec4 15450
ba93b8ac
DJ		 15451 switch (r_type)
15452 {
15453 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15454 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15455
ba93b8ac 15456 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15457 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15458
0855e32b
NS		 15459 case R_ARM_TLS_GOTDESC:
15460 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15461 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15462 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15463
ba93b8ac
DJ		 15464 default: tls_type = GOT_NORMAL; break;
15465 }
252b5132 15466
0e1862bb 15467 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15468 info->flags |= DF_STATIC_TLS;
15469
ba93b8ac
DJ		 15470 if (h != NULL)
15471 {
15472 h->got.refcount++;
15473 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15474 }
15475 else
15476 {
ba93b8ac 15477 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15478 if (!elf32_arm_allocate_local_sym_info (abfd))
15479 return FALSE;
15480 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15481 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15482 }
15483
0855e32b 15484 /* If a variable is accessed with both tls methods, two
99059e56 15485 slots may be created. */
0855e32b
NS		 15486 if (GOT_TLS_GD_ANY_P (old_tls_type)
15487 && GOT_TLS_GD_ANY_P (tls_type))
15488 tls_type |= old_tls_type;
15489
15490 /* We will already have issued an error message if there
15491 is a TLS/non-TLS mismatch, based on the symbol
15492 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15493 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15494 && tls_type != GOT_NORMAL)
15495 tls_type |= old_tls_type;
15496
0855e32b 15497 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15498 method, we're able to relax. Turn off the GDESC flag,
15499 without messing up with any other kind of tls types
6a631e86 15500 that may be involved. */
0855e32b
NS		 15501 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15502 tls_type &= ~GOT_TLS_GDESC;
15503
ba93b8ac
DJ		 15504 if (old_tls_type != tls_type)
15505 {
15506 if (h != NULL)
15507 elf32_arm_hash_entry (h)->tls_type = tls_type;
15508 else
15509 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15510 }
15511 }
8029a119 15512 /* Fall through. */
ba93b8ac
DJ		 15513
15514 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15515 case R_ARM_TLS_LDM32_FDPIC:
15516 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15517 htab->tls_ldm_got.refcount++;
8029a119 15518 /* Fall through. */
252b5132 15519
c19d1205 15520 case R_ARM_GOTOFF32:
5e681ec4 15521 case R_ARM_GOTPC:
cbc704f3
RS		 15522 if (htab->root.sgot == NULL
15523 && !create_got_section (htab->root.dynobj, info))
15524 return FALSE;
252b5132
RH		 15525 break;
15526
252b5132 15527 case R_ARM_PC24:
7359ea65 15528 case R_ARM_PLT32:
5b5bb741
PB		 15529 case R_ARM_CALL:
15530 case R_ARM_JUMP24:
eb043451 15531 case R_ARM_PREL31:
c19d1205 15532 case R_ARM_THM_CALL:
bd97cb95
DJ		 15533 case R_ARM_THM_JUMP24:
15534 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15535 call_reloc_p = TRUE;
15536 may_need_local_target_p = TRUE;
15537 break;
15538
15539 case R_ARM_ABS12:
15540 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15541 ldr __GOTT_INDEX__ offsets. */
15542 if (!htab->vxworks_p)
15543 {
15544 may_need_local_target_p = TRUE;
15545 break;
15546 }
aebf9be7 15547 else goto jump_over;
9eaff861 15548
f6e32f6d 15549 /* Fall through. */
39623e12 15550
96c23d59
JM		 15551 case R_ARM_MOVW_ABS_NC:
15552 case R_ARM_MOVT_ABS:
15553 case R_ARM_THM_MOVW_ABS_NC:
15554 case R_ARM_THM_MOVT_ABS:
0e1862bb 15555 if (bfd_link_pic (info))
96c23d59 15556 {
4eca0228 15557 _bfd_error_handler
871b3ab2 15558 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15559 abfd, elf32_arm_howto_table_1[r_type].name,
15560 (h) ? h->root.root.string : "a local symbol");
15561 bfd_set_error (bfd_error_bad_value);
15562 return FALSE;
15563 }
15564
15565 /* Fall through. */
39623e12
PB		 15566 case R_ARM_ABS32:
15567 case R_ARM_ABS32_NOI:
aebf9be7 15568 jump_over:
0e1862bb 15569 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15570 {
15571 h->pointer_equality_needed = 1;
15572 }
15573 /* Fall through. */
39623e12
PB		 15574 case R_ARM_REL32:
15575 case R_ARM_REL32_NOI:
b6895b4f
PB		 15576 case R_ARM_MOVW_PREL_NC:
15577 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15578 case R_ARM_THM_MOVW_PREL_NC:
15579 case R_ARM_THM_MOVT_PREL:
39623e12 15580
b7693d02 15581 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15582 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15583 || htab->fdpic_p)
34e77a92
RS		 15584 && (sec->flags & SEC_ALLOC) != 0)
15585 {
15586 if (h == NULL
469a3493 15587 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15588 {
15589 /* In shared libraries and relocatable executables,
15590 we treat local relative references as calls;
15591 see the related SYMBOL_CALLS_LOCAL code in
15592 allocate_dynrelocs. */
15593 call_reloc_p = TRUE;
15594 may_need_local_target_p = TRUE;
15595 }
15596 else
15597 /* We are creating a shared library or relocatable
15598 executable, and this is a reloc against a global symbol,
15599 or a non-PC-relative reloc against a local symbol.
15600 We may need to copy the reloc into the output. */
15601 may_become_dynamic_p = TRUE;
15602 }
f6e32f6d
RS		 15603 else
15604 may_need_local_target_p = TRUE;
252b5132
RH		 15605 break;
15606
99059e56
RM		 15607 /* This relocation describes the C++ object vtable hierarchy.
15608 Reconstruct it for later use during GC. */
15609 case R_ARM_GNU_VTINHERIT:
15610 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15611 return FALSE;
15612 break;
15613
15614 /* This relocation describes which C++ vtable entries are actually
15615 used. Record for later use during GC. */
15616 case R_ARM_GNU_VTENTRY:
a0ea3a14 15617 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15618 return FALSE;
15619 break;
15620 }
f6e32f6d
RS		 15621
15622 if (h != NULL)
15623 {
15624 if (call_reloc_p)
15625 /* We may need a .plt entry if the function this reloc
15626 refers to is in a different object, regardless of the
15627 symbol's type. We can't tell for sure yet, because
15628 something later might force the symbol local. */
15629 h->needs_plt = 1;
15630 else if (may_need_local_target_p)
15631 /* If this reloc is in a read-only section, we might
15632 need a copy reloc. We can't check reliably at this
15633 stage whether the section is read-only, as input
15634 sections have not yet been mapped to output sections.
15635 Tentatively set the flag for now, and correct in
15636 adjust_dynamic_symbol. */
15637 h->non_got_ref = 1;
15638 }
15639
34e77a92
RS		 15640 if (may_need_local_target_p
15641 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15642 {
34e77a92
RS		 15643 union gotplt_union *root_plt;
15644 struct arm_plt_info *arm_plt;
15645 struct arm_local_iplt_info *local_iplt;
15646
15647 if (h != NULL)
15648 {
15649 root_plt = &h->plt;
15650 arm_plt = &eh->plt;
15651 }
15652 else
15653 {
15654 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15655 if (local_iplt == NULL)
15656 return FALSE;
15657 root_plt = &local_iplt->root;
15658 arm_plt = &local_iplt->arm;
15659 }
15660
f6e32f6d
RS		 15661 /* If the symbol is a function that doesn't bind locally,
15662 this relocation will need a PLT entry. */
a8c887dd
NC		 15663 if (root_plt->refcount != -1)
15664 root_plt->refcount += 1;
34e77a92
RS		 15665
15666 if (!call_reloc_p)
15667 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15668
15669 /* It's too early to use htab->use_blx here, so we have to
15670 record possible blx references separately from
15671 relocs that definitely need a thumb stub. */
15672
15673 if (r_type == R_ARM_THM_CALL)
34e77a92 15674 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15675
15676 if (r_type == R_ARM_THM_JUMP24
15677 || r_type == R_ARM_THM_JUMP19)
34e77a92 15678 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15679 }
15680
15681 if (may_become_dynamic_p)
15682 {
15683 struct elf_dyn_relocs *p, **head;
15684
15685 /* Create a reloc section in dynobj. */
15686 if (sreloc == NULL)
15687 {
15688 sreloc = _bfd_elf_make_dynamic_reloc_section
15689 (sec, dynobj, 2, abfd, ! htab->use_rel);
15690
15691 if (sreloc == NULL)
15692 return FALSE;
15693
15694 /* BPABI objects never have dynamic relocations mapped. */
15695 if (htab->symbian_p)
15696 {
15697 flagword flags;
15698
15699 flags = bfd_get_section_flags (dynobj, sreloc);
15700 flags &= ~(SEC_LOAD | SEC_ALLOC);
15701 bfd_set_section_flags (dynobj, sreloc, flags);
15702 }
15703 }
15704
15705 /* If this is a global symbol, count the number of
15706 relocations we need for this symbol. */
15707 if (h != NULL)
15708 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15709 else
15710 {
34e77a92
RS		 15711 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15712 if (head == NULL)
f6e32f6d 15713 return FALSE;
f6e32f6d
RS		 15714 }
15715
15716 p = *head;
15717 if (p == NULL || p->sec != sec)
15718 {
15719 bfd_size_type amt = sizeof *p;
15720
15721 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15722 if (p == NULL)
15723 return FALSE;
15724 p->next = *head;
15725 *head = p;
15726 p->sec = sec;
15727 p->count = 0;
15728 p->pc_count = 0;
15729 }
15730
469a3493 15731 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15732 p->pc_count += 1;
15733 p->count += 1;
e8b09b87
CL		 15734 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15735 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15736 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15737 that will become rofixup. */
15738 /* This is due to the fact that we suppose all will become rofixup. */
15739 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15740 _bfd_error_handler
15741 (_("FDPIC does not yet support %s relocation"
15742 " to become dynamic for executable"),
15743 elf32_arm_howto_table_1[r_type].name);
15744 abort();
15745 }
f6e32f6d 15746 }
252b5132 15747 }
f21f3fe0 15748
b34976b6 15749 return TRUE;
252b5132
RH		 15750}
15751
9eaff861
AO		 15752static void
15753elf32_arm_update_relocs (asection *o,
15754 struct bfd_elf_section_reloc_data *reldata)
15755{
15756 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15757 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15758 const struct elf_backend_data *bed;
15759 _arm_elf_section_data *eado;
15760 struct bfd_link_order *p;
15761 bfd_byte *erela_head, *erela;
15762 Elf_Internal_Rela *irela_head, *irela;
15763 Elf_Internal_Shdr *rel_hdr;
15764 bfd *abfd;
15765 unsigned int count;
15766
15767 eado = get_arm_elf_section_data (o);
15768
15769 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15770 return;
15771
15772 abfd = o->owner;
15773 bed = get_elf_backend_data (abfd);
15774 rel_hdr = reldata->hdr;
15775
15776 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15777 {
15778 swap_in = bed->s->swap_reloc_in;
15779 swap_out = bed->s->swap_reloc_out;
15780 }
15781 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15782 {
15783 swap_in = bed->s->swap_reloca_in;
15784 swap_out = bed->s->swap_reloca_out;
15785 }
15786 else
15787 abort ();
15788
15789 erela_head = rel_hdr->contents;
15790 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15791 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15792
15793 erela = erela_head;
15794 irela = irela_head;
15795 count = 0;
15796
15797 for (p = o->map_head.link_order; p; p = p->next)
15798 {
15799 if (p->type == bfd_section_reloc_link_order
15800 || p->type == bfd_symbol_reloc_link_order)
15801 {
15802 (*swap_in) (abfd, erela, irela);
15803 erela += rel_hdr->sh_entsize;
15804 irela++;
15805 count++;
15806 }
15807 else if (p->type == bfd_indirect_link_order)
15808 {
15809 struct bfd_elf_section_reloc_data *input_reldata;
15810 arm_unwind_table_edit *edit_list, *edit_tail;
15811 _arm_elf_section_data *eadi;
15812 bfd_size_type j;
15813 bfd_vma offset;
15814 asection *i;
15815
15816 i = p->u.indirect.section;
15817
15818 eadi = get_arm_elf_section_data (i);
15819 edit_list = eadi->u.exidx.unwind_edit_list;
15820 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15821 offset = i->output_offset;
9eaff861
AO		 15822
15823 if (eadi->elf.rel.hdr &&
15824 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15825 input_reldata = &eadi->elf.rel;
15826 else if (eadi->elf.rela.hdr &&
15827 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15828 input_reldata = &eadi->elf.rela;
15829 else
15830 abort ();
15831
15832 if (edit_list)
15833 {
15834 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15835 {
15836 arm_unwind_table_edit *edit_node, *edit_next;
15837 bfd_vma bias;
c48182bf 15838 bfd_vma reloc_index;
9eaff861
AO		 15839
15840 (*swap_in) (abfd, erela, irela);
c48182bf 15841 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15842
15843 bias = 0;
15844 edit_node = edit_list;
15845 for (edit_next = edit_list;
c48182bf 15846 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15847 edit_next = edit_node->next)
15848 {
15849 bias++;
15850 edit_node = edit_next;
15851 }
15852
15853 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15854 || edit_node->index != reloc_index)
9eaff861
AO		 15855 {
15856 irela->r_offset -= bias * 8;
15857 irela++;
15858 count++;
15859 }
15860
15861 erela += rel_hdr->sh_entsize;
15862 }
15863
15864 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15865 {
15866 /* New relocation entity. */
15867 asection *text_sec = edit_tail->linked_section;
15868 asection *text_out = text_sec->output_section;
15869 bfd_vma exidx_offset = offset + i->size - 8;
15870
15871 irela->r_addend = 0;
15872 irela->r_offset = exidx_offset;
15873 irela->r_info = ELF32_R_INFO
15874 (text_out->target_index, R_ARM_PREL31);
15875 irela++;
15876 count++;
15877 }
15878 }
15879 else
15880 {
15881 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15882 {
15883 (*swap_in) (abfd, erela, irela);
15884 erela += rel_hdr->sh_entsize;
15885 irela++;
15886 }
15887
15888 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15889 }
15890 }
15891 }
15892
15893 reldata->count = count;
15894 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15895
15896 erela = erela_head;
15897 irela = irela_head;
15898 while (count > 0)
15899 {
15900 (*swap_out) (abfd, irela, erela);
15901 erela += rel_hdr->sh_entsize;
15902 irela++;
15903 count--;
15904 }
15905
15906 free (irela_head);
15907
15908 /* Hashes are no longer valid. */
15909 free (reldata->hashes);
15910 reldata->hashes = NULL;
15911}
15912
6a5bb875 15913/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15914 required if the corresponding code section is marked. Similarly, ARMv8-M
15915 secure entry functions can only be referenced by SG veneers which are
15916 created after the GC process. They need to be marked in case they reside in
15917 their own section (as would be the case if code was compiled with
15918 -ffunction-sections). */
6a5bb875
PB		 15919
15920static bfd_boolean
906e58ca
NC		 15921elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15922 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15923{
15924 bfd *sub;
15925 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15926 asection *cmse_sec;
15927 obj_attribute *out_attr;
15928 Elf_Internal_Shdr *symtab_hdr;
15929 unsigned i, sym_count, ext_start;
15930 const struct elf_backend_data *bed;
15931 struct elf_link_hash_entry **sym_hashes;
15932 struct elf32_arm_link_hash_entry *cmse_hash;
15933 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15934 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15935 asection *isec;
6a5bb875 15936
7f6ab9f8
AM		 15937 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15938
4ba2ef8f
TP		 15939 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15940 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15941 && out_attr[Tag_CPU_arch_profile].i == 'M';
15942
6a5bb875
PB		 15943 /* Marking EH data may cause additional code sections to be marked,
15944 requiring multiple passes. */
15945 again = TRUE;
15946 while (again)
15947 {
15948 again = FALSE;
c72f2fb2 15949 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15950 {
15951 asection *o;
15952
0ffa91dd 15953 if (! is_arm_elf (sub))
6a5bb875
PB		 15954 continue;
15955
15956 elf_shdrp = elf_elfsections (sub);
15957 for (o = sub->sections; o != NULL; o = o->next)
15958 {
15959 Elf_Internal_Shdr *hdr;
0ffa91dd 15960
6a5bb875 15961 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15962 if (hdr->sh_type == SHT_ARM_EXIDX
15963 && hdr->sh_link
15964 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15965 && !o->gc_mark
15966 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15967 {
15968 again = TRUE;
15969 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15970 return FALSE;
15971 }
15972 }
4ba2ef8f
TP		 15973
15974 /* Mark section holding ARMv8-M secure entry functions. We mark all
15975 of them so no need for a second browsing. */
15976 if (is_v8m && first_bfd_browse)
15977 {
15978 sym_hashes = elf_sym_hashes (sub);
15979 bed = get_elf_backend_data (sub);
15980 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15981 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15982 ext_start = symtab_hdr->sh_info;
15983
15984 /* Scan symbols. */
15985 for (i = ext_start; i < sym_count; i++)
15986 {
15987 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15988
15989 /* Assume it is a special symbol. If not, cmse_scan will
15990 warn about it and user can do something about it. */
baf46cd7
AM		 15991 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
15992 CMSE_PREFIX))
4ba2ef8f
TP		 15993 {
15994 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15995 if (!cmse_sec->gc_mark
15996 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 15997 return FALSE;
bb32413f
SP		 15998 /* The debug sections related to these secure entry
15999 functions are marked on enabling below flag. */
16000 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 16001 }
16002 }
bb32413f
SP		 16003
16004 if (debug_sec_need_to_be_marked)
16005 {
16006 /* Looping over all the sections of the object file containing
16007 Armv8-M secure entry functions and marking all the debug
16008 sections. */
16009 for (isec = sub->sections; isec != NULL; isec = isec->next)
16010 {
16011 /* If not a debug sections, skip it. */
16012 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
16013 isec->gc_mark = 1 ;
16014 }
16015 debug_sec_need_to_be_marked = FALSE;
16016 }
4ba2ef8f 16017 }
6a5bb875 16018 }
4ba2ef8f 16019 first_bfd_browse = FALSE;
6a5bb875
PB		 16020 }
16021
16022 return TRUE;
16023}
16024
3c9458e9
NC		 16025/* Treat mapping symbols as special target symbols. */
16026
16027static bfd_boolean
16028elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
16029{
b0796911
PB		 16030 return bfd_is_arm_special_symbol_name (sym->name,
16031 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 16032}
16033
62e0492f 16034/* This is a version of _bfd_elf_find_function() from dwarf2.c except that
0367ecfb
NC		 16035 ARM mapping symbols are ignored when looking for function names
16036 and STT_ARM_TFUNC is considered to a function type. */
252b5132 16037
0367ecfb 16038static bfd_boolean
62e0492f 16039arm_elf_find_function (bfd * abfd,
0367ecfb 16040 asymbol ** symbols,
fb167eb2 16041 asection * section,
07d6d2b8 16042 bfd_vma offset,
0367ecfb
NC		 16043 const char ** filename_ptr,
16044 const char ** functionname_ptr)
16045{
16046 const char * filename = NULL;
16047 asymbol * func = NULL;
16048 bfd_vma low_func = 0;
16049 asymbol ** p;
252b5132 16050
62e0492f
AL		 16051 if (symbols == NULL)
16052 return FALSE;
16053
16054 if (bfd_get_flavour (abfd) != bfd_target_elf_flavour)
16055 return FALSE;
16056
252b5132
RH		 16057 for (p = symbols; *p != NULL; p++)
16058 {
16059 elf_symbol_type *q;
16060
16061 q = (elf_symbol_type *) *p;
16062
252b5132
RH		 16063 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
16064 {
16065 default:
16066 break;
16067 case STT_FILE:
16068 filename = bfd_asymbol_name (&q->symbol);
16069 break;
252b5132
RH		 16070 case STT_FUNC:
16071 case STT_ARM_TFUNC:
9d2da7ca 16072 case STT_NOTYPE:
b0796911 16073 /* Skip mapping symbols. */
0367ecfb 16074 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 16075 && bfd_is_arm_special_symbol_name (q->symbol.name,
16076 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 16077 continue;
16078 /* Fall through. */
e6f7f6d1 16079 if (bfd_asymbol_section (&q->symbol) == section
252b5132
RH		 16080 && q->symbol.value >= low_func
16081 && q->symbol.value <= offset)
16082 {
16083 func = (asymbol *) q;
16084 low_func = q->symbol.value;
16085 }
16086 break;
16087 }
16088 }
16089
16090 if (func == NULL)
b34976b6 16091 return FALSE;
252b5132 16092
0367ecfb
NC		 16093 if (filename_ptr)
16094 *filename_ptr = filename;
16095 if (functionname_ptr)
16096 *functionname_ptr = bfd_asymbol_name (func);
16097
16098 return TRUE;
906e58ca 16099}
0367ecfb
NC		 16100
16101
16102/* Find the nearest line to a particular section and offset, for error
16103 reporting. This code is a duplicate of the code in elf.c, except
16104 that it uses arm_elf_find_function. */
16105
16106static bfd_boolean
07d6d2b8
AM		 16107elf32_arm_find_nearest_line (bfd * abfd,
16108 asymbol ** symbols,
16109 asection * section,
16110 bfd_vma offset,
0367ecfb
NC		 16111 const char ** filename_ptr,
16112 const char ** functionname_ptr,
fb167eb2
AM		 16113 unsigned int * line_ptr,
16114 unsigned int * discriminator_ptr)
0367ecfb
NC		 16115{
16116 bfd_boolean found = FALSE;
16117
fb167eb2 16118 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 16119 filename_ptr, functionname_ptr,
fb167eb2 16120 line_ptr, discriminator_ptr,
9defd221 16121 dwarf_debug_sections,
0367ecfb
NC		 16122 & elf_tdata (abfd)->dwarf2_find_line_info))
16123 {
16124 if (!*functionname_ptr)
fb167eb2 16125 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16126 *filename_ptr ? NULL : filename_ptr,
16127 functionname_ptr);
f21f3fe0 16128
0367ecfb
NC		 16129 return TRUE;
16130 }
16131
fb167eb2
AM		 16132 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
16133 uses DWARF1. */
16134
0367ecfb
NC		 16135 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
16136 & found, filename_ptr,
16137 functionname_ptr, line_ptr,
16138 & elf_tdata (abfd)->line_info))
16139 return FALSE;
16140
16141 if (found && (*functionname_ptr || *line_ptr))
16142 return TRUE;
16143
16144 if (symbols == NULL)
16145 return FALSE;
16146
fb167eb2 16147 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16148 filename_ptr, functionname_ptr))
16149 return FALSE;
16150
16151 *line_ptr = 0;
b34976b6 16152 return TRUE;
252b5132
RH		 16153}
16154
4ab527b0 16155static bfd_boolean
07d6d2b8 16156elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16157 const char ** filename_ptr,
16158 const char ** functionname_ptr,
16159 unsigned int * line_ptr)
16160{
16161 bfd_boolean found;
16162 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16163 functionname_ptr, line_ptr,
16164 & elf_tdata (abfd)->dwarf2_find_line_info);
16165 return found;
16166}
16167
63c1f59d
AM		 16168/* Find dynamic relocs for H that apply to read-only sections. */
16169
16170static asection *
16171readonly_dynrelocs (struct elf_link_hash_entry *h)
16172{
16173 struct elf_dyn_relocs *p;
16174
16175 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
16176 {
16177 asection *s = p->sec->output_section;
16178
16179 if (s != NULL && (s->flags & SEC_READONLY) != 0)
16180 return p->sec;
16181 }
16182 return NULL;
16183}
16184
252b5132
RH		 16185/* Adjust a symbol defined by a dynamic object and referenced by a
16186 regular object. The current definition is in some section of the
16187 dynamic object, but we're not including those sections. We have to
16188 change the definition to something the rest of the link can
16189 understand. */
16190
b34976b6 16191static bfd_boolean
57e8b36a
NC		 16192elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16193 struct elf_link_hash_entry * h)
252b5132
RH		 16194{
16195 bfd * dynobj;
5474d94f 16196 asection *s, *srel;
b7693d02 16197 struct elf32_arm_link_hash_entry * eh;
67687978 16198 struct elf32_arm_link_hash_table *globals;
252b5132 16199
67687978 16200 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16201 if (globals == NULL)
16202 return FALSE;
16203
252b5132
RH		 16204 dynobj = elf_hash_table (info)->dynobj;
16205
16206 /* Make sure we know what is going on here. */
16207 BFD_ASSERT (dynobj != NULL
f5385ebf 16208 && (h->needs_plt
34e77a92 16209 || h->type == STT_GNU_IFUNC
60d67dc8 16210 || h->is_weakalias
f5385ebf
AM		 16211 || (h->def_dynamic
16212 && h->ref_regular
16213 && !h->def_regular)));
252b5132 16214
b7693d02
DJ		 16215 eh = (struct elf32_arm_link_hash_entry *) h;
16216
252b5132
RH		 16217 /* If this is a function, put it in the procedure linkage table. We
16218 will fill in the contents of the procedure linkage table later,
16219 when we know the address of the .got section. */
34e77a92 16220 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16221 {
34e77a92
RS		 16222 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16223 symbol binds locally. */
5e681ec4 16224 if (h->plt.refcount <= 0
34e77a92
RS		 16225 || (h->type != STT_GNU_IFUNC
16226 && (SYMBOL_CALLS_LOCAL (info, h)
16227 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16228 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16229 {
16230 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16231 file, but the symbol was never referred to by a dynamic
16232 object, or if all references were garbage collected. In
16233 such a case, we don't actually need to build a procedure
16234 linkage table, and we can just do a PC24 reloc instead. */
16235 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16236 eh->plt.thumb_refcount = 0;
16237 eh->plt.maybe_thumb_refcount = 0;
16238 eh->plt.noncall_refcount = 0;
f5385ebf 16239 h->needs_plt = 0;
252b5132
RH		 16240 }
16241
b34976b6 16242 return TRUE;
252b5132 16243 }
5e681ec4 16244 else
b7693d02
DJ		 16245 {
16246 /* It's possible that we incorrectly decided a .plt reloc was
16247 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16248 in check_relocs. We can't decide accurately between function
16249 and non-function syms in check-relocs; Objects loaded later in
16250 the link may change h->type. So fix it now. */
16251 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16252 eh->plt.thumb_refcount = 0;
16253 eh->plt.maybe_thumb_refcount = 0;
16254 eh->plt.noncall_refcount = 0;
b7693d02 16255 }
252b5132
RH		 16256
16257 /* If this is a weak symbol, and there is a real definition, the
16258 processor independent code will have arranged for us to see the
16259 real definition first, and we can just use the same value. */
60d67dc8 16260 if (h->is_weakalias)
252b5132 16261 {
60d67dc8
AM		 16262 struct elf_link_hash_entry *def = weakdef (h);
16263 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16264 h->root.u.def.section = def->root.u.def.section;
16265 h->root.u.def.value = def->root.u.def.value;
b34976b6 16266 return TRUE;
252b5132
RH		 16267 }
16268
ba93b8ac
DJ		 16269 /* If there are no non-GOT references, we do not need a copy
16270 relocation. */
16271 if (!h->non_got_ref)
16272 return TRUE;
16273
252b5132
RH		 16274 /* This is a reference to a symbol defined by a dynamic object which
16275 is not a function. */
16276
16277 /* If we are creating a shared library, we must presume that the
16278 only references to the symbol are via the global offset table.
16279 For such cases we need not do anything here; the relocations will
67687978
PB		 16280 be handled correctly by relocate_section. Relocatable executables
16281 can reference data in shared objects directly, so we don't need to
16282 do anything here. */
0e1862bb 16283 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16284 return TRUE;
252b5132
RH		 16285
16286 /* We must allocate the symbol in our .dynbss section, which will
16287 become part of the .bss section of the executable. There will be
16288 an entry for this symbol in the .dynsym section. The dynamic
16289 object will contain position independent code, so all references
16290 from the dynamic object to this symbol will go through the global
16291 offset table. The dynamic linker will use the .dynsym entry to
16292 determine the address it must put in the global offset table, so
16293 both the dynamic object and the regular object will refer to the
16294 same memory location for the variable. */
5522f910
NC		 16295 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16296 linker to copy the initial value out of the dynamic object and into
16297 the runtime process image. We need to remember the offset into the
00a97672 16298 .rel(a).bss section we are going to use. */
5474d94f
AM		 16299 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16300 {
16301 s = globals->root.sdynrelro;
16302 srel = globals->root.sreldynrelro;
16303 }
16304 else
16305 {
16306 s = globals->root.sdynbss;
16307 srel = globals->root.srelbss;
16308 }
5522f910
NC		 16309 if (info->nocopyreloc == 0
16310 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16311 && h->size != 0)
252b5132 16312 {
47beaa6a 16313 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16314 h->needs_copy = 1;
252b5132
RH		 16315 }
16316
6cabe1ea 16317 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16318}
16319
5e681ec4
PB		 16320/* Allocate space in .plt, .got and associated reloc sections for
16321 dynamic relocs. */
16322
16323static bfd_boolean
47beaa6a 16324allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16325{
16326 struct bfd_link_info *info;
16327 struct elf32_arm_link_hash_table *htab;
16328 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16329 struct elf_dyn_relocs *p;
5e681ec4
PB		 16330
16331 if (h->root.type == bfd_link_hash_indirect)
16332 return TRUE;
16333
e6a6bb22
AM		 16334 eh = (struct elf32_arm_link_hash_entry *) h;
16335
5e681ec4
PB		 16336 info = (struct bfd_link_info *) inf;
16337 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16338 if (htab == NULL)
16339 return FALSE;
5e681ec4 16340
34e77a92 16341 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16342 && h->plt.refcount > 0)
16343 {
16344 /* Make sure this symbol is output as a dynamic symbol.
16345 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16346 if (h->dynindx == -1 && !h->forced_local
16347 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16348 {
c152c796 16349 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16350 return FALSE;
16351 }
16352
34e77a92
RS		 16353 /* If the call in the PLT entry binds locally, the associated
16354 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16355 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16356 than the .plt section. */
16357 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16358 {
16359 eh->is_iplt = 1;
16360 if (eh->plt.noncall_refcount == 0
16361 && SYMBOL_REFERENCES_LOCAL (info, h))
16362 /* All non-call references can be resolved directly.
16363 This means that they can (and in some cases, must)
16364 resolve directly to the run-time target, rather than
16365 to the PLT. That in turns means that any .got entry
16366 would be equal to the .igot.plt entry, so there's
16367 no point having both. */
16368 h->got.refcount = 0;
16369 }
16370
0e1862bb 16371 if (bfd_link_pic (info)
34e77a92 16372 || eh->is_iplt
7359ea65 16373 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16374 {
34e77a92 16375 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16376
5e681ec4
PB		 16377 /* If this symbol is not defined in a regular file, and we are
16378 not generating a shared library, then set the symbol to this
16379 location in the .plt. This is required to make function
16380 pointers compare as equal between the normal executable and
16381 the shared library. */
0e1862bb 16382 if (! bfd_link_pic (info)
f5385ebf 16383 && !h->def_regular)
5e681ec4 16384 {
34e77a92 16385 h->root.u.def.section = htab->root.splt;
5e681ec4 16386 h->root.u.def.value = h->plt.offset;
5e681ec4 16387
67d74e43
DJ		 16388 /* Make sure the function is not marked as Thumb, in case
16389 it is the target of an ABS32 relocation, which will
16390 point to the PLT entry. */
39d911fc 16391 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16392 }
022f8312 16393
00a97672
RS		 16394 /* VxWorks executables have a second set of relocations for
16395 each PLT entry. They go in a separate relocation section,
16396 which is processed by the kernel loader. */
0e1862bb 16397 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16398 {
16399 /* There is a relocation for the initial PLT entry:
16400 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16401 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16402 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16403
16404 /* There are two extra relocations for each subsequent
16405 PLT entry: an R_ARM_32 relocation for the GOT entry,
16406 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16407 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16408 }
5e681ec4
PB		 16409 }
16410 else
16411 {
16412 h->plt.offset = (bfd_vma) -1;
f5385ebf 16413 h->needs_plt = 0;
5e681ec4
PB		 16414 }
16415 }
16416 else
16417 {
16418 h->plt.offset = (bfd_vma) -1;
f5385ebf 16419 h->needs_plt = 0;
5e681ec4
PB		 16420 }
16421
0855e32b
NS		 16422 eh = (struct elf32_arm_link_hash_entry *) h;
16423 eh->tlsdesc_got = (bfd_vma) -1;
16424
5e681ec4
PB		 16425 if (h->got.refcount > 0)
16426 {
16427 asection *s;
16428 bfd_boolean dyn;
ba93b8ac
DJ		 16429 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16430 int indx;
5e681ec4
PB		 16431
16432 /* Make sure this symbol is output as a dynamic symbol.
16433 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16434 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16435 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16436 {
c152c796 16437 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16438 return FALSE;
16439 }
16440
e5a52504
MM		 16441 if (!htab->symbian_p)
16442 {
362d30a1 16443 s = htab->root.sgot;
e5a52504 16444 h->got.offset = s->size;
ba93b8ac
DJ		 16445
16446 if (tls_type == GOT_UNKNOWN)
16447 abort ();
16448
16449 if (tls_type == GOT_NORMAL)
16450 /* Non-TLS symbols need one GOT slot. */
16451 s->size += 4;
16452 else
16453 {
99059e56
RM		 16454 if (tls_type & GOT_TLS_GDESC)
16455 {
0855e32b 16456 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16457 eh->tlsdesc_got
0855e32b
NS		 16458 = (htab->root.sgotplt->size
16459 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16460 htab->root.sgotplt->size += 8;
16461 h->got.offset = (bfd_vma) -2;
34e77a92 16462 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16463 reloc in the middle of .got.plt. */
99059e56
RM		 16464 htab->num_tls_desc++;
16465 }
0855e32b 16466
ba93b8ac 16467 if (tls_type & GOT_TLS_GD)
0855e32b 16468 {
5c5a4843
CL		 16469 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16470 consecutive GOT slots. If the symbol is both GD
16471 and GDESC, got.offset may have been
16472 overwritten. */
0855e32b
NS		 16473 h->got.offset = s->size;
16474 s->size += 8;
16475 }
16476
ba93b8ac 16477 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16478 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16479 slot. */
ba93b8ac
DJ		 16480 s->size += 4;
16481 }
16482
e5a52504 16483 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16484
16485 indx = 0;
0e1862bb
L		 16486 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16487 bfd_link_pic (info),
16488 h)
16489 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16490 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16491 indx = h->dynindx;
16492
16493 if (tls_type != GOT_NORMAL
0e1862bb 16494 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 16495 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16496 || h->root.type != bfd_link_hash_undefweak))
16497 {
16498 if (tls_type & GOT_TLS_IE)
47beaa6a 16499 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16500
16501 if (tls_type & GOT_TLS_GD)
47beaa6a 16502 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16503
b38cadfb 16504 if (tls_type & GOT_TLS_GDESC)
0855e32b 16505 {
47beaa6a 16506 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16507 /* GDESC needs a trampoline to jump to. */
16508 htab->tls_trampoline = -1;
16509 }
16510
16511 /* Only GD needs it. GDESC just emits one relocation per
16512 2 entries. */
b38cadfb 16513 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16514 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16515 }
e8b09b87
CL		 16516 else if (((indx != -1) || htab->fdpic_p)
16517 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16518 {
16519 if (htab->root.dynamic_sections_created)
16520 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16521 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16522 }
34e77a92
RS		 16523 else if (h->type == STT_GNU_IFUNC
16524 && eh->plt.noncall_refcount == 0)
16525 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16526 they all resolve dynamically instead. Reserve room for the
16527 GOT entry's R_ARM_IRELATIVE relocation. */
16528 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 16529 else if (bfd_link_pic (info)
16530 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16531 || h->root.type != bfd_link_hash_undefweak))
b436d854 16532 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16533 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16534 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16535 /* Reserve room for rofixup for FDPIC executable. */
16536 /* TLS relocs do not need space since they are completely
16537 resolved. */
16538 htab->srofixup->size += 4;
e5a52504 16539 }
5e681ec4
PB		 16540 }
16541 else
16542 h->got.offset = (bfd_vma) -1;
16543
e8b09b87
CL		 16544 /* FDPIC support. */
16545 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16546 {
16547 /* Symbol musn't be exported. */
16548 if (h->dynindx != -1)
16549 abort();
16550
16551 /* We only allocate one function descriptor with its associated relocation. */
16552 if (eh->fdpic_cnts.funcdesc_offset == -1)
16553 {
16554 asection *s = htab->root.sgot;
16555
16556 eh->fdpic_cnts.funcdesc_offset = s->size;
16557 s->size += 8;
16558 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16559 if (bfd_link_pic(info))
16560 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16561 else
16562 htab->srofixup->size += 8;
16563 }
16564 }
16565
16566 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16567 {
16568 asection *s = htab->root.sgot;
16569
16570 if (htab->root.dynamic_sections_created && h->dynindx == -1
16571 && !h->forced_local)
16572 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16573 return FALSE;
16574
16575 if (h->dynindx == -1)
16576 {
16577 /* We only allocate one function descriptor with its associated relocation. q */
16578 if (eh->fdpic_cnts.funcdesc_offset == -1)
16579 {
16580
16581 eh->fdpic_cnts.funcdesc_offset = s->size;
16582 s->size += 8;
16583 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16584 if (bfd_link_pic(info))
16585 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16586 else
16587 htab->srofixup->size += 8;
16588 }
16589 }
16590
16591 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16592 R_ARM_RELATIVE/rofixup relocation on it. */
16593 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16594 s->size += 4;
16595 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16596 htab->srofixup->size += 4;
e8b09b87 16597 else
4b24dd1a 16598 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16599 }
16600
16601 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16602 {
16603 if (htab->root.dynamic_sections_created && h->dynindx == -1
16604 && !h->forced_local)
16605 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16606 return FALSE;
16607
16608 if (h->dynindx == -1)
16609 {
16610 /* We only allocate one function descriptor with its associated relocation. */
16611 if (eh->fdpic_cnts.funcdesc_offset == -1)
16612 {
16613 asection *s = htab->root.sgot;
16614
16615 eh->fdpic_cnts.funcdesc_offset = s->size;
16616 s->size += 8;
16617 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16618 if (bfd_link_pic(info))
16619 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16620 else
16621 htab->srofixup->size += 8;
16622 }
16623 }
16624 if (h->dynindx == -1 && !bfd_link_pic(info))
16625 {
16626 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16627 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16628 }
16629 else
16630 {
16631 /* Will need one dynamic reloc per reference. will be either
16632 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16633 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16634 eh->fdpic_cnts.funcdesc_cnt);
16635 }
16636 }
16637
a4fd1a8e
PB		 16638 /* Allocate stubs for exported Thumb functions on v4t. */
16639 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16640 && h->def_regular
39d911fc 16641 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16642 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16643 {
16644 struct elf_link_hash_entry * th;
16645 struct bfd_link_hash_entry * bh;
16646 struct elf_link_hash_entry * myh;
16647 char name[1024];
16648 asection *s;
16649 bh = NULL;
16650 /* Create a new symbol to regist the real location of the function. */
16651 s = h->root.u.def.section;
906e58ca 16652 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16653 _bfd_generic_link_add_one_symbol (info, s->owner,
16654 name, BSF_GLOBAL, s,
16655 h->root.u.def.value,
16656 NULL, TRUE, FALSE, &bh);
16657
16658 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16659 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16660 myh->forced_local = 1;
39d911fc 16661 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16662 eh->export_glue = myh;
16663 th = record_arm_to_thumb_glue (info, h);
16664 /* Point the symbol at the stub. */
16665 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16666 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16667 h->root.u.def.section = th->root.u.def.section;
16668 h->root.u.def.value = th->root.u.def.value & ~1;
16669 }
16670
0bdcacaf 16671 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16672 return TRUE;
16673
16674 /* In the shared -Bsymbolic case, discard space allocated for
16675 dynamic pc-relative relocs against symbols which turn out to be
16676 defined in regular objects. For the normal shared case, discard
16677 space for pc-relative relocs that have become local due to symbol
16678 visibility changes. */
16679
e8b09b87 16680 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16681 {
469a3493
RM		 16682 /* Relocs that use pc_count are PC-relative forms, which will appear
16683 on something like ".long foo - ." or "movw REG, foo - .". We want
16684 calls to protected symbols to resolve directly to the function
16685 rather than going via the plt. If people want function pointer
16686 comparisons to work as expected then they should avoid writing
16687 assembly like ".long foo - .". */
ba93b8ac
DJ		 16688 if (SYMBOL_CALLS_LOCAL (info, h))
16689 {
0bdcacaf 16690 struct elf_dyn_relocs **pp;
ba93b8ac 16691
0bdcacaf 16692 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16693 {
16694 p->count -= p->pc_count;
16695 p->pc_count = 0;
16696 if (p->count == 0)
16697 *pp = p->next;
16698 else
16699 pp = &p->next;
16700 }
16701 }
16702
4dfe6ac6 16703 if (htab->vxworks_p)
3348747a 16704 {
0bdcacaf 16705 struct elf_dyn_relocs **pp;
3348747a 16706
0bdcacaf 16707 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16708 {
0bdcacaf 16709 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16710 *pp = p->next;
16711 else
16712 pp = &p->next;
16713 }
16714 }
16715
ba93b8ac 16716 /* Also discard relocs on undefined weak syms with non-default
99059e56 16717 visibility. */
0bdcacaf 16718 if (eh->dyn_relocs != NULL
5e681ec4 16719 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16720 {
95b03e4a
L		 16721 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16722 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16723 eh->dyn_relocs = NULL;
22d606e9
AM		 16724
16725 /* Make sure undefined weak symbols are output as a dynamic
16726 symbol in PIEs. */
e8b09b87 16727 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16728 && !h->forced_local)
16729 {
16730 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16731 return FALSE;
16732 }
16733 }
16734
67687978
PB		 16735 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16736 && h->root.type == bfd_link_hash_new)
16737 {
16738 /* Output absolute symbols so that we can create relocations
16739 against them. For normal symbols we output a relocation
16740 against the section that contains them. */
16741 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16742 return FALSE;
16743 }
16744
5e681ec4
PB		 16745 }
16746 else
16747 {
16748 /* For the non-shared case, discard space for relocs against
16749 symbols which turn out to need copy relocs or are not
16750 dynamic. */
16751
f5385ebf
AM		 16752 if (!h->non_got_ref
16753 && ((h->def_dynamic
16754 && !h->def_regular)
5e681ec4
PB		 16755 || (htab->root.dynamic_sections_created
16756 && (h->root.type == bfd_link_hash_undefweak
16757 || h->root.type == bfd_link_hash_undefined))))
16758 {
16759 /* Make sure this symbol is output as a dynamic symbol.
16760 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16761 if (h->dynindx == -1 && !h->forced_local
16762 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16763 {
c152c796 16764 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16765 return FALSE;
16766 }
16767
16768 /* If that succeeded, we know we'll be keeping all the
16769 relocs. */
16770 if (h->dynindx != -1)
16771 goto keep;
16772 }
16773
0bdcacaf 16774 eh->dyn_relocs = NULL;
5e681ec4
PB		 16775
16776 keep: ;
16777 }
16778
16779 /* Finally, allocate space. */
0bdcacaf 16780 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16781 {
0bdcacaf 16782 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16783
34e77a92
RS		 16784 if (h->type == STT_GNU_IFUNC
16785 && eh->plt.noncall_refcount == 0
16786 && SYMBOL_REFERENCES_LOCAL (info, h))
16787 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16788 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16789 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16790 else if (htab->fdpic_p && !bfd_link_pic(info))
16791 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16792 else
16793 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16794 }
16795
16796 return TRUE;
16797}
16798
63c1f59d
AM		 16799/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16800 read-only sections. */
08d1f311
DJ		 16801
16802static bfd_boolean
63c1f59d 16803maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16804{
63c1f59d 16805 asection *sec;
08d1f311 16806
63c1f59d
AM		 16807 if (h->root.type == bfd_link_hash_indirect)
16808 return TRUE;
08d1f311 16809
63c1f59d
AM		 16810 sec = readonly_dynrelocs (h);
16811 if (sec != NULL)
16812 {
16813 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16814
63c1f59d
AM		 16815 info->flags |= DF_TEXTREL;
16816 info->callbacks->minfo
c1c8c1ef 16817 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16818 sec->owner, h->root.root.string, sec);
08d1f311 16819
63c1f59d
AM		 16820 /* Not an error, just cut short the traversal. */
16821 return FALSE;
08d1f311 16822 }
cb10292c 16823
08d1f311
DJ		 16824 return TRUE;
16825}
16826
d504ffc8
DJ		 16827void
16828bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16829 int byteswap_code)
16830{
16831 struct elf32_arm_link_hash_table *globals;
16832
16833 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16834 if (globals == NULL)
16835 return;
16836
d504ffc8
DJ		 16837 globals->byteswap_code = byteswap_code;
16838}
16839
252b5132
RH		 16840/* Set the sizes of the dynamic sections. */
16841
b34976b6 16842static bfd_boolean
57e8b36a
NC		 16843elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16844 struct bfd_link_info * info)
252b5132
RH		 16845{
16846 bfd * dynobj;
16847 asection * s;
b34976b6
AM		 16848 bfd_boolean plt;
16849 bfd_boolean relocs;
5e681ec4
PB		 16850 bfd *ibfd;
16851 struct elf32_arm_link_hash_table *htab;
252b5132 16852
5e681ec4 16853 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16854 if (htab == NULL)
16855 return FALSE;
16856
252b5132
RH		 16857 dynobj = elf_hash_table (info)->dynobj;
16858 BFD_ASSERT (dynobj != NULL);
39b41c9c 16859 check_use_blx (htab);
252b5132
RH		 16860
16861 if (elf_hash_table (info)->dynamic_sections_created)
16862 {
16863 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16864 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16865 {
3d4d4302 16866 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16867 BFD_ASSERT (s != NULL);
eea6121a 16868 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16869 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16870 }
16871 }
5e681ec4
PB		 16872
16873 /* Set up .got offsets for local syms, and space for local dynamic
16874 relocs. */
c72f2fb2 16875 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16876 {
5e681ec4
PB		 16877 bfd_signed_vma *local_got;
16878 bfd_signed_vma *end_local_got;
34e77a92 16879 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16880 char *local_tls_type;
0855e32b 16881 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16882 bfd_size_type locsymcount;
16883 Elf_Internal_Shdr *symtab_hdr;
16884 asection *srel;
4dfe6ac6 16885 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16886 unsigned int symndx;
e8b09b87 16887 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16888
0ffa91dd 16889 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16890 continue;
16891
16892 for (s = ibfd->sections; s != NULL; s = s->next)
16893 {
0bdcacaf 16894 struct elf_dyn_relocs *p;
5e681ec4 16895
0bdcacaf 16896 for (p = (struct elf_dyn_relocs *)
99059e56 16897 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16898 {
0bdcacaf
RS		 16899 if (!bfd_is_abs_section (p->sec)
16900 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16901 {
16902 /* Input section has been discarded, either because
16903 it is a copy of a linkonce section or due to
16904 linker script /DISCARD/, so we'll be discarding
16905 the relocs too. */
16906 }
3348747a 16907 else if (is_vxworks
0bdcacaf 16908 && strcmp (p->sec->output_section->name,
3348747a
NS		 16909 ".tls_vars") == 0)
16910 {
16911 /* Relocations in vxworks .tls_vars sections are
16912 handled specially by the loader. */
16913 }
5e681ec4
PB		 16914 else if (p->count != 0)
16915 {
0bdcacaf 16916 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16917 if (htab->fdpic_p && !bfd_link_pic(info))
16918 htab->srofixup->size += 4 * p->count;
16919 else
16920 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16921 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16922 info->flags |= DF_TEXTREL;
16923 }
16924 }
16925 }
16926
16927 local_got = elf_local_got_refcounts (ibfd);
16928 if (!local_got)
16929 continue;
16930
0ffa91dd 16931 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16932 locsymcount = symtab_hdr->sh_info;
16933 end_local_got = local_got + locsymcount;
34e77a92 16934 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16935 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16936 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16937 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16938 symndx = 0;
362d30a1
RS		 16939 s = htab->root.sgot;
16940 srel = htab->root.srelgot;
0855e32b 16941 for (; local_got < end_local_got;
34e77a92 16942 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16943 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16944 {
0855e32b 16945 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16946 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16947
16948 /* FDPIC support. */
16949 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16950 {
16951 if (local_fdpic_cnts->funcdesc_offset == -1)
16952 {
16953 local_fdpic_cnts->funcdesc_offset = s->size;
16954 s->size += 8;
16955
16956 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16957 if (bfd_link_pic(info))
16958 elf32_arm_allocate_dynrelocs (info, srel, 1);
16959 else
16960 htab->srofixup->size += 8;
16961 }
16962 }
16963
16964 if (local_fdpic_cnts->funcdesc_cnt > 0)
16965 {
16966 if (local_fdpic_cnts->funcdesc_offset == -1)
16967 {
16968 local_fdpic_cnts->funcdesc_offset = s->size;
16969 s->size += 8;
16970
16971 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16972 if (bfd_link_pic(info))
16973 elf32_arm_allocate_dynrelocs (info, srel, 1);
16974 else
16975 htab->srofixup->size += 8;
16976 }
16977
16978 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16979 if (bfd_link_pic(info))
16980 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16981 else
16982 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16983 }
16984
34e77a92
RS		 16985 if (local_iplt != NULL)
16986 {
16987 struct elf_dyn_relocs *p;
16988
16989 if (local_iplt->root.refcount > 0)
16990 {
16991 elf32_arm_allocate_plt_entry (info, TRUE,
16992 &local_iplt->root,
16993 &local_iplt->arm);
16994 if (local_iplt->arm.noncall_refcount == 0)
16995 /* All references to the PLT are calls, so all
16996 non-call references can resolve directly to the
16997 run-time target. This means that the .got entry
16998 would be the same as the .igot.plt entry, so there's
16999 no point creating both. */
17000 *local_got = 0;
17001 }
17002 else
17003 {
17004 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
17005 local_iplt->root.offset = (bfd_vma) -1;
17006 }
17007
17008 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
17009 {
17010 asection *psrel;
17011
17012 psrel = elf_section_data (p->sec)->sreloc;
17013 if (local_iplt->arm.noncall_refcount == 0)
17014 elf32_arm_allocate_irelocs (info, psrel, p->count);
17015 else
17016 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
17017 }
17018 }
5e681ec4
PB		 17019 if (*local_got > 0)
17020 {
34e77a92
RS		 17021 Elf_Internal_Sym *isym;
17022
eea6121a 17023 *local_got = s->size;
ba93b8ac
DJ		 17024 if (*local_tls_type & GOT_TLS_GD)
17025 /* TLS_GD relocs need an 8-byte structure in the GOT. */
17026 s->size += 8;
0855e32b
NS		 17027 if (*local_tls_type & GOT_TLS_GDESC)
17028 {
17029 *local_tlsdesc_gotent = htab->root.sgotplt->size
17030 - elf32_arm_compute_jump_table_size (htab);
17031 htab->root.sgotplt->size += 8;
17032 *local_got = (bfd_vma) -2;
34e77a92 17033 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 17034 reloc in the middle of .got.plt. */
99059e56 17035 htab->num_tls_desc++;
0855e32b 17036 }
ba93b8ac
DJ		 17037 if (*local_tls_type & GOT_TLS_IE)
17038 s->size += 4;
ba93b8ac 17039
0855e32b
NS		 17040 if (*local_tls_type & GOT_NORMAL)
17041 {
17042 /* If the symbol is both GD and GDESC, *local_got
17043 may have been overwritten. */
17044 *local_got = s->size;
17045 s->size += 4;
17046 }
17047
34e77a92
RS		 17048 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
17049 if (isym == NULL)
17050 return FALSE;
17051
17052 /* If all references to an STT_GNU_IFUNC PLT are calls,
17053 then all non-call references, including this GOT entry,
17054 resolve directly to the run-time target. */
17055 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
17056 && (local_iplt == NULL
17057 || local_iplt->arm.noncall_refcount == 0))
17058 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 17059 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 17060 {
e8b09b87 17061 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 17062 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 17063 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
17064 htab->srofixup->size += 4;
99059e56 17065
e8b09b87
CL		 17066 if ((bfd_link_pic (info) || htab->fdpic_p)
17067 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 17068 {
17069 elf32_arm_allocate_dynrelocs (info,
17070 htab->root.srelplt, 1);
17071 htab->tls_trampoline = -1;
17072 }
0855e32b 17073 }
5e681ec4
PB		 17074 }
17075 else
17076 *local_got = (bfd_vma) -1;
17077 }
252b5132
RH		 17078 }
17079
ba93b8ac
DJ		 17080 if (htab->tls_ldm_got.refcount > 0)
17081 {
17082 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 17083 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 17084 htab->tls_ldm_got.offset = htab->root.sgot->size;
17085 htab->root.sgot->size += 8;
0e1862bb 17086 if (bfd_link_pic (info))
47beaa6a 17087 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 17088 }
17089 else
17090 htab->tls_ldm_got.offset = -1;
17091
e8b09b87
CL		 17092 /* At the very end of the .rofixup section is a pointer to the GOT,
17093 reserve space for it. */
17094 if (htab->fdpic_p && htab->srofixup != NULL)
17095 htab->srofixup->size += 4;
17096
5e681ec4
PB		 17097 /* Allocate global sym .plt and .got entries, and space for global
17098 sym dynamic relocs. */
47beaa6a 17099 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 17100
d504ffc8 17101 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 17102 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 17103 {
0ffa91dd 17104 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 17105 continue;
17106
c7b8f16e
JB		 17107 /* Initialise mapping tables for code/data. */
17108 bfd_elf32_arm_init_maps (ibfd);
906e58ca 17109
c7b8f16e 17110 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 17111 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
17112 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 17113 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 17114 }
d504ffc8 17115
3e6b1042
DJ		 17116 /* Allocate space for the glue sections now that we've sized them. */
17117 bfd_elf32_arm_allocate_interworking_sections (info);
17118
0855e32b
NS		 17119 /* For every jump slot reserved in the sgotplt, reloc_count is
17120 incremented. However, when we reserve space for TLS descriptors,
17121 it's not incremented, so in order to compute the space reserved
17122 for them, it suffices to multiply the reloc count by the jump
17123 slot size. */
17124 if (htab->root.srelplt)
17125 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
17126
17127 if (htab->tls_trampoline)
17128 {
17129 if (htab->root.splt->size == 0)
17130 htab->root.splt->size += htab->plt_header_size;
b38cadfb 17131
0855e32b
NS		 17132 htab->tls_trampoline = htab->root.splt->size;
17133 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 17134
0855e32b 17135 /* If we're not using lazy TLS relocations, don't generate the
99059e56 17136 PLT and GOT entries they require. */
0855e32b
NS		 17137 if (!(info->flags & DF_BIND_NOW))
17138 {
17139 htab->dt_tlsdesc_got = htab->root.sgot->size;
17140 htab->root.sgot->size += 4;
17141
17142 htab->dt_tlsdesc_plt = htab->root.splt->size;
17143 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
17144 }
17145 }
17146
252b5132
RH		 17147 /* The check_relocs and adjust_dynamic_symbol entry points have
17148 determined the sizes of the various dynamic sections. Allocate
17149 memory for them. */
b34976b6
AM		 17150 plt = FALSE;
17151 relocs = FALSE;
252b5132
RH		 17152 for (s = dynobj->sections; s != NULL; s = s->next)
17153 {
17154 const char * name;
252b5132
RH		 17155
17156 if ((s->flags & SEC_LINKER_CREATED) == 0)
17157 continue;
17158
17159 /* It's OK to base decisions on the section name, because none
17160 of the dynobj section names depend upon the input files. */
17161 name = bfd_get_section_name (dynobj, s);
17162
34e77a92 17163 if (s == htab->root.splt)
252b5132 17164 {
c456f082
AM		 17165 /* Remember whether there is a PLT. */
17166 plt = s->size != 0;
252b5132 17167 }
0112cd26 17168 else if (CONST_STRNEQ (name, ".rel"))
252b5132 17169 {
c456f082 17170 if (s->size != 0)
252b5132 17171 {
252b5132 17172 /* Remember whether there are any reloc sections other
00a97672 17173 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17174 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17175 relocs = TRUE;
252b5132
RH		 17176
17177 /* We use the reloc_count field as a counter if we need
17178 to copy relocs into the output file. */
17179 s->reloc_count = 0;
17180 }
17181 }
34e77a92
RS		 17182 else if (s != htab->root.sgot
17183 && s != htab->root.sgotplt
17184 && s != htab->root.iplt
17185 && s != htab->root.igotplt
5474d94f 17186 && s != htab->root.sdynbss
e8b09b87
CL		 17187 && s != htab->root.sdynrelro
17188 && s != htab->srofixup)
252b5132
RH		 17189 {
17190 /* It's not one of our sections, so don't allocate space. */
17191 continue;
17192 }
17193
c456f082 17194 if (s->size == 0)
252b5132 17195 {
c456f082 17196 /* If we don't need this section, strip it from the
00a97672
RS		 17197 output file. This is mostly to handle .rel(a).bss and
17198 .rel(a).plt. We must create both sections in
c456f082
AM		 17199 create_dynamic_sections, because they must be created
17200 before the linker maps input sections to output
17201 sections. The linker does that before
17202 adjust_dynamic_symbol is called, and it is that
17203 function which decides whether anything needs to go
17204 into these sections. */
8423293d 17205 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17206 continue;
17207 }
17208
c456f082
AM		 17209 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17210 continue;
17211
252b5132 17212 /* Allocate memory for the section contents. */
21d799b5 17213 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17214 if (s->contents == NULL)
b34976b6 17215 return FALSE;
252b5132
RH		 17216 }
17217
17218 if (elf_hash_table (info)->dynamic_sections_created)
17219 {
17220 /* Add some entries to the .dynamic section. We fill in the
17221 values later, in elf32_arm_finish_dynamic_sections, but we
17222 must add the entries now so that we get the correct size for
17223 the .dynamic section. The DT_DEBUG entry is filled in by the
17224 dynamic linker and used by the debugger. */
dc810e39 17225#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17226 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17227
0e1862bb 17228 if (bfd_link_executable (info))
252b5132 17229 {
dc810e39 17230 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17231 return FALSE;
252b5132
RH		 17232 }
17233
17234 if (plt)
17235 {
dc810e39
AM		 17236 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17237 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17238 || !add_dynamic_entry (DT_PLTREL,
17239 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17240 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17241 return FALSE;
0855e32b 17242
5025eb7c
AO		 17243 if (htab->dt_tlsdesc_plt
17244 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17245 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17246 return FALSE;
252b5132
RH		 17247 }
17248
17249 if (relocs)
17250 {
00a97672
RS		 17251 if (htab->use_rel)
17252 {
17253 if (!add_dynamic_entry (DT_REL, 0)
17254 || !add_dynamic_entry (DT_RELSZ, 0)
17255 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17256 return FALSE;
17257 }
17258 else
17259 {
17260 if (!add_dynamic_entry (DT_RELA, 0)
17261 || !add_dynamic_entry (DT_RELASZ, 0)
17262 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17263 return FALSE;
17264 }
252b5132
RH		 17265 }
17266
08d1f311
DJ		 17267 /* If any dynamic relocs apply to a read-only section,
17268 then we need a DT_TEXTREL entry. */
17269 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17270 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17271
99e4ae17 17272 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17273 {
dc810e39 17274 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17275 return FALSE;
252b5132 17276 }
7a2b07ff
NS		 17277 if (htab->vxworks_p
17278 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17279 return FALSE;
252b5132 17280 }
8532796c 17281#undef add_dynamic_entry
252b5132 17282
b34976b6 17283 return TRUE;
252b5132
RH		 17284}
17285
0855e32b
NS		 17286/* Size sections even though they're not dynamic. We use it to setup
17287 _TLS_MODULE_BASE_, if needed. */
17288
17289static bfd_boolean
17290elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17291 struct bfd_link_info *info)
0855e32b
NS		 17292{
17293 asection *tls_sec;
cb10292c
CL		 17294 struct elf32_arm_link_hash_table *htab;
17295
17296 htab = elf32_arm_hash_table (info);
0855e32b 17297
0e1862bb 17298 if (bfd_link_relocatable (info))
0855e32b
NS		 17299 return TRUE;
17300
17301 tls_sec = elf_hash_table (info)->tls_sec;
17302
17303 if (tls_sec)
17304 {
17305 struct elf_link_hash_entry *tlsbase;
17306
17307 tlsbase = elf_link_hash_lookup
17308 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17309
17310 if (tlsbase)
99059e56
RM		 17311 {
17312 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17313 const struct elf_backend_data *bed
99059e56 17314 = get_elf_backend_data (output_bfd);
0855e32b 17315
99059e56 17316 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17317 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17318 tls_sec, 0, NULL, FALSE,
17319 bed->collect, &bh)))
17320 return FALSE;
b38cadfb 17321
99059e56
RM		 17322 tlsbase->type = STT_TLS;
17323 tlsbase = (struct elf_link_hash_entry *)bh;
17324 tlsbase->def_regular = 1;
17325 tlsbase->other = STV_HIDDEN;
17326 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17327 }
17328 }
cb10292c
CL		 17329
17330 if (htab->fdpic_p && !bfd_link_relocatable (info)
17331 && !bfd_elf_stack_segment_size (output_bfd, info,
17332 "__stacksize", DEFAULT_STACK_SIZE))
17333 return FALSE;
17334
0855e32b
NS		 17335 return TRUE;
17336}
17337
252b5132
RH		 17338/* Finish up dynamic symbol handling. We set the contents of various
17339 dynamic sections here. */
17340
b34976b6 17341static bfd_boolean
906e58ca
NC		 17342elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17343 struct bfd_link_info * info,
17344 struct elf_link_hash_entry * h,
17345 Elf_Internal_Sym * sym)
252b5132 17346{
e5a52504 17347 struct elf32_arm_link_hash_table *htab;
b7693d02 17348 struct elf32_arm_link_hash_entry *eh;
252b5132 17349
e5a52504 17350 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17351 if (htab == NULL)
17352 return FALSE;
17353
b7693d02 17354 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17355
17356 if (h->plt.offset != (bfd_vma) -1)
17357 {
34e77a92 17358 if (!eh->is_iplt)
e5a52504 17359 {
34e77a92 17360 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17361 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17362 h->dynindx, 0))
17363 return FALSE;
e5a52504 17364 }
57e8b36a 17365
f5385ebf 17366 if (!h->def_regular)
252b5132
RH		 17367 {
17368 /* Mark the symbol as undefined, rather than as defined in
3a635617 17369 the .plt section. */
252b5132 17370 sym->st_shndx = SHN_UNDEF;
3a635617 17371 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17372 Otherwise, the PLT entry would provide a definition for
17373 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17374 and so the symbol would never be NULL. Leave the value if
17375 there were any relocations where pointer equality matters
17376 (this is a clue for the dynamic linker, to make function
17377 pointer comparisons work between an application and shared
17378 library). */
97323ad1 17379 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17380 sym->st_value = 0;
252b5132 17381 }
34e77a92
RS		 17382 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17383 {
17384 /* At least one non-call relocation references this .iplt entry,
17385 so the .iplt entry is the function's canonical address. */
17386 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17387 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17388 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17389 (output_bfd, htab->root.iplt->output_section));
17390 sym->st_value = (h->plt.offset
17391 + htab->root.iplt->output_section->vma
17392 + htab->root.iplt->output_offset);
17393 }
252b5132
RH		 17394 }
17395
f5385ebf 17396 if (h->needs_copy)
252b5132
RH		 17397 {
17398 asection * s;
947216bf 17399 Elf_Internal_Rela rel;
252b5132
RH		 17400
17401 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17402 BFD_ASSERT (h->dynindx != -1
17403 && (h->root.type == bfd_link_hash_defined
17404 || h->root.type == bfd_link_hash_defweak));
17405
00a97672 17406 rel.r_addend = 0;
252b5132
RH		 17407 rel.r_offset = (h->root.u.def.value
17408 + h->root.u.def.section->output_section->vma
17409 + h->root.u.def.section->output_offset);
17410 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17411 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17412 s = htab->root.sreldynrelro;
17413 else
17414 s = htab->root.srelbss;
47beaa6a 17415 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17416 }
17417
00a97672 17418 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17419 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17420 it is relative to the ".got" section. */
9637f6ef 17421 if (h == htab->root.hdynamic
fac7bd64 17422 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17423 sym->st_shndx = SHN_ABS;
17424
b34976b6 17425 return TRUE;
252b5132
RH		 17426}
17427
0855e32b
NS		 17428static void
17429arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17430 void *contents,
17431 const unsigned long *template, unsigned count)
17432{
17433 unsigned ix;
b38cadfb 17434
0855e32b
NS		 17435 for (ix = 0; ix != count; ix++)
17436 {
17437 unsigned long insn = template[ix];
17438
17439 /* Emit mov pc,rx if bx is not permitted. */
17440 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17441 insn = (insn & 0xf000000f) | 0x01a0f000;
17442 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17443 }
17444}
17445
99059e56
RM		 17446/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17447 other variants, NaCl needs this entry in a static executable's
17448 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17449 zero. For .iplt really only the last bundle is useful, and .iplt
17450 could have a shorter first entry, with each individual PLT entry's
17451 relative branch calculated differently so it targets the last
17452 bundle instead of the instruction before it (labelled .Lplt_tail
17453 above). But it's simpler to keep the size and layout of PLT0
17454 consistent with the dynamic case, at the cost of some dead code at
17455 the start of .iplt and the one dead store to the stack at the start
17456 of .Lplt_tail. */
17457static void
17458arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17459 asection *plt, bfd_vma got_displacement)
17460{
17461 unsigned int i;
17462
17463 put_arm_insn (htab, output_bfd,
17464 elf32_arm_nacl_plt0_entry[0]
17465 | arm_movw_immediate (got_displacement),
17466 plt->contents + 0);
17467 put_arm_insn (htab, output_bfd,
17468 elf32_arm_nacl_plt0_entry[1]
17469 | arm_movt_immediate (got_displacement),
17470 plt->contents + 4);
17471
17472 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17473 put_arm_insn (htab, output_bfd,
17474 elf32_arm_nacl_plt0_entry[i],
17475 plt->contents + (i * 4));
17476}
17477
252b5132
RH		 17478/* Finish up the dynamic sections. */
17479
b34976b6 17480static bfd_boolean
57e8b36a 17481elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17482{
17483 bfd * dynobj;
17484 asection * sgot;
17485 asection * sdyn;
4dfe6ac6
NC		 17486 struct elf32_arm_link_hash_table *htab;
17487
17488 htab = elf32_arm_hash_table (info);
17489 if (htab == NULL)
17490 return FALSE;
252b5132
RH		 17491
17492 dynobj = elf_hash_table (info)->dynobj;
17493
362d30a1 17494 sgot = htab->root.sgotplt;
894891db
NC		 17495 /* A broken linker script might have discarded the dynamic sections.
17496 Catch this here so that we do not seg-fault later on. */
17497 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17498 return FALSE;
3d4d4302 17499 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17500
17501 if (elf_hash_table (info)->dynamic_sections_created)
17502 {
17503 asection *splt;
17504 Elf32_External_Dyn *dyncon, *dynconend;
17505
362d30a1 17506 splt = htab->root.splt;
24a1ba0f 17507 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17508 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17509
17510 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17511 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17512
252b5132
RH		 17513 for (; dyncon < dynconend; dyncon++)
17514 {
17515 Elf_Internal_Dyn dyn;
17516 const char * name;
17517 asection * s;
17518
17519 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17520
17521 switch (dyn.d_tag)
17522 {
229fcec5
MM		 17523 unsigned int type;
17524
252b5132 17525 default:
7a2b07ff
NS		 17526 if (htab->vxworks_p
17527 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17528 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17529 break;
17530
229fcec5
MM		 17531 case DT_HASH:
17532 name = ".hash";
17533 goto get_vma_if_bpabi;
17534 case DT_STRTAB:
17535 name = ".dynstr";
17536 goto get_vma_if_bpabi;
17537 case DT_SYMTAB:
17538 name = ".dynsym";
17539 goto get_vma_if_bpabi;
c0042f5d
MM		 17540 case DT_VERSYM:
17541 name = ".gnu.version";
17542 goto get_vma_if_bpabi;
17543 case DT_VERDEF:
17544 name = ".gnu.version_d";
17545 goto get_vma_if_bpabi;
17546 case DT_VERNEED:
17547 name = ".gnu.version_r";
17548 goto get_vma_if_bpabi;
17549
252b5132 17550 case DT_PLTGOT:
4ade44b7 17551 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17552 goto get_vma;
17553 case DT_JMPREL:
00a97672 17554 name = RELOC_SECTION (htab, ".plt");
252b5132 17555 get_vma:
4ade44b7 17556 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17557 if (s == NULL)
17558 {
4eca0228 17559 _bfd_error_handler
4ade44b7 17560 (_("could not find section %s"), name);
05456594
NC		 17561 bfd_set_error (bfd_error_invalid_operation);
17562 return FALSE;
17563 }
229fcec5 17564 if (!htab->symbian_p)
4ade44b7 17565 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17566 else
17567 /* In the BPABI, tags in the PT_DYNAMIC section point
17568 at the file offset, not the memory address, for the
17569 convenience of the post linker. */
4ade44b7 17570 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17571 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17572 break;
17573
229fcec5
MM		 17574 get_vma_if_bpabi:
17575 if (htab->symbian_p)
17576 goto get_vma;
17577 break;
17578
252b5132 17579 case DT_PLTRELSZ:
362d30a1 17580 s = htab->root.srelplt;
252b5132 17581 BFD_ASSERT (s != NULL);
eea6121a 17582 dyn.d_un.d_val = s->size;
252b5132
RH		 17583 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17584 break;
906e58ca 17585
252b5132 17586 case DT_RELSZ:
00a97672 17587 case DT_RELASZ:
229fcec5
MM		 17588 case DT_REL:
17589 case DT_RELA:
229fcec5
MM		 17590 /* In the BPABI, the DT_REL tag must point at the file
17591 offset, not the VMA, of the first relocation
17592 section. So, we use code similar to that in
17593 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17594 relocation section, since relocation sections are
17595 never allocated under the BPABI. PLT relocs are also
17596 included. */
229fcec5
MM		 17597 if (htab->symbian_p)
17598 {
17599 unsigned int i;
17600 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17601 ? SHT_REL : SHT_RELA);
17602 dyn.d_un.d_val = 0;
17603 for (i = 1; i < elf_numsections (output_bfd); i++)
17604 {
906e58ca 17605 Elf_Internal_Shdr *hdr
229fcec5
MM		 17606 = elf_elfsections (output_bfd)[i];
17607 if (hdr->sh_type == type)
17608 {
906e58ca 17609 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17610 || dyn.d_tag == DT_RELASZ)
17611 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17612 else if ((ufile_ptr) hdr->sh_offset
17613 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17614 dyn.d_un.d_val = hdr->sh_offset;
17615 }
17616 }
17617 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17618 }
252b5132 17619 break;
88f7bcd5 17620
0855e32b 17621 case DT_TLSDESC_PLT:
99059e56 17622 s = htab->root.splt;
0855e32b
NS		 17623 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17624 + htab->dt_tlsdesc_plt);
17625 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17626 break;
17627
17628 case DT_TLSDESC_GOT:
99059e56 17629 s = htab->root.sgot;
0855e32b 17630 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17631 + htab->dt_tlsdesc_got);
0855e32b
NS		 17632 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17633 break;
17634
88f7bcd5
NC		 17635 /* Set the bottom bit of DT_INIT/FINI if the
17636 corresponding function is Thumb. */
17637 case DT_INIT:
17638 name = info->init_function;
17639 goto get_sym;
17640 case DT_FINI:
17641 name = info->fini_function;
17642 get_sym:
17643 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17644 then there is nothing to adjust. */
88f7bcd5
NC		 17645 if (dyn.d_un.d_val != 0)
17646 {
17647 struct elf_link_hash_entry * eh;
17648
17649 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17650 FALSE, FALSE, TRUE);
39d911fc
TP		 17651 if (eh != NULL
17652 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17653 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17654 {
17655 dyn.d_un.d_val |= 1;
b34976b6 17656 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17657 }
17658 }
17659 break;
252b5132
RH		 17660 }
17661 }
17662
24a1ba0f 17663 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17664 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17665 {
00a97672
RS		 17666 const bfd_vma *plt0_entry;
17667 bfd_vma got_address, plt_address, got_displacement;
17668
17669 /* Calculate the addresses of the GOT and PLT. */
17670 got_address = sgot->output_section->vma + sgot->output_offset;
17671 plt_address = splt->output_section->vma + splt->output_offset;
17672
17673 if (htab->vxworks_p)
17674 {
17675 /* The VxWorks GOT is relocated by the dynamic linker.
17676 Therefore, we must emit relocations rather than simply
17677 computing the values now. */
17678 Elf_Internal_Rela rel;
17679
17680 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17681 put_arm_insn (htab, output_bfd, plt0_entry[0],
17682 splt->contents + 0);
17683 put_arm_insn (htab, output_bfd, plt0_entry[1],
17684 splt->contents + 4);
17685 put_arm_insn (htab, output_bfd, plt0_entry[2],
17686 splt->contents + 8);
00a97672
RS		 17687 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17688
8029a119 17689 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17690 rel.r_offset = plt_address + 12;
17691 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17692 rel.r_addend = 0;
17693 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17694 htab->srelplt2->contents);
17695 }
b38cadfb 17696 else if (htab->nacl_p)
99059e56
RM		 17697 arm_nacl_put_plt0 (htab, output_bfd, splt,
17698 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17699 else if (using_thumb_only (htab))
17700 {
17701 got_displacement = got_address - (plt_address + 12);
17702
17703 plt0_entry = elf32_thumb2_plt0_entry;
17704 put_arm_insn (htab, output_bfd, plt0_entry[0],
17705 splt->contents + 0);
17706 put_arm_insn (htab, output_bfd, plt0_entry[1],
17707 splt->contents + 4);
17708 put_arm_insn (htab, output_bfd, plt0_entry[2],
17709 splt->contents + 8);
17710
17711 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17712 }
00a97672
RS		 17713 else
17714 {
17715 got_displacement = got_address - (plt_address + 16);
17716
17717 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17718 put_arm_insn (htab, output_bfd, plt0_entry[0],
17719 splt->contents + 0);
17720 put_arm_insn (htab, output_bfd, plt0_entry[1],
17721 splt->contents + 4);
17722 put_arm_insn (htab, output_bfd, plt0_entry[2],
17723 splt->contents + 8);
17724 put_arm_insn (htab, output_bfd, plt0_entry[3],
17725 splt->contents + 12);
5e681ec4 17726
5e681ec4 17727#ifdef FOUR_WORD_PLT
00a97672
RS		 17728 /* The displacement value goes in the otherwise-unused
17729 last word of the second entry. */
17730 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17731#else
00a97672 17732 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17733#endif
00a97672 17734 }
f7a74f8c 17735 }
252b5132
RH		 17736
17737 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17738 really seem like the right value. */
74541ad4
AM		 17739 if (splt->output_section->owner == output_bfd)
17740 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17741
0855e32b
NS		 17742 if (htab->dt_tlsdesc_plt)
17743 {
17744 bfd_vma got_address
17745 = sgot->output_section->vma + sgot->output_offset;
17746 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17747 + htab->root.sgot->output_offset);
17748 bfd_vma plt_address
17749 = splt->output_section->vma + splt->output_offset;
17750
b38cadfb 17751 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17752 splt->contents + htab->dt_tlsdesc_plt,
17753 dl_tlsdesc_lazy_trampoline, 6);
17754
17755 bfd_put_32 (output_bfd,
17756 gotplt_address + htab->dt_tlsdesc_got
17757 - (plt_address + htab->dt_tlsdesc_plt)
17758 - dl_tlsdesc_lazy_trampoline[6],
17759 splt->contents + htab->dt_tlsdesc_plt + 24);
17760 bfd_put_32 (output_bfd,
17761 got_address - (plt_address + htab->dt_tlsdesc_plt)
17762 - dl_tlsdesc_lazy_trampoline[7],
17763 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17764 }
17765
17766 if (htab->tls_trampoline)
17767 {
b38cadfb 17768 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17769 splt->contents + htab->tls_trampoline,
17770 tls_trampoline, 3);
17771#ifdef FOUR_WORD_PLT
17772 bfd_put_32 (output_bfd, 0x00000000,
17773 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17774#endif
0855e32b
NS		 17775 }
17776
0e1862bb
L		 17777 if (htab->vxworks_p
17778 && !bfd_link_pic (info)
17779 && htab->root.splt->size > 0)
00a97672
RS		 17780 {
17781 /* Correct the .rel(a).plt.unloaded relocations. They will have
17782 incorrect symbol indexes. */
17783 int num_plts;
eed62c48 17784 unsigned char *p;
00a97672 17785
362d30a1 17786 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17787 / htab->plt_entry_size);
17788 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17789
17790 for (; num_plts; num_plts--)
17791 {
17792 Elf_Internal_Rela rel;
17793
17794 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17795 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17796 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17797 p += RELOC_SIZE (htab);
17798
17799 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17800 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17801 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17802 p += RELOC_SIZE (htab);
17803 }
17804 }
252b5132
RH		 17805 }
17806
99059e56
RM		 17807 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17808 /* NaCl uses a special first entry in .iplt too. */
17809 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17810
252b5132 17811 /* Fill in the first three entries in the global offset table. */
229fcec5 17812 if (sgot)
252b5132 17813 {
229fcec5
MM		 17814 if (sgot->size > 0)
17815 {
17816 if (sdyn == NULL)
17817 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17818 else
17819 bfd_put_32 (output_bfd,
17820 sdyn->output_section->vma + sdyn->output_offset,
17821 sgot->contents);
17822 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17823 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17824 }
252b5132 17825
229fcec5
MM		 17826 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17827 }
252b5132 17828
e8b09b87
CL		 17829 /* At the very end of the .rofixup section is a pointer to the GOT. */
17830 if (htab->fdpic_p && htab->srofixup != NULL)
17831 {
17832 struct elf_link_hash_entry *hgot = htab->root.hgot;
17833
17834 bfd_vma got_value = hgot->root.u.def.value
17835 + hgot->root.u.def.section->output_section->vma
17836 + hgot->root.u.def.section->output_offset;
17837
17838 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17839
17840 /* Make sure we allocated and generated the same number of fixups. */
17841 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17842 }
17843
b34976b6 17844 return TRUE;
252b5132
RH		 17845}
17846
ba96a88f 17847static void
57e8b36a 17848elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 17849{
9b485d32 17850 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17851 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17852 struct elf_segment_map *m;
ba96a88f
NC		 17853
17854 i_ehdrp = elf_elfheader (abfd);
17855
94a3258f
PB		 17856 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17857 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
17858 else
7394f108 17859 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 17860 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17861
93204d3a
PB		 17862 if (link_info)
17863 {
17864 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17865 if (globals != NULL && globals->byteswap_code)
93204d3a 17866 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17867
17868 if (globals->fdpic_p)
17869 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17870 }
3bfcb652
NC		 17871
17872 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17873 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17874 {
17875 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17876 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17877 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17878 else
17879 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17880 }
ac4c9b04
MG		 17881
17882 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17883 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17884 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17885 {
17886 unsigned int j;
17887
17888 if (m->count == 0)
17889 continue;
17890 for (j = 0; j < m->count; j++)
17891 {
f0728ee3 17892 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17893 break;
17894 }
17895 if (j == m->count)
17896 {
17897 m->p_flags = PF_X;
17898 m->p_flags_valid = 1;
17899 }
17900 }
ba96a88f
NC		 17901}
17902
99e4ae17 17903static enum elf_reloc_type_class
7e612e98
AM		 17904elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17905 const asection *rel_sec ATTRIBUTE_UNUSED,
17906 const Elf_Internal_Rela *rela)
99e4ae17 17907{
f51e552e 17908 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17909 {
17910 case R_ARM_RELATIVE:
17911 return reloc_class_relative;
17912 case R_ARM_JUMP_SLOT:
17913 return reloc_class_plt;
17914 case R_ARM_COPY:
17915 return reloc_class_copy;
109575d7
JW		 17916 case R_ARM_IRELATIVE:
17917 return reloc_class_ifunc;
99e4ae17
AJ		 17918 default:
17919 return reloc_class_normal;
17920 }
17921}
17922
e489d0ae 17923static void
cc364be6 17924arm_final_write_processing (bfd *abfd)
e16bb312 17925{
5a6c6817 17926 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17927}
17928
cc364be6
AM		 17929static bfd_boolean
17930elf32_arm_final_write_processing (bfd *abfd)
06f44071 17931{
cc364be6
AM		 17932 arm_final_write_processing (abfd);
17933 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17934}
17935
40a18ebd
NC		 17936/* Return TRUE if this is an unwinding table entry. */
17937
17938static bfd_boolean
17939is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17940{
0112cd26
NC		 17941 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17942 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17943}
17944
17945
17946/* Set the type and flags for an ARM section. We do this by
17947 the section name, which is a hack, but ought to work. */
17948
17949static bfd_boolean
17950elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17951{
17952 const char * name;
17953
17954 name = bfd_get_section_name (abfd, sec);
17955
17956 if (is_arm_elf_unwind_section_name (abfd, name))
17957 {
17958 hdr->sh_type = SHT_ARM_EXIDX;
17959 hdr->sh_flags |= SHF_LINK_ORDER;
17960 }
ac4c9b04 17961
f0728ee3
AV		 17962 if (sec->flags & SEC_ELF_PURECODE)
17963 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17964
40a18ebd
NC		 17965 return TRUE;
17966}
17967
6dc132d9
L		 17968/* Handle an ARM specific section when reading an object file. This is
17969 called when bfd_section_from_shdr finds a section with an unknown
17970 type. */
40a18ebd
NC		 17971
17972static bfd_boolean
17973elf32_arm_section_from_shdr (bfd *abfd,
17974 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17975 const char *name,
17976 int shindex)
40a18ebd
NC		 17977{
17978 /* There ought to be a place to keep ELF backend specific flags, but
17979 at the moment there isn't one. We just keep track of the
17980 sections by their name, instead. Fortunately, the ABI gives
17981 names for all the ARM specific sections, so we will probably get
17982 away with this. */
17983 switch (hdr->sh_type)
17984 {
17985 case SHT_ARM_EXIDX:
0951f019
RE		 17986 case SHT_ARM_PREEMPTMAP:
17987 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17988 break;
17989
17990 default:
17991 return FALSE;
17992 }
17993
6dc132d9 17994 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17995 return FALSE;
17996
17997 return TRUE;
17998}
e489d0ae 17999
44444f50
NC		 18000static _arm_elf_section_data *
18001get_arm_elf_section_data (asection * sec)
18002{
47b2e99c
JZ		 18003 if (sec && sec->owner && is_arm_elf (sec->owner))
18004 return elf32_arm_section_data (sec);
44444f50
NC		 18005 else
18006 return NULL;
8e3de13a
NC		 18007}
18008
4e617b1e
PB		 18009typedef struct
18010{
57402f1e 18011 void *flaginfo;
4e617b1e 18012 struct bfd_link_info *info;
91a5743d
PB		 18013 asection *sec;
18014 int sec_shndx;
6e0b88f1
AM		 18015 int (*func) (void *, const char *, Elf_Internal_Sym *,
18016 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 18017} output_arch_syminfo;
18018
18019enum map_symbol_type
18020{
18021 ARM_MAP_ARM,
18022 ARM_MAP_THUMB,
18023 ARM_MAP_DATA
18024};
18025
18026
7413f23f 18027/* Output a single mapping symbol. */
4e617b1e
PB		 18028
18029static bfd_boolean
7413f23f
DJ		 18030elf32_arm_output_map_sym (output_arch_syminfo *osi,
18031 enum map_symbol_type type,
18032 bfd_vma offset)
4e617b1e
PB		 18033{
18034 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 18035 Elf_Internal_Sym sym;
18036
91a5743d
PB		 18037 sym.st_value = osi->sec->output_section->vma
18038 + osi->sec->output_offset
18039 + offset;
4e617b1e
PB		 18040 sym.st_size = 0;
18041 sym.st_other = 0;
18042 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 18043 sym.st_shndx = osi->sec_shndx;
35fc36a8 18044 sym.st_target_internal = 0;
fe33d2fa 18045 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 18046 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 18047}
18048
34e77a92
RS		 18049/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
18050 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 18051
18052static bfd_boolean
34e77a92
RS		 18053elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
18054 bfd_boolean is_iplt_entry_p,
18055 union gotplt_union *root_plt,
18056 struct arm_plt_info *arm_plt)
4e617b1e 18057{
4e617b1e 18058 struct elf32_arm_link_hash_table *htab;
34e77a92 18059 bfd_vma addr, plt_header_size;
4e617b1e 18060
34e77a92 18061 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 18062 return TRUE;
18063
4dfe6ac6
NC		 18064 htab = elf32_arm_hash_table (osi->info);
18065 if (htab == NULL)
18066 return FALSE;
18067
34e77a92
RS		 18068 if (is_iplt_entry_p)
18069 {
18070 osi->sec = htab->root.iplt;
18071 plt_header_size = 0;
18072 }
18073 else
18074 {
18075 osi->sec = htab->root.splt;
18076 plt_header_size = htab->plt_header_size;
18077 }
18078 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
18079 (osi->info->output_bfd, osi->sec->output_section));
18080
18081 addr = root_plt->offset & -2;
4e617b1e
PB		 18082 if (htab->symbian_p)
18083 {
7413f23f 18084 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18085 return FALSE;
7413f23f 18086 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 18087 return FALSE;
18088 }
18089 else if (htab->vxworks_p)
18090 {
7413f23f 18091 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18092 return FALSE;
7413f23f 18093 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 18094 return FALSE;
7413f23f 18095 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 18096 return FALSE;
7413f23f 18097 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 18098 return FALSE;
18099 }
b38cadfb
NC		 18100 else if (htab->nacl_p)
18101 {
18102 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
18103 return FALSE;
18104 }
7801f98f
CL		 18105 else if (htab->fdpic_p)
18106 {
59029f57
CL		 18107 enum map_symbol_type type = using_thumb_only(htab)
18108 ? ARM_MAP_THUMB
18109 : ARM_MAP_ARM;
18110
7801f98f 18111 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 18112 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
18113 return FALSE;
59029f57 18114 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 18115 return FALSE;
7801f98f 18116 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 18117 return FALSE;
7801f98f 18118 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 18119 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
18120 return FALSE;
7801f98f 18121 }
eed94f8f
NC		 18122 else if (using_thumb_only (htab))
18123 {
18124 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
18125 return FALSE;
6a631e86 18126 }
4e617b1e
PB		 18127 else
18128 {
34e77a92 18129 bfd_boolean thumb_stub_p;
bd97cb95 18130
34e77a92
RS		 18131 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
18132 if (thumb_stub_p)
4e617b1e 18133 {
7413f23f 18134 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 18135 return FALSE;
18136 }
18137#ifdef FOUR_WORD_PLT
7413f23f 18138 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18139 return FALSE;
7413f23f 18140 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 18141 return FALSE;
18142#else
906e58ca 18143 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 18144 so only need to output a mapping symbol for the first PLT entry and
18145 entries with thumb thunks. */
34e77a92 18146 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 18147 {
7413f23f 18148 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 18149 return FALSE;
18150 }
18151#endif
18152 }
18153
18154 return TRUE;
18155}
18156
34e77a92
RS		 18157/* Output mapping symbols for PLT entries associated with H. */
18158
18159static bfd_boolean
18160elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
18161{
18162 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
18163 struct elf32_arm_link_hash_entry *eh;
18164
18165 if (h->root.type == bfd_link_hash_indirect)
18166 return TRUE;
18167
18168 if (h->root.type == bfd_link_hash_warning)
18169 /* When warning symbols are created, they **replace** the "real"
18170 entry in the hash table, thus we never get to see the real
18171 symbol in a hash traversal. So look at it now. */
18172 h = (struct elf_link_hash_entry *) h->root.u.i.link;
18173
18174 eh = (struct elf32_arm_link_hash_entry *) h;
18175 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
18176 &h->plt, &eh->plt);
18177}
18178
4f4faa4d
TP		 18179/* Bind a veneered symbol to its veneer identified by its hash entry
18180 STUB_ENTRY. The veneered location thus loose its symbol. */
18181
18182static void
18183arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
18184{
18185 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
18186
18187 BFD_ASSERT (hash);
18188 hash->root.root.u.def.section = stub_entry->stub_sec;
18189 hash->root.root.u.def.value = stub_entry->stub_offset;
18190 hash->root.size = stub_entry->stub_size;
18191}
18192
7413f23f
DJ		 18193/* Output a single local symbol for a generated stub. */
18194
18195static bfd_boolean
18196elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18197 bfd_vma offset, bfd_vma size)
18198{
7413f23f
DJ		 18199 Elf_Internal_Sym sym;
18200
7413f23f
DJ		 18201 sym.st_value = osi->sec->output_section->vma
18202 + osi->sec->output_offset
18203 + offset;
18204 sym.st_size = size;
18205 sym.st_other = 0;
18206 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18207 sym.st_shndx = osi->sec_shndx;
35fc36a8 18208 sym.st_target_internal = 0;
57402f1e 18209 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 18210}
4e617b1e 18211
da5938a2 18212static bfd_boolean
8029a119
NC		 18213arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18214 void * in_arg)
da5938a2
NC		 18215{
18216 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 18217 asection *stub_sec;
18218 bfd_vma addr;
7413f23f 18219 char *stub_name;
9a008db3 18220 output_arch_syminfo *osi;
d3ce72d0 18221 const insn_sequence *template_sequence;
461a49ca
DJ		 18222 enum stub_insn_type prev_type;
18223 int size;
18224 int i;
18225 enum map_symbol_type sym_type;
da5938a2
NC		 18226
18227 /* Massage our args to the form they really have. */
18228 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 18229 osi = (output_arch_syminfo *) in_arg;
da5938a2 18230
da5938a2
NC		 18231 stub_sec = stub_entry->stub_sec;
18232
18233 /* Ensure this stub is attached to the current section being
7413f23f 18234 processed. */
da5938a2
NC		 18235 if (stub_sec != osi->sec)
18236 return TRUE;
18237
7413f23f 18238 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18239 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18240
18241 if (arm_stub_sym_claimed (stub_entry->stub_type))
18242 arm_stub_claim_sym (stub_entry);
18243 else
7413f23f 18244 {
4f4faa4d
TP		 18245 stub_name = stub_entry->output_name;
18246 switch (template_sequence[0].type)
18247 {
18248 case ARM_TYPE:
18249 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18250 stub_entry->stub_size))
18251 return FALSE;
18252 break;
18253 case THUMB16_TYPE:
18254 case THUMB32_TYPE:
18255 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18256 stub_entry->stub_size))
18257 return FALSE;
18258 break;
18259 default:
18260 BFD_FAIL ();
18261 return 0;
18262 }
7413f23f 18263 }
da5938a2 18264
461a49ca
DJ		 18265 prev_type = DATA_TYPE;
18266 size = 0;
18267 for (i = 0; i < stub_entry->stub_template_size; i++)
18268 {
d3ce72d0 18269 switch (template_sequence[i].type)
461a49ca
DJ		 18270 {
18271 case ARM_TYPE:
18272 sym_type = ARM_MAP_ARM;
18273 break;
18274
18275 case THUMB16_TYPE:
48229727 18276 case THUMB32_TYPE:
461a49ca
DJ		 18277 sym_type = ARM_MAP_THUMB;
18278 break;
18279
18280 case DATA_TYPE:
18281 sym_type = ARM_MAP_DATA;
18282 break;
18283
18284 default:
18285 BFD_FAIL ();
4e31c731 18286 return FALSE;
461a49ca
DJ		 18287 }
18288
d3ce72d0 18289 if (template_sequence[i].type != prev_type)
461a49ca 18290 {
d3ce72d0 18291 prev_type = template_sequence[i].type;
461a49ca
DJ		 18292 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18293 return FALSE;
18294 }
18295
d3ce72d0 18296 switch (template_sequence[i].type)
461a49ca
DJ		 18297 {
18298 case ARM_TYPE:
48229727 18299 case THUMB32_TYPE:
461a49ca
DJ		 18300 size += 4;
18301 break;
18302
18303 case THUMB16_TYPE:
18304 size += 2;
18305 break;
18306
18307 case DATA_TYPE:
18308 size += 4;
18309 break;
18310
18311 default:
18312 BFD_FAIL ();
4e31c731 18313 return FALSE;
461a49ca
DJ		 18314 }
18315 }
18316
da5938a2
NC		 18317 return TRUE;
18318}
18319
33811162
DG		 18320/* Output mapping symbols for linker generated sections,
18321 and for those data-only sections that do not have a
18322 $d. */
4e617b1e
PB		 18323
18324static bfd_boolean
18325elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18326 struct bfd_link_info *info,
57402f1e 18327 void *flaginfo,
6e0b88f1
AM		 18328 int (*func) (void *, const char *,
18329 Elf_Internal_Sym *,
18330 asection *,
18331 struct elf_link_hash_entry *))
4e617b1e
PB		 18332{
18333 output_arch_syminfo osi;
18334 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18335 bfd_vma offset;
18336 bfd_size_type size;
33811162 18337 bfd *input_bfd;
4e617b1e
PB		 18338
18339 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18340 if (htab == NULL)
18341 return FALSE;
18342
906e58ca 18343 check_use_blx (htab);
91a5743d 18344
57402f1e 18345 osi.flaginfo = flaginfo;
4e617b1e
PB		 18346 osi.info = info;
18347 osi.func = func;
906e58ca 18348
33811162
DG		 18349 /* Add a $d mapping symbol to data-only sections that
18350 don't have any mapping symbol. This may result in (harmless) redundant
18351 mapping symbols. */
18352 for (input_bfd = info->input_bfds;
18353 input_bfd != NULL;
c72f2fb2 18354 input_bfd = input_bfd->link.next)
33811162
DG		 18355 {
18356 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18357 for (osi.sec = input_bfd->sections;
18358 osi.sec != NULL;
18359 osi.sec = osi.sec->next)
18360 {
18361 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18362 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18363 != 0)
33811162
DG		 18364 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18365 == SEC_HAS_CONTENTS
18366 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18367 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18368 && osi.sec->size > 0
18369 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18370 {
18371 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18372 (output_bfd, osi.sec->output_section);
18373 if (osi.sec_shndx != (int)SHN_BAD)
18374 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18375 }
18376 }
18377 }
18378
91a5743d
PB		 18379 /* ARM->Thumb glue. */
18380 if (htab->arm_glue_size > 0)
18381 {
3d4d4302
AM		 18382 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18383 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18384
18385 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18386 (output_bfd, osi.sec->output_section);
0e1862bb 18387 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18388 || htab->pic_veneer)
18389 size = ARM2THUMB_PIC_GLUE_SIZE;
18390 else if (htab->use_blx)
18391 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18392 else
18393 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18394
91a5743d
PB		 18395 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18396 {
7413f23f
DJ		 18397 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18398 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18399 }
18400 }
18401
18402 /* Thumb->ARM glue. */
18403 if (htab->thumb_glue_size > 0)
18404 {
3d4d4302
AM		 18405 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18406 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18407
18408 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18409 (output_bfd, osi.sec->output_section);
18410 size = THUMB2ARM_GLUE_SIZE;
18411
18412 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18413 {
7413f23f
DJ		 18414 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18415 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18416 }
18417 }
18418
845b51d6
PB		 18419 /* ARMv4 BX veneers. */
18420 if (htab->bx_glue_size > 0)
18421 {
3d4d4302
AM		 18422 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18423 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18424
18425 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18426 (output_bfd, osi.sec->output_section);
18427
7413f23f 18428 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18429 }
18430
8029a119
NC		 18431 /* Long calls stubs. */
18432 if (htab->stub_bfd && htab->stub_bfd->sections)
18433 {
da5938a2 18434 asection* stub_sec;
8029a119 18435
da5938a2
NC		 18436 for (stub_sec = htab->stub_bfd->sections;
18437 stub_sec != NULL;
8029a119
NC		 18438 stub_sec = stub_sec->next)
18439 {
18440 /* Ignore non-stub sections. */
18441 if (!strstr (stub_sec->name, STUB_SUFFIX))
18442 continue;
da5938a2 18443
8029a119 18444 osi.sec = stub_sec;
da5938a2 18445
8029a119
NC		 18446 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18447 (output_bfd, osi.sec->output_section);
da5938a2 18448
8029a119
NC		 18449 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18450 }
18451 }
da5938a2 18452
91a5743d 18453 /* Finally, output mapping symbols for the PLT. */
34e77a92 18454 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18455 {
34e77a92
RS		 18456 osi.sec = htab->root.splt;
18457 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18458 (output_bfd, osi.sec->output_section));
18459
18460 /* Output mapping symbols for the plt header. SymbianOS does not have a
18461 plt header. */
18462 if (htab->vxworks_p)
18463 {
18464 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18465 if (!bfd_link_pic (info))
34e77a92
RS		 18466 {
18467 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18468 return FALSE;
18469 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18470 return FALSE;
18471 }
18472 }
b38cadfb
NC		 18473 else if (htab->nacl_p)
18474 {
18475 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18476 return FALSE;
18477 }
59029f57 18478 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18479 {
18480 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18481 return FALSE;
18482 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18483 return FALSE;
18484 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18485 return FALSE;
18486 }
e8b09b87 18487 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18488 {
7413f23f 18489 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18490 return FALSE;
34e77a92
RS		 18491#ifndef FOUR_WORD_PLT
18492 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18493 return FALSE;
34e77a92 18494#endif
4e617b1e
PB		 18495 }
18496 }
99059e56
RM		 18497 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18498 {
18499 /* NaCl uses a special first entry in .iplt too. */
18500 osi.sec = htab->root.iplt;
18501 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18502 (output_bfd, osi.sec->output_section));
18503 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18504 return FALSE;
18505 }
34e77a92
RS		 18506 if ((htab->root.splt && htab->root.splt->size > 0)
18507 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18508 {
34e77a92
RS		 18509 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18510 for (input_bfd = info->input_bfds;
18511 input_bfd != NULL;
c72f2fb2 18512 input_bfd = input_bfd->link.next)
34e77a92
RS		 18513 {
18514 struct arm_local_iplt_info **local_iplt;
18515 unsigned int i, num_syms;
4e617b1e 18516
34e77a92
RS		 18517 local_iplt = elf32_arm_local_iplt (input_bfd);
18518 if (local_iplt != NULL)
18519 {
18520 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18521 for (i = 0; i < num_syms; i++)
18522 if (local_iplt[i] != NULL
18523 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18524 &local_iplt[i]->root,
18525 &local_iplt[i]->arm))
18526 return FALSE;
18527 }
18528 }
18529 }
0855e32b
NS		 18530 if (htab->dt_tlsdesc_plt != 0)
18531 {
18532 /* Mapping symbols for the lazy tls trampoline. */
18533 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18534 return FALSE;
b38cadfb 18535
0855e32b
NS		 18536 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18537 htab->dt_tlsdesc_plt + 24))
18538 return FALSE;
18539 }
18540 if (htab->tls_trampoline != 0)
18541 {
18542 /* Mapping symbols for the tls trampoline. */
18543 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18544 return FALSE;
18545#ifdef FOUR_WORD_PLT
18546 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18547 htab->tls_trampoline + 12))
18548 return FALSE;
b38cadfb 18549#endif
0855e32b 18550 }
b38cadfb 18551
4e617b1e
PB		 18552 return TRUE;
18553}
18554
54ddd295
TP		 18555/* Filter normal symbols of CMSE entry functions of ABFD to include in
18556 the import library. All SYMCOUNT symbols of ABFD can be examined
18557 from their pointers in SYMS. Pointers of symbols to keep should be
18558 stored continuously at the beginning of that array.
18559
18560 Returns the number of symbols to keep. */
18561
18562static unsigned int
18563elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18564 struct bfd_link_info *info,
18565 asymbol **syms, long symcount)
18566{
18567 size_t maxnamelen;
18568 char *cmse_name;
18569 long src_count, dst_count = 0;
18570 struct elf32_arm_link_hash_table *htab;
18571
18572 htab = elf32_arm_hash_table (info);
18573 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18574 symcount = 0;
18575
18576 maxnamelen = 128;
18577 cmse_name = (char *) bfd_malloc (maxnamelen);
18578 for (src_count = 0; src_count < symcount; src_count++)
18579 {
18580 struct elf32_arm_link_hash_entry *cmse_hash;
18581 asymbol *sym;
18582 flagword flags;
18583 char *name;
18584 size_t namelen;
18585
18586 sym = syms[src_count];
18587 flags = sym->flags;
18588 name = (char *) bfd_asymbol_name (sym);
18589
18590 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18591 continue;
18592 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18593 continue;
18594
18595 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18596 if (namelen > maxnamelen)
18597 {
18598 cmse_name = (char *)
18599 bfd_realloc (cmse_name, namelen);
18600 maxnamelen = namelen;
18601 }
18602 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18603 cmse_hash = (struct elf32_arm_link_hash_entry *)
18604 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18605
18606 if (!cmse_hash
18607 || (cmse_hash->root.root.type != bfd_link_hash_defined
18608 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18609 || cmse_hash->root.type != STT_FUNC)
18610 continue;
18611
54ddd295
TP		 18612 syms[dst_count++] = sym;
18613 }
18614 free (cmse_name);
18615
18616 syms[dst_count] = NULL;
18617
18618 return dst_count;
18619}
18620
18621/* Filter symbols of ABFD to include in the import library. All
18622 SYMCOUNT symbols of ABFD can be examined from their pointers in
18623 SYMS. Pointers of symbols to keep should be stored continuously at
18624 the beginning of that array.
18625
18626 Returns the number of symbols to keep. */
18627
18628static unsigned int
18629elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18630 struct bfd_link_info *info,
18631 asymbol **syms, long symcount)
18632{
18633 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18634
046734ff
TP		 18635 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18636 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18637 library to be a relocatable object file. */
18638 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18639 if (globals->cmse_implib)
18640 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18641 else
18642 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18643}
18644
e489d0ae
PB		 18645/* Allocate target specific section data. */
18646
18647static bfd_boolean
18648elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18649{
f592407e
AM		 18650 if (!sec->used_by_bfd)
18651 {
18652 _arm_elf_section_data *sdata;
18653 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18654
21d799b5 18655 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18656 if (sdata == NULL)
18657 return FALSE;
18658 sec->used_by_bfd = sdata;
18659 }
e489d0ae
PB		 18660
18661 return _bfd_elf_new_section_hook (abfd, sec);
18662}
18663
18664
18665/* Used to order a list of mapping symbols by address. */
18666
18667static int
18668elf32_arm_compare_mapping (const void * a, const void * b)
18669{
7f6a71ff
JM		 18670 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18671 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18672
18673 if (amap->vma > bmap->vma)
18674 return 1;
18675 else if (amap->vma < bmap->vma)
18676 return -1;
18677 else if (amap->type > bmap->type)
18678 /* Ensure results do not depend on the host qsort for objects with
18679 multiple mapping symbols at the same address by sorting on type
18680 after vma. */
18681 return 1;
18682 else if (amap->type < bmap->type)
18683 return -1;
18684 else
18685 return 0;
e489d0ae
PB		 18686}
18687
2468f9c9
PB		 18688/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18689
18690static unsigned long
18691offset_prel31 (unsigned long addr, bfd_vma offset)
18692{
18693 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18694}
18695
18696/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18697 relocations. */
18698
18699static void
18700copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18701{
18702 unsigned long first_word = bfd_get_32 (output_bfd, from);
18703 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18704
2468f9c9
PB		 18705 /* High bit of first word is supposed to be zero. */
18706 if ((first_word & 0x80000000ul) == 0)
18707 first_word = offset_prel31 (first_word, offset);
b38cadfb 18708
2468f9c9
PB		 18709 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18710 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18711 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18712 second_word = offset_prel31 (second_word, offset);
b38cadfb 18713
2468f9c9
PB		 18714 bfd_put_32 (output_bfd, first_word, to);
18715 bfd_put_32 (output_bfd, second_word, to + 4);
18716}
e489d0ae 18717
48229727
JB		 18718/* Data for make_branch_to_a8_stub(). */
18719
b38cadfb
NC		 18720struct a8_branch_to_stub_data
18721{
48229727
JB		 18722 asection *writing_section;
18723 bfd_byte *contents;
18724};
18725
18726
18727/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18728 places for a particular section. */
18729
18730static bfd_boolean
18731make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18732 void *in_arg)
48229727
JB		 18733{
18734 struct elf32_arm_stub_hash_entry *stub_entry;
18735 struct a8_branch_to_stub_data *data;
18736 bfd_byte *contents;
18737 unsigned long branch_insn;
18738 bfd_vma veneered_insn_loc, veneer_entry_loc;
18739 bfd_signed_vma branch_offset;
18740 bfd *abfd;
8d9d9490 18741 unsigned int loc;
48229727
JB		 18742
18743 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18744 data = (struct a8_branch_to_stub_data *) in_arg;
18745
18746 if (stub_entry->target_section != data->writing_section
4563a860 18747 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18748 return TRUE;
18749
18750 contents = data->contents;
18751
8d9d9490
TP		 18752 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18753 generated when both source and target are in the same section. */
48229727
JB		 18754 veneered_insn_loc = stub_entry->target_section->output_section->vma
18755 + stub_entry->target_section->output_offset
8d9d9490 18756 + stub_entry->source_value;
48229727
JB		 18757
18758 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18759 + stub_entry->stub_sec->output_offset
18760 + stub_entry->stub_offset;
18761
18762 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18763 veneered_insn_loc &= ~3u;
18764
18765 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18766
18767 abfd = stub_entry->target_section->owner;
8d9d9490 18768 loc = stub_entry->source_value;
48229727
JB		 18769
18770 /* We attempt to avoid this condition by setting stubs_always_after_branch
18771 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18772 This check is just to be on the safe side... */
18773 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18774 {
871b3ab2 18775 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18776 "allocated in unsafe location"), abfd);
48229727
JB		 18777 return FALSE;
18778 }
18779
18780 switch (stub_entry->stub_type)
18781 {
18782 case arm_stub_a8_veneer_b:
18783 case arm_stub_a8_veneer_b_cond:
18784 branch_insn = 0xf0009000;
18785 goto jump24;
18786
18787 case arm_stub_a8_veneer_blx:
18788 branch_insn = 0xf000e800;
18789 goto jump24;
18790
18791 case arm_stub_a8_veneer_bl:
18792 {
18793 unsigned int i1, j1, i2, j2, s;
18794
18795 branch_insn = 0xf000d000;
18796
18797 jump24:
18798 if (branch_offset < -16777216 || branch_offset > 16777214)
18799 {
18800 /* There's not much we can do apart from complain if this
18801 happens. */
871b3ab2 18802 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18803 "of range (input file too large)"), abfd);
48229727
JB		 18804 return FALSE;
18805 }
18806
18807 /* i1 = not(j1 eor s), so:
18808 not i1 = j1 eor s
18809 j1 = (not i1) eor s. */
18810
18811 branch_insn |= (branch_offset >> 1) & 0x7ff;
18812 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18813 i2 = (branch_offset >> 22) & 1;
18814 i1 = (branch_offset >> 23) & 1;
18815 s = (branch_offset >> 24) & 1;
18816 j1 = (!i1) ^ s;
18817 j2 = (!i2) ^ s;
18818 branch_insn |= j2 << 11;
18819 branch_insn |= j1 << 13;
18820 branch_insn |= s << 26;
18821 }
18822 break;
18823
18824 default:
18825 BFD_FAIL ();
18826 return FALSE;
18827 }
18828
8d9d9490
TP		 18829 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18830 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18831
18832 return TRUE;
18833}
18834
a504d23a
LA		 18835/* Beginning of stm32l4xx work-around. */
18836
18837/* Functions encoding instructions necessary for the emission of the
18838 fix-stm32l4xx-629360.
18839 Encoding is extracted from the
18840 ARM (C) Architecture Reference Manual
18841 ARMv7-A and ARMv7-R edition
18842 ARM DDI 0406C.b (ID072512). */
18843
18844static inline bfd_vma
82188b29 18845create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18846{
18847 /* A8.8.18 B (A8-334)
18848 B target_address (Encoding T4). */
18849 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18850 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18851 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18852
a504d23a
LA		 18853 int s = ((branch_offset & 0x1000000) >> 24);
18854 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18855 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18856
18857 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18858 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18859
18860 bfd_vma patched_inst = 0xf0009000
18861 | s << 26 /* S. */
18862 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18863 | j1 << 13 /* J1. */
18864 | j2 << 11 /* J2. */
18865 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18866
18867 return patched_inst;
18868}
18869
18870static inline bfd_vma
18871create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18872{
18873 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18874 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18875 bfd_vma patched_inst = 0xe8900000
18876 | (/*W=*/wback << 21)
18877 | (base_reg << 16)
18878 | (reg_mask & 0x0000ffff);
18879
18880 return patched_inst;
18881}
18882
18883static inline bfd_vma
18884create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18885{
18886 /* A8.8.60 LDMDB/LDMEA (A8-402)
18887 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18888 bfd_vma patched_inst = 0xe9100000
18889 | (/*W=*/wback << 21)
18890 | (base_reg << 16)
18891 | (reg_mask & 0x0000ffff);
18892
18893 return patched_inst;
18894}
18895
18896static inline bfd_vma
18897create_instruction_mov (int target_reg, int source_reg)
18898{
18899 /* A8.8.103 MOV (register) (A8-486)
18900 MOV Rd, Rm (Encoding T1). */
18901 bfd_vma patched_inst = 0x4600
18902 | (target_reg & 0x7)
18903 | ((target_reg & 0x8) >> 3) << 7
18904 | (source_reg << 3);
18905
18906 return patched_inst;
18907}
18908
18909static inline bfd_vma
18910create_instruction_sub (int target_reg, int source_reg, int value)
18911{
18912 /* A8.8.221 SUB (immediate) (A8-708)
18913 SUB Rd, Rn, #value (Encoding T3). */
18914 bfd_vma patched_inst = 0xf1a00000
18915 | (target_reg << 8)
18916 | (source_reg << 16)
18917 | (/*S=*/0 << 20)
18918 | ((value & 0x800) >> 11) << 26
18919 | ((value & 0x700) >> 8) << 12
18920 | (value & 0x0ff);
18921
18922 return patched_inst;
18923}
18924
18925static inline bfd_vma
9239bbd3 18926create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18927 int first_reg)
18928{
18929 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18930 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18931 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18932 | (/*W=*/wback << 21)
18933 | (base_reg << 16)
9239bbd3
CM		 18934 | (num_words & 0x000000ff)
18935 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18936 | (first_reg & 0x00000001) << 22;
18937
18938 return patched_inst;
18939}
18940
18941static inline bfd_vma
9239bbd3
CM		 18942create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18943 int first_reg)
a504d23a
LA		 18944{
18945 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18946 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18947 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18948 | (base_reg << 16)
9239bbd3
CM		 18949 | (num_words & 0x000000ff)
18950 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18951 | (first_reg & 0x00000001) << 22;
18952
18953 return patched_inst;
18954}
18955
18956static inline bfd_vma
18957create_instruction_udf_w (int value)
18958{
18959 /* A8.8.247 UDF (A8-758)
18960 Undefined (Encoding T2). */
18961 bfd_vma patched_inst = 0xf7f0a000
18962 | (value & 0x00000fff)
18963 | (value & 0x000f0000) << 16;
18964
18965 return patched_inst;
18966}
18967
18968static inline bfd_vma
18969create_instruction_udf (int value)
18970{
18971 /* A8.8.247 UDF (A8-758)
18972 Undefined (Encoding T1). */
18973 bfd_vma patched_inst = 0xde00
18974 | (value & 0xff);
18975
18976 return patched_inst;
18977}
18978
18979/* Functions writing an instruction in memory, returning the next
18980 memory position to write to. */
18981
18982static inline bfd_byte *
18983push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18984 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18985{
18986 put_thumb2_insn (htab, output_bfd, insn, pt);
18987 return pt + 4;
18988}
18989
18990static inline bfd_byte *
18991push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18992 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18993{
18994 put_thumb_insn (htab, output_bfd, insn, pt);
18995 return pt + 2;
18996}
18997
18998/* Function filling up a region in memory with T1 and T2 UDFs taking
18999 care of alignment. */
19000
19001static bfd_byte *
19002stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 19003 bfd * output_bfd,
19004 const bfd_byte * const base_stub_contents,
19005 bfd_byte * const from_stub_contents,
19006 const bfd_byte * const end_stub_contents)
a504d23a
LA		 19007{
19008 bfd_byte *current_stub_contents = from_stub_contents;
19009
19010 /* Fill the remaining of the stub with deterministic contents : UDF
19011 instructions.
19012 Check if realignment is needed on modulo 4 frontier using T1, to
19013 further use T2. */
19014 if ((current_stub_contents < end_stub_contents)
19015 && !((current_stub_contents - base_stub_contents) % 2)
19016 && ((current_stub_contents - base_stub_contents) % 4))
19017 current_stub_contents =
19018 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19019 create_instruction_udf (0));
19020
19021 for (; current_stub_contents < end_stub_contents;)
19022 current_stub_contents =
19023 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19024 create_instruction_udf_w (0));
19025
19026 return current_stub_contents;
19027}
19028
19029/* Functions writing the stream of instructions equivalent to the
19030 derived sequence for ldmia, ldmdb, vldm respectively. */
19031
19032static void
19033stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
19034 bfd * output_bfd,
19035 const insn32 initial_insn,
19036 const bfd_byte *const initial_insn_addr,
19037 bfd_byte *const base_stub_contents)
19038{
19039 int wback = (initial_insn & 0x00200000) >> 21;
19040 int ri, rn = (initial_insn & 0x000F0000) >> 16;
19041 int insn_all_registers = initial_insn & 0x0000ffff;
19042 int insn_low_registers, insn_high_registers;
19043 int usable_register_mask;
b25e998d 19044 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19045 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19046 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
19047 bfd_byte *current_stub_contents = base_stub_contents;
19048
19049 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
19050
19051 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19052 smaller than 8 registers load sequences that do not cause the
19053 hardware issue. */
19054 if (nb_registers <= 8)
19055 {
19056 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19057 current_stub_contents =
19058 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19059 initial_insn);
19060
19061 /* B initial_insn_addr+4. */
19062 if (!restore_pc)
19063 current_stub_contents =
19064 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19065 create_instruction_branch_absolute
82188b29 19066 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19067
19068 /* Fill the remaining of the stub with deterministic contents. */
19069 current_stub_contents =
19070 stm32l4xx_fill_stub_udf (htab, output_bfd,
19071 base_stub_contents, current_stub_contents,
19072 base_stub_contents +
19073 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19074
19075 return;
19076 }
19077
19078 /* - reg_list[13] == 0. */
19079 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
19080
19081 /* - reg_list[14] & reg_list[15] != 1. */
19082 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19083
19084 /* - if (wback==1) reg_list[rn] == 0. */
19085 BFD_ASSERT (!wback || !restore_rn);
19086
19087 /* - nb_registers > 8. */
b25e998d 19088 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19089
19090 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19091
19092 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
19093 - One with the 7 lowest registers (register mask 0x007F)
19094 This LDM will finally contain between 2 and 7 registers
19095 - One with the 7 highest registers (register mask 0xDF80)
19096 This ldm will finally contain between 2 and 7 registers. */
19097 insn_low_registers = insn_all_registers & 0x007F;
19098 insn_high_registers = insn_all_registers & 0xDF80;
19099
19100 /* A spare register may be needed during this veneer to temporarily
19101 handle the base register. This register will be restored with the
19102 last LDM operation.
19103 The usable register may be any general purpose register (that
19104 excludes PC, SP, LR : register mask is 0x1FFF). */
19105 usable_register_mask = 0x1FFF;
19106
19107 /* Generate the stub function. */
19108 if (wback)
19109 {
19110 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
19111 current_stub_contents =
19112 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19113 create_instruction_ldmia
19114 (rn, /*wback=*/1, insn_low_registers));
19115
19116 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19117 current_stub_contents =
19118 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19119 create_instruction_ldmia
19120 (rn, /*wback=*/1, insn_high_registers));
19121 if (!restore_pc)
19122 {
19123 /* B initial_insn_addr+4. */
19124 current_stub_contents =
19125 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19126 create_instruction_branch_absolute
82188b29 19127 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19128 }
19129 }
19130 else /* if (!wback). */
19131 {
19132 ri = rn;
19133
19134 /* If Rn is not part of the high-register-list, move it there. */
19135 if (!(insn_high_registers & (1 << rn)))
19136 {
19137 /* Choose a Ri in the high-register-list that will be restored. */
19138 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19139
19140 /* MOV Ri, Rn. */
19141 current_stub_contents =
19142 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19143 create_instruction_mov (ri, rn));
19144 }
19145
19146 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19147 current_stub_contents =
19148 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19149 create_instruction_ldmia
19150 (ri, /*wback=*/1, insn_low_registers));
19151
19152 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19153 current_stub_contents =
19154 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19155 create_instruction_ldmia
19156 (ri, /*wback=*/0, insn_high_registers));
19157
19158 if (!restore_pc)
19159 {
19160 /* B initial_insn_addr+4. */
19161 current_stub_contents =
19162 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19163 create_instruction_branch_absolute
82188b29 19164 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19165 }
19166 }
19167
19168 /* Fill the remaining of the stub with deterministic contents. */
19169 current_stub_contents =
19170 stm32l4xx_fill_stub_udf (htab, output_bfd,
19171 base_stub_contents, current_stub_contents,
19172 base_stub_contents +
19173 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19174}
19175
19176static void
19177stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19178 bfd * output_bfd,
19179 const insn32 initial_insn,
19180 const bfd_byte *const initial_insn_addr,
19181 bfd_byte *const base_stub_contents)
19182{
19183 int wback = (initial_insn & 0x00200000) >> 21;
19184 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19185 int insn_all_registers = initial_insn & 0x0000ffff;
19186 int insn_low_registers, insn_high_registers;
19187 int usable_register_mask;
19188 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19189 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 19190 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19191 bfd_byte *current_stub_contents = base_stub_contents;
19192
19193 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19194
19195 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19196 smaller than 8 registers load sequences that do not cause the
19197 hardware issue. */
19198 if (nb_registers <= 8)
19199 {
19200 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19201 current_stub_contents =
19202 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19203 initial_insn);
19204
19205 /* B initial_insn_addr+4. */
19206 current_stub_contents =
19207 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19208 create_instruction_branch_absolute
82188b29 19209 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19210
19211 /* Fill the remaining of the stub with deterministic contents. */
19212 current_stub_contents =
19213 stm32l4xx_fill_stub_udf (htab, output_bfd,
19214 base_stub_contents, current_stub_contents,
19215 base_stub_contents +
19216 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19217
19218 return;
19219 }
19220
19221 /* - reg_list[13] == 0. */
19222 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19223
19224 /* - reg_list[14] & reg_list[15] != 1. */
19225 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19226
19227 /* - if (wback==1) reg_list[rn] == 0. */
19228 BFD_ASSERT (!wback || !restore_rn);
19229
19230 /* - nb_registers > 8. */
b25e998d 19231 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19232
19233 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19234
19235 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19236 - One with the 7 lowest registers (register mask 0x007F)
19237 This LDM will finally contain between 2 and 7 registers
19238 - One with the 7 highest registers (register mask 0xDF80)
19239 This ldm will finally contain between 2 and 7 registers. */
19240 insn_low_registers = insn_all_registers & 0x007F;
19241 insn_high_registers = insn_all_registers & 0xDF80;
19242
19243 /* A spare register may be needed during this veneer to temporarily
19244 handle the base register. This register will be restored with
19245 the last LDM operation.
19246 The usable register may be any general purpose register (that excludes
19247 PC, SP, LR : register mask is 0x1FFF). */
19248 usable_register_mask = 0x1FFF;
19249
19250 /* Generate the stub function. */
19251 if (!wback && !restore_pc && !restore_rn)
19252 {
19253 /* Choose a Ri in the low-register-list that will be restored. */
19254 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19255
19256 /* MOV Ri, Rn. */
19257 current_stub_contents =
19258 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19259 create_instruction_mov (ri, rn));
19260
19261 /* LDMDB Ri!, {R-high-register-list}. */
19262 current_stub_contents =
19263 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19264 create_instruction_ldmdb
19265 (ri, /*wback=*/1, insn_high_registers));
19266
19267 /* LDMDB Ri, {R-low-register-list}. */
19268 current_stub_contents =
19269 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19270 create_instruction_ldmdb
19271 (ri, /*wback=*/0, insn_low_registers));
19272
19273 /* B initial_insn_addr+4. */
19274 current_stub_contents =
19275 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19276 create_instruction_branch_absolute
82188b29 19277 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19278 }
19279 else if (wback && !restore_pc && !restore_rn)
19280 {
19281 /* LDMDB Rn!, {R-high-register-list}. */
19282 current_stub_contents =
19283 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19284 create_instruction_ldmdb
19285 (rn, /*wback=*/1, insn_high_registers));
19286
19287 /* LDMDB Rn!, {R-low-register-list}. */
19288 current_stub_contents =
19289 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19290 create_instruction_ldmdb
19291 (rn, /*wback=*/1, insn_low_registers));
19292
19293 /* B initial_insn_addr+4. */
19294 current_stub_contents =
19295 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19296 create_instruction_branch_absolute
82188b29 19297 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19298 }
19299 else if (!wback && restore_pc && !restore_rn)
19300 {
19301 /* Choose a Ri in the high-register-list that will be restored. */
19302 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19303
19304 /* SUB Ri, Rn, #(4*nb_registers). */
19305 current_stub_contents =
19306 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19307 create_instruction_sub (ri, rn, (4 * nb_registers)));
19308
19309 /* LDMIA Ri!, {R-low-register-list}. */
19310 current_stub_contents =
19311 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19312 create_instruction_ldmia
19313 (ri, /*wback=*/1, insn_low_registers));
19314
19315 /* LDMIA Ri, {R-high-register-list}. */
19316 current_stub_contents =
19317 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19318 create_instruction_ldmia
19319 (ri, /*wback=*/0, insn_high_registers));
19320 }
19321 else if (wback && restore_pc && !restore_rn)
19322 {
19323 /* Choose a Ri in the high-register-list that will be restored. */
19324 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19325
19326 /* SUB Rn, Rn, #(4*nb_registers) */
19327 current_stub_contents =
19328 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19329 create_instruction_sub (rn, rn, (4 * nb_registers)));
19330
19331 /* MOV Ri, Rn. */
19332 current_stub_contents =
19333 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19334 create_instruction_mov (ri, rn));
19335
19336 /* LDMIA Ri!, {R-low-register-list}. */
19337 current_stub_contents =
19338 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19339 create_instruction_ldmia
19340 (ri, /*wback=*/1, insn_low_registers));
19341
19342 /* LDMIA Ri, {R-high-register-list}. */
19343 current_stub_contents =
19344 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19345 create_instruction_ldmia
19346 (ri, /*wback=*/0, insn_high_registers));
19347 }
19348 else if (!wback && !restore_pc && restore_rn)
19349 {
19350 ri = rn;
19351 if (!(insn_low_registers & (1 << rn)))
19352 {
19353 /* Choose a Ri in the low-register-list that will be restored. */
19354 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19355
19356 /* MOV Ri, Rn. */
19357 current_stub_contents =
19358 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19359 create_instruction_mov (ri, rn));
19360 }
19361
19362 /* LDMDB Ri!, {R-high-register-list}. */
19363 current_stub_contents =
19364 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19365 create_instruction_ldmdb
19366 (ri, /*wback=*/1, insn_high_registers));
19367
19368 /* LDMDB Ri, {R-low-register-list}. */
19369 current_stub_contents =
19370 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19371 create_instruction_ldmdb
19372 (ri, /*wback=*/0, insn_low_registers));
19373
19374 /* B initial_insn_addr+4. */
19375 current_stub_contents =
19376 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19377 create_instruction_branch_absolute
82188b29 19378 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19379 }
19380 else if (!wback && restore_pc && restore_rn)
19381 {
19382 ri = rn;
19383 if (!(insn_high_registers & (1 << rn)))
19384 {
19385 /* Choose a Ri in the high-register-list that will be restored. */
19386 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19387 }
19388
19389 /* SUB Ri, Rn, #(4*nb_registers). */
19390 current_stub_contents =
19391 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19392 create_instruction_sub (ri, rn, (4 * nb_registers)));
19393
19394 /* LDMIA Ri!, {R-low-register-list}. */
19395 current_stub_contents =
19396 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19397 create_instruction_ldmia
19398 (ri, /*wback=*/1, insn_low_registers));
19399
19400 /* LDMIA Ri, {R-high-register-list}. */
19401 current_stub_contents =
19402 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19403 create_instruction_ldmia
19404 (ri, /*wback=*/0, insn_high_registers));
19405 }
19406 else if (wback && restore_rn)
19407 {
19408 /* The assembler should not have accepted to encode this. */
19409 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19410 "undefined behavior.\n");
19411 }
19412
19413 /* Fill the remaining of the stub with deterministic contents. */
19414 current_stub_contents =
19415 stm32l4xx_fill_stub_udf (htab, output_bfd,
19416 base_stub_contents, current_stub_contents,
19417 base_stub_contents +
19418 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19419
19420}
19421
19422static void
19423stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19424 bfd * output_bfd,
19425 const insn32 initial_insn,
19426 const bfd_byte *const initial_insn_addr,
19427 bfd_byte *const base_stub_contents)
19428{
9239bbd3 19429 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 19430 bfd_byte *current_stub_contents = base_stub_contents;
19431
19432 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19433
19434 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19435 smaller than 8 words load sequences that do not cause the
a504d23a 19436 hardware issue. */
9239bbd3 19437 if (num_words <= 8)
a504d23a
LA		 19438 {
19439 /* Untouched instruction. */
19440 current_stub_contents =
19441 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19442 initial_insn);
19443
19444 /* B initial_insn_addr+4. */
19445 current_stub_contents =
19446 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19447 create_instruction_branch_absolute
82188b29 19448 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19449 }
19450 else
19451 {
9eaff861 19452 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19453 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19454 bfd_boolean is_ia_nobang = /* (IA without !). */
19455 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19456 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19457 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19458 bfd_boolean is_db_bang = /* (DB with !). */
19459 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19460 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19461 /* d = UInt (Vd:D);. */
9239bbd3 19462 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19463 | (((unsigned int)initial_insn << 9) >> 31);
19464
9239bbd3
CM		 19465 /* Compute the number of 8-words chunks needed to split. */
19466 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19467 int chunk;
19468
19469 /* The test coverage has been done assuming the following
19470 hypothesis that exactly one of the previous is_ predicates is
19471 true. */
9239bbd3
CM		 19472 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19473 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19474
9239bbd3 19475 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19476 cases, then we emit the adjustments:
19477
19478 vldm rx, {...}
19479 -> vldm rx!, {8_words_or_less} for each needed 8_word
19480 -> sub rx, rx, #size (list)
19481
19482 vldm rx!, {...}
19483 -> vldm rx!, {8_words_or_less} for each needed 8_word
19484 This also handles vpop instruction (when rx is sp)
19485
19486 vldmd rx!, {...}
19487 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19488 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19489 {
9239bbd3
CM		 19490 bfd_vma new_insn = 0;
19491
a504d23a
LA		 19492 if (is_ia_nobang || is_ia_bang)
19493 {
9239bbd3
CM		 19494 new_insn = create_instruction_vldmia
19495 (base_reg,
19496 is_dp,
19497 /*wback= . */1,
19498 chunks - (chunk + 1) ?
19499 8 : num_words - chunk * 8,
19500 first_reg + chunk * 8);
a504d23a
LA		 19501 }
19502 else if (is_db_bang)
19503 {
9239bbd3
CM		 19504 new_insn = create_instruction_vldmdb
19505 (base_reg,
19506 is_dp,
19507 chunks - (chunk + 1) ?
19508 8 : num_words - chunk * 8,
19509 first_reg + chunk * 8);
a504d23a 19510 }
9239bbd3
CM		 19511
19512 if (new_insn)
19513 current_stub_contents =
19514 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19515 new_insn);
a504d23a
LA		 19516 }
19517
19518 /* Only this case requires the base register compensation
19519 subtract. */
19520 if (is_ia_nobang)
19521 {
19522 current_stub_contents =
19523 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19524 create_instruction_sub
9239bbd3 19525 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19526 }
19527
19528 /* B initial_insn_addr+4. */
19529 current_stub_contents =
19530 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19531 create_instruction_branch_absolute
82188b29 19532 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19533 }
19534
19535 /* Fill the remaining of the stub with deterministic contents. */
19536 current_stub_contents =
19537 stm32l4xx_fill_stub_udf (htab, output_bfd,
19538 base_stub_contents, current_stub_contents,
19539 base_stub_contents +
19540 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19541}
19542
19543static void
19544stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19545 bfd * output_bfd,
19546 const insn32 wrong_insn,
19547 const bfd_byte *const wrong_insn_addr,
19548 bfd_byte *const stub_contents)
19549{
19550 if (is_thumb2_ldmia (wrong_insn))
19551 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19552 wrong_insn, wrong_insn_addr,
19553 stub_contents);
19554 else if (is_thumb2_ldmdb (wrong_insn))
19555 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19556 wrong_insn, wrong_insn_addr,
19557 stub_contents);
19558 else if (is_thumb2_vldm (wrong_insn))
19559 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19560 wrong_insn, wrong_insn_addr,
19561 stub_contents);
19562}
19563
19564/* End of stm32l4xx work-around. */
19565
19566
e489d0ae
PB		 19567/* Do code byteswapping. Return FALSE afterwards so that the section is
19568 written out as normal. */
19569
19570static bfd_boolean
c7b8f16e 19571elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19572 struct bfd_link_info *link_info,
19573 asection *sec,
e489d0ae
PB		 19574 bfd_byte *contents)
19575{
48229727 19576 unsigned int mapcount, errcount;
8e3de13a 19577 _arm_elf_section_data *arm_data;
c7b8f16e 19578 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19579 elf32_arm_section_map *map;
c7b8f16e 19580 elf32_vfp11_erratum_list *errnode;
a504d23a 19581 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19582 bfd_vma ptr;
19583 bfd_vma end;
c7b8f16e 19584 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19585 bfd_byte tmp;
48229727 19586 unsigned int i;
57e8b36a 19587
4dfe6ac6
NC		 19588 if (globals == NULL)
19589 return FALSE;
19590
8e3de13a
NC		 19591 /* If this section has not been allocated an _arm_elf_section_data
19592 structure then we cannot record anything. */
19593 arm_data = get_arm_elf_section_data (sec);
19594 if (arm_data == NULL)
19595 return FALSE;
19596
19597 mapcount = arm_data->mapcount;
19598 map = arm_data->map;
c7b8f16e
JB		 19599 errcount = arm_data->erratumcount;
19600
19601 if (errcount != 0)
19602 {
19603 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19604
19605 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19606 errnode = errnode->next)
19607 {
19608 bfd_vma target = errnode->vma - offset;
19609
19610 switch (errnode->type)
19611 {
19612 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19613 {
19614 bfd_vma branch_to_veneer;
19615 /* Original condition code of instruction, plus bit mask for
19616 ARM B instruction. */
19617 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19618 | 0x0a000000;
c7b8f16e
JB		 19619
19620 /* The instruction is before the label. */
91d6fa6a 19621 target -= 4;
c7b8f16e
JB		 19622
19623 /* Above offset included in -4 below. */
19624 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19625 - errnode->vma - 4;
c7b8f16e
JB		 19626
19627 if ((signed) branch_to_veneer < -(1 << 25)
19628 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19629 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19630 "range"), output_bfd);
c7b8f16e 19631
99059e56
RM		 19632 insn |= (branch_to_veneer >> 2) & 0xffffff;
19633 contents[endianflip ^ target] = insn & 0xff;
19634 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19635 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19636 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19637 }
19638 break;
c7b8f16e
JB		 19639
19640 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19641 {
19642 bfd_vma branch_from_veneer;
19643 unsigned int insn;
c7b8f16e 19644
99059e56
RM		 19645 /* Take size of veneer into account. */
19646 branch_from_veneer = errnode->u.v.branch->vma
19647 - errnode->vma - 12;
c7b8f16e
JB		 19648
19649 if ((signed) branch_from_veneer < -(1 << 25)
19650 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19651 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19652 "range"), output_bfd);
c7b8f16e 19653
99059e56
RM		 19654 /* Original instruction. */
19655 insn = errnode->u.v.branch->u.b.vfp_insn;
19656 contents[endianflip ^ target] = insn & 0xff;
19657 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19658 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19659 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19660
19661 /* Branch back to insn after original insn. */
19662 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19663 contents[endianflip ^ (target + 4)] = insn & 0xff;
19664 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19665 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19666 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19667 }
19668 break;
c7b8f16e 19669
99059e56
RM		 19670 default:
19671 abort ();
19672 }
19673 }
c7b8f16e 19674 }
e489d0ae 19675
a504d23a
LA		 19676 if (arm_data->stm32l4xx_erratumcount != 0)
19677 {
19678 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19679 stm32l4xx_errnode != 0;
19680 stm32l4xx_errnode = stm32l4xx_errnode->next)
19681 {
19682 bfd_vma target = stm32l4xx_errnode->vma - offset;
19683
19684 switch (stm32l4xx_errnode->type)
19685 {
19686 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19687 {
19688 unsigned int insn;
19689 bfd_vma branch_to_veneer =
19690 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19691
19692 if ((signed) branch_to_veneer < -(1 << 24)
19693 || (signed) branch_to_veneer >= (1 << 24))
19694 {
19695 bfd_vma out_of_range =
19696 ((signed) branch_to_veneer < -(1 << 24)) ?
19697 - branch_to_veneer - (1 << 24) :
19698 ((signed) branch_to_veneer >= (1 << 24)) ?
19699 branch_to_veneer - (1 << 24) : 0;
19700
4eca0228 19701 _bfd_error_handler
2dcf00ce 19702 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19703 "cannot create STM32L4XX veneer; "
19704 "jump out of range by %" PRId64 " bytes; "
19705 "cannot encode branch instruction"),
a504d23a 19706 output_bfd,
2dcf00ce
AM		 19707 (uint64_t) (stm32l4xx_errnode->vma - 4),
19708 (int64_t) out_of_range);
a504d23a
LA		 19709 continue;
19710 }
19711
19712 insn = create_instruction_branch_absolute
82188b29 19713 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19714
a2699ef2
AM		 19715 /* The instruction is before the label. */
19716 target -= 4;
19717
a504d23a
LA		 19718 put_thumb2_insn (globals, output_bfd,
19719 (bfd_vma) insn, contents + target);
19720 }
19721 break;
19722
19723 case STM32L4XX_ERRATUM_VENEER:
19724 {
82188b29
NC		 19725 bfd_byte * veneer;
19726 bfd_byte * veneer_r;
a504d23a
LA		 19727 unsigned int insn;
19728
82188b29
NC		 19729 veneer = contents + target;
19730 veneer_r = veneer
19731 + stm32l4xx_errnode->u.b.veneer->vma
19732 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19733
19734 if ((signed) (veneer_r - veneer -
19735 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19736 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19737 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19738 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19739 || (signed) (veneer_r - veneer) >= (1 << 24))
19740 {
90b6238f
AM		 19741 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19742 "veneer"), output_bfd);
a504d23a
LA		 19743 continue;
19744 }
19745
19746 /* Original instruction. */
19747 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19748
19749 stm32l4xx_create_replacing_stub
19750 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19751 }
19752 break;
19753
19754 default:
19755 abort ();
19756 }
19757 }
19758 }
19759
2468f9c9
PB		 19760 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19761 {
19762 arm_unwind_table_edit *edit_node
99059e56 19763 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19764 /* Now, sec->size is the size of the section we will write. The original
99059e56 19765 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19766 markers) was sec->rawsize. (This isn't the case if we perform no
19767 edits, then rawsize will be zero and we should use size). */
21d799b5 19768 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19769 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19770 unsigned int in_index, out_index;
19771 bfd_vma add_to_offsets = 0;
19772
19773 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19774 {
2468f9c9
PB		 19775 if (edit_node)
19776 {
19777 unsigned int edit_index = edit_node->index;
b38cadfb 19778
2468f9c9 19779 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19780 {
2468f9c9
PB		 19781 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19782 contents + in_index * 8, add_to_offsets);
19783 out_index++;
19784 in_index++;
19785 }
19786 else if (in_index == edit_index
19787 || (in_index * 8 >= input_size
19788 && edit_index == UINT_MAX))
99059e56 19789 {
2468f9c9
PB		 19790 switch (edit_node->type)
19791 {
19792 case DELETE_EXIDX_ENTRY:
19793 in_index++;
19794 add_to_offsets += 8;
19795 break;
b38cadfb 19796
2468f9c9
PB		 19797 case INSERT_EXIDX_CANTUNWIND_AT_END:
19798 {
99059e56 19799 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19800 bfd_vma text_offset = text_sec->output_section->vma
19801 + text_sec->output_offset
19802 + text_sec->size;
19803 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19804 unsigned long prel31_offset;
2468f9c9
PB		 19805
19806 /* Note: this is meant to be equivalent to an
19807 R_ARM_PREL31 relocation. These synthetic
19808 EXIDX_CANTUNWIND markers are not relocated by the
19809 usual BFD method. */
19810 prel31_offset = (text_offset - exidx_offset)
19811 & 0x7ffffffful;
491d01d3
YU		 19812 if (bfd_link_relocatable (link_info))
19813 {
19814 /* Here relocation for new EXIDX_CANTUNWIND is
19815 created, so there is no need to
19816 adjust offset by hand. */
19817 prel31_offset = text_sec->output_offset
19818 + text_sec->size;
491d01d3 19819 }
2468f9c9
PB		 19820
19821 /* First address we can't unwind. */
19822 bfd_put_32 (output_bfd, prel31_offset,
19823 &edited_contents[out_index * 8]);
19824
19825 /* Code for EXIDX_CANTUNWIND. */
19826 bfd_put_32 (output_bfd, 0x1,
19827 &edited_contents[out_index * 8 + 4]);
19828
19829 out_index++;
19830 add_to_offsets -= 8;
19831 }
19832 break;
19833 }
b38cadfb 19834
2468f9c9
PB		 19835 edit_node = edit_node->next;
19836 }
19837 }
19838 else
19839 {
19840 /* No more edits, copy remaining entries verbatim. */
19841 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19842 contents + in_index * 8, add_to_offsets);
19843 out_index++;
19844 in_index++;
19845 }
19846 }
19847
19848 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19849 bfd_set_section_contents (output_bfd, sec->output_section,
19850 edited_contents,
19851 (file_ptr) sec->output_offset, sec->size);
19852
19853 return TRUE;
19854 }
19855
48229727
JB		 19856 /* Fix code to point to Cortex-A8 erratum stubs. */
19857 if (globals->fix_cortex_a8)
19858 {
19859 struct a8_branch_to_stub_data data;
19860
19861 data.writing_section = sec;
19862 data.contents = contents;
19863
a504d23a
LA		 19864 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19865 & data);
48229727
JB		 19866 }
19867
e489d0ae
PB		 19868 if (mapcount == 0)
19869 return FALSE;
19870
c7b8f16e 19871 if (globals->byteswap_code)
e489d0ae 19872 {
c7b8f16e 19873 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19874
c7b8f16e
JB		 19875 ptr = map[0].vma;
19876 for (i = 0; i < mapcount; i++)
99059e56
RM		 19877 {
19878 if (i == mapcount - 1)
c7b8f16e 19879 end = sec->size;
99059e56
RM		 19880 else
19881 end = map[i + 1].vma;
e489d0ae 19882
99059e56 19883 switch (map[i].type)
e489d0ae 19884 {
c7b8f16e
JB		 19885 case 'a':
19886 /* Byte swap code words. */
19887 while (ptr + 3 < end)
99059e56
RM		 19888 {
19889 tmp = contents[ptr];
19890 contents[ptr] = contents[ptr + 3];
19891 contents[ptr + 3] = tmp;
19892 tmp = contents[ptr + 1];
19893 contents[ptr + 1] = contents[ptr + 2];
19894 contents[ptr + 2] = tmp;
19895 ptr += 4;
19896 }
c7b8f16e 19897 break;
e489d0ae 19898
c7b8f16e
JB		 19899 case 't':
19900 /* Byte swap code halfwords. */
19901 while (ptr + 1 < end)
99059e56
RM		 19902 {
19903 tmp = contents[ptr];
19904 contents[ptr] = contents[ptr + 1];
19905 contents[ptr + 1] = tmp;
19906 ptr += 2;
19907 }
c7b8f16e
JB		 19908 break;
19909
19910 case 'd':
19911 /* Leave data alone. */
19912 break;
19913 }
99059e56
RM		 19914 ptr = end;
19915 }
e489d0ae 19916 }
8e3de13a 19917
93204d3a 19918 free (map);
47b2e99c 19919 arm_data->mapcount = -1;
c7b8f16e 19920 arm_data->mapsize = 0;
8e3de13a 19921 arm_data->map = NULL;
8e3de13a 19922
e489d0ae
PB		 19923 return FALSE;
19924}
19925
0beaef2b
PB		 19926/* Mangle thumb function symbols as we read them in. */
19927
8384fb8f 19928static bfd_boolean
0beaef2b
PB		 19929elf32_arm_swap_symbol_in (bfd * abfd,
19930 const void *psrc,
19931 const void *pshn,
19932 Elf_Internal_Sym *dst)
19933{
8384fb8f
AM		 19934 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19935 return FALSE;
39d911fc 19936 dst->st_target_internal = 0;
0beaef2b
PB		 19937
19938 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19939 the address. */
63e1a0fc
PB		 19940 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19941 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19942 {
63e1a0fc
PB		 19943 if (dst->st_value & 1)
19944 {
19945 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19946 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19947 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19948 }
19949 else
39d911fc 19950 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19951 }
19952 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19953 {
19954 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19955 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19956 }
35fc36a8 19957 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19958 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19959 else
39d911fc 19960 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19961
8384fb8f 19962 return TRUE;
0beaef2b
PB		 19963}
19964
19965
19966/* Mangle thumb function symbols as we write them out. */
19967
19968static void
19969elf32_arm_swap_symbol_out (bfd *abfd,
19970 const Elf_Internal_Sym *src,
19971 void *cdst,
19972 void *shndx)
19973{
19974 Elf_Internal_Sym newsym;
19975
19976 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19977 of the address set, as per the new EABI. We do this unconditionally
19978 because objcopy does not set the elf header flags until after
19979 it writes out the symbol table. */
39d911fc 19980 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19981 {
19982 newsym = *src;
34e77a92
RS		 19983 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19984 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19985 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19986 {
19987 /* Do this only for defined symbols. At link type, the static
19988 linker will simulate the work of dynamic linker of resolving
19989 symbols and will carry over the thumbness of found symbols to
19990 the output symbol table. It's not clear how it happens, but
19991 the thumbness of undefined symbols can well be different at
19992 runtime, and writing '1' for them will be confusing for users
19993 and possibly for dynamic linker itself.
19994 */
19995 newsym.st_value |= 1;
19996 }
906e58ca 19997
0beaef2b
PB		 19998 src = &newsym;
19999 }
20000 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
20001}
20002
b294bdf8
MM		 20003/* Add the PT_ARM_EXIDX program header. */
20004
20005static bfd_boolean
906e58ca 20006elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 20007 struct bfd_link_info *info ATTRIBUTE_UNUSED)
20008{
20009 struct elf_segment_map *m;
20010 asection *sec;
20011
20012 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20013 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20014 {
20015 /* If there is already a PT_ARM_EXIDX header, then we do not
20016 want to add another one. This situation arises when running
20017 "strip"; the input binary already has the header. */
12bd6957 20018 m = elf_seg_map (abfd);
b294bdf8
MM		 20019 while (m && m->p_type != PT_ARM_EXIDX)
20020 m = m->next;
20021 if (!m)
20022 {
21d799b5 20023 m = (struct elf_segment_map *)
99059e56 20024 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 20025 if (m == NULL)
20026 return FALSE;
20027 m->p_type = PT_ARM_EXIDX;
20028 m->count = 1;
20029 m->sections[0] = sec;
20030
12bd6957
AM		 20031 m->next = elf_seg_map (abfd);
20032 elf_seg_map (abfd) = m;
b294bdf8
MM		 20033 }
20034 }
20035
20036 return TRUE;
20037}
20038
20039/* We may add a PT_ARM_EXIDX program header. */
20040
20041static int
a6b96beb
AM		 20042elf32_arm_additional_program_headers (bfd *abfd,
20043 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 20044{
20045 asection *sec;
20046
20047 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20048 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20049 return 1;
20050 else
20051 return 0;
20052}
20053
34e77a92
RS		 20054/* Hook called by the linker routine which adds symbols from an object
20055 file. */
20056
20057static bfd_boolean
20058elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
20059 Elf_Internal_Sym *sym, const char **namep,
20060 flagword *flagsp, asection **secp, bfd_vma *valp)
20061{
c792917c
NC		 20062 if (elf32_arm_hash_table (info) == NULL)
20063 return FALSE;
20064
34e77a92
RS		 20065 if (elf32_arm_hash_table (info)->vxworks_p
20066 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
20067 flagsp, secp, valp))
20068 return FALSE;
20069
20070 return TRUE;
20071}
20072
0beaef2b 20073/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 20074const struct elf_size_info elf32_arm_size_info =
20075{
0beaef2b
PB		 20076 sizeof (Elf32_External_Ehdr),
20077 sizeof (Elf32_External_Phdr),
20078 sizeof (Elf32_External_Shdr),
20079 sizeof (Elf32_External_Rel),
20080 sizeof (Elf32_External_Rela),
20081 sizeof (Elf32_External_Sym),
20082 sizeof (Elf32_External_Dyn),
20083 sizeof (Elf_External_Note),
20084 4,
20085 1,
20086 32, 2,
20087 ELFCLASS32, EV_CURRENT,
20088 bfd_elf32_write_out_phdrs,
20089 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 20090 bfd_elf32_checksum_contents,
0beaef2b
PB		 20091 bfd_elf32_write_relocs,
20092 elf32_arm_swap_symbol_in,
20093 elf32_arm_swap_symbol_out,
20094 bfd_elf32_slurp_reloc_table,
20095 bfd_elf32_slurp_symbol_table,
20096 bfd_elf32_swap_dyn_in,
20097 bfd_elf32_swap_dyn_out,
20098 bfd_elf32_swap_reloc_in,
20099 bfd_elf32_swap_reloc_out,
20100 bfd_elf32_swap_reloca_in,
20101 bfd_elf32_swap_reloca_out
20102};
20103
685e70ae
VK		 20104static bfd_vma
20105read_code32 (const bfd *abfd, const bfd_byte *addr)
20106{
20107 /* V7 BE8 code is always little endian. */
20108 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20109 return bfd_getl32 (addr);
20110
20111 return bfd_get_32 (abfd, addr);
20112}
20113
20114static bfd_vma
20115read_code16 (const bfd *abfd, const bfd_byte *addr)
20116{
20117 /* V7 BE8 code is always little endian. */
20118 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20119 return bfd_getl16 (addr);
20120
20121 return bfd_get_16 (abfd, addr);
20122}
20123
6a631e86
YG		 20124/* Return size of plt0 entry starting at ADDR
20125 or (bfd_vma) -1 if size can not be determined. */
20126
20127static bfd_vma
20128elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
20129{
20130 bfd_vma first_word;
20131 bfd_vma plt0_size;
20132
685e70ae 20133 first_word = read_code32 (abfd, addr);
6a631e86
YG		 20134
20135 if (first_word == elf32_arm_plt0_entry[0])
20136 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
20137 else if (first_word == elf32_thumb2_plt0_entry[0])
20138 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
20139 else
20140 /* We don't yet handle this PLT format. */
20141 return (bfd_vma) -1;
20142
20143 return plt0_size;
20144}
20145
20146/* Return size of plt entry starting at offset OFFSET
20147 of plt section located at address START
20148 or (bfd_vma) -1 if size can not be determined. */
20149
20150static bfd_vma
20151elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
20152{
20153 bfd_vma first_insn;
20154 bfd_vma plt_size = 0;
20155 const bfd_byte *addr = start + offset;
20156
20157 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 20158 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 20159 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
20160
20161 /* Respect Thumb stub if necessary. */
685e70ae 20162 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 20163 {
20164 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
20165 }
20166
20167 /* Strip immediate from first add. */
685e70ae 20168 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 20169
20170#ifdef FOUR_WORD_PLT
20171 if (first_insn == elf32_arm_plt_entry[0])
20172 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20173#else
20174 if (first_insn == elf32_arm_plt_entry_long[0])
20175 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20176 else if (first_insn == elf32_arm_plt_entry_short[0])
20177 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20178#endif
20179 else
20180 /* We don't yet handle this PLT format. */
20181 return (bfd_vma) -1;
20182
20183 return plt_size;
20184}
20185
20186/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20187
20188static long
20189elf32_arm_get_synthetic_symtab (bfd *abfd,
20190 long symcount ATTRIBUTE_UNUSED,
20191 asymbol **syms ATTRIBUTE_UNUSED,
20192 long dynsymcount,
20193 asymbol **dynsyms,
20194 asymbol **ret)
20195{
20196 asection *relplt;
20197 asymbol *s;
20198 arelent *p;
20199 long count, i, n;
20200 size_t size;
20201 Elf_Internal_Shdr *hdr;
20202 char *names;
20203 asection *plt;
20204 bfd_vma offset;
20205 bfd_byte *data;
20206
20207 *ret = NULL;
20208
20209 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20210 return 0;
20211
20212 if (dynsymcount <= 0)
20213 return 0;
20214
20215 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20216 if (relplt == NULL)
20217 return 0;
20218
20219 hdr = &elf_section_data (relplt)->this_hdr;
20220 if (hdr->sh_link != elf_dynsymtab (abfd)
20221 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20222 return 0;
20223
20224 plt = bfd_get_section_by_name (abfd, ".plt");
20225 if (plt == NULL)
20226 return 0;
20227
20228 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20229 return -1;
20230
20231 data = plt->contents;
20232 if (data == NULL)
20233 {
20234 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20235 return -1;
20236 bfd_cache_section_contents((asection *) plt, data);
20237 }
20238
20239 count = relplt->size / hdr->sh_entsize;
20240 size = count * sizeof (asymbol);
20241 p = relplt->relocation;
20242 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20243 {
20244 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20245 if (p->addend != 0)
20246 size += sizeof ("+0x") - 1 + 8;
20247 }
20248
20249 s = *ret = (asymbol *) bfd_malloc (size);
20250 if (s == NULL)
20251 return -1;
20252
20253 offset = elf32_arm_plt0_size (abfd, data);
20254 if (offset == (bfd_vma) -1)
20255 return -1;
20256
20257 names = (char *) (s + count);
20258 p = relplt->relocation;
20259 n = 0;
20260 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20261 {
20262 size_t len;
20263
20264 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20265 if (plt_size == (bfd_vma) -1)
20266 break;
20267
20268 *s = **p->sym_ptr_ptr;
20269 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20270 we are defining a symbol, ensure one of them is set. */
20271 if ((s->flags & BSF_LOCAL) == 0)
20272 s->flags |= BSF_GLOBAL;
20273 s->flags |= BSF_SYNTHETIC;
20274 s->section = plt;
20275 s->value = offset;
20276 s->name = names;
20277 s->udata.p = NULL;
20278 len = strlen ((*p->sym_ptr_ptr)->name);
20279 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20280 names += len;
20281 if (p->addend != 0)
20282 {
20283 char buf[30], *a;
20284
20285 memcpy (names, "+0x", sizeof ("+0x") - 1);
20286 names += sizeof ("+0x") - 1;
20287 bfd_sprintf_vma (abfd, buf, p->addend);
20288 for (a = buf; *a == '0'; ++a)
20289 ;
20290 len = strlen (a);
20291 memcpy (names, a, len);
20292 names += len;
20293 }
20294 memcpy (names, "@plt", sizeof ("@plt"));
20295 names += sizeof ("@plt");
20296 ++s, ++n;
20297 offset += plt_size;
20298 }
20299
20300 return n;
20301}
20302
ac4c9b04
MG		 20303static bfd_boolean
20304elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
20305{
f0728ee3
AV		 20306 if (hdr->sh_flags & SHF_ARM_PURECODE)
20307 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20308 return TRUE;
20309}
20310
20311static flagword
20312elf32_arm_lookup_section_flags (char *flag_name)
20313{
f0728ee3
AV		 20314 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20315 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20316
20317 return SEC_NO_FLAGS;
20318}
20319
491d01d3
YU		 20320static unsigned int
20321elf32_arm_count_additional_relocs (asection *sec)
20322{
20323 struct _arm_elf_section_data *arm_data;
20324 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20325
6342be70 20326 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20327}
20328
5522f910 20329/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20330 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20331 FALSE otherwise. ISECTION is the best guess matching section from the
20332 input bfd IBFD, but it might be NULL. */
20333
20334static bfd_boolean
20335elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20336 bfd *obfd ATTRIBUTE_UNUSED,
20337 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20338 Elf_Internal_Shdr *osection)
20339{
20340 switch (osection->sh_type)
20341 {
20342 case SHT_ARM_EXIDX:
20343 {
20344 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20345 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20346 unsigned i = 0;
20347
20348 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20349 osection->sh_info = 0;
20350
20351 /* The sh_link field must be set to the text section associated with
20352 this index section. Unfortunately the ARM EHABI does not specify
20353 exactly how to determine this association. Our caller does try
20354 to match up OSECTION with its corresponding input section however
20355 so that is a good first guess. */
20356 if (isection != NULL
20357 && osection->bfd_section != NULL
20358 && isection->bfd_section != NULL
20359 && isection->bfd_section->output_section != NULL
20360 && isection->bfd_section->output_section == osection->bfd_section
20361 && iheaders != NULL
20362 && isection->sh_link > 0
20363 && isection->sh_link < elf_numsections (ibfd)
20364 && iheaders[isection->sh_link]->bfd_section != NULL
20365 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20366 )
20367 {
20368 for (i = elf_numsections (obfd); i-- > 0;)
20369 if (oheaders[i]->bfd_section
20370 == iheaders[isection->sh_link]->bfd_section->output_section)
20371 break;
20372 }
9eaff861 20373
5522f910
NC		 20374 if (i == 0)
20375 {
20376 /* Failing that we have to find a matching section ourselves. If
20377 we had the output section name available we could compare that
20378 with input section names. Unfortunately we don't. So instead
20379 we use a simple heuristic and look for the nearest executable
20380 section before this one. */
20381 for (i = elf_numsections (obfd); i-- > 0;)
20382 if (oheaders[i] == osection)
20383 break;
20384 if (i == 0)
20385 break;
20386
20387 while (i-- > 0)
20388 if (oheaders[i]->sh_type == SHT_PROGBITS
20389 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20390 == (SHF_ALLOC | SHF_EXECINSTR))
20391 break;
20392 }
20393
20394 if (i)
20395 {
20396 osection->sh_link = i;
20397 /* If the text section was part of a group
20398 then the index section should be too. */
20399 if (oheaders[i]->sh_flags & SHF_GROUP)
20400 osection->sh_flags |= SHF_GROUP;
20401 return TRUE;
20402 }
20403 }
20404 break;
20405
20406 case SHT_ARM_PREEMPTMAP:
20407 osection->sh_flags = SHF_ALLOC;
20408 break;
20409
20410 case SHT_ARM_ATTRIBUTES:
20411 case SHT_ARM_DEBUGOVERLAY:
20412 case SHT_ARM_OVERLAYSECTION:
20413 default:
20414 break;
20415 }
20416
20417 return FALSE;
20418}
20419
d691934d
NC		 20420/* Returns TRUE if NAME is an ARM mapping symbol.
20421 Traditionally the symbols $a, $d and $t have been used.
20422 The ARM ELF standard also defines $x (for A64 code). It also allows a
20423 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20424 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20425 not support them here. $t.x indicates the start of ThumbEE instructions. */
20426
20427static bfd_boolean
20428is_arm_mapping_symbol (const char * name)
20429{
20430 return name != NULL /* Paranoia. */
20431 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20432 the mapping symbols could have acquired a prefix.
20433 We do not support this here, since such symbols no
20434 longer conform to the ARM ELF ABI. */
20435 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20436 && (name[2] == 0 || name[2] == '.');
20437 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20438 any characters that follow the period are legal characters for the body
20439 of a symbol's name. For now we just assume that this is the case. */
20440}
20441
fca2a38f
NC		 20442/* Make sure that mapping symbols in object files are not removed via the
20443 "strip --strip-unneeded" tool. These symbols are needed in order to
20444 correctly generate interworking veneers, and for byte swapping code
20445 regions. Once an object file has been linked, it is safe to remove the
20446 symbols as they will no longer be needed. */
20447
20448static void
20449elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20450{
20451 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20452 && sym->section != bfd_abs_section_ptr
d691934d 20453 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20454 sym->flags |= BSF_KEEP;
20455}
20456
5522f910
NC		 20457#undef elf_backend_copy_special_section_fields
20458#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20459
252b5132 20460#define ELF_ARCH bfd_arch_arm
ae95ffa6 20461#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20462#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20463#ifdef __QNXTARGET__
20464#define ELF_MAXPAGESIZE 0x1000
20465#else
7572ca89 20466#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20467#endif
b1342370 20468#define ELF_MINPAGESIZE 0x1000
24718e3b 20469#define ELF_COMMONPAGESIZE 0x1000
252b5132 20470
07d6d2b8 20471#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20472
99e4ae17
AJ		 20473#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20474#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20475#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20476#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20477#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20478#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20479#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 20480#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20481#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20482#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20483#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20484#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20485#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20486
07d6d2b8
AM		 20487#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20488#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20489#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20490#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20491#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20492#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20493#define elf_backend_write_section elf32_arm_write_section
252b5132 20494#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20495#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20496#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20497#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20498#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20499#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20500#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 20501#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 20502#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20503#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20504#define elf_backend_fake_sections elf32_arm_fake_sections
20505#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20506#define elf_backend_final_write_processing elf32_arm_final_write_processing
20507#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20508#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20509#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20510#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20511#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20512#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20513#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20514#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20515#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20516#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20517
20518#define elf_backend_can_refcount 1
20519#define elf_backend_can_gc_sections 1
20520#define elf_backend_plt_readonly 1
20521#define elf_backend_want_got_plt 1
20522#define elf_backend_want_plt_sym 0
5474d94f 20523#define elf_backend_want_dynrelro 1
906e58ca
NC		 20524#define elf_backend_may_use_rel_p 1
20525#define elf_backend_may_use_rela_p 0
4e7fd91e 20526#define elf_backend_default_use_rela_p 0
64f52338 20527#define elf_backend_dtrel_excludes_plt 1
252b5132 20528
04f7c78d 20529#define elf_backend_got_header_size 12
b68a20d6 20530#define elf_backend_extern_protected_data 1
04f7c78d 20531
07d6d2b8 20532#undef elf_backend_obj_attrs_vendor
906e58ca 20533#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20534#undef elf_backend_obj_attrs_section
906e58ca 20535#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20536#undef elf_backend_obj_attrs_arg_type
906e58ca 20537#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20538#undef elf_backend_obj_attrs_section_type
104d59d1 20539#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20540#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20541#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20542
07d6d2b8 20543#undef elf_backend_section_flags
ac4c9b04 20544#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20545#undef elf_backend_lookup_section_flags_hook
20546#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20547
a2f63b2e
MR		 20548#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20549
252b5132 20550#include "elf32-target.h"
7f266840 20551
b38cadfb
NC		 20552/* Native Client targets. */
20553
20554#undef TARGET_LITTLE_SYM
6d00b590 20555#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20556#undef TARGET_LITTLE_NAME
20557#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20558#undef TARGET_BIG_SYM
6d00b590 20559#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20560#undef TARGET_BIG_NAME
20561#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20562
20563/* Like elf32_arm_link_hash_table_create -- but overrides
20564 appropriately for NaCl. */
20565
20566static struct bfd_link_hash_table *
20567elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20568{
20569 struct bfd_link_hash_table *ret;
20570
20571 ret = elf32_arm_link_hash_table_create (abfd);
20572 if (ret)
20573 {
20574 struct elf32_arm_link_hash_table *htab
20575 = (struct elf32_arm_link_hash_table *) ret;
20576
20577 htab->nacl_p = 1;
20578
20579 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20580 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20581 }
20582 return ret;
20583}
20584
20585/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20586 really need to use elf32_arm_modify_segment_map. But we do it
20587 anyway just to reduce gratuitous differences with the stock ARM backend. */
20588
20589static bfd_boolean
20590elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20591{
20592 return (elf32_arm_modify_segment_map (abfd, info)
20593 && nacl_modify_segment_map (abfd, info));
20594}
20595
cc364be6
AM		 20596static bfd_boolean
20597elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20598{
cc364be6
AM		 20599 arm_final_write_processing (abfd);
20600 return nacl_final_write_processing (abfd);
887badb3
RM		 20601}
20602
6a631e86
YG		 20603static bfd_vma
20604elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20605 const arelent *rel ATTRIBUTE_UNUSED)
20606{
20607 return plt->vma
20608 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20609 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20610}
887badb3 20611
b38cadfb 20612#undef elf32_bed
6a631e86 20613#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20614#undef bfd_elf32_bfd_link_hash_table_create
20615#define bfd_elf32_bfd_link_hash_table_create \
20616 elf32_arm_nacl_link_hash_table_create
20617#undef elf_backend_plt_alignment
6a631e86 20618#define elf_backend_plt_alignment 4
b38cadfb
NC		 20619#undef elf_backend_modify_segment_map
20620#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20621#undef elf_backend_modify_program_headers
20622#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 20623#undef elf_backend_final_write_processing
20624#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20625#undef bfd_elf32_get_synthetic_symtab
20626#undef elf_backend_plt_sym_val
20627#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20628#undef elf_backend_copy_special_section_fields
b38cadfb 20629
887badb3
RM		 20630#undef ELF_MINPAGESIZE
20631#undef ELF_COMMONPAGESIZE
20632
b38cadfb
NC		 20633
20634#include "elf32-target.h"
20635
20636/* Reset to defaults. */
20637#undef elf_backend_plt_alignment
20638#undef elf_backend_modify_segment_map
20639#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20640#undef elf_backend_modify_program_headers
887badb3
RM		 20641#undef elf_backend_final_write_processing
20642#define elf_backend_final_write_processing elf32_arm_final_write_processing
20643#undef ELF_MINPAGESIZE
20644#define ELF_MINPAGESIZE 0x1000
20645#undef ELF_COMMONPAGESIZE
20646#define ELF_COMMONPAGESIZE 0x1000
20647
b38cadfb 20648
617a5ada
CL		 20649/* FDPIC Targets. */
20650
20651#undef TARGET_LITTLE_SYM
20652#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20653#undef TARGET_LITTLE_NAME
20654#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20655#undef TARGET_BIG_SYM
20656#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20657#undef TARGET_BIG_NAME
20658#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20659#undef elf_match_priority
20660#define elf_match_priority 128
18a20338
CL		 20661#undef ELF_OSABI
20662#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20663
20664/* Like elf32_arm_link_hash_table_create -- but overrides
20665 appropriately for FDPIC. */
20666
20667static struct bfd_link_hash_table *
20668elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20669{
20670 struct bfd_link_hash_table *ret;
20671
20672 ret = elf32_arm_link_hash_table_create (abfd);
20673 if (ret)
20674 {
20675 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20676
20677 htab->fdpic_p = 1;
20678 }
20679 return ret;
20680}
20681
e8b09b87
CL		 20682/* We need dynamic symbols for every section, since segments can
20683 relocate independently. */
20684static bfd_boolean
20685elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20686 struct bfd_link_info *info
20687 ATTRIBUTE_UNUSED,
20688 asection *p ATTRIBUTE_UNUSED)
20689{
20690 switch (elf_section_data (p)->this_hdr.sh_type)
20691 {
20692 case SHT_PROGBITS:
20693 case SHT_NOBITS:
20694 /* If sh_type is yet undecided, assume it could be
20695 SHT_PROGBITS/SHT_NOBITS. */
20696 case SHT_NULL:
20697 return FALSE;
20698
20699 /* There shouldn't be section relative relocations
20700 against any other section. */
20701 default:
20702 return TRUE;
20703 }
20704}
20705
617a5ada
CL		 20706#undef elf32_bed
20707#define elf32_bed elf32_arm_fdpic_bed
20708
20709#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20710#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20711
e8b09b87
CL		 20712#undef elf_backend_omit_section_dynsym
20713#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20714
617a5ada 20715#include "elf32-target.h"
e8b09b87 20716
617a5ada 20717#undef elf_match_priority
18a20338 20718#undef ELF_OSABI
e8b09b87 20719#undef elf_backend_omit_section_dynsym
617a5ada 20720
906e58ca 20721/* VxWorks Targets. */
4e7fd91e 20722
07d6d2b8
AM		 20723#undef TARGET_LITTLE_SYM
20724#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20725#undef TARGET_LITTLE_NAME
20726#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20727#undef TARGET_BIG_SYM
20728#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20729#undef TARGET_BIG_NAME
20730#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20731
20732/* Like elf32_arm_link_hash_table_create -- but overrides
20733 appropriately for VxWorks. */
906e58ca 20734
4e7fd91e
PB		 20735static struct bfd_link_hash_table *
20736elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20737{
20738 struct bfd_link_hash_table *ret;
20739
20740 ret = elf32_arm_link_hash_table_create (abfd);
20741 if (ret)
20742 {
20743 struct elf32_arm_link_hash_table *htab
00a97672 20744 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20745 htab->use_rel = 0;
00a97672 20746 htab->vxworks_p = 1;
4e7fd91e
PB		 20747 }
20748 return ret;
906e58ca 20749}
4e7fd91e 20750
cc364be6
AM		 20751static bfd_boolean
20752elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20753{
cc364be6
AM		 20754 arm_final_write_processing (abfd);
20755 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20756}
20757
906e58ca 20758#undef elf32_bed
4e7fd91e
PB		 20759#define elf32_bed elf32_arm_vxworks_bed
20760
906e58ca
NC		 20761#undef bfd_elf32_bfd_link_hash_table_create
20762#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20763#undef elf_backend_final_write_processing
20764#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20765#undef elf_backend_emit_relocs
9eaff861 20766#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20767
906e58ca 20768#undef elf_backend_may_use_rel_p
00a97672 20769#define elf_backend_may_use_rel_p 0
906e58ca 20770#undef elf_backend_may_use_rela_p
00a97672 20771#define elf_backend_may_use_rela_p 1
906e58ca 20772#undef elf_backend_default_use_rela_p
00a97672 20773#define elf_backend_default_use_rela_p 1
906e58ca 20774#undef elf_backend_want_plt_sym
00a97672 20775#define elf_backend_want_plt_sym 1
906e58ca 20776#undef ELF_MAXPAGESIZE
00a97672 20777#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20778
20779#include "elf32-target.h"
20780
20781
21d799b5
NC		 20782/* Merge backend specific data from an object file to the output
20783 object file when linking. */
20784
20785static bfd_boolean
50e03d47 20786elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20787{
50e03d47 20788 bfd *obfd = info->output_bfd;
21d799b5
NC		 20789 flagword out_flags;
20790 flagword in_flags;
20791 bfd_boolean flags_compatible = TRUE;
20792 asection *sec;
20793
cc643b88 20794 /* Check if we have the same endianness. */
50e03d47 20795 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20796 return FALSE;
20797
20798 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20799 return TRUE;
20800
50e03d47 20801 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20802 return FALSE;
20803
20804 /* The input BFD must have had its flags initialised. */
20805 /* The following seems bogus to me -- The flags are initialized in
20806 the assembler but I don't think an elf_flags_init field is
20807 written into the object. */
20808 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20809
20810 in_flags = elf_elfheader (ibfd)->e_flags;
20811 out_flags = elf_elfheader (obfd)->e_flags;
20812
20813 /* In theory there is no reason why we couldn't handle this. However
20814 in practice it isn't even close to working and there is no real
20815 reason to want it. */
20816 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20817 && !(ibfd->flags & DYNAMIC)
20818 && (in_flags & EF_ARM_BE8))
20819 {
871b3ab2 20820 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20821 ibfd);
20822 return FALSE;
20823 }
20824
20825 if (!elf_flags_init (obfd))
20826 {
20827 /* If the input is the default architecture and had the default
20828 flags then do not bother setting the flags for the output
20829 architecture, instead allow future merges to do this. If no
20830 future merges ever set these flags then they will retain their
99059e56
RM		 20831 uninitialised values, which surprise surprise, correspond
20832 to the default values. */
21d799b5
NC		 20833 if (bfd_get_arch_info (ibfd)->the_default
20834 && elf_elfheader (ibfd)->e_flags == 0)
20835 return TRUE;
20836
20837 elf_flags_init (obfd) = TRUE;
20838 elf_elfheader (obfd)->e_flags = in_flags;
20839
20840 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20841 && bfd_get_arch_info (obfd)->the_default)
20842 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20843
20844 return TRUE;
20845 }
20846
20847 /* Determine what should happen if the input ARM architecture
20848 does not match the output ARM architecture. */
20849 if (! bfd_arm_merge_machines (ibfd, obfd))
20850 return FALSE;
20851
20852 /* Identical flags must be compatible. */
20853 if (in_flags == out_flags)
20854 return TRUE;
20855
20856 /* Check to see if the input BFD actually contains any sections. If
20857 not, its flags may not have been initialised either, but it
20858 cannot actually cause any incompatiblity. Do not short-circuit
20859 dynamic objects; their section list may be emptied by
20860 elf_link_add_object_symbols.
20861
20862 Also check to see if there are no code sections in the input.
20863 In this case there is no need to check for code specific flags.
20864 XXX - do we need to worry about floating-point format compatability
20865 in data sections ? */
20866 if (!(ibfd->flags & DYNAMIC))
20867 {
20868 bfd_boolean null_input_bfd = TRUE;
20869 bfd_boolean only_data_sections = TRUE;
20870
20871 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20872 {
20873 /* Ignore synthetic glue sections. */
20874 if (strcmp (sec->name, ".glue_7")
20875 && strcmp (sec->name, ".glue_7t"))
20876 {
20877 if ((bfd_get_section_flags (ibfd, sec)
20878 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20879 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20880 only_data_sections = FALSE;
21d799b5
NC		 20881
20882 null_input_bfd = FALSE;
20883 break;
20884 }
20885 }
20886
20887 if (null_input_bfd || only_data_sections)
20888 return TRUE;
20889 }
20890
20891 /* Complain about various flag mismatches. */
20892 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20893 EF_ARM_EABI_VERSION (out_flags)))
20894 {
20895 _bfd_error_handler
90b6238f 20896 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20897 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20898 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20899 return FALSE;
20900 }
20901
20902 /* Not sure what needs to be checked for EABI versions >= 1. */
20903 /* VxWorks libraries do not use these flags. */
20904 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20905 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20906 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20907 {
20908 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20909 {
20910 _bfd_error_handler
871b3ab2 20911 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20912 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20913 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20914 flags_compatible = FALSE;
20915 }
20916
20917 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20918 {
20919 if (in_flags & EF_ARM_APCS_FLOAT)
20920 _bfd_error_handler
871b3ab2 20921 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20922 ibfd, obfd);
20923 else
20924 _bfd_error_handler
871b3ab2 20925 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20926 ibfd, obfd);
20927
20928 flags_compatible = FALSE;
20929 }
20930
20931 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20932 {
20933 if (in_flags & EF_ARM_VFP_FLOAT)
20934 _bfd_error_handler
90b6238f
AM		 20935 (_("error: %pB uses %s instructions, whereas %pB does not"),
20936 ibfd, "VFP", obfd);
21d799b5
NC		 20937 else
20938 _bfd_error_handler
90b6238f
AM		 20939 (_("error: %pB uses %s instructions, whereas %pB does not"),
20940 ibfd, "FPA", obfd);
21d799b5
NC		 20941
20942 flags_compatible = FALSE;
20943 }
20944
20945 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20946 {
20947 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20948 _bfd_error_handler
90b6238f
AM		 20949 (_("error: %pB uses %s instructions, whereas %pB does not"),
20950 ibfd, "Maverick", obfd);
21d799b5
NC		 20951 else
20952 _bfd_error_handler
90b6238f
AM		 20953 (_("error: %pB does not use %s instructions, whereas %pB does"),
20954 ibfd, "Maverick", obfd);
21d799b5
NC		 20955
20956 flags_compatible = FALSE;
20957 }
20958
20959#ifdef EF_ARM_SOFT_FLOAT
20960 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20961 {
20962 /* We can allow interworking between code that is VFP format
20963 layout, and uses either soft float or integer regs for
20964 passing floating point arguments and results. We already
20965 know that the APCS_FLOAT flags match; similarly for VFP
20966 flags. */
20967 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20968 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20969 {
20970 if (in_flags & EF_ARM_SOFT_FLOAT)
20971 _bfd_error_handler
871b3ab2 20972 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20973 ibfd, obfd);
20974 else
20975 _bfd_error_handler
871b3ab2 20976 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20977 ibfd, obfd);
20978
20979 flags_compatible = FALSE;
20980 }
20981 }
20982#endif
20983
20984 /* Interworking mismatch is only a warning. */
20985 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20986 {
20987 if (in_flags & EF_ARM_INTERWORK)
20988 {
20989 _bfd_error_handler
90b6238f 20990 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20991 ibfd, obfd);
20992 }
20993 else
20994 {
20995 _bfd_error_handler
90b6238f 20996 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20997 ibfd, obfd);
20998 }
20999 }
21000 }
21001
21002 return flags_compatible;
21003}
21004
21005
906e58ca 21006/* Symbian OS Targets. */
7f266840 21007
07d6d2b8
AM		 21008#undef TARGET_LITTLE_SYM
21009#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
21010#undef TARGET_LITTLE_NAME
21011#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
21012#undef TARGET_BIG_SYM
21013#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
21014#undef TARGET_BIG_NAME
21015#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 21016
21017/* Like elf32_arm_link_hash_table_create -- but overrides
21018 appropriately for Symbian OS. */
906e58ca 21019
7f266840
DJ		 21020static struct bfd_link_hash_table *
21021elf32_arm_symbian_link_hash_table_create (bfd *abfd)
21022{
21023 struct bfd_link_hash_table *ret;
21024
21025 ret = elf32_arm_link_hash_table_create (abfd);
21026 if (ret)
21027 {
21028 struct elf32_arm_link_hash_table *htab
21029 = (struct elf32_arm_link_hash_table *)ret;
21030 /* There is no PLT header for Symbian OS. */
21031 htab->plt_header_size = 0;
95720a86
DJ		 21032 /* The PLT entries are each one instruction and one word. */
21033 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 21034 htab->symbian_p = 1;
33bfe774
JB		 21035 /* Symbian uses armv5t or above, so use_blx is always true. */
21036 htab->use_blx = 1;
67687978 21037 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 21038 }
21039 return ret;
906e58ca 21040}
7f266840 21041
b35d266b 21042static const struct bfd_elf_special_section
551b43fd 21043elf32_arm_symbian_special_sections[] =
7f266840 21044{
5cd3778d
MM		 21045 /* In a BPABI executable, the dynamic linking sections do not go in
21046 the loadable read-only segment. The post-linker may wish to
21047 refer to these sections, but they are not part of the final
21048 program image. */
07d6d2b8
AM		 21049 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
21050 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
21051 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
21052 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
21053 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 21054 /* These sections do not need to be writable as the SymbianOS
21055 postlinker will arrange things so that no dynamic relocation is
21056 required. */
07d6d2b8
AM		 21057 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
21058 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 21059 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 21060 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 21061};
21062
c3c76620 21063static void
906e58ca 21064elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 21065 struct bfd_link_info *link_info)
c3c76620
MM		 21066{
21067 /* BPABI objects are never loaded directly by an OS kernel; they are
21068 processed by a postlinker first, into an OS-specific format. If
21069 the D_PAGED bit is set on the file, BFD will align segments on
21070 page boundaries, so that an OS can directly map the file. With
21071 BPABI objects, that just results in wasted space. In addition,
21072 because we clear the D_PAGED bit, map_sections_to_segments will
21073 recognize that the program headers should not be mapped into any
21074 loadable segment. */
21075 abfd->flags &= ~D_PAGED;
906e58ca 21076 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 21077}
7f266840
DJ		 21078
21079static bfd_boolean
906e58ca 21080elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 21081 struct bfd_link_info *info)
7f266840
DJ		 21082{
21083 struct elf_segment_map *m;
21084 asection *dynsec;
21085
7f266840
DJ		 21086 /* BPABI shared libraries and executables should have a PT_DYNAMIC
21087 segment. However, because the .dynamic section is not marked
21088 with SEC_LOAD, the generic ELF code will not create such a
21089 segment. */
21090 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
21091 if (dynsec)
21092 {
12bd6957 21093 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 21094 if (m->p_type == PT_DYNAMIC)
21095 break;
21096
21097 if (m == NULL)
21098 {
21099 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 21100 m->next = elf_seg_map (abfd);
21101 elf_seg_map (abfd) = m;
8ded5a0f 21102 }
7f266840
DJ		 21103 }
21104
b294bdf8
MM		 21105 /* Also call the generic arm routine. */
21106 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 21107}
21108
95720a86
DJ		 21109/* Return address for Ith PLT stub in section PLT, for relocation REL
21110 or (bfd_vma) -1 if it should not be included. */
21111
21112static bfd_vma
21113elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
21114 const arelent *rel ATTRIBUTE_UNUSED)
21115{
21116 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
21117}
21118
8029a119 21119#undef elf32_bed
7f266840
DJ		 21120#define elf32_bed elf32_arm_symbian_bed
21121
21122/* The dynamic sections are not allocated on SymbianOS; the postlinker
21123 will process them and then discard them. */
906e58ca 21124#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 21125#define ELF_DYNAMIC_SEC_FLAGS \
21126 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
21127
9eaff861 21128#undef elf_backend_emit_relocs
c3c76620 21129
906e58ca
NC		 21130#undef bfd_elf32_bfd_link_hash_table_create
21131#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
21132#undef elf_backend_special_sections
07d6d2b8 21133#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 21134#undef elf_backend_begin_write_processing
21135#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
21136#undef elf_backend_final_write_processing
21137#define elf_backend_final_write_processing elf32_arm_final_write_processing
21138
21139#undef elf_backend_modify_segment_map
7f266840
DJ		 21140#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
21141
21142/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 21143#undef elf_backend_got_header_size
7f266840
DJ		 21144#define elf_backend_got_header_size 0
21145
21146/* Similarly, there is no .got.plt section. */
906e58ca 21147#undef elf_backend_want_got_plt
7f266840
DJ		 21148#define elf_backend_want_got_plt 0
21149
906e58ca 21150#undef elf_backend_plt_sym_val
95720a86
DJ		 21151#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21152
906e58ca 21153#undef elf_backend_may_use_rel_p
00a97672 21154#define elf_backend_may_use_rel_p 1
906e58ca 21155#undef elf_backend_may_use_rela_p
00a97672 21156#define elf_backend_may_use_rela_p 0
906e58ca 21157#undef elf_backend_default_use_rela_p
00a97672 21158#define elf_backend_default_use_rela_p 0
906e58ca 21159#undef elf_backend_want_plt_sym
00a97672 21160#define elf_backend_want_plt_sym 0
64f52338
AM		 21161#undef elf_backend_dtrel_excludes_plt
21162#define elf_backend_dtrel_excludes_plt 0
906e58ca 21163#undef ELF_MAXPAGESIZE
00a97672 21164#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 21165
7f266840 21166#include "elf32-target.h"
GDB Binutils - Deliverables
This page took 5.771832 seconds and 4 git commands to generate.