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[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
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252b5132 1/* 32-bit ELF support for ARM
219d1afa 2 Copyright (C) 1998-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
f3185997 59#define elf_info_to_howto NULL
07d6d2b8 60#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
07d6d2b8 240 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
99059e56
RM		 334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
07d6d2b8 340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
99059e56
RM		 348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
07d6d2b8 354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
99059e56
RM		 362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
07d6d2b8 368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
99059e56
RM		 378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
07d6d2b8 384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
99059e56
RM		 392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
07d6d2b8 398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
99059e56
RM		 406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
07d6d2b8 412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
99059e56
RM		 420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
07d6d2b8 426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
99059e56
RM		 434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
07d6d2b8 440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
99059e56 446 TRUE, /* pc_relative */
07d6d2b8 447 0, /* bitpos */
99059e56
RM		 448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
99059e56 460 FALSE, /* pc_relative */
07d6d2b8 461 0, /* bitpos */
99059e56
RM		 462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
99059e56 474 TRUE, /* pc_relative */
07d6d2b8 475 0, /* bitpos */
99059e56
RM		 476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
07d6d2b8 909 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 917 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
07d6d2b8 937 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 945 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
07d6d2b8 951 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 959 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
07d6d2b8 965 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 973 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
07d6d2b8 979 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 987 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
07d6d2b8 993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1001 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
07d6d2b8 1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1015 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
07d6d2b8 1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1029 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
07d6d2b8 1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1043 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
07d6d2b8 1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1057 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
07d6d2b8 1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1071 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
07d6d2b8 1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1085 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
07d6d2b8 1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1099 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
07d6d2b8 1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1113 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
07d6d2b8 1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1127 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
07d6d2b8 1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1141 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
07d6d2b8 1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1155 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
07d6d2b8 1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1169 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
07d6d2b8 1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1183 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
07d6d2b8 1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1197 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
07d6d2b8 1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1211 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
07d6d2b8 1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1225 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
07d6d2b8 1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1239 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
07d6d2b8 1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1253 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
07d6d2b8 1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1267 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
07d6d2b8 1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1486
1487 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
99059e56 1494 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
99059e56 1509 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1510 NULL, /* special_function */
99059e56 1511 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
99059e56
RM		 1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
07d6d2b8 1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
99059e56
RM		 1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
07d6d2b8 1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
99059e56
RM		 1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
07d6d2b8 1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
99059e56
RM		 1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
07d6d2b8 1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
99059e56 1608 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
07d6d2b8 1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92 1748/* 160 onwards: */
5c5a4843 1749static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
99059e56
RM		 1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
188fd7ae
CL		 1763 FALSE), /* pcrel_offset */
1764 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1765 0, /* rightshift */
1766 2, /* size (0 = byte, 1 = short, 2 = long) */
1767 32, /* bitsize */
1768 FALSE, /* pc_relative */
1769 0, /* bitpos */
1770 complain_overflow_bitfield,/* complain_on_overflow */
1771 bfd_elf_generic_reloc, /* special_function */
1772 "R_ARM_GOTFUNCDESC", /* name */
1773 FALSE, /* partial_inplace */
1774 0, /* src_mask */
1775 0xffffffff, /* dst_mask */
1776 FALSE), /* pcrel_offset */
1777 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1778 0, /* rightshift */
1779 2, /* size (0 = byte, 1 = short, 2 = long) */
1780 32, /* bitsize */
1781 FALSE, /* pc_relative */
1782 0, /* bitpos */
1783 complain_overflow_bitfield,/* complain_on_overflow */
1784 bfd_elf_generic_reloc, /* special_function */
1785 "R_ARM_GOTOFFFUNCDESC",/* name */
1786 FALSE, /* partial_inplace */
1787 0, /* src_mask */
1788 0xffffffff, /* dst_mask */
1789 FALSE), /* pcrel_offset */
1790 HOWTO (R_ARM_FUNCDESC, /* type */
1791 0, /* rightshift */
1792 2, /* size (0 = byte, 1 = short, 2 = long) */
1793 32, /* bitsize */
1794 FALSE, /* pc_relative */
1795 0, /* bitpos */
1796 complain_overflow_bitfield,/* complain_on_overflow */
1797 bfd_elf_generic_reloc, /* special_function */
1798 "R_ARM_FUNCDESC", /* name */
1799 FALSE, /* partial_inplace */
1800 0, /* src_mask */
1801 0xffffffff, /* dst_mask */
1802 FALSE), /* pcrel_offset */
1803 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1804 0, /* rightshift */
1805 2, /* size (0 = byte, 1 = short, 2 = long) */
1806 64, /* bitsize */
1807 FALSE, /* pc_relative */
1808 0, /* bitpos */
1809 complain_overflow_bitfield,/* complain_on_overflow */
1810 bfd_elf_generic_reloc, /* special_function */
1811 "R_ARM_FUNCDESC_VALUE",/* name */
1812 FALSE, /* partial_inplace */
1813 0, /* src_mask */
1814 0xffffffff, /* dst_mask */
1815 FALSE), /* pcrel_offset */
5c5a4843
CL		 1816 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1817 0, /* rightshift */
1818 2, /* size (0 = byte, 1 = short, 2 = long) */
1819 32, /* bitsize */
1820 FALSE, /* pc_relative */
1821 0, /* bitpos */
1822 complain_overflow_bitfield,/* complain_on_overflow */
1823 bfd_elf_generic_reloc, /* special_function */
1824 "R_ARM_TLS_GD32_FDPIC",/* name */
1825 FALSE, /* partial_inplace */
1826 0, /* src_mask */
1827 0xffffffff, /* dst_mask */
1828 FALSE), /* pcrel_offset */
1829 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1830 0, /* rightshift */
1831 2, /* size (0 = byte, 1 = short, 2 = long) */
1832 32, /* bitsize */
1833 FALSE, /* pc_relative */
1834 0, /* bitpos */
1835 complain_overflow_bitfield,/* complain_on_overflow */
1836 bfd_elf_generic_reloc, /* special_function */
1837 "R_ARM_TLS_LDM32_FDPIC",/* name */
1838 FALSE, /* partial_inplace */
1839 0, /* src_mask */
1840 0xffffffff, /* dst_mask */
1841 FALSE), /* pcrel_offset */
1842 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1843 0, /* rightshift */
1844 2, /* size (0 = byte, 1 = short, 2 = long) */
1845 32, /* bitsize */
1846 FALSE, /* pc_relative */
1847 0, /* bitpos */
1848 complain_overflow_bitfield,/* complain_on_overflow */
1849 bfd_elf_generic_reloc, /* special_function */
1850 "R_ARM_TLS_IE32_FDPIC",/* name */
1851 FALSE, /* partial_inplace */
1852 0, /* src_mask */
1853 0xffffffff, /* dst_mask */
1854 FALSE), /* pcrel_offset */
34e77a92 1855};
c19d1205 1856
34e77a92
RS		 1857/* 249-255 extended, currently unused, relocations: */
1858static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1859{
1860 HOWTO (R_ARM_RREL32, /* type */
1861 0, /* rightshift */
1862 0, /* size (0 = byte, 1 = short, 2 = long) */
1863 0, /* bitsize */
1864 FALSE, /* pc_relative */
1865 0, /* bitpos */
1866 complain_overflow_dont,/* complain_on_overflow */
1867 bfd_elf_generic_reloc, /* special_function */
1868 "R_ARM_RREL32", /* name */
1869 FALSE, /* partial_inplace */
1870 0, /* src_mask */
1871 0, /* dst_mask */
1872 FALSE), /* pcrel_offset */
1873
1874 HOWTO (R_ARM_RABS32, /* type */
1875 0, /* rightshift */
1876 0, /* size (0 = byte, 1 = short, 2 = long) */
1877 0, /* bitsize */
1878 FALSE, /* pc_relative */
1879 0, /* bitpos */
1880 complain_overflow_dont,/* complain_on_overflow */
1881 bfd_elf_generic_reloc, /* special_function */
1882 "R_ARM_RABS32", /* name */
1883 FALSE, /* partial_inplace */
1884 0, /* src_mask */
1885 0, /* dst_mask */
1886 FALSE), /* pcrel_offset */
1887
1888 HOWTO (R_ARM_RPC24, /* type */
1889 0, /* rightshift */
1890 0, /* size (0 = byte, 1 = short, 2 = long) */
1891 0, /* bitsize */
1892 FALSE, /* pc_relative */
1893 0, /* bitpos */
1894 complain_overflow_dont,/* complain_on_overflow */
1895 bfd_elf_generic_reloc, /* special_function */
1896 "R_ARM_RPC24", /* name */
1897 FALSE, /* partial_inplace */
1898 0, /* src_mask */
1899 0, /* dst_mask */
1900 FALSE), /* pcrel_offset */
1901
1902 HOWTO (R_ARM_RBASE, /* type */
1903 0, /* rightshift */
1904 0, /* size (0 = byte, 1 = short, 2 = long) */
1905 0, /* bitsize */
1906 FALSE, /* pc_relative */
1907 0, /* bitpos */
1908 complain_overflow_dont,/* complain_on_overflow */
1909 bfd_elf_generic_reloc, /* special_function */
1910 "R_ARM_RBASE", /* name */
1911 FALSE, /* partial_inplace */
1912 0, /* src_mask */
1913 0, /* dst_mask */
1914 FALSE) /* pcrel_offset */
1915};
1916
1917static reloc_howto_type *
1918elf32_arm_howto_from_type (unsigned int r_type)
1919{
906e58ca 1920 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1921 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1922
188fd7ae
CL		 1923 if (r_type >= R_ARM_IRELATIVE
1924 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1925 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1926
c19d1205 1927 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1928 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1929 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1930
c19d1205 1931 return NULL;
7f266840
DJ		 1932}
1933
f3185997
NC		 1934static bfd_boolean
1935elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1936 Elf_Internal_Rela * elf_reloc)
1937{
1938 unsigned int r_type;
1939
1940 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1941 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1942 {
1943 /* xgettext:c-format */
1944 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1945 abfd, r_type);
1946 bfd_set_error (bfd_error_bad_value);
1947 return FALSE;
1948 }
1949 return TRUE;
7f266840
DJ		 1950}
1951
1952struct elf32_arm_reloc_map
1953 {
1954 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1955 unsigned char elf_reloc_val;
7f266840
DJ		 1956 };
1957
1958/* All entries in this list must also be present in elf32_arm_howto_table. */
1959static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1960 {
07d6d2b8 1961 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 1962 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1963 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1964 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 1965 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1966 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1967 {BFD_RELOC_32, R_ARM_ABS32},
1968 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1969 {BFD_RELOC_8, R_ARM_ABS8},
1970 {BFD_RELOC_16, R_ARM_ABS16},
1971 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 1972 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1973 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1974 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1975 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1976 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1977 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1978 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 1979 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1980 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1981 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
1982 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
1983 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
1984 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
1985 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1986 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 1987 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1988 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1989 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1990 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 1991 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 1992 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1993 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1994 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 1995 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 1996 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 1997 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 1998 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1999 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2000 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2001 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2002 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2003 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2004 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2005 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2006 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2007 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2008 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2009 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2010 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2011 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2012 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2013 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2014 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2015 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2016 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2017 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2018 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2019 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2020 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2021 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2022 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2023 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2024 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2025 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2026 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2027 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2028 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2029 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2030 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2031 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2032 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2033 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2034 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2035 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2036 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2037 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2038 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2039 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2040 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2041 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2042 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2043 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2044 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2045 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2046 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2047 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2048 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2049 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2050 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2051 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2052 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2053 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2054 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2055 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2056 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
2057 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 2058 };
2059
2060static reloc_howto_type *
f1c71a59
ZW		 2061elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2062 bfd_reloc_code_real_type code)
7f266840
DJ		 2063{
2064 unsigned int i;
8029a119 2065
906e58ca 2066 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2067 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2068 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2069
c19d1205 2070 return NULL;
7f266840
DJ		 2071}
2072
157090f7
AM		 2073static reloc_howto_type *
2074elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2075 const char *r_name)
2076{
2077 unsigned int i;
2078
906e58ca 2079 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2080 if (elf32_arm_howto_table_1[i].name != NULL
2081 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2082 return &elf32_arm_howto_table_1[i];
2083
906e58ca 2084 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2085 if (elf32_arm_howto_table_2[i].name != NULL
2086 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2087 return &elf32_arm_howto_table_2[i];
2088
34e77a92
RS		 2089 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2090 if (elf32_arm_howto_table_3[i].name != NULL
2091 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2092 return &elf32_arm_howto_table_3[i];
2093
157090f7
AM		 2094 return NULL;
2095}
2096
906e58ca
NC		 2097/* Support for core dump NOTE sections. */
2098
7f266840 2099static bfd_boolean
f1c71a59 2100elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2101{
2102 int offset;
2103 size_t size;
2104
2105 switch (note->descsz)
2106 {
2107 default:
2108 return FALSE;
2109
8029a119 2110 case 148: /* Linux/ARM 32-bit. */
7f266840 2111 /* pr_cursig */
228e534f 2112 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2113
2114 /* pr_pid */
228e534f 2115 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2116
2117 /* pr_reg */
2118 offset = 72;
2119 size = 72;
2120
2121 break;
2122 }
2123
2124 /* Make a ".reg/999" section. */
2125 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2126 size, note->descpos + offset);
2127}
2128
2129static bfd_boolean
f1c71a59 2130elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2131{
2132 switch (note->descsz)
2133 {
2134 default:
2135 return FALSE;
2136
8029a119 2137 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2138 elf_tdata (abfd)->core->pid
4395ee08 2139 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2140 elf_tdata (abfd)->core->program
7f266840 2141 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2142 elf_tdata (abfd)->core->command
7f266840
DJ		 2143 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2144 }
2145
2146 /* Note that for some reason, a spurious space is tacked
2147 onto the end of the args in some (at least one anyway)
2148 implementations, so strip it off if it exists. */
7f266840 2149 {
228e534f 2150 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2151 int n = strlen (command);
2152
2153 if (0 < n && command[n - 1] == ' ')
2154 command[n - 1] = '\0';
2155 }
2156
2157 return TRUE;
2158}
2159
1f20dca5
UW		 2160static char *
2161elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2162 int note_type, ...)
2163{
2164 switch (note_type)
2165 {
2166 default:
2167 return NULL;
2168
2169 case NT_PRPSINFO:
2170 {
602f1657 2171 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2172 va_list ap;
2173
2174 va_start (ap, note_type);
2175 memset (data, 0, sizeof (data));
2176 strncpy (data + 28, va_arg (ap, const char *), 16);
fe75810f 2177#if GCC_VERSION == 8001
95da9854
L		 2178 DIAGNOSTIC_PUSH;
2179 /* GCC 8.1 warns about 80 equals destination size with
2180 -Wstringop-truncation:
2181 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2182 */
95da9854
L		 2183 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2184#endif
1f20dca5 2185 strncpy (data + 44, va_arg (ap, const char *), 80);
fe75810f 2186#if GCC_VERSION == 8001
95da9854 2187 DIAGNOSTIC_POP;
fe75810f 2188#endif
1f20dca5
UW		 2189 va_end (ap);
2190
2191 return elfcore_write_note (abfd, buf, bufsiz,
2192 "CORE", note_type, data, sizeof (data));
2193 }
2194
2195 case NT_PRSTATUS:
2196 {
2197 char data[148];
2198 va_list ap;
2199 long pid;
2200 int cursig;
2201 const void *greg;
2202
2203 va_start (ap, note_type);
2204 memset (data, 0, sizeof (data));
2205 pid = va_arg (ap, long);
2206 bfd_put_32 (abfd, pid, data + 24);
2207 cursig = va_arg (ap, int);
2208 bfd_put_16 (abfd, cursig, data + 12);
2209 greg = va_arg (ap, const void *);
2210 memcpy (data + 72, greg, 72);
2211 va_end (ap);
2212
2213 return elfcore_write_note (abfd, buf, bufsiz,
2214 "CORE", note_type, data, sizeof (data));
2215 }
2216 }
2217}
2218
07d6d2b8
AM		 2219#define TARGET_LITTLE_SYM arm_elf32_le_vec
2220#define TARGET_LITTLE_NAME "elf32-littlearm"
2221#define TARGET_BIG_SYM arm_elf32_be_vec
2222#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2223
2224#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2225#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2226#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2227
252b5132
RH		 2228typedef unsigned long int insn32;
2229typedef unsigned short int insn16;
2230
3a4a14e9
PB		 2231/* In lieu of proper flags, assume all EABIv4 or later objects are
2232 interworkable. */
57e8b36a 2233#define INTERWORK_FLAG(abfd) \
3a4a14e9 2234 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2235 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2236 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2237
252b5132
RH		 2238/* The linker script knows the section names for placement.
2239 The entry_names are used to do simple name mangling on the stubs.
2240 Given a function name, and its type, the stub can be found. The
9b485d32 2241 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2242#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2243#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2244
2245#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2246#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2247
c7b8f16e
JB		 2248#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2249#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2250
a504d23a
LA		 2251#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2252#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2253
845b51d6
PB		 2254#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2255#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2256
7413f23f
DJ		 2257#define STUB_ENTRY_NAME "__%s_veneer"
2258
4ba2ef8f
TP		 2259#define CMSE_PREFIX "__acle_se_"
2260
252b5132
RH		 2261/* The name of the dynamic interpreter. This is put in the .interp
2262 section. */
2263#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2264
cb10292c
CL		 2265/* FDPIC default stack size. */
2266#define DEFAULT_STACK_SIZE 0x8000
2267
0855e32b 2268static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2269{
2270 0xe08e0000, /* add r0, lr, r0 */
2271 0xe5901004, /* ldr r1, [r0,#4] */
2272 0xe12fff11, /* bx r1 */
2273};
0855e32b
NS		 2274
2275static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2276{
2277 0xe52d2004, /* push {r2} */
2278 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2279 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2280 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2281 0xe081100f, /* 2: add r1, pc */
2282 0xe12fff12, /* bx r2 */
2283 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2284 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2285 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2286};
0855e32b 2287
7801f98f
CL		 2288/* ARM FDPIC PLT entry. */
2289/* The last 5 words contain PLT lazy fragment code and data. */
2290static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2291 {
2292 0xe59fc008, /* ldr r12, .L1 */
2293 0xe08cc009, /* add r12, r12, r9 */
2294 0xe59c9004, /* ldr r9, [r12, #4] */
2295 0xe59cf000, /* ldr pc, [r12] */
2296 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2297 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2298 0xe51fc00c, /* ldr r12, [pc, #-12] */
2299 0xe92d1000, /* push {r12} */
2300 0xe599c004, /* ldr r12, [r9, #4] */
2301 0xe599f000, /* ldr pc, [r9] */
2302 };
2303
59029f57
CL		 2304/* Thumb FDPIC PLT entry. */
2305/* The last 5 words contain PLT lazy fragment code and data. */
2306static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2307 {
2308 0xc00cf8df, /* ldr.w r12, .L1 */
2309 0x0c09eb0c, /* add.w r12, r12, r9 */
2310 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2311 0xf000f8dc, /* ldr.w pc, [r12] */
2312 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2313 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2314 0xc008f85f, /* ldr.w r12, .L2 */
2315 0xcd04f84d, /* push {r12} */
2316 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2317 0xf000f8d9, /* ldr.w pc, [r9] */
2318 };
2319
5e681ec4
PB		 2320#ifdef FOUR_WORD_PLT
2321
252b5132
RH		 2322/* The first entry in a procedure linkage table looks like
2323 this. It is set up so that any shared library function that is
59f2c4e7 2324 called before the relocation has been set up calls the dynamic
9b485d32 2325 linker first. */
e5a52504 2326static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2327{
2328 0xe52de004, /* str lr, [sp, #-4]! */
2329 0xe59fe010, /* ldr lr, [pc, #16] */
2330 0xe08fe00e, /* add lr, pc, lr */
2331 0xe5bef008, /* ldr pc, [lr, #8]! */
2332};
5e681ec4
PB		 2333
2334/* Subsequent entries in a procedure linkage table look like
2335 this. */
e5a52504 2336static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2337{
2338 0xe28fc600, /* add ip, pc, #NN */
2339 0xe28cca00, /* add ip, ip, #NN */
2340 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2341 0x00000000, /* unused */
2342};
5e681ec4 2343
eed94f8f 2344#else /* not FOUR_WORD_PLT */
5e681ec4 2345
5e681ec4
PB		 2346/* The first entry in a procedure linkage table looks like
2347 this. It is set up so that any shared library function that is
2348 called before the relocation has been set up calls the dynamic
2349 linker first. */
e5a52504 2350static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2351{
07d6d2b8
AM		 2352 0xe52de004, /* str lr, [sp, #-4]! */
2353 0xe59fe004, /* ldr lr, [pc, #4] */
2354 0xe08fe00e, /* add lr, pc, lr */
2355 0xe5bef008, /* ldr pc, [lr, #8]! */
2356 0x00000000, /* &GOT[0] - . */
b38cadfb 2357};
252b5132 2358
1db37fe6
YG		 2359/* By default subsequent entries in a procedure linkage table look like
2360 this. Offsets that don't fit into 28 bits will cause link error. */
2361static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2362{
2363 0xe28fc600, /* add ip, pc, #0xNN00000 */
2364 0xe28cca00, /* add ip, ip, #0xNN000 */
2365 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2366};
5e681ec4 2367
1db37fe6
YG		 2368/* When explicitly asked, we'll use this "long" entry format
2369 which can cope with arbitrary displacements. */
2370static const bfd_vma elf32_arm_plt_entry_long [] =
2371{
07d6d2b8
AM		 2372 0xe28fc200, /* add ip, pc, #0xN0000000 */
2373 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2374 0xe28cca00, /* add ip, ip, #0xNN000 */
2375 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2376};
2377
2378static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2379
eed94f8f
NC		 2380#endif /* not FOUR_WORD_PLT */
2381
2382/* The first entry in a procedure linkage table looks like this.
2383 It is set up so that any shared library function that is called before the
2384 relocation has been set up calls the dynamic linker first. */
2385static const bfd_vma elf32_thumb2_plt0_entry [] =
2386{
2387 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2388 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2389 0xf8dfb500, /* push {lr} */
2390 0x44fee008, /* ldr.w lr, [pc, #8] */
2391 /* add lr, pc */
eed94f8f 2392 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2393 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2394};
2395
2396/* Subsequent entries in a procedure linkage table for thumb only target
2397 look like this. */
2398static const bfd_vma elf32_thumb2_plt_entry [] =
2399{
2400 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2401 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2402 0x0c00f240, /* movw ip, #0xNNNN */
2403 0x0c00f2c0, /* movt ip, #0xNNNN */
2404 0xf8dc44fc, /* add ip, pc */
2405 0xbf00f000 /* ldr.w pc, [ip] */
2406 /* nop */
eed94f8f 2407};
252b5132 2408
00a97672
RS		 2409/* The format of the first entry in the procedure linkage table
2410 for a VxWorks executable. */
2411static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2412{
07d6d2b8
AM		 2413 0xe52dc008, /* str ip,[sp,#-8]! */
2414 0xe59fc000, /* ldr ip,[pc] */
2415 0xe59cf008, /* ldr pc,[ip,#8] */
2416 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2417};
00a97672
RS		 2418
2419/* The format of subsequent entries in a VxWorks executable. */
2420static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2421{
07d6d2b8
AM		 2422 0xe59fc000, /* ldr ip,[pc] */
2423 0xe59cf000, /* ldr pc,[ip] */
2424 0x00000000, /* .long @got */
2425 0xe59fc000, /* ldr ip,[pc] */
2426 0xea000000, /* b _PLT */
2427 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2428};
00a97672
RS		 2429
2430/* The format of entries in a VxWorks shared library. */
2431static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2432{
07d6d2b8
AM		 2433 0xe59fc000, /* ldr ip,[pc] */
2434 0xe79cf009, /* ldr pc,[ip,r9] */
2435 0x00000000, /* .long @got */
2436 0xe59fc000, /* ldr ip,[pc] */
2437 0xe599f008, /* ldr pc,[r9,#8] */
2438 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2439};
00a97672 2440
b7693d02
DJ		 2441/* An initial stub used if the PLT entry is referenced from Thumb code. */
2442#define PLT_THUMB_STUB_SIZE 4
2443static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2444{
2445 0x4778, /* bx pc */
2446 0x46c0 /* nop */
2447};
b7693d02 2448
e5a52504
MM		 2449/* The entries in a PLT when using a DLL-based target with multiple
2450 address spaces. */
906e58ca 2451static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2452{
07d6d2b8
AM		 2453 0xe51ff004, /* ldr pc, [pc, #-4] */
2454 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2455};
2456
2457/* The first entry in a procedure linkage table looks like
2458 this. It is set up so that any shared library function that is
2459 called before the relocation has been set up calls the dynamic
2460 linker first. */
2461static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2462{
2463 /* First bundle: */
2464 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2465 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2466 0xe08cc00f, /* add ip, ip, pc */
2467 0xe52dc008, /* str ip, [sp, #-8]! */
2468 /* Second bundle: */
edccdf7c
RM		 2469 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2470 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2471 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2472 0xe12fff1c, /* bx ip */
b38cadfb 2473 /* Third bundle: */
edccdf7c
RM		 2474 0xe320f000, /* nop */
2475 0xe320f000, /* nop */
2476 0xe320f000, /* nop */
b38cadfb
NC		 2477 /* .Lplt_tail: */
2478 0xe50dc004, /* str ip, [sp, #-4] */
2479 /* Fourth bundle: */
edccdf7c
RM		 2480 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2481 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2482 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2483 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2484};
2485#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2486
2487/* Subsequent entries in a procedure linkage table look like this. */
2488static const bfd_vma elf32_arm_nacl_plt_entry [] =
2489{
2490 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2491 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2492 0xe08cc00f, /* add ip, ip, pc */
2493 0xea000000, /* b .Lplt_tail */
2494};
e5a52504 2495
906e58ca
NC		 2496#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2497#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2498#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2499#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2500#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2501#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2502#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2503#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2504
461a49ca 2505enum stub_insn_type
b38cadfb
NC		 2506{
2507 THUMB16_TYPE = 1,
2508 THUMB32_TYPE,
2509 ARM_TYPE,
2510 DATA_TYPE
2511};
461a49ca 2512
48229727
JB		 2513#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2514/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2515 is inserted in arm_build_one_stub(). */
2516#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2517#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2518#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2519#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2520#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2521#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2522#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2523#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2524
2525typedef struct
2526{
07d6d2b8 2527 bfd_vma data;
b38cadfb 2528 enum stub_insn_type type;
07d6d2b8
AM		 2529 unsigned int r_type;
2530 int reloc_addend;
461a49ca
DJ		 2531} insn_sequence;
2532
fea2b4d6
CL		 2533/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2534 to reach the stub if necessary. */
461a49ca 2535static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2536{
07d6d2b8 2537 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2538 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2539};
906e58ca 2540
fea2b4d6
CL		 2541/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2542 available. */
461a49ca 2543static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2544{
07d6d2b8
AM		 2545 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2546 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2547 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2548};
906e58ca 2549
d3626fb0 2550/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2551static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2552{
07d6d2b8
AM		 2553 THUMB16_INSN (0xb401), /* push {r0} */
2554 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2555 THUMB16_INSN (0x4684), /* mov ip, r0 */
2556 THUMB16_INSN (0xbc01), /* pop {r0} */
2557 THUMB16_INSN (0x4760), /* bx ip */
2558 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2559 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2560};
906e58ca 2561
80c135e5
TP		 2562/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2563static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2564{
07d6d2b8 2565 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2566 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2567};
2568
d5a67c02
AV		 2569/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2570 M-profile architectures. */
2571static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2572{
2573 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2574 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2575 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2576};
2577
d3626fb0
CL		 2578/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2579 allowed. */
2580static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2581{
07d6d2b8
AM		 2582 THUMB16_INSN (0x4778), /* bx pc */
2583 THUMB16_INSN (0x46c0), /* nop */
2584 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2585 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2586 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2587};
d3626fb0 2588
fea2b4d6
CL		 2589/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2590 available. */
461a49ca 2591static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2592{
07d6d2b8
AM		 2593 THUMB16_INSN (0x4778), /* bx pc */
2594 THUMB16_INSN (0x46c0), /* nop */
2595 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2596 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2597};
906e58ca 2598
fea2b4d6
CL		 2599/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2600 one, when the destination is close enough. */
461a49ca 2601static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2602{
07d6d2b8
AM		 2603 THUMB16_INSN (0x4778), /* bx pc */
2604 THUMB16_INSN (0x46c0), /* nop */
b38cadfb
NC		 2605 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2606};
c820be07 2607
cf3eccff 2608/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2609 blx to reach the stub if necessary. */
cf3eccff 2610static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2611{
07d6d2b8
AM		 2612 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2613 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2614 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2615};
906e58ca 2616
cf3eccff
DJ		 2617/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2618 blx to reach the stub if necessary. We can not add into pc;
2619 it is not guaranteed to mode switch (different in ARMv6 and
2620 ARMv7). */
2621static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2622{
07d6d2b8
AM		 2623 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2624 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2625 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2626 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2627};
cf3eccff 2628
ebe24dd4
CL		 2629/* V4T ARM -> ARM long branch stub, PIC. */
2630static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2631{
07d6d2b8
AM		 2632 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2633 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2634 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2635 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2636};
ebe24dd4
CL		 2637
2638/* V4T Thumb -> ARM long branch stub, PIC. */
2639static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2640{
07d6d2b8
AM		 2641 THUMB16_INSN (0x4778), /* bx pc */
2642 THUMB16_INSN (0x46c0), /* nop */
2643 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2644 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2645 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2646};
ebe24dd4 2647
d3626fb0
CL		 2648/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2649 architectures. */
ebe24dd4 2650static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2651{
07d6d2b8
AM		 2652 THUMB16_INSN (0xb401), /* push {r0} */
2653 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2654 THUMB16_INSN (0x46fc), /* mov ip, pc */
2655 THUMB16_INSN (0x4484), /* add ip, r0 */
2656 THUMB16_INSN (0xbc01), /* pop {r0} */
2657 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2658 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2659};
ebe24dd4 2660
d3626fb0
CL		 2661/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2662 allowed. */
2663static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 THUMB16_INSN (0x4778), /* bx pc */
2666 THUMB16_INSN (0x46c0), /* nop */
2667 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2668 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2669 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2670 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2671};
d3626fb0 2672
0855e32b
NS		 2673/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2674 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2675static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2676{
07d6d2b8
AM		 2677 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2678 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2679 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2680};
2681
2682/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2683 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2684static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2685{
07d6d2b8
AM		 2686 THUMB16_INSN (0x4778), /* bx pc */
2687 THUMB16_INSN (0x46c0), /* nop */
2688 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2689 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2690 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2691};
2692
7a89b94e
NC		 2693/* NaCl ARM -> ARM long branch stub. */
2694static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2695{
2696 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2697 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2698 ARM_INSN (0xe12fff1c), /* bx ip */
2699 ARM_INSN (0xe320f000), /* nop */
2700 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2701 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2702 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2703 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2704};
2705
2706/* NaCl ARM -> ARM long branch stub, PIC. */
2707static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2708{
2709 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2710 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2711 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2712 ARM_INSN (0xe12fff1c), /* bx ip */
2713 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2714 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2715 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2716 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2717};
2718
4ba2ef8f
TP		 2719/* Stub used for transition to secure state (aka SG veneer). */
2720static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2721{
2722 THUMB32_INSN (0xe97fe97f), /* sg. */
2723 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2724};
2725
7a89b94e 2726
48229727
JB		 2727/* Cortex-A8 erratum-workaround stubs. */
2728
2729/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2730 can't use a conditional branch to reach this stub). */
2731
2732static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2733{
07d6d2b8 2734 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2735 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2736 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2737};
48229727
JB		 2738
2739/* Stub used for b.w and bl.w instructions. */
2740
2741static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2742{
2743 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2744};
48229727
JB		 2745
2746static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2747{
2748 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2749};
48229727
JB		 2750
2751/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2752 instruction (which switches to ARM mode) to point to this stub. Jump to the
2753 real destination using an ARM-mode branch. */
2754
2755static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2756{
2757 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2758};
48229727 2759
9553db3c
NC		 2760/* For each section group there can be a specially created linker section
2761 to hold the stubs for that group. The name of the stub section is based
2762 upon the name of another section within that group with the suffix below
2763 applied.
2764
2765 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2766 create what appeared to be a linker stub section when it actually
2767 contained user code/data. For example, consider this fragment:
b38cadfb 2768
9553db3c
NC		 2769 const char * stubborn_problems[] = { "np" };
2770
2771 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2772 section called:
2773
2774 .data.rel.local.stubborn_problems
2775
2776 This then causes problems in arm32_arm_build_stubs() as it triggers:
2777
2778 // Ignore non-stub sections.
2779 if (!strstr (stub_sec->name, STUB_SUFFIX))
2780 continue;
2781
2782 And so the section would be ignored instead of being processed. Hence
2783 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2784 C identifier. */
2785#define STUB_SUFFIX ".__stub"
906e58ca 2786
738a79f6
CL		 2787/* One entry per long/short branch stub defined above. */
2788#define DEF_STUBS \
2789 DEF_STUB(long_branch_any_any) \
2790 DEF_STUB(long_branch_v4t_arm_thumb) \
2791 DEF_STUB(long_branch_thumb_only) \
2792 DEF_STUB(long_branch_v4t_thumb_thumb) \
2793 DEF_STUB(long_branch_v4t_thumb_arm) \
2794 DEF_STUB(short_branch_v4t_thumb_arm) \
2795 DEF_STUB(long_branch_any_arm_pic) \
2796 DEF_STUB(long_branch_any_thumb_pic) \
2797 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2798 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2799 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2800 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2801 DEF_STUB(long_branch_any_tls_pic) \
2802 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2803 DEF_STUB(long_branch_arm_nacl) \
2804 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2805 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2806 DEF_STUB(a8_veneer_b_cond) \
2807 DEF_STUB(a8_veneer_b) \
2808 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2809 DEF_STUB(a8_veneer_blx) \
2810 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2811 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2812
2813#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2814enum elf32_arm_stub_type
2815{
906e58ca 2816 arm_stub_none,
738a79f6 2817 DEF_STUBS
4f4faa4d 2818 max_stub_type
738a79f6
CL		 2819};
2820#undef DEF_STUB
2821
8d9d9490
TP		 2822/* Note the first a8_veneer type. */
2823const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2824
738a79f6
CL		 2825typedef struct
2826{
d3ce72d0 2827 const insn_sequence* template_sequence;
738a79f6
CL		 2828 int template_size;
2829} stub_def;
2830
2831#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2832static const stub_def stub_definitions[] =
2833{
738a79f6
CL		 2834 {NULL, 0},
2835 DEF_STUBS
906e58ca
NC		 2836};
2837
2838struct elf32_arm_stub_hash_entry
2839{
2840 /* Base hash table entry structure. */
2841 struct bfd_hash_entry root;
2842
2843 /* The stub section. */
2844 asection *stub_sec;
2845
2846 /* Offset within stub_sec of the beginning of this stub. */
2847 bfd_vma stub_offset;
2848
2849 /* Given the symbol's value and its section we can determine its final
2850 value when building the stubs (so the stub knows where to jump). */
2851 bfd_vma target_value;
2852 asection *target_section;
2853
8d9d9490
TP		 2854 /* Same as above but for the source of the branch to the stub. Used for
2855 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2856 such, source section does not need to be recorded since Cortex-A8 erratum
2857 workaround stubs are only generated when both source and target are in the
2858 same section. */
2859 bfd_vma source_value;
48229727
JB		 2860
2861 /* The instruction which caused this stub to be generated (only valid for
2862 Cortex-A8 erratum workaround stubs at present). */
2863 unsigned long orig_insn;
2864
461a49ca 2865 /* The stub type. */
906e58ca 2866 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2867 /* Its encoding size in bytes. */
2868 int stub_size;
2869 /* Its template. */
2870 const insn_sequence *stub_template;
2871 /* The size of the template (number of entries). */
2872 int stub_template_size;
906e58ca
NC		 2873
2874 /* The symbol table entry, if any, that this was derived from. */
2875 struct elf32_arm_link_hash_entry *h;
2876
35fc36a8
RS		 2877 /* Type of branch. */
2878 enum arm_st_branch_type branch_type;
906e58ca
NC		 2879
2880 /* Where this stub is being called from, or, in the case of combined
2881 stub sections, the first input section in the group. */
2882 asection *id_sec;
7413f23f
DJ		 2883
2884 /* The name for the local symbol at the start of this stub. The
2885 stub name in the hash table has to be unique; this does not, so
2886 it can be friendlier. */
2887 char *output_name;
906e58ca
NC		 2888};
2889
e489d0ae
PB		 2890/* Used to build a map of a section. This is required for mixed-endian
2891 code/data. */
2892
2893typedef struct elf32_elf_section_map
2894{
2895 bfd_vma vma;
2896 char type;
2897}
2898elf32_arm_section_map;
2899
c7b8f16e
JB		 2900/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2901
2902typedef enum
2903{
2904 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2905 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2906 VFP11_ERRATUM_ARM_VENEER,
2907 VFP11_ERRATUM_THUMB_VENEER
2908}
2909elf32_vfp11_erratum_type;
2910
2911typedef struct elf32_vfp11_erratum_list
2912{
2913 struct elf32_vfp11_erratum_list *next;
2914 bfd_vma vma;
2915 union
2916 {
2917 struct
2918 {
2919 struct elf32_vfp11_erratum_list *veneer;
2920 unsigned int vfp_insn;
2921 } b;
2922 struct
2923 {
2924 struct elf32_vfp11_erratum_list *branch;
2925 unsigned int id;
2926 } v;
2927 } u;
2928 elf32_vfp11_erratum_type type;
2929}
2930elf32_vfp11_erratum_list;
2931
a504d23a
LA		 2932/* Information about a STM32L4XX erratum veneer, or a branch to such a
2933 veneer. */
2934typedef enum
2935{
2936 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2937 STM32L4XX_ERRATUM_VENEER
2938}
2939elf32_stm32l4xx_erratum_type;
2940
2941typedef struct elf32_stm32l4xx_erratum_list
2942{
2943 struct elf32_stm32l4xx_erratum_list *next;
2944 bfd_vma vma;
2945 union
2946 {
2947 struct
2948 {
2949 struct elf32_stm32l4xx_erratum_list *veneer;
2950 unsigned int insn;
2951 } b;
2952 struct
2953 {
2954 struct elf32_stm32l4xx_erratum_list *branch;
2955 unsigned int id;
2956 } v;
2957 } u;
2958 elf32_stm32l4xx_erratum_type type;
2959}
2960elf32_stm32l4xx_erratum_list;
2961
2468f9c9
PB		 2962typedef enum
2963{
2964 DELETE_EXIDX_ENTRY,
2965 INSERT_EXIDX_CANTUNWIND_AT_END
2966}
2967arm_unwind_edit_type;
2968
2969/* A (sorted) list of edits to apply to an unwind table. */
2970typedef struct arm_unwind_table_edit
2971{
2972 arm_unwind_edit_type type;
2973 /* Note: we sometimes want to insert an unwind entry corresponding to a
2974 section different from the one we're currently writing out, so record the
2975 (text) section this edit relates to here. */
2976 asection *linked_section;
2977 unsigned int index;
2978 struct arm_unwind_table_edit *next;
2979}
2980arm_unwind_table_edit;
2981
8e3de13a 2982typedef struct _arm_elf_section_data
e489d0ae 2983{
2468f9c9 2984 /* Information about mapping symbols. */
e489d0ae 2985 struct bfd_elf_section_data elf;
8e3de13a 2986 unsigned int mapcount;
c7b8f16e 2987 unsigned int mapsize;
e489d0ae 2988 elf32_arm_section_map *map;
2468f9c9 2989 /* Information about CPU errata. */
c7b8f16e
JB		 2990 unsigned int erratumcount;
2991 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2992 unsigned int stm32l4xx_erratumcount;
2993 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2994 unsigned int additional_reloc_count;
2468f9c9
PB		 2995 /* Information about unwind tables. */
2996 union
2997 {
2998 /* Unwind info attached to a text section. */
2999 struct
3000 {
3001 asection *arm_exidx_sec;
3002 } text;
3003
3004 /* Unwind info attached to an .ARM.exidx section. */
3005 struct
3006 {
3007 arm_unwind_table_edit *unwind_edit_list;
3008 arm_unwind_table_edit *unwind_edit_tail;
3009 } exidx;
3010 } u;
8e3de13a
NC		 3011}
3012_arm_elf_section_data;
e489d0ae
PB		 3013
3014#define elf32_arm_section_data(sec) \
8e3de13a 3015 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3016
48229727
JB		 3017/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3018 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3019 so may be created multiple times: we use an array of these entries whilst
3020 relaxing which we can refresh easily, then create stubs for each potentially
3021 erratum-triggering instruction once we've settled on a solution. */
3022
b38cadfb
NC		 3023struct a8_erratum_fix
3024{
48229727
JB		 3025 bfd *input_bfd;
3026 asection *section;
3027 bfd_vma offset;
8d9d9490 3028 bfd_vma target_offset;
48229727
JB		 3029 unsigned long orig_insn;
3030 char *stub_name;
3031 enum elf32_arm_stub_type stub_type;
35fc36a8 3032 enum arm_st_branch_type branch_type;
48229727
JB		 3033};
3034
3035/* A table of relocs applied to branches which might trigger Cortex-A8
3036 erratum. */
3037
b38cadfb
NC		 3038struct a8_erratum_reloc
3039{
48229727
JB		 3040 bfd_vma from;
3041 bfd_vma destination;
92750f34
DJ		 3042 struct elf32_arm_link_hash_entry *hash;
3043 const char *sym_name;
48229727 3044 unsigned int r_type;
35fc36a8 3045 enum arm_st_branch_type branch_type;
48229727
JB		 3046 bfd_boolean non_a8_stub;
3047};
3048
ba93b8ac
DJ		 3049/* The size of the thread control block. */
3050#define TCB_SIZE 8
3051
34e77a92
RS		 3052/* ARM-specific information about a PLT entry, over and above the usual
3053 gotplt_union. */
b38cadfb
NC		 3054struct arm_plt_info
3055{
34e77a92
RS		 3056 /* We reference count Thumb references to a PLT entry separately,
3057 so that we can emit the Thumb trampoline only if needed. */
3058 bfd_signed_vma thumb_refcount;
3059
3060 /* Some references from Thumb code may be eliminated by BL->BLX
3061 conversion, so record them separately. */
3062 bfd_signed_vma maybe_thumb_refcount;
3063
3064 /* How many of the recorded PLT accesses were from non-call relocations.
3065 This information is useful when deciding whether anything takes the
3066 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3067 non-call references to the function should resolve directly to the
3068 real runtime target. */
3069 unsigned int noncall_refcount;
3070
3071 /* Since PLT entries have variable size if the Thumb prologue is
3072 used, we need to record the index into .got.plt instead of
3073 recomputing it from the PLT offset. */
3074 bfd_signed_vma got_offset;
3075};
3076
3077/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3078struct arm_local_iplt_info
3079{
34e77a92
RS		 3080 /* The information that is usually found in the generic ELF part of
3081 the hash table entry. */
3082 union gotplt_union root;
3083
3084 /* The information that is usually found in the ARM-specific part of
3085 the hash table entry. */
3086 struct arm_plt_info arm;
3087
3088 /* A list of all potential dynamic relocations against this symbol. */
3089 struct elf_dyn_relocs *dyn_relocs;
3090};
3091
e8b09b87
CL		 3092/* Structure to handle FDPIC support for local functions. */
3093struct fdpic_local {
3094 unsigned int funcdesc_cnt;
3095 unsigned int gotofffuncdesc_cnt;
3096 int funcdesc_offset;
3097};
3098
0ffa91dd 3099struct elf_arm_obj_tdata
ba93b8ac
DJ		 3100{
3101 struct elf_obj_tdata root;
3102
3103 /* tls_type for each local got entry. */
3104 char *local_got_tls_type;
ee065d83 3105
0855e32b
NS		 3106 /* GOTPLT entries for TLS descriptors. */
3107 bfd_vma *local_tlsdesc_gotent;
3108
34e77a92
RS		 3109 /* Information for local symbols that need entries in .iplt. */
3110 struct arm_local_iplt_info **local_iplt;
3111
bf21ed78
MS		 3112 /* Zero to warn when linking objects with incompatible enum sizes. */
3113 int no_enum_size_warning;
a9dc9481
JM		 3114
3115 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3116 int no_wchar_size_warning;
e8b09b87
CL		 3117
3118 /* Maintains FDPIC counters and funcdesc info. */
3119 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3120};
3121
0ffa91dd
NC		 3122#define elf_arm_tdata(bfd) \
3123 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3124
0ffa91dd
NC		 3125#define elf32_arm_local_got_tls_type(bfd) \
3126 (elf_arm_tdata (bfd)->local_got_tls_type)
3127
0855e32b
NS		 3128#define elf32_arm_local_tlsdesc_gotent(bfd) \
3129 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3130
34e77a92
RS		 3131#define elf32_arm_local_iplt(bfd) \
3132 (elf_arm_tdata (bfd)->local_iplt)
3133
e8b09b87
CL		 3134#define elf32_arm_local_fdpic_cnts(bfd) \
3135 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3136
0ffa91dd
NC		 3137#define is_arm_elf(bfd) \
3138 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3139 && elf_tdata (bfd) != NULL \
4dfe6ac6 3140 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3141
3142static bfd_boolean
3143elf32_arm_mkobject (bfd *abfd)
3144{
0ffa91dd 3145 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3146 ARM_ELF_DATA);
ba93b8ac
DJ		 3147}
3148
ba93b8ac
DJ		 3149#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3150
e8b09b87
CL		 3151/* Structure to handle FDPIC support for extern functions. */
3152struct fdpic_global {
3153 unsigned int gotofffuncdesc_cnt;
3154 unsigned int gotfuncdesc_cnt;
3155 unsigned int funcdesc_cnt;
3156 int funcdesc_offset;
3157 int gotfuncdesc_offset;
3158};
3159
ba96a88f 3160/* Arm ELF linker hash entry. */
252b5132 3161struct elf32_arm_link_hash_entry
b38cadfb
NC		 3162{
3163 struct elf_link_hash_entry root;
252b5132 3164
b38cadfb
NC		 3165 /* Track dynamic relocs copied for this symbol. */
3166 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3167
b38cadfb
NC		 3168 /* ARM-specific PLT information. */
3169 struct arm_plt_info plt;
ba93b8ac
DJ		 3170
3171#define GOT_UNKNOWN 0
3172#define GOT_NORMAL 1
3173#define GOT_TLS_GD 2
3174#define GOT_TLS_IE 4
0855e32b
NS		 3175#define GOT_TLS_GDESC 8
3176#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3177 unsigned int tls_type : 8;
34e77a92 3178
b38cadfb
NC		 3179 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3180 unsigned int is_iplt : 1;
34e77a92 3181
b38cadfb 3182 unsigned int unused : 23;
a4fd1a8e 3183
b38cadfb
NC		 3184 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3185 starting at the end of the jump table. */
3186 bfd_vma tlsdesc_got;
0855e32b 3187
b38cadfb
NC		 3188 /* The symbol marking the real symbol location for exported thumb
3189 symbols with Arm stubs. */
3190 struct elf_link_hash_entry *export_glue;
906e58ca 3191
b38cadfb 3192 /* A pointer to the most recently used stub hash entry against this
8029a119 3193 symbol. */
b38cadfb 3194 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3195
3196 /* Counter for FDPIC relocations against this symbol. */
3197 struct fdpic_global fdpic_cnts;
b38cadfb 3198};
252b5132 3199
252b5132 3200/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3201#define elf32_arm_link_hash_traverse(table, func, info) \
3202 (elf_link_hash_traverse \
3203 (&(table)->root, \
b7693d02 3204 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3205 (info)))
3206
3207/* Get the ARM elf linker hash table from a link_info structure. */
3208#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3209 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3210 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3211
906e58ca
NC		 3212#define arm_stub_hash_lookup(table, string, create, copy) \
3213 ((struct elf32_arm_stub_hash_entry *) \
3214 bfd_hash_lookup ((table), (string), (create), (copy)))
3215
21d799b5
NC		 3216/* Array to keep track of which stub sections have been created, and
3217 information on stub grouping. */
3218struct map_stub
3219{
3220 /* This is the section to which stubs in the group will be
3221 attached. */
3222 asection *link_sec;
3223 /* The stub section. */
3224 asection *stub_sec;
3225};
3226
0855e32b
NS		 3227#define elf32_arm_compute_jump_table_size(htab) \
3228 ((htab)->next_tls_desc_index * 4)
3229
9b485d32 3230/* ARM ELF linker hash table. */
252b5132 3231struct elf32_arm_link_hash_table
906e58ca
NC		 3232{
3233 /* The main hash table. */
3234 struct elf_link_hash_table root;
252b5132 3235
906e58ca
NC		 3236 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3237 bfd_size_type thumb_glue_size;
252b5132 3238
906e58ca
NC		 3239 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3240 bfd_size_type arm_glue_size;
252b5132 3241
906e58ca
NC		 3242 /* The size in bytes of section containing the ARMv4 BX veneers. */
3243 bfd_size_type bx_glue_size;
845b51d6 3244
906e58ca
NC		 3245 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3246 veneer has been populated. */
3247 bfd_vma bx_glue_offset[15];
845b51d6 3248
906e58ca
NC		 3249 /* The size in bytes of the section containing glue for VFP11 erratum
3250 veneers. */
3251 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3252
a504d23a
LA		 3253 /* The size in bytes of the section containing glue for STM32L4XX erratum
3254 veneers. */
3255 bfd_size_type stm32l4xx_erratum_glue_size;
3256
48229727
JB		 3257 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3258 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3259 elf32_arm_write_section(). */
3260 struct a8_erratum_fix *a8_erratum_fixes;
3261 unsigned int num_a8_erratum_fixes;
3262
906e58ca
NC		 3263 /* An arbitrary input BFD chosen to hold the glue sections. */
3264 bfd * bfd_of_glue_owner;
ba96a88f 3265
906e58ca
NC		 3266 /* Nonzero to output a BE8 image. */
3267 int byteswap_code;
e489d0ae 3268
906e58ca
NC		 3269 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3270 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3271 int target1_is_rel;
9c504268 3272
906e58ca
NC		 3273 /* The relocation to use for R_ARM_TARGET2 relocations. */
3274 int target2_reloc;
eb043451 3275
906e58ca
NC		 3276 /* 0 = Ignore R_ARM_V4BX.
3277 1 = Convert BX to MOV PC.
3278 2 = Generate v4 interworing stubs. */
3279 int fix_v4bx;
319850b4 3280
48229727
JB		 3281 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3282 int fix_cortex_a8;
3283
2de70689
MGD		 3284 /* Whether we should fix the ARM1176 BLX immediate issue. */
3285 int fix_arm1176;
3286
906e58ca
NC		 3287 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3288 int use_blx;
33bfe774 3289
906e58ca
NC		 3290 /* What sort of code sequences we should look for which may trigger the
3291 VFP11 denorm erratum. */
3292 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3293
906e58ca
NC		 3294 /* Global counter for the number of fixes we have emitted. */
3295 int num_vfp11_fixes;
c7b8f16e 3296
a504d23a
LA		 3297 /* What sort of code sequences we should look for which may trigger the
3298 STM32L4XX erratum. */
3299 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3300
3301 /* Global counter for the number of fixes we have emitted. */
3302 int num_stm32l4xx_fixes;
3303
906e58ca
NC		 3304 /* Nonzero to force PIC branch veneers. */
3305 int pic_veneer;
27e55c4d 3306
906e58ca
NC		 3307 /* The number of bytes in the initial entry in the PLT. */
3308 bfd_size_type plt_header_size;
e5a52504 3309
906e58ca
NC		 3310 /* The number of bytes in the subsequent PLT etries. */
3311 bfd_size_type plt_entry_size;
e5a52504 3312
906e58ca
NC		 3313 /* True if the target system is VxWorks. */
3314 int vxworks_p;
00a97672 3315
906e58ca
NC		 3316 /* True if the target system is Symbian OS. */
3317 int symbian_p;
e5a52504 3318
b38cadfb
NC		 3319 /* True if the target system is Native Client. */
3320 int nacl_p;
3321
906e58ca 3322 /* True if the target uses REL relocations. */
f3185997 3323 bfd_boolean use_rel;
4e7fd91e 3324
54ddd295
TP		 3325 /* Nonzero if import library must be a secure gateway import library
3326 as per ARMv8-M Security Extensions. */
3327 int cmse_implib;
3328
0955507f
TP		 3329 /* The import library whose symbols' address must remain stable in
3330 the import library generated. */
3331 bfd *in_implib_bfd;
3332
0855e32b
NS		 3333 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3334 bfd_vma next_tls_desc_index;
3335
3336 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3337 bfd_vma num_tls_desc;
3338
906e58ca
NC		 3339 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3340 asection *srelplt2;
00a97672 3341
0855e32b
NS		 3342 /* The offset into splt of the PLT entry for the TLS descriptor
3343 resolver. Special values are 0, if not necessary (or not found
3344 to be necessary yet), and -1 if needed but not determined
3345 yet. */
3346 bfd_vma dt_tlsdesc_plt;
3347
3348 /* The offset into sgot of the GOT entry used by the PLT entry
3349 above. */
b38cadfb 3350 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3351
3352 /* Offset in .plt section of tls_arm_trampoline. */
3353 bfd_vma tls_trampoline;
3354
5c5a4843 3355 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3356 union
3357 {
3358 bfd_signed_vma refcount;
3359 bfd_vma offset;
3360 } tls_ldm_got;
b7693d02 3361
87d72d41
AM		 3362 /* Small local sym cache. */
3363 struct sym_cache sym_cache;
906e58ca
NC		 3364
3365 /* For convenience in allocate_dynrelocs. */
3366 bfd * obfd;
3367
0855e32b
NS		 3368 /* The amount of space used by the reserved portion of the sgotplt
3369 section, plus whatever space is used by the jump slots. */
3370 bfd_vma sgotplt_jump_table_size;
3371
906e58ca
NC		 3372 /* The stub hash table. */
3373 struct bfd_hash_table stub_hash_table;
3374
3375 /* Linker stub bfd. */
3376 bfd *stub_bfd;
3377
3378 /* Linker call-backs. */
6bde4c52
TP		 3379 asection * (*add_stub_section) (const char *, asection *, asection *,
3380 unsigned int);
906e58ca
NC		 3381 void (*layout_sections_again) (void);
3382
3383 /* Array to keep track of which stub sections have been created, and
3384 information on stub grouping. */
21d799b5 3385 struct map_stub *stub_group;
906e58ca 3386
4ba2ef8f
TP		 3387 /* Input stub section holding secure gateway veneers. */
3388 asection *cmse_stub_sec;
3389
0955507f
TP		 3390 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3391 start to be allocated. */
3392 bfd_vma new_cmse_stub_offset;
3393
fe33d2fa 3394 /* Number of elements in stub_group. */
7292b3ac 3395 unsigned int top_id;
fe33d2fa 3396
906e58ca
NC		 3397 /* Assorted information used by elf32_arm_size_stubs. */
3398 unsigned int bfd_count;
7292b3ac 3399 unsigned int top_index;
906e58ca 3400 asection **input_list;
617a5ada
CL		 3401
3402 /* True if the target system uses FDPIC. */
3403 int fdpic_p;
e8b09b87
CL		 3404
3405 /* Fixup section. Used for FDPIC. */
3406 asection *srofixup;
906e58ca 3407};
252b5132 3408
e8b09b87
CL		 3409/* Add an FDPIC read-only fixup. */
3410static void
3411arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3412{
3413 bfd_vma fixup_offset;
3414
3415 fixup_offset = srofixup->reloc_count++ * 4;
3416 BFD_ASSERT (fixup_offset < srofixup->size);
3417 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3418}
3419
a504d23a
LA		 3420static inline int
3421ctz (unsigned int mask)
3422{
3423#if GCC_VERSION >= 3004
3424 return __builtin_ctz (mask);
3425#else
3426 unsigned int i;
3427
3428 for (i = 0; i < 8 * sizeof (mask); i++)
3429 {
3430 if (mask & 0x1)
3431 break;
3432 mask = (mask >> 1);
3433 }
3434 return i;
3435#endif
3436}
3437
3438static inline int
b25e998d 3439elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3440{
3441#if GCC_VERSION >= 3004
3442 return __builtin_popcount (mask);
3443#else
b25e998d
CG		 3444 unsigned int i;
3445 int sum = 0;
a504d23a
LA		 3446
3447 for (i = 0; i < 8 * sizeof (mask); i++)
3448 {
3449 if (mask & 0x1)
3450 sum++;
3451 mask = (mask >> 1);
3452 }
3453 return sum;
3454#endif
3455}
3456
e8b09b87
CL		 3457static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3458 asection *sreloc, Elf_Internal_Rela *rel);
3459
3460static void
3461arm_elf_fill_funcdesc(bfd *output_bfd,
3462 struct bfd_link_info *info,
3463 int *funcdesc_offset,
3464 int dynindx,
3465 int offset,
3466 bfd_vma addr,
3467 bfd_vma dynreloc_value,
3468 bfd_vma seg)
3469{
3470 if ((*funcdesc_offset & 1) == 0)
3471 {
3472 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3473 asection *sgot = globals->root.sgot;
3474
3475 if (bfd_link_pic(info))
3476 {
3477 asection *srelgot = globals->root.srelgot;
3478 Elf_Internal_Rela outrel;
3479
3480 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3481 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3482 outrel.r_addend = 0;
3483
3484 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3485 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3486 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3487 }
3488 else
3489 {
3490 struct elf_link_hash_entry *hgot = globals->root.hgot;
3491 bfd_vma got_value = hgot->root.u.def.value
3492 + hgot->root.u.def.section->output_section->vma
3493 + hgot->root.u.def.section->output_offset;
3494
3495 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3496 sgot->output_section->vma + sgot->output_offset
3497 + offset);
3498 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3499 sgot->output_section->vma + sgot->output_offset
3500 + offset + 4);
3501 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3502 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3503 }
3504 *funcdesc_offset |= 1;
3505 }
3506}
3507
780a67af
NC		 3508/* Create an entry in an ARM ELF linker hash table. */
3509
3510static struct bfd_hash_entry *
57e8b36a 3511elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3512 struct bfd_hash_table * table,
3513 const char * string)
780a67af
NC		 3514{
3515 struct elf32_arm_link_hash_entry * ret =
3516 (struct elf32_arm_link_hash_entry *) entry;
3517
3518 /* Allocate the structure if it has not already been allocated by a
3519 subclass. */
906e58ca 3520 if (ret == NULL)
21d799b5 3521 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3522 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3523 if (ret == NULL)
780a67af
NC		 3524 return (struct bfd_hash_entry *) ret;
3525
3526 /* Call the allocation method of the superclass. */
3527 ret = ((struct elf32_arm_link_hash_entry *)
3528 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3529 table, string));
57e8b36a 3530 if (ret != NULL)
b7693d02 3531 {
0bdcacaf 3532 ret->dyn_relocs = NULL;
ba93b8ac 3533 ret->tls_type = GOT_UNKNOWN;
0855e32b 3534 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3535 ret->plt.thumb_refcount = 0;
3536 ret->plt.maybe_thumb_refcount = 0;
3537 ret->plt.noncall_refcount = 0;
3538 ret->plt.got_offset = -1;
3539 ret->is_iplt = FALSE;
a4fd1a8e 3540 ret->export_glue = NULL;
906e58ca
NC		 3541
3542 ret->stub_cache = NULL;
e8b09b87
CL		 3543
3544 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3545 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3546 ret->fdpic_cnts.funcdesc_cnt = 0;
3547 ret->fdpic_cnts.funcdesc_offset = -1;
3548 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3549 }
780a67af
NC		 3550
3551 return (struct bfd_hash_entry *) ret;
3552}
3553
34e77a92
RS		 3554/* Ensure that we have allocated bookkeeping structures for ABFD's local
3555 symbols. */
3556
3557static bfd_boolean
3558elf32_arm_allocate_local_sym_info (bfd *abfd)
3559{
3560 if (elf_local_got_refcounts (abfd) == NULL)
3561 {
3562 bfd_size_type num_syms;
3563 bfd_size_type size;
3564 char *data;
3565
3566 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3567 size = num_syms * (sizeof (bfd_signed_vma)
3568 + sizeof (struct arm_local_iplt_info *)
3569 + sizeof (bfd_vma)
e8b09b87
CL		 3570 + sizeof (char)
3571 + sizeof (struct fdpic_local));
34e77a92
RS		 3572 data = bfd_zalloc (abfd, size);
3573 if (data == NULL)
3574 return FALSE;
3575
e8b09b87
CL		 3576 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3577 data += num_syms * sizeof (struct fdpic_local);
3578
34e77a92
RS		 3579 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3580 data += num_syms * sizeof (bfd_signed_vma);
3581
3582 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3583 data += num_syms * sizeof (struct arm_local_iplt_info *);
3584
3585 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3586 data += num_syms * sizeof (bfd_vma);
3587
3588 elf32_arm_local_got_tls_type (abfd) = data;
3589 }
3590 return TRUE;
3591}
3592
3593/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3594 to input bfd ABFD. Create the information if it doesn't already exist.
3595 Return null if an allocation fails. */
3596
3597static struct arm_local_iplt_info *
3598elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3599{
3600 struct arm_local_iplt_info **ptr;
3601
3602 if (!elf32_arm_allocate_local_sym_info (abfd))
3603 return NULL;
3604
3605 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3606 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3607 if (*ptr == NULL)
3608 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3609 return *ptr;
3610}
3611
3612/* Try to obtain PLT information for the symbol with index R_SYMNDX
3613 in ABFD's symbol table. If the symbol is global, H points to its
3614 hash table entry, otherwise H is null.
3615
3616 Return true if the symbol does have PLT information. When returning
3617 true, point *ROOT_PLT at the target-independent reference count/offset
3618 union and *ARM_PLT at the ARM-specific information. */
3619
3620static bfd_boolean
4ba2ef8f
TP		 3621elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3622 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3623 unsigned long r_symndx, union gotplt_union **root_plt,
3624 struct arm_plt_info **arm_plt)
3625{
3626 struct arm_local_iplt_info *local_iplt;
3627
4ba2ef8f
TP		 3628 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3629 return FALSE;
3630
34e77a92
RS		 3631 if (h != NULL)
3632 {
3633 *root_plt = &h->root.plt;
3634 *arm_plt = &h->plt;
3635 return TRUE;
3636 }
3637
3638 if (elf32_arm_local_iplt (abfd) == NULL)
3639 return FALSE;
3640
3641 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3642 if (local_iplt == NULL)
3643 return FALSE;
3644
3645 *root_plt = &local_iplt->root;
3646 *arm_plt = &local_iplt->arm;
3647 return TRUE;
3648}
3649
59029f57
CL		 3650static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3651
34e77a92
RS		 3652/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3653 before it. */
3654
3655static bfd_boolean
3656elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3657 struct arm_plt_info *arm_plt)
3658{
3659 struct elf32_arm_link_hash_table *htab;
3660
3661 htab = elf32_arm_hash_table (info);
59029f57
CL		 3662
3663 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3664 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3665}
3666
3667/* Return a pointer to the head of the dynamic reloc list that should
3668 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3669 ABFD's symbol table. Return null if an error occurs. */
3670
3671static struct elf_dyn_relocs **
3672elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3673 Elf_Internal_Sym *isym)
3674{
3675 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3676 {
3677 struct arm_local_iplt_info *local_iplt;
3678
3679 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3680 if (local_iplt == NULL)
3681 return NULL;
3682 return &local_iplt->dyn_relocs;
3683 }
3684 else
3685 {
3686 /* Track dynamic relocs needed for local syms too.
3687 We really need local syms available to do this
3688 easily. Oh well. */
3689 asection *s;
3690 void *vpp;
3691
3692 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3693 if (s == NULL)
3694 abort ();
3695
3696 vpp = &elf_section_data (s)->local_dynrel;
3697 return (struct elf_dyn_relocs **) vpp;
3698 }
3699}
3700
906e58ca
NC		 3701/* Initialize an entry in the stub hash table. */
3702
3703static struct bfd_hash_entry *
3704stub_hash_newfunc (struct bfd_hash_entry *entry,
3705 struct bfd_hash_table *table,
3706 const char *string)
3707{
3708 /* Allocate the structure if it has not already been allocated by a
3709 subclass. */
3710 if (entry == NULL)
3711 {
21d799b5 3712 entry = (struct bfd_hash_entry *)
99059e56 3713 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3714 if (entry == NULL)
3715 return entry;
3716 }
3717
3718 /* Call the allocation method of the superclass. */
3719 entry = bfd_hash_newfunc (entry, table, string);
3720 if (entry != NULL)
3721 {
3722 struct elf32_arm_stub_hash_entry *eh;
3723
3724 /* Initialize the local fields. */
3725 eh = (struct elf32_arm_stub_hash_entry *) entry;
3726 eh->stub_sec = NULL;
0955507f 3727 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3728 eh->source_value = 0;
906e58ca
NC		 3729 eh->target_value = 0;
3730 eh->target_section = NULL;
cedfb179 3731 eh->orig_insn = 0;
906e58ca 3732 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3733 eh->stub_size = 0;
3734 eh->stub_template = NULL;
0955507f 3735 eh->stub_template_size = -1;
906e58ca
NC		 3736 eh->h = NULL;
3737 eh->id_sec = NULL;
d8d2f433 3738 eh->output_name = NULL;
906e58ca
NC		 3739 }
3740
3741 return entry;
3742}
3743
00a97672 3744/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3745 shortcuts to them in our hash table. */
3746
3747static bfd_boolean
57e8b36a 3748create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3749{
3750 struct elf32_arm_link_hash_table *htab;
3751
e5a52504 3752 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3753 if (htab == NULL)
3754 return FALSE;
3755
e5a52504
MM		 3756 /* BPABI objects never have a GOT, or associated sections. */
3757 if (htab->symbian_p)
3758 return TRUE;
3759
5e681ec4
PB		 3760 if (! _bfd_elf_create_got_section (dynobj, info))
3761 return FALSE;
3762
e8b09b87
CL		 3763 /* Also create .rofixup. */
3764 if (htab->fdpic_p)
3765 {
3766 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3767 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3768 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
3769 if (htab->srofixup == NULL || ! bfd_set_section_alignment (dynobj, htab->srofixup, 2))
3770 return FALSE;
3771 }
3772
5e681ec4
PB		 3773 return TRUE;
3774}
3775
34e77a92
RS		 3776/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3777
3778static bfd_boolean
3779create_ifunc_sections (struct bfd_link_info *info)
3780{
3781 struct elf32_arm_link_hash_table *htab;
3782 const struct elf_backend_data *bed;
3783 bfd *dynobj;
3784 asection *s;
3785 flagword flags;
b38cadfb 3786
34e77a92
RS		 3787 htab = elf32_arm_hash_table (info);
3788 dynobj = htab->root.dynobj;
3789 bed = get_elf_backend_data (dynobj);
3790 flags = bed->dynamic_sec_flags;
3791
3792 if (htab->root.iplt == NULL)
3793 {
3d4d4302
AM		 3794 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3795 flags | SEC_READONLY | SEC_CODE);
34e77a92 3796 if (s == NULL
a0f49396 3797 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3798 return FALSE;
3799 htab->root.iplt = s;
3800 }
3801
3802 if (htab->root.irelplt == NULL)
3803 {
3d4d4302
AM		 3804 s = bfd_make_section_anyway_with_flags (dynobj,
3805 RELOC_SECTION (htab, ".iplt"),
3806 flags | SEC_READONLY);
34e77a92 3807 if (s == NULL
a0f49396 3808 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3809 return FALSE;
3810 htab->root.irelplt = s;
3811 }
3812
3813 if (htab->root.igotplt == NULL)
3814 {
3d4d4302 3815 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3816 if (s == NULL
3817 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3818 return FALSE;
3819 htab->root.igotplt = s;
3820 }
3821 return TRUE;
3822}
3823
eed94f8f
NC		 3824/* Determine if we're dealing with a Thumb only architecture. */
3825
3826static bfd_boolean
3827using_thumb_only (struct elf32_arm_link_hash_table *globals)
3828{
2fd158eb
TP		 3829 int arch;
3830 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3831 Tag_CPU_arch_profile);
eed94f8f 3832
2fd158eb
TP		 3833 if (profile)
3834 return profile == 'M';
eed94f8f 3835
2fd158eb 3836 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3837
60a019a0 3838 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3839 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0 3840
2fd158eb
TP		 3841 if (arch == TAG_CPU_ARCH_V6_M
3842 || arch == TAG_CPU_ARCH_V6S_M
3843 || arch == TAG_CPU_ARCH_V7E_M
3844 || arch == TAG_CPU_ARCH_V8M_BASE
3845 || arch == TAG_CPU_ARCH_V8M_MAIN)
3846 return TRUE;
eed94f8f 3847
2fd158eb 3848 return FALSE;
eed94f8f
NC		 3849}
3850
3851/* Determine if we're dealing with a Thumb-2 object. */
3852
3853static bfd_boolean
3854using_thumb2 (struct elf32_arm_link_hash_table *globals)
3855{
60a019a0
TP		 3856 int arch;
3857 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3858 Tag_THUMB_ISA_use);
3859
3860 if (thumb_isa)
3861 return thumb_isa == 2;
3862
3863 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3864
3865 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3866 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3867
3868 return (arch == TAG_CPU_ARCH_V6T2
3869 || arch == TAG_CPU_ARCH_V7
3870 || arch == TAG_CPU_ARCH_V7E_M
3871 || arch == TAG_CPU_ARCH_V8
bff0500d 3872 || arch == TAG_CPU_ARCH_V8R
60a019a0 3873 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3874}
3875
5e866f5a
TP		 3876/* Determine whether Thumb-2 BL instruction is available. */
3877
3878static bfd_boolean
3879using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3880{
3881 int arch =
3882 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3883
3884 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3885 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
5e866f5a
TP		 3886
3887 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3888 return (arch == TAG_CPU_ARCH_V6T2
3889 || arch >= TAG_CPU_ARCH_V7);
3890}
3891
00a97672
RS		 3892/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3893 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3894 hash table. */
3895
3896static bfd_boolean
57e8b36a 3897elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3898{
3899 struct elf32_arm_link_hash_table *htab;
3900
3901 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3902 if (htab == NULL)
3903 return FALSE;
3904
362d30a1 3905 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3906 return FALSE;
3907
3908 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3909 return FALSE;
3910
00a97672
RS		 3911 if (htab->vxworks_p)
3912 {
3913 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3914 return FALSE;
3915
0e1862bb 3916 if (bfd_link_pic (info))
00a97672
RS		 3917 {
3918 htab->plt_header_size = 0;
3919 htab->plt_entry_size
3920 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3921 }
3922 else
3923 {
3924 htab->plt_header_size
3925 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3926 htab->plt_entry_size
3927 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3928 }
aebf9be7
NC		 3929
3930 if (elf_elfheader (dynobj))
3931 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3932 }
eed94f8f
NC		 3933 else
3934 {
3935 /* PR ld/16017
3936 Test for thumb only architectures. Note - we cannot just call
3937 using_thumb_only() as the attributes in the output bfd have not been
3938 initialised at this point, so instead we use the input bfd. */
3939 bfd * saved_obfd = htab->obfd;
3940
3941 htab->obfd = dynobj;
3942 if (using_thumb_only (htab))
3943 {
3944 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3945 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3946 }
3947 htab->obfd = saved_obfd;
3948 }
5e681ec4 3949
7801f98f
CL		 3950 if (htab->fdpic_p) {
3951 htab->plt_header_size = 0;
3952 if (info->flags & DF_BIND_NOW)
3953 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
3954 else
3955 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
3956 }
3957
362d30a1
RS		 3958 if (!htab->root.splt
3959 || !htab->root.srelplt
9d19e4fd
AM		 3960 || !htab->root.sdynbss
3961 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3962 abort ();
3963
3964 return TRUE;
3965}
3966
906e58ca
NC		 3967/* Copy the extra info we tack onto an elf_link_hash_entry. */
3968
3969static void
3970elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3971 struct elf_link_hash_entry *dir,
3972 struct elf_link_hash_entry *ind)
3973{
3974 struct elf32_arm_link_hash_entry *edir, *eind;
3975
3976 edir = (struct elf32_arm_link_hash_entry *) dir;
3977 eind = (struct elf32_arm_link_hash_entry *) ind;
3978
0bdcacaf 3979 if (eind->dyn_relocs != NULL)
906e58ca 3980 {
0bdcacaf 3981 if (edir->dyn_relocs != NULL)
906e58ca 3982 {
0bdcacaf
RS		 3983 struct elf_dyn_relocs **pp;
3984 struct elf_dyn_relocs *p;
906e58ca
NC		 3985
3986 /* Add reloc counts against the indirect sym to the direct sym
3987 list. Merge any entries against the same section. */
0bdcacaf 3988 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3989 {
0bdcacaf 3990 struct elf_dyn_relocs *q;
906e58ca 3991
0bdcacaf
RS		 3992 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3993 if (q->sec == p->sec)
906e58ca
NC		 3994 {
3995 q->pc_count += p->pc_count;
3996 q->count += p->count;
3997 *pp = p->next;
3998 break;
3999 }
4000 if (q == NULL)
4001 pp = &p->next;
4002 }
0bdcacaf 4003 *pp = edir->dyn_relocs;
906e58ca
NC		 4004 }
4005
0bdcacaf
RS		 4006 edir->dyn_relocs = eind->dyn_relocs;
4007 eind->dyn_relocs = NULL;
906e58ca
NC		 4008 }
4009
4010 if (ind->root.type == bfd_link_hash_indirect)
4011 {
4012 /* Copy over PLT info. */
34e77a92
RS		 4013 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4014 eind->plt.thumb_refcount = 0;
4015 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4016 eind->plt.maybe_thumb_refcount = 0;
4017 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4018 eind->plt.noncall_refcount = 0;
4019
e8b09b87
CL		 4020 /* Copy FDPIC counters. */
4021 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4022 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4023 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4024
34e77a92
RS		 4025 /* We should only allocate a function to .iplt once the final
4026 symbol information is known. */
4027 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4028
4029 if (dir->got.refcount <= 0)
4030 {
4031 edir->tls_type = eind->tls_type;
4032 eind->tls_type = GOT_UNKNOWN;
4033 }
4034 }
4035
4036 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4037}
4038
68faa637
AM		 4039/* Destroy an ARM elf linker hash table. */
4040
4041static void
d495ab0d 4042elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4043{
4044 struct elf32_arm_link_hash_table *ret
d495ab0d 4045 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4046
4047 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4048 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4049}
4050
906e58ca
NC		 4051/* Create an ARM elf linker hash table. */
4052
4053static struct bfd_link_hash_table *
4054elf32_arm_link_hash_table_create (bfd *abfd)
4055{
4056 struct elf32_arm_link_hash_table *ret;
4057 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4058
7bf52ea2 4059 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4060 if (ret == NULL)
4061 return NULL;
4062
4063 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4064 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4065 sizeof (struct elf32_arm_link_hash_entry),
4066 ARM_ELF_DATA))
906e58ca
NC		 4067 {
4068 free (ret);
4069 return NULL;
4070 }
4071
906e58ca 4072 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4073 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4074#ifdef FOUR_WORD_PLT
4075 ret->plt_header_size = 16;
4076 ret->plt_entry_size = 16;
4077#else
4078 ret->plt_header_size = 20;
1db37fe6 4079 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4080#endif
f3185997 4081 ret->use_rel = TRUE;
906e58ca 4082 ret->obfd = abfd;
617a5ada 4083 ret->fdpic_p = 0;
906e58ca
NC		 4084
4085 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4086 sizeof (struct elf32_arm_stub_hash_entry)))
4087 {
d495ab0d 4088 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4089 return NULL;
4090 }
d495ab0d 4091 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4092
4093 return &ret->root.root;
4094}
4095
cd1dac3d
DG		 4096/* Determine what kind of NOPs are available. */
4097
4098static bfd_boolean
4099arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4100{
4101 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4102 Tag_CPU_arch);
cd1dac3d 4103
60a019a0 4104 /* Force return logic to be reviewed for each new architecture. */
bff0500d 4105 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 4106
4107 return (arch == TAG_CPU_ARCH_V6T2
4108 || arch == TAG_CPU_ARCH_V6K
4109 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4110 || arch == TAG_CPU_ARCH_V8
4111 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4112}
4113
f4ac8484
DJ		 4114static bfd_boolean
4115arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4116{
4117 switch (stub_type)
4118 {
fea2b4d6 4119 case arm_stub_long_branch_thumb_only:
80c135e5 4120 case arm_stub_long_branch_thumb2_only:
d5a67c02 4121 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4122 case arm_stub_long_branch_v4t_thumb_arm:
4123 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4124 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4125 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4126 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4127 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4128 return TRUE;
4129 case arm_stub_none:
4130 BFD_FAIL ();
4131 return FALSE;
4132 break;
4133 default:
4134 return FALSE;
4135 }
4136}
4137
906e58ca
NC		 4138/* Determine the type of stub needed, if any, for a call. */
4139
4140static enum elf32_arm_stub_type
4141arm_type_of_stub (struct bfd_link_info *info,
4142 asection *input_sec,
4143 const Elf_Internal_Rela *rel,
34e77a92 4144 unsigned char st_type,
35fc36a8 4145 enum arm_st_branch_type *actual_branch_type,
906e58ca 4146 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4147 bfd_vma destination,
4148 asection *sym_sec,
4149 bfd *input_bfd,
4150 const char *name)
906e58ca
NC		 4151{
4152 bfd_vma location;
4153 bfd_signed_vma branch_offset;
4154 unsigned int r_type;
4155 struct elf32_arm_link_hash_table * globals;
5e866f5a 4156 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4157 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4158 int use_plt = 0;
35fc36a8 4159 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4160 union gotplt_union *root_plt;
4161 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4162 int arch;
4163 int thumb2_movw;
906e58ca 4164
35fc36a8 4165 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4166 return stub_type;
4167
906e58ca 4168 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4169 if (globals == NULL)
4170 return stub_type;
906e58ca
NC		 4171
4172 thumb_only = using_thumb_only (globals);
906e58ca 4173 thumb2 = using_thumb2 (globals);
5e866f5a 4174 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4175
d5a67c02
AV		 4176 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4177
4178 /* True for architectures that implement the thumb2 movw instruction. */
4179 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4180
906e58ca
NC		 4181 /* Determine where the call point is. */
4182 location = (input_sec->output_offset
4183 + input_sec->output_section->vma
4184 + rel->r_offset);
4185
906e58ca
NC		 4186 r_type = ELF32_R_TYPE (rel->r_info);
4187
39f21624
NC		 4188 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4189 are considering a function call relocation. */
c5423981 4190 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4191 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4192 && branch_type == ST_BRANCH_TO_ARM)
4193 branch_type = ST_BRANCH_TO_THUMB;
4194
34e77a92
RS		 4195 /* For TLS call relocs, it is the caller's responsibility to provide
4196 the address of the appropriate trampoline. */
4197 if (r_type != R_ARM_TLS_CALL
4198 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4199 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4200 ELF32_R_SYM (rel->r_info), &root_plt,
4201 &arm_plt)
34e77a92 4202 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4203 {
34e77a92 4204 asection *splt;
fe33d2fa 4205
34e77a92
RS		 4206 if (hash == NULL || hash->is_iplt)
4207 splt = globals->root.iplt;
4208 else
4209 splt = globals->root.splt;
4210 if (splt != NULL)
b38cadfb 4211 {
34e77a92
RS		 4212 use_plt = 1;
4213
4214 /* Note when dealing with PLT entries: the main PLT stub is in
4215 ARM mode, so if the branch is in Thumb mode, another
4216 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4217 PLT stub. If a long branch stub is needed, we'll add a
4218 Thumb->Arm one and branch directly to the ARM PLT entry.
4219 Here, we have to check if a pre-PLT Thumb->ARM stub
4220 is needed and if it will be close enough. */
34e77a92
RS		 4221
4222 destination = (splt->output_section->vma
4223 + splt->output_offset
4224 + root_plt->offset);
4225 st_type = STT_FUNC;
2df2751d
CL		 4226
4227 /* Thumb branch/call to PLT: it can become a branch to ARM
4228 or to Thumb. We must perform the same checks and
4229 corrections as in elf32_arm_final_link_relocate. */
4230 if ((r_type == R_ARM_THM_CALL)
4231 || (r_type == R_ARM_THM_JUMP24))
4232 {
4233 if (globals->use_blx
4234 && r_type == R_ARM_THM_CALL
4235 && !thumb_only)
4236 {
4237 /* If the Thumb BLX instruction is available, convert
4238 the BL to a BLX instruction to call the ARM-mode
4239 PLT entry. */
4240 branch_type = ST_BRANCH_TO_ARM;
4241 }
4242 else
4243 {
4244 if (!thumb_only)
4245 /* Target the Thumb stub before the ARM PLT entry. */
4246 destination -= PLT_THUMB_STUB_SIZE;
4247 branch_type = ST_BRANCH_TO_THUMB;
4248 }
4249 }
4250 else
4251 {
4252 branch_type = ST_BRANCH_TO_ARM;
4253 }
34e77a92 4254 }
5fa9e92f 4255 }
34e77a92
RS		 4256 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4257 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4258
fe33d2fa
CL		 4259 branch_offset = (bfd_signed_vma)(destination - location);
4260
0855e32b 4261 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4262 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4263 {
5fa9e92f
CL		 4264 /* Handle cases where:
4265 - this call goes too far (different Thumb/Thumb2 max
99059e56 4266 distance)
155d87d7 4267 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4268 Thumb->Arm branch (not bl). A stub is needed in this case,
4269 but only if this call is not through a PLT entry. Indeed,
695344c0 4270 PLT stubs handle mode switching already. */
5e866f5a 4271 if ((!thumb2_bl
906e58ca
NC		 4272 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4273 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4274 || (thumb2_bl
906e58ca
NC		 4275 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4276 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4277 || (thumb2
4278 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4279 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4280 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4281 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4282 && (((r_type == R_ARM_THM_CALL
4283 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4284 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4285 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4286 && !use_plt))
906e58ca 4287 {
2df2751d
CL		 4288 /* If we need to insert a Thumb-Thumb long branch stub to a
4289 PLT, use one that branches directly to the ARM PLT
4290 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4291 stub, undo this now. */
695344c0
NC		 4292 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4293 {
4294 branch_type = ST_BRANCH_TO_ARM;
4295 branch_offset += PLT_THUMB_STUB_SIZE;
4296 }
2df2751d 4297
35fc36a8 4298 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4299 {
4300 /* Thumb to thumb. */
4301 if (!thumb_only)
4302 {
d5a67c02 4303 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4304 _bfd_error_handler
871b3ab2 4305 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4306 " section with SHF_ARM_PURECODE section"
4307 " attribute is only supported for M-profile"
90b6238f 4308 " targets that implement the movw instruction"),
10463f39 4309 input_bfd, input_sec);
d5a67c02 4310
0e1862bb 4311 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4312 /* PIC stubs. */
155d87d7 4313 ? ((globals->use_blx
9553db3c 4314 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4315 /* V5T and above. Stub starts with ARM code, so
4316 we must be able to switch mode before
4317 reaching it, which is only possible for 'bl'
4318 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4319 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4320 /* On V4T, use Thumb code only. */
d3626fb0 4321 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4322
4323 /* non-PIC stubs. */
155d87d7 4324 : ((globals->use_blx
9553db3c 4325 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4326 /* V5T and above. */
4327 ? arm_stub_long_branch_any_any
4328 /* V4T. */
d3626fb0 4329 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4330 }
4331 else
4332 {
d5a67c02
AV		 4333 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4334 stub_type = arm_stub_long_branch_thumb2_only_pure;
4335 else
4336 {
4337 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4338 _bfd_error_handler
871b3ab2 4339 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4340 " section with SHF_ARM_PURECODE section"
4341 " attribute is only supported for M-profile"
90b6238f 4342 " targets that implement the movw instruction"),
10463f39 4343 input_bfd, input_sec);
d5a67c02
AV		 4344
4345 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4346 /* PIC stub. */
4347 ? arm_stub_long_branch_thumb_only_pic
4348 /* non-PIC stub. */
4349 : (thumb2 ? arm_stub_long_branch_thumb2_only
4350 : arm_stub_long_branch_thumb_only);
4351 }
906e58ca
NC		 4352 }
4353 }
4354 else
4355 {
d5a67c02 4356 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4357 _bfd_error_handler
871b3ab2 4358 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4359 " section with SHF_ARM_PURECODE section"
4360 " attribute is only supported" " for M-profile"
90b6238f 4361 " targets that implement the movw instruction"),
10463f39 4362 input_bfd, input_sec);
d5a67c02 4363
906e58ca 4364 /* Thumb to arm. */
c820be07
NC		 4365 if (sym_sec != NULL
4366 && sym_sec->owner != NULL
4367 && !INTERWORK_FLAG (sym_sec->owner))
4368 {
4eca0228 4369 _bfd_error_handler
90b6238f
AM		 4370 (_("%pB(%s): warning: interworking not enabled;"
4371 " first occurrence: %pB: %s call to %s"),
4372 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4373 }
4374
0855e32b 4375 stub_type =
0e1862bb 4376 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4377 /* PIC stubs. */
0855e32b 4378 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4379 /* TLS PIC stubs. */
0855e32b
NS		 4380 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4381 : arm_stub_long_branch_v4t_thumb_tls_pic)
4382 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4383 /* V5T PIC and above. */
4384 ? arm_stub_long_branch_any_arm_pic
4385 /* V4T PIC stub. */
4386 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4387
4388 /* non-PIC stubs. */
0855e32b 4389 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4390 /* V5T and above. */
4391 ? arm_stub_long_branch_any_any
4392 /* V4T. */
4393 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4394
4395 /* Handle v4t short branches. */
fea2b4d6 4396 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4397 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4398 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4399 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4400 }
4401 }
4402 }
fe33d2fa
CL		 4403 else if (r_type == R_ARM_CALL
4404 || r_type == R_ARM_JUMP24
0855e32b
NS		 4405 || r_type == R_ARM_PLT32
4406 || r_type == R_ARM_TLS_CALL)
906e58ca 4407 {
d5a67c02 4408 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4409 _bfd_error_handler
871b3ab2 4410 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4411 " section with SHF_ARM_PURECODE section"
4412 " attribute is only supported for M-profile"
90b6238f 4413 " targets that implement the movw instruction"),
10463f39 4414 input_bfd, input_sec);
35fc36a8 4415 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4416 {
4417 /* Arm to thumb. */
c820be07
NC		 4418
4419 if (sym_sec != NULL
4420 && sym_sec->owner != NULL
4421 && !INTERWORK_FLAG (sym_sec->owner))
4422 {
4eca0228 4423 _bfd_error_handler
90b6238f
AM		 4424 (_("%pB(%s): warning: interworking not enabled;"
4425 " first occurrence: %pB: %s call to %s"),
4426 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4427 }
4428
4429 /* We have an extra 2-bytes reach because of
4430 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4431 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4432 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4433 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4434 || (r_type == R_ARM_JUMP24)
4435 || (r_type == R_ARM_PLT32))
906e58ca 4436 {
0e1862bb 4437 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4438 /* PIC stubs. */
ebe24dd4
CL		 4439 ? ((globals->use_blx)
4440 /* V5T and above. */
4441 ? arm_stub_long_branch_any_thumb_pic
4442 /* V4T stub. */
4443 : arm_stub_long_branch_v4t_arm_thumb_pic)
4444
c2b4a39d
CL		 4445 /* non-PIC stubs. */
4446 : ((globals->use_blx)
4447 /* V5T and above. */
4448 ? arm_stub_long_branch_any_any
4449 /* V4T. */
4450 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4451 }
4452 }
4453 else
4454 {
4455 /* Arm to arm. */
4456 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4457 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4458 {
0855e32b 4459 stub_type =
0e1862bb 4460 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4461 /* PIC stubs. */
0855e32b 4462 ? (r_type == R_ARM_TLS_CALL
6a631e86 4463 /* TLS PIC Stub. */
0855e32b 4464 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4465 : (globals->nacl_p
4466 ? arm_stub_long_branch_arm_nacl_pic
4467 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4468 /* non-PIC stubs. */
7a89b94e
NC		 4469 : (globals->nacl_p
4470 ? arm_stub_long_branch_arm_nacl
4471 : arm_stub_long_branch_any_any);
906e58ca
NC		 4472 }
4473 }
4474 }
4475
fe33d2fa
CL		 4476 /* If a stub is needed, record the actual destination type. */
4477 if (stub_type != arm_stub_none)
35fc36a8 4478 *actual_branch_type = branch_type;
fe33d2fa 4479
906e58ca
NC		 4480 return stub_type;
4481}
4482
4483/* Build a name for an entry in the stub hash table. */
4484
4485static char *
4486elf32_arm_stub_name (const asection *input_section,
4487 const asection *sym_sec,
4488 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4489 const Elf_Internal_Rela *rel,
4490 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4491{
4492 char *stub_name;
4493 bfd_size_type len;
4494
4495 if (hash)
4496 {
fe33d2fa 4497 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4498 stub_name = (char *) bfd_malloc (len);
906e58ca 4499 if (stub_name != NULL)
fe33d2fa 4500 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4501 input_section->id & 0xffffffff,
4502 hash->root.root.root.string,
fe33d2fa
CL		 4503 (int) rel->r_addend & 0xffffffff,
4504 (int) stub_type);
906e58ca
NC		 4505 }
4506 else
4507 {
fe33d2fa 4508 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4509 stub_name = (char *) bfd_malloc (len);
906e58ca 4510 if (stub_name != NULL)
fe33d2fa 4511 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4512 input_section->id & 0xffffffff,
4513 sym_sec->id & 0xffffffff,
0855e32b
NS		 4514 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4515 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4516 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4517 (int) rel->r_addend & 0xffffffff,
4518 (int) stub_type);
906e58ca
NC		 4519 }
4520
4521 return stub_name;
4522}
4523
4524/* Look up an entry in the stub hash. Stub entries are cached because
4525 creating the stub name takes a bit of time. */
4526
4527static struct elf32_arm_stub_hash_entry *
4528elf32_arm_get_stub_entry (const asection *input_section,
4529 const asection *sym_sec,
4530 struct elf_link_hash_entry *hash,
4531 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4532 struct elf32_arm_link_hash_table *htab,
4533 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4534{
4535 struct elf32_arm_stub_hash_entry *stub_entry;
4536 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4537 const asection *id_sec;
4538
4539 if ((input_section->flags & SEC_CODE) == 0)
4540 return NULL;
4541
4542 /* If this input section is part of a group of sections sharing one
4543 stub section, then use the id of the first section in the group.
4544 Stub names need to include a section id, as there may well be
4545 more than one stub used to reach say, printf, and we need to
4546 distinguish between them. */
c2abbbeb 4547 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4548 id_sec = htab->stub_group[input_section->id].link_sec;
4549
4550 if (h != NULL && h->stub_cache != NULL
4551 && h->stub_cache->h == h
fe33d2fa
CL		 4552 && h->stub_cache->id_sec == id_sec
4553 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4554 {
4555 stub_entry = h->stub_cache;
4556 }
4557 else
4558 {
4559 char *stub_name;
4560
fe33d2fa 4561 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4562 if (stub_name == NULL)
4563 return NULL;
4564
4565 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4566 stub_name, FALSE, FALSE);
4567 if (h != NULL)
4568 h->stub_cache = stub_entry;
4569
4570 free (stub_name);
4571 }
4572
4573 return stub_entry;
4574}
4575
daa4adae
TP		 4576/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4577 section. */
4578
4579static bfd_boolean
4580arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4581{
4582 if (stub_type >= max_stub_type)
4583 abort (); /* Should be unreachable. */
4584
4ba2ef8f
TP		 4585 switch (stub_type)
4586 {
4587 case arm_stub_cmse_branch_thumb_only:
4588 return TRUE;
4589
4590 default:
4591 return FALSE;
4592 }
4593
4594 abort (); /* Should be unreachable. */
daa4adae
TP		 4595}
4596
4597/* Required alignment (as a power of 2) for the dedicated section holding
4598 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4599 with input sections. */
4600
4601static int
4602arm_dedicated_stub_output_section_required_alignment
4603 (enum elf32_arm_stub_type stub_type)
4604{
4605 if (stub_type >= max_stub_type)
4606 abort (); /* Should be unreachable. */
4607
4ba2ef8f
TP		 4608 switch (stub_type)
4609 {
4610 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4611 boundary. */
4612 case arm_stub_cmse_branch_thumb_only:
4613 return 5;
4614
4615 default:
4616 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4617 return 0;
4618 }
4619
4620 abort (); /* Should be unreachable. */
daa4adae
TP		 4621}
4622
4623/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4624 NULL if veneers of this type are interspersed with input sections. */
4625
4626static const char *
4627arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4628{
4629 if (stub_type >= max_stub_type)
4630 abort (); /* Should be unreachable. */
4631
4ba2ef8f
TP		 4632 switch (stub_type)
4633 {
4634 case arm_stub_cmse_branch_thumb_only:
4635 return ".gnu.sgstubs";
4636
4637 default:
4638 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4639 return NULL;
4640 }
4641
4642 abort (); /* Should be unreachable. */
daa4adae
TP		 4643}
4644
4645/* If veneers of type STUB_TYPE should go in a dedicated output section,
4646 returns the address of the hash table field in HTAB holding a pointer to the
4647 corresponding input section. Otherwise, returns NULL. */
4648
4649static asection **
4ba2ef8f
TP		 4650arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4651 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4652{
4653 if (stub_type >= max_stub_type)
4654 abort (); /* Should be unreachable. */
4655
4ba2ef8f
TP		 4656 switch (stub_type)
4657 {
4658 case arm_stub_cmse_branch_thumb_only:
4659 return &htab->cmse_stub_sec;
4660
4661 default:
4662 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4663 return NULL;
4664 }
4665
4666 abort (); /* Should be unreachable. */
daa4adae
TP		 4667}
4668
4669/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4670 is the section that branch into veneer and can be NULL if stub should go in
4671 a dedicated output section. Returns a pointer to the stub section, and the
4672 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4673 LINK_SEC_P may be NULL. */
906e58ca 4674
48229727
JB		 4675static asection *
4676elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4677 struct elf32_arm_link_hash_table *htab,
4678 enum elf32_arm_stub_type stub_type)
906e58ca 4679{
daa4adae
TP		 4680 asection *link_sec, *out_sec, **stub_sec_p;
4681 const char *stub_sec_prefix;
4682 bfd_boolean dedicated_output_section =
4683 arm_dedicated_stub_output_section_required (stub_type);
4684 int align;
906e58ca 4685
daa4adae 4686 if (dedicated_output_section)
906e58ca 4687 {
daa4adae
TP		 4688 bfd *output_bfd = htab->obfd;
4689 const char *out_sec_name =
4690 arm_dedicated_stub_output_section_name (stub_type);
4691 link_sec = NULL;
4692 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4693 stub_sec_prefix = out_sec_name;
4694 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4695 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4696 if (out_sec == NULL)
906e58ca 4697 {
90b6238f 4698 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4699 "section %s"), out_sec_name);
daa4adae 4700 return NULL;
906e58ca 4701 }
daa4adae
TP		 4702 }
4703 else
4704 {
c2abbbeb 4705 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4706 link_sec = htab->stub_group[section->id].link_sec;
4707 BFD_ASSERT (link_sec != NULL);
4708 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4709 if (*stub_sec_p == NULL)
4710 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4711 stub_sec_prefix = link_sec->name;
4712 out_sec = link_sec->output_section;
4713 align = htab->nacl_p ? 4 : 3;
906e58ca 4714 }
b38cadfb 4715
daa4adae
TP		 4716 if (*stub_sec_p == NULL)
4717 {
4718 size_t namelen;
4719 bfd_size_type len;
4720 char *s_name;
4721
4722 namelen = strlen (stub_sec_prefix);
4723 len = namelen + sizeof (STUB_SUFFIX);
4724 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4725 if (s_name == NULL)
4726 return NULL;
4727
4728 memcpy (s_name, stub_sec_prefix, namelen);
4729 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4730 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4731 align);
4732 if (*stub_sec_p == NULL)
4733 return NULL;
4734
4735 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4736 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4737 | SEC_KEEP;
4738 }
4739
4740 if (!dedicated_output_section)
4741 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4742
48229727
JB		 4743 if (link_sec_p)
4744 *link_sec_p = link_sec;
b38cadfb 4745
daa4adae 4746 return *stub_sec_p;
48229727
JB		 4747}
4748
4749/* Add a new stub entry to the stub hash. Not all fields of the new
4750 stub entry are initialised. */
4751
4752static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4753elf32_arm_add_stub (const char *stub_name, asection *section,
4754 struct elf32_arm_link_hash_table *htab,
4755 enum elf32_arm_stub_type stub_type)
48229727
JB		 4756{
4757 asection *link_sec;
4758 asection *stub_sec;
4759 struct elf32_arm_stub_hash_entry *stub_entry;
4760
daa4adae
TP		 4761 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4762 stub_type);
48229727
JB		 4763 if (stub_sec == NULL)
4764 return NULL;
906e58ca
NC		 4765
4766 /* Enter this entry into the linker stub hash table. */
4767 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4768 TRUE, FALSE);
4769 if (stub_entry == NULL)
4770 {
6bde4c52
TP		 4771 if (section == NULL)
4772 section = stub_sec;
871b3ab2 4773 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4774 section->owner, stub_name);
906e58ca
NC		 4775 return NULL;
4776 }
4777
4778 stub_entry->stub_sec = stub_sec;
0955507f 4779 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4780 stub_entry->id_sec = link_sec;
4781
906e58ca
NC		 4782 return stub_entry;
4783}
4784
4785/* Store an Arm insn into an output section not processed by
4786 elf32_arm_write_section. */
4787
4788static void
8029a119
NC		 4789put_arm_insn (struct elf32_arm_link_hash_table * htab,
4790 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4791{
4792 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4793 bfd_putl32 (val, ptr);
4794 else
4795 bfd_putb32 (val, ptr);
4796}
4797
4798/* Store a 16-bit Thumb insn into an output section not processed by
4799 elf32_arm_write_section. */
4800
4801static void
8029a119
NC		 4802put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4803 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4804{
4805 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4806 bfd_putl16 (val, ptr);
4807 else
4808 bfd_putb16 (val, ptr);
4809}
4810
a504d23a
LA		 4811/* Store a Thumb2 insn into an output section not processed by
4812 elf32_arm_write_section. */
4813
4814static void
4815put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4816 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4817{
4818 /* T2 instructions are 16-bit streamed. */
4819 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4820 {
4821 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4822 bfd_putl16 ((val & 0xffff), ptr + 2);
4823 }
4824 else
4825 {
4826 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4827 bfd_putb16 ((val & 0xffff), ptr + 2);
4828 }
4829}
4830
0855e32b
NS		 4831/* If it's possible to change R_TYPE to a more efficient access
4832 model, return the new reloc type. */
4833
4834static unsigned
b38cadfb 4835elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4836 struct elf_link_hash_entry *h)
4837{
4838 int is_local = (h == NULL);
4839
0e1862bb
L		 4840 if (bfd_link_pic (info)
4841 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4842 return r_type;
4843
b38cadfb 4844 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4845 switch (r_type)
4846 {
4847 case R_ARM_TLS_GOTDESC:
4848 case R_ARM_TLS_CALL:
4849 case R_ARM_THM_TLS_CALL:
4850 case R_ARM_TLS_DESCSEQ:
4851 case R_ARM_THM_TLS_DESCSEQ:
4852 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4853 }
4854
4855 return r_type;
4856}
4857
48229727
JB		 4858static bfd_reloc_status_type elf32_arm_final_link_relocate
4859 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4860 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4861 const char *, unsigned char, enum arm_st_branch_type,
4862 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4863
4563a860
JB		 4864static unsigned int
4865arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4866{
4867 switch (stub_type)
4868 {
4869 case arm_stub_a8_veneer_b_cond:
4870 case arm_stub_a8_veneer_b:
4871 case arm_stub_a8_veneer_bl:
4872 return 2;
4873
4874 case arm_stub_long_branch_any_any:
4875 case arm_stub_long_branch_v4t_arm_thumb:
4876 case arm_stub_long_branch_thumb_only:
80c135e5 4877 case arm_stub_long_branch_thumb2_only:
d5a67c02 4878 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4879 case arm_stub_long_branch_v4t_thumb_thumb:
4880 case arm_stub_long_branch_v4t_thumb_arm:
4881 case arm_stub_short_branch_v4t_thumb_arm:
4882 case arm_stub_long_branch_any_arm_pic:
4883 case arm_stub_long_branch_any_thumb_pic:
4884 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4885 case arm_stub_long_branch_v4t_arm_thumb_pic:
4886 case arm_stub_long_branch_v4t_thumb_arm_pic:
4887 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4888 case arm_stub_long_branch_any_tls_pic:
4889 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4890 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4891 case arm_stub_a8_veneer_blx:
4892 return 4;
b38cadfb 4893
7a89b94e
NC		 4894 case arm_stub_long_branch_arm_nacl:
4895 case arm_stub_long_branch_arm_nacl_pic:
4896 return 16;
4897
4563a860
JB		 4898 default:
4899 abort (); /* Should be unreachable. */
4900 }
4901}
4902
4f4faa4d
TP		 4903/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4904 veneering (TRUE) or have their own symbol (FALSE). */
4905
4906static bfd_boolean
4907arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4908{
4909 if (stub_type >= max_stub_type)
4910 abort (); /* Should be unreachable. */
4911
4ba2ef8f
TP		 4912 switch (stub_type)
4913 {
4914 case arm_stub_cmse_branch_thumb_only:
4915 return TRUE;
4916
4917 default:
4918 return FALSE;
4919 }
4920
4921 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4922}
4923
d7c5bd02
TP		 4924/* Returns the padding needed for the dedicated section used stubs of type
4925 STUB_TYPE. */
4926
4927static int
4928arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4929{
4930 if (stub_type >= max_stub_type)
4931 abort (); /* Should be unreachable. */
4932
4ba2ef8f
TP		 4933 switch (stub_type)
4934 {
4935 case arm_stub_cmse_branch_thumb_only:
4936 return 32;
4937
4938 default:
4939 return 0;
4940 }
4941
4942 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4943}
4944
0955507f
TP		 4945/* If veneers of type STUB_TYPE should go in a dedicated output section,
4946 returns the address of the hash table field in HTAB holding the offset at
4947 which new veneers should be layed out in the stub section. */
4948
4949static bfd_vma*
4950arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4951 enum elf32_arm_stub_type stub_type)
4952{
4953 switch (stub_type)
4954 {
4955 case arm_stub_cmse_branch_thumb_only:
4956 return &htab->new_cmse_stub_offset;
4957
4958 default:
4959 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4960 return NULL;
4961 }
4962}
4963
906e58ca
NC		 4964static bfd_boolean
4965arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4966 void * in_arg)
4967{
7a89b94e 4968#define MAXRELOCS 3
0955507f 4969 bfd_boolean removed_sg_veneer;
906e58ca 4970 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4971 struct elf32_arm_link_hash_table *globals;
906e58ca 4972 struct bfd_link_info *info;
906e58ca
NC		 4973 asection *stub_sec;
4974 bfd *stub_bfd;
906e58ca
NC		 4975 bfd_byte *loc;
4976 bfd_vma sym_value;
4977 int template_size;
4978 int size;
d3ce72d0 4979 const insn_sequence *template_sequence;
906e58ca 4980 int i;
48229727
JB		 4981 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4982 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4983 int nrelocs = 0;
0955507f 4984 int just_allocated = 0;
906e58ca
NC		 4985
4986 /* Massage our args to the form they really have. */
4987 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4988 info = (struct bfd_link_info *) in_arg;
4989
4990 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4991 if (globals == NULL)
4992 return FALSE;
906e58ca 4993
906e58ca
NC		 4994 stub_sec = stub_entry->stub_sec;
4995
4dfe6ac6 4996 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4997 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4998 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4999 return TRUE;
fe33d2fa 5000
0955507f
TP		 5001 /* Assign a slot at the end of section if none assigned yet. */
5002 if (stub_entry->stub_offset == (bfd_vma) -1)
5003 {
5004 stub_entry->stub_offset = stub_sec->size;
5005 just_allocated = 1;
5006 }
906e58ca
NC		 5007 loc = stub_sec->contents + stub_entry->stub_offset;
5008
5009 stub_bfd = stub_sec->owner;
5010
906e58ca
NC		 5011 /* This is the address of the stub destination. */
5012 sym_value = (stub_entry->target_value
5013 + stub_entry->target_section->output_offset
5014 + stub_entry->target_section->output_section->vma);
5015
d3ce72d0 5016 template_sequence = stub_entry->stub_template;
461a49ca 5017 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5018
5019 size = 0;
461a49ca 5020 for (i = 0; i < template_size; i++)
906e58ca 5021 {
d3ce72d0 5022 switch (template_sequence[i].type)
461a49ca
DJ		 5023 {
5024 case THUMB16_TYPE:
48229727 5025 {
d3ce72d0
NC		 5026 bfd_vma data = (bfd_vma) template_sequence[i].data;
5027 if (template_sequence[i].reloc_addend != 0)
48229727 5028 {
99059e56
RM		 5029 /* We've borrowed the reloc_addend field to mean we should
5030 insert a condition code into this (Thumb-1 branch)
5031 instruction. See THUMB16_BCOND_INSN. */
5032 BFD_ASSERT ((data & 0xff00) == 0xd000);
5033 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5034 }
fe33d2fa 5035 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5036 size += 2;
5037 }
461a49ca 5038 break;
906e58ca 5039
48229727 5040 case THUMB32_TYPE:
fe33d2fa
CL		 5041 bfd_put_16 (stub_bfd,
5042 (template_sequence[i].data >> 16) & 0xffff,
5043 loc + size);
5044 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5045 loc + size + 2);
99059e56
RM		 5046 if (template_sequence[i].r_type != R_ARM_NONE)
5047 {
5048 stub_reloc_idx[nrelocs] = i;
5049 stub_reloc_offset[nrelocs++] = size;
5050 }
5051 size += 4;
5052 break;
48229727 5053
461a49ca 5054 case ARM_TYPE:
fe33d2fa
CL		 5055 bfd_put_32 (stub_bfd, template_sequence[i].data,
5056 loc + size);
461a49ca
DJ		 5057 /* Handle cases where the target is encoded within the
5058 instruction. */
d3ce72d0 5059 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5060 {
48229727
JB		 5061 stub_reloc_idx[nrelocs] = i;
5062 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5063 }
5064 size += 4;
5065 break;
5066
5067 case DATA_TYPE:
d3ce72d0 5068 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5069 stub_reloc_idx[nrelocs] = i;
5070 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5071 size += 4;
5072 break;
5073
5074 default:
5075 BFD_FAIL ();
5076 return FALSE;
5077 }
906e58ca 5078 }
461a49ca 5079
0955507f
TP		 5080 if (just_allocated)
5081 stub_sec->size += size;
906e58ca 5082
461a49ca
DJ		 5083 /* Stub size has already been computed in arm_size_one_stub. Check
5084 consistency. */
5085 BFD_ASSERT (size == stub_entry->stub_size);
5086
906e58ca 5087 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5088 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5089 sym_value |= 1;
5090
0955507f
TP		 5091 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5092 to relocate in each stub. */
5093 removed_sg_veneer =
5094 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5095 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5096
48229727 5097 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5098 {
5099 Elf_Internal_Rela rel;
5100 bfd_boolean unresolved_reloc;
5101 char *error_message;
5102 bfd_vma points_to =
5103 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5104
5105 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5106 rel.r_info = ELF32_R_INFO (0,
5107 template_sequence[stub_reloc_idx[i]].r_type);
5108 rel.r_addend = 0;
5109
5110 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5111 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5112 template should refer back to the instruction after the original
5113 branch. We use target_section as Cortex-A8 erratum workaround stubs
5114 are only generated when both source and target are in the same
5115 section. */
5116 points_to = stub_entry->target_section->output_section->vma
5117 + stub_entry->target_section->output_offset
5118 + stub_entry->source_value;
5119
5120 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5121 (template_sequence[stub_reloc_idx[i]].r_type),
5122 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5123 points_to, info, stub_entry->target_section, "", STT_FUNC,
5124 stub_entry->branch_type,
5125 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5126 &error_message);
5127 }
906e58ca
NC		 5128
5129 return TRUE;
48229727 5130#undef MAXRELOCS
906e58ca
NC		 5131}
5132
48229727
JB		 5133/* Calculate the template, template size and instruction size for a stub.
5134 Return value is the instruction size. */
906e58ca 5135
48229727
JB		 5136static unsigned int
5137find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5138 const insn_sequence **stub_template,
5139 int *stub_template_size)
906e58ca 5140{
d3ce72d0 5141 const insn_sequence *template_sequence = NULL;
48229727
JB		 5142 int template_size = 0, i;
5143 unsigned int size;
906e58ca 5144
d3ce72d0 5145 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5146 if (stub_template)
5147 *stub_template = template_sequence;
5148
48229727 5149 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5150 if (stub_template_size)
5151 *stub_template_size = template_size;
906e58ca
NC		 5152
5153 size = 0;
461a49ca
DJ		 5154 for (i = 0; i < template_size; i++)
5155 {
d3ce72d0 5156 switch (template_sequence[i].type)
461a49ca
DJ		 5157 {
5158 case THUMB16_TYPE:
5159 size += 2;
5160 break;
5161
5162 case ARM_TYPE:
48229727 5163 case THUMB32_TYPE:
461a49ca
DJ		 5164 case DATA_TYPE:
5165 size += 4;
5166 break;
5167
5168 default:
5169 BFD_FAIL ();
2a229407 5170 return 0;
461a49ca
DJ		 5171 }
5172 }
5173
48229727
JB		 5174 return size;
5175}
5176
5177/* As above, but don't actually build the stub. Just bump offset so
5178 we know stub section sizes. */
5179
5180static bfd_boolean
5181arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5182 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5183{
5184 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5185 const insn_sequence *template_sequence;
48229727
JB		 5186 int template_size, size;
5187
5188 /* Massage our args to the form they really have. */
5189 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5190
5191 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5192 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5193
d3ce72d0 5194 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5195 &template_size);
5196
0955507f
TP		 5197 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5198 if (stub_entry->stub_template_size)
5199 {
5200 stub_entry->stub_size = size;
5201 stub_entry->stub_template = template_sequence;
5202 stub_entry->stub_template_size = template_size;
5203 }
5204
5205 /* Already accounted for. */
5206 if (stub_entry->stub_offset != (bfd_vma) -1)
5207 return TRUE;
461a49ca 5208
906e58ca
NC		 5209 size = (size + 7) & ~7;
5210 stub_entry->stub_sec->size += size;
461a49ca 5211
906e58ca
NC		 5212 return TRUE;
5213}
5214
5215/* External entry points for sizing and building linker stubs. */
5216
5217/* Set up various things so that we can make a list of input sections
5218 for each output section included in the link. Returns -1 on error,
5219 0 when no stubs will be needed, and 1 on success. */
5220
5221int
5222elf32_arm_setup_section_lists (bfd *output_bfd,
5223 struct bfd_link_info *info)
5224{
5225 bfd *input_bfd;
5226 unsigned int bfd_count;
7292b3ac 5227 unsigned int top_id, top_index;
906e58ca
NC		 5228 asection *section;
5229 asection **input_list, **list;
5230 bfd_size_type amt;
5231 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5232
4dfe6ac6
NC		 5233 if (htab == NULL)
5234 return 0;
906e58ca
NC		 5235 if (! is_elf_hash_table (htab))
5236 return 0;
5237
5238 /* Count the number of input BFDs and find the top input section id. */
5239 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5240 input_bfd != NULL;
c72f2fb2 5241 input_bfd = input_bfd->link.next)
906e58ca
NC		 5242 {
5243 bfd_count += 1;
5244 for (section = input_bfd->sections;
5245 section != NULL;
5246 section = section->next)
5247 {
5248 if (top_id < section->id)
5249 top_id = section->id;
5250 }
5251 }
5252 htab->bfd_count = bfd_count;
5253
5254 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5255 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5256 if (htab->stub_group == NULL)
5257 return -1;
fe33d2fa 5258 htab->top_id = top_id;
906e58ca
NC		 5259
5260 /* We can't use output_bfd->section_count here to find the top output
5261 section index as some sections may have been removed, and
5262 _bfd_strip_section_from_output doesn't renumber the indices. */
5263 for (section = output_bfd->sections, top_index = 0;
5264 section != NULL;
5265 section = section->next)
5266 {
5267 if (top_index < section->index)
5268 top_index = section->index;
5269 }
5270
5271 htab->top_index = top_index;
5272 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5273 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5274 htab->input_list = input_list;
5275 if (input_list == NULL)
5276 return -1;
5277
5278 /* For sections we aren't interested in, mark their entries with a
5279 value we can check later. */
5280 list = input_list + top_index;
5281 do
5282 *list = bfd_abs_section_ptr;
5283 while (list-- != input_list);
5284
5285 for (section = output_bfd->sections;
5286 section != NULL;
5287 section = section->next)
5288 {
5289 if ((section->flags & SEC_CODE) != 0)
5290 input_list[section->index] = NULL;
5291 }
5292
5293 return 1;
5294}
5295
5296/* The linker repeatedly calls this function for each input section,
5297 in the order that input sections are linked into output sections.
5298 Build lists of input sections to determine groupings between which
5299 we may insert linker stubs. */
5300
5301void
5302elf32_arm_next_input_section (struct bfd_link_info *info,
5303 asection *isec)
5304{
5305 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5306
4dfe6ac6
NC		 5307 if (htab == NULL)
5308 return;
5309
906e58ca
NC		 5310 if (isec->output_section->index <= htab->top_index)
5311 {
5312 asection **list = htab->input_list + isec->output_section->index;
5313
a7470592 5314 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5315 {
5316 /* Steal the link_sec pointer for our list. */
5317#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5318 /* This happens to make the list in reverse order,
07d72278 5319 which we reverse later. */
906e58ca
NC		 5320 PREV_SEC (isec) = *list;
5321 *list = isec;
5322 }
5323 }
5324}
5325
5326/* See whether we can group stub sections together. Grouping stub
5327 sections may result in fewer stubs. More importantly, we need to
07d72278 5328 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5329 .fini output sections respectively, because glibc splits the
5330 _init and _fini functions into multiple parts. Putting a stub in
5331 the middle of a function is not a good idea. */
5332
5333static void
5334group_sections (struct elf32_arm_link_hash_table *htab,
5335 bfd_size_type stub_group_size,
07d72278 5336 bfd_boolean stubs_always_after_branch)
906e58ca 5337{
07d72278 5338 asection **list = htab->input_list;
906e58ca
NC		 5339
5340 do
5341 {
5342 asection *tail = *list;
07d72278 5343 asection *head;
906e58ca
NC		 5344
5345 if (tail == bfd_abs_section_ptr)
5346 continue;
5347
07d72278
DJ		 5348 /* Reverse the list: we must avoid placing stubs at the
5349 beginning of the section because the beginning of the text
5350 section may be required for an interrupt vector in bare metal
5351 code. */
5352#define NEXT_SEC PREV_SEC
e780aef2
CL		 5353 head = NULL;
5354 while (tail != NULL)
99059e56
RM		 5355 {
5356 /* Pop from tail. */
5357 asection *item = tail;
5358 tail = PREV_SEC (item);
e780aef2 5359
99059e56
RM		 5360 /* Push on head. */
5361 NEXT_SEC (item) = head;
5362 head = item;
5363 }
07d72278
DJ		 5364
5365 while (head != NULL)
906e58ca
NC		 5366 {
5367 asection *curr;
07d72278 5368 asection *next;
e780aef2
CL		 5369 bfd_vma stub_group_start = head->output_offset;
5370 bfd_vma end_of_next;
906e58ca 5371
07d72278 5372 curr = head;
e780aef2 5373 while (NEXT_SEC (curr) != NULL)
8cd931b7 5374 {
e780aef2
CL		 5375 next = NEXT_SEC (curr);
5376 end_of_next = next->output_offset + next->size;
5377 if (end_of_next - stub_group_start >= stub_group_size)
5378 /* End of NEXT is too far from start, so stop. */
8cd931b7 5379 break;
e780aef2
CL		 5380 /* Add NEXT to the group. */
5381 curr = next;
8cd931b7 5382 }
906e58ca 5383
07d72278 5384 /* OK, the size from the start to the start of CURR is less
906e58ca 5385 than stub_group_size and thus can be handled by one stub
07d72278 5386 section. (Or the head section is itself larger than
906e58ca
NC		 5387 stub_group_size, in which case we may be toast.)
5388 We should really be keeping track of the total size of
5389 stubs added here, as stubs contribute to the final output
7fb9f789 5390 section size. */
906e58ca
NC		 5391 do
5392 {
07d72278 5393 next = NEXT_SEC (head);
906e58ca 5394 /* Set up this stub group. */
07d72278 5395 htab->stub_group[head->id].link_sec = curr;
906e58ca 5396 }
07d72278 5397 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5398
5399 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5400 bytes after the stub section can be handled by it too. */
5401 if (!stubs_always_after_branch)
906e58ca 5402 {
e780aef2
CL		 5403 stub_group_start = curr->output_offset + curr->size;
5404
8cd931b7 5405 while (next != NULL)
906e58ca 5406 {
e780aef2
CL		 5407 end_of_next = next->output_offset + next->size;
5408 if (end_of_next - stub_group_start >= stub_group_size)
5409 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5410 break;
e780aef2 5411 /* Add NEXT to the stub group. */
07d72278
DJ		 5412 head = next;
5413 next = NEXT_SEC (head);
5414 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5415 }
5416 }
07d72278 5417 head = next;
906e58ca
NC		 5418 }
5419 }
07d72278 5420 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5421
5422 free (htab->input_list);
5423#undef PREV_SEC
07d72278 5424#undef NEXT_SEC
906e58ca
NC		 5425}
5426
48229727
JB		 5427/* Comparison function for sorting/searching relocations relating to Cortex-A8
5428 erratum fix. */
5429
5430static int
5431a8_reloc_compare (const void *a, const void *b)
5432{
21d799b5
NC		 5433 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5434 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5435
5436 if (ra->from < rb->from)
5437 return -1;
5438 else if (ra->from > rb->from)
5439 return 1;
5440 else
5441 return 0;
5442}
5443
5444static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5445 const char *, char **);
5446
5447/* Helper function to scan code for sequences which might trigger the Cortex-A8
5448 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5449 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5450 otherwise. */
5451
81694485
NC		 5452static bfd_boolean
5453cortex_a8_erratum_scan (bfd *input_bfd,
5454 struct bfd_link_info *info,
48229727
JB		 5455 struct a8_erratum_fix **a8_fixes_p,
5456 unsigned int *num_a8_fixes_p,
5457 unsigned int *a8_fix_table_size_p,
5458 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5459 unsigned int num_a8_relocs,
5460 unsigned prev_num_a8_fixes,
5461 bfd_boolean *stub_changed_p)
48229727
JB		 5462{
5463 asection *section;
5464 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5465 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5466 unsigned int num_a8_fixes = *num_a8_fixes_p;
5467 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5468
4dfe6ac6
NC		 5469 if (htab == NULL)
5470 return FALSE;
5471
48229727
JB		 5472 for (section = input_bfd->sections;
5473 section != NULL;
5474 section = section->next)
5475 {
5476 bfd_byte *contents = NULL;
5477 struct _arm_elf_section_data *sec_data;
5478 unsigned int span;
5479 bfd_vma base_vma;
5480
5481 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5482 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5483 || (section->flags & SEC_EXCLUDE) != 0
5484 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5485 || (section->output_section == bfd_abs_section_ptr))
5486 continue;
48229727
JB		 5487
5488 base_vma = section->output_section->vma + section->output_offset;
5489
5490 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5491 contents = elf_section_data (section)->this_hdr.contents;
48229727 5492 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5493 return TRUE;
48229727
JB		 5494
5495 sec_data = elf32_arm_section_data (section);
5496
5497 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5498 {
5499 unsigned int span_start = sec_data->map[span].vma;
5500 unsigned int span_end = (span == sec_data->mapcount - 1)
5501 ? section->size : sec_data->map[span + 1].vma;
5502 unsigned int i;
5503 char span_type = sec_data->map[span].type;
5504 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5505
5506 if (span_type != 't')
5507 continue;
5508
5509 /* Span is entirely within a single 4KB region: skip scanning. */
5510 if (((base_vma + span_start) & ~0xfff)
48229727 5511 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5512 continue;
5513
5514 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5515
5516 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5517 * The branch target is in the same 4KB region as the
5518 first half of the branch.
5519 * The instruction before the branch is a 32-bit
5520 length non-branch instruction. */
5521 for (i = span_start; i < span_end;)
5522 {
5523 unsigned int insn = bfd_getl16 (&contents[i]);
5524 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5525 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5526
99059e56
RM		 5527 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5528 insn_32bit = TRUE;
48229727
JB		 5529
5530 if (insn_32bit)
99059e56
RM		 5531 {
5532 /* Load the rest of the insn (in manual-friendly order). */
5533 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5534
5535 /* Encoding T4: B<c>.W. */
5536 is_b = (insn & 0xf800d000) == 0xf0009000;
5537 /* Encoding T1: BL<c>.W. */
5538 is_bl = (insn & 0xf800d000) == 0xf000d000;
5539 /* Encoding T2: BLX<c>.W. */
5540 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5541 /* Encoding T3: B<c>.W (not permitted in IT block). */
5542 is_bcc = (insn & 0xf800d000) == 0xf0008000
5543 && (insn & 0x07f00000) != 0x03800000;
5544 }
5545
5546 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5547
99059e56 5548 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5549 && insn_32bit
5550 && is_32bit_branch
5551 && last_was_32bit
5552 && ! last_was_branch)
99059e56
RM		 5553 {
5554 bfd_signed_vma offset = 0;
5555 bfd_boolean force_target_arm = FALSE;
48229727 5556 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5557 bfd_vma target;
5558 enum elf32_arm_stub_type stub_type = arm_stub_none;
5559 struct a8_erratum_reloc key, *found;
5560 bfd_boolean use_plt = FALSE;
48229727 5561
99059e56
RM		 5562 key.from = base_vma + i;
5563 found = (struct a8_erratum_reloc *)
5564 bsearch (&key, a8_relocs, num_a8_relocs,
5565 sizeof (struct a8_erratum_reloc),
5566 &a8_reloc_compare);
48229727
JB		 5567
5568 if (found)
5569 {
5570 char *error_message = NULL;
5571 struct elf_link_hash_entry *entry;
5572
5573 /* We don't care about the error returned from this
99059e56 5574 function, only if there is glue or not. */
48229727
JB		 5575 entry = find_thumb_glue (info, found->sym_name,
5576 &error_message);
5577
5578 if (entry)
5579 found->non_a8_stub = TRUE;
5580
92750f34 5581 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5582 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5583 && found->hash->root.plt.offset != (bfd_vma) -1)
5584 use_plt = TRUE;
5585
5586 if (found->r_type == R_ARM_THM_CALL)
5587 {
35fc36a8
RS		 5588 if (found->branch_type == ST_BRANCH_TO_ARM
5589 || use_plt)
92750f34
DJ		 5590 force_target_arm = TRUE;
5591 else
5592 force_target_thumb = TRUE;
5593 }
48229727
JB		 5594 }
5595
99059e56 5596 /* Check if we have an offending branch instruction. */
48229727
JB		 5597
5598 if (found && found->non_a8_stub)
5599 /* We've already made a stub for this instruction, e.g.
5600 it's a long branch or a Thumb->ARM stub. Assume that
5601 stub will suffice to work around the A8 erratum (see
5602 setting of always_after_branch above). */
5603 ;
99059e56
RM		 5604 else if (is_bcc)
5605 {
5606 offset = (insn & 0x7ff) << 1;
5607 offset |= (insn & 0x3f0000) >> 4;
5608 offset |= (insn & 0x2000) ? 0x40000 : 0;
5609 offset |= (insn & 0x800) ? 0x80000 : 0;
5610 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5611 if (offset & 0x100000)
5612 offset |= ~ ((bfd_signed_vma) 0xfffff);
5613 stub_type = arm_stub_a8_veneer_b_cond;
5614 }
5615 else if (is_b || is_bl || is_blx)
5616 {
5617 int s = (insn & 0x4000000) != 0;
5618 int j1 = (insn & 0x2000) != 0;
5619 int j2 = (insn & 0x800) != 0;
5620 int i1 = !(j1 ^ s);
5621 int i2 = !(j2 ^ s);
5622
5623 offset = (insn & 0x7ff) << 1;
5624 offset |= (insn & 0x3ff0000) >> 4;
5625 offset |= i2 << 22;
5626 offset |= i1 << 23;
5627 offset |= s << 24;
5628 if (offset & 0x1000000)
5629 offset |= ~ ((bfd_signed_vma) 0xffffff);
5630
5631 if (is_blx)
5632 offset &= ~ ((bfd_signed_vma) 3);
5633
5634 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5635 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5636 }
5637
5638 if (stub_type != arm_stub_none)
5639 {
5640 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5641
5642 /* The original instruction is a BL, but the target is
99059e56 5643 an ARM instruction. If we were not making a stub,
48229727
JB		 5644 the BL would have been converted to a BLX. Use the
5645 BLX stub instead in that case. */
5646 if (htab->use_blx && force_target_arm
5647 && stub_type == arm_stub_a8_veneer_bl)
5648 {
5649 stub_type = arm_stub_a8_veneer_blx;
5650 is_blx = TRUE;
5651 is_bl = FALSE;
5652 }
5653 /* Conversely, if the original instruction was
5654 BLX but the target is Thumb mode, use the BL
5655 stub. */
5656 else if (force_target_thumb
5657 && stub_type == arm_stub_a8_veneer_blx)
5658 {
5659 stub_type = arm_stub_a8_veneer_bl;
5660 is_blx = FALSE;
5661 is_bl = TRUE;
5662 }
5663
99059e56
RM		 5664 if (is_blx)
5665 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5666
99059e56
RM		 5667 /* If we found a relocation, use the proper destination,
5668 not the offset in the (unrelocated) instruction.
48229727
JB		 5669 Note this is always done if we switched the stub type
5670 above. */
99059e56
RM		 5671 if (found)
5672 offset =
81694485 5673 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5674
99059e56
RM		 5675 /* If the stub will use a Thumb-mode branch to a
5676 PLT target, redirect it to the preceding Thumb
5677 entry point. */
5678 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5679 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5680
99059e56 5681 target = pc_for_insn + offset;
48229727 5682
99059e56
RM		 5683 /* The BLX stub is ARM-mode code. Adjust the offset to
5684 take the different PC value (+8 instead of +4) into
48229727 5685 account. */
99059e56
RM		 5686 if (stub_type == arm_stub_a8_veneer_blx)
5687 offset += 4;
5688
5689 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5690 {
5691 char *stub_name = NULL;
5692
5693 if (num_a8_fixes == a8_fix_table_size)
5694 {
5695 a8_fix_table_size *= 2;
5696 a8_fixes = (struct a8_erratum_fix *)
5697 bfd_realloc (a8_fixes,
5698 sizeof (struct a8_erratum_fix)
5699 * a8_fix_table_size);
5700 }
48229727 5701
eb7c4339
NS		 5702 if (num_a8_fixes < prev_num_a8_fixes)
5703 {
5704 /* If we're doing a subsequent scan,
5705 check if we've found the same fix as
5706 before, and try and reuse the stub
5707 name. */
5708 stub_name = a8_fixes[num_a8_fixes].stub_name;
5709 if ((a8_fixes[num_a8_fixes].section != section)
5710 || (a8_fixes[num_a8_fixes].offset != i))
5711 {
5712 free (stub_name);
5713 stub_name = NULL;
5714 *stub_changed_p = TRUE;
5715 }
5716 }
5717
5718 if (!stub_name)
5719 {
21d799b5 5720 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5721 if (stub_name != NULL)
5722 sprintf (stub_name, "%x:%x", section->id, i);
5723 }
48229727 5724
99059e56
RM		 5725 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5726 a8_fixes[num_a8_fixes].section = section;
5727 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5728 a8_fixes[num_a8_fixes].target_offset =
5729 target - base_vma;
99059e56
RM		 5730 a8_fixes[num_a8_fixes].orig_insn = insn;
5731 a8_fixes[num_a8_fixes].stub_name = stub_name;
5732 a8_fixes[num_a8_fixes].stub_type = stub_type;
5733 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5734 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5735
99059e56
RM		 5736 num_a8_fixes++;
5737 }
5738 }
5739 }
48229727 5740
99059e56
RM		 5741 i += insn_32bit ? 4 : 2;
5742 last_was_32bit = insn_32bit;
48229727 5743 last_was_branch = is_32bit_branch;
99059e56
RM		 5744 }
5745 }
48229727
JB		 5746
5747 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5748 free (contents);
48229727 5749 }
fe33d2fa 5750
48229727
JB		 5751 *a8_fixes_p = a8_fixes;
5752 *num_a8_fixes_p = num_a8_fixes;
5753 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5754
81694485 5755 return FALSE;
48229727
JB		 5756}
5757
b715f643
TP		 5758/* Create or update a stub entry depending on whether the stub can already be
5759 found in HTAB. The stub is identified by:
5760 - its type STUB_TYPE
5761 - its source branch (note that several can share the same stub) whose
5762 section and relocation (if any) are given by SECTION and IRELA
5763 respectively
5764 - its target symbol whose input section, hash, name, value and branch type
5765 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5766 respectively
5767
5768 If found, the value of the stub's target symbol is updated from SYM_VALUE
5769 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5770 TRUE and the stub entry is initialized.
5771
0955507f
TP		 5772 Returns the stub that was created or updated, or NULL if an error
5773 occurred. */
b715f643 5774
0955507f 5775static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5776elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5777 enum elf32_arm_stub_type stub_type, asection *section,
5778 Elf_Internal_Rela *irela, asection *sym_sec,
5779 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5780 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5781 bfd_boolean *new_stub)
5782{
5783 const asection *id_sec;
5784 char *stub_name;
5785 struct elf32_arm_stub_hash_entry *stub_entry;
5786 unsigned int r_type;
4f4faa4d 5787 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5788
5789 BFD_ASSERT (stub_type != arm_stub_none);
5790 *new_stub = FALSE;
5791
4f4faa4d
TP		 5792 if (sym_claimed)
5793 stub_name = sym_name;
5794 else
5795 {
5796 BFD_ASSERT (irela);
5797 BFD_ASSERT (section);
c2abbbeb 5798 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5799
4f4faa4d
TP		 5800 /* Support for grouping stub sections. */
5801 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5802
4f4faa4d
TP		 5803 /* Get the name of this stub. */
5804 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5805 stub_type);
5806 if (!stub_name)
0955507f 5807 return NULL;
4f4faa4d 5808 }
b715f643
TP		 5809
5810 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5811 FALSE);
5812 /* The proper stub has already been created, just update its value. */
5813 if (stub_entry != NULL)
5814 {
4f4faa4d
TP		 5815 if (!sym_claimed)
5816 free (stub_name);
b715f643 5817 stub_entry->target_value = sym_value;
0955507f 5818 return stub_entry;
b715f643
TP		 5819 }
5820
daa4adae 5821 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5822 if (stub_entry == NULL)
5823 {
4f4faa4d
TP		 5824 if (!sym_claimed)
5825 free (stub_name);
0955507f 5826 return NULL;
b715f643
TP		 5827 }
5828
5829 stub_entry->target_value = sym_value;
5830 stub_entry->target_section = sym_sec;
5831 stub_entry->stub_type = stub_type;
5832 stub_entry->h = hash;
5833 stub_entry->branch_type = branch_type;
5834
4f4faa4d
TP		 5835 if (sym_claimed)
5836 stub_entry->output_name = sym_name;
5837 else
b715f643 5838 {
4f4faa4d
TP		 5839 if (sym_name == NULL)
5840 sym_name = "unnamed";
5841 stub_entry->output_name = (char *)
5842 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5843 + strlen (sym_name));
5844 if (stub_entry->output_name == NULL)
5845 {
5846 free (stub_name);
0955507f 5847 return NULL;
4f4faa4d 5848 }
b715f643 5849
4f4faa4d
TP		 5850 /* For historical reasons, use the existing names for ARM-to-Thumb and
5851 Thumb-to-ARM stubs. */
5852 r_type = ELF32_R_TYPE (irela->r_info);
5853 if ((r_type == (unsigned int) R_ARM_THM_CALL
5854 || r_type == (unsigned int) R_ARM_THM_JUMP24
5855 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5856 && branch_type == ST_BRANCH_TO_ARM)
5857 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5858 else if ((r_type == (unsigned int) R_ARM_CALL
5859 || r_type == (unsigned int) R_ARM_JUMP24)
5860 && branch_type == ST_BRANCH_TO_THUMB)
5861 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5862 else
5863 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5864 }
b715f643
TP		 5865
5866 *new_stub = TRUE;
0955507f 5867 return stub_entry;
b715f643
TP		 5868}
5869
4ba2ef8f
TP		 5870/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5871 gateway veneer to transition from non secure to secure state and create them
5872 accordingly.
5873
5874 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5875 defines the conditions that govern Secure Gateway veneer creation for a
5876 given symbol <SYM> as follows:
5877 - it has function type
5878 - it has non local binding
5879 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5880 same type, binding and value as <SYM> (called normal symbol).
5881 An entry function can handle secure state transition itself in which case
5882 its special symbol would have a different value from the normal symbol.
5883
5884 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5885 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5886 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5887 created.
4ba2ef8f 5888
0955507f 5889 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5890
5891static bfd_boolean
5892cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5893 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5894 int *cmse_stub_created)
4ba2ef8f
TP		 5895{
5896 const struct elf_backend_data *bed;
5897 Elf_Internal_Shdr *symtab_hdr;
5898 unsigned i, j, sym_count, ext_start;
5899 Elf_Internal_Sym *cmse_sym, *local_syms;
5900 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5901 enum arm_st_branch_type branch_type;
5902 char *sym_name, *lsym_name;
5903 bfd_vma sym_value;
5904 asection *section;
0955507f
TP		 5905 struct elf32_arm_stub_hash_entry *stub_entry;
5906 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5907
5908 bed = get_elf_backend_data (input_bfd);
5909 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5910 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5911 ext_start = symtab_hdr->sh_info;
5912 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5913 && out_attr[Tag_CPU_arch_profile].i == 'M');
5914
5915 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5916 if (local_syms == NULL)
5917 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5918 symtab_hdr->sh_info, 0, NULL, NULL,
5919 NULL);
5920 if (symtab_hdr->sh_info && local_syms == NULL)
5921 return FALSE;
5922
5923 /* Scan symbols. */
5924 for (i = 0; i < sym_count; i++)
5925 {
5926 cmse_invalid = FALSE;
5927
5928 if (i < ext_start)
5929 {
5930 cmse_sym = &local_syms[i];
5931 /* Not a special symbol. */
5932 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5933 continue;
5934 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5935 symtab_hdr->sh_link,
5936 cmse_sym->st_name);
5937 /* Special symbol with local binding. */
5938 cmse_invalid = TRUE;
5939 }
5940 else
5941 {
5942 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5943 sym_name = (char *) cmse_hash->root.root.root.string;
5944
5945 /* Not a special symbol. */
5946 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5947 continue;
5948
5949 /* Special symbol has incorrect binding or type. */
5950 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5951 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5952 || cmse_hash->root.type != STT_FUNC)
5953 cmse_invalid = TRUE;
5954 }
5955
5956 if (!is_v8m)
5957 {
90b6238f
AM		 5958 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5959 "ARMv8-M architecture or later"),
4eca0228 5960 input_bfd, sym_name);
4ba2ef8f
TP		 5961 is_v8m = TRUE; /* Avoid multiple warning. */
5962 ret = FALSE;
5963 }
5964
5965 if (cmse_invalid)
5966 {
90b6238f
AM		 5967 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
5968 " a global or weak function symbol"),
4eca0228 5969 input_bfd, sym_name);
4ba2ef8f
TP		 5970 ret = FALSE;
5971 if (i < ext_start)
5972 continue;
5973 }
5974
5975 sym_name += strlen (CMSE_PREFIX);
5976 hash = (struct elf32_arm_link_hash_entry *)
5977 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5978
5979 /* No associated normal symbol or it is neither global nor weak. */
5980 if (!hash
5981 || (hash->root.root.type != bfd_link_hash_defined
5982 && hash->root.root.type != bfd_link_hash_defweak)
5983 || hash->root.type != STT_FUNC)
5984 {
5985 /* Initialize here to avoid warning about use of possibly
5986 uninitialized variable. */
5987 j = 0;
5988
5989 if (!hash)
5990 {
5991 /* Searching for a normal symbol with local binding. */
5992 for (; j < ext_start; j++)
5993 {
5994 lsym_name =
5995 bfd_elf_string_from_elf_section (input_bfd,
5996 symtab_hdr->sh_link,
5997 local_syms[j].st_name);
5998 if (!strcmp (sym_name, lsym_name))
5999 break;
6000 }
6001 }
6002
6003 if (hash || j < ext_start)
6004 {
4eca0228 6005 _bfd_error_handler
90b6238f
AM		 6006 (_("%pB: invalid standard symbol `%s'; it must be "
6007 "a global or weak function symbol"),
6008 input_bfd, sym_name);
4ba2ef8f
TP		 6009 }
6010 else
4eca0228 6011 _bfd_error_handler
90b6238f 6012 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6013 ret = FALSE;
6014 if (!hash)
6015 continue;
6016 }
6017
6018 sym_value = hash->root.root.u.def.value;
6019 section = hash->root.root.u.def.section;
6020
6021 if (cmse_hash->root.root.u.def.section != section)
6022 {
4eca0228 6023 _bfd_error_handler
90b6238f 6024 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6025 input_bfd, sym_name);
6026 ret = FALSE;
6027 }
6028 if (cmse_hash->root.root.u.def.value != sym_value)
6029 continue; /* Ignore: could be an entry function starting with SG. */
6030
6031 /* If this section is a link-once section that will be discarded, then
6032 don't create any stubs. */
6033 if (section->output_section == NULL)
6034 {
4eca0228 6035 _bfd_error_handler
90b6238f 6036 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6037 continue;
6038 }
6039
6040 if (hash->root.size == 0)
6041 {
4eca0228 6042 _bfd_error_handler
90b6238f 6043 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6044 ret = FALSE;
6045 }
6046
6047 if (!ret)
6048 continue;
6049 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6050 stub_entry
4ba2ef8f
TP		 6051 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6052 NULL, NULL, section, hash, sym_name,
6053 sym_value, branch_type, &new_stub);
6054
0955507f 6055 if (stub_entry == NULL)
4ba2ef8f
TP		 6056 ret = FALSE;
6057 else
6058 {
6059 BFD_ASSERT (new_stub);
0955507f 6060 (*cmse_stub_created)++;
4ba2ef8f
TP		 6061 }
6062 }
6063
6064 if (!symtab_hdr->contents)
6065 free (local_syms);
6066 return ret;
6067}
6068
0955507f
TP		 6069/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6070 code entry function, ie can be called from non secure code without using a
6071 veneer. */
6072
6073static bfd_boolean
6074cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6075{
42484486 6076 bfd_byte contents[4];
0955507f
TP		 6077 uint32_t first_insn;
6078 asection *section;
6079 file_ptr offset;
6080 bfd *abfd;
6081
6082 /* Defined symbol of function type. */
6083 if (hash->root.root.type != bfd_link_hash_defined
6084 && hash->root.root.type != bfd_link_hash_defweak)
6085 return FALSE;
6086 if (hash->root.type != STT_FUNC)
6087 return FALSE;
6088
6089 /* Read first instruction. */
6090 section = hash->root.root.u.def.section;
6091 abfd = section->owner;
6092 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6093 if (!bfd_get_section_contents (abfd, section, contents, offset,
6094 sizeof (contents)))
0955507f
TP		 6095 return FALSE;
6096
42484486
TP		 6097 first_insn = bfd_get_32 (abfd, contents);
6098
6099 /* Starts by SG instruction. */
0955507f
TP		 6100 return first_insn == 0xe97fe97f;
6101}
6102
6103/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6104 secure gateway veneers (ie. the veneers was not in the input import library)
6105 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6106
6107static bfd_boolean
6108arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6109{
6110 struct elf32_arm_stub_hash_entry *stub_entry;
6111 struct bfd_link_info *info;
6112
6113 /* Massage our args to the form they really have. */
6114 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6115 info = (struct bfd_link_info *) gen_info;
6116
6117 if (info->out_implib_bfd)
6118 return TRUE;
6119
6120 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6121 return TRUE;
6122
6123 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6124 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6125
6126 return TRUE;
6127}
6128
6129/* Set offset of each secure gateway veneers so that its address remain
6130 identical to the one in the input import library referred by
6131 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6132 (present in input import library but absent from the executable being
6133 linked) or if new veneers appeared and there is no output import library
6134 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6135 number of secure gateway veneers found in the input import library.
6136
6137 The function returns whether an error occurred. If no error occurred,
6138 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6139 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6140 veneer observed set for new veneers to be layed out after. */
6141
6142static bfd_boolean
6143set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6144 struct elf32_arm_link_hash_table *htab,
6145 int *cmse_stub_created)
6146{
6147 long symsize;
6148 char *sym_name;
6149 flagword flags;
6150 long i, symcount;
6151 bfd *in_implib_bfd;
6152 asection *stub_out_sec;
6153 bfd_boolean ret = TRUE;
6154 Elf_Internal_Sym *intsym;
6155 const char *out_sec_name;
6156 bfd_size_type cmse_stub_size;
6157 asymbol **sympp = NULL, *sym;
6158 struct elf32_arm_link_hash_entry *hash;
6159 const insn_sequence *cmse_stub_template;
6160 struct elf32_arm_stub_hash_entry *stub_entry;
6161 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6162 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6163 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6164
6165 /* No input secure gateway import library. */
6166 if (!htab->in_implib_bfd)
6167 return TRUE;
6168
6169 in_implib_bfd = htab->in_implib_bfd;
6170 if (!htab->cmse_implib)
6171 {
871b3ab2 6172 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6173 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6174 return FALSE;
6175 }
6176
6177 /* Get symbol table size. */
6178 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6179 if (symsize < 0)
6180 return FALSE;
6181
6182 /* Read in the input secure gateway import library's symbol table. */
6183 sympp = (asymbol **) xmalloc (symsize);
6184 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6185 if (symcount < 0)
6186 {
6187 ret = FALSE;
6188 goto free_sym_buf;
6189 }
6190
6191 htab->new_cmse_stub_offset = 0;
6192 cmse_stub_size =
6193 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6194 &cmse_stub_template,
6195 &cmse_stub_template_size);
6196 out_sec_name =
6197 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6198 stub_out_sec =
6199 bfd_get_section_by_name (htab->obfd, out_sec_name);
6200 if (stub_out_sec != NULL)
6201 cmse_stub_sec_vma = stub_out_sec->vma;
6202
6203 /* Set addresses of veneers mentionned in input secure gateway import
6204 library's symbol table. */
6205 for (i = 0; i < symcount; i++)
6206 {
6207 sym = sympp[i];
6208 flags = sym->flags;
6209 sym_name = (char *) bfd_asymbol_name (sym);
6210 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6211
6212 if (sym->section != bfd_abs_section_ptr
6213 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6214 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6215 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6216 != ST_BRANCH_TO_THUMB))
6217 {
90b6238f
AM		 6218 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6219 "symbol should be absolute, global and "
6220 "refer to Thumb functions"),
4eca0228 6221 in_implib_bfd, sym_name);
0955507f
TP		 6222 ret = FALSE;
6223 continue;
6224 }
6225
6226 veneer_value = bfd_asymbol_value (sym);
6227 stub_offset = veneer_value - cmse_stub_sec_vma;
6228 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6229 FALSE, FALSE);
6230 hash = (struct elf32_arm_link_hash_entry *)
6231 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6232
6233 /* Stub entry should have been created by cmse_scan or the symbol be of
6234 a secure function callable from non secure code. */
6235 if (!stub_entry && !hash)
6236 {
6237 bfd_boolean new_stub;
6238
4eca0228 6239 _bfd_error_handler
90b6238f 6240 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6241 hash = (struct elf32_arm_link_hash_entry *)
6242 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6243 stub_entry
6244 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6245 NULL, NULL, bfd_abs_section_ptr, hash,
6246 sym_name, veneer_value,
6247 ST_BRANCH_TO_THUMB, &new_stub);
6248 if (stub_entry == NULL)
6249 ret = FALSE;
6250 else
6251 {
6252 BFD_ASSERT (new_stub);
6253 new_cmse_stubs_created++;
6254 (*cmse_stub_created)++;
6255 }
6256 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6257 stub_entry->stub_offset = stub_offset;
6258 }
6259 /* Symbol found is not callable from non secure code. */
6260 else if (!stub_entry)
6261 {
6262 if (!cmse_entry_fct_p (hash))
6263 {
90b6238f 6264 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6265 sym_name);
0955507f
TP		 6266 ret = FALSE;
6267 }
6268 continue;
6269 }
6270 else
6271 {
6272 /* Only stubs for SG veneers should have been created. */
6273 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6274
6275 /* Check visibility hasn't changed. */
6276 if (!!(flags & BSF_GLOBAL)
6277 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6278 _bfd_error_handler
90b6238f 6279 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6280 sym_name);
6281
6282 stub_entry->stub_offset = stub_offset;
6283 }
6284
6285 /* Size should match that of a SG veneer. */
6286 if (intsym->st_size != cmse_stub_size)
6287 {
90b6238f 6288 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6289 in_implib_bfd, sym_name);
0955507f
TP		 6290 ret = FALSE;
6291 }
6292
6293 /* Previous veneer address is before current SG veneer section. */
6294 if (veneer_value < cmse_stub_sec_vma)
6295 {
6296 /* Avoid offset underflow. */
6297 if (stub_entry)
6298 stub_entry->stub_offset = 0;
6299 stub_offset = 0;
6300 ret = FALSE;
6301 }
6302
6303 /* Complain if stub offset not a multiple of stub size. */
6304 if (stub_offset % cmse_stub_size)
6305 {
4eca0228 6306 _bfd_error_handler
90b6238f
AM		 6307 (_("offset of veneer for entry function `%s' not a multiple of "
6308 "its size"), sym_name);
0955507f
TP		 6309 ret = FALSE;
6310 }
6311
6312 if (!ret)
6313 continue;
6314
6315 new_cmse_stubs_created--;
6316 if (veneer_value < cmse_stub_array_start)
6317 cmse_stub_array_start = veneer_value;
6318 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6319 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6320 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6321 }
6322
6323 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6324 {
6325 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6326 _bfd_error_handler
0955507f
TP		 6327 (_("new entry function(s) introduced but no output import library "
6328 "specified:"));
6329 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6330 }
6331
6332 if (cmse_stub_array_start != cmse_stub_sec_vma)
6333 {
4eca0228 6334 _bfd_error_handler
90b6238f 6335 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6336 out_sec_name);
6337 ret = FALSE;
6338 }
6339
6340free_sym_buf:
6341 free (sympp);
6342 return ret;
6343}
6344
906e58ca
NC		 6345/* Determine and set the size of the stub section for a final link.
6346
6347 The basic idea here is to examine all the relocations looking for
6348 PC-relative calls to a target that is unreachable with a "bl"
6349 instruction. */
6350
6351bfd_boolean
6352elf32_arm_size_stubs (bfd *output_bfd,
6353 bfd *stub_bfd,
6354 struct bfd_link_info *info,
6355 bfd_signed_vma group_size,
7a89b94e 6356 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6357 asection *,
7a89b94e 6358 unsigned int),
906e58ca
NC		 6359 void (*layout_sections_again) (void))
6360{
0955507f 6361 bfd_boolean ret = TRUE;
4ba2ef8f 6362 obj_attribute *out_attr;
0955507f 6363 int cmse_stub_created = 0;
906e58ca 6364 bfd_size_type stub_group_size;
4ba2ef8f 6365 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6366 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6367 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6368 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6369 struct a8_erratum_reloc *a8_relocs = NULL;
6370 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6371
4dfe6ac6
NC		 6372 if (htab == NULL)
6373 return FALSE;
6374
48229727
JB		 6375 if (htab->fix_cortex_a8)
6376 {
21d799b5 6377 a8_fixes = (struct a8_erratum_fix *)
99059e56 6378 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6379 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6380 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6381 }
906e58ca
NC		 6382
6383 /* Propagate mach to stub bfd, because it may not have been
6384 finalized when we created stub_bfd. */
6385 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6386 bfd_get_mach (output_bfd));
6387
6388 /* Stash our params away. */
6389 htab->stub_bfd = stub_bfd;
6390 htab->add_stub_section = add_stub_section;
6391 htab->layout_sections_again = layout_sections_again;
07d72278 6392 stubs_always_after_branch = group_size < 0;
48229727 6393
4ba2ef8f
TP		 6394 out_attr = elf_known_obj_attributes_proc (output_bfd);
6395 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6396
48229727
JB		 6397 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6398 as the first half of a 32-bit branch straddling two 4K pages. This is a
6399 crude way of enforcing that. */
6400 if (htab->fix_cortex_a8)
6401 stubs_always_after_branch = 1;
6402
906e58ca
NC		 6403 if (group_size < 0)
6404 stub_group_size = -group_size;
6405 else
6406 stub_group_size = group_size;
6407
6408 if (stub_group_size == 1)
6409 {
6410 /* Default values. */
6411 /* Thumb branch range is +-4MB has to be used as the default
6412 maximum size (a given section can contain both ARM and Thumb
6413 code, so the worst case has to be taken into account).
6414
6415 This value is 24K less than that, which allows for 2025
6416 12-byte stubs. If we exceed that, then we will fail to link.
6417 The user will have to relink with an explicit group size
6418 option. */
6419 stub_group_size = 4170000;
6420 }
6421
07d72278 6422 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6423
3ae046cc
NS		 6424 /* If we're applying the cortex A8 fix, we need to determine the
6425 program header size now, because we cannot change it later --
6426 that could alter section placements. Notice the A8 erratum fix
6427 ends up requiring the section addresses to remain unchanged
6428 modulo the page size. That's something we cannot represent
6429 inside BFD, and we don't want to force the section alignment to
6430 be the page size. */
6431 if (htab->fix_cortex_a8)
6432 (*htab->layout_sections_again) ();
6433
906e58ca
NC		 6434 while (1)
6435 {
6436 bfd *input_bfd;
6437 unsigned int bfd_indx;
6438 asection *stub_sec;
d7c5bd02 6439 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6440 bfd_boolean stub_changed = FALSE;
6441 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6442
48229727 6443 num_a8_fixes = 0;
906e58ca
NC		 6444 for (input_bfd = info->input_bfds, bfd_indx = 0;
6445 input_bfd != NULL;
c72f2fb2 6446 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6447 {
6448 Elf_Internal_Shdr *symtab_hdr;
6449 asection *section;
6450 Elf_Internal_Sym *local_syms = NULL;
6451
99059e56
RM		 6452 if (!is_arm_elf (input_bfd))
6453 continue;
adbcc655 6454
48229727
JB		 6455 num_a8_relocs = 0;
6456
906e58ca
NC		 6457 /* We'll need the symbol table in a second. */
6458 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6459 if (symtab_hdr->sh_info == 0)
6460 continue;
6461
4ba2ef8f
TP		 6462 /* Limit scan of symbols to object file whose profile is
6463 Microcontroller to not hinder performance in the general case. */
6464 if (m_profile && first_veneer_scan)
6465 {
6466 struct elf_link_hash_entry **sym_hashes;
6467
6468 sym_hashes = elf_sym_hashes (input_bfd);
6469 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6470 &cmse_stub_created))
4ba2ef8f 6471 goto error_ret_free_local;
0955507f
TP		 6472
6473 if (cmse_stub_created != 0)
6474 stub_changed = TRUE;
4ba2ef8f
TP		 6475 }
6476
906e58ca
NC		 6477 /* Walk over each section attached to the input bfd. */
6478 for (section = input_bfd->sections;
6479 section != NULL;
6480 section = section->next)
6481 {
6482 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6483
6484 /* If there aren't any relocs, then there's nothing more
6485 to do. */
6486 if ((section->flags & SEC_RELOC) == 0
6487 || section->reloc_count == 0
6488 || (section->flags & SEC_CODE) == 0)
6489 continue;
6490
6491 /* If this section is a link-once section that will be
6492 discarded, then don't create any stubs. */
6493 if (section->output_section == NULL
6494 || section->output_section->owner != output_bfd)
6495 continue;
6496
6497 /* Get the relocs. */
6498 internal_relocs
6499 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6500 NULL, info->keep_memory);
6501 if (internal_relocs == NULL)
6502 goto error_ret_free_local;
6503
6504 /* Now examine each relocation. */
6505 irela = internal_relocs;
6506 irelaend = irela + section->reloc_count;
6507 for (; irela < irelaend; irela++)
6508 {
6509 unsigned int r_type, r_indx;
906e58ca
NC		 6510 asection *sym_sec;
6511 bfd_vma sym_value;
6512 bfd_vma destination;
6513 struct elf32_arm_link_hash_entry *hash;
7413f23f 6514 const char *sym_name;
34e77a92 6515 unsigned char st_type;
35fc36a8 6516 enum arm_st_branch_type branch_type;
48229727 6517 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6518
6519 r_type = ELF32_R_TYPE (irela->r_info);
6520 r_indx = ELF32_R_SYM (irela->r_info);
6521
6522 if (r_type >= (unsigned int) R_ARM_max)
6523 {
6524 bfd_set_error (bfd_error_bad_value);
6525 error_ret_free_internal:
6526 if (elf_section_data (section)->relocs == NULL)
6527 free (internal_relocs);
15dd01b1
TP		 6528 /* Fall through. */
6529 error_ret_free_local:
6530 if (local_syms != NULL
6531 && (symtab_hdr->contents
6532 != (unsigned char *) local_syms))
6533 free (local_syms);
6534 return FALSE;
906e58ca 6535 }
b38cadfb 6536
0855e32b
NS		 6537 hash = NULL;
6538 if (r_indx >= symtab_hdr->sh_info)
6539 hash = elf32_arm_hash_entry
6540 (elf_sym_hashes (input_bfd)
6541 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6542
0855e32b
NS		 6543 /* Only look for stubs on branch instructions, or
6544 non-relaxed TLSCALL */
906e58ca 6545 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6546 && (r_type != (unsigned int) R_ARM_THM_CALL)
6547 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6548 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6549 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6550 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6551 && (r_type != (unsigned int) R_ARM_PLT32)
6552 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6553 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6554 && r_type == elf32_arm_tls_transition
6555 (info, r_type, &hash->root)
6556 && ((hash ? hash->tls_type
6557 : (elf32_arm_local_got_tls_type
6558 (input_bfd)[r_indx]))
6559 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6560 continue;
6561
6562 /* Now determine the call target, its name, value,
6563 section. */
6564 sym_sec = NULL;
6565 sym_value = 0;
6566 destination = 0;
7413f23f 6567 sym_name = NULL;
b38cadfb 6568
0855e32b
NS		 6569 if (r_type == (unsigned int) R_ARM_TLS_CALL
6570 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6571 {
6572 /* A non-relaxed TLS call. The target is the
6573 plt-resident trampoline and nothing to do
6574 with the symbol. */
6575 BFD_ASSERT (htab->tls_trampoline > 0);
6576 sym_sec = htab->root.splt;
6577 sym_value = htab->tls_trampoline;
6578 hash = 0;
34e77a92 6579 st_type = STT_FUNC;
35fc36a8 6580 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6581 }
6582 else if (!hash)
906e58ca
NC		 6583 {
6584 /* It's a local symbol. */
6585 Elf_Internal_Sym *sym;
906e58ca
NC		 6586
6587 if (local_syms == NULL)
6588 {
6589 local_syms
6590 = (Elf_Internal_Sym *) symtab_hdr->contents;
6591 if (local_syms == NULL)
6592 local_syms
6593 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6594 symtab_hdr->sh_info, 0,
6595 NULL, NULL, NULL);
6596 if (local_syms == NULL)
6597 goto error_ret_free_internal;
6598 }
6599
6600 sym = local_syms + r_indx;
f6d250ce
TS		 6601 if (sym->st_shndx == SHN_UNDEF)
6602 sym_sec = bfd_und_section_ptr;
6603 else if (sym->st_shndx == SHN_ABS)
6604 sym_sec = bfd_abs_section_ptr;
6605 else if (sym->st_shndx == SHN_COMMON)
6606 sym_sec = bfd_com_section_ptr;
6607 else
6608 sym_sec =
6609 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6610
ffcb4889
NS		 6611 if (!sym_sec)
6612 /* This is an undefined symbol. It can never
6a631e86 6613 be resolved. */
ffcb4889 6614 continue;
fe33d2fa 6615
906e58ca
NC		 6616 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6617 sym_value = sym->st_value;
6618 destination = (sym_value + irela->r_addend
6619 + sym_sec->output_offset
6620 + sym_sec->output_section->vma);
34e77a92 6621 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6622 branch_type =
6623 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6624 sym_name
6625 = bfd_elf_string_from_elf_section (input_bfd,
6626 symtab_hdr->sh_link,
6627 sym->st_name);
906e58ca
NC		 6628 }
6629 else
6630 {
6631 /* It's an external symbol. */
906e58ca
NC		 6632 while (hash->root.root.type == bfd_link_hash_indirect
6633 || hash->root.root.type == bfd_link_hash_warning)
6634 hash = ((struct elf32_arm_link_hash_entry *)
6635 hash->root.root.u.i.link);
6636
6637 if (hash->root.root.type == bfd_link_hash_defined
6638 || hash->root.root.type == bfd_link_hash_defweak)
6639 {
6640 sym_sec = hash->root.root.u.def.section;
6641 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6642
6643 struct elf32_arm_link_hash_table *globals =
6644 elf32_arm_hash_table (info);
6645
6646 /* For a destination in a shared library,
6647 use the PLT stub as target address to
6648 decide whether a branch stub is
6649 needed. */
4dfe6ac6 6650 if (globals != NULL
362d30a1 6651 && globals->root.splt != NULL
4dfe6ac6 6652 && hash != NULL
022f8312
CL		 6653 && hash->root.plt.offset != (bfd_vma) -1)
6654 {
362d30a1 6655 sym_sec = globals->root.splt;
022f8312
CL		 6656 sym_value = hash->root.plt.offset;
6657 if (sym_sec->output_section != NULL)
6658 destination = (sym_value
6659 + sym_sec->output_offset
6660 + sym_sec->output_section->vma);
6661 }
6662 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6663 destination = (sym_value + irela->r_addend
6664 + sym_sec->output_offset
6665 + sym_sec->output_section->vma);
6666 }
69c5861e
CL		 6667 else if ((hash->root.root.type == bfd_link_hash_undefined)
6668 || (hash->root.root.type == bfd_link_hash_undefweak))
6669 {
6670 /* For a shared library, use the PLT stub as
6671 target address to decide whether a long
6672 branch stub is needed.
6673 For absolute code, they cannot be handled. */
6674 struct elf32_arm_link_hash_table *globals =
6675 elf32_arm_hash_table (info);
6676
4dfe6ac6 6677 if (globals != NULL
362d30a1 6678 && globals->root.splt != NULL
4dfe6ac6 6679 && hash != NULL
69c5861e
CL		 6680 && hash->root.plt.offset != (bfd_vma) -1)
6681 {
362d30a1 6682 sym_sec = globals->root.splt;
69c5861e
CL		 6683 sym_value = hash->root.plt.offset;
6684 if (sym_sec->output_section != NULL)
6685 destination = (sym_value
6686 + sym_sec->output_offset
6687 + sym_sec->output_section->vma);
6688 }
6689 else
6690 continue;
6691 }
906e58ca
NC		 6692 else
6693 {
6694 bfd_set_error (bfd_error_bad_value);
6695 goto error_ret_free_internal;
6696 }
34e77a92 6697 st_type = hash->root.type;
39d911fc
TP		 6698 branch_type =
6699 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6700 sym_name = hash->root.root.root.string;
906e58ca
NC		 6701 }
6702
48229727 6703 do
7413f23f 6704 {
b715f643 6705 bfd_boolean new_stub;
0955507f 6706 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6707
48229727
JB		 6708 /* Determine what (if any) linker stub is needed. */
6709 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6710 st_type, &branch_type,
6711 hash, destination, sym_sec,
48229727
JB		 6712 input_bfd, sym_name);
6713 if (stub_type == arm_stub_none)
6714 break;
6715
48229727
JB		 6716 /* We've either created a stub for this reloc already,
6717 or we are about to. */
0955507f 6718 stub_entry =
b715f643
TP		 6719 elf32_arm_create_stub (htab, stub_type, section, irela,
6720 sym_sec, hash,
6721 (char *) sym_name, sym_value,
6722 branch_type, &new_stub);
7413f23f 6723
0955507f 6724 created_stub = stub_entry != NULL;
b715f643
TP		 6725 if (!created_stub)
6726 goto error_ret_free_internal;
6727 else if (!new_stub)
6728 break;
99059e56 6729 else
b715f643 6730 stub_changed = TRUE;
99059e56
RM		 6731 }
6732 while (0);
6733
6734 /* Look for relocations which might trigger Cortex-A8
6735 erratum. */
6736 if (htab->fix_cortex_a8
6737 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6738 || r_type == (unsigned int) R_ARM_THM_JUMP19
6739 || r_type == (unsigned int) R_ARM_THM_CALL
6740 || r_type == (unsigned int) R_ARM_THM_XPC22))
6741 {
6742 bfd_vma from = section->output_section->vma
6743 + section->output_offset
6744 + irela->r_offset;
6745
6746 if ((from & 0xfff) == 0xffe)
6747 {
6748 /* Found a candidate. Note we haven't checked the
6749 destination is within 4K here: if we do so (and
6750 don't create an entry in a8_relocs) we can't tell
6751 that a branch should have been relocated when
6752 scanning later. */
6753 if (num_a8_relocs == a8_reloc_table_size)
6754 {
6755 a8_reloc_table_size *= 2;
6756 a8_relocs = (struct a8_erratum_reloc *)
6757 bfd_realloc (a8_relocs,
6758 sizeof (struct a8_erratum_reloc)
6759 * a8_reloc_table_size);
6760 }
6761
6762 a8_relocs[num_a8_relocs].from = from;
6763 a8_relocs[num_a8_relocs].destination = destination;
6764 a8_relocs[num_a8_relocs].r_type = r_type;
6765 a8_relocs[num_a8_relocs].branch_type = branch_type;
6766 a8_relocs[num_a8_relocs].sym_name = sym_name;
6767 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6768 a8_relocs[num_a8_relocs].hash = hash;
6769
6770 num_a8_relocs++;
6771 }
6772 }
906e58ca
NC		 6773 }
6774
99059e56
RM		 6775 /* We're done with the internal relocs, free them. */
6776 if (elf_section_data (section)->relocs == NULL)
6777 free (internal_relocs);
6778 }
48229727 6779
99059e56 6780 if (htab->fix_cortex_a8)
48229727 6781 {
99059e56
RM		 6782 /* Sort relocs which might apply to Cortex-A8 erratum. */
6783 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6784 sizeof (struct a8_erratum_reloc),
99059e56 6785 &a8_reloc_compare);
48229727 6786
99059e56
RM		 6787 /* Scan for branches which might trigger Cortex-A8 erratum. */
6788 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6789 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6790 a8_relocs, num_a8_relocs,
6791 prev_num_a8_fixes, &stub_changed)
6792 != 0)
48229727 6793 goto error_ret_free_local;
5e681ec4 6794 }
7f991970
AM		 6795
6796 if (local_syms != NULL
6797 && symtab_hdr->contents != (unsigned char *) local_syms)
6798 {
6799 if (!info->keep_memory)
6800 free (local_syms);
6801 else
6802 symtab_hdr->contents = (unsigned char *) local_syms;
6803 }
5e681ec4
PB		 6804 }
6805
0955507f
TP		 6806 if (first_veneer_scan
6807 && !set_cmse_veneer_addr_from_implib (info, htab,
6808 &cmse_stub_created))
6809 ret = FALSE;
6810
eb7c4339 6811 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6812 stub_changed = TRUE;
48229727 6813
906e58ca
NC		 6814 if (!stub_changed)
6815 break;
5e681ec4 6816
906e58ca
NC		 6817 /* OK, we've added some stubs. Find out the new size of the
6818 stub sections. */
6819 for (stub_sec = htab->stub_bfd->sections;
6820 stub_sec != NULL;
6821 stub_sec = stub_sec->next)
3e6b1042
DJ		 6822 {
6823 /* Ignore non-stub sections. */
6824 if (!strstr (stub_sec->name, STUB_SUFFIX))
6825 continue;
6826
6827 stub_sec->size = 0;
6828 }
b34b2d70 6829
0955507f
TP		 6830 /* Add new SG veneers after those already in the input import
6831 library. */
6832 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6833 stub_type++)
6834 {
6835 bfd_vma *start_offset_p;
6836 asection **stub_sec_p;
6837
6838 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6839 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6840 if (start_offset_p == NULL)
6841 continue;
6842
6843 BFD_ASSERT (stub_sec_p != NULL);
6844 if (*stub_sec_p != NULL)
6845 (*stub_sec_p)->size = *start_offset_p;
6846 }
6847
d7c5bd02 6848 /* Compute stub section size, considering padding. */
906e58ca 6849 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6850 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6851 stub_type++)
6852 {
6853 int size, padding;
6854 asection **stub_sec_p;
6855
6856 padding = arm_dedicated_stub_section_padding (stub_type);
6857 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6858 /* Skip if no stub input section or no stub section padding
6859 required. */
6860 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6861 continue;
6862 /* Stub section padding required but no dedicated section. */
6863 BFD_ASSERT (stub_sec_p);
6864
6865 size = (*stub_sec_p)->size;
6866 size = (size + padding - 1) & ~(padding - 1);
6867 (*stub_sec_p)->size = size;
6868 }
906e58ca 6869
48229727
JB		 6870 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6871 if (htab->fix_cortex_a8)
99059e56
RM		 6872 for (i = 0; i < num_a8_fixes; i++)
6873 {
48229727 6874 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6875 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6876
6877 if (stub_sec == NULL)
7f991970 6878 return FALSE;
48229727 6879
99059e56
RM		 6880 stub_sec->size
6881 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6882 NULL);
6883 }
48229727
JB		 6884
6885
906e58ca
NC		 6886 /* Ask the linker to do its stuff. */
6887 (*htab->layout_sections_again) ();
4ba2ef8f 6888 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6889 }
6890
48229727
JB		 6891 /* Add stubs for Cortex-A8 erratum fixes now. */
6892 if (htab->fix_cortex_a8)
6893 {
6894 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6895 {
6896 struct elf32_arm_stub_hash_entry *stub_entry;
6897 char *stub_name = a8_fixes[i].stub_name;
6898 asection *section = a8_fixes[i].section;
6899 unsigned int section_id = a8_fixes[i].section->id;
6900 asection *link_sec = htab->stub_group[section_id].link_sec;
6901 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6902 const insn_sequence *template_sequence;
6903 int template_size, size = 0;
6904
6905 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6906 TRUE, FALSE);
6907 if (stub_entry == NULL)
6908 {
871b3ab2 6909 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6910 section->owner, stub_name);
99059e56
RM		 6911 return FALSE;
6912 }
6913
6914 stub_entry->stub_sec = stub_sec;
0955507f 6915 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6916 stub_entry->id_sec = link_sec;
6917 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6918 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6919 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6920 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6921 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6922 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6923
99059e56
RM		 6924 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6925 &template_sequence,
6926 &template_size);
48229727 6927
99059e56
RM		 6928 stub_entry->stub_size = size;
6929 stub_entry->stub_template = template_sequence;
6930 stub_entry->stub_template_size = template_size;
6931 }
48229727
JB		 6932
6933 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6934 elf32_arm_write_section(). */
48229727
JB		 6935 htab->a8_erratum_fixes = a8_fixes;
6936 htab->num_a8_erratum_fixes = num_a8_fixes;
6937 }
6938 else
6939 {
6940 htab->a8_erratum_fixes = NULL;
6941 htab->num_a8_erratum_fixes = 0;
6942 }
0955507f 6943 return ret;
5e681ec4
PB		 6944}
6945
906e58ca
NC		 6946/* Build all the stubs associated with the current output file. The
6947 stubs are kept in a hash table attached to the main linker hash
6948 table. We also set up the .plt entries for statically linked PIC
6949 functions here. This function is called via arm_elf_finish in the
6950 linker. */
252b5132 6951
906e58ca
NC		 6952bfd_boolean
6953elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6954{
906e58ca
NC		 6955 asection *stub_sec;
6956 struct bfd_hash_table *table;
0955507f 6957 enum elf32_arm_stub_type stub_type;
906e58ca 6958 struct elf32_arm_link_hash_table *htab;
252b5132 6959
906e58ca 6960 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6961 if (htab == NULL)
6962 return FALSE;
252b5132 6963
906e58ca
NC		 6964 for (stub_sec = htab->stub_bfd->sections;
6965 stub_sec != NULL;
6966 stub_sec = stub_sec->next)
252b5132 6967 {
906e58ca
NC		 6968 bfd_size_type size;
6969
8029a119 6970 /* Ignore non-stub sections. */
906e58ca
NC		 6971 if (!strstr (stub_sec->name, STUB_SUFFIX))
6972 continue;
6973
d7c5bd02 6974 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6975 must at least be done for stub section requiring padding and for SG
6976 veneers to ensure that a non secure code branching to a removed SG
6977 veneer causes an error. */
906e58ca 6978 size = stub_sec->size;
21d799b5 6979 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6980 if (stub_sec->contents == NULL && size != 0)
6981 return FALSE;
0955507f 6982
906e58ca 6983 stub_sec->size = 0;
252b5132
RH		 6984 }
6985
0955507f
TP		 6986 /* Add new SG veneers after those already in the input import library. */
6987 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6988 {
6989 bfd_vma *start_offset_p;
6990 asection **stub_sec_p;
6991
6992 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6993 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6994 if (start_offset_p == NULL)
6995 continue;
6996
6997 BFD_ASSERT (stub_sec_p != NULL);
6998 if (*stub_sec_p != NULL)
6999 (*stub_sec_p)->size = *start_offset_p;
7000 }
7001
906e58ca
NC		 7002 /* Build the stubs as directed by the stub hash table. */
7003 table = &htab->stub_hash_table;
7004 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7005 if (htab->fix_cortex_a8)
7006 {
7007 /* Place the cortex a8 stubs last. */
7008 htab->fix_cortex_a8 = -1;
7009 bfd_hash_traverse (table, arm_build_one_stub, info);
7010 }
252b5132 7011
906e58ca 7012 return TRUE;
252b5132
RH		 7013}
7014
9b485d32
NC		 7015/* Locate the Thumb encoded calling stub for NAME. */
7016
252b5132 7017static struct elf_link_hash_entry *
57e8b36a
NC		 7018find_thumb_glue (struct bfd_link_info *link_info,
7019 const char *name,
f2a9dd69 7020 char **error_message)
252b5132
RH		 7021{
7022 char *tmp_name;
7023 struct elf_link_hash_entry *hash;
7024 struct elf32_arm_link_hash_table *hash_table;
7025
7026 /* We need a pointer to the armelf specific hash table. */
7027 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7028 if (hash_table == NULL)
7029 return NULL;
252b5132 7030
21d799b5 7031 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7032 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7033
7034 BFD_ASSERT (tmp_name);
7035
7036 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7037
7038 hash = elf_link_hash_lookup
b34976b6 7039 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7040
b1657152 7041 if (hash == NULL
90b6238f
AM		 7042 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7043 "Thumb", tmp_name, name) == -1)
b1657152 7044 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7045
7046 free (tmp_name);
7047
7048 return hash;
7049}
7050
9b485d32
NC		 7051/* Locate the ARM encoded calling stub for NAME. */
7052
252b5132 7053static struct elf_link_hash_entry *
57e8b36a
NC		 7054find_arm_glue (struct bfd_link_info *link_info,
7055 const char *name,
f2a9dd69 7056 char **error_message)
252b5132
RH		 7057{
7058 char *tmp_name;
7059 struct elf_link_hash_entry *myh;
7060 struct elf32_arm_link_hash_table *hash_table;
7061
7062 /* We need a pointer to the elfarm specific hash table. */
7063 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7064 if (hash_table == NULL)
7065 return NULL;
252b5132 7066
21d799b5 7067 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7068 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7069
7070 BFD_ASSERT (tmp_name);
7071
7072 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7073
7074 myh = elf_link_hash_lookup
b34976b6 7075 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7076
b1657152 7077 if (myh == NULL
90b6238f
AM		 7078 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7079 "ARM", tmp_name, name) == -1)
b1657152 7080 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7081
7082 free (tmp_name);
7083
7084 return myh;
7085}
7086
8f6277f5 7087/* ARM->Thumb glue (static images):
252b5132
RH		 7088
7089 .arm
7090 __func_from_arm:
7091 ldr r12, __func_addr
7092 bx r12
7093 __func_addr:
906e58ca 7094 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7095
26079076
PB		 7096 (v5t static images)
7097 .arm
7098 __func_from_arm:
7099 ldr pc, __func_addr
7100 __func_addr:
906e58ca 7101 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7102
8f6277f5
PB		 7103 (relocatable images)
7104 .arm
7105 __func_from_arm:
7106 ldr r12, __func_offset
7107 add r12, r12, pc
7108 bx r12
7109 __func_offset:
8029a119 7110 .word func - . */
8f6277f5
PB		 7111
7112#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7113static const insn32 a2t1_ldr_insn = 0xe59fc000;
7114static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7115static const insn32 a2t3_func_addr_insn = 0x00000001;
7116
26079076
PB		 7117#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7118static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7119static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7120
8f6277f5
PB		 7121#define ARM2THUMB_PIC_GLUE_SIZE 16
7122static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7123static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7124static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7125
07d6d2b8 7126/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7127
07d6d2b8
AM		 7128 .thumb .thumb
7129 .align 2 .align 2
7130 __func_from_thumb: __func_from_thumb:
7131 bx pc push {r6, lr}
7132 nop ldr r6, __func_addr
7133 .arm mov lr, pc
7134 b func bx r6
99059e56
RM		 7135 .arm
7136 ;; back_to_thumb
7137 ldmia r13! {r6, lr}
7138 bx lr
7139 __func_addr:
07d6d2b8 7140 .word func */
252b5132
RH		 7141
7142#define THUMB2ARM_GLUE_SIZE 8
7143static const insn16 t2a1_bx_pc_insn = 0x4778;
7144static const insn16 t2a2_noop_insn = 0x46c0;
7145static const insn32 t2a3_b_insn = 0xea000000;
7146
c7b8f16e 7147#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7148#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7149#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7150
845b51d6
PB		 7151#define ARM_BX_VENEER_SIZE 12
7152static const insn32 armbx1_tst_insn = 0xe3100001;
7153static const insn32 armbx2_moveq_insn = 0x01a0f000;
7154static const insn32 armbx3_bx_insn = 0xe12fff10;
7155
7e392df6 7156#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7157static void
7158arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7159{
7160 asection * s;
8029a119 7161 bfd_byte * contents;
252b5132 7162
8029a119 7163 if (size == 0)
3e6b1042
DJ		 7164 {
7165 /* Do not include empty glue sections in the output. */
7166 if (abfd != NULL)
7167 {
3d4d4302 7168 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7169 if (s != NULL)
7170 s->flags |= SEC_EXCLUDE;
7171 }
7172 return;
7173 }
252b5132 7174
8029a119 7175 BFD_ASSERT (abfd != NULL);
252b5132 7176
3d4d4302 7177 s = bfd_get_linker_section (abfd, name);
8029a119 7178 BFD_ASSERT (s != NULL);
252b5132 7179
21d799b5 7180 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 7181
8029a119
NC		 7182 BFD_ASSERT (s->size == size);
7183 s->contents = contents;
7184}
906e58ca 7185
8029a119
NC		 7186bfd_boolean
7187bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7188{
7189 struct elf32_arm_link_hash_table * globals;
906e58ca 7190
8029a119
NC		 7191 globals = elf32_arm_hash_table (info);
7192 BFD_ASSERT (globals != NULL);
906e58ca 7193
8029a119
NC		 7194 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7195 globals->arm_glue_size,
7196 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7197
8029a119
NC		 7198 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7199 globals->thumb_glue_size,
7200 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7201
8029a119
NC		 7202 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7203 globals->vfp11_erratum_glue_size,
7204 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7205
a504d23a
LA		 7206 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7207 globals->stm32l4xx_erratum_glue_size,
7208 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7209
8029a119
NC		 7210 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7211 globals->bx_glue_size,
845b51d6
PB		 7212 ARM_BX_GLUE_SECTION_NAME);
7213
b34976b6 7214 return TRUE;
252b5132
RH		 7215}
7216
a4fd1a8e 7217/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7218 returns the symbol identifying the stub. */
7219
a4fd1a8e 7220static struct elf_link_hash_entry *
57e8b36a
NC		 7221record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7222 struct elf_link_hash_entry * h)
252b5132
RH		 7223{
7224 const char * name = h->root.root.string;
63b0f745 7225 asection * s;
252b5132
RH		 7226 char * tmp_name;
7227 struct elf_link_hash_entry * myh;
14a793b2 7228 struct bfd_link_hash_entry * bh;
252b5132 7229 struct elf32_arm_link_hash_table * globals;
dc810e39 7230 bfd_vma val;
2f475487 7231 bfd_size_type size;
252b5132
RH		 7232
7233 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7234 BFD_ASSERT (globals != NULL);
7235 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7236
3d4d4302 7237 s = bfd_get_linker_section
252b5132
RH		 7238 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7239
252b5132
RH		 7240 BFD_ASSERT (s != NULL);
7241
21d799b5 7242 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7243 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7244
7245 BFD_ASSERT (tmp_name);
7246
7247 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7248
7249 myh = elf_link_hash_lookup
b34976b6 7250 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7251
7252 if (myh != NULL)
7253 {
9b485d32 7254 /* We've already seen this guy. */
252b5132 7255 free (tmp_name);
a4fd1a8e 7256 return myh;
252b5132
RH		 7257 }
7258
57e8b36a
NC		 7259 /* The only trick here is using hash_table->arm_glue_size as the value.
7260 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7261 putting it. The +1 on the value marks that the stub has not been
7262 output yet - not that it is a Thumb function. */
14a793b2 7263 bh = NULL;
dc810e39
AM		 7264 val = globals->arm_glue_size + 1;
7265 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7266 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7267 NULL, TRUE, FALSE, &bh);
252b5132 7268
b7693d02
DJ		 7269 myh = (struct elf_link_hash_entry *) bh;
7270 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7271 myh->forced_local = 1;
7272
252b5132
RH		 7273 free (tmp_name);
7274
0e1862bb
L		 7275 if (bfd_link_pic (link_info)
7276 || globals->root.is_relocatable_executable
27e55c4d 7277 || globals->pic_veneer)
2f475487 7278 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7279 else if (globals->use_blx)
7280 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7281 else
2f475487
AM		 7282 size = ARM2THUMB_STATIC_GLUE_SIZE;
7283
7284 s->size += size;
7285 globals->arm_glue_size += size;
252b5132 7286
a4fd1a8e 7287 return myh;
252b5132
RH		 7288}
7289
845b51d6
PB		 7290/* Allocate space for ARMv4 BX veneers. */
7291
7292static void
7293record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7294{
7295 asection * s;
7296 struct elf32_arm_link_hash_table *globals;
7297 char *tmp_name;
7298 struct elf_link_hash_entry *myh;
7299 struct bfd_link_hash_entry *bh;
7300 bfd_vma val;
7301
7302 /* BX PC does not need a veneer. */
7303 if (reg == 15)
7304 return;
7305
7306 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7307 BFD_ASSERT (globals != NULL);
7308 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7309
7310 /* Check if this veneer has already been allocated. */
7311 if (globals->bx_glue_offset[reg])
7312 return;
7313
3d4d4302 7314 s = bfd_get_linker_section
845b51d6
PB		 7315 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7316
7317 BFD_ASSERT (s != NULL);
7318
7319 /* Add symbol for veneer. */
21d799b5
NC		 7320 tmp_name = (char *)
7321 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7322
845b51d6 7323 BFD_ASSERT (tmp_name);
906e58ca 7324
845b51d6 7325 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7326
845b51d6
PB		 7327 myh = elf_link_hash_lookup
7328 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7329
845b51d6 7330 BFD_ASSERT (myh == NULL);
906e58ca 7331
845b51d6
PB		 7332 bh = NULL;
7333 val = globals->bx_glue_size;
7334 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7335 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7336 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7337
7338 myh = (struct elf_link_hash_entry *) bh;
7339 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7340 myh->forced_local = 1;
7341
7342 s->size += ARM_BX_VENEER_SIZE;
7343 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7344 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7345}
7346
7347
c7b8f16e
JB		 7348/* Add an entry to the code/data map for section SEC. */
7349
7350static void
7351elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7352{
7353 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7354 unsigned int newidx;
906e58ca 7355
c7b8f16e
JB		 7356 if (sec_data->map == NULL)
7357 {
21d799b5 7358 sec_data->map = (elf32_arm_section_map *)
99059e56 7359 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7360 sec_data->mapcount = 0;
7361 sec_data->mapsize = 1;
7362 }
906e58ca 7363
c7b8f16e 7364 newidx = sec_data->mapcount++;
906e58ca 7365
c7b8f16e
JB		 7366 if (sec_data->mapcount > sec_data->mapsize)
7367 {
7368 sec_data->mapsize *= 2;
21d799b5 7369 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7370 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7371 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7372 }
7373
7374 if (sec_data->map)
7375 {
7376 sec_data->map[newidx].vma = vma;
7377 sec_data->map[newidx].type = type;
c7b8f16e 7378 }
c7b8f16e
JB		 7379}
7380
7381
7382/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7383 veneers are handled for now. */
7384
7385static bfd_vma
7386record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7387 elf32_vfp11_erratum_list *branch,
7388 bfd *branch_bfd,
7389 asection *branch_sec,
7390 unsigned int offset)
c7b8f16e
JB		 7391{
7392 asection *s;
7393 struct elf32_arm_link_hash_table *hash_table;
7394 char *tmp_name;
7395 struct elf_link_hash_entry *myh;
7396 struct bfd_link_hash_entry *bh;
7397 bfd_vma val;
7398 struct _arm_elf_section_data *sec_data;
c7b8f16e 7399 elf32_vfp11_erratum_list *newerr;
906e58ca 7400
c7b8f16e 7401 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7402 BFD_ASSERT (hash_table != NULL);
7403 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7404
3d4d4302 7405 s = bfd_get_linker_section
c7b8f16e 7406 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7407
c7b8f16e 7408 sec_data = elf32_arm_section_data (s);
906e58ca 7409
c7b8f16e 7410 BFD_ASSERT (s != NULL);
906e58ca 7411
21d799b5 7412 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7413 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7414
c7b8f16e 7415 BFD_ASSERT (tmp_name);
906e58ca 7416
c7b8f16e
JB		 7417 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7418 hash_table->num_vfp11_fixes);
906e58ca 7419
c7b8f16e
JB		 7420 myh = elf_link_hash_lookup
7421 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7422
c7b8f16e 7423 BFD_ASSERT (myh == NULL);
906e58ca 7424
c7b8f16e
JB		 7425 bh = NULL;
7426 val = hash_table->vfp11_erratum_glue_size;
7427 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7428 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7429 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7430
7431 myh = (struct elf_link_hash_entry *) bh;
7432 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7433 myh->forced_local = 1;
7434
7435 /* Link veneer back to calling location. */
c7e2358a 7436 sec_data->erratumcount += 1;
21d799b5
NC		 7437 newerr = (elf32_vfp11_erratum_list *)
7438 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7439
c7b8f16e
JB		 7440 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7441 newerr->vma = -1;
7442 newerr->u.v.branch = branch;
7443 newerr->u.v.id = hash_table->num_vfp11_fixes;
7444 branch->u.b.veneer = newerr;
7445
7446 newerr->next = sec_data->erratumlist;
7447 sec_data->erratumlist = newerr;
7448
7449 /* A symbol for the return from the veneer. */
7450 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7451 hash_table->num_vfp11_fixes);
7452
7453 myh = elf_link_hash_lookup
7454 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7455
c7b8f16e
JB		 7456 if (myh != NULL)
7457 abort ();
7458
7459 bh = NULL;
7460 val = offset + 4;
7461 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7462 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7463
c7b8f16e
JB		 7464 myh = (struct elf_link_hash_entry *) bh;
7465 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7466 myh->forced_local = 1;
7467
7468 free (tmp_name);
906e58ca 7469
c7b8f16e
JB		 7470 /* Generate a mapping symbol for the veneer section, and explicitly add an
7471 entry for that symbol to the code/data map for the section. */
7472 if (hash_table->vfp11_erratum_glue_size == 0)
7473 {
7474 bh = NULL;
7475 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7476 ever requires this erratum fix. */
c7b8f16e
JB		 7477 _bfd_generic_link_add_one_symbol (link_info,
7478 hash_table->bfd_of_glue_owner, "$a",
7479 BSF_LOCAL, s, 0, NULL,
99059e56 7480 TRUE, FALSE, &bh);
c7b8f16e
JB		 7481
7482 myh = (struct elf_link_hash_entry *) bh;
7483 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7484 myh->forced_local = 1;
906e58ca 7485
c7b8f16e 7486 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7487 BFDs. We must make a note of this generated mapping symbol
7488 ourselves so that code byteswapping works properly in
7489 elf32_arm_write_section. */
c7b8f16e
JB		 7490 elf32_arm_section_map_add (s, 'a', 0);
7491 }
906e58ca 7492
c7b8f16e
JB		 7493 s->size += VFP11_ERRATUM_VENEER_SIZE;
7494 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7495 hash_table->num_vfp11_fixes++;
906e58ca 7496
c7b8f16e
JB		 7497 /* The offset of the veneer. */
7498 return val;
7499}
7500
a504d23a
LA		 7501/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7502 veneers need to be handled because used only in Cortex-M. */
7503
7504static bfd_vma
7505record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7506 elf32_stm32l4xx_erratum_list *branch,
7507 bfd *branch_bfd,
7508 asection *branch_sec,
7509 unsigned int offset,
7510 bfd_size_type veneer_size)
7511{
7512 asection *s;
7513 struct elf32_arm_link_hash_table *hash_table;
7514 char *tmp_name;
7515 struct elf_link_hash_entry *myh;
7516 struct bfd_link_hash_entry *bh;
7517 bfd_vma val;
7518 struct _arm_elf_section_data *sec_data;
7519 elf32_stm32l4xx_erratum_list *newerr;
7520
7521 hash_table = elf32_arm_hash_table (link_info);
7522 BFD_ASSERT (hash_table != NULL);
7523 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7524
7525 s = bfd_get_linker_section
7526 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7527
7528 BFD_ASSERT (s != NULL);
7529
7530 sec_data = elf32_arm_section_data (s);
7531
7532 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7533 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7534
7535 BFD_ASSERT (tmp_name);
7536
7537 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7538 hash_table->num_stm32l4xx_fixes);
7539
7540 myh = elf_link_hash_lookup
7541 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7542
7543 BFD_ASSERT (myh == NULL);
7544
7545 bh = NULL;
7546 val = hash_table->stm32l4xx_erratum_glue_size;
7547 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7548 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7549 NULL, TRUE, FALSE, &bh);
7550
7551 myh = (struct elf_link_hash_entry *) bh;
7552 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7553 myh->forced_local = 1;
7554
7555 /* Link veneer back to calling location. */
7556 sec_data->stm32l4xx_erratumcount += 1;
7557 newerr = (elf32_stm32l4xx_erratum_list *)
7558 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7559
7560 newerr->type = STM32L4XX_ERRATUM_VENEER;
7561 newerr->vma = -1;
7562 newerr->u.v.branch = branch;
7563 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7564 branch->u.b.veneer = newerr;
7565
7566 newerr->next = sec_data->stm32l4xx_erratumlist;
7567 sec_data->stm32l4xx_erratumlist = newerr;
7568
7569 /* A symbol for the return from the veneer. */
7570 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7571 hash_table->num_stm32l4xx_fixes);
7572
7573 myh = elf_link_hash_lookup
7574 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7575
7576 if (myh != NULL)
7577 abort ();
7578
7579 bh = NULL;
7580 val = offset + 4;
7581 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7582 branch_sec, val, NULL, TRUE, FALSE, &bh);
7583
7584 myh = (struct elf_link_hash_entry *) bh;
7585 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7586 myh->forced_local = 1;
7587
7588 free (tmp_name);
7589
7590 /* Generate a mapping symbol for the veneer section, and explicitly add an
7591 entry for that symbol to the code/data map for the section. */
7592 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7593 {
7594 bh = NULL;
7595 /* Creates a THUMB symbol since there is no other choice. */
7596 _bfd_generic_link_add_one_symbol (link_info,
7597 hash_table->bfd_of_glue_owner, "$t",
7598 BSF_LOCAL, s, 0, NULL,
7599 TRUE, FALSE, &bh);
7600
7601 myh = (struct elf_link_hash_entry *) bh;
7602 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7603 myh->forced_local = 1;
7604
7605 /* The elf32_arm_init_maps function only cares about symbols from input
7606 BFDs. We must make a note of this generated mapping symbol
7607 ourselves so that code byteswapping works properly in
7608 elf32_arm_write_section. */
7609 elf32_arm_section_map_add (s, 't', 0);
7610 }
7611
7612 s->size += veneer_size;
7613 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7614 hash_table->num_stm32l4xx_fixes++;
7615
7616 /* The offset of the veneer. */
7617 return val;
7618}
7619
8029a119 7620#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7621 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7622 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7623
7624/* Create a fake section for use by the ARM backend of the linker. */
7625
7626static bfd_boolean
7627arm_make_glue_section (bfd * abfd, const char * name)
7628{
7629 asection * sec;
7630
3d4d4302 7631 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7632 if (sec != NULL)
7633 /* Already made. */
7634 return TRUE;
7635
3d4d4302 7636 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7637
7638 if (sec == NULL
7639 || !bfd_set_section_alignment (abfd, sec, 2))
7640 return FALSE;
7641
7642 /* Set the gc mark to prevent the section from being removed by garbage
7643 collection, despite the fact that no relocs refer to this section. */
7644 sec->gc_mark = 1;
7645
7646 return TRUE;
7647}
7648
1db37fe6
YG		 7649/* Set size of .plt entries. This function is called from the
7650 linker scripts in ld/emultempl/{armelf}.em. */
7651
7652void
7653bfd_elf32_arm_use_long_plt (void)
7654{
7655 elf32_arm_use_long_plt_entry = TRUE;
7656}
7657
8afb0e02
NC		 7658/* Add the glue sections to ABFD. This function is called from the
7659 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7660
b34976b6 7661bfd_boolean
57e8b36a
NC		 7662bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7663 struct bfd_link_info *info)
252b5132 7664{
a504d23a
LA		 7665 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7666 bfd_boolean dostm32l4xx = globals
7667 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7668 bfd_boolean addglue;
7669
8afb0e02
NC		 7670 /* If we are only performing a partial
7671 link do not bother adding the glue. */
0e1862bb 7672 if (bfd_link_relocatable (info))
b34976b6 7673 return TRUE;
252b5132 7674
a504d23a 7675 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7676 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7677 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7678 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7679
7680 if (!dostm32l4xx)
7681 return addglue;
7682
7683 return addglue
7684 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7685}
7686
daa4adae
TP		 7687/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7688 ensures they are not marked for deletion by
7689 strip_excluded_output_sections () when veneers are going to be created
7690 later. Not doing so would trigger assert on empty section size in
7691 lang_size_sections_1 (). */
7692
7693void
7694bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7695{
7696 enum elf32_arm_stub_type stub_type;
7697
7698 /* If we are only performing a partial
7699 link do not bother adding the glue. */
7700 if (bfd_link_relocatable (info))
7701 return;
7702
7703 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7704 {
7705 asection *out_sec;
7706 const char *out_sec_name;
7707
7708 if (!arm_dedicated_stub_output_section_required (stub_type))
7709 continue;
7710
7711 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7712 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7713 if (out_sec != NULL)
7714 out_sec->flags |= SEC_KEEP;
7715 }
7716}
7717
8afb0e02
NC		 7718/* Select a BFD to be used to hold the sections used by the glue code.
7719 This function is called from the linker scripts in ld/emultempl/
8029a119 7720 {armelf/pe}.em. */
8afb0e02 7721
b34976b6 7722bfd_boolean
57e8b36a 7723bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7724{
7725 struct elf32_arm_link_hash_table *globals;
7726
7727 /* If we are only performing a partial link
7728 do not bother getting a bfd to hold the glue. */
0e1862bb 7729 if (bfd_link_relocatable (info))
b34976b6 7730 return TRUE;
8afb0e02 7731
b7693d02
DJ		 7732 /* Make sure we don't attach the glue sections to a dynamic object. */
7733 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7734
8afb0e02 7735 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7736 BFD_ASSERT (globals != NULL);
7737
7738 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7739 return TRUE;
8afb0e02 7740
252b5132
RH		 7741 /* Save the bfd for later use. */
7742 globals->bfd_of_glue_owner = abfd;
cedb70c5 7743
b34976b6 7744 return TRUE;
252b5132
RH		 7745}
7746
906e58ca
NC		 7747static void
7748check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7749{
2de70689
MGD		 7750 int cpu_arch;
7751
b38cadfb 7752 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7753 Tag_CPU_arch);
7754
7755 if (globals->fix_arm1176)
7756 {
7757 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7758 globals->use_blx = 1;
7759 }
7760 else
7761 {
7762 if (cpu_arch > TAG_CPU_ARCH_V4T)
7763 globals->use_blx = 1;
7764 }
39b41c9c
PB		 7765}
7766
b34976b6 7767bfd_boolean
57e8b36a 7768bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7769 struct bfd_link_info *link_info)
252b5132
RH		 7770{
7771 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7772 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7773 Elf_Internal_Rela *irel, *irelend;
7774 bfd_byte *contents = NULL;
252b5132
RH		 7775
7776 asection *sec;
7777 struct elf32_arm_link_hash_table *globals;
7778
7779 /* If we are only performing a partial link do not bother
7780 to construct any glue. */
0e1862bb 7781 if (bfd_link_relocatable (link_info))
b34976b6 7782 return TRUE;
252b5132 7783
39ce1a6a
NC		 7784 /* Here we have a bfd that is to be included on the link. We have a
7785 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7786 globals = elf32_arm_hash_table (link_info);
252b5132 7787 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7788
7789 check_use_blx (globals);
252b5132 7790
d504ffc8 7791 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7792 {
90b6238f 7793 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7794 abfd);
e489d0ae
PB		 7795 return FALSE;
7796 }
f21f3fe0 7797
39ce1a6a
NC		 7798 /* PR 5398: If we have not decided to include any loadable sections in
7799 the output then we will not have a glue owner bfd. This is OK, it
7800 just means that there is nothing else for us to do here. */
7801 if (globals->bfd_of_glue_owner == NULL)
7802 return TRUE;
7803
252b5132
RH		 7804 /* Rummage around all the relocs and map the glue vectors. */
7805 sec = abfd->sections;
7806
7807 if (sec == NULL)
b34976b6 7808 return TRUE;
252b5132
RH		 7809
7810 for (; sec != NULL; sec = sec->next)
7811 {
7812 if (sec->reloc_count == 0)
7813 continue;
7814
2f475487
AM		 7815 if ((sec->flags & SEC_EXCLUDE) != 0)
7816 continue;
7817
0ffa91dd 7818 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7819
9b485d32 7820 /* Load the relocs. */
6cdc0ccc 7821 internal_relocs
906e58ca 7822 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7823
6cdc0ccc
AM		 7824 if (internal_relocs == NULL)
7825 goto error_return;
252b5132 7826
6cdc0ccc
AM		 7827 irelend = internal_relocs + sec->reloc_count;
7828 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7829 {
7830 long r_type;
7831 unsigned long r_index;
252b5132
RH		 7832
7833 struct elf_link_hash_entry *h;
7834
7835 r_type = ELF32_R_TYPE (irel->r_info);
7836 r_index = ELF32_R_SYM (irel->r_info);
7837
9b485d32 7838 /* These are the only relocation types we care about. */
ba96a88f 7839 if ( r_type != R_ARM_PC24
845b51d6 7840 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7841 continue;
7842
7843 /* Get the section contents if we haven't done so already. */
7844 if (contents == NULL)
7845 {
7846 /* Get cached copy if it exists. */
7847 if (elf_section_data (sec)->this_hdr.contents != NULL)
7848 contents = elf_section_data (sec)->this_hdr.contents;
7849 else
7850 {
7851 /* Go get them off disk. */
57e8b36a 7852 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7853 goto error_return;
7854 }
7855 }
7856
845b51d6
PB		 7857 if (r_type == R_ARM_V4BX)
7858 {
7859 int reg;
7860
7861 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7862 record_arm_bx_glue (link_info, reg);
7863 continue;
7864 }
7865
a7c10850 7866 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7867 h = NULL;
7868
9b485d32 7869 /* We don't care about local symbols. */
252b5132
RH		 7870 if (r_index < symtab_hdr->sh_info)
7871 continue;
7872
9b485d32 7873 /* This is an external symbol. */
252b5132
RH		 7874 r_index -= symtab_hdr->sh_info;
7875 h = (struct elf_link_hash_entry *)
7876 elf_sym_hashes (abfd)[r_index];
7877
7878 /* If the relocation is against a static symbol it must be within
7879 the current section and so cannot be a cross ARM/Thumb relocation. */
7880 if (h == NULL)
7881 continue;
7882
d504ffc8
DJ		 7883 /* If the call will go through a PLT entry then we do not need
7884 glue. */
362d30a1 7885 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7886 continue;
7887
252b5132
RH		 7888 switch (r_type)
7889 {
7890 case R_ARM_PC24:
7891 /* This one is a call from arm code. We need to look up
99059e56
RM		 7892 the target of the call. If it is a thumb target, we
7893 insert glue. */
39d911fc
TP		 7894 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7895 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7896 record_arm_to_thumb_glue (link_info, h);
7897 break;
7898
252b5132 7899 default:
c6596c5e 7900 abort ();
252b5132
RH		 7901 }
7902 }
6cdc0ccc
AM		 7903
7904 if (contents != NULL
7905 && elf_section_data (sec)->this_hdr.contents != contents)
7906 free (contents);
7907 contents = NULL;
7908
7909 if (internal_relocs != NULL
7910 && elf_section_data (sec)->relocs != internal_relocs)
7911 free (internal_relocs);
7912 internal_relocs = NULL;
252b5132
RH		 7913 }
7914
b34976b6 7915 return TRUE;
9a5aca8c 7916
252b5132 7917error_return:
6cdc0ccc
AM		 7918 if (contents != NULL
7919 && elf_section_data (sec)->this_hdr.contents != contents)
7920 free (contents);
7921 if (internal_relocs != NULL
7922 && elf_section_data (sec)->relocs != internal_relocs)
7923 free (internal_relocs);
9a5aca8c 7924
b34976b6 7925 return FALSE;
252b5132 7926}
7e392df6 7927#endif
252b5132 7928
eb043451 7929
c7b8f16e
JB		 7930/* Initialise maps of ARM/Thumb/data for input BFDs. */
7931
7932void
7933bfd_elf32_arm_init_maps (bfd *abfd)
7934{
7935 Elf_Internal_Sym *isymbuf;
7936 Elf_Internal_Shdr *hdr;
7937 unsigned int i, localsyms;
7938
af1f4419
NC		 7939 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7940 if (! is_arm_elf (abfd))
7941 return;
7942
c7b8f16e
JB		 7943 if ((abfd->flags & DYNAMIC) != 0)
7944 return;
7945
0ffa91dd 7946 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7947 localsyms = hdr->sh_info;
7948
7949 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7950 should contain the number of local symbols, which should come before any
7951 global symbols. Mapping symbols are always local. */
7952 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7953 NULL);
7954
7955 /* No internal symbols read? Skip this BFD. */
7956 if (isymbuf == NULL)
7957 return;
7958
7959 for (i = 0; i < localsyms; i++)
7960 {
7961 Elf_Internal_Sym *isym = &isymbuf[i];
7962 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7963 const char *name;
906e58ca 7964
c7b8f16e 7965 if (sec != NULL
99059e56
RM		 7966 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7967 {
7968 name = bfd_elf_string_from_elf_section (abfd,
7969 hdr->sh_link, isym->st_name);
906e58ca 7970
99059e56 7971 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7972 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7973 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7974 }
c7b8f16e
JB		 7975 }
7976}
7977
7978
48229727
JB		 7979/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7980 say what they wanted. */
7981
7982void
7983bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7984{
7985 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7986 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7987
4dfe6ac6
NC		 7988 if (globals == NULL)
7989 return;
7990
48229727
JB		 7991 if (globals->fix_cortex_a8 == -1)
7992 {
7993 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7994 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7995 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7996 || out_attr[Tag_CPU_arch_profile].i == 0))
7997 globals->fix_cortex_a8 = 1;
7998 else
7999 globals->fix_cortex_a8 = 0;
8000 }
8001}
8002
8003
c7b8f16e
JB		 8004void
8005bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8006{
8007 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8008 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8009
4dfe6ac6
NC		 8010 if (globals == NULL)
8011 return;
c7b8f16e
JB		 8012 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8013 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8014 {
8015 switch (globals->vfp11_fix)
99059e56
RM		 8016 {
8017 case BFD_ARM_VFP11_FIX_DEFAULT:
8018 case BFD_ARM_VFP11_FIX_NONE:
8019 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8020 break;
8021
8022 default:
8023 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8024 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8025 "workaround is not necessary for target architecture"), obfd);
8026 }
c7b8f16e
JB		 8027 }
8028 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8029 /* For earlier architectures, we might need the workaround, but do not
8030 enable it by default. If users is running with broken hardware, they
8031 must enable the erratum fix explicitly. */
8032 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8033}
8034
a504d23a
LA		 8035void
8036bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8037{
8038 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8039 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8040
8041 if (globals == NULL)
8042 return;
8043
8044 /* We assume only Cortex-M4 may require the fix. */
8045 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8046 || out_attr[Tag_CPU_arch_profile].i != 'M')
8047 {
8048 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8049 /* Give a warning, but do as the user requests anyway. */
4eca0228 8050 _bfd_error_handler
871b3ab2 8051 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8052 "workaround is not necessary for target architecture"), obfd);
8053 }
8054}
c7b8f16e 8055
906e58ca
NC		 8056enum bfd_arm_vfp11_pipe
8057{
c7b8f16e
JB		 8058 VFP11_FMAC,
8059 VFP11_LS,
8060 VFP11_DS,
8061 VFP11_BAD
8062};
8063
8064/* Return a VFP register number. This is encoded as RX:X for single-precision
8065 registers, or X:RX for double-precision registers, where RX is the group of
8066 four bits in the instruction encoding and X is the single extension bit.
8067 RX and X fields are specified using their lowest (starting) bit. The return
8068 value is:
8069
8070 0...31: single-precision registers s0...s31
8071 32...63: double-precision registers d0...d31.
906e58ca 8072
c7b8f16e
JB		 8073 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8074 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8075
c7b8f16e
JB		 8076static unsigned int
8077bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8078 unsigned int x)
c7b8f16e
JB		 8079{
8080 if (is_double)
8081 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8082 else
8083 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8084}
8085
8086/* Set bits in *WMASK according to a register number REG as encoded by
8087 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8088
8089static void
8090bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8091{
8092 if (reg < 32)
8093 *wmask |= 1 << reg;
8094 else if (reg < 48)
8095 *wmask |= 3 << ((reg - 32) * 2);
8096}
8097
8098/* Return TRUE if WMASK overwrites anything in REGS. */
8099
8100static bfd_boolean
8101bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8102{
8103 int i;
906e58ca 8104
c7b8f16e
JB		 8105 for (i = 0; i < numregs; i++)
8106 {
8107 unsigned int reg = regs[i];
8108
8109 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8110 return TRUE;
906e58ca 8111
c7b8f16e
JB		 8112 reg -= 32;
8113
8114 if (reg >= 16)
99059e56 8115 continue;
906e58ca 8116
c7b8f16e 8117 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8118 return TRUE;
c7b8f16e 8119 }
906e58ca 8120
c7b8f16e
JB		 8121 return FALSE;
8122}
8123
8124/* In this function, we're interested in two things: finding input registers
8125 for VFP data-processing instructions, and finding the set of registers which
8126 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8127 hold the written set, so FLDM etc. are easy to deal with (we're only
8128 interested in 32 SP registers or 16 dp registers, due to the VFP version
8129 implemented by the chip in question). DP registers are marked by setting
8130 both SP registers in the write mask). */
8131
8132static enum bfd_arm_vfp11_pipe
8133bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8134 int *numregs)
c7b8f16e 8135{
91d6fa6a 8136 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8137 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8138
8139 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8140 {
8141 unsigned int pqrs;
8142 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8143 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8144
8145 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8146 | ((insn & 0x00300000) >> 19)
8147 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8148
8149 switch (pqrs)
99059e56
RM		 8150 {
8151 case 0: /* fmac[sd]. */
8152 case 1: /* fnmac[sd]. */
8153 case 2: /* fmsc[sd]. */
8154 case 3: /* fnmsc[sd]. */
8155 vpipe = VFP11_FMAC;
8156 bfd_arm_vfp11_write_mask (destmask, fd);
8157 regs[0] = fd;
8158 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8159 regs[2] = fm;
8160 *numregs = 3;
8161 break;
8162
8163 case 4: /* fmul[sd]. */
8164 case 5: /* fnmul[sd]. */
8165 case 6: /* fadd[sd]. */
8166 case 7: /* fsub[sd]. */
8167 vpipe = VFP11_FMAC;
8168 goto vfp_binop;
8169
8170 case 8: /* fdiv[sd]. */
8171 vpipe = VFP11_DS;
8172 vfp_binop:
8173 bfd_arm_vfp11_write_mask (destmask, fd);
8174 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8175 regs[1] = fm;
8176 *numregs = 2;
8177 break;
8178
8179 case 15: /* extended opcode. */
8180 {
8181 unsigned int extn = ((insn >> 15) & 0x1e)
8182 | ((insn >> 7) & 1);
8183
8184 switch (extn)
8185 {
8186 case 0: /* fcpy[sd]. */
8187 case 1: /* fabs[sd]. */
8188 case 2: /* fneg[sd]. */
8189 case 8: /* fcmp[sd]. */
8190 case 9: /* fcmpe[sd]. */
8191 case 10: /* fcmpz[sd]. */
8192 case 11: /* fcmpez[sd]. */
8193 case 16: /* fuito[sd]. */
8194 case 17: /* fsito[sd]. */
8195 case 24: /* ftoui[sd]. */
8196 case 25: /* ftouiz[sd]. */
8197 case 26: /* ftosi[sd]. */
8198 case 27: /* ftosiz[sd]. */
8199 /* These instructions will not bounce due to underflow. */
8200 *numregs = 0;
8201 vpipe = VFP11_FMAC;
8202 break;
8203
8204 case 3: /* fsqrt[sd]. */
8205 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8206 registers to cause the erratum in previous instructions. */
8207 bfd_arm_vfp11_write_mask (destmask, fd);
8208 vpipe = VFP11_DS;
8209 break;
8210
8211 case 15: /* fcvt{ds,sd}. */
8212 {
8213 int rnum = 0;
8214
8215 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8216
8217 /* Only FCVTSD can underflow. */
99059e56
RM		 8218 if ((insn & 0x100) != 0)
8219 regs[rnum++] = fm;
c7b8f16e 8220
99059e56 8221 *numregs = rnum;
c7b8f16e 8222
99059e56
RM		 8223 vpipe = VFP11_FMAC;
8224 }
8225 break;
c7b8f16e 8226
99059e56
RM		 8227 default:
8228 return VFP11_BAD;
8229 }
8230 }
8231 break;
c7b8f16e 8232
99059e56
RM		 8233 default:
8234 return VFP11_BAD;
8235 }
c7b8f16e
JB		 8236 }
8237 /* Two-register transfer. */
8238 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8239 {
8240 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8241
c7b8f16e
JB		 8242 if ((insn & 0x100000) == 0)
8243 {
99059e56
RM		 8244 if (is_double)
8245 bfd_arm_vfp11_write_mask (destmask, fm);
8246 else
8247 {
8248 bfd_arm_vfp11_write_mask (destmask, fm);
8249 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8250 }
c7b8f16e
JB		 8251 }
8252
91d6fa6a 8253 vpipe = VFP11_LS;
c7b8f16e
JB		 8254 }
8255 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8256 {
8257 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8258 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8259
c7b8f16e 8260 switch (puw)
99059e56
RM		 8261 {
8262 case 0: /* Two-reg transfer. We should catch these above. */
8263 abort ();
906e58ca 8264
99059e56
RM		 8265 case 2: /* fldm[sdx]. */
8266 case 3:
8267 case 5:
8268 {
8269 unsigned int i, offset = insn & 0xff;
c7b8f16e 8270
99059e56
RM		 8271 if (is_double)
8272 offset >>= 1;
c7b8f16e 8273
99059e56
RM		 8274 for (i = fd; i < fd + offset; i++)
8275 bfd_arm_vfp11_write_mask (destmask, i);
8276 }
8277 break;
906e58ca 8278
99059e56
RM		 8279 case 4: /* fld[sd]. */
8280 case 6:
8281 bfd_arm_vfp11_write_mask (destmask, fd);
8282 break;
906e58ca 8283
99059e56
RM		 8284 default:
8285 return VFP11_BAD;
8286 }
c7b8f16e 8287
91d6fa6a 8288 vpipe = VFP11_LS;
c7b8f16e
JB		 8289 }
8290 /* Single-register transfer. Note L==0. */
8291 else if ((insn & 0x0f100e10) == 0x0e000a10)
8292 {
8293 unsigned int opcode = (insn >> 21) & 7;
8294 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8295
8296 switch (opcode)
99059e56
RM		 8297 {
8298 case 0: /* fmsr/fmdlr. */
8299 case 1: /* fmdhr. */
8300 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8301 destination register. I don't know if this is exactly right,
8302 but it is the conservative choice. */
8303 bfd_arm_vfp11_write_mask (destmask, fn);
8304 break;
8305
8306 case 7: /* fmxr. */
8307 break;
8308 }
c7b8f16e 8309
91d6fa6a 8310 vpipe = VFP11_LS;
c7b8f16e
JB		 8311 }
8312
91d6fa6a 8313 return vpipe;
c7b8f16e
JB		 8314}
8315
8316
8317static int elf32_arm_compare_mapping (const void * a, const void * b);
8318
8319
8320/* Look for potentially-troublesome code sequences which might trigger the
8321 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8322 (available from ARM) for details of the erratum. A short version is
8323 described in ld.texinfo. */
8324
8325bfd_boolean
8326bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8327{
8328 asection *sec;
8329 bfd_byte *contents = NULL;
8330 int state = 0;
8331 int regs[3], numregs = 0;
8332 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8333 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8334
4dfe6ac6
NC		 8335 if (globals == NULL)
8336 return FALSE;
8337
c7b8f16e
JB		 8338 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8339 The states transition as follows:
906e58ca 8340
c7b8f16e 8341 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8342 A VFP FMAC-pipeline instruction has been seen. Fill
8343 regs[0]..regs[numregs-1] with its input operands. Remember this
8344 instruction in 'first_fmac'.
c7b8f16e
JB		 8345
8346 1 -> 2
99059e56
RM		 8347 Any instruction, except for a VFP instruction which overwrites
8348 regs[*].
906e58ca 8349
c7b8f16e
JB		 8350 1 -> 3 [ -> 0 ] or
8351 2 -> 3 [ -> 0 ]
99059e56
RM		 8352 A VFP instruction has been seen which overwrites any of regs[*].
8353 We must make a veneer! Reset state to 0 before examining next
8354 instruction.
906e58ca 8355
c7b8f16e 8356 2 -> 0
99059e56
RM		 8357 If we fail to match anything in state 2, reset to state 0 and reset
8358 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8359
8360 If the VFP11 vector mode is in use, there must be at least two unrelated
8361 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8362 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8363
8364 /* If we are only performing a partial link do not bother
8365 to construct any glue. */
0e1862bb 8366 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8367 return TRUE;
8368
0ffa91dd
NC		 8369 /* Skip if this bfd does not correspond to an ELF image. */
8370 if (! is_arm_elf (abfd))
8371 return TRUE;
906e58ca 8372
c7b8f16e
JB		 8373 /* We should have chosen a fix type by the time we get here. */
8374 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8375
8376 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8377 return TRUE;
2e6030b9 8378
33a7ffc2
JM		 8379 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8380 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8381 return TRUE;
8382
c7b8f16e
JB		 8383 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8384 {
8385 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8386 struct _arm_elf_section_data *sec_data;
8387
8388 /* If we don't have executable progbits, we're not interested in this
99059e56 8389 section. Also skip if section is to be excluded. */
c7b8f16e 8390 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8391 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8392 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8393 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8394 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8395 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8396 continue;
c7b8f16e
JB		 8397
8398 sec_data = elf32_arm_section_data (sec);
906e58ca 8399
c7b8f16e 8400 if (sec_data->mapcount == 0)
99059e56 8401 continue;
906e58ca 8402
c7b8f16e
JB		 8403 if (elf_section_data (sec)->this_hdr.contents != NULL)
8404 contents = elf_section_data (sec)->this_hdr.contents;
8405 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8406 goto error_return;
8407
8408 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8409 elf32_arm_compare_mapping);
8410
8411 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8412 {
8413 unsigned int span_start = sec_data->map[span].vma;
8414 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8415 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8416 char span_type = sec_data->map[span].type;
8417
8418 /* FIXME: Only ARM mode is supported at present. We may need to
8419 support Thumb-2 mode also at some point. */
8420 if (span_type != 'a')
8421 continue;
8422
8423 for (i = span_start; i < span_end;)
8424 {
8425 unsigned int next_i = i + 4;
8426 unsigned int insn = bfd_big_endian (abfd)
8427 ? (contents[i] << 24)
8428 | (contents[i + 1] << 16)
8429 | (contents[i + 2] << 8)
8430 | contents[i + 3]
8431 : (contents[i + 3] << 24)
8432 | (contents[i + 2] << 16)
8433 | (contents[i + 1] << 8)
8434 | contents[i];
8435 unsigned int writemask = 0;
8436 enum bfd_arm_vfp11_pipe vpipe;
8437
8438 switch (state)
8439 {
8440 case 0:
8441 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8442 &numregs);
8443 /* I'm assuming the VFP11 erratum can trigger with denorm
8444 operands on either the FMAC or the DS pipeline. This might
8445 lead to slightly overenthusiastic veneer insertion. */
8446 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8447 {
8448 state = use_vector ? 1 : 2;
8449 first_fmac = i;
8450 veneer_of_insn = insn;
8451 }
8452 break;
8453
8454 case 1:
8455 {
8456 int other_regs[3], other_numregs;
8457 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8458 other_regs,
99059e56
RM		 8459 &other_numregs);
8460 if (vpipe != VFP11_BAD
8461 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8462 numregs))
99059e56
RM		 8463 state = 3;
8464 else
8465 state = 2;
8466 }
8467 break;
8468
8469 case 2:
8470 {
8471 int other_regs[3], other_numregs;
8472 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8473 other_regs,
99059e56
RM		 8474 &other_numregs);
8475 if (vpipe != VFP11_BAD
8476 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8477 numregs))
99059e56
RM		 8478 state = 3;
8479 else
8480 {
8481 state = 0;
8482 next_i = first_fmac + 4;
8483 }
8484 }
8485 break;
8486
8487 case 3:
8488 abort (); /* Should be unreachable. */
8489 }
8490
8491 if (state == 3)
8492 {
8493 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8494 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8495
8496 elf32_arm_section_data (sec)->erratumcount += 1;
8497
8498 newerr->u.b.vfp_insn = veneer_of_insn;
8499
8500 switch (span_type)
8501 {
8502 case 'a':
8503 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8504 break;
8505
8506 default:
8507 abort ();
8508 }
8509
8510 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8511 first_fmac);
8512
99059e56 8513 newerr->vma = -1;
c7b8f16e 8514
99059e56
RM		 8515 newerr->next = sec_data->erratumlist;
8516 sec_data->erratumlist = newerr;
c7b8f16e 8517
99059e56
RM		 8518 state = 0;
8519 }
c7b8f16e 8520
99059e56
RM		 8521 i = next_i;
8522 }
8523 }
906e58ca 8524
c7b8f16e 8525 if (contents != NULL
99059e56
RM		 8526 && elf_section_data (sec)->this_hdr.contents != contents)
8527 free (contents);
c7b8f16e
JB		 8528 contents = NULL;
8529 }
8530
8531 return TRUE;
8532
8533error_return:
8534 if (contents != NULL
8535 && elf_section_data (sec)->this_hdr.contents != contents)
8536 free (contents);
906e58ca 8537
c7b8f16e
JB		 8538 return FALSE;
8539}
8540
8541/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8542 after sections have been laid out, using specially-named symbols. */
8543
8544void
8545bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8546 struct bfd_link_info *link_info)
8547{
8548 asection *sec;
8549 struct elf32_arm_link_hash_table *globals;
8550 char *tmp_name;
906e58ca 8551
0e1862bb 8552 if (bfd_link_relocatable (link_info))
c7b8f16e 8553 return;
2e6030b9
MS		 8554
8555 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8556 if (! is_arm_elf (abfd))
2e6030b9
MS		 8557 return;
8558
c7b8f16e 8559 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8560 if (globals == NULL)
8561 return;
906e58ca 8562
21d799b5 8563 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8564 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8565
8566 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8567 {
8568 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8569 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8570
c7b8f16e 8571 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8572 {
8573 struct elf_link_hash_entry *myh;
8574 bfd_vma vma;
8575
8576 switch (errnode->type)
8577 {
8578 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8579 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8580 /* Find veneer symbol. */
8581 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8582 errnode->u.b.veneer->u.v.id);
8583
99059e56
RM		 8584 myh = elf_link_hash_lookup
8585 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8586
a504d23a 8587 if (myh == NULL)
90b6238f
AM		 8588 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8589 abfd, "VFP11", tmp_name);
a504d23a
LA		 8590
8591 vma = myh->root.u.def.section->output_section->vma
8592 + myh->root.u.def.section->output_offset
8593 + myh->root.u.def.value;
8594
8595 errnode->u.b.veneer->vma = vma;
8596 break;
8597
8598 case VFP11_ERRATUM_ARM_VENEER:
8599 case VFP11_ERRATUM_THUMB_VENEER:
8600 /* Find return location. */
8601 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8602 errnode->u.v.id);
8603
8604 myh = elf_link_hash_lookup
8605 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8606
8607 if (myh == NULL)
90b6238f
AM		 8608 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8609 abfd, "VFP11", tmp_name);
a504d23a
LA		 8610
8611 vma = myh->root.u.def.section->output_section->vma
8612 + myh->root.u.def.section->output_offset
8613 + myh->root.u.def.value;
8614
8615 errnode->u.v.branch->vma = vma;
8616 break;
8617
8618 default:
8619 abort ();
8620 }
8621 }
8622 }
8623
8624 free (tmp_name);
8625}
8626
8627/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8628 return locations after sections have been laid out, using
8629 specially-named symbols. */
8630
8631void
8632bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8633 struct bfd_link_info *link_info)
8634{
8635 asection *sec;
8636 struct elf32_arm_link_hash_table *globals;
8637 char *tmp_name;
8638
8639 if (bfd_link_relocatable (link_info))
8640 return;
8641
8642 /* Skip if this bfd does not correspond to an ELF image. */
8643 if (! is_arm_elf (abfd))
8644 return;
8645
8646 globals = elf32_arm_hash_table (link_info);
8647 if (globals == NULL)
8648 return;
8649
8650 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8651 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8652
8653 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8654 {
8655 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8656 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8657
8658 for (; errnode != NULL; errnode = errnode->next)
8659 {
8660 struct elf_link_hash_entry *myh;
8661 bfd_vma vma;
8662
8663 switch (errnode->type)
8664 {
8665 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8666 /* Find veneer symbol. */
8667 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8668 errnode->u.b.veneer->u.v.id);
8669
8670 myh = elf_link_hash_lookup
8671 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8672
8673 if (myh == NULL)
90b6238f
AM		 8674 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8675 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8676
8677 vma = myh->root.u.def.section->output_section->vma
8678 + myh->root.u.def.section->output_offset
8679 + myh->root.u.def.value;
8680
8681 errnode->u.b.veneer->vma = vma;
8682 break;
8683
8684 case STM32L4XX_ERRATUM_VENEER:
8685 /* Find return location. */
8686 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8687 errnode->u.v.id);
8688
8689 myh = elf_link_hash_lookup
8690 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8691
8692 if (myh == NULL)
90b6238f
AM		 8693 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8694 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8695
8696 vma = myh->root.u.def.section->output_section->vma
8697 + myh->root.u.def.section->output_offset
8698 + myh->root.u.def.value;
8699
8700 errnode->u.v.branch->vma = vma;
8701 break;
8702
8703 default:
8704 abort ();
8705 }
8706 }
8707 }
8708
8709 free (tmp_name);
8710}
8711
8712static inline bfd_boolean
8713is_thumb2_ldmia (const insn32 insn)
8714{
8715 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8716 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8717 return (insn & 0xffd02000) == 0xe8900000;
8718}
8719
8720static inline bfd_boolean
8721is_thumb2_ldmdb (const insn32 insn)
8722{
8723 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8724 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8725 return (insn & 0xffd02000) == 0xe9100000;
8726}
8727
8728static inline bfd_boolean
8729is_thumb2_vldm (const insn32 insn)
8730{
8731 /* A6.5 Extension register load or store instruction
8732 A7.7.229
9239bbd3
CM		 8733 We look for SP 32-bit and DP 64-bit registers.
8734 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8735 <list> is consecutive 64-bit registers
8736 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8737 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8738 <list> is consecutive 32-bit registers
8739 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8740 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8741 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8742 return
9239bbd3
CM		 8743 (((insn & 0xfe100f00) == 0xec100b00) ||
8744 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8745 && /* (IA without !). */
8746 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8747 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8748 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8749 /* (DB with !). */
8750 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8751}
8752
8753/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8754 VLDM opcode and:
8755 - computes the number and the mode of memory accesses
8756 - decides if the replacement should be done:
8757 . replaces only if > 8-word accesses
8758 . or (testing purposes only) replaces all accesses. */
8759
8760static bfd_boolean
8761stm32l4xx_need_create_replacing_stub (const insn32 insn,
8762 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8763{
9239bbd3 8764 int nb_words = 0;
a504d23a
LA		 8765
8766 /* The field encoding the register list is the same for both LDMIA
8767 and LDMDB encodings. */
8768 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8769 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8770 else if (is_thumb2_vldm (insn))
9239bbd3 8771 nb_words = (insn & 0xff);
a504d23a
LA		 8772
8773 /* DEFAULT mode accounts for the real bug condition situation,
8774 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8775 return
9239bbd3 8776 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8777 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8778}
8779
8780/* Look for potentially-troublesome code sequences which might trigger
8781 the STM STM32L4XX erratum. */
8782
8783bfd_boolean
8784bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8785 struct bfd_link_info *link_info)
8786{
8787 asection *sec;
8788 bfd_byte *contents = NULL;
8789 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8790
8791 if (globals == NULL)
8792 return FALSE;
8793
8794 /* If we are only performing a partial link do not bother
8795 to construct any glue. */
8796 if (bfd_link_relocatable (link_info))
8797 return TRUE;
8798
8799 /* Skip if this bfd does not correspond to an ELF image. */
8800 if (! is_arm_elf (abfd))
8801 return TRUE;
8802
8803 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8804 return TRUE;
8805
8806 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8807 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8808 return TRUE;
8809
8810 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8811 {
8812 unsigned int i, span;
8813 struct _arm_elf_section_data *sec_data;
8814
8815 /* If we don't have executable progbits, we're not interested in this
8816 section. Also skip if section is to be excluded. */
8817 if (elf_section_type (sec) != SHT_PROGBITS
8818 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8819 || (sec->flags & SEC_EXCLUDE) != 0
8820 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8821 || sec->output_section == bfd_abs_section_ptr
8822 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8823 continue;
8824
8825 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8826
a504d23a
LA		 8827 if (sec_data->mapcount == 0)
8828 continue;
c7b8f16e 8829
a504d23a
LA		 8830 if (elf_section_data (sec)->this_hdr.contents != NULL)
8831 contents = elf_section_data (sec)->this_hdr.contents;
8832 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8833 goto error_return;
c7b8f16e 8834
a504d23a
LA		 8835 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8836 elf32_arm_compare_mapping);
c7b8f16e 8837
a504d23a
LA		 8838 for (span = 0; span < sec_data->mapcount; span++)
8839 {
8840 unsigned int span_start = sec_data->map[span].vma;
8841 unsigned int span_end = (span == sec_data->mapcount - 1)
8842 ? sec->size : sec_data->map[span + 1].vma;
8843 char span_type = sec_data->map[span].type;
8844 int itblock_current_pos = 0;
c7b8f16e 8845
a504d23a
LA		 8846 /* Only Thumb2 mode need be supported with this CM4 specific
8847 code, we should not encounter any arm mode eg span_type
8848 != 'a'. */
8849 if (span_type != 't')
8850 continue;
c7b8f16e 8851
a504d23a
LA		 8852 for (i = span_start; i < span_end;)
8853 {
8854 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8855 bfd_boolean insn_32bit = FALSE;
8856 bfd_boolean is_ldm = FALSE;
8857 bfd_boolean is_vldm = FALSE;
8858 bfd_boolean is_not_last_in_it_block = FALSE;
8859
8860 /* The first 16-bits of all 32-bit thumb2 instructions start
8861 with opcode[15..13]=0b111 and the encoded op1 can be anything
8862 except opcode[12..11]!=0b00.
8863 See 32-bit Thumb instruction encoding. */
8864 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8865 insn_32bit = TRUE;
c7b8f16e 8866
a504d23a
LA		 8867 /* Compute the predicate that tells if the instruction
8868 is concerned by the IT block
8869 - Creates an error if there is a ldm that is not
8870 last in the IT block thus cannot be replaced
8871 - Otherwise we can create a branch at the end of the
8872 IT block, it will be controlled naturally by IT
8873 with the proper pseudo-predicate
8874 - So the only interesting predicate is the one that
8875 tells that we are not on the last item of an IT
8876 block. */
8877 if (itblock_current_pos != 0)
8878 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8879
a504d23a
LA		 8880 if (insn_32bit)
8881 {
8882 /* Load the rest of the insn (in manual-friendly order). */
8883 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8884 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8885 is_vldm = is_thumb2_vldm (insn);
8886
8887 /* Veneers are created for (v)ldm depending on
8888 option flags and memory accesses conditions; but
8889 if the instruction is not the last instruction of
8890 an IT block, we cannot create a jump there, so we
8891 bail out. */
5025eb7c
AO		 8892 if ((is_ldm || is_vldm)
8893 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8894 (insn, globals->stm32l4xx_fix))
8895 {
8896 if (is_not_last_in_it_block)
8897 {
4eca0228 8898 _bfd_error_handler
695344c0 8899 /* xgettext:c-format */
871b3ab2 8900 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8901 " in non-last IT block instruction:"
8902 " STM32L4XX veneer cannot be generated; "
8903 "use gcc option -mrestrict-it to generate"
8904 " only one instruction per IT block"),
d42c267e 8905 abfd, sec, i);
a504d23a
LA		 8906 }
8907 else
8908 {
8909 elf32_stm32l4xx_erratum_list *newerr =
8910 (elf32_stm32l4xx_erratum_list *)
8911 bfd_zmalloc
8912 (sizeof (elf32_stm32l4xx_erratum_list));
8913
8914 elf32_arm_section_data (sec)
8915 ->stm32l4xx_erratumcount += 1;
8916 newerr->u.b.insn = insn;
8917 /* We create only thumb branches. */
8918 newerr->type =
8919 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8920 record_stm32l4xx_erratum_veneer
8921 (link_info, newerr, abfd, sec,
8922 i,
8923 is_ldm ?
8924 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8925 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8926 newerr->vma = -1;
8927 newerr->next = sec_data->stm32l4xx_erratumlist;
8928 sec_data->stm32l4xx_erratumlist = newerr;
8929 }
8930 }
8931 }
8932 else
8933 {
8934 /* A7.7.37 IT p208
8935 IT blocks are only encoded in T1
8936 Encoding T1: IT{x{y{z}}} <firstcond>
8937 1 0 1 1 - 1 1 1 1 - firstcond - mask
8938 if mask = '0000' then see 'related encodings'
8939 We don't deal with UNPREDICTABLE, just ignore these.
8940 There can be no nested IT blocks so an IT block
8941 is naturally a new one for which it is worth
8942 computing its size. */
5025eb7c
AO		 8943 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8944 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8945 /* If we have a new IT block we compute its size. */
8946 if (is_newitblock)
8947 {
8948 /* Compute the number of instructions controlled
8949 by the IT block, it will be used to decide
8950 whether we are inside an IT block or not. */
8951 unsigned int mask = insn & 0x000f;
8952 itblock_current_pos = 4 - ctz (mask);
8953 }
8954 }
8955
8956 i += insn_32bit ? 4 : 2;
99059e56
RM		 8957 }
8958 }
a504d23a
LA		 8959
8960 if (contents != NULL
8961 && elf_section_data (sec)->this_hdr.contents != contents)
8962 free (contents);
8963 contents = NULL;
c7b8f16e 8964 }
906e58ca 8965
a504d23a
LA		 8966 return TRUE;
8967
8968error_return:
8969 if (contents != NULL
8970 && elf_section_data (sec)->this_hdr.contents != contents)
8971 free (contents);
c7b8f16e 8972
a504d23a
LA		 8973 return FALSE;
8974}
c7b8f16e 8975
eb043451
PB		 8976/* Set target relocation values needed during linking. */
8977
8978void
68c39892 8979bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8980 struct bfd_link_info *link_info,
68c39892 8981 struct elf32_arm_params *params)
eb043451
PB		 8982{
8983 struct elf32_arm_link_hash_table *globals;
8984
8985 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8986 if (globals == NULL)
8987 return;
eb043451 8988
68c39892 8989 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 8990 if (globals->fdpic_p)
8991 globals->target2_reloc = R_ARM_GOT32;
8992 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 8993 globals->target2_reloc = R_ARM_REL32;
68c39892 8994 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8995 globals->target2_reloc = R_ARM_ABS32;
68c39892 8996 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8997 globals->target2_reloc = R_ARM_GOT_PREL;
8998 else
8999 {
90b6238f 9000 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9001 params->target2_type);
eb043451 9002 }
68c39892
TP		 9003 globals->fix_v4bx = params->fix_v4bx;
9004 globals->use_blx |= params->use_blx;
9005 globals->vfp11_fix = params->vfp11_denorm_fix;
9006 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9007 if (globals->fdpic_p)
9008 globals->pic_veneer = 1;
9009 else
9010 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9011 globals->fix_cortex_a8 = params->fix_cortex_a8;
9012 globals->fix_arm1176 = params->fix_arm1176;
9013 globals->cmse_implib = params->cmse_implib;
9014 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9015
0ffa91dd 9016 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9017 elf_arm_tdata (output_bfd)->no_enum_size_warning
9018 = params->no_enum_size_warning;
9019 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9020 = params->no_wchar_size_warning;
eb043451 9021}
eb043451 9022
12a0a0fd 9023/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9024
12a0a0fd
PB		 9025static void
9026insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9027{
9028 bfd_vma upper;
9029 bfd_vma lower;
9030 int reloc_sign;
9031
9032 BFD_ASSERT ((offset & 1) == 0);
9033
9034 upper = bfd_get_16 (abfd, insn);
9035 lower = bfd_get_16 (abfd, insn + 2);
9036 reloc_sign = (offset < 0) ? 1 : 0;
9037 upper = (upper & ~(bfd_vma) 0x7ff)
9038 | ((offset >> 12) & 0x3ff)
9039 | (reloc_sign << 10);
906e58ca 9040 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9041 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9042 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9043 | ((offset >> 1) & 0x7ff);
9044 bfd_put_16 (abfd, upper, insn);
9045 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9046}
9047
9b485d32
NC		 9048/* Thumb code calling an ARM function. */
9049
252b5132 9050static int
57e8b36a 9051elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9052 const char * name,
9053 bfd * input_bfd,
9054 bfd * output_bfd,
9055 asection * input_section,
9056 bfd_byte * hit_data,
9057 asection * sym_sec,
9058 bfd_vma offset,
9059 bfd_signed_vma addend,
9060 bfd_vma val,
f2a9dd69 9061 char **error_message)
252b5132 9062{
bcbdc74c 9063 asection * s = 0;
dc810e39 9064 bfd_vma my_offset;
252b5132 9065 long int ret_offset;
bcbdc74c
NC		 9066 struct elf_link_hash_entry * myh;
9067 struct elf32_arm_link_hash_table * globals;
252b5132 9068
f2a9dd69 9069 myh = find_thumb_glue (info, name, error_message);
252b5132 9070 if (myh == NULL)
b34976b6 9071 return FALSE;
252b5132
RH		 9072
9073 globals = elf32_arm_hash_table (info);
252b5132
RH		 9074 BFD_ASSERT (globals != NULL);
9075 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9076
9077 my_offset = myh->root.u.def.value;
9078
3d4d4302
AM		 9079 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9080 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9081
9082 BFD_ASSERT (s != NULL);
9083 BFD_ASSERT (s->contents != NULL);
9084 BFD_ASSERT (s->output_section != NULL);
9085
9086 if ((my_offset & 0x01) == 0x01)
9087 {
9088 if (sym_sec != NULL
9089 && sym_sec->owner != NULL
9090 && !INTERWORK_FLAG (sym_sec->owner))
9091 {
4eca0228 9092 _bfd_error_handler
90b6238f
AM		 9093 (_("%pB(%s): warning: interworking not enabled;"
9094 " first occurrence: %pB: %s call to %s"),
9095 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9096
b34976b6 9097 return FALSE;
252b5132
RH		 9098 }
9099
9100 --my_offset;
9101 myh->root.u.def.value = my_offset;
9102
52ab56c2
PB		 9103 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9104 s->contents + my_offset);
252b5132 9105
52ab56c2
PB		 9106 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9107 s->contents + my_offset + 2);
252b5132
RH		 9108
9109 ret_offset =
9b485d32
NC		 9110 /* Address of destination of the stub. */
9111 ((bfd_signed_vma) val)
252b5132 9112 - ((bfd_signed_vma)
57e8b36a
NC		 9113 /* Offset from the start of the current section
9114 to the start of the stubs. */
9b485d32
NC		 9115 (s->output_offset
9116 /* Offset of the start of this stub from the start of the stubs. */
9117 + my_offset
9118 /* Address of the start of the current section. */
9119 + s->output_section->vma)
9120 /* The branch instruction is 4 bytes into the stub. */
9121 + 4
9122 /* ARM branches work from the pc of the instruction + 8. */
9123 + 8);
252b5132 9124
52ab56c2
PB		 9125 put_arm_insn (globals, output_bfd,
9126 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9127 s->contents + my_offset + 4);
252b5132
RH		 9128 }
9129
9130 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9131
427bfd90
NC		 9132 /* Now go back and fix up the original BL insn to point to here. */
9133 ret_offset =
9134 /* Address of where the stub is located. */
9135 (s->output_section->vma + s->output_offset + my_offset)
9136 /* Address of where the BL is located. */
57e8b36a
NC		 9137 - (input_section->output_section->vma + input_section->output_offset
9138 + offset)
427bfd90
NC		 9139 /* Addend in the relocation. */
9140 - addend
9141 /* Biassing for PC-relative addressing. */
9142 - 8;
252b5132 9143
12a0a0fd 9144 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9145
b34976b6 9146 return TRUE;
252b5132
RH		 9147}
9148
a4fd1a8e 9149/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9150
a4fd1a8e
PB		 9151static struct elf_link_hash_entry *
9152elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9153 const char * name,
9154 bfd * input_bfd,
9155 bfd * output_bfd,
9156 asection * sym_sec,
9157 bfd_vma val,
9158 asection * s,
9159 char ** error_message)
252b5132 9160{
dc810e39 9161 bfd_vma my_offset;
252b5132 9162 long int ret_offset;
bcbdc74c
NC		 9163 struct elf_link_hash_entry * myh;
9164 struct elf32_arm_link_hash_table * globals;
252b5132 9165
f2a9dd69 9166 myh = find_arm_glue (info, name, error_message);
252b5132 9167 if (myh == NULL)
a4fd1a8e 9168 return NULL;
252b5132
RH		 9169
9170 globals = elf32_arm_hash_table (info);
252b5132
RH		 9171 BFD_ASSERT (globals != NULL);
9172 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9173
9174 my_offset = myh->root.u.def.value;
252b5132
RH		 9175
9176 if ((my_offset & 0x01) == 0x01)
9177 {
9178 if (sym_sec != NULL
9179 && sym_sec->owner != NULL
9180 && !INTERWORK_FLAG (sym_sec->owner))
9181 {
4eca0228 9182 _bfd_error_handler
90b6238f
AM		 9183 (_("%pB(%s): warning: interworking not enabled;"
9184 " first occurrence: %pB: %s call to %s"),
9185 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9186 }
9b485d32 9187
252b5132
RH		 9188 --my_offset;
9189 myh->root.u.def.value = my_offset;
9190
0e1862bb
L		 9191 if (bfd_link_pic (info)
9192 || globals->root.is_relocatable_executable
27e55c4d 9193 || globals->pic_veneer)
8f6277f5
PB		 9194 {
9195 /* For relocatable objects we can't use absolute addresses,
9196 so construct the address from a relative offset. */
9197 /* TODO: If the offset is small it's probably worth
9198 constructing the address with adds. */
52ab56c2
PB		 9199 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9200 s->contents + my_offset);
9201 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9202 s->contents + my_offset + 4);
9203 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9204 s->contents + my_offset + 8);
8f6277f5
PB		 9205 /* Adjust the offset by 4 for the position of the add,
9206 and 8 for the pipeline offset. */
9207 ret_offset = (val - (s->output_offset
9208 + s->output_section->vma
9209 + my_offset + 12))
9210 | 1;
9211 bfd_put_32 (output_bfd, ret_offset,
9212 s->contents + my_offset + 12);
9213 }
26079076
PB		 9214 else if (globals->use_blx)
9215 {
9216 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9217 s->contents + my_offset);
9218
9219 /* It's a thumb address. Add the low order bit. */
9220 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9221 s->contents + my_offset + 4);
9222 }
8f6277f5
PB		 9223 else
9224 {
52ab56c2
PB		 9225 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9226 s->contents + my_offset);
252b5132 9227
52ab56c2
PB		 9228 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9229 s->contents + my_offset + 4);
252b5132 9230
8f6277f5
PB		 9231 /* It's a thumb address. Add the low order bit. */
9232 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9233 s->contents + my_offset + 8);
8029a119
NC		 9234
9235 my_offset += 12;
8f6277f5 9236 }
252b5132
RH		 9237 }
9238
9239 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9240
a4fd1a8e
PB		 9241 return myh;
9242}
9243
9244/* Arm code calling a Thumb function. */
9245
9246static int
9247elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9248 const char * name,
9249 bfd * input_bfd,
9250 bfd * output_bfd,
9251 asection * input_section,
9252 bfd_byte * hit_data,
9253 asection * sym_sec,
9254 bfd_vma offset,
9255 bfd_signed_vma addend,
9256 bfd_vma val,
f2a9dd69 9257 char **error_message)
a4fd1a8e
PB		 9258{
9259 unsigned long int tmp;
9260 bfd_vma my_offset;
9261 asection * s;
9262 long int ret_offset;
9263 struct elf_link_hash_entry * myh;
9264 struct elf32_arm_link_hash_table * globals;
9265
9266 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9267 BFD_ASSERT (globals != NULL);
9268 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9269
3d4d4302
AM		 9270 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9271 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9272 BFD_ASSERT (s != NULL);
9273 BFD_ASSERT (s->contents != NULL);
9274 BFD_ASSERT (s->output_section != NULL);
9275
9276 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9277 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9278 if (!myh)
9279 return FALSE;
9280
9281 my_offset = myh->root.u.def.value;
252b5132
RH		 9282 tmp = bfd_get_32 (input_bfd, hit_data);
9283 tmp = tmp & 0xFF000000;
9284
9b485d32 9285 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9286 ret_offset = (s->output_offset
9287 + my_offset
9288 + s->output_section->vma
9289 - (input_section->output_offset
9290 + input_section->output_section->vma
9291 + offset + addend)
9292 - 8);
9a5aca8c 9293
252b5132
RH		 9294 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9295
dc810e39 9296 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9297
b34976b6 9298 return TRUE;
252b5132
RH		 9299}
9300
a4fd1a8e
PB		 9301/* Populate Arm stub for an exported Thumb function. */
9302
9303static bfd_boolean
9304elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9305{
9306 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9307 asection * s;
9308 struct elf_link_hash_entry * myh;
9309 struct elf32_arm_link_hash_entry *eh;
9310 struct elf32_arm_link_hash_table * globals;
9311 asection *sec;
9312 bfd_vma val;
f2a9dd69 9313 char *error_message;
a4fd1a8e 9314
906e58ca 9315 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9316 /* Allocate stubs for exported Thumb functions on v4t. */
9317 if (eh->export_glue == NULL)
9318 return TRUE;
9319
9320 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9321 BFD_ASSERT (globals != NULL);
9322 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9323
3d4d4302
AM		 9324 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9325 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9326 BFD_ASSERT (s != NULL);
9327 BFD_ASSERT (s->contents != NULL);
9328 BFD_ASSERT (s->output_section != NULL);
9329
9330 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9331
9332 BFD_ASSERT (sec->output_section != NULL);
9333
a4fd1a8e
PB		 9334 val = eh->export_glue->root.u.def.value + sec->output_offset
9335 + sec->output_section->vma;
8029a119 9336
a4fd1a8e
PB		 9337 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9338 h->root.u.def.section->owner,
f2a9dd69
DJ		 9339 globals->obfd, sec, val, s,
9340 &error_message);
a4fd1a8e
PB		 9341 BFD_ASSERT (myh);
9342 return TRUE;
9343}
9344
845b51d6
PB		 9345/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9346
9347static bfd_vma
9348elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9349{
9350 bfd_byte *p;
9351 bfd_vma glue_addr;
9352 asection *s;
9353 struct elf32_arm_link_hash_table *globals;
9354
9355 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9356 BFD_ASSERT (globals != NULL);
9357 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9358
3d4d4302
AM		 9359 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9360 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9361 BFD_ASSERT (s != NULL);
9362 BFD_ASSERT (s->contents != NULL);
9363 BFD_ASSERT (s->output_section != NULL);
9364
9365 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9366
9367 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9368
9369 if ((globals->bx_glue_offset[reg] & 1) == 0)
9370 {
9371 p = s->contents + glue_addr;
9372 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9373 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9374 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9375 globals->bx_glue_offset[reg] |= 1;
9376 }
9377
9378 return glue_addr + s->output_section->vma + s->output_offset;
9379}
9380
a4fd1a8e
PB		 9381/* Generate Arm stubs for exported Thumb symbols. */
9382static void
906e58ca 9383elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9384 struct bfd_link_info *link_info)
9385{
9386 struct elf32_arm_link_hash_table * globals;
9387
8029a119
NC		 9388 if (link_info == NULL)
9389 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9390 return;
9391
9392 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9393 if (globals == NULL)
9394 return;
9395
84c08195
PB		 9396 /* If blx is available then exported Thumb symbols are OK and there is
9397 nothing to do. */
a4fd1a8e
PB		 9398 if (globals->use_blx)
9399 return;
9400
9401 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9402 link_info);
9403}
9404
47beaa6a
RS		 9405/* Reserve space for COUNT dynamic relocations in relocation selection
9406 SRELOC. */
9407
9408static void
9409elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9410 bfd_size_type count)
9411{
9412 struct elf32_arm_link_hash_table *htab;
9413
9414 htab = elf32_arm_hash_table (info);
9415 BFD_ASSERT (htab->root.dynamic_sections_created);
9416 if (sreloc == NULL)
9417 abort ();
9418 sreloc->size += RELOC_SIZE (htab) * count;
9419}
9420
34e77a92
RS		 9421/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9422 dynamic, the relocations should go in SRELOC, otherwise they should
9423 go in the special .rel.iplt section. */
9424
9425static void
9426elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9427 bfd_size_type count)
9428{
9429 struct elf32_arm_link_hash_table *htab;
9430
9431 htab = elf32_arm_hash_table (info);
9432 if (!htab->root.dynamic_sections_created)
9433 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9434 else
9435 {
9436 BFD_ASSERT (sreloc != NULL);
9437 sreloc->size += RELOC_SIZE (htab) * count;
9438 }
9439}
9440
47beaa6a
RS		 9441/* Add relocation REL to the end of relocation section SRELOC. */
9442
9443static void
9444elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9445 asection *sreloc, Elf_Internal_Rela *rel)
9446{
9447 bfd_byte *loc;
9448 struct elf32_arm_link_hash_table *htab;
9449
9450 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9451 if (!htab->root.dynamic_sections_created
9452 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9453 sreloc = htab->root.irelplt;
47beaa6a
RS		 9454 if (sreloc == NULL)
9455 abort ();
9456 loc = sreloc->contents;
9457 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9458 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9459 abort ();
9460 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9461}
9462
34e77a92
RS		 9463/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9464 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9465 to .plt. */
9466
9467static void
9468elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9469 bfd_boolean is_iplt_entry,
9470 union gotplt_union *root_plt,
9471 struct arm_plt_info *arm_plt)
9472{
9473 struct elf32_arm_link_hash_table *htab;
9474 asection *splt;
9475 asection *sgotplt;
9476
9477 htab = elf32_arm_hash_table (info);
9478
9479 if (is_iplt_entry)
9480 {
9481 splt = htab->root.iplt;
9482 sgotplt = htab->root.igotplt;
9483
99059e56
RM		 9484 /* NaCl uses a special first entry in .iplt too. */
9485 if (htab->nacl_p && splt->size == 0)
9486 splt->size += htab->plt_header_size;
9487
34e77a92
RS		 9488 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9489 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9490 }
9491 else
9492 {
9493 splt = htab->root.splt;
9494 sgotplt = htab->root.sgotplt;
9495
7801f98f
CL		 9496 if (htab->fdpic_p)
9497 {
9498 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9499 /* For lazy binding, relocations will be put into .rel.plt, in
9500 .rel.got otherwise. */
9501 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9502 if (info->flags & DF_BIND_NOW)
9503 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9504 else
9505 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9506 }
9507 else
9508 {
9509 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9510 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9511 }
34e77a92
RS		 9512
9513 /* If this is the first .plt entry, make room for the special
9514 first entry. */
9515 if (splt->size == 0)
9516 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9517
9518 htab->next_tls_desc_index++;
34e77a92
RS		 9519 }
9520
9521 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9522 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9523 splt->size += PLT_THUMB_STUB_SIZE;
9524 root_plt->offset = splt->size;
9525 splt->size += htab->plt_entry_size;
9526
9527 if (!htab->symbian_p)
9528 {
9529 /* We also need to make an entry in the .got.plt section, which
9530 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9531 if (is_iplt_entry)
9532 arm_plt->got_offset = sgotplt->size;
9533 else
9534 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9535 if (htab->fdpic_p)
9536 /* Function descriptor takes 64 bits in GOT. */
9537 sgotplt->size += 8;
9538 else
9539 sgotplt->size += 4;
34e77a92
RS		 9540 }
9541}
9542
b38cadfb
NC		 9543static bfd_vma
9544arm_movw_immediate (bfd_vma value)
9545{
9546 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9547}
9548
9549static bfd_vma
9550arm_movt_immediate (bfd_vma value)
9551{
9552 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9553}
9554
34e77a92
RS		 9555/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9556 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9557 Otherwise, DYNINDX is the index of the symbol in the dynamic
9558 symbol table and SYM_VALUE is undefined.
9559
9560 ROOT_PLT points to the offset of the PLT entry from the start of its
9561 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9562 bookkeeping information.
34e77a92 9563
57460bcf
NC		 9564 Returns FALSE if there was a problem. */
9565
9566static bfd_boolean
34e77a92
RS		 9567elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9568 union gotplt_union *root_plt,
9569 struct arm_plt_info *arm_plt,
9570 int dynindx, bfd_vma sym_value)
9571{
9572 struct elf32_arm_link_hash_table *htab;
9573 asection *sgot;
9574 asection *splt;
9575 asection *srel;
9576 bfd_byte *loc;
9577 bfd_vma plt_index;
9578 Elf_Internal_Rela rel;
9579 bfd_vma plt_header_size;
9580 bfd_vma got_header_size;
9581
9582 htab = elf32_arm_hash_table (info);
9583
9584 /* Pick the appropriate sections and sizes. */
9585 if (dynindx == -1)
9586 {
9587 splt = htab->root.iplt;
9588 sgot = htab->root.igotplt;
9589 srel = htab->root.irelplt;
9590
9591 /* There are no reserved entries in .igot.plt, and no special
9592 first entry in .iplt. */
9593 got_header_size = 0;
9594 plt_header_size = 0;
9595 }
9596 else
9597 {
9598 splt = htab->root.splt;
9599 sgot = htab->root.sgotplt;
9600 srel = htab->root.srelplt;
9601
9602 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9603 plt_header_size = htab->plt_header_size;
9604 }
9605 BFD_ASSERT (splt != NULL && srel != NULL);
9606
9607 /* Fill in the entry in the procedure linkage table. */
9608 if (htab->symbian_p)
9609 {
9610 BFD_ASSERT (dynindx >= 0);
9611 put_arm_insn (htab, output_bfd,
9612 elf32_arm_symbian_plt_entry[0],
9613 splt->contents + root_plt->offset);
9614 bfd_put_32 (output_bfd,
9615 elf32_arm_symbian_plt_entry[1],
9616 splt->contents + root_plt->offset + 4);
9617
9618 /* Fill in the entry in the .rel.plt section. */
9619 rel.r_offset = (splt->output_section->vma
9620 + splt->output_offset
9621 + root_plt->offset + 4);
9622 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9623
9624 /* Get the index in the procedure linkage table which
9625 corresponds to this symbol. This is the index of this symbol
9626 in all the symbols for which we are making plt entries. The
9627 first entry in the procedure linkage table is reserved. */
9628 plt_index = ((root_plt->offset - plt_header_size)
9629 / htab->plt_entry_size);
9630 }
9631 else
9632 {
9633 bfd_vma got_offset, got_address, plt_address;
9634 bfd_vma got_displacement, initial_got_entry;
9635 bfd_byte * ptr;
9636
9637 BFD_ASSERT (sgot != NULL);
9638
9639 /* Get the offset into the .(i)got.plt table of the entry that
9640 corresponds to this function. */
9641 got_offset = (arm_plt->got_offset & -2);
9642
9643 /* Get the index in the procedure linkage table which
9644 corresponds to this symbol. This is the index of this symbol
9645 in all the symbols for which we are making plt entries.
9646 After the reserved .got.plt entries, all symbols appear in
9647 the same order as in .plt. */
7801f98f
CL		 9648 if (htab->fdpic_p)
9649 /* Function descriptor takes 8 bytes. */
9650 plt_index = (got_offset - got_header_size) / 8;
9651 else
9652 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9653
9654 /* Calculate the address of the GOT entry. */
9655 got_address = (sgot->output_section->vma
9656 + sgot->output_offset
9657 + got_offset);
9658
9659 /* ...and the address of the PLT entry. */
9660 plt_address = (splt->output_section->vma
9661 + splt->output_offset
9662 + root_plt->offset);
9663
9664 ptr = splt->contents + root_plt->offset;
0e1862bb 9665 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9666 {
9667 unsigned int i;
9668 bfd_vma val;
9669
9670 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9671 {
9672 val = elf32_arm_vxworks_shared_plt_entry[i];
9673 if (i == 2)
9674 val |= got_address - sgot->output_section->vma;
9675 if (i == 5)
9676 val |= plt_index * RELOC_SIZE (htab);
9677 if (i == 2 || i == 5)
9678 bfd_put_32 (output_bfd, val, ptr);
9679 else
9680 put_arm_insn (htab, output_bfd, val, ptr);
9681 }
9682 }
9683 else if (htab->vxworks_p)
9684 {
9685 unsigned int i;
9686 bfd_vma val;
9687
9688 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9689 {
9690 val = elf32_arm_vxworks_exec_plt_entry[i];
9691 if (i == 2)
9692 val |= got_address;
9693 if (i == 4)
9694 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9695 if (i == 5)
9696 val |= plt_index * RELOC_SIZE (htab);
9697 if (i == 2 || i == 5)
9698 bfd_put_32 (output_bfd, val, ptr);
9699 else
9700 put_arm_insn (htab, output_bfd, val, ptr);
9701 }
9702
9703 loc = (htab->srelplt2->contents
9704 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9705
9706 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9707 referencing the GOT for this PLT entry. */
9708 rel.r_offset = plt_address + 8;
9709 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9710 rel.r_addend = got_offset;
9711 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9712 loc += RELOC_SIZE (htab);
9713
9714 /* Create the R_ARM_ABS32 relocation referencing the
9715 beginning of the PLT for this GOT entry. */
9716 rel.r_offset = got_address;
9717 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9718 rel.r_addend = 0;
9719 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9720 }
b38cadfb
NC		 9721 else if (htab->nacl_p)
9722 {
9723 /* Calculate the displacement between the PLT slot and the
9724 common tail that's part of the special initial PLT slot. */
6034aab8 9725 int32_t tail_displacement
b38cadfb
NC		 9726 = ((splt->output_section->vma + splt->output_offset
9727 + ARM_NACL_PLT_TAIL_OFFSET)
9728 - (plt_address + htab->plt_entry_size + 4));
9729 BFD_ASSERT ((tail_displacement & 3) == 0);
9730 tail_displacement >>= 2;
9731
9732 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9733 || (-tail_displacement & 0xff000000) == 0);
9734
9735 /* Calculate the displacement between the PLT slot and the entry
9736 in the GOT. The offset accounts for the value produced by
9737 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9738 got_displacement = (got_address
99059e56 9739 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9740
9741 /* NaCl does not support interworking at all. */
9742 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9743
9744 put_arm_insn (htab, output_bfd,
9745 elf32_arm_nacl_plt_entry[0]
9746 | arm_movw_immediate (got_displacement),
9747 ptr + 0);
9748 put_arm_insn (htab, output_bfd,
9749 elf32_arm_nacl_plt_entry[1]
9750 | arm_movt_immediate (got_displacement),
9751 ptr + 4);
9752 put_arm_insn (htab, output_bfd,
9753 elf32_arm_nacl_plt_entry[2],
9754 ptr + 8);
9755 put_arm_insn (htab, output_bfd,
9756 elf32_arm_nacl_plt_entry[3]
9757 | (tail_displacement & 0x00ffffff),
9758 ptr + 12);
9759 }
7801f98f
CL		 9760 else if (htab->fdpic_p)
9761 {
59029f57
CL		 9762 const bfd_vma *plt_entry = using_thumb_only(htab)
9763 ? elf32_arm_fdpic_thumb_plt_entry
9764 : elf32_arm_fdpic_plt_entry;
9765
7801f98f
CL		 9766 /* Fill-up Thumb stub if needed. */
9767 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9768 {
9769 put_thumb_insn (htab, output_bfd,
9770 elf32_arm_plt_thumb_stub[0], ptr - 4);
9771 put_thumb_insn (htab, output_bfd,
9772 elf32_arm_plt_thumb_stub[1], ptr - 2);
9773 }
59029f57
CL		 9774 /* As we are using 32 bit instructions even for the Thumb
9775 version, we have to use 'put_arm_insn' instead of
9776 'put_thumb_insn'. */
9777 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9778 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9779 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9780 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9781 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9782
9783 if (!(info->flags & DF_BIND_NOW))
9784 {
9785 /* funcdesc_value_reloc_offset. */
9786 bfd_put_32 (output_bfd,
9787 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9788 ptr + 20);
59029f57
CL		 9789 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9790 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9791 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9792 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9793 }
9794 }
57460bcf
NC		 9795 else if (using_thumb_only (htab))
9796 {
eed94f8f 9797 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9798 if (!using_thumb2 (htab))
eed94f8f
NC		 9799 {
9800 /* FIXME: We ought to be able to generate thumb-1 PLT
9801 instructions... */
90b6238f 9802 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9803 output_bfd);
9804 return FALSE;
9805 }
57460bcf 9806
eed94f8f
NC		 9807 /* Calculate the displacement between the PLT slot and the entry in
9808 the GOT. The 12-byte offset accounts for the value produced by
9809 adding to pc in the 3rd instruction of the PLT stub. */
9810 got_displacement = got_address - (plt_address + 12);
9811
9812 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9813 instead of 'put_thumb_insn'. */
9814 put_arm_insn (htab, output_bfd,
9815 elf32_thumb2_plt_entry[0]
9816 | ((got_displacement & 0x000000ff) << 16)
9817 | ((got_displacement & 0x00000700) << 20)
9818 | ((got_displacement & 0x00000800) >> 1)
9819 | ((got_displacement & 0x0000f000) >> 12),
9820 ptr + 0);
9821 put_arm_insn (htab, output_bfd,
9822 elf32_thumb2_plt_entry[1]
9823 | ((got_displacement & 0x00ff0000) )
9824 | ((got_displacement & 0x07000000) << 4)
9825 | ((got_displacement & 0x08000000) >> 17)
9826 | ((got_displacement & 0xf0000000) >> 28),
9827 ptr + 4);
9828 put_arm_insn (htab, output_bfd,
9829 elf32_thumb2_plt_entry[2],
9830 ptr + 8);
9831 put_arm_insn (htab, output_bfd,
9832 elf32_thumb2_plt_entry[3],
9833 ptr + 12);
57460bcf 9834 }
34e77a92
RS		 9835 else
9836 {
9837 /* Calculate the displacement between the PLT slot and the
9838 entry in the GOT. The eight-byte offset accounts for the
9839 value produced by adding to pc in the first instruction
9840 of the PLT stub. */
9841 got_displacement = got_address - (plt_address + 8);
9842
34e77a92
RS		 9843 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9844 {
9845 put_thumb_insn (htab, output_bfd,
9846 elf32_arm_plt_thumb_stub[0], ptr - 4);
9847 put_thumb_insn (htab, output_bfd,
9848 elf32_arm_plt_thumb_stub[1], ptr - 2);
9849 }
9850
1db37fe6
YG		 9851 if (!elf32_arm_use_long_plt_entry)
9852 {
9853 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9854
9855 put_arm_insn (htab, output_bfd,
9856 elf32_arm_plt_entry_short[0]
9857 | ((got_displacement & 0x0ff00000) >> 20),
9858 ptr + 0);
9859 put_arm_insn (htab, output_bfd,
9860 elf32_arm_plt_entry_short[1]
9861 | ((got_displacement & 0x000ff000) >> 12),
9862 ptr+ 4);
9863 put_arm_insn (htab, output_bfd,
9864 elf32_arm_plt_entry_short[2]
9865 | (got_displacement & 0x00000fff),
9866 ptr + 8);
34e77a92 9867#ifdef FOUR_WORD_PLT
1db37fe6 9868 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9869#endif
1db37fe6
YG		 9870 }
9871 else
9872 {
9873 put_arm_insn (htab, output_bfd,
9874 elf32_arm_plt_entry_long[0]
9875 | ((got_displacement & 0xf0000000) >> 28),
9876 ptr + 0);
9877 put_arm_insn (htab, output_bfd,
9878 elf32_arm_plt_entry_long[1]
9879 | ((got_displacement & 0x0ff00000) >> 20),
9880 ptr + 4);
9881 put_arm_insn (htab, output_bfd,
9882 elf32_arm_plt_entry_long[2]
9883 | ((got_displacement & 0x000ff000) >> 12),
9884 ptr+ 8);
9885 put_arm_insn (htab, output_bfd,
9886 elf32_arm_plt_entry_long[3]
9887 | (got_displacement & 0x00000fff),
9888 ptr + 12);
9889 }
34e77a92
RS		 9890 }
9891
9892 /* Fill in the entry in the .rel(a).(i)plt section. */
9893 rel.r_offset = got_address;
9894 rel.r_addend = 0;
9895 if (dynindx == -1)
9896 {
9897 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9898 The dynamic linker or static executable then calls SYM_VALUE
9899 to determine the correct run-time value of the .igot.plt entry. */
9900 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9901 initial_got_entry = sym_value;
9902 }
9903 else
9904 {
7801f98f
CL		 9905 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9906 used by PLT entry. */
9907 if (htab->fdpic_p)
9908 {
9909 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9910 initial_got_entry = 0;
9911 }
9912 else
9913 {
9914 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9915 initial_got_entry = (splt->output_section->vma
9916 + splt->output_offset);
9917 }
34e77a92
RS		 9918 }
9919
9920 /* Fill in the entry in the global offset table. */
9921 bfd_put_32 (output_bfd, initial_got_entry,
9922 sgot->contents + got_offset);
7801f98f
CL		 9923
9924 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9925 {
9926 /* Setup initial funcdesc value. */
9927 /* FIXME: we don't support lazy binding because there is a
9928 race condition between both words getting written and
9929 some other thread attempting to read them. The ARM
9930 architecture does not have an atomic 64 bit load/store
9931 instruction that could be used to prevent it; it is
9932 recommended that threaded FDPIC applications run with the
9933 LD_BIND_NOW environment variable set. */
9934 bfd_put_32(output_bfd, plt_address + 0x18,
9935 sgot->contents + got_offset);
9936 bfd_put_32(output_bfd, -1 /*TODO*/,
9937 sgot->contents + got_offset + 4);
9938 }
34e77a92
RS		 9939 }
9940
aba8c3de
WN		 9941 if (dynindx == -1)
9942 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9943 else
9944 {
7801f98f
CL		 9945 if (htab->fdpic_p)
9946 {
9947 /* For FDPIC we put PLT relocationss into .rel.got when not
9948 lazy binding otherwise we put them in .rel.plt. For now,
9949 we don't support lazy binding so put it in .rel.got. */
9950 if (info->flags & DF_BIND_NOW)
9951 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
9952 else
9953 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
9954 }
9955 else
9956 {
9957 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9958 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9959 }
aba8c3de 9960 }
57460bcf
NC		 9961
9962 return TRUE;
34e77a92
RS		 9963}
9964
eb043451
PB		 9965/* Some relocations map to different relocations depending on the
9966 target. Return the real relocation. */
8029a119 9967
eb043451
PB		 9968static int
9969arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9970 int r_type)
9971{
9972 switch (r_type)
9973 {
9974 case R_ARM_TARGET1:
9975 if (globals->target1_is_rel)
9976 return R_ARM_REL32;
9977 else
9978 return R_ARM_ABS32;
9979
9980 case R_ARM_TARGET2:
9981 return globals->target2_reloc;
9982
9983 default:
9984 return r_type;
9985 }
9986}
eb043451 9987
ba93b8ac
DJ		 9988/* Return the base VMA address which should be subtracted from real addresses
9989 when resolving @dtpoff relocation.
9990 This is PT_TLS segment p_vaddr. */
9991
9992static bfd_vma
9993dtpoff_base (struct bfd_link_info *info)
9994{
9995 /* If tls_sec is NULL, we should have signalled an error already. */
9996 if (elf_hash_table (info)->tls_sec == NULL)
9997 return 0;
9998 return elf_hash_table (info)->tls_sec->vma;
9999}
10000
10001/* Return the relocation value for @tpoff relocation
10002 if STT_TLS virtual address is ADDRESS. */
10003
10004static bfd_vma
10005tpoff (struct bfd_link_info *info, bfd_vma address)
10006{
10007 struct elf_link_hash_table *htab = elf_hash_table (info);
10008 bfd_vma base;
10009
10010 /* If tls_sec is NULL, we should have signalled an error already. */
10011 if (htab->tls_sec == NULL)
10012 return 0;
10013 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10014 return address - htab->tls_sec->vma + base;
10015}
10016
00a97672
RS		 10017/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10018 VALUE is the relocation value. */
10019
10020static bfd_reloc_status_type
10021elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10022{
10023 if (value > 0xfff)
10024 return bfd_reloc_overflow;
10025
10026 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10027 bfd_put_32 (abfd, value, data);
10028 return bfd_reloc_ok;
10029}
10030
0855e32b
NS		 10031/* Handle TLS relaxations. Relaxing is possible for symbols that use
10032 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10033 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10034
10035 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10036 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10037 case of error.
10038
10039 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10040 the pre-relaxed code. It would be nice if the relocs were updated
10041 to match the optimization. */
0855e32b 10042
b38cadfb 10043static bfd_reloc_status_type
0855e32b 10044elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10045 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10046 Elf_Internal_Rela *rel, unsigned long is_local)
10047{
10048 unsigned long insn;
b38cadfb 10049
0855e32b
NS		 10050 switch (ELF32_R_TYPE (rel->r_info))
10051 {
10052 default:
10053 return bfd_reloc_notsupported;
b38cadfb 10054
0855e32b
NS		 10055 case R_ARM_TLS_GOTDESC:
10056 if (is_local)
10057 insn = 0;
10058 else
10059 {
10060 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10061 if (insn & 1)
10062 insn -= 5; /* THUMB */
10063 else
10064 insn -= 8; /* ARM */
10065 }
10066 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10067 return bfd_reloc_continue;
10068
10069 case R_ARM_THM_TLS_DESCSEQ:
10070 /* Thumb insn. */
10071 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10072 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10073 {
10074 if (is_local)
10075 /* nop */
10076 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10077 }
10078 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10079 {
10080 if (is_local)
10081 /* nop */
10082 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10083 else
10084 /* ldr rx,[ry] */
10085 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10086 }
10087 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10088 {
10089 if (is_local)
10090 /* nop */
10091 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10092 else
10093 /* mov r0, rx */
10094 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10095 contents + rel->r_offset);
10096 }
10097 else
10098 {
10099 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10100 /* It's a 32 bit instruction, fetch the rest of it for
10101 error generation. */
10102 insn = (insn << 16)
10103 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10104 _bfd_error_handler
695344c0 10105 /* xgettext:c-format */
2dcf00ce 10106 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10107 "unexpected %s instruction '%#lx' in TLS trampoline"),
10108 input_bfd, input_sec, (uint64_t) rel->r_offset,
10109 "Thumb", insn);
0855e32b
NS		 10110 return bfd_reloc_notsupported;
10111 }
10112 break;
b38cadfb 10113
0855e32b
NS		 10114 case R_ARM_TLS_DESCSEQ:
10115 /* arm insn. */
10116 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10117 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10118 {
10119 if (is_local)
10120 /* mov rx, ry */
10121 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10122 contents + rel->r_offset);
10123 }
10124 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10125 {
10126 if (is_local)
10127 /* nop */
10128 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10129 else
10130 /* ldr rx,[ry] */
10131 bfd_put_32 (input_bfd, insn & 0xfffff000,
10132 contents + rel->r_offset);
10133 }
10134 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10135 {
10136 if (is_local)
10137 /* nop */
10138 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10139 else
10140 /* mov r0, rx */
10141 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10142 contents + rel->r_offset);
10143 }
10144 else
10145 {
4eca0228 10146 _bfd_error_handler
695344c0 10147 /* xgettext:c-format */
2dcf00ce 10148 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10149 "unexpected %s instruction '%#lx' in TLS trampoline"),
10150 input_bfd, input_sec, (uint64_t) rel->r_offset,
10151 "ARM", insn);
0855e32b
NS		 10152 return bfd_reloc_notsupported;
10153 }
10154 break;
10155
10156 case R_ARM_TLS_CALL:
10157 /* GD->IE relaxation, turn the instruction into 'nop' or
10158 'ldr r0, [pc,r0]' */
10159 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10160 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10161 break;
b38cadfb 10162
0855e32b 10163 case R_ARM_THM_TLS_CALL:
6a631e86 10164 /* GD->IE relaxation. */
0855e32b
NS		 10165 if (!is_local)
10166 /* add r0,pc; ldr r0, [r0] */
10167 insn = 0x44786800;
60a019a0 10168 else if (using_thumb2 (globals))
0855e32b
NS		 10169 /* nop.w */
10170 insn = 0xf3af8000;
10171 else
10172 /* nop; nop */
10173 insn = 0xbf00bf00;
b38cadfb 10174
0855e32b
NS		 10175 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10176 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10177 break;
10178 }
10179 return bfd_reloc_ok;
10180}
10181
4962c51a
MS		 10182/* For a given value of n, calculate the value of G_n as required to
10183 deal with group relocations. We return it in the form of an
10184 encoded constant-and-rotation, together with the final residual. If n is
10185 specified as less than zero, then final_residual is filled with the
10186 input value and no further action is performed. */
10187
10188static bfd_vma
10189calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10190{
10191 int current_n;
10192 bfd_vma g_n;
10193 bfd_vma encoded_g_n = 0;
10194 bfd_vma residual = value; /* Also known as Y_n. */
10195
10196 for (current_n = 0; current_n <= n; current_n++)
10197 {
10198 int shift;
10199
10200 /* Calculate which part of the value to mask. */
10201 if (residual == 0)
99059e56 10202 shift = 0;
4962c51a 10203 else
99059e56
RM		 10204 {
10205 int msb;
10206
10207 /* Determine the most significant bit in the residual and
10208 align the resulting value to a 2-bit boundary. */
10209 for (msb = 30; msb >= 0; msb -= 2)
10210 if (residual & (3 << msb))
10211 break;
10212
10213 /* The desired shift is now (msb - 6), or zero, whichever
10214 is the greater. */
10215 shift = msb - 6;
10216 if (shift < 0)
10217 shift = 0;
10218 }
4962c51a
MS		 10219
10220 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10221 g_n = residual & (0xff << shift);
10222 encoded_g_n = (g_n >> shift)
99059e56 10223 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10224
10225 /* Calculate the residual for the next time around. */
10226 residual &= ~g_n;
10227 }
10228
10229 *final_residual = residual;
10230
10231 return encoded_g_n;
10232}
10233
10234/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10235 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10236
4962c51a 10237static int
906e58ca 10238identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10239{
10240 int opcode = insn & 0x1e00000;
10241
10242 if (opcode == 1 << 23) /* ADD */
10243 return 1;
10244
10245 if (opcode == 1 << 22) /* SUB */
10246 return -1;
10247
10248 return 0;
10249}
10250
252b5132 10251/* Perform a relocation as part of a final link. */
9b485d32 10252
252b5132 10253static bfd_reloc_status_type
07d6d2b8
AM		 10254elf32_arm_final_link_relocate (reloc_howto_type * howto,
10255 bfd * input_bfd,
10256 bfd * output_bfd,
10257 asection * input_section,
10258 bfd_byte * contents,
10259 Elf_Internal_Rela * rel,
10260 bfd_vma value,
10261 struct bfd_link_info * info,
10262 asection * sym_sec,
10263 const char * sym_name,
10264 unsigned char st_type,
10265 enum arm_st_branch_type branch_type,
0945cdfd 10266 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10267 bfd_boolean * unresolved_reloc_p,
10268 char ** error_message)
10269{
10270 unsigned long r_type = howto->type;
10271 unsigned long r_symndx;
10272 bfd_byte * hit_data = contents + rel->r_offset;
10273 bfd_vma * local_got_offsets;
10274 bfd_vma * local_tlsdesc_gotents;
10275 asection * sgot;
10276 asection * splt;
10277 asection * sreloc = NULL;
10278 asection * srelgot;
10279 bfd_vma addend;
10280 bfd_signed_vma signed_addend;
10281 unsigned char dynreloc_st_type;
10282 bfd_vma dynreloc_value;
ba96a88f 10283 struct elf32_arm_link_hash_table * globals;
34e77a92 10284 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10285 union gotplt_union *root_plt;
10286 struct arm_plt_info *arm_plt;
10287 bfd_vma plt_offset;
10288 bfd_vma gotplt_offset;
10289 bfd_boolean has_iplt_entry;
10290 bfd_boolean resolved_to_zero;
f21f3fe0 10291
9c504268 10292 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10293 if (globals == NULL)
10294 return bfd_reloc_notsupported;
9c504268 10295
0ffa91dd 10296 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10297 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10298
10299 /* Some relocation types map to different relocations depending on the
9c504268 10300 target. We pick the right one here. */
eb043451 10301 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10302
10303 /* It is possible to have linker relaxations on some TLS access
10304 models. Update our information here. */
10305 r_type = elf32_arm_tls_transition (info, r_type, h);
10306
eb043451
PB		 10307 if (r_type != howto->type)
10308 howto = elf32_arm_howto_from_type (r_type);
9c504268 10309
34e77a92 10310 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10311 sgot = globals->root.sgot;
252b5132 10312 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10313 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10314
34e77a92
RS		 10315 if (globals->root.dynamic_sections_created)
10316 srelgot = globals->root.srelgot;
10317 else
10318 srelgot = NULL;
10319
252b5132
RH		 10320 r_symndx = ELF32_R_SYM (rel->r_info);
10321
4e7fd91e 10322 if (globals->use_rel)
ba96a88f 10323 {
4e7fd91e
PB		 10324 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10325
10326 if (addend & ((howto->src_mask + 1) >> 1))
10327 {
10328 signed_addend = -1;
10329 signed_addend &= ~ howto->src_mask;
10330 signed_addend |= addend;
10331 }
10332 else
10333 signed_addend = addend;
ba96a88f
NC		 10334 }
10335 else
4e7fd91e 10336 addend = signed_addend = rel->r_addend;
f21f3fe0 10337
39f21624
NC		 10338 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10339 are resolving a function call relocation. */
10340 if (using_thumb_only (globals)
10341 && (r_type == R_ARM_THM_CALL
10342 || r_type == R_ARM_THM_JUMP24)
10343 && branch_type == ST_BRANCH_TO_ARM)
10344 branch_type = ST_BRANCH_TO_THUMB;
10345
34e77a92
RS		 10346 /* Record the symbol information that should be used in dynamic
10347 relocations. */
10348 dynreloc_st_type = st_type;
10349 dynreloc_value = value;
10350 if (branch_type == ST_BRANCH_TO_THUMB)
10351 dynreloc_value |= 1;
10352
10353 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10354 VALUE appropriately for relocations that we resolve at link time. */
10355 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10356 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10357 &arm_plt)
34e77a92
RS		 10358 && root_plt->offset != (bfd_vma) -1)
10359 {
10360 plt_offset = root_plt->offset;
10361 gotplt_offset = arm_plt->got_offset;
10362
10363 if (h == NULL || eh->is_iplt)
10364 {
10365 has_iplt_entry = TRUE;
10366 splt = globals->root.iplt;
10367
10368 /* Populate .iplt entries here, because not all of them will
10369 be seen by finish_dynamic_symbol. The lower bit is set if
10370 we have already populated the entry. */
10371 if (plt_offset & 1)
10372 plt_offset--;
10373 else
10374 {
57460bcf
NC		 10375 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10376 -1, dynreloc_value))
10377 root_plt->offset |= 1;
10378 else
10379 return bfd_reloc_notsupported;
34e77a92
RS		 10380 }
10381
10382 /* Static relocations always resolve to the .iplt entry. */
10383 st_type = STT_FUNC;
10384 value = (splt->output_section->vma
10385 + splt->output_offset
10386 + plt_offset);
10387 branch_type = ST_BRANCH_TO_ARM;
10388
10389 /* If there are non-call relocations that resolve to the .iplt
10390 entry, then all dynamic ones must too. */
10391 if (arm_plt->noncall_refcount != 0)
10392 {
10393 dynreloc_st_type = st_type;
10394 dynreloc_value = value;
10395 }
10396 }
10397 else
10398 /* We populate the .plt entry in finish_dynamic_symbol. */
10399 splt = globals->root.splt;
10400 }
10401 else
10402 {
10403 splt = NULL;
10404 plt_offset = (bfd_vma) -1;
10405 gotplt_offset = (bfd_vma) -1;
10406 }
10407
95b03e4a
L		 10408 resolved_to_zero = (h != NULL
10409 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10410
252b5132
RH		 10411 switch (r_type)
10412 {
10413 case R_ARM_NONE:
28a094c2
DJ		 10414 /* We don't need to find a value for this symbol. It's just a
10415 marker. */
10416 *unresolved_reloc_p = FALSE;
252b5132
RH		 10417 return bfd_reloc_ok;
10418
00a97672
RS		 10419 case R_ARM_ABS12:
10420 if (!globals->vxworks_p)
10421 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10422 /* Fall through. */
00a97672 10423
252b5132
RH		 10424 case R_ARM_PC24:
10425 case R_ARM_ABS32:
bb224fc3 10426 case R_ARM_ABS32_NOI:
252b5132 10427 case R_ARM_REL32:
bb224fc3 10428 case R_ARM_REL32_NOI:
5b5bb741
PB		 10429 case R_ARM_CALL:
10430 case R_ARM_JUMP24:
dfc5f959 10431 case R_ARM_XPC25:
eb043451 10432 case R_ARM_PREL31:
7359ea65 10433 case R_ARM_PLT32:
7359ea65
DJ		 10434 /* Handle relocations which should use the PLT entry. ABS32/REL32
10435 will use the symbol's value, which may point to a PLT entry, but we
10436 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10437 branches in this object should go to it, except if the PLT is too
10438 far away, in which case a long branch stub should be inserted. */
bb224fc3 10439 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10440 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10441 && r_type != R_ARM_CALL
10442 && r_type != R_ARM_JUMP24
10443 && r_type != R_ARM_PLT32)
34e77a92 10444 && plt_offset != (bfd_vma) -1)
7359ea65 10445 {
34e77a92
RS		 10446 /* If we've created a .plt section, and assigned a PLT entry
10447 to this function, it must either be a STT_GNU_IFUNC reference
10448 or not be known to bind locally. In other cases, we should
10449 have cleared the PLT entry by now. */
10450 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10451
10452 value = (splt->output_section->vma
10453 + splt->output_offset
34e77a92 10454 + plt_offset);
0945cdfd 10455 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10456 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10457 contents, rel->r_offset, value,
00a97672 10458 rel->r_addend);
7359ea65
DJ		 10459 }
10460
67687978
PB		 10461 /* When generating a shared object or relocatable executable, these
10462 relocations are copied into the output file to be resolved at
10463 run time. */
0e1862bb 10464 if ((bfd_link_pic (info)
e8b09b87
CL		 10465 || globals->root.is_relocatable_executable
10466 || globals->fdpic_p)
7359ea65 10467 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10468 && !(globals->vxworks_p
3348747a
NS		 10469 && strcmp (input_section->output_section->name,
10470 ".tls_vars") == 0)
bb224fc3 10471 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10472 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10473 && !(input_bfd == globals->stub_bfd
10474 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10475 && (h == NULL
95b03e4a
L		 10476 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10477 && !resolved_to_zero)
7359ea65
DJ		 10478 || h->root.type != bfd_link_hash_undefweak)
10479 && r_type != R_ARM_PC24
5b5bb741
PB		 10480 && r_type != R_ARM_CALL
10481 && r_type != R_ARM_JUMP24
ee06dc07 10482 && r_type != R_ARM_PREL31
7359ea65 10483 && r_type != R_ARM_PLT32)
252b5132 10484 {
947216bf 10485 Elf_Internal_Rela outrel;
b34976b6 10486 bfd_boolean skip, relocate;
e8b09b87 10487 int isrofixup = 0;
f21f3fe0 10488
52db4ec2
JW		 10489 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10490 && !h->def_regular)
10491 {
10492 char *v = _("shared object");
10493
0e1862bb 10494 if (bfd_link_executable (info))
52db4ec2
JW		 10495 v = _("PIE executable");
10496
4eca0228 10497 _bfd_error_handler
871b3ab2 10498 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10499 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10500 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10501 return bfd_reloc_notsupported;
10502 }
10503
0945cdfd
DJ		 10504 *unresolved_reloc_p = FALSE;
10505
34e77a92 10506 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10507 {
83bac4b0
NC		 10508 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10509 ! globals->use_rel);
f21f3fe0 10510
83bac4b0 10511 if (sreloc == NULL)
252b5132 10512 return bfd_reloc_notsupported;
252b5132 10513 }
f21f3fe0 10514
b34976b6
AM		 10515 skip = FALSE;
10516 relocate = FALSE;
f21f3fe0 10517
00a97672 10518 outrel.r_addend = addend;
c629eae0
JJ		 10519 outrel.r_offset =
10520 _bfd_elf_section_offset (output_bfd, info, input_section,
10521 rel->r_offset);
10522 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10523 skip = TRUE;
0bb2d96a 10524 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10525 skip = TRUE, relocate = TRUE;
252b5132
RH		 10526 outrel.r_offset += (input_section->output_section->vma
10527 + input_section->output_offset);
f21f3fe0 10528
252b5132 10529 if (skip)
0bb2d96a 10530 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10531 else if (h != NULL
10532 && h->dynindx != -1
0e1862bb 10533 && (!bfd_link_pic (info)
1dcb9720
JW		 10534 || !(bfd_link_pie (info)
10535 || SYMBOLIC_BIND (info, h))
f5385ebf 10536 || !h->def_regular))
5e681ec4 10537 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10538 else
10539 {
a16385dc
MM		 10540 int symbol;
10541
5e681ec4 10542 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10543 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10544 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10545 if (globals->symbian_p)
6366ff1e 10546 {
74541ad4
AM		 10547 asection *osec;
10548
6366ff1e
MM		 10549 /* On Symbian OS, the data segment and text segement
10550 can be relocated independently. Therefore, we
10551 must indicate the segment to which this
10552 relocation is relative. The BPABI allows us to
10553 use any symbol in the right segment; we just use
10554 the section symbol as it is convenient. (We
10555 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10556 will not appear in the dynamic symbol table.)
10557
10558 Note that the dynamic linker ignores the section
10559 symbol value, so we don't subtract osec->vma
10560 from the emitted reloc addend. */
10dbd1f3 10561 if (sym_sec)
74541ad4 10562 osec = sym_sec->output_section;
10dbd1f3 10563 else
74541ad4
AM		 10564 osec = input_section->output_section;
10565 symbol = elf_section_data (osec)->dynindx;
10566 if (symbol == 0)
10567 {
10568 struct elf_link_hash_table *htab = elf_hash_table (info);
10569
10570 if ((osec->flags & SEC_READONLY) == 0
10571 && htab->data_index_section != NULL)
10572 osec = htab->data_index_section;
10573 else
10574 osec = htab->text_index_section;
10575 symbol = elf_section_data (osec)->dynindx;
10576 }
6366ff1e
MM		 10577 BFD_ASSERT (symbol != 0);
10578 }
a16385dc
MM		 10579 else
10580 /* On SVR4-ish systems, the dynamic loader cannot
10581 relocate the text and data segments independently,
10582 so the symbol does not matter. */
10583 symbol = 0;
34e77a92
RS		 10584 if (dynreloc_st_type == STT_GNU_IFUNC)
10585 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10586 to the .iplt entry. Instead, every non-call reference
10587 must use an R_ARM_IRELATIVE relocation to obtain the
10588 correct run-time address. */
10589 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10590 else if (globals->fdpic_p && !bfd_link_pic(info))
10591 isrofixup = 1;
34e77a92
RS		 10592 else
10593 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10594 if (globals->use_rel)
10595 relocate = TRUE;
10596 else
34e77a92 10597 outrel.r_addend += dynreloc_value;
252b5132 10598 }
f21f3fe0 10599
e8b09b87
CL		 10600 if (isrofixup)
10601 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10602 else
10603 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10604
f21f3fe0 10605 /* If this reloc is against an external symbol, we do not want to
252b5132 10606 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10607 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10608 if (! relocate)
10609 return bfd_reloc_ok;
9a5aca8c 10610
f21f3fe0 10611 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10612 contents, rel->r_offset,
10613 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10614 }
10615 else switch (r_type)
10616 {
00a97672
RS		 10617 case R_ARM_ABS12:
10618 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10619
dfc5f959 10620 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10621 case R_ARM_CALL:
10622 case R_ARM_JUMP24:
8029a119 10623 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10624 case R_ARM_PLT32:
906e58ca 10625 {
906e58ca
NC		 10626 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10627
dfc5f959 10628 if (r_type == R_ARM_XPC25)
252b5132 10629 {
dfc5f959
NC		 10630 /* Check for Arm calling Arm function. */
10631 /* FIXME: Should we translate the instruction into a BL
10632 instruction instead ? */
35fc36a8 10633 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10634 _bfd_error_handler
90b6238f
AM		 10635 (_("\%pB: warning: %s BLX instruction targets"
10636 " %s function '%s'"),
10637 input_bfd, "ARM",
10638 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10639 }
155d87d7 10640 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10641 {
10642 /* Check for Arm calling Thumb function. */
35fc36a8 10643 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10644 {
f2a9dd69
DJ		 10645 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10646 output_bfd, input_section,
10647 hit_data, sym_sec, rel->r_offset,
10648 signed_addend, value,
10649 error_message))
10650 return bfd_reloc_ok;
10651 else
10652 return bfd_reloc_dangerous;
dfc5f959 10653 }
252b5132 10654 }
ba96a88f 10655
906e58ca 10656 /* Check if a stub has to be inserted because the
8029a119 10657 destination is too far or we are changing mode. */
155d87d7
CL		 10658 if ( r_type == R_ARM_CALL
10659 || r_type == R_ARM_JUMP24
10660 || r_type == R_ARM_PLT32)
906e58ca 10661 {
fe33d2fa
CL		 10662 enum elf32_arm_stub_type stub_type = arm_stub_none;
10663 struct elf32_arm_link_hash_entry *hash;
10664
10665 hash = (struct elf32_arm_link_hash_entry *) h;
10666 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10667 st_type, &branch_type,
10668 hash, value, sym_sec,
fe33d2fa 10669 input_bfd, sym_name);
5fa9e92f 10670
fe33d2fa 10671 if (stub_type != arm_stub_none)
906e58ca
NC		 10672 {
10673 /* The target is out of reach, so redirect the
10674 branch to the local stub for this function. */
906e58ca
NC		 10675 stub_entry = elf32_arm_get_stub_entry (input_section,
10676 sym_sec, h,
fe33d2fa
CL		 10677 rel, globals,
10678 stub_type);
9cd3e4e5
NC		 10679 {
10680 if (stub_entry != NULL)
10681 value = (stub_entry->stub_offset
10682 + stub_entry->stub_sec->output_offset
10683 + stub_entry->stub_sec->output_section->vma);
10684
10685 if (plt_offset != (bfd_vma) -1)
10686 *unresolved_reloc_p = FALSE;
10687 }
906e58ca 10688 }
fe33d2fa
CL		 10689 else
10690 {
10691 /* If the call goes through a PLT entry, make sure to
10692 check distance to the right destination address. */
34e77a92 10693 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10694 {
10695 value = (splt->output_section->vma
10696 + splt->output_offset
34e77a92 10697 + plt_offset);
fe33d2fa
CL		 10698 *unresolved_reloc_p = FALSE;
10699 /* The PLT entry is in ARM mode, regardless of the
10700 target function. */
35fc36a8 10701 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10702 }
10703 }
906e58ca
NC		 10704 }
10705
dea514f5
PB		 10706 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10707 where:
10708 S is the address of the symbol in the relocation.
10709 P is address of the instruction being relocated.
10710 A is the addend (extracted from the instruction) in bytes.
10711
10712 S is held in 'value'.
10713 P is the base address of the section containing the
10714 instruction plus the offset of the reloc into that
10715 section, ie:
10716 (input_section->output_section->vma +
10717 input_section->output_offset +
10718 rel->r_offset).
10719 A is the addend, converted into bytes, ie:
10720 (signed_addend * 4)
10721
10722 Note: None of these operations have knowledge of the pipeline
10723 size of the processor, thus it is up to the assembler to
10724 encode this information into the addend. */
10725 value -= (input_section->output_section->vma
10726 + input_section->output_offset);
10727 value -= rel->r_offset;
4e7fd91e
PB		 10728 if (globals->use_rel)
10729 value += (signed_addend << howto->size);
10730 else
10731 /* RELA addends do not have to be adjusted by howto->size. */
10732 value += signed_addend;
23080146 10733
dcb5e6e6
NC		 10734 signed_addend = value;
10735 signed_addend >>= howto->rightshift;
9a5aca8c 10736
5ab79981 10737 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10738 the next instruction unless a PLT entry will be created.
77b4f08f 10739 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10740 The jump to the next instruction is optimized as a NOP depending
10741 on the architecture. */
ffcb4889 10742 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10743 && plt_offset == (bfd_vma) -1)
77b4f08f 10744 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10745 {
cd1dac3d
DG		 10746 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10747
10748 if (arch_has_arm_nop (globals))
10749 value |= 0x0320f000;
10750 else
10751 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10752 }
10753 else
59f2c4e7 10754 {
9b485d32 10755 /* Perform a signed range check. */
dcb5e6e6 10756 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10757 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10758 return bfd_reloc_overflow;
9a5aca8c 10759
5ab79981 10760 addend = (value & 2);
39b41c9c 10761
5ab79981
PB		 10762 value = (signed_addend & howto->dst_mask)
10763 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10764
5ab79981
PB		 10765 if (r_type == R_ARM_CALL)
10766 {
155d87d7 10767 /* Set the H bit in the BLX instruction. */
35fc36a8 10768 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10769 {
10770 if (addend)
10771 value |= (1 << 24);
10772 else
10773 value &= ~(bfd_vma)(1 << 24);
10774 }
10775
5ab79981 10776 /* Select the correct instruction (BL or BLX). */
906e58ca 10777 /* Only if we are not handling a BL to a stub. In this
8029a119 10778 case, mode switching is performed by the stub. */
35fc36a8 10779 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10780 value |= (1 << 28);
63e1a0fc 10781 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10782 {
10783 value &= ~(bfd_vma)(1 << 28);
10784 value |= (1 << 24);
10785 }
39b41c9c
PB		 10786 }
10787 }
906e58ca 10788 }
252b5132 10789 break;
f21f3fe0 10790
252b5132
RH		 10791 case R_ARM_ABS32:
10792 value += addend;
35fc36a8 10793 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10794 value |= 1;
10795 break;
f21f3fe0 10796
bb224fc3
MS		 10797 case R_ARM_ABS32_NOI:
10798 value += addend;
10799 break;
10800
252b5132 10801 case R_ARM_REL32:
a8bc6c78 10802 value += addend;
35fc36a8 10803 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10804 value |= 1;
252b5132 10805 value -= (input_section->output_section->vma
62efb346 10806 + input_section->output_offset + rel->r_offset);
252b5132 10807 break;
eb043451 10808
bb224fc3
MS		 10809 case R_ARM_REL32_NOI:
10810 value += addend;
10811 value -= (input_section->output_section->vma
10812 + input_section->output_offset + rel->r_offset);
10813 break;
10814
eb043451
PB		 10815 case R_ARM_PREL31:
10816 value -= (input_section->output_section->vma
10817 + input_section->output_offset + rel->r_offset);
10818 value += signed_addend;
10819 if (! h || h->root.type != bfd_link_hash_undefweak)
10820 {
8029a119 10821 /* Check for overflow. */
eb043451
PB		 10822 if ((value ^ (value >> 1)) & (1 << 30))
10823 return bfd_reloc_overflow;
10824 }
10825 value &= 0x7fffffff;
10826 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10827 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10828 value |= 1;
10829 break;
252b5132 10830 }
f21f3fe0 10831
252b5132
RH		 10832 bfd_put_32 (input_bfd, value, hit_data);
10833 return bfd_reloc_ok;
10834
10835 case R_ARM_ABS8:
fd0fd00c
MJ		 10836 /* PR 16202: Refectch the addend using the correct size. */
10837 if (globals->use_rel)
10838 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10839 value += addend;
4e67d4ca
DG		 10840
10841 /* There is no way to tell whether the user intended to use a signed or
10842 unsigned addend. When checking for overflow we accept either,
10843 as specified by the AAELF. */
10844 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10845 return bfd_reloc_overflow;
10846
10847 bfd_put_8 (input_bfd, value, hit_data);
10848 return bfd_reloc_ok;
10849
10850 case R_ARM_ABS16:
fd0fd00c
MJ		 10851 /* PR 16202: Refectch the addend using the correct size. */
10852 if (globals->use_rel)
10853 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10854 value += addend;
10855
4e67d4ca
DG		 10856 /* See comment for R_ARM_ABS8. */
10857 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10858 return bfd_reloc_overflow;
10859
10860 bfd_put_16 (input_bfd, value, hit_data);
10861 return bfd_reloc_ok;
10862
252b5132 10863 case R_ARM_THM_ABS5:
9b485d32 10864 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10865 if (globals->use_rel)
10866 {
10867 /* Need to refetch addend. */
10868 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10869 /* ??? Need to determine shift amount from operand size. */
10870 addend >>= howto->rightshift;
10871 }
252b5132
RH		 10872 value += addend;
10873
10874 /* ??? Isn't value unsigned? */
10875 if ((long) value > 0x1f || (long) value < -0x10)
10876 return bfd_reloc_overflow;
10877
10878 /* ??? Value needs to be properly shifted into place first. */
10879 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10880 bfd_put_16 (input_bfd, value, hit_data);
10881 return bfd_reloc_ok;
10882
2cab6cc3
MS		 10883 case R_ARM_THM_ALU_PREL_11_0:
10884 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10885 {
10886 bfd_vma insn;
10887 bfd_signed_vma relocation;
10888
10889 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10890 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10891
99059e56
RM		 10892 if (globals->use_rel)
10893 {
10894 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10895 | ((insn & (1 << 26)) >> 15);
10896 if (insn & 0xf00000)
10897 signed_addend = -signed_addend;
10898 }
2cab6cc3
MS		 10899
10900 relocation = value + signed_addend;
79f08007 10901 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10902 + input_section->output_offset
10903 + rel->r_offset);
2cab6cc3 10904
8c65b54f
CS		 10905 /* PR 21523: Use an absolute value. The user of this reloc will
10906 have already selected an ADD or SUB insn appropriately. */
e652757b 10907 value = labs (relocation);
2cab6cc3 10908
99059e56
RM		 10909 if (value >= 0x1000)
10910 return bfd_reloc_overflow;
2cab6cc3 10911
e645cf40
AG		 10912 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10913 if (branch_type == ST_BRANCH_TO_THUMB)
10914 value |= 1;
10915
2cab6cc3 10916 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10917 | ((value & 0x700) << 4)
10918 | ((value & 0x800) << 15);
10919 if (relocation < 0)
10920 insn |= 0xa00000;
2cab6cc3
MS		 10921
10922 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10923 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10924
99059e56 10925 return bfd_reloc_ok;
2cab6cc3
MS		 10926 }
10927
e1ec24c6
NC		 10928 case R_ARM_THM_PC8:
10929 /* PR 10073: This reloc is not generated by the GNU toolchain,
10930 but it is supported for compatibility with third party libraries
10931 generated by other compilers, specifically the ARM/IAR. */
10932 {
10933 bfd_vma insn;
10934 bfd_signed_vma relocation;
10935
10936 insn = bfd_get_16 (input_bfd, hit_data);
10937
99059e56 10938 if (globals->use_rel)
79f08007 10939 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10940
10941 relocation = value + addend;
79f08007 10942 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10943 + input_section->output_offset
10944 + rel->r_offset);
e1ec24c6 10945
b6518b38 10946 value = relocation;
e1ec24c6
NC		 10947
10948 /* We do not check for overflow of this reloc. Although strictly
10949 speaking this is incorrect, it appears to be necessary in order
10950 to work with IAR generated relocs. Since GCC and GAS do not
10951 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10952 a problem for them. */
10953 value &= 0x3fc;
10954
10955 insn = (insn & 0xff00) | (value >> 2);
10956
10957 bfd_put_16 (input_bfd, insn, hit_data);
10958
99059e56 10959 return bfd_reloc_ok;
e1ec24c6
NC		 10960 }
10961
2cab6cc3
MS		 10962 case R_ARM_THM_PC12:
10963 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10964 {
10965 bfd_vma insn;
10966 bfd_signed_vma relocation;
10967
10968 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10969 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10970
99059e56
RM		 10971 if (globals->use_rel)
10972 {
10973 signed_addend = insn & 0xfff;
10974 if (!(insn & (1 << 23)))
10975 signed_addend = -signed_addend;
10976 }
2cab6cc3
MS		 10977
10978 relocation = value + signed_addend;
79f08007 10979 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10980 + input_section->output_offset
10981 + rel->r_offset);
2cab6cc3 10982
b6518b38 10983 value = relocation;
2cab6cc3 10984
99059e56
RM		 10985 if (value >= 0x1000)
10986 return bfd_reloc_overflow;
2cab6cc3
MS		 10987
10988 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10989 if (relocation >= 0)
10990 insn |= (1 << 23);
2cab6cc3
MS		 10991
10992 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10993 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10994
99059e56 10995 return bfd_reloc_ok;
2cab6cc3
MS		 10996 }
10997
dfc5f959 10998 case R_ARM_THM_XPC22:
c19d1205 10999 case R_ARM_THM_CALL:
bd97cb95 11000 case R_ARM_THM_JUMP24:
dfc5f959 11001 /* Thumb BL (branch long instruction). */
252b5132 11002 {
b34976b6 11003 bfd_vma relocation;
99059e56 11004 bfd_vma reloc_sign;
b34976b6
AM		 11005 bfd_boolean overflow = FALSE;
11006 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11007 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11008 bfd_signed_vma reloc_signed_max;
11009 bfd_signed_vma reloc_signed_min;
b34976b6 11010 bfd_vma check;
252b5132 11011 bfd_signed_vma signed_check;
e95de063 11012 int bitsize;
cd1dac3d 11013 const int thumb2 = using_thumb2 (globals);
5e866f5a 11014 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11015
5ab79981 11016 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11017 the next instruction unless a PLT entry will be created.
11018 The jump to the next instruction is optimized as a NOP.W for
11019 Thumb-2 enabled architectures. */
19540007 11020 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11021 && plt_offset == (bfd_vma) -1)
5ab79981 11022 {
60a019a0 11023 if (thumb2)
cd1dac3d
DG		 11024 {
11025 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11026 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11027 }
11028 else
11029 {
11030 bfd_put_16 (input_bfd, 0xe000, hit_data);
11031 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11032 }
5ab79981
PB		 11033 return bfd_reloc_ok;
11034 }
11035
e95de063 11036 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11037 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11038 if (globals->use_rel)
11039 {
99059e56
RM		 11040 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11041 bfd_vma upper = upper_insn & 0x3ff;
11042 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11043 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11044 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11045 bfd_vma i1 = j1 ^ s ? 0 : 1;
11046 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11047
99059e56
RM		 11048 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11049 /* Sign extend. */
11050 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11051
4e7fd91e
PB		 11052 signed_addend = addend;
11053 }
cb1afa5c 11054
dfc5f959
NC		 11055 if (r_type == R_ARM_THM_XPC22)
11056 {
11057 /* Check for Thumb to Thumb call. */
11058 /* FIXME: Should we translate the instruction into a BL
11059 instruction instead ? */
35fc36a8 11060 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11061 _bfd_error_handler
90b6238f
AM		 11062 (_("%pB: warning: %s BLX instruction targets"
11063 " %s function '%s'"),
11064 input_bfd, "Thumb",
11065 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11066 }
11067 else
252b5132 11068 {
dfc5f959
NC		 11069 /* If it is not a call to Thumb, assume call to Arm.
11070 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11071 function call at all, but rather a long jump. Calls through
11072 the PLT do not require stubs. */
34e77a92 11073 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11074 {
bd97cb95 11075 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11076 {
11077 /* Convert BL to BLX. */
11078 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11079 }
155d87d7
CL		 11080 else if (( r_type != R_ARM_THM_CALL)
11081 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11082 {
11083 if (elf32_thumb_to_arm_stub
11084 (info, sym_name, input_bfd, output_bfd, input_section,
11085 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11086 error_message))
11087 return bfd_reloc_ok;
11088 else
11089 return bfd_reloc_dangerous;
11090 }
da5938a2 11091 }
35fc36a8
RS		 11092 else if (branch_type == ST_BRANCH_TO_THUMB
11093 && globals->use_blx
bd97cb95 11094 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11095 {
11096 /* Make sure this is a BL. */
11097 lower_insn |= 0x1800;
11098 }
252b5132 11099 }
f21f3fe0 11100
fe33d2fa 11101 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11102 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11103 {
11104 /* Check if a stub has to be inserted because the destination
8029a119 11105 is too far. */
fe33d2fa
CL		 11106 struct elf32_arm_stub_hash_entry *stub_entry;
11107 struct elf32_arm_link_hash_entry *hash;
11108
11109 hash = (struct elf32_arm_link_hash_entry *) h;
11110
11111 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11112 st_type, &branch_type,
11113 hash, value, sym_sec,
fe33d2fa
CL		 11114 input_bfd, sym_name);
11115
11116 if (stub_type != arm_stub_none)
906e58ca
NC		 11117 {
11118 /* The target is out of reach or we are changing modes, so
11119 redirect the branch to the local stub for this
11120 function. */
11121 stub_entry = elf32_arm_get_stub_entry (input_section,
11122 sym_sec, h,
fe33d2fa
CL		 11123 rel, globals,
11124 stub_type);
906e58ca 11125 if (stub_entry != NULL)
9cd3e4e5
NC		 11126 {
11127 value = (stub_entry->stub_offset
11128 + stub_entry->stub_sec->output_offset
11129 + stub_entry->stub_sec->output_section->vma);
11130
11131 if (plt_offset != (bfd_vma) -1)
11132 *unresolved_reloc_p = FALSE;
11133 }
906e58ca 11134
f4ac8484 11135 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11136 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11137 {
11138 if ((stub_entry
11139 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11140 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11141 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11142 }
906e58ca
NC		 11143 }
11144 }
11145
fe33d2fa 11146 /* Handle calls via the PLT. */
34e77a92 11147 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11148 {
11149 value = (splt->output_section->vma
11150 + splt->output_offset
34e77a92 11151 + plt_offset);
fe33d2fa 11152
eed94f8f
NC		 11153 if (globals->use_blx
11154 && r_type == R_ARM_THM_CALL
11155 && ! using_thumb_only (globals))
fe33d2fa
CL		 11156 {
11157 /* If the Thumb BLX instruction is available, convert
11158 the BL to a BLX instruction to call the ARM-mode
11159 PLT entry. */
11160 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11161 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11162 }
11163 else
11164 {
eed94f8f
NC		 11165 if (! using_thumb_only (globals))
11166 /* Target the Thumb stub before the ARM PLT entry. */
11167 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11168 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11169 }
11170 *unresolved_reloc_p = FALSE;
11171 }
11172
ba96a88f 11173 relocation = value + signed_addend;
f21f3fe0 11174
252b5132 11175 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11176 + input_section->output_offset
11177 + rel->r_offset);
9a5aca8c 11178
252b5132
RH		 11179 check = relocation >> howto->rightshift;
11180
11181 /* If this is a signed value, the rightshift just dropped
11182 leading 1 bits (assuming twos complement). */
11183 if ((bfd_signed_vma) relocation >= 0)
11184 signed_check = check;
11185 else
11186 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11187
e95de063
MS		 11188 /* Calculate the permissable maximum and minimum values for
11189 this relocation according to whether we're relocating for
11190 Thumb-2 or not. */
11191 bitsize = howto->bitsize;
5e866f5a 11192 if (!thumb2_bl)
e95de063 11193 bitsize -= 2;
f6ebfac0 11194 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11195 reloc_signed_min = ~reloc_signed_max;
11196
252b5132 11197 /* Assumes two's complement. */
ba96a88f 11198 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11199 overflow = TRUE;
252b5132 11200
bd97cb95 11201 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11202 /* For a BLX instruction, make sure that the relocation is rounded up
11203 to a word boundary. This follows the semantics of the instruction
11204 which specifies that bit 1 of the target address will come from bit
11205 1 of the base address. */
11206 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11207
e95de063
MS		 11208 /* Put RELOCATION back into the insn. Assumes two's complement.
11209 We use the Thumb-2 encoding, which is safe even if dealing with
11210 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11211 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11212 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11213 | ((relocation >> 12) & 0x3ff)
11214 | (reloc_sign << 10);
906e58ca 11215 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11216 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11217 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11218 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11219
252b5132
RH		 11220 /* Put the relocated value back in the object file: */
11221 bfd_put_16 (input_bfd, upper_insn, hit_data);
11222 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11223
11224 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11225 }
11226 break;
11227
c19d1205
ZW		 11228 case R_ARM_THM_JUMP19:
11229 /* Thumb32 conditional branch instruction. */
11230 {
11231 bfd_vma relocation;
11232 bfd_boolean overflow = FALSE;
11233 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11234 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11235 bfd_signed_vma reloc_signed_max = 0xffffe;
11236 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11237 bfd_signed_vma signed_check;
07d6d2b8 11238 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11239 struct elf32_arm_stub_hash_entry *stub_entry;
11240 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11241
11242 /* Need to refetch the addend, reconstruct the top three bits,
11243 and squish the two 11 bit pieces together. */
11244 if (globals->use_rel)
11245 {
11246 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11247 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11248 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11249 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11250 bfd_vma lower = (lower_insn & 0x07ff);
11251
a00a1f35
MS		 11252 upper |= J1 << 6;
11253 upper |= J2 << 7;
11254 upper |= (!S) << 8;
c19d1205
ZW		 11255 upper -= 0x0100; /* Sign extend. */
11256
11257 addend = (upper << 12) | (lower << 1);
11258 signed_addend = addend;
11259 }
11260
bd97cb95 11261 /* Handle calls via the PLT. */
34e77a92 11262 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11263 {
11264 value = (splt->output_section->vma
11265 + splt->output_offset
34e77a92 11266 + plt_offset);
bd97cb95
DJ		 11267 /* Target the Thumb stub before the ARM PLT entry. */
11268 value -= PLT_THUMB_STUB_SIZE;
11269 *unresolved_reloc_p = FALSE;
11270 }
11271
c5423981
TG		 11272 hash = (struct elf32_arm_link_hash_entry *)h;
11273
11274 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11275 st_type, &branch_type,
11276 hash, value, sym_sec,
11277 input_bfd, sym_name);
c5423981
TG		 11278 if (stub_type != arm_stub_none)
11279 {
11280 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11281 sym_sec, h,
11282 rel, globals,
11283 stub_type);
c5423981
TG		 11284 if (stub_entry != NULL)
11285 {
07d6d2b8
AM		 11286 value = (stub_entry->stub_offset
11287 + stub_entry->stub_sec->output_offset
11288 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11289 }
11290 }
c19d1205 11291
99059e56 11292 relocation = value + signed_addend;
c19d1205
ZW		 11293 relocation -= (input_section->output_section->vma
11294 + input_section->output_offset
11295 + rel->r_offset);
a00a1f35 11296 signed_check = (bfd_signed_vma) relocation;
c19d1205 11297
c19d1205
ZW		 11298 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11299 overflow = TRUE;
11300
11301 /* Put RELOCATION back into the insn. */
11302 {
11303 bfd_vma S = (relocation & 0x00100000) >> 20;
11304 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11305 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11306 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11307 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11308
a00a1f35 11309 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11310 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11311 }
11312
11313 /* Put the relocated value back in the object file: */
11314 bfd_put_16 (input_bfd, upper_insn, hit_data);
11315 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11316
11317 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11318 }
11319
11320 case R_ARM_THM_JUMP11:
11321 case R_ARM_THM_JUMP8:
11322 case R_ARM_THM_JUMP6:
51c5503b
NC		 11323 /* Thumb B (branch) instruction). */
11324 {
6cf9e9fe 11325 bfd_signed_vma relocation;
51c5503b
NC		 11326 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11327 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11328 bfd_signed_vma signed_check;
11329
c19d1205
ZW		 11330 /* CZB cannot jump backward. */
11331 if (r_type == R_ARM_THM_JUMP6)
11332 reloc_signed_min = 0;
11333
4e7fd91e 11334 if (globals->use_rel)
6cf9e9fe 11335 {
4e7fd91e
PB		 11336 /* Need to refetch addend. */
11337 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11338 if (addend & ((howto->src_mask + 1) >> 1))
11339 {
11340 signed_addend = -1;
11341 signed_addend &= ~ howto->src_mask;
11342 signed_addend |= addend;
11343 }
11344 else
11345 signed_addend = addend;
11346 /* The value in the insn has been right shifted. We need to
11347 undo this, so that we can perform the address calculation
11348 in terms of bytes. */
11349 signed_addend <<= howto->rightshift;
6cf9e9fe 11350 }
6cf9e9fe 11351 relocation = value + signed_addend;
51c5503b
NC		 11352
11353 relocation -= (input_section->output_section->vma
11354 + input_section->output_offset
11355 + rel->r_offset);
11356
6cf9e9fe
NC		 11357 relocation >>= howto->rightshift;
11358 signed_check = relocation;
c19d1205
ZW		 11359
11360 if (r_type == R_ARM_THM_JUMP6)
11361 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11362 else
11363 relocation &= howto->dst_mask;
51c5503b 11364 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11365
51c5503b
NC		 11366 bfd_put_16 (input_bfd, relocation, hit_data);
11367
11368 /* Assumes two's complement. */
11369 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11370 return bfd_reloc_overflow;
11371
11372 return bfd_reloc_ok;
11373 }
cedb70c5 11374
8375c36b
PB		 11375 case R_ARM_ALU_PCREL7_0:
11376 case R_ARM_ALU_PCREL15_8:
11377 case R_ARM_ALU_PCREL23_15:
11378 {
11379 bfd_vma insn;
11380 bfd_vma relocation;
11381
11382 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11383 if (globals->use_rel)
11384 {
11385 /* Extract the addend. */
11386 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11387 signed_addend = addend;
11388 }
8375c36b
PB		 11389 relocation = value + signed_addend;
11390
11391 relocation -= (input_section->output_section->vma
11392 + input_section->output_offset
11393 + rel->r_offset);
11394 insn = (insn & ~0xfff)
11395 | ((howto->bitpos << 7) & 0xf00)
11396 | ((relocation >> howto->bitpos) & 0xff);
11397 bfd_put_32 (input_bfd, value, hit_data);
11398 }
11399 return bfd_reloc_ok;
11400
252b5132
RH		 11401 case R_ARM_GNU_VTINHERIT:
11402 case R_ARM_GNU_VTENTRY:
11403 return bfd_reloc_ok;
11404
c19d1205 11405 case R_ARM_GOTOFF32:
252b5132 11406 /* Relocation is relative to the start of the
99059e56 11407 global offset table. */
252b5132
RH		 11408
11409 BFD_ASSERT (sgot != NULL);
11410 if (sgot == NULL)
99059e56 11411 return bfd_reloc_notsupported;
9a5aca8c 11412
cedb70c5 11413 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11414 address by one, so that attempts to call the function pointer will
11415 correctly interpret it as Thumb code. */
35fc36a8 11416 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11417 value += 1;
11418
252b5132 11419 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11420 calculation. We always want the start of .got. If we
11421 define _GLOBAL_OFFSET_TABLE in a different way, as is
11422 permitted by the ABI, we might have to change this
11423 calculation. */
252b5132 11424 value -= sgot->output_section->vma;
f21f3fe0 11425 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11426 contents, rel->r_offset, value,
00a97672 11427 rel->r_addend);
252b5132
RH		 11428
11429 case R_ARM_GOTPC:
a7c10850 11430 /* Use global offset table as symbol value. */
252b5132 11431 BFD_ASSERT (sgot != NULL);
f21f3fe0 11432
252b5132 11433 if (sgot == NULL)
99059e56 11434 return bfd_reloc_notsupported;
252b5132 11435
0945cdfd 11436 *unresolved_reloc_p = FALSE;
252b5132 11437 value = sgot->output_section->vma;
f21f3fe0 11438 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11439 contents, rel->r_offset, value,
00a97672 11440 rel->r_addend);
f21f3fe0 11441
252b5132 11442 case R_ARM_GOT32:
eb043451 11443 case R_ARM_GOT_PREL:
252b5132 11444 /* Relocation is to the entry for this symbol in the
99059e56 11445 global offset table. */
252b5132
RH		 11446 if (sgot == NULL)
11447 return bfd_reloc_notsupported;
f21f3fe0 11448
34e77a92
RS		 11449 if (dynreloc_st_type == STT_GNU_IFUNC
11450 && plt_offset != (bfd_vma) -1
11451 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11452 {
11453 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11454 symbol, and the relocation resolves directly to the runtime
11455 target rather than to the .iplt entry. This means that any
11456 .got entry would be the same value as the .igot.plt entry,
11457 so there's no point creating both. */
11458 sgot = globals->root.igotplt;
11459 value = sgot->output_offset + gotplt_offset;
11460 }
11461 else if (h != NULL)
252b5132
RH		 11462 {
11463 bfd_vma off;
f21f3fe0 11464
252b5132
RH		 11465 off = h->got.offset;
11466 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11467 if ((off & 1) != 0)
252b5132 11468 {
b436d854
RS		 11469 /* We have already processsed one GOT relocation against
11470 this symbol. */
11471 off &= ~1;
11472 if (globals->root.dynamic_sections_created
11473 && !SYMBOL_REFERENCES_LOCAL (info, h))
11474 *unresolved_reloc_p = FALSE;
11475 }
11476 else
11477 {
11478 Elf_Internal_Rela outrel;
e8b09b87 11479 int isrofixup = 0;
b436d854 11480
e8b09b87
CL		 11481 if (((h->dynindx != -1) || globals->fdpic_p)
11482 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11483 {
11484 /* If the symbol doesn't resolve locally in a static
11485 object, we have an undefined reference. If the
11486 symbol doesn't resolve locally in a dynamic object,
11487 it should be resolved by the dynamic linker. */
11488 if (globals->root.dynamic_sections_created)
11489 {
11490 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11491 *unresolved_reloc_p = FALSE;
11492 }
11493 else
11494 outrel.r_info = 0;
11495 outrel.r_addend = 0;
11496 }
252b5132
RH		 11497 else
11498 {
34e77a92 11499 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11500 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11501 else if (bfd_link_pic (info)
11502 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11503 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11504 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11505 else
2376f038
EB		 11506 {
11507 outrel.r_info = 0;
11508 if (globals->fdpic_p)
11509 isrofixup = 1;
11510 }
34e77a92 11511 outrel.r_addend = dynreloc_value;
b436d854 11512 }
ee29b9fb 11513
b436d854
RS		 11514 /* The GOT entry is initialized to zero by default.
11515 See if we should install a different value. */
11516 if (outrel.r_addend != 0
2376f038 11517 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11518 {
11519 bfd_put_32 (output_bfd, outrel.r_addend,
11520 sgot->contents + off);
11521 outrel.r_addend = 0;
252b5132 11522 }
f21f3fe0 11523
2376f038
EB		 11524 if (isrofixup)
11525 arm_elf_add_rofixup (output_bfd,
11526 elf32_arm_hash_table(info)->srofixup,
11527 sgot->output_section->vma
11528 + sgot->output_offset + off);
11529
11530 else if (outrel.r_info != 0)
b436d854
RS		 11531 {
11532 outrel.r_offset = (sgot->output_section->vma
11533 + sgot->output_offset
11534 + off);
11535 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11536 }
2376f038 11537
b436d854
RS		 11538 h->got.offset |= 1;
11539 }
252b5132
RH		 11540 value = sgot->output_offset + off;
11541 }
11542 else
11543 {
11544 bfd_vma off;
f21f3fe0 11545
5025eb7c
AO		 11546 BFD_ASSERT (local_got_offsets != NULL
11547 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11548
252b5132 11549 off = local_got_offsets[r_symndx];
f21f3fe0 11550
252b5132
RH		 11551 /* The offset must always be a multiple of 4. We use the
11552 least significant bit to record whether we have already
9b485d32 11553 generated the necessary reloc. */
252b5132
RH		 11554 if ((off & 1) != 0)
11555 off &= ~1;
11556 else
11557 {
2376f038
EB		 11558 Elf_Internal_Rela outrel;
11559 int isrofixup = 0;
f21f3fe0 11560
2376f038
EB		 11561 if (dynreloc_st_type == STT_GNU_IFUNC)
11562 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11563 else if (bfd_link_pic (info))
11564 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11565 else
252b5132 11566 {
2376f038
EB		 11567 outrel.r_info = 0;
11568 if (globals->fdpic_p)
11569 isrofixup = 1;
11570 }
11571
11572 /* The GOT entry is initialized to zero by default.
11573 See if we should install a different value. */
11574 if (globals->use_rel || outrel.r_info == 0)
11575 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11576
11577 if (isrofixup)
11578 arm_elf_add_rofixup (output_bfd,
11579 globals->srofixup,
11580 sgot->output_section->vma
11581 + sgot->output_offset + off);
f21f3fe0 11582
2376f038
EB		 11583 else if (outrel.r_info != 0)
11584 {
34e77a92 11585 outrel.r_addend = addend + dynreloc_value;
252b5132 11586 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11587 + sgot->output_offset
252b5132 11588 + off);
47beaa6a 11589 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11590 }
f21f3fe0 11591
252b5132
RH		 11592 local_got_offsets[r_symndx] |= 1;
11593 }
f21f3fe0 11594
252b5132
RH		 11595 value = sgot->output_offset + off;
11596 }
eb043451
PB		 11597 if (r_type != R_ARM_GOT32)
11598 value += sgot->output_section->vma;
9a5aca8c 11599
f21f3fe0 11600 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11601 contents, rel->r_offset, value,
00a97672 11602 rel->r_addend);
f21f3fe0 11603
ba93b8ac
DJ		 11604 case R_ARM_TLS_LDO32:
11605 value = value - dtpoff_base (info);
11606
11607 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11608 contents, rel->r_offset, value,
11609 rel->r_addend);
ba93b8ac
DJ		 11610
11611 case R_ARM_TLS_LDM32:
5c5a4843 11612 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11613 {
11614 bfd_vma off;
11615
362d30a1 11616 if (sgot == NULL)
ba93b8ac
DJ		 11617 abort ();
11618
11619 off = globals->tls_ldm_got.offset;
11620
11621 if ((off & 1) != 0)
11622 off &= ~1;
11623 else
11624 {
11625 /* If we don't know the module number, create a relocation
11626 for it. */
0e1862bb 11627 if (bfd_link_pic (info))
ba93b8ac
DJ		 11628 {
11629 Elf_Internal_Rela outrel;
ba93b8ac 11630
362d30a1 11631 if (srelgot == NULL)
ba93b8ac
DJ		 11632 abort ();
11633
00a97672 11634 outrel.r_addend = 0;
362d30a1
RS		 11635 outrel.r_offset = (sgot->output_section->vma
11636 + sgot->output_offset + off);
ba93b8ac
DJ		 11637 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11638
00a97672
RS		 11639 if (globals->use_rel)
11640 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11641 sgot->contents + off);
ba93b8ac 11642
47beaa6a 11643 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11644 }
11645 else
362d30a1 11646 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11647
11648 globals->tls_ldm_got.offset |= 1;
11649 }
11650
5c5a4843 11651 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11652 {
11653 bfd_put_32(output_bfd,
11654 globals->root.sgot->output_offset + off,
11655 contents + rel->r_offset);
11656
11657 return bfd_reloc_ok;
11658 }
11659 else
11660 {
11661 value = sgot->output_section->vma + sgot->output_offset + off
11662 - (input_section->output_section->vma
11663 + input_section->output_offset + rel->r_offset);
ba93b8ac 11664
e8b09b87
CL		 11665 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11666 contents, rel->r_offset, value,
11667 rel->r_addend);
11668 }
ba93b8ac
DJ		 11669 }
11670
0855e32b
NS		 11671 case R_ARM_TLS_CALL:
11672 case R_ARM_THM_TLS_CALL:
ba93b8ac 11673 case R_ARM_TLS_GD32:
5c5a4843 11674 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11675 case R_ARM_TLS_IE32:
5c5a4843 11676 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11677 case R_ARM_TLS_GOTDESC:
11678 case R_ARM_TLS_DESCSEQ:
11679 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11680 {
0855e32b
NS		 11681 bfd_vma off, offplt;
11682 int indx = 0;
ba93b8ac
DJ		 11683 char tls_type;
11684
0855e32b 11685 BFD_ASSERT (sgot != NULL);
ba93b8ac 11686
ba93b8ac
DJ		 11687 if (h != NULL)
11688 {
11689 bfd_boolean dyn;
11690 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11691 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11692 bfd_link_pic (info),
11693 h)
11694 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11695 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11696 {
11697 *unresolved_reloc_p = FALSE;
11698 indx = h->dynindx;
11699 }
11700 off = h->got.offset;
0855e32b 11701 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11702 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11703 }
11704 else
11705 {
0855e32b 11706 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11707 off = local_got_offsets[r_symndx];
0855e32b 11708 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11709 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11710 }
11711
0855e32b 11712 /* Linker relaxations happens from one of the
b38cadfb 11713 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11714 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11715 tls_type = GOT_TLS_IE;
0855e32b
NS		 11716
11717 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11718
11719 if ((off & 1) != 0)
11720 off &= ~1;
11721 else
11722 {
11723 bfd_boolean need_relocs = FALSE;
11724 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11725 int cur_off = off;
11726
11727 /* The GOT entries have not been initialized yet. Do it
11728 now, and emit any relocations. If both an IE GOT and a
11729 GD GOT are necessary, we emit the GD first. */
11730
0e1862bb 11731 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11732 && (h == NULL
95b03e4a
L		 11733 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11734 && !resolved_to_zero)
ba93b8ac
DJ		 11735 || h->root.type != bfd_link_hash_undefweak))
11736 {
11737 need_relocs = TRUE;
0855e32b 11738 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11739 }
11740
0855e32b
NS		 11741 if (tls_type & GOT_TLS_GDESC)
11742 {
47beaa6a
RS		 11743 bfd_byte *loc;
11744
0855e32b
NS		 11745 /* We should have relaxed, unless this is an undefined
11746 weak symbol. */
11747 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11748 || bfd_link_pic (info));
0855e32b 11749 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11750 <= globals->root.sgotplt->size);
0855e32b
NS		 11751
11752 outrel.r_addend = 0;
11753 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11754 + globals->root.sgotplt->output_offset
11755 + offplt
11756 + globals->sgotplt_jump_table_size);
b38cadfb 11757
0855e32b
NS		 11758 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11759 sreloc = globals->root.srelplt;
11760 loc = sreloc->contents;
11761 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11762 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11763 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11764
11765 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11766
11767 /* For globals, the first word in the relocation gets
11768 the relocation index and the top bit set, or zero,
11769 if we're binding now. For locals, it gets the
11770 symbol's offset in the tls section. */
99059e56 11771 bfd_put_32 (output_bfd,
0855e32b
NS		 11772 !h ? value - elf_hash_table (info)->tls_sec->vma
11773 : info->flags & DF_BIND_NOW ? 0
11774 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11775 globals->root.sgotplt->contents + offplt
11776 + globals->sgotplt_jump_table_size);
11777
0855e32b 11778 /* Second word in the relocation is always zero. */
99059e56 11779 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11780 globals->root.sgotplt->contents + offplt
11781 + globals->sgotplt_jump_table_size + 4);
0855e32b 11782 }
ba93b8ac
DJ		 11783 if (tls_type & GOT_TLS_GD)
11784 {
11785 if (need_relocs)
11786 {
00a97672 11787 outrel.r_addend = 0;
362d30a1
RS		 11788 outrel.r_offset = (sgot->output_section->vma
11789 + sgot->output_offset
00a97672 11790 + cur_off);
ba93b8ac 11791 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11792
00a97672
RS		 11793 if (globals->use_rel)
11794 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11795 sgot->contents + cur_off);
00a97672 11796
47beaa6a 11797 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11798
11799 if (indx == 0)
11800 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11801 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11802 else
11803 {
00a97672 11804 outrel.r_addend = 0;
ba93b8ac
DJ		 11805 outrel.r_info = ELF32_R_INFO (indx,
11806 R_ARM_TLS_DTPOFF32);
11807 outrel.r_offset += 4;
00a97672
RS		 11808
11809 if (globals->use_rel)
11810 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11811 sgot->contents + cur_off + 4);
00a97672 11812
47beaa6a
RS		 11813 elf32_arm_add_dynreloc (output_bfd, info,
11814 srelgot, &outrel);
ba93b8ac
DJ		 11815 }
11816 }
11817 else
11818 {
11819 /* If we are not emitting relocations for a
11820 general dynamic reference, then we must be in a
11821 static link or an executable link with the
11822 symbol binding locally. Mark it as belonging
11823 to module 1, the executable. */
11824 bfd_put_32 (output_bfd, 1,
362d30a1 11825 sgot->contents + cur_off);
ba93b8ac 11826 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11827 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11828 }
11829
11830 cur_off += 8;
11831 }
11832
11833 if (tls_type & GOT_TLS_IE)
11834 {
11835 if (need_relocs)
11836 {
00a97672
RS		 11837 if (indx == 0)
11838 outrel.r_addend = value - dtpoff_base (info);
11839 else
11840 outrel.r_addend = 0;
362d30a1
RS		 11841 outrel.r_offset = (sgot->output_section->vma
11842 + sgot->output_offset
ba93b8ac
DJ		 11843 + cur_off);
11844 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11845
00a97672
RS		 11846 if (globals->use_rel)
11847 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11848 sgot->contents + cur_off);
ba93b8ac 11849
47beaa6a 11850 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11851 }
11852 else
11853 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11854 sgot->contents + cur_off);
ba93b8ac
DJ		 11855 cur_off += 4;
11856 }
11857
11858 if (h != NULL)
11859 h->got.offset |= 1;
11860 else
11861 local_got_offsets[r_symndx] |= 1;
11862 }
11863
5c5a4843 11864 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11865 off += 8;
0855e32b
NS		 11866 else if (tls_type & GOT_TLS_GDESC)
11867 off = offplt;
11868
11869 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11870 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11871 {
11872 bfd_signed_vma offset;
12352d3f
PB		 11873 /* TLS stubs are arm mode. The original symbol is a
11874 data object, so branch_type is bogus. */
11875 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11876 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11877 = arm_type_of_stub (info, input_section, rel,
11878 st_type, &branch_type,
0855e32b
NS		 11879 (struct elf32_arm_link_hash_entry *)h,
11880 globals->tls_trampoline, globals->root.splt,
11881 input_bfd, sym_name);
11882
11883 if (stub_type != arm_stub_none)
11884 {
11885 struct elf32_arm_stub_hash_entry *stub_entry
11886 = elf32_arm_get_stub_entry
11887 (input_section, globals->root.splt, 0, rel,
11888 globals, stub_type);
11889 offset = (stub_entry->stub_offset
11890 + stub_entry->stub_sec->output_offset
11891 + stub_entry->stub_sec->output_section->vma);
11892 }
11893 else
11894 offset = (globals->root.splt->output_section->vma
11895 + globals->root.splt->output_offset
11896 + globals->tls_trampoline);
11897
11898 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11899 {
11900 unsigned long inst;
b38cadfb
NC		 11901
11902 offset -= (input_section->output_section->vma
11903 + input_section->output_offset
11904 + rel->r_offset + 8);
0855e32b
NS		 11905
11906 inst = offset >> 2;
11907 inst &= 0x00ffffff;
11908 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11909 }
11910 else
11911 {
11912 /* Thumb blx encodes the offset in a complicated
11913 fashion. */
11914 unsigned upper_insn, lower_insn;
11915 unsigned neg;
11916
b38cadfb
NC		 11917 offset -= (input_section->output_section->vma
11918 + input_section->output_offset
0855e32b 11919 + rel->r_offset + 4);
b38cadfb 11920
12352d3f
PB		 11921 if (stub_type != arm_stub_none
11922 && arm_stub_is_thumb (stub_type))
11923 {
11924 lower_insn = 0xd000;
11925 }
11926 else
11927 {
11928 lower_insn = 0xc000;
6a631e86 11929 /* Round up the offset to a word boundary. */
12352d3f
PB		 11930 offset = (offset + 2) & ~2;
11931 }
11932
0855e32b
NS		 11933 neg = offset < 0;
11934 upper_insn = (0xf000
11935 | ((offset >> 12) & 0x3ff)
11936 | (neg << 10));
12352d3f 11937 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11938 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11939 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11940 bfd_put_16 (input_bfd, upper_insn, hit_data);
11941 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11942 return bfd_reloc_ok;
11943 }
11944 }
11945 /* These relocations needs special care, as besides the fact
11946 they point somewhere in .gotplt, the addend must be
11947 adjusted accordingly depending on the type of instruction
6a631e86 11948 we refer to. */
0855e32b
NS		 11949 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11950 {
11951 unsigned long data, insn;
11952 unsigned thumb;
b38cadfb 11953
0855e32b
NS		 11954 data = bfd_get_32 (input_bfd, hit_data);
11955 thumb = data & 1;
11956 data &= ~1u;
b38cadfb 11957
0855e32b
NS		 11958 if (thumb)
11959 {
11960 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11961 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11962 insn = (insn << 16)
11963 | bfd_get_16 (input_bfd,
11964 contents + rel->r_offset - data + 2);
11965 if ((insn & 0xf800c000) == 0xf000c000)
11966 /* bl/blx */
11967 value = -6;
11968 else if ((insn & 0xffffff00) == 0x4400)
11969 /* add */
11970 value = -5;
11971 else
11972 {
4eca0228 11973 _bfd_error_handler
695344c0 11974 /* xgettext:c-format */
2dcf00ce 11975 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11976 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11977 "referenced by TLS_GOTDESC"),
11978 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11979 "Thumb", insn);
0855e32b
NS		 11980 return bfd_reloc_notsupported;
11981 }
11982 }
11983 else
11984 {
11985 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11986
11987 switch (insn >> 24)
11988 {
11989 case 0xeb: /* bl */
11990 case 0xfa: /* blx */
11991 value = -4;
11992 break;
11993
11994 case 0xe0: /* add */
11995 value = -8;
11996 break;
b38cadfb 11997
0855e32b 11998 default:
4eca0228 11999 _bfd_error_handler
695344c0 12000 /* xgettext:c-format */
2dcf00ce 12001 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12002 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12003 "referenced by TLS_GOTDESC"),
12004 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12005 "ARM", insn);
0855e32b
NS		 12006 return bfd_reloc_notsupported;
12007 }
12008 }
b38cadfb 12009
0855e32b
NS		 12010 value += ((globals->root.sgotplt->output_section->vma
12011 + globals->root.sgotplt->output_offset + off)
12012 - (input_section->output_section->vma
12013 + input_section->output_offset
12014 + rel->r_offset)
12015 + globals->sgotplt_jump_table_size);
12016 }
12017 else
12018 value = ((globals->root.sgot->output_section->vma
12019 + globals->root.sgot->output_offset + off)
12020 - (input_section->output_section->vma
12021 + input_section->output_offset + rel->r_offset));
ba93b8ac 12022
5c5a4843
CL		 12023 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12024 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12025 {
12026 /* For FDPIC relocations, resolve to the offset of the GOT
12027 entry from the start of GOT. */
12028 bfd_put_32(output_bfd,
12029 globals->root.sgot->output_offset + off,
12030 contents + rel->r_offset);
12031
12032 return bfd_reloc_ok;
12033 }
12034 else
12035 {
12036 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12037 contents, rel->r_offset, value,
12038 rel->r_addend);
12039 }
ba93b8ac
DJ		 12040 }
12041
12042 case R_ARM_TLS_LE32:
3cbc1e5e 12043 if (bfd_link_dll (info))
ba93b8ac 12044 {
4eca0228 12045 _bfd_error_handler
695344c0 12046 /* xgettext:c-format */
2dcf00ce
AM		 12047 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12048 "in shared object"),
12049 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12050 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12051 }
12052 else
12053 value = tpoff (info, value);
906e58ca 12054
ba93b8ac 12055 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12056 contents, rel->r_offset, value,
12057 rel->r_addend);
ba93b8ac 12058
319850b4
JB		 12059 case R_ARM_V4BX:
12060 if (globals->fix_v4bx)
845b51d6
PB		 12061 {
12062 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12063
845b51d6
PB		 12064 /* Ensure that we have a BX instruction. */
12065 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12066
845b51d6
PB		 12067 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12068 {
12069 /* Branch to veneer. */
12070 bfd_vma glue_addr;
12071 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12072 glue_addr -= input_section->output_section->vma
12073 + input_section->output_offset
12074 + rel->r_offset + 8;
12075 insn = (insn & 0xf0000000) | 0x0a000000
12076 | ((glue_addr >> 2) & 0x00ffffff);
12077 }
12078 else
12079 {
12080 /* Preserve Rm (lowest four bits) and the condition code
12081 (highest four bits). Other bits encode MOV PC,Rm. */
12082 insn = (insn & 0xf000000f) | 0x01a0f000;
12083 }
319850b4 12084
845b51d6
PB		 12085 bfd_put_32 (input_bfd, insn, hit_data);
12086 }
319850b4
JB		 12087 return bfd_reloc_ok;
12088
b6895b4f
PB		 12089 case R_ARM_MOVW_ABS_NC:
12090 case R_ARM_MOVT_ABS:
12091 case R_ARM_MOVW_PREL_NC:
12092 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12093 /* Until we properly support segment-base-relative addressing then
12094 we assume the segment base to be zero, as for the group relocations.
12095 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12096 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12097 case R_ARM_MOVW_BREL_NC:
12098 case R_ARM_MOVW_BREL:
12099 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12100 {
12101 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12102
12103 if (globals->use_rel)
12104 {
12105 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12106 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12107 }
92f5d02b 12108
b6895b4f 12109 value += signed_addend;
b6895b4f
PB		 12110
12111 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12112 value -= (input_section->output_section->vma
12113 + input_section->output_offset + rel->r_offset);
12114
92f5d02b 12115 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12116 return bfd_reloc_overflow;
92f5d02b 12117
35fc36a8 12118 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12119 value |= 1;
12120
12121 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12122 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12123 value >>= 16;
12124
12125 insn &= 0xfff0f000;
12126 insn |= value & 0xfff;
12127 insn |= (value & 0xf000) << 4;
12128 bfd_put_32 (input_bfd, insn, hit_data);
12129 }
12130 return bfd_reloc_ok;
12131
12132 case R_ARM_THM_MOVW_ABS_NC:
12133 case R_ARM_THM_MOVT_ABS:
12134 case R_ARM_THM_MOVW_PREL_NC:
12135 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12136 /* Until we properly support segment-base-relative addressing then
12137 we assume the segment base to be zero, as for the above relocations.
12138 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12139 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12140 as R_ARM_THM_MOVT_ABS. */
12141 case R_ARM_THM_MOVW_BREL_NC:
12142 case R_ARM_THM_MOVW_BREL:
12143 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12144 {
12145 bfd_vma insn;
906e58ca 12146
b6895b4f
PB		 12147 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12148 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12149
12150 if (globals->use_rel)
12151 {
12152 addend = ((insn >> 4) & 0xf000)
12153 | ((insn >> 15) & 0x0800)
12154 | ((insn >> 4) & 0x0700)
07d6d2b8 12155 | (insn & 0x00ff);
39623e12 12156 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12157 }
92f5d02b 12158
b6895b4f 12159 value += signed_addend;
b6895b4f
PB		 12160
12161 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12162 value -= (input_section->output_section->vma
12163 + input_section->output_offset + rel->r_offset);
12164
92f5d02b 12165 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12166 return bfd_reloc_overflow;
92f5d02b 12167
35fc36a8 12168 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12169 value |= 1;
12170
12171 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12172 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12173 value >>= 16;
12174
12175 insn &= 0xfbf08f00;
12176 insn |= (value & 0xf000) << 4;
12177 insn |= (value & 0x0800) << 15;
12178 insn |= (value & 0x0700) << 4;
12179 insn |= (value & 0x00ff);
12180
12181 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12182 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12183 }
12184 return bfd_reloc_ok;
12185
4962c51a
MS		 12186 case R_ARM_ALU_PC_G0_NC:
12187 case R_ARM_ALU_PC_G1_NC:
12188 case R_ARM_ALU_PC_G0:
12189 case R_ARM_ALU_PC_G1:
12190 case R_ARM_ALU_PC_G2:
12191 case R_ARM_ALU_SB_G0_NC:
12192 case R_ARM_ALU_SB_G1_NC:
12193 case R_ARM_ALU_SB_G0:
12194 case R_ARM_ALU_SB_G1:
12195 case R_ARM_ALU_SB_G2:
12196 {
12197 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12198 bfd_vma pc = input_section->output_section->vma
4962c51a 12199 + input_section->output_offset + rel->r_offset;
31a91d61 12200 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12201 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12202 bfd_vma residual;
12203 bfd_vma g_n;
4962c51a 12204 bfd_signed_vma signed_value;
99059e56
RM		 12205 int group = 0;
12206
12207 /* Determine which group of bits to select. */
12208 switch (r_type)
12209 {
12210 case R_ARM_ALU_PC_G0_NC:
12211 case R_ARM_ALU_PC_G0:
12212 case R_ARM_ALU_SB_G0_NC:
12213 case R_ARM_ALU_SB_G0:
12214 group = 0;
12215 break;
12216
12217 case R_ARM_ALU_PC_G1_NC:
12218 case R_ARM_ALU_PC_G1:
12219 case R_ARM_ALU_SB_G1_NC:
12220 case R_ARM_ALU_SB_G1:
12221 group = 1;
12222 break;
12223
12224 case R_ARM_ALU_PC_G2:
12225 case R_ARM_ALU_SB_G2:
12226 group = 2;
12227 break;
12228
12229 default:
12230 abort ();
12231 }
12232
12233 /* If REL, extract the addend from the insn. If RELA, it will
12234 have already been fetched for us. */
4962c51a 12235 if (globals->use_rel)
99059e56
RM		 12236 {
12237 int negative;
12238 bfd_vma constant = insn & 0xff;
12239 bfd_vma rotation = (insn & 0xf00) >> 8;
12240
12241 if (rotation == 0)
12242 signed_addend = constant;
12243 else
12244 {
12245 /* Compensate for the fact that in the instruction, the
12246 rotation is stored in multiples of 2 bits. */
12247 rotation *= 2;
12248
12249 /* Rotate "constant" right by "rotation" bits. */
12250 signed_addend = (constant >> rotation) |
12251 (constant << (8 * sizeof (bfd_vma) - rotation));
12252 }
12253
12254 /* Determine if the instruction is an ADD or a SUB.
12255 (For REL, this determines the sign of the addend.) */
12256 negative = identify_add_or_sub (insn);
12257 if (negative == 0)
12258 {
4eca0228 12259 _bfd_error_handler
695344c0 12260 /* xgettext:c-format */
90b6238f 12261 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12262 "are allowed for ALU group relocations"),
12263 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12264 return bfd_reloc_overflow;
12265 }
12266
12267 signed_addend *= negative;
12268 }
4962c51a
MS		 12269
12270 /* Compute the value (X) to go in the place. */
99059e56
RM		 12271 if (r_type == R_ARM_ALU_PC_G0_NC
12272 || r_type == R_ARM_ALU_PC_G1_NC
12273 || r_type == R_ARM_ALU_PC_G0
12274 || r_type == R_ARM_ALU_PC_G1
12275 || r_type == R_ARM_ALU_PC_G2)
12276 /* PC relative. */
12277 signed_value = value - pc + signed_addend;
12278 else
12279 /* Section base relative. */
12280 signed_value = value - sb + signed_addend;
12281
12282 /* If the target symbol is a Thumb function, then set the
12283 Thumb bit in the address. */
35fc36a8 12284 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12285 signed_value |= 1;
12286
99059e56
RM		 12287 /* Calculate the value of the relevant G_n, in encoded
12288 constant-with-rotation format. */
b6518b38
NC		 12289 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12290 group, &residual);
99059e56
RM		 12291
12292 /* Check for overflow if required. */
12293 if ((r_type == R_ARM_ALU_PC_G0
12294 || r_type == R_ARM_ALU_PC_G1
12295 || r_type == R_ARM_ALU_PC_G2
12296 || r_type == R_ARM_ALU_SB_G0
12297 || r_type == R_ARM_ALU_SB_G1
12298 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12299 {
4eca0228 12300 _bfd_error_handler
695344c0 12301 /* xgettext:c-format */
90b6238f 12302 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12303 "splitting %#" PRIx64 " for group relocation %s"),
12304 input_bfd, input_section, (uint64_t) rel->r_offset,
12305 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12306 howto->name);
99059e56
RM		 12307 return bfd_reloc_overflow;
12308 }
12309
12310 /* Mask out the value and the ADD/SUB part of the opcode; take care
12311 not to destroy the S bit. */
12312 insn &= 0xff1ff000;
12313
12314 /* Set the opcode according to whether the value to go in the
12315 place is negative. */
12316 if (signed_value < 0)
12317 insn |= 1 << 22;
12318 else
12319 insn |= 1 << 23;
12320
12321 /* Encode the offset. */
12322 insn |= g_n;
4962c51a
MS		 12323
12324 bfd_put_32 (input_bfd, insn, hit_data);
12325 }
12326 return bfd_reloc_ok;
12327
12328 case R_ARM_LDR_PC_G0:
12329 case R_ARM_LDR_PC_G1:
12330 case R_ARM_LDR_PC_G2:
12331 case R_ARM_LDR_SB_G0:
12332 case R_ARM_LDR_SB_G1:
12333 case R_ARM_LDR_SB_G2:
12334 {
12335 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12336 bfd_vma pc = input_section->output_section->vma
4962c51a 12337 + input_section->output_offset + rel->r_offset;
31a91d61 12338 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12339 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12340 bfd_vma residual;
4962c51a 12341 bfd_signed_vma signed_value;
99059e56
RM		 12342 int group = 0;
12343
12344 /* Determine which groups of bits to calculate. */
12345 switch (r_type)
12346 {
12347 case R_ARM_LDR_PC_G0:
12348 case R_ARM_LDR_SB_G0:
12349 group = 0;
12350 break;
12351
12352 case R_ARM_LDR_PC_G1:
12353 case R_ARM_LDR_SB_G1:
12354 group = 1;
12355 break;
12356
12357 case R_ARM_LDR_PC_G2:
12358 case R_ARM_LDR_SB_G2:
12359 group = 2;
12360 break;
12361
12362 default:
12363 abort ();
12364 }
12365
12366 /* If REL, extract the addend from the insn. If RELA, it will
12367 have already been fetched for us. */
4962c51a 12368 if (globals->use_rel)
99059e56
RM		 12369 {
12370 int negative = (insn & (1 << 23)) ? 1 : -1;
12371 signed_addend = negative * (insn & 0xfff);
12372 }
4962c51a
MS		 12373
12374 /* Compute the value (X) to go in the place. */
99059e56
RM		 12375 if (r_type == R_ARM_LDR_PC_G0
12376 || r_type == R_ARM_LDR_PC_G1
12377 || r_type == R_ARM_LDR_PC_G2)
12378 /* PC relative. */
12379 signed_value = value - pc + signed_addend;
12380 else
12381 /* Section base relative. */
12382 signed_value = value - sb + signed_addend;
12383
12384 /* Calculate the value of the relevant G_{n-1} to obtain
12385 the residual at that stage. */
b6518b38
NC		 12386 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12387 group - 1, &residual);
99059e56
RM		 12388
12389 /* Check for overflow. */
12390 if (residual >= 0x1000)
12391 {
4eca0228 12392 _bfd_error_handler
695344c0 12393 /* xgettext:c-format */
90b6238f 12394 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12395 "splitting %#" PRIx64 " for group relocation %s"),
12396 input_bfd, input_section, (uint64_t) rel->r_offset,
12397 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12398 howto->name);
99059e56
RM		 12399 return bfd_reloc_overflow;
12400 }
12401
12402 /* Mask out the value and U bit. */
12403 insn &= 0xff7ff000;
12404
12405 /* Set the U bit if the value to go in the place is non-negative. */
12406 if (signed_value >= 0)
12407 insn |= 1 << 23;
12408
12409 /* Encode the offset. */
12410 insn |= residual;
4962c51a
MS		 12411
12412 bfd_put_32 (input_bfd, insn, hit_data);
12413 }
12414 return bfd_reloc_ok;
12415
12416 case R_ARM_LDRS_PC_G0:
12417 case R_ARM_LDRS_PC_G1:
12418 case R_ARM_LDRS_PC_G2:
12419 case R_ARM_LDRS_SB_G0:
12420 case R_ARM_LDRS_SB_G1:
12421 case R_ARM_LDRS_SB_G2:
12422 {
12423 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12424 bfd_vma pc = input_section->output_section->vma
4962c51a 12425 + input_section->output_offset + rel->r_offset;
31a91d61 12426 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12427 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12428 bfd_vma residual;
4962c51a 12429 bfd_signed_vma signed_value;
99059e56
RM		 12430 int group = 0;
12431
12432 /* Determine which groups of bits to calculate. */
12433 switch (r_type)
12434 {
12435 case R_ARM_LDRS_PC_G0:
12436 case R_ARM_LDRS_SB_G0:
12437 group = 0;
12438 break;
12439
12440 case R_ARM_LDRS_PC_G1:
12441 case R_ARM_LDRS_SB_G1:
12442 group = 1;
12443 break;
12444
12445 case R_ARM_LDRS_PC_G2:
12446 case R_ARM_LDRS_SB_G2:
12447 group = 2;
12448 break;
12449
12450 default:
12451 abort ();
12452 }
12453
12454 /* If REL, extract the addend from the insn. If RELA, it will
12455 have already been fetched for us. */
4962c51a 12456 if (globals->use_rel)
99059e56
RM		 12457 {
12458 int negative = (insn & (1 << 23)) ? 1 : -1;
12459 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12460 }
4962c51a
MS		 12461
12462 /* Compute the value (X) to go in the place. */
99059e56
RM		 12463 if (r_type == R_ARM_LDRS_PC_G0
12464 || r_type == R_ARM_LDRS_PC_G1
12465 || r_type == R_ARM_LDRS_PC_G2)
12466 /* PC relative. */
12467 signed_value = value - pc + signed_addend;
12468 else
12469 /* Section base relative. */
12470 signed_value = value - sb + signed_addend;
12471
12472 /* Calculate the value of the relevant G_{n-1} to obtain
12473 the residual at that stage. */
b6518b38
NC		 12474 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12475 group - 1, &residual);
99059e56
RM		 12476
12477 /* Check for overflow. */
12478 if (residual >= 0x100)
12479 {
4eca0228 12480 _bfd_error_handler
695344c0 12481 /* xgettext:c-format */
90b6238f 12482 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12483 "splitting %#" PRIx64 " for group relocation %s"),
12484 input_bfd, input_section, (uint64_t) rel->r_offset,
12485 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12486 howto->name);
99059e56
RM		 12487 return bfd_reloc_overflow;
12488 }
12489
12490 /* Mask out the value and U bit. */
12491 insn &= 0xff7ff0f0;
12492
12493 /* Set the U bit if the value to go in the place is non-negative. */
12494 if (signed_value >= 0)
12495 insn |= 1 << 23;
12496
12497 /* Encode the offset. */
12498 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12499
12500 bfd_put_32 (input_bfd, insn, hit_data);
12501 }
12502 return bfd_reloc_ok;
12503
12504 case R_ARM_LDC_PC_G0:
12505 case R_ARM_LDC_PC_G1:
12506 case R_ARM_LDC_PC_G2:
12507 case R_ARM_LDC_SB_G0:
12508 case R_ARM_LDC_SB_G1:
12509 case R_ARM_LDC_SB_G2:
12510 {
12511 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12512 bfd_vma pc = input_section->output_section->vma
4962c51a 12513 + input_section->output_offset + rel->r_offset;
31a91d61 12514 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12515 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12516 bfd_vma residual;
4962c51a 12517 bfd_signed_vma signed_value;
99059e56
RM		 12518 int group = 0;
12519
12520 /* Determine which groups of bits to calculate. */
12521 switch (r_type)
12522 {
12523 case R_ARM_LDC_PC_G0:
12524 case R_ARM_LDC_SB_G0:
12525 group = 0;
12526 break;
12527
12528 case R_ARM_LDC_PC_G1:
12529 case R_ARM_LDC_SB_G1:
12530 group = 1;
12531 break;
12532
12533 case R_ARM_LDC_PC_G2:
12534 case R_ARM_LDC_SB_G2:
12535 group = 2;
12536 break;
12537
12538 default:
12539 abort ();
12540 }
12541
12542 /* If REL, extract the addend from the insn. If RELA, it will
12543 have already been fetched for us. */
4962c51a 12544 if (globals->use_rel)
99059e56
RM		 12545 {
12546 int negative = (insn & (1 << 23)) ? 1 : -1;
12547 signed_addend = negative * ((insn & 0xff) << 2);
12548 }
4962c51a
MS		 12549
12550 /* Compute the value (X) to go in the place. */
99059e56
RM		 12551 if (r_type == R_ARM_LDC_PC_G0
12552 || r_type == R_ARM_LDC_PC_G1
12553 || r_type == R_ARM_LDC_PC_G2)
12554 /* PC relative. */
12555 signed_value = value - pc + signed_addend;
12556 else
12557 /* Section base relative. */
12558 signed_value = value - sb + signed_addend;
12559
12560 /* Calculate the value of the relevant G_{n-1} to obtain
12561 the residual at that stage. */
b6518b38
NC		 12562 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12563 group - 1, &residual);
99059e56
RM		 12564
12565 /* Check for overflow. (The absolute value to go in the place must be
12566 divisible by four and, after having been divided by four, must
12567 fit in eight bits.) */
12568 if ((residual & 0x3) != 0 || residual >= 0x400)
12569 {
4eca0228 12570 _bfd_error_handler
695344c0 12571 /* xgettext:c-format */
90b6238f 12572 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12573 "splitting %#" PRIx64 " for group relocation %s"),
12574 input_bfd, input_section, (uint64_t) rel->r_offset,
12575 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12576 howto->name);
99059e56
RM		 12577 return bfd_reloc_overflow;
12578 }
12579
12580 /* Mask out the value and U bit. */
12581 insn &= 0xff7fff00;
12582
12583 /* Set the U bit if the value to go in the place is non-negative. */
12584 if (signed_value >= 0)
12585 insn |= 1 << 23;
12586
12587 /* Encode the offset. */
12588 insn |= residual >> 2;
4962c51a
MS		 12589
12590 bfd_put_32 (input_bfd, insn, hit_data);
12591 }
12592 return bfd_reloc_ok;
12593
72d98d16
MG		 12594 case R_ARM_THM_ALU_ABS_G0_NC:
12595 case R_ARM_THM_ALU_ABS_G1_NC:
12596 case R_ARM_THM_ALU_ABS_G2_NC:
12597 case R_ARM_THM_ALU_ABS_G3_NC:
12598 {
12599 const int shift_array[4] = {0, 8, 16, 24};
12600 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12601 bfd_vma addr = value;
12602 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12603
12604 /* Compute address. */
12605 if (globals->use_rel)
12606 signed_addend = insn & 0xff;
12607 addr += signed_addend;
12608 if (branch_type == ST_BRANCH_TO_THUMB)
12609 addr |= 1;
12610 /* Clean imm8 insn. */
12611 insn &= 0xff00;
12612 /* And update with correct part of address. */
12613 insn |= (addr >> shift) & 0xff;
12614 /* Update insn. */
12615 bfd_put_16 (input_bfd, insn, hit_data);
12616 }
12617
12618 *unresolved_reloc_p = FALSE;
12619 return bfd_reloc_ok;
12620
e8b09b87
CL		 12621 case R_ARM_GOTOFFFUNCDESC:
12622 {
12623 if (h == NULL)
12624 {
12625 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12626 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12627 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12628 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12629 bfd_vma seg = -1;
12630
12631 if (bfd_link_pic(info) && dynindx == 0)
12632 abort();
12633
12634 /* Resolve relocation. */
12635 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12636 , contents + rel->r_offset);
12637 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12638 not done yet. */
12639 arm_elf_fill_funcdesc(output_bfd, info,
12640 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12641 dynindx, offset, addr, dynreloc_value, seg);
12642 }
12643 else
12644 {
12645 int dynindx;
12646 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12647 bfd_vma addr;
12648 bfd_vma seg = -1;
12649
12650 /* For static binaries, sym_sec can be null. */
12651 if (sym_sec)
12652 {
12653 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12654 addr = dynreloc_value - sym_sec->output_section->vma;
12655 }
12656 else
12657 {
12658 dynindx = 0;
12659 addr = 0;
12660 }
12661
12662 if (bfd_link_pic(info) && dynindx == 0)
12663 abort();
12664
12665 /* This case cannot occur since funcdesc is allocated by
12666 the dynamic loader so we cannot resolve the relocation. */
12667 if (h->dynindx != -1)
12668 abort();
12669
12670 /* Resolve relocation. */
12671 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12672 contents + rel->r_offset);
12673 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12674 arm_elf_fill_funcdesc(output_bfd, info,
12675 &eh->fdpic_cnts.funcdesc_offset,
12676 dynindx, offset, addr, dynreloc_value, seg);
12677 }
12678 }
12679 *unresolved_reloc_p = FALSE;
12680 return bfd_reloc_ok;
12681
12682 case R_ARM_GOTFUNCDESC:
12683 {
12684 if (h != NULL)
12685 {
12686 Elf_Internal_Rela outrel;
12687
12688 /* Resolve relocation. */
12689 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12690 + sgot->output_offset),
12691 contents + rel->r_offset);
12692 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12693 if(h->dynindx == -1)
12694 {
12695 int dynindx;
12696 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12697 bfd_vma addr;
12698 bfd_vma seg = -1;
12699
12700 /* For static binaries sym_sec can be null. */
12701 if (sym_sec)
12702 {
12703 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12704 addr = dynreloc_value - sym_sec->output_section->vma;
12705 }
12706 else
12707 {
12708 dynindx = 0;
12709 addr = 0;
12710 }
12711
12712 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12713 arm_elf_fill_funcdesc(output_bfd, info,
12714 &eh->fdpic_cnts.funcdesc_offset,
12715 dynindx, offset, addr, dynreloc_value, seg);
12716 }
12717
12718 /* Add a dynamic relocation on GOT entry if not already done. */
12719 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12720 {
12721 if (h->dynindx == -1)
12722 {
12723 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12724 if (h->root.type == bfd_link_hash_undefweak)
12725 bfd_put_32(output_bfd, 0, sgot->contents
12726 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12727 else
12728 bfd_put_32(output_bfd, sgot->output_section->vma
12729 + sgot->output_offset
12730 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12731 sgot->contents
12732 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12733 }
12734 else
12735 {
12736 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12737 }
12738 outrel.r_offset = sgot->output_section->vma
12739 + sgot->output_offset
12740 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12741 outrel.r_addend = 0;
12742 if (h->dynindx == -1 && !bfd_link_pic(info))
12743 if (h->root.type == bfd_link_hash_undefweak)
12744 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
12745 else
12746 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12747 else
12748 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12749 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12750 }
12751 }
12752 else
12753 {
12754 /* Such relocation on static function should not have been
12755 emitted by the compiler. */
12756 abort();
12757 }
12758 }
12759 *unresolved_reloc_p = FALSE;
12760 return bfd_reloc_ok;
12761
12762 case R_ARM_FUNCDESC:
12763 {
12764 if (h == NULL)
12765 {
12766 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12767 Elf_Internal_Rela outrel;
12768 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12769 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12770 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12771 bfd_vma seg = -1;
12772
12773 if (bfd_link_pic(info) && dynindx == 0)
12774 abort();
12775
12776 /* Replace static FUNCDESC relocation with a
12777 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12778 executable. */
12779 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12780 outrel.r_offset = input_section->output_section->vma
12781 + input_section->output_offset + rel->r_offset;
12782 outrel.r_addend = 0;
12783 if (bfd_link_pic(info))
12784 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12785 else
12786 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12787
12788 bfd_put_32 (input_bfd, sgot->output_section->vma
12789 + sgot->output_offset + offset, hit_data);
12790
12791 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12792 arm_elf_fill_funcdesc(output_bfd, info,
12793 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12794 dynindx, offset, addr, dynreloc_value, seg);
12795 }
12796 else
12797 {
12798 if (h->dynindx == -1)
12799 {
12800 int dynindx;
12801 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12802 bfd_vma addr;
12803 bfd_vma seg = -1;
12804 Elf_Internal_Rela outrel;
12805
12806 /* For static binaries sym_sec can be null. */
12807 if (sym_sec)
12808 {
12809 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12810 addr = dynreloc_value - sym_sec->output_section->vma;
12811 }
12812 else
12813 {
12814 dynindx = 0;
12815 addr = 0;
12816 }
12817
12818 if (bfd_link_pic(info) && dynindx == 0)
12819 abort();
12820
12821 /* Replace static FUNCDESC relocation with a
12822 R_ARM_RELATIVE dynamic relocation. */
12823 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12824 outrel.r_offset = input_section->output_section->vma
12825 + input_section->output_offset + rel->r_offset;
12826 outrel.r_addend = 0;
12827 if (bfd_link_pic(info))
12828 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12829 else
12830 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12831
12832 bfd_put_32 (input_bfd, sgot->output_section->vma
12833 + sgot->output_offset + offset, hit_data);
12834
12835 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12836 arm_elf_fill_funcdesc(output_bfd, info,
12837 &eh->fdpic_cnts.funcdesc_offset,
12838 dynindx, offset, addr, dynreloc_value, seg);
12839 }
12840 else
12841 {
12842 Elf_Internal_Rela outrel;
12843
12844 /* Add a dynamic relocation. */
12845 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12846 outrel.r_offset = input_section->output_section->vma
12847 + input_section->output_offset + rel->r_offset;
12848 outrel.r_addend = 0;
12849 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12850 }
12851 }
12852 }
12853 *unresolved_reloc_p = FALSE;
12854 return bfd_reloc_ok;
12855
252b5132
RH		 12856 default:
12857 return bfd_reloc_notsupported;
12858 }
12859}
12860
98c1d4aa
NC		 12861/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12862static void
07d6d2b8
AM		 12863arm_add_to_rel (bfd * abfd,
12864 bfd_byte * address,
57e8b36a 12865 reloc_howto_type * howto,
07d6d2b8 12866 bfd_signed_vma increment)
98c1d4aa 12867{
98c1d4aa
NC		 12868 bfd_signed_vma addend;
12869
bd97cb95
DJ		 12870 if (howto->type == R_ARM_THM_CALL
12871 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12872 {
9a5aca8c
AM		 12873 int upper_insn, lower_insn;
12874 int upper, lower;
98c1d4aa 12875
9a5aca8c
AM		 12876 upper_insn = bfd_get_16 (abfd, address);
12877 lower_insn = bfd_get_16 (abfd, address + 2);
12878 upper = upper_insn & 0x7ff;
12879 lower = lower_insn & 0x7ff;
12880
12881 addend = (upper << 12) | (lower << 1);
ddda4409 12882 addend += increment;
9a5aca8c 12883 addend >>= 1;
98c1d4aa 12884
9a5aca8c
AM		 12885 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12886 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12887
dc810e39
AM		 12888 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12889 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12890 }
12891 else
12892 {
07d6d2b8 12893 bfd_vma contents;
9a5aca8c
AM		 12894
12895 contents = bfd_get_32 (abfd, address);
12896
12897 /* Get the (signed) value from the instruction. */
12898 addend = contents & howto->src_mask;
12899 if (addend & ((howto->src_mask + 1) >> 1))
12900 {
12901 bfd_signed_vma mask;
12902
12903 mask = -1;
12904 mask &= ~ howto->src_mask;
12905 addend |= mask;
12906 }
12907
12908 /* Add in the increment, (which is a byte value). */
12909 switch (howto->type)
12910 {
12911 default:
12912 addend += increment;
12913 break;
12914
12915 case R_ARM_PC24:
c6596c5e 12916 case R_ARM_PLT32:
5b5bb741
PB		 12917 case R_ARM_CALL:
12918 case R_ARM_JUMP24:
9a5aca8c 12919 addend <<= howto->size;
dc810e39 12920 addend += increment;
9a5aca8c
AM		 12921
12922 /* Should we check for overflow here ? */
12923
12924 /* Drop any undesired bits. */
12925 addend >>= howto->rightshift;
12926 break;
12927 }
12928
12929 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12930
12931 bfd_put_32 (abfd, contents, address);
ddda4409 12932 }
98c1d4aa 12933}
252b5132 12934
ba93b8ac
DJ		 12935#define IS_ARM_TLS_RELOC(R_TYPE) \
12936 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 12937 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 12938 || (R_TYPE) == R_ARM_TLS_LDO32 \
12939 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 12940 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 12941 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12942 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12943 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12944 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 12945 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 12946 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 12947 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12948
12949/* Specific set of relocations for the gnu tls dialect. */
12950#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12951 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12952 || (R_TYPE) == R_ARM_TLS_CALL \
12953 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12954 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12955 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12956
252b5132 12957/* Relocate an ARM ELF section. */
906e58ca 12958
b34976b6 12959static bfd_boolean
07d6d2b8 12960elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 12961 struct bfd_link_info * info,
07d6d2b8
AM		 12962 bfd * input_bfd,
12963 asection * input_section,
12964 bfd_byte * contents,
12965 Elf_Internal_Rela * relocs,
12966 Elf_Internal_Sym * local_syms,
12967 asection ** local_sections)
252b5132 12968{
b34976b6
AM		 12969 Elf_Internal_Shdr *symtab_hdr;
12970 struct elf_link_hash_entry **sym_hashes;
12971 Elf_Internal_Rela *rel;
12972 Elf_Internal_Rela *relend;
12973 const char *name;
b32d3aa2 12974 struct elf32_arm_link_hash_table * globals;
252b5132 12975
4e7fd91e 12976 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12977 if (globals == NULL)
12978 return FALSE;
b491616a 12979
0ffa91dd 12980 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12981 sym_hashes = elf_sym_hashes (input_bfd);
12982
12983 rel = relocs;
12984 relend = relocs + input_section->reloc_count;
12985 for (; rel < relend; rel++)
12986 {
07d6d2b8
AM		 12987 int r_type;
12988 reloc_howto_type * howto;
12989 unsigned long r_symndx;
12990 Elf_Internal_Sym * sym;
12991 asection * sec;
252b5132 12992 struct elf_link_hash_entry * h;
07d6d2b8
AM		 12993 bfd_vma relocation;
12994 bfd_reloc_status_type r;
12995 arelent bfd_reloc;
12996 char sym_type;
12997 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12998 char *error_message = NULL;
f21f3fe0 12999
252b5132 13000 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13001 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13002 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13003
ba96a88f 13004 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13005 || r_type == R_ARM_GNU_VTINHERIT)
13006 continue;
252b5132 13007
47aeb64c
NC		 13008 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13009
13010 if (howto == NULL)
13011 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13012
252b5132
RH		 13013 h = NULL;
13014 sym = NULL;
13015 sec = NULL;
9b485d32 13016
252b5132
RH		 13017 if (r_symndx < symtab_hdr->sh_info)
13018 {
13019 sym = local_syms + r_symndx;
ba93b8ac 13020 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13021 sec = local_sections[r_symndx];
ffcb4889
NS		 13022
13023 /* An object file might have a reference to a local
13024 undefined symbol. This is a daft object file, but we
13025 should at least do something about it. V4BX & NONE
13026 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13027 allowed to use the undefined symbol, so allow those.
13028 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13029 if (r_type != R_ARM_V4BX
13030 && r_type != R_ARM_NONE
77b4f08f 13031 && r_symndx != STN_UNDEF
ffcb4889
NS		 13032 && bfd_is_und_section (sec)
13033 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13034 (*info->callbacks->undefined_symbol)
13035 (info, bfd_elf_string_from_elf_section
13036 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13037 input_bfd, input_section,
13038 rel->r_offset, TRUE);
b38cadfb 13039
4e7fd91e 13040 if (globals->use_rel)
f8df10f4 13041 {
4e7fd91e
PB		 13042 relocation = (sec->output_section->vma
13043 + sec->output_offset
13044 + sym->st_value);
0e1862bb 13045 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13046 && (sec->flags & SEC_MERGE)
13047 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13048 {
4e7fd91e
PB		 13049 asection *msec;
13050 bfd_vma addend, value;
13051
39623e12 13052 switch (r_type)
4e7fd91e 13053 {
39623e12
PB		 13054 case R_ARM_MOVW_ABS_NC:
13055 case R_ARM_MOVT_ABS:
13056 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13057 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13058 addend = (addend ^ 0x8000) - 0x8000;
13059 break;
f8df10f4 13060
39623e12
PB		 13061 case R_ARM_THM_MOVW_ABS_NC:
13062 case R_ARM_THM_MOVT_ABS:
13063 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13064 << 16;
13065 value |= bfd_get_16 (input_bfd,
13066 contents + rel->r_offset + 2);
13067 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13068 | ((value & 0x04000000) >> 15);
13069 addend = (addend ^ 0x8000) - 0x8000;
13070 break;
f8df10f4 13071
39623e12
PB		 13072 default:
13073 if (howto->rightshift
13074 || (howto->src_mask & (howto->src_mask + 1)))
13075 {
4eca0228 13076 _bfd_error_handler
695344c0 13077 /* xgettext:c-format */
2dcf00ce
AM		 13078 (_("%pB(%pA+%#" PRIx64 "): "
13079 "%s relocation against SEC_MERGE section"),
39623e12 13080 input_bfd, input_section,
2dcf00ce 13081 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13082 return FALSE;
13083 }
13084
13085 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13086
13087 /* Get the (signed) value from the instruction. */
13088 addend = value & howto->src_mask;
13089 if (addend & ((howto->src_mask + 1) >> 1))
13090 {
13091 bfd_signed_vma mask;
13092
13093 mask = -1;
13094 mask &= ~ howto->src_mask;
13095 addend |= mask;
13096 }
13097 break;
4e7fd91e 13098 }
39623e12 13099
4e7fd91e
PB		 13100 msec = sec;
13101 addend =
13102 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13103 - relocation;
13104 addend += msec->output_section->vma + msec->output_offset;
39623e12 13105
cc643b88 13106 /* Cases here must match those in the preceding
39623e12
PB		 13107 switch statement. */
13108 switch (r_type)
13109 {
13110 case R_ARM_MOVW_ABS_NC:
13111 case R_ARM_MOVT_ABS:
13112 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13113 | (addend & 0xfff);
13114 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13115 break;
13116
13117 case R_ARM_THM_MOVW_ABS_NC:
13118 case R_ARM_THM_MOVT_ABS:
13119 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13120 | (addend & 0xff) | ((addend & 0x0800) << 15);
13121 bfd_put_16 (input_bfd, value >> 16,
13122 contents + rel->r_offset);
13123 bfd_put_16 (input_bfd, value,
13124 contents + rel->r_offset + 2);
13125 break;
13126
13127 default:
13128 value = (value & ~ howto->dst_mask)
13129 | (addend & howto->dst_mask);
13130 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13131 break;
13132 }
f8df10f4 13133 }
f8df10f4 13134 }
4e7fd91e
PB		 13135 else
13136 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13137 }
13138 else
13139 {
62d887d4 13140 bfd_boolean warned, ignored;
560e09e9 13141
b2a8e766
AM		 13142 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13143 r_symndx, symtab_hdr, sym_hashes,
13144 h, sec, relocation,
62d887d4 13145 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13146
13147 sym_type = h->type;
252b5132
RH		 13148 }
13149
dbaa2011 13150 if (sec != NULL && discarded_section (sec))
e4067dbb 13151 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13152 rel, 1, relend, howto, 0, contents);
ab96bf03 13153
0e1862bb 13154 if (bfd_link_relocatable (info))
ab96bf03
AM		 13155 {
13156 /* This is a relocatable link. We don't have to change
13157 anything, unless the reloc is against a section symbol,
13158 in which case we have to adjust according to where the
13159 section symbol winds up in the output section. */
13160 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13161 {
13162 if (globals->use_rel)
13163 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13164 howto, (bfd_signed_vma) sec->output_offset);
13165 else
13166 rel->r_addend += sec->output_offset;
13167 }
13168 continue;
13169 }
13170
252b5132
RH		 13171 if (h != NULL)
13172 name = h->root.root.string;
13173 else
13174 {
13175 name = (bfd_elf_string_from_elf_section
13176 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13177 if (name == NULL || *name == '\0')
13178 name = bfd_section_name (input_bfd, sec);
13179 }
f21f3fe0 13180
cf35638d 13181 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13182 && r_type != R_ARM_NONE
13183 && (h == NULL
13184 || h->root.type == bfd_link_hash_defined
13185 || h->root.type == bfd_link_hash_defweak)
13186 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13187 {
4eca0228 13188 _bfd_error_handler
ba93b8ac 13189 ((sym_type == STT_TLS
695344c0 13190 /* xgettext:c-format */
2dcf00ce 13191 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13192 /* xgettext:c-format */
2dcf00ce 13193 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13194 input_bfd,
13195 input_section,
2dcf00ce 13196 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13197 howto->name,
13198 name);
13199 }
13200
0855e32b 13201 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13202 done, i.e., the relaxation produced the final output we want,
13203 and we won't let anybody mess with it. Also, we have to do
13204 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13205 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13206 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13207 || (IS_ARM_TLS_GNU_RELOC (r_type)
13208 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13209 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13210 & GOT_TLS_GDESC)))
13211 {
13212 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13213 contents, rel, h == NULL);
13214 /* This may have been marked unresolved because it came from
13215 a shared library. But we've just dealt with that. */
13216 unresolved_reloc = 0;
13217 }
13218 else
13219 r = bfd_reloc_continue;
b38cadfb 13220
39d911fc
TP		 13221 if (r == bfd_reloc_continue)
13222 {
13223 unsigned char branch_type =
13224 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13225 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13226
13227 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13228 input_section, contents, rel,
13229 relocation, info, sec, name,
13230 sym_type, branch_type, h,
13231 &unresolved_reloc,
13232 &error_message);
13233 }
0945cdfd
DJ		 13234
13235 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13236 because such sections are not SEC_ALLOC and thus ld.so will
13237 not process them. */
13238 if (unresolved_reloc
99059e56
RM		 13239 && !((input_section->flags & SEC_DEBUGGING) != 0
13240 && h->def_dynamic)
1d5316ab
AM		 13241 && _bfd_elf_section_offset (output_bfd, info, input_section,
13242 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13243 {
4eca0228 13244 _bfd_error_handler
695344c0 13245 /* xgettext:c-format */
2dcf00ce
AM		 13246 (_("%pB(%pA+%#" PRIx64 "): "
13247 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13248 input_bfd,
13249 input_section,
2dcf00ce 13250 (uint64_t) rel->r_offset,
843fe662
L		 13251 howto->name,
13252 h->root.root.string);
0945cdfd
DJ		 13253 return FALSE;
13254 }
252b5132
RH		 13255
13256 if (r != bfd_reloc_ok)
13257 {
252b5132
RH		 13258 switch (r)
13259 {
13260 case bfd_reloc_overflow:
cf919dfd
PB		 13261 /* If the overflowing reloc was to an undefined symbol,
13262 we have already printed one error message and there
13263 is no point complaining again. */
1a72702b
AM		 13264 if (!h || h->root.type != bfd_link_hash_undefined)
13265 (*info->callbacks->reloc_overflow)
13266 (info, (h ? &h->root : NULL), name, howto->name,
13267 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13268 break;
13269
13270 case bfd_reloc_undefined:
1a72702b
AM		 13271 (*info->callbacks->undefined_symbol)
13272 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13273 break;
13274
13275 case bfd_reloc_outofrange:
f2a9dd69 13276 error_message = _("out of range");
252b5132
RH		 13277 goto common_error;
13278
13279 case bfd_reloc_notsupported:
f2a9dd69 13280 error_message = _("unsupported relocation");
252b5132
RH		 13281 goto common_error;
13282
13283 case bfd_reloc_dangerous:
f2a9dd69 13284 /* error_message should already be set. */
252b5132
RH		 13285 goto common_error;
13286
13287 default:
f2a9dd69 13288 error_message = _("unknown error");
8029a119 13289 /* Fall through. */
252b5132
RH		 13290
13291 common_error:
f2a9dd69 13292 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13293 (*info->callbacks->reloc_dangerous)
13294 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13295 break;
13296 }
13297 }
13298 }
13299
b34976b6 13300 return TRUE;
252b5132
RH		 13301}
13302
91d6fa6a 13303/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13304 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13305 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13306 maintaining that condition). */
13307
13308static void
13309add_unwind_table_edit (arm_unwind_table_edit **head,
13310 arm_unwind_table_edit **tail,
13311 arm_unwind_edit_type type,
13312 asection *linked_section,
91d6fa6a 13313 unsigned int tindex)
2468f9c9 13314{
21d799b5
NC		 13315 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13316 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13317
2468f9c9
PB		 13318 new_edit->type = type;
13319 new_edit->linked_section = linked_section;
91d6fa6a 13320 new_edit->index = tindex;
b38cadfb 13321
91d6fa6a 13322 if (tindex > 0)
2468f9c9
PB		 13323 {
13324 new_edit->next = NULL;
13325
13326 if (*tail)
13327 (*tail)->next = new_edit;
13328
13329 (*tail) = new_edit;
13330
13331 if (!*head)
13332 (*head) = new_edit;
13333 }
13334 else
13335 {
13336 new_edit->next = *head;
13337
13338 if (!*tail)
13339 *tail = new_edit;
13340
13341 *head = new_edit;
13342 }
13343}
13344
13345static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13346
13347/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13348static void
13349adjust_exidx_size(asection *exidx_sec, int adjust)
13350{
13351 asection *out_sec;
13352
13353 if (!exidx_sec->rawsize)
13354 exidx_sec->rawsize = exidx_sec->size;
13355
13356 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
13357 out_sec = exidx_sec->output_section;
13358 /* Adjust size of output section. */
13359 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
13360}
13361
13362/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13363static void
13364insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13365{
13366 struct _arm_elf_section_data *exidx_arm_data;
13367
13368 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13369 add_unwind_table_edit (
13370 &exidx_arm_data->u.exidx.unwind_edit_list,
13371 &exidx_arm_data->u.exidx.unwind_edit_tail,
13372 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13373
491d01d3
YU		 13374 exidx_arm_data->additional_reloc_count++;
13375
2468f9c9
PB		 13376 adjust_exidx_size(exidx_sec, 8);
13377}
13378
13379/* Scan .ARM.exidx tables, and create a list describing edits which should be
13380 made to those tables, such that:
b38cadfb 13381
2468f9c9
PB		 13382 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13383 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13384 codes which have been inlined into the index).
2468f9c9 13385
85fdf906
AH		 13386 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13387
2468f9c9 13388 The edits are applied when the tables are written
b38cadfb 13389 (in elf32_arm_write_section). */
2468f9c9
PB		 13390
13391bfd_boolean
13392elf32_arm_fix_exidx_coverage (asection **text_section_order,
13393 unsigned int num_text_sections,
85fdf906
AH		 13394 struct bfd_link_info *info,
13395 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13396{
13397 bfd *inp;
13398 unsigned int last_second_word = 0, i;
13399 asection *last_exidx_sec = NULL;
13400 asection *last_text_sec = NULL;
13401 int last_unwind_type = -1;
13402
13403 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13404 text sections. */
c72f2fb2 13405 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13406 {
13407 asection *sec;
b38cadfb 13408
2468f9c9 13409 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13410 {
2468f9c9
PB		 13411 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13412 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13413
dec9d5df 13414 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13415 continue;
b38cadfb 13416
2468f9c9
PB		 13417 if (elf_sec->linked_to)
13418 {
13419 Elf_Internal_Shdr *linked_hdr
99059e56 13420 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13421 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13422 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13423
13424 if (linked_sec_arm_data == NULL)
99059e56 13425 continue;
2468f9c9
PB		 13426
13427 /* Link this .ARM.exidx section back from the text section it
99059e56 13428 describes. */
2468f9c9
PB		 13429 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13430 }
13431 }
13432 }
13433
13434 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13435 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13436 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13437
13438 for (i = 0; i < num_text_sections; i++)
13439 {
13440 asection *sec = text_section_order[i];
13441 asection *exidx_sec;
13442 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13443 struct _arm_elf_section_data *exidx_arm_data;
13444 bfd_byte *contents = NULL;
13445 int deleted_exidx_bytes = 0;
13446 bfd_vma j;
13447 arm_unwind_table_edit *unwind_edit_head = NULL;
13448 arm_unwind_table_edit *unwind_edit_tail = NULL;
13449 Elf_Internal_Shdr *hdr;
13450 bfd *ibfd;
13451
13452 if (arm_data == NULL)
99059e56 13453 continue;
2468f9c9
PB		 13454
13455 exidx_sec = arm_data->u.text.arm_exidx_sec;
13456 if (exidx_sec == NULL)
13457 {
13458 /* Section has no unwind data. */
13459 if (last_unwind_type == 0 || !last_exidx_sec)
13460 continue;
13461
13462 /* Ignore zero sized sections. */
13463 if (sec->size == 0)
13464 continue;
13465
13466 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13467 last_unwind_type = 0;
13468 continue;
13469 }
13470
22a8f80e
PB		 13471 /* Skip /DISCARD/ sections. */
13472 if (bfd_is_abs_section (exidx_sec->output_section))
13473 continue;
13474
2468f9c9
PB		 13475 hdr = &elf_section_data (exidx_sec)->this_hdr;
13476 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13477 continue;
b38cadfb 13478
2468f9c9
PB		 13479 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13480 if (exidx_arm_data == NULL)
99059e56 13481 continue;
b38cadfb 13482
2468f9c9 13483 ibfd = exidx_sec->owner;
b38cadfb 13484
2468f9c9
PB		 13485 if (hdr->contents != NULL)
13486 contents = hdr->contents;
13487 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13488 /* An error? */
13489 continue;
13490
ac06903d
YU		 13491 if (last_unwind_type > 0)
13492 {
13493 unsigned int first_word = bfd_get_32 (ibfd, contents);
13494 /* Add cantunwind if first unwind item does not match section
13495 start. */
13496 if (first_word != sec->vma)
13497 {
13498 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13499 last_unwind_type = 0;
13500 }
13501 }
13502
2468f9c9
PB		 13503 for (j = 0; j < hdr->sh_size; j += 8)
13504 {
13505 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13506 int unwind_type;
13507 int elide = 0;
13508
13509 /* An EXIDX_CANTUNWIND entry. */
13510 if (second_word == 1)
13511 {
13512 if (last_unwind_type == 0)
13513 elide = 1;
13514 unwind_type = 0;
13515 }
13516 /* Inlined unwinding data. Merge if equal to previous. */
13517 else if ((second_word & 0x80000000) != 0)
13518 {
85fdf906
AH		 13519 if (merge_exidx_entries
13520 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13521 elide = 1;
13522 unwind_type = 1;
13523 last_second_word = second_word;
13524 }
13525 /* Normal table entry. In theory we could merge these too,
13526 but duplicate entries are likely to be much less common. */
13527 else
13528 unwind_type = 2;
13529
491d01d3 13530 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13531 {
13532 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13533 DELETE_EXIDX_ENTRY, NULL, j / 8);
13534
13535 deleted_exidx_bytes += 8;
13536 }
13537
13538 last_unwind_type = unwind_type;
13539 }
13540
13541 /* Free contents if we allocated it ourselves. */
13542 if (contents != hdr->contents)
99059e56 13543 free (contents);
2468f9c9
PB		 13544
13545 /* Record edits to be applied later (in elf32_arm_write_section). */
13546 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13547 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13548
2468f9c9
PB		 13549 if (deleted_exidx_bytes > 0)
13550 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13551
13552 last_exidx_sec = exidx_sec;
13553 last_text_sec = sec;
13554 }
13555
13556 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13557 if (!bfd_link_relocatable (info) && last_exidx_sec
13558 && last_unwind_type != 0)
2468f9c9
PB		 13559 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13560
13561 return TRUE;
13562}
13563
3e6b1042
DJ		 13564static bfd_boolean
13565elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13566 bfd *ibfd, const char *name)
13567{
13568 asection *sec, *osec;
13569
3d4d4302 13570 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13571 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13572 return TRUE;
13573
13574 osec = sec->output_section;
13575 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13576 return TRUE;
13577
13578 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13579 sec->output_offset, sec->size))
13580 return FALSE;
13581
13582 return TRUE;
13583}
13584
13585static bfd_boolean
13586elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13587{
13588 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13589 asection *sec, *osec;
3e6b1042 13590
4dfe6ac6
NC		 13591 if (globals == NULL)
13592 return FALSE;
13593
3e6b1042
DJ		 13594 /* Invoke the regular ELF backend linker to do all the work. */
13595 if (!bfd_elf_final_link (abfd, info))
13596 return FALSE;
13597
fe33d2fa
CL		 13598 /* Process stub sections (eg BE8 encoding, ...). */
13599 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13600 unsigned int i;
cdb21a0a
NS		 13601 for (i=0; i<htab->top_id; i++)
13602 {
13603 sec = htab->stub_group[i].stub_sec;
13604 /* Only process it once, in its link_sec slot. */
13605 if (sec && i == htab->stub_group[i].link_sec->id)
13606 {
13607 osec = sec->output_section;
13608 elf32_arm_write_section (abfd, info, sec, sec->contents);
13609 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13610 sec->output_offset, sec->size))
13611 return FALSE;
13612 }
fe33d2fa 13613 }
fe33d2fa 13614
3e6b1042
DJ		 13615 /* Write out any glue sections now that we have created all the
13616 stubs. */
13617 if (globals->bfd_of_glue_owner != NULL)
13618 {
13619 if (! elf32_arm_output_glue_section (info, abfd,
13620 globals->bfd_of_glue_owner,
13621 ARM2THUMB_GLUE_SECTION_NAME))
13622 return FALSE;
13623
13624 if (! elf32_arm_output_glue_section (info, abfd,
13625 globals->bfd_of_glue_owner,
13626 THUMB2ARM_GLUE_SECTION_NAME))
13627 return FALSE;
13628
13629 if (! elf32_arm_output_glue_section (info, abfd,
13630 globals->bfd_of_glue_owner,
13631 VFP11_ERRATUM_VENEER_SECTION_NAME))
13632 return FALSE;
13633
a504d23a
LA		 13634 if (! elf32_arm_output_glue_section (info, abfd,
13635 globals->bfd_of_glue_owner,
13636 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13637 return FALSE;
13638
3e6b1042
DJ		 13639 if (! elf32_arm_output_glue_section (info, abfd,
13640 globals->bfd_of_glue_owner,
13641 ARM_BX_GLUE_SECTION_NAME))
13642 return FALSE;
13643 }
13644
13645 return TRUE;
13646}
13647
5968a7b8
NC		 13648/* Return a best guess for the machine number based on the attributes. */
13649
13650static unsigned int
13651bfd_arm_get_mach_from_attributes (bfd * abfd)
13652{
13653 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13654
13655 switch (arch)
13656 {
c0c468d5 13657 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13658 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13659 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13660 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13661
13662 case TAG_CPU_ARCH_V5TE:
13663 {
13664 char * name;
13665
13666 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13667 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13668
13669 if (name)
13670 {
13671 if (strcmp (name, "IWMMXT2") == 0)
13672 return bfd_mach_arm_iWMMXt2;
13673
13674 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13675 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13676
13677 if (strcmp (name, "XSCALE") == 0)
13678 {
13679 int wmmx;
13680
13681 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13682 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13683 switch (wmmx)
13684 {
13685 case 1: return bfd_mach_arm_iWMMXt;
13686 case 2: return bfd_mach_arm_iWMMXt2;
13687 default: return bfd_mach_arm_XScale;
13688 }
13689 }
5968a7b8
NC		 13690 }
13691
13692 return bfd_mach_arm_5TE;
13693 }
13694
c0c468d5
TP		 13695 case TAG_CPU_ARCH_V5TEJ:
13696 return bfd_mach_arm_5TEJ;
13697 case TAG_CPU_ARCH_V6:
13698 return bfd_mach_arm_6;
13699 case TAG_CPU_ARCH_V6KZ:
13700 return bfd_mach_arm_6KZ;
13701 case TAG_CPU_ARCH_V6T2:
13702 return bfd_mach_arm_6T2;
13703 case TAG_CPU_ARCH_V6K:
13704 return bfd_mach_arm_6K;
13705 case TAG_CPU_ARCH_V7:
13706 return bfd_mach_arm_7;
13707 case TAG_CPU_ARCH_V6_M:
13708 return bfd_mach_arm_6M;
13709 case TAG_CPU_ARCH_V6S_M:
13710 return bfd_mach_arm_6SM;
13711 case TAG_CPU_ARCH_V7E_M:
13712 return bfd_mach_arm_7EM;
13713 case TAG_CPU_ARCH_V8:
13714 return bfd_mach_arm_8;
13715 case TAG_CPU_ARCH_V8R:
13716 return bfd_mach_arm_8R;
13717 case TAG_CPU_ARCH_V8M_BASE:
13718 return bfd_mach_arm_8M_BASE;
13719 case TAG_CPU_ARCH_V8M_MAIN:
13720 return bfd_mach_arm_8M_MAIN;
13721
5968a7b8 13722 default:
c0c468d5
TP		 13723 /* Force entry to be added for any new known Tag_CPU_arch value. */
13724 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13725
13726 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13727 return bfd_mach_arm_unknown;
13728 }
13729}
13730
c178919b
NC		 13731/* Set the right machine number. */
13732
13733static bfd_boolean
57e8b36a 13734elf32_arm_object_p (bfd *abfd)
c178919b 13735{
5a6c6817 13736 unsigned int mach;
57e8b36a 13737
5a6c6817 13738 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13739
5968a7b8
NC		 13740 if (mach == bfd_mach_arm_unknown)
13741 {
13742 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13743 mach = bfd_mach_arm_ep9312;
13744 else
13745 mach = bfd_arm_get_mach_from_attributes (abfd);
13746 }
c178919b 13747
5968a7b8 13748 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13749 return TRUE;
13750}
13751
fc830a83 13752/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13753
b34976b6 13754static bfd_boolean
57e8b36a 13755elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13756{
13757 if (elf_flags_init (abfd)
13758 && elf_elfheader (abfd)->e_flags != flags)
13759 {
fc830a83
NC		 13760 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13761 {
fd2ec330 13762 if (flags & EF_ARM_INTERWORK)
4eca0228 13763 _bfd_error_handler
90b6238f 13764 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13765 abfd);
fc830a83 13766 else
d003868e 13767 _bfd_error_handler
90b6238f 13768 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13769 abfd);
fc830a83 13770 }
252b5132
RH		 13771 }
13772 else
13773 {
13774 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13775 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13776 }
13777
b34976b6 13778 return TRUE;
252b5132
RH		 13779}
13780
fc830a83 13781/* Copy backend specific data from one object module to another. */
9b485d32 13782
b34976b6 13783static bfd_boolean
57e8b36a 13784elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13785{
13786 flagword in_flags;
13787 flagword out_flags;
13788
0ffa91dd 13789 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13790 return TRUE;
252b5132 13791
fc830a83 13792 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13793 out_flags = elf_elfheader (obfd)->e_flags;
13794
fc830a83
NC		 13795 if (elf_flags_init (obfd)
13796 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13797 && in_flags != out_flags)
252b5132 13798 {
252b5132 13799 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13800 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13801 return FALSE;
252b5132
RH		 13802
13803 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13804 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13805 return FALSE;
252b5132
RH		 13806
13807 /* If the src and dest have different interworking flags
99059e56 13808 then turn off the interworking bit. */
fd2ec330 13809 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13810 {
fd2ec330 13811 if (out_flags & EF_ARM_INTERWORK)
d003868e 13812 _bfd_error_handler
90b6238f 13813 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13814 obfd, ibfd);
252b5132 13815
fd2ec330 13816 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13817 }
1006ba19
PB		 13818
13819 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13820 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13821 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13822 }
13823
13824 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13825 elf_flags_init (obfd) = TRUE;
252b5132 13826
e2349352 13827 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13828}
13829
13830/* Values for Tag_ABI_PCS_R9_use. */
13831enum
13832{
13833 AEABI_R9_V6,
13834 AEABI_R9_SB,
13835 AEABI_R9_TLS,
13836 AEABI_R9_unused
13837};
13838
13839/* Values for Tag_ABI_PCS_RW_data. */
13840enum
13841{
13842 AEABI_PCS_RW_data_absolute,
13843 AEABI_PCS_RW_data_PCrel,
13844 AEABI_PCS_RW_data_SBrel,
13845 AEABI_PCS_RW_data_unused
13846};
13847
13848/* Values for Tag_ABI_enum_size. */
13849enum
13850{
13851 AEABI_enum_unused,
13852 AEABI_enum_short,
13853 AEABI_enum_wide,
13854 AEABI_enum_forced_wide
13855};
13856
104d59d1
JM		 13857/* Determine whether an object attribute tag takes an integer, a
13858 string or both. */
906e58ca 13859
104d59d1
JM		 13860static int
13861elf32_arm_obj_attrs_arg_type (int tag)
13862{
13863 if (tag == Tag_compatibility)
3483fe2e 13864 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13865 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13866 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13867 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13868 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13869 else if (tag < 32)
3483fe2e 13870 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13871 else
3483fe2e 13872 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13873}
13874
5aa6ff7c
AS		 13875/* The ABI defines that Tag_conformance should be emitted first, and that
13876 Tag_nodefaults should be second (if either is defined). This sets those
13877 two positions, and bumps up the position of all the remaining tags to
13878 compensate. */
13879static int
13880elf32_arm_obj_attrs_order (int num)
13881{
3de4a297 13882 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13883 return Tag_conformance;
3de4a297 13884 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13885 return Tag_nodefaults;
13886 if ((num - 2) < Tag_nodefaults)
13887 return num - 2;
13888 if ((num - 1) < Tag_conformance)
13889 return num - 1;
13890 return num;
13891}
13892
e8b36cd1
JM		 13893/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13894static bfd_boolean
13895elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13896{
13897 if ((tag & 127) < 64)
13898 {
13899 _bfd_error_handler
90b6238f 13900 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 13901 abfd, tag);
13902 bfd_set_error (bfd_error_bad_value);
13903 return FALSE;
13904 }
13905 else
13906 {
13907 _bfd_error_handler
90b6238f 13908 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 13909 abfd, tag);
13910 return TRUE;
13911 }
13912}
13913
91e22acd
AS		 13914/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13915 Returns -1 if no architecture could be read. */
13916
13917static int
13918get_secondary_compatible_arch (bfd *abfd)
13919{
13920 obj_attribute *attr =
13921 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13922
13923 /* Note: the tag and its argument below are uleb128 values, though
13924 currently-defined values fit in one byte for each. */
13925 if (attr->s
13926 && attr->s[0] == Tag_CPU_arch
13927 && (attr->s[1] & 128) != 128
13928 && attr->s[2] == 0)
13929 return attr->s[1];
13930
13931 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13932 return -1;
13933}
13934
13935/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13936 The tag is removed if ARCH is -1. */
13937
8e79c3df 13938static void
91e22acd 13939set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13940{
91e22acd
AS		 13941 obj_attribute *attr =
13942 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13943
91e22acd
AS		 13944 if (arch == -1)
13945 {
13946 attr->s = NULL;
13947 return;
8e79c3df 13948 }
91e22acd
AS		 13949
13950 /* Note: the tag and its argument below are uleb128 values, though
13951 currently-defined values fit in one byte for each. */
13952 if (!attr->s)
21d799b5 13953 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13954 attr->s[0] = Tag_CPU_arch;
13955 attr->s[1] = arch;
13956 attr->s[2] = '\0';
8e79c3df
CM		 13957}
13958
91e22acd
AS		 13959/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13960 into account. */
13961
13962static int
13963tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13964 int newtag, int secondary_compat)
8e79c3df 13965{
91e22acd
AS		 13966#define T(X) TAG_CPU_ARCH_##X
13967 int tagl, tagh, result;
13968 const int v6t2[] =
13969 {
13970 T(V6T2), /* PRE_V4. */
13971 T(V6T2), /* V4. */
13972 T(V6T2), /* V4T. */
13973 T(V6T2), /* V5T. */
13974 T(V6T2), /* V5TE. */
13975 T(V6T2), /* V5TEJ. */
13976 T(V6T2), /* V6. */
13977 T(V7), /* V6KZ. */
13978 T(V6T2) /* V6T2. */
13979 };
13980 const int v6k[] =
13981 {
13982 T(V6K), /* PRE_V4. */
13983 T(V6K), /* V4. */
13984 T(V6K), /* V4T. */
13985 T(V6K), /* V5T. */
13986 T(V6K), /* V5TE. */
13987 T(V6K), /* V5TEJ. */
13988 T(V6K), /* V6. */
13989 T(V6KZ), /* V6KZ. */
13990 T(V7), /* V6T2. */
13991 T(V6K) /* V6K. */
13992 };
13993 const int v7[] =
13994 {
13995 T(V7), /* PRE_V4. */
13996 T(V7), /* V4. */
13997 T(V7), /* V4T. */
13998 T(V7), /* V5T. */
13999 T(V7), /* V5TE. */
14000 T(V7), /* V5TEJ. */
14001 T(V7), /* V6. */
14002 T(V7), /* V6KZ. */
14003 T(V7), /* V6T2. */
14004 T(V7), /* V6K. */
14005 T(V7) /* V7. */
14006 };
14007 const int v6_m[] =
14008 {
07d6d2b8
AM		 14009 -1, /* PRE_V4. */
14010 -1, /* V4. */
91e22acd
AS		 14011 T(V6K), /* V4T. */
14012 T(V6K), /* V5T. */
14013 T(V6K), /* V5TE. */
14014 T(V6K), /* V5TEJ. */
14015 T(V6K), /* V6. */
14016 T(V6KZ), /* V6KZ. */
14017 T(V7), /* V6T2. */
14018 T(V6K), /* V6K. */
14019 T(V7), /* V7. */
14020 T(V6_M) /* V6_M. */
14021 };
14022 const int v6s_m[] =
14023 {
07d6d2b8
AM		 14024 -1, /* PRE_V4. */
14025 -1, /* V4. */
91e22acd
AS		 14026 T(V6K), /* V4T. */
14027 T(V6K), /* V5T. */
14028 T(V6K), /* V5TE. */
14029 T(V6K), /* V5TEJ. */
14030 T(V6K), /* V6. */
14031 T(V6KZ), /* V6KZ. */
14032 T(V7), /* V6T2. */
14033 T(V6K), /* V6K. */
14034 T(V7), /* V7. */
14035 T(V6S_M), /* V6_M. */
14036 T(V6S_M) /* V6S_M. */
14037 };
9e3c6df6
PB		 14038 const int v7e_m[] =
14039 {
07d6d2b8
AM		 14040 -1, /* PRE_V4. */
14041 -1, /* V4. */
9e3c6df6
PB		 14042 T(V7E_M), /* V4T. */
14043 T(V7E_M), /* V5T. */
14044 T(V7E_M), /* V5TE. */
14045 T(V7E_M), /* V5TEJ. */
14046 T(V7E_M), /* V6. */
14047 T(V7E_M), /* V6KZ. */
14048 T(V7E_M), /* V6T2. */
14049 T(V7E_M), /* V6K. */
14050 T(V7E_M), /* V7. */
14051 T(V7E_M), /* V6_M. */
14052 T(V7E_M), /* V6S_M. */
14053 T(V7E_M) /* V7E_M. */
14054 };
bca38921
MGD		 14055 const int v8[] =
14056 {
14057 T(V8), /* PRE_V4. */
14058 T(V8), /* V4. */
14059 T(V8), /* V4T. */
14060 T(V8), /* V5T. */
14061 T(V8), /* V5TE. */
14062 T(V8), /* V5TEJ. */
14063 T(V8), /* V6. */
14064 T(V8), /* V6KZ. */
14065 T(V8), /* V6T2. */
14066 T(V8), /* V6K. */
14067 T(V8), /* V7. */
14068 T(V8), /* V6_M. */
14069 T(V8), /* V6S_M. */
14070 T(V8), /* V7E_M. */
14071 T(V8) /* V8. */
14072 };
bff0500d
TP		 14073 const int v8r[] =
14074 {
14075 T(V8R), /* PRE_V4. */
14076 T(V8R), /* V4. */
14077 T(V8R), /* V4T. */
14078 T(V8R), /* V5T. */
14079 T(V8R), /* V5TE. */
14080 T(V8R), /* V5TEJ. */
14081 T(V8R), /* V6. */
14082 T(V8R), /* V6KZ. */
14083 T(V8R), /* V6T2. */
14084 T(V8R), /* V6K. */
14085 T(V8R), /* V7. */
14086 T(V8R), /* V6_M. */
14087 T(V8R), /* V6S_M. */
14088 T(V8R), /* V7E_M. */
14089 T(V8), /* V8. */
14090 T(V8R), /* V8R. */
14091 };
2fd158eb
TP		 14092 const int v8m_baseline[] =
14093 {
14094 -1, /* PRE_V4. */
14095 -1, /* V4. */
14096 -1, /* V4T. */
14097 -1, /* V5T. */
14098 -1, /* V5TE. */
14099 -1, /* V5TEJ. */
14100 -1, /* V6. */
14101 -1, /* V6KZ. */
14102 -1, /* V6T2. */
14103 -1, /* V6K. */
14104 -1, /* V7. */
14105 T(V8M_BASE), /* V6_M. */
14106 T(V8M_BASE), /* V6S_M. */
14107 -1, /* V7E_M. */
14108 -1, /* V8. */
bff0500d 14109 -1, /* V8R. */
2fd158eb
TP		 14110 T(V8M_BASE) /* V8-M BASELINE. */
14111 };
14112 const int v8m_mainline[] =
14113 {
14114 -1, /* PRE_V4. */
14115 -1, /* V4. */
14116 -1, /* V4T. */
14117 -1, /* V5T. */
14118 -1, /* V5TE. */
14119 -1, /* V5TEJ. */
14120 -1, /* V6. */
14121 -1, /* V6KZ. */
14122 -1, /* V6T2. */
14123 -1, /* V6K. */
14124 T(V8M_MAIN), /* V7. */
14125 T(V8M_MAIN), /* V6_M. */
14126 T(V8M_MAIN), /* V6S_M. */
14127 T(V8M_MAIN), /* V7E_M. */
14128 -1, /* V8. */
bff0500d 14129 -1, /* V8R. */
2fd158eb
TP		 14130 T(V8M_MAIN), /* V8-M BASELINE. */
14131 T(V8M_MAIN) /* V8-M MAINLINE. */
14132 };
91e22acd
AS		 14133 const int v4t_plus_v6_m[] =
14134 {
14135 -1, /* PRE_V4. */
14136 -1, /* V4. */
14137 T(V4T), /* V4T. */
14138 T(V5T), /* V5T. */
14139 T(V5TE), /* V5TE. */
14140 T(V5TEJ), /* V5TEJ. */
14141 T(V6), /* V6. */
14142 T(V6KZ), /* V6KZ. */
14143 T(V6T2), /* V6T2. */
14144 T(V6K), /* V6K. */
14145 T(V7), /* V7. */
14146 T(V6_M), /* V6_M. */
14147 T(V6S_M), /* V6S_M. */
9e3c6df6 14148 T(V7E_M), /* V7E_M. */
bca38921 14149 T(V8), /* V8. */
bff0500d 14150 -1, /* V8R. */
2fd158eb
TP		 14151 T(V8M_BASE), /* V8-M BASELINE. */
14152 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 14153 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14154 };
14155 const int *comb[] =
14156 {
14157 v6t2,
14158 v6k,
14159 v7,
14160 v6_m,
14161 v6s_m,
9e3c6df6 14162 v7e_m,
bca38921 14163 v8,
bff0500d 14164 v8r,
2fd158eb
TP		 14165 v8m_baseline,
14166 v8m_mainline,
91e22acd
AS		 14167 /* Pseudo-architecture. */
14168 v4t_plus_v6_m
14169 };
14170
14171 /* Check we've not got a higher architecture than we know about. */
14172
9e3c6df6 14173 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14174 {
90b6238f 14175 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14176 return -1;
14177 }
14178
14179 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14180
14181 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14182 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14183 oldtag = T(V4T_PLUS_V6_M);
14184
14185 /* And override the new tag if we have a Tag_also_compatible_with on the
14186 input. */
14187
14188 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14189 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14190 newtag = T(V4T_PLUS_V6_M);
14191
14192 tagl = (oldtag < newtag) ? oldtag : newtag;
14193 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14194
14195 /* Architectures before V6KZ add features monotonically. */
14196 if (tagh <= TAG_CPU_ARCH_V6KZ)
14197 return result;
14198
4ed7ed8d 14199 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14200
14201 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14202 as the canonical version. */
14203 if (result == T(V4T_PLUS_V6_M))
14204 {
14205 result = T(V4T);
14206 *secondary_compat_out = T(V6_M);
14207 }
14208 else
14209 *secondary_compat_out = -1;
14210
14211 if (result == -1)
14212 {
90b6238f 14213 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14214 ibfd, oldtag, newtag);
14215 return -1;
14216 }
14217
14218 return result;
14219#undef T
8e79c3df
CM		 14220}
14221
ac56ee8f
MGD		 14222/* Query attributes object to see if integer divide instructions may be
14223 present in an object. */
14224static bfd_boolean
14225elf32_arm_attributes_accept_div (const obj_attribute *attr)
14226{
14227 int arch = attr[Tag_CPU_arch].i;
14228 int profile = attr[Tag_CPU_arch_profile].i;
14229
14230 switch (attr[Tag_DIV_use].i)
14231 {
14232 case 0:
14233 /* Integer divide allowed if instruction contained in archetecture. */
14234 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14235 return TRUE;
14236 else if (arch >= TAG_CPU_ARCH_V7E_M)
14237 return TRUE;
14238 else
14239 return FALSE;
14240
14241 case 1:
14242 /* Integer divide explicitly prohibited. */
14243 return FALSE;
14244
14245 default:
14246 /* Unrecognised case - treat as allowing divide everywhere. */
14247 case 2:
14248 /* Integer divide allowed in ARM state. */
14249 return TRUE;
14250 }
14251}
14252
14253/* Query attributes object to see if integer divide instructions are
14254 forbidden to be in the object. This is not the inverse of
14255 elf32_arm_attributes_accept_div. */
14256static bfd_boolean
14257elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14258{
14259 return attr[Tag_DIV_use].i == 1;
14260}
14261
ee065d83
PB		 14262/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14263 are conflicting attributes. */
906e58ca 14264
ee065d83 14265static bfd_boolean
50e03d47 14266elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14267{
50e03d47 14268 bfd *obfd = info->output_bfd;
104d59d1
JM		 14269 obj_attribute *in_attr;
14270 obj_attribute *out_attr;
ee065d83
PB		 14271 /* Some tags have 0 = don't care, 1 = strong requirement,
14272 2 = weak requirement. */
91e22acd 14273 static const int order_021[3] = {0, 2, 1};
ee065d83 14274 int i;
91e22acd 14275 bfd_boolean result = TRUE;
9274e9de 14276 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14277
3e6b1042
DJ		 14278 /* Skip the linker stubs file. This preserves previous behavior
14279 of accepting unknown attributes in the first input file - but
14280 is that a bug? */
14281 if (ibfd->flags & BFD_LINKER_CREATED)
14282 return TRUE;
14283
9274e9de
TG		 14284 /* Skip any input that hasn't attribute section.
14285 This enables to link object files without attribute section with
14286 any others. */
14287 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14288 return TRUE;
14289
104d59d1 14290 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14291 {
14292 /* This is the first object. Copy the attributes. */
104d59d1 14293 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14294
cd21e546
MGD		 14295 out_attr = elf_known_obj_attributes_proc (obfd);
14296
004ae526
PB		 14297 /* Use the Tag_null value to indicate the attributes have been
14298 initialized. */
cd21e546 14299 out_attr[0].i = 1;
004ae526 14300
cd21e546
MGD		 14301 /* We do not output objects with Tag_MPextension_use_legacy - we move
14302 the attribute's value to Tag_MPextension_use. */
14303 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14304 {
14305 if (out_attr[Tag_MPextension_use].i != 0
14306 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14307 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14308 {
14309 _bfd_error_handler
871b3ab2 14310 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14311 "Tag_MPextension_use attributes"), ibfd);
14312 result = FALSE;
14313 }
14314
14315 out_attr[Tag_MPextension_use] =
14316 out_attr[Tag_MPextension_use_legacy];
14317 out_attr[Tag_MPextension_use_legacy].type = 0;
14318 out_attr[Tag_MPextension_use_legacy].i = 0;
14319 }
14320
14321 return result;
ee065d83
PB		 14322 }
14323
104d59d1
JM		 14324 in_attr = elf_known_obj_attributes_proc (ibfd);
14325 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14326 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14327 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14328 {
5c294fee
TG		 14329 /* Ignore mismatches if the object doesn't use floating point or is
14330 floating point ABI independent. */
14331 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14332 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14333 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14334 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14335 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14336 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14337 {
14338 _bfd_error_handler
871b3ab2 14339 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14340 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14341 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14342 result = FALSE;
ee065d83
PB		 14343 }
14344 }
14345
3de4a297 14346 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14347 {
14348 /* Merge this attribute with existing attributes. */
14349 switch (i)
14350 {
14351 case Tag_CPU_raw_name:
14352 case Tag_CPU_name:
6a631e86 14353 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14354 break;
14355
14356 case Tag_ABI_optimization_goals:
14357 case Tag_ABI_FP_optimization_goals:
14358 /* Use the first value seen. */
14359 break;
14360
14361 case Tag_CPU_arch:
91e22acd
AS		 14362 {
14363 int secondary_compat = -1, secondary_compat_out = -1;
14364 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14365 int arch_attr;
14366 static const char *name_table[] =
14367 {
91e22acd
AS		 14368 /* These aren't real CPU names, but we can't guess
14369 that from the architecture version alone. */
14370 "Pre v4",
14371 "ARM v4",
14372 "ARM v4T",
14373 "ARM v5T",
14374 "ARM v5TE",
14375 "ARM v5TEJ",
14376 "ARM v6",
14377 "ARM v6KZ",
14378 "ARM v6T2",
14379 "ARM v6K",
14380 "ARM v7",
14381 "ARM v6-M",
bca38921 14382 "ARM v6S-M",
2fd158eb
TP		 14383 "ARM v8",
14384 "",
14385 "ARM v8-M.baseline",
14386 "ARM v8-M.mainline",
91e22acd
AS		 14387 };
14388
14389 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14390 secondary_compat = get_secondary_compatible_arch (ibfd);
14391 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14392 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14393 &secondary_compat_out,
14394 in_attr[i].i,
14395 secondary_compat);
14396
14397 /* Return with error if failed to merge. */
14398 if (arch_attr == -1)
14399 return FALSE;
14400
14401 out_attr[i].i = arch_attr;
14402
91e22acd
AS		 14403 set_secondary_compatible_arch (obfd, secondary_compat_out);
14404
14405 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14406 if (out_attr[i].i == saved_out_attr)
14407 ; /* Leave the names alone. */
14408 else if (out_attr[i].i == in_attr[i].i)
14409 {
14410 /* The output architecture has been changed to match the
14411 input architecture. Use the input names. */
14412 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14413 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14414 : NULL;
14415 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14416 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14417 : NULL;
14418 }
14419 else
14420 {
14421 out_attr[Tag_CPU_name].s = NULL;
14422 out_attr[Tag_CPU_raw_name].s = NULL;
14423 }
14424
14425 /* If we still don't have a value for Tag_CPU_name,
14426 make one up now. Tag_CPU_raw_name remains blank. */
14427 if (out_attr[Tag_CPU_name].s == NULL
14428 && out_attr[i].i < ARRAY_SIZE (name_table))
14429 out_attr[Tag_CPU_name].s =
14430 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14431 }
14432 break;
14433
ee065d83
PB		 14434 case Tag_ARM_ISA_use:
14435 case Tag_THUMB_ISA_use:
ee065d83 14436 case Tag_WMMX_arch:
91e22acd
AS		 14437 case Tag_Advanced_SIMD_arch:
14438 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14439 case Tag_ABI_FP_rounding:
ee065d83
PB		 14440 case Tag_ABI_FP_exceptions:
14441 case Tag_ABI_FP_user_exceptions:
14442 case Tag_ABI_FP_number_model:
75375b3e 14443 case Tag_FP_HP_extension:
91e22acd
AS		 14444 case Tag_CPU_unaligned_access:
14445 case Tag_T2EE_use:
91e22acd 14446 case Tag_MPextension_use:
ee065d83
PB		 14447 /* Use the largest value specified. */
14448 if (in_attr[i].i > out_attr[i].i)
14449 out_attr[i].i = in_attr[i].i;
14450 break;
14451
75375b3e 14452 case Tag_ABI_align_preserved:
91e22acd
AS		 14453 case Tag_ABI_PCS_RO_data:
14454 /* Use the smallest value specified. */
14455 if (in_attr[i].i < out_attr[i].i)
14456 out_attr[i].i = in_attr[i].i;
14457 break;
14458
75375b3e 14459 case Tag_ABI_align_needed:
91e22acd 14460 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14461 && (in_attr[Tag_ABI_align_preserved].i == 0
14462 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14463 {
91e22acd
AS		 14464 /* This error message should be enabled once all non-conformant
14465 binaries in the toolchain have had the attributes set
14466 properly.
ee065d83 14467 _bfd_error_handler
871b3ab2 14468 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14469 obfd, ibfd);
14470 result = FALSE; */
ee065d83 14471 }
91e22acd
AS		 14472 /* Fall through. */
14473 case Tag_ABI_FP_denormal:
14474 case Tag_ABI_PCS_GOT_use:
14475 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14476 value if greater than 2 (for future-proofing). */
14477 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14478 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14479 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14480 out_attr[i].i = in_attr[i].i;
14481 break;
91e22acd 14482
75375b3e
MGD		 14483 case Tag_Virtualization_use:
14484 /* The virtualization tag effectively stores two bits of
14485 information: the intended use of TrustZone (in bit 0), and the
14486 intended use of Virtualization (in bit 1). */
14487 if (out_attr[i].i == 0)
14488 out_attr[i].i = in_attr[i].i;
14489 else if (in_attr[i].i != 0
14490 && in_attr[i].i != out_attr[i].i)
14491 {
14492 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14493 out_attr[i].i = 3;
14494 else
14495 {
14496 _bfd_error_handler
871b3ab2
AM		 14497 (_("error: %pB: unable to merge virtualization attributes "
14498 "with %pB"),
75375b3e
MGD		 14499 obfd, ibfd);
14500 result = FALSE;
14501 }
14502 }
14503 break;
91e22acd
AS		 14504
14505 case Tag_CPU_arch_profile:
14506 if (out_attr[i].i != in_attr[i].i)
14507 {
14508 /* 0 will merge with anything.
14509 'A' and 'S' merge to 'A'.
14510 'R' and 'S' merge to 'R'.
99059e56 14511 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14512 if (out_attr[i].i == 0
14513 || (out_attr[i].i == 'S'
14514 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14515 out_attr[i].i = in_attr[i].i;
14516 else if (in_attr[i].i == 0
14517 || (in_attr[i].i == 'S'
14518 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14519 ; /* Do nothing. */
91e22acd
AS		 14520 else
14521 {
14522 _bfd_error_handler
90b6238f 14523 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14524 ibfd,
14525 in_attr[i].i ? in_attr[i].i : '0',
14526 out_attr[i].i ? out_attr[i].i : '0');
14527 result = FALSE;
14528 }
14529 }
14530 break;
15afaa63
TP		 14531
14532 case Tag_DSP_extension:
14533 /* No need to change output value if any of:
14534 - pre (<=) ARMv5T input architecture (do not have DSP)
14535 - M input profile not ARMv7E-M and do not have DSP. */
14536 if (in_attr[Tag_CPU_arch].i <= 3
14537 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14538 && in_attr[Tag_CPU_arch].i != 13
14539 && in_attr[i].i == 0))
14540 ; /* Do nothing. */
14541 /* Output value should be 0 if DSP part of architecture, ie.
14542 - post (>=) ARMv5te architecture output
14543 - A, R or S profile output or ARMv7E-M output architecture. */
14544 else if (out_attr[Tag_CPU_arch].i >= 4
14545 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14546 || out_attr[Tag_CPU_arch_profile].i == 'R'
14547 || out_attr[Tag_CPU_arch_profile].i == 'S'
14548 || out_attr[Tag_CPU_arch].i == 13))
14549 out_attr[i].i = 0;
14550 /* Otherwise, DSP instructions are added and not part of output
14551 architecture. */
14552 else
14553 out_attr[i].i = 1;
14554 break;
14555
75375b3e 14556 case Tag_FP_arch:
62f3b8c8 14557 {
4547cb56
NC		 14558 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14559 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14560 when it's 0. It might mean absence of FP hardware if
99654aaf 14561 Tag_FP_arch is zero. */
4547cb56 14562
a715796b 14563#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14564 static const struct
14565 {
14566 int ver;
14567 int regs;
bca38921 14568 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14569 {
14570 {0, 0},
14571 {1, 16},
14572 {2, 16},
14573 {3, 32},
14574 {3, 16},
14575 {4, 32},
bca38921 14576 {4, 16},
a715796b
TG		 14577 {8, 32},
14578 {8, 16}
62f3b8c8
PB		 14579 };
14580 int ver;
14581 int regs;
14582 int newval;
14583
4547cb56
NC		 14584 /* If the output has no requirement about FP hardware,
14585 follow the requirement of the input. */
14586 if (out_attr[i].i == 0)
14587 {
4ec192e6
RE		 14588 /* This assert is still reasonable, we shouldn't
14589 produce the suspicious build attribute
14590 combination (See below for in_attr). */
4547cb56
NC		 14591 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14592 out_attr[i].i = in_attr[i].i;
14593 out_attr[Tag_ABI_HardFP_use].i
14594 = in_attr[Tag_ABI_HardFP_use].i;
14595 break;
14596 }
14597 /* If the input has no requirement about FP hardware, do
14598 nothing. */
14599 else if (in_attr[i].i == 0)
14600 {
4ec192e6
RE		 14601 /* We used to assert that Tag_ABI_HardFP_use was
14602 zero here, but we should never assert when
14603 consuming an object file that has suspicious
14604 build attributes. The single precision variant
14605 of 'no FP architecture' is still 'no FP
14606 architecture', so we just ignore the tag in this
14607 case. */
4547cb56
NC		 14608 break;
14609 }
14610
14611 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14612 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14613
14614 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14615 do nothing. */
14616 if (in_attr[Tag_ABI_HardFP_use].i == 0
14617 && out_attr[Tag_ABI_HardFP_use].i == 0)
14618 ;
14619 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14620 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14621 else if (in_attr[Tag_ABI_HardFP_use].i
14622 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14623 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14624
14625 /* Now we can handle Tag_FP_arch. */
14626
bca38921
MGD		 14627 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14628 pick the biggest. */
14629 if (in_attr[i].i >= VFP_VERSION_COUNT
14630 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14631 {
14632 out_attr[i] = in_attr[i];
14633 break;
14634 }
14635 /* The output uses the superset of input features
14636 (ISA version) and registers. */
14637 ver = vfp_versions[in_attr[i].i].ver;
14638 if (ver < vfp_versions[out_attr[i].i].ver)
14639 ver = vfp_versions[out_attr[i].i].ver;
14640 regs = vfp_versions[in_attr[i].i].regs;
14641 if (regs < vfp_versions[out_attr[i].i].regs)
14642 regs = vfp_versions[out_attr[i].i].regs;
14643 /* This assumes all possible supersets are also a valid
99059e56 14644 options. */
bca38921 14645 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14646 {
14647 if (regs == vfp_versions[newval].regs
14648 && ver == vfp_versions[newval].ver)
14649 break;
14650 }
14651 out_attr[i].i = newval;
14652 }
b1cc4aeb 14653 break;
ee065d83
PB		 14654 case Tag_PCS_config:
14655 if (out_attr[i].i == 0)
14656 out_attr[i].i = in_attr[i].i;
b6009aca 14657 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14658 {
14659 /* It's sometimes ok to mix different configs, so this is only
99059e56 14660 a warning. */
ee065d83 14661 _bfd_error_handler
90b6238f 14662 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14663 }
14664 break;
14665 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14666 if (in_attr[i].i != out_attr[i].i
14667 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14668 && in_attr[i].i != AEABI_R9_unused)
14669 {
14670 _bfd_error_handler
90b6238f 14671 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14672 result = FALSE;
ee065d83
PB		 14673 }
14674 if (out_attr[i].i == AEABI_R9_unused)
14675 out_attr[i].i = in_attr[i].i;
14676 break;
14677 case Tag_ABI_PCS_RW_data:
14678 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14679 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14680 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14681 {
14682 _bfd_error_handler
871b3ab2 14683 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14684 ibfd);
91e22acd 14685 result = FALSE;
ee065d83
PB		 14686 }
14687 /* Use the smallest value specified. */
14688 if (in_attr[i].i < out_attr[i].i)
14689 out_attr[i].i = in_attr[i].i;
14690 break;
ee065d83 14691 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14692 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14693 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14694 {
14695 _bfd_error_handler
871b3ab2 14696 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14697 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14698 }
a9dc9481 14699 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14700 out_attr[i].i = in_attr[i].i;
14701 break;
ee065d83
PB		 14702 case Tag_ABI_enum_size:
14703 if (in_attr[i].i != AEABI_enum_unused)
14704 {
14705 if (out_attr[i].i == AEABI_enum_unused
14706 || out_attr[i].i == AEABI_enum_forced_wide)
14707 {
14708 /* The existing object is compatible with anything.
14709 Use whatever requirements the new object has. */
14710 out_attr[i].i = in_attr[i].i;
14711 }
14712 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14713 && out_attr[i].i != in_attr[i].i
0ffa91dd 14714 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14715 {
91e22acd 14716 static const char *aeabi_enum_names[] =
bf21ed78 14717 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14718 const char *in_name =
14719 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14720 ? aeabi_enum_names[in_attr[i].i]
14721 : "<unknown>";
14722 const char *out_name =
14723 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14724 ? aeabi_enum_names[out_attr[i].i]
14725 : "<unknown>";
ee065d83 14726 _bfd_error_handler
871b3ab2 14727 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14728 ibfd, in_name, out_name);
ee065d83
PB		 14729 }
14730 }
14731 break;
14732 case Tag_ABI_VFP_args:
14733 /* Aready done. */
14734 break;
14735 case Tag_ABI_WMMX_args:
14736 if (in_attr[i].i != out_attr[i].i)
14737 {
14738 _bfd_error_handler
871b3ab2 14739 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14740 ibfd, obfd);
91e22acd 14741 result = FALSE;
ee065d83
PB		 14742 }
14743 break;
7b86a9fa
AS		 14744 case Tag_compatibility:
14745 /* Merged in target-independent code. */
14746 break;
91e22acd 14747 case Tag_ABI_HardFP_use:
4547cb56 14748 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14749 break;
14750 case Tag_ABI_FP_16bit_format:
14751 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14752 {
14753 if (in_attr[i].i != out_attr[i].i)
14754 {
14755 _bfd_error_handler
871b3ab2 14756 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14757 ibfd, obfd);
14758 result = FALSE;
14759 }
14760 }
14761 if (in_attr[i].i != 0)
14762 out_attr[i].i = in_attr[i].i;
14763 break;
7b86a9fa 14764
cd21e546 14765 case Tag_DIV_use:
ac56ee8f
MGD		 14766 /* A value of zero on input means that the divide instruction may
14767 be used if available in the base architecture as specified via
14768 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14769 the user did not want divide instructions. A value of 2
14770 explicitly means that divide instructions were allowed in ARM
14771 and Thumb state. */
14772 if (in_attr[i].i == out_attr[i].i)
14773 /* Do nothing. */ ;
14774 else if (elf32_arm_attributes_forbid_div (in_attr)
14775 && !elf32_arm_attributes_accept_div (out_attr))
14776 out_attr[i].i = 1;
14777 else if (elf32_arm_attributes_forbid_div (out_attr)
14778 && elf32_arm_attributes_accept_div (in_attr))
14779 out_attr[i].i = in_attr[i].i;
14780 else if (in_attr[i].i == 2)
14781 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14782 break;
14783
14784 case Tag_MPextension_use_legacy:
14785 /* We don't output objects with Tag_MPextension_use_legacy - we
14786 move the value to Tag_MPextension_use. */
14787 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14788 {
14789 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14790 {
14791 _bfd_error_handler
871b3ab2 14792 (_("%pB has both the current and legacy "
b38cadfb 14793 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14794 ibfd);
14795 result = FALSE;
14796 }
14797 }
14798
14799 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14800 out_attr[Tag_MPextension_use] = in_attr[i];
14801
14802 break;
14803
91e22acd 14804 case Tag_nodefaults:
2d0bb761
AS		 14805 /* This tag is set if it exists, but the value is unused (and is
14806 typically zero). We don't actually need to do anything here -
14807 the merge happens automatically when the type flags are merged
14808 below. */
91e22acd
AS		 14809 break;
14810 case Tag_also_compatible_with:
14811 /* Already done in Tag_CPU_arch. */
14812 break;
14813 case Tag_conformance:
14814 /* Keep the attribute if it matches. Throw it away otherwise.
14815 No attribute means no claim to conform. */
14816 if (!in_attr[i].s || !out_attr[i].s
14817 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14818 out_attr[i].s = NULL;
14819 break;
3cfad14c 14820
91e22acd 14821 default:
e8b36cd1
JM		 14822 result
14823 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14824 }
14825
14826 /* If out_attr was copied from in_attr then it won't have a type yet. */
14827 if (in_attr[i].type && !out_attr[i].type)
14828 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14829 }
14830
104d59d1 14831 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14832 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14833 return FALSE;
ee065d83 14834
104d59d1 14835 /* Check for any attributes not known on ARM. */
e8b36cd1 14836 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14837
91e22acd 14838 return result;
252b5132
RH		 14839}
14840
3a4a14e9
PB		 14841
14842/* Return TRUE if the two EABI versions are incompatible. */
14843
14844static bfd_boolean
14845elf32_arm_versions_compatible (unsigned iver, unsigned over)
14846{
14847 /* v4 and v5 are the same spec before and after it was released,
14848 so allow mixing them. */
14849 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14850 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14851 return TRUE;
14852
14853 return (iver == over);
14854}
14855
252b5132
RH		 14856/* Merge backend specific data from an object file to the output
14857 object file when linking. */
9b485d32 14858
b34976b6 14859static bfd_boolean
50e03d47 14860elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14861
9b485d32
NC		 14862/* Display the flags field. */
14863
b34976b6 14864static bfd_boolean
57e8b36a 14865elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14866{
fc830a83
NC		 14867 FILE * file = (FILE *) ptr;
14868 unsigned long flags;
252b5132
RH		 14869
14870 BFD_ASSERT (abfd != NULL && ptr != NULL);
14871
14872 /* Print normal ELF private data. */
14873 _bfd_elf_print_private_bfd_data (abfd, ptr);
14874
fc830a83 14875 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14876 /* Ignore init flag - it may not be set, despite the flags field
14877 containing valid data. */
252b5132 14878
9b485d32 14879 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14880
fc830a83
NC		 14881 switch (EF_ARM_EABI_VERSION (flags))
14882 {
14883 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14884 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14885 official ARM ELF extended ABI. Hence they are only decoded if
14886 the EABI version is not set. */
fd2ec330 14887 if (flags & EF_ARM_INTERWORK)
9b485d32 14888 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14889
fd2ec330 14890 if (flags & EF_ARM_APCS_26)
6c571f00 14891 fprintf (file, " [APCS-26]");
fc830a83 14892 else
6c571f00 14893 fprintf (file, " [APCS-32]");
9a5aca8c 14894
96a846ea
RE		 14895 if (flags & EF_ARM_VFP_FLOAT)
14896 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14897 else if (flags & EF_ARM_MAVERICK_FLOAT)
14898 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14899 else
14900 fprintf (file, _(" [FPA float format]"));
14901
fd2ec330 14902 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14903 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14904
fd2ec330 14905 if (flags & EF_ARM_PIC)
9b485d32 14906 fprintf (file, _(" [position independent]"));
fc830a83 14907
fd2ec330 14908 if (flags & EF_ARM_NEW_ABI)
9b485d32 14909 fprintf (file, _(" [new ABI]"));
9a5aca8c 14910
fd2ec330 14911 if (flags & EF_ARM_OLD_ABI)
9b485d32 14912 fprintf (file, _(" [old ABI]"));
9a5aca8c 14913
fd2ec330 14914 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14915 fprintf (file, _(" [software FP]"));
9a5aca8c 14916
96a846ea
RE		 14917 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14918 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14919 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14920 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14921 break;
9a5aca8c 14922
fc830a83 14923 case EF_ARM_EABI_VER1:
9b485d32 14924 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14925
fc830a83 14926 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14927 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14928 else
9b485d32 14929 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14930
fc830a83
NC		 14931 flags &= ~ EF_ARM_SYMSARESORTED;
14932 break;
9a5aca8c 14933
fd2ec330
PB		 14934 case EF_ARM_EABI_VER2:
14935 fprintf (file, _(" [Version2 EABI]"));
14936
14937 if (flags & EF_ARM_SYMSARESORTED)
14938 fprintf (file, _(" [sorted symbol table]"));
14939 else
14940 fprintf (file, _(" [unsorted symbol table]"));
14941
14942 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14943 fprintf (file, _(" [dynamic symbols use segment index]"));
14944
14945 if (flags & EF_ARM_MAPSYMSFIRST)
14946 fprintf (file, _(" [mapping symbols precede others]"));
14947
99e4ae17 14948 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14949 | EF_ARM_MAPSYMSFIRST);
14950 break;
14951
d507cf36
PB		 14952 case EF_ARM_EABI_VER3:
14953 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14954 break;
14955
14956 case EF_ARM_EABI_VER4:
14957 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14958 goto eabi;
d507cf36 14959
3a4a14e9
PB		 14960 case EF_ARM_EABI_VER5:
14961 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14962
14963 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14964 fprintf (file, _(" [soft-float ABI]"));
14965
14966 if (flags & EF_ARM_ABI_FLOAT_HARD)
14967 fprintf (file, _(" [hard-float ABI]"));
14968
14969 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14970
3a4a14e9 14971 eabi:
d507cf36
PB		 14972 if (flags & EF_ARM_BE8)
14973 fprintf (file, _(" [BE8]"));
14974
14975 if (flags & EF_ARM_LE8)
14976 fprintf (file, _(" [LE8]"));
14977
14978 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14979 break;
14980
fc830a83 14981 default:
9b485d32 14982 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14983 break;
14984 }
252b5132 14985
fc830a83 14986 flags &= ~ EF_ARM_EABIMASK;
252b5132 14987
fc830a83 14988 if (flags & EF_ARM_RELEXEC)
9b485d32 14989 fprintf (file, _(" [relocatable executable]"));
252b5132 14990
18a20338
CL		 14991 if (flags & EF_ARM_PIC)
14992 fprintf (file, _(" [position independent]"));
14993
14994 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
14995 fprintf (file, _(" [FDPIC ABI supplement]"));
14996
14997 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 14998
14999 if (flags)
9b485d32 15000 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15001
252b5132
RH		 15002 fputc ('\n', file);
15003
b34976b6 15004 return TRUE;
252b5132
RH		 15005}
15006
15007static int
57e8b36a 15008elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15009{
2f0ca46a
NC		 15010 switch (ELF_ST_TYPE (elf_sym->st_info))
15011 {
15012 case STT_ARM_TFUNC:
15013 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15014
2f0ca46a
NC		 15015 case STT_ARM_16BIT:
15016 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15017 This allows us to distinguish between data used by Thumb instructions
15018 and non-data (which is probably code) inside Thumb regions of an
15019 executable. */
1a0eb693 15020 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15021 return ELF_ST_TYPE (elf_sym->st_info);
15022 break;
9a5aca8c 15023
ce855c42
NC		 15024 default:
15025 break;
2f0ca46a
NC		 15026 }
15027
15028 return type;
252b5132 15029}
f21f3fe0 15030
252b5132 15031static asection *
07adf181
AM		 15032elf32_arm_gc_mark_hook (asection *sec,
15033 struct bfd_link_info *info,
15034 Elf_Internal_Rela *rel,
15035 struct elf_link_hash_entry *h,
15036 Elf_Internal_Sym *sym)
252b5132
RH		 15037{
15038 if (h != NULL)
07adf181 15039 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15040 {
15041 case R_ARM_GNU_VTINHERIT:
15042 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15043 return NULL;
15044 }
9ad5cbcf 15045
07adf181 15046 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15047}
15048
780a67af
NC		 15049/* Look through the relocs for a section during the first phase. */
15050
b34976b6 15051static bfd_boolean
57e8b36a
NC		 15052elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15053 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15054{
b34976b6
AM		 15055 Elf_Internal_Shdr *symtab_hdr;
15056 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15057 const Elf_Internal_Rela *rel;
15058 const Elf_Internal_Rela *rel_end;
15059 bfd *dynobj;
5e681ec4 15060 asection *sreloc;
5e681ec4 15061 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15062 bfd_boolean call_reloc_p;
15063 bfd_boolean may_become_dynamic_p;
15064 bfd_boolean may_need_local_target_p;
ce98a316 15065 unsigned long nsyms;
9a5aca8c 15066
0e1862bb 15067 if (bfd_link_relocatable (info))
b34976b6 15068 return TRUE;
9a5aca8c 15069
0ffa91dd
NC		 15070 BFD_ASSERT (is_arm_elf (abfd));
15071
5e681ec4 15072 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15073 if (htab == NULL)
15074 return FALSE;
15075
5e681ec4 15076 sreloc = NULL;
9a5aca8c 15077
67687978
PB		 15078 /* Create dynamic sections for relocatable executables so that we can
15079 copy relocations. */
15080 if (htab->root.is_relocatable_executable
15081 && ! htab->root.dynamic_sections_created)
15082 {
15083 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15084 return FALSE;
15085 }
15086
cbc704f3
RS		 15087 if (htab->root.dynobj == NULL)
15088 htab->root.dynobj = abfd;
34e77a92
RS		 15089 if (!create_ifunc_sections (info))
15090 return FALSE;
cbc704f3
RS		 15091
15092 dynobj = htab->root.dynobj;
15093
0ffa91dd 15094 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15095 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15096 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15097
252b5132
RH		 15098 rel_end = relocs + sec->reloc_count;
15099 for (rel = relocs; rel < rel_end; rel++)
15100 {
34e77a92 15101 Elf_Internal_Sym *isym;
252b5132 15102 struct elf_link_hash_entry *h;
b7693d02 15103 struct elf32_arm_link_hash_entry *eh;
d42c267e 15104 unsigned int r_symndx;
eb043451 15105 int r_type;
9a5aca8c 15106
252b5132 15107 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15108 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15109 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15110
ce98a316
NC		 15111 if (r_symndx >= nsyms
15112 /* PR 9934: It is possible to have relocations that do not
15113 refer to symbols, thus it is also possible to have an
15114 object file containing relocations but no symbol table. */
cf35638d 15115 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15116 {
871b3ab2 15117 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15118 r_symndx);
ba93b8ac
DJ		 15119 return FALSE;
15120 }
15121
34e77a92
RS		 15122 h = NULL;
15123 isym = NULL;
15124 if (nsyms > 0)
973a3492 15125 {
34e77a92
RS		 15126 if (r_symndx < symtab_hdr->sh_info)
15127 {
15128 /* A local symbol. */
15129 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15130 abfd, r_symndx);
15131 if (isym == NULL)
15132 return FALSE;
15133 }
15134 else
15135 {
15136 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15137 while (h->root.type == bfd_link_hash_indirect
15138 || h->root.type == bfd_link_hash_warning)
15139 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15140 }
973a3492 15141 }
9a5aca8c 15142
b7693d02
DJ		 15143 eh = (struct elf32_arm_link_hash_entry *) h;
15144
f6e32f6d
RS		 15145 call_reloc_p = FALSE;
15146 may_become_dynamic_p = FALSE;
15147 may_need_local_target_p = FALSE;
15148
0855e32b
NS		 15149 /* Could be done earlier, if h were already available. */
15150 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15151 switch (r_type)
99059e56 15152 {
e8b09b87
CL		 15153 case R_ARM_GOTOFFFUNCDESC:
15154 {
15155 if (h == NULL)
15156 {
15157 if (!elf32_arm_allocate_local_sym_info (abfd))
15158 return FALSE;
15159 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15160 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15161 }
15162 else
15163 {
15164 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15165 }
15166 }
15167 break;
15168
15169 case R_ARM_GOTFUNCDESC:
15170 {
15171 if (h == NULL)
15172 {
15173 /* Such a relocation is not supposed to be generated
15174 by gcc on a static function. */
15175 /* Anyway if needed it could be handled. */
15176 abort();
15177 }
15178 else
15179 {
15180 eh->fdpic_cnts.gotfuncdesc_cnt++;
15181 }
15182 }
15183 break;
15184
15185 case R_ARM_FUNCDESC:
15186 {
15187 if (h == NULL)
15188 {
15189 if (!elf32_arm_allocate_local_sym_info (abfd))
15190 return FALSE;
15191 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15192 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15193 }
15194 else
15195 {
15196 eh->fdpic_cnts.funcdesc_cnt++;
15197 }
15198 }
15199 break;
15200
5e681ec4 15201 case R_ARM_GOT32:
eb043451 15202 case R_ARM_GOT_PREL:
ba93b8ac 15203 case R_ARM_TLS_GD32:
5c5a4843 15204 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15205 case R_ARM_TLS_IE32:
5c5a4843 15206 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15207 case R_ARM_TLS_GOTDESC:
15208 case R_ARM_TLS_DESCSEQ:
15209 case R_ARM_THM_TLS_DESCSEQ:
15210 case R_ARM_TLS_CALL:
15211 case R_ARM_THM_TLS_CALL:
5e681ec4 15212 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15213 {
15214 int tls_type, old_tls_type;
5e681ec4 15215
ba93b8ac
DJ		 15216 switch (r_type)
15217 {
15218 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15219 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15220
ba93b8ac 15221 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15222 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15223
0855e32b
NS		 15224 case R_ARM_TLS_GOTDESC:
15225 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15226 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15227 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15228
ba93b8ac
DJ		 15229 default: tls_type = GOT_NORMAL; break;
15230 }
252b5132 15231
0e1862bb 15232 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15233 info->flags |= DF_STATIC_TLS;
15234
ba93b8ac
DJ		 15235 if (h != NULL)
15236 {
15237 h->got.refcount++;
15238 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15239 }
15240 else
15241 {
ba93b8ac 15242 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15243 if (!elf32_arm_allocate_local_sym_info (abfd))
15244 return FALSE;
15245 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15246 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15247 }
15248
0855e32b 15249 /* If a variable is accessed with both tls methods, two
99059e56 15250 slots may be created. */
0855e32b
NS		 15251 if (GOT_TLS_GD_ANY_P (old_tls_type)
15252 && GOT_TLS_GD_ANY_P (tls_type))
15253 tls_type |= old_tls_type;
15254
15255 /* We will already have issued an error message if there
15256 is a TLS/non-TLS mismatch, based on the symbol
15257 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15258 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15259 && tls_type != GOT_NORMAL)
15260 tls_type |= old_tls_type;
15261
0855e32b 15262 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15263 method, we're able to relax. Turn off the GDESC flag,
15264 without messing up with any other kind of tls types
6a631e86 15265 that may be involved. */
0855e32b
NS		 15266 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15267 tls_type &= ~GOT_TLS_GDESC;
15268
ba93b8ac
DJ		 15269 if (old_tls_type != tls_type)
15270 {
15271 if (h != NULL)
15272 elf32_arm_hash_entry (h)->tls_type = tls_type;
15273 else
15274 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15275 }
15276 }
8029a119 15277 /* Fall through. */
ba93b8ac
DJ		 15278
15279 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15280 case R_ARM_TLS_LDM32_FDPIC:
15281 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15282 htab->tls_ldm_got.refcount++;
8029a119 15283 /* Fall through. */
252b5132 15284
c19d1205 15285 case R_ARM_GOTOFF32:
5e681ec4 15286 case R_ARM_GOTPC:
cbc704f3
RS		 15287 if (htab->root.sgot == NULL
15288 && !create_got_section (htab->root.dynobj, info))
15289 return FALSE;
252b5132
RH		 15290 break;
15291
252b5132 15292 case R_ARM_PC24:
7359ea65 15293 case R_ARM_PLT32:
5b5bb741
PB		 15294 case R_ARM_CALL:
15295 case R_ARM_JUMP24:
eb043451 15296 case R_ARM_PREL31:
c19d1205 15297 case R_ARM_THM_CALL:
bd97cb95
DJ		 15298 case R_ARM_THM_JUMP24:
15299 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15300 call_reloc_p = TRUE;
15301 may_need_local_target_p = TRUE;
15302 break;
15303
15304 case R_ARM_ABS12:
15305 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15306 ldr __GOTT_INDEX__ offsets. */
15307 if (!htab->vxworks_p)
15308 {
15309 may_need_local_target_p = TRUE;
15310 break;
15311 }
aebf9be7 15312 else goto jump_over;
9eaff861 15313
f6e32f6d 15314 /* Fall through. */
39623e12 15315
96c23d59
JM		 15316 case R_ARM_MOVW_ABS_NC:
15317 case R_ARM_MOVT_ABS:
15318 case R_ARM_THM_MOVW_ABS_NC:
15319 case R_ARM_THM_MOVT_ABS:
0e1862bb 15320 if (bfd_link_pic (info))
96c23d59 15321 {
4eca0228 15322 _bfd_error_handler
871b3ab2 15323 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15324 abfd, elf32_arm_howto_table_1[r_type].name,
15325 (h) ? h->root.root.string : "a local symbol");
15326 bfd_set_error (bfd_error_bad_value);
15327 return FALSE;
15328 }
15329
15330 /* Fall through. */
39623e12
PB		 15331 case R_ARM_ABS32:
15332 case R_ARM_ABS32_NOI:
aebf9be7 15333 jump_over:
0e1862bb 15334 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15335 {
15336 h->pointer_equality_needed = 1;
15337 }
15338 /* Fall through. */
39623e12
PB		 15339 case R_ARM_REL32:
15340 case R_ARM_REL32_NOI:
b6895b4f
PB		 15341 case R_ARM_MOVW_PREL_NC:
15342 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15343 case R_ARM_THM_MOVW_PREL_NC:
15344 case R_ARM_THM_MOVT_PREL:
39623e12 15345
b7693d02 15346 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15347 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15348 || htab->fdpic_p)
34e77a92
RS		 15349 && (sec->flags & SEC_ALLOC) != 0)
15350 {
15351 if (h == NULL
469a3493 15352 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15353 {
15354 /* In shared libraries and relocatable executables,
15355 we treat local relative references as calls;
15356 see the related SYMBOL_CALLS_LOCAL code in
15357 allocate_dynrelocs. */
15358 call_reloc_p = TRUE;
15359 may_need_local_target_p = TRUE;
15360 }
15361 else
15362 /* We are creating a shared library or relocatable
15363 executable, and this is a reloc against a global symbol,
15364 or a non-PC-relative reloc against a local symbol.
15365 We may need to copy the reloc into the output. */
15366 may_become_dynamic_p = TRUE;
15367 }
f6e32f6d
RS		 15368 else
15369 may_need_local_target_p = TRUE;
252b5132
RH		 15370 break;
15371
99059e56
RM		 15372 /* This relocation describes the C++ object vtable hierarchy.
15373 Reconstruct it for later use during GC. */
15374 case R_ARM_GNU_VTINHERIT:
15375 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15376 return FALSE;
15377 break;
15378
15379 /* This relocation describes which C++ vtable entries are actually
15380 used. Record for later use during GC. */
15381 case R_ARM_GNU_VTENTRY:
15382 BFD_ASSERT (h != NULL);
15383 if (h != NULL
15384 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
15385 return FALSE;
15386 break;
15387 }
f6e32f6d
RS		 15388
15389 if (h != NULL)
15390 {
15391 if (call_reloc_p)
15392 /* We may need a .plt entry if the function this reloc
15393 refers to is in a different object, regardless of the
15394 symbol's type. We can't tell for sure yet, because
15395 something later might force the symbol local. */
15396 h->needs_plt = 1;
15397 else if (may_need_local_target_p)
15398 /* If this reloc is in a read-only section, we might
15399 need a copy reloc. We can't check reliably at this
15400 stage whether the section is read-only, as input
15401 sections have not yet been mapped to output sections.
15402 Tentatively set the flag for now, and correct in
15403 adjust_dynamic_symbol. */
15404 h->non_got_ref = 1;
15405 }
15406
34e77a92
RS		 15407 if (may_need_local_target_p
15408 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15409 {
34e77a92
RS		 15410 union gotplt_union *root_plt;
15411 struct arm_plt_info *arm_plt;
15412 struct arm_local_iplt_info *local_iplt;
15413
15414 if (h != NULL)
15415 {
15416 root_plt = &h->plt;
15417 arm_plt = &eh->plt;
15418 }
15419 else
15420 {
15421 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15422 if (local_iplt == NULL)
15423 return FALSE;
15424 root_plt = &local_iplt->root;
15425 arm_plt = &local_iplt->arm;
15426 }
15427
f6e32f6d
RS		 15428 /* If the symbol is a function that doesn't bind locally,
15429 this relocation will need a PLT entry. */
a8c887dd
NC		 15430 if (root_plt->refcount != -1)
15431 root_plt->refcount += 1;
34e77a92
RS		 15432
15433 if (!call_reloc_p)
15434 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15435
15436 /* It's too early to use htab->use_blx here, so we have to
15437 record possible blx references separately from
15438 relocs that definitely need a thumb stub. */
15439
15440 if (r_type == R_ARM_THM_CALL)
34e77a92 15441 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15442
15443 if (r_type == R_ARM_THM_JUMP24
15444 || r_type == R_ARM_THM_JUMP19)
34e77a92 15445 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15446 }
15447
15448 if (may_become_dynamic_p)
15449 {
15450 struct elf_dyn_relocs *p, **head;
15451
15452 /* Create a reloc section in dynobj. */
15453 if (sreloc == NULL)
15454 {
15455 sreloc = _bfd_elf_make_dynamic_reloc_section
15456 (sec, dynobj, 2, abfd, ! htab->use_rel);
15457
15458 if (sreloc == NULL)
15459 return FALSE;
15460
15461 /* BPABI objects never have dynamic relocations mapped. */
15462 if (htab->symbian_p)
15463 {
15464 flagword flags;
15465
15466 flags = bfd_get_section_flags (dynobj, sreloc);
15467 flags &= ~(SEC_LOAD | SEC_ALLOC);
15468 bfd_set_section_flags (dynobj, sreloc, flags);
15469 }
15470 }
15471
15472 /* If this is a global symbol, count the number of
15473 relocations we need for this symbol. */
15474 if (h != NULL)
15475 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15476 else
15477 {
34e77a92
RS		 15478 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15479 if (head == NULL)
f6e32f6d 15480 return FALSE;
f6e32f6d
RS		 15481 }
15482
15483 p = *head;
15484 if (p == NULL || p->sec != sec)
15485 {
15486 bfd_size_type amt = sizeof *p;
15487
15488 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15489 if (p == NULL)
15490 return FALSE;
15491 p->next = *head;
15492 *head = p;
15493 p->sec = sec;
15494 p->count = 0;
15495 p->pc_count = 0;
15496 }
15497
469a3493 15498 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15499 p->pc_count += 1;
15500 p->count += 1;
e8b09b87
CL		 15501 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15502 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15503 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15504 that will become rofixup. */
15505 /* This is due to the fact that we suppose all will become rofixup. */
15506 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15507 _bfd_error_handler
15508 (_("FDPIC does not yet support %s relocation"
15509 " to become dynamic for executable"),
15510 elf32_arm_howto_table_1[r_type].name);
15511 abort();
15512 }
f6e32f6d 15513 }
252b5132 15514 }
f21f3fe0 15515
b34976b6 15516 return TRUE;
252b5132
RH		 15517}
15518
9eaff861
AO		 15519static void
15520elf32_arm_update_relocs (asection *o,
15521 struct bfd_elf_section_reloc_data *reldata)
15522{
15523 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15524 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15525 const struct elf_backend_data *bed;
15526 _arm_elf_section_data *eado;
15527 struct bfd_link_order *p;
15528 bfd_byte *erela_head, *erela;
15529 Elf_Internal_Rela *irela_head, *irela;
15530 Elf_Internal_Shdr *rel_hdr;
15531 bfd *abfd;
15532 unsigned int count;
15533
15534 eado = get_arm_elf_section_data (o);
15535
15536 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15537 return;
15538
15539 abfd = o->owner;
15540 bed = get_elf_backend_data (abfd);
15541 rel_hdr = reldata->hdr;
15542
15543 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15544 {
15545 swap_in = bed->s->swap_reloc_in;
15546 swap_out = bed->s->swap_reloc_out;
15547 }
15548 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15549 {
15550 swap_in = bed->s->swap_reloca_in;
15551 swap_out = bed->s->swap_reloca_out;
15552 }
15553 else
15554 abort ();
15555
15556 erela_head = rel_hdr->contents;
15557 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15558 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15559
15560 erela = erela_head;
15561 irela = irela_head;
15562 count = 0;
15563
15564 for (p = o->map_head.link_order; p; p = p->next)
15565 {
15566 if (p->type == bfd_section_reloc_link_order
15567 || p->type == bfd_symbol_reloc_link_order)
15568 {
15569 (*swap_in) (abfd, erela, irela);
15570 erela += rel_hdr->sh_entsize;
15571 irela++;
15572 count++;
15573 }
15574 else if (p->type == bfd_indirect_link_order)
15575 {
15576 struct bfd_elf_section_reloc_data *input_reldata;
15577 arm_unwind_table_edit *edit_list, *edit_tail;
15578 _arm_elf_section_data *eadi;
15579 bfd_size_type j;
15580 bfd_vma offset;
15581 asection *i;
15582
15583 i = p->u.indirect.section;
15584
15585 eadi = get_arm_elf_section_data (i);
15586 edit_list = eadi->u.exidx.unwind_edit_list;
15587 edit_tail = eadi->u.exidx.unwind_edit_tail;
15588 offset = o->vma + i->output_offset;
15589
15590 if (eadi->elf.rel.hdr &&
15591 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15592 input_reldata = &eadi->elf.rel;
15593 else if (eadi->elf.rela.hdr &&
15594 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15595 input_reldata = &eadi->elf.rela;
15596 else
15597 abort ();
15598
15599 if (edit_list)
15600 {
15601 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15602 {
15603 arm_unwind_table_edit *edit_node, *edit_next;
15604 bfd_vma bias;
c48182bf 15605 bfd_vma reloc_index;
9eaff861
AO		 15606
15607 (*swap_in) (abfd, erela, irela);
c48182bf 15608 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15609
15610 bias = 0;
15611 edit_node = edit_list;
15612 for (edit_next = edit_list;
c48182bf 15613 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15614 edit_next = edit_node->next)
15615 {
15616 bias++;
15617 edit_node = edit_next;
15618 }
15619
15620 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15621 || edit_node->index != reloc_index)
9eaff861
AO		 15622 {
15623 irela->r_offset -= bias * 8;
15624 irela++;
15625 count++;
15626 }
15627
15628 erela += rel_hdr->sh_entsize;
15629 }
15630
15631 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15632 {
15633 /* New relocation entity. */
15634 asection *text_sec = edit_tail->linked_section;
15635 asection *text_out = text_sec->output_section;
15636 bfd_vma exidx_offset = offset + i->size - 8;
15637
15638 irela->r_addend = 0;
15639 irela->r_offset = exidx_offset;
15640 irela->r_info = ELF32_R_INFO
15641 (text_out->target_index, R_ARM_PREL31);
15642 irela++;
15643 count++;
15644 }
15645 }
15646 else
15647 {
15648 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15649 {
15650 (*swap_in) (abfd, erela, irela);
15651 erela += rel_hdr->sh_entsize;
15652 irela++;
15653 }
15654
15655 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15656 }
15657 }
15658 }
15659
15660 reldata->count = count;
15661 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15662
15663 erela = erela_head;
15664 irela = irela_head;
15665 while (count > 0)
15666 {
15667 (*swap_out) (abfd, irela, erela);
15668 erela += rel_hdr->sh_entsize;
15669 irela++;
15670 count--;
15671 }
15672
15673 free (irela_head);
15674
15675 /* Hashes are no longer valid. */
15676 free (reldata->hashes);
15677 reldata->hashes = NULL;
15678}
15679
6a5bb875 15680/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15681 required if the corresponding code section is marked. Similarly, ARMv8-M
15682 secure entry functions can only be referenced by SG veneers which are
15683 created after the GC process. They need to be marked in case they reside in
15684 their own section (as would be the case if code was compiled with
15685 -ffunction-sections). */
6a5bb875
PB		 15686
15687static bfd_boolean
906e58ca
NC		 15688elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15689 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15690{
15691 bfd *sub;
15692 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15693 asection *cmse_sec;
15694 obj_attribute *out_attr;
15695 Elf_Internal_Shdr *symtab_hdr;
15696 unsigned i, sym_count, ext_start;
15697 const struct elf_backend_data *bed;
15698 struct elf_link_hash_entry **sym_hashes;
15699 struct elf32_arm_link_hash_entry *cmse_hash;
15700 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15701
7f6ab9f8
AM		 15702 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15703
4ba2ef8f
TP		 15704 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15705 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15706 && out_attr[Tag_CPU_arch_profile].i == 'M';
15707
6a5bb875
PB		 15708 /* Marking EH data may cause additional code sections to be marked,
15709 requiring multiple passes. */
15710 again = TRUE;
15711 while (again)
15712 {
15713 again = FALSE;
c72f2fb2 15714 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15715 {
15716 asection *o;
15717
0ffa91dd 15718 if (! is_arm_elf (sub))
6a5bb875
PB		 15719 continue;
15720
15721 elf_shdrp = elf_elfsections (sub);
15722 for (o = sub->sections; o != NULL; o = o->next)
15723 {
15724 Elf_Internal_Shdr *hdr;
0ffa91dd 15725
6a5bb875 15726 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15727 if (hdr->sh_type == SHT_ARM_EXIDX
15728 && hdr->sh_link
15729 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15730 && !o->gc_mark
15731 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15732 {
15733 again = TRUE;
15734 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15735 return FALSE;
15736 }
15737 }
4ba2ef8f
TP		 15738
15739 /* Mark section holding ARMv8-M secure entry functions. We mark all
15740 of them so no need for a second browsing. */
15741 if (is_v8m && first_bfd_browse)
15742 {
15743 sym_hashes = elf_sym_hashes (sub);
15744 bed = get_elf_backend_data (sub);
15745 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15746 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15747 ext_start = symtab_hdr->sh_info;
15748
15749 /* Scan symbols. */
15750 for (i = ext_start; i < sym_count; i++)
15751 {
15752 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15753
15754 /* Assume it is a special symbol. If not, cmse_scan will
15755 warn about it and user can do something about it. */
15756 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15757 {
15758 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15759 if (!cmse_sec->gc_mark
15760 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15761 return FALSE;
15762 }
15763 }
15764 }
6a5bb875 15765 }
4ba2ef8f 15766 first_bfd_browse = FALSE;
6a5bb875
PB		 15767 }
15768
15769 return TRUE;
15770}
15771
3c9458e9
NC		 15772/* Treat mapping symbols as special target symbols. */
15773
15774static bfd_boolean
15775elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15776{
b0796911
PB		 15777 return bfd_is_arm_special_symbol_name (sym->name,
15778 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15779}
15780
0367ecfb
NC		 15781/* This is a copy of elf_find_function() from elf.c except that
15782 ARM mapping symbols are ignored when looking for function names
15783 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15784
0367ecfb 15785static bfd_boolean
07d6d2b8 15786arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15787 asymbol ** symbols,
fb167eb2 15788 asection * section,
07d6d2b8 15789 bfd_vma offset,
0367ecfb
NC		 15790 const char ** filename_ptr,
15791 const char ** functionname_ptr)
15792{
15793 const char * filename = NULL;
15794 asymbol * func = NULL;
15795 bfd_vma low_func = 0;
15796 asymbol ** p;
252b5132
RH		 15797
15798 for (p = symbols; *p != NULL; p++)
15799 {
15800 elf_symbol_type *q;
15801
15802 q = (elf_symbol_type *) *p;
15803
252b5132
RH		 15804 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15805 {
15806 default:
15807 break;
15808 case STT_FILE:
15809 filename = bfd_asymbol_name (&q->symbol);
15810 break;
252b5132
RH		 15811 case STT_FUNC:
15812 case STT_ARM_TFUNC:
9d2da7ca 15813 case STT_NOTYPE:
b0796911 15814 /* Skip mapping symbols. */
0367ecfb 15815 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15816 && bfd_is_arm_special_symbol_name (q->symbol.name,
15817 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15818 continue;
15819 /* Fall through. */
6b40fcba 15820 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15821 && q->symbol.value >= low_func
15822 && q->symbol.value <= offset)
15823 {
15824 func = (asymbol *) q;
15825 low_func = q->symbol.value;
15826 }
15827 break;
15828 }
15829 }
15830
15831 if (func == NULL)
b34976b6 15832 return FALSE;
252b5132 15833
0367ecfb
NC		 15834 if (filename_ptr)
15835 *filename_ptr = filename;
15836 if (functionname_ptr)
15837 *functionname_ptr = bfd_asymbol_name (func);
15838
15839 return TRUE;
906e58ca 15840}
0367ecfb
NC		 15841
15842
15843/* Find the nearest line to a particular section and offset, for error
15844 reporting. This code is a duplicate of the code in elf.c, except
15845 that it uses arm_elf_find_function. */
15846
15847static bfd_boolean
07d6d2b8
AM		 15848elf32_arm_find_nearest_line (bfd * abfd,
15849 asymbol ** symbols,
15850 asection * section,
15851 bfd_vma offset,
0367ecfb
NC		 15852 const char ** filename_ptr,
15853 const char ** functionname_ptr,
fb167eb2
AM		 15854 unsigned int * line_ptr,
15855 unsigned int * discriminator_ptr)
0367ecfb
NC		 15856{
15857 bfd_boolean found = FALSE;
15858
fb167eb2 15859 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15860 filename_ptr, functionname_ptr,
fb167eb2
AM		 15861 line_ptr, discriminator_ptr,
15862 dwarf_debug_sections, 0,
0367ecfb
NC		 15863 & elf_tdata (abfd)->dwarf2_find_line_info))
15864 {
15865 if (!*functionname_ptr)
fb167eb2 15866 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15867 *filename_ptr ? NULL : filename_ptr,
15868 functionname_ptr);
f21f3fe0 15869
0367ecfb
NC		 15870 return TRUE;
15871 }
15872
fb167eb2
AM		 15873 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15874 uses DWARF1. */
15875
0367ecfb
NC		 15876 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15877 & found, filename_ptr,
15878 functionname_ptr, line_ptr,
15879 & elf_tdata (abfd)->line_info))
15880 return FALSE;
15881
15882 if (found && (*functionname_ptr || *line_ptr))
15883 return TRUE;
15884
15885 if (symbols == NULL)
15886 return FALSE;
15887
fb167eb2 15888 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15889 filename_ptr, functionname_ptr))
15890 return FALSE;
15891
15892 *line_ptr = 0;
b34976b6 15893 return TRUE;
252b5132
RH		 15894}
15895
4ab527b0 15896static bfd_boolean
07d6d2b8 15897elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 15898 const char ** filename_ptr,
15899 const char ** functionname_ptr,
15900 unsigned int * line_ptr)
15901{
15902 bfd_boolean found;
15903 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15904 functionname_ptr, line_ptr,
15905 & elf_tdata (abfd)->dwarf2_find_line_info);
15906 return found;
15907}
15908
63c1f59d
AM		 15909/* Find dynamic relocs for H that apply to read-only sections. */
15910
15911static asection *
15912readonly_dynrelocs (struct elf_link_hash_entry *h)
15913{
15914 struct elf_dyn_relocs *p;
15915
15916 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
15917 {
15918 asection *s = p->sec->output_section;
15919
15920 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15921 return p->sec;
15922 }
15923 return NULL;
15924}
15925
252b5132
RH		 15926/* Adjust a symbol defined by a dynamic object and referenced by a
15927 regular object. The current definition is in some section of the
15928 dynamic object, but we're not including those sections. We have to
15929 change the definition to something the rest of the link can
15930 understand. */
15931
b34976b6 15932static bfd_boolean
57e8b36a
NC		 15933elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15934 struct elf_link_hash_entry * h)
252b5132
RH		 15935{
15936 bfd * dynobj;
5474d94f 15937 asection *s, *srel;
b7693d02 15938 struct elf32_arm_link_hash_entry * eh;
67687978 15939 struct elf32_arm_link_hash_table *globals;
252b5132 15940
67687978 15941 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15942 if (globals == NULL)
15943 return FALSE;
15944
252b5132
RH		 15945 dynobj = elf_hash_table (info)->dynobj;
15946
15947 /* Make sure we know what is going on here. */
15948 BFD_ASSERT (dynobj != NULL
f5385ebf 15949 && (h->needs_plt
34e77a92 15950 || h->type == STT_GNU_IFUNC
60d67dc8 15951 || h->is_weakalias
f5385ebf
AM		 15952 || (h->def_dynamic
15953 && h->ref_regular
15954 && !h->def_regular)));
252b5132 15955
b7693d02
DJ		 15956 eh = (struct elf32_arm_link_hash_entry *) h;
15957
252b5132
RH		 15958 /* If this is a function, put it in the procedure linkage table. We
15959 will fill in the contents of the procedure linkage table later,
15960 when we know the address of the .got section. */
34e77a92 15961 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15962 {
34e77a92
RS		 15963 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15964 symbol binds locally. */
5e681ec4 15965 if (h->plt.refcount <= 0
34e77a92
RS		 15966 || (h->type != STT_GNU_IFUNC
15967 && (SYMBOL_CALLS_LOCAL (info, h)
15968 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15969 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15970 {
15971 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15972 file, but the symbol was never referred to by a dynamic
15973 object, or if all references were garbage collected. In
15974 such a case, we don't actually need to build a procedure
15975 linkage table, and we can just do a PC24 reloc instead. */
15976 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15977 eh->plt.thumb_refcount = 0;
15978 eh->plt.maybe_thumb_refcount = 0;
15979 eh->plt.noncall_refcount = 0;
f5385ebf 15980 h->needs_plt = 0;
252b5132
RH		 15981 }
15982
b34976b6 15983 return TRUE;
252b5132 15984 }
5e681ec4 15985 else
b7693d02
DJ		 15986 {
15987 /* It's possible that we incorrectly decided a .plt reloc was
15988 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15989 in check_relocs. We can't decide accurately between function
15990 and non-function syms in check-relocs; Objects loaded later in
15991 the link may change h->type. So fix it now. */
15992 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15993 eh->plt.thumb_refcount = 0;
15994 eh->plt.maybe_thumb_refcount = 0;
15995 eh->plt.noncall_refcount = 0;
b7693d02 15996 }
252b5132
RH		 15997
15998 /* If this is a weak symbol, and there is a real definition, the
15999 processor independent code will have arranged for us to see the
16000 real definition first, and we can just use the same value. */
60d67dc8 16001 if (h->is_weakalias)
252b5132 16002 {
60d67dc8
AM		 16003 struct elf_link_hash_entry *def = weakdef (h);
16004 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16005 h->root.u.def.section = def->root.u.def.section;
16006 h->root.u.def.value = def->root.u.def.value;
b34976b6 16007 return TRUE;
252b5132
RH		 16008 }
16009
ba93b8ac
DJ		 16010 /* If there are no non-GOT references, we do not need a copy
16011 relocation. */
16012 if (!h->non_got_ref)
16013 return TRUE;
16014
252b5132
RH		 16015 /* This is a reference to a symbol defined by a dynamic object which
16016 is not a function. */
16017
16018 /* If we are creating a shared library, we must presume that the
16019 only references to the symbol are via the global offset table.
16020 For such cases we need not do anything here; the relocations will
67687978
PB		 16021 be handled correctly by relocate_section. Relocatable executables
16022 can reference data in shared objects directly, so we don't need to
16023 do anything here. */
0e1862bb 16024 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16025 return TRUE;
252b5132
RH		 16026
16027 /* We must allocate the symbol in our .dynbss section, which will
16028 become part of the .bss section of the executable. There will be
16029 an entry for this symbol in the .dynsym section. The dynamic
16030 object will contain position independent code, so all references
16031 from the dynamic object to this symbol will go through the global
16032 offset table. The dynamic linker will use the .dynsym entry to
16033 determine the address it must put in the global offset table, so
16034 both the dynamic object and the regular object will refer to the
16035 same memory location for the variable. */
5522f910
NC		 16036 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16037 linker to copy the initial value out of the dynamic object and into
16038 the runtime process image. We need to remember the offset into the
00a97672 16039 .rel(a).bss section we are going to use. */
5474d94f
AM		 16040 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16041 {
16042 s = globals->root.sdynrelro;
16043 srel = globals->root.sreldynrelro;
16044 }
16045 else
16046 {
16047 s = globals->root.sdynbss;
16048 srel = globals->root.srelbss;
16049 }
5522f910
NC		 16050 if (info->nocopyreloc == 0
16051 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16052 && h->size != 0)
252b5132 16053 {
47beaa6a 16054 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16055 h->needs_copy = 1;
252b5132
RH		 16056 }
16057
6cabe1ea 16058 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16059}
16060
5e681ec4
PB		 16061/* Allocate space in .plt, .got and associated reloc sections for
16062 dynamic relocs. */
16063
16064static bfd_boolean
47beaa6a 16065allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16066{
16067 struct bfd_link_info *info;
16068 struct elf32_arm_link_hash_table *htab;
16069 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16070 struct elf_dyn_relocs *p;
5e681ec4
PB		 16071
16072 if (h->root.type == bfd_link_hash_indirect)
16073 return TRUE;
16074
e6a6bb22
AM		 16075 eh = (struct elf32_arm_link_hash_entry *) h;
16076
5e681ec4
PB		 16077 info = (struct bfd_link_info *) inf;
16078 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16079 if (htab == NULL)
16080 return FALSE;
5e681ec4 16081
34e77a92 16082 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16083 && h->plt.refcount > 0)
16084 {
16085 /* Make sure this symbol is output as a dynamic symbol.
16086 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16087 if (h->dynindx == -1 && !h->forced_local
16088 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16089 {
c152c796 16090 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16091 return FALSE;
16092 }
16093
34e77a92
RS		 16094 /* If the call in the PLT entry binds locally, the associated
16095 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16096 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16097 than the .plt section. */
16098 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16099 {
16100 eh->is_iplt = 1;
16101 if (eh->plt.noncall_refcount == 0
16102 && SYMBOL_REFERENCES_LOCAL (info, h))
16103 /* All non-call references can be resolved directly.
16104 This means that they can (and in some cases, must)
16105 resolve directly to the run-time target, rather than
16106 to the PLT. That in turns means that any .got entry
16107 would be equal to the .igot.plt entry, so there's
16108 no point having both. */
16109 h->got.refcount = 0;
16110 }
16111
0e1862bb 16112 if (bfd_link_pic (info)
34e77a92 16113 || eh->is_iplt
7359ea65 16114 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16115 {
34e77a92 16116 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16117
5e681ec4
PB		 16118 /* If this symbol is not defined in a regular file, and we are
16119 not generating a shared library, then set the symbol to this
16120 location in the .plt. This is required to make function
16121 pointers compare as equal between the normal executable and
16122 the shared library. */
0e1862bb 16123 if (! bfd_link_pic (info)
f5385ebf 16124 && !h->def_regular)
5e681ec4 16125 {
34e77a92 16126 h->root.u.def.section = htab->root.splt;
5e681ec4 16127 h->root.u.def.value = h->plt.offset;
5e681ec4 16128
67d74e43
DJ		 16129 /* Make sure the function is not marked as Thumb, in case
16130 it is the target of an ABS32 relocation, which will
16131 point to the PLT entry. */
39d911fc 16132 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16133 }
022f8312 16134
00a97672
RS		 16135 /* VxWorks executables have a second set of relocations for
16136 each PLT entry. They go in a separate relocation section,
16137 which is processed by the kernel loader. */
0e1862bb 16138 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16139 {
16140 /* There is a relocation for the initial PLT entry:
16141 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16142 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16143 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16144
16145 /* There are two extra relocations for each subsequent
16146 PLT entry: an R_ARM_32 relocation for the GOT entry,
16147 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16148 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16149 }
5e681ec4
PB		 16150 }
16151 else
16152 {
16153 h->plt.offset = (bfd_vma) -1;
f5385ebf 16154 h->needs_plt = 0;
5e681ec4
PB		 16155 }
16156 }
16157 else
16158 {
16159 h->plt.offset = (bfd_vma) -1;
f5385ebf 16160 h->needs_plt = 0;
5e681ec4
PB		 16161 }
16162
0855e32b
NS		 16163 eh = (struct elf32_arm_link_hash_entry *) h;
16164 eh->tlsdesc_got = (bfd_vma) -1;
16165
5e681ec4
PB		 16166 if (h->got.refcount > 0)
16167 {
16168 asection *s;
16169 bfd_boolean dyn;
ba93b8ac
DJ		 16170 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16171 int indx;
5e681ec4
PB		 16172
16173 /* Make sure this symbol is output as a dynamic symbol.
16174 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16175 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16176 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16177 {
c152c796 16178 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16179 return FALSE;
16180 }
16181
e5a52504
MM		 16182 if (!htab->symbian_p)
16183 {
362d30a1 16184 s = htab->root.sgot;
e5a52504 16185 h->got.offset = s->size;
ba93b8ac
DJ		 16186
16187 if (tls_type == GOT_UNKNOWN)
16188 abort ();
16189
16190 if (tls_type == GOT_NORMAL)
16191 /* Non-TLS symbols need one GOT slot. */
16192 s->size += 4;
16193 else
16194 {
99059e56
RM		 16195 if (tls_type & GOT_TLS_GDESC)
16196 {
0855e32b 16197 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16198 eh->tlsdesc_got
0855e32b
NS		 16199 = (htab->root.sgotplt->size
16200 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16201 htab->root.sgotplt->size += 8;
16202 h->got.offset = (bfd_vma) -2;
34e77a92 16203 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16204 reloc in the middle of .got.plt. */
99059e56
RM		 16205 htab->num_tls_desc++;
16206 }
0855e32b 16207
ba93b8ac 16208 if (tls_type & GOT_TLS_GD)
0855e32b 16209 {
5c5a4843
CL		 16210 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16211 consecutive GOT slots. If the symbol is both GD
16212 and GDESC, got.offset may have been
16213 overwritten. */
0855e32b
NS		 16214 h->got.offset = s->size;
16215 s->size += 8;
16216 }
16217
ba93b8ac 16218 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16219 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16220 slot. */
ba93b8ac
DJ		 16221 s->size += 4;
16222 }
16223
e5a52504 16224 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16225
16226 indx = 0;
0e1862bb
L		 16227 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16228 bfd_link_pic (info),
16229 h)
16230 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16231 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16232 indx = h->dynindx;
16233
16234 if (tls_type != GOT_NORMAL
0e1862bb 16235 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 16236 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16237 || h->root.type != bfd_link_hash_undefweak))
16238 {
16239 if (tls_type & GOT_TLS_IE)
47beaa6a 16240 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16241
16242 if (tls_type & GOT_TLS_GD)
47beaa6a 16243 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16244
b38cadfb 16245 if (tls_type & GOT_TLS_GDESC)
0855e32b 16246 {
47beaa6a 16247 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16248 /* GDESC needs a trampoline to jump to. */
16249 htab->tls_trampoline = -1;
16250 }
16251
16252 /* Only GD needs it. GDESC just emits one relocation per
16253 2 entries. */
b38cadfb 16254 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16255 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16256 }
e8b09b87
CL		 16257 else if (((indx != -1) || htab->fdpic_p)
16258 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16259 {
16260 if (htab->root.dynamic_sections_created)
16261 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16262 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16263 }
34e77a92
RS		 16264 else if (h->type == STT_GNU_IFUNC
16265 && eh->plt.noncall_refcount == 0)
16266 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16267 they all resolve dynamically instead. Reserve room for the
16268 GOT entry's R_ARM_IRELATIVE relocation. */
16269 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 16270 else if (bfd_link_pic (info)
16271 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16272 || h->root.type != bfd_link_hash_undefweak))
b436d854 16273 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16274 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16275 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16276 /* Reserve room for rofixup for FDPIC executable. */
16277 /* TLS relocs do not need space since they are completely
16278 resolved. */
16279 htab->srofixup->size += 4;
e5a52504 16280 }
5e681ec4
PB		 16281 }
16282 else
16283 h->got.offset = (bfd_vma) -1;
16284
e8b09b87
CL		 16285 /* FDPIC support. */
16286 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16287 {
16288 /* Symbol musn't be exported. */
16289 if (h->dynindx != -1)
16290 abort();
16291
16292 /* We only allocate one function descriptor with its associated relocation. */
16293 if (eh->fdpic_cnts.funcdesc_offset == -1)
16294 {
16295 asection *s = htab->root.sgot;
16296
16297 eh->fdpic_cnts.funcdesc_offset = s->size;
16298 s->size += 8;
16299 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16300 if (bfd_link_pic(info))
16301 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16302 else
16303 htab->srofixup->size += 8;
16304 }
16305 }
16306
16307 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16308 {
16309 asection *s = htab->root.sgot;
16310
16311 if (htab->root.dynamic_sections_created && h->dynindx == -1
16312 && !h->forced_local)
16313 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16314 return FALSE;
16315
16316 if (h->dynindx == -1)
16317 {
16318 /* We only allocate one function descriptor with its associated relocation. q */
16319 if (eh->fdpic_cnts.funcdesc_offset == -1)
16320 {
16321
16322 eh->fdpic_cnts.funcdesc_offset = s->size;
16323 s->size += 8;
16324 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16325 if (bfd_link_pic(info))
16326 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16327 else
16328 htab->srofixup->size += 8;
16329 }
16330 }
16331
16332 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16333 R_ARM_RELATIVE/rofixup relocation on it. */
16334 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16335 s->size += 4;
16336 if (h->dynindx == -1 && !bfd_link_pic(info))
16337 htab->srofixup->size += 4;
16338 else
16339 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16340 }
16341
16342 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16343 {
16344 if (htab->root.dynamic_sections_created && h->dynindx == -1
16345 && !h->forced_local)
16346 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16347 return FALSE;
16348
16349 if (h->dynindx == -1)
16350 {
16351 /* We only allocate one function descriptor with its associated relocation. */
16352 if (eh->fdpic_cnts.funcdesc_offset == -1)
16353 {
16354 asection *s = htab->root.sgot;
16355
16356 eh->fdpic_cnts.funcdesc_offset = s->size;
16357 s->size += 8;
16358 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16359 if (bfd_link_pic(info))
16360 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16361 else
16362 htab->srofixup->size += 8;
16363 }
16364 }
16365 if (h->dynindx == -1 && !bfd_link_pic(info))
16366 {
16367 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16368 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16369 }
16370 else
16371 {
16372 /* Will need one dynamic reloc per reference. will be either
16373 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16374 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16375 eh->fdpic_cnts.funcdesc_cnt);
16376 }
16377 }
16378
a4fd1a8e
PB		 16379 /* Allocate stubs for exported Thumb functions on v4t. */
16380 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16381 && h->def_regular
39d911fc 16382 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16383 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16384 {
16385 struct elf_link_hash_entry * th;
16386 struct bfd_link_hash_entry * bh;
16387 struct elf_link_hash_entry * myh;
16388 char name[1024];
16389 asection *s;
16390 bh = NULL;
16391 /* Create a new symbol to regist the real location of the function. */
16392 s = h->root.u.def.section;
906e58ca 16393 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16394 _bfd_generic_link_add_one_symbol (info, s->owner,
16395 name, BSF_GLOBAL, s,
16396 h->root.u.def.value,
16397 NULL, TRUE, FALSE, &bh);
16398
16399 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16400 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16401 myh->forced_local = 1;
39d911fc 16402 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16403 eh->export_glue = myh;
16404 th = record_arm_to_thumb_glue (info, h);
16405 /* Point the symbol at the stub. */
16406 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16407 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16408 h->root.u.def.section = th->root.u.def.section;
16409 h->root.u.def.value = th->root.u.def.value & ~1;
16410 }
16411
0bdcacaf 16412 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16413 return TRUE;
16414
16415 /* In the shared -Bsymbolic case, discard space allocated for
16416 dynamic pc-relative relocs against symbols which turn out to be
16417 defined in regular objects. For the normal shared case, discard
16418 space for pc-relative relocs that have become local due to symbol
16419 visibility changes. */
16420
e8b09b87 16421 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16422 {
469a3493
RM		 16423 /* Relocs that use pc_count are PC-relative forms, which will appear
16424 on something like ".long foo - ." or "movw REG, foo - .". We want
16425 calls to protected symbols to resolve directly to the function
16426 rather than going via the plt. If people want function pointer
16427 comparisons to work as expected then they should avoid writing
16428 assembly like ".long foo - .". */
ba93b8ac
DJ		 16429 if (SYMBOL_CALLS_LOCAL (info, h))
16430 {
0bdcacaf 16431 struct elf_dyn_relocs **pp;
ba93b8ac 16432
0bdcacaf 16433 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16434 {
16435 p->count -= p->pc_count;
16436 p->pc_count = 0;
16437 if (p->count == 0)
16438 *pp = p->next;
16439 else
16440 pp = &p->next;
16441 }
16442 }
16443
4dfe6ac6 16444 if (htab->vxworks_p)
3348747a 16445 {
0bdcacaf 16446 struct elf_dyn_relocs **pp;
3348747a 16447
0bdcacaf 16448 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16449 {
0bdcacaf 16450 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16451 *pp = p->next;
16452 else
16453 pp = &p->next;
16454 }
16455 }
16456
ba93b8ac 16457 /* Also discard relocs on undefined weak syms with non-default
99059e56 16458 visibility. */
0bdcacaf 16459 if (eh->dyn_relocs != NULL
5e681ec4 16460 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16461 {
95b03e4a
L		 16462 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16463 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16464 eh->dyn_relocs = NULL;
22d606e9
AM		 16465
16466 /* Make sure undefined weak symbols are output as a dynamic
16467 symbol in PIEs. */
e8b09b87 16468 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16469 && !h->forced_local)
16470 {
16471 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16472 return FALSE;
16473 }
16474 }
16475
67687978
PB		 16476 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16477 && h->root.type == bfd_link_hash_new)
16478 {
16479 /* Output absolute symbols so that we can create relocations
16480 against them. For normal symbols we output a relocation
16481 against the section that contains them. */
16482 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16483 return FALSE;
16484 }
16485
5e681ec4
PB		 16486 }
16487 else
16488 {
16489 /* For the non-shared case, discard space for relocs against
16490 symbols which turn out to need copy relocs or are not
16491 dynamic. */
16492
f5385ebf
AM		 16493 if (!h->non_got_ref
16494 && ((h->def_dynamic
16495 && !h->def_regular)
5e681ec4
PB		 16496 || (htab->root.dynamic_sections_created
16497 && (h->root.type == bfd_link_hash_undefweak
16498 || h->root.type == bfd_link_hash_undefined))))
16499 {
16500 /* Make sure this symbol is output as a dynamic symbol.
16501 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16502 if (h->dynindx == -1 && !h->forced_local
16503 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16504 {
c152c796 16505 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16506 return FALSE;
16507 }
16508
16509 /* If that succeeded, we know we'll be keeping all the
16510 relocs. */
16511 if (h->dynindx != -1)
16512 goto keep;
16513 }
16514
0bdcacaf 16515 eh->dyn_relocs = NULL;
5e681ec4
PB		 16516
16517 keep: ;
16518 }
16519
16520 /* Finally, allocate space. */
0bdcacaf 16521 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16522 {
0bdcacaf 16523 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16524
34e77a92
RS		 16525 if (h->type == STT_GNU_IFUNC
16526 && eh->plt.noncall_refcount == 0
16527 && SYMBOL_REFERENCES_LOCAL (info, h))
16528 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16529 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16530 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16531 else if (htab->fdpic_p && !bfd_link_pic(info))
16532 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16533 else
16534 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16535 }
16536
16537 return TRUE;
16538}
16539
63c1f59d
AM		 16540/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16541 read-only sections. */
08d1f311
DJ		 16542
16543static bfd_boolean
63c1f59d 16544maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16545{
63c1f59d 16546 asection *sec;
08d1f311 16547
63c1f59d
AM		 16548 if (h->root.type == bfd_link_hash_indirect)
16549 return TRUE;
08d1f311 16550
63c1f59d
AM		 16551 sec = readonly_dynrelocs (h);
16552 if (sec != NULL)
16553 {
16554 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16555
63c1f59d
AM		 16556 info->flags |= DF_TEXTREL;
16557 info->callbacks->minfo
c1c8c1ef 16558 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16559 sec->owner, h->root.root.string, sec);
08d1f311 16560
63c1f59d
AM		 16561 /* Not an error, just cut short the traversal. */
16562 return FALSE;
08d1f311 16563 }
cb10292c 16564
08d1f311
DJ		 16565 return TRUE;
16566}
16567
d504ffc8
DJ		 16568void
16569bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16570 int byteswap_code)
16571{
16572 struct elf32_arm_link_hash_table *globals;
16573
16574 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16575 if (globals == NULL)
16576 return;
16577
d504ffc8
DJ		 16578 globals->byteswap_code = byteswap_code;
16579}
16580
252b5132
RH		 16581/* Set the sizes of the dynamic sections. */
16582
b34976b6 16583static bfd_boolean
57e8b36a
NC		 16584elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16585 struct bfd_link_info * info)
252b5132
RH		 16586{
16587 bfd * dynobj;
16588 asection * s;
b34976b6
AM		 16589 bfd_boolean plt;
16590 bfd_boolean relocs;
5e681ec4
PB		 16591 bfd *ibfd;
16592 struct elf32_arm_link_hash_table *htab;
252b5132 16593
5e681ec4 16594 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16595 if (htab == NULL)
16596 return FALSE;
16597
252b5132
RH		 16598 dynobj = elf_hash_table (info)->dynobj;
16599 BFD_ASSERT (dynobj != NULL);
39b41c9c 16600 check_use_blx (htab);
252b5132
RH		 16601
16602 if (elf_hash_table (info)->dynamic_sections_created)
16603 {
16604 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16605 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16606 {
3d4d4302 16607 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16608 BFD_ASSERT (s != NULL);
eea6121a 16609 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16610 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16611 }
16612 }
5e681ec4
PB		 16613
16614 /* Set up .got offsets for local syms, and space for local dynamic
16615 relocs. */
c72f2fb2 16616 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16617 {
5e681ec4
PB		 16618 bfd_signed_vma *local_got;
16619 bfd_signed_vma *end_local_got;
34e77a92 16620 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16621 char *local_tls_type;
0855e32b 16622 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16623 bfd_size_type locsymcount;
16624 Elf_Internal_Shdr *symtab_hdr;
16625 asection *srel;
4dfe6ac6 16626 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16627 unsigned int symndx;
e8b09b87 16628 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16629
0ffa91dd 16630 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16631 continue;
16632
16633 for (s = ibfd->sections; s != NULL; s = s->next)
16634 {
0bdcacaf 16635 struct elf_dyn_relocs *p;
5e681ec4 16636
0bdcacaf 16637 for (p = (struct elf_dyn_relocs *)
99059e56 16638 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16639 {
0bdcacaf
RS		 16640 if (!bfd_is_abs_section (p->sec)
16641 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16642 {
16643 /* Input section has been discarded, either because
16644 it is a copy of a linkonce section or due to
16645 linker script /DISCARD/, so we'll be discarding
16646 the relocs too. */
16647 }
3348747a 16648 else if (is_vxworks
0bdcacaf 16649 && strcmp (p->sec->output_section->name,
3348747a
NS		 16650 ".tls_vars") == 0)
16651 {
16652 /* Relocations in vxworks .tls_vars sections are
16653 handled specially by the loader. */
16654 }
5e681ec4
PB		 16655 else if (p->count != 0)
16656 {
0bdcacaf 16657 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16658 if (htab->fdpic_p && !bfd_link_pic(info))
16659 htab->srofixup->size += 4 * p->count;
16660 else
16661 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16662 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16663 info->flags |= DF_TEXTREL;
16664 }
16665 }
16666 }
16667
16668 local_got = elf_local_got_refcounts (ibfd);
16669 if (!local_got)
16670 continue;
16671
0ffa91dd 16672 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16673 locsymcount = symtab_hdr->sh_info;
16674 end_local_got = local_got + locsymcount;
34e77a92 16675 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16676 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16677 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16678 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16679 symndx = 0;
362d30a1
RS		 16680 s = htab->root.sgot;
16681 srel = htab->root.srelgot;
0855e32b 16682 for (; local_got < end_local_got;
34e77a92 16683 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16684 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16685 {
0855e32b 16686 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16687 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16688
16689 /* FDPIC support. */
16690 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16691 {
16692 if (local_fdpic_cnts->funcdesc_offset == -1)
16693 {
16694 local_fdpic_cnts->funcdesc_offset = s->size;
16695 s->size += 8;
16696
16697 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16698 if (bfd_link_pic(info))
16699 elf32_arm_allocate_dynrelocs (info, srel, 1);
16700 else
16701 htab->srofixup->size += 8;
16702 }
16703 }
16704
16705 if (local_fdpic_cnts->funcdesc_cnt > 0)
16706 {
16707 if (local_fdpic_cnts->funcdesc_offset == -1)
16708 {
16709 local_fdpic_cnts->funcdesc_offset = s->size;
16710 s->size += 8;
16711
16712 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16713 if (bfd_link_pic(info))
16714 elf32_arm_allocate_dynrelocs (info, srel, 1);
16715 else
16716 htab->srofixup->size += 8;
16717 }
16718
16719 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16720 if (bfd_link_pic(info))
16721 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16722 else
16723 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16724 }
16725
34e77a92
RS		 16726 if (local_iplt != NULL)
16727 {
16728 struct elf_dyn_relocs *p;
16729
16730 if (local_iplt->root.refcount > 0)
16731 {
16732 elf32_arm_allocate_plt_entry (info, TRUE,
16733 &local_iplt->root,
16734 &local_iplt->arm);
16735 if (local_iplt->arm.noncall_refcount == 0)
16736 /* All references to the PLT are calls, so all
16737 non-call references can resolve directly to the
16738 run-time target. This means that the .got entry
16739 would be the same as the .igot.plt entry, so there's
16740 no point creating both. */
16741 *local_got = 0;
16742 }
16743 else
16744 {
16745 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16746 local_iplt->root.offset = (bfd_vma) -1;
16747 }
16748
16749 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16750 {
16751 asection *psrel;
16752
16753 psrel = elf_section_data (p->sec)->sreloc;
16754 if (local_iplt->arm.noncall_refcount == 0)
16755 elf32_arm_allocate_irelocs (info, psrel, p->count);
16756 else
16757 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16758 }
16759 }
5e681ec4
PB		 16760 if (*local_got > 0)
16761 {
34e77a92
RS		 16762 Elf_Internal_Sym *isym;
16763
eea6121a 16764 *local_got = s->size;
ba93b8ac
DJ		 16765 if (*local_tls_type & GOT_TLS_GD)
16766 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16767 s->size += 8;
0855e32b
NS		 16768 if (*local_tls_type & GOT_TLS_GDESC)
16769 {
16770 *local_tlsdesc_gotent = htab->root.sgotplt->size
16771 - elf32_arm_compute_jump_table_size (htab);
16772 htab->root.sgotplt->size += 8;
16773 *local_got = (bfd_vma) -2;
34e77a92 16774 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16775 reloc in the middle of .got.plt. */
99059e56 16776 htab->num_tls_desc++;
0855e32b 16777 }
ba93b8ac
DJ		 16778 if (*local_tls_type & GOT_TLS_IE)
16779 s->size += 4;
ba93b8ac 16780
0855e32b
NS		 16781 if (*local_tls_type & GOT_NORMAL)
16782 {
16783 /* If the symbol is both GD and GDESC, *local_got
16784 may have been overwritten. */
16785 *local_got = s->size;
16786 s->size += 4;
16787 }
16788
34e77a92
RS		 16789 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
16790 if (isym == NULL)
16791 return FALSE;
16792
16793 /* If all references to an STT_GNU_IFUNC PLT are calls,
16794 then all non-call references, including this GOT entry,
16795 resolve directly to the run-time target. */
16796 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16797 && (local_iplt == NULL
16798 || local_iplt->arm.noncall_refcount == 0))
16799 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16800 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16801 {
e8b09b87 16802 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16803 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16804 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16805 htab->srofixup->size += 4;
99059e56 16806
e8b09b87
CL		 16807 if ((bfd_link_pic (info) || htab->fdpic_p)
16808 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16809 {
16810 elf32_arm_allocate_dynrelocs (info,
16811 htab->root.srelplt, 1);
16812 htab->tls_trampoline = -1;
16813 }
0855e32b 16814 }
5e681ec4
PB		 16815 }
16816 else
16817 *local_got = (bfd_vma) -1;
16818 }
252b5132
RH		 16819 }
16820
ba93b8ac
DJ		 16821 if (htab->tls_ldm_got.refcount > 0)
16822 {
16823 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 16824 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 16825 htab->tls_ldm_got.offset = htab->root.sgot->size;
16826 htab->root.sgot->size += 8;
0e1862bb 16827 if (bfd_link_pic (info))
47beaa6a 16828 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16829 }
16830 else
16831 htab->tls_ldm_got.offset = -1;
16832
e8b09b87
CL		 16833 /* At the very end of the .rofixup section is a pointer to the GOT,
16834 reserve space for it. */
16835 if (htab->fdpic_p && htab->srofixup != NULL)
16836 htab->srofixup->size += 4;
16837
5e681ec4
PB		 16838 /* Allocate global sym .plt and .got entries, and space for global
16839 sym dynamic relocs. */
47beaa6a 16840 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16841
d504ffc8 16842 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16843 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16844 {
0ffa91dd 16845 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16846 continue;
16847
c7b8f16e
JB		 16848 /* Initialise mapping tables for code/data. */
16849 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16850
c7b8f16e 16851 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16852 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16853 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 16854 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 16855 }
d504ffc8 16856
3e6b1042
DJ		 16857 /* Allocate space for the glue sections now that we've sized them. */
16858 bfd_elf32_arm_allocate_interworking_sections (info);
16859
0855e32b
NS		 16860 /* For every jump slot reserved in the sgotplt, reloc_count is
16861 incremented. However, when we reserve space for TLS descriptors,
16862 it's not incremented, so in order to compute the space reserved
16863 for them, it suffices to multiply the reloc count by the jump
16864 slot size. */
16865 if (htab->root.srelplt)
16866 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16867
16868 if (htab->tls_trampoline)
16869 {
16870 if (htab->root.splt->size == 0)
16871 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16872
0855e32b
NS		 16873 htab->tls_trampoline = htab->root.splt->size;
16874 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16875
0855e32b 16876 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16877 PLT and GOT entries they require. */
0855e32b
NS		 16878 if (!(info->flags & DF_BIND_NOW))
16879 {
16880 htab->dt_tlsdesc_got = htab->root.sgot->size;
16881 htab->root.sgot->size += 4;
16882
16883 htab->dt_tlsdesc_plt = htab->root.splt->size;
16884 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16885 }
16886 }
16887
252b5132
RH		 16888 /* The check_relocs and adjust_dynamic_symbol entry points have
16889 determined the sizes of the various dynamic sections. Allocate
16890 memory for them. */
b34976b6
AM		 16891 plt = FALSE;
16892 relocs = FALSE;
252b5132
RH		 16893 for (s = dynobj->sections; s != NULL; s = s->next)
16894 {
16895 const char * name;
252b5132
RH		 16896
16897 if ((s->flags & SEC_LINKER_CREATED) == 0)
16898 continue;
16899
16900 /* It's OK to base decisions on the section name, because none
16901 of the dynobj section names depend upon the input files. */
16902 name = bfd_get_section_name (dynobj, s);
16903
34e77a92 16904 if (s == htab->root.splt)
252b5132 16905 {
c456f082
AM		 16906 /* Remember whether there is a PLT. */
16907 plt = s->size != 0;
252b5132 16908 }
0112cd26 16909 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16910 {
c456f082 16911 if (s->size != 0)
252b5132 16912 {
252b5132 16913 /* Remember whether there are any reloc sections other
00a97672 16914 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16915 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16916 relocs = TRUE;
252b5132
RH		 16917
16918 /* We use the reloc_count field as a counter if we need
16919 to copy relocs into the output file. */
16920 s->reloc_count = 0;
16921 }
16922 }
34e77a92
RS		 16923 else if (s != htab->root.sgot
16924 && s != htab->root.sgotplt
16925 && s != htab->root.iplt
16926 && s != htab->root.igotplt
5474d94f 16927 && s != htab->root.sdynbss
e8b09b87
CL		 16928 && s != htab->root.sdynrelro
16929 && s != htab->srofixup)
252b5132
RH		 16930 {
16931 /* It's not one of our sections, so don't allocate space. */
16932 continue;
16933 }
16934
c456f082 16935 if (s->size == 0)
252b5132 16936 {
c456f082 16937 /* If we don't need this section, strip it from the
00a97672
RS		 16938 output file. This is mostly to handle .rel(a).bss and
16939 .rel(a).plt. We must create both sections in
c456f082
AM		 16940 create_dynamic_sections, because they must be created
16941 before the linker maps input sections to output
16942 sections. The linker does that before
16943 adjust_dynamic_symbol is called, and it is that
16944 function which decides whether anything needs to go
16945 into these sections. */
8423293d 16946 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16947 continue;
16948 }
16949
c456f082
AM		 16950 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16951 continue;
16952
252b5132 16953 /* Allocate memory for the section contents. */
21d799b5 16954 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16955 if (s->contents == NULL)
b34976b6 16956 return FALSE;
252b5132
RH		 16957 }
16958
16959 if (elf_hash_table (info)->dynamic_sections_created)
16960 {
16961 /* Add some entries to the .dynamic section. We fill in the
16962 values later, in elf32_arm_finish_dynamic_sections, but we
16963 must add the entries now so that we get the correct size for
16964 the .dynamic section. The DT_DEBUG entry is filled in by the
16965 dynamic linker and used by the debugger. */
dc810e39 16966#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16967 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16968
0e1862bb 16969 if (bfd_link_executable (info))
252b5132 16970 {
dc810e39 16971 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16972 return FALSE;
252b5132
RH		 16973 }
16974
16975 if (plt)
16976 {
dc810e39
AM		 16977 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16978 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16979 || !add_dynamic_entry (DT_PLTREL,
16980 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16981 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16982 return FALSE;
0855e32b 16983
5025eb7c
AO		 16984 if (htab->dt_tlsdesc_plt
16985 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16986 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16987 return FALSE;
252b5132
RH		 16988 }
16989
16990 if (relocs)
16991 {
00a97672
RS		 16992 if (htab->use_rel)
16993 {
16994 if (!add_dynamic_entry (DT_REL, 0)
16995 || !add_dynamic_entry (DT_RELSZ, 0)
16996 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16997 return FALSE;
16998 }
16999 else
17000 {
17001 if (!add_dynamic_entry (DT_RELA, 0)
17002 || !add_dynamic_entry (DT_RELASZ, 0)
17003 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17004 return FALSE;
17005 }
252b5132
RH		 17006 }
17007
08d1f311
DJ		 17008 /* If any dynamic relocs apply to a read-only section,
17009 then we need a DT_TEXTREL entry. */
17010 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17011 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17012
99e4ae17 17013 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17014 {
dc810e39 17015 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17016 return FALSE;
252b5132 17017 }
7a2b07ff
NS		 17018 if (htab->vxworks_p
17019 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17020 return FALSE;
252b5132 17021 }
8532796c 17022#undef add_dynamic_entry
252b5132 17023
b34976b6 17024 return TRUE;
252b5132
RH		 17025}
17026
0855e32b
NS		 17027/* Size sections even though they're not dynamic. We use it to setup
17028 _TLS_MODULE_BASE_, if needed. */
17029
17030static bfd_boolean
17031elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17032 struct bfd_link_info *info)
0855e32b
NS		 17033{
17034 asection *tls_sec;
cb10292c
CL		 17035 struct elf32_arm_link_hash_table *htab;
17036
17037 htab = elf32_arm_hash_table (info);
0855e32b 17038
0e1862bb 17039 if (bfd_link_relocatable (info))
0855e32b
NS		 17040 return TRUE;
17041
17042 tls_sec = elf_hash_table (info)->tls_sec;
17043
17044 if (tls_sec)
17045 {
17046 struct elf_link_hash_entry *tlsbase;
17047
17048 tlsbase = elf_link_hash_lookup
17049 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17050
17051 if (tlsbase)
99059e56
RM		 17052 {
17053 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17054 const struct elf_backend_data *bed
99059e56 17055 = get_elf_backend_data (output_bfd);
0855e32b 17056
99059e56 17057 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17058 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17059 tls_sec, 0, NULL, FALSE,
17060 bed->collect, &bh)))
17061 return FALSE;
b38cadfb 17062
99059e56
RM		 17063 tlsbase->type = STT_TLS;
17064 tlsbase = (struct elf_link_hash_entry *)bh;
17065 tlsbase->def_regular = 1;
17066 tlsbase->other = STV_HIDDEN;
17067 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17068 }
17069 }
cb10292c
CL		 17070
17071 if (htab->fdpic_p && !bfd_link_relocatable (info)
17072 && !bfd_elf_stack_segment_size (output_bfd, info,
17073 "__stacksize", DEFAULT_STACK_SIZE))
17074 return FALSE;
17075
0855e32b
NS		 17076 return TRUE;
17077}
17078
252b5132
RH		 17079/* Finish up dynamic symbol handling. We set the contents of various
17080 dynamic sections here. */
17081
b34976b6 17082static bfd_boolean
906e58ca
NC		 17083elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17084 struct bfd_link_info * info,
17085 struct elf_link_hash_entry * h,
17086 Elf_Internal_Sym * sym)
252b5132 17087{
e5a52504 17088 struct elf32_arm_link_hash_table *htab;
b7693d02 17089 struct elf32_arm_link_hash_entry *eh;
252b5132 17090
e5a52504 17091 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17092 if (htab == NULL)
17093 return FALSE;
17094
b7693d02 17095 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17096
17097 if (h->plt.offset != (bfd_vma) -1)
17098 {
34e77a92 17099 if (!eh->is_iplt)
e5a52504 17100 {
34e77a92 17101 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17102 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17103 h->dynindx, 0))
17104 return FALSE;
e5a52504 17105 }
57e8b36a 17106
f5385ebf 17107 if (!h->def_regular)
252b5132
RH		 17108 {
17109 /* Mark the symbol as undefined, rather than as defined in
3a635617 17110 the .plt section. */
252b5132 17111 sym->st_shndx = SHN_UNDEF;
3a635617 17112 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17113 Otherwise, the PLT entry would provide a definition for
17114 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17115 and so the symbol would never be NULL. Leave the value if
17116 there were any relocations where pointer equality matters
17117 (this is a clue for the dynamic linker, to make function
17118 pointer comparisons work between an application and shared
17119 library). */
97323ad1 17120 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17121 sym->st_value = 0;
252b5132 17122 }
34e77a92
RS		 17123 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17124 {
17125 /* At least one non-call relocation references this .iplt entry,
17126 so the .iplt entry is the function's canonical address. */
17127 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17128 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17129 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17130 (output_bfd, htab->root.iplt->output_section));
17131 sym->st_value = (h->plt.offset
17132 + htab->root.iplt->output_section->vma
17133 + htab->root.iplt->output_offset);
17134 }
252b5132
RH		 17135 }
17136
f5385ebf 17137 if (h->needs_copy)
252b5132
RH		 17138 {
17139 asection * s;
947216bf 17140 Elf_Internal_Rela rel;
252b5132
RH		 17141
17142 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17143 BFD_ASSERT (h->dynindx != -1
17144 && (h->root.type == bfd_link_hash_defined
17145 || h->root.type == bfd_link_hash_defweak));
17146
00a97672 17147 rel.r_addend = 0;
252b5132
RH		 17148 rel.r_offset = (h->root.u.def.value
17149 + h->root.u.def.section->output_section->vma
17150 + h->root.u.def.section->output_offset);
17151 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17152 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17153 s = htab->root.sreldynrelro;
17154 else
17155 s = htab->root.srelbss;
47beaa6a 17156 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17157 }
17158
00a97672 17159 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17160 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17161 it is relative to the ".got" section. */
9637f6ef 17162 if (h == htab->root.hdynamic
fac7bd64 17163 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17164 sym->st_shndx = SHN_ABS;
17165
b34976b6 17166 return TRUE;
252b5132
RH		 17167}
17168
0855e32b
NS		 17169static void
17170arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17171 void *contents,
17172 const unsigned long *template, unsigned count)
17173{
17174 unsigned ix;
b38cadfb 17175
0855e32b
NS		 17176 for (ix = 0; ix != count; ix++)
17177 {
17178 unsigned long insn = template[ix];
17179
17180 /* Emit mov pc,rx if bx is not permitted. */
17181 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17182 insn = (insn & 0xf000000f) | 0x01a0f000;
17183 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17184 }
17185}
17186
99059e56
RM		 17187/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17188 other variants, NaCl needs this entry in a static executable's
17189 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17190 zero. For .iplt really only the last bundle is useful, and .iplt
17191 could have a shorter first entry, with each individual PLT entry's
17192 relative branch calculated differently so it targets the last
17193 bundle instead of the instruction before it (labelled .Lplt_tail
17194 above). But it's simpler to keep the size and layout of PLT0
17195 consistent with the dynamic case, at the cost of some dead code at
17196 the start of .iplt and the one dead store to the stack at the start
17197 of .Lplt_tail. */
17198static void
17199arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17200 asection *plt, bfd_vma got_displacement)
17201{
17202 unsigned int i;
17203
17204 put_arm_insn (htab, output_bfd,
17205 elf32_arm_nacl_plt0_entry[0]
17206 | arm_movw_immediate (got_displacement),
17207 plt->contents + 0);
17208 put_arm_insn (htab, output_bfd,
17209 elf32_arm_nacl_plt0_entry[1]
17210 | arm_movt_immediate (got_displacement),
17211 plt->contents + 4);
17212
17213 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17214 put_arm_insn (htab, output_bfd,
17215 elf32_arm_nacl_plt0_entry[i],
17216 plt->contents + (i * 4));
17217}
17218
252b5132
RH		 17219/* Finish up the dynamic sections. */
17220
b34976b6 17221static bfd_boolean
57e8b36a 17222elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17223{
17224 bfd * dynobj;
17225 asection * sgot;
17226 asection * sdyn;
4dfe6ac6
NC		 17227 struct elf32_arm_link_hash_table *htab;
17228
17229 htab = elf32_arm_hash_table (info);
17230 if (htab == NULL)
17231 return FALSE;
252b5132
RH		 17232
17233 dynobj = elf_hash_table (info)->dynobj;
17234
362d30a1 17235 sgot = htab->root.sgotplt;
894891db
NC		 17236 /* A broken linker script might have discarded the dynamic sections.
17237 Catch this here so that we do not seg-fault later on. */
17238 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17239 return FALSE;
3d4d4302 17240 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17241
17242 if (elf_hash_table (info)->dynamic_sections_created)
17243 {
17244 asection *splt;
17245 Elf32_External_Dyn *dyncon, *dynconend;
17246
362d30a1 17247 splt = htab->root.splt;
24a1ba0f 17248 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17249 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17250
17251 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17252 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17253
252b5132
RH		 17254 for (; dyncon < dynconend; dyncon++)
17255 {
17256 Elf_Internal_Dyn dyn;
17257 const char * name;
17258 asection * s;
17259
17260 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17261
17262 switch (dyn.d_tag)
17263 {
229fcec5
MM		 17264 unsigned int type;
17265
252b5132 17266 default:
7a2b07ff
NS		 17267 if (htab->vxworks_p
17268 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17269 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17270 break;
17271
229fcec5
MM		 17272 case DT_HASH:
17273 name = ".hash";
17274 goto get_vma_if_bpabi;
17275 case DT_STRTAB:
17276 name = ".dynstr";
17277 goto get_vma_if_bpabi;
17278 case DT_SYMTAB:
17279 name = ".dynsym";
17280 goto get_vma_if_bpabi;
c0042f5d
MM		 17281 case DT_VERSYM:
17282 name = ".gnu.version";
17283 goto get_vma_if_bpabi;
17284 case DT_VERDEF:
17285 name = ".gnu.version_d";
17286 goto get_vma_if_bpabi;
17287 case DT_VERNEED:
17288 name = ".gnu.version_r";
17289 goto get_vma_if_bpabi;
17290
252b5132 17291 case DT_PLTGOT:
4ade44b7 17292 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17293 goto get_vma;
17294 case DT_JMPREL:
00a97672 17295 name = RELOC_SECTION (htab, ".plt");
252b5132 17296 get_vma:
4ade44b7 17297 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17298 if (s == NULL)
17299 {
4eca0228 17300 _bfd_error_handler
4ade44b7 17301 (_("could not find section %s"), name);
05456594
NC		 17302 bfd_set_error (bfd_error_invalid_operation);
17303 return FALSE;
17304 }
229fcec5 17305 if (!htab->symbian_p)
4ade44b7 17306 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17307 else
17308 /* In the BPABI, tags in the PT_DYNAMIC section point
17309 at the file offset, not the memory address, for the
17310 convenience of the post linker. */
4ade44b7 17311 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17312 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17313 break;
17314
229fcec5
MM		 17315 get_vma_if_bpabi:
17316 if (htab->symbian_p)
17317 goto get_vma;
17318 break;
17319
252b5132 17320 case DT_PLTRELSZ:
362d30a1 17321 s = htab->root.srelplt;
252b5132 17322 BFD_ASSERT (s != NULL);
eea6121a 17323 dyn.d_un.d_val = s->size;
252b5132
RH		 17324 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17325 break;
906e58ca 17326
252b5132 17327 case DT_RELSZ:
00a97672 17328 case DT_RELASZ:
229fcec5
MM		 17329 case DT_REL:
17330 case DT_RELA:
229fcec5
MM		 17331 /* In the BPABI, the DT_REL tag must point at the file
17332 offset, not the VMA, of the first relocation
17333 section. So, we use code similar to that in
17334 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17335 relocation section, since relocation sections are
17336 never allocated under the BPABI. PLT relocs are also
17337 included. */
229fcec5
MM		 17338 if (htab->symbian_p)
17339 {
17340 unsigned int i;
17341 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17342 ? SHT_REL : SHT_RELA);
17343 dyn.d_un.d_val = 0;
17344 for (i = 1; i < elf_numsections (output_bfd); i++)
17345 {
906e58ca 17346 Elf_Internal_Shdr *hdr
229fcec5
MM		 17347 = elf_elfsections (output_bfd)[i];
17348 if (hdr->sh_type == type)
17349 {
906e58ca 17350 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17351 || dyn.d_tag == DT_RELASZ)
17352 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17353 else if ((ufile_ptr) hdr->sh_offset
17354 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17355 dyn.d_un.d_val = hdr->sh_offset;
17356 }
17357 }
17358 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17359 }
252b5132 17360 break;
88f7bcd5 17361
0855e32b 17362 case DT_TLSDESC_PLT:
99059e56 17363 s = htab->root.splt;
0855e32b
NS		 17364 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17365 + htab->dt_tlsdesc_plt);
17366 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17367 break;
17368
17369 case DT_TLSDESC_GOT:
99059e56 17370 s = htab->root.sgot;
0855e32b 17371 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17372 + htab->dt_tlsdesc_got);
0855e32b
NS		 17373 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17374 break;
17375
88f7bcd5
NC		 17376 /* Set the bottom bit of DT_INIT/FINI if the
17377 corresponding function is Thumb. */
17378 case DT_INIT:
17379 name = info->init_function;
17380 goto get_sym;
17381 case DT_FINI:
17382 name = info->fini_function;
17383 get_sym:
17384 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17385 then there is nothing to adjust. */
88f7bcd5
NC		 17386 if (dyn.d_un.d_val != 0)
17387 {
17388 struct elf_link_hash_entry * eh;
17389
17390 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17391 FALSE, FALSE, TRUE);
39d911fc
TP		 17392 if (eh != NULL
17393 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17394 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17395 {
17396 dyn.d_un.d_val |= 1;
b34976b6 17397 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17398 }
17399 }
17400 break;
252b5132
RH		 17401 }
17402 }
17403
24a1ba0f 17404 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17405 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17406 {
00a97672
RS		 17407 const bfd_vma *plt0_entry;
17408 bfd_vma got_address, plt_address, got_displacement;
17409
17410 /* Calculate the addresses of the GOT and PLT. */
17411 got_address = sgot->output_section->vma + sgot->output_offset;
17412 plt_address = splt->output_section->vma + splt->output_offset;
17413
17414 if (htab->vxworks_p)
17415 {
17416 /* The VxWorks GOT is relocated by the dynamic linker.
17417 Therefore, we must emit relocations rather than simply
17418 computing the values now. */
17419 Elf_Internal_Rela rel;
17420
17421 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17422 put_arm_insn (htab, output_bfd, plt0_entry[0],
17423 splt->contents + 0);
17424 put_arm_insn (htab, output_bfd, plt0_entry[1],
17425 splt->contents + 4);
17426 put_arm_insn (htab, output_bfd, plt0_entry[2],
17427 splt->contents + 8);
00a97672
RS		 17428 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17429
8029a119 17430 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17431 rel.r_offset = plt_address + 12;
17432 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17433 rel.r_addend = 0;
17434 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17435 htab->srelplt2->contents);
17436 }
b38cadfb 17437 else if (htab->nacl_p)
99059e56
RM		 17438 arm_nacl_put_plt0 (htab, output_bfd, splt,
17439 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17440 else if (using_thumb_only (htab))
17441 {
17442 got_displacement = got_address - (plt_address + 12);
17443
17444 plt0_entry = elf32_thumb2_plt0_entry;
17445 put_arm_insn (htab, output_bfd, plt0_entry[0],
17446 splt->contents + 0);
17447 put_arm_insn (htab, output_bfd, plt0_entry[1],
17448 splt->contents + 4);
17449 put_arm_insn (htab, output_bfd, plt0_entry[2],
17450 splt->contents + 8);
17451
17452 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17453 }
00a97672
RS		 17454 else
17455 {
17456 got_displacement = got_address - (plt_address + 16);
17457
17458 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17459 put_arm_insn (htab, output_bfd, plt0_entry[0],
17460 splt->contents + 0);
17461 put_arm_insn (htab, output_bfd, plt0_entry[1],
17462 splt->contents + 4);
17463 put_arm_insn (htab, output_bfd, plt0_entry[2],
17464 splt->contents + 8);
17465 put_arm_insn (htab, output_bfd, plt0_entry[3],
17466 splt->contents + 12);
5e681ec4 17467
5e681ec4 17468#ifdef FOUR_WORD_PLT
00a97672
RS		 17469 /* The displacement value goes in the otherwise-unused
17470 last word of the second entry. */
17471 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17472#else
00a97672 17473 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17474#endif
00a97672 17475 }
f7a74f8c 17476 }
252b5132
RH		 17477
17478 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17479 really seem like the right value. */
74541ad4
AM		 17480 if (splt->output_section->owner == output_bfd)
17481 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17482
0855e32b
NS		 17483 if (htab->dt_tlsdesc_plt)
17484 {
17485 bfd_vma got_address
17486 = sgot->output_section->vma + sgot->output_offset;
17487 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17488 + htab->root.sgot->output_offset);
17489 bfd_vma plt_address
17490 = splt->output_section->vma + splt->output_offset;
17491
b38cadfb 17492 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17493 splt->contents + htab->dt_tlsdesc_plt,
17494 dl_tlsdesc_lazy_trampoline, 6);
17495
17496 bfd_put_32 (output_bfd,
17497 gotplt_address + htab->dt_tlsdesc_got
17498 - (plt_address + htab->dt_tlsdesc_plt)
17499 - dl_tlsdesc_lazy_trampoline[6],
17500 splt->contents + htab->dt_tlsdesc_plt + 24);
17501 bfd_put_32 (output_bfd,
17502 got_address - (plt_address + htab->dt_tlsdesc_plt)
17503 - dl_tlsdesc_lazy_trampoline[7],
17504 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17505 }
17506
17507 if (htab->tls_trampoline)
17508 {
b38cadfb 17509 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17510 splt->contents + htab->tls_trampoline,
17511 tls_trampoline, 3);
17512#ifdef FOUR_WORD_PLT
17513 bfd_put_32 (output_bfd, 0x00000000,
17514 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17515#endif
0855e32b
NS		 17516 }
17517
0e1862bb
L		 17518 if (htab->vxworks_p
17519 && !bfd_link_pic (info)
17520 && htab->root.splt->size > 0)
00a97672
RS		 17521 {
17522 /* Correct the .rel(a).plt.unloaded relocations. They will have
17523 incorrect symbol indexes. */
17524 int num_plts;
eed62c48 17525 unsigned char *p;
00a97672 17526
362d30a1 17527 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17528 / htab->plt_entry_size);
17529 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17530
17531 for (; num_plts; num_plts--)
17532 {
17533 Elf_Internal_Rela rel;
17534
17535 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17536 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17537 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17538 p += RELOC_SIZE (htab);
17539
17540 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17541 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17542 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17543 p += RELOC_SIZE (htab);
17544 }
17545 }
252b5132
RH		 17546 }
17547
99059e56
RM		 17548 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17549 /* NaCl uses a special first entry in .iplt too. */
17550 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17551
252b5132 17552 /* Fill in the first three entries in the global offset table. */
229fcec5 17553 if (sgot)
252b5132 17554 {
229fcec5
MM		 17555 if (sgot->size > 0)
17556 {
17557 if (sdyn == NULL)
17558 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17559 else
17560 bfd_put_32 (output_bfd,
17561 sdyn->output_section->vma + sdyn->output_offset,
17562 sgot->contents);
17563 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17564 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17565 }
252b5132 17566
229fcec5
MM		 17567 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17568 }
252b5132 17569
e8b09b87
CL		 17570 /* At the very end of the .rofixup section is a pointer to the GOT. */
17571 if (htab->fdpic_p && htab->srofixup != NULL)
17572 {
17573 struct elf_link_hash_entry *hgot = htab->root.hgot;
17574
17575 bfd_vma got_value = hgot->root.u.def.value
17576 + hgot->root.u.def.section->output_section->vma
17577 + hgot->root.u.def.section->output_offset;
17578
17579 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17580
17581 /* Make sure we allocated and generated the same number of fixups. */
17582 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17583 }
17584
b34976b6 17585 return TRUE;
252b5132
RH		 17586}
17587
ba96a88f 17588static void
57e8b36a 17589elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 17590{
9b485d32 17591 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17592 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17593 struct elf_segment_map *m;
ba96a88f
NC		 17594
17595 i_ehdrp = elf_elfheader (abfd);
17596
94a3258f
PB		 17597 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17598 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
17599 else
7394f108 17600 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 17601 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17602
93204d3a
PB		 17603 if (link_info)
17604 {
17605 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17606 if (globals != NULL && globals->byteswap_code)
93204d3a 17607 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17608
17609 if (globals->fdpic_p)
17610 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17611 }
3bfcb652
NC		 17612
17613 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17614 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17615 {
17616 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17617 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17618 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17619 else
17620 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17621 }
ac4c9b04
MG		 17622
17623 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17624 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17625 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17626 {
17627 unsigned int j;
17628
17629 if (m->count == 0)
17630 continue;
17631 for (j = 0; j < m->count; j++)
17632 {
f0728ee3 17633 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17634 break;
17635 }
17636 if (j == m->count)
17637 {
17638 m->p_flags = PF_X;
17639 m->p_flags_valid = 1;
17640 }
17641 }
ba96a88f
NC		 17642}
17643
99e4ae17 17644static enum elf_reloc_type_class
7e612e98
AM		 17645elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17646 const asection *rel_sec ATTRIBUTE_UNUSED,
17647 const Elf_Internal_Rela *rela)
99e4ae17 17648{
f51e552e 17649 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17650 {
17651 case R_ARM_RELATIVE:
17652 return reloc_class_relative;
17653 case R_ARM_JUMP_SLOT:
17654 return reloc_class_plt;
17655 case R_ARM_COPY:
17656 return reloc_class_copy;
109575d7
JW		 17657 case R_ARM_IRELATIVE:
17658 return reloc_class_ifunc;
99e4ae17
AJ		 17659 default:
17660 return reloc_class_normal;
17661 }
17662}
17663
e489d0ae 17664static void
57e8b36a 17665elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 17666{
5a6c6817 17667 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17668}
17669
40a18ebd
NC		 17670/* Return TRUE if this is an unwinding table entry. */
17671
17672static bfd_boolean
17673is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17674{
0112cd26
NC		 17675 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17676 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17677}
17678
17679
17680/* Set the type and flags for an ARM section. We do this by
17681 the section name, which is a hack, but ought to work. */
17682
17683static bfd_boolean
17684elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17685{
17686 const char * name;
17687
17688 name = bfd_get_section_name (abfd, sec);
17689
17690 if (is_arm_elf_unwind_section_name (abfd, name))
17691 {
17692 hdr->sh_type = SHT_ARM_EXIDX;
17693 hdr->sh_flags |= SHF_LINK_ORDER;
17694 }
ac4c9b04 17695
f0728ee3
AV		 17696 if (sec->flags & SEC_ELF_PURECODE)
17697 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17698
40a18ebd
NC		 17699 return TRUE;
17700}
17701
6dc132d9
L		 17702/* Handle an ARM specific section when reading an object file. This is
17703 called when bfd_section_from_shdr finds a section with an unknown
17704 type. */
40a18ebd
NC		 17705
17706static bfd_boolean
17707elf32_arm_section_from_shdr (bfd *abfd,
17708 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17709 const char *name,
17710 int shindex)
40a18ebd
NC		 17711{
17712 /* There ought to be a place to keep ELF backend specific flags, but
17713 at the moment there isn't one. We just keep track of the
17714 sections by their name, instead. Fortunately, the ABI gives
17715 names for all the ARM specific sections, so we will probably get
17716 away with this. */
17717 switch (hdr->sh_type)
17718 {
17719 case SHT_ARM_EXIDX:
0951f019
RE		 17720 case SHT_ARM_PREEMPTMAP:
17721 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17722 break;
17723
17724 default:
17725 return FALSE;
17726 }
17727
6dc132d9 17728 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17729 return FALSE;
17730
17731 return TRUE;
17732}
e489d0ae 17733
44444f50
NC		 17734static _arm_elf_section_data *
17735get_arm_elf_section_data (asection * sec)
17736{
47b2e99c
JZ		 17737 if (sec && sec->owner && is_arm_elf (sec->owner))
17738 return elf32_arm_section_data (sec);
44444f50
NC		 17739 else
17740 return NULL;
8e3de13a
NC		 17741}
17742
4e617b1e
PB		 17743typedef struct
17744{
57402f1e 17745 void *flaginfo;
4e617b1e 17746 struct bfd_link_info *info;
91a5743d
PB		 17747 asection *sec;
17748 int sec_shndx;
6e0b88f1
AM		 17749 int (*func) (void *, const char *, Elf_Internal_Sym *,
17750 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17751} output_arch_syminfo;
17752
17753enum map_symbol_type
17754{
17755 ARM_MAP_ARM,
17756 ARM_MAP_THUMB,
17757 ARM_MAP_DATA
17758};
17759
17760
7413f23f 17761/* Output a single mapping symbol. */
4e617b1e
PB		 17762
17763static bfd_boolean
7413f23f
DJ		 17764elf32_arm_output_map_sym (output_arch_syminfo *osi,
17765 enum map_symbol_type type,
17766 bfd_vma offset)
4e617b1e
PB		 17767{
17768 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17769 Elf_Internal_Sym sym;
17770
91a5743d
PB		 17771 sym.st_value = osi->sec->output_section->vma
17772 + osi->sec->output_offset
17773 + offset;
4e617b1e
PB		 17774 sym.st_size = 0;
17775 sym.st_other = 0;
17776 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17777 sym.st_shndx = osi->sec_shndx;
35fc36a8 17778 sym.st_target_internal = 0;
fe33d2fa 17779 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17780 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17781}
17782
34e77a92
RS		 17783/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17784 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17785
17786static bfd_boolean
34e77a92
RS		 17787elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17788 bfd_boolean is_iplt_entry_p,
17789 union gotplt_union *root_plt,
17790 struct arm_plt_info *arm_plt)
4e617b1e 17791{
4e617b1e 17792 struct elf32_arm_link_hash_table *htab;
34e77a92 17793 bfd_vma addr, plt_header_size;
4e617b1e 17794
34e77a92 17795 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17796 return TRUE;
17797
4dfe6ac6
NC		 17798 htab = elf32_arm_hash_table (osi->info);
17799 if (htab == NULL)
17800 return FALSE;
17801
34e77a92
RS		 17802 if (is_iplt_entry_p)
17803 {
17804 osi->sec = htab->root.iplt;
17805 plt_header_size = 0;
17806 }
17807 else
17808 {
17809 osi->sec = htab->root.splt;
17810 plt_header_size = htab->plt_header_size;
17811 }
17812 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
17813 (osi->info->output_bfd, osi->sec->output_section));
17814
17815 addr = root_plt->offset & -2;
4e617b1e
PB		 17816 if (htab->symbian_p)
17817 {
7413f23f 17818 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17819 return FALSE;
7413f23f 17820 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 17821 return FALSE;
17822 }
17823 else if (htab->vxworks_p)
17824 {
7413f23f 17825 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17826 return FALSE;
7413f23f 17827 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 17828 return FALSE;
7413f23f 17829 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 17830 return FALSE;
7413f23f 17831 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 17832 return FALSE;
17833 }
b38cadfb
NC		 17834 else if (htab->nacl_p)
17835 {
17836 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17837 return FALSE;
17838 }
7801f98f
CL		 17839 else if (htab->fdpic_p)
17840 {
59029f57
CL		 17841 enum map_symbol_type type = using_thumb_only(htab)
17842 ? ARM_MAP_THUMB
17843 : ARM_MAP_ARM;
17844
7801f98f
CL		 17845 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
17846 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
17847 return FALSE;
59029f57 17848 if (!elf32_arm_output_map_sym (osi, type, addr))
7801f98f
CL		 17849 return FALSE;
17850 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
17851 return FALSE;
17852 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
59029f57 17853 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
7801f98f
CL		 17854 return FALSE;
17855 }
eed94f8f
NC		 17856 else if (using_thumb_only (htab))
17857 {
17858 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17859 return FALSE;
6a631e86 17860 }
4e617b1e
PB		 17861 else
17862 {
34e77a92 17863 bfd_boolean thumb_stub_p;
bd97cb95 17864
34e77a92
RS		 17865 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17866 if (thumb_stub_p)
4e617b1e 17867 {
7413f23f 17868 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17869 return FALSE;
17870 }
17871#ifdef FOUR_WORD_PLT
7413f23f 17872 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17873 return FALSE;
7413f23f 17874 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17875 return FALSE;
17876#else
906e58ca 17877 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17878 so only need to output a mapping symbol for the first PLT entry and
17879 entries with thumb thunks. */
34e77a92 17880 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17881 {
7413f23f 17882 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17883 return FALSE;
17884 }
17885#endif
17886 }
17887
17888 return TRUE;
17889}
17890
34e77a92
RS		 17891/* Output mapping symbols for PLT entries associated with H. */
17892
17893static bfd_boolean
17894elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17895{
17896 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17897 struct elf32_arm_link_hash_entry *eh;
17898
17899 if (h->root.type == bfd_link_hash_indirect)
17900 return TRUE;
17901
17902 if (h->root.type == bfd_link_hash_warning)
17903 /* When warning symbols are created, they **replace** the "real"
17904 entry in the hash table, thus we never get to see the real
17905 symbol in a hash traversal. So look at it now. */
17906 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17907
17908 eh = (struct elf32_arm_link_hash_entry *) h;
17909 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17910 &h->plt, &eh->plt);
17911}
17912
4f4faa4d
TP		 17913/* Bind a veneered symbol to its veneer identified by its hash entry
17914 STUB_ENTRY. The veneered location thus loose its symbol. */
17915
17916static void
17917arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17918{
17919 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17920
17921 BFD_ASSERT (hash);
17922 hash->root.root.u.def.section = stub_entry->stub_sec;
17923 hash->root.root.u.def.value = stub_entry->stub_offset;
17924 hash->root.size = stub_entry->stub_size;
17925}
17926
7413f23f
DJ		 17927/* Output a single local symbol for a generated stub. */
17928
17929static bfd_boolean
17930elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17931 bfd_vma offset, bfd_vma size)
17932{
7413f23f
DJ		 17933 Elf_Internal_Sym sym;
17934
7413f23f
DJ		 17935 sym.st_value = osi->sec->output_section->vma
17936 + osi->sec->output_offset
17937 + offset;
17938 sym.st_size = size;
17939 sym.st_other = 0;
17940 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17941 sym.st_shndx = osi->sec_shndx;
35fc36a8 17942 sym.st_target_internal = 0;
57402f1e 17943 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17944}
4e617b1e 17945
da5938a2 17946static bfd_boolean
8029a119
NC		 17947arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17948 void * in_arg)
da5938a2
NC		 17949{
17950 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17951 asection *stub_sec;
17952 bfd_vma addr;
7413f23f 17953 char *stub_name;
9a008db3 17954 output_arch_syminfo *osi;
d3ce72d0 17955 const insn_sequence *template_sequence;
461a49ca
DJ		 17956 enum stub_insn_type prev_type;
17957 int size;
17958 int i;
17959 enum map_symbol_type sym_type;
da5938a2
NC		 17960
17961 /* Massage our args to the form they really have. */
17962 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17963 osi = (output_arch_syminfo *) in_arg;
da5938a2 17964
da5938a2
NC		 17965 stub_sec = stub_entry->stub_sec;
17966
17967 /* Ensure this stub is attached to the current section being
7413f23f 17968 processed. */
da5938a2
NC		 17969 if (stub_sec != osi->sec)
17970 return TRUE;
17971
7413f23f 17972 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17973 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17974
17975 if (arm_stub_sym_claimed (stub_entry->stub_type))
17976 arm_stub_claim_sym (stub_entry);
17977 else
7413f23f 17978 {
4f4faa4d
TP		 17979 stub_name = stub_entry->output_name;
17980 switch (template_sequence[0].type)
17981 {
17982 case ARM_TYPE:
17983 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17984 stub_entry->stub_size))
17985 return FALSE;
17986 break;
17987 case THUMB16_TYPE:
17988 case THUMB32_TYPE:
17989 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17990 stub_entry->stub_size))
17991 return FALSE;
17992 break;
17993 default:
17994 BFD_FAIL ();
17995 return 0;
17996 }
7413f23f 17997 }
da5938a2 17998
461a49ca
DJ		 17999 prev_type = DATA_TYPE;
18000 size = 0;
18001 for (i = 0; i < stub_entry->stub_template_size; i++)
18002 {
d3ce72d0 18003 switch (template_sequence[i].type)
461a49ca
DJ		 18004 {
18005 case ARM_TYPE:
18006 sym_type = ARM_MAP_ARM;
18007 break;
18008
18009 case THUMB16_TYPE:
48229727 18010 case THUMB32_TYPE:
461a49ca
DJ		 18011 sym_type = ARM_MAP_THUMB;
18012 break;
18013
18014 case DATA_TYPE:
18015 sym_type = ARM_MAP_DATA;
18016 break;
18017
18018 default:
18019 BFD_FAIL ();
4e31c731 18020 return FALSE;
461a49ca
DJ		 18021 }
18022
d3ce72d0 18023 if (template_sequence[i].type != prev_type)
461a49ca 18024 {
d3ce72d0 18025 prev_type = template_sequence[i].type;
461a49ca
DJ		 18026 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18027 return FALSE;
18028 }
18029
d3ce72d0 18030 switch (template_sequence[i].type)
461a49ca
DJ		 18031 {
18032 case ARM_TYPE:
48229727 18033 case THUMB32_TYPE:
461a49ca
DJ		 18034 size += 4;
18035 break;
18036
18037 case THUMB16_TYPE:
18038 size += 2;
18039 break;
18040
18041 case DATA_TYPE:
18042 size += 4;
18043 break;
18044
18045 default:
18046 BFD_FAIL ();
4e31c731 18047 return FALSE;
461a49ca
DJ		 18048 }
18049 }
18050
da5938a2
NC		 18051 return TRUE;
18052}
18053
33811162
DG		 18054/* Output mapping symbols for linker generated sections,
18055 and for those data-only sections that do not have a
18056 $d. */
4e617b1e
PB		 18057
18058static bfd_boolean
18059elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18060 struct bfd_link_info *info,
57402f1e 18061 void *flaginfo,
6e0b88f1
AM		 18062 int (*func) (void *, const char *,
18063 Elf_Internal_Sym *,
18064 asection *,
18065 struct elf_link_hash_entry *))
4e617b1e
PB		 18066{
18067 output_arch_syminfo osi;
18068 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18069 bfd_vma offset;
18070 bfd_size_type size;
33811162 18071 bfd *input_bfd;
4e617b1e
PB		 18072
18073 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18074 if (htab == NULL)
18075 return FALSE;
18076
906e58ca 18077 check_use_blx (htab);
91a5743d 18078
57402f1e 18079 osi.flaginfo = flaginfo;
4e617b1e
PB		 18080 osi.info = info;
18081 osi.func = func;
906e58ca 18082
33811162
DG		 18083 /* Add a $d mapping symbol to data-only sections that
18084 don't have any mapping symbol. This may result in (harmless) redundant
18085 mapping symbols. */
18086 for (input_bfd = info->input_bfds;
18087 input_bfd != NULL;
c72f2fb2 18088 input_bfd = input_bfd->link.next)
33811162
DG		 18089 {
18090 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18091 for (osi.sec = input_bfd->sections;
18092 osi.sec != NULL;
18093 osi.sec = osi.sec->next)
18094 {
18095 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18096 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18097 != 0)
33811162
DG		 18098 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18099 == SEC_HAS_CONTENTS
18100 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18101 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18102 && osi.sec->size > 0
18103 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18104 {
18105 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18106 (output_bfd, osi.sec->output_section);
18107 if (osi.sec_shndx != (int)SHN_BAD)
18108 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18109 }
18110 }
18111 }
18112
91a5743d
PB		 18113 /* ARM->Thumb glue. */
18114 if (htab->arm_glue_size > 0)
18115 {
3d4d4302
AM		 18116 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18117 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18118
18119 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18120 (output_bfd, osi.sec->output_section);
0e1862bb 18121 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18122 || htab->pic_veneer)
18123 size = ARM2THUMB_PIC_GLUE_SIZE;
18124 else if (htab->use_blx)
18125 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18126 else
18127 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18128
91a5743d
PB		 18129 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18130 {
7413f23f
DJ		 18131 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18132 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18133 }
18134 }
18135
18136 /* Thumb->ARM glue. */
18137 if (htab->thumb_glue_size > 0)
18138 {
3d4d4302
AM		 18139 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18140 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18141
18142 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18143 (output_bfd, osi.sec->output_section);
18144 size = THUMB2ARM_GLUE_SIZE;
18145
18146 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18147 {
7413f23f
DJ		 18148 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18149 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18150 }
18151 }
18152
845b51d6
PB		 18153 /* ARMv4 BX veneers. */
18154 if (htab->bx_glue_size > 0)
18155 {
3d4d4302
AM		 18156 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18157 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18158
18159 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18160 (output_bfd, osi.sec->output_section);
18161
7413f23f 18162 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18163 }
18164
8029a119
NC		 18165 /* Long calls stubs. */
18166 if (htab->stub_bfd && htab->stub_bfd->sections)
18167 {
da5938a2 18168 asection* stub_sec;
8029a119 18169
da5938a2
NC		 18170 for (stub_sec = htab->stub_bfd->sections;
18171 stub_sec != NULL;
8029a119
NC		 18172 stub_sec = stub_sec->next)
18173 {
18174 /* Ignore non-stub sections. */
18175 if (!strstr (stub_sec->name, STUB_SUFFIX))
18176 continue;
da5938a2 18177
8029a119 18178 osi.sec = stub_sec;
da5938a2 18179
8029a119
NC		 18180 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18181 (output_bfd, osi.sec->output_section);
da5938a2 18182
8029a119
NC		 18183 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18184 }
18185 }
da5938a2 18186
91a5743d 18187 /* Finally, output mapping symbols for the PLT. */
34e77a92 18188 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18189 {
34e77a92
RS		 18190 osi.sec = htab->root.splt;
18191 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18192 (output_bfd, osi.sec->output_section));
18193
18194 /* Output mapping symbols for the plt header. SymbianOS does not have a
18195 plt header. */
18196 if (htab->vxworks_p)
18197 {
18198 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18199 if (!bfd_link_pic (info))
34e77a92
RS		 18200 {
18201 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18202 return FALSE;
18203 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18204 return FALSE;
18205 }
18206 }
b38cadfb
NC		 18207 else if (htab->nacl_p)
18208 {
18209 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18210 return FALSE;
18211 }
59029f57 18212 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18213 {
18214 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18215 return FALSE;
18216 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18217 return FALSE;
18218 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18219 return FALSE;
18220 }
e8b09b87 18221 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18222 {
7413f23f 18223 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18224 return FALSE;
34e77a92
RS		 18225#ifndef FOUR_WORD_PLT
18226 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18227 return FALSE;
34e77a92 18228#endif
4e617b1e
PB		 18229 }
18230 }
99059e56
RM		 18231 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18232 {
18233 /* NaCl uses a special first entry in .iplt too. */
18234 osi.sec = htab->root.iplt;
18235 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18236 (output_bfd, osi.sec->output_section));
18237 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18238 return FALSE;
18239 }
34e77a92
RS		 18240 if ((htab->root.splt && htab->root.splt->size > 0)
18241 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18242 {
34e77a92
RS		 18243 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18244 for (input_bfd = info->input_bfds;
18245 input_bfd != NULL;
c72f2fb2 18246 input_bfd = input_bfd->link.next)
34e77a92
RS		 18247 {
18248 struct arm_local_iplt_info **local_iplt;
18249 unsigned int i, num_syms;
4e617b1e 18250
34e77a92
RS		 18251 local_iplt = elf32_arm_local_iplt (input_bfd);
18252 if (local_iplt != NULL)
18253 {
18254 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18255 for (i = 0; i < num_syms; i++)
18256 if (local_iplt[i] != NULL
18257 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18258 &local_iplt[i]->root,
18259 &local_iplt[i]->arm))
18260 return FALSE;
18261 }
18262 }
18263 }
0855e32b
NS		 18264 if (htab->dt_tlsdesc_plt != 0)
18265 {
18266 /* Mapping symbols for the lazy tls trampoline. */
18267 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18268 return FALSE;
b38cadfb 18269
0855e32b
NS		 18270 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18271 htab->dt_tlsdesc_plt + 24))
18272 return FALSE;
18273 }
18274 if (htab->tls_trampoline != 0)
18275 {
18276 /* Mapping symbols for the tls trampoline. */
18277 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18278 return FALSE;
18279#ifdef FOUR_WORD_PLT
18280 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18281 htab->tls_trampoline + 12))
18282 return FALSE;
b38cadfb 18283#endif
0855e32b 18284 }
b38cadfb 18285
4e617b1e
PB		 18286 return TRUE;
18287}
18288
54ddd295
TP		 18289/* Filter normal symbols of CMSE entry functions of ABFD to include in
18290 the import library. All SYMCOUNT symbols of ABFD can be examined
18291 from their pointers in SYMS. Pointers of symbols to keep should be
18292 stored continuously at the beginning of that array.
18293
18294 Returns the number of symbols to keep. */
18295
18296static unsigned int
18297elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18298 struct bfd_link_info *info,
18299 asymbol **syms, long symcount)
18300{
18301 size_t maxnamelen;
18302 char *cmse_name;
18303 long src_count, dst_count = 0;
18304 struct elf32_arm_link_hash_table *htab;
18305
18306 htab = elf32_arm_hash_table (info);
18307 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18308 symcount = 0;
18309
18310 maxnamelen = 128;
18311 cmse_name = (char *) bfd_malloc (maxnamelen);
18312 for (src_count = 0; src_count < symcount; src_count++)
18313 {
18314 struct elf32_arm_link_hash_entry *cmse_hash;
18315 asymbol *sym;
18316 flagword flags;
18317 char *name;
18318 size_t namelen;
18319
18320 sym = syms[src_count];
18321 flags = sym->flags;
18322 name = (char *) bfd_asymbol_name (sym);
18323
18324 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18325 continue;
18326 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18327 continue;
18328
18329 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18330 if (namelen > maxnamelen)
18331 {
18332 cmse_name = (char *)
18333 bfd_realloc (cmse_name, namelen);
18334 maxnamelen = namelen;
18335 }
18336 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18337 cmse_hash = (struct elf32_arm_link_hash_entry *)
18338 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18339
18340 if (!cmse_hash
18341 || (cmse_hash->root.root.type != bfd_link_hash_defined
18342 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18343 || cmse_hash->root.type != STT_FUNC)
18344 continue;
18345
18346 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
18347 continue;
18348
18349 syms[dst_count++] = sym;
18350 }
18351 free (cmse_name);
18352
18353 syms[dst_count] = NULL;
18354
18355 return dst_count;
18356}
18357
18358/* Filter symbols of ABFD to include in the import library. All
18359 SYMCOUNT symbols of ABFD can be examined from their pointers in
18360 SYMS. Pointers of symbols to keep should be stored continuously at
18361 the beginning of that array.
18362
18363 Returns the number of symbols to keep. */
18364
18365static unsigned int
18366elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18367 struct bfd_link_info *info,
18368 asymbol **syms, long symcount)
18369{
18370 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18371
046734ff
TP		 18372 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18373 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18374 library to be a relocatable object file. */
18375 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18376 if (globals->cmse_implib)
18377 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18378 else
18379 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18380}
18381
e489d0ae
PB		 18382/* Allocate target specific section data. */
18383
18384static bfd_boolean
18385elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18386{
f592407e
AM		 18387 if (!sec->used_by_bfd)
18388 {
18389 _arm_elf_section_data *sdata;
18390 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18391
21d799b5 18392 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18393 if (sdata == NULL)
18394 return FALSE;
18395 sec->used_by_bfd = sdata;
18396 }
e489d0ae
PB		 18397
18398 return _bfd_elf_new_section_hook (abfd, sec);
18399}
18400
18401
18402/* Used to order a list of mapping symbols by address. */
18403
18404static int
18405elf32_arm_compare_mapping (const void * a, const void * b)
18406{
7f6a71ff
JM		 18407 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18408 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18409
18410 if (amap->vma > bmap->vma)
18411 return 1;
18412 else if (amap->vma < bmap->vma)
18413 return -1;
18414 else if (amap->type > bmap->type)
18415 /* Ensure results do not depend on the host qsort for objects with
18416 multiple mapping symbols at the same address by sorting on type
18417 after vma. */
18418 return 1;
18419 else if (amap->type < bmap->type)
18420 return -1;
18421 else
18422 return 0;
e489d0ae
PB		 18423}
18424
2468f9c9
PB		 18425/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18426
18427static unsigned long
18428offset_prel31 (unsigned long addr, bfd_vma offset)
18429{
18430 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18431}
18432
18433/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18434 relocations. */
18435
18436static void
18437copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18438{
18439 unsigned long first_word = bfd_get_32 (output_bfd, from);
18440 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18441
2468f9c9
PB		 18442 /* High bit of first word is supposed to be zero. */
18443 if ((first_word & 0x80000000ul) == 0)
18444 first_word = offset_prel31 (first_word, offset);
b38cadfb 18445
2468f9c9
PB		 18446 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18447 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18448 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18449 second_word = offset_prel31 (second_word, offset);
b38cadfb 18450
2468f9c9
PB		 18451 bfd_put_32 (output_bfd, first_word, to);
18452 bfd_put_32 (output_bfd, second_word, to + 4);
18453}
e489d0ae 18454
48229727
JB		 18455/* Data for make_branch_to_a8_stub(). */
18456
b38cadfb
NC		 18457struct a8_branch_to_stub_data
18458{
48229727
JB		 18459 asection *writing_section;
18460 bfd_byte *contents;
18461};
18462
18463
18464/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18465 places for a particular section. */
18466
18467static bfd_boolean
18468make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18469 void *in_arg)
48229727
JB		 18470{
18471 struct elf32_arm_stub_hash_entry *stub_entry;
18472 struct a8_branch_to_stub_data *data;
18473 bfd_byte *contents;
18474 unsigned long branch_insn;
18475 bfd_vma veneered_insn_loc, veneer_entry_loc;
18476 bfd_signed_vma branch_offset;
18477 bfd *abfd;
8d9d9490 18478 unsigned int loc;
48229727
JB		 18479
18480 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18481 data = (struct a8_branch_to_stub_data *) in_arg;
18482
18483 if (stub_entry->target_section != data->writing_section
4563a860 18484 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18485 return TRUE;
18486
18487 contents = data->contents;
18488
8d9d9490
TP		 18489 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18490 generated when both source and target are in the same section. */
48229727
JB		 18491 veneered_insn_loc = stub_entry->target_section->output_section->vma
18492 + stub_entry->target_section->output_offset
8d9d9490 18493 + stub_entry->source_value;
48229727
JB		 18494
18495 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18496 + stub_entry->stub_sec->output_offset
18497 + stub_entry->stub_offset;
18498
18499 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18500 veneered_insn_loc &= ~3u;
18501
18502 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18503
18504 abfd = stub_entry->target_section->owner;
8d9d9490 18505 loc = stub_entry->source_value;
48229727
JB		 18506
18507 /* We attempt to avoid this condition by setting stubs_always_after_branch
18508 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18509 This check is just to be on the safe side... */
18510 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18511 {
871b3ab2 18512 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18513 "allocated in unsafe location"), abfd);
48229727
JB		 18514 return FALSE;
18515 }
18516
18517 switch (stub_entry->stub_type)
18518 {
18519 case arm_stub_a8_veneer_b:
18520 case arm_stub_a8_veneer_b_cond:
18521 branch_insn = 0xf0009000;
18522 goto jump24;
18523
18524 case arm_stub_a8_veneer_blx:
18525 branch_insn = 0xf000e800;
18526 goto jump24;
18527
18528 case arm_stub_a8_veneer_bl:
18529 {
18530 unsigned int i1, j1, i2, j2, s;
18531
18532 branch_insn = 0xf000d000;
18533
18534 jump24:
18535 if (branch_offset < -16777216 || branch_offset > 16777214)
18536 {
18537 /* There's not much we can do apart from complain if this
18538 happens. */
871b3ab2 18539 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18540 "of range (input file too large)"), abfd);
48229727
JB		 18541 return FALSE;
18542 }
18543
18544 /* i1 = not(j1 eor s), so:
18545 not i1 = j1 eor s
18546 j1 = (not i1) eor s. */
18547
18548 branch_insn |= (branch_offset >> 1) & 0x7ff;
18549 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18550 i2 = (branch_offset >> 22) & 1;
18551 i1 = (branch_offset >> 23) & 1;
18552 s = (branch_offset >> 24) & 1;
18553 j1 = (!i1) ^ s;
18554 j2 = (!i2) ^ s;
18555 branch_insn |= j2 << 11;
18556 branch_insn |= j1 << 13;
18557 branch_insn |= s << 26;
18558 }
18559 break;
18560
18561 default:
18562 BFD_FAIL ();
18563 return FALSE;
18564 }
18565
8d9d9490
TP		 18566 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18567 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18568
18569 return TRUE;
18570}
18571
a504d23a
LA		 18572/* Beginning of stm32l4xx work-around. */
18573
18574/* Functions encoding instructions necessary for the emission of the
18575 fix-stm32l4xx-629360.
18576 Encoding is extracted from the
18577 ARM (C) Architecture Reference Manual
18578 ARMv7-A and ARMv7-R edition
18579 ARM DDI 0406C.b (ID072512). */
18580
18581static inline bfd_vma
82188b29 18582create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18583{
18584 /* A8.8.18 B (A8-334)
18585 B target_address (Encoding T4). */
18586 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18587 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18588 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18589
a504d23a
LA		 18590 int s = ((branch_offset & 0x1000000) >> 24);
18591 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18592 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18593
18594 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18595 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18596
18597 bfd_vma patched_inst = 0xf0009000
18598 | s << 26 /* S. */
18599 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18600 | j1 << 13 /* J1. */
18601 | j2 << 11 /* J2. */
18602 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18603
18604 return patched_inst;
18605}
18606
18607static inline bfd_vma
18608create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18609{
18610 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18611 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18612 bfd_vma patched_inst = 0xe8900000
18613 | (/*W=*/wback << 21)
18614 | (base_reg << 16)
18615 | (reg_mask & 0x0000ffff);
18616
18617 return patched_inst;
18618}
18619
18620static inline bfd_vma
18621create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18622{
18623 /* A8.8.60 LDMDB/LDMEA (A8-402)
18624 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18625 bfd_vma patched_inst = 0xe9100000
18626 | (/*W=*/wback << 21)
18627 | (base_reg << 16)
18628 | (reg_mask & 0x0000ffff);
18629
18630 return patched_inst;
18631}
18632
18633static inline bfd_vma
18634create_instruction_mov (int target_reg, int source_reg)
18635{
18636 /* A8.8.103 MOV (register) (A8-486)
18637 MOV Rd, Rm (Encoding T1). */
18638 bfd_vma patched_inst = 0x4600
18639 | (target_reg & 0x7)
18640 | ((target_reg & 0x8) >> 3) << 7
18641 | (source_reg << 3);
18642
18643 return patched_inst;
18644}
18645
18646static inline bfd_vma
18647create_instruction_sub (int target_reg, int source_reg, int value)
18648{
18649 /* A8.8.221 SUB (immediate) (A8-708)
18650 SUB Rd, Rn, #value (Encoding T3). */
18651 bfd_vma patched_inst = 0xf1a00000
18652 | (target_reg << 8)
18653 | (source_reg << 16)
18654 | (/*S=*/0 << 20)
18655 | ((value & 0x800) >> 11) << 26
18656 | ((value & 0x700) >> 8) << 12
18657 | (value & 0x0ff);
18658
18659 return patched_inst;
18660}
18661
18662static inline bfd_vma
9239bbd3 18663create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18664 int first_reg)
18665{
18666 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18667 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18668 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18669 | (/*W=*/wback << 21)
18670 | (base_reg << 16)
9239bbd3
CM		 18671 | (num_words & 0x000000ff)
18672 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18673 | (first_reg & 0x00000001) << 22;
18674
18675 return patched_inst;
18676}
18677
18678static inline bfd_vma
9239bbd3
CM		 18679create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18680 int first_reg)
a504d23a
LA		 18681{
18682 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18683 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18684 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18685 | (base_reg << 16)
9239bbd3
CM		 18686 | (num_words & 0x000000ff)
18687 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18688 | (first_reg & 0x00000001) << 22;
18689
18690 return patched_inst;
18691}
18692
18693static inline bfd_vma
18694create_instruction_udf_w (int value)
18695{
18696 /* A8.8.247 UDF (A8-758)
18697 Undefined (Encoding T2). */
18698 bfd_vma patched_inst = 0xf7f0a000
18699 | (value & 0x00000fff)
18700 | (value & 0x000f0000) << 16;
18701
18702 return patched_inst;
18703}
18704
18705static inline bfd_vma
18706create_instruction_udf (int value)
18707{
18708 /* A8.8.247 UDF (A8-758)
18709 Undefined (Encoding T1). */
18710 bfd_vma patched_inst = 0xde00
18711 | (value & 0xff);
18712
18713 return patched_inst;
18714}
18715
18716/* Functions writing an instruction in memory, returning the next
18717 memory position to write to. */
18718
18719static inline bfd_byte *
18720push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18721 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18722{
18723 put_thumb2_insn (htab, output_bfd, insn, pt);
18724 return pt + 4;
18725}
18726
18727static inline bfd_byte *
18728push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18729 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18730{
18731 put_thumb_insn (htab, output_bfd, insn, pt);
18732 return pt + 2;
18733}
18734
18735/* Function filling up a region in memory with T1 and T2 UDFs taking
18736 care of alignment. */
18737
18738static bfd_byte *
18739stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18740 bfd * output_bfd,
18741 const bfd_byte * const base_stub_contents,
18742 bfd_byte * const from_stub_contents,
18743 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18744{
18745 bfd_byte *current_stub_contents = from_stub_contents;
18746
18747 /* Fill the remaining of the stub with deterministic contents : UDF
18748 instructions.
18749 Check if realignment is needed on modulo 4 frontier using T1, to
18750 further use T2. */
18751 if ((current_stub_contents < end_stub_contents)
18752 && !((current_stub_contents - base_stub_contents) % 2)
18753 && ((current_stub_contents - base_stub_contents) % 4))
18754 current_stub_contents =
18755 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18756 create_instruction_udf (0));
18757
18758 for (; current_stub_contents < end_stub_contents;)
18759 current_stub_contents =
18760 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18761 create_instruction_udf_w (0));
18762
18763 return current_stub_contents;
18764}
18765
18766/* Functions writing the stream of instructions equivalent to the
18767 derived sequence for ldmia, ldmdb, vldm respectively. */
18768
18769static void
18770stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18771 bfd * output_bfd,
18772 const insn32 initial_insn,
18773 const bfd_byte *const initial_insn_addr,
18774 bfd_byte *const base_stub_contents)
18775{
18776 int wback = (initial_insn & 0x00200000) >> 21;
18777 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18778 int insn_all_registers = initial_insn & 0x0000ffff;
18779 int insn_low_registers, insn_high_registers;
18780 int usable_register_mask;
b25e998d 18781 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18782 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18783 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18784 bfd_byte *current_stub_contents = base_stub_contents;
18785
18786 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18787
18788 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18789 smaller than 8 registers load sequences that do not cause the
18790 hardware issue. */
18791 if (nb_registers <= 8)
18792 {
18793 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18794 current_stub_contents =
18795 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18796 initial_insn);
18797
18798 /* B initial_insn_addr+4. */
18799 if (!restore_pc)
18800 current_stub_contents =
18801 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18802 create_instruction_branch_absolute
82188b29 18803 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18804
18805 /* Fill the remaining of the stub with deterministic contents. */
18806 current_stub_contents =
18807 stm32l4xx_fill_stub_udf (htab, output_bfd,
18808 base_stub_contents, current_stub_contents,
18809 base_stub_contents +
18810 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18811
18812 return;
18813 }
18814
18815 /* - reg_list[13] == 0. */
18816 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
18817
18818 /* - reg_list[14] & reg_list[15] != 1. */
18819 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18820
18821 /* - if (wback==1) reg_list[rn] == 0. */
18822 BFD_ASSERT (!wback || !restore_rn);
18823
18824 /* - nb_registers > 8. */
b25e998d 18825 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18826
18827 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18828
18829 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18830 - One with the 7 lowest registers (register mask 0x007F)
18831 This LDM will finally contain between 2 and 7 registers
18832 - One with the 7 highest registers (register mask 0xDF80)
18833 This ldm will finally contain between 2 and 7 registers. */
18834 insn_low_registers = insn_all_registers & 0x007F;
18835 insn_high_registers = insn_all_registers & 0xDF80;
18836
18837 /* A spare register may be needed during this veneer to temporarily
18838 handle the base register. This register will be restored with the
18839 last LDM operation.
18840 The usable register may be any general purpose register (that
18841 excludes PC, SP, LR : register mask is 0x1FFF). */
18842 usable_register_mask = 0x1FFF;
18843
18844 /* Generate the stub function. */
18845 if (wback)
18846 {
18847 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18848 current_stub_contents =
18849 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18850 create_instruction_ldmia
18851 (rn, /*wback=*/1, insn_low_registers));
18852
18853 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18854 current_stub_contents =
18855 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18856 create_instruction_ldmia
18857 (rn, /*wback=*/1, insn_high_registers));
18858 if (!restore_pc)
18859 {
18860 /* B initial_insn_addr+4. */
18861 current_stub_contents =
18862 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18863 create_instruction_branch_absolute
82188b29 18864 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18865 }
18866 }
18867 else /* if (!wback). */
18868 {
18869 ri = rn;
18870
18871 /* If Rn is not part of the high-register-list, move it there. */
18872 if (!(insn_high_registers & (1 << rn)))
18873 {
18874 /* Choose a Ri in the high-register-list that will be restored. */
18875 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18876
18877 /* MOV Ri, Rn. */
18878 current_stub_contents =
18879 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18880 create_instruction_mov (ri, rn));
18881 }
18882
18883 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18884 current_stub_contents =
18885 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18886 create_instruction_ldmia
18887 (ri, /*wback=*/1, insn_low_registers));
18888
18889 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18890 current_stub_contents =
18891 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18892 create_instruction_ldmia
18893 (ri, /*wback=*/0, insn_high_registers));
18894
18895 if (!restore_pc)
18896 {
18897 /* B initial_insn_addr+4. */
18898 current_stub_contents =
18899 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18900 create_instruction_branch_absolute
82188b29 18901 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18902 }
18903 }
18904
18905 /* Fill the remaining of the stub with deterministic contents. */
18906 current_stub_contents =
18907 stm32l4xx_fill_stub_udf (htab, output_bfd,
18908 base_stub_contents, current_stub_contents,
18909 base_stub_contents +
18910 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18911}
18912
18913static void
18914stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18915 bfd * output_bfd,
18916 const insn32 initial_insn,
18917 const bfd_byte *const initial_insn_addr,
18918 bfd_byte *const base_stub_contents)
18919{
18920 int wback = (initial_insn & 0x00200000) >> 21;
18921 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18922 int insn_all_registers = initial_insn & 0x0000ffff;
18923 int insn_low_registers, insn_high_registers;
18924 int usable_register_mask;
18925 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18926 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18927 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18928 bfd_byte *current_stub_contents = base_stub_contents;
18929
18930 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18931
18932 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18933 smaller than 8 registers load sequences that do not cause the
18934 hardware issue. */
18935 if (nb_registers <= 8)
18936 {
18937 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18938 current_stub_contents =
18939 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18940 initial_insn);
18941
18942 /* B initial_insn_addr+4. */
18943 current_stub_contents =
18944 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18945 create_instruction_branch_absolute
82188b29 18946 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18947
18948 /* Fill the remaining of the stub with deterministic contents. */
18949 current_stub_contents =
18950 stm32l4xx_fill_stub_udf (htab, output_bfd,
18951 base_stub_contents, current_stub_contents,
18952 base_stub_contents +
18953 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18954
18955 return;
18956 }
18957
18958 /* - reg_list[13] == 0. */
18959 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18960
18961 /* - reg_list[14] & reg_list[15] != 1. */
18962 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18963
18964 /* - if (wback==1) reg_list[rn] == 0. */
18965 BFD_ASSERT (!wback || !restore_rn);
18966
18967 /* - nb_registers > 8. */
b25e998d 18968 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18969
18970 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18971
18972 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18973 - One with the 7 lowest registers (register mask 0x007F)
18974 This LDM will finally contain between 2 and 7 registers
18975 - One with the 7 highest registers (register mask 0xDF80)
18976 This ldm will finally contain between 2 and 7 registers. */
18977 insn_low_registers = insn_all_registers & 0x007F;
18978 insn_high_registers = insn_all_registers & 0xDF80;
18979
18980 /* A spare register may be needed during this veneer to temporarily
18981 handle the base register. This register will be restored with
18982 the last LDM operation.
18983 The usable register may be any general purpose register (that excludes
18984 PC, SP, LR : register mask is 0x1FFF). */
18985 usable_register_mask = 0x1FFF;
18986
18987 /* Generate the stub function. */
18988 if (!wback && !restore_pc && !restore_rn)
18989 {
18990 /* Choose a Ri in the low-register-list that will be restored. */
18991 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18992
18993 /* MOV Ri, Rn. */
18994 current_stub_contents =
18995 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18996 create_instruction_mov (ri, rn));
18997
18998 /* LDMDB Ri!, {R-high-register-list}. */
18999 current_stub_contents =
19000 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19001 create_instruction_ldmdb
19002 (ri, /*wback=*/1, insn_high_registers));
19003
19004 /* LDMDB Ri, {R-low-register-list}. */
19005 current_stub_contents =
19006 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19007 create_instruction_ldmdb
19008 (ri, /*wback=*/0, insn_low_registers));
19009
19010 /* B initial_insn_addr+4. */
19011 current_stub_contents =
19012 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19013 create_instruction_branch_absolute
82188b29 19014 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19015 }
19016 else if (wback && !restore_pc && !restore_rn)
19017 {
19018 /* LDMDB Rn!, {R-high-register-list}. */
19019 current_stub_contents =
19020 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19021 create_instruction_ldmdb
19022 (rn, /*wback=*/1, insn_high_registers));
19023
19024 /* LDMDB Rn!, {R-low-register-list}. */
19025 current_stub_contents =
19026 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19027 create_instruction_ldmdb
19028 (rn, /*wback=*/1, insn_low_registers));
19029
19030 /* B initial_insn_addr+4. */
19031 current_stub_contents =
19032 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19033 create_instruction_branch_absolute
82188b29 19034 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19035 }
19036 else if (!wback && restore_pc && !restore_rn)
19037 {
19038 /* Choose a Ri in the high-register-list that will be restored. */
19039 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19040
19041 /* SUB Ri, Rn, #(4*nb_registers). */
19042 current_stub_contents =
19043 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19044 create_instruction_sub (ri, rn, (4 * nb_registers)));
19045
19046 /* LDMIA Ri!, {R-low-register-list}. */
19047 current_stub_contents =
19048 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19049 create_instruction_ldmia
19050 (ri, /*wback=*/1, insn_low_registers));
19051
19052 /* LDMIA Ri, {R-high-register-list}. */
19053 current_stub_contents =
19054 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19055 create_instruction_ldmia
19056 (ri, /*wback=*/0, insn_high_registers));
19057 }
19058 else if (wback && restore_pc && !restore_rn)
19059 {
19060 /* Choose a Ri in the high-register-list that will be restored. */
19061 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19062
19063 /* SUB Rn, Rn, #(4*nb_registers) */
19064 current_stub_contents =
19065 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19066 create_instruction_sub (rn, rn, (4 * nb_registers)));
19067
19068 /* MOV Ri, Rn. */
19069 current_stub_contents =
19070 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19071 create_instruction_mov (ri, rn));
19072
19073 /* LDMIA Ri!, {R-low-register-list}. */
19074 current_stub_contents =
19075 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19076 create_instruction_ldmia
19077 (ri, /*wback=*/1, insn_low_registers));
19078
19079 /* LDMIA Ri, {R-high-register-list}. */
19080 current_stub_contents =
19081 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19082 create_instruction_ldmia
19083 (ri, /*wback=*/0, insn_high_registers));
19084 }
19085 else if (!wback && !restore_pc && restore_rn)
19086 {
19087 ri = rn;
19088 if (!(insn_low_registers & (1 << rn)))
19089 {
19090 /* Choose a Ri in the low-register-list that will be restored. */
19091 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19092
19093 /* MOV Ri, Rn. */
19094 current_stub_contents =
19095 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19096 create_instruction_mov (ri, rn));
19097 }
19098
19099 /* LDMDB Ri!, {R-high-register-list}. */
19100 current_stub_contents =
19101 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19102 create_instruction_ldmdb
19103 (ri, /*wback=*/1, insn_high_registers));
19104
19105 /* LDMDB Ri, {R-low-register-list}. */
19106 current_stub_contents =
19107 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19108 create_instruction_ldmdb
19109 (ri, /*wback=*/0, insn_low_registers));
19110
19111 /* B initial_insn_addr+4. */
19112 current_stub_contents =
19113 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19114 create_instruction_branch_absolute
82188b29 19115 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19116 }
19117 else if (!wback && restore_pc && restore_rn)
19118 {
19119 ri = rn;
19120 if (!(insn_high_registers & (1 << rn)))
19121 {
19122 /* Choose a Ri in the high-register-list that will be restored. */
19123 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19124 }
19125
19126 /* SUB Ri, Rn, #(4*nb_registers). */
19127 current_stub_contents =
19128 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19129 create_instruction_sub (ri, rn, (4 * nb_registers)));
19130
19131 /* LDMIA Ri!, {R-low-register-list}. */
19132 current_stub_contents =
19133 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19134 create_instruction_ldmia
19135 (ri, /*wback=*/1, insn_low_registers));
19136
19137 /* LDMIA Ri, {R-high-register-list}. */
19138 current_stub_contents =
19139 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19140 create_instruction_ldmia
19141 (ri, /*wback=*/0, insn_high_registers));
19142 }
19143 else if (wback && restore_rn)
19144 {
19145 /* The assembler should not have accepted to encode this. */
19146 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19147 "undefined behavior.\n");
19148 }
19149
19150 /* Fill the remaining of the stub with deterministic contents. */
19151 current_stub_contents =
19152 stm32l4xx_fill_stub_udf (htab, output_bfd,
19153 base_stub_contents, current_stub_contents,
19154 base_stub_contents +
19155 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19156
19157}
19158
19159static void
19160stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19161 bfd * output_bfd,
19162 const insn32 initial_insn,
19163 const bfd_byte *const initial_insn_addr,
19164 bfd_byte *const base_stub_contents)
19165{
9239bbd3 19166 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 19167 bfd_byte *current_stub_contents = base_stub_contents;
19168
19169 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19170
19171 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19172 smaller than 8 words load sequences that do not cause the
a504d23a 19173 hardware issue. */
9239bbd3 19174 if (num_words <= 8)
a504d23a
LA		 19175 {
19176 /* Untouched instruction. */
19177 current_stub_contents =
19178 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19179 initial_insn);
19180
19181 /* B initial_insn_addr+4. */
19182 current_stub_contents =
19183 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19184 create_instruction_branch_absolute
82188b29 19185 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19186 }
19187 else
19188 {
9eaff861 19189 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19190 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19191 bfd_boolean is_ia_nobang = /* (IA without !). */
19192 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19193 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19194 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19195 bfd_boolean is_db_bang = /* (DB with !). */
19196 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19197 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19198 /* d = UInt (Vd:D);. */
9239bbd3 19199 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19200 | (((unsigned int)initial_insn << 9) >> 31);
19201
9239bbd3
CM		 19202 /* Compute the number of 8-words chunks needed to split. */
19203 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19204 int chunk;
19205
19206 /* The test coverage has been done assuming the following
19207 hypothesis that exactly one of the previous is_ predicates is
19208 true. */
9239bbd3
CM		 19209 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19210 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19211
9239bbd3 19212 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19213 cases, then we emit the adjustments:
19214
19215 vldm rx, {...}
19216 -> vldm rx!, {8_words_or_less} for each needed 8_word
19217 -> sub rx, rx, #size (list)
19218
19219 vldm rx!, {...}
19220 -> vldm rx!, {8_words_or_less} for each needed 8_word
19221 This also handles vpop instruction (when rx is sp)
19222
19223 vldmd rx!, {...}
19224 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19225 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19226 {
9239bbd3
CM		 19227 bfd_vma new_insn = 0;
19228
a504d23a
LA		 19229 if (is_ia_nobang || is_ia_bang)
19230 {
9239bbd3
CM		 19231 new_insn = create_instruction_vldmia
19232 (base_reg,
19233 is_dp,
19234 /*wback= . */1,
19235 chunks - (chunk + 1) ?
19236 8 : num_words - chunk * 8,
19237 first_reg + chunk * 8);
a504d23a
LA		 19238 }
19239 else if (is_db_bang)
19240 {
9239bbd3
CM		 19241 new_insn = create_instruction_vldmdb
19242 (base_reg,
19243 is_dp,
19244 chunks - (chunk + 1) ?
19245 8 : num_words - chunk * 8,
19246 first_reg + chunk * 8);
a504d23a 19247 }
9239bbd3
CM		 19248
19249 if (new_insn)
19250 current_stub_contents =
19251 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19252 new_insn);
a504d23a
LA		 19253 }
19254
19255 /* Only this case requires the base register compensation
19256 subtract. */
19257 if (is_ia_nobang)
19258 {
19259 current_stub_contents =
19260 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19261 create_instruction_sub
9239bbd3 19262 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19263 }
19264
19265 /* B initial_insn_addr+4. */
19266 current_stub_contents =
19267 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19268 create_instruction_branch_absolute
82188b29 19269 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19270 }
19271
19272 /* Fill the remaining of the stub with deterministic contents. */
19273 current_stub_contents =
19274 stm32l4xx_fill_stub_udf (htab, output_bfd,
19275 base_stub_contents, current_stub_contents,
19276 base_stub_contents +
19277 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19278}
19279
19280static void
19281stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19282 bfd * output_bfd,
19283 const insn32 wrong_insn,
19284 const bfd_byte *const wrong_insn_addr,
19285 bfd_byte *const stub_contents)
19286{
19287 if (is_thumb2_ldmia (wrong_insn))
19288 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19289 wrong_insn, wrong_insn_addr,
19290 stub_contents);
19291 else if (is_thumb2_ldmdb (wrong_insn))
19292 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19293 wrong_insn, wrong_insn_addr,
19294 stub_contents);
19295 else if (is_thumb2_vldm (wrong_insn))
19296 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19297 wrong_insn, wrong_insn_addr,
19298 stub_contents);
19299}
19300
19301/* End of stm32l4xx work-around. */
19302
19303
e489d0ae
PB		 19304/* Do code byteswapping. Return FALSE afterwards so that the section is
19305 written out as normal. */
19306
19307static bfd_boolean
c7b8f16e 19308elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19309 struct bfd_link_info *link_info,
19310 asection *sec,
e489d0ae
PB		 19311 bfd_byte *contents)
19312{
48229727 19313 unsigned int mapcount, errcount;
8e3de13a 19314 _arm_elf_section_data *arm_data;
c7b8f16e 19315 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19316 elf32_arm_section_map *map;
c7b8f16e 19317 elf32_vfp11_erratum_list *errnode;
a504d23a 19318 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19319 bfd_vma ptr;
19320 bfd_vma end;
c7b8f16e 19321 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19322 bfd_byte tmp;
48229727 19323 unsigned int i;
57e8b36a 19324
4dfe6ac6
NC		 19325 if (globals == NULL)
19326 return FALSE;
19327
8e3de13a
NC		 19328 /* If this section has not been allocated an _arm_elf_section_data
19329 structure then we cannot record anything. */
19330 arm_data = get_arm_elf_section_data (sec);
19331 if (arm_data == NULL)
19332 return FALSE;
19333
19334 mapcount = arm_data->mapcount;
19335 map = arm_data->map;
c7b8f16e
JB		 19336 errcount = arm_data->erratumcount;
19337
19338 if (errcount != 0)
19339 {
19340 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19341
19342 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19343 errnode = errnode->next)
19344 {
19345 bfd_vma target = errnode->vma - offset;
19346
19347 switch (errnode->type)
19348 {
19349 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19350 {
19351 bfd_vma branch_to_veneer;
19352 /* Original condition code of instruction, plus bit mask for
19353 ARM B instruction. */
19354 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19355 | 0x0a000000;
c7b8f16e
JB		 19356
19357 /* The instruction is before the label. */
91d6fa6a 19358 target -= 4;
c7b8f16e
JB		 19359
19360 /* Above offset included in -4 below. */
19361 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19362 - errnode->vma - 4;
c7b8f16e
JB		 19363
19364 if ((signed) branch_to_veneer < -(1 << 25)
19365 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19366 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19367 "range"), output_bfd);
c7b8f16e 19368
99059e56
RM		 19369 insn |= (branch_to_veneer >> 2) & 0xffffff;
19370 contents[endianflip ^ target] = insn & 0xff;
19371 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19372 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19373 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19374 }
19375 break;
c7b8f16e
JB		 19376
19377 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19378 {
19379 bfd_vma branch_from_veneer;
19380 unsigned int insn;
c7b8f16e 19381
99059e56
RM		 19382 /* Take size of veneer into account. */
19383 branch_from_veneer = errnode->u.v.branch->vma
19384 - errnode->vma - 12;
c7b8f16e
JB		 19385
19386 if ((signed) branch_from_veneer < -(1 << 25)
19387 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19388 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19389 "range"), output_bfd);
c7b8f16e 19390
99059e56
RM		 19391 /* Original instruction. */
19392 insn = errnode->u.v.branch->u.b.vfp_insn;
19393 contents[endianflip ^ target] = insn & 0xff;
19394 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19395 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19396 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19397
19398 /* Branch back to insn after original insn. */
19399 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19400 contents[endianflip ^ (target + 4)] = insn & 0xff;
19401 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19402 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19403 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19404 }
19405 break;
c7b8f16e 19406
99059e56
RM		 19407 default:
19408 abort ();
19409 }
19410 }
c7b8f16e 19411 }
e489d0ae 19412
a504d23a
LA		 19413 if (arm_data->stm32l4xx_erratumcount != 0)
19414 {
19415 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19416 stm32l4xx_errnode != 0;
19417 stm32l4xx_errnode = stm32l4xx_errnode->next)
19418 {
19419 bfd_vma target = stm32l4xx_errnode->vma - offset;
19420
19421 switch (stm32l4xx_errnode->type)
19422 {
19423 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19424 {
19425 unsigned int insn;
19426 bfd_vma branch_to_veneer =
19427 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19428
19429 if ((signed) branch_to_veneer < -(1 << 24)
19430 || (signed) branch_to_veneer >= (1 << 24))
19431 {
19432 bfd_vma out_of_range =
19433 ((signed) branch_to_veneer < -(1 << 24)) ?
19434 - branch_to_veneer - (1 << 24) :
19435 ((signed) branch_to_veneer >= (1 << 24)) ?
19436 branch_to_veneer - (1 << 24) : 0;
19437
4eca0228 19438 _bfd_error_handler
2dcf00ce 19439 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19440 "cannot create STM32L4XX veneer; "
19441 "jump out of range by %" PRId64 " bytes; "
19442 "cannot encode branch instruction"),
a504d23a 19443 output_bfd,
2dcf00ce
AM		 19444 (uint64_t) (stm32l4xx_errnode->vma - 4),
19445 (int64_t) out_of_range);
a504d23a
LA		 19446 continue;
19447 }
19448
19449 insn = create_instruction_branch_absolute
82188b29 19450 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 19451
19452 /* The instruction is before the label. */
19453 target -= 4;
19454
19455 put_thumb2_insn (globals, output_bfd,
19456 (bfd_vma) insn, contents + target);
19457 }
19458 break;
19459
19460 case STM32L4XX_ERRATUM_VENEER:
19461 {
82188b29
NC		 19462 bfd_byte * veneer;
19463 bfd_byte * veneer_r;
a504d23a
LA		 19464 unsigned int insn;
19465
82188b29
NC		 19466 veneer = contents + target;
19467 veneer_r = veneer
19468 + stm32l4xx_errnode->u.b.veneer->vma
19469 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19470
19471 if ((signed) (veneer_r - veneer -
19472 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19473 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19474 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19475 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19476 || (signed) (veneer_r - veneer) >= (1 << 24))
19477 {
90b6238f
AM		 19478 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19479 "veneer"), output_bfd);
a504d23a
LA		 19480 continue;
19481 }
19482
19483 /* Original instruction. */
19484 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19485
19486 stm32l4xx_create_replacing_stub
19487 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19488 }
19489 break;
19490
19491 default:
19492 abort ();
19493 }
19494 }
19495 }
19496
2468f9c9
PB		 19497 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19498 {
19499 arm_unwind_table_edit *edit_node
99059e56 19500 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19501 /* Now, sec->size is the size of the section we will write. The original
99059e56 19502 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19503 markers) was sec->rawsize. (This isn't the case if we perform no
19504 edits, then rawsize will be zero and we should use size). */
21d799b5 19505 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19506 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19507 unsigned int in_index, out_index;
19508 bfd_vma add_to_offsets = 0;
19509
19510 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19511 {
2468f9c9
PB		 19512 if (edit_node)
19513 {
19514 unsigned int edit_index = edit_node->index;
b38cadfb 19515
2468f9c9 19516 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19517 {
2468f9c9
PB		 19518 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19519 contents + in_index * 8, add_to_offsets);
19520 out_index++;
19521 in_index++;
19522 }
19523 else if (in_index == edit_index
19524 || (in_index * 8 >= input_size
19525 && edit_index == UINT_MAX))
99059e56 19526 {
2468f9c9
PB		 19527 switch (edit_node->type)
19528 {
19529 case DELETE_EXIDX_ENTRY:
19530 in_index++;
19531 add_to_offsets += 8;
19532 break;
b38cadfb 19533
2468f9c9
PB		 19534 case INSERT_EXIDX_CANTUNWIND_AT_END:
19535 {
99059e56 19536 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19537 bfd_vma text_offset = text_sec->output_section->vma
19538 + text_sec->output_offset
19539 + text_sec->size;
19540 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19541 unsigned long prel31_offset;
2468f9c9
PB		 19542
19543 /* Note: this is meant to be equivalent to an
19544 R_ARM_PREL31 relocation. These synthetic
19545 EXIDX_CANTUNWIND markers are not relocated by the
19546 usual BFD method. */
19547 prel31_offset = (text_offset - exidx_offset)
19548 & 0x7ffffffful;
491d01d3
YU		 19549 if (bfd_link_relocatable (link_info))
19550 {
19551 /* Here relocation for new EXIDX_CANTUNWIND is
19552 created, so there is no need to
19553 adjust offset by hand. */
19554 prel31_offset = text_sec->output_offset
19555 + text_sec->size;
491d01d3 19556 }
2468f9c9
PB		 19557
19558 /* First address we can't unwind. */
19559 bfd_put_32 (output_bfd, prel31_offset,
19560 &edited_contents[out_index * 8]);
19561
19562 /* Code for EXIDX_CANTUNWIND. */
19563 bfd_put_32 (output_bfd, 0x1,
19564 &edited_contents[out_index * 8 + 4]);
19565
19566 out_index++;
19567 add_to_offsets -= 8;
19568 }
19569 break;
19570 }
b38cadfb 19571
2468f9c9
PB		 19572 edit_node = edit_node->next;
19573 }
19574 }
19575 else
19576 {
19577 /* No more edits, copy remaining entries verbatim. */
19578 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19579 contents + in_index * 8, add_to_offsets);
19580 out_index++;
19581 in_index++;
19582 }
19583 }
19584
19585 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19586 bfd_set_section_contents (output_bfd, sec->output_section,
19587 edited_contents,
19588 (file_ptr) sec->output_offset, sec->size);
19589
19590 return TRUE;
19591 }
19592
48229727
JB		 19593 /* Fix code to point to Cortex-A8 erratum stubs. */
19594 if (globals->fix_cortex_a8)
19595 {
19596 struct a8_branch_to_stub_data data;
19597
19598 data.writing_section = sec;
19599 data.contents = contents;
19600
a504d23a
LA		 19601 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19602 & data);
48229727
JB		 19603 }
19604
e489d0ae
PB		 19605 if (mapcount == 0)
19606 return FALSE;
19607
c7b8f16e 19608 if (globals->byteswap_code)
e489d0ae 19609 {
c7b8f16e 19610 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19611
c7b8f16e
JB		 19612 ptr = map[0].vma;
19613 for (i = 0; i < mapcount; i++)
99059e56
RM		 19614 {
19615 if (i == mapcount - 1)
c7b8f16e 19616 end = sec->size;
99059e56
RM		 19617 else
19618 end = map[i + 1].vma;
e489d0ae 19619
99059e56 19620 switch (map[i].type)
e489d0ae 19621 {
c7b8f16e
JB		 19622 case 'a':
19623 /* Byte swap code words. */
19624 while (ptr + 3 < end)
99059e56
RM		 19625 {
19626 tmp = contents[ptr];
19627 contents[ptr] = contents[ptr + 3];
19628 contents[ptr + 3] = tmp;
19629 tmp = contents[ptr + 1];
19630 contents[ptr + 1] = contents[ptr + 2];
19631 contents[ptr + 2] = tmp;
19632 ptr += 4;
19633 }
c7b8f16e 19634 break;
e489d0ae 19635
c7b8f16e
JB		 19636 case 't':
19637 /* Byte swap code halfwords. */
19638 while (ptr + 1 < end)
99059e56
RM		 19639 {
19640 tmp = contents[ptr];
19641 contents[ptr] = contents[ptr + 1];
19642 contents[ptr + 1] = tmp;
19643 ptr += 2;
19644 }
c7b8f16e
JB		 19645 break;
19646
19647 case 'd':
19648 /* Leave data alone. */
19649 break;
19650 }
99059e56
RM		 19651 ptr = end;
19652 }
e489d0ae 19653 }
8e3de13a 19654
93204d3a 19655 free (map);
47b2e99c 19656 arm_data->mapcount = -1;
c7b8f16e 19657 arm_data->mapsize = 0;
8e3de13a 19658 arm_data->map = NULL;
8e3de13a 19659
e489d0ae
PB		 19660 return FALSE;
19661}
19662
0beaef2b
PB		 19663/* Mangle thumb function symbols as we read them in. */
19664
8384fb8f 19665static bfd_boolean
0beaef2b
PB		 19666elf32_arm_swap_symbol_in (bfd * abfd,
19667 const void *psrc,
19668 const void *pshn,
19669 Elf_Internal_Sym *dst)
19670{
4ba2ef8f
TP		 19671 Elf_Internal_Shdr *symtab_hdr;
19672 const char *name = NULL;
19673
8384fb8f
AM		 19674 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19675 return FALSE;
39d911fc 19676 dst->st_target_internal = 0;
0beaef2b
PB		 19677
19678 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19679 the address. */
63e1a0fc
PB		 19680 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19681 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19682 {
63e1a0fc
PB		 19683 if (dst->st_value & 1)
19684 {
19685 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19686 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19687 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19688 }
19689 else
39d911fc 19690 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19691 }
19692 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19693 {
19694 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19695 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19696 }
35fc36a8 19697 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19698 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19699 else
39d911fc 19700 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19701
4ba2ef8f
TP		 19702 /* Mark CMSE special symbols. */
19703 symtab_hdr = & elf_symtab_hdr (abfd);
19704 if (symtab_hdr->sh_size)
19705 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
19706 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
19707 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
19708
8384fb8f 19709 return TRUE;
0beaef2b
PB		 19710}
19711
19712
19713/* Mangle thumb function symbols as we write them out. */
19714
19715static void
19716elf32_arm_swap_symbol_out (bfd *abfd,
19717 const Elf_Internal_Sym *src,
19718 void *cdst,
19719 void *shndx)
19720{
19721 Elf_Internal_Sym newsym;
19722
19723 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19724 of the address set, as per the new EABI. We do this unconditionally
19725 because objcopy does not set the elf header flags until after
19726 it writes out the symbol table. */
39d911fc 19727 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19728 {
19729 newsym = *src;
34e77a92
RS		 19730 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19731 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19732 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19733 {
19734 /* Do this only for defined symbols. At link type, the static
19735 linker will simulate the work of dynamic linker of resolving
19736 symbols and will carry over the thumbness of found symbols to
19737 the output symbol table. It's not clear how it happens, but
19738 the thumbness of undefined symbols can well be different at
19739 runtime, and writing '1' for them will be confusing for users
19740 and possibly for dynamic linker itself.
19741 */
19742 newsym.st_value |= 1;
19743 }
906e58ca 19744
0beaef2b
PB		 19745 src = &newsym;
19746 }
19747 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19748}
19749
b294bdf8
MM		 19750/* Add the PT_ARM_EXIDX program header. */
19751
19752static bfd_boolean
906e58ca 19753elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19754 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19755{
19756 struct elf_segment_map *m;
19757 asection *sec;
19758
19759 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19760 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19761 {
19762 /* If there is already a PT_ARM_EXIDX header, then we do not
19763 want to add another one. This situation arises when running
19764 "strip"; the input binary already has the header. */
12bd6957 19765 m = elf_seg_map (abfd);
b294bdf8
MM		 19766 while (m && m->p_type != PT_ARM_EXIDX)
19767 m = m->next;
19768 if (!m)
19769 {
21d799b5 19770 m = (struct elf_segment_map *)
99059e56 19771 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19772 if (m == NULL)
19773 return FALSE;
19774 m->p_type = PT_ARM_EXIDX;
19775 m->count = 1;
19776 m->sections[0] = sec;
19777
12bd6957
AM		 19778 m->next = elf_seg_map (abfd);
19779 elf_seg_map (abfd) = m;
b294bdf8
MM		 19780 }
19781 }
19782
19783 return TRUE;
19784}
19785
19786/* We may add a PT_ARM_EXIDX program header. */
19787
19788static int
a6b96beb
AM		 19789elf32_arm_additional_program_headers (bfd *abfd,
19790 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19791{
19792 asection *sec;
19793
19794 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19795 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19796 return 1;
19797 else
19798 return 0;
19799}
19800
34e77a92
RS		 19801/* Hook called by the linker routine which adds symbols from an object
19802 file. */
19803
19804static bfd_boolean
19805elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19806 Elf_Internal_Sym *sym, const char **namep,
19807 flagword *flagsp, asection **secp, bfd_vma *valp)
19808{
c792917c
NC		 19809 if (elf32_arm_hash_table (info) == NULL)
19810 return FALSE;
19811
34e77a92
RS		 19812 if (elf32_arm_hash_table (info)->vxworks_p
19813 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
19814 flagsp, secp, valp))
19815 return FALSE;
19816
19817 return TRUE;
19818}
19819
0beaef2b 19820/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 19821const struct elf_size_info elf32_arm_size_info =
19822{
0beaef2b
PB		 19823 sizeof (Elf32_External_Ehdr),
19824 sizeof (Elf32_External_Phdr),
19825 sizeof (Elf32_External_Shdr),
19826 sizeof (Elf32_External_Rel),
19827 sizeof (Elf32_External_Rela),
19828 sizeof (Elf32_External_Sym),
19829 sizeof (Elf32_External_Dyn),
19830 sizeof (Elf_External_Note),
19831 4,
19832 1,
19833 32, 2,
19834 ELFCLASS32, EV_CURRENT,
19835 bfd_elf32_write_out_phdrs,
19836 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 19837 bfd_elf32_checksum_contents,
0beaef2b
PB		 19838 bfd_elf32_write_relocs,
19839 elf32_arm_swap_symbol_in,
19840 elf32_arm_swap_symbol_out,
19841 bfd_elf32_slurp_reloc_table,
19842 bfd_elf32_slurp_symbol_table,
19843 bfd_elf32_swap_dyn_in,
19844 bfd_elf32_swap_dyn_out,
19845 bfd_elf32_swap_reloc_in,
19846 bfd_elf32_swap_reloc_out,
19847 bfd_elf32_swap_reloca_in,
19848 bfd_elf32_swap_reloca_out
19849};
19850
685e70ae
VK		 19851static bfd_vma
19852read_code32 (const bfd *abfd, const bfd_byte *addr)
19853{
19854 /* V7 BE8 code is always little endian. */
19855 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19856 return bfd_getl32 (addr);
19857
19858 return bfd_get_32 (abfd, addr);
19859}
19860
19861static bfd_vma
19862read_code16 (const bfd *abfd, const bfd_byte *addr)
19863{
19864 /* V7 BE8 code is always little endian. */
19865 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19866 return bfd_getl16 (addr);
19867
19868 return bfd_get_16 (abfd, addr);
19869}
19870
6a631e86
YG		 19871/* Return size of plt0 entry starting at ADDR
19872 or (bfd_vma) -1 if size can not be determined. */
19873
19874static bfd_vma
19875elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19876{
19877 bfd_vma first_word;
19878 bfd_vma plt0_size;
19879
685e70ae 19880 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19881
19882 if (first_word == elf32_arm_plt0_entry[0])
19883 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19884 else if (first_word == elf32_thumb2_plt0_entry[0])
19885 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19886 else
19887 /* We don't yet handle this PLT format. */
19888 return (bfd_vma) -1;
19889
19890 return plt0_size;
19891}
19892
19893/* Return size of plt entry starting at offset OFFSET
19894 of plt section located at address START
19895 or (bfd_vma) -1 if size can not be determined. */
19896
19897static bfd_vma
19898elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19899{
19900 bfd_vma first_insn;
19901 bfd_vma plt_size = 0;
19902 const bfd_byte *addr = start + offset;
19903
19904 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19905 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19906 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19907
19908 /* Respect Thumb stub if necessary. */
685e70ae 19909 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19910 {
19911 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19912 }
19913
19914 /* Strip immediate from first add. */
685e70ae 19915 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19916
19917#ifdef FOUR_WORD_PLT
19918 if (first_insn == elf32_arm_plt_entry[0])
19919 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19920#else
19921 if (first_insn == elf32_arm_plt_entry_long[0])
19922 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19923 else if (first_insn == elf32_arm_plt_entry_short[0])
19924 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19925#endif
19926 else
19927 /* We don't yet handle this PLT format. */
19928 return (bfd_vma) -1;
19929
19930 return plt_size;
19931}
19932
19933/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19934
19935static long
19936elf32_arm_get_synthetic_symtab (bfd *abfd,
19937 long symcount ATTRIBUTE_UNUSED,
19938 asymbol **syms ATTRIBUTE_UNUSED,
19939 long dynsymcount,
19940 asymbol **dynsyms,
19941 asymbol **ret)
19942{
19943 asection *relplt;
19944 asymbol *s;
19945 arelent *p;
19946 long count, i, n;
19947 size_t size;
19948 Elf_Internal_Shdr *hdr;
19949 char *names;
19950 asection *plt;
19951 bfd_vma offset;
19952 bfd_byte *data;
19953
19954 *ret = NULL;
19955
19956 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19957 return 0;
19958
19959 if (dynsymcount <= 0)
19960 return 0;
19961
19962 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19963 if (relplt == NULL)
19964 return 0;
19965
19966 hdr = &elf_section_data (relplt)->this_hdr;
19967 if (hdr->sh_link != elf_dynsymtab (abfd)
19968 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19969 return 0;
19970
19971 plt = bfd_get_section_by_name (abfd, ".plt");
19972 if (plt == NULL)
19973 return 0;
19974
19975 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19976 return -1;
19977
19978 data = plt->contents;
19979 if (data == NULL)
19980 {
19981 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19982 return -1;
19983 bfd_cache_section_contents((asection *) plt, data);
19984 }
19985
19986 count = relplt->size / hdr->sh_entsize;
19987 size = count * sizeof (asymbol);
19988 p = relplt->relocation;
19989 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19990 {
19991 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19992 if (p->addend != 0)
19993 size += sizeof ("+0x") - 1 + 8;
19994 }
19995
19996 s = *ret = (asymbol *) bfd_malloc (size);
19997 if (s == NULL)
19998 return -1;
19999
20000 offset = elf32_arm_plt0_size (abfd, data);
20001 if (offset == (bfd_vma) -1)
20002 return -1;
20003
20004 names = (char *) (s + count);
20005 p = relplt->relocation;
20006 n = 0;
20007 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20008 {
20009 size_t len;
20010
20011 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20012 if (plt_size == (bfd_vma) -1)
20013 break;
20014
20015 *s = **p->sym_ptr_ptr;
20016 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20017 we are defining a symbol, ensure one of them is set. */
20018 if ((s->flags & BSF_LOCAL) == 0)
20019 s->flags |= BSF_GLOBAL;
20020 s->flags |= BSF_SYNTHETIC;
20021 s->section = plt;
20022 s->value = offset;
20023 s->name = names;
20024 s->udata.p = NULL;
20025 len = strlen ((*p->sym_ptr_ptr)->name);
20026 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20027 names += len;
20028 if (p->addend != 0)
20029 {
20030 char buf[30], *a;
20031
20032 memcpy (names, "+0x", sizeof ("+0x") - 1);
20033 names += sizeof ("+0x") - 1;
20034 bfd_sprintf_vma (abfd, buf, p->addend);
20035 for (a = buf; *a == '0'; ++a)
20036 ;
20037 len = strlen (a);
20038 memcpy (names, a, len);
20039 names += len;
20040 }
20041 memcpy (names, "@plt", sizeof ("@plt"));
20042 names += sizeof ("@plt");
20043 ++s, ++n;
20044 offset += plt_size;
20045 }
20046
20047 return n;
20048}
20049
ac4c9b04
MG		 20050static bfd_boolean
20051elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
20052{
f0728ee3
AV		 20053 if (hdr->sh_flags & SHF_ARM_PURECODE)
20054 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20055 return TRUE;
20056}
20057
20058static flagword
20059elf32_arm_lookup_section_flags (char *flag_name)
20060{
f0728ee3
AV		 20061 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20062 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20063
20064 return SEC_NO_FLAGS;
20065}
20066
491d01d3
YU		 20067static unsigned int
20068elf32_arm_count_additional_relocs (asection *sec)
20069{
20070 struct _arm_elf_section_data *arm_data;
20071 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20072
6342be70 20073 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20074}
20075
5522f910 20076/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20077 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20078 FALSE otherwise. ISECTION is the best guess matching section from the
20079 input bfd IBFD, but it might be NULL. */
20080
20081static bfd_boolean
20082elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20083 bfd *obfd ATTRIBUTE_UNUSED,
20084 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20085 Elf_Internal_Shdr *osection)
20086{
20087 switch (osection->sh_type)
20088 {
20089 case SHT_ARM_EXIDX:
20090 {
20091 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20092 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20093 unsigned i = 0;
20094
20095 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20096 osection->sh_info = 0;
20097
20098 /* The sh_link field must be set to the text section associated with
20099 this index section. Unfortunately the ARM EHABI does not specify
20100 exactly how to determine this association. Our caller does try
20101 to match up OSECTION with its corresponding input section however
20102 so that is a good first guess. */
20103 if (isection != NULL
20104 && osection->bfd_section != NULL
20105 && isection->bfd_section != NULL
20106 && isection->bfd_section->output_section != NULL
20107 && isection->bfd_section->output_section == osection->bfd_section
20108 && iheaders != NULL
20109 && isection->sh_link > 0
20110 && isection->sh_link < elf_numsections (ibfd)
20111 && iheaders[isection->sh_link]->bfd_section != NULL
20112 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20113 )
20114 {
20115 for (i = elf_numsections (obfd); i-- > 0;)
20116 if (oheaders[i]->bfd_section
20117 == iheaders[isection->sh_link]->bfd_section->output_section)
20118 break;
20119 }
9eaff861 20120
5522f910
NC		 20121 if (i == 0)
20122 {
20123 /* Failing that we have to find a matching section ourselves. If
20124 we had the output section name available we could compare that
20125 with input section names. Unfortunately we don't. So instead
20126 we use a simple heuristic and look for the nearest executable
20127 section before this one. */
20128 for (i = elf_numsections (obfd); i-- > 0;)
20129 if (oheaders[i] == osection)
20130 break;
20131 if (i == 0)
20132 break;
20133
20134 while (i-- > 0)
20135 if (oheaders[i]->sh_type == SHT_PROGBITS
20136 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20137 == (SHF_ALLOC | SHF_EXECINSTR))
20138 break;
20139 }
20140
20141 if (i)
20142 {
20143 osection->sh_link = i;
20144 /* If the text section was part of a group
20145 then the index section should be too. */
20146 if (oheaders[i]->sh_flags & SHF_GROUP)
20147 osection->sh_flags |= SHF_GROUP;
20148 return TRUE;
20149 }
20150 }
20151 break;
20152
20153 case SHT_ARM_PREEMPTMAP:
20154 osection->sh_flags = SHF_ALLOC;
20155 break;
20156
20157 case SHT_ARM_ATTRIBUTES:
20158 case SHT_ARM_DEBUGOVERLAY:
20159 case SHT_ARM_OVERLAYSECTION:
20160 default:
20161 break;
20162 }
20163
20164 return FALSE;
20165}
20166
d691934d
NC		 20167/* Returns TRUE if NAME is an ARM mapping symbol.
20168 Traditionally the symbols $a, $d and $t have been used.
20169 The ARM ELF standard also defines $x (for A64 code). It also allows a
20170 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20171 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20172 not support them here. $t.x indicates the start of ThumbEE instructions. */
20173
20174static bfd_boolean
20175is_arm_mapping_symbol (const char * name)
20176{
20177 return name != NULL /* Paranoia. */
20178 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20179 the mapping symbols could have acquired a prefix.
20180 We do not support this here, since such symbols no
20181 longer conform to the ARM ELF ABI. */
20182 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20183 && (name[2] == 0 || name[2] == '.');
20184 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20185 any characters that follow the period are legal characters for the body
20186 of a symbol's name. For now we just assume that this is the case. */
20187}
20188
fca2a38f
NC		 20189/* Make sure that mapping symbols in object files are not removed via the
20190 "strip --strip-unneeded" tool. These symbols are needed in order to
20191 correctly generate interworking veneers, and for byte swapping code
20192 regions. Once an object file has been linked, it is safe to remove the
20193 symbols as they will no longer be needed. */
20194
20195static void
20196elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20197{
20198 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20199 && sym->section != bfd_abs_section_ptr
d691934d 20200 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20201 sym->flags |= BSF_KEEP;
20202}
20203
5522f910
NC		 20204#undef elf_backend_copy_special_section_fields
20205#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20206
252b5132 20207#define ELF_ARCH bfd_arch_arm
ae95ffa6 20208#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20209#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20210#ifdef __QNXTARGET__
20211#define ELF_MAXPAGESIZE 0x1000
20212#else
7572ca89 20213#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20214#endif
b1342370 20215#define ELF_MINPAGESIZE 0x1000
24718e3b 20216#define ELF_COMMONPAGESIZE 0x1000
252b5132 20217
07d6d2b8 20218#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20219
99e4ae17
AJ		 20220#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20221#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20222#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20223#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20224#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20225#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20226#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 20227#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20228#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20229#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20230#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20231#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20232#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20233
07d6d2b8
AM		 20234#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20235#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20236#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20237#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20238#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20239#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20240#define elf_backend_write_section elf32_arm_write_section
252b5132 20241#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20242#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20243#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20244#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20245#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20246#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20247#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 20248#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 20249#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20250#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20251#define elf_backend_fake_sections elf32_arm_fake_sections
20252#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20253#define elf_backend_final_write_processing elf32_arm_final_write_processing
20254#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20255#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20256#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20257#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20258#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20259#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20260#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20261#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20262#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20263#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20264
20265#define elf_backend_can_refcount 1
20266#define elf_backend_can_gc_sections 1
20267#define elf_backend_plt_readonly 1
20268#define elf_backend_want_got_plt 1
20269#define elf_backend_want_plt_sym 0
5474d94f 20270#define elf_backend_want_dynrelro 1
906e58ca
NC		 20271#define elf_backend_may_use_rel_p 1
20272#define elf_backend_may_use_rela_p 0
4e7fd91e 20273#define elf_backend_default_use_rela_p 0
64f52338 20274#define elf_backend_dtrel_excludes_plt 1
252b5132 20275
04f7c78d 20276#define elf_backend_got_header_size 12
b68a20d6 20277#define elf_backend_extern_protected_data 1
04f7c78d 20278
07d6d2b8 20279#undef elf_backend_obj_attrs_vendor
906e58ca 20280#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20281#undef elf_backend_obj_attrs_section
906e58ca 20282#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20283#undef elf_backend_obj_attrs_arg_type
906e58ca 20284#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20285#undef elf_backend_obj_attrs_section_type
104d59d1 20286#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20287#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20288#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20289
07d6d2b8 20290#undef elf_backend_section_flags
ac4c9b04 20291#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20292#undef elf_backend_lookup_section_flags_hook
20293#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20294
a2f63b2e
MR		 20295#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20296
252b5132 20297#include "elf32-target.h"
7f266840 20298
b38cadfb
NC		 20299/* Native Client targets. */
20300
20301#undef TARGET_LITTLE_SYM
6d00b590 20302#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20303#undef TARGET_LITTLE_NAME
20304#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20305#undef TARGET_BIG_SYM
6d00b590 20306#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20307#undef TARGET_BIG_NAME
20308#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20309
20310/* Like elf32_arm_link_hash_table_create -- but overrides
20311 appropriately for NaCl. */
20312
20313static struct bfd_link_hash_table *
20314elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20315{
20316 struct bfd_link_hash_table *ret;
20317
20318 ret = elf32_arm_link_hash_table_create (abfd);
20319 if (ret)
20320 {
20321 struct elf32_arm_link_hash_table *htab
20322 = (struct elf32_arm_link_hash_table *) ret;
20323
20324 htab->nacl_p = 1;
20325
20326 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20327 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20328 }
20329 return ret;
20330}
20331
20332/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20333 really need to use elf32_arm_modify_segment_map. But we do it
20334 anyway just to reduce gratuitous differences with the stock ARM backend. */
20335
20336static bfd_boolean
20337elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20338{
20339 return (elf32_arm_modify_segment_map (abfd, info)
20340 && nacl_modify_segment_map (abfd, info));
20341}
20342
887badb3
RM		 20343static void
20344elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
20345{
20346 elf32_arm_final_write_processing (abfd, linker);
20347 nacl_final_write_processing (abfd, linker);
20348}
20349
6a631e86
YG		 20350static bfd_vma
20351elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20352 const arelent *rel ATTRIBUTE_UNUSED)
20353{
20354 return plt->vma
20355 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20356 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20357}
887badb3 20358
b38cadfb 20359#undef elf32_bed
6a631e86 20360#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20361#undef bfd_elf32_bfd_link_hash_table_create
20362#define bfd_elf32_bfd_link_hash_table_create \
20363 elf32_arm_nacl_link_hash_table_create
20364#undef elf_backend_plt_alignment
6a631e86 20365#define elf_backend_plt_alignment 4
b38cadfb
NC		 20366#undef elf_backend_modify_segment_map
20367#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20368#undef elf_backend_modify_program_headers
20369#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 20370#undef elf_backend_final_write_processing
20371#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20372#undef bfd_elf32_get_synthetic_symtab
20373#undef elf_backend_plt_sym_val
20374#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20375#undef elf_backend_copy_special_section_fields
b38cadfb 20376
887badb3
RM		 20377#undef ELF_MINPAGESIZE
20378#undef ELF_COMMONPAGESIZE
20379
b38cadfb
NC		 20380
20381#include "elf32-target.h"
20382
20383/* Reset to defaults. */
20384#undef elf_backend_plt_alignment
20385#undef elf_backend_modify_segment_map
20386#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20387#undef elf_backend_modify_program_headers
887badb3
RM		 20388#undef elf_backend_final_write_processing
20389#define elf_backend_final_write_processing elf32_arm_final_write_processing
20390#undef ELF_MINPAGESIZE
20391#define ELF_MINPAGESIZE 0x1000
20392#undef ELF_COMMONPAGESIZE
20393#define ELF_COMMONPAGESIZE 0x1000
20394
b38cadfb 20395
617a5ada
CL		 20396/* FDPIC Targets. */
20397
20398#undef TARGET_LITTLE_SYM
20399#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20400#undef TARGET_LITTLE_NAME
20401#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20402#undef TARGET_BIG_SYM
20403#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20404#undef TARGET_BIG_NAME
20405#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20406#undef elf_match_priority
20407#define elf_match_priority 128
18a20338
CL		 20408#undef ELF_OSABI
20409#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20410
20411/* Like elf32_arm_link_hash_table_create -- but overrides
20412 appropriately for FDPIC. */
20413
20414static struct bfd_link_hash_table *
20415elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20416{
20417 struct bfd_link_hash_table *ret;
20418
20419 ret = elf32_arm_link_hash_table_create (abfd);
20420 if (ret)
20421 {
20422 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20423
20424 htab->fdpic_p = 1;
20425 }
20426 return ret;
20427}
20428
e8b09b87
CL		 20429/* We need dynamic symbols for every section, since segments can
20430 relocate independently. */
20431static bfd_boolean
20432elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20433 struct bfd_link_info *info
20434 ATTRIBUTE_UNUSED,
20435 asection *p ATTRIBUTE_UNUSED)
20436{
20437 switch (elf_section_data (p)->this_hdr.sh_type)
20438 {
20439 case SHT_PROGBITS:
20440 case SHT_NOBITS:
20441 /* If sh_type is yet undecided, assume it could be
20442 SHT_PROGBITS/SHT_NOBITS. */
20443 case SHT_NULL:
20444 return FALSE;
20445
20446 /* There shouldn't be section relative relocations
20447 against any other section. */
20448 default:
20449 return TRUE;
20450 }
20451}
20452
617a5ada
CL		 20453#undef elf32_bed
20454#define elf32_bed elf32_arm_fdpic_bed
20455
20456#undef bfd_elf32_bfd_link_hash_table_create
20457#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
20458
e8b09b87
CL		 20459#undef elf_backend_omit_section_dynsym
20460#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20461
617a5ada 20462#include "elf32-target.h"
e8b09b87 20463
617a5ada 20464#undef elf_match_priority
18a20338 20465#undef ELF_OSABI
e8b09b87 20466#undef elf_backend_omit_section_dynsym
617a5ada 20467
906e58ca 20468/* VxWorks Targets. */
4e7fd91e 20469
07d6d2b8
AM		 20470#undef TARGET_LITTLE_SYM
20471#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20472#undef TARGET_LITTLE_NAME
20473#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20474#undef TARGET_BIG_SYM
20475#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20476#undef TARGET_BIG_NAME
20477#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20478
20479/* Like elf32_arm_link_hash_table_create -- but overrides
20480 appropriately for VxWorks. */
906e58ca 20481
4e7fd91e
PB		 20482static struct bfd_link_hash_table *
20483elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20484{
20485 struct bfd_link_hash_table *ret;
20486
20487 ret = elf32_arm_link_hash_table_create (abfd);
20488 if (ret)
20489 {
20490 struct elf32_arm_link_hash_table *htab
00a97672 20491 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20492 htab->use_rel = 0;
00a97672 20493 htab->vxworks_p = 1;
4e7fd91e
PB		 20494 }
20495 return ret;
906e58ca 20496}
4e7fd91e 20497
00a97672
RS		 20498static void
20499elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
20500{
20501 elf32_arm_final_write_processing (abfd, linker);
20502 elf_vxworks_final_write_processing (abfd, linker);
20503}
20504
906e58ca 20505#undef elf32_bed
4e7fd91e
PB		 20506#define elf32_bed elf32_arm_vxworks_bed
20507
906e58ca
NC		 20508#undef bfd_elf32_bfd_link_hash_table_create
20509#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20510#undef elf_backend_final_write_processing
20511#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20512#undef elf_backend_emit_relocs
9eaff861 20513#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20514
906e58ca 20515#undef elf_backend_may_use_rel_p
00a97672 20516#define elf_backend_may_use_rel_p 0
906e58ca 20517#undef elf_backend_may_use_rela_p
00a97672 20518#define elf_backend_may_use_rela_p 1
906e58ca 20519#undef elf_backend_default_use_rela_p
00a97672 20520#define elf_backend_default_use_rela_p 1
906e58ca 20521#undef elf_backend_want_plt_sym
00a97672 20522#define elf_backend_want_plt_sym 1
906e58ca 20523#undef ELF_MAXPAGESIZE
00a97672 20524#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20525
20526#include "elf32-target.h"
20527
20528
21d799b5
NC		 20529/* Merge backend specific data from an object file to the output
20530 object file when linking. */
20531
20532static bfd_boolean
50e03d47 20533elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20534{
50e03d47 20535 bfd *obfd = info->output_bfd;
21d799b5
NC		 20536 flagword out_flags;
20537 flagword in_flags;
20538 bfd_boolean flags_compatible = TRUE;
20539 asection *sec;
20540
cc643b88 20541 /* Check if we have the same endianness. */
50e03d47 20542 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20543 return FALSE;
20544
20545 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20546 return TRUE;
20547
50e03d47 20548 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20549 return FALSE;
20550
20551 /* The input BFD must have had its flags initialised. */
20552 /* The following seems bogus to me -- The flags are initialized in
20553 the assembler but I don't think an elf_flags_init field is
20554 written into the object. */
20555 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20556
20557 in_flags = elf_elfheader (ibfd)->e_flags;
20558 out_flags = elf_elfheader (obfd)->e_flags;
20559
20560 /* In theory there is no reason why we couldn't handle this. However
20561 in practice it isn't even close to working and there is no real
20562 reason to want it. */
20563 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20564 && !(ibfd->flags & DYNAMIC)
20565 && (in_flags & EF_ARM_BE8))
20566 {
871b3ab2 20567 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20568 ibfd);
20569 return FALSE;
20570 }
20571
20572 if (!elf_flags_init (obfd))
20573 {
20574 /* If the input is the default architecture and had the default
20575 flags then do not bother setting the flags for the output
20576 architecture, instead allow future merges to do this. If no
20577 future merges ever set these flags then they will retain their
99059e56
RM		 20578 uninitialised values, which surprise surprise, correspond
20579 to the default values. */
21d799b5
NC		 20580 if (bfd_get_arch_info (ibfd)->the_default
20581 && elf_elfheader (ibfd)->e_flags == 0)
20582 return TRUE;
20583
20584 elf_flags_init (obfd) = TRUE;
20585 elf_elfheader (obfd)->e_flags = in_flags;
20586
20587 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20588 && bfd_get_arch_info (obfd)->the_default)
20589 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20590
20591 return TRUE;
20592 }
20593
20594 /* Determine what should happen if the input ARM architecture
20595 does not match the output ARM architecture. */
20596 if (! bfd_arm_merge_machines (ibfd, obfd))
20597 return FALSE;
20598
20599 /* Identical flags must be compatible. */
20600 if (in_flags == out_flags)
20601 return TRUE;
20602
20603 /* Check to see if the input BFD actually contains any sections. If
20604 not, its flags may not have been initialised either, but it
20605 cannot actually cause any incompatiblity. Do not short-circuit
20606 dynamic objects; their section list may be emptied by
20607 elf_link_add_object_symbols.
20608
20609 Also check to see if there are no code sections in the input.
20610 In this case there is no need to check for code specific flags.
20611 XXX - do we need to worry about floating-point format compatability
20612 in data sections ? */
20613 if (!(ibfd->flags & DYNAMIC))
20614 {
20615 bfd_boolean null_input_bfd = TRUE;
20616 bfd_boolean only_data_sections = TRUE;
20617
20618 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20619 {
20620 /* Ignore synthetic glue sections. */
20621 if (strcmp (sec->name, ".glue_7")
20622 && strcmp (sec->name, ".glue_7t"))
20623 {
20624 if ((bfd_get_section_flags (ibfd, sec)
20625 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20626 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20627 only_data_sections = FALSE;
21d799b5
NC		 20628
20629 null_input_bfd = FALSE;
20630 break;
20631 }
20632 }
20633
20634 if (null_input_bfd || only_data_sections)
20635 return TRUE;
20636 }
20637
20638 /* Complain about various flag mismatches. */
20639 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20640 EF_ARM_EABI_VERSION (out_flags)))
20641 {
20642 _bfd_error_handler
90b6238f 20643 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20644 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20645 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20646 return FALSE;
20647 }
20648
20649 /* Not sure what needs to be checked for EABI versions >= 1. */
20650 /* VxWorks libraries do not use these flags. */
20651 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20652 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20653 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20654 {
20655 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20656 {
20657 _bfd_error_handler
871b3ab2 20658 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20659 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20660 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20661 flags_compatible = FALSE;
20662 }
20663
20664 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20665 {
20666 if (in_flags & EF_ARM_APCS_FLOAT)
20667 _bfd_error_handler
871b3ab2 20668 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20669 ibfd, obfd);
20670 else
20671 _bfd_error_handler
871b3ab2 20672 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20673 ibfd, obfd);
20674
20675 flags_compatible = FALSE;
20676 }
20677
20678 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20679 {
20680 if (in_flags & EF_ARM_VFP_FLOAT)
20681 _bfd_error_handler
90b6238f
AM		 20682 (_("error: %pB uses %s instructions, whereas %pB does not"),
20683 ibfd, "VFP", obfd);
21d799b5
NC		 20684 else
20685 _bfd_error_handler
90b6238f
AM		 20686 (_("error: %pB uses %s instructions, whereas %pB does not"),
20687 ibfd, "FPA", obfd);
21d799b5
NC		 20688
20689 flags_compatible = FALSE;
20690 }
20691
20692 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20693 {
20694 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20695 _bfd_error_handler
90b6238f
AM		 20696 (_("error: %pB uses %s instructions, whereas %pB does not"),
20697 ibfd, "Maverick", obfd);
21d799b5
NC		 20698 else
20699 _bfd_error_handler
90b6238f
AM		 20700 (_("error: %pB does not use %s instructions, whereas %pB does"),
20701 ibfd, "Maverick", obfd);
21d799b5
NC		 20702
20703 flags_compatible = FALSE;
20704 }
20705
20706#ifdef EF_ARM_SOFT_FLOAT
20707 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20708 {
20709 /* We can allow interworking between code that is VFP format
20710 layout, and uses either soft float or integer regs for
20711 passing floating point arguments and results. We already
20712 know that the APCS_FLOAT flags match; similarly for VFP
20713 flags. */
20714 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20715 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20716 {
20717 if (in_flags & EF_ARM_SOFT_FLOAT)
20718 _bfd_error_handler
871b3ab2 20719 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20720 ibfd, obfd);
20721 else
20722 _bfd_error_handler
871b3ab2 20723 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20724 ibfd, obfd);
20725
20726 flags_compatible = FALSE;
20727 }
20728 }
20729#endif
20730
20731 /* Interworking mismatch is only a warning. */
20732 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20733 {
20734 if (in_flags & EF_ARM_INTERWORK)
20735 {
20736 _bfd_error_handler
90b6238f 20737 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20738 ibfd, obfd);
20739 }
20740 else
20741 {
20742 _bfd_error_handler
90b6238f 20743 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20744 ibfd, obfd);
20745 }
20746 }
20747 }
20748
20749 return flags_compatible;
20750}
20751
20752
906e58ca 20753/* Symbian OS Targets. */
7f266840 20754
07d6d2b8
AM		 20755#undef TARGET_LITTLE_SYM
20756#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20757#undef TARGET_LITTLE_NAME
20758#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20759#undef TARGET_BIG_SYM
20760#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20761#undef TARGET_BIG_NAME
20762#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20763
20764/* Like elf32_arm_link_hash_table_create -- but overrides
20765 appropriately for Symbian OS. */
906e58ca 20766
7f266840
DJ		 20767static struct bfd_link_hash_table *
20768elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20769{
20770 struct bfd_link_hash_table *ret;
20771
20772 ret = elf32_arm_link_hash_table_create (abfd);
20773 if (ret)
20774 {
20775 struct elf32_arm_link_hash_table *htab
20776 = (struct elf32_arm_link_hash_table *)ret;
20777 /* There is no PLT header for Symbian OS. */
20778 htab->plt_header_size = 0;
95720a86
DJ		 20779 /* The PLT entries are each one instruction and one word. */
20780 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 20781 htab->symbian_p = 1;
33bfe774
JB		 20782 /* Symbian uses armv5t or above, so use_blx is always true. */
20783 htab->use_blx = 1;
67687978 20784 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20785 }
20786 return ret;
906e58ca 20787}
7f266840 20788
b35d266b 20789static const struct bfd_elf_special_section
551b43fd 20790elf32_arm_symbian_special_sections[] =
7f266840 20791{
5cd3778d
MM		 20792 /* In a BPABI executable, the dynamic linking sections do not go in
20793 the loadable read-only segment. The post-linker may wish to
20794 refer to these sections, but they are not part of the final
20795 program image. */
07d6d2b8
AM		 20796 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20797 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20798 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20799 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20800 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20801 /* These sections do not need to be writable as the SymbianOS
20802 postlinker will arrange things so that no dynamic relocation is
20803 required. */
07d6d2b8
AM		 20804 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20805 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20806 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 20807 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 20808};
20809
c3c76620 20810static void
906e58ca 20811elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 20812 struct bfd_link_info *link_info)
c3c76620
MM		 20813{
20814 /* BPABI objects are never loaded directly by an OS kernel; they are
20815 processed by a postlinker first, into an OS-specific format. If
20816 the D_PAGED bit is set on the file, BFD will align segments on
20817 page boundaries, so that an OS can directly map the file. With
20818 BPABI objects, that just results in wasted space. In addition,
20819 because we clear the D_PAGED bit, map_sections_to_segments will
20820 recognize that the program headers should not be mapped into any
20821 loadable segment. */
20822 abfd->flags &= ~D_PAGED;
906e58ca 20823 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 20824}
7f266840
DJ		 20825
20826static bfd_boolean
906e58ca 20827elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 20828 struct bfd_link_info *info)
7f266840
DJ		 20829{
20830 struct elf_segment_map *m;
20831 asection *dynsec;
20832
7f266840
DJ		 20833 /* BPABI shared libraries and executables should have a PT_DYNAMIC
20834 segment. However, because the .dynamic section is not marked
20835 with SEC_LOAD, the generic ELF code will not create such a
20836 segment. */
20837 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
20838 if (dynsec)
20839 {
12bd6957 20840 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 20841 if (m->p_type == PT_DYNAMIC)
20842 break;
20843
20844 if (m == NULL)
20845 {
20846 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 20847 m->next = elf_seg_map (abfd);
20848 elf_seg_map (abfd) = m;
8ded5a0f 20849 }
7f266840
DJ		 20850 }
20851
b294bdf8
MM		 20852 /* Also call the generic arm routine. */
20853 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 20854}
20855
95720a86
DJ		 20856/* Return address for Ith PLT stub in section PLT, for relocation REL
20857 or (bfd_vma) -1 if it should not be included. */
20858
20859static bfd_vma
20860elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
20861 const arelent *rel ATTRIBUTE_UNUSED)
20862{
20863 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
20864}
20865
8029a119 20866#undef elf32_bed
7f266840
DJ		 20867#define elf32_bed elf32_arm_symbian_bed
20868
20869/* The dynamic sections are not allocated on SymbianOS; the postlinker
20870 will process them and then discard them. */
906e58ca 20871#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 20872#define ELF_DYNAMIC_SEC_FLAGS \
20873 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
20874
9eaff861 20875#undef elf_backend_emit_relocs
c3c76620 20876
906e58ca
NC		 20877#undef bfd_elf32_bfd_link_hash_table_create
20878#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
20879#undef elf_backend_special_sections
07d6d2b8 20880#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 20881#undef elf_backend_begin_write_processing
20882#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
20883#undef elf_backend_final_write_processing
20884#define elf_backend_final_write_processing elf32_arm_final_write_processing
20885
20886#undef elf_backend_modify_segment_map
7f266840
DJ		 20887#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
20888
20889/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 20890#undef elf_backend_got_header_size
7f266840
DJ		 20891#define elf_backend_got_header_size 0
20892
20893/* Similarly, there is no .got.plt section. */
906e58ca 20894#undef elf_backend_want_got_plt
7f266840
DJ		 20895#define elf_backend_want_got_plt 0
20896
906e58ca 20897#undef elf_backend_plt_sym_val
95720a86
DJ		 20898#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
20899
906e58ca 20900#undef elf_backend_may_use_rel_p
00a97672 20901#define elf_backend_may_use_rel_p 1
906e58ca 20902#undef elf_backend_may_use_rela_p
00a97672 20903#define elf_backend_may_use_rela_p 0
906e58ca 20904#undef elf_backend_default_use_rela_p
00a97672 20905#define elf_backend_default_use_rela_p 0
906e58ca 20906#undef elf_backend_want_plt_sym
00a97672 20907#define elf_backend_want_plt_sym 0
64f52338
AM		 20908#undef elf_backend_dtrel_excludes_plt
20909#define elf_backend_dtrel_excludes_plt 0
906e58ca 20910#undef ELF_MAXPAGESIZE
00a97672 20911#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 20912
7f266840 20913#include "elf32-target.h"
GDB Binutils - Deliverables
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